1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
59 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
62 #include "gstab.h" /* for N_SLINE */
65 #ifndef TARGET_NO_PROTOTYPE
66 #define TARGET_NO_PROTOTYPE 0
69 #define min(A,B) ((A) < (B) ? (A) : (B))
70 #define max(A,B) ((A) > (B) ? (A) : (B))
72 /* Structure used to define the rs6000 stack */
73 typedef struct rs6000_stack {
74 int first_gp_reg_save; /* first callee saved GP register used */
75 int first_fp_reg_save; /* first callee saved FP register used */
76 int first_altivec_reg_save; /* first callee saved AltiVec register used */
77 int lr_save_p; /* true if the link reg needs to be saved */
78 int cr_save_p; /* true if the CR reg needs to be saved */
79 unsigned int vrsave_mask; /* mask of vec registers to save */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
82 int world_save_p; /* true if we're saving *everything*:
83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int varargs_save_offset; /* offset to save the varargs registers */
93 int ehrd_offset; /* offset to EH return data */
94 int reg_size; /* register size (4 or 8) */
95 HOST_WIDE_INT vars_size; /* variable save area size */
96 int parm_size; /* outgoing parameter size */
97 int save_size; /* save area size */
98 int fixed_size; /* fixed size of stack frame */
99 int gp_size; /* size of saved GP registers */
100 int fp_size; /* size of saved FP registers */
101 int altivec_size; /* size of saved AltiVec registers */
102 int cr_size; /* size to hold CR if not in save_size */
103 int vrsave_size; /* size to hold VRSAVE if not in save_size */
104 int altivec_padding_size; /* size of altivec alignment padding if
106 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
107 int spe_padding_size;
108 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
109 int spe_64bit_regs_used;
112 /* A C structure for machine-specific, per-function data.
113 This is added to the cfun structure. */
114 typedef struct machine_function GTY(())
116 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
117 int ra_needs_full_frame;
118 /* Some local-dynamic symbol. */
119 const char *some_ld_name;
120 /* Whether the instruction chain has been scanned already. */
121 int insn_chain_scanned_p;
122 /* Flags if __builtin_return_address (0) was used. */
124 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
125 varargs save area. */
126 HOST_WIDE_INT varargs_save_offset;
129 /* Target cpu type */
131 enum processor_type rs6000_cpu;
132 struct rs6000_cpu_select rs6000_select[3] =
134 /* switch name, tune arch */
135 { (const char *)0, "--with-cpu=", 1, 1 },
136 { (const char *)0, "-mcpu=", 1, 1 },
137 { (const char *)0, "-mtune=", 1, 0 },
140 /* Always emit branch hint bits. */
141 static GTY(()) bool rs6000_always_hint;
143 /* Schedule instructions for group formation. */
144 static GTY(()) bool rs6000_sched_groups;
146 /* Support for -msched-costly-dep option. */
147 const char *rs6000_sched_costly_dep_str;
148 enum rs6000_dependence_cost rs6000_sched_costly_dep;
150 /* Support for -minsert-sched-nops option. */
151 const char *rs6000_sched_insert_nops_str;
152 enum rs6000_nop_insertion rs6000_sched_insert_nops;
154 /* Support targetm.vectorize.builtin_mask_for_load. */
155 static GTY(()) tree altivec_builtin_mask_for_load;
157 /* Size of long double */
158 int rs6000_long_double_type_size;
160 /* Whether -mabi=altivec has appeared */
161 int rs6000_altivec_abi;
163 /* Nonzero if we want SPE ABI extensions. */
166 /* Nonzero if floating point operations are done in the GPRs. */
167 int rs6000_float_gprs = 0;
169 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
170 int rs6000_darwin64_abi;
172 /* Set to nonzero once AIX common-mode calls have been defined. */
173 static GTY(()) int common_mode_defined;
175 /* Save information from a "cmpxx" operation until the branch or scc is
177 rtx rs6000_compare_op0, rs6000_compare_op1;
178 int rs6000_compare_fp_p;
180 /* Label number of label created for -mrelocatable, to call to so we can
181 get the address of the GOT section */
182 int rs6000_pic_labelno;
185 /* Which abi to adhere to */
186 const char *rs6000_abi_name;
188 /* Semantics of the small data area */
189 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
191 /* Which small data model to use */
192 const char *rs6000_sdata_name = (char *)0;
194 /* Counter for labels which are to be placed in .fixup. */
195 int fixuplabelno = 0;
198 /* Bit size of immediate TLS offsets and string from which it is decoded. */
199 int rs6000_tls_size = 32;
200 const char *rs6000_tls_size_string;
202 /* ABI enumeration available for subtarget to use. */
203 enum rs6000_abi rs6000_current_abi;
205 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
209 const char *rs6000_debug_name;
210 int rs6000_debug_stack; /* debug stack applications */
211 int rs6000_debug_arg; /* debug argument handling */
213 /* Value is TRUE if register/mode pair is acceptable. */
214 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
216 /* Built in types. */
218 tree rs6000_builtin_types[RS6000_BTI_MAX];
219 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
221 const char *rs6000_traceback_name;
223 traceback_default = 0,
229 /* Flag to say the TOC is initialized */
231 char toc_label_name[10];
233 static GTY(()) section *read_only_data_section;
234 static GTY(()) section *private_data_section;
235 static GTY(()) section *read_only_private_data_section;
236 static GTY(()) section *sdata2_section;
237 static GTY(()) section *toc_section;
239 /* Control alignment for fields within structures. */
240 /* String from -malign-XXXXX. */
241 int rs6000_alignment_flags;
243 /* True for any options that were explicitly set. */
245 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
246 bool alignment; /* True if -malign- was used. */
247 bool abi; /* True if -mabi= was used. */
248 bool spe; /* True if -mspe= was used. */
249 bool float_gprs; /* True if -mfloat-gprs= was used. */
250 bool isel; /* True if -misel was used. */
251 bool long_double; /* True if -mlong-double- was used. */
252 } rs6000_explicit_options;
254 struct builtin_description
256 /* mask is not const because we're going to alter it below. This
257 nonsense will go away when we rewrite the -march infrastructure
258 to give us more target flag bits. */
260 const enum insn_code icode;
261 const char *const name;
262 const enum rs6000_builtins code;
265 /* Target cpu costs. */
267 struct processor_costs {
268 const int mulsi; /* cost of SImode multiplication. */
269 const int mulsi_const; /* cost of SImode multiplication by constant. */
270 const int mulsi_const9; /* cost of SImode mult by short constant. */
271 const int muldi; /* cost of DImode multiplication. */
272 const int divsi; /* cost of SImode division. */
273 const int divdi; /* cost of DImode division. */
274 const int fp; /* cost of simple SFmode and DFmode insns. */
275 const int dmul; /* cost of DFmode multiplication (and fmadd). */
276 const int sdiv; /* cost of SFmode division (fdivs). */
277 const int ddiv; /* cost of DFmode division (fdiv). */
280 const struct processor_costs *rs6000_cost;
282 /* Processor costs (relative to an add) */
284 /* Instruction size costs on 32bit processors. */
286 struct processor_costs size32_cost = {
287 COSTS_N_INSNS (1), /* mulsi */
288 COSTS_N_INSNS (1), /* mulsi_const */
289 COSTS_N_INSNS (1), /* mulsi_const9 */
290 COSTS_N_INSNS (1), /* muldi */
291 COSTS_N_INSNS (1), /* divsi */
292 COSTS_N_INSNS (1), /* divdi */
293 COSTS_N_INSNS (1), /* fp */
294 COSTS_N_INSNS (1), /* dmul */
295 COSTS_N_INSNS (1), /* sdiv */
296 COSTS_N_INSNS (1), /* ddiv */
299 /* Instruction size costs on 64bit processors. */
301 struct processor_costs size64_cost = {
302 COSTS_N_INSNS (1), /* mulsi */
303 COSTS_N_INSNS (1), /* mulsi_const */
304 COSTS_N_INSNS (1), /* mulsi_const9 */
305 COSTS_N_INSNS (1), /* muldi */
306 COSTS_N_INSNS (1), /* divsi */
307 COSTS_N_INSNS (1), /* divdi */
308 COSTS_N_INSNS (1), /* fp */
309 COSTS_N_INSNS (1), /* dmul */
310 COSTS_N_INSNS (1), /* sdiv */
311 COSTS_N_INSNS (1), /* ddiv */
314 /* Instruction costs on RIOS1 processors. */
316 struct processor_costs rios1_cost = {
317 COSTS_N_INSNS (5), /* mulsi */
318 COSTS_N_INSNS (4), /* mulsi_const */
319 COSTS_N_INSNS (3), /* mulsi_const9 */
320 COSTS_N_INSNS (5), /* muldi */
321 COSTS_N_INSNS (19), /* divsi */
322 COSTS_N_INSNS (19), /* divdi */
323 COSTS_N_INSNS (2), /* fp */
324 COSTS_N_INSNS (2), /* dmul */
325 COSTS_N_INSNS (19), /* sdiv */
326 COSTS_N_INSNS (19), /* ddiv */
329 /* Instruction costs on RIOS2 processors. */
331 struct processor_costs rios2_cost = {
332 COSTS_N_INSNS (2), /* mulsi */
333 COSTS_N_INSNS (2), /* mulsi_const */
334 COSTS_N_INSNS (2), /* mulsi_const9 */
335 COSTS_N_INSNS (2), /* muldi */
336 COSTS_N_INSNS (13), /* divsi */
337 COSTS_N_INSNS (13), /* divdi */
338 COSTS_N_INSNS (2), /* fp */
339 COSTS_N_INSNS (2), /* dmul */
340 COSTS_N_INSNS (17), /* sdiv */
341 COSTS_N_INSNS (17), /* ddiv */
344 /* Instruction costs on RS64A processors. */
346 struct processor_costs rs64a_cost = {
347 COSTS_N_INSNS (20), /* mulsi */
348 COSTS_N_INSNS (12), /* mulsi_const */
349 COSTS_N_INSNS (8), /* mulsi_const9 */
350 COSTS_N_INSNS (34), /* muldi */
351 COSTS_N_INSNS (65), /* divsi */
352 COSTS_N_INSNS (67), /* divdi */
353 COSTS_N_INSNS (4), /* fp */
354 COSTS_N_INSNS (4), /* dmul */
355 COSTS_N_INSNS (31), /* sdiv */
356 COSTS_N_INSNS (31), /* ddiv */
359 /* Instruction costs on MPCCORE processors. */
361 struct processor_costs mpccore_cost = {
362 COSTS_N_INSNS (2), /* mulsi */
363 COSTS_N_INSNS (2), /* mulsi_const */
364 COSTS_N_INSNS (2), /* mulsi_const9 */
365 COSTS_N_INSNS (2), /* muldi */
366 COSTS_N_INSNS (6), /* divsi */
367 COSTS_N_INSNS (6), /* divdi */
368 COSTS_N_INSNS (4), /* fp */
369 COSTS_N_INSNS (5), /* dmul */
370 COSTS_N_INSNS (10), /* sdiv */
371 COSTS_N_INSNS (17), /* ddiv */
374 /* Instruction costs on PPC403 processors. */
376 struct processor_costs ppc403_cost = {
377 COSTS_N_INSNS (4), /* mulsi */
378 COSTS_N_INSNS (4), /* mulsi_const */
379 COSTS_N_INSNS (4), /* mulsi_const9 */
380 COSTS_N_INSNS (4), /* muldi */
381 COSTS_N_INSNS (33), /* divsi */
382 COSTS_N_INSNS (33), /* divdi */
383 COSTS_N_INSNS (11), /* fp */
384 COSTS_N_INSNS (11), /* dmul */
385 COSTS_N_INSNS (11), /* sdiv */
386 COSTS_N_INSNS (11), /* ddiv */
389 /* Instruction costs on PPC405 processors. */
391 struct processor_costs ppc405_cost = {
392 COSTS_N_INSNS (5), /* mulsi */
393 COSTS_N_INSNS (4), /* mulsi_const */
394 COSTS_N_INSNS (3), /* mulsi_const9 */
395 COSTS_N_INSNS (5), /* muldi */
396 COSTS_N_INSNS (35), /* divsi */
397 COSTS_N_INSNS (35), /* divdi */
398 COSTS_N_INSNS (11), /* fp */
399 COSTS_N_INSNS (11), /* dmul */
400 COSTS_N_INSNS (11), /* sdiv */
401 COSTS_N_INSNS (11), /* ddiv */
404 /* Instruction costs on PPC440 processors. */
406 struct processor_costs ppc440_cost = {
407 COSTS_N_INSNS (3), /* mulsi */
408 COSTS_N_INSNS (2), /* mulsi_const */
409 COSTS_N_INSNS (2), /* mulsi_const9 */
410 COSTS_N_INSNS (3), /* muldi */
411 COSTS_N_INSNS (34), /* divsi */
412 COSTS_N_INSNS (34), /* divdi */
413 COSTS_N_INSNS (5), /* fp */
414 COSTS_N_INSNS (5), /* dmul */
415 COSTS_N_INSNS (19), /* sdiv */
416 COSTS_N_INSNS (33), /* ddiv */
419 /* Instruction costs on PPC601 processors. */
421 struct processor_costs ppc601_cost = {
422 COSTS_N_INSNS (5), /* mulsi */
423 COSTS_N_INSNS (5), /* mulsi_const */
424 COSTS_N_INSNS (5), /* mulsi_const9 */
425 COSTS_N_INSNS (5), /* muldi */
426 COSTS_N_INSNS (36), /* divsi */
427 COSTS_N_INSNS (36), /* divdi */
428 COSTS_N_INSNS (4), /* fp */
429 COSTS_N_INSNS (5), /* dmul */
430 COSTS_N_INSNS (17), /* sdiv */
431 COSTS_N_INSNS (31), /* ddiv */
434 /* Instruction costs on PPC603 processors. */
436 struct processor_costs ppc603_cost = {
437 COSTS_N_INSNS (5), /* mulsi */
438 COSTS_N_INSNS (3), /* mulsi_const */
439 COSTS_N_INSNS (2), /* mulsi_const9 */
440 COSTS_N_INSNS (5), /* muldi */
441 COSTS_N_INSNS (37), /* divsi */
442 COSTS_N_INSNS (37), /* divdi */
443 COSTS_N_INSNS (3), /* fp */
444 COSTS_N_INSNS (4), /* dmul */
445 COSTS_N_INSNS (18), /* sdiv */
446 COSTS_N_INSNS (33), /* ddiv */
449 /* Instruction costs on PPC604 processors. */
451 struct processor_costs ppc604_cost = {
452 COSTS_N_INSNS (4), /* mulsi */
453 COSTS_N_INSNS (4), /* mulsi_const */
454 COSTS_N_INSNS (4), /* mulsi_const9 */
455 COSTS_N_INSNS (4), /* muldi */
456 COSTS_N_INSNS (20), /* divsi */
457 COSTS_N_INSNS (20), /* divdi */
458 COSTS_N_INSNS (3), /* fp */
459 COSTS_N_INSNS (3), /* dmul */
460 COSTS_N_INSNS (18), /* sdiv */
461 COSTS_N_INSNS (32), /* ddiv */
464 /* Instruction costs on PPC604e processors. */
466 struct processor_costs ppc604e_cost = {
467 COSTS_N_INSNS (2), /* mulsi */
468 COSTS_N_INSNS (2), /* mulsi_const */
469 COSTS_N_INSNS (2), /* mulsi_const9 */
470 COSTS_N_INSNS (2), /* muldi */
471 COSTS_N_INSNS (20), /* divsi */
472 COSTS_N_INSNS (20), /* divdi */
473 COSTS_N_INSNS (3), /* fp */
474 COSTS_N_INSNS (3), /* dmul */
475 COSTS_N_INSNS (18), /* sdiv */
476 COSTS_N_INSNS (32), /* ddiv */
479 /* Instruction costs on PPC620 processors. */
481 struct processor_costs ppc620_cost = {
482 COSTS_N_INSNS (5), /* mulsi */
483 COSTS_N_INSNS (4), /* mulsi_const */
484 COSTS_N_INSNS (3), /* mulsi_const9 */
485 COSTS_N_INSNS (7), /* muldi */
486 COSTS_N_INSNS (21), /* divsi */
487 COSTS_N_INSNS (37), /* divdi */
488 COSTS_N_INSNS (3), /* fp */
489 COSTS_N_INSNS (3), /* dmul */
490 COSTS_N_INSNS (18), /* sdiv */
491 COSTS_N_INSNS (32), /* ddiv */
494 /* Instruction costs on PPC630 processors. */
496 struct processor_costs ppc630_cost = {
497 COSTS_N_INSNS (5), /* mulsi */
498 COSTS_N_INSNS (4), /* mulsi_const */
499 COSTS_N_INSNS (3), /* mulsi_const9 */
500 COSTS_N_INSNS (7), /* muldi */
501 COSTS_N_INSNS (21), /* divsi */
502 COSTS_N_INSNS (37), /* divdi */
503 COSTS_N_INSNS (3), /* fp */
504 COSTS_N_INSNS (3), /* dmul */
505 COSTS_N_INSNS (17), /* sdiv */
506 COSTS_N_INSNS (21), /* ddiv */
509 /* Instruction costs on PPC750 and PPC7400 processors. */
511 struct processor_costs ppc750_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (3), /* mulsi_const */
514 COSTS_N_INSNS (2), /* mulsi_const9 */
515 COSTS_N_INSNS (5), /* muldi */
516 COSTS_N_INSNS (17), /* divsi */
517 COSTS_N_INSNS (17), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (31), /* ddiv */
524 /* Instruction costs on PPC7450 processors. */
526 struct processor_costs ppc7450_cost = {
527 COSTS_N_INSNS (4), /* mulsi */
528 COSTS_N_INSNS (3), /* mulsi_const */
529 COSTS_N_INSNS (3), /* mulsi_const9 */
530 COSTS_N_INSNS (4), /* muldi */
531 COSTS_N_INSNS (23), /* divsi */
532 COSTS_N_INSNS (23), /* divdi */
533 COSTS_N_INSNS (5), /* fp */
534 COSTS_N_INSNS (5), /* dmul */
535 COSTS_N_INSNS (21), /* sdiv */
536 COSTS_N_INSNS (35), /* ddiv */
539 /* Instruction costs on PPC8540 processors. */
541 struct processor_costs ppc8540_cost = {
542 COSTS_N_INSNS (4), /* mulsi */
543 COSTS_N_INSNS (4), /* mulsi_const */
544 COSTS_N_INSNS (4), /* mulsi_const9 */
545 COSTS_N_INSNS (4), /* muldi */
546 COSTS_N_INSNS (19), /* divsi */
547 COSTS_N_INSNS (19), /* divdi */
548 COSTS_N_INSNS (4), /* fp */
549 COSTS_N_INSNS (4), /* dmul */
550 COSTS_N_INSNS (29), /* sdiv */
551 COSTS_N_INSNS (29), /* ddiv */
554 /* Instruction costs on POWER4 and POWER5 processors. */
556 struct processor_costs power4_cost = {
557 COSTS_N_INSNS (3), /* mulsi */
558 COSTS_N_INSNS (2), /* mulsi_const */
559 COSTS_N_INSNS (2), /* mulsi_const9 */
560 COSTS_N_INSNS (4), /* muldi */
561 COSTS_N_INSNS (18), /* divsi */
562 COSTS_N_INSNS (34), /* divdi */
563 COSTS_N_INSNS (3), /* fp */
564 COSTS_N_INSNS (3), /* dmul */
565 COSTS_N_INSNS (17), /* sdiv */
566 COSTS_N_INSNS (17), /* ddiv */
570 static bool rs6000_function_ok_for_sibcall (tree, tree);
571 static const char *rs6000_invalid_within_doloop (rtx);
572 static rtx rs6000_generate_compare (enum rtx_code);
573 static void rs6000_maybe_dead (rtx);
574 static void rs6000_emit_stack_tie (void);
575 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
576 static rtx spe_synthesize_frame_save (rtx);
577 static bool spe_func_has_64bit_regs_p (void);
578 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
580 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
581 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
582 static unsigned rs6000_hash_constant (rtx);
583 static unsigned toc_hash_function (const void *);
584 static int toc_hash_eq (const void *, const void *);
585 static int constant_pool_expr_1 (rtx, int *, int *);
586 static bool constant_pool_expr_p (rtx);
587 static bool legitimate_indexed_address_p (rtx, int);
588 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
589 static struct machine_function * rs6000_init_machine_status (void);
590 static bool rs6000_assemble_integer (rtx, unsigned int, int);
591 static bool no_global_regs_above (int);
592 #ifdef HAVE_GAS_HIDDEN
593 static void rs6000_assemble_visibility (tree, int);
595 static int rs6000_ra_ever_killed (void);
596 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
597 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
598 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
599 static const char *rs6000_mangle_fundamental_type (tree);
600 extern const struct attribute_spec rs6000_attribute_table[];
601 static void rs6000_set_default_type_attributes (tree);
602 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
603 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
604 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
606 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
607 static bool rs6000_return_in_memory (tree, tree);
608 static void rs6000_file_start (void);
610 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
611 static void rs6000_elf_asm_out_constructor (rtx, int);
612 static void rs6000_elf_asm_out_destructor (rtx, int);
613 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
614 static void rs6000_elf_asm_init_sections (void);
615 static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
616 static void rs6000_elf_unique_section (tree, int);
617 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
618 unsigned HOST_WIDE_INT);
619 static void rs6000_elf_encode_section_info (tree, rtx, int)
623 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
624 static void rs6000_xcoff_asm_init_sections (void);
625 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
626 static section *rs6000_xcoff_select_section (tree, int,
627 unsigned HOST_WIDE_INT);
628 static void rs6000_xcoff_unique_section (tree, int);
629 static section *rs6000_xcoff_select_rtx_section
630 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
631 static const char * rs6000_xcoff_strip_name_encoding (const char *);
632 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
633 static void rs6000_xcoff_file_start (void);
634 static void rs6000_xcoff_file_end (void);
636 static int rs6000_variable_issue (FILE *, int, rtx, int);
637 static bool rs6000_rtx_costs (rtx, int, int, int *);
638 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
639 static bool is_microcoded_insn (rtx);
640 static int is_dispatch_slot_restricted (rtx);
641 static bool is_cracked_insn (rtx);
642 static bool is_branch_slot_insn (rtx);
643 static int rs6000_adjust_priority (rtx, int);
644 static int rs6000_issue_rate (void);
645 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
646 static rtx get_next_active_insn (rtx, rtx);
647 static bool insn_terminates_group_p (rtx , enum group_termination);
648 static bool is_costly_group (rtx *, rtx);
649 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
650 static int redefine_groups (FILE *, int, rtx, rtx);
651 static int pad_groups (FILE *, int, rtx, rtx);
652 static void rs6000_sched_finish (FILE *, int);
653 static int rs6000_use_sched_lookahead (void);
654 static tree rs6000_builtin_mask_for_load (void);
656 static void def_builtin (int, const char *, tree, int);
657 static void rs6000_init_builtins (void);
658 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
659 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
660 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
661 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
662 static void altivec_init_builtins (void);
663 static void rs6000_common_init_builtins (void);
664 static void rs6000_init_libfuncs (void);
666 static void enable_mask_for_builtins (struct builtin_description *, int,
667 enum rs6000_builtins,
668 enum rs6000_builtins);
669 static tree build_opaque_vector_type (tree, int);
670 static void spe_init_builtins (void);
671 static rtx spe_expand_builtin (tree, rtx, bool *);
672 static rtx spe_expand_stv_builtin (enum insn_code, tree);
673 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
674 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
675 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
676 static rs6000_stack_t *rs6000_stack_info (void);
677 static void debug_stack_info (rs6000_stack_t *);
679 static rtx altivec_expand_builtin (tree, rtx, bool *);
680 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
681 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
682 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
683 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
684 static rtx altivec_expand_predicate_builtin (enum insn_code,
685 const char *, tree, rtx);
686 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
687 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
688 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
689 static rtx altivec_expand_vec_set_builtin (tree);
690 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
691 static int get_element_number (tree, tree);
692 static bool rs6000_handle_option (size_t, const char *, int);
693 static void rs6000_parse_tls_size_option (void);
694 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
695 static int first_altivec_reg_to_save (void);
696 static unsigned int compute_vrsave_mask (void);
697 static void compute_save_world_info (rs6000_stack_t *info_ptr);
698 static void is_altivec_return_reg (rtx, void *);
699 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
700 int easy_vector_constant (rtx, enum machine_mode);
701 static bool rs6000_is_opaque_type (tree);
702 static rtx rs6000_dwarf_register_span (rtx);
703 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
704 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
705 static rtx rs6000_tls_get_addr (void);
706 static rtx rs6000_got_sym (void);
707 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
708 static const char *rs6000_get_some_local_dynamic_name (void);
709 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
710 static rtx rs6000_complex_function_value (enum machine_mode);
711 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
712 enum machine_mode, tree);
713 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
715 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
716 tree, HOST_WIDE_INT);
717 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
720 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
723 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
724 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
725 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
726 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
727 enum machine_mode, tree,
729 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
731 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
733 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
735 static void macho_branch_islands (void);
736 static void add_compiler_branch_island (tree, tree, int);
737 static int no_previous_def (tree function_name);
738 static tree get_prev_label (tree function_name);
739 static void rs6000_darwin_file_start (void);
742 static tree rs6000_build_builtin_va_list (void);
743 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
744 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
745 static bool rs6000_vector_mode_supported_p (enum machine_mode);
746 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
748 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
750 static int get_vsel_insn (enum machine_mode);
751 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
752 static tree rs6000_stack_protect_fail (void);
754 const int INSN_NOT_AVAILABLE = -1;
755 static enum machine_mode rs6000_eh_return_filter_mode (void);
757 /* Hash table stuff for keeping track of TOC entries. */
759 struct toc_hash_struct GTY(())
761 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
762 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
764 enum machine_mode key_mode;
768 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
770 /* Default register names. */
771 char rs6000_reg_names[][8] =
773 "0", "1", "2", "3", "4", "5", "6", "7",
774 "8", "9", "10", "11", "12", "13", "14", "15",
775 "16", "17", "18", "19", "20", "21", "22", "23",
776 "24", "25", "26", "27", "28", "29", "30", "31",
777 "0", "1", "2", "3", "4", "5", "6", "7",
778 "8", "9", "10", "11", "12", "13", "14", "15",
779 "16", "17", "18", "19", "20", "21", "22", "23",
780 "24", "25", "26", "27", "28", "29", "30", "31",
781 "mq", "lr", "ctr","ap",
782 "0", "1", "2", "3", "4", "5", "6", "7",
784 /* AltiVec registers. */
785 "0", "1", "2", "3", "4", "5", "6", "7",
786 "8", "9", "10", "11", "12", "13", "14", "15",
787 "16", "17", "18", "19", "20", "21", "22", "23",
788 "24", "25", "26", "27", "28", "29", "30", "31",
791 "spe_acc", "spefscr",
792 /* Soft frame pointer. */
796 #ifdef TARGET_REGNAMES
797 static const char alt_reg_names[][8] =
799 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
800 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
801 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
802 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
803 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
804 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
805 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
806 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
807 "mq", "lr", "ctr", "ap",
808 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
810 /* AltiVec registers. */
811 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
812 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
813 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
814 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
817 "spe_acc", "spefscr",
818 /* Soft frame pointer. */
823 #ifndef MASK_STRICT_ALIGN
824 #define MASK_STRICT_ALIGN 0
826 #ifndef TARGET_PROFILE_KERNEL
827 #define TARGET_PROFILE_KERNEL 0
830 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
831 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
833 /* Initialize the GCC target structure. */
834 #undef TARGET_ATTRIBUTE_TABLE
835 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
836 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
837 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
839 #undef TARGET_ASM_ALIGNED_DI_OP
840 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
842 /* Default unaligned ops are only provided for ELF. Find the ops needed
843 for non-ELF systems. */
844 #ifndef OBJECT_FORMAT_ELF
846 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
848 #undef TARGET_ASM_UNALIGNED_HI_OP
849 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
850 #undef TARGET_ASM_UNALIGNED_SI_OP
851 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
852 #undef TARGET_ASM_UNALIGNED_DI_OP
853 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
856 #undef TARGET_ASM_UNALIGNED_HI_OP
857 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
858 #undef TARGET_ASM_UNALIGNED_SI_OP
859 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
860 #undef TARGET_ASM_UNALIGNED_DI_OP
861 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
862 #undef TARGET_ASM_ALIGNED_DI_OP
863 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
867 /* This hook deals with fixups for relocatable code and DI-mode objects
869 #undef TARGET_ASM_INTEGER
870 #define TARGET_ASM_INTEGER rs6000_assemble_integer
872 #ifdef HAVE_GAS_HIDDEN
873 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
874 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
877 #undef TARGET_HAVE_TLS
878 #define TARGET_HAVE_TLS HAVE_AS_TLS
880 #undef TARGET_CANNOT_FORCE_CONST_MEM
881 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
883 #undef TARGET_ASM_FUNCTION_PROLOGUE
884 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
885 #undef TARGET_ASM_FUNCTION_EPILOGUE
886 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
888 #undef TARGET_SCHED_VARIABLE_ISSUE
889 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
891 #undef TARGET_SCHED_ISSUE_RATE
892 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
893 #undef TARGET_SCHED_ADJUST_COST
894 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
895 #undef TARGET_SCHED_ADJUST_PRIORITY
896 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
897 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
898 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
899 #undef TARGET_SCHED_FINISH
900 #define TARGET_SCHED_FINISH rs6000_sched_finish
902 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
903 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
905 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
906 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
908 #undef TARGET_INIT_BUILTINS
909 #define TARGET_INIT_BUILTINS rs6000_init_builtins
911 #undef TARGET_EXPAND_BUILTIN
912 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
914 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
915 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
917 #undef TARGET_INIT_LIBFUNCS
918 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
921 #undef TARGET_BINDS_LOCAL_P
922 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
925 #undef TARGET_ASM_OUTPUT_MI_THUNK
926 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
928 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
929 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
931 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
932 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
934 #undef TARGET_INVALID_WITHIN_DOLOOP
935 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
937 #undef TARGET_RTX_COSTS
938 #define TARGET_RTX_COSTS rs6000_rtx_costs
939 #undef TARGET_ADDRESS_COST
940 #define TARGET_ADDRESS_COST hook_int_rtx_0
942 #undef TARGET_VECTOR_OPAQUE_P
943 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
945 #undef TARGET_DWARF_REGISTER_SPAN
946 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
948 /* On rs6000, function arguments are promoted, as are function return
950 #undef TARGET_PROMOTE_FUNCTION_ARGS
951 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
952 #undef TARGET_PROMOTE_FUNCTION_RETURN
953 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
955 #undef TARGET_RETURN_IN_MEMORY
956 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
958 #undef TARGET_SETUP_INCOMING_VARARGS
959 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
961 /* Always strict argument naming on rs6000. */
962 #undef TARGET_STRICT_ARGUMENT_NAMING
963 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
964 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
965 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
966 #undef TARGET_SPLIT_COMPLEX_ARG
967 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
968 #undef TARGET_MUST_PASS_IN_STACK
969 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
970 #undef TARGET_PASS_BY_REFERENCE
971 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
972 #undef TARGET_ARG_PARTIAL_BYTES
973 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
975 #undef TARGET_BUILD_BUILTIN_VA_LIST
976 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
978 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
979 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
981 #undef TARGET_EH_RETURN_FILTER_MODE
982 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
984 #undef TARGET_VECTOR_MODE_SUPPORTED_P
985 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
987 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
988 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
990 #undef TARGET_HANDLE_OPTION
991 #define TARGET_HANDLE_OPTION rs6000_handle_option
993 #undef TARGET_DEFAULT_TARGET_FLAGS
994 #define TARGET_DEFAULT_TARGET_FLAGS \
995 (TARGET_DEFAULT | MASK_SCHED_PROLOG)
997 #undef TARGET_STACK_PROTECT_FAIL
998 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1000 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1001 The PowerPC architecture requires only weak consistency among
1002 processors--that is, memory accesses between processors need not be
1003 sequentially consistent and memory accesses among processors can occur
1004 in any order. The ability to order memory accesses weakly provides
1005 opportunities for more efficient use of the system bus. Unless a
1006 dependency exists, the 604e allows read operations to precede store
1008 #undef TARGET_RELAXED_ORDERING
1009 #define TARGET_RELAXED_ORDERING true
1012 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1013 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1016 struct gcc_target targetm = TARGET_INITIALIZER;
1019 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1022 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1024 /* The GPRs can hold any mode, but values bigger than one register
1025 cannot go past R31. */
1026 if (INT_REGNO_P (regno))
1027 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1029 /* The float registers can only hold floating modes and DImode. */
1030 if (FP_REGNO_P (regno))
1032 (SCALAR_FLOAT_MODE_P (mode)
1033 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1034 || (GET_MODE_CLASS (mode) == MODE_INT
1035 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1037 /* The CR register can only hold CC modes. */
1038 if (CR_REGNO_P (regno))
1039 return GET_MODE_CLASS (mode) == MODE_CC;
1041 if (XER_REGNO_P (regno))
1042 return mode == PSImode;
1044 /* AltiVec only in AldyVec registers. */
1045 if (ALTIVEC_REGNO_P (regno))
1046 return ALTIVEC_VECTOR_MODE (mode);
1048 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1049 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1052 /* We cannot put TImode anywhere except general register and it must be
1053 able to fit within the register set. */
1055 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1058 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1060 rs6000_init_hard_regno_mode_ok (void)
1064 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1065 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1066 if (rs6000_hard_regno_mode_ok (r, m))
1067 rs6000_hard_regno_mode_ok_p[m][r] = true;
1070 /* If not otherwise specified by a target, make 'long double' equivalent to
1073 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1074 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1077 /* Override command line options. Mostly we process the processor
1078 type and sometimes adjust other TARGET_ options. */
1081 rs6000_override_options (const char *default_cpu)
1084 struct rs6000_cpu_select *ptr;
1087 /* Simplifications for entries below. */
1090 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1091 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1094 /* This table occasionally claims that a processor does not support
1095 a particular feature even though it does, but the feature is slower
1096 than the alternative. Thus, it shouldn't be relied on as a
1097 complete description of the processor's support.
1099 Please keep this list in order, and don't forget to update the
1100 documentation in invoke.texi when adding a new processor or
1104 const char *const name; /* Canonical processor name. */
1105 const enum processor_type processor; /* Processor type enum value. */
1106 const int target_enable; /* Target flags to enable. */
1107 } const processor_target_table[]
1108 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1109 {"403", PROCESSOR_PPC403,
1110 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1111 {"405", PROCESSOR_PPC405,
1112 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW},
1113 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_MULHW},
1114 {"440", PROCESSOR_PPC440,
1115 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW},
1116 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_MULHW},
1117 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1118 {"601", PROCESSOR_PPC601,
1119 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1120 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1121 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1122 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1123 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1124 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1125 {"620", PROCESSOR_PPC620,
1126 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1127 {"630", PROCESSOR_PPC630,
1128 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1129 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1130 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1131 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1132 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1133 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1134 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1135 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1136 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1137 /* 8548 has a dummy entry for now. */
1138 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1139 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1140 {"970", PROCESSOR_POWER4,
1141 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1142 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1143 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1144 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1145 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1146 {"G5", PROCESSOR_POWER4,
1147 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1148 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1149 {"power2", PROCESSOR_POWER,
1150 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1151 {"power3", PROCESSOR_PPC630,
1152 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1153 {"power4", PROCESSOR_POWER4,
1154 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1155 {"power5", PROCESSOR_POWER5,
1156 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1157 | MASK_MFCRF | MASK_POPCNTB},
1158 {"power5+", PROCESSOR_POWER5,
1159 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1160 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1161 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1162 {"powerpc64", PROCESSOR_POWERPC64,
1163 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1164 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1165 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1166 {"rios2", PROCESSOR_RIOS2,
1167 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1168 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1169 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1170 {"rs64", PROCESSOR_RS64A,
1171 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1174 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1176 /* Some OSs don't support saving the high part of 64-bit registers on
1177 context switch. Other OSs don't support saving Altivec registers.
1178 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1179 settings; if the user wants either, the user must explicitly specify
1180 them and we won't interfere with the user's specification. */
1183 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1184 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1185 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1186 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW)
1189 rs6000_init_hard_regno_mode_ok ();
1191 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1192 #ifdef OS_MISSING_POWERPC64
1193 if (OS_MISSING_POWERPC64)
1194 set_masks &= ~MASK_POWERPC64;
1196 #ifdef OS_MISSING_ALTIVEC
1197 if (OS_MISSING_ALTIVEC)
1198 set_masks &= ~MASK_ALTIVEC;
1201 /* Don't override by the processor default if given explicitly. */
1202 set_masks &= ~target_flags_explicit;
1204 /* Identify the processor type. */
1205 rs6000_select[0].string = default_cpu;
1206 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1208 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1210 ptr = &rs6000_select[i];
1211 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1213 for (j = 0; j < ptt_size; j++)
1214 if (! strcmp (ptr->string, processor_target_table[j].name))
1216 if (ptr->set_tune_p)
1217 rs6000_cpu = processor_target_table[j].processor;
1219 if (ptr->set_arch_p)
1221 target_flags &= ~set_masks;
1222 target_flags |= (processor_target_table[j].target_enable
1229 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1236 /* If we are optimizing big endian systems for space, use the load/store
1237 multiple and string instructions. */
1238 if (BYTES_BIG_ENDIAN && optimize_size)
1239 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1241 /* Don't allow -mmultiple or -mstring on little endian systems
1242 unless the cpu is a 750, because the hardware doesn't support the
1243 instructions used in little endian mode, and causes an alignment
1244 trap. The 750 does not cause an alignment trap (except when the
1245 target is unaligned). */
1247 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1249 if (TARGET_MULTIPLE)
1251 target_flags &= ~MASK_MULTIPLE;
1252 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1253 warning (0, "-mmultiple is not supported on little endian systems");
1258 target_flags &= ~MASK_STRING;
1259 if ((target_flags_explicit & MASK_STRING) != 0)
1260 warning (0, "-mstring is not supported on little endian systems");
1264 /* Set debug flags */
1265 if (rs6000_debug_name)
1267 if (! strcmp (rs6000_debug_name, "all"))
1268 rs6000_debug_stack = rs6000_debug_arg = 1;
1269 else if (! strcmp (rs6000_debug_name, "stack"))
1270 rs6000_debug_stack = 1;
1271 else if (! strcmp (rs6000_debug_name, "arg"))
1272 rs6000_debug_arg = 1;
1274 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1277 if (rs6000_traceback_name)
1279 if (! strncmp (rs6000_traceback_name, "full", 4))
1280 rs6000_traceback = traceback_full;
1281 else if (! strncmp (rs6000_traceback_name, "part", 4))
1282 rs6000_traceback = traceback_part;
1283 else if (! strncmp (rs6000_traceback_name, "no", 2))
1284 rs6000_traceback = traceback_none;
1286 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1287 rs6000_traceback_name);
1290 if (!rs6000_explicit_options.long_double)
1291 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1293 /* Set Altivec ABI as default for powerpc64 linux. */
1294 if (TARGET_ELF && TARGET_64BIT)
1296 rs6000_altivec_abi = 1;
1297 TARGET_ALTIVEC_VRSAVE = 1;
1300 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1301 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1303 rs6000_darwin64_abi = 1;
1305 darwin_one_byte_bool = 1;
1307 /* Default to natural alignment, for better performance. */
1308 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1311 /* Handle -mtls-size option. */
1312 rs6000_parse_tls_size_option ();
1314 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1315 SUBTARGET_OVERRIDE_OPTIONS;
1317 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1318 SUBSUBTARGET_OVERRIDE_OPTIONS;
1320 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1321 SUB3TARGET_OVERRIDE_OPTIONS;
1327 error ("AltiVec and E500 instructions cannot coexist");
1329 /* The e500 does not have string instructions, and we set
1330 MASK_STRING above when optimizing for size. */
1331 if ((target_flags & MASK_STRING) != 0)
1332 target_flags = target_flags & ~MASK_STRING;
1334 else if (rs6000_select[1].string != NULL)
1336 /* For the powerpc-eabispe configuration, we set all these by
1337 default, so let's unset them if we manually set another
1338 CPU that is not the E500. */
1339 if (!rs6000_explicit_options.abi)
1341 if (!rs6000_explicit_options.spe)
1343 if (!rs6000_explicit_options.float_gprs)
1344 rs6000_float_gprs = 0;
1345 if (!rs6000_explicit_options.isel)
1347 if (!rs6000_explicit_options.long_double)
1348 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1351 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1352 && rs6000_cpu != PROCESSOR_POWER5);
1353 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1354 || rs6000_cpu == PROCESSOR_POWER5);
1356 rs6000_sched_restricted_insns_priority
1357 = (rs6000_sched_groups ? 1 : 0);
1359 /* Handle -msched-costly-dep option. */
1360 rs6000_sched_costly_dep
1361 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1363 if (rs6000_sched_costly_dep_str)
1365 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1366 rs6000_sched_costly_dep = no_dep_costly;
1367 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1368 rs6000_sched_costly_dep = all_deps_costly;
1369 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1370 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1371 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1372 rs6000_sched_costly_dep = store_to_load_dep_costly;
1374 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1377 /* Handle -minsert-sched-nops option. */
1378 rs6000_sched_insert_nops
1379 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1381 if (rs6000_sched_insert_nops_str)
1383 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1384 rs6000_sched_insert_nops = sched_finish_none;
1385 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1386 rs6000_sched_insert_nops = sched_finish_pad_groups;
1387 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1388 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1390 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1393 #ifdef TARGET_REGNAMES
1394 /* If the user desires alternate register names, copy in the
1395 alternate names now. */
1396 if (TARGET_REGNAMES)
1397 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1400 /* Set aix_struct_return last, after the ABI is determined.
1401 If -maix-struct-return or -msvr4-struct-return was explicitly
1402 used, don't override with the ABI default. */
1403 if (!rs6000_explicit_options.aix_struct_ret)
1404 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1406 if (TARGET_LONG_DOUBLE_128
1407 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1408 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1411 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1413 /* We can only guarantee the availability of DI pseudo-ops when
1414 assembling for 64-bit targets. */
1417 targetm.asm_out.aligned_op.di = NULL;
1418 targetm.asm_out.unaligned_op.di = NULL;
1421 /* Set branch target alignment, if not optimizing for size. */
1424 if (rs6000_sched_groups)
1426 if (align_functions <= 0)
1427 align_functions = 16;
1428 if (align_jumps <= 0)
1430 if (align_loops <= 0)
1433 if (align_jumps_max_skip <= 0)
1434 align_jumps_max_skip = 15;
1435 if (align_loops_max_skip <= 0)
1436 align_loops_max_skip = 15;
1439 /* Arrange to save and restore machine status around nested functions. */
1440 init_machine_status = rs6000_init_machine_status;
1442 /* We should always be splitting complex arguments, but we can't break
1443 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1444 if (DEFAULT_ABI != ABI_AIX)
1445 targetm.calls.split_complex_arg = NULL;
1447 /* Initialize rs6000_cost with the appropriate target costs. */
1449 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1453 case PROCESSOR_RIOS1:
1454 rs6000_cost = &rios1_cost;
1457 case PROCESSOR_RIOS2:
1458 rs6000_cost = &rios2_cost;
1461 case PROCESSOR_RS64A:
1462 rs6000_cost = &rs64a_cost;
1465 case PROCESSOR_MPCCORE:
1466 rs6000_cost = &mpccore_cost;
1469 case PROCESSOR_PPC403:
1470 rs6000_cost = &ppc403_cost;
1473 case PROCESSOR_PPC405:
1474 rs6000_cost = &ppc405_cost;
1477 case PROCESSOR_PPC440:
1478 rs6000_cost = &ppc440_cost;
1481 case PROCESSOR_PPC601:
1482 rs6000_cost = &ppc601_cost;
1485 case PROCESSOR_PPC603:
1486 rs6000_cost = &ppc603_cost;
1489 case PROCESSOR_PPC604:
1490 rs6000_cost = &ppc604_cost;
1493 case PROCESSOR_PPC604e:
1494 rs6000_cost = &ppc604e_cost;
1497 case PROCESSOR_PPC620:
1498 rs6000_cost = &ppc620_cost;
1501 case PROCESSOR_PPC630:
1502 rs6000_cost = &ppc630_cost;
1505 case PROCESSOR_PPC750:
1506 case PROCESSOR_PPC7400:
1507 rs6000_cost = &ppc750_cost;
1510 case PROCESSOR_PPC7450:
1511 rs6000_cost = &ppc7450_cost;
1514 case PROCESSOR_PPC8540:
1515 rs6000_cost = &ppc8540_cost;
1518 case PROCESSOR_POWER4:
1519 case PROCESSOR_POWER5:
1520 rs6000_cost = &power4_cost;
1528 /* Implement targetm.vectorize.builtin_mask_for_load. */
1530 rs6000_builtin_mask_for_load (void)
1533 return altivec_builtin_mask_for_load;
1538 /* Handle generic options of the form -mfoo=yes/no.
1539 NAME is the option name.
1540 VALUE is the option value.
1541 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1542 whether the option value is 'yes' or 'no' respectively. */
1544 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1548 else if (!strcmp (value, "yes"))
1550 else if (!strcmp (value, "no"))
1553 error ("unknown -m%s= option specified: '%s'", name, value);
1556 /* Validate and record the size specified with the -mtls-size option. */
1559 rs6000_parse_tls_size_option (void)
1561 if (rs6000_tls_size_string == 0)
1563 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1564 rs6000_tls_size = 16;
1565 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1566 rs6000_tls_size = 32;
1567 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1568 rs6000_tls_size = 64;
1570 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1574 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1576 if (DEFAULT_ABI == ABI_DARWIN)
1577 /* The Darwin libraries never set errno, so we might as well
1578 avoid calling them when that's the only reason we would. */
1579 flag_errno_math = 0;
1581 /* Double growth factor to counter reduced min jump length. */
1582 set_param_value ("max-grow-copy-bb-insns", 16);
1585 /* Implement TARGET_HANDLE_OPTION. */
1588 rs6000_handle_option (size_t code, const char *arg, int value)
1593 target_flags &= ~(MASK_POWER | MASK_POWER2
1594 | MASK_MULTIPLE | MASK_STRING);
1595 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1596 | MASK_MULTIPLE | MASK_STRING);
1598 case OPT_mno_powerpc:
1599 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1600 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1601 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1602 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1605 target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1606 | MASK_NO_SUM_IN_TOC);
1607 target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1608 | MASK_NO_SUM_IN_TOC);
1609 #ifdef TARGET_USES_SYSV4_OPT
1610 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1611 just the same as -mminimal-toc. */
1612 target_flags |= MASK_MINIMAL_TOC;
1613 target_flags_explicit |= MASK_MINIMAL_TOC;
1617 #ifdef TARGET_USES_SYSV4_OPT
1619 /* Make -mtoc behave like -mminimal-toc. */
1620 target_flags |= MASK_MINIMAL_TOC;
1621 target_flags_explicit |= MASK_MINIMAL_TOC;
1625 #ifdef TARGET_USES_AIX64_OPT
1630 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1631 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1632 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1635 #ifdef TARGET_USES_AIX64_OPT
1640 target_flags &= ~MASK_POWERPC64;
1641 target_flags_explicit |= MASK_POWERPC64;
1644 case OPT_minsert_sched_nops_:
1645 rs6000_sched_insert_nops_str = arg;
1648 case OPT_mminimal_toc:
1651 target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1652 target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1659 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1660 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1667 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1668 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1672 case OPT_mpowerpc_gpopt:
1673 case OPT_mpowerpc_gfxopt:
1676 target_flags |= MASK_POWERPC;
1677 target_flags_explicit |= MASK_POWERPC;
1681 case OPT_maix_struct_return:
1682 case OPT_msvr4_struct_return:
1683 rs6000_explicit_options.aix_struct_ret = true;
1687 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1691 rs6000_explicit_options.isel = true;
1692 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1696 rs6000_explicit_options.spe = true;
1697 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1698 /* No SPE means 64-bit long doubles, even if an E500. */
1700 rs6000_long_double_type_size = 64;
1704 rs6000_debug_name = arg;
1707 #ifdef TARGET_USES_SYSV4_OPT
1709 rs6000_abi_name = arg;
1713 rs6000_sdata_name = arg;
1716 case OPT_mtls_size_:
1717 rs6000_tls_size_string = arg;
1720 case OPT_mrelocatable:
1723 target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1724 target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1728 case OPT_mrelocatable_lib:
1731 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1732 | MASK_NO_FP_IN_TOC;
1733 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1734 | MASK_NO_FP_IN_TOC;
1738 target_flags &= ~MASK_RELOCATABLE;
1739 target_flags_explicit |= MASK_RELOCATABLE;
1745 rs6000_explicit_options.abi = true;
1746 if (!strcmp (arg, "altivec"))
1748 rs6000_altivec_abi = 1;
1751 else if (! strcmp (arg, "no-altivec"))
1752 rs6000_altivec_abi = 0;
1753 else if (! strcmp (arg, "spe"))
1756 rs6000_altivec_abi = 0;
1757 if (!TARGET_SPE_ABI)
1758 error ("not configured for ABI: '%s'", arg);
1760 else if (! strcmp (arg, "no-spe"))
1763 /* These are here for testing during development only, do not
1764 document in the manual please. */
1765 else if (! strcmp (arg, "d64"))
1767 rs6000_darwin64_abi = 1;
1768 warning (0, "Using darwin64 ABI");
1770 else if (! strcmp (arg, "d32"))
1772 rs6000_darwin64_abi = 0;
1773 warning (0, "Using old darwin ABI");
1778 error ("unknown ABI specified: '%s'", arg);
1784 rs6000_select[1].string = arg;
1788 rs6000_select[2].string = arg;
1791 case OPT_mtraceback_:
1792 rs6000_traceback_name = arg;
1795 case OPT_mfloat_gprs_:
1796 rs6000_explicit_options.float_gprs = true;
1797 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1798 rs6000_float_gprs = 1;
1799 else if (! strcmp (arg, "double"))
1800 rs6000_float_gprs = 2;
1801 else if (! strcmp (arg, "no"))
1802 rs6000_float_gprs = 0;
1805 error ("invalid option for -mfloat-gprs: '%s'", arg);
1810 case OPT_mlong_double_:
1811 rs6000_explicit_options.long_double = true;
1812 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1813 if (value != 64 && value != 128)
1815 error ("Unknown switch -mlong-double-%s", arg);
1816 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1820 rs6000_long_double_type_size = value;
1823 case OPT_msched_costly_dep_:
1824 rs6000_sched_costly_dep_str = arg;
1828 rs6000_explicit_options.alignment = true;
1829 if (! strcmp (arg, "power"))
1831 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1832 some C library functions, so warn about it. The flag may be
1833 useful for performance studies from time to time though, so
1834 don't disable it entirely. */
1835 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1836 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1837 " it is incompatible with the installed C and C++ libraries");
1838 rs6000_alignment_flags = MASK_ALIGN_POWER;
1840 else if (! strcmp (arg, "natural"))
1841 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1844 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1852 /* Do anything needed at the start of the asm file. */
1855 rs6000_file_start (void)
1859 const char *start = buffer;
1860 struct rs6000_cpu_select *ptr;
1861 const char *default_cpu = TARGET_CPU_DEFAULT;
1862 FILE *file = asm_out_file;
1864 default_file_start ();
1866 #ifdef TARGET_BI_ARCH
1867 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1871 if (flag_verbose_asm)
1873 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1874 rs6000_select[0].string = default_cpu;
1876 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1878 ptr = &rs6000_select[i];
1879 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1881 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1886 if (PPC405_ERRATUM77)
1888 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1892 #ifdef USING_ELFOS_H
1893 switch (rs6000_sdata)
1895 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1896 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1897 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1898 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1901 if (rs6000_sdata && g_switch_value)
1903 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1913 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1915 switch_to_section (toc_section);
1916 switch_to_section (text_section);
1921 /* Return nonzero if this function is known to have a null epilogue. */
1924 direct_return (void)
1926 if (reload_completed)
1928 rs6000_stack_t *info = rs6000_stack_info ();
1930 if (info->first_gp_reg_save == 32
1931 && info->first_fp_reg_save == 64
1932 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1933 && ! info->lr_save_p
1934 && ! info->cr_save_p
1935 && info->vrsave_mask == 0
1943 /* Return the number of instructions it takes to form a constant in an
1944 integer register. */
1947 num_insns_constant_wide (HOST_WIDE_INT value)
1949 /* signed constant loadable with {cal|addi} */
1950 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1953 /* constant loadable with {cau|addis} */
1954 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1957 #if HOST_BITS_PER_WIDE_INT == 64
1958 else if (TARGET_POWERPC64)
1960 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1961 HOST_WIDE_INT high = value >> 31;
1963 if (high == 0 || high == -1)
1969 return num_insns_constant_wide (high) + 1;
1971 return (num_insns_constant_wide (high)
1972 + num_insns_constant_wide (low) + 1);
1981 num_insns_constant (rtx op, enum machine_mode mode)
1983 HOST_WIDE_INT low, high;
1985 switch (GET_CODE (op))
1988 #if HOST_BITS_PER_WIDE_INT == 64
1989 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1990 && mask64_operand (op, mode))
1994 return num_insns_constant_wide (INTVAL (op));
2002 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2003 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2004 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2007 if (mode == VOIDmode || mode == DImode)
2009 high = CONST_DOUBLE_HIGH (op);
2010 low = CONST_DOUBLE_LOW (op);
2017 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2018 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2019 high = l[WORDS_BIG_ENDIAN == 0];
2020 low = l[WORDS_BIG_ENDIAN != 0];
2024 return (num_insns_constant_wide (low)
2025 + num_insns_constant_wide (high));
2028 if ((high == 0 && low >= 0)
2029 || (high == -1 && low < 0))
2030 return num_insns_constant_wide (low);
2032 else if (mask64_operand (op, mode))
2036 return num_insns_constant_wide (high) + 1;
2039 return (num_insns_constant_wide (high)
2040 + num_insns_constant_wide (low) + 1);
2049 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2050 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2051 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2052 all items are set to the same value and contain COPIES replicas of the
2053 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2054 operand and the others are set to the value of the operand's msb. */
2057 vspltis_constant (rtx op, unsigned step, unsigned copies)
2059 enum machine_mode mode = GET_MODE (op);
2060 enum machine_mode inner = GET_MODE_INNER (mode);
2063 unsigned nunits = GET_MODE_NUNITS (mode);
2064 unsigned bitsize = GET_MODE_BITSIZE (inner);
2065 unsigned mask = GET_MODE_MASK (inner);
2067 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2068 HOST_WIDE_INT val = INTVAL (last);
2069 HOST_WIDE_INT splat_val = val;
2070 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2072 /* Construct the value to be splatted, if possible. If not, return 0. */
2073 for (i = 2; i <= copies; i *= 2)
2075 HOST_WIDE_INT small_val;
2077 small_val = splat_val >> bitsize;
2079 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2081 splat_val = small_val;
2084 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2085 if (EASY_VECTOR_15 (splat_val))
2088 /* Also check if we can splat, and then add the result to itself. Do so if
2089 the value is positive, of if the splat instruction is using OP's mode;
2090 for splat_val < 0, the splat and the add should use the same mode. */
2091 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2092 && (splat_val >= 0 || (step == 1 && copies == 1)))
2098 /* Check if VAL is present in every STEP-th element, and the
2099 other elements are filled with its most significant bit. */
2100 for (i = 0; i < nunits - 1; ++i)
2102 HOST_WIDE_INT desired_val;
2103 if (((i + 1) & (step - 1)) == 0)
2106 desired_val = msb_val;
2108 if (desired_val != INTVAL (CONST_VECTOR_ELT (op, i)))
2116 /* Return true if OP is of the given MODE and can be synthesized
2117 with a vspltisb, vspltish or vspltisw. */
2120 easy_altivec_constant (rtx op, enum machine_mode mode)
2122 unsigned step, copies;
2124 if (mode == VOIDmode)
2125 mode = GET_MODE (op);
2126 else if (mode != GET_MODE (op))
2129 /* Start with a vspltisw. */
2130 step = GET_MODE_NUNITS (mode) / 4;
2133 if (vspltis_constant (op, step, copies))
2136 /* Then try with a vspltish. */
2142 if (vspltis_constant (op, step, copies))
2145 /* And finally a vspltisb. */
2151 if (vspltis_constant (op, step, copies))
2157 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2158 result is OP. Abort if it is not possible. */
2161 gen_easy_altivec_constant (rtx op)
2163 enum machine_mode mode = GET_MODE (op);
2164 int nunits = GET_MODE_NUNITS (mode);
2165 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2166 unsigned step = nunits / 4;
2167 unsigned copies = 1;
2169 /* Start with a vspltisw. */
2170 if (vspltis_constant (op, step, copies))
2171 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2173 /* Then try with a vspltish. */
2179 if (vspltis_constant (op, step, copies))
2180 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2182 /* And finally a vspltisb. */
2188 if (vspltis_constant (op, step, copies))
2189 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2195 output_vec_const_move (rtx *operands)
2198 enum machine_mode mode;
2203 mode = GET_MODE (dest);
2208 if (zero_constant (vec, mode))
2209 return "vxor %0,%0,%0";
2211 splat_vec = gen_easy_altivec_constant (vec);
2212 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2213 operands[1] = XEXP (splat_vec, 0);
2214 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2217 switch (GET_MODE (splat_vec))
2220 return "vspltisw %0,%1";
2223 return "vspltish %0,%1";
2226 return "vspltisb %0,%1";
2233 gcc_assert (TARGET_SPE);
2235 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2236 pattern of V1DI, V4HI, and V2SF.
2238 FIXME: We should probably return # and add post reload
2239 splitters for these, but this way is so easy ;-). */
2240 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2241 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2242 operands[1] = CONST_VECTOR_ELT (vec, 0);
2243 operands[2] = CONST_VECTOR_ELT (vec, 1);
2245 return "li %0,%1\n\tevmergelo %0,%0,%0";
2247 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2250 /* Initialize vector TARGET to VALS. */
2253 rs6000_expand_vector_init (rtx target, rtx vals)
2255 enum machine_mode mode = GET_MODE (target);
2256 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2257 int n_elts = GET_MODE_NUNITS (mode);
2258 int n_var = 0, one_var = -1;
2259 bool all_same = true, all_const_zero = true;
2263 for (i = 0; i < n_elts; ++i)
2265 x = XVECEXP (vals, 0, i);
2266 if (!CONSTANT_P (x))
2267 ++n_var, one_var = i;
2268 else if (x != CONST0_RTX (inner_mode))
2269 all_const_zero = false;
2271 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2277 if (mode != V4SFmode && all_const_zero)
2279 /* Zero register. */
2280 emit_insn (gen_rtx_SET (VOIDmode, target,
2281 gen_rtx_XOR (mode, target, target)));
2284 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2286 /* Splat immediate. */
2287 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2291 ; /* Splat vector element. */
2294 /* Load from constant pool. */
2295 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2300 /* Store value to stack temp. Load vector element. Splat. */
2303 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2304 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2305 XVECEXP (vals, 0, 0));
2306 x = gen_rtx_UNSPEC (VOIDmode,
2307 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2308 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2310 gen_rtx_SET (VOIDmode,
2313 x = gen_rtx_VEC_SELECT (inner_mode, target,
2314 gen_rtx_PARALLEL (VOIDmode,
2315 gen_rtvec (1, const0_rtx)));
2316 emit_insn (gen_rtx_SET (VOIDmode, target,
2317 gen_rtx_VEC_DUPLICATE (mode, x)));
2321 /* One field is non-constant. Load constant then overwrite
2325 rtx copy = copy_rtx (vals);
2327 /* Load constant part of vector, substitute neighboring value for
2329 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2330 rs6000_expand_vector_init (target, copy);
2332 /* Insert variable. */
2333 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2337 /* Construct the vector in memory one field at a time
2338 and load the whole vector. */
2339 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2340 for (i = 0; i < n_elts; i++)
2341 emit_move_insn (adjust_address_nv (mem, inner_mode,
2342 i * GET_MODE_SIZE (inner_mode)),
2343 XVECEXP (vals, 0, i));
2344 emit_move_insn (target, mem);
2347 /* Set field ELT of TARGET to VAL. */
2350 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2352 enum machine_mode mode = GET_MODE (target);
2353 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2354 rtx reg = gen_reg_rtx (mode);
2356 int width = GET_MODE_SIZE (inner_mode);
2359 /* Load single variable value. */
2360 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2361 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2362 x = gen_rtx_UNSPEC (VOIDmode,
2363 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2364 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2366 gen_rtx_SET (VOIDmode,
2370 /* Linear sequence. */
2371 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2372 for (i = 0; i < 16; ++i)
2373 XVECEXP (mask, 0, i) = GEN_INT (i);
2375 /* Set permute mask to insert element into target. */
2376 for (i = 0; i < width; ++i)
2377 XVECEXP (mask, 0, elt*width + i)
2378 = GEN_INT (i + 0x10);
2379 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2380 x = gen_rtx_UNSPEC (mode,
2381 gen_rtvec (3, target, reg,
2382 force_reg (V16QImode, x)),
2384 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2387 /* Extract field ELT from VEC into TARGET. */
2390 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2392 enum machine_mode mode = GET_MODE (vec);
2393 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2396 /* Allocate mode-sized buffer. */
2397 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2399 /* Add offset to field within buffer matching vector element. */
2400 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2402 /* Store single field into mode-sized buffer. */
2403 x = gen_rtx_UNSPEC (VOIDmode,
2404 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2405 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2407 gen_rtx_SET (VOIDmode,
2410 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2413 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2414 implement ANDing by the mask IN. */
2416 build_mask64_2_operands (rtx in, rtx *out)
2418 #if HOST_BITS_PER_WIDE_INT >= 64
2419 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2422 gcc_assert (GET_CODE (in) == CONST_INT);
2427 /* Assume c initially something like 0x00fff000000fffff. The idea
2428 is to rotate the word so that the middle ^^^^^^ group of zeros
2429 is at the MS end and can be cleared with an rldicl mask. We then
2430 rotate back and clear off the MS ^^ group of zeros with a
2432 c = ~c; /* c == 0xff000ffffff00000 */
2433 lsb = c & -c; /* lsb == 0x0000000000100000 */
2434 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2435 c = ~c; /* c == 0x00fff000000fffff */
2436 c &= -lsb; /* c == 0x00fff00000000000 */
2437 lsb = c & -c; /* lsb == 0x0000100000000000 */
2438 c = ~c; /* c == 0xff000fffffffffff */
2439 c &= -lsb; /* c == 0xff00000000000000 */
2441 while ((lsb >>= 1) != 0)
2442 shift++; /* shift == 44 on exit from loop */
2443 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2444 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2445 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2449 /* Assume c initially something like 0xff000f0000000000. The idea
2450 is to rotate the word so that the ^^^ middle group of zeros
2451 is at the LS end and can be cleared with an rldicr mask. We then
2452 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2454 lsb = c & -c; /* lsb == 0x0000010000000000 */
2455 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2456 c = ~c; /* c == 0x00fff0ffffffffff */
2457 c &= -lsb; /* c == 0x00fff00000000000 */
2458 lsb = c & -c; /* lsb == 0x0000100000000000 */
2459 c = ~c; /* c == 0xff000fffffffffff */
2460 c &= -lsb; /* c == 0xff00000000000000 */
2462 while ((lsb >>= 1) != 0)
2463 shift++; /* shift == 44 on exit from loop */
2464 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2465 m1 >>= shift; /* m1 == 0x0000000000000fff */
2466 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2469 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2470 masks will be all 1's. We are guaranteed more than one transition. */
2471 out[0] = GEN_INT (64 - shift);
2472 out[1] = GEN_INT (m1);
2473 out[2] = GEN_INT (shift);
2474 out[3] = GEN_INT (m2);
2482 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2485 invalid_e500_subreg (rtx op, enum machine_mode mode)
2487 /* Reject (subreg:SI (reg:DF)). */
2488 if (GET_CODE (op) == SUBREG
2490 && REG_P (SUBREG_REG (op))
2491 && GET_MODE (SUBREG_REG (op)) == DFmode)
2494 /* Reject (subreg:DF (reg:DI)). */
2495 if (GET_CODE (op) == SUBREG
2497 && REG_P (SUBREG_REG (op))
2498 && GET_MODE (SUBREG_REG (op)) == DImode)
2504 /* Darwin, AIX increases natural record alignment to doubleword if the first
2505 field is an FP double while the FP fields remain word aligned. */
2508 rs6000_special_round_type_align (tree type, unsigned int computed,
2509 unsigned int specified)
2511 unsigned int align = MAX (computed, specified);
2512 tree field = TYPE_FIELDS (type);
2514 /* Skip all non field decls */
2515 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2516 field = TREE_CHAIN (field);
2518 if (field != NULL && field != type)
2520 type = TREE_TYPE (field);
2521 while (TREE_CODE (type) == ARRAY_TYPE)
2522 type = TREE_TYPE (type);
2524 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2525 align = MAX (align, 64);
2531 /* Return 1 for an operand in small memory on V.4/eabi. */
2534 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2535 enum machine_mode mode ATTRIBUTE_UNUSED)
2540 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2543 if (DEFAULT_ABI != ABI_V4)
2546 if (GET_CODE (op) == SYMBOL_REF)
2549 else if (GET_CODE (op) != CONST
2550 || GET_CODE (XEXP (op, 0)) != PLUS
2551 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2552 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2557 rtx sum = XEXP (op, 0);
2558 HOST_WIDE_INT summand;
2560 /* We have to be careful here, because it is the referenced address
2561 that must be 32k from _SDA_BASE_, not just the symbol. */
2562 summand = INTVAL (XEXP (sum, 1));
2563 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2566 sym_ref = XEXP (sum, 0);
2569 return SYMBOL_REF_SMALL_P (sym_ref);
2575 /* Return true if either operand is a general purpose register. */
2578 gpr_or_gpr_p (rtx op0, rtx op1)
2580 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2581 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2585 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2588 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2590 switch (GET_CODE (op))
2593 if (RS6000_SYMBOL_REF_TLS_P (op))
2595 else if (CONSTANT_POOL_ADDRESS_P (op))
2597 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2605 else if (! strcmp (XSTR (op, 0), toc_label_name))
2614 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2615 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2617 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2626 constant_pool_expr_p (rtx op)
2630 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2634 toc_relative_expr_p (rtx op)
2638 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2642 legitimate_constant_pool_address_p (rtx x)
2645 && GET_CODE (x) == PLUS
2646 && GET_CODE (XEXP (x, 0)) == REG
2647 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2648 && constant_pool_expr_p (XEXP (x, 1)));
2652 rs6000_legitimate_small_data_p (enum machine_mode mode, rtx x)
2654 return (DEFAULT_ABI == ABI_V4
2655 && !flag_pic && !TARGET_TOC
2656 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2657 && small_data_operand (x, mode));
2660 /* SPE offset addressing is limited to 5-bits worth of double words. */
2661 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2664 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2666 unsigned HOST_WIDE_INT offset, extra;
2668 if (GET_CODE (x) != PLUS)
2670 if (GET_CODE (XEXP (x, 0)) != REG)
2672 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2674 if (legitimate_constant_pool_address_p (x))
2676 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2679 offset = INTVAL (XEXP (x, 1));
2687 /* AltiVec vector modes. Only reg+reg addressing is valid and
2688 constant offset zero should not occur due to canonicalization.
2689 Allow any offset when not strict before reload. */
2696 /* SPE vector modes. */
2697 return SPE_CONST_OFFSET_OK (offset);
2700 if (TARGET_E500_DOUBLE)
2701 return SPE_CONST_OFFSET_OK (offset);
2704 /* On e500v2, we may have:
2706 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2708 Which gets addressed with evldd instructions. */
2709 if (TARGET_E500_DOUBLE)
2710 return SPE_CONST_OFFSET_OK (offset);
2712 if (mode == DFmode || !TARGET_POWERPC64)
2714 else if (offset & 3)
2720 if (mode == TFmode || !TARGET_POWERPC64)
2722 else if (offset & 3)
2733 return (offset < 0x10000) && (offset + extra < 0x10000);
2737 legitimate_indexed_address_p (rtx x, int strict)
2741 if (GET_CODE (x) != PLUS)
2747 /* Recognize the rtl generated by reload which we know will later be
2748 replaced with proper base and index regs. */
2750 && reload_in_progress
2751 && (REG_P (op0) || GET_CODE (op0) == PLUS)
2755 return (REG_P (op0) && REG_P (op1)
2756 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
2757 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2758 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2759 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
2763 legitimate_indirect_address_p (rtx x, int strict)
2765 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2769 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2771 if (!TARGET_MACHO || !flag_pic
2772 || mode != SImode || GET_CODE (x) != MEM)
2776 if (GET_CODE (x) != LO_SUM)
2778 if (GET_CODE (XEXP (x, 0)) != REG)
2780 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2784 return CONSTANT_P (x);
2788 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2790 if (GET_CODE (x) != LO_SUM)
2792 if (GET_CODE (XEXP (x, 0)) != REG)
2794 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2796 /* Restrict addressing for DI because of our SUBREG hackery. */
2797 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2801 if (TARGET_ELF || TARGET_MACHO)
2803 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2807 if (GET_MODE_NUNITS (mode) != 1)
2809 if (GET_MODE_BITSIZE (mode) > 64
2810 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2811 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2814 return CONSTANT_P (x);
2821 /* Try machine-dependent ways of modifying an illegitimate address
2822 to be legitimate. If we find one, return the new, valid address.
2823 This is used from only one place: `memory_address' in explow.c.
2825 OLDX is the address as it was before break_out_memory_refs was
2826 called. In some cases it is useful to look at this to decide what
2829 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2831 It is always safe for this function to do nothing. It exists to
2832 recognize opportunities to optimize the output.
2834 On RS/6000, first check for the sum of a register with a constant
2835 integer that is out of range. If so, generate code to add the
2836 constant with the low-order 16 bits masked to the register and force
2837 this result into another register (this can be done with `cau').
2838 Then generate an address of REG+(CONST&0xffff), allowing for the
2839 possibility of bit 16 being a one.
2841 Then check for the sum of a register and something not constant, try to
2842 load the other things into a register and return the sum. */
2845 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2846 enum machine_mode mode)
2848 if (GET_CODE (x) == SYMBOL_REF)
2850 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2852 return rs6000_legitimize_tls_address (x, model);
2855 if (GET_CODE (x) == PLUS
2856 && GET_CODE (XEXP (x, 0)) == REG
2857 && GET_CODE (XEXP (x, 1)) == CONST_INT
2858 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2860 HOST_WIDE_INT high_int, low_int;
2862 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2863 high_int = INTVAL (XEXP (x, 1)) - low_int;
2864 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2865 GEN_INT (high_int)), 0);
2866 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2868 else if (GET_CODE (x) == PLUS
2869 && GET_CODE (XEXP (x, 0)) == REG
2870 && GET_CODE (XEXP (x, 1)) != CONST_INT
2871 && GET_MODE_NUNITS (mode) == 1
2872 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2874 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2876 && (TARGET_POWERPC64 || mode != DImode)
2879 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2880 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2882 else if (ALTIVEC_VECTOR_MODE (mode))
2886 /* Make sure both operands are registers. */
2887 if (GET_CODE (x) == PLUS)
2888 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2889 force_reg (Pmode, XEXP (x, 1)));
2891 reg = force_reg (Pmode, x);
2894 else if (SPE_VECTOR_MODE (mode)
2895 || (TARGET_E500_DOUBLE && (mode == DFmode
2896 || mode == DImode)))
2900 /* We accept [reg + reg] and [reg + OFFSET]. */
2902 if (GET_CODE (x) == PLUS)
2904 rtx op1 = XEXP (x, 0);
2905 rtx op2 = XEXP (x, 1);
2907 op1 = force_reg (Pmode, op1);
2909 if (GET_CODE (op2) != REG
2910 && (GET_CODE (op2) != CONST_INT
2911 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2912 op2 = force_reg (Pmode, op2);
2914 return gen_rtx_PLUS (Pmode, op1, op2);
2917 return force_reg (Pmode, x);
2923 && GET_CODE (x) != CONST_INT
2924 && GET_CODE (x) != CONST_DOUBLE
2926 && GET_MODE_NUNITS (mode) == 1
2927 && (GET_MODE_BITSIZE (mode) <= 32
2928 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2930 rtx reg = gen_reg_rtx (Pmode);
2931 emit_insn (gen_elf_high (reg, x));
2932 return gen_rtx_LO_SUM (Pmode, reg, x);
2934 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2937 && ! MACHO_DYNAMIC_NO_PIC_P
2939 && GET_CODE (x) != CONST_INT
2940 && GET_CODE (x) != CONST_DOUBLE
2942 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2946 rtx reg = gen_reg_rtx (Pmode);
2947 emit_insn (gen_macho_high (reg, x));
2948 return gen_rtx_LO_SUM (Pmode, reg, x);
2951 && constant_pool_expr_p (x)
2952 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2954 return create_TOC_reference (x);
2960 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
2961 We need to emit DTP-relative relocations. */
2964 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2969 fputs ("\t.long\t", file);
2972 fputs (DOUBLE_INT_ASM_OP, file);
2977 output_addr_const (file, x);
2978 fputs ("@dtprel+0x8000", file);
2981 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2983 static GTY(()) rtx rs6000_tls_symbol;
2985 rs6000_tls_get_addr (void)
2987 if (!rs6000_tls_symbol)
2988 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2990 return rs6000_tls_symbol;
2993 /* Construct the SYMBOL_REF for TLS GOT references. */
2995 static GTY(()) rtx rs6000_got_symbol;
2997 rs6000_got_sym (void)
2999 if (!rs6000_got_symbol)
3001 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3002 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3003 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3006 return rs6000_got_symbol;
3009 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3010 this (thread-local) address. */
3013 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3017 dest = gen_reg_rtx (Pmode);
3018 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3024 tlsreg = gen_rtx_REG (Pmode, 13);
3025 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3029 tlsreg = gen_rtx_REG (Pmode, 2);
3030 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3034 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3038 tmp = gen_reg_rtx (Pmode);
3041 tlsreg = gen_rtx_REG (Pmode, 13);
3042 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3046 tlsreg = gen_rtx_REG (Pmode, 2);
3047 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3051 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3053 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3058 rtx r3, got, tga, tmp1, tmp2, eqv;
3060 /* We currently use relocations like @got@tlsgd for tls, which
3061 means the linker will handle allocation of tls entries, placing
3062 them in the .got section. So use a pointer to the .got section,
3063 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3064 or to secondary GOT sections used by 32-bit -fPIC. */
3066 got = gen_rtx_REG (Pmode, 2);
3070 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3073 rtx gsym = rs6000_got_sym ();
3074 got = gen_reg_rtx (Pmode);
3076 rs6000_emit_move (got, gsym, Pmode);
3079 rtx tempLR, tmp3, mem;
3082 tempLR = gen_reg_rtx (Pmode);
3083 tmp1 = gen_reg_rtx (Pmode);
3084 tmp2 = gen_reg_rtx (Pmode);
3085 tmp3 = gen_reg_rtx (Pmode);
3086 mem = gen_const_mem (Pmode, tmp1);
3088 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3089 emit_move_insn (tmp1, tempLR);
3090 emit_move_insn (tmp2, mem);
3091 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3092 last = emit_move_insn (got, tmp3);
3093 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3095 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3097 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3103 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3105 r3 = gen_rtx_REG (Pmode, 3);
3107 insn = gen_tls_gd_64 (r3, got, addr);
3109 insn = gen_tls_gd_32 (r3, got, addr);
3112 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3113 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3114 insn = emit_call_insn (insn);
3115 CONST_OR_PURE_CALL_P (insn) = 1;
3116 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3117 insn = get_insns ();
3119 emit_libcall_block (insn, dest, r3, addr);
3121 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3123 r3 = gen_rtx_REG (Pmode, 3);
3125 insn = gen_tls_ld_64 (r3, got);
3127 insn = gen_tls_ld_32 (r3, got);
3130 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3131 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3132 insn = emit_call_insn (insn);
3133 CONST_OR_PURE_CALL_P (insn) = 1;
3134 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3135 insn = get_insns ();
3137 tmp1 = gen_reg_rtx (Pmode);
3138 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3140 emit_libcall_block (insn, tmp1, r3, eqv);
3141 if (rs6000_tls_size == 16)
3144 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3146 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3148 else if (rs6000_tls_size == 32)
3150 tmp2 = gen_reg_rtx (Pmode);
3152 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3154 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3157 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3159 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3163 tmp2 = gen_reg_rtx (Pmode);
3165 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3167 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3169 insn = gen_rtx_SET (Pmode, dest,
3170 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3176 /* IE, or 64 bit offset LE. */
3177 tmp2 = gen_reg_rtx (Pmode);
3179 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3181 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3184 insn = gen_tls_tls_64 (dest, tmp2, addr);
3186 insn = gen_tls_tls_32 (dest, tmp2, addr);
3194 /* Return 1 if X contains a thread-local symbol. */
3197 rs6000_tls_referenced_p (rtx x)
3199 if (! TARGET_HAVE_TLS)
3202 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3205 /* Return 1 if *X is a thread-local symbol. This is the same as
3206 rs6000_tls_symbol_ref except for the type of the unused argument. */
3209 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3211 return RS6000_SYMBOL_REF_TLS_P (*x);
3214 /* The convention appears to be to define this wherever it is used.
3215 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3216 is now used here. */
3217 #ifndef REG_MODE_OK_FOR_BASE_P
3218 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3221 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3222 replace the input X, or the original X if no replacement is called for.
3223 The output parameter *WIN is 1 if the calling macro should goto WIN,
3226 For RS/6000, we wish to handle large displacements off a base
3227 register by splitting the addend across an addiu/addis and the mem insn.
3228 This cuts number of extra insns needed from 3 to 1.
3230 On Darwin, we use this to generate code for floating point constants.
3231 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3232 The Darwin code is inside #if TARGET_MACHO because only then is
3233 machopic_function_base_name() defined. */
3235 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3236 int opnum, int type,
3237 int ind_levels ATTRIBUTE_UNUSED, int *win)
3239 /* We must recognize output that we have already generated ourselves. */
3240 if (GET_CODE (x) == PLUS
3241 && GET_CODE (XEXP (x, 0)) == PLUS
3242 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3243 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3244 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3246 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3247 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3248 opnum, (enum reload_type)type);
3254 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3255 && GET_CODE (x) == LO_SUM
3256 && GET_CODE (XEXP (x, 0)) == PLUS
3257 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3258 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3259 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3260 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3261 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3262 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3263 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3265 /* Result of previous invocation of this function on Darwin
3266 floating point constant. */
3267 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3268 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3269 opnum, (enum reload_type)type);
3275 /* Force ld/std non-word aligned offset into base register by wrapping
3277 if (GET_CODE (x) == PLUS
3278 && GET_CODE (XEXP (x, 0)) == REG
3279 && REGNO (XEXP (x, 0)) < 32
3280 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3281 && GET_CODE (XEXP (x, 1)) == CONST_INT
3282 && (INTVAL (XEXP (x, 1)) & 3) != 0
3283 && !ALTIVEC_VECTOR_MODE (mode)
3284 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3285 && TARGET_POWERPC64)
3287 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3288 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3289 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3290 opnum, (enum reload_type) type);
3295 if (GET_CODE (x) == PLUS
3296 && GET_CODE (XEXP (x, 0)) == REG
3297 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3298 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3299 && GET_CODE (XEXP (x, 1)) == CONST_INT
3300 && !SPE_VECTOR_MODE (mode)
3301 && !(TARGET_E500_DOUBLE && (mode == DFmode
3303 && !ALTIVEC_VECTOR_MODE (mode))
3305 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3306 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3308 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3310 /* Check for 32-bit overflow. */
3311 if (high + low != val)
3317 /* Reload the high part into a base reg; leave the low part
3318 in the mem directly. */
3320 x = gen_rtx_PLUS (GET_MODE (x),
3321 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3325 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3326 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3327 opnum, (enum reload_type)type);
3332 if (GET_CODE (x) == SYMBOL_REF
3333 && !ALTIVEC_VECTOR_MODE (mode)
3335 && DEFAULT_ABI == ABI_DARWIN
3336 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3338 && DEFAULT_ABI == ABI_V4
3341 /* Don't do this for TFmode, since the result isn't offsettable.
3342 The same goes for DImode without 64-bit gprs. */
3344 && (mode != DImode || TARGET_POWERPC64))
3349 rtx offset = gen_rtx_CONST (Pmode,
3350 gen_rtx_MINUS (Pmode, x,
3351 machopic_function_base_sym ()));
3352 x = gen_rtx_LO_SUM (GET_MODE (x),
3353 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3354 gen_rtx_HIGH (Pmode, offset)), offset);
3358 x = gen_rtx_LO_SUM (GET_MODE (x),
3359 gen_rtx_HIGH (Pmode, x), x);
3361 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3362 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3363 opnum, (enum reload_type)type);
3368 /* Reload an offset address wrapped by an AND that represents the
3369 masking of the lower bits. Strip the outer AND and let reload
3370 convert the offset address into an indirect address. */
3372 && ALTIVEC_VECTOR_MODE (mode)
3373 && GET_CODE (x) == AND
3374 && GET_CODE (XEXP (x, 0)) == PLUS
3375 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3376 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3377 && GET_CODE (XEXP (x, 1)) == CONST_INT
3378 && INTVAL (XEXP (x, 1)) == -16)
3386 && constant_pool_expr_p (x)
3387 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3389 (x) = create_TOC_reference (x);
3397 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3398 that is a valid memory address for an instruction.
3399 The MODE argument is the machine mode for the MEM expression
3400 that wants to use this address.
3402 On the RS/6000, there are four valid address: a SYMBOL_REF that
3403 refers to a constant pool entry of an address (or the sum of it
3404 plus a constant), a short (16-bit signed) constant plus a register,
3405 the sum of two registers, or a register indirect, possibly with an
3406 auto-increment. For DFmode and DImode with a constant plus register,
3407 we must ensure that both words are addressable or PowerPC64 with offset
3410 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3411 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3412 adjacent memory cells are accessed by adding word-sized offsets
3413 during assembly output. */
3415 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3417 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3419 && ALTIVEC_VECTOR_MODE (mode)
3420 && GET_CODE (x) == AND
3421 && GET_CODE (XEXP (x, 1)) == CONST_INT
3422 && INTVAL (XEXP (x, 1)) == -16)
3425 if (RS6000_SYMBOL_REF_TLS_P (x))
3427 if (legitimate_indirect_address_p (x, reg_ok_strict))
3429 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3430 && !ALTIVEC_VECTOR_MODE (mode)
3431 && !SPE_VECTOR_MODE (mode)
3432 /* Restrict addressing for DI because of our SUBREG hackery. */
3433 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3435 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3437 if (rs6000_legitimate_small_data_p (mode, x))
3439 if (legitimate_constant_pool_address_p (x))
3441 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3443 && GET_CODE (x) == PLUS
3444 && GET_CODE (XEXP (x, 0)) == REG
3445 && (XEXP (x, 0) == virtual_stack_vars_rtx
3446 || XEXP (x, 0) == arg_pointer_rtx)
3447 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3449 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3453 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3455 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3456 && (TARGET_POWERPC64 || mode != DImode)
3457 && legitimate_indexed_address_p (x, reg_ok_strict))
3459 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3464 /* Go to LABEL if ADDR (a legitimate address expression)
3465 has an effect that depends on the machine mode it is used for.
3467 On the RS/6000 this is true of all integral offsets (since AltiVec
3468 modes don't allow them) or is a pre-increment or decrement.
3470 ??? Except that due to conceptual problems in offsettable_address_p
3471 we can't really report the problems of integral offsets. So leave
3472 this assuming that the adjustable offset must be valid for the
3473 sub-words of a TFmode operand, which is what we had before. */
3476 rs6000_mode_dependent_address (rtx addr)
3478 switch (GET_CODE (addr))
3481 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3483 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3484 return val + 12 + 0x8000 >= 0x10000;
3493 return TARGET_UPDATE;
3502 /* Return number of consecutive hard regs needed starting at reg REGNO
3503 to hold something of mode MODE.
3504 This is ordinarily the length in words of a value of mode MODE
3505 but can be less for certain modes in special long registers.
3507 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3508 scalar instructions. The upper 32 bits are only available to the
3511 POWER and PowerPC GPRs hold 32 bits worth;
3512 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3515 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3517 if (FP_REGNO_P (regno))
3518 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3520 if (TARGET_E500_DOUBLE && mode == DFmode)
3523 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3524 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3526 if (ALTIVEC_REGNO_P (regno))
3528 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3530 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3533 /* Change register usage conditional on target flags. */
3535 rs6000_conditional_register_usage (void)
3539 /* Set MQ register fixed (already call_used) if not POWER
3540 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3545 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3547 fixed_regs[13] = call_used_regs[13]
3548 = call_really_used_regs[13] = 1;
3550 /* Conditionally disable FPRs. */
3551 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3552 for (i = 32; i < 64; i++)
3553 fixed_regs[i] = call_used_regs[i]
3554 = call_really_used_regs[i] = 1;
3556 /* The TOC register is not killed across calls in a way that is
3557 visible to the compiler. */
3558 if (DEFAULT_ABI == ABI_AIX)
3559 call_really_used_regs[2] = 0;
3561 if (DEFAULT_ABI == ABI_V4
3562 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3564 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3566 if (DEFAULT_ABI == ABI_V4
3567 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3569 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3570 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3571 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3573 if (DEFAULT_ABI == ABI_DARWIN
3574 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3575 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3576 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3577 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3579 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3580 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3581 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3584 global_regs[VSCR_REGNO] = 1;
3588 global_regs[SPEFSCR_REGNO] = 1;
3589 fixed_regs[FIXED_SCRATCH]
3590 = call_used_regs[FIXED_SCRATCH]
3591 = call_really_used_regs[FIXED_SCRATCH] = 1;
3594 if (! TARGET_ALTIVEC)
3596 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3597 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3598 call_really_used_regs[VRSAVE_REGNO] = 1;
3601 if (TARGET_ALTIVEC_ABI)
3602 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3603 call_used_regs[i] = call_really_used_regs[i] = 1;
3606 /* Try to output insns to set TARGET equal to the constant C if it can
3607 be done in less than N insns. Do all computations in MODE.
3608 Returns the place where the output has been placed if it can be
3609 done and the insns have been emitted. If it would take more than N
3610 insns, zero is returned and no insns and emitted. */
3613 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3614 rtx source, int n ATTRIBUTE_UNUSED)
3616 rtx result, insn, set;
3617 HOST_WIDE_INT c0, c1;
3624 dest = gen_reg_rtx (mode);
3625 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3629 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3631 emit_insn (gen_rtx_SET (VOIDmode, result,
3632 GEN_INT (INTVAL (source)
3633 & (~ (HOST_WIDE_INT) 0xffff))));
3634 emit_insn (gen_rtx_SET (VOIDmode, dest,
3635 gen_rtx_IOR (SImode, result,
3636 GEN_INT (INTVAL (source) & 0xffff))));
3641 switch (GET_CODE (source))
3644 c0 = INTVAL (source);
3649 #if HOST_BITS_PER_WIDE_INT >= 64
3650 c0 = CONST_DOUBLE_LOW (source);
3653 c0 = CONST_DOUBLE_LOW (source);
3654 c1 = CONST_DOUBLE_HIGH (source);
3662 result = rs6000_emit_set_long_const (dest, c0, c1);
3669 insn = get_last_insn ();
3670 set = single_set (insn);
3671 if (! CONSTANT_P (SET_SRC (set)))
3672 set_unique_reg_note (insn, REG_EQUAL, source);
3677 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3678 fall back to a straight forward decomposition. We do this to avoid
3679 exponential run times encountered when looking for longer sequences
3680 with rs6000_emit_set_const. */
3682 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3684 if (!TARGET_POWERPC64)
3686 rtx operand1, operand2;
3688 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3690 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3692 emit_move_insn (operand1, GEN_INT (c1));
3693 emit_move_insn (operand2, GEN_INT (c2));
3697 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3700 ud2 = (c1 & 0xffff0000) >> 16;
3701 #if HOST_BITS_PER_WIDE_INT >= 64
3705 ud4 = (c2 & 0xffff0000) >> 16;
3707 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3708 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3711 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3713 emit_move_insn (dest, GEN_INT (ud1));
3716 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3717 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3720 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3723 emit_move_insn (dest, GEN_INT (ud2 << 16));
3725 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3727 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3728 || (ud4 == 0 && ! (ud3 & 0x8000)))
3731 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3734 emit_move_insn (dest, GEN_INT (ud3 << 16));
3737 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3738 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3740 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3745 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3748 emit_move_insn (dest, GEN_INT (ud4 << 16));
3751 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3753 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3755 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3756 GEN_INT (ud2 << 16)));
3758 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3764 /* Helper for the following. Get rid of [r+r] memory refs
3765 in cases where it won't work (TImode, TFmode). */
3768 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3770 if (GET_CODE (operands[0]) == MEM
3771 && GET_CODE (XEXP (operands[0], 0)) != REG
3772 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3773 && ! reload_in_progress)
3775 = replace_equiv_address (operands[0],
3776 copy_addr_to_reg (XEXP (operands[0], 0)));
3778 if (GET_CODE (operands[1]) == MEM
3779 && GET_CODE (XEXP (operands[1], 0)) != REG
3780 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3781 && ! reload_in_progress)
3783 = replace_equiv_address (operands[1],
3784 copy_addr_to_reg (XEXP (operands[1], 0)));
3787 /* Emit a move from SOURCE to DEST in mode MODE. */
3789 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3793 operands[1] = source;
3795 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3796 if (GET_CODE (operands[1]) == CONST_DOUBLE
3797 && ! FLOAT_MODE_P (mode)
3798 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3800 /* FIXME. This should never happen. */
3801 /* Since it seems that it does, do the safe thing and convert
3803 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3805 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3806 || FLOAT_MODE_P (mode)
3807 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3808 || CONST_DOUBLE_LOW (operands[1]) < 0)
3809 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3810 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3812 /* Check if GCC is setting up a block move that will end up using FP
3813 registers as temporaries. We must make sure this is acceptable. */
3814 if (GET_CODE (operands[0]) == MEM
3815 && GET_CODE (operands[1]) == MEM
3817 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3818 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3819 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3820 ? 32 : MEM_ALIGN (operands[0])))
3821 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3823 : MEM_ALIGN (operands[1]))))
3824 && ! MEM_VOLATILE_P (operands [0])
3825 && ! MEM_VOLATILE_P (operands [1]))
3827 emit_move_insn (adjust_address (operands[0], SImode, 0),
3828 adjust_address (operands[1], SImode, 0));
3829 emit_move_insn (adjust_address (operands[0], SImode, 4),
3830 adjust_address (operands[1], SImode, 4));
3834 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3835 && !gpc_reg_operand (operands[1], mode))
3836 operands[1] = force_reg (mode, operands[1]);
3838 if (mode == SFmode && ! TARGET_POWERPC
3839 && TARGET_HARD_FLOAT && TARGET_FPRS
3840 && GET_CODE (operands[0]) == MEM)
3844 if (reload_in_progress || reload_completed)
3845 regnum = true_regnum (operands[1]);
3846 else if (GET_CODE (operands[1]) == REG)
3847 regnum = REGNO (operands[1]);
3851 /* If operands[1] is a register, on POWER it may have
3852 double-precision data in it, so truncate it to single
3854 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3857 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3858 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3859 operands[1] = newreg;
3863 /* Recognize the case where operand[1] is a reference to thread-local
3864 data and load its address to a register. */
3865 if (rs6000_tls_referenced_p (operands[1]))
3867 enum tls_model model;
3868 rtx tmp = operands[1];
3871 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3873 addend = XEXP (XEXP (tmp, 0), 1);
3874 tmp = XEXP (XEXP (tmp, 0), 0);
3877 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3878 model = SYMBOL_REF_TLS_MODEL (tmp);
3879 gcc_assert (model != 0);
3881 tmp = rs6000_legitimize_tls_address (tmp, model);
3884 tmp = gen_rtx_PLUS (mode, tmp, addend);
3885 tmp = force_operand (tmp, operands[0]);
3890 /* Handle the case where reload calls us with an invalid address. */
3891 if (reload_in_progress && mode == Pmode
3892 && (! general_operand (operands[1], mode)
3893 || ! nonimmediate_operand (operands[0], mode)))
3896 /* 128-bit constant floating-point values on Darwin should really be
3897 loaded as two parts. */
3898 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3899 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3900 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3902 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3903 know how to get a DFmode SUBREG of a TFmode. */
3904 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3905 simplify_gen_subreg (DImode, operands[1], mode, 0),
3907 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3908 GET_MODE_SIZE (DImode)),
3909 simplify_gen_subreg (DImode, operands[1], mode,
3910 GET_MODE_SIZE (DImode)),
3915 /* FIXME: In the long term, this switch statement should go away
3916 and be replaced by a sequence of tests based on things like
3922 if (CONSTANT_P (operands[1])
3923 && GET_CODE (operands[1]) != CONST_INT)
3924 operands[1] = force_const_mem (mode, operands[1]);
3928 rs6000_eliminate_indexed_memrefs (operands);
3933 if (CONSTANT_P (operands[1])
3934 && ! easy_fp_constant (operands[1], mode))
3935 operands[1] = force_const_mem (mode, operands[1]);
3946 if (CONSTANT_P (operands[1])
3947 && !easy_vector_constant (operands[1], mode))
3948 operands[1] = force_const_mem (mode, operands[1]);
3953 /* Use default pattern for address of ELF small data */
3956 && DEFAULT_ABI == ABI_V4
3957 && (GET_CODE (operands[1]) == SYMBOL_REF
3958 || GET_CODE (operands[1]) == CONST)
3959 && small_data_operand (operands[1], mode))
3961 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3965 if (DEFAULT_ABI == ABI_V4
3966 && mode == Pmode && mode == SImode
3967 && flag_pic == 1 && got_operand (operands[1], mode))
3969 emit_insn (gen_movsi_got (operands[0], operands[1]));
3973 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3977 && CONSTANT_P (operands[1])
3978 && GET_CODE (operands[1]) != HIGH
3979 && GET_CODE (operands[1]) != CONST_INT)
3981 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3983 /* If this is a function address on -mcall-aixdesc,
3984 convert it to the address of the descriptor. */
3985 if (DEFAULT_ABI == ABI_AIX
3986 && GET_CODE (operands[1]) == SYMBOL_REF
3987 && XSTR (operands[1], 0)[0] == '.')
3989 const char *name = XSTR (operands[1], 0);
3991 while (*name == '.')
3993 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3994 CONSTANT_POOL_ADDRESS_P (new_ref)
3995 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3996 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3997 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3998 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3999 operands[1] = new_ref;
4002 if (DEFAULT_ABI == ABI_DARWIN)
4005 if (MACHO_DYNAMIC_NO_PIC_P)
4007 /* Take care of any required data indirection. */
4008 operands[1] = rs6000_machopic_legitimize_pic_address (
4009 operands[1], mode, operands[0]);
4010 if (operands[0] != operands[1])
4011 emit_insn (gen_rtx_SET (VOIDmode,
4012 operands[0], operands[1]));
4016 emit_insn (gen_macho_high (target, operands[1]));
4017 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4021 emit_insn (gen_elf_high (target, operands[1]));
4022 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4026 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4027 and we have put it in the TOC, we just need to make a TOC-relative
4030 && GET_CODE (operands[1]) == SYMBOL_REF
4031 && constant_pool_expr_p (operands[1])
4032 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4033 get_pool_mode (operands[1])))
4035 operands[1] = create_TOC_reference (operands[1]);
4037 else if (mode == Pmode
4038 && CONSTANT_P (operands[1])
4039 && ((GET_CODE (operands[1]) != CONST_INT
4040 && ! easy_fp_constant (operands[1], mode))
4041 || (GET_CODE (operands[1]) == CONST_INT
4042 && num_insns_constant (operands[1], mode) > 2)
4043 || (GET_CODE (operands[0]) == REG
4044 && FP_REGNO_P (REGNO (operands[0]))))
4045 && GET_CODE (operands[1]) != HIGH
4046 && ! legitimate_constant_pool_address_p (operands[1])
4047 && ! toc_relative_expr_p (operands[1]))
4049 /* Emit a USE operation so that the constant isn't deleted if
4050 expensive optimizations are turned on because nobody
4051 references it. This should only be done for operands that
4052 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4053 This should not be done for operands that contain LABEL_REFs.
4054 For now, we just handle the obvious case. */
4055 if (GET_CODE (operands[1]) != LABEL_REF)
4056 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4059 /* Darwin uses a special PIC legitimizer. */
4060 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4063 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4065 if (operands[0] != operands[1])
4066 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4071 /* If we are to limit the number of things we put in the TOC and
4072 this is a symbol plus a constant we can add in one insn,
4073 just put the symbol in the TOC and add the constant. Don't do
4074 this if reload is in progress. */
4075 if (GET_CODE (operands[1]) == CONST
4076 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4077 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4078 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4079 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4080 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4081 && ! side_effects_p (operands[0]))
4084 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4085 rtx other = XEXP (XEXP (operands[1], 0), 1);
4087 sym = force_reg (mode, sym);
4089 emit_insn (gen_addsi3 (operands[0], sym, other));
4091 emit_insn (gen_adddi3 (operands[0], sym, other));
4095 operands[1] = force_const_mem (mode, operands[1]);
4098 && constant_pool_expr_p (XEXP (operands[1], 0))
4099 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4100 get_pool_constant (XEXP (operands[1], 0)),
4101 get_pool_mode (XEXP (operands[1], 0))))
4104 = gen_const_mem (mode,
4105 create_TOC_reference (XEXP (operands[1], 0)));
4106 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4112 rs6000_eliminate_indexed_memrefs (operands);
4116 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4118 gen_rtx_SET (VOIDmode,
4119 operands[0], operands[1]),
4120 gen_rtx_CLOBBER (VOIDmode,
4121 gen_rtx_SCRATCH (SImode)))));
4130 /* Above, we may have called force_const_mem which may have returned
4131 an invalid address. If we can, fix this up; otherwise, reload will
4132 have to deal with it. */
4133 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4134 operands[1] = validize_mem (operands[1]);
4137 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4140 /* Nonzero if we can use a floating-point register to pass this arg. */
4141 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4142 (SCALAR_FLOAT_MODE_P (MODE) \
4143 && (CUM)->fregno <= FP_ARG_MAX_REG \
4144 && TARGET_HARD_FLOAT && TARGET_FPRS)
4146 /* Nonzero if we can use an AltiVec register to pass this arg. */
4147 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4148 (ALTIVEC_VECTOR_MODE (MODE) \
4149 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4150 && TARGET_ALTIVEC_ABI \
4153 /* Return a nonzero value to say to return the function value in
4154 memory, just as large structures are always returned. TYPE will be
4155 the data type of the value, and FNTYPE will be the type of the
4156 function doing the returning, or @code{NULL} for libcalls.
4158 The AIX ABI for the RS/6000 specifies that all structures are
4159 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4160 specifies that structures <= 8 bytes are returned in r3/r4, but a
4161 draft put them in memory, and GCC used to implement the draft
4162 instead of the final standard. Therefore, aix_struct_return
4163 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4164 compatibility can change DRAFT_V4_STRUCT_RET to override the
4165 default, and -m switches get the final word. See
4166 rs6000_override_options for more details.
4168 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4169 long double support is enabled. These values are returned in memory.
4171 int_size_in_bytes returns -1 for variable size objects, which go in
4172 memory always. The cast to unsigned makes -1 > 8. */
4175 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4177 /* In the darwin64 abi, try to use registers for larger structs
4179 if (rs6000_darwin64_abi
4180 && TREE_CODE (type) == RECORD_TYPE
4181 && int_size_in_bytes (type) > 0)
4183 CUMULATIVE_ARGS valcum;
4187 valcum.fregno = FP_ARG_MIN_REG;
4188 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4189 /* Do a trial code generation as if this were going to be passed
4190 as an argument; if any part goes in memory, we return NULL. */
4191 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4194 /* Otherwise fall through to more conventional ABI rules. */
4197 if (AGGREGATE_TYPE_P (type)
4198 && (aix_struct_return
4199 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4202 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4203 modes only exist for GCC vector types if -maltivec. */
4204 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4205 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4208 /* Return synthetic vectors in memory. */
4209 if (TREE_CODE (type) == VECTOR_TYPE
4210 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4212 static bool warned_for_return_big_vectors = false;
4213 if (!warned_for_return_big_vectors)
4215 warning (0, "GCC vector returned by reference: "
4216 "non-standard ABI extension with no compatibility guarantee");
4217 warned_for_return_big_vectors = true;
4222 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4228 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4229 for a call to a function whose data type is FNTYPE.
4230 For a library call, FNTYPE is 0.
4232 For incoming args we set the number of arguments in the prototype large
4233 so we never return a PARALLEL. */
4236 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4237 rtx libname ATTRIBUTE_UNUSED, int incoming,
4238 int libcall, int n_named_args)
4240 static CUMULATIVE_ARGS zero_cumulative;
4242 *cum = zero_cumulative;
4244 cum->fregno = FP_ARG_MIN_REG;
4245 cum->vregno = ALTIVEC_ARG_MIN_REG;
4246 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4247 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4248 ? CALL_LIBCALL : CALL_NORMAL);
4249 cum->sysv_gregno = GP_ARG_MIN_REG;
4250 cum->stdarg = fntype
4251 && (TYPE_ARG_TYPES (fntype) != 0
4252 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4253 != void_type_node));
4255 cum->nargs_prototype = 0;
4256 if (incoming || cum->prototype)
4257 cum->nargs_prototype = n_named_args;
4259 /* Check for a longcall attribute. */
4260 if ((!fntype && rs6000_default_long_calls)
4262 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4263 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4264 cum->call_cookie |= CALL_LONG;
4266 if (TARGET_DEBUG_ARG)
4268 fprintf (stderr, "\ninit_cumulative_args:");
4271 tree ret_type = TREE_TYPE (fntype);
4272 fprintf (stderr, " ret code = %s,",
4273 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4276 if (cum->call_cookie & CALL_LONG)
4277 fprintf (stderr, " longcall,");
4279 fprintf (stderr, " proto = %d, nargs = %d\n",
4280 cum->prototype, cum->nargs_prototype);
4285 && TARGET_ALTIVEC_ABI
4286 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4288 error ("cannot return value in vector register because"
4289 " altivec instructions are disabled, use -maltivec"
4294 /* Return true if TYPE must be passed on the stack and not in registers. */
4297 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4299 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4300 return must_pass_in_stack_var_size (mode, type);
4302 return must_pass_in_stack_var_size_or_pad (mode, type);
4305 /* If defined, a C expression which determines whether, and in which
4306 direction, to pad out an argument with extra space. The value
4307 should be of type `enum direction': either `upward' to pad above
4308 the argument, `downward' to pad below, or `none' to inhibit
4311 For the AIX ABI structs are always stored left shifted in their
4315 function_arg_padding (enum machine_mode mode, tree type)
4317 #ifndef AGGREGATE_PADDING_FIXED
4318 #define AGGREGATE_PADDING_FIXED 0
4320 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4321 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4324 if (!AGGREGATE_PADDING_FIXED)
4326 /* GCC used to pass structures of the same size as integer types as
4327 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4328 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4329 passed padded downward, except that -mstrict-align further
4330 muddied the water in that multi-component structures of 2 and 4
4331 bytes in size were passed padded upward.
4333 The following arranges for best compatibility with previous
4334 versions of gcc, but removes the -mstrict-align dependency. */
4335 if (BYTES_BIG_ENDIAN)
4337 HOST_WIDE_INT size = 0;
4339 if (mode == BLKmode)
4341 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4342 size = int_size_in_bytes (type);
4345 size = GET_MODE_SIZE (mode);
4347 if (size == 1 || size == 2 || size == 4)
4353 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4355 if (type != 0 && AGGREGATE_TYPE_P (type))
4359 /* Fall back to the default. */
4360 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4363 /* If defined, a C expression that gives the alignment boundary, in bits,
4364 of an argument with the specified mode and type. If it is not defined,
4365 PARM_BOUNDARY is used for all arguments.
4367 V.4 wants long longs to be double word aligned.
4368 Doubleword align SPE vectors.
4369 Quadword align Altivec vectors.
4370 Quadword align large synthetic vector types. */
4373 function_arg_boundary (enum machine_mode mode, tree type)
4375 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4377 else if (SPE_VECTOR_MODE (mode)
4378 || (type && TREE_CODE (type) == VECTOR_TYPE
4379 && int_size_in_bytes (type) >= 8
4380 && int_size_in_bytes (type) < 16))
4382 else if (ALTIVEC_VECTOR_MODE (mode)
4383 || (type && TREE_CODE (type) == VECTOR_TYPE
4384 && int_size_in_bytes (type) >= 16))
4386 else if (rs6000_darwin64_abi && mode == BLKmode
4387 && type && TYPE_ALIGN (type) > 64)
4390 return PARM_BOUNDARY;
4393 /* For a function parm of MODE and TYPE, return the starting word in
4394 the parameter area. NWORDS of the parameter area are already used. */
4397 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4400 unsigned int parm_offset;
4402 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4403 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4404 return nwords + (-(parm_offset + nwords) & align);
4407 /* Compute the size (in words) of a function argument. */
4409 static unsigned long
4410 rs6000_arg_size (enum machine_mode mode, tree type)
4414 if (mode != BLKmode)
4415 size = GET_MODE_SIZE (mode);
4417 size = int_size_in_bytes (type);
4420 return (size + 3) >> 2;
4422 return (size + 7) >> 3;
4425 /* Use this to flush pending int fields. */
4428 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4429 HOST_WIDE_INT bitpos)
4431 unsigned int startbit, endbit;
4432 int intregs, intoffset;
4433 enum machine_mode mode;
4435 if (cum->intoffset == -1)
4438 intoffset = cum->intoffset;
4439 cum->intoffset = -1;
4441 if (intoffset % BITS_PER_WORD != 0)
4443 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4445 if (mode == BLKmode)
4447 /* We couldn't find an appropriate mode, which happens,
4448 e.g., in packed structs when there are 3 bytes to load.
4449 Back intoffset back to the beginning of the word in this
4451 intoffset = intoffset & -BITS_PER_WORD;
4455 startbit = intoffset & -BITS_PER_WORD;
4456 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4457 intregs = (endbit - startbit) / BITS_PER_WORD;
4458 cum->words += intregs;
4461 /* The darwin64 ABI calls for us to recurse down through structs,
4462 looking for elements passed in registers. Unfortunately, we have
4463 to track int register count here also because of misalignments
4464 in powerpc alignment mode. */
4467 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4469 HOST_WIDE_INT startbitpos)
4473 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4474 if (TREE_CODE (f) == FIELD_DECL)
4476 HOST_WIDE_INT bitpos = startbitpos;
4477 tree ftype = TREE_TYPE (f);
4478 enum machine_mode mode = TYPE_MODE (ftype);
4480 if (DECL_SIZE (f) != 0
4481 && host_integerp (bit_position (f), 1))
4482 bitpos += int_bit_position (f);
4484 /* ??? FIXME: else assume zero offset. */
4486 if (TREE_CODE (ftype) == RECORD_TYPE)
4487 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4488 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4490 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4491 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4492 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4494 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4496 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4500 else if (cum->intoffset == -1)
4501 cum->intoffset = bitpos;
4505 /* Update the data in CUM to advance over an argument
4506 of mode MODE and data type TYPE.
4507 (TYPE is null for libcalls where that information may not be available.)
4509 Note that for args passed by reference, function_arg will be called
4510 with MODE and TYPE set to that of the pointer to the arg, not the arg
4514 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4515 tree type, int named, int depth)
4519 /* Only tick off an argument if we're not recursing. */
4521 cum->nargs_prototype--;
4523 if (TARGET_ALTIVEC_ABI
4524 && (ALTIVEC_VECTOR_MODE (mode)
4525 || (type && TREE_CODE (type) == VECTOR_TYPE
4526 && int_size_in_bytes (type) == 16)))
4530 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4533 if (!TARGET_ALTIVEC)
4534 error ("cannot pass argument in vector register because"
4535 " altivec instructions are disabled, use -maltivec"
4538 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4539 even if it is going to be passed in a vector register.
4540 Darwin does the same for variable-argument functions. */
4541 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4542 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4552 /* Vector parameters must be 16-byte aligned. This places
4553 them at 2 mod 4 in terms of words in 32-bit mode, since
4554 the parameter save area starts at offset 24 from the
4555 stack. In 64-bit mode, they just have to start on an
4556 even word, since the parameter save area is 16-byte
4557 aligned. Space for GPRs is reserved even if the argument
4558 will be passed in memory. */
4560 align = (2 - cum->words) & 3;
4562 align = cum->words & 1;
4563 cum->words += align + rs6000_arg_size (mode, type);
4565 if (TARGET_DEBUG_ARG)
4567 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4569 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4570 cum->nargs_prototype, cum->prototype,
4571 GET_MODE_NAME (mode));
4575 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4577 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4580 else if (rs6000_darwin64_abi
4582 && TREE_CODE (type) == RECORD_TYPE
4583 && (size = int_size_in_bytes (type)) > 0)
4585 /* Variable sized types have size == -1 and are
4586 treated as if consisting entirely of ints.
4587 Pad to 16 byte boundary if needed. */
4588 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4589 && (cum->words % 2) != 0)
4591 /* For varargs, we can just go up by the size of the struct. */
4593 cum->words += (size + 7) / 8;
4596 /* It is tempting to say int register count just goes up by
4597 sizeof(type)/8, but this is wrong in a case such as
4598 { int; double; int; } [powerpc alignment]. We have to
4599 grovel through the fields for these too. */
4601 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4602 rs6000_darwin64_record_arg_advance_flush (cum,
4603 size * BITS_PER_UNIT);
4606 else if (DEFAULT_ABI == ABI_V4)
4608 if (TARGET_HARD_FLOAT && TARGET_FPRS
4609 && (mode == SFmode || mode == DFmode))
4611 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4616 cum->words += cum->words & 1;
4617 cum->words += rs6000_arg_size (mode, type);
4622 int n_words = rs6000_arg_size (mode, type);
4623 int gregno = cum->sysv_gregno;
4625 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4626 (r7,r8) or (r9,r10). As does any other 2 word item such
4627 as complex int due to a historical mistake. */
4629 gregno += (1 - gregno) & 1;
4631 /* Multi-reg args are not split between registers and stack. */
4632 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4634 /* Long long and SPE vectors are aligned on the stack.
4635 So are other 2 word items such as complex int due to
4636 a historical mistake. */
4638 cum->words += cum->words & 1;
4639 cum->words += n_words;
4642 /* Note: continuing to accumulate gregno past when we've started
4643 spilling to the stack indicates the fact that we've started
4644 spilling to the stack to expand_builtin_saveregs. */
4645 cum->sysv_gregno = gregno + n_words;
4648 if (TARGET_DEBUG_ARG)
4650 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4651 cum->words, cum->fregno);
4652 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4653 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4654 fprintf (stderr, "mode = %4s, named = %d\n",
4655 GET_MODE_NAME (mode), named);
4660 int n_words = rs6000_arg_size (mode, type);
4661 int start_words = cum->words;
4662 int align_words = rs6000_parm_start (mode, type, start_words);
4664 cum->words = align_words + n_words;
4666 if (SCALAR_FLOAT_MODE_P (mode)
4667 && TARGET_HARD_FLOAT && TARGET_FPRS)
4668 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4670 if (TARGET_DEBUG_ARG)
4672 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4673 cum->words, cum->fregno);
4674 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4675 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4676 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4677 named, align_words - start_words, depth);
4683 spe_build_register_parallel (enum machine_mode mode, int gregno)
4690 r1 = gen_rtx_REG (DImode, gregno);
4691 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4692 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4695 r1 = gen_rtx_REG (DImode, gregno);
4696 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4697 r3 = gen_rtx_REG (DImode, gregno + 2);
4698 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4699 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4706 /* Determine where to put a SIMD argument on the SPE. */
4708 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4711 int gregno = cum->sysv_gregno;
4713 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4714 are passed and returned in a pair of GPRs for ABI compatibility. */
4715 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4717 int n_words = rs6000_arg_size (mode, type);
4719 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4721 gregno += (1 - gregno) & 1;
4723 /* Multi-reg args are not split between registers and stack. */
4724 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4727 return spe_build_register_parallel (mode, gregno);
4731 int n_words = rs6000_arg_size (mode, type);
4733 /* SPE vectors are put in odd registers. */
4734 if (n_words == 2 && (gregno & 1) == 0)
4737 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4740 enum machine_mode m = SImode;
4742 r1 = gen_rtx_REG (m, gregno);
4743 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4744 r2 = gen_rtx_REG (m, gregno + 1);
4745 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4746 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4753 if (gregno <= GP_ARG_MAX_REG)
4754 return gen_rtx_REG (mode, gregno);
4760 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4761 structure between cum->intoffset and bitpos to integer registers. */
4764 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4765 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4767 enum machine_mode mode;
4769 unsigned int startbit, endbit;
4770 int this_regno, intregs, intoffset;
4773 if (cum->intoffset == -1)
4776 intoffset = cum->intoffset;
4777 cum->intoffset = -1;
4779 /* If this is the trailing part of a word, try to only load that
4780 much into the register. Otherwise load the whole register. Note
4781 that in the latter case we may pick up unwanted bits. It's not a
4782 problem at the moment but may wish to revisit. */
4784 if (intoffset % BITS_PER_WORD != 0)
4786 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4788 if (mode == BLKmode)
4790 /* We couldn't find an appropriate mode, which happens,
4791 e.g., in packed structs when there are 3 bytes to load.
4792 Back intoffset back to the beginning of the word in this
4794 intoffset = intoffset & -BITS_PER_WORD;
4801 startbit = intoffset & -BITS_PER_WORD;
4802 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4803 intregs = (endbit - startbit) / BITS_PER_WORD;
4804 this_regno = cum->words + intoffset / BITS_PER_WORD;
4806 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4809 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4813 intoffset /= BITS_PER_UNIT;
4816 regno = GP_ARG_MIN_REG + this_regno;
4817 reg = gen_rtx_REG (mode, regno);
4819 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4822 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4826 while (intregs > 0);
4829 /* Recursive workhorse for the following. */
4832 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4833 HOST_WIDE_INT startbitpos, rtx rvec[],
4838 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4839 if (TREE_CODE (f) == FIELD_DECL)
4841 HOST_WIDE_INT bitpos = startbitpos;
4842 tree ftype = TREE_TYPE (f);
4843 enum machine_mode mode = TYPE_MODE (ftype);
4845 if (DECL_SIZE (f) != 0
4846 && host_integerp (bit_position (f), 1))
4847 bitpos += int_bit_position (f);
4849 /* ??? FIXME: else assume zero offset. */
4851 if (TREE_CODE (ftype) == RECORD_TYPE)
4852 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4853 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4858 case SCmode: mode = SFmode; break;
4859 case DCmode: mode = DFmode; break;
4860 case TCmode: mode = TFmode; break;
4864 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4866 = gen_rtx_EXPR_LIST (VOIDmode,
4867 gen_rtx_REG (mode, cum->fregno++),
4868 GEN_INT (bitpos / BITS_PER_UNIT));
4872 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4874 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4876 = gen_rtx_EXPR_LIST (VOIDmode,
4877 gen_rtx_REG (mode, cum->vregno++),
4878 GEN_INT (bitpos / BITS_PER_UNIT));
4880 else if (cum->intoffset == -1)
4881 cum->intoffset = bitpos;
4885 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4886 the register(s) to be used for each field and subfield of a struct
4887 being passed by value, along with the offset of where the
4888 register's value may be found in the block. FP fields go in FP
4889 register, vector fields go in vector registers, and everything
4890 else goes in int registers, packed as in memory.
4892 This code is also used for function return values. RETVAL indicates
4893 whether this is the case.
4895 Much of this is taken from the SPARC V9 port, which has a similar
4896 calling convention. */
4899 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4900 int named, bool retval)
4902 rtx rvec[FIRST_PSEUDO_REGISTER];
4903 int k = 1, kbase = 1;
4904 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4905 /* This is a copy; modifications are not visible to our caller. */
4906 CUMULATIVE_ARGS copy_cum = *orig_cum;
4907 CUMULATIVE_ARGS *cum = ©_cum;
4909 /* Pad to 16 byte boundary if needed. */
4910 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4911 && (cum->words % 2) != 0)
4918 /* Put entries into rvec[] for individual FP and vector fields, and
4919 for the chunks of memory that go in int regs. Note we start at
4920 element 1; 0 is reserved for an indication of using memory, and
4921 may or may not be filled in below. */
4922 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4923 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4925 /* If any part of the struct went on the stack put all of it there.
4926 This hack is because the generic code for
4927 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4928 parts of the struct are not at the beginning. */
4932 return NULL_RTX; /* doesn't go in registers at all */
4934 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4936 if (k > 1 || cum->use_stack)
4937 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4942 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4945 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4949 rtx rvec[GP_ARG_NUM_REG + 1];
4951 if (align_words >= GP_ARG_NUM_REG)
4954 n_units = rs6000_arg_size (mode, type);
4956 /* Optimize the simple case where the arg fits in one gpr, except in
4957 the case of BLKmode due to assign_parms assuming that registers are
4958 BITS_PER_WORD wide. */
4960 || (n_units == 1 && mode != BLKmode))
4961 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4964 if (align_words + n_units > GP_ARG_NUM_REG)
4965 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4966 using a magic NULL_RTX component.
4967 FIXME: This is not strictly correct. Only some of the arg
4968 belongs in memory, not all of it. However, there isn't any way
4969 to do this currently, apart from building rtx descriptions for
4970 the pieces of memory we want stored. Due to bugs in the generic
4971 code we can't use the normal function_arg_partial_nregs scheme
4972 with the PARALLEL arg description we emit here.
4973 In any case, the code to store the whole arg to memory is often
4974 more efficient than code to store pieces, and we know that space
4975 is available in the right place for the whole arg. */
4976 /* FIXME: This should be fixed since the conversion to
4977 TARGET_ARG_PARTIAL_BYTES. */
4978 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4983 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4984 rtx off = GEN_INT (i++ * 4);
4985 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4987 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4989 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4992 /* Determine where to put an argument to a function.
4993 Value is zero to push the argument on the stack,
4994 or a hard register in which to store the argument.
4996 MODE is the argument's machine mode.
4997 TYPE is the data type of the argument (as a tree).
4998 This is null for libcalls where that information may
5000 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5001 the preceding args and about the function being called. It is
5002 not modified in this routine.
5003 NAMED is nonzero if this argument is a named parameter
5004 (otherwise it is an extra parameter matching an ellipsis).
5006 On RS/6000 the first eight words of non-FP are normally in registers
5007 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5008 Under V.4, the first 8 FP args are in registers.
5010 If this is floating-point and no prototype is specified, we use
5011 both an FP and integer register (or possibly FP reg and stack). Library
5012 functions (when CALL_LIBCALL is set) always have the proper types for args,
5013 so we can pass the FP value just in one register. emit_library_function
5014 doesn't support PARALLEL anyway.
5016 Note that for args passed by reference, function_arg will be called
5017 with MODE and TYPE set to that of the pointer to the arg, not the arg
5021 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5022 tree type, int named)
5024 enum rs6000_abi abi = DEFAULT_ABI;
5026 /* Return a marker to indicate whether CR1 needs to set or clear the
5027 bit that V.4 uses to say fp args were passed in registers.
5028 Assume that we don't need the marker for software floating point,
5029 or compiler generated library calls. */
5030 if (mode == VOIDmode)
5033 && (cum->call_cookie & CALL_LIBCALL) == 0
5035 || (cum->nargs_prototype < 0
5036 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5038 /* For the SPE, we need to crxor CR6 always. */
5040 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5041 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5042 return GEN_INT (cum->call_cookie
5043 | ((cum->fregno == FP_ARG_MIN_REG)
5044 ? CALL_V4_SET_FP_ARGS
5045 : CALL_V4_CLEAR_FP_ARGS));
5048 return GEN_INT (cum->call_cookie);
5051 if (rs6000_darwin64_abi && mode == BLKmode
5052 && TREE_CODE (type) == RECORD_TYPE)
5054 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5055 if (rslt != NULL_RTX)
5057 /* Else fall through to usual handling. */
5060 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5061 if (TARGET_64BIT && ! cum->prototype)
5063 /* Vector parameters get passed in vector register
5064 and also in GPRs or memory, in absence of prototype. */
5067 align_words = (cum->words + 1) & ~1;
5069 if (align_words >= GP_ARG_NUM_REG)
5075 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5077 return gen_rtx_PARALLEL (mode,
5079 gen_rtx_EXPR_LIST (VOIDmode,
5081 gen_rtx_EXPR_LIST (VOIDmode,
5082 gen_rtx_REG (mode, cum->vregno),
5086 return gen_rtx_REG (mode, cum->vregno);
5087 else if (TARGET_ALTIVEC_ABI
5088 && (ALTIVEC_VECTOR_MODE (mode)
5089 || (type && TREE_CODE (type) == VECTOR_TYPE
5090 && int_size_in_bytes (type) == 16)))
5092 if (named || abi == ABI_V4)
5096 /* Vector parameters to varargs functions under AIX or Darwin
5097 get passed in memory and possibly also in GPRs. */
5098 int align, align_words, n_words;
5099 enum machine_mode part_mode;
5101 /* Vector parameters must be 16-byte aligned. This places them at
5102 2 mod 4 in terms of words in 32-bit mode, since the parameter
5103 save area starts at offset 24 from the stack. In 64-bit mode,
5104 they just have to start on an even word, since the parameter
5105 save area is 16-byte aligned. */
5107 align = (2 - cum->words) & 3;
5109 align = cum->words & 1;
5110 align_words = cum->words + align;
5112 /* Out of registers? Memory, then. */
5113 if (align_words >= GP_ARG_NUM_REG)
5116 if (TARGET_32BIT && TARGET_POWERPC64)
5117 return rs6000_mixed_function_arg (mode, type, align_words);
5119 /* The vector value goes in GPRs. Only the part of the
5120 value in GPRs is reported here. */
5122 n_words = rs6000_arg_size (mode, type);
5123 if (align_words + n_words > GP_ARG_NUM_REG)
5124 /* Fortunately, there are only two possibilities, the value
5125 is either wholly in GPRs or half in GPRs and half not. */
5128 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5131 else if (TARGET_SPE_ABI && TARGET_SPE
5132 && (SPE_VECTOR_MODE (mode)
5133 || (TARGET_E500_DOUBLE && (mode == DFmode
5134 || mode == DCmode))))
5135 return rs6000_spe_function_arg (cum, mode, type);
5137 else if (abi == ABI_V4)
5139 if (TARGET_HARD_FLOAT && TARGET_FPRS
5140 && (mode == SFmode || mode == DFmode))
5142 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5143 return gen_rtx_REG (mode, cum->fregno);
5149 int n_words = rs6000_arg_size (mode, type);
5150 int gregno = cum->sysv_gregno;
5152 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5153 (r7,r8) or (r9,r10). As does any other 2 word item such
5154 as complex int due to a historical mistake. */
5156 gregno += (1 - gregno) & 1;
5158 /* Multi-reg args are not split between registers and stack. */
5159 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5162 if (TARGET_32BIT && TARGET_POWERPC64)
5163 return rs6000_mixed_function_arg (mode, type,
5164 gregno - GP_ARG_MIN_REG);
5165 return gen_rtx_REG (mode, gregno);
5170 int align_words = rs6000_parm_start (mode, type, cum->words);
5172 if (USE_FP_FOR_ARG_P (cum, mode, type))
5174 rtx rvec[GP_ARG_NUM_REG + 1];
5178 enum machine_mode fmode = mode;
5179 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5181 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5183 /* Currently, we only ever need one reg here because complex
5184 doubles are split. */
5185 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5187 /* Long double split over regs and memory. */
5191 /* Do we also need to pass this arg in the parameter save
5194 && (cum->nargs_prototype <= 0
5195 || (DEFAULT_ABI == ABI_AIX
5197 && align_words >= GP_ARG_NUM_REG)));
5199 if (!needs_psave && mode == fmode)
5200 return gen_rtx_REG (fmode, cum->fregno);
5205 /* Describe the part that goes in gprs or the stack.
5206 This piece must come first, before the fprs. */
5207 if (align_words < GP_ARG_NUM_REG)
5209 unsigned long n_words = rs6000_arg_size (mode, type);
5211 if (align_words + n_words > GP_ARG_NUM_REG
5212 || (TARGET_32BIT && TARGET_POWERPC64))
5214 /* If this is partially on the stack, then we only
5215 include the portion actually in registers here. */
5216 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5219 if (align_words + n_words > GP_ARG_NUM_REG
5220 && (TARGET_32BIT && TARGET_POWERPC64))
5221 /* Not all of the arg fits in gprs. Say that it
5222 goes in memory too, using a magic NULL_RTX
5223 component. Also see comment in
5224 rs6000_mixed_function_arg for why the normal
5225 function_arg_partial_nregs scheme doesn't work
5227 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5231 r = gen_rtx_REG (rmode,
5232 GP_ARG_MIN_REG + align_words);
5233 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5234 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5236 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5240 /* The whole arg fits in gprs. */
5241 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5242 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5246 /* It's entirely in memory. */
5247 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5250 /* Describe where this piece goes in the fprs. */
5251 r = gen_rtx_REG (fmode, cum->fregno);
5252 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5254 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5256 else if (align_words < GP_ARG_NUM_REG)
5258 if (TARGET_32BIT && TARGET_POWERPC64)
5259 return rs6000_mixed_function_arg (mode, type, align_words);
5261 if (mode == BLKmode)
5264 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5271 /* For an arg passed partly in registers and partly in memory, this is
5272 the number of bytes passed in registers. For args passed entirely in
5273 registers or entirely in memory, zero. When an arg is described by a
5274 PARALLEL, perhaps using more than one register type, this function
5275 returns the number of bytes used by the first element of the PARALLEL. */
5278 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5279 tree type, bool named)
5284 if (DEFAULT_ABI == ABI_V4)
5287 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5288 && cum->nargs_prototype >= 0)
5291 /* In this complicated case we just disable the partial_nregs code. */
5292 if (rs6000_darwin64_abi && mode == BLKmode
5293 && TREE_CODE (type) == RECORD_TYPE
5294 && int_size_in_bytes (type) > 0)
5297 align_words = rs6000_parm_start (mode, type, cum->words);
5299 if (USE_FP_FOR_ARG_P (cum, mode, type)
5300 /* If we are passing this arg in the fixed parameter save area
5301 (gprs or memory) as well as fprs, then this function should
5302 return the number of bytes passed in the parameter save area
5303 rather than bytes passed in fprs. */
5305 && (cum->nargs_prototype <= 0
5306 || (DEFAULT_ABI == ABI_AIX
5308 && align_words >= GP_ARG_NUM_REG))))
5310 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5311 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5312 else if (cum->nargs_prototype >= 0)
5316 if (align_words < GP_ARG_NUM_REG
5317 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5318 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5320 if (ret != 0 && TARGET_DEBUG_ARG)
5321 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5326 /* A C expression that indicates when an argument must be passed by
5327 reference. If nonzero for an argument, a copy of that argument is
5328 made in memory and a pointer to the argument is passed instead of
5329 the argument itself. The pointer is passed in whatever way is
5330 appropriate for passing a pointer to that type.
5332 Under V.4, aggregates and long double are passed by reference.
5334 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5335 reference unless the AltiVec vector extension ABI is in force.
5337 As an extension to all ABIs, variable sized types are passed by
5341 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5342 enum machine_mode mode, tree type,
5343 bool named ATTRIBUTE_UNUSED)
5345 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5347 if (TARGET_DEBUG_ARG)
5348 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5355 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5357 if (TARGET_DEBUG_ARG)
5358 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5362 if (int_size_in_bytes (type) < 0)
5364 if (TARGET_DEBUG_ARG)
5365 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5369 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5370 modes only exist for GCC vector types if -maltivec. */
5371 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5373 if (TARGET_DEBUG_ARG)
5374 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5378 /* Pass synthetic vectors in memory. */
5379 if (TREE_CODE (type) == VECTOR_TYPE
5380 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5382 static bool warned_for_pass_big_vectors = false;
5383 if (TARGET_DEBUG_ARG)
5384 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5385 if (!warned_for_pass_big_vectors)
5387 warning (0, "GCC vector passed by reference: "
5388 "non-standard ABI extension with no compatibility guarantee");
5389 warned_for_pass_big_vectors = true;
5398 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5401 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5406 for (i = 0; i < nregs; i++)
5408 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5409 if (reload_completed)
5411 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5414 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5415 i * GET_MODE_SIZE (reg_mode));
5418 tem = replace_equiv_address (tem, XEXP (tem, 0));
5422 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5426 /* Perform any needed actions needed for a function that is receiving a
5427 variable number of arguments.
5431 MODE and TYPE are the mode and type of the current parameter.
5433 PRETEND_SIZE is a variable that should be set to the amount of stack
5434 that must be pushed by the prolog to pretend that our caller pushed
5437 Normally, this macro will push all remaining incoming registers on the
5438 stack and set PRETEND_SIZE to the length of the registers pushed. */
5441 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5442 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5445 CUMULATIVE_ARGS next_cum;
5446 int reg_size = TARGET_32BIT ? 4 : 8;
5447 rtx save_area = NULL_RTX, mem;
5448 int first_reg_offset, set;
5450 /* Skip the last named argument. */
5452 function_arg_advance (&next_cum, mode, type, 1, 0);
5454 if (DEFAULT_ABI == ABI_V4)
5456 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5460 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5461 HOST_WIDE_INT offset = 0;
5463 /* Try to optimize the size of the varargs save area.
5464 The ABI requires that ap.reg_save_area is doubleword
5465 aligned, but we don't need to allocate space for all
5466 the bytes, only those to which we actually will save
5468 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5469 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5470 if (TARGET_HARD_FLOAT && TARGET_FPRS
5471 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5472 && cfun->va_list_fpr_size)
5475 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5476 * UNITS_PER_FP_WORD;
5477 if (cfun->va_list_fpr_size
5478 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5479 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5481 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5482 * UNITS_PER_FP_WORD;
5486 offset = -((first_reg_offset * reg_size) & ~7);
5487 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5489 gpr_reg_num = cfun->va_list_gpr_size;
5490 if (reg_size == 4 && (first_reg_offset & 1))
5493 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5496 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5498 - (int) (GP_ARG_NUM_REG * reg_size);
5500 if (gpr_size + fpr_size)
5503 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5504 gcc_assert (GET_CODE (reg_save_area) == MEM);
5505 reg_save_area = XEXP (reg_save_area, 0);
5506 if (GET_CODE (reg_save_area) == PLUS)
5508 gcc_assert (XEXP (reg_save_area, 0)
5509 == virtual_stack_vars_rtx);
5510 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5511 offset += INTVAL (XEXP (reg_save_area, 1));
5514 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5517 cfun->machine->varargs_save_offset = offset;
5518 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5523 first_reg_offset = next_cum.words;
5524 save_area = virtual_incoming_args_rtx;
5526 if (targetm.calls.must_pass_in_stack (mode, type))
5527 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5530 set = get_varargs_alias_set ();
5531 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5532 && cfun->va_list_gpr_size)
5534 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5536 if (va_list_gpr_counter_field)
5538 /* V4 va_list_gpr_size counts number of registers needed. */
5539 if (nregs > cfun->va_list_gpr_size)
5540 nregs = cfun->va_list_gpr_size;
5544 /* char * va_list instead counts number of bytes needed. */
5545 if (nregs > cfun->va_list_gpr_size / reg_size)
5546 nregs = cfun->va_list_gpr_size / reg_size;
5549 mem = gen_rtx_MEM (BLKmode,
5550 plus_constant (save_area,
5551 first_reg_offset * reg_size));
5552 MEM_NOTRAP_P (mem) = 1;
5553 set_mem_alias_set (mem, set);
5554 set_mem_align (mem, BITS_PER_WORD);
5556 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5560 /* Save FP registers if needed. */
5561 if (DEFAULT_ABI == ABI_V4
5562 && TARGET_HARD_FLOAT && TARGET_FPRS
5564 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5565 && cfun->va_list_fpr_size)
5567 int fregno = next_cum.fregno, nregs;
5568 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5569 rtx lab = gen_label_rtx ();
5570 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5571 * UNITS_PER_FP_WORD);
5574 (gen_rtx_SET (VOIDmode,
5576 gen_rtx_IF_THEN_ELSE (VOIDmode,
5577 gen_rtx_NE (VOIDmode, cr1,
5579 gen_rtx_LABEL_REF (VOIDmode, lab),
5583 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5584 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5586 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5587 MEM_NOTRAP_P (mem) = 1;
5588 set_mem_alias_set (mem, set);
5589 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5590 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5597 /* Create the va_list data type. */
5600 rs6000_build_builtin_va_list (void)
5602 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5604 /* For AIX, prefer 'char *' because that's what the system
5605 header files like. */
5606 if (DEFAULT_ABI != ABI_V4)
5607 return build_pointer_type (char_type_node);
5609 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5610 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5612 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5613 unsigned_char_type_node);
5614 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5615 unsigned_char_type_node);
5616 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5618 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5619 short_unsigned_type_node);
5620 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5622 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5625 va_list_gpr_counter_field = f_gpr;
5626 va_list_fpr_counter_field = f_fpr;
5628 DECL_FIELD_CONTEXT (f_gpr) = record;
5629 DECL_FIELD_CONTEXT (f_fpr) = record;
5630 DECL_FIELD_CONTEXT (f_res) = record;
5631 DECL_FIELD_CONTEXT (f_ovf) = record;
5632 DECL_FIELD_CONTEXT (f_sav) = record;
5634 TREE_CHAIN (record) = type_decl;
5635 TYPE_NAME (record) = type_decl;
5636 TYPE_FIELDS (record) = f_gpr;
5637 TREE_CHAIN (f_gpr) = f_fpr;
5638 TREE_CHAIN (f_fpr) = f_res;
5639 TREE_CHAIN (f_res) = f_ovf;
5640 TREE_CHAIN (f_ovf) = f_sav;
5642 layout_type (record);
5644 /* The correct type is an array type of one element. */
5645 return build_array_type (record, build_index_type (size_zero_node));
5648 /* Implement va_start. */
5651 rs6000_va_start (tree valist, rtx nextarg)
5653 HOST_WIDE_INT words, n_gpr, n_fpr;
5654 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5655 tree gpr, fpr, ovf, sav, t;
5657 /* Only SVR4 needs something special. */
5658 if (DEFAULT_ABI != ABI_V4)
5660 std_expand_builtin_va_start (valist, nextarg);
5664 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5665 f_fpr = TREE_CHAIN (f_gpr);
5666 f_res = TREE_CHAIN (f_fpr);
5667 f_ovf = TREE_CHAIN (f_res);
5668 f_sav = TREE_CHAIN (f_ovf);
5670 valist = build_va_arg_indirect_ref (valist);
5671 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5672 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5673 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5674 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5676 /* Count number of gp and fp argument registers used. */
5677 words = current_function_args_info.words;
5678 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5680 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5683 if (TARGET_DEBUG_ARG)
5684 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5685 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5686 words, n_gpr, n_fpr);
5688 if (cfun->va_list_gpr_size)
5690 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5691 build_int_cst (NULL_TREE, n_gpr));
5692 TREE_SIDE_EFFECTS (t) = 1;
5693 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5696 if (cfun->va_list_fpr_size)
5698 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5699 build_int_cst (NULL_TREE, n_fpr));
5700 TREE_SIDE_EFFECTS (t) = 1;
5701 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5704 /* Find the overflow area. */
5705 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5707 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
5708 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5709 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5710 TREE_SIDE_EFFECTS (t) = 1;
5711 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5713 /* If there were no va_arg invocations, don't set up the register
5715 if (!cfun->va_list_gpr_size
5716 && !cfun->va_list_fpr_size
5717 && n_gpr < GP_ARG_NUM_REG
5718 && n_fpr < FP_ARG_V4_MAX_REG)
5721 /* Find the register save area. */
5722 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5723 if (cfun->machine->varargs_save_offset)
5724 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
5725 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5726 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5727 TREE_SIDE_EFFECTS (t) = 1;
5728 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5731 /* Implement va_arg. */
5734 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5736 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5737 tree gpr, fpr, ovf, sav, reg, t, u;
5738 int size, rsize, n_reg, sav_ofs, sav_scale;
5739 tree lab_false, lab_over, addr;
5741 tree ptrtype = build_pointer_type (type);
5743 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5745 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5746 return build_va_arg_indirect_ref (t);
5749 if (DEFAULT_ABI != ABI_V4)
5751 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5753 tree elem_type = TREE_TYPE (type);
5754 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5755 int elem_size = GET_MODE_SIZE (elem_mode);
5757 if (elem_size < UNITS_PER_WORD)
5759 tree real_part, imag_part;
5760 tree post = NULL_TREE;
5762 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5764 /* Copy the value into a temporary, lest the formal temporary
5765 be reused out from under us. */
5766 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5767 append_to_statement_list (post, pre_p);
5769 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5772 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
5776 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5779 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5780 f_fpr = TREE_CHAIN (f_gpr);
5781 f_res = TREE_CHAIN (f_fpr);
5782 f_ovf = TREE_CHAIN (f_res);
5783 f_sav = TREE_CHAIN (f_ovf);
5785 valist = build_va_arg_indirect_ref (valist);
5786 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5787 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5788 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5789 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5791 size = int_size_in_bytes (type);
5792 rsize = (size + 3) / 4;
5795 if (TARGET_HARD_FLOAT && TARGET_FPRS
5796 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5798 /* FP args go in FP registers, if present. */
5803 if (TYPE_MODE (type) == DFmode)
5808 /* Otherwise into GP registers. */
5817 /* Pull the value out of the saved registers.... */
5820 addr = create_tmp_var (ptr_type_node, "addr");
5821 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5823 /* AltiVec vectors never go in registers when -mabi=altivec. */
5824 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5828 lab_false = create_artificial_label ();
5829 lab_over = create_artificial_label ();
5831 /* Long long and SPE vectors are aligned in the registers.
5832 As are any other 2 gpr item such as complex int due to a
5833 historical mistake. */
5837 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5838 size_int (n_reg - 1));
5839 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5842 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5843 t = build2 (GE_EXPR, boolean_type_node, u, t);
5844 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5845 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5846 gimplify_and_add (t, pre_p);
5850 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5852 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5853 u = build1 (CONVERT_EXPR, integer_type_node, u);
5854 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5855 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5857 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5858 gimplify_and_add (t, pre_p);
5860 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5861 gimplify_and_add (t, pre_p);
5863 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5864 append_to_statement_list (t, pre_p);
5868 /* Ensure that we don't find any more args in regs.
5869 Alignment has taken care of the n_reg == 2 case. */
5870 t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5871 gimplify_and_add (t, pre_p);
5875 /* ... otherwise out of the overflow area. */
5877 /* Care for on-stack alignment if needed. */
5881 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5882 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5883 build_int_cst (NULL_TREE, -align));
5885 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5887 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5888 gimplify_and_add (u, pre_p);
5890 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5891 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5892 gimplify_and_add (t, pre_p);
5896 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5897 append_to_statement_list (t, pre_p);
5900 addr = fold_convert (ptrtype, addr);
5901 return build_va_arg_indirect_ref (addr);
5907 def_builtin (int mask, const char *name, tree type, int code)
5909 if (mask & target_flags)
5911 if (rs6000_builtin_decls[code])
5914 rs6000_builtin_decls[code] =
5915 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
5920 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5922 static const struct builtin_description bdesc_3arg[] =
5924 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5925 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5926 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5927 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5928 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5929 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5930 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5931 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5932 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5933 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5934 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5935 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5936 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5937 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5938 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5939 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5940 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5941 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5942 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5943 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5944 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5945 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5946 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5948 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
5949 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
5950 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
5951 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
5952 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
5953 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
5954 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
5955 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
5956 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
5957 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
5958 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
5959 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
5960 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
5961 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
5962 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
5965 /* DST operations: void foo (void *, const int, const char). */
5967 static const struct builtin_description bdesc_dst[] =
5969 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5970 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5971 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5972 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
5974 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
5975 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
5976 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
5977 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
5980 /* Simple binary operations: VECc = foo (VECa, VECb). */
5982 static struct builtin_description bdesc_2arg[] =
5984 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5985 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5986 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5987 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5988 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5989 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5990 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5991 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5992 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5993 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5994 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5995 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5996 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5997 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5998 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5999 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6000 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6001 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6002 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6003 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6004 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6005 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6006 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6007 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6008 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6009 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6010 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6011 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6012 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6013 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6014 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6015 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6016 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6017 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6018 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6019 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6020 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6021 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6022 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6023 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6024 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6025 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6026 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6027 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6028 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6029 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6030 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6031 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6032 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6033 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6034 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6035 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6036 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6037 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6038 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6039 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6040 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6041 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6042 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6043 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6044 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6045 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6046 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6047 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6048 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6049 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6050 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6051 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6052 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6053 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6054 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6055 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6056 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6057 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6058 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6059 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6060 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6061 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6062 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6063 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6064 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6065 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6066 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6067 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6068 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6069 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6070 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6071 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6072 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6073 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6074 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6075 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6076 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6077 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6078 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6079 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6080 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6081 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6082 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6083 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6084 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6085 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6086 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6087 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6088 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6089 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6090 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6091 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6092 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6093 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6094 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6096 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6097 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6098 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6099 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6100 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6101 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6102 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6103 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6104 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6105 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6106 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6107 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6108 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6109 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6110 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6111 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6112 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6113 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6114 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6115 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6116 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6117 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6118 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6119 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6120 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6121 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6122 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6123 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6124 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6125 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6126 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6127 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6128 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6129 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6130 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6131 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6132 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6133 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6134 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6135 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6136 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6137 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6138 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6139 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6140 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6141 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6142 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6143 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6144 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6145 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6146 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6147 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6148 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6149 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6150 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6151 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6152 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6153 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6154 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6155 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6156 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6157 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6158 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6159 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6160 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6161 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6162 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6163 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6164 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6165 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6166 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6167 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6168 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6169 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6170 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6171 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6172 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6173 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6174 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6175 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6176 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6177 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6178 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6179 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6180 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6181 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6182 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6183 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6184 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6185 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6186 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6187 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6188 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6189 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6190 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6191 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6192 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6196 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6197 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6217 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6218 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6219 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6220 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6221 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6222 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6224 /* Place holder, leave as first spe builtin. */
6225 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6226 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6227 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6228 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6229 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6230 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6231 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6232 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6233 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6234 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6235 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6236 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6237 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6238 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6239 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6240 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6241 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6242 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6243 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6244 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6245 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6246 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6247 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6248 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6249 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6250 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6251 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6252 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6253 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6254 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6255 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6256 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6257 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6258 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6259 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6260 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6261 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6262 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6263 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6264 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6265 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6266 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6267 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6268 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6269 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6270 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6271 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6272 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6273 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6274 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6275 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6276 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6277 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6278 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6279 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6280 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6281 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6282 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6283 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6284 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6285 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6286 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6287 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6288 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6289 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6290 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6291 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6292 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6293 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6294 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6295 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6296 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6297 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6298 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6299 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6300 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6301 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6302 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6303 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6304 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6305 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6306 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6307 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6308 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6309 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6310 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6311 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6312 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6313 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6314 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6315 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6316 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6317 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6318 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6319 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6320 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6321 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6322 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6323 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6324 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6325 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6326 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6327 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6328 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6329 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6330 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6331 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6332 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6333 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6335 /* SPE binary operations expecting a 5-bit unsigned literal. */
6336 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6338 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6339 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6340 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6341 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6342 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6343 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6344 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6345 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6346 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6347 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6348 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6349 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6350 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6351 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6352 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6353 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6354 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6355 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6356 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6357 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6358 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6359 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6360 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6361 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6362 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6363 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6365 /* Place-holder. Leave as last binary SPE builtin. */
6366 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6369 /* AltiVec predicates. */
6371 struct builtin_description_predicates
6373 const unsigned int mask;
6374 const enum insn_code icode;
6376 const char *const name;
6377 const enum rs6000_builtins code;
6380 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6382 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6383 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6384 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6385 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6386 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6387 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6388 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6389 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6390 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6391 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6392 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6393 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6394 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6396 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6397 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6398 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6401 /* SPE predicates. */
6402 static struct builtin_description bdesc_spe_predicates[] =
6404 /* Place-holder. Leave as first. */
6405 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6406 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6407 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6408 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6409 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6410 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6411 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6412 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6413 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6414 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6415 /* Place-holder. Leave as last. */
6416 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6419 /* SPE evsel predicates. */
6420 static struct builtin_description bdesc_spe_evsel[] =
6422 /* Place-holder. Leave as first. */
6423 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6424 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6425 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6426 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6427 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6428 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6429 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6430 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6431 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6432 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6433 /* Place-holder. Leave as last. */
6434 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6437 /* ABS* operations. */
6439 static const struct builtin_description bdesc_abs[] =
6441 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6442 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6443 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6444 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6445 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6446 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6447 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6450 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6453 static struct builtin_description bdesc_1arg[] =
6455 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6456 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6457 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6458 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6459 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6460 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6461 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6462 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6463 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6464 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6465 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6466 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6467 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6468 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6469 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6470 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6471 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6473 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6474 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6475 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6476 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6477 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6478 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6479 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6480 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6481 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6482 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6483 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6484 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6485 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6486 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6487 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6488 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6489 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6490 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6491 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6493 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6494 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6495 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6496 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6497 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6498 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6499 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6500 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6501 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6502 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6503 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6504 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6505 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6506 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6507 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6508 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6509 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6510 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6511 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6512 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6513 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6514 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6515 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6516 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6517 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6518 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6519 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6520 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6521 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6522 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6524 /* Place-holder. Leave as last unary SPE builtin. */
6525 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6529 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6532 tree arg0 = TREE_VALUE (arglist);
6533 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6534 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6535 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6537 if (icode == CODE_FOR_nothing)
6538 /* Builtin not supported on this processor. */
6541 /* If we got invalid arguments bail out before generating bad rtl. */
6542 if (arg0 == error_mark_node)
6545 if (icode == CODE_FOR_altivec_vspltisb
6546 || icode == CODE_FOR_altivec_vspltish
6547 || icode == CODE_FOR_altivec_vspltisw
6548 || icode == CODE_FOR_spe_evsplatfi
6549 || icode == CODE_FOR_spe_evsplati)
6551 /* Only allow 5-bit *signed* literals. */
6552 if (GET_CODE (op0) != CONST_INT
6553 || INTVAL (op0) > 15
6554 || INTVAL (op0) < -16)
6556 error ("argument 1 must be a 5-bit signed literal");
6562 || GET_MODE (target) != tmode
6563 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6564 target = gen_reg_rtx (tmode);
6566 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6567 op0 = copy_to_mode_reg (mode0, op0);
6569 pat = GEN_FCN (icode) (target, op0);
6578 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6580 rtx pat, scratch1, scratch2;
6581 tree arg0 = TREE_VALUE (arglist);
6582 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6583 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6584 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6586 /* If we have invalid arguments, bail out before generating bad rtl. */
6587 if (arg0 == error_mark_node)
6591 || GET_MODE (target) != tmode
6592 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6593 target = gen_reg_rtx (tmode);
6595 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6596 op0 = copy_to_mode_reg (mode0, op0);
6598 scratch1 = gen_reg_rtx (mode0);
6599 scratch2 = gen_reg_rtx (mode0);
6601 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6610 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6613 tree arg0 = TREE_VALUE (arglist);
6614 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6615 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6616 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6617 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6618 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6619 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6621 if (icode == CODE_FOR_nothing)
6622 /* Builtin not supported on this processor. */
6625 /* If we got invalid arguments bail out before generating bad rtl. */
6626 if (arg0 == error_mark_node || arg1 == error_mark_node)
6629 if (icode == CODE_FOR_altivec_vcfux
6630 || icode == CODE_FOR_altivec_vcfsx
6631 || icode == CODE_FOR_altivec_vctsxs
6632 || icode == CODE_FOR_altivec_vctuxs
6633 || icode == CODE_FOR_altivec_vspltb
6634 || icode == CODE_FOR_altivec_vsplth
6635 || icode == CODE_FOR_altivec_vspltw
6636 || icode == CODE_FOR_spe_evaddiw
6637 || icode == CODE_FOR_spe_evldd
6638 || icode == CODE_FOR_spe_evldh
6639 || icode == CODE_FOR_spe_evldw
6640 || icode == CODE_FOR_spe_evlhhesplat
6641 || icode == CODE_FOR_spe_evlhhossplat
6642 || icode == CODE_FOR_spe_evlhhousplat
6643 || icode == CODE_FOR_spe_evlwhe
6644 || icode == CODE_FOR_spe_evlwhos
6645 || icode == CODE_FOR_spe_evlwhou
6646 || icode == CODE_FOR_spe_evlwhsplat
6647 || icode == CODE_FOR_spe_evlwwsplat
6648 || icode == CODE_FOR_spe_evrlwi
6649 || icode == CODE_FOR_spe_evslwi
6650 || icode == CODE_FOR_spe_evsrwis
6651 || icode == CODE_FOR_spe_evsubifw
6652 || icode == CODE_FOR_spe_evsrwiu)
6654 /* Only allow 5-bit unsigned literals. */
6656 if (TREE_CODE (arg1) != INTEGER_CST
6657 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6659 error ("argument 2 must be a 5-bit unsigned literal");
6665 || GET_MODE (target) != tmode
6666 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6667 target = gen_reg_rtx (tmode);
6669 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6670 op0 = copy_to_mode_reg (mode0, op0);
6671 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6672 op1 = copy_to_mode_reg (mode1, op1);
6674 pat = GEN_FCN (icode) (target, op0, op1);
6683 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6684 tree arglist, rtx target)
6687 tree cr6_form = TREE_VALUE (arglist);
6688 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6689 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6690 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6691 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6692 enum machine_mode tmode = SImode;
6693 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6694 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6697 if (TREE_CODE (cr6_form) != INTEGER_CST)
6699 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6703 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6705 gcc_assert (mode0 == mode1);
6707 /* If we have invalid arguments, bail out before generating bad rtl. */
6708 if (arg0 == error_mark_node || arg1 == error_mark_node)
6712 || GET_MODE (target) != tmode
6713 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6714 target = gen_reg_rtx (tmode);
6716 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6717 op0 = copy_to_mode_reg (mode0, op0);
6718 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6719 op1 = copy_to_mode_reg (mode1, op1);
6721 scratch = gen_reg_rtx (mode0);
6723 pat = GEN_FCN (icode) (scratch, op0, op1,
6724 gen_rtx_SYMBOL_REF (Pmode, opcode));
6729 /* The vec_any* and vec_all* predicates use the same opcodes for two
6730 different operations, but the bits in CR6 will be different
6731 depending on what information we want. So we have to play tricks
6732 with CR6 to get the right bits out.
6734 If you think this is disgusting, look at the specs for the
6735 AltiVec predicates. */
6737 switch (cr6_form_int)
6740 emit_insn (gen_cr6_test_for_zero (target));
6743 emit_insn (gen_cr6_test_for_zero_reverse (target));
6746 emit_insn (gen_cr6_test_for_lt (target));
6749 emit_insn (gen_cr6_test_for_lt_reverse (target));
6752 error ("argument 1 of __builtin_altivec_predicate is out of range");
6760 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6763 tree arg0 = TREE_VALUE (arglist);
6764 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6765 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6766 enum machine_mode mode0 = Pmode;
6767 enum machine_mode mode1 = Pmode;
6768 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6769 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6771 if (icode == CODE_FOR_nothing)
6772 /* Builtin not supported on this processor. */
6775 /* If we got invalid arguments bail out before generating bad rtl. */
6776 if (arg0 == error_mark_node || arg1 == error_mark_node)
6780 || GET_MODE (target) != tmode
6781 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6782 target = gen_reg_rtx (tmode);
6784 op1 = copy_to_mode_reg (mode1, op1);
6786 if (op0 == const0_rtx)
6788 addr = gen_rtx_MEM (tmode, op1);
6792 op0 = copy_to_mode_reg (mode0, op0);
6793 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6796 pat = GEN_FCN (icode) (target, addr);
6806 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6808 tree arg0 = TREE_VALUE (arglist);
6809 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6810 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6811 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6812 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6813 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6815 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6816 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6817 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6819 /* Invalid arguments. Bail before doing anything stoopid! */
6820 if (arg0 == error_mark_node
6821 || arg1 == error_mark_node
6822 || arg2 == error_mark_node)
6825 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6826 op0 = copy_to_mode_reg (mode2, op0);
6827 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6828 op1 = copy_to_mode_reg (mode0, op1);
6829 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6830 op2 = copy_to_mode_reg (mode1, op2);
6832 pat = GEN_FCN (icode) (op1, op2, op0);
6839 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6841 tree arg0 = TREE_VALUE (arglist);
6842 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6843 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6844 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6845 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6846 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6848 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6849 enum machine_mode mode1 = Pmode;
6850 enum machine_mode mode2 = Pmode;
6852 /* Invalid arguments. Bail before doing anything stoopid! */
6853 if (arg0 == error_mark_node
6854 || arg1 == error_mark_node
6855 || arg2 == error_mark_node)
6858 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6859 op0 = copy_to_mode_reg (tmode, op0);
6861 op2 = copy_to_mode_reg (mode2, op2);
6863 if (op1 == const0_rtx)
6865 addr = gen_rtx_MEM (tmode, op2);
6869 op1 = copy_to_mode_reg (mode1, op1);
6870 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6873 pat = GEN_FCN (icode) (addr, op0);
6880 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6883 tree arg0 = TREE_VALUE (arglist);
6884 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6885 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6886 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6887 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6888 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6889 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6890 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6891 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6892 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6894 if (icode == CODE_FOR_nothing)
6895 /* Builtin not supported on this processor. */
6898 /* If we got invalid arguments bail out before generating bad rtl. */
6899 if (arg0 == error_mark_node
6900 || arg1 == error_mark_node
6901 || arg2 == error_mark_node)
6904 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6905 || icode == CODE_FOR_altivec_vsldoi_v4si
6906 || icode == CODE_FOR_altivec_vsldoi_v8hi
6907 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6909 /* Only allow 4-bit unsigned literals. */
6911 if (TREE_CODE (arg2) != INTEGER_CST
6912 || TREE_INT_CST_LOW (arg2) & ~0xf)
6914 error ("argument 3 must be a 4-bit unsigned literal");
6920 || GET_MODE (target) != tmode
6921 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6922 target = gen_reg_rtx (tmode);
6924 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6925 op0 = copy_to_mode_reg (mode0, op0);
6926 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6927 op1 = copy_to_mode_reg (mode1, op1);
6928 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6929 op2 = copy_to_mode_reg (mode2, op2);
6931 pat = GEN_FCN (icode) (target, op0, op1, op2);
6939 /* Expand the lvx builtins. */
6941 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6943 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6944 tree arglist = TREE_OPERAND (exp, 1);
6945 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6947 enum machine_mode tmode, mode0;
6949 enum insn_code icode;
6953 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6954 icode = CODE_FOR_altivec_lvx_v16qi;
6956 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6957 icode = CODE_FOR_altivec_lvx_v8hi;
6959 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6960 icode = CODE_FOR_altivec_lvx_v4si;
6962 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6963 icode = CODE_FOR_altivec_lvx_v4sf;
6972 arg0 = TREE_VALUE (arglist);
6973 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6974 tmode = insn_data[icode].operand[0].mode;
6975 mode0 = insn_data[icode].operand[1].mode;
6978 || GET_MODE (target) != tmode
6979 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6980 target = gen_reg_rtx (tmode);
6982 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6983 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6985 pat = GEN_FCN (icode) (target, op0);
6992 /* Expand the stvx builtins. */
6994 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6997 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6998 tree arglist = TREE_OPERAND (exp, 1);
6999 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7001 enum machine_mode mode0, mode1;
7003 enum insn_code icode;
7007 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7008 icode = CODE_FOR_altivec_stvx_v16qi;
7010 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7011 icode = CODE_FOR_altivec_stvx_v8hi;
7013 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7014 icode = CODE_FOR_altivec_stvx_v4si;
7016 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7017 icode = CODE_FOR_altivec_stvx_v4sf;
7024 arg0 = TREE_VALUE (arglist);
7025 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7026 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7027 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7028 mode0 = insn_data[icode].operand[0].mode;
7029 mode1 = insn_data[icode].operand[1].mode;
7031 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7032 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7033 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7034 op1 = copy_to_mode_reg (mode1, op1);
7036 pat = GEN_FCN (icode) (op0, op1);
7044 /* Expand the dst builtins. */
7046 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7049 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7050 tree arglist = TREE_OPERAND (exp, 1);
7051 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7052 tree arg0, arg1, arg2;
7053 enum machine_mode mode0, mode1, mode2;
7054 rtx pat, op0, op1, op2;
7055 struct builtin_description *d;
7060 /* Handle DST variants. */
7061 d = (struct builtin_description *) bdesc_dst;
7062 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7063 if (d->code == fcode)
7065 arg0 = TREE_VALUE (arglist);
7066 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7067 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7068 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7069 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7070 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7071 mode0 = insn_data[d->icode].operand[0].mode;
7072 mode1 = insn_data[d->icode].operand[1].mode;
7073 mode2 = insn_data[d->icode].operand[2].mode;
7075 /* Invalid arguments, bail out before generating bad rtl. */
7076 if (arg0 == error_mark_node
7077 || arg1 == error_mark_node
7078 || arg2 == error_mark_node)
7083 if (TREE_CODE (arg2) != INTEGER_CST
7084 || TREE_INT_CST_LOW (arg2) & ~0x3)
7086 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7090 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7091 op0 = copy_to_mode_reg (Pmode, op0);
7092 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7093 op1 = copy_to_mode_reg (mode1, op1);
7095 pat = GEN_FCN (d->icode) (op0, op1, op2);
7105 /* Expand vec_init builtin. */
7107 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7109 enum machine_mode tmode = TYPE_MODE (type);
7110 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7111 int i, n_elt = GET_MODE_NUNITS (tmode);
7112 rtvec v = rtvec_alloc (n_elt);
7114 gcc_assert (VECTOR_MODE_P (tmode));
7116 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7118 rtx x = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0);
7119 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7122 gcc_assert (arglist == NULL);
7124 if (!target || !register_operand (target, tmode))
7125 target = gen_reg_rtx (tmode);
7127 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7131 /* Return the integer constant in ARG. Constrain it to be in the range
7132 of the subparts of VEC_TYPE; issue an error if not. */
7135 get_element_number (tree vec_type, tree arg)
7137 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7139 if (!host_integerp (arg, 1)
7140 || (elt = tree_low_cst (arg, 1), elt > max))
7142 error ("selector must be an integer constant in the range 0..%wi", max);
7149 /* Expand vec_set builtin. */
7151 altivec_expand_vec_set_builtin (tree arglist)
7153 enum machine_mode tmode, mode1;
7154 tree arg0, arg1, arg2;
7158 arg0 = TREE_VALUE (arglist);
7159 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7160 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7162 tmode = TYPE_MODE (TREE_TYPE (arg0));
7163 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7164 gcc_assert (VECTOR_MODE_P (tmode));
7166 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7167 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7168 elt = get_element_number (TREE_TYPE (arg0), arg2);
7170 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7171 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7173 op0 = force_reg (tmode, op0);
7174 op1 = force_reg (mode1, op1);
7176 rs6000_expand_vector_set (op0, op1, elt);
7181 /* Expand vec_ext builtin. */
7183 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7185 enum machine_mode tmode, mode0;
7190 arg0 = TREE_VALUE (arglist);
7191 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7193 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7194 elt = get_element_number (TREE_TYPE (arg0), arg1);
7196 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7197 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7198 gcc_assert (VECTOR_MODE_P (mode0));
7200 op0 = force_reg (mode0, op0);
7202 if (optimize || !target || !register_operand (target, tmode))
7203 target = gen_reg_rtx (tmode);
7205 rs6000_expand_vector_extract (target, op0, elt);
7210 /* Expand the builtin in EXP and store the result in TARGET. Store
7211 true in *EXPANDEDP if we found a builtin to expand. */
7213 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7215 struct builtin_description *d;
7216 struct builtin_description_predicates *dp;
7218 enum insn_code icode;
7219 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7220 tree arglist = TREE_OPERAND (exp, 1);
7223 enum machine_mode tmode, mode0;
7224 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7226 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7227 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7230 error ("unresolved overload for Altivec builtin %qF", fndecl);
7234 target = altivec_expand_ld_builtin (exp, target, expandedp);
7238 target = altivec_expand_st_builtin (exp, target, expandedp);
7242 target = altivec_expand_dst_builtin (exp, target, expandedp);
7250 case ALTIVEC_BUILTIN_STVX:
7251 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7252 case ALTIVEC_BUILTIN_STVEBX:
7253 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7254 case ALTIVEC_BUILTIN_STVEHX:
7255 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7256 case ALTIVEC_BUILTIN_STVEWX:
7257 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7258 case ALTIVEC_BUILTIN_STVXL:
7259 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7261 case ALTIVEC_BUILTIN_MFVSCR:
7262 icode = CODE_FOR_altivec_mfvscr;
7263 tmode = insn_data[icode].operand[0].mode;
7266 || GET_MODE (target) != tmode
7267 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7268 target = gen_reg_rtx (tmode);
7270 pat = GEN_FCN (icode) (target);
7276 case ALTIVEC_BUILTIN_MTVSCR:
7277 icode = CODE_FOR_altivec_mtvscr;
7278 arg0 = TREE_VALUE (arglist);
7279 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7280 mode0 = insn_data[icode].operand[0].mode;
7282 /* If we got invalid arguments bail out before generating bad rtl. */
7283 if (arg0 == error_mark_node)
7286 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7287 op0 = copy_to_mode_reg (mode0, op0);
7289 pat = GEN_FCN (icode) (op0);
7294 case ALTIVEC_BUILTIN_DSSALL:
7295 emit_insn (gen_altivec_dssall ());
7298 case ALTIVEC_BUILTIN_DSS:
7299 icode = CODE_FOR_altivec_dss;
7300 arg0 = TREE_VALUE (arglist);
7302 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7303 mode0 = insn_data[icode].operand[0].mode;
7305 /* If we got invalid arguments bail out before generating bad rtl. */
7306 if (arg0 == error_mark_node)
7309 if (TREE_CODE (arg0) != INTEGER_CST
7310 || TREE_INT_CST_LOW (arg0) & ~0x3)
7312 error ("argument to dss must be a 2-bit unsigned literal");
7316 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7317 op0 = copy_to_mode_reg (mode0, op0);
7319 emit_insn (gen_altivec_dss (op0));
7322 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7323 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7324 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7325 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7326 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7328 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7329 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7330 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7331 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7332 return altivec_expand_vec_set_builtin (arglist);
7334 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7335 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7336 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7337 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7338 return altivec_expand_vec_ext_builtin (arglist, target);
7345 /* Expand abs* operations. */
7346 d = (struct builtin_description *) bdesc_abs;
7347 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7348 if (d->code == fcode)
7349 return altivec_expand_abs_builtin (d->icode, arglist, target);
7351 /* Expand the AltiVec predicates. */
7352 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7353 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7354 if (dp->code == fcode)
7355 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7358 /* LV* are funky. We initialized them differently. */
7361 case ALTIVEC_BUILTIN_LVSL:
7362 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7364 case ALTIVEC_BUILTIN_LVSR:
7365 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7367 case ALTIVEC_BUILTIN_LVEBX:
7368 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7370 case ALTIVEC_BUILTIN_LVEHX:
7371 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7373 case ALTIVEC_BUILTIN_LVEWX:
7374 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7376 case ALTIVEC_BUILTIN_LVXL:
7377 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7379 case ALTIVEC_BUILTIN_LVX:
7380 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7391 /* Binops that need to be initialized manually, but can be expanded
7392 automagically by rs6000_expand_binop_builtin. */
7393 static struct builtin_description bdesc_2arg_spe[] =
7395 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7396 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7397 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7398 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7399 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7400 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7401 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7402 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7403 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7404 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7405 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7406 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7407 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7408 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7409 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7410 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7411 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7412 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7413 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7414 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7415 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7416 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7419 /* Expand the builtin in EXP and store the result in TARGET. Store
7420 true in *EXPANDEDP if we found a builtin to expand.
7422 This expands the SPE builtins that are not simple unary and binary
7425 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7427 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7428 tree arglist = TREE_OPERAND (exp, 1);
7430 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7431 enum insn_code icode;
7432 enum machine_mode tmode, mode0;
7434 struct builtin_description *d;
7439 /* Syntax check for a 5-bit unsigned immediate. */
7442 case SPE_BUILTIN_EVSTDD:
7443 case SPE_BUILTIN_EVSTDH:
7444 case SPE_BUILTIN_EVSTDW:
7445 case SPE_BUILTIN_EVSTWHE:
7446 case SPE_BUILTIN_EVSTWHO:
7447 case SPE_BUILTIN_EVSTWWE:
7448 case SPE_BUILTIN_EVSTWWO:
7449 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7450 if (TREE_CODE (arg1) != INTEGER_CST
7451 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7453 error ("argument 2 must be a 5-bit unsigned literal");
7461 /* The evsplat*i instructions are not quite generic. */
7464 case SPE_BUILTIN_EVSPLATFI:
7465 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7467 case SPE_BUILTIN_EVSPLATI:
7468 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7474 d = (struct builtin_description *) bdesc_2arg_spe;
7475 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7476 if (d->code == fcode)
7477 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7479 d = (struct builtin_description *) bdesc_spe_predicates;
7480 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7481 if (d->code == fcode)
7482 return spe_expand_predicate_builtin (d->icode, arglist, target);
7484 d = (struct builtin_description *) bdesc_spe_evsel;
7485 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7486 if (d->code == fcode)
7487 return spe_expand_evsel_builtin (d->icode, arglist, target);
7491 case SPE_BUILTIN_EVSTDDX:
7492 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7493 case SPE_BUILTIN_EVSTDHX:
7494 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7495 case SPE_BUILTIN_EVSTDWX:
7496 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7497 case SPE_BUILTIN_EVSTWHEX:
7498 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7499 case SPE_BUILTIN_EVSTWHOX:
7500 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7501 case SPE_BUILTIN_EVSTWWEX:
7502 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7503 case SPE_BUILTIN_EVSTWWOX:
7504 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7505 case SPE_BUILTIN_EVSTDD:
7506 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7507 case SPE_BUILTIN_EVSTDH:
7508 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7509 case SPE_BUILTIN_EVSTDW:
7510 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7511 case SPE_BUILTIN_EVSTWHE:
7512 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7513 case SPE_BUILTIN_EVSTWHO:
7514 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7515 case SPE_BUILTIN_EVSTWWE:
7516 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7517 case SPE_BUILTIN_EVSTWWO:
7518 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7519 case SPE_BUILTIN_MFSPEFSCR:
7520 icode = CODE_FOR_spe_mfspefscr;
7521 tmode = insn_data[icode].operand[0].mode;
7524 || GET_MODE (target) != tmode
7525 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7526 target = gen_reg_rtx (tmode);
7528 pat = GEN_FCN (icode) (target);
7533 case SPE_BUILTIN_MTSPEFSCR:
7534 icode = CODE_FOR_spe_mtspefscr;
7535 arg0 = TREE_VALUE (arglist);
7536 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7537 mode0 = insn_data[icode].operand[0].mode;
7539 if (arg0 == error_mark_node)
7542 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7543 op0 = copy_to_mode_reg (mode0, op0);
7545 pat = GEN_FCN (icode) (op0);
7558 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7560 rtx pat, scratch, tmp;
7561 tree form = TREE_VALUE (arglist);
7562 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7563 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7564 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7565 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7566 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7567 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7571 if (TREE_CODE (form) != INTEGER_CST)
7573 error ("argument 1 of __builtin_spe_predicate must be a constant");
7577 form_int = TREE_INT_CST_LOW (form);
7579 gcc_assert (mode0 == mode1);
7581 if (arg0 == error_mark_node || arg1 == error_mark_node)
7585 || GET_MODE (target) != SImode
7586 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7587 target = gen_reg_rtx (SImode);
7589 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7590 op0 = copy_to_mode_reg (mode0, op0);
7591 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7592 op1 = copy_to_mode_reg (mode1, op1);
7594 scratch = gen_reg_rtx (CCmode);
7596 pat = GEN_FCN (icode) (scratch, op0, op1);
7601 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7602 _lower_. We use one compare, but look in different bits of the
7603 CR for each variant.
7605 There are 2 elements in each SPE simd type (upper/lower). The CR
7606 bits are set as follows:
7608 BIT0 | BIT 1 | BIT 2 | BIT 3
7609 U | L | (U | L) | (U & L)
7611 So, for an "all" relationship, BIT 3 would be set.
7612 For an "any" relationship, BIT 2 would be set. Etc.
7614 Following traditional nomenclature, these bits map to:
7616 BIT0 | BIT 1 | BIT 2 | BIT 3
7619 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7624 /* All variant. OV bit. */
7626 /* We need to get to the OV bit, which is the ORDERED bit. We
7627 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7628 that's ugly and will make validate_condition_mode die.
7629 So let's just use another pattern. */
7630 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7632 /* Any variant. EQ bit. */
7636 /* Upper variant. LT bit. */
7640 /* Lower variant. GT bit. */
7645 error ("argument 1 of __builtin_spe_predicate is out of range");
7649 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7650 emit_move_insn (target, tmp);
7655 /* The evsel builtins look like this:
7657 e = __builtin_spe_evsel_OP (a, b, c, d);
7661 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7662 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7666 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7669 tree arg0 = TREE_VALUE (arglist);
7670 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7671 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7672 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7673 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7674 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7675 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7676 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7677 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7678 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7680 gcc_assert (mode0 == mode1);
7682 if (arg0 == error_mark_node || arg1 == error_mark_node
7683 || arg2 == error_mark_node || arg3 == error_mark_node)
7687 || GET_MODE (target) != mode0
7688 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7689 target = gen_reg_rtx (mode0);
7691 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7692 op0 = copy_to_mode_reg (mode0, op0);
7693 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7694 op1 = copy_to_mode_reg (mode0, op1);
7695 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7696 op2 = copy_to_mode_reg (mode0, op2);
7697 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7698 op3 = copy_to_mode_reg (mode0, op3);
7700 /* Generate the compare. */
7701 scratch = gen_reg_rtx (CCmode);
7702 pat = GEN_FCN (icode) (scratch, op0, op1);
7707 if (mode0 == V2SImode)
7708 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7710 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7715 /* Expand an expression EXP that calls a built-in function,
7716 with result going to TARGET if that's convenient
7717 (and in mode MODE if that's convenient).
7718 SUBTARGET may be used as the target for computing one of EXP's operands.
7719 IGNORE is nonzero if the value is to be ignored. */
7722 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7723 enum machine_mode mode ATTRIBUTE_UNUSED,
7724 int ignore ATTRIBUTE_UNUSED)
7726 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7727 tree arglist = TREE_OPERAND (exp, 1);
7728 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7729 struct builtin_description *d;
7734 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7735 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7737 int icode = (int) CODE_FOR_altivec_lvsr;
7738 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7739 enum machine_mode mode = insn_data[icode].operand[1].mode;
7743 gcc_assert (TARGET_ALTIVEC);
7745 arg = TREE_VALUE (arglist);
7746 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7747 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7748 addr = memory_address (mode, op);
7749 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7753 /* For the load case need to negate the address. */
7754 op = gen_reg_rtx (GET_MODE (addr));
7755 emit_insn (gen_rtx_SET (VOIDmode, op,
7756 gen_rtx_NEG (GET_MODE (addr), addr)));
7758 op = gen_rtx_MEM (mode, op);
7761 || GET_MODE (target) != tmode
7762 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7763 target = gen_reg_rtx (tmode);
7765 /*pat = gen_altivec_lvsr (target, op);*/
7766 pat = GEN_FCN (icode) (target, op);
7776 ret = altivec_expand_builtin (exp, target, &success);
7783 ret = spe_expand_builtin (exp, target, &success);
7789 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7791 /* Handle simple unary operations. */
7792 d = (struct builtin_description *) bdesc_1arg;
7793 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7794 if (d->code == fcode)
7795 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7797 /* Handle simple binary operations. */
7798 d = (struct builtin_description *) bdesc_2arg;
7799 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7800 if (d->code == fcode)
7801 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7803 /* Handle simple ternary operations. */
7804 d = (struct builtin_description *) bdesc_3arg;
7805 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7806 if (d->code == fcode)
7807 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7813 build_opaque_vector_type (tree node, int nunits)
7815 node = copy_node (node);
7816 TYPE_MAIN_VARIANT (node) = node;
7817 return build_vector_type (node, nunits);
7821 rs6000_init_builtins (void)
7823 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7824 V2SF_type_node = build_vector_type (float_type_node, 2);
7825 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7826 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7827 V4SF_type_node = build_vector_type (float_type_node, 4);
7828 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7829 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7831 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7832 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7833 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7835 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7836 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7837 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7838 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7840 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7841 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7842 'vector unsigned short'. */
7844 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7845 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7846 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7847 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7849 long_integer_type_internal_node = long_integer_type_node;
7850 long_unsigned_type_internal_node = long_unsigned_type_node;
7851 intQI_type_internal_node = intQI_type_node;
7852 uintQI_type_internal_node = unsigned_intQI_type_node;
7853 intHI_type_internal_node = intHI_type_node;
7854 uintHI_type_internal_node = unsigned_intHI_type_node;
7855 intSI_type_internal_node = intSI_type_node;
7856 uintSI_type_internal_node = unsigned_intSI_type_node;
7857 float_type_internal_node = float_type_node;
7858 void_type_internal_node = void_type_node;
7860 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7861 get_identifier ("__bool char"),
7862 bool_char_type_node));
7863 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7864 get_identifier ("__bool short"),
7865 bool_short_type_node));
7866 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7867 get_identifier ("__bool int"),
7868 bool_int_type_node));
7869 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7870 get_identifier ("__pixel"),
7873 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7874 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7875 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7876 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7878 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7879 get_identifier ("__vector unsigned char"),
7880 unsigned_V16QI_type_node));
7881 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7882 get_identifier ("__vector signed char"),
7884 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7885 get_identifier ("__vector __bool char"),
7886 bool_V16QI_type_node));
7888 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7889 get_identifier ("__vector unsigned short"),
7890 unsigned_V8HI_type_node));
7891 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7892 get_identifier ("__vector signed short"),
7894 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7895 get_identifier ("__vector __bool short"),
7896 bool_V8HI_type_node));
7898 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7899 get_identifier ("__vector unsigned int"),
7900 unsigned_V4SI_type_node));
7901 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7902 get_identifier ("__vector signed int"),
7904 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7905 get_identifier ("__vector __bool int"),
7906 bool_V4SI_type_node));
7908 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7909 get_identifier ("__vector float"),
7911 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7912 get_identifier ("__vector __pixel"),
7913 pixel_V8HI_type_node));
7916 spe_init_builtins ();
7918 altivec_init_builtins ();
7919 if (TARGET_ALTIVEC || TARGET_SPE)
7920 rs6000_common_init_builtins ();
7923 /* Search through a set of builtins and enable the mask bits.
7924 DESC is an array of builtins.
7925 SIZE is the total number of builtins.
7926 START is the builtin enum at which to start.
7927 END is the builtin enum at which to end. */
7929 enable_mask_for_builtins (struct builtin_description *desc, int size,
7930 enum rs6000_builtins start,
7931 enum rs6000_builtins end)
7935 for (i = 0; i < size; ++i)
7936 if (desc[i].code == start)
7942 for (; i < size; ++i)
7944 /* Flip all the bits on. */
7945 desc[i].mask = target_flags;
7946 if (desc[i].code == end)
7952 spe_init_builtins (void)
7954 tree endlink = void_list_node;
7955 tree puint_type_node = build_pointer_type (unsigned_type_node);
7956 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7957 struct builtin_description *d;
7960 tree v2si_ftype_4_v2si
7961 = build_function_type
7962 (opaque_V2SI_type_node,
7963 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7964 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7965 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7966 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7969 tree v2sf_ftype_4_v2sf
7970 = build_function_type
7971 (opaque_V2SF_type_node,
7972 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7973 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7974 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7975 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7978 tree int_ftype_int_v2si_v2si
7979 = build_function_type
7981 tree_cons (NULL_TREE, integer_type_node,
7982 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7983 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7986 tree int_ftype_int_v2sf_v2sf
7987 = build_function_type
7989 tree_cons (NULL_TREE, integer_type_node,
7990 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7991 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7994 tree void_ftype_v2si_puint_int
7995 = build_function_type (void_type_node,
7996 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7997 tree_cons (NULL_TREE, puint_type_node,
7998 tree_cons (NULL_TREE,
8002 tree void_ftype_v2si_puint_char
8003 = build_function_type (void_type_node,
8004 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8005 tree_cons (NULL_TREE, puint_type_node,
8006 tree_cons (NULL_TREE,
8010 tree void_ftype_v2si_pv2si_int
8011 = build_function_type (void_type_node,
8012 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8013 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8014 tree_cons (NULL_TREE,
8018 tree void_ftype_v2si_pv2si_char
8019 = build_function_type (void_type_node,
8020 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8021 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8022 tree_cons (NULL_TREE,
8027 = build_function_type (void_type_node,
8028 tree_cons (NULL_TREE, integer_type_node, endlink));
8031 = build_function_type (integer_type_node, endlink);
8033 tree v2si_ftype_pv2si_int
8034 = build_function_type (opaque_V2SI_type_node,
8035 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8036 tree_cons (NULL_TREE, integer_type_node,
8039 tree v2si_ftype_puint_int
8040 = build_function_type (opaque_V2SI_type_node,
8041 tree_cons (NULL_TREE, puint_type_node,
8042 tree_cons (NULL_TREE, integer_type_node,
8045 tree v2si_ftype_pushort_int
8046 = build_function_type (opaque_V2SI_type_node,
8047 tree_cons (NULL_TREE, pushort_type_node,
8048 tree_cons (NULL_TREE, integer_type_node,
8051 tree v2si_ftype_signed_char
8052 = build_function_type (opaque_V2SI_type_node,
8053 tree_cons (NULL_TREE, signed_char_type_node,
8056 /* The initialization of the simple binary and unary builtins is
8057 done in rs6000_common_init_builtins, but we have to enable the
8058 mask bits here manually because we have run out of `target_flags'
8059 bits. We really need to redesign this mask business. */
8061 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8062 ARRAY_SIZE (bdesc_2arg),
8065 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8066 ARRAY_SIZE (bdesc_1arg),
8068 SPE_BUILTIN_EVSUBFUSIAAW);
8069 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8070 ARRAY_SIZE (bdesc_spe_predicates),
8071 SPE_BUILTIN_EVCMPEQ,
8072 SPE_BUILTIN_EVFSTSTLT);
8073 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8074 ARRAY_SIZE (bdesc_spe_evsel),
8075 SPE_BUILTIN_EVSEL_CMPGTS,
8076 SPE_BUILTIN_EVSEL_FSTSTEQ);
8078 (*lang_hooks.decls.pushdecl)
8079 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8080 opaque_V2SI_type_node));
8082 /* Initialize irregular SPE builtins. */
8084 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8085 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8086 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8087 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8088 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8089 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8090 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8091 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8092 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8093 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8094 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8095 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8096 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8097 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8098 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8099 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8100 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8101 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8104 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8105 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8106 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8107 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8108 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8109 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8110 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8111 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8112 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8113 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8114 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8115 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8116 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8117 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8118 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8119 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8120 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8121 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8122 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8123 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8124 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8125 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8128 d = (struct builtin_description *) bdesc_spe_predicates;
8129 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8133 switch (insn_data[d->icode].operand[1].mode)
8136 type = int_ftype_int_v2si_v2si;
8139 type = int_ftype_int_v2sf_v2sf;
8145 def_builtin (d->mask, d->name, type, d->code);
8148 /* Evsel predicates. */
8149 d = (struct builtin_description *) bdesc_spe_evsel;
8150 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8154 switch (insn_data[d->icode].operand[1].mode)
8157 type = v2si_ftype_4_v2si;
8160 type = v2sf_ftype_4_v2sf;
8166 def_builtin (d->mask, d->name, type, d->code);
8171 altivec_init_builtins (void)
8173 struct builtin_description *d;
8174 struct builtin_description_predicates *dp;
8178 tree pfloat_type_node = build_pointer_type (float_type_node);
8179 tree pint_type_node = build_pointer_type (integer_type_node);
8180 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8181 tree pchar_type_node = build_pointer_type (char_type_node);
8183 tree pvoid_type_node = build_pointer_type (void_type_node);
8185 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8186 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8187 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8188 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8190 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8192 tree int_ftype_opaque
8193 = build_function_type_list (integer_type_node,
8194 opaque_V4SI_type_node, NULL_TREE);
8196 tree opaque_ftype_opaque_int
8197 = build_function_type_list (opaque_V4SI_type_node,
8198 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8199 tree opaque_ftype_opaque_opaque_int
8200 = build_function_type_list (opaque_V4SI_type_node,
8201 opaque_V4SI_type_node, opaque_V4SI_type_node,
8202 integer_type_node, NULL_TREE);
8203 tree int_ftype_int_opaque_opaque
8204 = build_function_type_list (integer_type_node,
8205 integer_type_node, opaque_V4SI_type_node,
8206 opaque_V4SI_type_node, NULL_TREE);
8207 tree int_ftype_int_v4si_v4si
8208 = build_function_type_list (integer_type_node,
8209 integer_type_node, V4SI_type_node,
8210 V4SI_type_node, NULL_TREE);
8211 tree v4sf_ftype_pcfloat
8212 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8213 tree void_ftype_pfloat_v4sf
8214 = build_function_type_list (void_type_node,
8215 pfloat_type_node, V4SF_type_node, NULL_TREE);
8216 tree v4si_ftype_pcint
8217 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8218 tree void_ftype_pint_v4si
8219 = build_function_type_list (void_type_node,
8220 pint_type_node, V4SI_type_node, NULL_TREE);
8221 tree v8hi_ftype_pcshort
8222 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8223 tree void_ftype_pshort_v8hi
8224 = build_function_type_list (void_type_node,
8225 pshort_type_node, V8HI_type_node, NULL_TREE);
8226 tree v16qi_ftype_pcchar
8227 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8228 tree void_ftype_pchar_v16qi
8229 = build_function_type_list (void_type_node,
8230 pchar_type_node, V16QI_type_node, NULL_TREE);
8231 tree void_ftype_v4si
8232 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8233 tree v8hi_ftype_void
8234 = build_function_type (V8HI_type_node, void_list_node);
8235 tree void_ftype_void
8236 = build_function_type (void_type_node, void_list_node);
8238 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8240 tree opaque_ftype_long_pcvoid
8241 = build_function_type_list (opaque_V4SI_type_node,
8242 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8243 tree v16qi_ftype_long_pcvoid
8244 = build_function_type_list (V16QI_type_node,
8245 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8246 tree v8hi_ftype_long_pcvoid
8247 = build_function_type_list (V8HI_type_node,
8248 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8249 tree v4si_ftype_long_pcvoid
8250 = build_function_type_list (V4SI_type_node,
8251 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8253 tree void_ftype_opaque_long_pvoid
8254 = build_function_type_list (void_type_node,
8255 opaque_V4SI_type_node, long_integer_type_node,
8256 pvoid_type_node, NULL_TREE);
8257 tree void_ftype_v4si_long_pvoid
8258 = build_function_type_list (void_type_node,
8259 V4SI_type_node, long_integer_type_node,
8260 pvoid_type_node, NULL_TREE);
8261 tree void_ftype_v16qi_long_pvoid
8262 = build_function_type_list (void_type_node,
8263 V16QI_type_node, long_integer_type_node,
8264 pvoid_type_node, NULL_TREE);
8265 tree void_ftype_v8hi_long_pvoid
8266 = build_function_type_list (void_type_node,
8267 V8HI_type_node, long_integer_type_node,
8268 pvoid_type_node, NULL_TREE);
8269 tree int_ftype_int_v8hi_v8hi
8270 = build_function_type_list (integer_type_node,
8271 integer_type_node, V8HI_type_node,
8272 V8HI_type_node, NULL_TREE);
8273 tree int_ftype_int_v16qi_v16qi
8274 = build_function_type_list (integer_type_node,
8275 integer_type_node, V16QI_type_node,
8276 V16QI_type_node, NULL_TREE);
8277 tree int_ftype_int_v4sf_v4sf
8278 = build_function_type_list (integer_type_node,
8279 integer_type_node, V4SF_type_node,
8280 V4SF_type_node, NULL_TREE);
8281 tree v4si_ftype_v4si
8282 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8283 tree v8hi_ftype_v8hi
8284 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8285 tree v16qi_ftype_v16qi
8286 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8287 tree v4sf_ftype_v4sf
8288 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8289 tree void_ftype_pcvoid_int_int
8290 = build_function_type_list (void_type_node,
8291 pcvoid_type_node, integer_type_node,
8292 integer_type_node, NULL_TREE);
8294 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8295 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8296 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8297 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8298 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8299 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8300 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8301 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8302 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8303 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8304 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8305 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8306 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8307 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8308 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8309 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8310 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8311 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8312 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8313 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8314 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8315 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8316 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8317 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8318 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8319 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8320 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8321 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8322 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8323 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8324 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8325 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8326 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8327 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8328 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8329 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8330 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8331 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8332 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8333 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8334 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8335 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8336 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8337 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8338 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8339 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8341 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8343 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8344 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8345 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8346 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8347 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8348 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8349 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8350 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8351 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8352 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8354 /* Add the DST variants. */
8355 d = (struct builtin_description *) bdesc_dst;
8356 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8357 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8359 /* Initialize the predicates. */
8360 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8361 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8363 enum machine_mode mode1;
8365 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8366 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8371 mode1 = insn_data[dp->icode].operand[1].mode;
8376 type = int_ftype_int_opaque_opaque;
8379 type = int_ftype_int_v4si_v4si;
8382 type = int_ftype_int_v8hi_v8hi;
8385 type = int_ftype_int_v16qi_v16qi;
8388 type = int_ftype_int_v4sf_v4sf;
8394 def_builtin (dp->mask, dp->name, type, dp->code);
8397 /* Initialize the abs* operators. */
8398 d = (struct builtin_description *) bdesc_abs;
8399 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8401 enum machine_mode mode0;
8404 mode0 = insn_data[d->icode].operand[0].mode;
8409 type = v4si_ftype_v4si;
8412 type = v8hi_ftype_v8hi;
8415 type = v16qi_ftype_v16qi;
8418 type = v4sf_ftype_v4sf;
8424 def_builtin (d->mask, d->name, type, d->code);
8431 /* Initialize target builtin that implements
8432 targetm.vectorize.builtin_mask_for_load. */
8434 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8435 v16qi_ftype_long_pcvoid,
8436 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8438 tree_cons (get_identifier ("const"),
8439 NULL_TREE, NULL_TREE));
8440 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8441 altivec_builtin_mask_for_load = decl;
8444 /* Access to the vec_init patterns. */
8445 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8446 integer_type_node, integer_type_node,
8447 integer_type_node, NULL_TREE);
8448 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8449 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8451 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8452 short_integer_type_node,
8453 short_integer_type_node,
8454 short_integer_type_node,
8455 short_integer_type_node,
8456 short_integer_type_node,
8457 short_integer_type_node,
8458 short_integer_type_node, NULL_TREE);
8459 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8460 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8462 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8463 char_type_node, char_type_node,
8464 char_type_node, char_type_node,
8465 char_type_node, char_type_node,
8466 char_type_node, char_type_node,
8467 char_type_node, char_type_node,
8468 char_type_node, char_type_node,
8469 char_type_node, char_type_node,
8470 char_type_node, NULL_TREE);
8471 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8472 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8474 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8475 float_type_node, float_type_node,
8476 float_type_node, NULL_TREE);
8477 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8478 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8480 /* Access to the vec_set patterns. */
8481 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8483 integer_type_node, NULL_TREE);
8484 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8485 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8487 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8489 integer_type_node, NULL_TREE);
8490 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8491 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8493 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8495 integer_type_node, NULL_TREE);
8496 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8497 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8499 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8501 integer_type_node, NULL_TREE);
8502 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8503 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8505 /* Access to the vec_extract patterns. */
8506 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8507 integer_type_node, NULL_TREE);
8508 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8509 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8511 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8512 integer_type_node, NULL_TREE);
8513 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8514 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8516 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8517 integer_type_node, NULL_TREE);
8518 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8519 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8521 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8522 integer_type_node, NULL_TREE);
8523 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8524 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8528 rs6000_common_init_builtins (void)
8530 struct builtin_description *d;
8533 tree v4sf_ftype_v4sf_v4sf_v16qi
8534 = build_function_type_list (V4SF_type_node,
8535 V4SF_type_node, V4SF_type_node,
8536 V16QI_type_node, NULL_TREE);
8537 tree v4si_ftype_v4si_v4si_v16qi
8538 = build_function_type_list (V4SI_type_node,
8539 V4SI_type_node, V4SI_type_node,
8540 V16QI_type_node, NULL_TREE);
8541 tree v8hi_ftype_v8hi_v8hi_v16qi
8542 = build_function_type_list (V8HI_type_node,
8543 V8HI_type_node, V8HI_type_node,
8544 V16QI_type_node, NULL_TREE);
8545 tree v16qi_ftype_v16qi_v16qi_v16qi
8546 = build_function_type_list (V16QI_type_node,
8547 V16QI_type_node, V16QI_type_node,
8548 V16QI_type_node, NULL_TREE);
8550 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8552 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8553 tree v16qi_ftype_int
8554 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8555 tree v8hi_ftype_v16qi
8556 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8557 tree v4sf_ftype_v4sf
8558 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8560 tree v2si_ftype_v2si_v2si
8561 = build_function_type_list (opaque_V2SI_type_node,
8562 opaque_V2SI_type_node,
8563 opaque_V2SI_type_node, NULL_TREE);
8565 tree v2sf_ftype_v2sf_v2sf
8566 = build_function_type_list (opaque_V2SF_type_node,
8567 opaque_V2SF_type_node,
8568 opaque_V2SF_type_node, NULL_TREE);
8570 tree v2si_ftype_int_int
8571 = build_function_type_list (opaque_V2SI_type_node,
8572 integer_type_node, integer_type_node,
8575 tree opaque_ftype_opaque
8576 = build_function_type_list (opaque_V4SI_type_node,
8577 opaque_V4SI_type_node, NULL_TREE);
8579 tree v2si_ftype_v2si
8580 = build_function_type_list (opaque_V2SI_type_node,
8581 opaque_V2SI_type_node, NULL_TREE);
8583 tree v2sf_ftype_v2sf
8584 = build_function_type_list (opaque_V2SF_type_node,
8585 opaque_V2SF_type_node, NULL_TREE);
8587 tree v2sf_ftype_v2si
8588 = build_function_type_list (opaque_V2SF_type_node,
8589 opaque_V2SI_type_node, NULL_TREE);
8591 tree v2si_ftype_v2sf
8592 = build_function_type_list (opaque_V2SI_type_node,
8593 opaque_V2SF_type_node, NULL_TREE);
8595 tree v2si_ftype_v2si_char
8596 = build_function_type_list (opaque_V2SI_type_node,
8597 opaque_V2SI_type_node,
8598 char_type_node, NULL_TREE);
8600 tree v2si_ftype_int_char
8601 = build_function_type_list (opaque_V2SI_type_node,
8602 integer_type_node, char_type_node, NULL_TREE);
8604 tree v2si_ftype_char
8605 = build_function_type_list (opaque_V2SI_type_node,
8606 char_type_node, NULL_TREE);
8608 tree int_ftype_int_int
8609 = build_function_type_list (integer_type_node,
8610 integer_type_node, integer_type_node,
8613 tree opaque_ftype_opaque_opaque
8614 = build_function_type_list (opaque_V4SI_type_node,
8615 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8616 tree v4si_ftype_v4si_v4si
8617 = build_function_type_list (V4SI_type_node,
8618 V4SI_type_node, V4SI_type_node, NULL_TREE);
8619 tree v4sf_ftype_v4si_int
8620 = build_function_type_list (V4SF_type_node,
8621 V4SI_type_node, integer_type_node, NULL_TREE);
8622 tree v4si_ftype_v4sf_int
8623 = build_function_type_list (V4SI_type_node,
8624 V4SF_type_node, integer_type_node, NULL_TREE);
8625 tree v4si_ftype_v4si_int
8626 = build_function_type_list (V4SI_type_node,
8627 V4SI_type_node, integer_type_node, NULL_TREE);
8628 tree v8hi_ftype_v8hi_int
8629 = build_function_type_list (V8HI_type_node,
8630 V8HI_type_node, integer_type_node, NULL_TREE);
8631 tree v16qi_ftype_v16qi_int
8632 = build_function_type_list (V16QI_type_node,
8633 V16QI_type_node, integer_type_node, NULL_TREE);
8634 tree v16qi_ftype_v16qi_v16qi_int
8635 = build_function_type_list (V16QI_type_node,
8636 V16QI_type_node, V16QI_type_node,
8637 integer_type_node, NULL_TREE);
8638 tree v8hi_ftype_v8hi_v8hi_int
8639 = build_function_type_list (V8HI_type_node,
8640 V8HI_type_node, V8HI_type_node,
8641 integer_type_node, NULL_TREE);
8642 tree v4si_ftype_v4si_v4si_int
8643 = build_function_type_list (V4SI_type_node,
8644 V4SI_type_node, V4SI_type_node,
8645 integer_type_node, NULL_TREE);
8646 tree v4sf_ftype_v4sf_v4sf_int
8647 = build_function_type_list (V4SF_type_node,
8648 V4SF_type_node, V4SF_type_node,
8649 integer_type_node, NULL_TREE);
8650 tree v4sf_ftype_v4sf_v4sf
8651 = build_function_type_list (V4SF_type_node,
8652 V4SF_type_node, V4SF_type_node, NULL_TREE);
8653 tree opaque_ftype_opaque_opaque_opaque
8654 = build_function_type_list (opaque_V4SI_type_node,
8655 opaque_V4SI_type_node, opaque_V4SI_type_node,
8656 opaque_V4SI_type_node, NULL_TREE);
8657 tree v4sf_ftype_v4sf_v4sf_v4si
8658 = build_function_type_list (V4SF_type_node,
8659 V4SF_type_node, V4SF_type_node,
8660 V4SI_type_node, NULL_TREE);
8661 tree v4sf_ftype_v4sf_v4sf_v4sf
8662 = build_function_type_list (V4SF_type_node,
8663 V4SF_type_node, V4SF_type_node,
8664 V4SF_type_node, NULL_TREE);
8665 tree v4si_ftype_v4si_v4si_v4si
8666 = build_function_type_list (V4SI_type_node,
8667 V4SI_type_node, V4SI_type_node,
8668 V4SI_type_node, NULL_TREE);
8669 tree v8hi_ftype_v8hi_v8hi
8670 = build_function_type_list (V8HI_type_node,
8671 V8HI_type_node, V8HI_type_node, NULL_TREE);
8672 tree v8hi_ftype_v8hi_v8hi_v8hi
8673 = build_function_type_list (V8HI_type_node,
8674 V8HI_type_node, V8HI_type_node,
8675 V8HI_type_node, NULL_TREE);
8676 tree v4si_ftype_v8hi_v8hi_v4si
8677 = build_function_type_list (V4SI_type_node,
8678 V8HI_type_node, V8HI_type_node,
8679 V4SI_type_node, NULL_TREE);
8680 tree v4si_ftype_v16qi_v16qi_v4si
8681 = build_function_type_list (V4SI_type_node,
8682 V16QI_type_node, V16QI_type_node,
8683 V4SI_type_node, NULL_TREE);
8684 tree v16qi_ftype_v16qi_v16qi
8685 = build_function_type_list (V16QI_type_node,
8686 V16QI_type_node, V16QI_type_node, NULL_TREE);
8687 tree v4si_ftype_v4sf_v4sf
8688 = build_function_type_list (V4SI_type_node,
8689 V4SF_type_node, V4SF_type_node, NULL_TREE);
8690 tree v8hi_ftype_v16qi_v16qi
8691 = build_function_type_list (V8HI_type_node,
8692 V16QI_type_node, V16QI_type_node, NULL_TREE);
8693 tree v4si_ftype_v8hi_v8hi
8694 = build_function_type_list (V4SI_type_node,
8695 V8HI_type_node, V8HI_type_node, NULL_TREE);
8696 tree v8hi_ftype_v4si_v4si
8697 = build_function_type_list (V8HI_type_node,
8698 V4SI_type_node, V4SI_type_node, NULL_TREE);
8699 tree v16qi_ftype_v8hi_v8hi
8700 = build_function_type_list (V16QI_type_node,
8701 V8HI_type_node, V8HI_type_node, NULL_TREE);
8702 tree v4si_ftype_v16qi_v4si
8703 = build_function_type_list (V4SI_type_node,
8704 V16QI_type_node, V4SI_type_node, NULL_TREE);
8705 tree v4si_ftype_v16qi_v16qi
8706 = build_function_type_list (V4SI_type_node,
8707 V16QI_type_node, V16QI_type_node, NULL_TREE);
8708 tree v4si_ftype_v8hi_v4si
8709 = build_function_type_list (V4SI_type_node,
8710 V8HI_type_node, V4SI_type_node, NULL_TREE);
8711 tree v4si_ftype_v8hi
8712 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8713 tree int_ftype_v4si_v4si
8714 = build_function_type_list (integer_type_node,
8715 V4SI_type_node, V4SI_type_node, NULL_TREE);
8716 tree int_ftype_v4sf_v4sf
8717 = build_function_type_list (integer_type_node,
8718 V4SF_type_node, V4SF_type_node, NULL_TREE);
8719 tree int_ftype_v16qi_v16qi
8720 = build_function_type_list (integer_type_node,
8721 V16QI_type_node, V16QI_type_node, NULL_TREE);
8722 tree int_ftype_v8hi_v8hi
8723 = build_function_type_list (integer_type_node,
8724 V8HI_type_node, V8HI_type_node, NULL_TREE);
8726 /* Add the simple ternary operators. */
8727 d = (struct builtin_description *) bdesc_3arg;
8728 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8730 enum machine_mode mode0, mode1, mode2, mode3;
8732 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8733 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8744 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8747 mode0 = insn_data[d->icode].operand[0].mode;
8748 mode1 = insn_data[d->icode].operand[1].mode;
8749 mode2 = insn_data[d->icode].operand[2].mode;
8750 mode3 = insn_data[d->icode].operand[3].mode;
8753 /* When all four are of the same mode. */
8754 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8759 type = opaque_ftype_opaque_opaque_opaque;
8762 type = v4si_ftype_v4si_v4si_v4si;
8765 type = v4sf_ftype_v4sf_v4sf_v4sf;
8768 type = v8hi_ftype_v8hi_v8hi_v8hi;
8771 type = v16qi_ftype_v16qi_v16qi_v16qi;
8777 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8782 type = v4si_ftype_v4si_v4si_v16qi;
8785 type = v4sf_ftype_v4sf_v4sf_v16qi;
8788 type = v8hi_ftype_v8hi_v8hi_v16qi;
8791 type = v16qi_ftype_v16qi_v16qi_v16qi;
8797 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8798 && mode3 == V4SImode)
8799 type = v4si_ftype_v16qi_v16qi_v4si;
8800 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8801 && mode3 == V4SImode)
8802 type = v4si_ftype_v8hi_v8hi_v4si;
8803 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8804 && mode3 == V4SImode)
8805 type = v4sf_ftype_v4sf_v4sf_v4si;
8807 /* vchar, vchar, vchar, 4 bit literal. */
8808 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8810 type = v16qi_ftype_v16qi_v16qi_int;
8812 /* vshort, vshort, vshort, 4 bit literal. */
8813 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8815 type = v8hi_ftype_v8hi_v8hi_int;
8817 /* vint, vint, vint, 4 bit literal. */
8818 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8820 type = v4si_ftype_v4si_v4si_int;
8822 /* vfloat, vfloat, vfloat, 4 bit literal. */
8823 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8825 type = v4sf_ftype_v4sf_v4sf_int;
8830 def_builtin (d->mask, d->name, type, d->code);
8833 /* Add the simple binary operators. */
8834 d = (struct builtin_description *) bdesc_2arg;
8835 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8837 enum machine_mode mode0, mode1, mode2;
8839 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8840 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8850 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8853 mode0 = insn_data[d->icode].operand[0].mode;
8854 mode1 = insn_data[d->icode].operand[1].mode;
8855 mode2 = insn_data[d->icode].operand[2].mode;
8858 /* When all three operands are of the same mode. */
8859 if (mode0 == mode1 && mode1 == mode2)
8864 type = opaque_ftype_opaque_opaque;
8867 type = v4sf_ftype_v4sf_v4sf;
8870 type = v4si_ftype_v4si_v4si;
8873 type = v16qi_ftype_v16qi_v16qi;
8876 type = v8hi_ftype_v8hi_v8hi;
8879 type = v2si_ftype_v2si_v2si;
8882 type = v2sf_ftype_v2sf_v2sf;
8885 type = int_ftype_int_int;
8892 /* A few other combos we really don't want to do manually. */
8894 /* vint, vfloat, vfloat. */
8895 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8896 type = v4si_ftype_v4sf_v4sf;
8898 /* vshort, vchar, vchar. */
8899 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8900 type = v8hi_ftype_v16qi_v16qi;
8902 /* vint, vshort, vshort. */
8903 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8904 type = v4si_ftype_v8hi_v8hi;
8906 /* vshort, vint, vint. */
8907 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8908 type = v8hi_ftype_v4si_v4si;
8910 /* vchar, vshort, vshort. */
8911 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8912 type = v16qi_ftype_v8hi_v8hi;
8914 /* vint, vchar, vint. */
8915 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8916 type = v4si_ftype_v16qi_v4si;
8918 /* vint, vchar, vchar. */
8919 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8920 type = v4si_ftype_v16qi_v16qi;
8922 /* vint, vshort, vint. */
8923 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8924 type = v4si_ftype_v8hi_v4si;
8926 /* vint, vint, 5 bit literal. */
8927 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8928 type = v4si_ftype_v4si_int;
8930 /* vshort, vshort, 5 bit literal. */
8931 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8932 type = v8hi_ftype_v8hi_int;
8934 /* vchar, vchar, 5 bit literal. */
8935 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8936 type = v16qi_ftype_v16qi_int;
8938 /* vfloat, vint, 5 bit literal. */
8939 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8940 type = v4sf_ftype_v4si_int;
8942 /* vint, vfloat, 5 bit literal. */
8943 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8944 type = v4si_ftype_v4sf_int;
8946 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8947 type = v2si_ftype_int_int;
8949 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8950 type = v2si_ftype_v2si_char;
8952 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8953 type = v2si_ftype_int_char;
8958 gcc_assert (mode0 == SImode);
8962 type = int_ftype_v4si_v4si;
8965 type = int_ftype_v4sf_v4sf;
8968 type = int_ftype_v16qi_v16qi;
8971 type = int_ftype_v8hi_v8hi;
8978 def_builtin (d->mask, d->name, type, d->code);
8981 /* Add the simple unary operators. */
8982 d = (struct builtin_description *) bdesc_1arg;
8983 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8985 enum machine_mode mode0, mode1;
8987 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8988 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8997 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9000 mode0 = insn_data[d->icode].operand[0].mode;
9001 mode1 = insn_data[d->icode].operand[1].mode;
9004 if (mode0 == V4SImode && mode1 == QImode)
9005 type = v4si_ftype_int;
9006 else if (mode0 == V8HImode && mode1 == QImode)
9007 type = v8hi_ftype_int;
9008 else if (mode0 == V16QImode && mode1 == QImode)
9009 type = v16qi_ftype_int;
9010 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9011 type = opaque_ftype_opaque;
9012 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9013 type = v4sf_ftype_v4sf;
9014 else if (mode0 == V8HImode && mode1 == V16QImode)
9015 type = v8hi_ftype_v16qi;
9016 else if (mode0 == V4SImode && mode1 == V8HImode)
9017 type = v4si_ftype_v8hi;
9018 else if (mode0 == V2SImode && mode1 == V2SImode)
9019 type = v2si_ftype_v2si;
9020 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9021 type = v2sf_ftype_v2sf;
9022 else if (mode0 == V2SFmode && mode1 == V2SImode)
9023 type = v2sf_ftype_v2si;
9024 else if (mode0 == V2SImode && mode1 == V2SFmode)
9025 type = v2si_ftype_v2sf;
9026 else if (mode0 == V2SImode && mode1 == QImode)
9027 type = v2si_ftype_char;
9031 def_builtin (d->mask, d->name, type, d->code);
9036 rs6000_init_libfuncs (void)
9038 if (!TARGET_HARD_FLOAT)
9041 if (DEFAULT_ABI != ABI_V4)
9043 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
9045 /* AIX library routines for float->int conversion. */
9046 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9047 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9048 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9049 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9052 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9053 if (!TARGET_XL_COMPAT)
9055 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9056 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9057 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9058 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9062 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9063 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9064 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9065 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9070 /* 32-bit SVR4 quad floating point routines. */
9072 set_optab_libfunc (add_optab, TFmode, "_q_add");
9073 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9074 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9075 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9076 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9077 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9078 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9080 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9081 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9082 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9083 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9084 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9085 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9087 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9088 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9089 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9090 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9091 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9092 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9093 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9094 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9099 /* Expand a block clear operation, and return 1 if successful. Return 0
9100 if we should let the compiler generate normal code.
9102 operands[0] is the destination
9103 operands[1] is the length
9104 operands[3] is the alignment */
9107 expand_block_clear (rtx operands[])
9109 rtx orig_dest = operands[0];
9110 rtx bytes_rtx = operands[1];
9111 rtx align_rtx = operands[3];
9112 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9113 HOST_WIDE_INT align;
9114 HOST_WIDE_INT bytes;
9119 /* If this is not a fixed size move, just call memcpy */
9123 /* This must be a fixed size alignment */
9124 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9125 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9127 /* Anything to clear? */
9128 bytes = INTVAL (bytes_rtx);
9132 /* Use the builtin memset after a point, to avoid huge code bloat.
9133 When optimize_size, avoid any significant code bloat; calling
9134 memset is about 4 instructions, so allow for one instruction to
9135 load zero and three to do clearing. */
9136 if (TARGET_ALTIVEC && align >= 128)
9138 else if (TARGET_POWERPC64 && align >= 32)
9143 if (optimize_size && bytes > 3 * clear_step)
9145 if (! optimize_size && bytes > 8 * clear_step)
9148 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9150 enum machine_mode mode = BLKmode;
9153 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9158 else if (bytes >= 8 && TARGET_POWERPC64
9159 /* 64-bit loads and stores require word-aligned
9161 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9166 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9167 { /* move 4 bytes */
9171 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9172 { /* move 2 bytes */
9176 else /* move 1 byte at a time */
9182 dest = adjust_address (orig_dest, mode, offset);
9184 emit_move_insn (dest, CONST0_RTX (mode));
9191 /* Expand a block move operation, and return 1 if successful. Return 0
9192 if we should let the compiler generate normal code.
9194 operands[0] is the destination
9195 operands[1] is the source
9196 operands[2] is the length
9197 operands[3] is the alignment */
9199 #define MAX_MOVE_REG 4
9202 expand_block_move (rtx operands[])
9204 rtx orig_dest = operands[0];
9205 rtx orig_src = operands[1];
9206 rtx bytes_rtx = operands[2];
9207 rtx align_rtx = operands[3];
9208 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9213 rtx stores[MAX_MOVE_REG];
9216 /* If this is not a fixed size move, just call memcpy */
9220 /* This must be a fixed size alignment */
9221 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9222 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9224 /* Anything to move? */
9225 bytes = INTVAL (bytes_rtx);
9229 /* store_one_arg depends on expand_block_move to handle at least the size of
9230 reg_parm_stack_space. */
9231 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9234 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9237 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9238 rtx (*mov) (rtx, rtx);
9240 enum machine_mode mode = BLKmode;
9243 /* Altivec first, since it will be faster than a string move
9244 when it applies, and usually not significantly larger. */
9245 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9249 gen_func.mov = gen_movv4si;
9251 else if (TARGET_STRING
9252 && bytes > 24 /* move up to 32 bytes at a time */
9260 && ! fixed_regs[12])
9262 move_bytes = (bytes > 32) ? 32 : bytes;
9263 gen_func.movmemsi = gen_movmemsi_8reg;
9265 else if (TARGET_STRING
9266 && bytes > 16 /* move up to 24 bytes at a time */
9272 && ! fixed_regs[10])
9274 move_bytes = (bytes > 24) ? 24 : bytes;
9275 gen_func.movmemsi = gen_movmemsi_6reg;
9277 else if (TARGET_STRING
9278 && bytes > 8 /* move up to 16 bytes at a time */
9284 move_bytes = (bytes > 16) ? 16 : bytes;
9285 gen_func.movmemsi = gen_movmemsi_4reg;
9287 else if (bytes >= 8 && TARGET_POWERPC64
9288 /* 64-bit loads and stores require word-aligned
9290 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9294 gen_func.mov = gen_movdi;
9296 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9297 { /* move up to 8 bytes at a time */
9298 move_bytes = (bytes > 8) ? 8 : bytes;
9299 gen_func.movmemsi = gen_movmemsi_2reg;
9301 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9302 { /* move 4 bytes */
9305 gen_func.mov = gen_movsi;
9307 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9308 { /* move 2 bytes */
9311 gen_func.mov = gen_movhi;
9313 else if (TARGET_STRING && bytes > 1)
9314 { /* move up to 4 bytes at a time */
9315 move_bytes = (bytes > 4) ? 4 : bytes;
9316 gen_func.movmemsi = gen_movmemsi_1reg;
9318 else /* move 1 byte at a time */
9322 gen_func.mov = gen_movqi;
9325 src = adjust_address (orig_src, mode, offset);
9326 dest = adjust_address (orig_dest, mode, offset);
9328 if (mode != BLKmode)
9330 rtx tmp_reg = gen_reg_rtx (mode);
9332 emit_insn ((*gen_func.mov) (tmp_reg, src));
9333 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9336 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9339 for (i = 0; i < num_reg; i++)
9340 emit_insn (stores[i]);
9344 if (mode == BLKmode)
9346 /* Move the address into scratch registers. The movmemsi
9347 patterns require zero offset. */
9348 if (!REG_P (XEXP (src, 0)))
9350 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9351 src = replace_equiv_address (src, src_reg);
9353 set_mem_size (src, GEN_INT (move_bytes));
9355 if (!REG_P (XEXP (dest, 0)))
9357 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9358 dest = replace_equiv_address (dest, dest_reg);
9360 set_mem_size (dest, GEN_INT (move_bytes));
9362 emit_insn ((*gen_func.movmemsi) (dest, src,
9363 GEN_INT (move_bytes & 31),
9372 /* Return a string to perform a load_multiple operation.
9373 operands[0] is the vector.
9374 operands[1] is the source address.
9375 operands[2] is the first destination register. */
9378 rs6000_output_load_multiple (rtx operands[3])
9380 /* We have to handle the case where the pseudo used to contain the address
9381 is assigned to one of the output registers. */
9383 int words = XVECLEN (operands[0], 0);
9386 if (XVECLEN (operands[0], 0) == 1)
9387 return "{l|lwz} %2,0(%1)";
9389 for (i = 0; i < words; i++)
9390 if (refers_to_regno_p (REGNO (operands[2]) + i,
9391 REGNO (operands[2]) + i + 1, operands[1], 0))
9395 xop[0] = GEN_INT (4 * (words-1));
9396 xop[1] = operands[1];
9397 xop[2] = operands[2];
9398 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9403 xop[0] = GEN_INT (4 * (words-1));
9404 xop[1] = operands[1];
9405 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9406 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9411 for (j = 0; j < words; j++)
9414 xop[0] = GEN_INT (j * 4);
9415 xop[1] = operands[1];
9416 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9417 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9419 xop[0] = GEN_INT (i * 4);
9420 xop[1] = operands[1];
9421 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9426 return "{lsi|lswi} %2,%1,%N0";
9430 /* A validation routine: say whether CODE, a condition code, and MODE
9431 match. The other alternatives either don't make sense or should
9432 never be generated. */
9435 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9437 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9438 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9439 && GET_MODE_CLASS (mode) == MODE_CC);
9441 /* These don't make sense. */
9442 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9443 || mode != CCUNSmode);
9445 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9446 || mode == CCUNSmode);
9448 gcc_assert (mode == CCFPmode
9449 || (code != ORDERED && code != UNORDERED
9450 && code != UNEQ && code != LTGT
9451 && code != UNGT && code != UNLT
9452 && code != UNGE && code != UNLE));
9454 /* These should never be generated except for
9455 flag_finite_math_only. */
9456 gcc_assert (mode != CCFPmode
9457 || flag_finite_math_only
9458 || (code != LE && code != GE
9459 && code != UNEQ && code != LTGT
9460 && code != UNGT && code != UNLT));
9462 /* These are invalid; the information is not there. */
9463 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9467 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9468 mask required to convert the result of a rotate insn into a shift
9469 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9472 includes_lshift_p (rtx shiftop, rtx andop)
9474 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9476 shift_mask <<= INTVAL (shiftop);
9478 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9481 /* Similar, but for right shift. */
9484 includes_rshift_p (rtx shiftop, rtx andop)
9486 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9488 shift_mask >>= INTVAL (shiftop);
9490 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9493 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9494 to perform a left shift. It must have exactly SHIFTOP least
9495 significant 0's, then one or more 1's, then zero or more 0's. */
9498 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9500 if (GET_CODE (andop) == CONST_INT)
9502 HOST_WIDE_INT c, lsb, shift_mask;
9505 if (c == 0 || c == ~0)
9509 shift_mask <<= INTVAL (shiftop);
9511 /* Find the least significant one bit. */
9514 /* It must coincide with the LSB of the shift mask. */
9515 if (-lsb != shift_mask)
9518 /* Invert to look for the next transition (if any). */
9521 /* Remove the low group of ones (originally low group of zeros). */
9524 /* Again find the lsb, and check we have all 1's above. */
9528 else if (GET_CODE (andop) == CONST_DOUBLE
9529 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9531 HOST_WIDE_INT low, high, lsb;
9532 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9534 low = CONST_DOUBLE_LOW (andop);
9535 if (HOST_BITS_PER_WIDE_INT < 64)
9536 high = CONST_DOUBLE_HIGH (andop);
9538 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9539 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9542 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9544 shift_mask_high = ~0;
9545 if (INTVAL (shiftop) > 32)
9546 shift_mask_high <<= INTVAL (shiftop) - 32;
9550 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9557 return high == -lsb;
9560 shift_mask_low = ~0;
9561 shift_mask_low <<= INTVAL (shiftop);
9565 if (-lsb != shift_mask_low)
9568 if (HOST_BITS_PER_WIDE_INT < 64)
9573 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9576 return high == -lsb;
9580 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9586 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9587 to perform a left shift. It must have SHIFTOP or more least
9588 significant 0's, with the remainder of the word 1's. */
9591 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9593 if (GET_CODE (andop) == CONST_INT)
9595 HOST_WIDE_INT c, lsb, shift_mask;
9598 shift_mask <<= INTVAL (shiftop);
9601 /* Find the least significant one bit. */
9604 /* It must be covered by the shift mask.
9605 This test also rejects c == 0. */
9606 if ((lsb & shift_mask) == 0)
9609 /* Check we have all 1's above the transition, and reject all 1's. */
9610 return c == -lsb && lsb != 1;
9612 else if (GET_CODE (andop) == CONST_DOUBLE
9613 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9615 HOST_WIDE_INT low, lsb, shift_mask_low;
9617 low = CONST_DOUBLE_LOW (andop);
9619 if (HOST_BITS_PER_WIDE_INT < 64)
9621 HOST_WIDE_INT high, shift_mask_high;
9623 high = CONST_DOUBLE_HIGH (andop);
9627 shift_mask_high = ~0;
9628 if (INTVAL (shiftop) > 32)
9629 shift_mask_high <<= INTVAL (shiftop) - 32;
9633 if ((lsb & shift_mask_high) == 0)
9636 return high == -lsb;
9642 shift_mask_low = ~0;
9643 shift_mask_low <<= INTVAL (shiftop);
9647 if ((lsb & shift_mask_low) == 0)
9650 return low == -lsb && lsb != 1;
9656 /* Return 1 if operands will generate a valid arguments to rlwimi
9657 instruction for insert with right shift in 64-bit mode. The mask may
9658 not start on the first bit or stop on the last bit because wrap-around
9659 effects of instruction do not correspond to semantics of RTL insn. */
9662 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9664 if (INTVAL (startop) < 64
9665 && INTVAL (startop) > 32
9666 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9667 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9668 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9669 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9670 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9676 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9677 for lfq and stfq insns iff the registers are hard registers. */
9680 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9682 /* We might have been passed a SUBREG. */
9683 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9686 /* We might have been passed non floating point registers. */
9687 if (!FP_REGNO_P (REGNO (reg1))
9688 || !FP_REGNO_P (REGNO (reg2)))
9691 return (REGNO (reg1) == REGNO (reg2) - 1);
9694 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9695 addr1 and addr2 must be in consecutive memory locations
9696 (addr2 == addr1 + 8). */
9699 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9702 unsigned int reg1, reg2;
9703 int offset1, offset2;
9705 /* The mems cannot be volatile. */
9706 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9709 addr1 = XEXP (mem1, 0);
9710 addr2 = XEXP (mem2, 0);
9712 /* Extract an offset (if used) from the first addr. */
9713 if (GET_CODE (addr1) == PLUS)
9715 /* If not a REG, return zero. */
9716 if (GET_CODE (XEXP (addr1, 0)) != REG)
9720 reg1 = REGNO (XEXP (addr1, 0));
9721 /* The offset must be constant! */
9722 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9724 offset1 = INTVAL (XEXP (addr1, 1));
9727 else if (GET_CODE (addr1) != REG)
9731 reg1 = REGNO (addr1);
9732 /* This was a simple (mem (reg)) expression. Offset is 0. */
9736 /* And now for the second addr. */
9737 if (GET_CODE (addr2) == PLUS)
9739 /* If not a REG, return zero. */
9740 if (GET_CODE (XEXP (addr2, 0)) != REG)
9744 reg2 = REGNO (XEXP (addr2, 0));
9745 /* The offset must be constant. */
9746 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9748 offset2 = INTVAL (XEXP (addr2, 1));
9751 else if (GET_CODE (addr2) != REG)
9755 reg2 = REGNO (addr2);
9756 /* This was a simple (mem (reg)) expression. Offset is 0. */
9760 /* Both of these must have the same base register. */
9764 /* The offset for the second addr must be 8 more than the first addr. */
9765 if (offset2 != offset1 + 8)
9768 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9773 /* Return the register class of a scratch register needed to copy IN into
9774 or out of a register in CLASS in MODE. If it can be done directly,
9775 NO_REGS is returned. */
9778 rs6000_secondary_reload_class (enum reg_class class,
9779 enum machine_mode mode ATTRIBUTE_UNUSED,
9784 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9786 && MACHOPIC_INDIRECT
9790 /* We cannot copy a symbolic operand directly into anything
9791 other than BASE_REGS for TARGET_ELF. So indicate that a
9792 register from BASE_REGS is needed as an intermediate
9795 On Darwin, pic addresses require a load from memory, which
9796 needs a base register. */
9797 if (class != BASE_REGS
9798 && (GET_CODE (in) == SYMBOL_REF
9799 || GET_CODE (in) == HIGH
9800 || GET_CODE (in) == LABEL_REF
9801 || GET_CODE (in) == CONST))
9805 if (GET_CODE (in) == REG)
9808 if (regno >= FIRST_PSEUDO_REGISTER)
9810 regno = true_regnum (in);
9811 if (regno >= FIRST_PSEUDO_REGISTER)
9815 else if (GET_CODE (in) == SUBREG)
9817 regno = true_regnum (in);
9818 if (regno >= FIRST_PSEUDO_REGISTER)
9824 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9826 if (class == GENERAL_REGS || class == BASE_REGS
9827 || (regno >= 0 && INT_REGNO_P (regno)))
9830 /* Constants, memory, and FP registers can go into FP registers. */
9831 if ((regno == -1 || FP_REGNO_P (regno))
9832 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9835 /* Memory, and AltiVec registers can go into AltiVec registers. */
9836 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9837 && class == ALTIVEC_REGS)
9840 /* We can copy among the CR registers. */
9841 if ((class == CR_REGS || class == CR0_REGS)
9842 && regno >= 0 && CR_REGNO_P (regno))
9845 /* Otherwise, we need GENERAL_REGS. */
9846 return GENERAL_REGS;
9849 /* Given a comparison operation, return the bit number in CCR to test. We
9850 know this is a valid comparison.
9852 SCC_P is 1 if this is for an scc. That means that %D will have been
9853 used instead of %C, so the bits will be in different places.
9855 Return -1 if OP isn't a valid comparison for some reason. */
9858 ccr_bit (rtx op, int scc_p)
9860 enum rtx_code code = GET_CODE (op);
9861 enum machine_mode cc_mode;
9866 if (!COMPARISON_P (op))
9871 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9873 cc_mode = GET_MODE (reg);
9874 cc_regnum = REGNO (reg);
9875 base_bit = 4 * (cc_regnum - CR0_REGNO);
9877 validate_condition_mode (code, cc_mode);
9879 /* When generating a sCOND operation, only positive conditions are
9882 || code == EQ || code == GT || code == LT || code == UNORDERED
9883 || code == GTU || code == LTU);
9888 return scc_p ? base_bit + 3 : base_bit + 2;
9890 return base_bit + 2;
9891 case GT: case GTU: case UNLE:
9892 return base_bit + 1;
9893 case LT: case LTU: case UNGE:
9895 case ORDERED: case UNORDERED:
9896 return base_bit + 3;
9899 /* If scc, we will have done a cror to put the bit in the
9900 unordered position. So test that bit. For integer, this is ! LT
9901 unless this is an scc insn. */
9902 return scc_p ? base_bit + 3 : base_bit;
9905 return scc_p ? base_bit + 3 : base_bit + 1;
9912 /* Return the GOT register. */
9915 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9917 /* The second flow pass currently (June 1999) can't update
9918 regs_ever_live without disturbing other parts of the compiler, so
9919 update it here to make the prolog/epilogue code happy. */
9920 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9921 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9923 current_function_uses_pic_offset_table = 1;
9925 return pic_offset_table_rtx;
9928 /* Function to init struct machine_function.
9929 This will be called, via a pointer variable,
9930 from push_function_context. */
9932 static struct machine_function *
9933 rs6000_init_machine_status (void)
9935 return ggc_alloc_cleared (sizeof (machine_function));
9938 /* These macros test for integers and extract the low-order bits. */
9940 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9941 && GET_MODE (X) == VOIDmode)
9943 #define INT_LOWPART(X) \
9944 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9950 unsigned long val = INT_LOWPART (op);
9952 /* If the high bit is zero, the value is the first 1 bit we find
9954 if ((val & 0x80000000) == 0)
9956 gcc_assert (val & 0xffffffff);
9959 while (((val <<= 1) & 0x80000000) == 0)
9964 /* If the high bit is set and the low bit is not, or the mask is all
9965 1's, the value is zero. */
9966 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9969 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9972 while (((val >>= 1) & 1) != 0)
9982 unsigned long val = INT_LOWPART (op);
9984 /* If the low bit is zero, the value is the first 1 bit we find from
9988 gcc_assert (val & 0xffffffff);
9991 while (((val >>= 1) & 1) == 0)
9997 /* If the low bit is set and the high bit is not, or the mask is all
9998 1's, the value is 31. */
9999 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10002 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10005 while (((val <<= 1) & 0x80000000) != 0)
10011 /* Locate some local-dynamic symbol still in use by this function
10012 so that we can print its name in some tls_ld pattern. */
10014 static const char *
10015 rs6000_get_some_local_dynamic_name (void)
10019 if (cfun->machine->some_ld_name)
10020 return cfun->machine->some_ld_name;
10022 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10024 && for_each_rtx (&PATTERN (insn),
10025 rs6000_get_some_local_dynamic_name_1, 0))
10026 return cfun->machine->some_ld_name;
10028 gcc_unreachable ();
10031 /* Helper function for rs6000_get_some_local_dynamic_name. */
10034 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10038 if (GET_CODE (x) == SYMBOL_REF)
10040 const char *str = XSTR (x, 0);
10041 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10043 cfun->machine->some_ld_name = str;
10051 /* Write out a function code label. */
10054 rs6000_output_function_entry (FILE *file, const char *fname)
10056 if (fname[0] != '.')
10058 switch (DEFAULT_ABI)
10061 gcc_unreachable ();
10067 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10076 RS6000_OUTPUT_BASENAME (file, fname);
10078 assemble_name (file, fname);
10081 /* Print an operand. Recognize special options, documented below. */
10084 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10085 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10087 #define SMALL_DATA_RELOC "sda21"
10088 #define SMALL_DATA_REG 0
10092 print_operand (FILE *file, rtx x, int code)
10096 unsigned HOST_WIDE_INT uval;
10101 /* Write out an instruction after the call which may be replaced
10102 with glue code by the loader. This depends on the AIX version. */
10103 asm_fprintf (file, RS6000_CALL_GLUE);
10106 /* %a is output_address. */
10109 /* If X is a constant integer whose low-order 5 bits are zero,
10110 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10111 in the AIX assembler where "sri" with a zero shift count
10112 writes a trash instruction. */
10113 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10120 /* If constant, low-order 16 bits of constant, unsigned.
10121 Otherwise, write normally. */
10123 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10125 print_operand (file, x, 0);
10129 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10130 for 64-bit mask direction. */
10131 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10134 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10138 /* X is a CR register. Print the number of the GT bit of the CR. */
10139 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10140 output_operand_lossage ("invalid %%E value");
10142 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10146 /* Like 'J' but get to the EQ bit. */
10147 gcc_assert (GET_CODE (x) == REG);
10149 /* Bit 1 is EQ bit. */
10150 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10152 fprintf (file, "%d", i);
10156 /* X is a CR register. Print the number of the EQ bit of the CR */
10157 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10158 output_operand_lossage ("invalid %%E value");
10160 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10164 /* X is a CR register. Print the shift count needed to move it
10165 to the high-order four bits. */
10166 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10167 output_operand_lossage ("invalid %%f value");
10169 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10173 /* Similar, but print the count for the rotate in the opposite
10175 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10176 output_operand_lossage ("invalid %%F value");
10178 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10182 /* X is a constant integer. If it is negative, print "m",
10183 otherwise print "z". This is to make an aze or ame insn. */
10184 if (GET_CODE (x) != CONST_INT)
10185 output_operand_lossage ("invalid %%G value");
10186 else if (INTVAL (x) >= 0)
10193 /* If constant, output low-order five bits. Otherwise, write
10196 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10198 print_operand (file, x, 0);
10202 /* If constant, output low-order six bits. Otherwise, write
10205 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10207 print_operand (file, x, 0);
10211 /* Print `i' if this is a constant, else nothing. */
10217 /* Write the bit number in CCR for jump. */
10218 i = ccr_bit (x, 0);
10220 output_operand_lossage ("invalid %%j code");
10222 fprintf (file, "%d", i);
10226 /* Similar, but add one for shift count in rlinm for scc and pass
10227 scc flag to `ccr_bit'. */
10228 i = ccr_bit (x, 1);
10230 output_operand_lossage ("invalid %%J code");
10232 /* If we want bit 31, write a shift count of zero, not 32. */
10233 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10237 /* X must be a constant. Write the 1's complement of the
10240 output_operand_lossage ("invalid %%k value");
10242 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10246 /* X must be a symbolic constant on ELF. Write an
10247 expression suitable for an 'addi' that adds in the low 16
10248 bits of the MEM. */
10249 if (GET_CODE (x) != CONST)
10251 print_operand_address (file, x);
10252 fputs ("@l", file);
10256 if (GET_CODE (XEXP (x, 0)) != PLUS
10257 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10258 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10259 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10260 output_operand_lossage ("invalid %%K value");
10261 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10262 fputs ("@l", file);
10263 /* For GNU as, there must be a non-alphanumeric character
10264 between 'l' and the number. The '-' is added by
10265 print_operand() already. */
10266 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10268 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10272 /* %l is output_asm_label. */
10275 /* Write second word of DImode or DFmode reference. Works on register
10276 or non-indexed memory only. */
10277 if (GET_CODE (x) == REG)
10278 fputs (reg_names[REGNO (x) + 1], file);
10279 else if (GET_CODE (x) == MEM)
10281 /* Handle possible auto-increment. Since it is pre-increment and
10282 we have already done it, we can just use an offset of word. */
10283 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10284 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10285 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10288 output_address (XEXP (adjust_address_nv (x, SImode,
10292 if (small_data_operand (x, GET_MODE (x)))
10293 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10294 reg_names[SMALL_DATA_REG]);
10299 /* MB value for a mask operand. */
10300 if (! mask_operand (x, SImode))
10301 output_operand_lossage ("invalid %%m value");
10303 fprintf (file, "%d", extract_MB (x));
10307 /* ME value for a mask operand. */
10308 if (! mask_operand (x, SImode))
10309 output_operand_lossage ("invalid %%M value");
10311 fprintf (file, "%d", extract_ME (x));
10314 /* %n outputs the negative of its operand. */
10317 /* Write the number of elements in the vector times 4. */
10318 if (GET_CODE (x) != PARALLEL)
10319 output_operand_lossage ("invalid %%N value");
10321 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10325 /* Similar, but subtract 1 first. */
10326 if (GET_CODE (x) != PARALLEL)
10327 output_operand_lossage ("invalid %%O value");
10329 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10333 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10335 || INT_LOWPART (x) < 0
10336 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10337 output_operand_lossage ("invalid %%p value");
10339 fprintf (file, "%d", i);
10343 /* The operand must be an indirect memory reference. The result
10344 is the register name. */
10345 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10346 || REGNO (XEXP (x, 0)) >= 32)
10347 output_operand_lossage ("invalid %%P value");
10349 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10353 /* This outputs the logical code corresponding to a boolean
10354 expression. The expression may have one or both operands
10355 negated (if one, only the first one). For condition register
10356 logical operations, it will also treat the negated
10357 CR codes as NOTs, but not handle NOTs of them. */
10359 const char *const *t = 0;
10361 enum rtx_code code = GET_CODE (x);
10362 static const char * const tbl[3][3] = {
10363 { "and", "andc", "nor" },
10364 { "or", "orc", "nand" },
10365 { "xor", "eqv", "xor" } };
10369 else if (code == IOR)
10371 else if (code == XOR)
10374 output_operand_lossage ("invalid %%q value");
10376 if (GET_CODE (XEXP (x, 0)) != NOT)
10380 if (GET_CODE (XEXP (x, 1)) == NOT)
10398 /* X is a CR register. Print the mask for `mtcrf'. */
10399 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10400 output_operand_lossage ("invalid %%R value");
10402 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10406 /* Low 5 bits of 32 - value */
10408 output_operand_lossage ("invalid %%s value");
10410 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10414 /* PowerPC64 mask position. All 0's is excluded.
10415 CONST_INT 32-bit mask is considered sign-extended so any
10416 transition must occur within the CONST_INT, not on the boundary. */
10417 if (! mask64_operand (x, DImode))
10418 output_operand_lossage ("invalid %%S value");
10420 uval = INT_LOWPART (x);
10422 if (uval & 1) /* Clear Left */
10424 #if HOST_BITS_PER_WIDE_INT > 64
10425 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10429 else /* Clear Right */
10432 #if HOST_BITS_PER_WIDE_INT > 64
10433 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10439 gcc_assert (i >= 0);
10440 fprintf (file, "%d", i);
10444 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10445 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10447 /* Bit 3 is OV bit. */
10448 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10450 /* If we want bit 31, write a shift count of zero, not 32. */
10451 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10455 /* Print the symbolic name of a branch target register. */
10456 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10457 && REGNO (x) != COUNT_REGISTER_REGNUM))
10458 output_operand_lossage ("invalid %%T value");
10459 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10460 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10462 fputs ("ctr", file);
10466 /* High-order 16 bits of constant for use in unsigned operand. */
10468 output_operand_lossage ("invalid %%u value");
10470 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10471 (INT_LOWPART (x) >> 16) & 0xffff);
10475 /* High-order 16 bits of constant for use in signed operand. */
10477 output_operand_lossage ("invalid %%v value");
10479 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10480 (INT_LOWPART (x) >> 16) & 0xffff);
10484 /* Print `u' if this has an auto-increment or auto-decrement. */
10485 if (GET_CODE (x) == MEM
10486 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10487 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10492 /* Print the trap code for this operand. */
10493 switch (GET_CODE (x))
10496 fputs ("eq", file); /* 4 */
10499 fputs ("ne", file); /* 24 */
10502 fputs ("lt", file); /* 16 */
10505 fputs ("le", file); /* 20 */
10508 fputs ("gt", file); /* 8 */
10511 fputs ("ge", file); /* 12 */
10514 fputs ("llt", file); /* 2 */
10517 fputs ("lle", file); /* 6 */
10520 fputs ("lgt", file); /* 1 */
10523 fputs ("lge", file); /* 5 */
10526 gcc_unreachable ();
10531 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10534 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10535 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10537 print_operand (file, x, 0);
10541 /* MB value for a PowerPC64 rldic operand. */
10542 val = (GET_CODE (x) == CONST_INT
10543 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10548 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10549 if ((val <<= 1) < 0)
10552 #if HOST_BITS_PER_WIDE_INT == 32
10553 if (GET_CODE (x) == CONST_INT && i >= 0)
10554 i += 32; /* zero-extend high-part was all 0's */
10555 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10557 val = CONST_DOUBLE_LOW (x);
10563 for ( ; i < 64; i++)
10564 if ((val <<= 1) < 0)
10569 fprintf (file, "%d", i + 1);
10573 if (GET_CODE (x) == MEM
10574 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10579 /* Like 'L', for third word of TImode */
10580 if (GET_CODE (x) == REG)
10581 fputs (reg_names[REGNO (x) + 2], file);
10582 else if (GET_CODE (x) == MEM)
10584 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10585 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10586 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10588 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10589 if (small_data_operand (x, GET_MODE (x)))
10590 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10591 reg_names[SMALL_DATA_REG]);
10596 /* X is a SYMBOL_REF. Write out the name preceded by a
10597 period and without any trailing data in brackets. Used for function
10598 names. If we are configured for System V (or the embedded ABI) on
10599 the PowerPC, do not emit the period, since those systems do not use
10600 TOCs and the like. */
10601 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10603 /* Mark the decl as referenced so that cgraph will output the
10605 if (SYMBOL_REF_DECL (x))
10606 mark_decl_referenced (SYMBOL_REF_DECL (x));
10608 /* For macho, check to see if we need a stub. */
10611 const char *name = XSTR (x, 0);
10613 if (MACHOPIC_INDIRECT
10614 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10615 name = machopic_indirection_name (x, /*stub_p=*/true);
10617 assemble_name (file, name);
10619 else if (!DOT_SYMBOLS)
10620 assemble_name (file, XSTR (x, 0));
10622 rs6000_output_function_entry (file, XSTR (x, 0));
10626 /* Like 'L', for last word of TImode. */
10627 if (GET_CODE (x) == REG)
10628 fputs (reg_names[REGNO (x) + 3], file);
10629 else if (GET_CODE (x) == MEM)
10631 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10632 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10633 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10635 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10636 if (small_data_operand (x, GET_MODE (x)))
10637 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10638 reg_names[SMALL_DATA_REG]);
10642 /* Print AltiVec or SPE memory operand. */
10647 gcc_assert (GET_CODE (x) == MEM);
10653 /* Handle [reg]. */
10654 if (GET_CODE (tmp) == REG)
10656 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10659 /* Handle [reg+UIMM]. */
10660 else if (GET_CODE (tmp) == PLUS &&
10661 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10665 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10667 x = INTVAL (XEXP (tmp, 1));
10668 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10672 /* Fall through. Must be [reg+reg]. */
10675 && GET_CODE (tmp) == AND
10676 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10677 && INTVAL (XEXP (tmp, 1)) == -16)
10678 tmp = XEXP (tmp, 0);
10679 if (GET_CODE (tmp) == REG)
10680 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10683 gcc_assert (GET_CODE (tmp) == PLUS
10684 && REG_P (XEXP (tmp, 0))
10685 && REG_P (XEXP (tmp, 1)));
10687 if (REGNO (XEXP (tmp, 0)) == 0)
10688 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10689 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10691 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10692 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10698 if (GET_CODE (x) == REG)
10699 fprintf (file, "%s", reg_names[REGNO (x)]);
10700 else if (GET_CODE (x) == MEM)
10702 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10703 know the width from the mode. */
10704 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10705 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10706 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10707 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10708 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10709 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10711 output_address (XEXP (x, 0));
10714 output_addr_const (file, x);
10718 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10722 output_operand_lossage ("invalid %%xn code");
10726 /* Print the address of an operand. */
10729 print_operand_address (FILE *file, rtx x)
10731 if (GET_CODE (x) == REG)
10732 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10733 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10734 || GET_CODE (x) == LABEL_REF)
10736 output_addr_const (file, x);
10737 if (small_data_operand (x, GET_MODE (x)))
10738 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10739 reg_names[SMALL_DATA_REG]);
10741 gcc_assert (!TARGET_TOC);
10743 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10745 gcc_assert (REG_P (XEXP (x, 0)));
10746 if (REGNO (XEXP (x, 0)) == 0)
10747 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10748 reg_names[ REGNO (XEXP (x, 0)) ]);
10750 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10751 reg_names[ REGNO (XEXP (x, 1)) ]);
10753 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10754 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10755 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10757 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10758 && CONSTANT_P (XEXP (x, 1)))
10760 output_addr_const (file, XEXP (x, 1));
10761 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10765 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10766 && CONSTANT_P (XEXP (x, 1)))
10768 fprintf (file, "lo16(");
10769 output_addr_const (file, XEXP (x, 1));
10770 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10773 else if (legitimate_constant_pool_address_p (x))
10775 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10777 rtx contains_minus = XEXP (x, 1);
10781 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10782 turn it into (sym) for output_addr_const. */
10783 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10784 contains_minus = XEXP (contains_minus, 0);
10786 minus = XEXP (contains_minus, 0);
10787 symref = XEXP (minus, 0);
10788 XEXP (contains_minus, 0) = symref;
10793 name = XSTR (symref, 0);
10794 newname = alloca (strlen (name) + sizeof ("@toc"));
10795 strcpy (newname, name);
10796 strcat (newname, "@toc");
10797 XSTR (symref, 0) = newname;
10799 output_addr_const (file, XEXP (x, 1));
10801 XSTR (symref, 0) = name;
10802 XEXP (contains_minus, 0) = minus;
10805 output_addr_const (file, XEXP (x, 1));
10807 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10810 gcc_unreachable ();
10813 /* Target hook for assembling integer objects. The PowerPC version has
10814 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10815 is defined. It also needs to handle DI-mode objects on 64-bit
10819 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10821 #ifdef RELOCATABLE_NEEDS_FIXUP
10822 /* Special handling for SI values. */
10823 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10825 static int recurse = 0;
10827 /* For -mrelocatable, we mark all addresses that need to be fixed up
10828 in the .fixup section. */
10829 if (TARGET_RELOCATABLE
10830 && in_section != toc_section
10831 && in_section != text_section
10832 && unlikely_text_section_p (in_section)
10834 && GET_CODE (x) != CONST_INT
10835 && GET_CODE (x) != CONST_DOUBLE
10841 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10843 ASM_OUTPUT_LABEL (asm_out_file, buf);
10844 fprintf (asm_out_file, "\t.long\t(");
10845 output_addr_const (asm_out_file, x);
10846 fprintf (asm_out_file, ")@fixup\n");
10847 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10848 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10849 fprintf (asm_out_file, "\t.long\t");
10850 assemble_name (asm_out_file, buf);
10851 fprintf (asm_out_file, "\n\t.previous\n");
10855 /* Remove initial .'s to turn a -mcall-aixdesc function
10856 address into the address of the descriptor, not the function
10858 else if (GET_CODE (x) == SYMBOL_REF
10859 && XSTR (x, 0)[0] == '.'
10860 && DEFAULT_ABI == ABI_AIX)
10862 const char *name = XSTR (x, 0);
10863 while (*name == '.')
10866 fprintf (asm_out_file, "\t.long\t%s\n", name);
10870 #endif /* RELOCATABLE_NEEDS_FIXUP */
10871 return default_assemble_integer (x, size, aligned_p);
10874 #ifdef HAVE_GAS_HIDDEN
10875 /* Emit an assembler directive to set symbol visibility for DECL to
10876 VISIBILITY_TYPE. */
10879 rs6000_assemble_visibility (tree decl, int vis)
10881 /* Functions need to have their entry point symbol visibility set as
10882 well as their descriptor symbol visibility. */
10883 if (DEFAULT_ABI == ABI_AIX
10885 && TREE_CODE (decl) == FUNCTION_DECL)
10887 static const char * const visibility_types[] = {
10888 NULL, "internal", "hidden", "protected"
10891 const char *name, *type;
10893 name = ((* targetm.strip_name_encoding)
10894 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10895 type = visibility_types[vis];
10897 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10898 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10901 default_assemble_visibility (decl, vis);
10906 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10908 /* Reversal of FP compares takes care -- an ordered compare
10909 becomes an unordered compare and vice versa. */
10910 if (mode == CCFPmode
10911 && (!flag_finite_math_only
10912 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10913 || code == UNEQ || code == LTGT))
10914 return reverse_condition_maybe_unordered (code);
10916 return reverse_condition (code);
10919 /* Generate a compare for CODE. Return a brand-new rtx that
10920 represents the result of the compare. */
10923 rs6000_generate_compare (enum rtx_code code)
10925 enum machine_mode comp_mode;
10926 rtx compare_result;
10928 if (rs6000_compare_fp_p)
10929 comp_mode = CCFPmode;
10930 else if (code == GTU || code == LTU
10931 || code == GEU || code == LEU)
10932 comp_mode = CCUNSmode;
10933 else if ((code == EQ || code == NE)
10934 && GET_CODE (rs6000_compare_op0) == SUBREG
10935 && GET_CODE (rs6000_compare_op1) == SUBREG
10936 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10937 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10938 /* These are unsigned values, perhaps there will be a later
10939 ordering compare that can be shared with this one.
10940 Unfortunately we cannot detect the signedness of the operands
10941 for non-subregs. */
10942 comp_mode = CCUNSmode;
10944 comp_mode = CCmode;
10946 /* First, the compare. */
10947 compare_result = gen_reg_rtx (comp_mode);
10949 /* SPE FP compare instructions on the GPRs. Yuck! */
10950 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10951 && rs6000_compare_fp_p)
10953 rtx cmp, or_result, compare_result2;
10954 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10956 if (op_mode == VOIDmode)
10957 op_mode = GET_MODE (rs6000_compare_op1);
10959 /* Note: The E500 comparison instructions set the GT bit (x +
10960 1), on success. This explains the mess. */
10964 case EQ: case UNEQ: case NE: case LTGT:
10968 cmp = flag_unsafe_math_optimizations
10969 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10970 rs6000_compare_op1)
10971 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10972 rs6000_compare_op1);
10976 cmp = flag_unsafe_math_optimizations
10977 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10978 rs6000_compare_op1)
10979 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10980 rs6000_compare_op1);
10984 gcc_unreachable ();
10988 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10992 cmp = flag_unsafe_math_optimizations
10993 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10994 rs6000_compare_op1)
10995 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10996 rs6000_compare_op1);
11000 cmp = flag_unsafe_math_optimizations
11001 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11002 rs6000_compare_op1)
11003 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11004 rs6000_compare_op1);
11008 gcc_unreachable ();
11012 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11016 cmp = flag_unsafe_math_optimizations
11017 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11018 rs6000_compare_op1)
11019 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11020 rs6000_compare_op1);
11024 cmp = flag_unsafe_math_optimizations
11025 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11026 rs6000_compare_op1)
11027 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11028 rs6000_compare_op1);
11032 gcc_unreachable ();
11036 gcc_unreachable ();
11039 /* Synthesize LE and GE from LT/GT || EQ. */
11040 if (code == LE || code == GE || code == LEU || code == GEU)
11046 case LE: code = LT; break;
11047 case GE: code = GT; break;
11048 case LEU: code = LT; break;
11049 case GEU: code = GT; break;
11050 default: gcc_unreachable ();
11053 compare_result2 = gen_reg_rtx (CCFPmode);
11059 cmp = flag_unsafe_math_optimizations
11060 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11061 rs6000_compare_op1)
11062 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11063 rs6000_compare_op1);
11067 cmp = flag_unsafe_math_optimizations
11068 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11069 rs6000_compare_op1)
11070 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11071 rs6000_compare_op1);
11075 gcc_unreachable ();
11079 /* OR them together. */
11080 or_result = gen_reg_rtx (CCFPmode);
11081 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11083 compare_result = or_result;
11088 if (code == NE || code == LTGT)
11098 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11099 CLOBBERs to match cmptf_internal2 pattern. */
11100 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11101 && GET_MODE (rs6000_compare_op0) == TFmode
11102 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11103 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11104 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11106 gen_rtx_SET (VOIDmode,
11108 gen_rtx_COMPARE (comp_mode,
11109 rs6000_compare_op0,
11110 rs6000_compare_op1)),
11111 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11112 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11113 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11114 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11115 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11116 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11117 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11118 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11119 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11120 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11122 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11123 comp_mode = CCEQmode;
11124 compare_result = gen_reg_rtx (CCEQmode);
11126 emit_insn (gen_stack_protect_testdi (compare_result,
11127 rs6000_compare_op0, op1));
11129 emit_insn (gen_stack_protect_testsi (compare_result,
11130 rs6000_compare_op0, op1));
11133 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11134 gen_rtx_COMPARE (comp_mode,
11135 rs6000_compare_op0,
11136 rs6000_compare_op1)));
11139 /* Some kinds of FP comparisons need an OR operation;
11140 under flag_finite_math_only we don't bother. */
11141 if (rs6000_compare_fp_p
11142 && !flag_finite_math_only
11143 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11144 && (code == LE || code == GE
11145 || code == UNEQ || code == LTGT
11146 || code == UNGT || code == UNLT))
11148 enum rtx_code or1, or2;
11149 rtx or1_rtx, or2_rtx, compare2_rtx;
11150 rtx or_result = gen_reg_rtx (CCEQmode);
11154 case LE: or1 = LT; or2 = EQ; break;
11155 case GE: or1 = GT; or2 = EQ; break;
11156 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11157 case LTGT: or1 = LT; or2 = GT; break;
11158 case UNGT: or1 = UNORDERED; or2 = GT; break;
11159 case UNLT: or1 = UNORDERED; or2 = LT; break;
11160 default: gcc_unreachable ();
11162 validate_condition_mode (or1, comp_mode);
11163 validate_condition_mode (or2, comp_mode);
11164 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11165 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11166 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11167 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11169 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11171 compare_result = or_result;
11175 validate_condition_mode (code, GET_MODE (compare_result));
11177 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11181 /* Emit the RTL for an sCOND pattern. */
11184 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11187 enum machine_mode op_mode;
11188 enum rtx_code cond_code;
11190 condition_rtx = rs6000_generate_compare (code);
11191 cond_code = GET_CODE (condition_rtx);
11193 if (TARGET_E500 && rs6000_compare_fp_p
11194 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11198 PUT_MODE (condition_rtx, SImode);
11199 t = XEXP (condition_rtx, 0);
11201 gcc_assert (cond_code == NE || cond_code == EQ);
11203 if (cond_code == NE)
11204 emit_insn (gen_e500_flip_gt_bit (t, t));
11206 emit_insn (gen_move_from_CR_gt_bit (result, t));
11210 if (cond_code == NE
11211 || cond_code == GE || cond_code == LE
11212 || cond_code == GEU || cond_code == LEU
11213 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11215 rtx not_result = gen_reg_rtx (CCEQmode);
11216 rtx not_op, rev_cond_rtx;
11217 enum machine_mode cc_mode;
11219 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11221 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11222 SImode, XEXP (condition_rtx, 0), const0_rtx);
11223 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11224 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11225 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11228 op_mode = GET_MODE (rs6000_compare_op0);
11229 if (op_mode == VOIDmode)
11230 op_mode = GET_MODE (rs6000_compare_op1);
11232 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11234 PUT_MODE (condition_rtx, DImode);
11235 convert_move (result, condition_rtx, 0);
11239 PUT_MODE (condition_rtx, SImode);
11240 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11244 /* Emit a branch of kind CODE to location LOC. */
11247 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11249 rtx condition_rtx, loc_ref;
11251 condition_rtx = rs6000_generate_compare (code);
11252 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11253 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11254 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11255 loc_ref, pc_rtx)));
11258 /* Return the string to output a conditional branch to LABEL, which is
11259 the operand number of the label, or -1 if the branch is really a
11260 conditional return.
11262 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11263 condition code register and its mode specifies what kind of
11264 comparison we made.
11266 REVERSED is nonzero if we should reverse the sense of the comparison.
11268 INSN is the insn. */
11271 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11273 static char string[64];
11274 enum rtx_code code = GET_CODE (op);
11275 rtx cc_reg = XEXP (op, 0);
11276 enum machine_mode mode = GET_MODE (cc_reg);
11277 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11278 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11279 int really_reversed = reversed ^ need_longbranch;
11285 validate_condition_mode (code, mode);
11287 /* Work out which way this really branches. We could use
11288 reverse_condition_maybe_unordered here always but this
11289 makes the resulting assembler clearer. */
11290 if (really_reversed)
11292 /* Reversal of FP compares takes care -- an ordered compare
11293 becomes an unordered compare and vice versa. */
11294 if (mode == CCFPmode)
11295 code = reverse_condition_maybe_unordered (code);
11297 code = reverse_condition (code);
11300 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11302 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11307 /* Opposite of GT. */
11316 gcc_unreachable ();
11322 /* Not all of these are actually distinct opcodes, but
11323 we distinguish them for clarity of the resulting assembler. */
11324 case NE: case LTGT:
11325 ccode = "ne"; break;
11326 case EQ: case UNEQ:
11327 ccode = "eq"; break;
11329 ccode = "ge"; break;
11330 case GT: case GTU: case UNGT:
11331 ccode = "gt"; break;
11333 ccode = "le"; break;
11334 case LT: case LTU: case UNLT:
11335 ccode = "lt"; break;
11336 case UNORDERED: ccode = "un"; break;
11337 case ORDERED: ccode = "nu"; break;
11338 case UNGE: ccode = "nl"; break;
11339 case UNLE: ccode = "ng"; break;
11341 gcc_unreachable ();
11344 /* Maybe we have a guess as to how likely the branch is.
11345 The old mnemonics don't have a way to specify this information. */
11347 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11348 if (note != NULL_RTX)
11350 /* PROB is the difference from 50%. */
11351 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11353 /* Only hint for highly probable/improbable branches on newer
11354 cpus as static prediction overrides processor dynamic
11355 prediction. For older cpus we may as well always hint, but
11356 assume not taken for branches that are very close to 50% as a
11357 mispredicted taken branch is more expensive than a
11358 mispredicted not-taken branch. */
11359 if (rs6000_always_hint
11360 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11362 if (abs (prob) > REG_BR_PROB_BASE / 20
11363 && ((prob > 0) ^ need_longbranch))
11371 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11373 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11375 /* We need to escape any '%' characters in the reg_names string.
11376 Assume they'd only be the first character.... */
11377 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11379 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11383 /* If the branch distance was too far, we may have to use an
11384 unconditional branch to go the distance. */
11385 if (need_longbranch)
11386 s += sprintf (s, ",$+8\n\tb %s", label);
11388 s += sprintf (s, ",%s", label);
11394 /* Return the string to flip the GT bit on a CR. */
11396 output_e500_flip_gt_bit (rtx dst, rtx src)
11398 static char string[64];
11401 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11402 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11405 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11406 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11408 sprintf (string, "crnot %d,%d", a, b);
11412 /* Return insn index for the vector compare instruction for given CODE,
11413 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11417 get_vec_cmp_insn (enum rtx_code code,
11418 enum machine_mode dest_mode,
11419 enum machine_mode op_mode)
11421 if (!TARGET_ALTIVEC)
11422 return INSN_NOT_AVAILABLE;
11427 if (dest_mode == V16QImode && op_mode == V16QImode)
11428 return UNSPEC_VCMPEQUB;
11429 if (dest_mode == V8HImode && op_mode == V8HImode)
11430 return UNSPEC_VCMPEQUH;
11431 if (dest_mode == V4SImode && op_mode == V4SImode)
11432 return UNSPEC_VCMPEQUW;
11433 if (dest_mode == V4SImode && op_mode == V4SFmode)
11434 return UNSPEC_VCMPEQFP;
11437 if (dest_mode == V4SImode && op_mode == V4SFmode)
11438 return UNSPEC_VCMPGEFP;
11440 if (dest_mode == V16QImode && op_mode == V16QImode)
11441 return UNSPEC_VCMPGTSB;
11442 if (dest_mode == V8HImode && op_mode == V8HImode)
11443 return UNSPEC_VCMPGTSH;
11444 if (dest_mode == V4SImode && op_mode == V4SImode)
11445 return UNSPEC_VCMPGTSW;
11446 if (dest_mode == V4SImode && op_mode == V4SFmode)
11447 return UNSPEC_VCMPGTFP;
11450 if (dest_mode == V16QImode && op_mode == V16QImode)
11451 return UNSPEC_VCMPGTUB;
11452 if (dest_mode == V8HImode && op_mode == V8HImode)
11453 return UNSPEC_VCMPGTUH;
11454 if (dest_mode == V4SImode && op_mode == V4SImode)
11455 return UNSPEC_VCMPGTUW;
11460 return INSN_NOT_AVAILABLE;
11463 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11464 DMODE is expected destination mode. This is a recursive function. */
11467 rs6000_emit_vector_compare (enum rtx_code rcode,
11469 enum machine_mode dmode)
11473 enum machine_mode dest_mode;
11474 enum machine_mode op_mode = GET_MODE (op1);
11476 gcc_assert (TARGET_ALTIVEC);
11477 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11479 /* Floating point vector compare instructions uses destination V4SImode.
11480 Move destination to appropriate mode later. */
11481 if (dmode == V4SFmode)
11482 dest_mode = V4SImode;
11486 mask = gen_reg_rtx (dest_mode);
11487 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11489 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11491 bool swap_operands = false;
11492 bool try_again = false;
11497 swap_operands = true;
11502 swap_operands = true;
11506 /* Treat A != B as ~(A==B). */
11508 enum insn_code nor_code;
11509 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11512 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11513 gcc_assert (nor_code != CODE_FOR_nothing);
11514 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11516 if (dmode != dest_mode)
11518 rtx temp = gen_reg_rtx (dest_mode);
11519 convert_move (temp, mask, 0);
11529 /* Try GT/GTU/LT/LTU OR EQ */
11532 enum insn_code ior_code;
11533 enum rtx_code new_code;
11554 gcc_unreachable ();
11557 c_rtx = rs6000_emit_vector_compare (new_code,
11558 op0, op1, dest_mode);
11559 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11562 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11563 gcc_assert (ior_code != CODE_FOR_nothing);
11564 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11565 if (dmode != dest_mode)
11567 rtx temp = gen_reg_rtx (dest_mode);
11568 convert_move (temp, mask, 0);
11575 gcc_unreachable ();
11580 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11581 /* You only get two chances. */
11582 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11594 emit_insn (gen_rtx_SET (VOIDmode, mask,
11595 gen_rtx_UNSPEC (dest_mode,
11596 gen_rtvec (2, op0, op1),
11598 if (dmode != dest_mode)
11600 rtx temp = gen_reg_rtx (dest_mode);
11601 convert_move (temp, mask, 0);
11607 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11608 valid insn doesn exist for given mode. */
11611 get_vsel_insn (enum machine_mode mode)
11616 return UNSPEC_VSEL4SI;
11619 return UNSPEC_VSEL4SF;
11622 return UNSPEC_VSEL8HI;
11625 return UNSPEC_VSEL16QI;
11628 return INSN_NOT_AVAILABLE;
11631 return INSN_NOT_AVAILABLE;
11634 /* Emit vector select insn where DEST is destination using
11635 operands OP1, OP2 and MASK. */
11638 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11641 enum machine_mode dest_mode = GET_MODE (dest);
11642 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11644 temp = gen_reg_rtx (dest_mode);
11646 /* For each vector element, select op1 when mask is 1 otherwise
11648 t = gen_rtx_SET (VOIDmode, temp,
11649 gen_rtx_UNSPEC (dest_mode,
11650 gen_rtvec (3, op2, op1, mask),
11653 emit_move_insn (dest, temp);
11657 /* Emit vector conditional expression.
11658 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11659 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11662 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11663 rtx cond, rtx cc_op0, rtx cc_op1)
11665 enum machine_mode dest_mode = GET_MODE (dest);
11666 enum rtx_code rcode = GET_CODE (cond);
11669 if (!TARGET_ALTIVEC)
11672 /* Get the vector mask for the given relational operations. */
11673 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11675 rs6000_emit_vector_select (dest, op1, op2, mask);
11680 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11681 operands of the last comparison is nonzero/true, FALSE_COND if it
11682 is zero/false. Return 0 if the hardware has no such operation. */
11685 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11687 enum rtx_code code = GET_CODE (op);
11688 rtx op0 = rs6000_compare_op0;
11689 rtx op1 = rs6000_compare_op1;
11690 REAL_VALUE_TYPE c1;
11691 enum machine_mode compare_mode = GET_MODE (op0);
11692 enum machine_mode result_mode = GET_MODE (dest);
11694 bool is_against_zero;
11696 /* These modes should always match. */
11697 if (GET_MODE (op1) != compare_mode
11698 /* In the isel case however, we can use a compare immediate, so
11699 op1 may be a small constant. */
11700 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11702 if (GET_MODE (true_cond) != result_mode)
11704 if (GET_MODE (false_cond) != result_mode)
11707 /* First, work out if the hardware can do this at all, or
11708 if it's too slow.... */
11709 if (! rs6000_compare_fp_p)
11712 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11715 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11716 && SCALAR_FLOAT_MODE_P (compare_mode))
11719 is_against_zero = op1 == CONST0_RTX (compare_mode);
11721 /* A floating-point subtract might overflow, underflow, or produce
11722 an inexact result, thus changing the floating-point flags, so it
11723 can't be generated if we care about that. It's safe if one side
11724 of the construct is zero, since then no subtract will be
11726 if (SCALAR_FLOAT_MODE_P (compare_mode)
11727 && flag_trapping_math && ! is_against_zero)
11730 /* Eliminate half of the comparisons by switching operands, this
11731 makes the remaining code simpler. */
11732 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11733 || code == LTGT || code == LT || code == UNLE)
11735 code = reverse_condition_maybe_unordered (code);
11737 true_cond = false_cond;
11741 /* UNEQ and LTGT take four instructions for a comparison with zero,
11742 it'll probably be faster to use a branch here too. */
11743 if (code == UNEQ && HONOR_NANS (compare_mode))
11746 if (GET_CODE (op1) == CONST_DOUBLE)
11747 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11749 /* We're going to try to implement comparisons by performing
11750 a subtract, then comparing against zero. Unfortunately,
11751 Inf - Inf is NaN which is not zero, and so if we don't
11752 know that the operand is finite and the comparison
11753 would treat EQ different to UNORDERED, we can't do it. */
11754 if (HONOR_INFINITIES (compare_mode)
11755 && code != GT && code != UNGE
11756 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11757 /* Constructs of the form (a OP b ? a : b) are safe. */
11758 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11759 || (! rtx_equal_p (op0, true_cond)
11760 && ! rtx_equal_p (op1, true_cond))))
11763 /* At this point we know we can use fsel. */
11765 /* Reduce the comparison to a comparison against zero. */
11766 if (! is_against_zero)
11768 temp = gen_reg_rtx (compare_mode);
11769 emit_insn (gen_rtx_SET (VOIDmode, temp,
11770 gen_rtx_MINUS (compare_mode, op0, op1)));
11772 op1 = CONST0_RTX (compare_mode);
11775 /* If we don't care about NaNs we can reduce some of the comparisons
11776 down to faster ones. */
11777 if (! HONOR_NANS (compare_mode))
11783 true_cond = false_cond;
11796 /* Now, reduce everything down to a GE. */
11803 temp = gen_reg_rtx (compare_mode);
11804 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11809 temp = gen_reg_rtx (compare_mode);
11810 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11815 temp = gen_reg_rtx (compare_mode);
11816 emit_insn (gen_rtx_SET (VOIDmode, temp,
11817 gen_rtx_NEG (compare_mode,
11818 gen_rtx_ABS (compare_mode, op0))));
11823 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11824 temp = gen_reg_rtx (result_mode);
11825 emit_insn (gen_rtx_SET (VOIDmode, temp,
11826 gen_rtx_IF_THEN_ELSE (result_mode,
11827 gen_rtx_GE (VOIDmode,
11829 true_cond, false_cond)));
11830 false_cond = true_cond;
11833 temp = gen_reg_rtx (compare_mode);
11834 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11839 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11840 temp = gen_reg_rtx (result_mode);
11841 emit_insn (gen_rtx_SET (VOIDmode, temp,
11842 gen_rtx_IF_THEN_ELSE (result_mode,
11843 gen_rtx_GE (VOIDmode,
11845 true_cond, false_cond)));
11846 true_cond = false_cond;
11849 temp = gen_reg_rtx (compare_mode);
11850 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11855 gcc_unreachable ();
11858 emit_insn (gen_rtx_SET (VOIDmode, dest,
11859 gen_rtx_IF_THEN_ELSE (result_mode,
11860 gen_rtx_GE (VOIDmode,
11862 true_cond, false_cond)));
11866 /* Same as above, but for ints (isel). */
11869 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11871 rtx condition_rtx, cr;
11873 /* All isel implementations thus far are 32-bits. */
11874 if (GET_MODE (rs6000_compare_op0) != SImode)
11877 /* We still have to do the compare, because isel doesn't do a
11878 compare, it just looks at the CRx bits set by a previous compare
11880 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11881 cr = XEXP (condition_rtx, 0);
11883 if (GET_MODE (cr) == CCmode)
11884 emit_insn (gen_isel_signed (dest, condition_rtx,
11885 true_cond, false_cond, cr));
11887 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11888 true_cond, false_cond, cr));
11894 output_isel (rtx *operands)
11896 enum rtx_code code;
11898 code = GET_CODE (operands[1]);
11899 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11901 PUT_CODE (operands[1], reverse_condition (code));
11902 return "isel %0,%3,%2,%j1";
11905 return "isel %0,%2,%3,%j1";
11909 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11911 enum machine_mode mode = GET_MODE (op0);
11915 if (code == SMAX || code == SMIN)
11920 if (code == SMAX || code == UMAX)
11921 target = emit_conditional_move (dest, c, op0, op1, mode,
11922 op0, op1, mode, 0);
11924 target = emit_conditional_move (dest, c, op0, op1, mode,
11925 op1, op0, mode, 0);
11926 gcc_assert (target);
11927 if (target != dest)
11928 emit_move_insn (dest, target);
11931 /* Emit instructions to perform a load-reserved/store-conditional operation.
11932 The operation performed is an atomic
11933 (set M (CODE:MODE M OP))
11934 If not NULL, BEFORE is atomically set to M before the operation, and
11935 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11936 If SYNC_P then a memory barrier is emitted before the operation.
11937 Either OP or M may be wrapped in a NOT operation. */
11940 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
11941 rtx m, rtx op, rtx before_param, rtx after_param,
11944 enum machine_mode used_mode;
11945 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
11948 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
11949 rtx shift = NULL_RTX;
11952 emit_insn (gen_memory_barrier ());
11954 if (GET_CODE (m) == NOT)
11955 used_m = XEXP (m, 0);
11959 /* If this is smaller than SImode, we'll have to use SImode with
11961 if (mode == QImode || mode == HImode)
11965 if (MEM_ALIGN (used_m) >= 32)
11968 if (BYTES_BIG_ENDIAN)
11969 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
11971 shift = GEN_INT (ishift);
11975 rtx addrSI, aligned_addr;
11976 int shift_mask = mode == QImode ? 0x18 : 0x10;
11978 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
11979 XEXP (used_m, 0)));
11980 shift = gen_reg_rtx (SImode);
11982 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
11983 GEN_INT (shift_mask)));
11984 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
11986 aligned_addr = expand_binop (Pmode, and_optab,
11988 GEN_INT (-4), NULL_RTX,
11989 1, OPTAB_LIB_WIDEN);
11990 used_m = change_address (used_m, SImode, aligned_addr);
11991 set_mem_align (used_m, 32);
11992 /* It's safe to keep the old alias set of USED_M, because
11993 the operation is atomic and only affects the original
11995 if (GET_CODE (m) == NOT)
11996 m = gen_rtx_NOT (SImode, used_m);
12001 if (GET_CODE (op) == NOT)
12003 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12004 oldop = gen_rtx_NOT (SImode, oldop);
12007 oldop = lowpart_subreg (SImode, op, mode);
12013 newop = expand_binop (SImode, and_optab,
12014 oldop, GEN_INT (imask), NULL_RTX,
12015 1, OPTAB_LIB_WIDEN);
12016 emit_insn (gen_ashlsi3 (newop, newop, shift));
12020 newop = expand_binop (SImode, ior_optab,
12021 oldop, GEN_INT (~imask), NULL_RTX,
12022 1, OPTAB_LIB_WIDEN);
12023 emit_insn (gen_rotlsi3 (newop, newop, shift));
12031 newop = expand_binop (SImode, and_optab,
12032 oldop, GEN_INT (imask), NULL_RTX,
12033 1, OPTAB_LIB_WIDEN);
12034 emit_insn (gen_ashlsi3 (newop, newop, shift));
12036 mask = gen_reg_rtx (SImode);
12037 emit_move_insn (mask, GEN_INT (imask));
12038 emit_insn (gen_ashlsi3 (mask, mask, shift));
12041 newop = gen_rtx_PLUS (SImode, m, newop);
12043 newop = gen_rtx_MINUS (SImode, m, newop);
12044 newop = gen_rtx_AND (SImode, newop, mask);
12045 newop = gen_rtx_IOR (SImode, newop,
12046 gen_rtx_AND (SImode,
12047 gen_rtx_NOT (SImode, mask),
12053 gcc_unreachable ();
12056 if (GET_CODE (m) == NOT)
12060 mask = gen_reg_rtx (SImode);
12061 emit_move_insn (mask, GEN_INT (imask));
12062 emit_insn (gen_ashlsi3 (mask, mask, shift));
12064 xorm = gen_rtx_XOR (SImode, used_m, mask);
12065 /* Depending on the value of 'op', the XOR or the operation might
12066 be able to be simplified away. */
12067 newop = simplify_gen_binary (code, SImode, xorm, newop);
12070 used_mode = SImode;
12071 before = gen_reg_rtx (used_mode);
12072 after = gen_reg_rtx (used_mode);
12077 before = before_param;
12078 after = after_param;
12080 if (before == NULL_RTX)
12081 before = gen_reg_rtx (used_mode);
12082 if (after == NULL_RTX)
12083 after = gen_reg_rtx (used_mode);
12086 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12087 && used_mode != mode)
12088 the_op = op; /* Computed above. */
12089 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12090 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12092 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12094 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12095 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12096 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12097 gen_rtx_UNSPEC (used_mode,
12098 gen_rtvec (1, the_op),
12100 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12102 if ((code == PLUS || code == MINUS) && used_mode != mode)
12103 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12104 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12106 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12107 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12109 /* Shift and mask the return values properly. */
12110 if (used_mode != mode && before_param)
12112 emit_insn (gen_lshrsi3 (before, before, shift));
12113 convert_move (before_param, before, 1);
12116 if (used_mode != mode && after_param)
12118 emit_insn (gen_lshrsi3 (after, after, shift));
12119 convert_move (after_param, after, 1);
12122 /* The previous sequence will end with a branch that's dependent on
12123 the conditional store, so placing an isync will ensure that no
12124 other instructions (especially, no load or store instructions)
12125 can start before the atomic operation completes. */
12127 emit_insn (gen_isync ());
12130 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12131 COND is true. Mark the jump as unlikely to be taken. */
12134 emit_unlikely_jump (rtx cond, rtx label)
12136 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12139 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12140 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12141 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12144 /* A subroutine of the atomic operation splitters. Emit a load-locked
12145 instruction in MODE. */
12148 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12150 rtx (*fn) (rtx, rtx) = NULL;
12151 if (mode == SImode)
12152 fn = gen_load_locked_si;
12153 else if (mode == DImode)
12154 fn = gen_load_locked_di;
12155 emit_insn (fn (reg, mem));
12158 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12159 instruction in MODE. */
12162 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12164 rtx (*fn) (rtx, rtx, rtx) = NULL;
12165 if (mode == SImode)
12166 fn = gen_store_conditional_si;
12167 else if (mode == DImode)
12168 fn = gen_store_conditional_di;
12170 /* Emit sync before stwcx. to address PPC405 Erratum. */
12171 if (PPC405_ERRATUM77)
12172 emit_insn (gen_memory_barrier ());
12174 emit_insn (fn (res, mem, val));
12177 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12178 to perform. MEM is the memory on which to operate. VAL is the second
12179 operand of the binary operator. BEFORE and AFTER are optional locations to
12180 return the value of MEM either before of after the operation. SCRATCH is
12181 a scratch register. */
12184 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12185 rtx before, rtx after, rtx scratch)
12187 enum machine_mode mode = GET_MODE (mem);
12188 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12190 emit_insn (gen_memory_barrier ());
12192 label = gen_label_rtx ();
12193 emit_label (label);
12194 label = gen_rtx_LABEL_REF (VOIDmode, label);
12196 if (before == NULL_RTX)
12198 emit_load_locked (mode, before, mem);
12201 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12202 else if (code == AND)
12203 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12205 x = gen_rtx_fmt_ee (code, mode, before, val);
12207 if (after != NULL_RTX)
12208 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12209 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12211 emit_store_conditional (mode, cond, mem, scratch);
12213 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12214 emit_unlikely_jump (x, label);
12216 emit_insn (gen_isync ());
12219 /* Expand an atomic compare and swap operation. MEM is the memory on which
12220 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12221 value to be stored. SCRATCH is a scratch GPR. */
12224 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12227 enum machine_mode mode = GET_MODE (mem);
12228 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12230 emit_insn (gen_memory_barrier ());
12232 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12233 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12234 emit_label (XEXP (label1, 0));
12236 emit_load_locked (mode, retval, mem);
12238 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12239 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12241 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12242 emit_unlikely_jump (x, label2);
12244 emit_move_insn (scratch, newval);
12245 emit_store_conditional (mode, cond, mem, scratch);
12247 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12248 emit_unlikely_jump (x, label1);
12250 emit_insn (gen_isync ());
12251 emit_label (XEXP (label2, 0));
12254 /* Expand an atomic test and set operation. MEM is the memory on which
12255 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12258 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12260 enum machine_mode mode = GET_MODE (mem);
12261 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12263 emit_insn (gen_memory_barrier ());
12265 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12266 emit_label (XEXP (label, 0));
12268 emit_load_locked (mode, retval, mem);
12269 emit_move_insn (scratch, val);
12270 emit_store_conditional (mode, cond, mem, scratch);
12272 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12273 emit_unlikely_jump (x, label);
12275 emit_insn (gen_isync ());
12278 /* Emit instructions to move SRC to DST. Called by splitters for
12279 multi-register moves. It will emit at most one instruction for
12280 each register that is accessed; that is, it won't emit li/lis pairs
12281 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12285 rs6000_split_multireg_move (rtx dst, rtx src)
12287 /* The register number of the first register being moved. */
12289 /* The mode that is to be moved. */
12290 enum machine_mode mode;
12291 /* The mode that the move is being done in, and its size. */
12292 enum machine_mode reg_mode;
12294 /* The number of registers that will be moved. */
12297 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12298 mode = GET_MODE (dst);
12299 nregs = hard_regno_nregs[reg][mode];
12300 if (FP_REGNO_P (reg))
12302 else if (ALTIVEC_REGNO_P (reg))
12303 reg_mode = V16QImode;
12305 reg_mode = word_mode;
12306 reg_mode_size = GET_MODE_SIZE (reg_mode);
12308 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12310 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12312 /* Move register range backwards, if we might have destructive
12315 for (i = nregs - 1; i >= 0; i--)
12316 emit_insn (gen_rtx_SET (VOIDmode,
12317 simplify_gen_subreg (reg_mode, dst, mode,
12318 i * reg_mode_size),
12319 simplify_gen_subreg (reg_mode, src, mode,
12320 i * reg_mode_size)));
12326 bool used_update = false;
12328 if (MEM_P (src) && INT_REGNO_P (reg))
12332 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12333 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12336 breg = XEXP (XEXP (src, 0), 0);
12337 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12338 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12339 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12340 emit_insn (TARGET_32BIT
12341 ? gen_addsi3 (breg, breg, delta_rtx)
12342 : gen_adddi3 (breg, breg, delta_rtx));
12343 src = replace_equiv_address (src, breg);
12345 else if (! offsettable_memref_p (src))
12348 basereg = gen_rtx_REG (Pmode, reg);
12349 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12350 src = replace_equiv_address (src, basereg);
12353 breg = XEXP (src, 0);
12354 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12355 breg = XEXP (breg, 0);
12357 /* If the base register we are using to address memory is
12358 also a destination reg, then change that register last. */
12360 && REGNO (breg) >= REGNO (dst)
12361 && REGNO (breg) < REGNO (dst) + nregs)
12362 j = REGNO (breg) - REGNO (dst);
12365 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12369 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12370 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12373 breg = XEXP (XEXP (dst, 0), 0);
12374 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12375 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12376 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12378 /* We have to update the breg before doing the store.
12379 Use store with update, if available. */
12383 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12384 emit_insn (TARGET_32BIT
12385 ? (TARGET_POWERPC64
12386 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12387 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12388 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12389 used_update = true;
12392 emit_insn (TARGET_32BIT
12393 ? gen_addsi3 (breg, breg, delta_rtx)
12394 : gen_adddi3 (breg, breg, delta_rtx));
12395 dst = replace_equiv_address (dst, breg);
12398 gcc_assert (offsettable_memref_p (dst));
12401 for (i = 0; i < nregs; i++)
12403 /* Calculate index to next subword. */
12408 /* If compiler already emitted move of first word by
12409 store with update, no need to do anything. */
12410 if (j == 0 && used_update)
12413 emit_insn (gen_rtx_SET (VOIDmode,
12414 simplify_gen_subreg (reg_mode, dst, mode,
12415 j * reg_mode_size),
12416 simplify_gen_subreg (reg_mode, src, mode,
12417 j * reg_mode_size)));
12423 /* This page contains routines that are used to determine what the
12424 function prologue and epilogue code will do and write them out. */
12426 /* Return the first fixed-point register that is required to be
12427 saved. 32 if none. */
12430 first_reg_to_save (void)
12434 /* Find lowest numbered live register. */
12435 for (first_reg = 13; first_reg <= 31; first_reg++)
12436 if (regs_ever_live[first_reg]
12437 && (! call_used_regs[first_reg]
12438 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12439 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12440 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12441 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12446 && current_function_uses_pic_offset_table
12447 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12448 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12454 /* Similar, for FP regs. */
12457 first_fp_reg_to_save (void)
12461 /* Find lowest numbered live register. */
12462 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12463 if (regs_ever_live[first_reg])
12469 /* Similar, for AltiVec regs. */
12472 first_altivec_reg_to_save (void)
12476 /* Stack frame remains as is unless we are in AltiVec ABI. */
12477 if (! TARGET_ALTIVEC_ABI)
12478 return LAST_ALTIVEC_REGNO + 1;
12480 /* Find lowest numbered live register. */
12481 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12482 if (regs_ever_live[i])
12488 /* Return a 32-bit mask of the AltiVec registers we need to set in
12489 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12490 the 32-bit word is 0. */
12492 static unsigned int
12493 compute_vrsave_mask (void)
12495 unsigned int i, mask = 0;
12497 /* First, find out if we use _any_ altivec registers. */
12498 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12499 if (regs_ever_live[i])
12500 mask |= ALTIVEC_REG_BIT (i);
12505 /* Next, remove the argument registers from the set. These must
12506 be in the VRSAVE mask set by the caller, so we don't need to add
12507 them in again. More importantly, the mask we compute here is
12508 used to generate CLOBBERs in the set_vrsave insn, and we do not
12509 wish the argument registers to die. */
12510 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12511 mask &= ~ALTIVEC_REG_BIT (i);
12513 /* Similarly, remove the return value from the set. */
12516 diddle_return_value (is_altivec_return_reg, &yes);
12518 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12524 /* For a very restricted set of circumstances, we can cut down the
12525 size of prologues/epilogues by calling our own save/restore-the-world
12529 compute_save_world_info (rs6000_stack_t *info_ptr)
12531 info_ptr->world_save_p = 1;
12532 info_ptr->world_save_p
12533 = (WORLD_SAVE_P (info_ptr)
12534 && DEFAULT_ABI == ABI_DARWIN
12535 && ! (current_function_calls_setjmp && flag_exceptions)
12536 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12537 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12538 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12539 && info_ptr->cr_save_p);
12541 /* This will not work in conjunction with sibcalls. Make sure there
12542 are none. (This check is expensive, but seldom executed.) */
12543 if (WORLD_SAVE_P (info_ptr))
12546 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12547 if ( GET_CODE (insn) == CALL_INSN
12548 && SIBLING_CALL_P (insn))
12550 info_ptr->world_save_p = 0;
12555 if (WORLD_SAVE_P (info_ptr))
12557 /* Even if we're not touching VRsave, make sure there's room on the
12558 stack for it, if it looks like we're calling SAVE_WORLD, which
12559 will attempt to save it. */
12560 info_ptr->vrsave_size = 4;
12562 /* "Save" the VRsave register too if we're saving the world. */
12563 if (info_ptr->vrsave_mask == 0)
12564 info_ptr->vrsave_mask = compute_vrsave_mask ();
12566 /* Because the Darwin register save/restore routines only handle
12567 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12569 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12570 && (info_ptr->first_altivec_reg_save
12571 >= FIRST_SAVED_ALTIVEC_REGNO));
12578 is_altivec_return_reg (rtx reg, void *xyes)
12580 bool *yes = (bool *) xyes;
12581 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12586 /* Calculate the stack information for the current function. This is
12587 complicated by having two separate calling sequences, the AIX calling
12588 sequence and the V.4 calling sequence.
12590 AIX (and Darwin/Mac OS X) stack frames look like:
12592 SP----> +---------------------------------------+
12593 | back chain to caller | 0 0
12594 +---------------------------------------+
12595 | saved CR | 4 8 (8-11)
12596 +---------------------------------------+
12598 +---------------------------------------+
12599 | reserved for compilers | 12 24
12600 +---------------------------------------+
12601 | reserved for binders | 16 32
12602 +---------------------------------------+
12603 | saved TOC pointer | 20 40
12604 +---------------------------------------+
12605 | Parameter save area (P) | 24 48
12606 +---------------------------------------+
12607 | Alloca space (A) | 24+P etc.
12608 +---------------------------------------+
12609 | Local variable space (L) | 24+P+A
12610 +---------------------------------------+
12611 | Float/int conversion temporary (X) | 24+P+A+L
12612 +---------------------------------------+
12613 | Save area for AltiVec registers (W) | 24+P+A+L+X
12614 +---------------------------------------+
12615 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12616 +---------------------------------------+
12617 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12618 +---------------------------------------+
12619 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12620 +---------------------------------------+
12621 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12622 +---------------------------------------+
12623 old SP->| back chain to caller's caller |
12624 +---------------------------------------+
12626 The required alignment for AIX configurations is two words (i.e., 8
12630 V.4 stack frames look like:
12632 SP----> +---------------------------------------+
12633 | back chain to caller | 0
12634 +---------------------------------------+
12635 | caller's saved LR | 4
12636 +---------------------------------------+
12637 | Parameter save area (P) | 8
12638 +---------------------------------------+
12639 | Alloca space (A) | 8+P
12640 +---------------------------------------+
12641 | Varargs save area (V) | 8+P+A
12642 +---------------------------------------+
12643 | Local variable space (L) | 8+P+A+V
12644 +---------------------------------------+
12645 | Float/int conversion temporary (X) | 8+P+A+V+L
12646 +---------------------------------------+
12647 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12648 +---------------------------------------+
12649 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12650 +---------------------------------------+
12651 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12652 +---------------------------------------+
12653 | SPE: area for 64-bit GP registers |
12654 +---------------------------------------+
12655 | SPE alignment padding |
12656 +---------------------------------------+
12657 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12658 +---------------------------------------+
12659 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12660 +---------------------------------------+
12661 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12662 +---------------------------------------+
12663 old SP->| back chain to caller's caller |
12664 +---------------------------------------+
12666 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12667 given. (But note below and in sysv4.h that we require only 8 and
12668 may round up the size of our stack frame anyways. The historical
12669 reason is early versions of powerpc-linux which didn't properly
12670 align the stack at program startup. A happy side-effect is that
12671 -mno-eabi libraries can be used with -meabi programs.)
12673 The EABI configuration defaults to the V.4 layout. However,
12674 the stack alignment requirements may differ. If -mno-eabi is not
12675 given, the required stack alignment is 8 bytes; if -mno-eabi is
12676 given, the required alignment is 16 bytes. (But see V.4 comment
12679 #ifndef ABI_STACK_BOUNDARY
12680 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12683 static rs6000_stack_t *
12684 rs6000_stack_info (void)
12686 static rs6000_stack_t info;
12687 rs6000_stack_t *info_ptr = &info;
12688 int reg_size = TARGET_32BIT ? 4 : 8;
12691 HOST_WIDE_INT non_fixed_size;
12693 memset (&info, 0, sizeof (info));
12697 /* Cache value so we don't rescan instruction chain over and over. */
12698 if (cfun->machine->insn_chain_scanned_p == 0)
12699 cfun->machine->insn_chain_scanned_p
12700 = spe_func_has_64bit_regs_p () + 1;
12701 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12704 /* Select which calling sequence. */
12705 info_ptr->abi = DEFAULT_ABI;
12707 /* Calculate which registers need to be saved & save area size. */
12708 info_ptr->first_gp_reg_save = first_reg_to_save ();
12709 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12710 even if it currently looks like we won't. */
12711 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12712 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12713 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12714 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12715 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12717 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12719 /* For the SPE, we have an additional upper 32-bits on each GPR.
12720 Ideally we should save the entire 64-bits only when the upper
12721 half is used in SIMD instructions. Since we only record
12722 registers live (not the size they are used in), this proves
12723 difficult because we'd have to traverse the instruction chain at
12724 the right time, taking reload into account. This is a real pain,
12725 so we opt to save the GPRs in 64-bits always if but one register
12726 gets used in 64-bits. Otherwise, all the registers in the frame
12727 get saved in 32-bits.
12729 So... since when we save all GPRs (except the SP) in 64-bits, the
12730 traditional GP save area will be empty. */
12731 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12732 info_ptr->gp_size = 0;
12734 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12735 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12737 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12738 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12739 - info_ptr->first_altivec_reg_save);
12741 /* Does this function call anything? */
12742 info_ptr->calls_p = (! current_function_is_leaf
12743 || cfun->machine->ra_needs_full_frame);
12745 /* Determine if we need to save the link register. */
12746 if ((DEFAULT_ABI == ABI_AIX
12747 && current_function_profile
12748 && !TARGET_PROFILE_KERNEL)
12749 #ifdef TARGET_RELOCATABLE
12750 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12752 || (info_ptr->first_fp_reg_save != 64
12753 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12754 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12755 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12756 || info_ptr->calls_p
12757 || rs6000_ra_ever_killed ())
12759 info_ptr->lr_save_p = 1;
12760 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12763 /* Determine if we need to save the condition code registers. */
12764 if (regs_ever_live[CR2_REGNO]
12765 || regs_ever_live[CR3_REGNO]
12766 || regs_ever_live[CR4_REGNO])
12768 info_ptr->cr_save_p = 1;
12769 if (DEFAULT_ABI == ABI_V4)
12770 info_ptr->cr_size = reg_size;
12773 /* If the current function calls __builtin_eh_return, then we need
12774 to allocate stack space for registers that will hold data for
12775 the exception handler. */
12776 if (current_function_calls_eh_return)
12779 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12782 /* SPE saves EH registers in 64-bits. */
12783 ehrd_size = i * (TARGET_SPE_ABI
12784 && info_ptr->spe_64bit_regs_used != 0
12785 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12790 /* Determine various sizes. */
12791 info_ptr->reg_size = reg_size;
12792 info_ptr->fixed_size = RS6000_SAVE_AREA;
12793 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12794 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12795 TARGET_ALTIVEC ? 16 : 8);
12796 if (FRAME_GROWS_DOWNWARD)
12797 info_ptr->vars_size
12798 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
12799 + info_ptr->parm_size,
12800 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
12801 - (info_ptr->fixed_size + info_ptr->vars_size
12802 + info_ptr->parm_size);
12804 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12805 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12807 info_ptr->spe_gp_size = 0;
12809 if (TARGET_ALTIVEC_ABI)
12810 info_ptr->vrsave_mask = compute_vrsave_mask ();
12812 info_ptr->vrsave_mask = 0;
12814 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12815 info_ptr->vrsave_size = 4;
12817 info_ptr->vrsave_size = 0;
12819 compute_save_world_info (info_ptr);
12821 /* Calculate the offsets. */
12822 switch (DEFAULT_ABI)
12826 gcc_unreachable ();
12830 info_ptr->fp_save_offset = - info_ptr->fp_size;
12831 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12833 if (TARGET_ALTIVEC_ABI)
12835 info_ptr->vrsave_save_offset
12836 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12838 /* Align stack so vector save area is on a quadword boundary. */
12839 if (info_ptr->altivec_size != 0)
12840 info_ptr->altivec_padding_size
12841 = 16 - (-info_ptr->vrsave_save_offset % 16);
12843 info_ptr->altivec_padding_size = 0;
12845 info_ptr->altivec_save_offset
12846 = info_ptr->vrsave_save_offset
12847 - info_ptr->altivec_padding_size
12848 - info_ptr->altivec_size;
12850 /* Adjust for AltiVec case. */
12851 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12854 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12855 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12856 info_ptr->lr_save_offset = 2*reg_size;
12860 info_ptr->fp_save_offset = - info_ptr->fp_size;
12861 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12862 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12864 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12866 /* Align stack so SPE GPR save area is aligned on a
12867 double-word boundary. */
12868 if (info_ptr->spe_gp_size != 0)
12869 info_ptr->spe_padding_size
12870 = 8 - (-info_ptr->cr_save_offset % 8);
12872 info_ptr->spe_padding_size = 0;
12874 info_ptr->spe_gp_save_offset
12875 = info_ptr->cr_save_offset
12876 - info_ptr->spe_padding_size
12877 - info_ptr->spe_gp_size;
12879 /* Adjust for SPE case. */
12880 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
12882 else if (TARGET_ALTIVEC_ABI)
12884 info_ptr->vrsave_save_offset
12885 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12887 /* Align stack so vector save area is on a quadword boundary. */
12888 if (info_ptr->altivec_size != 0)
12889 info_ptr->altivec_padding_size
12890 = 16 - (-info_ptr->vrsave_save_offset % 16);
12892 info_ptr->altivec_padding_size = 0;
12894 info_ptr->altivec_save_offset
12895 = info_ptr->vrsave_save_offset
12896 - info_ptr->altivec_padding_size
12897 - info_ptr->altivec_size;
12899 /* Adjust for AltiVec case. */
12900 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
12903 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
12904 info_ptr->ehrd_offset -= ehrd_size;
12905 info_ptr->lr_save_offset = reg_size;
12909 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
12910 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12911 + info_ptr->gp_size
12912 + info_ptr->altivec_size
12913 + info_ptr->altivec_padding_size
12914 + info_ptr->spe_gp_size
12915 + info_ptr->spe_padding_size
12917 + info_ptr->cr_size
12918 + info_ptr->vrsave_size,
12921 non_fixed_size = (info_ptr->vars_size
12922 + info_ptr->parm_size
12923 + info_ptr->save_size);
12925 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12926 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
12928 /* Determine if we need to allocate any stack frame:
12930 For AIX we need to push the stack if a frame pointer is needed
12931 (because the stack might be dynamically adjusted), if we are
12932 debugging, if we make calls, or if the sum of fp_save, gp_save,
12933 and local variables are more than the space needed to save all
12934 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12935 + 18*8 = 288 (GPR13 reserved).
12937 For V.4 we don't have the stack cushion that AIX uses, but assume
12938 that the debugger can handle stackless frames. */
12940 if (info_ptr->calls_p)
12941 info_ptr->push_p = 1;
12943 else if (DEFAULT_ABI == ABI_V4)
12944 info_ptr->push_p = non_fixed_size != 0;
12946 else if (frame_pointer_needed)
12947 info_ptr->push_p = 1;
12949 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12950 info_ptr->push_p = 1;
12953 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
12955 /* Zero offsets if we're not saving those registers. */
12956 if (info_ptr->fp_size == 0)
12957 info_ptr->fp_save_offset = 0;
12959 if (info_ptr->gp_size == 0)
12960 info_ptr->gp_save_offset = 0;
12962 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12963 info_ptr->altivec_save_offset = 0;
12965 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12966 info_ptr->vrsave_save_offset = 0;
12968 if (! TARGET_SPE_ABI
12969 || info_ptr->spe_64bit_regs_used == 0
12970 || info_ptr->spe_gp_size == 0)
12971 info_ptr->spe_gp_save_offset = 0;
12973 if (! info_ptr->lr_save_p)
12974 info_ptr->lr_save_offset = 0;
12976 if (! info_ptr->cr_save_p)
12977 info_ptr->cr_save_offset = 0;
12982 /* Return true if the current function uses any GPRs in 64-bit SIMD
12986 spe_func_has_64bit_regs_p (void)
12990 /* Functions that save and restore all the call-saved registers will
12991 need to save/restore the registers in 64-bits. */
12992 if (current_function_calls_eh_return
12993 || current_function_calls_setjmp
12994 || current_function_has_nonlocal_goto)
12997 insns = get_insns ();
12999 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13005 /* FIXME: This should be implemented with attributes...
13007 (set_attr "spe64" "true")....then,
13008 if (get_spe64(insn)) return true;
13010 It's the only reliable way to do the stuff below. */
13012 i = PATTERN (insn);
13013 if (GET_CODE (i) == SET)
13015 enum machine_mode mode = GET_MODE (SET_SRC (i));
13017 if (SPE_VECTOR_MODE (mode))
13019 if (TARGET_E500_DOUBLE && mode == DFmode)
13029 debug_stack_info (rs6000_stack_t *info)
13031 const char *abi_string;
13034 info = rs6000_stack_info ();
13036 fprintf (stderr, "\nStack information for function %s:\n",
13037 ((current_function_decl && DECL_NAME (current_function_decl))
13038 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13043 default: abi_string = "Unknown"; break;
13044 case ABI_NONE: abi_string = "NONE"; break;
13045 case ABI_AIX: abi_string = "AIX"; break;
13046 case ABI_DARWIN: abi_string = "Darwin"; break;
13047 case ABI_V4: abi_string = "V.4"; break;
13050 fprintf (stderr, "\tABI = %5s\n", abi_string);
13052 if (TARGET_ALTIVEC_ABI)
13053 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13055 if (TARGET_SPE_ABI)
13056 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13058 if (info->first_gp_reg_save != 32)
13059 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13061 if (info->first_fp_reg_save != 64)
13062 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13064 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13065 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13066 info->first_altivec_reg_save);
13068 if (info->lr_save_p)
13069 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13071 if (info->cr_save_p)
13072 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13074 if (info->vrsave_mask)
13075 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13078 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13081 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13083 if (info->gp_save_offset)
13084 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13086 if (info->fp_save_offset)
13087 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13089 if (info->altivec_save_offset)
13090 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13091 info->altivec_save_offset);
13093 if (info->spe_gp_save_offset)
13094 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13095 info->spe_gp_save_offset);
13097 if (info->vrsave_save_offset)
13098 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13099 info->vrsave_save_offset);
13101 if (info->lr_save_offset)
13102 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13104 if (info->cr_save_offset)
13105 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13107 if (info->varargs_save_offset)
13108 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13110 if (info->total_size)
13111 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13114 if (info->vars_size)
13115 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13118 if (info->parm_size)
13119 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13121 if (info->fixed_size)
13122 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13125 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13127 if (info->spe_gp_size)
13128 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13131 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13133 if (info->altivec_size)
13134 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13136 if (info->vrsave_size)
13137 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13139 if (info->altivec_padding_size)
13140 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13141 info->altivec_padding_size);
13143 if (info->spe_padding_size)
13144 fprintf (stderr, "\tspe_padding_size = %5d\n",
13145 info->spe_padding_size);
13148 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13150 if (info->save_size)
13151 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13153 if (info->reg_size != 4)
13154 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13156 fprintf (stderr, "\n");
13160 rs6000_return_addr (int count, rtx frame)
13162 /* Currently we don't optimize very well between prolog and body
13163 code and for PIC code the code can be actually quite bad, so
13164 don't try to be too clever here. */
13165 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13167 cfun->machine->ra_needs_full_frame = 1;
13174 plus_constant (copy_to_reg
13175 (gen_rtx_MEM (Pmode,
13176 memory_address (Pmode, frame))),
13177 RETURN_ADDRESS_OFFSET)));
13180 cfun->machine->ra_need_lr = 1;
13181 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13184 /* Say whether a function is a candidate for sibcall handling or not.
13185 We do not allow indirect calls to be optimized into sibling calls.
13186 Also, we can't do it if there are any vector parameters; there's
13187 nowhere to put the VRsave code so it works; note that functions with
13188 vector parameters are required to have a prototype, so the argument
13189 type info must be available here. (The tail recursion case can work
13190 with vector parameters, but there's no way to distinguish here.) */
13192 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13197 if (TARGET_ALTIVEC_VRSAVE)
13199 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13200 type; type = TREE_CHAIN (type))
13202 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13206 if (DEFAULT_ABI == ABI_DARWIN
13207 || (*targetm.binds_local_p) (decl))
13209 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13211 if (!lookup_attribute ("longcall", attr_list)
13212 || lookup_attribute ("shortcall", attr_list))
13219 /* NULL if INSN insn is valid within a low-overhead loop.
13220 Otherwise return why doloop cannot be applied.
13221 PowerPC uses the COUNT register for branch on table instructions. */
13223 static const char *
13224 rs6000_invalid_within_doloop (rtx insn)
13227 return "Function call in the loop.";
13230 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13231 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13232 return "Computed branch in the loop.";
13238 rs6000_ra_ever_killed (void)
13244 if (current_function_is_thunk)
13247 /* regs_ever_live has LR marked as used if any sibcalls are present,
13248 but this should not force saving and restoring in the
13249 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13250 clobbers LR, so that is inappropriate. */
13252 /* Also, the prologue can generate a store into LR that
13253 doesn't really count, like this:
13256 bcl to set PIC register
13260 When we're called from the epilogue, we need to avoid counting
13261 this as a store. */
13263 push_topmost_sequence ();
13264 top = get_insns ();
13265 pop_topmost_sequence ();
13266 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13268 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13274 if (!SIBLING_CALL_P (insn))
13277 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13279 else if (set_of (reg, insn) != NULL_RTX
13280 && !prologue_epilogue_contains (insn))
13287 /* Add a REG_MAYBE_DEAD note to the insn. */
13289 rs6000_maybe_dead (rtx insn)
13291 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13296 /* Emit instructions needed to load the TOC register.
13297 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13298 a constant pool; or for SVR4 -fpic. */
13301 rs6000_emit_load_toc_table (int fromprolog)
13304 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13306 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13309 rtx lab, tmp1, tmp2, got, tempLR;
13311 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13312 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13314 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13316 got = rs6000_got_sym ();
13317 tmp1 = tmp2 = dest;
13320 tmp1 = gen_reg_rtx (Pmode);
13321 tmp2 = gen_reg_rtx (Pmode);
13323 tempLR = (fromprolog
13324 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13325 : gen_reg_rtx (Pmode));
13326 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13328 rs6000_maybe_dead (insn);
13329 insn = emit_move_insn (tmp1, tempLR);
13331 rs6000_maybe_dead (insn);
13332 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13334 rs6000_maybe_dead (insn);
13335 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13337 rs6000_maybe_dead (insn);
13339 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13341 rtx tempLR = (fromprolog
13342 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13343 : gen_reg_rtx (Pmode));
13345 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13347 rs6000_maybe_dead (insn);
13348 insn = emit_move_insn (dest, tempLR);
13350 rs6000_maybe_dead (insn);
13352 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13355 rtx tempLR = (fromprolog
13356 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13357 : gen_reg_rtx (Pmode));
13358 rtx temp0 = (fromprolog
13359 ? gen_rtx_REG (Pmode, 0)
13360 : gen_reg_rtx (Pmode));
13366 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13367 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13369 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13370 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13372 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13374 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13375 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13383 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13384 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13385 emit_move_insn (dest, tempLR);
13386 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13388 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13390 rs6000_maybe_dead (insn);
13392 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13394 /* This is for AIX code running in non-PIC ELF32. */
13397 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13398 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13400 insn = emit_insn (gen_elf_high (dest, realsym));
13402 rs6000_maybe_dead (insn);
13403 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13405 rs6000_maybe_dead (insn);
13409 gcc_assert (DEFAULT_ABI == ABI_AIX);
13412 insn = emit_insn (gen_load_toc_aix_si (dest));
13414 insn = emit_insn (gen_load_toc_aix_di (dest));
13416 rs6000_maybe_dead (insn);
13420 /* Emit instructions to restore the link register after determining where
13421 its value has been stored. */
13424 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13426 rs6000_stack_t *info = rs6000_stack_info ();
13429 operands[0] = source;
13430 operands[1] = scratch;
13432 if (info->lr_save_p)
13434 rtx frame_rtx = stack_pointer_rtx;
13435 HOST_WIDE_INT sp_offset = 0;
13438 if (frame_pointer_needed
13439 || current_function_calls_alloca
13440 || info->total_size > 32767)
13442 tmp = gen_frame_mem (Pmode, frame_rtx);
13443 emit_move_insn (operands[1], tmp);
13444 frame_rtx = operands[1];
13446 else if (info->push_p)
13447 sp_offset = info->total_size;
13449 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13450 tmp = gen_frame_mem (Pmode, tmp);
13451 emit_move_insn (tmp, operands[0]);
13454 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13457 static GTY(()) int set = -1;
13460 get_TOC_alias_set (void)
13463 set = new_alias_set ();
13467 /* This returns nonzero if the current function uses the TOC. This is
13468 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13469 is generated by the ABI_V4 load_toc_* patterns. */
13476 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13479 rtx pat = PATTERN (insn);
13482 if (GET_CODE (pat) == PARALLEL)
13483 for (i = 0; i < XVECLEN (pat, 0); i++)
13485 rtx sub = XVECEXP (pat, 0, i);
13486 if (GET_CODE (sub) == USE)
13488 sub = XEXP (sub, 0);
13489 if (GET_CODE (sub) == UNSPEC
13490 && XINT (sub, 1) == UNSPEC_TOC)
13500 create_TOC_reference (rtx symbol)
13502 return gen_rtx_PLUS (Pmode,
13503 gen_rtx_REG (Pmode, TOC_REGISTER),
13504 gen_rtx_CONST (Pmode,
13505 gen_rtx_MINUS (Pmode, symbol,
13506 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13509 /* If _Unwind_* has been called from within the same module,
13510 toc register is not guaranteed to be saved to 40(1) on function
13511 entry. Save it there in that case. */
13514 rs6000_aix_emit_builtin_unwind_init (void)
13517 rtx stack_top = gen_reg_rtx (Pmode);
13518 rtx opcode_addr = gen_reg_rtx (Pmode);
13519 rtx opcode = gen_reg_rtx (SImode);
13520 rtx tocompare = gen_reg_rtx (SImode);
13521 rtx no_toc_save_needed = gen_label_rtx ();
13523 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13524 emit_move_insn (stack_top, mem);
13526 mem = gen_frame_mem (Pmode,
13527 gen_rtx_PLUS (Pmode, stack_top,
13528 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13529 emit_move_insn (opcode_addr, mem);
13530 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13531 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13532 : 0xE8410028, SImode));
13534 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13535 SImode, NULL_RTX, NULL_RTX,
13536 no_toc_save_needed);
13538 mem = gen_frame_mem (Pmode,
13539 gen_rtx_PLUS (Pmode, stack_top,
13540 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13541 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13542 emit_label (no_toc_save_needed);
13545 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13546 and the change to the stack pointer. */
13549 rs6000_emit_stack_tie (void)
13551 rtx mem = gen_frame_mem (BLKmode,
13552 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13554 emit_insn (gen_stack_tie (mem));
13557 /* Emit the correct code for allocating stack space, as insns.
13558 If COPY_R12, make sure a copy of the old frame is left in r12.
13559 The generated code may use hard register 0 as a temporary. */
13562 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13565 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13566 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13567 rtx todec = gen_int_mode (-size, Pmode);
13569 if (INTVAL (todec) != -size)
13571 warning (0, "stack frame too large");
13572 emit_insn (gen_trap ());
13576 if (current_function_limit_stack)
13578 if (REG_P (stack_limit_rtx)
13579 && REGNO (stack_limit_rtx) > 1
13580 && REGNO (stack_limit_rtx) <= 31)
13582 emit_insn (TARGET_32BIT
13583 ? gen_addsi3 (tmp_reg,
13586 : gen_adddi3 (tmp_reg,
13590 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13593 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13595 && DEFAULT_ABI == ABI_V4)
13597 rtx toload = gen_rtx_CONST (VOIDmode,
13598 gen_rtx_PLUS (Pmode,
13602 emit_insn (gen_elf_high (tmp_reg, toload));
13603 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13604 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13608 warning (0, "stack limit expression is not supported");
13611 if (copy_r12 || ! TARGET_UPDATE)
13612 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13618 /* Need a note here so that try_split doesn't get confused. */
13619 if (get_last_insn () == NULL_RTX)
13620 emit_note (NOTE_INSN_DELETED);
13621 insn = emit_move_insn (tmp_reg, todec);
13622 try_split (PATTERN (insn), insn, 0);
13626 insn = emit_insn (TARGET_32BIT
13627 ? gen_movsi_update (stack_reg, stack_reg,
13629 : gen_movdi_di_update (stack_reg, stack_reg,
13630 todec, stack_reg));
13634 insn = emit_insn (TARGET_32BIT
13635 ? gen_addsi3 (stack_reg, stack_reg, todec)
13636 : gen_adddi3 (stack_reg, stack_reg, todec));
13637 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13638 gen_rtx_REG (Pmode, 12));
13641 RTX_FRAME_RELATED_P (insn) = 1;
13643 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13644 gen_rtx_SET (VOIDmode, stack_reg,
13645 gen_rtx_PLUS (Pmode, stack_reg,
13650 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13651 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13652 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13653 deduce these equivalences by itself so it wasn't necessary to hold
13654 its hand so much. */
13657 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13658 rtx reg2, rtx rreg)
13662 /* copy_rtx will not make unique copies of registers, so we need to
13663 ensure we don't have unwanted sharing here. */
13665 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13668 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13670 real = copy_rtx (PATTERN (insn));
13672 if (reg2 != NULL_RTX)
13673 real = replace_rtx (real, reg2, rreg);
13675 real = replace_rtx (real, reg,
13676 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13677 STACK_POINTER_REGNUM),
13680 /* We expect that 'real' is either a SET or a PARALLEL containing
13681 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13682 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13684 if (GET_CODE (real) == SET)
13688 temp = simplify_rtx (SET_SRC (set));
13690 SET_SRC (set) = temp;
13691 temp = simplify_rtx (SET_DEST (set));
13693 SET_DEST (set) = temp;
13694 if (GET_CODE (SET_DEST (set)) == MEM)
13696 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13698 XEXP (SET_DEST (set), 0) = temp;
13705 gcc_assert (GET_CODE (real) == PARALLEL);
13706 for (i = 0; i < XVECLEN (real, 0); i++)
13707 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13709 rtx set = XVECEXP (real, 0, i);
13711 temp = simplify_rtx (SET_SRC (set));
13713 SET_SRC (set) = temp;
13714 temp = simplify_rtx (SET_DEST (set));
13716 SET_DEST (set) = temp;
13717 if (GET_CODE (SET_DEST (set)) == MEM)
13719 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13721 XEXP (SET_DEST (set), 0) = temp;
13723 RTX_FRAME_RELATED_P (set) = 1;
13728 real = spe_synthesize_frame_save (real);
13730 RTX_FRAME_RELATED_P (insn) = 1;
13731 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13736 /* Given an SPE frame note, return a PARALLEL of SETs with the
13737 original note, plus a synthetic register save. */
13740 spe_synthesize_frame_save (rtx real)
13742 rtx synth, offset, reg, real2;
13744 if (GET_CODE (real) != SET
13745 || GET_MODE (SET_SRC (real)) != V2SImode)
13748 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13749 frame related note. The parallel contains a set of the register
13750 being saved, and another set to a synthetic register (n+1200).
13751 This is so we can differentiate between 64-bit and 32-bit saves.
13752 Words cannot describe this nastiness. */
13754 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13755 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13756 && GET_CODE (SET_SRC (real)) == REG);
13759 (set (mem (plus (reg x) (const y)))
13762 (set (mem (plus (reg x) (const y+4)))
13766 real2 = copy_rtx (real);
13767 PUT_MODE (SET_DEST (real2), SImode);
13768 reg = SET_SRC (real2);
13769 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13770 synth = copy_rtx (real2);
13772 if (BYTES_BIG_ENDIAN)
13774 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13775 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13778 reg = SET_SRC (synth);
13780 synth = replace_rtx (synth, reg,
13781 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13783 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13784 synth = replace_rtx (synth, offset,
13785 GEN_INT (INTVAL (offset)
13786 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13788 RTX_FRAME_RELATED_P (synth) = 1;
13789 RTX_FRAME_RELATED_P (real2) = 1;
13790 if (BYTES_BIG_ENDIAN)
13791 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13793 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13798 /* Returns an insn that has a vrsave set operation with the
13799 appropriate CLOBBERs. */
13802 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13805 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13806 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13809 = gen_rtx_SET (VOIDmode,
13811 gen_rtx_UNSPEC_VOLATILE (SImode,
13812 gen_rtvec (2, reg, vrsave),
13813 UNSPECV_SET_VRSAVE));
13817 /* We need to clobber the registers in the mask so the scheduler
13818 does not move sets to VRSAVE before sets of AltiVec registers.
13820 However, if the function receives nonlocal gotos, reload will set
13821 all call saved registers live. We will end up with:
13823 (set (reg 999) (mem))
13824 (parallel [ (set (reg vrsave) (unspec blah))
13825 (clobber (reg 999))])
13827 The clobber will cause the store into reg 999 to be dead, and
13828 flow will attempt to delete an epilogue insn. In this case, we
13829 need an unspec use/set of the register. */
13831 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13832 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13834 if (!epiloguep || call_used_regs [i])
13835 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13836 gen_rtx_REG (V4SImode, i));
13839 rtx reg = gen_rtx_REG (V4SImode, i);
13842 = gen_rtx_SET (VOIDmode,
13844 gen_rtx_UNSPEC (V4SImode,
13845 gen_rtvec (1, reg), 27));
13849 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13851 for (i = 0; i < nclobs; ++i)
13852 XVECEXP (insn, 0, i) = clobs[i];
13857 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13858 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13861 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13862 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13864 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13865 rtx replacea, replaceb;
13867 int_rtx = GEN_INT (offset);
13869 /* Some cases that need register indexed addressing. */
13870 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13871 || (TARGET_E500_DOUBLE && mode == DFmode)
13873 && SPE_VECTOR_MODE (mode)
13874 && !SPE_CONST_OFFSET_OK (offset)))
13876 /* Whomever calls us must make sure r11 is available in the
13877 flow path of instructions in the prologue. */
13878 offset_rtx = gen_rtx_REG (Pmode, 11);
13879 emit_move_insn (offset_rtx, int_rtx);
13881 replacea = offset_rtx;
13882 replaceb = int_rtx;
13886 offset_rtx = int_rtx;
13887 replacea = NULL_RTX;
13888 replaceb = NULL_RTX;
13891 reg = gen_rtx_REG (mode, regno);
13892 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13893 mem = gen_frame_mem (mode, addr);
13895 insn = emit_move_insn (mem, reg);
13897 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13900 /* Emit an offset memory reference suitable for a frame store, while
13901 converting to a valid addressing mode. */
13904 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
13906 rtx int_rtx, offset_rtx;
13908 int_rtx = GEN_INT (offset);
13910 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13911 || (TARGET_E500_DOUBLE && mode == DFmode))
13913 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13914 emit_move_insn (offset_rtx, int_rtx);
13917 offset_rtx = int_rtx;
13919 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13922 /* Look for user-defined global regs. We should not save and restore these,
13923 and cannot use stmw/lmw if there are any in its range. */
13926 no_global_regs_above (int first_greg)
13929 for (i = 0; i < 32 - first_greg; i++)
13930 if (global_regs[first_greg + i])
13935 #ifndef TARGET_FIX_AND_CONTINUE
13936 #define TARGET_FIX_AND_CONTINUE 0
13939 /* Emit function prologue as insns. */
13942 rs6000_emit_prologue (void)
13944 rs6000_stack_t *info = rs6000_stack_info ();
13945 enum machine_mode reg_mode = Pmode;
13946 int reg_size = TARGET_32BIT ? 4 : 8;
13947 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13948 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13949 rtx frame_reg_rtx = sp_reg_rtx;
13950 rtx cr_save_rtx = NULL_RTX;
13952 int saving_FPRs_inline;
13953 int using_store_multiple;
13954 HOST_WIDE_INT sp_offset = 0;
13956 if (TARGET_FIX_AND_CONTINUE)
13958 /* gdb on darwin arranges to forward a function from the old
13959 address by modifying the first 5 instructions of the function
13960 to branch to the overriding function. This is necessary to
13961 permit function pointers that point to the old function to
13962 actually forward to the new function. */
13963 emit_insn (gen_nop ());
13964 emit_insn (gen_nop ());
13965 emit_insn (gen_nop ());
13966 emit_insn (gen_nop ());
13967 emit_insn (gen_nop ());
13970 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13972 reg_mode = V2SImode;
13976 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13977 && (!TARGET_SPE_ABI
13978 || info->spe_64bit_regs_used == 0)
13979 && info->first_gp_reg_save < 31
13980 && no_global_regs_above (info->first_gp_reg_save));
13981 saving_FPRs_inline = (info->first_fp_reg_save == 64
13982 || FP_SAVE_INLINE (info->first_fp_reg_save)
13983 || current_function_calls_eh_return
13984 || cfun->machine->ra_need_lr);
13986 /* For V.4, update stack before we do any saving and set back pointer. */
13988 && (DEFAULT_ABI == ABI_V4
13989 || current_function_calls_eh_return))
13991 if (info->total_size < 32767)
13992 sp_offset = info->total_size;
13994 frame_reg_rtx = frame_ptr_rtx;
13995 rs6000_emit_allocate_stack (info->total_size,
13996 (frame_reg_rtx != sp_reg_rtx
13997 && (info->cr_save_p
13999 || info->first_fp_reg_save < 64
14000 || info->first_gp_reg_save < 32
14002 if (frame_reg_rtx != sp_reg_rtx)
14003 rs6000_emit_stack_tie ();
14006 /* Handle world saves specially here. */
14007 if (WORLD_SAVE_P (info))
14013 /* save_world expects lr in r0. */
14014 if (info->lr_save_p)
14016 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14017 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14018 RTX_FRAME_RELATED_P (insn) = 1;
14021 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14022 assumptions about the offsets of various bits of the stack
14024 gcc_assert (info->gp_save_offset == -220
14025 && info->fp_save_offset == -144
14026 && info->lr_save_offset == 8
14027 && info->cr_save_offset == 4
14030 && (!current_function_calls_eh_return
14031 || info->ehrd_offset == -432)
14032 && info->vrsave_save_offset == -224
14033 && info->altivec_save_offset == (-224 -16 -192));
14035 treg = gen_rtx_REG (SImode, 11);
14036 emit_move_insn (treg, GEN_INT (-info->total_size));
14038 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14039 in R11. It also clobbers R12, so beware! */
14041 /* Preserve CR2 for save_world prologues */
14043 sz += 32 - info->first_gp_reg_save;
14044 sz += 64 - info->first_fp_reg_save;
14045 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14046 p = rtvec_alloc (sz);
14048 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14049 gen_rtx_REG (Pmode,
14050 LINK_REGISTER_REGNUM));
14051 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14052 gen_rtx_SYMBOL_REF (Pmode,
14054 /* We do floats first so that the instruction pattern matches
14056 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14058 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14059 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14060 GEN_INT (info->fp_save_offset
14061 + sp_offset + 8 * i));
14062 rtx mem = gen_frame_mem (DFmode, addr);
14064 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14066 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14068 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14069 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14070 GEN_INT (info->altivec_save_offset
14071 + sp_offset + 16 * i));
14072 rtx mem = gen_frame_mem (V4SImode, addr);
14074 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14076 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14078 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14079 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14080 GEN_INT (info->gp_save_offset
14081 + sp_offset + reg_size * i));
14082 rtx mem = gen_frame_mem (reg_mode, addr);
14084 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14088 /* CR register traditionally saved as CR2. */
14089 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14090 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14091 GEN_INT (info->cr_save_offset
14093 rtx mem = gen_frame_mem (reg_mode, addr);
14095 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14097 /* Prevent any attempt to delete the setting of r0 and treg! */
14098 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14099 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14100 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14102 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14103 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14104 NULL_RTX, NULL_RTX);
14106 if (current_function_calls_eh_return)
14111 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14112 if (regno == INVALID_REGNUM)
14114 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14115 info->ehrd_offset + sp_offset
14116 + reg_size * (int) i,
14122 /* Save AltiVec registers if needed. */
14123 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14127 /* There should be a non inline version of this, for when we
14128 are saving lots of vector registers. */
14129 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14130 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14132 rtx areg, savereg, mem;
14135 offset = info->altivec_save_offset + sp_offset
14136 + 16 * (i - info->first_altivec_reg_save);
14138 savereg = gen_rtx_REG (V4SImode, i);
14140 areg = gen_rtx_REG (Pmode, 0);
14141 emit_move_insn (areg, GEN_INT (offset));
14143 /* AltiVec addressing mode is [reg+reg]. */
14144 mem = gen_frame_mem (V4SImode,
14145 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14147 insn = emit_move_insn (mem, savereg);
14149 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14150 areg, GEN_INT (offset));
14154 /* VRSAVE is a bit vector representing which AltiVec registers
14155 are used. The OS uses this to determine which vector
14156 registers to save on a context switch. We need to save
14157 VRSAVE on the stack frame, add whatever AltiVec registers we
14158 used in this function, and do the corresponding magic in the
14161 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14162 && info->vrsave_mask != 0)
14164 rtx reg, mem, vrsave;
14167 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14168 as frame_reg_rtx and r11 as the static chain pointer for
14169 nested functions. */
14170 reg = gen_rtx_REG (SImode, 0);
14171 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14173 emit_insn (gen_get_vrsave_internal (reg));
14175 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14177 if (!WORLD_SAVE_P (info))
14180 offset = info->vrsave_save_offset + sp_offset;
14181 mem = gen_frame_mem (SImode,
14182 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14183 GEN_INT (offset)));
14184 insn = emit_move_insn (mem, reg);
14187 /* Include the registers in the mask. */
14188 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14190 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14193 /* If we use the link register, get it into r0. */
14194 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14196 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14197 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14198 RTX_FRAME_RELATED_P (insn) = 1;
14201 /* If we need to save CR, put it into r12. */
14202 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14206 cr_save_rtx = gen_rtx_REG (SImode, 12);
14207 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14208 RTX_FRAME_RELATED_P (insn) = 1;
14209 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14210 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14211 But that's OK. All we have to do is specify that _one_ condition
14212 code register is saved in this stack slot. The thrower's epilogue
14213 will then restore all the call-saved registers.
14214 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14215 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14216 gen_rtx_REG (SImode, CR2_REGNO));
14217 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14222 /* Do any required saving of fpr's. If only one or two to save, do
14223 it ourselves. Otherwise, call function. */
14224 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14227 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14228 if ((regs_ever_live[info->first_fp_reg_save+i]
14229 && ! call_used_regs[info->first_fp_reg_save+i]))
14230 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14231 info->first_fp_reg_save + i,
14232 info->fp_save_offset + sp_offset + 8 * i,
14235 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14239 const char *alloc_rname;
14241 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14243 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14244 gen_rtx_REG (Pmode,
14245 LINK_REGISTER_REGNUM));
14246 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14247 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14248 alloc_rname = ggc_strdup (rname);
14249 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14250 gen_rtx_SYMBOL_REF (Pmode,
14252 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14254 rtx addr, reg, mem;
14255 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14256 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14257 GEN_INT (info->fp_save_offset
14258 + sp_offset + 8*i));
14259 mem = gen_frame_mem (DFmode, addr);
14261 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14263 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14264 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14265 NULL_RTX, NULL_RTX);
14268 /* Save GPRs. This is done as a PARALLEL if we are using
14269 the store-multiple instructions. */
14270 if (!WORLD_SAVE_P (info) && using_store_multiple)
14274 p = rtvec_alloc (32 - info->first_gp_reg_save);
14275 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14277 rtx addr, reg, mem;
14278 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14279 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14280 GEN_INT (info->gp_save_offset
14283 mem = gen_frame_mem (reg_mode, addr);
14285 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14287 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14288 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14289 NULL_RTX, NULL_RTX);
14291 else if (!WORLD_SAVE_P (info))
14294 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14295 if ((regs_ever_live[info->first_gp_reg_save + i]
14296 && (!call_used_regs[info->first_gp_reg_save + i]
14297 || (i + info->first_gp_reg_save
14298 == RS6000_PIC_OFFSET_TABLE_REGNUM
14299 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14300 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14301 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14302 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14304 rtx addr, reg, mem;
14305 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14307 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14309 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14312 if (!SPE_CONST_OFFSET_OK (offset))
14314 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14315 emit_move_insn (b, GEN_INT (offset));
14318 b = GEN_INT (offset);
14320 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14321 mem = gen_frame_mem (V2SImode, addr);
14322 insn = emit_move_insn (mem, reg);
14324 if (GET_CODE (b) == CONST_INT)
14325 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14326 NULL_RTX, NULL_RTX);
14328 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14329 b, GEN_INT (offset));
14333 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14334 GEN_INT (info->gp_save_offset
14337 mem = gen_frame_mem (reg_mode, addr);
14339 insn = emit_move_insn (mem, reg);
14340 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14341 NULL_RTX, NULL_RTX);
14346 /* ??? There's no need to emit actual instructions here, but it's the
14347 easiest way to get the frame unwind information emitted. */
14348 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14350 unsigned int i, regno;
14352 /* In AIX ABI we need to pretend we save r2 here. */
14355 rtx addr, reg, mem;
14357 reg = gen_rtx_REG (reg_mode, 2);
14358 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14359 GEN_INT (sp_offset + 5 * reg_size));
14360 mem = gen_frame_mem (reg_mode, addr);
14362 insn = emit_move_insn (mem, reg);
14363 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14364 NULL_RTX, NULL_RTX);
14365 PATTERN (insn) = gen_blockage ();
14370 regno = EH_RETURN_DATA_REGNO (i);
14371 if (regno == INVALID_REGNUM)
14374 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14375 info->ehrd_offset + sp_offset
14376 + reg_size * (int) i,
14381 /* Save lr if we used it. */
14382 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14384 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14385 GEN_INT (info->lr_save_offset + sp_offset));
14386 rtx reg = gen_rtx_REG (Pmode, 0);
14387 rtx mem = gen_rtx_MEM (Pmode, addr);
14388 /* This should not be of frame_alias_set, because of
14389 __builtin_return_address. */
14391 insn = emit_move_insn (mem, reg);
14392 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14393 NULL_RTX, NULL_RTX);
14396 /* Save CR if we use any that must be preserved. */
14397 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14399 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14400 GEN_INT (info->cr_save_offset + sp_offset));
14401 rtx mem = gen_frame_mem (SImode, addr);
14402 /* See the large comment above about why CR2_REGNO is used. */
14403 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14405 /* If r12 was used to hold the original sp, copy cr into r0 now
14407 if (REGNO (frame_reg_rtx) == 12)
14411 cr_save_rtx = gen_rtx_REG (SImode, 0);
14412 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14413 RTX_FRAME_RELATED_P (insn) = 1;
14414 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14415 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14420 insn = emit_move_insn (mem, cr_save_rtx);
14422 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14423 NULL_RTX, NULL_RTX);
14426 /* Update stack and set back pointer unless this is V.4,
14427 for which it was done previously. */
14428 if (!WORLD_SAVE_P (info) && info->push_p
14429 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14430 rs6000_emit_allocate_stack (info->total_size, FALSE);
14432 /* Set frame pointer, if needed. */
14433 if (frame_pointer_needed)
14435 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14437 RTX_FRAME_RELATED_P (insn) = 1;
14440 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14441 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14442 || (DEFAULT_ABI == ABI_V4
14443 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14444 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14446 /* If emit_load_toc_table will use the link register, we need to save
14447 it. We use R12 for this purpose because emit_load_toc_table
14448 can use register 0. This allows us to use a plain 'blr' to return
14449 from the procedure more often. */
14450 int save_LR_around_toc_setup = (TARGET_ELF
14451 && DEFAULT_ABI != ABI_AIX
14453 && ! info->lr_save_p
14454 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14455 if (save_LR_around_toc_setup)
14457 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14459 insn = emit_move_insn (frame_ptr_rtx, lr);
14460 rs6000_maybe_dead (insn);
14461 RTX_FRAME_RELATED_P (insn) = 1;
14463 rs6000_emit_load_toc_table (TRUE);
14465 insn = emit_move_insn (lr, frame_ptr_rtx);
14466 rs6000_maybe_dead (insn);
14467 RTX_FRAME_RELATED_P (insn) = 1;
14470 rs6000_emit_load_toc_table (TRUE);
14474 if (DEFAULT_ABI == ABI_DARWIN
14475 && flag_pic && current_function_uses_pic_offset_table)
14477 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14478 rtx src = machopic_function_base_sym ();
14480 /* Save and restore LR locally around this call (in R0). */
14481 if (!info->lr_save_p)
14482 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14484 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14486 insn = emit_move_insn (gen_rtx_REG (Pmode,
14487 RS6000_PIC_OFFSET_TABLE_REGNUM),
14489 rs6000_maybe_dead (insn);
14491 if (!info->lr_save_p)
14492 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14497 /* Write function prologue. */
14500 rs6000_output_function_prologue (FILE *file,
14501 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14503 rs6000_stack_t *info = rs6000_stack_info ();
14505 if (TARGET_DEBUG_STACK)
14506 debug_stack_info (info);
14508 /* Write .extern for any function we will call to save and restore
14510 if (info->first_fp_reg_save < 64
14511 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14512 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14513 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14514 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14515 RESTORE_FP_SUFFIX);
14517 /* Write .extern for AIX common mode routines, if needed. */
14518 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14520 fputs ("\t.extern __mulh\n", file);
14521 fputs ("\t.extern __mull\n", file);
14522 fputs ("\t.extern __divss\n", file);
14523 fputs ("\t.extern __divus\n", file);
14524 fputs ("\t.extern __quoss\n", file);
14525 fputs ("\t.extern __quous\n", file);
14526 common_mode_defined = 1;
14529 if (! HAVE_prologue)
14533 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14534 the "toplevel" insn chain. */
14535 emit_note (NOTE_INSN_DELETED);
14536 rs6000_emit_prologue ();
14537 emit_note (NOTE_INSN_DELETED);
14539 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14543 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14545 INSN_ADDRESSES_NEW (insn, addr);
14550 if (TARGET_DEBUG_STACK)
14551 debug_rtx_list (get_insns (), 100);
14552 final (get_insns (), file, FALSE);
14556 rs6000_pic_labelno++;
14559 /* Emit function epilogue as insns.
14561 At present, dwarf2out_frame_debug_expr doesn't understand
14562 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14563 anywhere in the epilogue. Most of the insns below would in any case
14564 need special notes to explain where r11 is in relation to the stack. */
14567 rs6000_emit_epilogue (int sibcall)
14569 rs6000_stack_t *info;
14570 int restoring_FPRs_inline;
14571 int using_load_multiple;
14572 int using_mfcr_multiple;
14573 int use_backchain_to_restore_sp;
14575 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14576 rtx frame_reg_rtx = sp_reg_rtx;
14577 enum machine_mode reg_mode = Pmode;
14578 int reg_size = TARGET_32BIT ? 4 : 8;
14581 info = rs6000_stack_info ();
14583 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14585 reg_mode = V2SImode;
14589 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14590 && (!TARGET_SPE_ABI
14591 || info->spe_64bit_regs_used == 0)
14592 && info->first_gp_reg_save < 31
14593 && no_global_regs_above (info->first_gp_reg_save));
14594 restoring_FPRs_inline = (sibcall
14595 || current_function_calls_eh_return
14596 || info->first_fp_reg_save == 64
14597 || FP_SAVE_INLINE (info->first_fp_reg_save));
14598 use_backchain_to_restore_sp = (frame_pointer_needed
14599 || current_function_calls_alloca
14600 || info->total_size > 32767);
14601 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14602 || rs6000_cpu == PROCESSOR_PPC603
14603 || rs6000_cpu == PROCESSOR_PPC750
14606 if (WORLD_SAVE_P (info))
14610 const char *alloc_rname;
14613 /* eh_rest_world_r10 will return to the location saved in the LR
14614 stack slot (which is not likely to be our caller.)
14615 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14616 rest_world is similar, except any R10 parameter is ignored.
14617 The exception-handling stuff that was here in 2.95 is no
14618 longer necessary. */
14622 + 32 - info->first_gp_reg_save
14623 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14624 + 63 + 1 - info->first_fp_reg_save);
14626 strcpy (rname, ((current_function_calls_eh_return) ?
14627 "*eh_rest_world_r10" : "*rest_world"));
14628 alloc_rname = ggc_strdup (rname);
14631 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14632 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14633 gen_rtx_REG (Pmode,
14634 LINK_REGISTER_REGNUM));
14636 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14637 /* The instruction pattern requires a clobber here;
14638 it is shared with the restVEC helper. */
14640 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14643 /* CR register traditionally saved as CR2. */
14644 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14645 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14646 GEN_INT (info->cr_save_offset));
14647 rtx mem = gen_frame_mem (reg_mode, addr);
14649 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14652 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14654 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14655 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14656 GEN_INT (info->gp_save_offset
14658 rtx mem = gen_frame_mem (reg_mode, addr);
14660 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14662 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14664 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14665 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14666 GEN_INT (info->altivec_save_offset
14668 rtx mem = gen_frame_mem (V4SImode, addr);
14670 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14672 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14674 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14675 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14676 GEN_INT (info->fp_save_offset
14678 rtx mem = gen_frame_mem (DFmode, addr);
14680 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14683 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14685 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14687 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14689 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14691 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14692 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14697 /* If we have a frame pointer, a call to alloca, or a large stack
14698 frame, restore the old stack pointer using the backchain. Otherwise,
14699 we know what size to update it with. */
14700 if (use_backchain_to_restore_sp)
14702 /* Under V.4, don't reset the stack pointer until after we're done
14703 loading the saved registers. */
14704 if (DEFAULT_ABI == ABI_V4)
14705 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14707 emit_move_insn (frame_reg_rtx,
14708 gen_rtx_MEM (Pmode, sp_reg_rtx));
14710 else if (info->push_p)
14712 if (DEFAULT_ABI == ABI_V4
14713 || current_function_calls_eh_return)
14714 sp_offset = info->total_size;
14717 emit_insn (TARGET_32BIT
14718 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14719 GEN_INT (info->total_size))
14720 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14721 GEN_INT (info->total_size)));
14725 /* Restore AltiVec registers if needed. */
14726 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14730 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14731 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14733 rtx addr, areg, mem;
14735 areg = gen_rtx_REG (Pmode, 0);
14737 (areg, GEN_INT (info->altivec_save_offset
14739 + 16 * (i - info->first_altivec_reg_save)));
14741 /* AltiVec addressing mode is [reg+reg]. */
14742 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14743 mem = gen_frame_mem (V4SImode, addr);
14745 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14749 /* Restore VRSAVE if needed. */
14750 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14751 && info->vrsave_mask != 0)
14753 rtx addr, mem, reg;
14755 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14756 GEN_INT (info->vrsave_save_offset + sp_offset));
14757 mem = gen_frame_mem (SImode, addr);
14758 reg = gen_rtx_REG (SImode, 12);
14759 emit_move_insn (reg, mem);
14761 emit_insn (generate_set_vrsave (reg, info, 1));
14764 /* Get the old lr if we saved it. */
14765 if (info->lr_save_p)
14767 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14768 info->lr_save_offset + sp_offset);
14770 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14773 /* Get the old cr if we saved it. */
14774 if (info->cr_save_p)
14776 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14777 GEN_INT (info->cr_save_offset + sp_offset));
14778 rtx mem = gen_frame_mem (SImode, addr);
14780 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14783 /* Set LR here to try to overlap restores below. */
14784 if (info->lr_save_p)
14785 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14786 gen_rtx_REG (Pmode, 0));
14788 /* Load exception handler data registers, if needed. */
14789 if (current_function_calls_eh_return)
14791 unsigned int i, regno;
14795 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14796 GEN_INT (sp_offset + 5 * reg_size));
14797 rtx mem = gen_frame_mem (reg_mode, addr);
14799 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14806 regno = EH_RETURN_DATA_REGNO (i);
14807 if (regno == INVALID_REGNUM)
14810 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14811 info->ehrd_offset + sp_offset
14812 + reg_size * (int) i);
14814 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14818 /* Restore GPRs. This is done as a PARALLEL if we are using
14819 the load-multiple instructions. */
14820 if (using_load_multiple)
14823 p = rtvec_alloc (32 - info->first_gp_reg_save);
14824 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14826 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14827 GEN_INT (info->gp_save_offset
14830 rtx mem = gen_frame_mem (reg_mode, addr);
14833 gen_rtx_SET (VOIDmode,
14834 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14837 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14840 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14841 if ((regs_ever_live[info->first_gp_reg_save + i]
14842 && (!call_used_regs[info->first_gp_reg_save + i]
14843 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14844 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14845 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14846 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14847 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14849 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14850 GEN_INT (info->gp_save_offset
14853 rtx mem = gen_frame_mem (reg_mode, addr);
14855 /* Restore 64-bit quantities for SPE. */
14856 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14858 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14861 if (!SPE_CONST_OFFSET_OK (offset))
14863 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14864 emit_move_insn (b, GEN_INT (offset));
14867 b = GEN_INT (offset);
14869 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14870 mem = gen_frame_mem (V2SImode, addr);
14873 emit_move_insn (gen_rtx_REG (reg_mode,
14874 info->first_gp_reg_save + i), mem);
14877 /* Restore fpr's if we need to do it without calling a function. */
14878 if (restoring_FPRs_inline)
14879 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14880 if ((regs_ever_live[info->first_fp_reg_save+i]
14881 && ! call_used_regs[info->first_fp_reg_save+i]))
14884 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14885 GEN_INT (info->fp_save_offset
14888 mem = gen_frame_mem (DFmode, addr);
14890 emit_move_insn (gen_rtx_REG (DFmode,
14891 info->first_fp_reg_save + i),
14895 /* If we saved cr, restore it here. Just those that were used. */
14896 if (info->cr_save_p)
14898 rtx r12_rtx = gen_rtx_REG (SImode, 12);
14901 if (using_mfcr_multiple)
14903 for (i = 0; i < 8; i++)
14904 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14906 gcc_assert (count);
14909 if (using_mfcr_multiple && count > 1)
14914 p = rtvec_alloc (count);
14917 for (i = 0; i < 8; i++)
14918 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14920 rtvec r = rtvec_alloc (2);
14921 RTVEC_ELT (r, 0) = r12_rtx;
14922 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
14923 RTVEC_ELT (p, ndx) =
14924 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
14925 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
14928 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14929 gcc_assert (ndx == count);
14932 for (i = 0; i < 8; i++)
14933 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14935 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
14941 /* If this is V.4, unwind the stack pointer after all of the loads
14943 if (frame_reg_rtx != sp_reg_rtx)
14945 /* This blockage is needed so that sched doesn't decide to move
14946 the sp change before the register restores. */
14947 rs6000_emit_stack_tie ();
14948 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
14950 else if (sp_offset != 0)
14951 emit_insn (TARGET_32BIT
14952 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14953 GEN_INT (sp_offset))
14954 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14955 GEN_INT (sp_offset)));
14957 if (current_function_calls_eh_return)
14959 rtx sa = EH_RETURN_STACKADJ_RTX;
14960 emit_insn (TARGET_32BIT
14961 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14962 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14968 if (! restoring_FPRs_inline)
14969 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14971 p = rtvec_alloc (2);
14973 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
14974 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14975 gen_rtx_REG (Pmode,
14976 LINK_REGISTER_REGNUM));
14978 /* If we have to restore more than two FP registers, branch to the
14979 restore function. It will return to our caller. */
14980 if (! restoring_FPRs_inline)
14984 const char *alloc_rname;
14986 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
14987 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
14988 alloc_rname = ggc_strdup (rname);
14989 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14990 gen_rtx_SYMBOL_REF (Pmode,
14993 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14996 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14997 GEN_INT (info->fp_save_offset + 8*i));
14998 mem = gen_frame_mem (DFmode, addr);
15000 RTVEC_ELT (p, i+3) =
15001 gen_rtx_SET (VOIDmode,
15002 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15007 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15011 /* Write function epilogue. */
15014 rs6000_output_function_epilogue (FILE *file,
15015 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15017 rs6000_stack_t *info = rs6000_stack_info ();
15019 if (! HAVE_epilogue)
15021 rtx insn = get_last_insn ();
15022 /* If the last insn was a BARRIER, we don't have to write anything except
15023 the trace table. */
15024 if (GET_CODE (insn) == NOTE)
15025 insn = prev_nonnote_insn (insn);
15026 if (insn == 0 || GET_CODE (insn) != BARRIER)
15028 /* This is slightly ugly, but at least we don't have two
15029 copies of the epilogue-emitting code. */
15032 /* A NOTE_INSN_DELETED is supposed to be at the start
15033 and end of the "toplevel" insn chain. */
15034 emit_note (NOTE_INSN_DELETED);
15035 rs6000_emit_epilogue (FALSE);
15036 emit_note (NOTE_INSN_DELETED);
15038 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15042 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15044 INSN_ADDRESSES_NEW (insn, addr);
15049 if (TARGET_DEBUG_STACK)
15050 debug_rtx_list (get_insns (), 100);
15051 final (get_insns (), file, FALSE);
15057 macho_branch_islands ();
15058 /* Mach-O doesn't support labels at the end of objects, so if
15059 it looks like we might want one, insert a NOP. */
15061 rtx insn = get_last_insn ();
15064 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15065 insn = PREV_INSN (insn);
15069 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15070 fputs ("\tnop\n", file);
15074 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15077 We don't output a traceback table if -finhibit-size-directive was
15078 used. The documentation for -finhibit-size-directive reads
15079 ``don't output a @code{.size} assembler directive, or anything
15080 else that would cause trouble if the function is split in the
15081 middle, and the two halves are placed at locations far apart in
15082 memory.'' The traceback table has this property, since it
15083 includes the offset from the start of the function to the
15084 traceback table itself.
15086 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15087 different traceback table. */
15088 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15089 && rs6000_traceback != traceback_none)
15091 const char *fname = NULL;
15092 const char *language_string = lang_hooks.name;
15093 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15095 int optional_tbtab;
15097 if (rs6000_traceback == traceback_full)
15098 optional_tbtab = 1;
15099 else if (rs6000_traceback == traceback_part)
15100 optional_tbtab = 0;
15102 optional_tbtab = !optimize_size && !TARGET_ELF;
15104 if (optional_tbtab)
15106 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15107 while (*fname == '.') /* V.4 encodes . in the name */
15110 /* Need label immediately before tbtab, so we can compute
15111 its offset from the function start. */
15112 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15113 ASM_OUTPUT_LABEL (file, fname);
15116 /* The .tbtab pseudo-op can only be used for the first eight
15117 expressions, since it can't handle the possibly variable
15118 length fields that follow. However, if you omit the optional
15119 fields, the assembler outputs zeros for all optional fields
15120 anyways, giving each variable length field is minimum length
15121 (as defined in sys/debug.h). Thus we can not use the .tbtab
15122 pseudo-op at all. */
15124 /* An all-zero word flags the start of the tbtab, for debuggers
15125 that have to find it by searching forward from the entry
15126 point or from the current pc. */
15127 fputs ("\t.long 0\n", file);
15129 /* Tbtab format type. Use format type 0. */
15130 fputs ("\t.byte 0,", file);
15132 /* Language type. Unfortunately, there does not seem to be any
15133 official way to discover the language being compiled, so we
15134 use language_string.
15135 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15136 Java is 13. Objective-C is 14. */
15137 if (! strcmp (language_string, "GNU C"))
15139 else if (! strcmp (language_string, "GNU F77")
15140 || ! strcmp (language_string, "GNU F95"))
15142 else if (! strcmp (language_string, "GNU Pascal"))
15144 else if (! strcmp (language_string, "GNU Ada"))
15146 else if (! strcmp (language_string, "GNU C++"))
15148 else if (! strcmp (language_string, "GNU Java"))
15150 else if (! strcmp (language_string, "GNU Objective-C"))
15153 gcc_unreachable ();
15154 fprintf (file, "%d,", i);
15156 /* 8 single bit fields: global linkage (not set for C extern linkage,
15157 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15158 from start of procedure stored in tbtab, internal function, function
15159 has controlled storage, function has no toc, function uses fp,
15160 function logs/aborts fp operations. */
15161 /* Assume that fp operations are used if any fp reg must be saved. */
15162 fprintf (file, "%d,",
15163 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15165 /* 6 bitfields: function is interrupt handler, name present in
15166 proc table, function calls alloca, on condition directives
15167 (controls stack walks, 3 bits), saves condition reg, saves
15169 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15170 set up as a frame pointer, even when there is no alloca call. */
15171 fprintf (file, "%d,",
15172 ((optional_tbtab << 6)
15173 | ((optional_tbtab & frame_pointer_needed) << 5)
15174 | (info->cr_save_p << 1)
15175 | (info->lr_save_p)));
15177 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15179 fprintf (file, "%d,",
15180 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15182 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15183 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15185 if (optional_tbtab)
15187 /* Compute the parameter info from the function decl argument
15190 int next_parm_info_bit = 31;
15192 for (decl = DECL_ARGUMENTS (current_function_decl);
15193 decl; decl = TREE_CHAIN (decl))
15195 rtx parameter = DECL_INCOMING_RTL (decl);
15196 enum machine_mode mode = GET_MODE (parameter);
15198 if (GET_CODE (parameter) == REG)
15200 if (SCALAR_FLOAT_MODE_P (mode))
15218 gcc_unreachable ();
15221 /* If only one bit will fit, don't or in this entry. */
15222 if (next_parm_info_bit > 0)
15223 parm_info |= (bits << (next_parm_info_bit - 1));
15224 next_parm_info_bit -= 2;
15228 fixed_parms += ((GET_MODE_SIZE (mode)
15229 + (UNITS_PER_WORD - 1))
15231 next_parm_info_bit -= 1;
15237 /* Number of fixed point parameters. */
15238 /* This is actually the number of words of fixed point parameters; thus
15239 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15240 fprintf (file, "%d,", fixed_parms);
15242 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15244 /* This is actually the number of fp registers that hold parameters;
15245 and thus the maximum value is 13. */
15246 /* Set parameters on stack bit if parameters are not in their original
15247 registers, regardless of whether they are on the stack? Xlc
15248 seems to set the bit when not optimizing. */
15249 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15251 if (! optional_tbtab)
15254 /* Optional fields follow. Some are variable length. */
15256 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15257 11 double float. */
15258 /* There is an entry for each parameter in a register, in the order that
15259 they occur in the parameter list. Any intervening arguments on the
15260 stack are ignored. If the list overflows a long (max possible length
15261 34 bits) then completely leave off all elements that don't fit. */
15262 /* Only emit this long if there was at least one parameter. */
15263 if (fixed_parms || float_parms)
15264 fprintf (file, "\t.long %d\n", parm_info);
15266 /* Offset from start of code to tb table. */
15267 fputs ("\t.long ", file);
15268 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15270 RS6000_OUTPUT_BASENAME (file, fname);
15272 assemble_name (file, fname);
15274 rs6000_output_function_entry (file, fname);
15277 /* Interrupt handler mask. */
15278 /* Omit this long, since we never set the interrupt handler bit
15281 /* Number of CTL (controlled storage) anchors. */
15282 /* Omit this long, since the has_ctl bit is never set above. */
15284 /* Displacement into stack of each CTL anchor. */
15285 /* Omit this list of longs, because there are no CTL anchors. */
15287 /* Length of function name. */
15290 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15292 /* Function name. */
15293 assemble_string (fname, strlen (fname));
15295 /* Register for alloca automatic storage; this is always reg 31.
15296 Only emit this if the alloca bit was set above. */
15297 if (frame_pointer_needed)
15298 fputs ("\t.byte 31\n", file);
15300 fputs ("\t.align 2\n", file);
15304 /* A C compound statement that outputs the assembler code for a thunk
15305 function, used to implement C++ virtual function calls with
15306 multiple inheritance. The thunk acts as a wrapper around a virtual
15307 function, adjusting the implicit object parameter before handing
15308 control off to the real function.
15310 First, emit code to add the integer DELTA to the location that
15311 contains the incoming first argument. Assume that this argument
15312 contains a pointer, and is the one used to pass the `this' pointer
15313 in C++. This is the incoming argument *before* the function
15314 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15315 values of all other incoming arguments.
15317 After the addition, emit code to jump to FUNCTION, which is a
15318 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15319 not touch the return address. Hence returning from FUNCTION will
15320 return to whoever called the current `thunk'.
15322 The effect must be as if FUNCTION had been called directly with the
15323 adjusted first argument. This macro is responsible for emitting
15324 all of the code for a thunk function; output_function_prologue()
15325 and output_function_epilogue() are not invoked.
15327 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15328 been extracted from it.) It might possibly be useful on some
15329 targets, but probably not.
15331 If you do not define this macro, the target-independent code in the
15332 C++ frontend will generate a less efficient heavyweight thunk that
15333 calls FUNCTION instead of jumping to it. The generic approach does
15334 not support varargs. */
15337 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15338 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15341 rtx this, insn, funexp;
15343 reload_completed = 1;
15344 epilogue_completed = 1;
15345 no_new_pseudos = 1;
15346 reset_block_changes ();
15348 /* Mark the end of the (empty) prologue. */
15349 emit_note (NOTE_INSN_PROLOGUE_END);
15351 /* Find the "this" pointer. If the function returns a structure,
15352 the structure return pointer is in r3. */
15353 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15354 this = gen_rtx_REG (Pmode, 4);
15356 this = gen_rtx_REG (Pmode, 3);
15358 /* Apply the constant offset, if required. */
15361 rtx delta_rtx = GEN_INT (delta);
15362 emit_insn (TARGET_32BIT
15363 ? gen_addsi3 (this, this, delta_rtx)
15364 : gen_adddi3 (this, this, delta_rtx));
15367 /* Apply the offset from the vtable, if required. */
15370 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15371 rtx tmp = gen_rtx_REG (Pmode, 12);
15373 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15374 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15376 emit_insn (TARGET_32BIT
15377 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15378 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15379 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15383 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15385 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15387 emit_insn (TARGET_32BIT
15388 ? gen_addsi3 (this, this, tmp)
15389 : gen_adddi3 (this, this, tmp));
15392 /* Generate a tail call to the target function. */
15393 if (!TREE_USED (function))
15395 assemble_external (function);
15396 TREE_USED (function) = 1;
15398 funexp = XEXP (DECL_RTL (function), 0);
15399 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15402 if (MACHOPIC_INDIRECT)
15403 funexp = machopic_indirect_call_target (funexp);
15406 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15407 generate sibcall RTL explicitly. */
15408 insn = emit_call_insn (
15409 gen_rtx_PARALLEL (VOIDmode,
15411 gen_rtx_CALL (VOIDmode,
15412 funexp, const0_rtx),
15413 gen_rtx_USE (VOIDmode, const0_rtx),
15414 gen_rtx_USE (VOIDmode,
15415 gen_rtx_REG (SImode,
15416 LINK_REGISTER_REGNUM)),
15417 gen_rtx_RETURN (VOIDmode))));
15418 SIBLING_CALL_P (insn) = 1;
15421 /* Run just enough of rest_of_compilation to get the insns emitted.
15422 There's not really enough bulk here to make other passes such as
15423 instruction scheduling worth while. Note that use_thunk calls
15424 assemble_start_function and assemble_end_function. */
15425 insn = get_insns ();
15426 insn_locators_initialize ();
15427 shorten_branches (insn);
15428 final_start_function (insn, file, 1);
15429 final (insn, file, 1);
15430 final_end_function ();
15432 reload_completed = 0;
15433 epilogue_completed = 0;
15434 no_new_pseudos = 0;
15437 /* A quick summary of the various types of 'constant-pool tables'
15440 Target Flags Name One table per
15441 AIX (none) AIX TOC object file
15442 AIX -mfull-toc AIX TOC object file
15443 AIX -mminimal-toc AIX minimal TOC translation unit
15444 SVR4/EABI (none) SVR4 SDATA object file
15445 SVR4/EABI -fpic SVR4 pic object file
15446 SVR4/EABI -fPIC SVR4 PIC translation unit
15447 SVR4/EABI -mrelocatable EABI TOC function
15448 SVR4/EABI -maix AIX TOC object file
15449 SVR4/EABI -maix -mminimal-toc
15450 AIX minimal TOC translation unit
15452 Name Reg. Set by entries contains:
15453 made by addrs? fp? sum?
15455 AIX TOC 2 crt0 as Y option option
15456 AIX minimal TOC 30 prolog gcc Y Y option
15457 SVR4 SDATA 13 crt0 gcc N Y N
15458 SVR4 pic 30 prolog ld Y not yet N
15459 SVR4 PIC 30 prolog gcc Y option option
15460 EABI TOC 30 prolog gcc Y option option
15464 /* Hash functions for the hash table. */
15467 rs6000_hash_constant (rtx k)
15469 enum rtx_code code = GET_CODE (k);
15470 enum machine_mode mode = GET_MODE (k);
15471 unsigned result = (code << 3) ^ mode;
15472 const char *format;
15475 format = GET_RTX_FORMAT (code);
15476 flen = strlen (format);
15482 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15485 if (mode != VOIDmode)
15486 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15498 for (; fidx < flen; fidx++)
15499 switch (format[fidx])
15504 const char *str = XSTR (k, fidx);
15505 len = strlen (str);
15506 result = result * 613 + len;
15507 for (i = 0; i < len; i++)
15508 result = result * 613 + (unsigned) str[i];
15513 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15517 result = result * 613 + (unsigned) XINT (k, fidx);
15520 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15521 result = result * 613 + (unsigned) XWINT (k, fidx);
15525 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15526 result = result * 613 + (unsigned) (XWINT (k, fidx)
15533 gcc_unreachable ();
15540 toc_hash_function (const void *hash_entry)
15542 const struct toc_hash_struct *thc =
15543 (const struct toc_hash_struct *) hash_entry;
15544 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15547 /* Compare H1 and H2 for equivalence. */
15550 toc_hash_eq (const void *h1, const void *h2)
15552 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15553 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15555 if (((const struct toc_hash_struct *) h1)->key_mode
15556 != ((const struct toc_hash_struct *) h2)->key_mode)
15559 return rtx_equal_p (r1, r2);
15562 /* These are the names given by the C++ front-end to vtables, and
15563 vtable-like objects. Ideally, this logic should not be here;
15564 instead, there should be some programmatic way of inquiring as
15565 to whether or not an object is a vtable. */
15567 #define VTABLE_NAME_P(NAME) \
15568 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15569 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15570 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15571 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15572 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15575 rs6000_output_symbol_ref (FILE *file, rtx x)
15577 /* Currently C++ toc references to vtables can be emitted before it
15578 is decided whether the vtable is public or private. If this is
15579 the case, then the linker will eventually complain that there is
15580 a reference to an unknown section. Thus, for vtables only,
15581 we emit the TOC reference to reference the symbol and not the
15583 const char *name = XSTR (x, 0);
15585 if (VTABLE_NAME_P (name))
15587 RS6000_OUTPUT_BASENAME (file, name);
15590 assemble_name (file, name);
15593 /* Output a TOC entry. We derive the entry name from what is being
15597 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15600 const char *name = buf;
15601 const char *real_name;
15603 HOST_WIDE_INT offset = 0;
15605 gcc_assert (!TARGET_NO_TOC);
15607 /* When the linker won't eliminate them, don't output duplicate
15608 TOC entries (this happens on AIX if there is any kind of TOC,
15609 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15611 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15613 struct toc_hash_struct *h;
15616 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15617 time because GGC is not initialized at that point. */
15618 if (toc_hash_table == NULL)
15619 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15620 toc_hash_eq, NULL);
15622 h = ggc_alloc (sizeof (*h));
15624 h->key_mode = mode;
15625 h->labelno = labelno;
15627 found = htab_find_slot (toc_hash_table, h, 1);
15628 if (*found == NULL)
15630 else /* This is indeed a duplicate.
15631 Set this label equal to that label. */
15633 fputs ("\t.set ", file);
15634 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15635 fprintf (file, "%d,", labelno);
15636 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15637 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15643 /* If we're going to put a double constant in the TOC, make sure it's
15644 aligned properly when strict alignment is on. */
15645 if (GET_CODE (x) == CONST_DOUBLE
15646 && STRICT_ALIGNMENT
15647 && GET_MODE_BITSIZE (mode) >= 64
15648 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15649 ASM_OUTPUT_ALIGN (file, 3);
15652 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15654 /* Handle FP constants specially. Note that if we have a minimal
15655 TOC, things we put here aren't actually in the TOC, so we can allow
15657 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15659 REAL_VALUE_TYPE rv;
15662 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15663 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15667 if (TARGET_MINIMAL_TOC)
15668 fputs (DOUBLE_INT_ASM_OP, file);
15670 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15671 k[0] & 0xffffffff, k[1] & 0xffffffff,
15672 k[2] & 0xffffffff, k[3] & 0xffffffff);
15673 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15674 k[0] & 0xffffffff, k[1] & 0xffffffff,
15675 k[2] & 0xffffffff, k[3] & 0xffffffff);
15680 if (TARGET_MINIMAL_TOC)
15681 fputs ("\t.long ", file);
15683 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15684 k[0] & 0xffffffff, k[1] & 0xffffffff,
15685 k[2] & 0xffffffff, k[3] & 0xffffffff);
15686 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15687 k[0] & 0xffffffff, k[1] & 0xffffffff,
15688 k[2] & 0xffffffff, k[3] & 0xffffffff);
15692 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
15694 REAL_VALUE_TYPE rv;
15697 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15698 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15702 if (TARGET_MINIMAL_TOC)
15703 fputs (DOUBLE_INT_ASM_OP, file);
15705 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15706 k[0] & 0xffffffff, k[1] & 0xffffffff);
15707 fprintf (file, "0x%lx%08lx\n",
15708 k[0] & 0xffffffff, k[1] & 0xffffffff);
15713 if (TARGET_MINIMAL_TOC)
15714 fputs ("\t.long ", file);
15716 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15717 k[0] & 0xffffffff, k[1] & 0xffffffff);
15718 fprintf (file, "0x%lx,0x%lx\n",
15719 k[0] & 0xffffffff, k[1] & 0xffffffff);
15723 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
15725 REAL_VALUE_TYPE rv;
15728 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15729 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15733 if (TARGET_MINIMAL_TOC)
15734 fputs (DOUBLE_INT_ASM_OP, file);
15736 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15737 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15742 if (TARGET_MINIMAL_TOC)
15743 fputs ("\t.long ", file);
15745 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15746 fprintf (file, "0x%lx\n", l & 0xffffffff);
15750 else if (GET_MODE (x) == VOIDmode
15751 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15753 unsigned HOST_WIDE_INT low;
15754 HOST_WIDE_INT high;
15756 if (GET_CODE (x) == CONST_DOUBLE)
15758 low = CONST_DOUBLE_LOW (x);
15759 high = CONST_DOUBLE_HIGH (x);
15762 #if HOST_BITS_PER_WIDE_INT == 32
15765 high = (low & 0x80000000) ? ~0 : 0;
15769 low = INTVAL (x) & 0xffffffff;
15770 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15774 /* TOC entries are always Pmode-sized, but since this
15775 is a bigendian machine then if we're putting smaller
15776 integer constants in the TOC we have to pad them.
15777 (This is still a win over putting the constants in
15778 a separate constant pool, because then we'd have
15779 to have both a TOC entry _and_ the actual constant.)
15781 For a 32-bit target, CONST_INT values are loaded and shifted
15782 entirely within `low' and can be stored in one TOC entry. */
15784 /* It would be easy to make this work, but it doesn't now. */
15785 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
15787 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15789 #if HOST_BITS_PER_WIDE_INT == 32
15790 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15791 POINTER_SIZE, &low, &high, 0);
15794 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15795 high = (HOST_WIDE_INT) low >> 32;
15802 if (TARGET_MINIMAL_TOC)
15803 fputs (DOUBLE_INT_ASM_OP, file);
15805 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15806 (long) high & 0xffffffff, (long) low & 0xffffffff);
15807 fprintf (file, "0x%lx%08lx\n",
15808 (long) high & 0xffffffff, (long) low & 0xffffffff);
15813 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15815 if (TARGET_MINIMAL_TOC)
15816 fputs ("\t.long ", file);
15818 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15819 (long) high & 0xffffffff, (long) low & 0xffffffff);
15820 fprintf (file, "0x%lx,0x%lx\n",
15821 (long) high & 0xffffffff, (long) low & 0xffffffff);
15825 if (TARGET_MINIMAL_TOC)
15826 fputs ("\t.long ", file);
15828 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15829 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15835 if (GET_CODE (x) == CONST)
15837 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
15839 base = XEXP (XEXP (x, 0), 0);
15840 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15843 switch (GET_CODE (base))
15846 name = XSTR (base, 0);
15850 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
15851 CODE_LABEL_NUMBER (XEXP (base, 0)));
15855 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15859 gcc_unreachable ();
15862 real_name = (*targetm.strip_name_encoding) (name);
15863 if (TARGET_MINIMAL_TOC)
15864 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15867 fprintf (file, "\t.tc %s", real_name);
15870 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
15872 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
15874 fputs ("[TC],", file);
15877 /* Currently C++ toc references to vtables can be emitted before it
15878 is decided whether the vtable is public or private. If this is
15879 the case, then the linker will eventually complain that there is
15880 a TOC reference to an unknown section. Thus, for vtables only,
15881 we emit the TOC reference to reference the symbol and not the
15883 if (VTABLE_NAME_P (name))
15885 RS6000_OUTPUT_BASENAME (file, name);
15887 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
15888 else if (offset > 0)
15889 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
15892 output_addr_const (file, x);
15896 /* Output an assembler pseudo-op to write an ASCII string of N characters
15897 starting at P to FILE.
15899 On the RS/6000, we have to do this using the .byte operation and
15900 write out special characters outside the quoted string.
15901 Also, the assembler is broken; very long strings are truncated,
15902 so we must artificially break them up early. */
15905 output_ascii (FILE *file, const char *p, int n)
15908 int i, count_string;
15909 const char *for_string = "\t.byte \"";
15910 const char *for_decimal = "\t.byte ";
15911 const char *to_close = NULL;
15914 for (i = 0; i < n; i++)
15917 if (c >= ' ' && c < 0177)
15920 fputs (for_string, file);
15923 /* Write two quotes to get one. */
15931 for_decimal = "\"\n\t.byte ";
15935 if (count_string >= 512)
15937 fputs (to_close, file);
15939 for_string = "\t.byte \"";
15940 for_decimal = "\t.byte ";
15948 fputs (for_decimal, file);
15949 fprintf (file, "%d", c);
15951 for_string = "\n\t.byte \"";
15952 for_decimal = ", ";
15958 /* Now close the string if we have written one. Then end the line. */
15960 fputs (to_close, file);
15963 /* Generate a unique section name for FILENAME for a section type
15964 represented by SECTION_DESC. Output goes into BUF.
15966 SECTION_DESC can be any string, as long as it is different for each
15967 possible section type.
15969 We name the section in the same manner as xlc. The name begins with an
15970 underscore followed by the filename (after stripping any leading directory
15971 names) with the last period replaced by the string SECTION_DESC. If
15972 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15976 rs6000_gen_section_name (char **buf, const char *filename,
15977 const char *section_desc)
15979 const char *q, *after_last_slash, *last_period = 0;
15983 after_last_slash = filename;
15984 for (q = filename; *q; q++)
15987 after_last_slash = q + 1;
15988 else if (*q == '.')
15992 len = strlen (after_last_slash) + strlen (section_desc) + 2;
15993 *buf = (char *) xmalloc (len);
15998 for (q = after_last_slash; *q; q++)
16000 if (q == last_period)
16002 strcpy (p, section_desc);
16003 p += strlen (section_desc);
16007 else if (ISALNUM (*q))
16011 if (last_period == 0)
16012 strcpy (p, section_desc);
16017 /* Emit profile function. */
16020 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16022 /* Non-standard profiling for kernels, which just saves LR then calls
16023 _mcount without worrying about arg saves. The idea is to change
16024 the function prologue as little as possible as it isn't easy to
16025 account for arg save/restore code added just for _mcount. */
16026 if (TARGET_PROFILE_KERNEL)
16029 if (DEFAULT_ABI == ABI_AIX)
16031 #ifndef NO_PROFILE_COUNTERS
16032 # define NO_PROFILE_COUNTERS 0
16034 if (NO_PROFILE_COUNTERS)
16035 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16039 const char *label_name;
16042 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16043 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16044 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16046 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16050 else if (DEFAULT_ABI == ABI_DARWIN)
16052 const char *mcount_name = RS6000_MCOUNT;
16053 int caller_addr_regno = LINK_REGISTER_REGNUM;
16055 /* Be conservative and always set this, at least for now. */
16056 current_function_uses_pic_offset_table = 1;
16059 /* For PIC code, set up a stub and collect the caller's address
16060 from r0, which is where the prologue puts it. */
16061 if (MACHOPIC_INDIRECT
16062 && current_function_uses_pic_offset_table)
16063 caller_addr_regno = 0;
16065 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16067 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16071 /* Write function profiler code. */
16074 output_function_profiler (FILE *file, int labelno)
16078 switch (DEFAULT_ABI)
16081 gcc_unreachable ();
16086 warning (0, "no profiling of 64-bit code for this ABI");
16089 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16090 fprintf (file, "\tmflr %s\n", reg_names[0]);
16091 if (NO_PROFILE_COUNTERS)
16093 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16094 reg_names[0], reg_names[1]);
16096 else if (TARGET_SECURE_PLT && flag_pic)
16098 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16099 reg_names[0], reg_names[1]);
16100 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16101 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16102 reg_names[12], reg_names[12]);
16103 assemble_name (file, buf);
16104 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16105 assemble_name (file, buf);
16106 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16108 else if (flag_pic == 1)
16110 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16111 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16112 reg_names[0], reg_names[1]);
16113 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16114 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16115 assemble_name (file, buf);
16116 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16118 else if (flag_pic > 1)
16120 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16121 reg_names[0], reg_names[1]);
16122 /* Now, we need to get the address of the label. */
16123 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16124 assemble_name (file, buf);
16125 fputs ("-.\n1:", file);
16126 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16127 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16128 reg_names[0], reg_names[11]);
16129 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16130 reg_names[0], reg_names[0], reg_names[11]);
16134 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16135 assemble_name (file, buf);
16136 fputs ("@ha\n", file);
16137 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16138 reg_names[0], reg_names[1]);
16139 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16140 assemble_name (file, buf);
16141 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16144 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16145 fprintf (file, "\tbl %s%s\n",
16146 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16151 if (!TARGET_PROFILE_KERNEL)
16153 /* Don't do anything, done in output_profile_hook (). */
16157 gcc_assert (!TARGET_32BIT);
16159 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16160 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16162 if (cfun->static_chain_decl != NULL)
16164 asm_fprintf (file, "\tstd %s,24(%s)\n",
16165 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16166 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16167 asm_fprintf (file, "\tld %s,24(%s)\n",
16168 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16171 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16178 /* Power4 load update and store update instructions are cracked into a
16179 load or store and an integer insn which are executed in the same cycle.
16180 Branches have their own dispatch slot which does not count against the
16181 GCC issue rate, but it changes the program flow so there are no other
16182 instructions to issue in this cycle. */
16185 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16186 int verbose ATTRIBUTE_UNUSED,
16187 rtx insn, int more)
16189 if (GET_CODE (PATTERN (insn)) == USE
16190 || GET_CODE (PATTERN (insn)) == CLOBBER)
16193 if (rs6000_sched_groups)
16195 if (is_microcoded_insn (insn))
16197 else if (is_cracked_insn (insn))
16198 return more > 2 ? more - 2 : 0;
16204 /* Adjust the cost of a scheduling dependency. Return the new cost of
16205 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16208 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16210 if (! recog_memoized (insn))
16213 if (REG_NOTE_KIND (link) != 0)
16216 if (REG_NOTE_KIND (link) == 0)
16218 /* Data dependency; DEP_INSN writes a register that INSN reads
16219 some cycles later. */
16221 /* Separate a load from a narrower, dependent store. */
16222 if (rs6000_sched_groups
16223 && GET_CODE (PATTERN (insn)) == SET
16224 && GET_CODE (PATTERN (dep_insn)) == SET
16225 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16226 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16227 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16228 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16231 switch (get_attr_type (insn))
16234 /* Tell the first scheduling pass about the latency between
16235 a mtctr and bctr (and mtlr and br/blr). The first
16236 scheduling pass will not know about this latency since
16237 the mtctr instruction, which has the latency associated
16238 to it, will be generated by reload. */
16239 return TARGET_POWER ? 5 : 4;
16241 /* Leave some extra cycles between a compare and its
16242 dependent branch, to inhibit expensive mispredicts. */
16243 if ((rs6000_cpu_attr == CPU_PPC603
16244 || rs6000_cpu_attr == CPU_PPC604
16245 || rs6000_cpu_attr == CPU_PPC604E
16246 || rs6000_cpu_attr == CPU_PPC620
16247 || rs6000_cpu_attr == CPU_PPC630
16248 || rs6000_cpu_attr == CPU_PPC750
16249 || rs6000_cpu_attr == CPU_PPC7400
16250 || rs6000_cpu_attr == CPU_PPC7450
16251 || rs6000_cpu_attr == CPU_POWER4
16252 || rs6000_cpu_attr == CPU_POWER5)
16253 && recog_memoized (dep_insn)
16254 && (INSN_CODE (dep_insn) >= 0)
16255 && (get_attr_type (dep_insn) == TYPE_CMP
16256 || get_attr_type (dep_insn) == TYPE_COMPARE
16257 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16258 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16259 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16260 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16261 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16262 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16267 /* Fall out to return default cost. */
16273 /* The function returns a true if INSN is microcoded.
16274 Return false otherwise. */
16277 is_microcoded_insn (rtx insn)
16279 if (!insn || !INSN_P (insn)
16280 || GET_CODE (PATTERN (insn)) == USE
16281 || GET_CODE (PATTERN (insn)) == CLOBBER)
16284 if (rs6000_sched_groups)
16286 enum attr_type type = get_attr_type (insn);
16287 if (type == TYPE_LOAD_EXT_U
16288 || type == TYPE_LOAD_EXT_UX
16289 || type == TYPE_LOAD_UX
16290 || type == TYPE_STORE_UX
16291 || type == TYPE_MFCR)
16298 /* The function returns a nonzero value if INSN can be scheduled only
16299 as the first insn in a dispatch group ("dispatch-slot restricted").
16300 In this case, the returned value indicates how many dispatch slots
16301 the insn occupies (at the beginning of the group).
16302 Return 0 otherwise. */
16305 is_dispatch_slot_restricted (rtx insn)
16307 enum attr_type type;
16309 if (!rs6000_sched_groups)
16313 || insn == NULL_RTX
16314 || GET_CODE (insn) == NOTE
16315 || GET_CODE (PATTERN (insn)) == USE
16316 || GET_CODE (PATTERN (insn)) == CLOBBER)
16319 type = get_attr_type (insn);
16326 case TYPE_DELAYED_CR:
16327 case TYPE_CR_LOGICAL:
16340 if (rs6000_cpu == PROCESSOR_POWER5
16341 && is_cracked_insn (insn))
16347 /* The function returns true if INSN is cracked into 2 instructions
16348 by the processor (and therefore occupies 2 issue slots). */
16351 is_cracked_insn (rtx insn)
16353 if (!insn || !INSN_P (insn)
16354 || GET_CODE (PATTERN (insn)) == USE
16355 || GET_CODE (PATTERN (insn)) == CLOBBER)
16358 if (rs6000_sched_groups)
16360 enum attr_type type = get_attr_type (insn);
16361 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16362 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16363 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16364 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16365 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16366 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16367 || type == TYPE_IDIV || type == TYPE_LDIV
16368 || type == TYPE_INSERT_WORD)
16375 /* The function returns true if INSN can be issued only from
16376 the branch slot. */
16379 is_branch_slot_insn (rtx insn)
16381 if (!insn || !INSN_P (insn)
16382 || GET_CODE (PATTERN (insn)) == USE
16383 || GET_CODE (PATTERN (insn)) == CLOBBER)
16386 if (rs6000_sched_groups)
16388 enum attr_type type = get_attr_type (insn);
16389 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16397 /* A C statement (sans semicolon) to update the integer scheduling
16398 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16399 INSN earlier, reduce the priority to execute INSN later. Do not
16400 define this macro if you do not need to adjust the scheduling
16401 priorities of insns. */
16404 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16406 /* On machines (like the 750) which have asymmetric integer units,
16407 where one integer unit can do multiply and divides and the other
16408 can't, reduce the priority of multiply/divide so it is scheduled
16409 before other integer operations. */
16412 if (! INSN_P (insn))
16415 if (GET_CODE (PATTERN (insn)) == USE)
16418 switch (rs6000_cpu_attr) {
16420 switch (get_attr_type (insn))
16427 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16428 priority, priority);
16429 if (priority >= 0 && priority < 0x01000000)
16436 if (is_dispatch_slot_restricted (insn)
16437 && reload_completed
16438 && current_sched_info->sched_max_insns_priority
16439 && rs6000_sched_restricted_insns_priority)
16442 /* Prioritize insns that can be dispatched only in the first
16444 if (rs6000_sched_restricted_insns_priority == 1)
16445 /* Attach highest priority to insn. This means that in
16446 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16447 precede 'priority' (critical path) considerations. */
16448 return current_sched_info->sched_max_insns_priority;
16449 else if (rs6000_sched_restricted_insns_priority == 2)
16450 /* Increase priority of insn by a minimal amount. This means that in
16451 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16452 considerations precede dispatch-slot restriction considerations. */
16453 return (priority + 1);
16459 /* Return how many instructions the machine can issue per cycle. */
16462 rs6000_issue_rate (void)
16464 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16465 if (!reload_completed)
16468 switch (rs6000_cpu_attr) {
16469 case CPU_RIOS1: /* ? */
16471 case CPU_PPC601: /* ? */
16494 /* Return how many instructions to look ahead for better insn
16498 rs6000_use_sched_lookahead (void)
16500 if (rs6000_cpu_attr == CPU_PPC8540)
16505 /* Determine is PAT refers to memory. */
16508 is_mem_ref (rtx pat)
16514 if (GET_CODE (pat) == MEM)
16517 /* Recursively process the pattern. */
16518 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16520 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16523 ret |= is_mem_ref (XEXP (pat, i));
16524 else if (fmt[i] == 'E')
16525 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16526 ret |= is_mem_ref (XVECEXP (pat, i, j));
16532 /* Determine if PAT is a PATTERN of a load insn. */
16535 is_load_insn1 (rtx pat)
16537 if (!pat || pat == NULL_RTX)
16540 if (GET_CODE (pat) == SET)
16541 return is_mem_ref (SET_SRC (pat));
16543 if (GET_CODE (pat) == PARALLEL)
16547 for (i = 0; i < XVECLEN (pat, 0); i++)
16548 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16555 /* Determine if INSN loads from memory. */
16558 is_load_insn (rtx insn)
16560 if (!insn || !INSN_P (insn))
16563 if (GET_CODE (insn) == CALL_INSN)
16566 return is_load_insn1 (PATTERN (insn));
16569 /* Determine if PAT is a PATTERN of a store insn. */
16572 is_store_insn1 (rtx pat)
16574 if (!pat || pat == NULL_RTX)
16577 if (GET_CODE (pat) == SET)
16578 return is_mem_ref (SET_DEST (pat));
16580 if (GET_CODE (pat) == PARALLEL)
16584 for (i = 0; i < XVECLEN (pat, 0); i++)
16585 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16592 /* Determine if INSN stores to memory. */
16595 is_store_insn (rtx insn)
16597 if (!insn || !INSN_P (insn))
16600 return is_store_insn1 (PATTERN (insn));
16603 /* Returns whether the dependence between INSN and NEXT is considered
16604 costly by the given target. */
16607 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16610 /* If the flag is not enabled - no dependence is considered costly;
16611 allow all dependent insns in the same group.
16612 This is the most aggressive option. */
16613 if (rs6000_sched_costly_dep == no_dep_costly)
16616 /* If the flag is set to 1 - a dependence is always considered costly;
16617 do not allow dependent instructions in the same group.
16618 This is the most conservative option. */
16619 if (rs6000_sched_costly_dep == all_deps_costly)
16622 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16623 && is_load_insn (next)
16624 && is_store_insn (insn))
16625 /* Prevent load after store in the same group. */
16628 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16629 && is_load_insn (next)
16630 && is_store_insn (insn)
16631 && (!link || (int) REG_NOTE_KIND (link) == 0))
16632 /* Prevent load after store in the same group if it is a true
16636 /* The flag is set to X; dependences with latency >= X are considered costly,
16637 and will not be scheduled in the same group. */
16638 if (rs6000_sched_costly_dep <= max_dep_latency
16639 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16645 /* Return the next insn after INSN that is found before TAIL is reached,
16646 skipping any "non-active" insns - insns that will not actually occupy
16647 an issue slot. Return NULL_RTX if such an insn is not found. */
16650 get_next_active_insn (rtx insn, rtx tail)
16652 if (insn == NULL_RTX || insn == tail)
16657 insn = NEXT_INSN (insn);
16658 if (insn == NULL_RTX || insn == tail)
16663 || (NONJUMP_INSN_P (insn)
16664 && GET_CODE (PATTERN (insn)) != USE
16665 && GET_CODE (PATTERN (insn)) != CLOBBER
16666 && INSN_CODE (insn) != CODE_FOR_stack_tie))
16672 /* Return whether the presence of INSN causes a dispatch group termination
16673 of group WHICH_GROUP.
16675 If WHICH_GROUP == current_group, this function will return true if INSN
16676 causes the termination of the current group (i.e, the dispatch group to
16677 which INSN belongs). This means that INSN will be the last insn in the
16678 group it belongs to.
16680 If WHICH_GROUP == previous_group, this function will return true if INSN
16681 causes the termination of the previous group (i.e, the dispatch group that
16682 precedes the group to which INSN belongs). This means that INSN will be
16683 the first insn in the group it belongs to). */
16686 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16688 enum attr_type type;
16693 type = get_attr_type (insn);
16695 if (is_microcoded_insn (insn))
16698 if (which_group == current_group)
16700 if (is_branch_slot_insn (insn))
16704 else if (which_group == previous_group)
16706 if (is_dispatch_slot_restricted (insn))
16714 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16715 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16718 is_costly_group (rtx *group_insns, rtx next_insn)
16723 int issue_rate = rs6000_issue_rate ();
16725 for (i = 0; i < issue_rate; i++)
16727 rtx insn = group_insns[i];
16730 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16732 rtx next = XEXP (link, 0);
16733 if (next == next_insn)
16735 cost = insn_cost (insn, link, next_insn);
16736 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16745 /* Utility of the function redefine_groups.
16746 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16747 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16748 to keep it "far" (in a separate group) from GROUP_INSNS, following
16749 one of the following schemes, depending on the value of the flag
16750 -minsert_sched_nops = X:
16751 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16752 in order to force NEXT_INSN into a separate group.
16753 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16754 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16755 insertion (has a group just ended, how many vacant issue slots remain in the
16756 last group, and how many dispatch groups were encountered so far). */
16759 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16760 rtx next_insn, bool *group_end, int can_issue_more,
16765 int issue_rate = rs6000_issue_rate ();
16766 bool end = *group_end;
16769 if (next_insn == NULL_RTX)
16770 return can_issue_more;
16772 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16773 return can_issue_more;
16775 force = is_costly_group (group_insns, next_insn);
16777 return can_issue_more;
16779 if (sched_verbose > 6)
16780 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16781 *group_count ,can_issue_more);
16783 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16786 can_issue_more = 0;
16788 /* Since only a branch can be issued in the last issue_slot, it is
16789 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16790 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16791 in this case the last nop will start a new group and the branch
16792 will be forced to the new group. */
16793 if (can_issue_more && !is_branch_slot_insn (next_insn))
16796 while (can_issue_more > 0)
16799 emit_insn_before (nop, next_insn);
16807 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16809 int n_nops = rs6000_sched_insert_nops;
16811 /* Nops can't be issued from the branch slot, so the effective
16812 issue_rate for nops is 'issue_rate - 1'. */
16813 if (can_issue_more == 0)
16814 can_issue_more = issue_rate;
16816 if (can_issue_more == 0)
16818 can_issue_more = issue_rate - 1;
16821 for (i = 0; i < issue_rate; i++)
16823 group_insns[i] = 0;
16830 emit_insn_before (nop, next_insn);
16831 if (can_issue_more == issue_rate - 1) /* new group begins */
16834 if (can_issue_more == 0)
16836 can_issue_more = issue_rate - 1;
16839 for (i = 0; i < issue_rate; i++)
16841 group_insns[i] = 0;
16847 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16850 /* Is next_insn going to start a new group? */
16853 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16854 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16855 || (can_issue_more < issue_rate &&
16856 insn_terminates_group_p (next_insn, previous_group)));
16857 if (*group_end && end)
16860 if (sched_verbose > 6)
16861 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16862 *group_count, can_issue_more);
16863 return can_issue_more;
16866 return can_issue_more;
16869 /* This function tries to synch the dispatch groups that the compiler "sees"
16870 with the dispatch groups that the processor dispatcher is expected to
16871 form in practice. It tries to achieve this synchronization by forcing the
16872 estimated processor grouping on the compiler (as opposed to the function
16873 'pad_goups' which tries to force the scheduler's grouping on the processor).
16875 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16876 examines the (estimated) dispatch groups that will be formed by the processor
16877 dispatcher. It marks these group boundaries to reflect the estimated
16878 processor grouping, overriding the grouping that the scheduler had marked.
16879 Depending on the value of the flag '-minsert-sched-nops' this function can
16880 force certain insns into separate groups or force a certain distance between
16881 them by inserting nops, for example, if there exists a "costly dependence"
16884 The function estimates the group boundaries that the processor will form as
16885 follows: It keeps track of how many vacant issue slots are available after
16886 each insn. A subsequent insn will start a new group if one of the following
16888 - no more vacant issue slots remain in the current dispatch group.
16889 - only the last issue slot, which is the branch slot, is vacant, but the next
16890 insn is not a branch.
16891 - only the last 2 or less issue slots, including the branch slot, are vacant,
16892 which means that a cracked insn (which occupies two issue slots) can't be
16893 issued in this group.
16894 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16895 start a new group. */
16898 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16900 rtx insn, next_insn;
16902 int can_issue_more;
16905 int group_count = 0;
16909 issue_rate = rs6000_issue_rate ();
16910 group_insns = alloca (issue_rate * sizeof (rtx));
16911 for (i = 0; i < issue_rate; i++)
16913 group_insns[i] = 0;
16915 can_issue_more = issue_rate;
16917 insn = get_next_active_insn (prev_head_insn, tail);
16920 while (insn != NULL_RTX)
16922 slot = (issue_rate - can_issue_more);
16923 group_insns[slot] = insn;
16925 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16926 if (insn_terminates_group_p (insn, current_group))
16927 can_issue_more = 0;
16929 next_insn = get_next_active_insn (insn, tail);
16930 if (next_insn == NULL_RTX)
16931 return group_count + 1;
16933 /* Is next_insn going to start a new group? */
16935 = (can_issue_more == 0
16936 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16937 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16938 || (can_issue_more < issue_rate &&
16939 insn_terminates_group_p (next_insn, previous_group)));
16941 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
16942 next_insn, &group_end, can_issue_more,
16948 can_issue_more = 0;
16949 for (i = 0; i < issue_rate; i++)
16951 group_insns[i] = 0;
16955 if (GET_MODE (next_insn) == TImode && can_issue_more)
16956 PUT_MODE (next_insn, VOIDmode);
16957 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
16958 PUT_MODE (next_insn, TImode);
16961 if (can_issue_more == 0)
16962 can_issue_more = issue_rate;
16965 return group_count;
16968 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16969 dispatch group boundaries that the scheduler had marked. Pad with nops
16970 any dispatch groups which have vacant issue slots, in order to force the
16971 scheduler's grouping on the processor dispatcher. The function
16972 returns the number of dispatch groups found. */
16975 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16977 rtx insn, next_insn;
16980 int can_issue_more;
16982 int group_count = 0;
16984 /* Initialize issue_rate. */
16985 issue_rate = rs6000_issue_rate ();
16986 can_issue_more = issue_rate;
16988 insn = get_next_active_insn (prev_head_insn, tail);
16989 next_insn = get_next_active_insn (insn, tail);
16991 while (insn != NULL_RTX)
16994 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16996 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16998 if (next_insn == NULL_RTX)
17003 /* If the scheduler had marked group termination at this location
17004 (between insn and next_indn), and neither insn nor next_insn will
17005 force group termination, pad the group with nops to force group
17008 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
17009 && !insn_terminates_group_p (insn, current_group)
17010 && !insn_terminates_group_p (next_insn, previous_group))
17012 if (!is_branch_slot_insn (next_insn))
17015 while (can_issue_more)
17018 emit_insn_before (nop, next_insn);
17023 can_issue_more = issue_rate;
17028 next_insn = get_next_active_insn (insn, tail);
17031 return group_count;
17034 /* The following function is called at the end of scheduling BB.
17035 After reload, it inserts nops at insn group bundling. */
17038 rs6000_sched_finish (FILE *dump, int sched_verbose)
17043 fprintf (dump, "=== Finishing schedule.\n");
17045 if (reload_completed && rs6000_sched_groups)
17047 if (rs6000_sched_insert_nops == sched_finish_none)
17050 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17051 n_groups = pad_groups (dump, sched_verbose,
17052 current_sched_info->prev_head,
17053 current_sched_info->next_tail);
17055 n_groups = redefine_groups (dump, sched_verbose,
17056 current_sched_info->prev_head,
17057 current_sched_info->next_tail);
17059 if (sched_verbose >= 6)
17061 fprintf (dump, "ngroups = %d\n", n_groups);
17062 print_rtl (dump, current_sched_info->prev_head);
17063 fprintf (dump, "Done finish_sched\n");
17068 /* Length in units of the trampoline for entering a nested function. */
17071 rs6000_trampoline_size (void)
17075 switch (DEFAULT_ABI)
17078 gcc_unreachable ();
17081 ret = (TARGET_32BIT) ? 12 : 24;
17086 ret = (TARGET_32BIT) ? 40 : 48;
17093 /* Emit RTL insns to initialize the variable parts of a trampoline.
17094 FNADDR is an RTX for the address of the function's pure code.
17095 CXT is an RTX for the static chain value for the function. */
17098 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17100 enum machine_mode pmode = Pmode;
17101 int regsize = (TARGET_32BIT) ? 4 : 8;
17102 rtx ctx_reg = force_reg (pmode, cxt);
17104 switch (DEFAULT_ABI)
17107 gcc_unreachable ();
17109 /* Macros to shorten the code expansions below. */
17110 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17111 #define MEM_PLUS(addr,offset) \
17112 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17114 /* Under AIX, just build the 3 word function descriptor */
17117 rtx fn_reg = gen_reg_rtx (pmode);
17118 rtx toc_reg = gen_reg_rtx (pmode);
17119 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17120 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17121 emit_move_insn (MEM_DEREF (addr), fn_reg);
17122 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17123 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17127 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17130 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
17131 FALSE, VOIDmode, 4,
17133 GEN_INT (rs6000_trampoline_size ()), SImode,
17143 /* Table of valid machine attributes. */
17145 const struct attribute_spec rs6000_attribute_table[] =
17147 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17148 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17149 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17150 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17151 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17152 SUBTARGET_ATTRIBUTE_TABLE,
17154 { NULL, 0, 0, false, false, false, NULL }
17157 /* Handle the "altivec" attribute. The attribute may have
17158 arguments as follows:
17160 __attribute__((altivec(vector__)))
17161 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17162 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17164 and may appear more than once (e.g., 'vector bool char') in a
17165 given declaration. */
17168 rs6000_handle_altivec_attribute (tree *node,
17169 tree name ATTRIBUTE_UNUSED,
17171 int flags ATTRIBUTE_UNUSED,
17172 bool *no_add_attrs)
17174 tree type = *node, result = NULL_TREE;
17175 enum machine_mode mode;
17178 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17179 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17180 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17183 while (POINTER_TYPE_P (type)
17184 || TREE_CODE (type) == FUNCTION_TYPE
17185 || TREE_CODE (type) == METHOD_TYPE
17186 || TREE_CODE (type) == ARRAY_TYPE)
17187 type = TREE_TYPE (type);
17189 mode = TYPE_MODE (type);
17191 /* Check for invalid AltiVec type qualifiers. */
17192 if (type == long_unsigned_type_node || type == long_integer_type_node)
17195 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17196 else if (rs6000_warn_altivec_long)
17197 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17199 else if (type == long_long_unsigned_type_node
17200 || type == long_long_integer_type_node)
17201 error ("use of %<long long%> in AltiVec types is invalid");
17202 else if (type == double_type_node)
17203 error ("use of %<double%> in AltiVec types is invalid");
17204 else if (type == long_double_type_node)
17205 error ("use of %<long double%> in AltiVec types is invalid");
17206 else if (type == boolean_type_node)
17207 error ("use of boolean types in AltiVec types is invalid");
17208 else if (TREE_CODE (type) == COMPLEX_TYPE)
17209 error ("use of %<complex%> in AltiVec types is invalid");
17211 switch (altivec_type)
17214 unsigned_p = TYPE_UNSIGNED (type);
17218 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17221 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17224 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17226 case SFmode: result = V4SF_type_node; break;
17227 /* If the user says 'vector int bool', we may be handed the 'bool'
17228 attribute _before_ the 'vector' attribute, and so select the
17229 proper type in the 'b' case below. */
17230 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17238 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17239 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17240 case QImode: case V16QImode: result = bool_V16QI_type_node;
17247 case V8HImode: result = pixel_V8HI_type_node;
17253 if (result && result != type && TYPE_READONLY (type))
17254 result = build_qualified_type (result, TYPE_QUAL_CONST);
17256 *no_add_attrs = true; /* No need to hang on to the attribute. */
17259 *node = reconstruct_complex_type (*node, result);
17264 /* AltiVec defines four built-in scalar types that serve as vector
17265 elements; we must teach the compiler how to mangle them. */
17267 static const char *
17268 rs6000_mangle_fundamental_type (tree type)
17270 if (type == bool_char_type_node) return "U6__boolc";
17271 if (type == bool_short_type_node) return "U6__bools";
17272 if (type == pixel_type_node) return "u7__pixel";
17273 if (type == bool_int_type_node) return "U6__booli";
17275 /* For all other types, use normal C++ mangling. */
17279 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17280 struct attribute_spec.handler. */
17283 rs6000_handle_longcall_attribute (tree *node, tree name,
17284 tree args ATTRIBUTE_UNUSED,
17285 int flags ATTRIBUTE_UNUSED,
17286 bool *no_add_attrs)
17288 if (TREE_CODE (*node) != FUNCTION_TYPE
17289 && TREE_CODE (*node) != FIELD_DECL
17290 && TREE_CODE (*node) != TYPE_DECL)
17292 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17293 IDENTIFIER_POINTER (name));
17294 *no_add_attrs = true;
17300 /* Set longcall attributes on all functions declared when
17301 rs6000_default_long_calls is true. */
17303 rs6000_set_default_type_attributes (tree type)
17305 if (rs6000_default_long_calls
17306 && (TREE_CODE (type) == FUNCTION_TYPE
17307 || TREE_CODE (type) == METHOD_TYPE))
17308 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17310 TYPE_ATTRIBUTES (type));
17313 /* Return a reference suitable for calling a function with the
17314 longcall attribute. */
17317 rs6000_longcall_ref (rtx call_ref)
17319 const char *call_name;
17322 if (GET_CODE (call_ref) != SYMBOL_REF)
17325 /* System V adds '.' to the internal name, so skip them. */
17326 call_name = XSTR (call_ref, 0);
17327 if (*call_name == '.')
17329 while (*call_name == '.')
17332 node = get_identifier (call_name);
17333 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17336 return force_reg (Pmode, call_ref);
17339 #ifdef USING_ELFOS_H
17341 /* A get_unnamed_section callback, used for switching to toc_section. */
17344 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
17346 if (DEFAULT_ABI == ABI_AIX
17347 && TARGET_MINIMAL_TOC
17348 && !TARGET_RELOCATABLE)
17350 if (!toc_initialized)
17352 toc_initialized = 1;
17353 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17354 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
17355 fprintf (asm_out_file, "\t.tc ");
17356 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
17357 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17358 fprintf (asm_out_file, "\n");
17360 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17361 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17362 fprintf (asm_out_file, " = .+32768\n");
17365 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17367 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
17368 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17371 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17372 if (!toc_initialized)
17374 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17375 fprintf (asm_out_file, " = .+32768\n");
17376 toc_initialized = 1;
17381 /* Implement TARGET_ASM_INIT_SECTIONS. */
17384 rs6000_elf_asm_init_sections (void)
17387 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
17390 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
17391 SDATA2_SECTION_ASM_OP);
17394 /* Implement TARGET_SELECT_RTX_SECTION. */
17397 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17398 unsigned HOST_WIDE_INT align)
17400 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17401 return toc_section;
17403 return default_elf_select_rtx_section (mode, x, align);
17406 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
17409 rs6000_elf_select_section (tree decl, int reloc,
17410 unsigned HOST_WIDE_INT align)
17412 /* Pretend that we're always building for a shared library when
17413 ABI_AIX, because otherwise we end up with dynamic relocations
17414 in read-only sections. This happens for function pointers,
17415 references to vtables in typeinfo, and probably other cases. */
17416 return default_elf_select_section_1 (decl, reloc, align,
17417 flag_pic || DEFAULT_ABI == ABI_AIX);
17420 /* A C statement to build up a unique section name, expressed as a
17421 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17422 RELOC indicates whether the initial value of EXP requires
17423 link-time relocations. If you do not define this macro, GCC will use
17424 the symbol name prefixed by `.' as the section name. Note - this
17425 macro can now be called for uninitialized data items as well as
17426 initialized data and functions. */
17429 rs6000_elf_unique_section (tree decl, int reloc)
17431 /* As above, pretend that we're always building for a shared library
17432 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17433 default_unique_section_1 (decl, reloc,
17434 flag_pic || DEFAULT_ABI == ABI_AIX);
17437 /* For a SYMBOL_REF, set generic flags and then perform some
17438 target-specific processing.
17440 When the AIX ABI is requested on a non-AIX system, replace the
17441 function name with the real name (with a leading .) rather than the
17442 function descriptor name. This saves a lot of overriding code to
17443 read the prefixes. */
17446 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17448 default_encode_section_info (decl, rtl, first);
17451 && TREE_CODE (decl) == FUNCTION_DECL
17453 && DEFAULT_ABI == ABI_AIX)
17455 rtx sym_ref = XEXP (rtl, 0);
17456 size_t len = strlen (XSTR (sym_ref, 0));
17457 char *str = alloca (len + 2);
17459 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17460 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17465 rs6000_elf_in_small_data_p (tree decl)
17467 if (rs6000_sdata == SDATA_NONE)
17470 /* We want to merge strings, so we never consider them small data. */
17471 if (TREE_CODE (decl) == STRING_CST)
17474 /* Functions are never in the small data area. */
17475 if (TREE_CODE (decl) == FUNCTION_DECL)
17478 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17480 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17481 if (strcmp (section, ".sdata") == 0
17482 || strcmp (section, ".sdata2") == 0
17483 || strcmp (section, ".sbss") == 0
17484 || strcmp (section, ".sbss2") == 0
17485 || strcmp (section, ".PPC.EMB.sdata0") == 0
17486 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17491 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17494 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17495 /* If it's not public, and we're not going to reference it there,
17496 there's no need to put it in the small data section. */
17497 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17504 #endif /* USING_ELFOS_H */
17507 /* Return a REG that occurs in ADDR with coefficient 1.
17508 ADDR can be effectively incremented by incrementing REG.
17510 r0 is special and we must not select it as an address
17511 register by this routine since our caller will try to
17512 increment the returned register via an "la" instruction. */
17515 find_addr_reg (rtx addr)
17517 while (GET_CODE (addr) == PLUS)
17519 if (GET_CODE (XEXP (addr, 0)) == REG
17520 && REGNO (XEXP (addr, 0)) != 0)
17521 addr = XEXP (addr, 0);
17522 else if (GET_CODE (XEXP (addr, 1)) == REG
17523 && REGNO (XEXP (addr, 1)) != 0)
17524 addr = XEXP (addr, 1);
17525 else if (CONSTANT_P (XEXP (addr, 0)))
17526 addr = XEXP (addr, 1);
17527 else if (CONSTANT_P (XEXP (addr, 1)))
17528 addr = XEXP (addr, 0);
17530 gcc_unreachable ();
17532 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17537 rs6000_fatal_bad_address (rtx op)
17539 fatal_insn ("bad address", op);
17544 static tree branch_island_list = 0;
17546 /* Remember to generate a branch island for far calls to the given
17550 add_compiler_branch_island (tree label_name, tree function_name,
17553 tree branch_island = build_tree_list (function_name, label_name);
17554 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17555 TREE_CHAIN (branch_island) = branch_island_list;
17556 branch_island_list = branch_island;
17559 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17560 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17561 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17562 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17564 /* Generate far-jump branch islands for everything on the
17565 branch_island_list. Invoked immediately after the last instruction
17566 of the epilogue has been emitted; the branch-islands must be
17567 appended to, and contiguous with, the function body. Mach-O stubs
17568 are generated in machopic_output_stub(). */
17571 macho_branch_islands (void)
17574 tree branch_island;
17576 for (branch_island = branch_island_list;
17578 branch_island = TREE_CHAIN (branch_island))
17580 const char *label =
17581 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17583 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17584 char name_buf[512];
17585 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17586 if (name[0] == '*' || name[0] == '&')
17587 strcpy (name_buf, name+1);
17591 strcpy (name_buf+1, name);
17593 strcpy (tmp_buf, "\n");
17594 strcat (tmp_buf, label);
17595 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17596 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17597 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17598 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17601 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17602 strcat (tmp_buf, label);
17603 strcat (tmp_buf, "_pic\n");
17604 strcat (tmp_buf, label);
17605 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17607 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17608 strcat (tmp_buf, name_buf);
17609 strcat (tmp_buf, " - ");
17610 strcat (tmp_buf, label);
17611 strcat (tmp_buf, "_pic)\n");
17613 strcat (tmp_buf, "\tmtlr r0\n");
17615 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17616 strcat (tmp_buf, name_buf);
17617 strcat (tmp_buf, " - ");
17618 strcat (tmp_buf, label);
17619 strcat (tmp_buf, "_pic)\n");
17621 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17625 strcat (tmp_buf, ":\nlis r12,hi16(");
17626 strcat (tmp_buf, name_buf);
17627 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17628 strcat (tmp_buf, name_buf);
17629 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17631 output_asm_insn (tmp_buf, 0);
17632 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17633 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17634 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17635 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17638 branch_island_list = 0;
17641 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17642 already there or not. */
17645 no_previous_def (tree function_name)
17647 tree branch_island;
17648 for (branch_island = branch_island_list;
17650 branch_island = TREE_CHAIN (branch_island))
17651 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17656 /* GET_PREV_LABEL gets the label name from the previous definition of
17660 get_prev_label (tree function_name)
17662 tree branch_island;
17663 for (branch_island = branch_island_list;
17665 branch_island = TREE_CHAIN (branch_island))
17666 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17667 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17671 /* INSN is either a function call or a millicode call. It may have an
17672 unconditional jump in its delay slot.
17674 CALL_DEST is the routine we are calling. */
17677 output_call (rtx insn, rtx *operands, int dest_operand_number,
17678 int cookie_operand_number)
17680 static char buf[256];
17681 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17682 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17685 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17687 if (no_previous_def (funname))
17689 int line_number = 0;
17690 rtx label_rtx = gen_label_rtx ();
17691 char *label_buf, temp_buf[256];
17692 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17693 CODE_LABEL_NUMBER (label_rtx));
17694 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17695 labelname = get_identifier (label_buf);
17696 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17698 line_number = NOTE_LINE_NUMBER (insn);
17699 add_compiler_branch_island (labelname, funname, line_number);
17702 labelname = get_prev_label (funname);
17704 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17705 instruction will reach 'foo', otherwise link as 'bl L42'".
17706 "L42" should be a 'branch island', that will do a far jump to
17707 'foo'. Branch islands are generated in
17708 macho_branch_islands(). */
17709 sprintf (buf, "jbsr %%z%d,%.246s",
17710 dest_operand_number, IDENTIFIER_POINTER (labelname));
17713 sprintf (buf, "bl %%z%d", dest_operand_number);
17717 /* Generate PIC and indirect symbol stubs. */
17720 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17722 unsigned int length;
17723 char *symbol_name, *lazy_ptr_name;
17724 char *local_label_0;
17725 static int label = 0;
17727 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17728 symb = (*targetm.strip_name_encoding) (symb);
17731 length = strlen (symb);
17732 symbol_name = alloca (length + 32);
17733 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17735 lazy_ptr_name = alloca (length + 32);
17736 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17739 switch_to_section (machopic_picsymbol_stub1_section);
17741 switch_to_section (machopic_symbol_stub1_section);
17745 fprintf (file, "\t.align 5\n");
17747 fprintf (file, "%s:\n", stub);
17748 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17751 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
17752 sprintf (local_label_0, "\"L%011d$spb\"", label);
17754 fprintf (file, "\tmflr r0\n");
17755 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17756 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17757 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17758 lazy_ptr_name, local_label_0);
17759 fprintf (file, "\tmtlr r0\n");
17760 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17761 (TARGET_64BIT ? "ldu" : "lwzu"),
17762 lazy_ptr_name, local_label_0);
17763 fprintf (file, "\tmtctr r12\n");
17764 fprintf (file, "\tbctr\n");
17768 fprintf (file, "\t.align 4\n");
17770 fprintf (file, "%s:\n", stub);
17771 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17773 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17774 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17775 (TARGET_64BIT ? "ldu" : "lwzu"),
17777 fprintf (file, "\tmtctr r12\n");
17778 fprintf (file, "\tbctr\n");
17781 switch_to_section (machopic_lazy_symbol_ptr_section);
17782 fprintf (file, "%s:\n", lazy_ptr_name);
17783 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17784 fprintf (file, "%sdyld_stub_binding_helper\n",
17785 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17788 /* Legitimize PIC addresses. If the address is already
17789 position-independent, we return ORIG. Newly generated
17790 position-independent addresses go into a reg. This is REG if non
17791 zero, otherwise we allocate register(s) as necessary. */
17793 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
17796 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17801 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17802 reg = gen_reg_rtx (Pmode);
17804 if (GET_CODE (orig) == CONST)
17808 if (GET_CODE (XEXP (orig, 0)) == PLUS
17809 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17812 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
17814 /* Use a different reg for the intermediate value, as
17815 it will be marked UNCHANGING. */
17816 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17817 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17820 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17823 if (GET_CODE (offset) == CONST_INT)
17825 if (SMALL_INT (offset))
17826 return plus_constant (base, INTVAL (offset));
17827 else if (! reload_in_progress && ! reload_completed)
17828 offset = force_reg (Pmode, offset);
17831 rtx mem = force_const_mem (Pmode, orig);
17832 return machopic_legitimize_pic_address (mem, Pmode, reg);
17835 return gen_rtx_PLUS (Pmode, base, offset);
17838 /* Fall back on generic machopic code. */
17839 return machopic_legitimize_pic_address (orig, mode, reg);
17842 /* Output a .machine directive for the Darwin assembler, and call
17843 the generic start_file routine. */
17846 rs6000_darwin_file_start (void)
17848 static const struct
17854 { "ppc64", "ppc64", MASK_64BIT },
17855 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17856 { "power4", "ppc970", 0 },
17857 { "G5", "ppc970", 0 },
17858 { "7450", "ppc7450", 0 },
17859 { "7400", "ppc7400", MASK_ALTIVEC },
17860 { "G4", "ppc7400", 0 },
17861 { "750", "ppc750", 0 },
17862 { "740", "ppc750", 0 },
17863 { "G3", "ppc750", 0 },
17864 { "604e", "ppc604e", 0 },
17865 { "604", "ppc604", 0 },
17866 { "603e", "ppc603", 0 },
17867 { "603", "ppc603", 0 },
17868 { "601", "ppc601", 0 },
17869 { NULL, "ppc", 0 } };
17870 const char *cpu_id = "";
17873 rs6000_file_start ();
17875 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17876 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17877 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17878 && rs6000_select[i].string[0] != '\0')
17879 cpu_id = rs6000_select[i].string;
17881 /* Look through the mapping array. Pick the first name that either
17882 matches the argument, has a bit set in IF_SET that is also set
17883 in the target flags, or has a NULL name. */
17886 while (mapping[i].arg != NULL
17887 && strcmp (mapping[i].arg, cpu_id) != 0
17888 && (mapping[i].if_set & target_flags) == 0)
17891 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17894 #endif /* TARGET_MACHO */
17897 static unsigned int
17898 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
17900 return default_section_type_flags_1 (decl, name, reloc,
17901 flag_pic || DEFAULT_ABI == ABI_AIX);
17904 /* Record an element in the table of global constructors. SYMBOL is
17905 a SYMBOL_REF of the function to be called; PRIORITY is a number
17906 between 0 and MAX_INIT_PRIORITY.
17908 This differs from default_named_section_asm_out_constructor in
17909 that we have special handling for -mrelocatable. */
17912 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
17914 const char *section = ".ctors";
17917 if (priority != DEFAULT_INIT_PRIORITY)
17919 sprintf (buf, ".ctors.%.5u",
17920 /* Invert the numbering so the linker puts us in the proper
17921 order; constructors are run from right to left, and the
17922 linker sorts in increasing order. */
17923 MAX_INIT_PRIORITY - priority);
17927 switch_to_section (get_section (section, SECTION_WRITE, NULL));
17928 assemble_align (POINTER_SIZE);
17930 if (TARGET_RELOCATABLE)
17932 fputs ("\t.long (", asm_out_file);
17933 output_addr_const (asm_out_file, symbol);
17934 fputs (")@fixup\n", asm_out_file);
17937 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17941 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
17943 const char *section = ".dtors";
17946 if (priority != DEFAULT_INIT_PRIORITY)
17948 sprintf (buf, ".dtors.%.5u",
17949 /* Invert the numbering so the linker puts us in the proper
17950 order; constructors are run from right to left, and the
17951 linker sorts in increasing order. */
17952 MAX_INIT_PRIORITY - priority);
17956 switch_to_section (get_section (section, SECTION_WRITE, NULL));
17957 assemble_align (POINTER_SIZE);
17959 if (TARGET_RELOCATABLE)
17961 fputs ("\t.long (", asm_out_file);
17962 output_addr_const (asm_out_file, symbol);
17963 fputs (")@fixup\n", asm_out_file);
17966 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17970 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
17974 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17975 ASM_OUTPUT_LABEL (file, name);
17976 fputs (DOUBLE_INT_ASM_OP, file);
17977 rs6000_output_function_entry (file, name);
17978 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17981 fputs ("\t.size\t", file);
17982 assemble_name (file, name);
17983 fputs (",24\n\t.type\t.", file);
17984 assemble_name (file, name);
17985 fputs (",@function\n", file);
17986 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17988 fputs ("\t.globl\t.", file);
17989 assemble_name (file, name);
17994 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17995 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17996 rs6000_output_function_entry (file, name);
17997 fputs (":\n", file);
18001 if (TARGET_RELOCATABLE
18002 && !TARGET_SECURE_PLT
18003 && (get_pool_size () != 0 || current_function_profile)
18008 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
18010 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18011 fprintf (file, "\t.long ");
18012 assemble_name (file, buf);
18014 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18015 assemble_name (file, buf);
18019 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18020 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18022 if (DEFAULT_ABI == ABI_AIX)
18024 const char *desc_name, *orig_name;
18026 orig_name = (*targetm.strip_name_encoding) (name);
18027 desc_name = orig_name;
18028 while (*desc_name == '.')
18031 if (TREE_PUBLIC (decl))
18032 fprintf (file, "\t.globl %s\n", desc_name);
18034 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18035 fprintf (file, "%s:\n", desc_name);
18036 fprintf (file, "\t.long %s\n", orig_name);
18037 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
18038 if (DEFAULT_ABI == ABI_AIX)
18039 fputs ("\t.long 0\n", file);
18040 fprintf (file, "\t.previous\n");
18042 ASM_OUTPUT_LABEL (file, name);
18046 rs6000_elf_end_indicate_exec_stack (void)
18049 file_end_indicate_exec_stack ();
18055 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18057 fputs (GLOBAL_ASM_OP, stream);
18058 RS6000_OUTPUT_BASENAME (stream, name);
18059 putc ('\n', stream);
18062 /* A get_unnamed_decl callback, used for read-only sections. PTR
18063 points to the section string variable. */
18066 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
18068 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
18069 *(const char *const *) directive);
18072 /* Likewise for read-write sections. */
18075 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
18077 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
18078 *(const char *const *) directive);
18081 /* A get_unnamed_section callback, used for switching to toc_section. */
18084 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18086 if (TARGET_MINIMAL_TOC)
18088 /* toc_section is always selected at least once from
18089 rs6000_xcoff_file_start, so this is guaranteed to
18090 always be defined once and only once in each file. */
18091 if (!toc_initialized)
18093 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
18094 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
18095 toc_initialized = 1;
18097 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
18098 (TARGET_32BIT ? "" : ",3"));
18101 fputs ("\t.toc\n", asm_out_file);
18104 /* Implement TARGET_ASM_INIT_SECTIONS. */
18107 rs6000_xcoff_asm_init_sections (void)
18109 read_only_data_section
18110 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18111 &xcoff_read_only_section_name);
18113 private_data_section
18114 = get_unnamed_section (SECTION_WRITE,
18115 rs6000_xcoff_output_readwrite_section_asm_op,
18116 &xcoff_private_data_section_name);
18118 read_only_private_data_section
18119 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18120 &xcoff_private_data_section_name);
18123 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
18125 readonly_data_section = read_only_data_section;
18126 exception_section = data_section;
18130 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18131 tree decl ATTRIBUTE_UNUSED)
18134 static const char * const suffix[3] = { "PR", "RO", "RW" };
18136 if (flags & SECTION_CODE)
18138 else if (flags & SECTION_WRITE)
18143 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18144 (flags & SECTION_CODE) ? "." : "",
18145 name, suffix[smclass], flags & SECTION_ENTSIZE);
18149 rs6000_xcoff_select_section (tree decl, int reloc,
18150 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18152 if (decl_readonly_section_1 (decl, reloc, 1))
18154 if (TREE_PUBLIC (decl))
18155 return read_only_data_section;
18157 return read_only_private_data_section;
18161 if (TREE_PUBLIC (decl))
18162 return data_section;
18164 return private_data_section;
18169 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18173 /* Use select_section for private and uninitialized data. */
18174 if (!TREE_PUBLIC (decl)
18175 || DECL_COMMON (decl)
18176 || DECL_INITIAL (decl) == NULL_TREE
18177 || DECL_INITIAL (decl) == error_mark_node
18178 || (flag_zero_initialized_in_bss
18179 && initializer_zerop (DECL_INITIAL (decl))))
18182 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18183 name = (*targetm.strip_name_encoding) (name);
18184 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18187 /* Select section for constant in constant pool.
18189 On RS/6000, all constants are in the private read-only data area.
18190 However, if this is being placed in the TOC it must be output as a
18194 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18195 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18197 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18198 return toc_section;
18200 return read_only_private_data_section;
18203 /* Remove any trailing [DS] or the like from the symbol name. */
18205 static const char *
18206 rs6000_xcoff_strip_name_encoding (const char *name)
18211 len = strlen (name);
18212 if (name[len - 1] == ']')
18213 return ggc_alloc_string (name, len - 4);
18218 /* Section attributes. AIX is always PIC. */
18220 static unsigned int
18221 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18223 unsigned int align;
18224 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18226 /* Align to at least UNIT size. */
18227 if (flags & SECTION_CODE)
18228 align = MIN_UNITS_PER_WORD;
18230 /* Increase alignment of large objects if not already stricter. */
18231 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18232 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18233 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18235 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18238 /* Output at beginning of assembler file.
18240 Initialize the section names for the RS/6000 at this point.
18242 Specify filename, including full path, to assembler.
18244 We want to go into the TOC section so at least one .toc will be emitted.
18245 Also, in order to output proper .bs/.es pairs, we need at least one static
18246 [RW] section emitted.
18248 Finally, declare mcount when profiling to make the assembler happy. */
18251 rs6000_xcoff_file_start (void)
18253 rs6000_gen_section_name (&xcoff_bss_section_name,
18254 main_input_filename, ".bss_");
18255 rs6000_gen_section_name (&xcoff_private_data_section_name,
18256 main_input_filename, ".rw_");
18257 rs6000_gen_section_name (&xcoff_read_only_section_name,
18258 main_input_filename, ".ro_");
18260 fputs ("\t.file\t", asm_out_file);
18261 output_quoted_string (asm_out_file, main_input_filename);
18262 fputc ('\n', asm_out_file);
18263 if (write_symbols != NO_DEBUG)
18264 switch_to_section (private_data_section);
18265 switch_to_section (text_section);
18267 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18268 rs6000_file_start ();
18271 /* Output at end of assembler file.
18272 On the RS/6000, referencing data should automatically pull in text. */
18275 rs6000_xcoff_file_end (void)
18277 switch_to_section (text_section);
18278 fputs ("_section_.text:\n", asm_out_file);
18279 switch_to_section (data_section);
18280 fputs (TARGET_32BIT
18281 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18284 #endif /* TARGET_XCOFF */
18286 /* Compute a (partial) cost for rtx X. Return true if the complete
18287 cost has been computed, and false if subexpressions should be
18288 scanned. In either case, *TOTAL contains the cost result. */
18291 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18293 enum machine_mode mode = GET_MODE (x);
18297 /* On the RS/6000, if it is valid in the insn, it is free. */
18299 if (((outer_code == SET
18300 || outer_code == PLUS
18301 || outer_code == MINUS)
18302 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18303 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
18304 || (outer_code == AND
18305 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18306 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18307 mode == SImode ? 'L' : 'J'))
18308 || mask_operand (x, mode)
18310 && mask64_operand (x, DImode))))
18311 || ((outer_code == IOR || outer_code == XOR)
18312 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18313 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18314 mode == SImode ? 'L' : 'J'))))
18315 || outer_code == ASHIFT
18316 || outer_code == ASHIFTRT
18317 || outer_code == LSHIFTRT
18318 || outer_code == ROTATE
18319 || outer_code == ROTATERT
18320 || outer_code == ZERO_EXTRACT
18321 || (outer_code == MULT
18322 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18323 || ((outer_code == DIV || outer_code == UDIV
18324 || outer_code == MOD || outer_code == UMOD)
18325 && exact_log2 (INTVAL (x)) >= 0)
18326 || (outer_code == COMPARE
18327 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18328 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
18329 || (outer_code == EQ
18330 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18331 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18332 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18333 mode == SImode ? 'L' : 'J'))))
18334 || (outer_code == GTU
18335 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18336 || (outer_code == LTU
18337 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
18342 else if ((outer_code == PLUS
18343 && reg_or_add_cint_operand (x, VOIDmode))
18344 || (outer_code == MINUS
18345 && reg_or_sub_cint_operand (x, VOIDmode))
18346 || ((outer_code == SET
18347 || outer_code == IOR
18348 || outer_code == XOR)
18350 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18352 *total = COSTS_N_INSNS (1);
18359 && ((outer_code == AND
18360 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18361 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
18362 || mask_operand (x, DImode)
18363 || mask64_operand (x, DImode)))
18364 || ((outer_code == IOR || outer_code == XOR)
18365 && CONST_DOUBLE_HIGH (x) == 0
18366 && (CONST_DOUBLE_LOW (x)
18367 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18372 else if (mode == DImode
18373 && (outer_code == SET
18374 || outer_code == IOR
18375 || outer_code == XOR)
18376 && CONST_DOUBLE_HIGH (x) == 0)
18378 *total = COSTS_N_INSNS (1);
18387 /* When optimizing for size, MEM should be slightly more expensive
18388 than generating address, e.g., (plus (reg) (const)).
18389 L1 cache latency is about two instructions. */
18390 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18398 if (mode == DFmode)
18400 if (GET_CODE (XEXP (x, 0)) == MULT)
18402 /* FNMA accounted in outer NEG. */
18403 if (outer_code == NEG)
18404 *total = rs6000_cost->dmul - rs6000_cost->fp;
18406 *total = rs6000_cost->dmul;
18409 *total = rs6000_cost->fp;
18411 else if (mode == SFmode)
18413 /* FNMA accounted in outer NEG. */
18414 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18417 *total = rs6000_cost->fp;
18420 *total = COSTS_N_INSNS (1);
18424 if (mode == DFmode)
18426 if (GET_CODE (XEXP (x, 0)) == MULT)
18428 /* FNMA accounted in outer NEG. */
18429 if (outer_code == NEG)
18432 *total = rs6000_cost->dmul;
18435 *total = rs6000_cost->fp;
18437 else if (mode == SFmode)
18439 /* FNMA accounted in outer NEG. */
18440 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18443 *total = rs6000_cost->fp;
18446 *total = COSTS_N_INSNS (1);
18450 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18451 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
18453 if (INTVAL (XEXP (x, 1)) >= -256
18454 && INTVAL (XEXP (x, 1)) <= 255)
18455 *total = rs6000_cost->mulsi_const9;
18457 *total = rs6000_cost->mulsi_const;
18459 /* FMA accounted in outer PLUS/MINUS. */
18460 else if ((mode == DFmode || mode == SFmode)
18461 && (outer_code == PLUS || outer_code == MINUS))
18463 else if (mode == DFmode)
18464 *total = rs6000_cost->dmul;
18465 else if (mode == SFmode)
18466 *total = rs6000_cost->fp;
18467 else if (mode == DImode)
18468 *total = rs6000_cost->muldi;
18470 *total = rs6000_cost->mulsi;
18475 if (FLOAT_MODE_P (mode))
18477 *total = mode == DFmode ? rs6000_cost->ddiv
18478 : rs6000_cost->sdiv;
18485 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18486 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18488 if (code == DIV || code == MOD)
18490 *total = COSTS_N_INSNS (2);
18493 *total = COSTS_N_INSNS (1);
18497 if (GET_MODE (XEXP (x, 1)) == DImode)
18498 *total = rs6000_cost->divdi;
18500 *total = rs6000_cost->divsi;
18502 /* Add in shift and subtract for MOD. */
18503 if (code == MOD || code == UMOD)
18504 *total += COSTS_N_INSNS (2);
18508 *total = COSTS_N_INSNS (4);
18512 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18523 *total = COSTS_N_INSNS (1);
18531 /* Handle mul_highpart. */
18532 if (outer_code == TRUNCATE
18533 && GET_CODE (XEXP (x, 0)) == MULT)
18535 if (mode == DImode)
18536 *total = rs6000_cost->muldi;
18538 *total = rs6000_cost->mulsi;
18541 else if (outer_code == AND)
18544 *total = COSTS_N_INSNS (1);
18549 if (GET_CODE (XEXP (x, 0)) == MEM)
18552 *total = COSTS_N_INSNS (1);
18558 if (!FLOAT_MODE_P (mode))
18560 *total = COSTS_N_INSNS (1);
18566 case UNSIGNED_FLOAT:
18569 case FLOAT_TRUNCATE:
18570 *total = rs6000_cost->fp;
18574 if (mode == DFmode)
18577 *total = rs6000_cost->fp;
18581 switch (XINT (x, 1))
18584 *total = rs6000_cost->fp;
18596 *total = COSTS_N_INSNS (1);
18599 else if (FLOAT_MODE_P (mode)
18600 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18602 *total = rs6000_cost->fp;
18610 /* Carry bit requires mode == Pmode.
18611 NEG or PLUS already counted so only add one. */
18613 && (outer_code == NEG || outer_code == PLUS))
18615 *total = COSTS_N_INSNS (1);
18618 if (outer_code == SET)
18620 if (XEXP (x, 1) == const0_rtx)
18622 *total = COSTS_N_INSNS (2);
18625 else if (mode == Pmode)
18627 *total = COSTS_N_INSNS (3);
18636 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18638 *total = COSTS_N_INSNS (2);
18642 if (outer_code == COMPARE)
18656 /* A C expression returning the cost of moving data from a register of class
18657 CLASS1 to one of CLASS2. */
18660 rs6000_register_move_cost (enum machine_mode mode,
18661 enum reg_class from, enum reg_class to)
18663 /* Moves from/to GENERAL_REGS. */
18664 if (reg_classes_intersect_p (to, GENERAL_REGS)
18665 || reg_classes_intersect_p (from, GENERAL_REGS))
18667 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18670 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18671 return (rs6000_memory_move_cost (mode, from, 0)
18672 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18674 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18676 else if (from == CR_REGS)
18680 /* A move will cost one instruction per GPR moved. */
18681 return 2 * hard_regno_nregs[0][mode];
18684 /* Moving between two similar registers is just one instruction. */
18685 else if (reg_classes_intersect_p (to, from))
18686 return mode == TFmode ? 4 : 2;
18688 /* Everything else has to go through GENERAL_REGS. */
18690 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18691 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18694 /* A C expressions returning the cost of moving data of MODE from a register to
18698 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18699 int in ATTRIBUTE_UNUSED)
18701 if (reg_classes_intersect_p (class, GENERAL_REGS))
18702 return 4 * hard_regno_nregs[0][mode];
18703 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18704 return 4 * hard_regno_nregs[32][mode];
18705 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18706 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
18708 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18711 /* Newton-Raphson approximation of single-precision floating point divide n/d.
18712 Assumes no trapping math and finite arguments. */
18715 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
18717 rtx x0, e0, e1, y1, u0, v0, one;
18719 x0 = gen_reg_rtx (SFmode);
18720 e0 = gen_reg_rtx (SFmode);
18721 e1 = gen_reg_rtx (SFmode);
18722 y1 = gen_reg_rtx (SFmode);
18723 u0 = gen_reg_rtx (SFmode);
18724 v0 = gen_reg_rtx (SFmode);
18725 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
18727 /* x0 = 1./d estimate */
18728 emit_insn (gen_rtx_SET (VOIDmode, x0,
18729 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
18731 /* e0 = 1. - d * x0 */
18732 emit_insn (gen_rtx_SET (VOIDmode, e0,
18733 gen_rtx_MINUS (SFmode, one,
18734 gen_rtx_MULT (SFmode, d, x0))));
18735 /* e1 = e0 + e0 * e0 */
18736 emit_insn (gen_rtx_SET (VOIDmode, e1,
18737 gen_rtx_PLUS (SFmode,
18738 gen_rtx_MULT (SFmode, e0, e0), e0)));
18739 /* y1 = x0 + e1 * x0 */
18740 emit_insn (gen_rtx_SET (VOIDmode, y1,
18741 gen_rtx_PLUS (SFmode,
18742 gen_rtx_MULT (SFmode, e1, x0), x0)));
18744 emit_insn (gen_rtx_SET (VOIDmode, u0,
18745 gen_rtx_MULT (SFmode, n, y1)));
18746 /* v0 = n - d * u0 */
18747 emit_insn (gen_rtx_SET (VOIDmode, v0,
18748 gen_rtx_MINUS (SFmode, n,
18749 gen_rtx_MULT (SFmode, d, u0))));
18750 /* res = u0 + v0 * y1 */
18751 emit_insn (gen_rtx_SET (VOIDmode, res,
18752 gen_rtx_PLUS (SFmode,
18753 gen_rtx_MULT (SFmode, v0, y1), u0)));
18756 /* Newton-Raphson approximation of double-precision floating point divide n/d.
18757 Assumes no trapping math and finite arguments. */
18760 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
18762 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
18764 x0 = gen_reg_rtx (DFmode);
18765 e0 = gen_reg_rtx (DFmode);
18766 e1 = gen_reg_rtx (DFmode);
18767 e2 = gen_reg_rtx (DFmode);
18768 y1 = gen_reg_rtx (DFmode);
18769 y2 = gen_reg_rtx (DFmode);
18770 y3 = gen_reg_rtx (DFmode);
18771 u0 = gen_reg_rtx (DFmode);
18772 v0 = gen_reg_rtx (DFmode);
18773 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
18775 /* x0 = 1./d estimate */
18776 emit_insn (gen_rtx_SET (VOIDmode, x0,
18777 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
18779 /* e0 = 1. - d * x0 */
18780 emit_insn (gen_rtx_SET (VOIDmode, e0,
18781 gen_rtx_MINUS (DFmode, one,
18782 gen_rtx_MULT (SFmode, d, x0))));
18783 /* y1 = x0 + e0 * x0 */
18784 emit_insn (gen_rtx_SET (VOIDmode, y1,
18785 gen_rtx_PLUS (DFmode,
18786 gen_rtx_MULT (DFmode, e0, x0), x0)));
18788 emit_insn (gen_rtx_SET (VOIDmode, e1,
18789 gen_rtx_MULT (DFmode, e0, e0)));
18790 /* y2 = y1 + e1 * y1 */
18791 emit_insn (gen_rtx_SET (VOIDmode, y2,
18792 gen_rtx_PLUS (DFmode,
18793 gen_rtx_MULT (DFmode, e1, y1), y1)));
18795 emit_insn (gen_rtx_SET (VOIDmode, e2,
18796 gen_rtx_MULT (DFmode, e1, e1)));
18797 /* y3 = y2 + e2 * y2 */
18798 emit_insn (gen_rtx_SET (VOIDmode, y3,
18799 gen_rtx_PLUS (DFmode,
18800 gen_rtx_MULT (DFmode, e2, y2), y2)));
18802 emit_insn (gen_rtx_SET (VOIDmode, u0,
18803 gen_rtx_MULT (DFmode, n, y3)));
18804 /* v0 = n - d * u0 */
18805 emit_insn (gen_rtx_SET (VOIDmode, v0,
18806 gen_rtx_MINUS (DFmode, n,
18807 gen_rtx_MULT (DFmode, d, u0))));
18808 /* res = u0 + v0 * y3 */
18809 emit_insn (gen_rtx_SET (VOIDmode, res,
18810 gen_rtx_PLUS (DFmode,
18811 gen_rtx_MULT (DFmode, v0, y3), u0)));
18814 /* Return an RTX representing where to find the function value of a
18815 function returning MODE. */
18817 rs6000_complex_function_value (enum machine_mode mode)
18819 unsigned int regno;
18821 enum machine_mode inner = GET_MODE_INNER (mode);
18822 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18824 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18825 regno = FP_ARG_RETURN;
18828 regno = GP_ARG_RETURN;
18830 /* 32-bit is OK since it'll go in r3/r4. */
18831 if (TARGET_32BIT && inner_bytes >= 4)
18832 return gen_rtx_REG (mode, regno);
18835 if (inner_bytes >= 8)
18836 return gen_rtx_REG (mode, regno);
18838 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18840 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18841 GEN_INT (inner_bytes));
18842 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18845 /* Define how to find the value returned by a function.
18846 VALTYPE is the data type of the value (as a tree).
18847 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18848 otherwise, FUNC is 0.
18850 On the SPE, both FPs and vectors are returned in r3.
18852 On RS/6000 an integer value is in r3 and a floating-point value is in
18853 fp1, unless -msoft-float. */
18856 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18858 enum machine_mode mode;
18859 unsigned int regno;
18861 /* Special handling for structs in darwin64. */
18862 if (rs6000_darwin64_abi
18863 && TYPE_MODE (valtype) == BLKmode
18864 && TREE_CODE (valtype) == RECORD_TYPE
18865 && int_size_in_bytes (valtype) > 0)
18867 CUMULATIVE_ARGS valcum;
18871 valcum.fregno = FP_ARG_MIN_REG;
18872 valcum.vregno = ALTIVEC_ARG_MIN_REG;
18873 /* Do a trial code generation as if this were going to be passed as
18874 an argument; if any part goes in memory, we return NULL. */
18875 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
18878 /* Otherwise fall through to standard ABI rules. */
18881 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18883 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18884 return gen_rtx_PARALLEL (DImode,
18886 gen_rtx_EXPR_LIST (VOIDmode,
18887 gen_rtx_REG (SImode, GP_ARG_RETURN),
18889 gen_rtx_EXPR_LIST (VOIDmode,
18890 gen_rtx_REG (SImode,
18891 GP_ARG_RETURN + 1),
18894 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
18896 return gen_rtx_PARALLEL (DCmode,
18898 gen_rtx_EXPR_LIST (VOIDmode,
18899 gen_rtx_REG (SImode, GP_ARG_RETURN),
18901 gen_rtx_EXPR_LIST (VOIDmode,
18902 gen_rtx_REG (SImode,
18903 GP_ARG_RETURN + 1),
18905 gen_rtx_EXPR_LIST (VOIDmode,
18906 gen_rtx_REG (SImode,
18907 GP_ARG_RETURN + 2),
18909 gen_rtx_EXPR_LIST (VOIDmode,
18910 gen_rtx_REG (SImode,
18911 GP_ARG_RETURN + 3),
18914 if ((INTEGRAL_TYPE_P (valtype)
18915 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18916 || POINTER_TYPE_P (valtype))
18917 mode = TARGET_32BIT ? SImode : DImode;
18919 mode = TYPE_MODE (valtype);
18921 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
18922 regno = FP_ARG_RETURN;
18923 else if (TREE_CODE (valtype) == COMPLEX_TYPE
18924 && targetm.calls.split_complex_arg)
18925 return rs6000_complex_function_value (mode);
18926 else if (TREE_CODE (valtype) == VECTOR_TYPE
18927 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
18928 && ALTIVEC_VECTOR_MODE (mode))
18929 regno = ALTIVEC_ARG_RETURN;
18930 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18931 && (mode == DFmode || mode == DCmode))
18932 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18934 regno = GP_ARG_RETURN;
18936 return gen_rtx_REG (mode, regno);
18939 /* Define how to find the value returned by a library function
18940 assuming the value has mode MODE. */
18942 rs6000_libcall_value (enum machine_mode mode)
18944 unsigned int regno;
18946 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18948 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18949 return gen_rtx_PARALLEL (DImode,
18951 gen_rtx_EXPR_LIST (VOIDmode,
18952 gen_rtx_REG (SImode, GP_ARG_RETURN),
18954 gen_rtx_EXPR_LIST (VOIDmode,
18955 gen_rtx_REG (SImode,
18956 GP_ARG_RETURN + 1),
18960 if (SCALAR_FLOAT_MODE_P (mode)
18961 && TARGET_HARD_FLOAT && TARGET_FPRS)
18962 regno = FP_ARG_RETURN;
18963 else if (ALTIVEC_VECTOR_MODE (mode)
18964 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
18965 regno = ALTIVEC_ARG_RETURN;
18966 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
18967 return rs6000_complex_function_value (mode);
18968 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18969 && (mode == DFmode || mode == DCmode))
18970 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18972 regno = GP_ARG_RETURN;
18974 return gen_rtx_REG (mode, regno);
18977 /* Define the offset between two registers, FROM to be eliminated and its
18978 replacement TO, at the start of a routine. */
18980 rs6000_initial_elimination_offset (int from, int to)
18982 rs6000_stack_t *info = rs6000_stack_info ();
18983 HOST_WIDE_INT offset;
18985 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18986 offset = info->push_p ? 0 : -info->total_size;
18987 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18989 offset = info->push_p ? 0 : -info->total_size;
18990 if (FRAME_GROWS_DOWNWARD)
18991 offset += info->fixed_size + info->vars_size + info->parm_size;
18993 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
18994 offset = FRAME_GROWS_DOWNWARD
18995 ? info->fixed_size + info->vars_size + info->parm_size
18997 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
18998 offset = info->total_size;
18999 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19000 offset = info->push_p ? info->total_size : 0;
19001 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
19004 gcc_unreachable ();
19009 /* Return true if TYPE is a SPE or AltiVec opaque type. */
19012 rs6000_is_opaque_type (tree type)
19014 return (type == opaque_V2SI_type_node
19015 || type == opaque_V2SF_type_node
19016 || type == opaque_p_V2SI_type_node
19017 || type == opaque_V4SI_type_node);
19021 rs6000_dwarf_register_span (rtx reg)
19026 && (SPE_VECTOR_MODE (GET_MODE (reg))
19027 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
19032 regno = REGNO (reg);
19034 /* The duality of the SPE register size wreaks all kinds of havoc.
19035 This is a way of distinguishing r0 in 32-bits from r0 in
19038 gen_rtx_PARALLEL (VOIDmode,
19041 gen_rtx_REG (SImode, regno + 1200),
19042 gen_rtx_REG (SImode, regno))
19044 gen_rtx_REG (SImode, regno),
19045 gen_rtx_REG (SImode, regno + 1200)));
19048 /* Map internal gcc register numbers to DWARF2 register numbers. */
19051 rs6000_dbx_register_number (unsigned int regno)
19053 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
19055 if (regno == MQ_REGNO)
19057 if (regno == LINK_REGISTER_REGNUM)
19059 if (regno == COUNT_REGISTER_REGNUM)
19061 if (CR_REGNO_P (regno))
19062 return regno - CR0_REGNO + 86;
19063 if (regno == XER_REGNO)
19065 if (ALTIVEC_REGNO_P (regno))
19066 return regno - FIRST_ALTIVEC_REGNO + 1124;
19067 if (regno == VRSAVE_REGNO)
19069 if (regno == VSCR_REGNO)
19071 if (regno == SPE_ACC_REGNO)
19073 if (regno == SPEFSCR_REGNO)
19075 /* SPE high reg number. We get these values of regno from
19076 rs6000_dwarf_register_span. */
19077 gcc_assert (regno >= 1200 && regno < 1232);
19081 /* target hook eh_return_filter_mode */
19082 static enum machine_mode
19083 rs6000_eh_return_filter_mode (void)
19085 return TARGET_32BIT ? SImode : word_mode;
19088 /* Target hook for vector_mode_supported_p. */
19090 rs6000_vector_mode_supported_p (enum machine_mode mode)
19093 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
19096 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
19103 /* Target hook for invalid_arg_for_unprototyped_fn. */
19104 static const char *
19105 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
19107 return (!rs6000_darwin64_abi
19109 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
19110 && (funcdecl == NULL_TREE
19111 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19112 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19113 ? N_("AltiVec argument passed to unprototyped function")
19117 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19118 setup by using __stack_chk_fail_local hidden function instead of
19119 calling __stack_chk_fail directly. Otherwise it is better to call
19120 __stack_chk_fail directly. */
19123 rs6000_stack_protect_fail (void)
19125 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19126 ? default_hidden_stack_protect_fail ()
19127 : default_external_stack_protect_fail ();
19130 #include "gt-rs6000.h"