1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
39 extern char *language_string;
40 extern int profile_block_flag;
42 #define min(A,B) ((A) < (B) ? (A) : (B))
43 #define max(A,B) ((A) > (B) ? (A) : (B))
47 enum processor_type rs6000_cpu;
48 char *rs6000_cpu_string;
50 /* Set to non-zero by "fix" operation to indicate that itrunc and
51 uitrunc must be defined. */
53 int rs6000_trunc_used;
55 /* Set to non-zero once they have been defined. */
57 static int trunc_defined;
59 /* Set to non-zero once AIX common-mode calls have been defined. */
60 static int common_mode_defined;
61 /* Save information from a "cmpxx" operation until the branch or scc is
64 rtx rs6000_compare_op0, rs6000_compare_op1;
65 int rs6000_compare_fp_p;
68 /* Label number of label created for -mrelocatable, to call to so we can
69 get the address of the GOT section */
70 int rs6000_pic_labelno;
73 /* Override command line options. Mostly we process the processor
74 type and sometimes adjust other TARGET_ options. */
77 rs6000_override_options ()
81 /* Simplify the entries below by making a mask for any POWER
82 variant and any PowerPC variant. */
84 #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE)
85 #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
86 | MASK_PPC_GFXOPT | MASK_POWERPC64)
87 #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
91 char *name; /* Canonical processor name. */
92 enum processor_type processor; /* Processor type enum value. */
93 int target_enable; /* Target flags to enable. */
94 int target_disable; /* Target flags to disable. */
95 } processor_target_table[]
96 = {{"common", PROCESSOR_COMMON, 0, POWER_MASKS | POWERPC_MASKS},
97 {"power", PROCESSOR_POWER,
98 MASK_POWER | MASK_MULTIPLE,
99 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
100 {"powerpc", PROCESSOR_POWERPC,
101 MASK_POWERPC | MASK_NEW_MNEMONICS,
102 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
103 {"rios", PROCESSOR_RIOS1,
104 MASK_POWER | MASK_MULTIPLE,
105 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
106 {"rios1", PROCESSOR_RIOS1,
107 MASK_POWER | MASK_MULTIPLE,
108 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
109 {"rsc", PROCESSOR_PPC601,
110 MASK_POWER | MASK_MULTIPLE,
111 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
112 {"rsc1", PROCESSOR_PPC601,
113 MASK_POWER | MASK_MULTIPLE,
114 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
115 {"rios2", PROCESSOR_RIOS2,
116 MASK_POWER | MASK_MULTIPLE | MASK_POWER2,
117 POWERPC_MASKS | MASK_NEW_MNEMONICS},
118 {"403", PROCESSOR_PPC403,
119 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
120 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
121 {"mpc403", PROCESSOR_PPC403,
122 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
123 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
124 {"ppc403", PROCESSOR_PPC403,
125 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
126 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
127 {"601", PROCESSOR_PPC601,
128 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE,
129 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
130 {"mpc601", PROCESSOR_PPC601,
131 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE,
132 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
133 {"ppc601", PROCESSOR_PPC601,
134 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE,
135 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
136 {"603", PROCESSOR_PPC603,
137 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
138 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
139 {"mpc603", PROCESSOR_PPC603,
140 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
141 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
142 {"ppc603", PROCESSOR_PPC603,
143 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
144 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
145 {"604", PROCESSOR_PPC604,
146 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
147 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
148 {"mpc604", PROCESSOR_PPC604,
149 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
150 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
151 {"ppc604", PROCESSOR_PPC604,
152 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
153 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}};
155 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
157 int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */
159 profile_block_flag = 0;
161 /* Identify the processor type */
162 if (rs6000_cpu_string == 0)
163 rs6000_cpu = PROCESSOR_DEFAULT;
166 for (i = 0; i < ptt_size; i++)
167 if (! strcmp (rs6000_cpu_string, processor_target_table[i].name))
169 rs6000_cpu = processor_target_table[i].processor;
170 target_flags |= processor_target_table[i].target_enable;
171 target_flags &= ~processor_target_table[i].target_disable;
177 error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string);
178 rs6000_cpu_string = "default";
179 rs6000_cpu = PROCESSOR_DEFAULT;
183 /* If -mmultiple or -mno-multiple was explicitly used, don't
184 override with the processor default */
185 if (TARGET_MULTIPLE_SET)
186 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
188 /* Don't allow -mmultiple or -mstring on little endian systems, because the
189 hardware doesn't support the instructions used in little endian mode */
190 if (!BYTES_BIG_ENDIAN)
194 target_flags &= ~MASK_MULTIPLE;
195 if (TARGET_MULTIPLE_SET)
196 warning ("-mmultiple is not supported on little endian systems");
201 target_flags &= ~MASK_STRING;
202 warning ("-mstring is not supported on little endian systems");
206 #ifdef SUBTARGET_OVERRIDE_OPTIONS
207 SUBTARGET_OVERRIDE_OPTIONS;
211 /* Create a CONST_DOUBLE like immed_double_const, except reverse the
212 two parts of the constant if the target is little endian. */
214 struct rtx_def *rs6000_immed_double_const (i0, i1, mode)
215 HOST_WIDE_INT i0, i1;
216 enum machine_mode mode;
218 if (! WORDS_BIG_ENDIAN)
219 return immed_double_const (i1, i0, mode);
221 return immed_double_const (i0, i1, mode);
225 /* Return non-zero if this function is known to have a null epilogue. */
230 return (reload_completed
231 && first_reg_to_save () == 32
232 && first_fp_reg_to_save () == 64
233 && ! regs_ever_live[65]
234 && ! rs6000_pushes_stack ());
237 /* Returns 1 always. */
240 any_operand (op, mode)
242 enum machine_mode mode;
247 /* Return 1 if OP is a constant that can fit in a D field. */
250 short_cint_operand (op, mode)
252 enum machine_mode mode;
254 return (GET_CODE (op) == CONST_INT
255 && (unsigned) (INTVAL (op) + 0x8000) < 0x10000);
258 /* Similar for a unsigned D field. */
261 u_short_cint_operand (op, mode)
263 enum machine_mode mode;
265 return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0);
268 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
271 non_short_cint_operand (op, mode)
273 enum machine_mode mode;
275 return (GET_CODE (op) == CONST_INT
276 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000);
279 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
283 gpc_reg_operand (op, mode)
285 enum machine_mode mode;
287 return (register_operand (op, mode)
288 && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64));
291 /* Returns 1 if OP is either a pseudo-register or a register denoting a
295 cc_reg_operand (op, mode)
297 enum machine_mode mode;
299 return (register_operand (op, mode)
300 && (GET_CODE (op) != REG
301 || REGNO (op) >= FIRST_PSEUDO_REGISTER
302 || CR_REGNO_P (REGNO (op))));
305 /* Returns 1 if OP is either a constant integer valid for a D-field or a
306 non-special register. If a register, it must be in the proper mode unless
310 reg_or_short_operand (op, mode)
312 enum machine_mode mode;
314 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
317 /* Similar, except check if the negation of the constant would be valid for
321 reg_or_neg_short_operand (op, mode)
323 enum machine_mode mode;
325 if (GET_CODE (op) == CONST_INT)
326 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
328 return gpc_reg_operand (op, mode);
331 /* Return 1 if the operand is either a register or an integer whose high-order
335 reg_or_u_short_operand (op, mode)
337 enum machine_mode mode;
339 if (GET_CODE (op) == CONST_INT
340 && (INTVAL (op) & 0xffff0000) == 0)
343 return gpc_reg_operand (op, mode);
346 /* Return 1 is the operand is either a non-special register or ANY
350 reg_or_cint_operand (op, mode)
352 enum machine_mode mode;
354 return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode);
357 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
358 with one instruction per word. We only do this if we can safely read
359 CONST_DOUBLE_{LOW,HIGH}. */
362 easy_fp_constant (op, mode)
364 register enum machine_mode mode;
368 if (GET_CODE (op) != CONST_DOUBLE
369 || GET_MODE (op) != mode
370 || GET_MODE_CLASS (mode) != MODE_FLOAT)
373 high = operand_subword (op, 0, 0, mode);
374 low = operand_subword (op, 1, 0, mode);
376 if (high == 0 || ! input_operand (high, word_mode))
379 return (mode == SFmode
380 || (low != 0 && input_operand (low, word_mode)));
383 /* Return 1 if the operand is a constant whose low-order 32 bits are
387 low_32_bit_operand (op, mode)
389 enum machine_mode mode;
393 if (GET_CODE (op) != CONST_DOUBLE && GET_CODE (op) != CONST_INT)
396 low = operand_subword (op, 1, 0, mode);
397 return low != 0 && GET_CODE (low) == CONST_INT && INTVAL (low) == 0;
400 /* Return 1 if the operand is either a floating-point register, a pseudo
401 register, or memory. */
404 fp_reg_or_mem_operand (op, mode)
406 enum machine_mode mode;
408 return (memory_operand (op, mode)
409 || (register_operand (op, mode)
410 && (GET_CODE (op) != REG
411 || REGNO (op) >= FIRST_PSEUDO_REGISTER
412 || FP_REGNO_P (REGNO (op)))));
415 /* Return 1 if the operand is either an easy FP constant (see above) or
419 mem_or_easy_const_operand (op, mode)
421 enum machine_mode mode;
423 return memory_operand (op, mode) || easy_fp_constant (op, mode);
426 /* Return 1 if the operand is either a non-special register or an item
427 that can be used as the operand of an SI add insn. */
430 add_operand (op, mode)
432 enum machine_mode mode;
434 return (reg_or_short_operand (op, mode)
435 || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
438 /* Return 1 if OP is a constant but not a valid add_operand. */
441 non_add_cint_operand (op, mode)
443 enum machine_mode mode;
445 return (GET_CODE (op) == CONST_INT
446 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000
447 && (INTVAL (op) & 0xffff) != 0);
450 /* Return 1 if the operand is a non-special register or a constant that
451 can be used as the operand of an OR or XOR insn on the RS/6000. */
454 logical_operand (op, mode)
456 enum machine_mode mode;
458 return (gpc_reg_operand (op, mode)
459 || (GET_CODE (op) == CONST_INT
460 && ((INTVAL (op) & 0xffff0000) == 0
461 || (INTVAL (op) & 0xffff) == 0)));
464 /* Return 1 if C is a constant that is not a logical operand (as
468 non_logical_cint_operand (op, mode)
470 enum machine_mode mode;
472 return (GET_CODE (op) == CONST_INT
473 && (INTVAL (op) & 0xffff0000) != 0
474 && (INTVAL (op) & 0xffff) != 0);
477 /* Return 1 if C is a constant that can be encoded in a mask on the
478 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
479 Reject all ones and all zeros, since these should have been optimized
480 away and confuse the making of MB and ME. */
490 if (c == 0 || c == ~0)
493 last_bit_value = c & 1;
495 for (i = 1; i < 32; i++)
496 if (((c >>= 1) & 1) != last_bit_value)
497 last_bit_value ^= 1, transitions++;
499 return transitions <= 2;
502 /* Return 1 if the operand is a constant that is a mask on the RS/6000. */
505 mask_operand (op, mode)
507 enum machine_mode mode;
509 return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op));
512 /* Return 1 if the operand is either a non-special register or a
513 constant that can be used as the operand of an RS/6000 logical AND insn. */
516 and_operand (op, mode)
518 enum machine_mode mode;
520 return (reg_or_short_operand (op, mode)
521 || logical_operand (op, mode)
522 || mask_operand (op, mode));
525 /* Return 1 if the operand is a constant but not a valid operand for an AND
529 non_and_cint_operand (op, mode)
531 enum machine_mode mode;
533 return GET_CODE (op) == CONST_INT && ! and_operand (op, mode);
536 /* Return 1 if the operand is a general register or memory operand. */
539 reg_or_mem_operand (op, mode)
541 register enum machine_mode mode;
543 return gpc_reg_operand (op, mode) || memory_operand (op, mode);
546 /* Return 1 if the operand is a general register or memory operand without
547 pre-inc or pre_dec which produces invalid form of PowerPC lwa
551 lwa_operand (op, mode)
553 register enum machine_mode mode;
557 if (reload_completed && GET_CODE (inner) == SUBREG)
558 inner = SUBREG_REG (inner);
560 return gpc_reg_operand (inner, mode)
561 || (memory_operand (inner, mode)
562 && GET_CODE (XEXP (inner, 0)) != PRE_INC
563 && GET_CODE (XEXP (inner, 0)) != PRE_DEC);
566 /* Return 1 if the operand, used inside a MEM, is a valid first argument
567 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
571 call_operand (op, mode)
573 enum machine_mode mode;
575 if (mode != VOIDmode && GET_MODE (op) != mode)
578 return (GET_CODE (op) == SYMBOL_REF
579 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
583 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
587 current_file_function_operand (op, mode)
589 enum machine_mode mode;
591 return (GET_CODE (op) == SYMBOL_REF
592 && (SYMBOL_REF_FLAG (op)
593 || op == XEXP (DECL_RTL (current_function_decl), 0)));
597 /* Return 1 if this operand is a valid input for a move insn. */
600 input_operand (op, mode)
602 enum machine_mode mode;
604 /* Memory is always valid. */
605 if (memory_operand (op, mode))
608 /* For floating-point, easy constants are valid. */
609 if (GET_MODE_CLASS (mode) == MODE_FLOAT
611 && easy_fp_constant (op, mode))
614 /* For floating-point or multi-word mode, the only remaining valid type
616 if (GET_MODE_CLASS (mode) == MODE_FLOAT
617 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
618 return register_operand (op, mode);
620 /* The only cases left are integral modes one word or smaller (we
621 do not get called for MODE_CC values). These can be in any
623 if (register_operand (op, mode))
626 /* For HImode and QImode, any constant is valid. */
627 if ((mode == HImode || mode == QImode)
628 && GET_CODE (op) == CONST_INT)
631 /* A SYMBOL_REF referring to the TOC is valid. */
632 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
635 /* Otherwise, we will be doing this SET with an add, so anything valid
636 for an add will be valid. */
637 return add_operand (op, mode);
640 /* Expand a block move operation, and return 1 if successful. Return 0
641 if we should let the compiler generate normal code.
643 operands[0] is the destination
644 operands[1] is the source
645 operands[2] is the length
646 operands[3] is the alignment */
648 #define MAX_MOVE_REG 4
651 expand_block_move (operands)
654 rtx bytes_rtx = operands[2];
655 rtx align_rtx = operands[3];
656 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
657 int align = XINT (align_rtx, 0);
667 rtx stores[MAX_MOVE_REG];
670 /* If this is not a fixed size move, just call memcpy */
674 /* Anything to move? */
675 bytes = INTVAL (bytes_rtx);
679 /* Don't support real large moves. If string instructions are not used,
680 then don't generate more than 8 loads. */
686 else if (!STRICT_ALIGNMENT)
691 else if (bytes > 8*align)
694 /* Move the address into scratch registers. */
695 dest_reg = copy_addr_to_reg (XEXP (operands[0], 0));
696 src_reg = copy_addr_to_reg (XEXP (operands[1], 0));
698 if (TARGET_STRING) /* string instructions are available */
700 for ( ; bytes > 0; bytes -= move_bytes)
702 if (bytes > 24 /* move up to 32 bytes at a time */
712 move_bytes = (bytes > 32) ? 32 : bytes;
713 emit_insn (gen_movstrsi_8reg (dest_reg,
715 GEN_INT ((move_bytes == 32) ? 0 : move_bytes),
717 GEN_INT ((bytes > move_bytes) ? move_bytes : 0)));
719 else if (bytes > 16 /* move up to 24 bytes at a time */
727 move_bytes = (bytes > 24) ? 24 : bytes;
728 emit_insn (gen_movstrsi_6reg (dest_reg,
730 GEN_INT (move_bytes),
732 GEN_INT ((bytes > move_bytes) ? move_bytes : 0)));
734 else if (bytes > 8 /* move up to 16 bytes at a time */
740 move_bytes = (bytes > 16) ? 16 : bytes;
741 emit_insn (gen_movstrsi_4reg (dest_reg,
743 GEN_INT (move_bytes),
745 GEN_INT ((bytes > move_bytes) ? move_bytes : 0)));
747 else if (bytes > 4 && !TARGET_64BIT)
748 { /* move up to 8 bytes at a time */
749 move_bytes = (bytes > 8) ? 8 : bytes;
750 emit_insn (gen_movstrsi_2reg (dest_reg,
752 GEN_INT (move_bytes),
754 GEN_INT ((bytes > move_bytes) ? move_bytes : 0)));
756 else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
759 tmp_reg = gen_reg_rtx (SImode);
760 emit_move_insn (tmp_reg, gen_rtx (MEM, SImode, src_reg));
761 emit_move_insn (gen_rtx (MEM, SImode, dest_reg), tmp_reg);
762 if (bytes > move_bytes)
764 emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes)));
765 emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes)));
768 else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT))
771 tmp_reg = gen_reg_rtx (HImode);
772 emit_move_insn (tmp_reg, gen_rtx (MEM, HImode, src_reg));
773 emit_move_insn (gen_rtx (MEM, HImode, dest_reg), tmp_reg);
775 else if (bytes == 1) /* move 1 byte */
778 tmp_reg = gen_reg_rtx (QImode);
779 emit_move_insn (tmp_reg, gen_rtx (MEM, QImode, src_reg));
780 emit_move_insn (gen_rtx (MEM, QImode, dest_reg), tmp_reg);
783 { /* move up to 4 bytes at a time */
784 move_bytes = (bytes > 4) ? 4 : bytes;
785 emit_insn (gen_movstrsi_1reg (dest_reg,
787 GEN_INT (move_bytes),
789 GEN_INT ((bytes > move_bytes) ? move_bytes : 0)));
794 else /* string instructions not available */
796 num_reg = offset = 0;
797 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
799 /* Calculate the correct offset for src/dest */
803 dest_addr = dest_reg;
807 src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset));
808 dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset));
811 /* Generate the appropriate load and store, saving the stores for later */
812 if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
815 tmp_reg = gen_reg_rtx (SImode);
816 emit_insn (gen_movsi (tmp_reg, gen_rtx (MEM, SImode, src_addr)));
817 stores[ num_reg++ ] = gen_movsi (gen_rtx (MEM, SImode, dest_addr), tmp_reg);
819 else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT))
822 tmp_reg = gen_reg_rtx (HImode);
823 emit_insn (gen_movhi (tmp_reg, gen_rtx (MEM, HImode, src_addr)));
824 stores[ num_reg++ ] = gen_movhi (gen_rtx (MEM, HImode, dest_addr), tmp_reg);
829 tmp_reg = gen_reg_rtx (QImode);
830 emit_insn (gen_movqi (tmp_reg, gen_rtx (MEM, QImode, src_addr)));
831 stores[ num_reg++ ] = gen_movqi (gen_rtx (MEM, QImode, dest_addr), tmp_reg);
834 if (num_reg >= MAX_MOVE_REG)
836 for (i = 0; i < num_reg; i++)
837 emit_insn (stores[i]);
844 for (i = 0; i < num_reg; i++)
845 emit_insn (stores[i]);
853 /* Return 1 if OP is a load multiple operation. It is known to be a
854 PARALLEL and the first section will be tested. */
857 load_multiple_operation (op, mode)
859 enum machine_mode mode;
861 int count = XVECLEN (op, 0);
866 /* Perform a quick check so we don't blow up below. */
868 || GET_CODE (XVECEXP (op, 0, 0)) != SET
869 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
870 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
873 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
874 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
876 for (i = 1; i < count; i++)
878 rtx elt = XVECEXP (op, 0, i);
880 if (GET_CODE (elt) != SET
881 || GET_CODE (SET_DEST (elt)) != REG
882 || GET_MODE (SET_DEST (elt)) != SImode
883 || REGNO (SET_DEST (elt)) != dest_regno + i
884 || GET_CODE (SET_SRC (elt)) != MEM
885 || GET_MODE (SET_SRC (elt)) != SImode
886 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
887 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
888 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
889 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
896 /* Similar, but tests for store multiple. Here, the second vector element
897 is a CLOBBER. It will be tested later. */
900 store_multiple_operation (op, mode)
902 enum machine_mode mode;
904 int count = XVECLEN (op, 0) - 1;
909 /* Perform a quick check so we don't blow up below. */
911 || GET_CODE (XVECEXP (op, 0, 0)) != SET
912 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
913 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
916 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
917 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
919 for (i = 1; i < count; i++)
921 rtx elt = XVECEXP (op, 0, i + 1);
923 if (GET_CODE (elt) != SET
924 || GET_CODE (SET_SRC (elt)) != REG
925 || GET_MODE (SET_SRC (elt)) != SImode
926 || REGNO (SET_SRC (elt)) != src_regno + i
927 || GET_CODE (SET_DEST (elt)) != MEM
928 || GET_MODE (SET_DEST (elt)) != SImode
929 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
930 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
931 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
932 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
939 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
940 We only check the opcode against the mode of the CC value here. */
943 branch_comparison_operator (op, mode)
945 enum machine_mode mode;
947 enum rtx_code code = GET_CODE (op);
948 enum machine_mode cc_mode;
950 if (GET_RTX_CLASS (code) != '<')
953 cc_mode = GET_MODE (XEXP (op, 0));
954 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
957 if ((code == GT || code == LT || code == GE || code == LE)
958 && cc_mode == CCUNSmode)
961 if ((code == GTU || code == LTU || code == GEU || code == LEU)
962 && (cc_mode != CCUNSmode))
968 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
969 We check the opcode against the mode of the CC value and disallow EQ or
970 NE comparisons for integers. */
973 scc_comparison_operator (op, mode)
975 enum machine_mode mode;
977 enum rtx_code code = GET_CODE (op);
978 enum machine_mode cc_mode;
980 if (GET_MODE (op) != mode && mode != VOIDmode)
983 if (GET_RTX_CLASS (code) != '<')
986 cc_mode = GET_MODE (XEXP (op, 0));
987 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
990 if (code == NE && cc_mode != CCFPmode)
993 if ((code == GT || code == LT || code == GE || code == LE)
994 && cc_mode == CCUNSmode)
997 if ((code == GTU || code == LTU || code == GEU || code == LEU)
998 && (cc_mode != CCUNSmode))
1001 if (cc_mode == CCEQmode && code != EQ && code != NE)
1007 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
1008 mask required to convert the result of a rotate insn into a shift
1009 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
1012 includes_lshift_p (shiftop, andop)
1013 register rtx shiftop;
1016 int shift_mask = (~0 << INTVAL (shiftop));
1018 return (INTVAL (andop) & ~shift_mask) == 0;
1021 /* Similar, but for right shift. */
1024 includes_rshift_p (shiftop, andop)
1025 register rtx shiftop;
1028 unsigned shift_mask = ~0;
1030 shift_mask >>= INTVAL (shiftop);
1032 return (INTVAL (andop) & ~ shift_mask) == 0;
1035 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
1036 for lfq and stfq insns.
1038 Note reg1 and reg2 *must* be hard registers. To be sure we will
1039 abort if we are passed pseudo registers. */
1042 registers_ok_for_quad_peep (reg1, reg2)
1045 /* We might have been passed a SUBREG. */
1046 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
1049 return (REGNO (reg1) == REGNO (reg2) - 1);
1052 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and
1053 addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */
1056 addrs_ok_for_quad_peep (addr1, addr2)
1063 /* Extract an offset (if used) from the first addr. */
1064 if (GET_CODE (addr1) == PLUS)
1066 /* If not a REG, return zero. */
1067 if (GET_CODE (XEXP (addr1, 0)) != REG)
1071 reg1 = REGNO (XEXP (addr1, 0));
1072 /* The offset must be constant! */
1073 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
1075 offset1 = INTVAL (XEXP (addr1, 1));
1078 else if (GET_CODE (addr1) != REG)
1082 reg1 = REGNO (addr1);
1083 /* This was a simple (mem (reg)) expression. Offset is 0. */
1087 /* Make sure the second address is a (mem (plus (reg) (const_int). */
1088 if (GET_CODE (addr2) != PLUS)
1091 if (GET_CODE (XEXP (addr2, 0)) != REG
1092 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
1095 if (reg1 != REGNO (XEXP (addr2, 0)))
1098 /* The offset for the second addr must be 8 more than the first addr. */
1099 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
1102 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
1107 /* Return the register class of a scratch register needed to copy IN into
1108 or out of a register in CLASS in MODE. If it can be done directly,
1109 NO_REGS is returned. */
1112 secondary_reload_class (class, mode, in)
1113 enum reg_class class;
1114 enum machine_mode mode;
1117 int regno = true_regnum (in);
1119 if (regno >= FIRST_PSEUDO_REGISTER)
1122 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
1124 if (class == GENERAL_REGS || class == BASE_REGS
1125 || (regno >= 0 && INT_REGNO_P (regno)))
1128 /* Constants, memory, and FP registers can go into FP registers. */
1129 if ((regno == -1 || FP_REGNO_P (regno))
1130 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
1133 /* We can copy among the CR registers. */
1134 if ((class == CR_REGS || class == CR0_REGS)
1135 && regno >= 0 && CR_REGNO_P (regno))
1138 /* Otherwise, we need GENERAL_REGS. */
1139 return GENERAL_REGS;
1142 /* Given a comparison operation, return the bit number in CCR to test. We
1143 know this is a valid comparison.
1145 SCC_P is 1 if this is for an scc. That means that %D will have been
1146 used instead of %C, so the bits will be in different places.
1148 Return -1 if OP isn't a valid comparison for some reason. */
1155 enum rtx_code code = GET_CODE (op);
1156 enum machine_mode cc_mode;
1160 if (GET_RTX_CLASS (code) != '<')
1163 cc_mode = GET_MODE (XEXP (op, 0));
1164 cc_regnum = REGNO (XEXP (op, 0));
1165 base_bit = 4 * (cc_regnum - 68);
1167 /* In CCEQmode cases we have made sure that the result is always in the
1168 third bit of the CR field. */
1170 if (cc_mode == CCEQmode)
1171 return base_bit + 3;
1176 return scc_p ? base_bit + 3 : base_bit + 2;
1178 return base_bit + 2;
1180 return base_bit + 1;
1185 /* If floating-point, we will have done a cror to put the bit in the
1186 unordered position. So test that bit. For integer, this is ! LT
1187 unless this is an scc insn. */
1188 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit;
1191 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1;
1198 /* Print an operand. Recognize special options, documented below. */
1201 print_operand (file, x, code)
1209 /* These macros test for integers and extract the low-order bits. */
1211 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
1212 && GET_MODE (X) == VOIDmode)
1214 #define INT_LOWPART(X) \
1215 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
1220 /* Write out an instruction after the call which may be replaced
1221 with glue code by the loader. This depends on the AIX version. */
1222 asm_fprintf (file, RS6000_CALL_GLUE);
1226 /* Write the register number of the TOC register. */
1227 fputs (TARGET_MINIMAL_TOC ? "30" : "2", file);
1231 /* If X is a constant integer whose low-order 5 bits are zero,
1232 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
1233 in the AIX assembler where "sri" with a zero shift count
1234 write a trash instruction. */
1235 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
1242 /* Low-order 16 bits of constant, unsigned. */
1244 output_operand_lossage ("invalid %%b value");
1246 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
1250 /* This is an optional cror needed for LE or GE floating-point
1251 comparisons. Otherwise write nothing. */
1252 if ((GET_CODE (x) == LE || GET_CODE (x) == GE)
1253 && GET_MODE (XEXP (x, 0)) == CCFPmode)
1255 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1257 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
1258 base_bit + 2, base_bit + (GET_CODE (x) == GE));
1263 /* Similar, except that this is for an scc, so we must be able to
1264 encode the test in a single bit that is one. We do the above
1265 for any LE, GE, GEU, or LEU and invert the bit for NE. */
1266 if (GET_CODE (x) == LE || GET_CODE (x) == GE
1267 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
1269 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1271 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
1273 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
1276 else if (GET_CODE (x) == NE)
1278 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1280 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
1281 base_bit + 2, base_bit + 2);
1286 /* X is a CR register. Print the number of the third bit of the CR */
1287 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1288 output_operand_lossage ("invalid %%E value");
1290 fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3);
1294 /* X is a CR register. Print the shift count needed to move it
1295 to the high-order four bits. */
1296 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1297 output_operand_lossage ("invalid %%f value");
1299 fprintf (file, "%d", 4 * (REGNO (x) - 68));
1303 /* Similar, but print the count for the rotate in the opposite
1305 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1306 output_operand_lossage ("invalid %%F value");
1308 fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68));
1312 /* X is a constant integer. If it is negative, print "m",
1313 otherwise print "z". This is to make a aze or ame insn. */
1314 if (GET_CODE (x) != CONST_INT)
1315 output_operand_lossage ("invalid %%G value");
1316 else if (INTVAL (x) >= 0)
1323 /* If constant, output low-order five bits. Otherwise,
1326 fprintf (file, "%d", INT_LOWPART (x) & 31);
1328 print_operand (file, x, 0);
1332 /* Print `i' if this is a constant, else nothing. */
1338 /* Write the bit number in CCR for jump. */
1341 output_operand_lossage ("invalid %%j code");
1343 fprintf (file, "%d", i);
1347 /* Similar, but add one for shift count in rlinm for scc and pass
1348 scc flag to `ccr_bit'. */
1351 output_operand_lossage ("invalid %%J code");
1353 /* If we want bit 31, write a shift count of zero, not 32. */
1354 fprintf (file, "%d", i == 31 ? 0 : i + 1);
1358 /* X must be a constant. Write the 1's complement of the
1361 output_operand_lossage ("invalid %%k value");
1363 fprintf (file, "%d", ~ INT_LOWPART (x));
1367 /* Write second word of DImode or DFmode reference. Works on register
1368 or non-indexed memory only. */
1369 if (GET_CODE (x) == REG)
1370 fprintf (file, "%d", REGNO (x) + 1);
1371 else if (GET_CODE (x) == MEM)
1373 /* Handle possible auto-increment. Since it is pre-increment and
1374 we have already done it, we can just use an offset of four. */
1375 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1376 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1377 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1379 output_address (plus_constant (XEXP (x, 0), 4));
1384 /* MB value for a mask operand. */
1385 if (! mask_operand (x, VOIDmode))
1386 output_operand_lossage ("invalid %%m value");
1388 val = INT_LOWPART (x);
1390 /* If the high bit is set and the low bit is not, the value is zero.
1391 If the high bit is zero, the value is the first 1 bit we find from
1393 if (val < 0 && (val & 1) == 0)
1395 fprintf (file, "0");
1400 for (i = 1; i < 32; i++)
1401 if ((val <<= 1) < 0)
1403 fprintf (file, "%d", i);
1407 /* Otherwise, look for the first 0 bit from the right. The result is its
1408 number plus 1. We know the low-order bit is one. */
1409 for (i = 0; i < 32; i++)
1410 if (((val >>= 1) & 1) == 0)
1413 /* If we ended in ...01, I would be 0. The correct value is 31, so
1415 fprintf (file, "%d", 31 - i);
1419 /* ME value for a mask operand. */
1420 if (! mask_operand (x, VOIDmode))
1421 output_operand_lossage ("invalid %%m value");
1423 val = INT_LOWPART (x);
1425 /* If the low bit is set and the high bit is not, the value is 31.
1426 If the low bit is zero, the value is the first 1 bit we find from
1428 if ((val & 1) && val >= 0)
1433 else if ((val & 1) == 0)
1435 for (i = 0; i < 32; i++)
1436 if ((val >>= 1) & 1)
1439 /* If we had ....10, I would be 0. The result should be
1440 30, so we need 30 - i. */
1441 fprintf (file, "%d", 30 - i);
1445 /* Otherwise, look for the first 0 bit from the left. The result is its
1446 number minus 1. We know the high-order bit is one. */
1447 for (i = 0; i < 32; i++)
1448 if ((val <<= 1) >= 0)
1451 fprintf (file, "%d", i);
1455 /* Write the number of elements in the vector times 4. */
1456 if (GET_CODE (x) != PARALLEL)
1457 output_operand_lossage ("invalid %%N value");
1459 fprintf (file, "%d", XVECLEN (x, 0) * 4);
1463 /* Similar, but subtract 1 first. */
1464 if (GET_CODE (x) != PARALLEL)
1465 output_operand_lossage ("invalid %%N value");
1467 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
1471 /* X is a CONST_INT that is a power of two. Output the logarithm. */
1473 || (i = exact_log2 (INT_LOWPART (x))) < 0)
1474 output_operand_lossage ("invalid %%p value");
1476 fprintf (file, "%d", i);
1480 /* The operand must be an indirect memory reference. The result
1481 is the register number. */
1482 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
1483 || REGNO (XEXP (x, 0)) >= 32)
1484 output_operand_lossage ("invalid %%P value");
1486 fprintf (file, "%d", REGNO (XEXP (x, 0)));
1490 /* X is a CR register. Print the mask for `mtcrf'. */
1491 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1492 output_operand_lossage ("invalid %%R value");
1494 fprintf (file, "%d", 128 >> (REGNO (x) - 68));
1498 /* Low 5 bits of 32 - value */
1500 output_operand_lossage ("invalid %%s value");
1502 fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
1506 /* Write 12 if this jump operation will branch if true, 4 otherwise.
1507 All floating-point operations except NE branch true and integer
1508 EQ, LT, GT, LTU and GTU also branch true. */
1509 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1510 output_operand_lossage ("invalid %%t value");
1512 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1513 && GET_CODE (x) != NE)
1514 || GET_CODE (x) == EQ
1515 || GET_CODE (x) == LT || GET_CODE (x) == GT
1516 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1523 /* Opposite of 't': write 4 if this jump operation will branch if true,
1525 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1526 output_operand_lossage ("invalid %%t value");
1528 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1529 && GET_CODE (x) != NE)
1530 || GET_CODE (x) == EQ
1531 || GET_CODE (x) == LT || GET_CODE (x) == GT
1532 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1539 /* High-order 16 bits of constant. */
1541 output_operand_lossage ("invalid %%u value");
1543 fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
1547 /* Print `u' if this has an auto-increment or auto-decrement. */
1548 if (GET_CODE (x) == MEM
1549 && (GET_CODE (XEXP (x, 0)) == PRE_INC
1550 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
1555 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
1558 fprintf (file, "%d",
1559 (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
1561 print_operand (file, x, 0);
1565 /* If constant, low-order 16 bits of constant, unsigned.
1566 Otherwise, write normally. */
1568 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
1570 print_operand (file, x, 0);
1574 if (GET_CODE (x) == MEM
1575 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0)))
1580 /* Like 'L', for third word of TImode */
1581 if (GET_CODE (x) == REG)
1582 fprintf (file, "%d", REGNO (x) + 2);
1583 else if (GET_CODE (x) == MEM)
1585 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1586 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1587 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
1589 output_address (plus_constant (XEXP (x, 0), 8));
1594 /* X is a SYMBOL_REF. Write out the name preceded by a
1595 period and without any trailing data in brackets. Used for function
1596 names. If we are configured for System V (or the embedded ABI) on
1597 the PowerPC, do not emit the period, since those systems do not use
1598 TOCs and the like. */
1599 if (GET_CODE (x) != SYMBOL_REF)
1602 #ifndef USING_SVR4_H
1605 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
1609 /* Like 'L', for last word of TImode. */
1610 if (GET_CODE (x) == REG)
1611 fprintf (file, "%d", REGNO (x) + 3);
1612 else if (GET_CODE (x) == MEM)
1614 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1615 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1616 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
1618 output_address (plus_constant (XEXP (x, 0), 12));
1623 if (GET_CODE (x) == REG)
1624 fprintf (file, "%s", reg_names[REGNO (x)]);
1625 else if (GET_CODE (x) == MEM)
1627 /* We need to handle PRE_INC and PRE_DEC here, since we need to
1628 know the width from the mode. */
1629 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
1630 fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)),
1631 REGNO (XEXP (XEXP (x, 0), 0)));
1632 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
1633 fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)),
1634 REGNO (XEXP (XEXP (x, 0), 0)));
1636 output_address (XEXP (x, 0));
1639 output_addr_const (file, x);
1643 output_operand_lossage ("invalid %%xn code");
1647 /* Print the address of an operand. */
1650 print_operand_address (file, x)
1654 if (GET_CODE (x) == REG)
1655 fprintf (file, "0(%d)", REGNO (x));
1656 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
1658 output_addr_const (file, x);
1659 /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead
1660 of the toc pointer. */
1661 if (TARGET_MINIMAL_TOC)
1662 fprintf (file, "(30)");
1664 fprintf (file, "(2)");
1666 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
1668 if (REGNO (XEXP (x, 0)) == 0)
1669 fprintf (file, "%d,%d", REGNO (XEXP (x, 1)), REGNO (XEXP (x, 0)));
1671 fprintf (file, "%d,%d", REGNO (XEXP (x, 0)), REGNO (XEXP (x, 1)));
1673 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1674 fprintf (file, "%d(%d)", INTVAL (XEXP (x, 1)), REGNO (XEXP (x, 0)));
1679 /* This page contains routines that are used to determine what the function
1680 prologue and epilogue code will do and write them out. */
1682 /* Return the first fixed-point register that is required to be saved. 32 if
1686 first_reg_to_save ()
1690 /* Find lowest numbered live register. */
1691 for (first_reg = 13; first_reg <= 31; first_reg++)
1692 if (regs_ever_live[first_reg])
1695 /* If profiling, then we must save/restore every register that contains
1696 a parameter before/after the .mcount call. Use registers from 30 down
1697 to 23 to do this. Don't use the frame pointer in reg 31.
1699 For now, save enough room for all of the parameter registers. */
1707 /* Similar, for FP regs. */
1710 first_fp_reg_to_save ()
1714 /* Find lowest numbered live register. */
1715 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
1716 if (regs_ever_live[first_reg])
1722 /* Return 1 if we need to save CR. */
1727 return regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72];
1730 /* Compute the size of the save area in the stack, including the space for
1738 /* We have the six fixed words, plus the size of the register save
1739 areas, rounded to a double-word. */
1740 size = 6 + (32 - first_reg_to_save ()) + (64 - first_fp_reg_to_save ()) * 2;
1747 /* Return non-zero if this function makes calls. */
1750 rs6000_makes_calls ()
1754 /* If we are profiling, we will be making a call to mcount. */
1758 for (insn = get_insns (); insn; insn = next_insn (insn))
1759 if (GET_CODE (insn) == CALL_INSN)
1765 /* Return non-zero if this function needs to push space on the stack. */
1768 rs6000_pushes_stack ()
1770 int total_size = (rs6000_sa_size () + get_frame_size ()
1771 + current_function_outgoing_args_size);
1773 /* We need to push the stack if a frame pointer is needed (because the
1774 stack might be dynamically adjusted), if we are debugging, if the
1775 total stack size is more than 220 bytes, or if we make calls. */
1777 return (frame_pointer_needed || write_symbols != NO_DEBUG
1779 || rs6000_makes_calls ());
1783 /* Write out a System V.4 style traceback table before the prologue
1785 At present, only emit the basic tag table (ie, do not emit tag_types other
1786 than 0, which might use more than 1 tag word).
1788 The first tag word looks like:
1791 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1792 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1793 | 0 |ver| tag |e|s| alloca | # fprs | # gprs |s|l|c|f|
1794 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1799 svr4_traceback (file, name, decl)
1804 int first_reg = first_reg_to_save ();
1805 int first_fp_reg = first_fp_reg_to_save ();
1806 int pushes_stack = rs6000_pushes_stack ();
1808 long version = 0; /* version number */
1809 long tag_type = 0; /* function type */
1810 long extended_tag = 0; /* additional tag words needed */
1811 long spare = 0; /* reserved for future use */
1812 long alloca_reg; /* stack/frame register */
1813 long fpr_max = 64 - first_fp_reg; /* # of floating point registers saved */
1814 long gpr_max = 32 - first_reg; /* # of general purpose registers saved */
1815 long sp_max; /* 1 if the function acquires a stack frame */
1816 long lr_max; /* 1 if the function stores the link register */
1817 long cr_max; /* 1 if the function has a CR save word */
1818 long fpscr_max = 0; /* 1 if the function has a FPSCR save word */
1820 if (frame_pointer_needed)
1823 else if (pushes_stack != 0)
1829 lr_max = (regs_ever_live[65] || first_fp_reg < 62 || profile_flag);
1830 cr_max = (must_save_cr () != 0);
1831 sp_max = (pushes_stack != 0);
1833 tag = (((version & 3) << 24)
1834 | ((tag_type & 7) << 21)
1835 | ((extended_tag & 1) << 20)
1836 | ((spare & 1) << 19)
1837 | ((alloca_reg & 0x1f) << 14)
1838 | ((fpr_max & 0x1f) << 9)
1839 | ((gpr_max & 0x1f) << 4)
1840 | ((sp_max & 1) << 3)
1841 | ((lr_max & 1) << 2)
1842 | ((cr_max & 1) << 1)
1843 | ((fpscr_max & 1) << 0));
1845 fprintf (file, "\t.long 0x%lx\n", tag);
1848 #endif /* USING_SVR4_H */
1850 /* Write function prologue. */
1853 output_prolog (file, size)
1857 int first_reg = first_reg_to_save ();
1858 int must_push = rs6000_pushes_stack ();
1859 int first_fp_reg = first_fp_reg_to_save ();
1860 int basic_size = rs6000_sa_size ();
1861 int total_size = (basic_size + size + current_function_outgoing_args_size);
1864 /* If this is eabi, call __eabi with main, but do so before the minimal TOC
1865 is setup, so we can't use the normal mechanism. */
1866 #if defined(USING_SVR4_H) && defined(NAME__MAIN) && !defined(INVOKE__main)
1869 if (IDENTIFIER_LENGTH (DECL_NAME (current_function_decl)) == 4
1870 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), "main"))
1873 regs_ever_live[65] = 1;
1877 /* Round size to multiple of 8 bytes. */
1878 total_size = (total_size + 7) & ~7;
1880 /* Write .extern for any function we will call to save and restore fp
1882 if (first_fp_reg < 62)
1883 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
1884 SAVE_FP_PREFIX, first_fp_reg - 32, SAVE_FP_SUFFIX,
1885 RESTORE_FP_PREFIX, first_fp_reg - 32, RESTORE_FP_SUFFIX);
1887 /* Write .extern for truncation routines, if needed. */
1888 if (rs6000_trunc_used && ! trunc_defined)
1890 fprintf (file, "\t.extern .%s\n\t.extern .%s\n",
1891 RS6000_ITRUNC, RS6000_UITRUNC);
1894 /* Write .extern for AIX common mode routines, if needed. */
1895 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
1897 fputs ("\t.extern __mulh\n", file);
1898 fputs ("\t.extern __mull\n", file);
1899 fputs ("\t.extern __divss\n", file);
1900 fputs ("\t.extern __divus\n", file);
1901 fputs ("\t.extern __quoss\n", file);
1902 fputs ("\t.extern __quous\n", file);
1903 common_mode_defined = 1;
1907 /* If we have a relocatable GOT section, we need to save the LR. */
1908 if (TARGET_RELOCATABLE && get_pool_size () != 0)
1909 regs_ever_live[65] = 1;
1912 /* If we have to call a function to save fpr's, or if we are doing profiling,
1913 then we will be using LR. */
1914 if (first_fp_reg < 62 || profile_flag)
1915 regs_ever_live[65] = 1;
1917 /* If we use the link register, get it into r0. */
1918 if (regs_ever_live[65])
1919 asm_fprintf (file, "\tmflr 0\n");
1921 /* If we need to save CR, put it into r12. */
1922 if (must_save_cr ())
1923 asm_fprintf (file, "\tmfcr 12\n");
1925 /* Do any required saving of fpr's. If only one or two to save, do it
1926 ourself. Otherwise, call function. Note that since they are statically
1927 linked, we do not need a nop following them. */
1928 if (first_fp_reg == 62)
1929 asm_fprintf (file, "\tstfd 30,-16(1)\n\tstfd 31,-8(1)\n");
1930 else if (first_fp_reg == 63)
1931 asm_fprintf (file, "\tstfd 31,-8(1)\n");
1932 else if (first_fp_reg != 64)
1933 asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX, first_fp_reg - 32, SAVE_FP_SUFFIX);
1935 /* Now save gpr's. */
1936 if (! TARGET_MULTIPLE || first_reg == 31)
1940 for (regno = first_reg,
1941 loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8;
1944 asm_fprintf (file, "\t{st|stw} %d,%d(1)\n", regno, loc);
1947 else if (first_reg != 32)
1948 asm_fprintf (file, "\t{stm|stmw} %d,%d(1)\n", first_reg,
1949 - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8);
1951 /* Save lr if we used it. */
1952 if (regs_ever_live[65])
1953 asm_fprintf (file, "\t{st|stw} 0,8(1)\n");
1955 /* Save CR if we use any that must be preserved. */
1956 if (must_save_cr ())
1957 asm_fprintf (file, "\t{st|stw} 12,4(1)\n");
1959 /* Update stack and set back pointer. */
1962 if (total_size < 32767)
1963 asm_fprintf (file, "\t{stu|stwu} 1,%d(1)\n", - total_size);
1966 asm_fprintf (file, "\t{liu|lis} 0,%d\n\t{oril|ori} 0,0,%d\n",
1967 (total_size >> 16) & 0xffff, total_size & 0xffff);
1969 asm_fprintf (file, "\tsubf 12,0,1\n");
1971 asm_fprintf (file, "\t{sf|subfc} 12,0,1\n");
1972 asm_fprintf (file, "\t{st|stw} 1,0(12)\n\tmr 1,12\n");
1976 /* Set frame pointer, if needed. */
1977 if (frame_pointer_needed)
1978 asm_fprintf (file, "\tmr 31,1\n");
1980 /* If this is eabi, call __eabi before loading up the minimal TOC */
1981 #if defined(USING_SVR4_H) && defined(NAME__MAIN) && !defined(INVOKE__main)
1983 fprintf (file, "\tbl %s\n", NAME__MAIN);
1986 /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
1987 TOC_TABLE address into register 30. */
1988 if (TARGET_MINIMAL_TOC && get_pool_size () != 0)
1993 if (TARGET_RELOCATABLE)
1995 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
1996 fprintf (file, "\tbl ");
1997 assemble_name (file, buf);
1998 fprintf (file, "\n");
2000 ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno);
2001 fprintf (file, "\tmflr 30\n");
2003 if (TARGET_POWERPC64)
2004 fprintf (file, "\tld 0,");
2005 else if (TARGET_NEW_MNEMONICS)
2006 fprintf (file, "\tlwz 0,");
2008 fprintf (file, "\tl 0,");
2010 fprintf (file, "(");
2011 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
2012 assemble_name (file, buf);
2013 fprintf (file, "-");
2014 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
2015 assemble_name (file, buf);
2016 fprintf (file, ")(30)\n");
2017 asm_fprintf (file, "\t{cax|add} 30,0,30\n");
2018 rs6000_pic_labelno++;
2020 else if (TARGET_NO_TOC)
2022 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
2023 asm_fprintf (file, "\t{cau|addis} 30,0,");
2024 assemble_name (file, buf);
2025 asm_fprintf (file, "@ha\n");
2026 asm_fprintf (file, "\t{cal|addi} 30,30,");
2027 assemble_name (file, buf);
2028 asm_fprintf (file, "@l\n");
2031 #endif /* USING_SVR4_H */
2033 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0);
2034 asm_fprintf (file, "\t{l|lwz} 30,");
2035 assemble_name (file, buf);
2036 asm_fprintf (file, "(2)\n");
2041 /* Write function epilogue. */
2044 output_epilog (file, size)
2048 int first_reg = first_reg_to_save ();
2049 int must_push = rs6000_pushes_stack ();
2050 int first_fp_reg = first_fp_reg_to_save ();
2051 int basic_size = rs6000_sa_size ();
2052 int total_size = (basic_size + size + current_function_outgoing_args_size);
2053 rtx insn = get_last_insn ();
2055 /* Round size to multiple of 8 bytes. */
2056 total_size = (total_size + 7) & ~7;
2058 /* If the last insn was a BARRIER, we don't have to write anything except
2060 if (GET_CODE (insn) == NOTE)
2061 insn = prev_nonnote_insn (insn);
2062 if (insn == 0 || GET_CODE (insn) != BARRIER)
2064 /* If we have a frame pointer, a call to alloca, or a large stack
2065 frame, restore the old stack pointer using the backchain. Otherwise,
2066 we know what size to update it with. */
2067 if (frame_pointer_needed || current_function_calls_alloca
2068 || total_size > 32767)
2069 asm_fprintf (file, "\t{l|lwz} 1,0(1)\n");
2071 asm_fprintf (file, "\t{cal 1,%d(1)|addi 1,1,%d}\n", total_size);
2073 /* Get the old lr if we saved it. */
2074 if (regs_ever_live[65])
2075 asm_fprintf (file, "\t{l|lwz} 0,8(1)\n");
2077 /* Get the old cr if we saved it. */
2078 if (must_save_cr ())
2079 asm_fprintf (file, "\t{l|lwz} 12,4(1)\n");
2081 /* Set LR here to try to overlap restores below. */
2082 if (regs_ever_live[65])
2083 asm_fprintf (file, "\tmtlr 0\n");
2085 /* Restore gpr's. */
2086 if (! TARGET_MULTIPLE || first_reg == 31)
2090 for (regno = first_reg,
2091 loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8;
2094 asm_fprintf (file, "\t{l|lwz} %d,%d(1)\n", regno, loc);
2097 else if (first_reg != 32)
2098 asm_fprintf (file, "\t{lm|lmw} %d,%d(1)\n", first_reg,
2099 - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8);
2101 /* Restore fpr's if we can do it without calling a function. */
2102 if (first_fp_reg == 62)
2103 asm_fprintf (file, "\tlfd 30,-16(1)\n\tlfd 31,-8(1)\n");
2104 else if (first_fp_reg == 63)
2105 asm_fprintf (file, "\tlfd 31,-8(1)\n");
2107 /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
2109 if (must_save_cr ())
2110 asm_fprintf (file, "\tmtcrf %d,12\n",
2111 (regs_ever_live[70] != 0) * 0x20
2112 + (regs_ever_live[71] != 0) * 0x10
2113 + (regs_ever_live[72] != 0) * 0x8);
2115 /* If we have to restore more than two FP registers, branch to the
2116 restore function. It will return to our caller. */
2117 if (first_fp_reg < 62)
2118 asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX, first_fp_reg - 32, RESTORE_FP_SUFFIX);
2120 asm_fprintf (file, "\t{br|blr}\n");
2123 /* Output a traceback table here. See /usr/include/sys/debug.h for info
2126 We don't output a traceback table if -finhibit-size-directive was
2127 used. The documentation for -finhibit-size-directive reads
2128 ``don't output a @code{.size} assembler directive, or anything
2129 else that would cause trouble if the function is split in the
2130 middle, and the two halves are placed at locations far apart in
2131 memory.'' The traceback table has this property, since it
2132 includes the offset from the start of the function to the
2133 traceback table itself.
2135 System V.4 Powerpc's (and the embedded ABI derived from it) use a
2136 different traceback table located before the prologue. */
2137 #ifndef USING_SVR4_H
2138 if (! flag_inhibit_size_directive)
2140 char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
2141 int fixed_parms, float_parms, parm_info;
2144 /* Need label immediately before tbtab, so we can compute its offset
2145 from the function start. */
2148 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
2149 ASM_OUTPUT_LABEL (file, fname);
2151 /* The .tbtab pseudo-op can only be used for the first eight
2152 expressions, since it can't handle the possibly variable
2153 length fields that follow. However, if you omit the optional
2154 fields, the assembler outputs zeros for all optional fields
2155 anyways, giving each variable length field is minimum length
2156 (as defined in sys/debug.h). Thus we can not use the .tbtab
2157 pseudo-op at all. */
2159 /* An all-zero word flags the start of the tbtab, for debuggers
2160 that have to find it by searching forward from the entry
2161 point or from the current pc. */
2162 fprintf (file, "\t.long 0\n");
2164 /* Tbtab format type. Use format type 0. */
2165 fprintf (file, "\t.byte 0,");
2167 /* Language type. Unfortunately, there doesn't seem to be any
2168 official way to get this info, so we use language_string. C
2169 is 0. C++ is 9. No number defined for Obj-C, so use the
2170 value for C for now. */
2171 if (! strcmp (language_string, "GNU C")
2172 || ! strcmp (language_string, "GNU Obj-C"))
2174 else if (! strcmp (language_string, "GNU F77"))
2176 else if (! strcmp (language_string, "GNU Ada"))
2178 else if (! strcmp (language_string, "GNU PASCAL"))
2180 else if (! strcmp (language_string, "GNU C++"))
2184 fprintf (file, "%d,", i);
2186 /* 8 single bit fields: global linkage (not set for C extern linkage,
2187 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
2188 from start of procedure stored in tbtab, internal function, function
2189 has controlled storage, function has no toc, function uses fp,
2190 function logs/aborts fp operations. */
2191 /* Assume that fp operations are used if any fp reg must be saved. */
2192 fprintf (file, "%d,", (1 << 5) | ((first_fp_reg != 64) << 1));
2194 /* 6 bitfields: function is interrupt handler, name present in
2195 proc table, function calls alloca, on condition directives
2196 (controls stack walks, 3 bits), saves condition reg, saves
2198 /* The `function calls alloca' bit seems to be set whenever reg 31 is
2199 set up as a frame pointer, even when there is no alloca call. */
2200 fprintf (file, "%d,",
2201 ((1 << 6) | (frame_pointer_needed << 5)
2202 | (must_save_cr () << 1) | (regs_ever_live[65])));
2204 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
2206 fprintf (file, "%d,",
2207 (must_push << 7) | (64 - first_fp_reg_to_save ()));
2209 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
2210 fprintf (file, "%d,", (32 - first_reg_to_save ()));
2213 /* Compute the parameter info from the function decl argument
2216 int next_parm_info_bit;
2218 next_parm_info_bit = 31;
2223 for (decl = DECL_ARGUMENTS (current_function_decl);
2224 decl; decl = TREE_CHAIN (decl))
2226 rtx parameter = DECL_INCOMING_RTL (decl);
2227 enum machine_mode mode = GET_MODE (parameter);
2229 if (GET_CODE (parameter) == REG)
2231 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2239 else if (mode == DFmode)
2244 /* If only one bit will fit, don't or in this entry. */
2245 if (next_parm_info_bit > 0)
2246 parm_info |= (bits << (next_parm_info_bit - 1));
2247 next_parm_info_bit -= 2;
2251 fixed_parms += ((GET_MODE_SIZE (mode)
2252 + (UNITS_PER_WORD - 1))
2254 next_parm_info_bit -= 1;
2260 /* Number of fixed point parameters. */
2261 /* This is actually the number of words of fixed point parameters; thus
2262 an 8 byte struct counts as 2; and thus the maximum value is 8. */
2263 fprintf (file, "%d,", fixed_parms);
2265 /* 2 bitfields: number of floating point parameters (7 bits), parameters
2267 /* This is actually the number of fp registers that hold parameters;
2268 and thus the maximum value is 13. */
2269 /* Set parameters on stack bit if parameters are not in their original
2270 registers, regardless of whether they are on the stack? Xlc
2271 seems to set the bit when not optimizing. */
2272 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
2274 /* Optional fields follow. Some are variable length. */
2276 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
2278 /* There is an entry for each parameter in a register, in the order that
2279 they occur in the parameter list. Any intervening arguments on the
2280 stack are ignored. If the list overflows a long (max possible length
2281 34 bits) then completely leave off all elements that don't fit. */
2282 /* Only emit this long if there was at least one parameter. */
2283 if (fixed_parms || float_parms)
2284 fprintf (file, "\t.long %d\n", parm_info);
2286 /* Offset from start of code to tb table. */
2287 fprintf (file, "\t.long ");
2288 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
2289 RS6000_OUTPUT_BASENAME (file, fname);
2290 fprintf (file, "-.");
2291 RS6000_OUTPUT_BASENAME (file, fname);
2292 fprintf (file, "\n");
2294 /* Interrupt handler mask. */
2295 /* Omit this long, since we never set the interrupt handler bit
2298 /* Number of CTL (controlled storage) anchors. */
2299 /* Omit this long, since the has_ctl bit is never set above. */
2301 /* Displacement into stack of each CTL anchor. */
2302 /* Omit this list of longs, because there are no CTL anchors. */
2304 /* Length of function name. */
2305 fprintf (file, "\t.short %d\n", strlen (fname));
2307 /* Function name. */
2308 assemble_string (fname, strlen (fname));
2310 /* Register for alloca automatic storage; this is always reg 31.
2311 Only emit this if the alloca bit was set above. */
2312 if (frame_pointer_needed)
2313 fprintf (file, "\t.byte 31\n");
2315 #endif /* !USING_SVR4_H */
2318 /* Output a TOC entry. We derive the entry name from what is
2322 output_toc (file, x, labelno)
2333 if (TARGET_MINIMAL_TOC)
2335 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
2336 fprintf (file, "%d = .-", labelno);
2337 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC");
2338 fprintf (file, "1\n");
2341 #endif /* USING_SVR4_H */
2342 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
2344 /* Handle FP constants specially. Note that if we have a minimal
2345 TOC, things we put here aren't actually in the TOC, so we can allow
2347 if (GET_CODE (x) == CONST_DOUBLE
2348 && GET_MODE (x) == DFmode
2349 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
2354 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2355 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
2356 if (TARGET_MINIMAL_TOC)
2357 fprintf (file, "\t.long %ld\n\t.long %ld\n", l[0], l[1]);
2359 fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n",
2360 l[0], l[1], l[0], l[1]);
2363 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode
2364 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
2366 rtx val = operand_subword (x, 0, 0, SFmode);
2368 if (val == 0 || GET_CODE (val) != CONST_INT)
2371 if (TARGET_MINIMAL_TOC)
2372 fprintf (file, "\t.long %d\n", INTVAL (val));
2374 fprintf (file, "\t.tc FS_%x[TC],%d\n", INTVAL (val), INTVAL (val));
2378 if (GET_CODE (x) == CONST)
2380 base = XEXP (XEXP (x, 0), 0);
2381 offset = INTVAL (XEXP (XEXP (x, 0), 1));
2384 if (GET_CODE (base) == SYMBOL_REF)
2385 name = XSTR (base, 0);
2386 else if (GET_CODE (base) == LABEL_REF)
2387 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
2388 else if (GET_CODE (base) == CODE_LABEL)
2389 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
2393 if (TARGET_MINIMAL_TOC)
2394 fprintf (file, "\t.long ");
2397 fprintf (file, "\t.tc ");
2398 RS6000_OUTPUT_BASENAME (file, name);
2401 fprintf (file, ".N%d", - offset);
2403 fprintf (file, ".P%d", offset);
2405 fprintf (file, "[TC],");
2407 output_addr_const (file, x);
2408 fprintf (file, "\n");
2411 /* Output an assembler pseudo-op to write an ASCII string of N characters
2412 starting at P to FILE.
2414 On the RS/6000, we have to do this using the .byte operation and
2415 write out special characters outside the quoted string.
2416 Also, the assembler is broken; very long strings are truncated,
2417 so we must artificially break them up early. */
2420 output_ascii (file, p, n)
2426 int i, count_string;
2427 char *for_string = "\t.byte \"";
2428 char *for_decimal = "\t.byte ";
2429 char *to_close = NULL;
2432 for (i = 0; i < n; i++)
2435 if (c >= ' ' && c < 0177)
2438 fputs (for_string, file);
2441 /* Write two quotes to get one. */
2449 for_decimal = "\"\n\t.byte ";
2453 if (count_string >= 512)
2455 fputs (to_close, file);
2457 for_string = "\t.byte \"";
2458 for_decimal = "\t.byte ";
2466 fputs (for_decimal, file);
2467 fprintf (file, "%d", c);
2469 for_string = "\n\t.byte \"";
2476 /* Now close the string if we have written one. Then end the line. */
2478 fprintf (file, to_close);
2481 /* Generate a unique section name for FILENAME for a section type
2482 represented by SECTION_DESC. Output goes into BUF.
2484 SECTION_DESC can be any string, as long as it is different for each
2485 possible section type.
2487 We name the section in the same manner as xlc. The name begins with an
2488 underscore followed by the filename (after stripping any leading directory
2489 names) with the last period replaced by the string SECTION_DESC. If
2490 FILENAME does not contain a period, SECTION_DESC is appended to the end of
2494 rs6000_gen_section_name (buf, filename, section_desc)
2499 char *q, *after_last_slash, *last_period;
2503 after_last_slash = filename;
2504 for (q = filename; *q; q++)
2507 after_last_slash = q + 1;
2512 len = strlen (after_last_slash) + strlen (section_desc) + 2;
2513 *buf = (char *) permalloc (len);
2518 for (q = after_last_slash; *q; q++)
2520 if (q == last_period)
2522 strcpy (p, section_desc);
2523 p += strlen (section_desc);
2526 else if (isalnum (*q))
2530 if (last_period == 0)
2531 strcpy (p, section_desc);
2536 /* Write function profiler code. */
2539 output_function_profiler (file, labelno)
2546 /* The last used parameter register. */
2551 /* Set up a TOC entry for the profiler label. */
2553 ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno);
2554 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
2555 if (TARGET_MINIMAL_TOC)
2557 fprintf (file, "\t.long ");
2558 assemble_name (file, buf);
2559 fprintf (file, "\n");
2563 fprintf (file, "\t.tc\t");
2564 assemble_name (file, buf);
2565 fprintf (file, "[TC],");
2566 assemble_name (file, buf);
2567 fprintf (file, "\n");
2571 /* Figure out last used parameter register. The proper thing to do is
2572 to walk incoming args of the function. A function might have live
2573 parameter registers even if it has no incoming args. */
2575 for (last_parm_reg = 10;
2576 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
2580 /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since
2581 it might be set up as the frame pointer. */
2583 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
2584 fprintf (file, "\tai %d,%d,0\n", j, i);
2586 /* Load location address into r3, and call mcount. */
2588 ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno);
2589 fprintf (file, "\tl 3,");
2590 assemble_name (file, buf);
2591 fprintf (file, "(2)\n\tbl .mcount\n");
2593 /* Restore parameter registers. */
2595 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
2596 fprintf (file, "\tai %d,%d,0\n", i, j);
2600 /* Adjust the cost of a scheduling dependency. Return the new cost of
2601 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
2604 rs6000_adjust_cost (insn, link, dep_insn, cost)
2610 if (! recog_memoized (insn))
2613 if (REG_NOTE_KIND (link) != 0)
2616 if (REG_NOTE_KIND (link) == 0)
2618 /* Data dependency; DEP_INSN writes a register that INSN reads some
2621 /* Tell the first scheduling pass about the latency between a mtctr
2622 and bctr (and mtlr and br/blr). The first scheduling pass will not
2623 know about this latency since the mtctr instruction, which has the
2624 latency associated to it, will be generated by reload. */
2625 if (get_attr_type (insn) == TYPE_JMPREG)
2626 return TARGET_POWER ? 5 : 4;
2628 /* Fall out to return default cost. */