1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
61 #include "gstab.h" /* for N_SLINE */
64 #ifndef TARGET_NO_PROTOTYPE
65 #define TARGET_NO_PROTOTYPE 0
68 #define min(A,B) ((A) < (B) ? (A) : (B))
69 #define max(A,B) ((A) > (B) ? (A) : (B))
71 /* Structure used to define the rs6000 stack */
72 typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
82 int world_save_p; /* true if we're saving *everything*:
83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
116 /* Target cpu type */
118 enum processor_type rs6000_cpu;
119 struct rs6000_cpu_select rs6000_select[3] =
121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
127 /* Always emit branch hint bits. */
128 static GTY(()) bool rs6000_always_hint;
130 /* Schedule instructions for group formation. */
131 static GTY(()) bool rs6000_sched_groups;
133 /* Support for -msched-costly-dep option. */
134 const char *rs6000_sched_costly_dep_str;
135 enum rs6000_dependence_cost rs6000_sched_costly_dep;
137 /* Support for -minsert-sched-nops option. */
138 const char *rs6000_sched_insert_nops_str;
139 enum rs6000_nop_insertion rs6000_sched_insert_nops;
141 /* Support targetm.vectorize.builtin_mask_for_load. */
142 static GTY(()) tree altivec_builtin_mask_for_load;
144 /* Size of long double */
145 int rs6000_long_double_type_size;
147 /* Whether -mabi=altivec has appeared */
148 int rs6000_altivec_abi;
150 /* Nonzero if we want SPE ABI extensions. */
153 /* Nonzero if floating point operations are done in the GPRs. */
154 int rs6000_float_gprs = 0;
156 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
157 int rs6000_darwin64_abi;
159 /* Set to nonzero once AIX common-mode calls have been defined. */
160 static GTY(()) int common_mode_defined;
162 /* Save information from a "cmpxx" operation until the branch or scc is
164 rtx rs6000_compare_op0, rs6000_compare_op1;
165 int rs6000_compare_fp_p;
167 /* Label number of label created for -mrelocatable, to call to so we can
168 get the address of the GOT section */
169 int rs6000_pic_labelno;
172 /* Which abi to adhere to */
173 const char *rs6000_abi_name;
175 /* Semantics of the small data area */
176 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
178 /* Which small data model to use */
179 const char *rs6000_sdata_name = (char *)0;
181 /* Counter for labels which are to be placed in .fixup. */
182 int fixuplabelno = 0;
185 /* Bit size of immediate TLS offsets and string from which it is decoded. */
186 int rs6000_tls_size = 32;
187 const char *rs6000_tls_size_string;
189 /* ABI enumeration available for subtarget to use. */
190 enum rs6000_abi rs6000_current_abi;
192 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
196 const char *rs6000_debug_name;
197 int rs6000_debug_stack; /* debug stack applications */
198 int rs6000_debug_arg; /* debug argument handling */
200 /* Value is TRUE if register/mode pair is acceptable. */
201 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
203 /* Built in types. */
205 tree rs6000_builtin_types[RS6000_BTI_MAX];
206 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
208 const char *rs6000_traceback_name;
210 traceback_default = 0,
216 /* Flag to say the TOC is initialized */
218 char toc_label_name[10];
220 /* Alias set for saves and restores from the rs6000 stack. */
221 static GTY(()) int rs6000_sr_alias_set;
223 /* Control alignment for fields within structures. */
224 /* String from -malign-XXXXX. */
225 int rs6000_alignment_flags;
227 /* True for any options that were explicitly set. */
229 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
230 bool alignment; /* True if -malign- was used. */
231 bool abi; /* True if -mabi= was used. */
232 bool spe; /* True if -mspe= was used. */
233 bool float_gprs; /* True if -mfloat-gprs= was used. */
234 bool isel; /* True if -misel was used. */
235 bool long_double; /* True if -mlong-double- was used. */
236 } rs6000_explicit_options;
238 struct builtin_description
240 /* mask is not const because we're going to alter it below. This
241 nonsense will go away when we rewrite the -march infrastructure
242 to give us more target flag bits. */
244 const enum insn_code icode;
245 const char *const name;
246 const enum rs6000_builtins code;
249 /* Target cpu costs. */
251 struct processor_costs {
252 const int mulsi; /* cost of SImode multiplication. */
253 const int mulsi_const; /* cost of SImode multiplication by constant. */
254 const int mulsi_const9; /* cost of SImode mult by short constant. */
255 const int muldi; /* cost of DImode multiplication. */
256 const int divsi; /* cost of SImode division. */
257 const int divdi; /* cost of DImode division. */
258 const int fp; /* cost of simple SFmode and DFmode insns. */
259 const int dmul; /* cost of DFmode multiplication (and fmadd). */
260 const int sdiv; /* cost of SFmode division (fdivs). */
261 const int ddiv; /* cost of DFmode division (fdiv). */
264 const struct processor_costs *rs6000_cost;
266 /* Processor costs (relative to an add) */
268 /* Instruction size costs on 32bit processors. */
270 struct processor_costs size32_cost = {
271 COSTS_N_INSNS (1), /* mulsi */
272 COSTS_N_INSNS (1), /* mulsi_const */
273 COSTS_N_INSNS (1), /* mulsi_const9 */
274 COSTS_N_INSNS (1), /* muldi */
275 COSTS_N_INSNS (1), /* divsi */
276 COSTS_N_INSNS (1), /* divdi */
277 COSTS_N_INSNS (1), /* fp */
278 COSTS_N_INSNS (1), /* dmul */
279 COSTS_N_INSNS (1), /* sdiv */
280 COSTS_N_INSNS (1), /* ddiv */
283 /* Instruction size costs on 64bit processors. */
285 struct processor_costs size64_cost = {
286 COSTS_N_INSNS (1), /* mulsi */
287 COSTS_N_INSNS (1), /* mulsi_const */
288 COSTS_N_INSNS (1), /* mulsi_const9 */
289 COSTS_N_INSNS (1), /* muldi */
290 COSTS_N_INSNS (1), /* divsi */
291 COSTS_N_INSNS (1), /* divdi */
292 COSTS_N_INSNS (1), /* fp */
293 COSTS_N_INSNS (1), /* dmul */
294 COSTS_N_INSNS (1), /* sdiv */
295 COSTS_N_INSNS (1), /* ddiv */
298 /* Instruction costs on RIOS1 processors. */
300 struct processor_costs rios1_cost = {
301 COSTS_N_INSNS (5), /* mulsi */
302 COSTS_N_INSNS (4), /* mulsi_const */
303 COSTS_N_INSNS (3), /* mulsi_const9 */
304 COSTS_N_INSNS (5), /* muldi */
305 COSTS_N_INSNS (19), /* divsi */
306 COSTS_N_INSNS (19), /* divdi */
307 COSTS_N_INSNS (2), /* fp */
308 COSTS_N_INSNS (2), /* dmul */
309 COSTS_N_INSNS (19), /* sdiv */
310 COSTS_N_INSNS (19), /* ddiv */
313 /* Instruction costs on RIOS2 processors. */
315 struct processor_costs rios2_cost = {
316 COSTS_N_INSNS (2), /* mulsi */
317 COSTS_N_INSNS (2), /* mulsi_const */
318 COSTS_N_INSNS (2), /* mulsi_const9 */
319 COSTS_N_INSNS (2), /* muldi */
320 COSTS_N_INSNS (13), /* divsi */
321 COSTS_N_INSNS (13), /* divdi */
322 COSTS_N_INSNS (2), /* fp */
323 COSTS_N_INSNS (2), /* dmul */
324 COSTS_N_INSNS (17), /* sdiv */
325 COSTS_N_INSNS (17), /* ddiv */
328 /* Instruction costs on RS64A processors. */
330 struct processor_costs rs64a_cost = {
331 COSTS_N_INSNS (20), /* mulsi */
332 COSTS_N_INSNS (12), /* mulsi_const */
333 COSTS_N_INSNS (8), /* mulsi_const9 */
334 COSTS_N_INSNS (34), /* muldi */
335 COSTS_N_INSNS (65), /* divsi */
336 COSTS_N_INSNS (67), /* divdi */
337 COSTS_N_INSNS (4), /* fp */
338 COSTS_N_INSNS (4), /* dmul */
339 COSTS_N_INSNS (31), /* sdiv */
340 COSTS_N_INSNS (31), /* ddiv */
343 /* Instruction costs on MPCCORE processors. */
345 struct processor_costs mpccore_cost = {
346 COSTS_N_INSNS (2), /* mulsi */
347 COSTS_N_INSNS (2), /* mulsi_const */
348 COSTS_N_INSNS (2), /* mulsi_const9 */
349 COSTS_N_INSNS (2), /* muldi */
350 COSTS_N_INSNS (6), /* divsi */
351 COSTS_N_INSNS (6), /* divdi */
352 COSTS_N_INSNS (4), /* fp */
353 COSTS_N_INSNS (5), /* dmul */
354 COSTS_N_INSNS (10), /* sdiv */
355 COSTS_N_INSNS (17), /* ddiv */
358 /* Instruction costs on PPC403 processors. */
360 struct processor_costs ppc403_cost = {
361 COSTS_N_INSNS (4), /* mulsi */
362 COSTS_N_INSNS (4), /* mulsi_const */
363 COSTS_N_INSNS (4), /* mulsi_const9 */
364 COSTS_N_INSNS (4), /* muldi */
365 COSTS_N_INSNS (33), /* divsi */
366 COSTS_N_INSNS (33), /* divdi */
367 COSTS_N_INSNS (11), /* fp */
368 COSTS_N_INSNS (11), /* dmul */
369 COSTS_N_INSNS (11), /* sdiv */
370 COSTS_N_INSNS (11), /* ddiv */
373 /* Instruction costs on PPC405 processors. */
375 struct processor_costs ppc405_cost = {
376 COSTS_N_INSNS (5), /* mulsi */
377 COSTS_N_INSNS (4), /* mulsi_const */
378 COSTS_N_INSNS (3), /* mulsi_const9 */
379 COSTS_N_INSNS (5), /* muldi */
380 COSTS_N_INSNS (35), /* divsi */
381 COSTS_N_INSNS (35), /* divdi */
382 COSTS_N_INSNS (11), /* fp */
383 COSTS_N_INSNS (11), /* dmul */
384 COSTS_N_INSNS (11), /* sdiv */
385 COSTS_N_INSNS (11), /* ddiv */
388 /* Instruction costs on PPC440 processors. */
390 struct processor_costs ppc440_cost = {
391 COSTS_N_INSNS (3), /* mulsi */
392 COSTS_N_INSNS (2), /* mulsi_const */
393 COSTS_N_INSNS (2), /* mulsi_const9 */
394 COSTS_N_INSNS (3), /* muldi */
395 COSTS_N_INSNS (34), /* divsi */
396 COSTS_N_INSNS (34), /* divdi */
397 COSTS_N_INSNS (5), /* fp */
398 COSTS_N_INSNS (5), /* dmul */
399 COSTS_N_INSNS (19), /* sdiv */
400 COSTS_N_INSNS (33), /* ddiv */
403 /* Instruction costs on PPC601 processors. */
405 struct processor_costs ppc601_cost = {
406 COSTS_N_INSNS (5), /* mulsi */
407 COSTS_N_INSNS (5), /* mulsi_const */
408 COSTS_N_INSNS (5), /* mulsi_const9 */
409 COSTS_N_INSNS (5), /* muldi */
410 COSTS_N_INSNS (36), /* divsi */
411 COSTS_N_INSNS (36), /* divdi */
412 COSTS_N_INSNS (4), /* fp */
413 COSTS_N_INSNS (5), /* dmul */
414 COSTS_N_INSNS (17), /* sdiv */
415 COSTS_N_INSNS (31), /* ddiv */
418 /* Instruction costs on PPC603 processors. */
420 struct processor_costs ppc603_cost = {
421 COSTS_N_INSNS (5), /* mulsi */
422 COSTS_N_INSNS (3), /* mulsi_const */
423 COSTS_N_INSNS (2), /* mulsi_const9 */
424 COSTS_N_INSNS (5), /* muldi */
425 COSTS_N_INSNS (37), /* divsi */
426 COSTS_N_INSNS (37), /* divdi */
427 COSTS_N_INSNS (3), /* fp */
428 COSTS_N_INSNS (4), /* dmul */
429 COSTS_N_INSNS (18), /* sdiv */
430 COSTS_N_INSNS (33), /* ddiv */
433 /* Instruction costs on PPC604 processors. */
435 struct processor_costs ppc604_cost = {
436 COSTS_N_INSNS (4), /* mulsi */
437 COSTS_N_INSNS (4), /* mulsi_const */
438 COSTS_N_INSNS (4), /* mulsi_const9 */
439 COSTS_N_INSNS (4), /* muldi */
440 COSTS_N_INSNS (20), /* divsi */
441 COSTS_N_INSNS (20), /* divdi */
442 COSTS_N_INSNS (3), /* fp */
443 COSTS_N_INSNS (3), /* dmul */
444 COSTS_N_INSNS (18), /* sdiv */
445 COSTS_N_INSNS (32), /* ddiv */
448 /* Instruction costs on PPC604e processors. */
450 struct processor_costs ppc604e_cost = {
451 COSTS_N_INSNS (2), /* mulsi */
452 COSTS_N_INSNS (2), /* mulsi_const */
453 COSTS_N_INSNS (2), /* mulsi_const9 */
454 COSTS_N_INSNS (2), /* muldi */
455 COSTS_N_INSNS (20), /* divsi */
456 COSTS_N_INSNS (20), /* divdi */
457 COSTS_N_INSNS (3), /* fp */
458 COSTS_N_INSNS (3), /* dmul */
459 COSTS_N_INSNS (18), /* sdiv */
460 COSTS_N_INSNS (32), /* ddiv */
463 /* Instruction costs on PPC620 processors. */
465 struct processor_costs ppc620_cost = {
466 COSTS_N_INSNS (5), /* mulsi */
467 COSTS_N_INSNS (4), /* mulsi_const */
468 COSTS_N_INSNS (3), /* mulsi_const9 */
469 COSTS_N_INSNS (7), /* muldi */
470 COSTS_N_INSNS (21), /* divsi */
471 COSTS_N_INSNS (37), /* divdi */
472 COSTS_N_INSNS (3), /* fp */
473 COSTS_N_INSNS (3), /* dmul */
474 COSTS_N_INSNS (18), /* sdiv */
475 COSTS_N_INSNS (32), /* ddiv */
478 /* Instruction costs on PPC630 processors. */
480 struct processor_costs ppc630_cost = {
481 COSTS_N_INSNS (5), /* mulsi */
482 COSTS_N_INSNS (4), /* mulsi_const */
483 COSTS_N_INSNS (3), /* mulsi_const9 */
484 COSTS_N_INSNS (7), /* muldi */
485 COSTS_N_INSNS (21), /* divsi */
486 COSTS_N_INSNS (37), /* divdi */
487 COSTS_N_INSNS (3), /* fp */
488 COSTS_N_INSNS (3), /* dmul */
489 COSTS_N_INSNS (17), /* sdiv */
490 COSTS_N_INSNS (21), /* ddiv */
493 /* Instruction costs on PPC750 and PPC7400 processors. */
495 struct processor_costs ppc750_cost = {
496 COSTS_N_INSNS (5), /* mulsi */
497 COSTS_N_INSNS (3), /* mulsi_const */
498 COSTS_N_INSNS (2), /* mulsi_const9 */
499 COSTS_N_INSNS (5), /* muldi */
500 COSTS_N_INSNS (17), /* divsi */
501 COSTS_N_INSNS (17), /* divdi */
502 COSTS_N_INSNS (3), /* fp */
503 COSTS_N_INSNS (3), /* dmul */
504 COSTS_N_INSNS (17), /* sdiv */
505 COSTS_N_INSNS (31), /* ddiv */
508 /* Instruction costs on PPC7450 processors. */
510 struct processor_costs ppc7450_cost = {
511 COSTS_N_INSNS (4), /* mulsi */
512 COSTS_N_INSNS (3), /* mulsi_const */
513 COSTS_N_INSNS (3), /* mulsi_const9 */
514 COSTS_N_INSNS (4), /* muldi */
515 COSTS_N_INSNS (23), /* divsi */
516 COSTS_N_INSNS (23), /* divdi */
517 COSTS_N_INSNS (5), /* fp */
518 COSTS_N_INSNS (5), /* dmul */
519 COSTS_N_INSNS (21), /* sdiv */
520 COSTS_N_INSNS (35), /* ddiv */
523 /* Instruction costs on PPC8540 processors. */
525 struct processor_costs ppc8540_cost = {
526 COSTS_N_INSNS (4), /* mulsi */
527 COSTS_N_INSNS (4), /* mulsi_const */
528 COSTS_N_INSNS (4), /* mulsi_const9 */
529 COSTS_N_INSNS (4), /* muldi */
530 COSTS_N_INSNS (19), /* divsi */
531 COSTS_N_INSNS (19), /* divdi */
532 COSTS_N_INSNS (4), /* fp */
533 COSTS_N_INSNS (4), /* dmul */
534 COSTS_N_INSNS (29), /* sdiv */
535 COSTS_N_INSNS (29), /* ddiv */
538 /* Instruction costs on POWER4 and POWER5 processors. */
540 struct processor_costs power4_cost = {
541 COSTS_N_INSNS (3), /* mulsi */
542 COSTS_N_INSNS (2), /* mulsi_const */
543 COSTS_N_INSNS (2), /* mulsi_const9 */
544 COSTS_N_INSNS (4), /* muldi */
545 COSTS_N_INSNS (18), /* divsi */
546 COSTS_N_INSNS (34), /* divdi */
547 COSTS_N_INSNS (3), /* fp */
548 COSTS_N_INSNS (3), /* dmul */
549 COSTS_N_INSNS (17), /* sdiv */
550 COSTS_N_INSNS (17), /* ddiv */
554 static bool rs6000_function_ok_for_sibcall (tree, tree);
555 static const char *rs6000_invalid_within_doloop (rtx);
556 static rtx rs6000_generate_compare (enum rtx_code);
557 static void rs6000_maybe_dead (rtx);
558 static void rs6000_emit_stack_tie (void);
559 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
560 static rtx spe_synthesize_frame_save (rtx);
561 static bool spe_func_has_64bit_regs_p (void);
562 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
564 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
565 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
566 static unsigned rs6000_hash_constant (rtx);
567 static unsigned toc_hash_function (const void *);
568 static int toc_hash_eq (const void *, const void *);
569 static int constant_pool_expr_1 (rtx, int *, int *);
570 static bool constant_pool_expr_p (rtx);
571 static bool legitimate_small_data_p (enum machine_mode, rtx);
572 static bool legitimate_indexed_address_p (rtx, int);
573 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
574 static struct machine_function * rs6000_init_machine_status (void);
575 static bool rs6000_assemble_integer (rtx, unsigned int, int);
576 static bool no_global_regs_above (int);
577 #ifdef HAVE_GAS_HIDDEN
578 static void rs6000_assemble_visibility (tree, int);
580 static int rs6000_ra_ever_killed (void);
581 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
582 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
583 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
584 static const char *rs6000_mangle_fundamental_type (tree);
585 extern const struct attribute_spec rs6000_attribute_table[];
586 static void rs6000_set_default_type_attributes (tree);
587 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
588 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
589 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
591 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
592 static bool rs6000_return_in_memory (tree, tree);
593 static void rs6000_file_start (void);
595 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
596 static void rs6000_elf_asm_out_constructor (rtx, int);
597 static void rs6000_elf_asm_out_destructor (rtx, int);
598 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
599 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
600 static void rs6000_elf_unique_section (tree, int);
601 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
602 unsigned HOST_WIDE_INT);
603 static void rs6000_elf_encode_section_info (tree, rtx, int)
605 static bool rs6000_elf_in_small_data_p (tree);
608 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
609 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
610 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
611 static void rs6000_xcoff_unique_section (tree, int);
612 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
613 unsigned HOST_WIDE_INT);
614 static const char * rs6000_xcoff_strip_name_encoding (const char *);
615 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
616 static void rs6000_xcoff_file_start (void);
617 static void rs6000_xcoff_file_end (void);
619 static int rs6000_variable_issue (FILE *, int, rtx, int);
620 static bool rs6000_rtx_costs (rtx, int, int, int *);
621 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
622 static bool is_microcoded_insn (rtx);
623 static int is_dispatch_slot_restricted (rtx);
624 static bool is_cracked_insn (rtx);
625 static bool is_branch_slot_insn (rtx);
626 static int rs6000_adjust_priority (rtx, int);
627 static int rs6000_issue_rate (void);
628 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
629 static rtx get_next_active_insn (rtx, rtx);
630 static bool insn_terminates_group_p (rtx , enum group_termination);
631 static bool is_costly_group (rtx *, rtx);
632 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
633 static int redefine_groups (FILE *, int, rtx, rtx);
634 static int pad_groups (FILE *, int, rtx, rtx);
635 static void rs6000_sched_finish (FILE *, int);
636 static int rs6000_use_sched_lookahead (void);
637 static tree rs6000_builtin_mask_for_load (void);
639 static void def_builtin (int, const char *, tree, int);
640 static void rs6000_init_builtins (void);
641 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
642 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
643 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
644 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
645 static void altivec_init_builtins (void);
646 static void rs6000_common_init_builtins (void);
647 static void rs6000_init_libfuncs (void);
649 static void enable_mask_for_builtins (struct builtin_description *, int,
650 enum rs6000_builtins,
651 enum rs6000_builtins);
652 static tree build_opaque_vector_type (tree, int);
653 static void spe_init_builtins (void);
654 static rtx spe_expand_builtin (tree, rtx, bool *);
655 static rtx spe_expand_stv_builtin (enum insn_code, tree);
656 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
657 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
658 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
659 static rs6000_stack_t *rs6000_stack_info (void);
660 static void debug_stack_info (rs6000_stack_t *);
662 static rtx altivec_expand_builtin (tree, rtx, bool *);
663 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
664 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
665 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
666 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
667 static rtx altivec_expand_predicate_builtin (enum insn_code,
668 const char *, tree, rtx);
669 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
670 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
671 static bool rs6000_handle_option (size_t, const char *, int);
672 static void rs6000_parse_tls_size_option (void);
673 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
674 static int first_altivec_reg_to_save (void);
675 static unsigned int compute_vrsave_mask (void);
676 static void compute_save_world_info (rs6000_stack_t *info_ptr);
677 static void is_altivec_return_reg (rtx, void *);
678 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
679 int easy_vector_constant (rtx, enum machine_mode);
680 static bool rs6000_is_opaque_type (tree);
681 static rtx rs6000_dwarf_register_span (rtx);
682 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
683 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
684 static rtx rs6000_tls_get_addr (void);
685 static rtx rs6000_got_sym (void);
686 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
687 static const char *rs6000_get_some_local_dynamic_name (void);
688 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
689 static rtx rs6000_complex_function_value (enum machine_mode);
690 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
691 enum machine_mode, tree);
692 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
694 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
695 tree, HOST_WIDE_INT);
696 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
699 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
702 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
703 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
704 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
705 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
706 enum machine_mode, tree,
708 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
710 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
712 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
714 static void macho_branch_islands (void);
715 static void add_compiler_branch_island (tree, tree, int);
716 static int no_previous_def (tree function_name);
717 static tree get_prev_label (tree function_name);
718 static void rs6000_darwin_file_start (void);
721 static tree rs6000_build_builtin_va_list (void);
722 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
723 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
724 static bool rs6000_vector_mode_supported_p (enum machine_mode);
725 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
727 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
729 static int get_vsel_insn (enum machine_mode);
730 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
731 static tree rs6000_stack_protect_fail (void);
733 const int INSN_NOT_AVAILABLE = -1;
734 static enum machine_mode rs6000_eh_return_filter_mode (void);
736 /* Hash table stuff for keeping track of TOC entries. */
738 struct toc_hash_struct GTY(())
740 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
741 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
743 enum machine_mode key_mode;
747 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
749 /* Default register names. */
750 char rs6000_reg_names[][8] =
752 "0", "1", "2", "3", "4", "5", "6", "7",
753 "8", "9", "10", "11", "12", "13", "14", "15",
754 "16", "17", "18", "19", "20", "21", "22", "23",
755 "24", "25", "26", "27", "28", "29", "30", "31",
756 "0", "1", "2", "3", "4", "5", "6", "7",
757 "8", "9", "10", "11", "12", "13", "14", "15",
758 "16", "17", "18", "19", "20", "21", "22", "23",
759 "24", "25", "26", "27", "28", "29", "30", "31",
760 "mq", "lr", "ctr","ap",
761 "0", "1", "2", "3", "4", "5", "6", "7",
763 /* AltiVec registers. */
764 "0", "1", "2", "3", "4", "5", "6", "7",
765 "8", "9", "10", "11", "12", "13", "14", "15",
766 "16", "17", "18", "19", "20", "21", "22", "23",
767 "24", "25", "26", "27", "28", "29", "30", "31",
770 "spe_acc", "spefscr",
771 /* Soft frame pointer. */
775 #ifdef TARGET_REGNAMES
776 static const char alt_reg_names[][8] =
778 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
779 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
780 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
781 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
782 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
783 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
784 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
785 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
786 "mq", "lr", "ctr", "ap",
787 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
789 /* AltiVec registers. */
790 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
791 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
792 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
793 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
796 "spe_acc", "spefscr",
797 /* Soft frame pointer. */
802 #ifndef MASK_STRICT_ALIGN
803 #define MASK_STRICT_ALIGN 0
805 #ifndef TARGET_PROFILE_KERNEL
806 #define TARGET_PROFILE_KERNEL 0
809 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
810 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
812 /* Initialize the GCC target structure. */
813 #undef TARGET_ATTRIBUTE_TABLE
814 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
815 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
816 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
818 #undef TARGET_ASM_ALIGNED_DI_OP
819 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
821 /* Default unaligned ops are only provided for ELF. Find the ops needed
822 for non-ELF systems. */
823 #ifndef OBJECT_FORMAT_ELF
825 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
827 #undef TARGET_ASM_UNALIGNED_HI_OP
828 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
829 #undef TARGET_ASM_UNALIGNED_SI_OP
830 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
831 #undef TARGET_ASM_UNALIGNED_DI_OP
832 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
835 #undef TARGET_ASM_UNALIGNED_HI_OP
836 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
837 #undef TARGET_ASM_UNALIGNED_SI_OP
838 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
839 #undef TARGET_ASM_UNALIGNED_DI_OP
840 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
841 #undef TARGET_ASM_ALIGNED_DI_OP
842 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
846 /* This hook deals with fixups for relocatable code and DI-mode objects
848 #undef TARGET_ASM_INTEGER
849 #define TARGET_ASM_INTEGER rs6000_assemble_integer
851 #ifdef HAVE_GAS_HIDDEN
852 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
853 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
856 #undef TARGET_HAVE_TLS
857 #define TARGET_HAVE_TLS HAVE_AS_TLS
859 #undef TARGET_CANNOT_FORCE_CONST_MEM
860 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
862 #undef TARGET_ASM_FUNCTION_PROLOGUE
863 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
864 #undef TARGET_ASM_FUNCTION_EPILOGUE
865 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
867 #undef TARGET_SCHED_VARIABLE_ISSUE
868 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
870 #undef TARGET_SCHED_ISSUE_RATE
871 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
872 #undef TARGET_SCHED_ADJUST_COST
873 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
874 #undef TARGET_SCHED_ADJUST_PRIORITY
875 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
876 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
877 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
878 #undef TARGET_SCHED_FINISH
879 #define TARGET_SCHED_FINISH rs6000_sched_finish
881 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
882 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
884 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
885 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
887 #undef TARGET_INIT_BUILTINS
888 #define TARGET_INIT_BUILTINS rs6000_init_builtins
890 #undef TARGET_EXPAND_BUILTIN
891 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
893 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
894 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
896 #undef TARGET_INIT_LIBFUNCS
897 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
900 #undef TARGET_BINDS_LOCAL_P
901 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
904 #undef TARGET_ASM_OUTPUT_MI_THUNK
905 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
907 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
908 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
910 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
911 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
913 #undef TARGET_INVALID_WITHIN_DOLOOP
914 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
916 #undef TARGET_RTX_COSTS
917 #define TARGET_RTX_COSTS rs6000_rtx_costs
918 #undef TARGET_ADDRESS_COST
919 #define TARGET_ADDRESS_COST hook_int_rtx_0
921 #undef TARGET_VECTOR_OPAQUE_P
922 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
924 #undef TARGET_DWARF_REGISTER_SPAN
925 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
927 /* On rs6000, function arguments are promoted, as are function return
929 #undef TARGET_PROMOTE_FUNCTION_ARGS
930 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
931 #undef TARGET_PROMOTE_FUNCTION_RETURN
932 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
934 #undef TARGET_RETURN_IN_MEMORY
935 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
937 #undef TARGET_SETUP_INCOMING_VARARGS
938 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
940 /* Always strict argument naming on rs6000. */
941 #undef TARGET_STRICT_ARGUMENT_NAMING
942 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
943 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
944 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
945 #undef TARGET_SPLIT_COMPLEX_ARG
946 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
947 #undef TARGET_MUST_PASS_IN_STACK
948 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
949 #undef TARGET_PASS_BY_REFERENCE
950 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
951 #undef TARGET_ARG_PARTIAL_BYTES
952 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
954 #undef TARGET_BUILD_BUILTIN_VA_LIST
955 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
957 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
958 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
960 #undef TARGET_EH_RETURN_FILTER_MODE
961 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
963 #undef TARGET_VECTOR_MODE_SUPPORTED_P
964 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
966 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
967 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
969 #undef TARGET_HANDLE_OPTION
970 #define TARGET_HANDLE_OPTION rs6000_handle_option
972 #undef TARGET_DEFAULT_TARGET_FLAGS
973 #define TARGET_DEFAULT_TARGET_FLAGS \
974 (TARGET_DEFAULT | MASK_SCHED_PROLOG)
976 #undef TARGET_STACK_PROTECT_FAIL
977 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
979 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
980 The PowerPC architecture requires only weak consistency among
981 processors--that is, memory accesses between processors need not be
982 sequentially consistent and memory accesses among processors can occur
983 in any order. The ability to order memory accesses weakly provides
984 opportunities for more efficient use of the system bus. Unless a
985 dependency exists, the 604e allows read operations to precede store
987 #undef TARGET_RELAXED_ORDERING
988 #define TARGET_RELAXED_ORDERING true
991 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
992 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
995 struct gcc_target targetm = TARGET_INITIALIZER;
998 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1001 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1003 /* The GPRs can hold any mode, but values bigger than one register
1004 cannot go past R31. */
1005 if (INT_REGNO_P (regno))
1006 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1008 /* The float registers can only hold floating modes and DImode. */
1009 if (FP_REGNO_P (regno))
1011 (GET_MODE_CLASS (mode) == MODE_FLOAT
1012 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1013 || (GET_MODE_CLASS (mode) == MODE_INT
1014 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1016 /* The CR register can only hold CC modes. */
1017 if (CR_REGNO_P (regno))
1018 return GET_MODE_CLASS (mode) == MODE_CC;
1020 if (XER_REGNO_P (regno))
1021 return mode == PSImode;
1023 /* AltiVec only in AldyVec registers. */
1024 if (ALTIVEC_REGNO_P (regno))
1025 return ALTIVEC_VECTOR_MODE (mode);
1027 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1028 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1031 /* We cannot put TImode anywhere except general register and it must be
1032 able to fit within the register set. */
1034 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1037 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1039 rs6000_init_hard_regno_mode_ok (void)
1043 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1044 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1045 if (rs6000_hard_regno_mode_ok (r, m))
1046 rs6000_hard_regno_mode_ok_p[m][r] = true;
1049 /* If not otherwise specified by a target, make 'long double' equivalent to
1052 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1053 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1056 /* Override command line options. Mostly we process the processor
1057 type and sometimes adjust other TARGET_ options. */
1060 rs6000_override_options (const char *default_cpu)
1063 struct rs6000_cpu_select *ptr;
1066 /* Simplifications for entries below. */
1069 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1070 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1073 /* This table occasionally claims that a processor does not support
1074 a particular feature even though it does, but the feature is slower
1075 than the alternative. Thus, it shouldn't be relied on as a
1076 complete description of the processor's support.
1078 Please keep this list in order, and don't forget to update the
1079 documentation in invoke.texi when adding a new processor or
1083 const char *const name; /* Canonical processor name. */
1084 const enum processor_type processor; /* Processor type enum value. */
1085 const int target_enable; /* Target flags to enable. */
1086 } const processor_target_table[]
1087 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1088 {"403", PROCESSOR_PPC403,
1089 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1090 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1091 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1092 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1093 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1094 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1095 {"601", PROCESSOR_PPC601,
1096 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1097 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1098 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1099 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1100 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1101 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1102 {"620", PROCESSOR_PPC620,
1103 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1104 {"630", PROCESSOR_PPC630,
1105 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1106 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1107 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1108 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1109 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1110 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1111 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1112 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1113 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1114 /* 8548 has a dummy entry for now. */
1115 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1116 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1117 {"970", PROCESSOR_POWER4,
1118 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1119 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1120 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1121 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1122 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1123 {"G5", PROCESSOR_POWER4,
1124 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1125 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1126 {"power2", PROCESSOR_POWER,
1127 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1128 {"power3", PROCESSOR_PPC630,
1129 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1130 {"power4", PROCESSOR_POWER4,
1131 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1132 {"power5", PROCESSOR_POWER5,
1133 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1134 | MASK_MFCRF | MASK_POPCNTB},
1135 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1136 {"powerpc64", PROCESSOR_POWERPC64,
1137 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1138 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1139 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1140 {"rios2", PROCESSOR_RIOS2,
1141 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1142 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1143 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1144 {"rs64", PROCESSOR_RS64A,
1145 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1148 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1150 /* Some OSs don't support saving the high part of 64-bit registers on
1151 context switch. Other OSs don't support saving Altivec registers.
1152 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1153 settings; if the user wants either, the user must explicitly specify
1154 them and we won't interfere with the user's specification. */
1157 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1158 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1159 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1163 rs6000_init_hard_regno_mode_ok ();
1165 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1166 #ifdef OS_MISSING_POWERPC64
1167 if (OS_MISSING_POWERPC64)
1168 set_masks &= ~MASK_POWERPC64;
1170 #ifdef OS_MISSING_ALTIVEC
1171 if (OS_MISSING_ALTIVEC)
1172 set_masks &= ~MASK_ALTIVEC;
1175 /* Don't override by the processor default if given explicitly. */
1176 set_masks &= ~target_flags_explicit;
1178 /* Identify the processor type. */
1179 rs6000_select[0].string = default_cpu;
1180 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1182 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1184 ptr = &rs6000_select[i];
1185 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1187 for (j = 0; j < ptt_size; j++)
1188 if (! strcmp (ptr->string, processor_target_table[j].name))
1190 if (ptr->set_tune_p)
1191 rs6000_cpu = processor_target_table[j].processor;
1193 if (ptr->set_arch_p)
1195 target_flags &= ~set_masks;
1196 target_flags |= (processor_target_table[j].target_enable
1203 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1210 /* If we are optimizing big endian systems for space, use the load/store
1211 multiple and string instructions. */
1212 if (BYTES_BIG_ENDIAN && optimize_size)
1213 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1215 /* Don't allow -mmultiple or -mstring on little endian systems
1216 unless the cpu is a 750, because the hardware doesn't support the
1217 instructions used in little endian mode, and causes an alignment
1218 trap. The 750 does not cause an alignment trap (except when the
1219 target is unaligned). */
1221 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1223 if (TARGET_MULTIPLE)
1225 target_flags &= ~MASK_MULTIPLE;
1226 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1227 warning (0, "-mmultiple is not supported on little endian systems");
1232 target_flags &= ~MASK_STRING;
1233 if ((target_flags_explicit & MASK_STRING) != 0)
1234 warning (0, "-mstring is not supported on little endian systems");
1238 /* Set debug flags */
1239 if (rs6000_debug_name)
1241 if (! strcmp (rs6000_debug_name, "all"))
1242 rs6000_debug_stack = rs6000_debug_arg = 1;
1243 else if (! strcmp (rs6000_debug_name, "stack"))
1244 rs6000_debug_stack = 1;
1245 else if (! strcmp (rs6000_debug_name, "arg"))
1246 rs6000_debug_arg = 1;
1248 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1251 if (rs6000_traceback_name)
1253 if (! strncmp (rs6000_traceback_name, "full", 4))
1254 rs6000_traceback = traceback_full;
1255 else if (! strncmp (rs6000_traceback_name, "part", 4))
1256 rs6000_traceback = traceback_part;
1257 else if (! strncmp (rs6000_traceback_name, "no", 2))
1258 rs6000_traceback = traceback_none;
1260 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1261 rs6000_traceback_name);
1264 if (!rs6000_explicit_options.long_double)
1265 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1267 /* Set Altivec ABI as default for powerpc64 linux. */
1268 if (TARGET_ELF && TARGET_64BIT)
1270 rs6000_altivec_abi = 1;
1271 TARGET_ALTIVEC_VRSAVE = 1;
1274 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1275 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1277 rs6000_darwin64_abi = 1;
1279 darwin_one_byte_bool = 1;
1281 /* Default to natural alignment, for better performance. */
1282 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1285 /* Handle -mtls-size option. */
1286 rs6000_parse_tls_size_option ();
1288 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1289 SUBTARGET_OVERRIDE_OPTIONS;
1291 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1292 SUBSUBTARGET_OVERRIDE_OPTIONS;
1294 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1295 SUB3TARGET_OVERRIDE_OPTIONS;
1301 error ("AltiVec and E500 instructions cannot coexist");
1303 /* The e500 does not have string instructions, and we set
1304 MASK_STRING above when optimizing for size. */
1305 if ((target_flags & MASK_STRING) != 0)
1306 target_flags = target_flags & ~MASK_STRING;
1308 else if (rs6000_select[1].string != NULL)
1310 /* For the powerpc-eabispe configuration, we set all these by
1311 default, so let's unset them if we manually set another
1312 CPU that is not the E500. */
1313 if (!rs6000_explicit_options.abi)
1315 if (!rs6000_explicit_options.spe)
1317 if (!rs6000_explicit_options.float_gprs)
1318 rs6000_float_gprs = 0;
1319 if (!rs6000_explicit_options.isel)
1321 if (!rs6000_explicit_options.long_double)
1322 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1325 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1326 && rs6000_cpu != PROCESSOR_POWER5);
1327 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1328 || rs6000_cpu == PROCESSOR_POWER5);
1330 rs6000_sched_restricted_insns_priority
1331 = (rs6000_sched_groups ? 1 : 0);
1333 /* Handle -msched-costly-dep option. */
1334 rs6000_sched_costly_dep
1335 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1337 if (rs6000_sched_costly_dep_str)
1339 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1340 rs6000_sched_costly_dep = no_dep_costly;
1341 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1342 rs6000_sched_costly_dep = all_deps_costly;
1343 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1344 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1345 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1346 rs6000_sched_costly_dep = store_to_load_dep_costly;
1348 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1351 /* Handle -minsert-sched-nops option. */
1352 rs6000_sched_insert_nops
1353 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1355 if (rs6000_sched_insert_nops_str)
1357 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1358 rs6000_sched_insert_nops = sched_finish_none;
1359 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1360 rs6000_sched_insert_nops = sched_finish_pad_groups;
1361 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1362 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1364 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1367 #ifdef TARGET_REGNAMES
1368 /* If the user desires alternate register names, copy in the
1369 alternate names now. */
1370 if (TARGET_REGNAMES)
1371 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1374 /* Set aix_struct_return last, after the ABI is determined.
1375 If -maix-struct-return or -msvr4-struct-return was explicitly
1376 used, don't override with the ABI default. */
1377 if (!rs6000_explicit_options.aix_struct_ret)
1378 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1380 if (TARGET_LONG_DOUBLE_128
1381 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1382 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1384 /* Allocate an alias set for register saves & restores from stack. */
1385 rs6000_sr_alias_set = new_alias_set ();
1388 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1390 /* We can only guarantee the availability of DI pseudo-ops when
1391 assembling for 64-bit targets. */
1394 targetm.asm_out.aligned_op.di = NULL;
1395 targetm.asm_out.unaligned_op.di = NULL;
1398 /* Set branch target alignment, if not optimizing for size. */
1401 if (rs6000_sched_groups)
1403 if (align_functions <= 0)
1404 align_functions = 16;
1405 if (align_jumps <= 0)
1407 if (align_loops <= 0)
1410 if (align_jumps_max_skip <= 0)
1411 align_jumps_max_skip = 15;
1412 if (align_loops_max_skip <= 0)
1413 align_loops_max_skip = 15;
1416 /* Arrange to save and restore machine status around nested functions. */
1417 init_machine_status = rs6000_init_machine_status;
1419 /* We should always be splitting complex arguments, but we can't break
1420 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1421 if (DEFAULT_ABI != ABI_AIX)
1422 targetm.calls.split_complex_arg = NULL;
1424 /* Initialize rs6000_cost with the appropriate target costs. */
1426 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1430 case PROCESSOR_RIOS1:
1431 rs6000_cost = &rios1_cost;
1434 case PROCESSOR_RIOS2:
1435 rs6000_cost = &rios2_cost;
1438 case PROCESSOR_RS64A:
1439 rs6000_cost = &rs64a_cost;
1442 case PROCESSOR_MPCCORE:
1443 rs6000_cost = &mpccore_cost;
1446 case PROCESSOR_PPC403:
1447 rs6000_cost = &ppc403_cost;
1450 case PROCESSOR_PPC405:
1451 rs6000_cost = &ppc405_cost;
1454 case PROCESSOR_PPC440:
1455 rs6000_cost = &ppc440_cost;
1458 case PROCESSOR_PPC601:
1459 rs6000_cost = &ppc601_cost;
1462 case PROCESSOR_PPC603:
1463 rs6000_cost = &ppc603_cost;
1466 case PROCESSOR_PPC604:
1467 rs6000_cost = &ppc604_cost;
1470 case PROCESSOR_PPC604e:
1471 rs6000_cost = &ppc604e_cost;
1474 case PROCESSOR_PPC620:
1475 rs6000_cost = &ppc620_cost;
1478 case PROCESSOR_PPC630:
1479 rs6000_cost = &ppc630_cost;
1482 case PROCESSOR_PPC750:
1483 case PROCESSOR_PPC7400:
1484 rs6000_cost = &ppc750_cost;
1487 case PROCESSOR_PPC7450:
1488 rs6000_cost = &ppc7450_cost;
1491 case PROCESSOR_PPC8540:
1492 rs6000_cost = &ppc8540_cost;
1495 case PROCESSOR_POWER4:
1496 case PROCESSOR_POWER5:
1497 rs6000_cost = &power4_cost;
1505 /* Implement targetm.vectorize.builtin_mask_for_load. */
1507 rs6000_builtin_mask_for_load (void)
1510 return altivec_builtin_mask_for_load;
1515 /* Handle generic options of the form -mfoo=yes/no.
1516 NAME is the option name.
1517 VALUE is the option value.
1518 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1519 whether the option value is 'yes' or 'no' respectively. */
1521 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1525 else if (!strcmp (value, "yes"))
1527 else if (!strcmp (value, "no"))
1530 error ("unknown -m%s= option specified: '%s'", name, value);
1533 /* Validate and record the size specified with the -mtls-size option. */
1536 rs6000_parse_tls_size_option (void)
1538 if (rs6000_tls_size_string == 0)
1540 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1541 rs6000_tls_size = 16;
1542 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1543 rs6000_tls_size = 32;
1544 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1545 rs6000_tls_size = 64;
1547 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1551 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1553 if (DEFAULT_ABI == ABI_DARWIN)
1554 /* The Darwin libraries never set errno, so we might as well
1555 avoid calling them when that's the only reason we would. */
1556 flag_errno_math = 0;
1559 /* Implement TARGET_HANDLE_OPTION. */
1562 rs6000_handle_option (size_t code, const char *arg, int value)
1567 target_flags &= ~(MASK_POWER | MASK_POWER2
1568 | MASK_MULTIPLE | MASK_STRING);
1569 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1570 | MASK_MULTIPLE | MASK_STRING);
1572 case OPT_mno_powerpc:
1573 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1574 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1575 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1576 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1579 target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1580 | MASK_NO_SUM_IN_TOC);
1581 target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1582 | MASK_NO_SUM_IN_TOC);
1583 #ifdef TARGET_USES_SYSV4_OPT
1584 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1585 just the same as -mminimal-toc. */
1586 target_flags |= MASK_MINIMAL_TOC;
1587 target_flags_explicit |= MASK_MINIMAL_TOC;
1591 #ifdef TARGET_USES_SYSV4_OPT
1593 /* Make -mtoc behave like -mminimal-toc. */
1594 target_flags |= MASK_MINIMAL_TOC;
1595 target_flags_explicit |= MASK_MINIMAL_TOC;
1599 #ifdef TARGET_USES_AIX64_OPT
1604 target_flags |= MASK_POWERPC64 | MASK_POWERPC | MASK_PPC_GFXOPT;
1605 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC
1609 #ifdef TARGET_USES_AIX64_OPT
1614 target_flags &= ~MASK_POWERPC64;
1615 target_flags_explicit |= MASK_POWERPC64;
1618 case OPT_minsert_sched_nops_:
1619 rs6000_sched_insert_nops_str = arg;
1622 case OPT_mminimal_toc:
1625 target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1626 target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1633 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1634 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1641 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1642 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1646 case OPT_mpowerpc_gpopt:
1647 case OPT_mpowerpc_gfxopt:
1650 target_flags |= MASK_POWERPC;
1651 target_flags_explicit |= MASK_POWERPC;
1655 case OPT_maix_struct_return:
1656 case OPT_msvr4_struct_return:
1657 rs6000_explicit_options.aix_struct_ret = true;
1661 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1665 rs6000_explicit_options.isel = true;
1666 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1670 rs6000_explicit_options.spe = true;
1671 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1672 /* No SPE means 64-bit long doubles, even if an E500. */
1674 rs6000_long_double_type_size = 64;
1678 rs6000_debug_name = arg;
1681 #ifdef TARGET_USES_SYSV4_OPT
1683 rs6000_abi_name = arg;
1687 rs6000_sdata_name = arg;
1690 case OPT_mtls_size_:
1691 rs6000_tls_size_string = arg;
1694 case OPT_mrelocatable:
1697 target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1698 target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1702 case OPT_mrelocatable_lib:
1705 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1706 | MASK_NO_FP_IN_TOC;
1707 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1708 | MASK_NO_FP_IN_TOC;
1712 target_flags &= ~MASK_RELOCATABLE;
1713 target_flags_explicit |= MASK_RELOCATABLE;
1719 rs6000_explicit_options.abi = true;
1720 if (!strcmp (arg, "altivec"))
1722 rs6000_altivec_abi = 1;
1725 else if (! strcmp (arg, "no-altivec"))
1726 rs6000_altivec_abi = 0;
1727 else if (! strcmp (arg, "spe"))
1730 rs6000_altivec_abi = 0;
1731 if (!TARGET_SPE_ABI)
1732 error ("not configured for ABI: '%s'", arg);
1734 else if (! strcmp (arg, "no-spe"))
1737 /* These are here for testing during development only, do not
1738 document in the manual please. */
1739 else if (! strcmp (arg, "d64"))
1741 rs6000_darwin64_abi = 1;
1742 warning (0, "Using darwin64 ABI");
1744 else if (! strcmp (arg, "d32"))
1746 rs6000_darwin64_abi = 0;
1747 warning (0, "Using old darwin ABI");
1752 error ("unknown ABI specified: '%s'", arg);
1758 rs6000_select[1].string = arg;
1762 rs6000_select[2].string = arg;
1765 case OPT_mtraceback_:
1766 rs6000_traceback_name = arg;
1769 case OPT_mfloat_gprs_:
1770 rs6000_explicit_options.float_gprs = true;
1771 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1772 rs6000_float_gprs = 1;
1773 else if (! strcmp (arg, "double"))
1774 rs6000_float_gprs = 2;
1775 else if (! strcmp (arg, "no"))
1776 rs6000_float_gprs = 0;
1779 error ("invalid option for -mfloat-gprs: '%s'", arg);
1784 case OPT_mlong_double_:
1785 rs6000_explicit_options.long_double = true;
1786 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1787 if (value != 64 && value != 128)
1789 error ("Unknown switch -mlong-double-%s", arg);
1790 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1794 rs6000_long_double_type_size = value;
1797 case OPT_msched_costly_dep_:
1798 rs6000_sched_costly_dep_str = arg;
1802 rs6000_explicit_options.alignment = true;
1803 if (! strcmp (arg, "power"))
1805 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1806 some C library functions, so warn about it. The flag may be
1807 useful for performance studies from time to time though, so
1808 don't disable it entirely. */
1809 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1810 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1811 " it is incompatible with the installed C and C++ libraries");
1812 rs6000_alignment_flags = MASK_ALIGN_POWER;
1814 else if (! strcmp (arg, "natural"))
1815 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1818 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1826 /* Do anything needed at the start of the asm file. */
1829 rs6000_file_start (void)
1833 const char *start = buffer;
1834 struct rs6000_cpu_select *ptr;
1835 const char *default_cpu = TARGET_CPU_DEFAULT;
1836 FILE *file = asm_out_file;
1838 default_file_start ();
1840 #ifdef TARGET_BI_ARCH
1841 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1845 if (flag_verbose_asm)
1847 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1848 rs6000_select[0].string = default_cpu;
1850 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1852 ptr = &rs6000_select[i];
1853 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1855 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1860 if (PPC405_ERRATUM77)
1862 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1866 #ifdef USING_ELFOS_H
1867 switch (rs6000_sdata)
1869 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1870 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1871 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1872 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1875 if (rs6000_sdata && g_switch_value)
1877 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1887 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1895 /* Return nonzero if this function is known to have a null epilogue. */
1898 direct_return (void)
1900 if (reload_completed)
1902 rs6000_stack_t *info = rs6000_stack_info ();
1904 if (info->first_gp_reg_save == 32
1905 && info->first_fp_reg_save == 64
1906 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1907 && ! info->lr_save_p
1908 && ! info->cr_save_p
1909 && info->vrsave_mask == 0
1917 /* Return the number of instructions it takes to form a constant in an
1918 integer register. */
1921 num_insns_constant_wide (HOST_WIDE_INT value)
1923 /* signed constant loadable with {cal|addi} */
1924 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1927 /* constant loadable with {cau|addis} */
1928 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1931 #if HOST_BITS_PER_WIDE_INT == 64
1932 else if (TARGET_POWERPC64)
1934 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1935 HOST_WIDE_INT high = value >> 31;
1937 if (high == 0 || high == -1)
1943 return num_insns_constant_wide (high) + 1;
1945 return (num_insns_constant_wide (high)
1946 + num_insns_constant_wide (low) + 1);
1955 num_insns_constant (rtx op, enum machine_mode mode)
1957 HOST_WIDE_INT low, high;
1959 switch (GET_CODE (op))
1962 #if HOST_BITS_PER_WIDE_INT == 64
1963 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1964 && mask_operand (op, mode))
1968 return num_insns_constant_wide (INTVAL (op));
1976 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1977 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1978 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1981 if (mode == VOIDmode || mode == DImode)
1983 high = CONST_DOUBLE_HIGH (op);
1984 low = CONST_DOUBLE_LOW (op);
1991 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1992 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1993 high = l[WORDS_BIG_ENDIAN == 0];
1994 low = l[WORDS_BIG_ENDIAN != 0];
1998 return (num_insns_constant_wide (low)
1999 + num_insns_constant_wide (high));
2002 if ((high == 0 && low >= 0)
2003 || (high == -1 && low < 0))
2004 return num_insns_constant_wide (low);
2006 else if (mask_operand (op, mode))
2010 return num_insns_constant_wide (high) + 1;
2013 return (num_insns_constant_wide (high)
2014 + num_insns_constant_wide (low) + 1);
2022 /* Returns the constant for the splat instruction, if exists. */
2025 easy_vector_splat_const (int cst, enum machine_mode mode)
2030 if (EASY_VECTOR_15 (cst)
2031 || EASY_VECTOR_15_ADD_SELF (cst))
2033 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
2039 if (EASY_VECTOR_15 (cst)
2040 || EASY_VECTOR_15_ADD_SELF (cst))
2042 if ((cst & 0xff) != ((cst >> 8) & 0xff))
2048 if (EASY_VECTOR_15 (cst)
2049 || EASY_VECTOR_15_ADD_SELF (cst))
2057 /* Return nonzero if all elements of a vector have the same value. */
2060 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2064 units = CONST_VECTOR_NUNITS (op);
2066 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2067 for (i = 1; i < units; ++i)
2068 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2070 if (i == units && easy_vector_splat_const (cst, mode))
2075 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2078 gen_easy_vector_constant_add_self (rtx op)
2082 units = GET_MODE_NUNITS (GET_MODE (op));
2083 v = rtvec_alloc (units);
2085 for (i = 0; i < units; i++)
2087 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2088 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
2092 output_vec_const_move (rtx *operands)
2095 enum machine_mode mode;
2101 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2102 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2103 mode = GET_MODE (dest);
2107 if (zero_constant (vec, mode))
2108 return "vxor %0,%0,%0";
2110 gcc_assert (easy_vector_constant (vec, mode));
2112 operands[1] = GEN_INT (cst);
2116 if (EASY_VECTOR_15 (cst))
2118 operands[1] = GEN_INT (cst);
2119 return "vspltisw %0,%1";
2121 else if (EASY_VECTOR_15_ADD_SELF (cst))
2127 if (EASY_VECTOR_15 (cst))
2129 operands[1] = GEN_INT (cst);
2130 return "vspltish %0,%1";
2132 else if (EASY_VECTOR_15_ADD_SELF (cst))
2138 if (EASY_VECTOR_15 (cst))
2140 operands[1] = GEN_INT (cst);
2141 return "vspltisb %0,%1";
2143 else if (EASY_VECTOR_15_ADD_SELF (cst))
2151 gcc_assert (TARGET_SPE);
2153 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2154 pattern of V1DI, V4HI, and V2SF.
2156 FIXME: We should probably return # and add post reload
2157 splitters for these, but this way is so easy ;-). */
2158 operands[1] = GEN_INT (cst);
2159 operands[2] = GEN_INT (cst2);
2161 return "li %0,%1\n\tevmergelo %0,%0,%0";
2163 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2167 mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2170 if (GET_CODE (op) == CONST_INT)
2172 HOST_WIDE_INT c, lsb;
2177 /* Disallow all zeros. */
2181 /* We can use a single rlwinm insn if no upper bits of C are set
2182 AND there are zero, one or two transitions in the _whole_ of
2184 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2186 /* We don't change the number of transitions by inverting,
2187 so make sure we start with the LS bit zero. */
2191 /* Find the first transition. */
2194 /* Invert to look for a second transition. */
2197 /* Erase first transition. */
2200 /* Find the second transition. */
2203 /* Invert to look for a third transition. */
2206 /* Erase second transition. */
2209 if (one_ok && !(allow_one || c))
2212 /* Find the third transition (if any). */
2215 /* Match if all the bits above are 1's (or c is zero). */
2221 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2222 implement ANDing by the mask IN. */
2224 build_mask64_2_operands (rtx in, rtx *out)
2226 #if HOST_BITS_PER_WIDE_INT >= 64
2227 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2230 gcc_assert (GET_CODE (in) == CONST_INT);
2235 /* Assume c initially something like 0x00fff000000fffff. The idea
2236 is to rotate the word so that the middle ^^^^^^ group of zeros
2237 is at the MS end and can be cleared with an rldicl mask. We then
2238 rotate back and clear off the MS ^^ group of zeros with a
2240 c = ~c; /* c == 0xff000ffffff00000 */
2241 lsb = c & -c; /* lsb == 0x0000000000100000 */
2242 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2243 c = ~c; /* c == 0x00fff000000fffff */
2244 c &= -lsb; /* c == 0x00fff00000000000 */
2245 lsb = c & -c; /* lsb == 0x0000100000000000 */
2246 c = ~c; /* c == 0xff000fffffffffff */
2247 c &= -lsb; /* c == 0xff00000000000000 */
2249 while ((lsb >>= 1) != 0)
2250 shift++; /* shift == 44 on exit from loop */
2251 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2252 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2253 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2257 /* Assume c initially something like 0xff000f0000000000. The idea
2258 is to rotate the word so that the ^^^ middle group of zeros
2259 is at the LS end and can be cleared with an rldicr mask. We then
2260 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2262 lsb = c & -c; /* lsb == 0x0000010000000000 */
2263 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2264 c = ~c; /* c == 0x00fff0ffffffffff */
2265 c &= -lsb; /* c == 0x00fff00000000000 */
2266 lsb = c & -c; /* lsb == 0x0000100000000000 */
2267 c = ~c; /* c == 0xff000fffffffffff */
2268 c &= -lsb; /* c == 0xff00000000000000 */
2270 while ((lsb >>= 1) != 0)
2271 shift++; /* shift == 44 on exit from loop */
2272 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2273 m1 >>= shift; /* m1 == 0x0000000000000fff */
2274 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2277 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2278 masks will be all 1's. We are guaranteed more than one transition. */
2279 out[0] = GEN_INT (64 - shift);
2280 out[1] = GEN_INT (m1);
2281 out[2] = GEN_INT (shift);
2282 out[3] = GEN_INT (m2);
2290 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2293 invalid_e500_subreg (rtx op, enum machine_mode mode)
2295 /* Reject (subreg:SI (reg:DF)). */
2296 if (GET_CODE (op) == SUBREG
2298 && REG_P (SUBREG_REG (op))
2299 && GET_MODE (SUBREG_REG (op)) == DFmode)
2302 /* Reject (subreg:DF (reg:DI)). */
2303 if (GET_CODE (op) == SUBREG
2305 && REG_P (SUBREG_REG (op))
2306 && GET_MODE (SUBREG_REG (op)) == DImode)
2312 /* Darwin, AIX increases natural record alignment to doubleword if the first
2313 field is an FP double while the FP fields remain word aligned. */
2316 rs6000_special_round_type_align (tree type, int computed, int specified)
2318 tree field = TYPE_FIELDS (type);
2320 /* Skip all non field decls */
2321 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2322 field = TREE_CHAIN (field);
2324 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
2325 return MAX (computed, specified);
2327 return MAX (MAX (computed, specified), 64);
2330 /* Return 1 for an operand in small memory on V.4/eabi. */
2333 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2334 enum machine_mode mode ATTRIBUTE_UNUSED)
2339 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2342 if (DEFAULT_ABI != ABI_V4)
2345 if (GET_CODE (op) == SYMBOL_REF)
2348 else if (GET_CODE (op) != CONST
2349 || GET_CODE (XEXP (op, 0)) != PLUS
2350 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2351 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2356 rtx sum = XEXP (op, 0);
2357 HOST_WIDE_INT summand;
2359 /* We have to be careful here, because it is the referenced address
2360 that must be 32k from _SDA_BASE_, not just the symbol. */
2361 summand = INTVAL (XEXP (sum, 1));
2362 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2365 sym_ref = XEXP (sum, 0);
2368 return SYMBOL_REF_SMALL_P (sym_ref);
2374 /* Return true if either operand is a general purpose register. */
2377 gpr_or_gpr_p (rtx op0, rtx op1)
2379 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2380 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2384 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2387 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2389 switch (GET_CODE (op))
2392 if (RS6000_SYMBOL_REF_TLS_P (op))
2394 else if (CONSTANT_POOL_ADDRESS_P (op))
2396 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2404 else if (! strcmp (XSTR (op, 0), toc_label_name))
2413 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2414 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2416 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2425 constant_pool_expr_p (rtx op)
2429 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2433 toc_relative_expr_p (rtx op)
2437 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2441 legitimate_constant_pool_address_p (rtx x)
2444 && GET_CODE (x) == PLUS
2445 && GET_CODE (XEXP (x, 0)) == REG
2446 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2447 && constant_pool_expr_p (XEXP (x, 1)));
2451 legitimate_small_data_p (enum machine_mode mode, rtx x)
2453 return (DEFAULT_ABI == ABI_V4
2454 && !flag_pic && !TARGET_TOC
2455 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2456 && small_data_operand (x, mode));
2459 /* SPE offset addressing is limited to 5-bits worth of double words. */
2460 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2463 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2465 unsigned HOST_WIDE_INT offset, extra;
2467 if (GET_CODE (x) != PLUS)
2469 if (GET_CODE (XEXP (x, 0)) != REG)
2471 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2473 if (legitimate_constant_pool_address_p (x))
2475 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2478 offset = INTVAL (XEXP (x, 1));
2486 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2487 which leaves the only valid constant offset of zero, which by
2488 canonicalization rules is also invalid. */
2495 /* SPE vector modes. */
2496 return SPE_CONST_OFFSET_OK (offset);
2499 if (TARGET_E500_DOUBLE)
2500 return SPE_CONST_OFFSET_OK (offset);
2503 /* On e500v2, we may have:
2505 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2507 Which gets addressed with evldd instructions. */
2508 if (TARGET_E500_DOUBLE)
2509 return SPE_CONST_OFFSET_OK (offset);
2511 if (mode == DFmode || !TARGET_POWERPC64)
2513 else if (offset & 3)
2519 if (mode == TFmode || !TARGET_POWERPC64)
2521 else if (offset & 3)
2532 return (offset < 0x10000) && (offset + extra < 0x10000);
2536 legitimate_indexed_address_p (rtx x, int strict)
2540 if (GET_CODE (x) != PLUS)
2546 if (!REG_P (op0) || !REG_P (op1))
2549 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2550 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2551 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2552 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2556 legitimate_indirect_address_p (rtx x, int strict)
2558 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2562 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2564 if (!TARGET_MACHO || !flag_pic
2565 || mode != SImode || GET_CODE (x) != MEM)
2569 if (GET_CODE (x) != LO_SUM)
2571 if (GET_CODE (XEXP (x, 0)) != REG)
2573 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2577 return CONSTANT_P (x);
2581 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2583 if (GET_CODE (x) != LO_SUM)
2585 if (GET_CODE (XEXP (x, 0)) != REG)
2587 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2589 /* Restrict addressing for DI because of our SUBREG hackery. */
2590 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2594 if (TARGET_ELF || TARGET_MACHO)
2596 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2600 if (GET_MODE_NUNITS (mode) != 1)
2602 if (GET_MODE_BITSIZE (mode) > 64
2603 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2604 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2607 return CONSTANT_P (x);
2614 /* Try machine-dependent ways of modifying an illegitimate address
2615 to be legitimate. If we find one, return the new, valid address.
2616 This is used from only one place: `memory_address' in explow.c.
2618 OLDX is the address as it was before break_out_memory_refs was
2619 called. In some cases it is useful to look at this to decide what
2622 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2624 It is always safe for this function to do nothing. It exists to
2625 recognize opportunities to optimize the output.
2627 On RS/6000, first check for the sum of a register with a constant
2628 integer that is out of range. If so, generate code to add the
2629 constant with the low-order 16 bits masked to the register and force
2630 this result into another register (this can be done with `cau').
2631 Then generate an address of REG+(CONST&0xffff), allowing for the
2632 possibility of bit 16 being a one.
2634 Then check for the sum of a register and something not constant, try to
2635 load the other things into a register and return the sum. */
2638 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2639 enum machine_mode mode)
2641 if (GET_CODE (x) == SYMBOL_REF)
2643 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2645 return rs6000_legitimize_tls_address (x, model);
2648 if (GET_CODE (x) == PLUS
2649 && GET_CODE (XEXP (x, 0)) == REG
2650 && GET_CODE (XEXP (x, 1)) == CONST_INT
2651 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2653 HOST_WIDE_INT high_int, low_int;
2655 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2656 high_int = INTVAL (XEXP (x, 1)) - low_int;
2657 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2658 GEN_INT (high_int)), 0);
2659 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2661 else if (GET_CODE (x) == PLUS
2662 && GET_CODE (XEXP (x, 0)) == REG
2663 && GET_CODE (XEXP (x, 1)) != CONST_INT
2664 && GET_MODE_NUNITS (mode) == 1
2665 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2667 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2669 && (TARGET_POWERPC64 || mode != DImode)
2672 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2673 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2675 else if (ALTIVEC_VECTOR_MODE (mode))
2679 /* Make sure both operands are registers. */
2680 if (GET_CODE (x) == PLUS)
2681 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2682 force_reg (Pmode, XEXP (x, 1)));
2684 reg = force_reg (Pmode, x);
2687 else if (SPE_VECTOR_MODE (mode)
2688 || (TARGET_E500_DOUBLE && (mode == DFmode
2689 || mode == DImode)))
2693 /* We accept [reg + reg] and [reg + OFFSET]. */
2695 if (GET_CODE (x) == PLUS)
2697 rtx op1 = XEXP (x, 0);
2698 rtx op2 = XEXP (x, 1);
2700 op1 = force_reg (Pmode, op1);
2702 if (GET_CODE (op2) != REG
2703 && (GET_CODE (op2) != CONST_INT
2704 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2705 op2 = force_reg (Pmode, op2);
2707 return gen_rtx_PLUS (Pmode, op1, op2);
2710 return force_reg (Pmode, x);
2716 && GET_CODE (x) != CONST_INT
2717 && GET_CODE (x) != CONST_DOUBLE
2719 && GET_MODE_NUNITS (mode) == 1
2720 && (GET_MODE_BITSIZE (mode) <= 32
2721 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2723 rtx reg = gen_reg_rtx (Pmode);
2724 emit_insn (gen_elf_high (reg, x));
2725 return gen_rtx_LO_SUM (Pmode, reg, x);
2727 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2730 && ! MACHO_DYNAMIC_NO_PIC_P
2732 && GET_CODE (x) != CONST_INT
2733 && GET_CODE (x) != CONST_DOUBLE
2735 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2739 rtx reg = gen_reg_rtx (Pmode);
2740 emit_insn (gen_macho_high (reg, x));
2741 return gen_rtx_LO_SUM (Pmode, reg, x);
2744 && constant_pool_expr_p (x)
2745 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2747 return create_TOC_reference (x);
2753 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
2754 We need to emit DTP-relative relocations. */
2757 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2762 fputs ("\t.long\t", file);
2765 fputs (DOUBLE_INT_ASM_OP, file);
2770 output_addr_const (file, x);
2771 fputs ("@dtprel+0x8000", file);
2774 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2776 static GTY(()) rtx rs6000_tls_symbol;
2778 rs6000_tls_get_addr (void)
2780 if (!rs6000_tls_symbol)
2781 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2783 return rs6000_tls_symbol;
2786 /* Construct the SYMBOL_REF for TLS GOT references. */
2788 static GTY(()) rtx rs6000_got_symbol;
2790 rs6000_got_sym (void)
2792 if (!rs6000_got_symbol)
2794 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2795 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2796 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2799 return rs6000_got_symbol;
2802 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2803 this (thread-local) address. */
2806 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2810 dest = gen_reg_rtx (Pmode);
2811 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2817 tlsreg = gen_rtx_REG (Pmode, 13);
2818 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2822 tlsreg = gen_rtx_REG (Pmode, 2);
2823 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2827 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2831 tmp = gen_reg_rtx (Pmode);
2834 tlsreg = gen_rtx_REG (Pmode, 13);
2835 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2839 tlsreg = gen_rtx_REG (Pmode, 2);
2840 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2844 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2846 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2851 rtx r3, got, tga, tmp1, tmp2, eqv;
2854 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2858 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2861 rtx gsym = rs6000_got_sym ();
2862 got = gen_reg_rtx (Pmode);
2864 rs6000_emit_move (got, gsym, Pmode);
2867 rtx tempLR, tmp3, mem;
2870 tempLR = gen_reg_rtx (Pmode);
2871 tmp1 = gen_reg_rtx (Pmode);
2872 tmp2 = gen_reg_rtx (Pmode);
2873 tmp3 = gen_reg_rtx (Pmode);
2874 mem = gen_const_mem (Pmode, tmp1);
2876 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
2877 emit_move_insn (tmp1, tempLR);
2878 emit_move_insn (tmp2, mem);
2879 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2880 last = emit_move_insn (got, tmp3);
2881 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2883 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2885 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2891 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2893 r3 = gen_rtx_REG (Pmode, 3);
2895 insn = gen_tls_gd_64 (r3, got, addr);
2897 insn = gen_tls_gd_32 (r3, got, addr);
2900 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2901 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2902 insn = emit_call_insn (insn);
2903 CONST_OR_PURE_CALL_P (insn) = 1;
2904 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2905 insn = get_insns ();
2907 emit_libcall_block (insn, dest, r3, addr);
2909 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2911 r3 = gen_rtx_REG (Pmode, 3);
2913 insn = gen_tls_ld_64 (r3, got);
2915 insn = gen_tls_ld_32 (r3, got);
2918 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2919 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2920 insn = emit_call_insn (insn);
2921 CONST_OR_PURE_CALL_P (insn) = 1;
2922 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2923 insn = get_insns ();
2925 tmp1 = gen_reg_rtx (Pmode);
2926 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2928 emit_libcall_block (insn, tmp1, r3, eqv);
2929 if (rs6000_tls_size == 16)
2932 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2934 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2936 else if (rs6000_tls_size == 32)
2938 tmp2 = gen_reg_rtx (Pmode);
2940 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2942 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2945 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2947 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2951 tmp2 = gen_reg_rtx (Pmode);
2953 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2955 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2957 insn = gen_rtx_SET (Pmode, dest,
2958 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2964 /* IE, or 64 bit offset LE. */
2965 tmp2 = gen_reg_rtx (Pmode);
2967 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2969 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2972 insn = gen_tls_tls_64 (dest, tmp2, addr);
2974 insn = gen_tls_tls_32 (dest, tmp2, addr);
2982 /* Return 1 if X contains a thread-local symbol. */
2985 rs6000_tls_referenced_p (rtx x)
2987 if (! TARGET_HAVE_TLS)
2990 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2993 /* Return 1 if *X is a thread-local symbol. This is the same as
2994 rs6000_tls_symbol_ref except for the type of the unused argument. */
2997 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2999 return RS6000_SYMBOL_REF_TLS_P (*x);
3002 /* The convention appears to be to define this wherever it is used.
3003 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3004 is now used here. */
3005 #ifndef REG_MODE_OK_FOR_BASE_P
3006 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3009 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3010 replace the input X, or the original X if no replacement is called for.
3011 The output parameter *WIN is 1 if the calling macro should goto WIN,
3014 For RS/6000, we wish to handle large displacements off a base
3015 register by splitting the addend across an addiu/addis and the mem insn.
3016 This cuts number of extra insns needed from 3 to 1.
3018 On Darwin, we use this to generate code for floating point constants.
3019 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3020 The Darwin code is inside #if TARGET_MACHO because only then is
3021 machopic_function_base_name() defined. */
3023 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3024 int opnum, int type,
3025 int ind_levels ATTRIBUTE_UNUSED, int *win)
3027 /* We must recognize output that we have already generated ourselves. */
3028 if (GET_CODE (x) == PLUS
3029 && GET_CODE (XEXP (x, 0)) == PLUS
3030 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3031 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3032 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3034 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3035 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3036 opnum, (enum reload_type)type);
3042 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3043 && GET_CODE (x) == LO_SUM
3044 && GET_CODE (XEXP (x, 0)) == PLUS
3045 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3046 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3047 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3048 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3049 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3050 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3051 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3053 /* Result of previous invocation of this function on Darwin
3054 floating point constant. */
3055 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3056 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3057 opnum, (enum reload_type)type);
3063 /* Force ld/std non-word aligned offset into base register by wrapping
3065 if (GET_CODE (x) == PLUS
3066 && GET_CODE (XEXP (x, 0)) == REG
3067 && REGNO (XEXP (x, 0)) < 32
3068 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3069 && GET_CODE (XEXP (x, 1)) == CONST_INT
3070 && (INTVAL (XEXP (x, 1)) & 3) != 0
3071 && !ALTIVEC_VECTOR_MODE (mode)
3072 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3073 && TARGET_POWERPC64)
3075 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3076 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3077 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3078 opnum, (enum reload_type) type);
3083 if (GET_CODE (x) == PLUS
3084 && GET_CODE (XEXP (x, 0)) == REG
3085 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3086 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3087 && GET_CODE (XEXP (x, 1)) == CONST_INT
3088 && !SPE_VECTOR_MODE (mode)
3089 && !(TARGET_E500_DOUBLE && (mode == DFmode
3091 && !ALTIVEC_VECTOR_MODE (mode))
3093 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3094 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3096 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3098 /* Check for 32-bit overflow. */
3099 if (high + low != val)
3105 /* Reload the high part into a base reg; leave the low part
3106 in the mem directly. */
3108 x = gen_rtx_PLUS (GET_MODE (x),
3109 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3113 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3114 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3115 opnum, (enum reload_type)type);
3121 if (GET_CODE (x) == SYMBOL_REF
3122 && DEFAULT_ABI == ABI_DARWIN
3123 && !ALTIVEC_VECTOR_MODE (mode)
3124 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3125 /* Don't do this for TFmode, since the result isn't offsettable.
3126 The same goes for DImode without 64-bit gprs. */
3128 && (mode != DImode || TARGET_POWERPC64))
3132 rtx offset = gen_rtx_CONST (Pmode,
3133 gen_rtx_MINUS (Pmode, x,
3134 machopic_function_base_sym ()));
3135 x = gen_rtx_LO_SUM (GET_MODE (x),
3136 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3137 gen_rtx_HIGH (Pmode, offset)), offset);
3140 x = gen_rtx_LO_SUM (GET_MODE (x),
3141 gen_rtx_HIGH (Pmode, x), x);
3143 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3144 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3145 opnum, (enum reload_type)type);
3152 && constant_pool_expr_p (x)
3153 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3155 (x) = create_TOC_reference (x);
3163 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3164 that is a valid memory address for an instruction.
3165 The MODE argument is the machine mode for the MEM expression
3166 that wants to use this address.
3168 On the RS/6000, there are four valid address: a SYMBOL_REF that
3169 refers to a constant pool entry of an address (or the sum of it
3170 plus a constant), a short (16-bit signed) constant plus a register,
3171 the sum of two registers, or a register indirect, possibly with an
3172 auto-increment. For DFmode and DImode with a constant plus register,
3173 we must ensure that both words are addressable or PowerPC64 with offset
3176 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3177 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3178 adjacent memory cells are accessed by adding word-sized offsets
3179 during assembly output. */
3181 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3183 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3185 && ALTIVEC_VECTOR_MODE (mode)
3186 && GET_CODE (x) == AND
3187 && GET_CODE (XEXP (x, 1)) == CONST_INT
3188 && INTVAL (XEXP (x, 1)) == -16)
3191 if (RS6000_SYMBOL_REF_TLS_P (x))
3193 if (legitimate_indirect_address_p (x, reg_ok_strict))
3195 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3196 && !ALTIVEC_VECTOR_MODE (mode)
3197 && !SPE_VECTOR_MODE (mode)
3198 /* Restrict addressing for DI because of our SUBREG hackery. */
3199 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3201 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3203 if (legitimate_small_data_p (mode, x))
3205 if (legitimate_constant_pool_address_p (x))
3207 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3209 && GET_CODE (x) == PLUS
3210 && GET_CODE (XEXP (x, 0)) == REG
3211 && (XEXP (x, 0) == virtual_stack_vars_rtx
3212 || XEXP (x, 0) == arg_pointer_rtx)
3213 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3215 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3219 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3221 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3222 && (TARGET_POWERPC64 || mode != DImode)
3223 && legitimate_indexed_address_p (x, reg_ok_strict))
3225 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3230 /* Go to LABEL if ADDR (a legitimate address expression)
3231 has an effect that depends on the machine mode it is used for.
3233 On the RS/6000 this is true of all integral offsets (since AltiVec
3234 modes don't allow them) or is a pre-increment or decrement.
3236 ??? Except that due to conceptual problems in offsettable_address_p
3237 we can't really report the problems of integral offsets. So leave
3238 this assuming that the adjustable offset must be valid for the
3239 sub-words of a TFmode operand, which is what we had before. */
3242 rs6000_mode_dependent_address (rtx addr)
3244 switch (GET_CODE (addr))
3247 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3249 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3250 return val + 12 + 0x8000 >= 0x10000;
3259 return TARGET_UPDATE;
3268 /* Return number of consecutive hard regs needed starting at reg REGNO
3269 to hold something of mode MODE.
3270 This is ordinarily the length in words of a value of mode MODE
3271 but can be less for certain modes in special long registers.
3273 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3274 scalar instructions. The upper 32 bits are only available to the
3277 POWER and PowerPC GPRs hold 32 bits worth;
3278 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3281 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3283 if (FP_REGNO_P (regno))
3284 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3286 if (TARGET_E500_DOUBLE && mode == DFmode)
3289 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3290 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3292 if (ALTIVEC_REGNO_P (regno))
3294 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3296 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3299 /* Change register usage conditional on target flags. */
3301 rs6000_conditional_register_usage (void)
3305 /* Set MQ register fixed (already call_used) if not POWER
3306 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3311 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3313 fixed_regs[13] = call_used_regs[13]
3314 = call_really_used_regs[13] = 1;
3316 /* Conditionally disable FPRs. */
3317 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3318 for (i = 32; i < 64; i++)
3319 fixed_regs[i] = call_used_regs[i]
3320 = call_really_used_regs[i] = 1;
3322 /* The TOC register is not killed across calls in a way that is
3323 visible to the compiler. */
3324 if (DEFAULT_ABI == ABI_AIX)
3325 call_really_used_regs[2] = 0;
3327 if (DEFAULT_ABI == ABI_V4
3328 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3330 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3332 if (DEFAULT_ABI == ABI_V4
3333 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3335 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3336 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3337 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3339 if (DEFAULT_ABI == ABI_DARWIN
3340 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3341 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3342 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3343 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3345 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3346 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3347 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3350 global_regs[VSCR_REGNO] = 1;
3354 global_regs[SPEFSCR_REGNO] = 1;
3355 fixed_regs[FIXED_SCRATCH]
3356 = call_used_regs[FIXED_SCRATCH]
3357 = call_really_used_regs[FIXED_SCRATCH] = 1;
3360 if (! TARGET_ALTIVEC)
3362 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3363 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3364 call_really_used_regs[VRSAVE_REGNO] = 1;
3367 if (TARGET_ALTIVEC_ABI)
3368 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3369 call_used_regs[i] = call_really_used_regs[i] = 1;
3372 /* Try to output insns to set TARGET equal to the constant C if it can
3373 be done in less than N insns. Do all computations in MODE.
3374 Returns the place where the output has been placed if it can be
3375 done and the insns have been emitted. If it would take more than N
3376 insns, zero is returned and no insns and emitted. */
3379 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3380 rtx source, int n ATTRIBUTE_UNUSED)
3382 rtx result, insn, set;
3383 HOST_WIDE_INT c0, c1;
3390 dest = gen_reg_rtx (mode);
3391 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3395 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3397 emit_insn (gen_rtx_SET (VOIDmode, result,
3398 GEN_INT (INTVAL (source)
3399 & (~ (HOST_WIDE_INT) 0xffff))));
3400 emit_insn (gen_rtx_SET (VOIDmode, dest,
3401 gen_rtx_IOR (SImode, result,
3402 GEN_INT (INTVAL (source) & 0xffff))));
3407 switch (GET_CODE (source))
3410 c0 = INTVAL (source);
3415 #if HOST_BITS_PER_WIDE_INT >= 64
3416 c0 = CONST_DOUBLE_LOW (source);
3419 c0 = CONST_DOUBLE_LOW (source);
3420 c1 = CONST_DOUBLE_HIGH (source);
3428 result = rs6000_emit_set_long_const (dest, c0, c1);
3435 insn = get_last_insn ();
3436 set = single_set (insn);
3437 if (! CONSTANT_P (SET_SRC (set)))
3438 set_unique_reg_note (insn, REG_EQUAL, source);
3443 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3444 fall back to a straight forward decomposition. We do this to avoid
3445 exponential run times encountered when looking for longer sequences
3446 with rs6000_emit_set_const. */
3448 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3450 if (!TARGET_POWERPC64)
3452 rtx operand1, operand2;
3454 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3456 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3458 emit_move_insn (operand1, GEN_INT (c1));
3459 emit_move_insn (operand2, GEN_INT (c2));
3463 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3466 ud2 = (c1 & 0xffff0000) >> 16;
3467 #if HOST_BITS_PER_WIDE_INT >= 64
3471 ud4 = (c2 & 0xffff0000) >> 16;
3473 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3474 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3477 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3479 emit_move_insn (dest, GEN_INT (ud1));
3482 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3483 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3486 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3489 emit_move_insn (dest, GEN_INT (ud2 << 16));
3491 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3493 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3494 || (ud4 == 0 && ! (ud3 & 0x8000)))
3497 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3500 emit_move_insn (dest, GEN_INT (ud3 << 16));
3503 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3504 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3506 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3511 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3514 emit_move_insn (dest, GEN_INT (ud4 << 16));
3517 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3519 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3521 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3522 GEN_INT (ud2 << 16)));
3524 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3530 /* Helper for the following. Get rid of [r+r] memory refs
3531 in cases where it won't work (TImode, TFmode). */
3534 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3536 if (GET_CODE (operands[0]) == MEM
3537 && GET_CODE (XEXP (operands[0], 0)) != REG
3538 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3539 && ! reload_in_progress)
3541 = replace_equiv_address (operands[0],
3542 copy_addr_to_reg (XEXP (operands[0], 0)));
3544 if (GET_CODE (operands[1]) == MEM
3545 && GET_CODE (XEXP (operands[1], 0)) != REG
3546 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3547 && ! reload_in_progress)
3549 = replace_equiv_address (operands[1],
3550 copy_addr_to_reg (XEXP (operands[1], 0)));
3553 /* Emit a move from SOURCE to DEST in mode MODE. */
3555 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3559 operands[1] = source;
3561 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3562 if (GET_CODE (operands[1]) == CONST_DOUBLE
3563 && ! FLOAT_MODE_P (mode)
3564 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3566 /* FIXME. This should never happen. */
3567 /* Since it seems that it does, do the safe thing and convert
3569 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3571 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3572 || FLOAT_MODE_P (mode)
3573 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3574 || CONST_DOUBLE_LOW (operands[1]) < 0)
3575 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3576 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3578 /* Check if GCC is setting up a block move that will end up using FP
3579 registers as temporaries. We must make sure this is acceptable. */
3580 if (GET_CODE (operands[0]) == MEM
3581 && GET_CODE (operands[1]) == MEM
3583 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3584 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3585 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3586 ? 32 : MEM_ALIGN (operands[0])))
3587 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3589 : MEM_ALIGN (operands[1]))))
3590 && ! MEM_VOLATILE_P (operands [0])
3591 && ! MEM_VOLATILE_P (operands [1]))
3593 emit_move_insn (adjust_address (operands[0], SImode, 0),
3594 adjust_address (operands[1], SImode, 0));
3595 emit_move_insn (adjust_address (operands[0], SImode, 4),
3596 adjust_address (operands[1], SImode, 4));
3600 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3601 && !gpc_reg_operand (operands[1], mode))
3602 operands[1] = force_reg (mode, operands[1]);
3604 if (mode == SFmode && ! TARGET_POWERPC
3605 && TARGET_HARD_FLOAT && TARGET_FPRS
3606 && GET_CODE (operands[0]) == MEM)
3610 if (reload_in_progress || reload_completed)
3611 regnum = true_regnum (operands[1]);
3612 else if (GET_CODE (operands[1]) == REG)
3613 regnum = REGNO (operands[1]);
3617 /* If operands[1] is a register, on POWER it may have
3618 double-precision data in it, so truncate it to single
3620 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3623 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3624 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3625 operands[1] = newreg;
3629 /* Recognize the case where operand[1] is a reference to thread-local
3630 data and load its address to a register. */
3631 if (rs6000_tls_referenced_p (operands[1]))
3633 enum tls_model model;
3634 rtx tmp = operands[1];
3637 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3639 addend = XEXP (XEXP (tmp, 0), 1);
3640 tmp = XEXP (XEXP (tmp, 0), 0);
3643 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3644 model = SYMBOL_REF_TLS_MODEL (tmp);
3645 gcc_assert (model != 0);
3647 tmp = rs6000_legitimize_tls_address (tmp, model);
3650 tmp = gen_rtx_PLUS (mode, tmp, addend);
3651 tmp = force_operand (tmp, operands[0]);
3656 /* Handle the case where reload calls us with an invalid address. */
3657 if (reload_in_progress && mode == Pmode
3658 && (! general_operand (operands[1], mode)
3659 || ! nonimmediate_operand (operands[0], mode)))
3662 /* 128-bit constant floating-point values on Darwin should really be
3663 loaded as two parts. */
3664 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3665 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3666 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3668 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3669 know how to get a DFmode SUBREG of a TFmode. */
3670 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3671 simplify_gen_subreg (DImode, operands[1], mode, 0),
3673 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3674 GET_MODE_SIZE (DImode)),
3675 simplify_gen_subreg (DImode, operands[1], mode,
3676 GET_MODE_SIZE (DImode)),
3681 /* FIXME: In the long term, this switch statement should go away
3682 and be replaced by a sequence of tests based on things like
3688 if (CONSTANT_P (operands[1])
3689 && GET_CODE (operands[1]) != CONST_INT)
3690 operands[1] = force_const_mem (mode, operands[1]);
3694 rs6000_eliminate_indexed_memrefs (operands);
3699 if (CONSTANT_P (operands[1])
3700 && ! easy_fp_constant (operands[1], mode))
3701 operands[1] = force_const_mem (mode, operands[1]);
3712 if (CONSTANT_P (operands[1])
3713 && !easy_vector_constant (operands[1], mode))
3714 operands[1] = force_const_mem (mode, operands[1]);
3719 /* Use default pattern for address of ELF small data */
3722 && DEFAULT_ABI == ABI_V4
3723 && (GET_CODE (operands[1]) == SYMBOL_REF
3724 || GET_CODE (operands[1]) == CONST)
3725 && small_data_operand (operands[1], mode))
3727 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3731 if (DEFAULT_ABI == ABI_V4
3732 && mode == Pmode && mode == SImode
3733 && flag_pic == 1 && got_operand (operands[1], mode))
3735 emit_insn (gen_movsi_got (operands[0], operands[1]));
3739 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3743 && CONSTANT_P (operands[1])
3744 && GET_CODE (operands[1]) != HIGH
3745 && GET_CODE (operands[1]) != CONST_INT)
3747 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3749 /* If this is a function address on -mcall-aixdesc,
3750 convert it to the address of the descriptor. */
3751 if (DEFAULT_ABI == ABI_AIX
3752 && GET_CODE (operands[1]) == SYMBOL_REF
3753 && XSTR (operands[1], 0)[0] == '.')
3755 const char *name = XSTR (operands[1], 0);
3757 while (*name == '.')
3759 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3760 CONSTANT_POOL_ADDRESS_P (new_ref)
3761 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3762 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3763 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3764 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3765 operands[1] = new_ref;
3768 if (DEFAULT_ABI == ABI_DARWIN)
3771 if (MACHO_DYNAMIC_NO_PIC_P)
3773 /* Take care of any required data indirection. */
3774 operands[1] = rs6000_machopic_legitimize_pic_address (
3775 operands[1], mode, operands[0]);
3776 if (operands[0] != operands[1])
3777 emit_insn (gen_rtx_SET (VOIDmode,
3778 operands[0], operands[1]));
3782 emit_insn (gen_macho_high (target, operands[1]));
3783 emit_insn (gen_macho_low (operands[0], target, operands[1]));
3787 emit_insn (gen_elf_high (target, operands[1]));
3788 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3792 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3793 and we have put it in the TOC, we just need to make a TOC-relative
3796 && GET_CODE (operands[1]) == SYMBOL_REF
3797 && constant_pool_expr_p (operands[1])
3798 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3799 get_pool_mode (operands[1])))
3801 operands[1] = create_TOC_reference (operands[1]);
3803 else if (mode == Pmode
3804 && CONSTANT_P (operands[1])
3805 && ((GET_CODE (operands[1]) != CONST_INT
3806 && ! easy_fp_constant (operands[1], mode))
3807 || (GET_CODE (operands[1]) == CONST_INT
3808 && num_insns_constant (operands[1], mode) > 2)
3809 || (GET_CODE (operands[0]) == REG
3810 && FP_REGNO_P (REGNO (operands[0]))))
3811 && GET_CODE (operands[1]) != HIGH
3812 && ! legitimate_constant_pool_address_p (operands[1])
3813 && ! toc_relative_expr_p (operands[1]))
3815 /* Emit a USE operation so that the constant isn't deleted if
3816 expensive optimizations are turned on because nobody
3817 references it. This should only be done for operands that
3818 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3819 This should not be done for operands that contain LABEL_REFs.
3820 For now, we just handle the obvious case. */
3821 if (GET_CODE (operands[1]) != LABEL_REF)
3822 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3825 /* Darwin uses a special PIC legitimizer. */
3826 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3829 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3831 if (operands[0] != operands[1])
3832 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3837 /* If we are to limit the number of things we put in the TOC and
3838 this is a symbol plus a constant we can add in one insn,
3839 just put the symbol in the TOC and add the constant. Don't do
3840 this if reload is in progress. */
3841 if (GET_CODE (operands[1]) == CONST
3842 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3843 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3844 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3845 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3846 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3847 && ! side_effects_p (operands[0]))
3850 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3851 rtx other = XEXP (XEXP (operands[1], 0), 1);
3853 sym = force_reg (mode, sym);
3855 emit_insn (gen_addsi3 (operands[0], sym, other));
3857 emit_insn (gen_adddi3 (operands[0], sym, other));
3861 operands[1] = force_const_mem (mode, operands[1]);
3864 && constant_pool_expr_p (XEXP (operands[1], 0))
3865 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3866 get_pool_constant (XEXP (operands[1], 0)),
3867 get_pool_mode (XEXP (operands[1], 0))))
3870 = gen_const_mem (mode,
3871 create_TOC_reference (XEXP (operands[1], 0)));
3872 set_mem_alias_set (operands[1], get_TOC_alias_set ());
3878 rs6000_eliminate_indexed_memrefs (operands);
3882 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3884 gen_rtx_SET (VOIDmode,
3885 operands[0], operands[1]),
3886 gen_rtx_CLOBBER (VOIDmode,
3887 gen_rtx_SCRATCH (SImode)))));
3896 /* Above, we may have called force_const_mem which may have returned
3897 an invalid address. If we can, fix this up; otherwise, reload will
3898 have to deal with it. */
3899 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3900 operands[1] = validize_mem (operands[1]);
3903 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3906 /* Nonzero if we can use a floating-point register to pass this arg. */
3907 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3908 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3909 && (CUM)->fregno <= FP_ARG_MAX_REG \
3910 && TARGET_HARD_FLOAT && TARGET_FPRS)
3912 /* Nonzero if we can use an AltiVec register to pass this arg. */
3913 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3914 (ALTIVEC_VECTOR_MODE (MODE) \
3915 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3916 && TARGET_ALTIVEC_ABI \
3919 /* Return a nonzero value to say to return the function value in
3920 memory, just as large structures are always returned. TYPE will be
3921 the data type of the value, and FNTYPE will be the type of the
3922 function doing the returning, or @code{NULL} for libcalls.
3924 The AIX ABI for the RS/6000 specifies that all structures are
3925 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3926 specifies that structures <= 8 bytes are returned in r3/r4, but a
3927 draft put them in memory, and GCC used to implement the draft
3928 instead of the final standard. Therefore, aix_struct_return
3929 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3930 compatibility can change DRAFT_V4_STRUCT_RET to override the
3931 default, and -m switches get the final word. See
3932 rs6000_override_options for more details.
3934 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3935 long double support is enabled. These values are returned in memory.
3937 int_size_in_bytes returns -1 for variable size objects, which go in
3938 memory always. The cast to unsigned makes -1 > 8. */
3941 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3943 /* In the darwin64 abi, try to use registers for larger structs
3945 if (rs6000_darwin64_abi
3946 && TREE_CODE (type) == RECORD_TYPE
3947 && int_size_in_bytes (type) > 0)
3949 CUMULATIVE_ARGS valcum;
3953 valcum.fregno = FP_ARG_MIN_REG;
3954 valcum.vregno = ALTIVEC_ARG_MIN_REG;
3955 /* Do a trial code generation as if this were going to be passed
3956 as an argument; if any part goes in memory, we return NULL. */
3957 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
3960 /* Otherwise fall through to more conventional ABI rules. */
3963 if (AGGREGATE_TYPE_P (type)
3964 && (aix_struct_return
3965 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3968 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
3969 modes only exist for GCC vector types if -maltivec. */
3970 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
3971 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
3974 /* Return synthetic vectors in memory. */
3975 if (TREE_CODE (type) == VECTOR_TYPE
3976 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
3978 static bool warned_for_return_big_vectors = false;
3979 if (!warned_for_return_big_vectors)
3981 warning (0, "GCC vector returned by reference: "
3982 "non-standard ABI extension with no compatibility guarantee");
3983 warned_for_return_big_vectors = true;
3988 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3994 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3995 for a call to a function whose data type is FNTYPE.
3996 For a library call, FNTYPE is 0.
3998 For incoming args we set the number of arguments in the prototype large
3999 so we never return a PARALLEL. */
4002 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4003 rtx libname ATTRIBUTE_UNUSED, int incoming,
4004 int libcall, int n_named_args)
4006 static CUMULATIVE_ARGS zero_cumulative;
4008 *cum = zero_cumulative;
4010 cum->fregno = FP_ARG_MIN_REG;
4011 cum->vregno = ALTIVEC_ARG_MIN_REG;
4012 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4013 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4014 ? CALL_LIBCALL : CALL_NORMAL);
4015 cum->sysv_gregno = GP_ARG_MIN_REG;
4016 cum->stdarg = fntype
4017 && (TYPE_ARG_TYPES (fntype) != 0
4018 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4019 != void_type_node));
4021 cum->nargs_prototype = 0;
4022 if (incoming || cum->prototype)
4023 cum->nargs_prototype = n_named_args;
4025 /* Check for a longcall attribute. */
4026 if ((!fntype && rs6000_default_long_calls)
4028 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4029 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4030 cum->call_cookie |= CALL_LONG;
4032 if (TARGET_DEBUG_ARG)
4034 fprintf (stderr, "\ninit_cumulative_args:");
4037 tree ret_type = TREE_TYPE (fntype);
4038 fprintf (stderr, " ret code = %s,",
4039 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4042 if (cum->call_cookie & CALL_LONG)
4043 fprintf (stderr, " longcall,");
4045 fprintf (stderr, " proto = %d, nargs = %d\n",
4046 cum->prototype, cum->nargs_prototype);
4051 && TARGET_ALTIVEC_ABI
4052 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4054 error ("cannot return value in vector register because"
4055 " altivec instructions are disabled, use -maltivec"
4060 /* Return true if TYPE must be passed on the stack and not in registers. */
4063 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4065 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4066 return must_pass_in_stack_var_size (mode, type);
4068 return must_pass_in_stack_var_size_or_pad (mode, type);
4071 /* If defined, a C expression which determines whether, and in which
4072 direction, to pad out an argument with extra space. The value
4073 should be of type `enum direction': either `upward' to pad above
4074 the argument, `downward' to pad below, or `none' to inhibit
4077 For the AIX ABI structs are always stored left shifted in their
4081 function_arg_padding (enum machine_mode mode, tree type)
4083 #ifndef AGGREGATE_PADDING_FIXED
4084 #define AGGREGATE_PADDING_FIXED 0
4086 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4087 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4090 if (!AGGREGATE_PADDING_FIXED)
4092 /* GCC used to pass structures of the same size as integer types as
4093 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4094 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4095 passed padded downward, except that -mstrict-align further
4096 muddied the water in that multi-component structures of 2 and 4
4097 bytes in size were passed padded upward.
4099 The following arranges for best compatibility with previous
4100 versions of gcc, but removes the -mstrict-align dependency. */
4101 if (BYTES_BIG_ENDIAN)
4103 HOST_WIDE_INT size = 0;
4105 if (mode == BLKmode)
4107 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4108 size = int_size_in_bytes (type);
4111 size = GET_MODE_SIZE (mode);
4113 if (size == 1 || size == 2 || size == 4)
4119 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4121 if (type != 0 && AGGREGATE_TYPE_P (type))
4125 /* Fall back to the default. */
4126 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4129 /* If defined, a C expression that gives the alignment boundary, in bits,
4130 of an argument with the specified mode and type. If it is not defined,
4131 PARM_BOUNDARY is used for all arguments.
4133 V.4 wants long longs to be double word aligned.
4134 Doubleword align SPE vectors.
4135 Quadword align Altivec vectors.
4136 Quadword align large synthetic vector types. */
4139 function_arg_boundary (enum machine_mode mode, tree type)
4141 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4143 else if (SPE_VECTOR_MODE (mode)
4144 || (type && TREE_CODE (type) == VECTOR_TYPE
4145 && int_size_in_bytes (type) >= 8
4146 && int_size_in_bytes (type) < 16))
4148 else if (ALTIVEC_VECTOR_MODE (mode)
4149 || (type && TREE_CODE (type) == VECTOR_TYPE
4150 && int_size_in_bytes (type) >= 16))
4152 else if (rs6000_darwin64_abi && mode == BLKmode
4153 && type && TYPE_ALIGN (type) > 64)
4156 return PARM_BOUNDARY;
4159 /* For a function parm of MODE and TYPE, return the starting word in
4160 the parameter area. NWORDS of the parameter area are already used. */
4163 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4166 unsigned int parm_offset;
4168 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4169 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4170 return nwords + (-(parm_offset + nwords) & align);
4173 /* Compute the size (in words) of a function argument. */
4175 static unsigned long
4176 rs6000_arg_size (enum machine_mode mode, tree type)
4180 if (mode != BLKmode)
4181 size = GET_MODE_SIZE (mode);
4183 size = int_size_in_bytes (type);
4186 return (size + 3) >> 2;
4188 return (size + 7) >> 3;
4191 /* Use this to flush pending int fields. */
4194 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4195 HOST_WIDE_INT bitpos)
4197 unsigned int startbit, endbit;
4198 int intregs, intoffset;
4199 enum machine_mode mode;
4201 if (cum->intoffset == -1)
4204 intoffset = cum->intoffset;
4205 cum->intoffset = -1;
4207 if (intoffset % BITS_PER_WORD != 0)
4209 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4211 if (mode == BLKmode)
4213 /* We couldn't find an appropriate mode, which happens,
4214 e.g., in packed structs when there are 3 bytes to load.
4215 Back intoffset back to the beginning of the word in this
4217 intoffset = intoffset & -BITS_PER_WORD;
4221 startbit = intoffset & -BITS_PER_WORD;
4222 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4223 intregs = (endbit - startbit) / BITS_PER_WORD;
4224 cum->words += intregs;
4227 /* The darwin64 ABI calls for us to recurse down through structs,
4228 looking for elements passed in registers. Unfortunately, we have
4229 to track int register count here also because of misalignments
4230 in powerpc alignment mode. */
4233 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4235 HOST_WIDE_INT startbitpos)
4239 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4240 if (TREE_CODE (f) == FIELD_DECL)
4242 HOST_WIDE_INT bitpos = startbitpos;
4243 tree ftype = TREE_TYPE (f);
4244 enum machine_mode mode = TYPE_MODE (ftype);
4246 if (DECL_SIZE (f) != 0
4247 && host_integerp (bit_position (f), 1))
4248 bitpos += int_bit_position (f);
4250 /* ??? FIXME: else assume zero offset. */
4252 if (TREE_CODE (ftype) == RECORD_TYPE)
4253 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4254 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4256 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4257 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4258 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4260 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4262 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4266 else if (cum->intoffset == -1)
4267 cum->intoffset = bitpos;
4271 /* Update the data in CUM to advance over an argument
4272 of mode MODE and data type TYPE.
4273 (TYPE is null for libcalls where that information may not be available.)
4275 Note that for args passed by reference, function_arg will be called
4276 with MODE and TYPE set to that of the pointer to the arg, not the arg
4280 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4281 tree type, int named, int depth)
4285 /* Only tick off an argument if we're not recursing. */
4287 cum->nargs_prototype--;
4289 if (TARGET_ALTIVEC_ABI
4290 && (ALTIVEC_VECTOR_MODE (mode)
4291 || (type && TREE_CODE (type) == VECTOR_TYPE
4292 && int_size_in_bytes (type) == 16)))
4296 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4299 if (!TARGET_ALTIVEC)
4300 error ("cannot pass argument in vector register because"
4301 " altivec instructions are disabled, use -maltivec"
4304 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4305 even if it is going to be passed in a vector register.
4306 Darwin does the same for variable-argument functions. */
4307 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4308 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4318 /* Vector parameters must be 16-byte aligned. This places
4319 them at 2 mod 4 in terms of words in 32-bit mode, since
4320 the parameter save area starts at offset 24 from the
4321 stack. In 64-bit mode, they just have to start on an
4322 even word, since the parameter save area is 16-byte
4323 aligned. Space for GPRs is reserved even if the argument
4324 will be passed in memory. */
4326 align = (2 - cum->words) & 3;
4328 align = cum->words & 1;
4329 cum->words += align + rs6000_arg_size (mode, type);
4331 if (TARGET_DEBUG_ARG)
4333 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4335 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4336 cum->nargs_prototype, cum->prototype,
4337 GET_MODE_NAME (mode));
4341 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4343 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4346 else if (rs6000_darwin64_abi
4348 && TREE_CODE (type) == RECORD_TYPE
4349 && (size = int_size_in_bytes (type)) > 0)
4351 /* Variable sized types have size == -1 and are
4352 treated as if consisting entirely of ints.
4353 Pad to 16 byte boundary if needed. */
4354 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4355 && (cum->words % 2) != 0)
4357 /* For varargs, we can just go up by the size of the struct. */
4359 cum->words += (size + 7) / 8;
4362 /* It is tempting to say int register count just goes up by
4363 sizeof(type)/8, but this is wrong in a case such as
4364 { int; double; int; } [powerpc alignment]. We have to
4365 grovel through the fields for these too. */
4367 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4368 rs6000_darwin64_record_arg_advance_flush (cum,
4369 size * BITS_PER_UNIT);
4372 else if (DEFAULT_ABI == ABI_V4)
4374 if (TARGET_HARD_FLOAT && TARGET_FPRS
4375 && (mode == SFmode || mode == DFmode))
4377 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4382 cum->words += cum->words & 1;
4383 cum->words += rs6000_arg_size (mode, type);
4388 int n_words = rs6000_arg_size (mode, type);
4389 int gregno = cum->sysv_gregno;
4391 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4392 (r7,r8) or (r9,r10). As does any other 2 word item such
4393 as complex int due to a historical mistake. */
4395 gregno += (1 - gregno) & 1;
4397 /* Multi-reg args are not split between registers and stack. */
4398 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4400 /* Long long and SPE vectors are aligned on the stack.
4401 So are other 2 word items such as complex int due to
4402 a historical mistake. */
4404 cum->words += cum->words & 1;
4405 cum->words += n_words;
4408 /* Note: continuing to accumulate gregno past when we've started
4409 spilling to the stack indicates the fact that we've started
4410 spilling to the stack to expand_builtin_saveregs. */
4411 cum->sysv_gregno = gregno + n_words;
4414 if (TARGET_DEBUG_ARG)
4416 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4417 cum->words, cum->fregno);
4418 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4419 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4420 fprintf (stderr, "mode = %4s, named = %d\n",
4421 GET_MODE_NAME (mode), named);
4426 int n_words = rs6000_arg_size (mode, type);
4427 int start_words = cum->words;
4428 int align_words = rs6000_parm_start (mode, type, start_words);
4430 cum->words = align_words + n_words;
4432 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4433 && TARGET_HARD_FLOAT && TARGET_FPRS)
4434 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4436 if (TARGET_DEBUG_ARG)
4438 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4439 cum->words, cum->fregno);
4440 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4441 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4442 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4443 named, align_words - start_words, depth);
4449 spe_build_register_parallel (enum machine_mode mode, int gregno)
4456 r1 = gen_rtx_REG (DImode, gregno);
4457 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4458 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4461 r1 = gen_rtx_REG (DImode, gregno);
4462 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4463 r3 = gen_rtx_REG (DImode, gregno + 2);
4464 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4465 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4472 /* Determine where to put a SIMD argument on the SPE. */
4474 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4477 int gregno = cum->sysv_gregno;
4479 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4480 are passed and returned in a pair of GPRs for ABI compatibility. */
4481 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4483 int n_words = rs6000_arg_size (mode, type);
4485 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4487 gregno += (1 - gregno) & 1;
4489 /* Multi-reg args are not split between registers and stack. */
4490 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4493 return spe_build_register_parallel (mode, gregno);
4497 int n_words = rs6000_arg_size (mode, type);
4499 /* SPE vectors are put in odd registers. */
4500 if (n_words == 2 && (gregno & 1) == 0)
4503 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4506 enum machine_mode m = SImode;
4508 r1 = gen_rtx_REG (m, gregno);
4509 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4510 r2 = gen_rtx_REG (m, gregno + 1);
4511 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4512 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4519 if (gregno <= GP_ARG_MAX_REG)
4520 return gen_rtx_REG (mode, gregno);
4526 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4527 structure between cum->intoffset and bitpos to integer registers. */
4530 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4531 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4533 enum machine_mode mode;
4535 unsigned int startbit, endbit;
4536 int this_regno, intregs, intoffset;
4539 if (cum->intoffset == -1)
4542 intoffset = cum->intoffset;
4543 cum->intoffset = -1;
4545 /* If this is the trailing part of a word, try to only load that
4546 much into the register. Otherwise load the whole register. Note
4547 that in the latter case we may pick up unwanted bits. It's not a
4548 problem at the moment but may wish to revisit. */
4550 if (intoffset % BITS_PER_WORD != 0)
4552 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4554 if (mode == BLKmode)
4556 /* We couldn't find an appropriate mode, which happens,
4557 e.g., in packed structs when there are 3 bytes to load.
4558 Back intoffset back to the beginning of the word in this
4560 intoffset = intoffset & -BITS_PER_WORD;
4567 startbit = intoffset & -BITS_PER_WORD;
4568 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4569 intregs = (endbit - startbit) / BITS_PER_WORD;
4570 this_regno = cum->words + intoffset / BITS_PER_WORD;
4572 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4575 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4579 intoffset /= BITS_PER_UNIT;
4582 regno = GP_ARG_MIN_REG + this_regno;
4583 reg = gen_rtx_REG (mode, regno);
4585 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4588 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4592 while (intregs > 0);
4595 /* Recursive workhorse for the following. */
4598 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4599 HOST_WIDE_INT startbitpos, rtx rvec[],
4604 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4605 if (TREE_CODE (f) == FIELD_DECL)
4607 HOST_WIDE_INT bitpos = startbitpos;
4608 tree ftype = TREE_TYPE (f);
4609 enum machine_mode mode = TYPE_MODE (ftype);
4611 if (DECL_SIZE (f) != 0
4612 && host_integerp (bit_position (f), 1))
4613 bitpos += int_bit_position (f);
4615 /* ??? FIXME: else assume zero offset. */
4617 if (TREE_CODE (ftype) == RECORD_TYPE)
4618 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4619 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4624 case SCmode: mode = SFmode; break;
4625 case DCmode: mode = DFmode; break;
4626 case TCmode: mode = TFmode; break;
4630 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4632 = gen_rtx_EXPR_LIST (VOIDmode,
4633 gen_rtx_REG (mode, cum->fregno++),
4634 GEN_INT (bitpos / BITS_PER_UNIT));
4638 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4640 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4642 = gen_rtx_EXPR_LIST (VOIDmode,
4643 gen_rtx_REG (mode, cum->vregno++),
4644 GEN_INT (bitpos / BITS_PER_UNIT));
4646 else if (cum->intoffset == -1)
4647 cum->intoffset = bitpos;
4651 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4652 the register(s) to be used for each field and subfield of a struct
4653 being passed by value, along with the offset of where the
4654 register's value may be found in the block. FP fields go in FP
4655 register, vector fields go in vector registers, and everything
4656 else goes in int registers, packed as in memory.
4658 This code is also used for function return values. RETVAL indicates
4659 whether this is the case.
4661 Much of this is taken from the Sparc V9 port, which has a similar
4662 calling convention. */
4665 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4666 int named, bool retval)
4668 rtx rvec[FIRST_PSEUDO_REGISTER];
4669 int k = 1, kbase = 1;
4670 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4671 /* This is a copy; modifications are not visible to our caller. */
4672 CUMULATIVE_ARGS copy_cum = *orig_cum;
4673 CUMULATIVE_ARGS *cum = ©_cum;
4675 /* Pad to 16 byte boundary if needed. */
4676 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4677 && (cum->words % 2) != 0)
4684 /* Put entries into rvec[] for individual FP and vector fields, and
4685 for the chunks of memory that go in int regs. Note we start at
4686 element 1; 0 is reserved for an indication of using memory, and
4687 may or may not be filled in below. */
4688 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4689 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4691 /* If any part of the struct went on the stack put all of it there.
4692 This hack is because the generic code for
4693 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4694 parts of the struct are not at the beginning. */
4698 return NULL_RTX; /* doesn't go in registers at all */
4700 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4702 if (k > 1 || cum->use_stack)
4703 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4708 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4711 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4715 rtx rvec[GP_ARG_NUM_REG + 1];
4717 if (align_words >= GP_ARG_NUM_REG)
4720 n_units = rs6000_arg_size (mode, type);
4722 /* Optimize the simple case where the arg fits in one gpr, except in
4723 the case of BLKmode due to assign_parms assuming that registers are
4724 BITS_PER_WORD wide. */
4726 || (n_units == 1 && mode != BLKmode))
4727 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4730 if (align_words + n_units > GP_ARG_NUM_REG)
4731 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4732 using a magic NULL_RTX component.
4733 FIXME: This is not strictly correct. Only some of the arg
4734 belongs in memory, not all of it. However, there isn't any way
4735 to do this currently, apart from building rtx descriptions for
4736 the pieces of memory we want stored. Due to bugs in the generic
4737 code we can't use the normal function_arg_partial_nregs scheme
4738 with the PARALLEL arg description we emit here.
4739 In any case, the code to store the whole arg to memory is often
4740 more efficient than code to store pieces, and we know that space
4741 is available in the right place for the whole arg. */
4742 /* FIXME: This should be fixed since the conversion to
4743 TARGET_ARG_PARTIAL_BYTES. */
4744 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4749 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4750 rtx off = GEN_INT (i++ * 4);
4751 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4753 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4755 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4758 /* Determine where to put an argument to a function.
4759 Value is zero to push the argument on the stack,
4760 or a hard register in which to store the argument.
4762 MODE is the argument's machine mode.
4763 TYPE is the data type of the argument (as a tree).
4764 This is null for libcalls where that information may
4766 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4767 the preceding args and about the function being called. It is
4768 not modified in this routine.
4769 NAMED is nonzero if this argument is a named parameter
4770 (otherwise it is an extra parameter matching an ellipsis).
4772 On RS/6000 the first eight words of non-FP are normally in registers
4773 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4774 Under V.4, the first 8 FP args are in registers.
4776 If this is floating-point and no prototype is specified, we use
4777 both an FP and integer register (or possibly FP reg and stack). Library
4778 functions (when CALL_LIBCALL is set) always have the proper types for args,
4779 so we can pass the FP value just in one register. emit_library_function
4780 doesn't support PARALLEL anyway.
4782 Note that for args passed by reference, function_arg will be called
4783 with MODE and TYPE set to that of the pointer to the arg, not the arg
4787 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4788 tree type, int named)
4790 enum rs6000_abi abi = DEFAULT_ABI;
4792 /* Return a marker to indicate whether CR1 needs to set or clear the
4793 bit that V.4 uses to say fp args were passed in registers.
4794 Assume that we don't need the marker for software floating point,
4795 or compiler generated library calls. */
4796 if (mode == VOIDmode)
4799 && cum->nargs_prototype < 0
4800 && (cum->call_cookie & CALL_LIBCALL) == 0
4801 && (cum->prototype || TARGET_NO_PROTOTYPE))
4803 /* For the SPE, we need to crxor CR6 always. */
4805 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4806 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4807 return GEN_INT (cum->call_cookie
4808 | ((cum->fregno == FP_ARG_MIN_REG)
4809 ? CALL_V4_SET_FP_ARGS
4810 : CALL_V4_CLEAR_FP_ARGS));
4813 return GEN_INT (cum->call_cookie);
4816 if (rs6000_darwin64_abi && mode == BLKmode
4817 && TREE_CODE (type) == RECORD_TYPE)
4819 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
4820 if (rslt != NULL_RTX)
4822 /* Else fall through to usual handling. */
4825 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4826 if (TARGET_64BIT && ! cum->prototype)
4828 /* Vector parameters get passed in vector register
4829 and also in GPRs or memory, in absence of prototype. */
4832 align_words = (cum->words + 1) & ~1;
4834 if (align_words >= GP_ARG_NUM_REG)
4840 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4842 return gen_rtx_PARALLEL (mode,
4844 gen_rtx_EXPR_LIST (VOIDmode,
4846 gen_rtx_EXPR_LIST (VOIDmode,
4847 gen_rtx_REG (mode, cum->vregno),
4851 return gen_rtx_REG (mode, cum->vregno);
4852 else if (TARGET_ALTIVEC_ABI
4853 && (ALTIVEC_VECTOR_MODE (mode)
4854 || (type && TREE_CODE (type) == VECTOR_TYPE
4855 && int_size_in_bytes (type) == 16)))
4857 if (named || abi == ABI_V4)
4861 /* Vector parameters to varargs functions under AIX or Darwin
4862 get passed in memory and possibly also in GPRs. */
4863 int align, align_words, n_words;
4864 enum machine_mode part_mode;
4866 /* Vector parameters must be 16-byte aligned. This places them at
4867 2 mod 4 in terms of words in 32-bit mode, since the parameter
4868 save area starts at offset 24 from the stack. In 64-bit mode,
4869 they just have to start on an even word, since the parameter
4870 save area is 16-byte aligned. */
4872 align = (2 - cum->words) & 3;
4874 align = cum->words & 1;
4875 align_words = cum->words + align;
4877 /* Out of registers? Memory, then. */
4878 if (align_words >= GP_ARG_NUM_REG)
4881 if (TARGET_32BIT && TARGET_POWERPC64)
4882 return rs6000_mixed_function_arg (mode, type, align_words);
4884 /* The vector value goes in GPRs. Only the part of the
4885 value in GPRs is reported here. */
4887 n_words = rs6000_arg_size (mode, type);
4888 if (align_words + n_words > GP_ARG_NUM_REG)
4889 /* Fortunately, there are only two possibilities, the value
4890 is either wholly in GPRs or half in GPRs and half not. */
4893 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4896 else if (TARGET_SPE_ABI && TARGET_SPE
4897 && (SPE_VECTOR_MODE (mode)
4898 || (TARGET_E500_DOUBLE && (mode == DFmode
4899 || mode == DCmode))))
4900 return rs6000_spe_function_arg (cum, mode, type);
4902 else if (abi == ABI_V4)
4904 if (TARGET_HARD_FLOAT && TARGET_FPRS
4905 && (mode == SFmode || mode == DFmode))
4907 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4908 return gen_rtx_REG (mode, cum->fregno);
4914 int n_words = rs6000_arg_size (mode, type);
4915 int gregno = cum->sysv_gregno;
4917 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4918 (r7,r8) or (r9,r10). As does any other 2 word item such
4919 as complex int due to a historical mistake. */
4921 gregno += (1 - gregno) & 1;
4923 /* Multi-reg args are not split between registers and stack. */
4924 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4927 if (TARGET_32BIT && TARGET_POWERPC64)
4928 return rs6000_mixed_function_arg (mode, type,
4929 gregno - GP_ARG_MIN_REG);
4930 return gen_rtx_REG (mode, gregno);
4935 int align_words = rs6000_parm_start (mode, type, cum->words);
4937 if (USE_FP_FOR_ARG_P (cum, mode, type))
4939 rtx rvec[GP_ARG_NUM_REG + 1];
4943 enum machine_mode fmode = mode;
4944 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4946 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4948 /* Currently, we only ever need one reg here because complex
4949 doubles are split. */
4950 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
4952 /* Long double split over regs and memory. */
4956 /* Do we also need to pass this arg in the parameter save
4959 && (cum->nargs_prototype <= 0
4960 || (DEFAULT_ABI == ABI_AIX
4962 && align_words >= GP_ARG_NUM_REG)));
4964 if (!needs_psave && mode == fmode)
4965 return gen_rtx_REG (fmode, cum->fregno);
4970 /* Describe the part that goes in gprs or the stack.
4971 This piece must come first, before the fprs. */
4972 if (align_words < GP_ARG_NUM_REG)
4974 unsigned long n_words = rs6000_arg_size (mode, type);
4976 if (align_words + n_words > GP_ARG_NUM_REG
4977 || (TARGET_32BIT && TARGET_POWERPC64))
4979 /* If this is partially on the stack, then we only
4980 include the portion actually in registers here. */
4981 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
4984 if (align_words + n_words > GP_ARG_NUM_REG
4985 && (TARGET_32BIT && TARGET_POWERPC64))
4986 /* Not all of the arg fits in gprs. Say that it
4987 goes in memory too, using a magic NULL_RTX
4988 component. Also see comment in
4989 rs6000_mixed_function_arg for why the normal
4990 function_arg_partial_nregs scheme doesn't work
4992 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
4996 r = gen_rtx_REG (rmode,
4997 GP_ARG_MIN_REG + align_words);
4998 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
4999 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5001 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5005 /* The whole arg fits in gprs. */
5006 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5007 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5011 /* It's entirely in memory. */
5012 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5015 /* Describe where this piece goes in the fprs. */
5016 r = gen_rtx_REG (fmode, cum->fregno);
5017 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5019 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5021 else if (align_words < GP_ARG_NUM_REG)
5023 if (TARGET_32BIT && TARGET_POWERPC64)
5024 return rs6000_mixed_function_arg (mode, type, align_words);
5026 if (mode == BLKmode)
5029 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5036 /* For an arg passed partly in registers and partly in memory, this is
5037 the number of bytes passed in registers. For args passed entirely in
5038 registers or entirely in memory, zero. When an arg is described by a
5039 PARALLEL, perhaps using more than one register type, this function
5040 returns the number of bytes used by the first element of the PARALLEL. */
5043 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5044 tree type, bool named)
5049 if (DEFAULT_ABI == ABI_V4)
5052 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5053 && cum->nargs_prototype >= 0)
5056 /* In this complicated case we just disable the partial_nregs code. */
5057 if (rs6000_darwin64_abi && mode == BLKmode
5058 && TREE_CODE (type) == RECORD_TYPE
5059 && int_size_in_bytes (type) > 0)
5062 align_words = rs6000_parm_start (mode, type, cum->words);
5064 if (USE_FP_FOR_ARG_P (cum, mode, type)
5065 /* If we are passing this arg in the fixed parameter save area
5066 (gprs or memory) as well as fprs, then this function should
5067 return the number of bytes passed in the parameter save area
5068 rather than bytes passed in fprs. */
5070 && (cum->nargs_prototype <= 0
5071 || (DEFAULT_ABI == ABI_AIX
5073 && align_words >= GP_ARG_NUM_REG))))
5075 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5076 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5077 else if (cum->nargs_prototype >= 0)
5081 if (align_words < GP_ARG_NUM_REG
5082 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5083 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5085 if (ret != 0 && TARGET_DEBUG_ARG)
5086 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5091 /* A C expression that indicates when an argument must be passed by
5092 reference. If nonzero for an argument, a copy of that argument is
5093 made in memory and a pointer to the argument is passed instead of
5094 the argument itself. The pointer is passed in whatever way is
5095 appropriate for passing a pointer to that type.
5097 Under V.4, aggregates and long double are passed by reference.
5099 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5100 reference unless the AltiVec vector extension ABI is in force.
5102 As an extension to all ABIs, variable sized types are passed by
5106 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5107 enum machine_mode mode, tree type,
5108 bool named ATTRIBUTE_UNUSED)
5110 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5112 if (TARGET_DEBUG_ARG)
5113 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5120 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5122 if (TARGET_DEBUG_ARG)
5123 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5127 if (int_size_in_bytes (type) < 0)
5129 if (TARGET_DEBUG_ARG)
5130 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5134 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5135 modes only exist for GCC vector types if -maltivec. */
5136 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5138 if (TARGET_DEBUG_ARG)
5139 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5143 /* Pass synthetic vectors in memory. */
5144 if (TREE_CODE (type) == VECTOR_TYPE
5145 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5147 static bool warned_for_pass_big_vectors = false;
5148 if (TARGET_DEBUG_ARG)
5149 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5150 if (!warned_for_pass_big_vectors)
5152 warning (0, "GCC vector passed by reference: "
5153 "non-standard ABI extension with no compatibility guarantee");
5154 warned_for_pass_big_vectors = true;
5163 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5166 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5171 for (i = 0; i < nregs; i++)
5173 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5174 if (reload_completed)
5176 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5179 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5180 i * GET_MODE_SIZE (reg_mode));
5183 tem = replace_equiv_address (tem, XEXP (tem, 0));
5187 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5191 /* Perform any needed actions needed for a function that is receiving a
5192 variable number of arguments.
5196 MODE and TYPE are the mode and type of the current parameter.
5198 PRETEND_SIZE is a variable that should be set to the amount of stack
5199 that must be pushed by the prolog to pretend that our caller pushed
5202 Normally, this macro will push all remaining incoming registers on the
5203 stack and set PRETEND_SIZE to the length of the registers pushed. */
5206 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5207 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5210 CUMULATIVE_ARGS next_cum;
5211 int reg_size = TARGET_32BIT ? 4 : 8;
5212 rtx save_area = NULL_RTX, mem;
5213 int first_reg_offset, set;
5215 /* Skip the last named argument. */
5217 function_arg_advance (&next_cum, mode, type, 1, 0);
5219 if (DEFAULT_ABI == ABI_V4)
5222 save_area = plus_constant (virtual_stack_vars_rtx,
5223 - RS6000_VARARGS_SIZE);
5225 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5229 first_reg_offset = next_cum.words;
5230 save_area = virtual_incoming_args_rtx;
5232 if (targetm.calls.must_pass_in_stack (mode, type))
5233 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5236 set = get_varargs_alias_set ();
5237 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5238 && cfun->va_list_gpr_size)
5240 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5242 if (va_list_gpr_counter_field)
5244 /* V4 va_list_gpr_size counts number of registers needed. */
5245 if (nregs > cfun->va_list_gpr_size)
5246 nregs = cfun->va_list_gpr_size;
5250 /* char * va_list instead counts number of bytes needed. */
5251 if (nregs > cfun->va_list_gpr_size / reg_size)
5252 nregs = cfun->va_list_gpr_size / reg_size;
5255 mem = gen_rtx_MEM (BLKmode,
5256 plus_constant (save_area,
5257 first_reg_offset * reg_size)),
5258 set_mem_alias_set (mem, set);
5259 set_mem_align (mem, BITS_PER_WORD);
5261 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5265 /* Save FP registers if needed. */
5266 if (DEFAULT_ABI == ABI_V4
5267 && TARGET_HARD_FLOAT && TARGET_FPRS
5269 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5270 && cfun->va_list_fpr_size)
5272 int fregno = next_cum.fregno, nregs;
5273 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5274 rtx lab = gen_label_rtx ();
5275 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5278 (gen_rtx_SET (VOIDmode,
5280 gen_rtx_IF_THEN_ELSE (VOIDmode,
5281 gen_rtx_NE (VOIDmode, cr1,
5283 gen_rtx_LABEL_REF (VOIDmode, lab),
5287 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5288 fregno++, off += 8, nregs++)
5290 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5291 set_mem_alias_set (mem, set);
5292 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5293 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5300 /* Create the va_list data type. */
5303 rs6000_build_builtin_va_list (void)
5305 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5307 /* For AIX, prefer 'char *' because that's what the system
5308 header files like. */
5309 if (DEFAULT_ABI != ABI_V4)
5310 return build_pointer_type (char_type_node);
5312 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5313 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5315 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5316 unsigned_char_type_node);
5317 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5318 unsigned_char_type_node);
5319 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5321 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5322 short_unsigned_type_node);
5323 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5325 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5328 va_list_gpr_counter_field = f_gpr;
5329 va_list_fpr_counter_field = f_fpr;
5331 DECL_FIELD_CONTEXT (f_gpr) = record;
5332 DECL_FIELD_CONTEXT (f_fpr) = record;
5333 DECL_FIELD_CONTEXT (f_res) = record;
5334 DECL_FIELD_CONTEXT (f_ovf) = record;
5335 DECL_FIELD_CONTEXT (f_sav) = record;
5337 TREE_CHAIN (record) = type_decl;
5338 TYPE_NAME (record) = type_decl;
5339 TYPE_FIELDS (record) = f_gpr;
5340 TREE_CHAIN (f_gpr) = f_fpr;
5341 TREE_CHAIN (f_fpr) = f_res;
5342 TREE_CHAIN (f_res) = f_ovf;
5343 TREE_CHAIN (f_ovf) = f_sav;
5345 layout_type (record);
5347 /* The correct type is an array type of one element. */
5348 return build_array_type (record, build_index_type (size_zero_node));
5351 /* Implement va_start. */
5354 rs6000_va_start (tree valist, rtx nextarg)
5356 HOST_WIDE_INT words, n_gpr, n_fpr;
5357 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5358 tree gpr, fpr, ovf, sav, t;
5360 /* Only SVR4 needs something special. */
5361 if (DEFAULT_ABI != ABI_V4)
5363 std_expand_builtin_va_start (valist, nextarg);
5367 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5368 f_fpr = TREE_CHAIN (f_gpr);
5369 f_res = TREE_CHAIN (f_fpr);
5370 f_ovf = TREE_CHAIN (f_res);
5371 f_sav = TREE_CHAIN (f_ovf);
5373 valist = build_va_arg_indirect_ref (valist);
5374 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5375 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5376 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5377 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5379 /* Count number of gp and fp argument registers used. */
5380 words = current_function_args_info.words;
5381 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5383 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5386 if (TARGET_DEBUG_ARG)
5387 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5388 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5389 words, n_gpr, n_fpr);
5391 if (cfun->va_list_gpr_size)
5393 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5394 build_int_cst (NULL_TREE, n_gpr));
5395 TREE_SIDE_EFFECTS (t) = 1;
5396 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5399 if (cfun->va_list_fpr_size)
5401 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5402 build_int_cst (NULL_TREE, n_fpr));
5403 TREE_SIDE_EFFECTS (t) = 1;
5404 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5407 /* Find the overflow area. */
5408 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5410 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5411 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5412 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5413 TREE_SIDE_EFFECTS (t) = 1;
5414 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5416 /* If there were no va_arg invocations, don't set up the register
5418 if (!cfun->va_list_gpr_size
5419 && !cfun->va_list_fpr_size
5420 && n_gpr < GP_ARG_NUM_REG
5421 && n_fpr < FP_ARG_V4_MAX_REG)
5424 /* Find the register save area. */
5425 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5426 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5427 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
5428 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5429 TREE_SIDE_EFFECTS (t) = 1;
5430 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5433 /* Implement va_arg. */
5436 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5438 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5439 tree gpr, fpr, ovf, sav, reg, t, u;
5440 int size, rsize, n_reg, sav_ofs, sav_scale;
5441 tree lab_false, lab_over, addr;
5443 tree ptrtype = build_pointer_type (type);
5445 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5447 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5448 return build_va_arg_indirect_ref (t);
5451 if (DEFAULT_ABI != ABI_V4)
5453 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5455 tree elem_type = TREE_TYPE (type);
5456 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5457 int elem_size = GET_MODE_SIZE (elem_mode);
5459 if (elem_size < UNITS_PER_WORD)
5461 tree real_part, imag_part;
5462 tree post = NULL_TREE;
5464 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5466 /* Copy the value into a temporary, lest the formal temporary
5467 be reused out from under us. */
5468 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5469 append_to_statement_list (post, pre_p);
5471 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5474 return build (COMPLEX_EXPR, type, real_part, imag_part);
5478 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5481 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5482 f_fpr = TREE_CHAIN (f_gpr);
5483 f_res = TREE_CHAIN (f_fpr);
5484 f_ovf = TREE_CHAIN (f_res);
5485 f_sav = TREE_CHAIN (f_ovf);
5487 valist = build_va_arg_indirect_ref (valist);
5488 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5489 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5490 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5491 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5493 size = int_size_in_bytes (type);
5494 rsize = (size + 3) / 4;
5497 if (TARGET_HARD_FLOAT && TARGET_FPRS
5498 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5500 /* FP args go in FP registers, if present. */
5505 if (TYPE_MODE (type) == DFmode)
5510 /* Otherwise into GP registers. */
5519 /* Pull the value out of the saved registers.... */
5522 addr = create_tmp_var (ptr_type_node, "addr");
5523 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5525 /* AltiVec vectors never go in registers when -mabi=altivec. */
5526 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5530 lab_false = create_artificial_label ();
5531 lab_over = create_artificial_label ();
5533 /* Long long and SPE vectors are aligned in the registers.
5534 As are any other 2 gpr item such as complex int due to a
5535 historical mistake. */
5539 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5540 size_int (n_reg - 1));
5541 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5544 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5545 t = build2 (GE_EXPR, boolean_type_node, u, t);
5546 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5547 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5548 gimplify_and_add (t, pre_p);
5552 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5554 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5555 u = build1 (CONVERT_EXPR, integer_type_node, u);
5556 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5557 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5559 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5560 gimplify_and_add (t, pre_p);
5562 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5563 gimplify_and_add (t, pre_p);
5565 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5566 append_to_statement_list (t, pre_p);
5570 /* Ensure that we don't find any more args in regs.
5571 Alignment has taken care of the n_reg == 2 case. */
5572 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5573 gimplify_and_add (t, pre_p);
5577 /* ... otherwise out of the overflow area. */
5579 /* Care for on-stack alignment if needed. */
5583 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5584 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5585 build_int_cst (NULL_TREE, -align));
5587 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5589 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5590 gimplify_and_add (u, pre_p);
5592 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5593 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5594 gimplify_and_add (t, pre_p);
5598 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5599 append_to_statement_list (t, pre_p);
5602 addr = fold_convert (ptrtype, addr);
5603 return build_va_arg_indirect_ref (addr);
5609 def_builtin (int mask, const char *name, tree type, int code)
5611 if (mask & target_flags)
5613 if (rs6000_builtin_decls[code])
5616 rs6000_builtin_decls[code] =
5617 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
5622 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5624 static const struct builtin_description bdesc_3arg[] =
5626 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5627 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5628 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5629 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5630 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5631 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5632 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5633 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5634 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5635 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5636 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5637 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5638 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5639 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5640 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5641 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5642 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5643 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5644 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5645 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5646 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5647 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5648 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5650 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
5651 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
5652 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
5653 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
5654 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
5655 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
5656 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
5657 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
5658 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
5659 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
5660 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
5661 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
5662 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
5663 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
5664 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
5667 /* DST operations: void foo (void *, const int, const char). */
5669 static const struct builtin_description bdesc_dst[] =
5671 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5672 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5673 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5674 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
5676 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
5677 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
5678 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
5679 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
5682 /* Simple binary operations: VECc = foo (VECa, VECb). */
5684 static struct builtin_description bdesc_2arg[] =
5686 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5687 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5688 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5689 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5690 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5691 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5692 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5693 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5694 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5695 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5696 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5697 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5698 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5699 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5700 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5701 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5702 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5703 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5704 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5705 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5706 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5707 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5708 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5709 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5710 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5711 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5712 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5713 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5714 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5715 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5716 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5717 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5718 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5719 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5720 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5721 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5722 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5723 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5724 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5725 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5726 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5727 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5728 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5729 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5730 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5731 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5732 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5733 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5734 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5735 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5736 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5737 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5738 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5739 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5740 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5741 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5742 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5743 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5744 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5745 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5746 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5747 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5748 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5749 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5750 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5751 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5752 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5753 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5754 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5755 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5756 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5757 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5758 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5759 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5760 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5761 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5762 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5763 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5764 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5765 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5766 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5767 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5768 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5769 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5770 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5771 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5772 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5773 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5774 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5775 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5776 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5777 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5778 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5779 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5780 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5781 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5782 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5783 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5784 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5785 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5786 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5787 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5788 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5789 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5790 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5791 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5792 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5793 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5794 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5795 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5796 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5797 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5798 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5800 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
5801 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
5802 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
5803 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
5804 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
5805 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
5806 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
5807 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
5808 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
5809 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
5810 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
5811 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
5812 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
5813 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
5814 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
5815 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
5816 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
5817 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
5818 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
5819 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
5820 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
5821 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
5822 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
5823 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
5824 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
5825 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
5826 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
5827 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
5828 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
5829 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
5830 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
5831 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
5832 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
5833 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
5834 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
5835 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
5836 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
5837 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
5838 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
5839 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
5840 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
5841 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
5842 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
5843 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
5844 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
5845 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
5846 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
5847 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
5848 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
5849 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
5850 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
5851 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
5852 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
5853 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
5854 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
5855 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
5856 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
5857 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
5858 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
5859 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
5860 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
5861 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
5862 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
5863 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
5864 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
5865 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
5866 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
5867 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
5868 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
5869 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
5870 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
5871 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
5872 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
5873 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
5874 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
5875 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
5876 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
5877 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
5878 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
5879 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
5880 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
5881 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
5882 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
5883 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
5884 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
5885 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
5886 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
5887 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
5888 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
5889 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
5890 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
5891 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
5892 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
5893 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
5894 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
5895 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
5896 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
5897 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
5898 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
5899 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
5900 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
5901 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
5902 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
5903 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
5904 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
5905 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
5906 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
5907 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
5908 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
5909 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
5910 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
5911 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
5912 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
5913 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
5914 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
5915 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
5916 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
5917 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
5918 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
5919 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
5920 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
5921 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
5922 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
5923 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
5924 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
5925 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
5926 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
5928 /* Place holder, leave as first spe builtin. */
5929 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5930 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5931 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5932 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5933 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5934 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5935 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5936 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5937 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5938 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5939 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5940 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5941 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5942 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5943 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5944 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5945 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5946 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5947 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5948 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5949 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5950 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5951 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5952 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5953 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5954 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5955 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5956 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5957 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5958 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5959 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5960 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5961 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5962 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5963 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5964 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5965 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5966 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5967 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5968 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5969 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5970 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5971 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5972 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5973 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5974 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5975 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5976 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5977 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5978 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5979 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5980 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5981 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5982 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5983 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5984 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5985 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5986 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5987 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5988 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5989 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5990 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5991 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5992 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5993 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5994 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5995 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5996 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5997 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5998 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5999 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6000 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6001 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6002 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6003 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6004 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6005 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6006 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6007 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6008 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6009 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6010 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6011 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6012 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6013 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6014 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6015 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6016 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6017 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6018 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6019 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6020 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6021 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6022 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6023 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6024 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6025 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6026 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6027 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6028 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6029 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6030 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6031 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6032 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6033 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6034 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6035 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6036 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6037 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6039 /* SPE binary operations expecting a 5-bit unsigned literal. */
6040 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6042 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6043 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6044 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6045 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6046 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6047 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6048 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6049 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6050 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6051 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6052 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6053 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6054 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6055 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6056 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6057 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6058 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6059 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6060 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6061 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6062 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6063 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6064 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6065 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6066 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6067 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6069 /* Place-holder. Leave as last binary SPE builtin. */
6070 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6073 /* AltiVec predicates. */
6075 struct builtin_description_predicates
6077 const unsigned int mask;
6078 const enum insn_code icode;
6080 const char *const name;
6081 const enum rs6000_builtins code;
6084 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6086 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6087 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6088 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6089 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6090 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6091 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6092 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6093 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6094 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6095 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6096 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6097 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6098 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6100 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6101 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6102 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6105 /* SPE predicates. */
6106 static struct builtin_description bdesc_spe_predicates[] =
6108 /* Place-holder. Leave as first. */
6109 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6110 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6111 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6112 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6113 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6114 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6115 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6116 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6117 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6118 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6119 /* Place-holder. Leave as last. */
6120 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6123 /* SPE evsel predicates. */
6124 static struct builtin_description bdesc_spe_evsel[] =
6126 /* Place-holder. Leave as first. */
6127 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6128 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6129 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6130 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6131 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6132 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6133 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6134 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6135 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6136 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6137 /* Place-holder. Leave as last. */
6138 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6141 /* ABS* operations. */
6143 static const struct builtin_description bdesc_abs[] =
6145 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6146 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6147 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6148 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6149 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6150 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6151 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6154 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6157 static struct builtin_description bdesc_1arg[] =
6159 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6160 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6161 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6162 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6163 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6164 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6165 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6166 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6167 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6168 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6169 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6170 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6171 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6172 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6173 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6174 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6175 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6177 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6178 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6179 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6180 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6181 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6182 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6183 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6184 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6185 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6186 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6187 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6188 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6189 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6190 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6191 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6192 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6197 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6198 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6199 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6200 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6201 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6202 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6203 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6204 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6205 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6206 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6207 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6208 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6209 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6210 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6211 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6212 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6213 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6214 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6215 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6216 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6217 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6218 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6219 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6220 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6221 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6222 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6223 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6224 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6225 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6226 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6228 /* Place-holder. Leave as last unary SPE builtin. */
6229 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6233 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6236 tree arg0 = TREE_VALUE (arglist);
6237 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6238 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6239 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6241 if (icode == CODE_FOR_nothing)
6242 /* Builtin not supported on this processor. */
6245 /* If we got invalid arguments bail out before generating bad rtl. */
6246 if (arg0 == error_mark_node)
6249 if (icode == CODE_FOR_altivec_vspltisb
6250 || icode == CODE_FOR_altivec_vspltish
6251 || icode == CODE_FOR_altivec_vspltisw
6252 || icode == CODE_FOR_spe_evsplatfi
6253 || icode == CODE_FOR_spe_evsplati)
6255 /* Only allow 5-bit *signed* literals. */
6256 if (GET_CODE (op0) != CONST_INT
6257 || INTVAL (op0) > 15
6258 || INTVAL (op0) < -16)
6260 error ("argument 1 must be a 5-bit signed literal");
6266 || GET_MODE (target) != tmode
6267 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6268 target = gen_reg_rtx (tmode);
6270 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6271 op0 = copy_to_mode_reg (mode0, op0);
6273 pat = GEN_FCN (icode) (target, op0);
6282 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6284 rtx pat, scratch1, scratch2;
6285 tree arg0 = TREE_VALUE (arglist);
6286 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6287 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6288 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6290 /* If we have invalid arguments, bail out before generating bad rtl. */
6291 if (arg0 == error_mark_node)
6295 || GET_MODE (target) != tmode
6296 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6297 target = gen_reg_rtx (tmode);
6299 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6300 op0 = copy_to_mode_reg (mode0, op0);
6302 scratch1 = gen_reg_rtx (mode0);
6303 scratch2 = gen_reg_rtx (mode0);
6305 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6314 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6317 tree arg0 = TREE_VALUE (arglist);
6318 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6319 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6320 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6321 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6322 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6323 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6325 if (icode == CODE_FOR_nothing)
6326 /* Builtin not supported on this processor. */
6329 /* If we got invalid arguments bail out before generating bad rtl. */
6330 if (arg0 == error_mark_node || arg1 == error_mark_node)
6333 if (icode == CODE_FOR_altivec_vcfux
6334 || icode == CODE_FOR_altivec_vcfsx
6335 || icode == CODE_FOR_altivec_vctsxs
6336 || icode == CODE_FOR_altivec_vctuxs
6337 || icode == CODE_FOR_altivec_vspltb
6338 || icode == CODE_FOR_altivec_vsplth
6339 || icode == CODE_FOR_altivec_vspltw
6340 || icode == CODE_FOR_spe_evaddiw
6341 || icode == CODE_FOR_spe_evldd
6342 || icode == CODE_FOR_spe_evldh
6343 || icode == CODE_FOR_spe_evldw
6344 || icode == CODE_FOR_spe_evlhhesplat
6345 || icode == CODE_FOR_spe_evlhhossplat
6346 || icode == CODE_FOR_spe_evlhhousplat
6347 || icode == CODE_FOR_spe_evlwhe
6348 || icode == CODE_FOR_spe_evlwhos
6349 || icode == CODE_FOR_spe_evlwhou
6350 || icode == CODE_FOR_spe_evlwhsplat
6351 || icode == CODE_FOR_spe_evlwwsplat
6352 || icode == CODE_FOR_spe_evrlwi
6353 || icode == CODE_FOR_spe_evslwi
6354 || icode == CODE_FOR_spe_evsrwis
6355 || icode == CODE_FOR_spe_evsubifw
6356 || icode == CODE_FOR_spe_evsrwiu)
6358 /* Only allow 5-bit unsigned literals. */
6360 if (TREE_CODE (arg1) != INTEGER_CST
6361 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6363 error ("argument 2 must be a 5-bit unsigned literal");
6369 || GET_MODE (target) != tmode
6370 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6371 target = gen_reg_rtx (tmode);
6373 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6374 op0 = copy_to_mode_reg (mode0, op0);
6375 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6376 op1 = copy_to_mode_reg (mode1, op1);
6378 pat = GEN_FCN (icode) (target, op0, op1);
6387 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6388 tree arglist, rtx target)
6391 tree cr6_form = TREE_VALUE (arglist);
6392 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6393 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6394 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6395 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6396 enum machine_mode tmode = SImode;
6397 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6398 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6401 if (TREE_CODE (cr6_form) != INTEGER_CST)
6403 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6407 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6409 gcc_assert (mode0 == mode1);
6411 /* If we have invalid arguments, bail out before generating bad rtl. */
6412 if (arg0 == error_mark_node || arg1 == error_mark_node)
6416 || GET_MODE (target) != tmode
6417 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6418 target = gen_reg_rtx (tmode);
6420 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6421 op0 = copy_to_mode_reg (mode0, op0);
6422 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6423 op1 = copy_to_mode_reg (mode1, op1);
6425 scratch = gen_reg_rtx (mode0);
6427 pat = GEN_FCN (icode) (scratch, op0, op1,
6428 gen_rtx_SYMBOL_REF (Pmode, opcode));
6433 /* The vec_any* and vec_all* predicates use the same opcodes for two
6434 different operations, but the bits in CR6 will be different
6435 depending on what information we want. So we have to play tricks
6436 with CR6 to get the right bits out.
6438 If you think this is disgusting, look at the specs for the
6439 AltiVec predicates. */
6441 switch (cr6_form_int)
6444 emit_insn (gen_cr6_test_for_zero (target));
6447 emit_insn (gen_cr6_test_for_zero_reverse (target));
6450 emit_insn (gen_cr6_test_for_lt (target));
6453 emit_insn (gen_cr6_test_for_lt_reverse (target));
6456 error ("argument 1 of __builtin_altivec_predicate is out of range");
6464 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6467 tree arg0 = TREE_VALUE (arglist);
6468 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6469 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6470 enum machine_mode mode0 = Pmode;
6471 enum machine_mode mode1 = Pmode;
6472 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6473 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6475 if (icode == CODE_FOR_nothing)
6476 /* Builtin not supported on this processor. */
6479 /* If we got invalid arguments bail out before generating bad rtl. */
6480 if (arg0 == error_mark_node || arg1 == error_mark_node)
6484 || GET_MODE (target) != tmode
6485 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6486 target = gen_reg_rtx (tmode);
6488 op1 = copy_to_mode_reg (mode1, op1);
6490 if (op0 == const0_rtx)
6492 addr = gen_rtx_MEM (tmode, op1);
6496 op0 = copy_to_mode_reg (mode0, op0);
6497 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6500 pat = GEN_FCN (icode) (target, addr);
6510 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6512 tree arg0 = TREE_VALUE (arglist);
6513 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6514 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6515 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6516 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6517 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6519 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6520 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6521 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6523 /* Invalid arguments. Bail before doing anything stoopid! */
6524 if (arg0 == error_mark_node
6525 || arg1 == error_mark_node
6526 || arg2 == error_mark_node)
6529 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6530 op0 = copy_to_mode_reg (mode2, op0);
6531 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6532 op1 = copy_to_mode_reg (mode0, op1);
6533 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6534 op2 = copy_to_mode_reg (mode1, op2);
6536 pat = GEN_FCN (icode) (op1, op2, op0);
6543 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6545 tree arg0 = TREE_VALUE (arglist);
6546 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6547 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6548 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6549 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6550 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6552 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6553 enum machine_mode mode1 = Pmode;
6554 enum machine_mode mode2 = Pmode;
6556 /* Invalid arguments. Bail before doing anything stoopid! */
6557 if (arg0 == error_mark_node
6558 || arg1 == error_mark_node
6559 || arg2 == error_mark_node)
6562 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6563 op0 = copy_to_mode_reg (tmode, op0);
6565 op2 = copy_to_mode_reg (mode2, op2);
6567 if (op1 == const0_rtx)
6569 addr = gen_rtx_MEM (tmode, op2);
6573 op1 = copy_to_mode_reg (mode1, op1);
6574 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6577 pat = GEN_FCN (icode) (addr, op0);
6584 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6587 tree arg0 = TREE_VALUE (arglist);
6588 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6589 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6590 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6591 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6592 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6593 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6594 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6595 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6596 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6598 if (icode == CODE_FOR_nothing)
6599 /* Builtin not supported on this processor. */
6602 /* If we got invalid arguments bail out before generating bad rtl. */
6603 if (arg0 == error_mark_node
6604 || arg1 == error_mark_node
6605 || arg2 == error_mark_node)
6608 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6609 || icode == CODE_FOR_altivec_vsldoi_v4si
6610 || icode == CODE_FOR_altivec_vsldoi_v8hi
6611 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6613 /* Only allow 4-bit unsigned literals. */
6615 if (TREE_CODE (arg2) != INTEGER_CST
6616 || TREE_INT_CST_LOW (arg2) & ~0xf)
6618 error ("argument 3 must be a 4-bit unsigned literal");
6624 || GET_MODE (target) != tmode
6625 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6626 target = gen_reg_rtx (tmode);
6628 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6629 op0 = copy_to_mode_reg (mode0, op0);
6630 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6631 op1 = copy_to_mode_reg (mode1, op1);
6632 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6633 op2 = copy_to_mode_reg (mode2, op2);
6635 pat = GEN_FCN (icode) (target, op0, op1, op2);
6643 /* Expand the lvx builtins. */
6645 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6647 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6648 tree arglist = TREE_OPERAND (exp, 1);
6649 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6651 enum machine_mode tmode, mode0;
6653 enum insn_code icode;
6657 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6658 icode = CODE_FOR_altivec_lvx_v16qi;
6660 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6661 icode = CODE_FOR_altivec_lvx_v8hi;
6663 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6664 icode = CODE_FOR_altivec_lvx_v4si;
6666 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6667 icode = CODE_FOR_altivec_lvx_v4sf;
6676 arg0 = TREE_VALUE (arglist);
6677 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6678 tmode = insn_data[icode].operand[0].mode;
6679 mode0 = insn_data[icode].operand[1].mode;
6682 || GET_MODE (target) != tmode
6683 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6684 target = gen_reg_rtx (tmode);
6686 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6687 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6689 pat = GEN_FCN (icode) (target, op0);
6696 /* Expand the stvx builtins. */
6698 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6701 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6702 tree arglist = TREE_OPERAND (exp, 1);
6703 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6705 enum machine_mode mode0, mode1;
6707 enum insn_code icode;
6711 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6712 icode = CODE_FOR_altivec_stvx_v16qi;
6714 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6715 icode = CODE_FOR_altivec_stvx_v8hi;
6717 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6718 icode = CODE_FOR_altivec_stvx_v4si;
6720 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6721 icode = CODE_FOR_altivec_stvx_v4sf;
6728 arg0 = TREE_VALUE (arglist);
6729 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6730 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6731 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6732 mode0 = insn_data[icode].operand[0].mode;
6733 mode1 = insn_data[icode].operand[1].mode;
6735 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6736 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6737 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6738 op1 = copy_to_mode_reg (mode1, op1);
6740 pat = GEN_FCN (icode) (op0, op1);
6748 /* Expand the dst builtins. */
6750 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6753 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6754 tree arglist = TREE_OPERAND (exp, 1);
6755 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6756 tree arg0, arg1, arg2;
6757 enum machine_mode mode0, mode1, mode2;
6758 rtx pat, op0, op1, op2;
6759 struct builtin_description *d;
6764 /* Handle DST variants. */
6765 d = (struct builtin_description *) bdesc_dst;
6766 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6767 if (d->code == fcode)
6769 arg0 = TREE_VALUE (arglist);
6770 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6771 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6772 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6773 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6774 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6775 mode0 = insn_data[d->icode].operand[0].mode;
6776 mode1 = insn_data[d->icode].operand[1].mode;
6777 mode2 = insn_data[d->icode].operand[2].mode;
6779 /* Invalid arguments, bail out before generating bad rtl. */
6780 if (arg0 == error_mark_node
6781 || arg1 == error_mark_node
6782 || arg2 == error_mark_node)
6787 if (TREE_CODE (arg2) != INTEGER_CST
6788 || TREE_INT_CST_LOW (arg2) & ~0x3)
6790 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
6794 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
6795 op0 = copy_to_mode_reg (Pmode, op0);
6796 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6797 op1 = copy_to_mode_reg (mode1, op1);
6799 pat = GEN_FCN (d->icode) (op0, op1, op2);
6809 /* Expand the builtin in EXP and store the result in TARGET. Store
6810 true in *EXPANDEDP if we found a builtin to expand. */
6812 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
6814 struct builtin_description *d;
6815 struct builtin_description_predicates *dp;
6817 enum insn_code icode;
6818 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6819 tree arglist = TREE_OPERAND (exp, 1);
6822 enum machine_mode tmode, mode0;
6823 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6825 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
6826 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
6829 error ("unresolved overload for Altivec builtin %qE", fndecl);
6833 target = altivec_expand_ld_builtin (exp, target, expandedp);
6837 target = altivec_expand_st_builtin (exp, target, expandedp);
6841 target = altivec_expand_dst_builtin (exp, target, expandedp);
6849 case ALTIVEC_BUILTIN_STVX:
6850 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6851 case ALTIVEC_BUILTIN_STVEBX:
6852 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6853 case ALTIVEC_BUILTIN_STVEHX:
6854 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6855 case ALTIVEC_BUILTIN_STVEWX:
6856 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6857 case ALTIVEC_BUILTIN_STVXL:
6858 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
6860 case ALTIVEC_BUILTIN_MFVSCR:
6861 icode = CODE_FOR_altivec_mfvscr;
6862 tmode = insn_data[icode].operand[0].mode;
6865 || GET_MODE (target) != tmode
6866 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6867 target = gen_reg_rtx (tmode);
6869 pat = GEN_FCN (icode) (target);
6875 case ALTIVEC_BUILTIN_MTVSCR:
6876 icode = CODE_FOR_altivec_mtvscr;
6877 arg0 = TREE_VALUE (arglist);
6878 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6879 mode0 = insn_data[icode].operand[0].mode;
6881 /* If we got invalid arguments bail out before generating bad rtl. */
6882 if (arg0 == error_mark_node)
6885 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6886 op0 = copy_to_mode_reg (mode0, op0);
6888 pat = GEN_FCN (icode) (op0);
6893 case ALTIVEC_BUILTIN_DSSALL:
6894 emit_insn (gen_altivec_dssall ());
6897 case ALTIVEC_BUILTIN_DSS:
6898 icode = CODE_FOR_altivec_dss;
6899 arg0 = TREE_VALUE (arglist);
6901 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6902 mode0 = insn_data[icode].operand[0].mode;
6904 /* If we got invalid arguments bail out before generating bad rtl. */
6905 if (arg0 == error_mark_node)
6908 if (TREE_CODE (arg0) != INTEGER_CST
6909 || TREE_INT_CST_LOW (arg0) & ~0x3)
6911 error ("argument to dss must be a 2-bit unsigned literal");
6915 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6916 op0 = copy_to_mode_reg (mode0, op0);
6918 emit_insn (gen_altivec_dss (op0));
6922 /* Expand abs* operations. */
6923 d = (struct builtin_description *) bdesc_abs;
6924 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6925 if (d->code == fcode)
6926 return altivec_expand_abs_builtin (d->icode, arglist, target);
6928 /* Expand the AltiVec predicates. */
6929 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6930 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6931 if (dp->code == fcode)
6932 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6935 /* LV* are funky. We initialized them differently. */
6938 case ALTIVEC_BUILTIN_LVSL:
6939 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
6941 case ALTIVEC_BUILTIN_LVSR:
6942 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
6944 case ALTIVEC_BUILTIN_LVEBX:
6945 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
6947 case ALTIVEC_BUILTIN_LVEHX:
6948 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
6950 case ALTIVEC_BUILTIN_LVEWX:
6951 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
6953 case ALTIVEC_BUILTIN_LVXL:
6954 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
6956 case ALTIVEC_BUILTIN_LVX:
6957 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
6968 /* Binops that need to be initialized manually, but can be expanded
6969 automagically by rs6000_expand_binop_builtin. */
6970 static struct builtin_description bdesc_2arg_spe[] =
6972 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6973 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6974 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6975 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6976 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6977 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6978 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6979 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6980 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6981 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6982 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6983 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6984 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6985 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6986 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6987 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6988 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6989 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6990 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6991 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6992 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6993 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6996 /* Expand the builtin in EXP and store the result in TARGET. Store
6997 true in *EXPANDEDP if we found a builtin to expand.
6999 This expands the SPE builtins that are not simple unary and binary
7002 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7004 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7005 tree arglist = TREE_OPERAND (exp, 1);
7007 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7008 enum insn_code icode;
7009 enum machine_mode tmode, mode0;
7011 struct builtin_description *d;
7016 /* Syntax check for a 5-bit unsigned immediate. */
7019 case SPE_BUILTIN_EVSTDD:
7020 case SPE_BUILTIN_EVSTDH:
7021 case SPE_BUILTIN_EVSTDW:
7022 case SPE_BUILTIN_EVSTWHE:
7023 case SPE_BUILTIN_EVSTWHO:
7024 case SPE_BUILTIN_EVSTWWE:
7025 case SPE_BUILTIN_EVSTWWO:
7026 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7027 if (TREE_CODE (arg1) != INTEGER_CST
7028 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7030 error ("argument 2 must be a 5-bit unsigned literal");
7038 /* The evsplat*i instructions are not quite generic. */
7041 case SPE_BUILTIN_EVSPLATFI:
7042 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7044 case SPE_BUILTIN_EVSPLATI:
7045 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7051 d = (struct builtin_description *) bdesc_2arg_spe;
7052 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7053 if (d->code == fcode)
7054 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7056 d = (struct builtin_description *) bdesc_spe_predicates;
7057 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7058 if (d->code == fcode)
7059 return spe_expand_predicate_builtin (d->icode, arglist, target);
7061 d = (struct builtin_description *) bdesc_spe_evsel;
7062 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7063 if (d->code == fcode)
7064 return spe_expand_evsel_builtin (d->icode, arglist, target);
7068 case SPE_BUILTIN_EVSTDDX:
7069 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7070 case SPE_BUILTIN_EVSTDHX:
7071 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7072 case SPE_BUILTIN_EVSTDWX:
7073 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7074 case SPE_BUILTIN_EVSTWHEX:
7075 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7076 case SPE_BUILTIN_EVSTWHOX:
7077 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7078 case SPE_BUILTIN_EVSTWWEX:
7079 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7080 case SPE_BUILTIN_EVSTWWOX:
7081 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7082 case SPE_BUILTIN_EVSTDD:
7083 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7084 case SPE_BUILTIN_EVSTDH:
7085 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7086 case SPE_BUILTIN_EVSTDW:
7087 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7088 case SPE_BUILTIN_EVSTWHE:
7089 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7090 case SPE_BUILTIN_EVSTWHO:
7091 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7092 case SPE_BUILTIN_EVSTWWE:
7093 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7094 case SPE_BUILTIN_EVSTWWO:
7095 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7096 case SPE_BUILTIN_MFSPEFSCR:
7097 icode = CODE_FOR_spe_mfspefscr;
7098 tmode = insn_data[icode].operand[0].mode;
7101 || GET_MODE (target) != tmode
7102 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7103 target = gen_reg_rtx (tmode);
7105 pat = GEN_FCN (icode) (target);
7110 case SPE_BUILTIN_MTSPEFSCR:
7111 icode = CODE_FOR_spe_mtspefscr;
7112 arg0 = TREE_VALUE (arglist);
7113 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7114 mode0 = insn_data[icode].operand[0].mode;
7116 if (arg0 == error_mark_node)
7119 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7120 op0 = copy_to_mode_reg (mode0, op0);
7122 pat = GEN_FCN (icode) (op0);
7135 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7137 rtx pat, scratch, tmp;
7138 tree form = TREE_VALUE (arglist);
7139 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7140 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7141 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7142 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7143 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7144 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7148 if (TREE_CODE (form) != INTEGER_CST)
7150 error ("argument 1 of __builtin_spe_predicate must be a constant");
7154 form_int = TREE_INT_CST_LOW (form);
7156 gcc_assert (mode0 == mode1);
7158 if (arg0 == error_mark_node || arg1 == error_mark_node)
7162 || GET_MODE (target) != SImode
7163 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7164 target = gen_reg_rtx (SImode);
7166 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7167 op0 = copy_to_mode_reg (mode0, op0);
7168 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7169 op1 = copy_to_mode_reg (mode1, op1);
7171 scratch = gen_reg_rtx (CCmode);
7173 pat = GEN_FCN (icode) (scratch, op0, op1);
7178 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7179 _lower_. We use one compare, but look in different bits of the
7180 CR for each variant.
7182 There are 2 elements in each SPE simd type (upper/lower). The CR
7183 bits are set as follows:
7185 BIT0 | BIT 1 | BIT 2 | BIT 3
7186 U | L | (U | L) | (U & L)
7188 So, for an "all" relationship, BIT 3 would be set.
7189 For an "any" relationship, BIT 2 would be set. Etc.
7191 Following traditional nomenclature, these bits map to:
7193 BIT0 | BIT 1 | BIT 2 | BIT 3
7196 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7201 /* All variant. OV bit. */
7203 /* We need to get to the OV bit, which is the ORDERED bit. We
7204 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7205 that's ugly and will make validate_condition_mode die.
7206 So let's just use another pattern. */
7207 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7209 /* Any variant. EQ bit. */
7213 /* Upper variant. LT bit. */
7217 /* Lower variant. GT bit. */
7222 error ("argument 1 of __builtin_spe_predicate is out of range");
7226 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7227 emit_move_insn (target, tmp);
7232 /* The evsel builtins look like this:
7234 e = __builtin_spe_evsel_OP (a, b, c, d);
7238 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7239 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7243 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7246 tree arg0 = TREE_VALUE (arglist);
7247 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7248 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7249 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7250 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7251 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7252 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7253 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7254 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7255 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7257 gcc_assert (mode0 == mode1);
7259 if (arg0 == error_mark_node || arg1 == error_mark_node
7260 || arg2 == error_mark_node || arg3 == error_mark_node)
7264 || GET_MODE (target) != mode0
7265 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7266 target = gen_reg_rtx (mode0);
7268 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7269 op0 = copy_to_mode_reg (mode0, op0);
7270 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7271 op1 = copy_to_mode_reg (mode0, op1);
7272 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7273 op2 = copy_to_mode_reg (mode0, op2);
7274 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7275 op3 = copy_to_mode_reg (mode0, op3);
7277 /* Generate the compare. */
7278 scratch = gen_reg_rtx (CCmode);
7279 pat = GEN_FCN (icode) (scratch, op0, op1);
7284 if (mode0 == V2SImode)
7285 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7287 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7292 /* Expand an expression EXP that calls a built-in function,
7293 with result going to TARGET if that's convenient
7294 (and in mode MODE if that's convenient).
7295 SUBTARGET may be used as the target for computing one of EXP's operands.
7296 IGNORE is nonzero if the value is to be ignored. */
7299 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7300 enum machine_mode mode ATTRIBUTE_UNUSED,
7301 int ignore ATTRIBUTE_UNUSED)
7303 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7304 tree arglist = TREE_OPERAND (exp, 1);
7305 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7306 struct builtin_description *d;
7311 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7312 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7314 int icode = (int) CODE_FOR_altivec_lvsr;
7315 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7316 enum machine_mode mode = insn_data[icode].operand[1].mode;
7320 gcc_assert (TARGET_ALTIVEC);
7322 arg = TREE_VALUE (arglist);
7323 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7324 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7325 addr = memory_address (mode, op);
7326 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7330 /* For the load case need to negate the address. */
7331 op = gen_reg_rtx (GET_MODE (addr));
7332 emit_insn (gen_rtx_SET (VOIDmode, op,
7333 gen_rtx_NEG (GET_MODE (addr), addr)));
7335 op = gen_rtx_MEM (mode, op);
7338 || GET_MODE (target) != tmode
7339 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7340 target = gen_reg_rtx (tmode);
7342 /*pat = gen_altivec_lvsr (target, op);*/
7343 pat = GEN_FCN (icode) (target, op);
7353 ret = altivec_expand_builtin (exp, target, &success);
7360 ret = spe_expand_builtin (exp, target, &success);
7366 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7368 /* Handle simple unary operations. */
7369 d = (struct builtin_description *) bdesc_1arg;
7370 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7371 if (d->code == fcode)
7372 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7374 /* Handle simple binary operations. */
7375 d = (struct builtin_description *) bdesc_2arg;
7376 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7377 if (d->code == fcode)
7378 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7380 /* Handle simple ternary operations. */
7381 d = (struct builtin_description *) bdesc_3arg;
7382 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7383 if (d->code == fcode)
7384 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7390 build_opaque_vector_type (tree node, int nunits)
7392 node = copy_node (node);
7393 TYPE_MAIN_VARIANT (node) = node;
7394 return build_vector_type (node, nunits);
7398 rs6000_init_builtins (void)
7400 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7401 V2SF_type_node = build_vector_type (float_type_node, 2);
7402 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7403 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7404 V4SF_type_node = build_vector_type (float_type_node, 4);
7405 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7406 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7408 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7409 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7410 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7412 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7413 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7414 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7415 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7417 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7418 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7419 'vector unsigned short'. */
7421 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7422 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7423 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7424 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7426 long_integer_type_internal_node = long_integer_type_node;
7427 long_unsigned_type_internal_node = long_unsigned_type_node;
7428 intQI_type_internal_node = intQI_type_node;
7429 uintQI_type_internal_node = unsigned_intQI_type_node;
7430 intHI_type_internal_node = intHI_type_node;
7431 uintHI_type_internal_node = unsigned_intHI_type_node;
7432 intSI_type_internal_node = intSI_type_node;
7433 uintSI_type_internal_node = unsigned_intSI_type_node;
7434 float_type_internal_node = float_type_node;
7435 void_type_internal_node = void_type_node;
7437 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7438 get_identifier ("__bool char"),
7439 bool_char_type_node));
7440 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7441 get_identifier ("__bool short"),
7442 bool_short_type_node));
7443 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7444 get_identifier ("__bool int"),
7445 bool_int_type_node));
7446 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7447 get_identifier ("__pixel"),
7450 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7451 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7452 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7453 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7455 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7456 get_identifier ("__vector unsigned char"),
7457 unsigned_V16QI_type_node));
7458 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7459 get_identifier ("__vector signed char"),
7461 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7462 get_identifier ("__vector __bool char"),
7463 bool_V16QI_type_node));
7465 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7466 get_identifier ("__vector unsigned short"),
7467 unsigned_V8HI_type_node));
7468 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7469 get_identifier ("__vector signed short"),
7471 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7472 get_identifier ("__vector __bool short"),
7473 bool_V8HI_type_node));
7475 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7476 get_identifier ("__vector unsigned int"),
7477 unsigned_V4SI_type_node));
7478 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7479 get_identifier ("__vector signed int"),
7481 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7482 get_identifier ("__vector __bool int"),
7483 bool_V4SI_type_node));
7485 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7486 get_identifier ("__vector float"),
7488 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7489 get_identifier ("__vector __pixel"),
7490 pixel_V8HI_type_node));
7493 spe_init_builtins ();
7495 altivec_init_builtins ();
7496 if (TARGET_ALTIVEC || TARGET_SPE)
7497 rs6000_common_init_builtins ();
7500 /* Search through a set of builtins and enable the mask bits.
7501 DESC is an array of builtins.
7502 SIZE is the total number of builtins.
7503 START is the builtin enum at which to start.
7504 END is the builtin enum at which to end. */
7506 enable_mask_for_builtins (struct builtin_description *desc, int size,
7507 enum rs6000_builtins start,
7508 enum rs6000_builtins end)
7512 for (i = 0; i < size; ++i)
7513 if (desc[i].code == start)
7519 for (; i < size; ++i)
7521 /* Flip all the bits on. */
7522 desc[i].mask = target_flags;
7523 if (desc[i].code == end)
7529 spe_init_builtins (void)
7531 tree endlink = void_list_node;
7532 tree puint_type_node = build_pointer_type (unsigned_type_node);
7533 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7534 struct builtin_description *d;
7537 tree v2si_ftype_4_v2si
7538 = build_function_type
7539 (opaque_V2SI_type_node,
7540 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7541 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7542 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7543 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7546 tree v2sf_ftype_4_v2sf
7547 = build_function_type
7548 (opaque_V2SF_type_node,
7549 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7550 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7551 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7552 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7555 tree int_ftype_int_v2si_v2si
7556 = build_function_type
7558 tree_cons (NULL_TREE, integer_type_node,
7559 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7560 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7563 tree int_ftype_int_v2sf_v2sf
7564 = build_function_type
7566 tree_cons (NULL_TREE, integer_type_node,
7567 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7568 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7571 tree void_ftype_v2si_puint_int
7572 = build_function_type (void_type_node,
7573 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7574 tree_cons (NULL_TREE, puint_type_node,
7575 tree_cons (NULL_TREE,
7579 tree void_ftype_v2si_puint_char
7580 = build_function_type (void_type_node,
7581 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7582 tree_cons (NULL_TREE, puint_type_node,
7583 tree_cons (NULL_TREE,
7587 tree void_ftype_v2si_pv2si_int
7588 = build_function_type (void_type_node,
7589 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7590 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7591 tree_cons (NULL_TREE,
7595 tree void_ftype_v2si_pv2si_char
7596 = build_function_type (void_type_node,
7597 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7598 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7599 tree_cons (NULL_TREE,
7604 = build_function_type (void_type_node,
7605 tree_cons (NULL_TREE, integer_type_node, endlink));
7608 = build_function_type (integer_type_node, endlink);
7610 tree v2si_ftype_pv2si_int
7611 = build_function_type (opaque_V2SI_type_node,
7612 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7613 tree_cons (NULL_TREE, integer_type_node,
7616 tree v2si_ftype_puint_int
7617 = build_function_type (opaque_V2SI_type_node,
7618 tree_cons (NULL_TREE, puint_type_node,
7619 tree_cons (NULL_TREE, integer_type_node,
7622 tree v2si_ftype_pushort_int
7623 = build_function_type (opaque_V2SI_type_node,
7624 tree_cons (NULL_TREE, pushort_type_node,
7625 tree_cons (NULL_TREE, integer_type_node,
7628 tree v2si_ftype_signed_char
7629 = build_function_type (opaque_V2SI_type_node,
7630 tree_cons (NULL_TREE, signed_char_type_node,
7633 /* The initialization of the simple binary and unary builtins is
7634 done in rs6000_common_init_builtins, but we have to enable the
7635 mask bits here manually because we have run out of `target_flags'
7636 bits. We really need to redesign this mask business. */
7638 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7639 ARRAY_SIZE (bdesc_2arg),
7642 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7643 ARRAY_SIZE (bdesc_1arg),
7645 SPE_BUILTIN_EVSUBFUSIAAW);
7646 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7647 ARRAY_SIZE (bdesc_spe_predicates),
7648 SPE_BUILTIN_EVCMPEQ,
7649 SPE_BUILTIN_EVFSTSTLT);
7650 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7651 ARRAY_SIZE (bdesc_spe_evsel),
7652 SPE_BUILTIN_EVSEL_CMPGTS,
7653 SPE_BUILTIN_EVSEL_FSTSTEQ);
7655 (*lang_hooks.decls.pushdecl)
7656 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7657 opaque_V2SI_type_node));
7659 /* Initialize irregular SPE builtins. */
7661 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7662 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7663 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7664 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7665 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7666 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7667 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7668 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7669 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7670 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7671 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7672 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7673 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7674 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7675 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7676 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
7677 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7678 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
7681 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7682 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7683 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7684 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7685 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7686 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7687 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7688 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7689 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7690 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7691 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7692 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7693 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7694 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7695 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7696 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7697 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7698 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7699 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7700 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7701 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7702 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7705 d = (struct builtin_description *) bdesc_spe_predicates;
7706 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7710 switch (insn_data[d->icode].operand[1].mode)
7713 type = int_ftype_int_v2si_v2si;
7716 type = int_ftype_int_v2sf_v2sf;
7722 def_builtin (d->mask, d->name, type, d->code);
7725 /* Evsel predicates. */
7726 d = (struct builtin_description *) bdesc_spe_evsel;
7727 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7731 switch (insn_data[d->icode].operand[1].mode)
7734 type = v2si_ftype_4_v2si;
7737 type = v2sf_ftype_4_v2sf;
7743 def_builtin (d->mask, d->name, type, d->code);
7748 altivec_init_builtins (void)
7750 struct builtin_description *d;
7751 struct builtin_description_predicates *dp;
7753 tree pfloat_type_node = build_pointer_type (float_type_node);
7754 tree pint_type_node = build_pointer_type (integer_type_node);
7755 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7756 tree pchar_type_node = build_pointer_type (char_type_node);
7758 tree pvoid_type_node = build_pointer_type (void_type_node);
7760 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7761 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7762 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7763 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7765 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7767 tree int_ftype_opaque
7768 = build_function_type_list (integer_type_node,
7769 opaque_V4SI_type_node, NULL_TREE);
7771 tree opaque_ftype_opaque_int
7772 = build_function_type_list (opaque_V4SI_type_node,
7773 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
7774 tree opaque_ftype_opaque_opaque_int
7775 = build_function_type_list (opaque_V4SI_type_node,
7776 opaque_V4SI_type_node, opaque_V4SI_type_node,
7777 integer_type_node, NULL_TREE);
7778 tree int_ftype_int_opaque_opaque
7779 = build_function_type_list (integer_type_node,
7780 integer_type_node, opaque_V4SI_type_node,
7781 opaque_V4SI_type_node, NULL_TREE);
7782 tree int_ftype_int_v4si_v4si
7783 = build_function_type_list (integer_type_node,
7784 integer_type_node, V4SI_type_node,
7785 V4SI_type_node, NULL_TREE);
7786 tree v4sf_ftype_pcfloat
7787 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
7788 tree void_ftype_pfloat_v4sf
7789 = build_function_type_list (void_type_node,
7790 pfloat_type_node, V4SF_type_node, NULL_TREE);
7791 tree v4si_ftype_pcint
7792 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7793 tree void_ftype_pint_v4si
7794 = build_function_type_list (void_type_node,
7795 pint_type_node, V4SI_type_node, NULL_TREE);
7796 tree v8hi_ftype_pcshort
7797 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
7798 tree void_ftype_pshort_v8hi
7799 = build_function_type_list (void_type_node,
7800 pshort_type_node, V8HI_type_node, NULL_TREE);
7801 tree v16qi_ftype_pcchar
7802 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
7803 tree void_ftype_pchar_v16qi
7804 = build_function_type_list (void_type_node,
7805 pchar_type_node, V16QI_type_node, NULL_TREE);
7806 tree void_ftype_v4si
7807 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
7808 tree v8hi_ftype_void
7809 = build_function_type (V8HI_type_node, void_list_node);
7810 tree void_ftype_void
7811 = build_function_type (void_type_node, void_list_node);
7813 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
7815 tree opaque_ftype_long_pcvoid
7816 = build_function_type_list (opaque_V4SI_type_node,
7817 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7818 tree v16qi_ftype_long_pcvoid
7819 = build_function_type_list (V16QI_type_node,
7820 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7821 tree v8hi_ftype_long_pcvoid
7822 = build_function_type_list (V8HI_type_node,
7823 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7824 tree v4si_ftype_long_pcvoid
7825 = build_function_type_list (V4SI_type_node,
7826 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7828 tree void_ftype_opaque_long_pvoid
7829 = build_function_type_list (void_type_node,
7830 opaque_V4SI_type_node, long_integer_type_node,
7831 pvoid_type_node, NULL_TREE);
7832 tree void_ftype_v4si_long_pvoid
7833 = build_function_type_list (void_type_node,
7834 V4SI_type_node, long_integer_type_node,
7835 pvoid_type_node, NULL_TREE);
7836 tree void_ftype_v16qi_long_pvoid
7837 = build_function_type_list (void_type_node,
7838 V16QI_type_node, long_integer_type_node,
7839 pvoid_type_node, NULL_TREE);
7840 tree void_ftype_v8hi_long_pvoid
7841 = build_function_type_list (void_type_node,
7842 V8HI_type_node, long_integer_type_node,
7843 pvoid_type_node, NULL_TREE);
7844 tree int_ftype_int_v8hi_v8hi
7845 = build_function_type_list (integer_type_node,
7846 integer_type_node, V8HI_type_node,
7847 V8HI_type_node, NULL_TREE);
7848 tree int_ftype_int_v16qi_v16qi
7849 = build_function_type_list (integer_type_node,
7850 integer_type_node, V16QI_type_node,
7851 V16QI_type_node, NULL_TREE);
7852 tree int_ftype_int_v4sf_v4sf
7853 = build_function_type_list (integer_type_node,
7854 integer_type_node, V4SF_type_node,
7855 V4SF_type_node, NULL_TREE);
7856 tree v4si_ftype_v4si
7857 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7858 tree v8hi_ftype_v8hi
7859 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7860 tree v16qi_ftype_v16qi
7861 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7862 tree v4sf_ftype_v4sf
7863 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7864 tree void_ftype_pcvoid_int_int
7865 = build_function_type_list (void_type_node,
7866 pcvoid_type_node, integer_type_node,
7867 integer_type_node, NULL_TREE);
7869 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7870 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7871 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7872 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7873 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7874 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7875 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7876 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7877 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7878 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7879 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7880 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7881 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7882 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7883 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7884 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
7885 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7886 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7887 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
7888 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
7889 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7890 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7891 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7892 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7893 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7894 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7895 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7896 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7897 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7898 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7899 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7900 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
7901 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
7902 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
7903 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
7904 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
7905 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
7906 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
7907 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
7908 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
7909 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
7910 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
7911 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
7912 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
7913 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
7914 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
7916 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
7918 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
7919 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
7920 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
7921 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
7922 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
7923 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
7924 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
7925 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
7926 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
7927 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
7929 /* Add the DST variants. */
7930 d = (struct builtin_description *) bdesc_dst;
7931 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7932 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
7934 /* Initialize the predicates. */
7935 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7936 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7938 enum machine_mode mode1;
7940 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7941 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
7946 mode1 = insn_data[dp->icode].operand[1].mode;
7951 type = int_ftype_int_opaque_opaque;
7954 type = int_ftype_int_v4si_v4si;
7957 type = int_ftype_int_v8hi_v8hi;
7960 type = int_ftype_int_v16qi_v16qi;
7963 type = int_ftype_int_v4sf_v4sf;
7969 def_builtin (dp->mask, dp->name, type, dp->code);
7972 /* Initialize the abs* operators. */
7973 d = (struct builtin_description *) bdesc_abs;
7974 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7976 enum machine_mode mode0;
7979 mode0 = insn_data[d->icode].operand[0].mode;
7984 type = v4si_ftype_v4si;
7987 type = v8hi_ftype_v8hi;
7990 type = v16qi_ftype_v16qi;
7993 type = v4sf_ftype_v4sf;
7999 def_builtin (d->mask, d->name, type, d->code);
8006 /* Initialize target builtin that implements
8007 targetm.vectorize.builtin_mask_for_load. */
8009 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8010 v16qi_ftype_long_pcvoid,
8011 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8013 tree_cons (get_identifier ("const"),
8014 NULL_TREE, NULL_TREE));
8015 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8016 altivec_builtin_mask_for_load = decl;
8021 rs6000_common_init_builtins (void)
8023 struct builtin_description *d;
8026 tree v4sf_ftype_v4sf_v4sf_v16qi
8027 = build_function_type_list (V4SF_type_node,
8028 V4SF_type_node, V4SF_type_node,
8029 V16QI_type_node, NULL_TREE);
8030 tree v4si_ftype_v4si_v4si_v16qi
8031 = build_function_type_list (V4SI_type_node,
8032 V4SI_type_node, V4SI_type_node,
8033 V16QI_type_node, NULL_TREE);
8034 tree v8hi_ftype_v8hi_v8hi_v16qi
8035 = build_function_type_list (V8HI_type_node,
8036 V8HI_type_node, V8HI_type_node,
8037 V16QI_type_node, NULL_TREE);
8038 tree v16qi_ftype_v16qi_v16qi_v16qi
8039 = build_function_type_list (V16QI_type_node,
8040 V16QI_type_node, V16QI_type_node,
8041 V16QI_type_node, NULL_TREE);
8043 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8045 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8046 tree v16qi_ftype_int
8047 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8048 tree v8hi_ftype_v16qi
8049 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8050 tree v4sf_ftype_v4sf
8051 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8053 tree v2si_ftype_v2si_v2si
8054 = build_function_type_list (opaque_V2SI_type_node,
8055 opaque_V2SI_type_node,
8056 opaque_V2SI_type_node, NULL_TREE);
8058 tree v2sf_ftype_v2sf_v2sf
8059 = build_function_type_list (opaque_V2SF_type_node,
8060 opaque_V2SF_type_node,
8061 opaque_V2SF_type_node, NULL_TREE);
8063 tree v2si_ftype_int_int
8064 = build_function_type_list (opaque_V2SI_type_node,
8065 integer_type_node, integer_type_node,
8068 tree opaque_ftype_opaque
8069 = build_function_type_list (opaque_V4SI_type_node,
8070 opaque_V4SI_type_node, NULL_TREE);
8072 tree v2si_ftype_v2si
8073 = build_function_type_list (opaque_V2SI_type_node,
8074 opaque_V2SI_type_node, NULL_TREE);
8076 tree v2sf_ftype_v2sf
8077 = build_function_type_list (opaque_V2SF_type_node,
8078 opaque_V2SF_type_node, NULL_TREE);
8080 tree v2sf_ftype_v2si
8081 = build_function_type_list (opaque_V2SF_type_node,
8082 opaque_V2SI_type_node, NULL_TREE);
8084 tree v2si_ftype_v2sf
8085 = build_function_type_list (opaque_V2SI_type_node,
8086 opaque_V2SF_type_node, NULL_TREE);
8088 tree v2si_ftype_v2si_char
8089 = build_function_type_list (opaque_V2SI_type_node,
8090 opaque_V2SI_type_node,
8091 char_type_node, NULL_TREE);
8093 tree v2si_ftype_int_char
8094 = build_function_type_list (opaque_V2SI_type_node,
8095 integer_type_node, char_type_node, NULL_TREE);
8097 tree v2si_ftype_char
8098 = build_function_type_list (opaque_V2SI_type_node,
8099 char_type_node, NULL_TREE);
8101 tree int_ftype_int_int
8102 = build_function_type_list (integer_type_node,
8103 integer_type_node, integer_type_node,
8106 tree opaque_ftype_opaque_opaque
8107 = build_function_type_list (opaque_V4SI_type_node,
8108 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8109 tree v4si_ftype_v4si_v4si
8110 = build_function_type_list (V4SI_type_node,
8111 V4SI_type_node, V4SI_type_node, NULL_TREE);
8112 tree v4sf_ftype_v4si_int
8113 = build_function_type_list (V4SF_type_node,
8114 V4SI_type_node, integer_type_node, NULL_TREE);
8115 tree v4si_ftype_v4sf_int
8116 = build_function_type_list (V4SI_type_node,
8117 V4SF_type_node, integer_type_node, NULL_TREE);
8118 tree v4si_ftype_v4si_int
8119 = build_function_type_list (V4SI_type_node,
8120 V4SI_type_node, integer_type_node, NULL_TREE);
8121 tree v8hi_ftype_v8hi_int
8122 = build_function_type_list (V8HI_type_node,
8123 V8HI_type_node, integer_type_node, NULL_TREE);
8124 tree v16qi_ftype_v16qi_int
8125 = build_function_type_list (V16QI_type_node,
8126 V16QI_type_node, integer_type_node, NULL_TREE);
8127 tree v16qi_ftype_v16qi_v16qi_int
8128 = build_function_type_list (V16QI_type_node,
8129 V16QI_type_node, V16QI_type_node,
8130 integer_type_node, NULL_TREE);
8131 tree v8hi_ftype_v8hi_v8hi_int
8132 = build_function_type_list (V8HI_type_node,
8133 V8HI_type_node, V8HI_type_node,
8134 integer_type_node, NULL_TREE);
8135 tree v4si_ftype_v4si_v4si_int
8136 = build_function_type_list (V4SI_type_node,
8137 V4SI_type_node, V4SI_type_node,
8138 integer_type_node, NULL_TREE);
8139 tree v4sf_ftype_v4sf_v4sf_int
8140 = build_function_type_list (V4SF_type_node,
8141 V4SF_type_node, V4SF_type_node,
8142 integer_type_node, NULL_TREE);
8143 tree v4sf_ftype_v4sf_v4sf
8144 = build_function_type_list (V4SF_type_node,
8145 V4SF_type_node, V4SF_type_node, NULL_TREE);
8146 tree opaque_ftype_opaque_opaque_opaque
8147 = build_function_type_list (opaque_V4SI_type_node,
8148 opaque_V4SI_type_node, opaque_V4SI_type_node,
8149 opaque_V4SI_type_node, NULL_TREE);
8150 tree v4sf_ftype_v4sf_v4sf_v4si
8151 = build_function_type_list (V4SF_type_node,
8152 V4SF_type_node, V4SF_type_node,
8153 V4SI_type_node, NULL_TREE);
8154 tree v4sf_ftype_v4sf_v4sf_v4sf
8155 = build_function_type_list (V4SF_type_node,
8156 V4SF_type_node, V4SF_type_node,
8157 V4SF_type_node, NULL_TREE);
8158 tree v4si_ftype_v4si_v4si_v4si
8159 = build_function_type_list (V4SI_type_node,
8160 V4SI_type_node, V4SI_type_node,
8161 V4SI_type_node, NULL_TREE);
8162 tree v8hi_ftype_v8hi_v8hi
8163 = build_function_type_list (V8HI_type_node,
8164 V8HI_type_node, V8HI_type_node, NULL_TREE);
8165 tree v8hi_ftype_v8hi_v8hi_v8hi
8166 = build_function_type_list (V8HI_type_node,
8167 V8HI_type_node, V8HI_type_node,
8168 V8HI_type_node, NULL_TREE);
8169 tree v4si_ftype_v8hi_v8hi_v4si
8170 = build_function_type_list (V4SI_type_node,
8171 V8HI_type_node, V8HI_type_node,
8172 V4SI_type_node, NULL_TREE);
8173 tree v4si_ftype_v16qi_v16qi_v4si
8174 = build_function_type_list (V4SI_type_node,
8175 V16QI_type_node, V16QI_type_node,
8176 V4SI_type_node, NULL_TREE);
8177 tree v16qi_ftype_v16qi_v16qi
8178 = build_function_type_list (V16QI_type_node,
8179 V16QI_type_node, V16QI_type_node, NULL_TREE);
8180 tree v4si_ftype_v4sf_v4sf
8181 = build_function_type_list (V4SI_type_node,
8182 V4SF_type_node, V4SF_type_node, NULL_TREE);
8183 tree v8hi_ftype_v16qi_v16qi
8184 = build_function_type_list (V8HI_type_node,
8185 V16QI_type_node, V16QI_type_node, NULL_TREE);
8186 tree v4si_ftype_v8hi_v8hi
8187 = build_function_type_list (V4SI_type_node,
8188 V8HI_type_node, V8HI_type_node, NULL_TREE);
8189 tree v8hi_ftype_v4si_v4si
8190 = build_function_type_list (V8HI_type_node,
8191 V4SI_type_node, V4SI_type_node, NULL_TREE);
8192 tree v16qi_ftype_v8hi_v8hi
8193 = build_function_type_list (V16QI_type_node,
8194 V8HI_type_node, V8HI_type_node, NULL_TREE);
8195 tree v4si_ftype_v16qi_v4si
8196 = build_function_type_list (V4SI_type_node,
8197 V16QI_type_node, V4SI_type_node, NULL_TREE);
8198 tree v4si_ftype_v16qi_v16qi
8199 = build_function_type_list (V4SI_type_node,
8200 V16QI_type_node, V16QI_type_node, NULL_TREE);
8201 tree v4si_ftype_v8hi_v4si
8202 = build_function_type_list (V4SI_type_node,
8203 V8HI_type_node, V4SI_type_node, NULL_TREE);
8204 tree v4si_ftype_v8hi
8205 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8206 tree int_ftype_v4si_v4si
8207 = build_function_type_list (integer_type_node,
8208 V4SI_type_node, V4SI_type_node, NULL_TREE);
8209 tree int_ftype_v4sf_v4sf
8210 = build_function_type_list (integer_type_node,
8211 V4SF_type_node, V4SF_type_node, NULL_TREE);
8212 tree int_ftype_v16qi_v16qi
8213 = build_function_type_list (integer_type_node,
8214 V16QI_type_node, V16QI_type_node, NULL_TREE);
8215 tree int_ftype_v8hi_v8hi
8216 = build_function_type_list (integer_type_node,
8217 V8HI_type_node, V8HI_type_node, NULL_TREE);
8219 /* Add the simple ternary operators. */
8220 d = (struct builtin_description *) bdesc_3arg;
8221 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8223 enum machine_mode mode0, mode1, mode2, mode3;
8225 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8226 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8237 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8240 mode0 = insn_data[d->icode].operand[0].mode;
8241 mode1 = insn_data[d->icode].operand[1].mode;
8242 mode2 = insn_data[d->icode].operand[2].mode;
8243 mode3 = insn_data[d->icode].operand[3].mode;
8246 /* When all four are of the same mode. */
8247 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8252 type = opaque_ftype_opaque_opaque_opaque;
8255 type = v4si_ftype_v4si_v4si_v4si;
8258 type = v4sf_ftype_v4sf_v4sf_v4sf;
8261 type = v8hi_ftype_v8hi_v8hi_v8hi;
8264 type = v16qi_ftype_v16qi_v16qi_v16qi;
8270 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8275 type = v4si_ftype_v4si_v4si_v16qi;
8278 type = v4sf_ftype_v4sf_v4sf_v16qi;
8281 type = v8hi_ftype_v8hi_v8hi_v16qi;
8284 type = v16qi_ftype_v16qi_v16qi_v16qi;
8290 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8291 && mode3 == V4SImode)
8292 type = v4si_ftype_v16qi_v16qi_v4si;
8293 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8294 && mode3 == V4SImode)
8295 type = v4si_ftype_v8hi_v8hi_v4si;
8296 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8297 && mode3 == V4SImode)
8298 type = v4sf_ftype_v4sf_v4sf_v4si;
8300 /* vchar, vchar, vchar, 4 bit literal. */
8301 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8303 type = v16qi_ftype_v16qi_v16qi_int;
8305 /* vshort, vshort, vshort, 4 bit literal. */
8306 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8308 type = v8hi_ftype_v8hi_v8hi_int;
8310 /* vint, vint, vint, 4 bit literal. */
8311 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8313 type = v4si_ftype_v4si_v4si_int;
8315 /* vfloat, vfloat, vfloat, 4 bit literal. */
8316 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8318 type = v4sf_ftype_v4sf_v4sf_int;
8323 def_builtin (d->mask, d->name, type, d->code);
8326 /* Add the simple binary operators. */
8327 d = (struct builtin_description *) bdesc_2arg;
8328 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8330 enum machine_mode mode0, mode1, mode2;
8332 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8333 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8343 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8346 mode0 = insn_data[d->icode].operand[0].mode;
8347 mode1 = insn_data[d->icode].operand[1].mode;
8348 mode2 = insn_data[d->icode].operand[2].mode;
8351 /* When all three operands are of the same mode. */
8352 if (mode0 == mode1 && mode1 == mode2)
8357 type = opaque_ftype_opaque_opaque;
8360 type = v4sf_ftype_v4sf_v4sf;
8363 type = v4si_ftype_v4si_v4si;
8366 type = v16qi_ftype_v16qi_v16qi;
8369 type = v8hi_ftype_v8hi_v8hi;
8372 type = v2si_ftype_v2si_v2si;
8375 type = v2sf_ftype_v2sf_v2sf;
8378 type = int_ftype_int_int;
8385 /* A few other combos we really don't want to do manually. */
8387 /* vint, vfloat, vfloat. */
8388 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8389 type = v4si_ftype_v4sf_v4sf;
8391 /* vshort, vchar, vchar. */
8392 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8393 type = v8hi_ftype_v16qi_v16qi;
8395 /* vint, vshort, vshort. */
8396 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8397 type = v4si_ftype_v8hi_v8hi;
8399 /* vshort, vint, vint. */
8400 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8401 type = v8hi_ftype_v4si_v4si;
8403 /* vchar, vshort, vshort. */
8404 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8405 type = v16qi_ftype_v8hi_v8hi;
8407 /* vint, vchar, vint. */
8408 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8409 type = v4si_ftype_v16qi_v4si;
8411 /* vint, vchar, vchar. */
8412 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8413 type = v4si_ftype_v16qi_v16qi;
8415 /* vint, vshort, vint. */
8416 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8417 type = v4si_ftype_v8hi_v4si;
8419 /* vint, vint, 5 bit literal. */
8420 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8421 type = v4si_ftype_v4si_int;
8423 /* vshort, vshort, 5 bit literal. */
8424 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8425 type = v8hi_ftype_v8hi_int;
8427 /* vchar, vchar, 5 bit literal. */
8428 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8429 type = v16qi_ftype_v16qi_int;
8431 /* vfloat, vint, 5 bit literal. */
8432 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8433 type = v4sf_ftype_v4si_int;
8435 /* vint, vfloat, 5 bit literal. */
8436 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8437 type = v4si_ftype_v4sf_int;
8439 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8440 type = v2si_ftype_int_int;
8442 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8443 type = v2si_ftype_v2si_char;
8445 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8446 type = v2si_ftype_int_char;
8451 gcc_assert (mode0 == SImode);
8455 type = int_ftype_v4si_v4si;
8458 type = int_ftype_v4sf_v4sf;
8461 type = int_ftype_v16qi_v16qi;
8464 type = int_ftype_v8hi_v8hi;
8471 def_builtin (d->mask, d->name, type, d->code);
8474 /* Add the simple unary operators. */
8475 d = (struct builtin_description *) bdesc_1arg;
8476 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8478 enum machine_mode mode0, mode1;
8480 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8481 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8490 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8493 mode0 = insn_data[d->icode].operand[0].mode;
8494 mode1 = insn_data[d->icode].operand[1].mode;
8497 if (mode0 == V4SImode && mode1 == QImode)
8498 type = v4si_ftype_int;
8499 else if (mode0 == V8HImode && mode1 == QImode)
8500 type = v8hi_ftype_int;
8501 else if (mode0 == V16QImode && mode1 == QImode)
8502 type = v16qi_ftype_int;
8503 else if (mode0 == VOIDmode && mode1 == VOIDmode)
8504 type = opaque_ftype_opaque;
8505 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8506 type = v4sf_ftype_v4sf;
8507 else if (mode0 == V8HImode && mode1 == V16QImode)
8508 type = v8hi_ftype_v16qi;
8509 else if (mode0 == V4SImode && mode1 == V8HImode)
8510 type = v4si_ftype_v8hi;
8511 else if (mode0 == V2SImode && mode1 == V2SImode)
8512 type = v2si_ftype_v2si;
8513 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8514 type = v2sf_ftype_v2sf;
8515 else if (mode0 == V2SFmode && mode1 == V2SImode)
8516 type = v2sf_ftype_v2si;
8517 else if (mode0 == V2SImode && mode1 == V2SFmode)
8518 type = v2si_ftype_v2sf;
8519 else if (mode0 == V2SImode && mode1 == QImode)
8520 type = v2si_ftype_char;
8524 def_builtin (d->mask, d->name, type, d->code);
8529 rs6000_init_libfuncs (void)
8531 if (!TARGET_HARD_FLOAT)
8534 if (DEFAULT_ABI != ABI_V4)
8536 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8538 /* AIX library routines for float->int conversion. */
8539 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8540 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8541 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8542 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8545 /* AIX/Darwin/64-bit Linux quad floating point routines. */
8546 if (!TARGET_XL_COMPAT)
8548 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
8549 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
8550 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
8551 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
8555 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8556 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8557 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8558 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8563 /* 32-bit SVR4 quad floating point routines. */
8565 set_optab_libfunc (add_optab, TFmode, "_q_add");
8566 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8567 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8568 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8569 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8570 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8571 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8573 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8574 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8575 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8576 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8577 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8578 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8580 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8581 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8582 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8583 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8584 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8585 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8586 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8591 /* Expand a block clear operation, and return 1 if successful. Return 0
8592 if we should let the compiler generate normal code.
8594 operands[0] is the destination
8595 operands[1] is the length
8596 operands[3] is the alignment */
8599 expand_block_clear (rtx operands[])
8601 rtx orig_dest = operands[0];
8602 rtx bytes_rtx = operands[1];
8603 rtx align_rtx = operands[3];
8604 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8605 HOST_WIDE_INT align;
8606 HOST_WIDE_INT bytes;
8611 /* If this is not a fixed size move, just call memcpy */
8615 /* This must be a fixed size alignment */
8616 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
8617 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8619 /* Anything to clear? */
8620 bytes = INTVAL (bytes_rtx);
8624 /* Use the builtin memset after a point, to avoid huge code bloat.
8625 When optimize_size, avoid any significant code bloat; calling
8626 memset is about 4 instructions, so allow for one instruction to
8627 load zero and three to do clearing. */
8628 if (TARGET_ALTIVEC && align >= 128)
8630 else if (TARGET_POWERPC64 && align >= 32)
8635 if (optimize_size && bytes > 3 * clear_step)
8637 if (! optimize_size && bytes > 8 * clear_step)
8640 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8642 enum machine_mode mode = BLKmode;
8645 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8650 else if (bytes >= 8 && TARGET_POWERPC64
8651 /* 64-bit loads and stores require word-aligned
8653 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8658 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8659 { /* move 4 bytes */
8663 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8664 { /* move 2 bytes */
8668 else /* move 1 byte at a time */
8674 dest = adjust_address (orig_dest, mode, offset);
8676 emit_move_insn (dest, CONST0_RTX (mode));
8683 /* Expand a block move operation, and return 1 if successful. Return 0
8684 if we should let the compiler generate normal code.
8686 operands[0] is the destination
8687 operands[1] is the source
8688 operands[2] is the length
8689 operands[3] is the alignment */
8691 #define MAX_MOVE_REG 4
8694 expand_block_move (rtx operands[])
8696 rtx orig_dest = operands[0];
8697 rtx orig_src = operands[1];
8698 rtx bytes_rtx = operands[2];
8699 rtx align_rtx = operands[3];
8700 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8705 rtx stores[MAX_MOVE_REG];
8708 /* If this is not a fixed size move, just call memcpy */
8712 /* This must be a fixed size alignment */
8713 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
8714 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8716 /* Anything to move? */
8717 bytes = INTVAL (bytes_rtx);
8721 /* store_one_arg depends on expand_block_move to handle at least the size of
8722 reg_parm_stack_space. */
8723 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
8726 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
8729 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
8730 rtx (*mov) (rtx, rtx);
8732 enum machine_mode mode = BLKmode;
8735 /* Altivec first, since it will be faster than a string move
8736 when it applies, and usually not significantly larger. */
8737 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8741 gen_func.mov = gen_movv4si;
8743 else if (TARGET_STRING
8744 && bytes > 24 /* move up to 32 bytes at a time */
8752 && ! fixed_regs[12])
8754 move_bytes = (bytes > 32) ? 32 : bytes;
8755 gen_func.movmemsi = gen_movmemsi_8reg;
8757 else if (TARGET_STRING
8758 && bytes > 16 /* move up to 24 bytes at a time */
8764 && ! fixed_regs[10])
8766 move_bytes = (bytes > 24) ? 24 : bytes;
8767 gen_func.movmemsi = gen_movmemsi_6reg;
8769 else if (TARGET_STRING
8770 && bytes > 8 /* move up to 16 bytes at a time */
8776 move_bytes = (bytes > 16) ? 16 : bytes;
8777 gen_func.movmemsi = gen_movmemsi_4reg;
8779 else if (bytes >= 8 && TARGET_POWERPC64
8780 /* 64-bit loads and stores require word-aligned
8782 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8786 gen_func.mov = gen_movdi;
8788 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8789 { /* move up to 8 bytes at a time */
8790 move_bytes = (bytes > 8) ? 8 : bytes;
8791 gen_func.movmemsi = gen_movmemsi_2reg;
8793 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8794 { /* move 4 bytes */
8797 gen_func.mov = gen_movsi;
8799 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8800 { /* move 2 bytes */
8803 gen_func.mov = gen_movhi;
8805 else if (TARGET_STRING && bytes > 1)
8806 { /* move up to 4 bytes at a time */
8807 move_bytes = (bytes > 4) ? 4 : bytes;
8808 gen_func.movmemsi = gen_movmemsi_1reg;
8810 else /* move 1 byte at a time */
8814 gen_func.mov = gen_movqi;
8817 src = adjust_address (orig_src, mode, offset);
8818 dest = adjust_address (orig_dest, mode, offset);
8820 if (mode != BLKmode)
8822 rtx tmp_reg = gen_reg_rtx (mode);
8824 emit_insn ((*gen_func.mov) (tmp_reg, src));
8825 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
8828 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8831 for (i = 0; i < num_reg; i++)
8832 emit_insn (stores[i]);
8836 if (mode == BLKmode)
8838 /* Move the address into scratch registers. The movmemsi
8839 patterns require zero offset. */
8840 if (!REG_P (XEXP (src, 0)))
8842 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8843 src = replace_equiv_address (src, src_reg);
8845 set_mem_size (src, GEN_INT (move_bytes));
8847 if (!REG_P (XEXP (dest, 0)))
8849 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8850 dest = replace_equiv_address (dest, dest_reg);
8852 set_mem_size (dest, GEN_INT (move_bytes));
8854 emit_insn ((*gen_func.movmemsi) (dest, src,
8855 GEN_INT (move_bytes & 31),
8864 /* Return a string to perform a load_multiple operation.
8865 operands[0] is the vector.
8866 operands[1] is the source address.
8867 operands[2] is the first destination register. */
8870 rs6000_output_load_multiple (rtx operands[3])
8872 /* We have to handle the case where the pseudo used to contain the address
8873 is assigned to one of the output registers. */
8875 int words = XVECLEN (operands[0], 0);
8878 if (XVECLEN (operands[0], 0) == 1)
8879 return "{l|lwz} %2,0(%1)";
8881 for (i = 0; i < words; i++)
8882 if (refers_to_regno_p (REGNO (operands[2]) + i,
8883 REGNO (operands[2]) + i + 1, operands[1], 0))
8887 xop[0] = GEN_INT (4 * (words-1));
8888 xop[1] = operands[1];
8889 xop[2] = operands[2];
8890 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8895 xop[0] = GEN_INT (4 * (words-1));
8896 xop[1] = operands[1];
8897 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8898 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8903 for (j = 0; j < words; j++)
8906 xop[0] = GEN_INT (j * 4);
8907 xop[1] = operands[1];
8908 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8909 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8911 xop[0] = GEN_INT (i * 4);
8912 xop[1] = operands[1];
8913 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8918 return "{lsi|lswi} %2,%1,%N0";
8922 /* A validation routine: say whether CODE, a condition code, and MODE
8923 match. The other alternatives either don't make sense or should
8924 never be generated. */
8927 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
8929 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
8930 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
8931 && GET_MODE_CLASS (mode) == MODE_CC);
8933 /* These don't make sense. */
8934 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
8935 || mode != CCUNSmode);
8937 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
8938 || mode == CCUNSmode);
8940 gcc_assert (mode == CCFPmode
8941 || (code != ORDERED && code != UNORDERED
8942 && code != UNEQ && code != LTGT
8943 && code != UNGT && code != UNLT
8944 && code != UNGE && code != UNLE));
8946 /* These should never be generated except for
8947 flag_finite_math_only. */
8948 gcc_assert (mode != CCFPmode
8949 || flag_finite_math_only
8950 || (code != LE && code != GE
8951 && code != UNEQ && code != LTGT
8952 && code != UNGT && code != UNLT));
8954 /* These are invalid; the information is not there. */
8955 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
8959 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8960 mask required to convert the result of a rotate insn into a shift
8961 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
8964 includes_lshift_p (rtx shiftop, rtx andop)
8966 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8968 shift_mask <<= INTVAL (shiftop);
8970 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8973 /* Similar, but for right shift. */
8976 includes_rshift_p (rtx shiftop, rtx andop)
8978 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8980 shift_mask >>= INTVAL (shiftop);
8982 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8985 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8986 to perform a left shift. It must have exactly SHIFTOP least
8987 significant 0's, then one or more 1's, then zero or more 0's. */
8990 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8992 if (GET_CODE (andop) == CONST_INT)
8994 HOST_WIDE_INT c, lsb, shift_mask;
8997 if (c == 0 || c == ~0)
9001 shift_mask <<= INTVAL (shiftop);
9003 /* Find the least significant one bit. */
9006 /* It must coincide with the LSB of the shift mask. */
9007 if (-lsb != shift_mask)
9010 /* Invert to look for the next transition (if any). */
9013 /* Remove the low group of ones (originally low group of zeros). */
9016 /* Again find the lsb, and check we have all 1's above. */
9020 else if (GET_CODE (andop) == CONST_DOUBLE
9021 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9023 HOST_WIDE_INT low, high, lsb;
9024 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9026 low = CONST_DOUBLE_LOW (andop);
9027 if (HOST_BITS_PER_WIDE_INT < 64)
9028 high = CONST_DOUBLE_HIGH (andop);
9030 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9031 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9034 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9036 shift_mask_high = ~0;
9037 if (INTVAL (shiftop) > 32)
9038 shift_mask_high <<= INTVAL (shiftop) - 32;
9042 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9049 return high == -lsb;
9052 shift_mask_low = ~0;
9053 shift_mask_low <<= INTVAL (shiftop);
9057 if (-lsb != shift_mask_low)
9060 if (HOST_BITS_PER_WIDE_INT < 64)
9065 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9068 return high == -lsb;
9072 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9078 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9079 to perform a left shift. It must have SHIFTOP or more least
9080 significant 0's, with the remainder of the word 1's. */
9083 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9085 if (GET_CODE (andop) == CONST_INT)
9087 HOST_WIDE_INT c, lsb, shift_mask;
9090 shift_mask <<= INTVAL (shiftop);
9093 /* Find the least significant one bit. */
9096 /* It must be covered by the shift mask.
9097 This test also rejects c == 0. */
9098 if ((lsb & shift_mask) == 0)
9101 /* Check we have all 1's above the transition, and reject all 1's. */
9102 return c == -lsb && lsb != 1;
9104 else if (GET_CODE (andop) == CONST_DOUBLE
9105 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9107 HOST_WIDE_INT low, lsb, shift_mask_low;
9109 low = CONST_DOUBLE_LOW (andop);
9111 if (HOST_BITS_PER_WIDE_INT < 64)
9113 HOST_WIDE_INT high, shift_mask_high;
9115 high = CONST_DOUBLE_HIGH (andop);
9119 shift_mask_high = ~0;
9120 if (INTVAL (shiftop) > 32)
9121 shift_mask_high <<= INTVAL (shiftop) - 32;
9125 if ((lsb & shift_mask_high) == 0)
9128 return high == -lsb;
9134 shift_mask_low = ~0;
9135 shift_mask_low <<= INTVAL (shiftop);
9139 if ((lsb & shift_mask_low) == 0)
9142 return low == -lsb && lsb != 1;
9148 /* Return 1 if operands will generate a valid arguments to rlwimi
9149 instruction for insert with right shift in 64-bit mode. The mask may
9150 not start on the first bit or stop on the last bit because wrap-around
9151 effects of instruction do not correspond to semantics of RTL insn. */
9154 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9156 if (INTVAL (startop) < 64
9157 && INTVAL (startop) > 32
9158 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9159 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9160 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9161 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9162 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9168 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9169 for lfq and stfq insns iff the registers are hard registers. */
9172 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9174 /* We might have been passed a SUBREG. */
9175 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9178 /* We might have been passed non floating point registers. */
9179 if (!FP_REGNO_P (REGNO (reg1))
9180 || !FP_REGNO_P (REGNO (reg2)))
9183 return (REGNO (reg1) == REGNO (reg2) - 1);
9186 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9187 addr1 and addr2 must be in consecutive memory locations
9188 (addr2 == addr1 + 8). */
9191 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9197 /* The mems cannot be volatile. */
9198 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9201 addr1 = XEXP (mem1, 0);
9202 addr2 = XEXP (mem2, 0);
9204 /* Extract an offset (if used) from the first addr. */
9205 if (GET_CODE (addr1) == PLUS)
9207 /* If not a REG, return zero. */
9208 if (GET_CODE (XEXP (addr1, 0)) != REG)
9212 reg1 = REGNO (XEXP (addr1, 0));
9213 /* The offset must be constant! */
9214 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9216 offset1 = INTVAL (XEXP (addr1, 1));
9219 else if (GET_CODE (addr1) != REG)
9223 reg1 = REGNO (addr1);
9224 /* This was a simple (mem (reg)) expression. Offset is 0. */
9228 /* Make sure the second address is a (mem (plus (reg) (const_int)))
9229 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
9230 register as addr1. */
9231 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
9233 if (GET_CODE (addr2) != PLUS)
9236 if (GET_CODE (XEXP (addr2, 0)) != REG
9237 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9240 if (reg1 != REGNO (XEXP (addr2, 0)))
9243 /* The offset for the second addr must be 8 more than the first addr. */
9244 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
9247 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9252 /* Return the register class of a scratch register needed to copy IN into
9253 or out of a register in CLASS in MODE. If it can be done directly,
9254 NO_REGS is returned. */
9257 secondary_reload_class (enum reg_class class,
9258 enum machine_mode mode ATTRIBUTE_UNUSED,
9263 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9265 && MACHOPIC_INDIRECT
9269 /* We cannot copy a symbolic operand directly into anything
9270 other than BASE_REGS for TARGET_ELF. So indicate that a
9271 register from BASE_REGS is needed as an intermediate
9274 On Darwin, pic addresses require a load from memory, which
9275 needs a base register. */
9276 if (class != BASE_REGS
9277 && (GET_CODE (in) == SYMBOL_REF
9278 || GET_CODE (in) == HIGH
9279 || GET_CODE (in) == LABEL_REF
9280 || GET_CODE (in) == CONST))
9284 if (GET_CODE (in) == REG)
9287 if (regno >= FIRST_PSEUDO_REGISTER)
9289 regno = true_regnum (in);
9290 if (regno >= FIRST_PSEUDO_REGISTER)
9294 else if (GET_CODE (in) == SUBREG)
9296 regno = true_regnum (in);
9297 if (regno >= FIRST_PSEUDO_REGISTER)
9303 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9305 if (class == GENERAL_REGS || class == BASE_REGS
9306 || (regno >= 0 && INT_REGNO_P (regno)))
9309 /* Constants, memory, and FP registers can go into FP registers. */
9310 if ((regno == -1 || FP_REGNO_P (regno))
9311 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9314 /* Memory, and AltiVec registers can go into AltiVec registers. */
9315 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9316 && class == ALTIVEC_REGS)
9319 /* We can copy among the CR registers. */
9320 if ((class == CR_REGS || class == CR0_REGS)
9321 && regno >= 0 && CR_REGNO_P (regno))
9324 /* Otherwise, we need GENERAL_REGS. */
9325 return GENERAL_REGS;
9328 /* Given a comparison operation, return the bit number in CCR to test. We
9329 know this is a valid comparison.
9331 SCC_P is 1 if this is for an scc. That means that %D will have been
9332 used instead of %C, so the bits will be in different places.
9334 Return -1 if OP isn't a valid comparison for some reason. */
9337 ccr_bit (rtx op, int scc_p)
9339 enum rtx_code code = GET_CODE (op);
9340 enum machine_mode cc_mode;
9345 if (!COMPARISON_P (op))
9350 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9352 cc_mode = GET_MODE (reg);
9353 cc_regnum = REGNO (reg);
9354 base_bit = 4 * (cc_regnum - CR0_REGNO);
9356 validate_condition_mode (code, cc_mode);
9358 /* When generating a sCOND operation, only positive conditions are
9361 || code == EQ || code == GT || code == LT || code == UNORDERED
9362 || code == GTU || code == LTU);
9367 return scc_p ? base_bit + 3 : base_bit + 2;
9369 return base_bit + 2;
9370 case GT: case GTU: case UNLE:
9371 return base_bit + 1;
9372 case LT: case LTU: case UNGE:
9374 case ORDERED: case UNORDERED:
9375 return base_bit + 3;
9378 /* If scc, we will have done a cror to put the bit in the
9379 unordered position. So test that bit. For integer, this is ! LT
9380 unless this is an scc insn. */
9381 return scc_p ? base_bit + 3 : base_bit;
9384 return scc_p ? base_bit + 3 : base_bit + 1;
9391 /* Return the GOT register. */
9394 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9396 /* The second flow pass currently (June 1999) can't update
9397 regs_ever_live without disturbing other parts of the compiler, so
9398 update it here to make the prolog/epilogue code happy. */
9399 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9400 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9402 current_function_uses_pic_offset_table = 1;
9404 return pic_offset_table_rtx;
9407 /* Function to init struct machine_function.
9408 This will be called, via a pointer variable,
9409 from push_function_context. */
9411 static struct machine_function *
9412 rs6000_init_machine_status (void)
9414 return ggc_alloc_cleared (sizeof (machine_function));
9417 /* These macros test for integers and extract the low-order bits. */
9419 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9420 && GET_MODE (X) == VOIDmode)
9422 #define INT_LOWPART(X) \
9423 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9429 unsigned long val = INT_LOWPART (op);
9431 /* If the high bit is zero, the value is the first 1 bit we find
9433 if ((val & 0x80000000) == 0)
9435 gcc_assert (val & 0xffffffff);
9438 while (((val <<= 1) & 0x80000000) == 0)
9443 /* If the high bit is set and the low bit is not, or the mask is all
9444 1's, the value is zero. */
9445 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9448 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9451 while (((val >>= 1) & 1) != 0)
9461 unsigned long val = INT_LOWPART (op);
9463 /* If the low bit is zero, the value is the first 1 bit we find from
9467 gcc_assert (val & 0xffffffff);
9470 while (((val >>= 1) & 1) == 0)
9476 /* If the low bit is set and the high bit is not, or the mask is all
9477 1's, the value is 31. */
9478 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9481 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9484 while (((val <<= 1) & 0x80000000) != 0)
9490 /* Locate some local-dynamic symbol still in use by this function
9491 so that we can print its name in some tls_ld pattern. */
9494 rs6000_get_some_local_dynamic_name (void)
9498 if (cfun->machine->some_ld_name)
9499 return cfun->machine->some_ld_name;
9501 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9503 && for_each_rtx (&PATTERN (insn),
9504 rs6000_get_some_local_dynamic_name_1, 0))
9505 return cfun->machine->some_ld_name;
9510 /* Helper function for rs6000_get_some_local_dynamic_name. */
9513 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9517 if (GET_CODE (x) == SYMBOL_REF)
9519 const char *str = XSTR (x, 0);
9520 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9522 cfun->machine->some_ld_name = str;
9530 /* Write out a function code label. */
9533 rs6000_output_function_entry (FILE *file, const char *fname)
9535 if (fname[0] != '.')
9537 switch (DEFAULT_ABI)
9546 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9555 RS6000_OUTPUT_BASENAME (file, fname);
9557 assemble_name (file, fname);
9560 /* Print an operand. Recognize special options, documented below. */
9563 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
9564 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
9566 #define SMALL_DATA_RELOC "sda21"
9567 #define SMALL_DATA_REG 0
9571 print_operand (FILE *file, rtx x, int code)
9575 unsigned HOST_WIDE_INT uval;
9580 /* Write out an instruction after the call which may be replaced
9581 with glue code by the loader. This depends on the AIX version. */
9582 asm_fprintf (file, RS6000_CALL_GLUE);
9585 /* %a is output_address. */
9588 /* If X is a constant integer whose low-order 5 bits are zero,
9589 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
9590 in the AIX assembler where "sri" with a zero shift count
9591 writes a trash instruction. */
9592 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
9599 /* If constant, low-order 16 bits of constant, unsigned.
9600 Otherwise, write normally. */
9602 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9604 print_operand (file, x, 0);
9608 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9609 for 64-bit mask direction. */
9610 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
9613 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9617 /* X is a CR register. Print the number of the GT bit of the CR. */
9618 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9619 output_operand_lossage ("invalid %%E value");
9621 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9625 /* Like 'J' but get to the EQ bit. */
9626 gcc_assert (GET_CODE (x) == REG);
9628 /* Bit 1 is EQ bit. */
9629 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
9631 fprintf (file, "%d", i);
9635 /* X is a CR register. Print the number of the EQ bit of the CR */
9636 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9637 output_operand_lossage ("invalid %%E value");
9639 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
9643 /* X is a CR register. Print the shift count needed to move it
9644 to the high-order four bits. */
9645 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9646 output_operand_lossage ("invalid %%f value");
9648 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9652 /* Similar, but print the count for the rotate in the opposite
9654 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9655 output_operand_lossage ("invalid %%F value");
9657 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9661 /* X is a constant integer. If it is negative, print "m",
9662 otherwise print "z". This is to make an aze or ame insn. */
9663 if (GET_CODE (x) != CONST_INT)
9664 output_operand_lossage ("invalid %%G value");
9665 else if (INTVAL (x) >= 0)
9672 /* If constant, output low-order five bits. Otherwise, write
9675 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9677 print_operand (file, x, 0);
9681 /* If constant, output low-order six bits. Otherwise, write
9684 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
9686 print_operand (file, x, 0);
9690 /* Print `i' if this is a constant, else nothing. */
9696 /* Write the bit number in CCR for jump. */
9699 output_operand_lossage ("invalid %%j code");
9701 fprintf (file, "%d", i);
9705 /* Similar, but add one for shift count in rlinm for scc and pass
9706 scc flag to `ccr_bit'. */
9709 output_operand_lossage ("invalid %%J code");
9711 /* If we want bit 31, write a shift count of zero, not 32. */
9712 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9716 /* X must be a constant. Write the 1's complement of the
9719 output_operand_lossage ("invalid %%k value");
9721 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9725 /* X must be a symbolic constant on ELF. Write an
9726 expression suitable for an 'addi' that adds in the low 16
9728 if (GET_CODE (x) != CONST)
9730 print_operand_address (file, x);
9735 if (GET_CODE (XEXP (x, 0)) != PLUS
9736 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9737 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9738 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
9739 output_operand_lossage ("invalid %%K value");
9740 print_operand_address (file, XEXP (XEXP (x, 0), 0));
9742 /* For GNU as, there must be a non-alphanumeric character
9743 between 'l' and the number. The '-' is added by
9744 print_operand() already. */
9745 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9747 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9751 /* %l is output_asm_label. */
9754 /* Write second word of DImode or DFmode reference. Works on register
9755 or non-indexed memory only. */
9756 if (GET_CODE (x) == REG)
9757 fputs (reg_names[REGNO (x) + 1], file);
9758 else if (GET_CODE (x) == MEM)
9760 /* Handle possible auto-increment. Since it is pre-increment and
9761 we have already done it, we can just use an offset of word. */
9762 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9763 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9764 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9767 output_address (XEXP (adjust_address_nv (x, SImode,
9771 if (small_data_operand (x, GET_MODE (x)))
9772 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9773 reg_names[SMALL_DATA_REG]);
9778 /* MB value for a mask operand. */
9779 if (! mask_operand (x, SImode))
9780 output_operand_lossage ("invalid %%m value");
9782 fprintf (file, "%d", extract_MB (x));
9786 /* ME value for a mask operand. */
9787 if (! mask_operand (x, SImode))
9788 output_operand_lossage ("invalid %%M value");
9790 fprintf (file, "%d", extract_ME (x));
9793 /* %n outputs the negative of its operand. */
9796 /* Write the number of elements in the vector times 4. */
9797 if (GET_CODE (x) != PARALLEL)
9798 output_operand_lossage ("invalid %%N value");
9800 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9804 /* Similar, but subtract 1 first. */
9805 if (GET_CODE (x) != PARALLEL)
9806 output_operand_lossage ("invalid %%O value");
9808 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9812 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9814 || INT_LOWPART (x) < 0
9815 || (i = exact_log2 (INT_LOWPART (x))) < 0)
9816 output_operand_lossage ("invalid %%p value");
9818 fprintf (file, "%d", i);
9822 /* The operand must be an indirect memory reference. The result
9823 is the register name. */
9824 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9825 || REGNO (XEXP (x, 0)) >= 32)
9826 output_operand_lossage ("invalid %%P value");
9828 fputs (reg_names[REGNO (XEXP (x, 0))], file);
9832 /* This outputs the logical code corresponding to a boolean
9833 expression. The expression may have one or both operands
9834 negated (if one, only the first one). For condition register
9835 logical operations, it will also treat the negated
9836 CR codes as NOTs, but not handle NOTs of them. */
9838 const char *const *t = 0;
9840 enum rtx_code code = GET_CODE (x);
9841 static const char * const tbl[3][3] = {
9842 { "and", "andc", "nor" },
9843 { "or", "orc", "nand" },
9844 { "xor", "eqv", "xor" } };
9848 else if (code == IOR)
9850 else if (code == XOR)
9853 output_operand_lossage ("invalid %%q value");
9855 if (GET_CODE (XEXP (x, 0)) != NOT)
9859 if (GET_CODE (XEXP (x, 1)) == NOT)
9877 /* X is a CR register. Print the mask for `mtcrf'. */
9878 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9879 output_operand_lossage ("invalid %%R value");
9881 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9885 /* Low 5 bits of 32 - value */
9887 output_operand_lossage ("invalid %%s value");
9889 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9893 /* PowerPC64 mask position. All 0's is excluded.
9894 CONST_INT 32-bit mask is considered sign-extended so any
9895 transition must occur within the CONST_INT, not on the boundary. */
9896 if (! mask_operand (x, DImode))
9897 output_operand_lossage ("invalid %%S value");
9899 uval = INT_LOWPART (x);
9901 if (uval & 1) /* Clear Left */
9903 #if HOST_BITS_PER_WIDE_INT > 64
9904 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9908 else /* Clear Right */
9911 #if HOST_BITS_PER_WIDE_INT > 64
9912 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9918 gcc_assert (i >= 0);
9919 fprintf (file, "%d", i);
9923 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
9924 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
9926 /* Bit 3 is OV bit. */
9927 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9929 /* If we want bit 31, write a shift count of zero, not 32. */
9930 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9934 /* Print the symbolic name of a branch target register. */
9935 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9936 && REGNO (x) != COUNT_REGISTER_REGNUM))
9937 output_operand_lossage ("invalid %%T value");
9938 else if (REGNO (x) == LINK_REGISTER_REGNUM)
9939 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9941 fputs ("ctr", file);
9945 /* High-order 16 bits of constant for use in unsigned operand. */
9947 output_operand_lossage ("invalid %%u value");
9949 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9950 (INT_LOWPART (x) >> 16) & 0xffff);
9954 /* High-order 16 bits of constant for use in signed operand. */
9956 output_operand_lossage ("invalid %%v value");
9958 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9959 (INT_LOWPART (x) >> 16) & 0xffff);
9963 /* Print `u' if this has an auto-increment or auto-decrement. */
9964 if (GET_CODE (x) == MEM
9965 && (GET_CODE (XEXP (x, 0)) == PRE_INC
9966 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
9971 /* Print the trap code for this operand. */
9972 switch (GET_CODE (x))
9975 fputs ("eq", file); /* 4 */
9978 fputs ("ne", file); /* 24 */
9981 fputs ("lt", file); /* 16 */
9984 fputs ("le", file); /* 20 */
9987 fputs ("gt", file); /* 8 */
9990 fputs ("ge", file); /* 12 */
9993 fputs ("llt", file); /* 2 */
9996 fputs ("lle", file); /* 6 */
9999 fputs ("lgt", file); /* 1 */
10002 fputs ("lge", file); /* 5 */
10005 gcc_unreachable ();
10010 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10013 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10014 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10016 print_operand (file, x, 0);
10020 /* MB value for a PowerPC64 rldic operand. */
10021 val = (GET_CODE (x) == CONST_INT
10022 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10027 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10028 if ((val <<= 1) < 0)
10031 #if HOST_BITS_PER_WIDE_INT == 32
10032 if (GET_CODE (x) == CONST_INT && i >= 0)
10033 i += 32; /* zero-extend high-part was all 0's */
10034 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10036 val = CONST_DOUBLE_LOW (x);
10042 for ( ; i < 64; i++)
10043 if ((val <<= 1) < 0)
10048 fprintf (file, "%d", i + 1);
10052 if (GET_CODE (x) == MEM
10053 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10058 /* Like 'L', for third word of TImode */
10059 if (GET_CODE (x) == REG)
10060 fputs (reg_names[REGNO (x) + 2], file);
10061 else if (GET_CODE (x) == MEM)
10063 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10064 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10065 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10067 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10068 if (small_data_operand (x, GET_MODE (x)))
10069 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10070 reg_names[SMALL_DATA_REG]);
10075 /* X is a SYMBOL_REF. Write out the name preceded by a
10076 period and without any trailing data in brackets. Used for function
10077 names. If we are configured for System V (or the embedded ABI) on
10078 the PowerPC, do not emit the period, since those systems do not use
10079 TOCs and the like. */
10080 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10082 /* Mark the decl as referenced so that cgraph will output the
10084 if (SYMBOL_REF_DECL (x))
10085 mark_decl_referenced (SYMBOL_REF_DECL (x));
10087 /* For macho, check to see if we need a stub. */
10090 const char *name = XSTR (x, 0);
10092 if (MACHOPIC_INDIRECT
10093 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10094 name = machopic_indirection_name (x, /*stub_p=*/true);
10096 assemble_name (file, name);
10098 else if (!DOT_SYMBOLS)
10099 assemble_name (file, XSTR (x, 0));
10101 rs6000_output_function_entry (file, XSTR (x, 0));
10105 /* Like 'L', for last word of TImode. */
10106 if (GET_CODE (x) == REG)
10107 fputs (reg_names[REGNO (x) + 3], file);
10108 else if (GET_CODE (x) == MEM)
10110 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10111 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10112 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10114 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10115 if (small_data_operand (x, GET_MODE (x)))
10116 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10117 reg_names[SMALL_DATA_REG]);
10121 /* Print AltiVec or SPE memory operand. */
10126 gcc_assert (GET_CODE (x) == MEM);
10132 /* Handle [reg]. */
10133 if (GET_CODE (tmp) == REG)
10135 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10138 /* Handle [reg+UIMM]. */
10139 else if (GET_CODE (tmp) == PLUS &&
10140 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10144 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10146 x = INTVAL (XEXP (tmp, 1));
10147 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10151 /* Fall through. Must be [reg+reg]. */
10154 && GET_CODE (tmp) == AND
10155 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10156 && INTVAL (XEXP (tmp, 1)) == -16)
10157 tmp = XEXP (tmp, 0);
10158 if (GET_CODE (tmp) == REG)
10159 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10162 gcc_assert (GET_CODE (tmp) == PLUS
10163 && GET_CODE (XEXP (tmp, 1)) == REG);
10165 if (REGNO (XEXP (tmp, 0)) == 0)
10166 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10167 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10169 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10170 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10176 if (GET_CODE (x) == REG)
10177 fprintf (file, "%s", reg_names[REGNO (x)]);
10178 else if (GET_CODE (x) == MEM)
10180 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10181 know the width from the mode. */
10182 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10183 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10184 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10185 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10186 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10187 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10189 output_address (XEXP (x, 0));
10192 output_addr_const (file, x);
10196 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10200 output_operand_lossage ("invalid %%xn code");
10204 /* Print the address of an operand. */
10207 print_operand_address (FILE *file, rtx x)
10209 if (GET_CODE (x) == REG)
10210 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10211 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10212 || GET_CODE (x) == LABEL_REF)
10214 output_addr_const (file, x);
10215 if (small_data_operand (x, GET_MODE (x)))
10216 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10217 reg_names[SMALL_DATA_REG]);
10219 gcc_assert (!TARGET_TOC);
10221 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10223 if (REGNO (XEXP (x, 0)) == 0)
10224 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10225 reg_names[ REGNO (XEXP (x, 0)) ]);
10227 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10228 reg_names[ REGNO (XEXP (x, 1)) ]);
10230 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10231 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10232 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10234 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10235 && CONSTANT_P (XEXP (x, 1)))
10237 output_addr_const (file, XEXP (x, 1));
10238 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10242 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10243 && CONSTANT_P (XEXP (x, 1)))
10245 fprintf (file, "lo16(");
10246 output_addr_const (file, XEXP (x, 1));
10247 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10250 else if (legitimate_constant_pool_address_p (x))
10252 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10254 rtx contains_minus = XEXP (x, 1);
10258 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10259 turn it into (sym) for output_addr_const. */
10260 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10261 contains_minus = XEXP (contains_minus, 0);
10263 minus = XEXP (contains_minus, 0);
10264 symref = XEXP (minus, 0);
10265 XEXP (contains_minus, 0) = symref;
10270 name = XSTR (symref, 0);
10271 newname = alloca (strlen (name) + sizeof ("@toc"));
10272 strcpy (newname, name);
10273 strcat (newname, "@toc");
10274 XSTR (symref, 0) = newname;
10276 output_addr_const (file, XEXP (x, 1));
10278 XSTR (symref, 0) = name;
10279 XEXP (contains_minus, 0) = minus;
10282 output_addr_const (file, XEXP (x, 1));
10284 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10287 gcc_unreachable ();
10290 /* Target hook for assembling integer objects. The PowerPC version has
10291 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10292 is defined. It also needs to handle DI-mode objects on 64-bit
10296 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10298 #ifdef RELOCATABLE_NEEDS_FIXUP
10299 /* Special handling for SI values. */
10300 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10302 extern int in_toc_section (void);
10303 static int recurse = 0;
10305 /* For -mrelocatable, we mark all addresses that need to be fixed up
10306 in the .fixup section. */
10307 if (TARGET_RELOCATABLE
10308 && !in_toc_section ()
10309 && !in_text_section ()
10310 && !in_unlikely_text_section ()
10312 && GET_CODE (x) != CONST_INT
10313 && GET_CODE (x) != CONST_DOUBLE
10319 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10321 ASM_OUTPUT_LABEL (asm_out_file, buf);
10322 fprintf (asm_out_file, "\t.long\t(");
10323 output_addr_const (asm_out_file, x);
10324 fprintf (asm_out_file, ")@fixup\n");
10325 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10326 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10327 fprintf (asm_out_file, "\t.long\t");
10328 assemble_name (asm_out_file, buf);
10329 fprintf (asm_out_file, "\n\t.previous\n");
10333 /* Remove initial .'s to turn a -mcall-aixdesc function
10334 address into the address of the descriptor, not the function
10336 else if (GET_CODE (x) == SYMBOL_REF
10337 && XSTR (x, 0)[0] == '.'
10338 && DEFAULT_ABI == ABI_AIX)
10340 const char *name = XSTR (x, 0);
10341 while (*name == '.')
10344 fprintf (asm_out_file, "\t.long\t%s\n", name);
10348 #endif /* RELOCATABLE_NEEDS_FIXUP */
10349 return default_assemble_integer (x, size, aligned_p);
10352 #ifdef HAVE_GAS_HIDDEN
10353 /* Emit an assembler directive to set symbol visibility for DECL to
10354 VISIBILITY_TYPE. */
10357 rs6000_assemble_visibility (tree decl, int vis)
10359 /* Functions need to have their entry point symbol visibility set as
10360 well as their descriptor symbol visibility. */
10361 if (DEFAULT_ABI == ABI_AIX
10363 && TREE_CODE (decl) == FUNCTION_DECL)
10365 static const char * const visibility_types[] = {
10366 NULL, "internal", "hidden", "protected"
10369 const char *name, *type;
10371 name = ((* targetm.strip_name_encoding)
10372 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10373 type = visibility_types[vis];
10375 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10376 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10379 default_assemble_visibility (decl, vis);
10384 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10386 /* Reversal of FP compares takes care -- an ordered compare
10387 becomes an unordered compare and vice versa. */
10388 if (mode == CCFPmode
10389 && (!flag_finite_math_only
10390 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10391 || code == UNEQ || code == LTGT))
10392 return reverse_condition_maybe_unordered (code);
10394 return reverse_condition (code);
10397 /* Generate a compare for CODE. Return a brand-new rtx that
10398 represents the result of the compare. */
10401 rs6000_generate_compare (enum rtx_code code)
10403 enum machine_mode comp_mode;
10404 rtx compare_result;
10406 if (rs6000_compare_fp_p)
10407 comp_mode = CCFPmode;
10408 else if (code == GTU || code == LTU
10409 || code == GEU || code == LEU)
10410 comp_mode = CCUNSmode;
10411 else if ((code == EQ || code == NE)
10412 && GET_CODE (rs6000_compare_op0) == SUBREG
10413 && GET_CODE (rs6000_compare_op1) == SUBREG
10414 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10415 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10416 /* These are unsigned values, perhaps there will be a later
10417 ordering compare that can be shared with this one.
10418 Unfortunately we cannot detect the signedness of the operands
10419 for non-subregs. */
10420 comp_mode = CCUNSmode;
10422 comp_mode = CCmode;
10424 /* First, the compare. */
10425 compare_result = gen_reg_rtx (comp_mode);
10427 /* SPE FP compare instructions on the GPRs. Yuck! */
10428 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10429 && rs6000_compare_fp_p)
10431 rtx cmp, or_result, compare_result2;
10432 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10434 if (op_mode == VOIDmode)
10435 op_mode = GET_MODE (rs6000_compare_op1);
10437 /* Note: The E500 comparison instructions set the GT bit (x +
10438 1), on success. This explains the mess. */
10442 case EQ: case UNEQ: case NE: case LTGT:
10446 cmp = flag_unsafe_math_optimizations
10447 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10448 rs6000_compare_op1)
10449 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10450 rs6000_compare_op1);
10454 cmp = flag_unsafe_math_optimizations
10455 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10456 rs6000_compare_op1)
10457 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10458 rs6000_compare_op1);
10462 gcc_unreachable ();
10466 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10470 cmp = flag_unsafe_math_optimizations
10471 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10472 rs6000_compare_op1)
10473 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10474 rs6000_compare_op1);
10478 cmp = flag_unsafe_math_optimizations
10479 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10480 rs6000_compare_op1)
10481 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10482 rs6000_compare_op1);
10486 gcc_unreachable ();
10490 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
10494 cmp = flag_unsafe_math_optimizations
10495 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10496 rs6000_compare_op1)
10497 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10498 rs6000_compare_op1);
10502 cmp = flag_unsafe_math_optimizations
10503 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10504 rs6000_compare_op1)
10505 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10506 rs6000_compare_op1);
10510 gcc_unreachable ();
10514 gcc_unreachable ();
10517 /* Synthesize LE and GE from LT/GT || EQ. */
10518 if (code == LE || code == GE || code == LEU || code == GEU)
10524 case LE: code = LT; break;
10525 case GE: code = GT; break;
10526 case LEU: code = LT; break;
10527 case GEU: code = GT; break;
10528 default: gcc_unreachable ();
10531 compare_result2 = gen_reg_rtx (CCFPmode);
10537 cmp = flag_unsafe_math_optimizations
10538 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10539 rs6000_compare_op1)
10540 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10541 rs6000_compare_op1);
10545 cmp = flag_unsafe_math_optimizations
10546 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
10547 rs6000_compare_op1)
10548 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
10549 rs6000_compare_op1);
10553 gcc_unreachable ();
10557 /* OR them together. */
10558 or_result = gen_reg_rtx (CCFPmode);
10559 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
10561 compare_result = or_result;
10566 if (code == NE || code == LTGT)
10576 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
10577 CLOBBERs to match cmptf_internal2 pattern. */
10578 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
10579 && GET_MODE (rs6000_compare_op0) == TFmode
10580 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10581 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
10582 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10584 gen_rtx_SET (VOIDmode,
10586 gen_rtx_COMPARE (comp_mode,
10587 rs6000_compare_op0,
10588 rs6000_compare_op1)),
10589 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10590 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10591 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10592 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10593 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10594 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10595 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10596 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
10597 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
10598 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
10600 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
10601 comp_mode = CCEQmode;
10602 compare_result = gen_reg_rtx (CCEQmode);
10604 emit_insn (gen_stack_protect_testdi (compare_result,
10605 rs6000_compare_op0, op1));
10607 emit_insn (gen_stack_protect_testsi (compare_result,
10608 rs6000_compare_op0, op1));
10611 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
10612 gen_rtx_COMPARE (comp_mode,
10613 rs6000_compare_op0,
10614 rs6000_compare_op1)));
10617 /* Some kinds of FP comparisons need an OR operation;
10618 under flag_finite_math_only we don't bother. */
10619 if (rs6000_compare_fp_p
10620 && !flag_finite_math_only
10621 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
10622 && (code == LE || code == GE
10623 || code == UNEQ || code == LTGT
10624 || code == UNGT || code == UNLT))
10626 enum rtx_code or1, or2;
10627 rtx or1_rtx, or2_rtx, compare2_rtx;
10628 rtx or_result = gen_reg_rtx (CCEQmode);
10632 case LE: or1 = LT; or2 = EQ; break;
10633 case GE: or1 = GT; or2 = EQ; break;
10634 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
10635 case LTGT: or1 = LT; or2 = GT; break;
10636 case UNGT: or1 = UNORDERED; or2 = GT; break;
10637 case UNLT: or1 = UNORDERED; or2 = LT; break;
10638 default: gcc_unreachable ();
10640 validate_condition_mode (or1, comp_mode);
10641 validate_condition_mode (or2, comp_mode);
10642 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10643 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
10644 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10645 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10647 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10649 compare_result = or_result;
10653 validate_condition_mode (code, GET_MODE (compare_result));
10655 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
10659 /* Emit the RTL for an sCOND pattern. */
10662 rs6000_emit_sCOND (enum rtx_code code, rtx result)
10665 enum machine_mode op_mode;
10666 enum rtx_code cond_code;
10668 condition_rtx = rs6000_generate_compare (code);
10669 cond_code = GET_CODE (condition_rtx);
10671 if (TARGET_E500 && rs6000_compare_fp_p
10672 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10676 PUT_MODE (condition_rtx, SImode);
10677 t = XEXP (condition_rtx, 0);
10679 gcc_assert (cond_code == NE || cond_code == EQ);
10681 if (cond_code == NE)
10682 emit_insn (gen_e500_flip_gt_bit (t, t));
10684 emit_insn (gen_move_from_CR_gt_bit (result, t));
10688 if (cond_code == NE
10689 || cond_code == GE || cond_code == LE
10690 || cond_code == GEU || cond_code == LEU
10691 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10693 rtx not_result = gen_reg_rtx (CCEQmode);
10694 rtx not_op, rev_cond_rtx;
10695 enum machine_mode cc_mode;
10697 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10699 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
10700 SImode, XEXP (condition_rtx, 0), const0_rtx);
10701 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10702 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10703 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10706 op_mode = GET_MODE (rs6000_compare_op0);
10707 if (op_mode == VOIDmode)
10708 op_mode = GET_MODE (rs6000_compare_op1);
10710 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10712 PUT_MODE (condition_rtx, DImode);
10713 convert_move (result, condition_rtx, 0);
10717 PUT_MODE (condition_rtx, SImode);
10718 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10722 /* Emit a branch of kind CODE to location LOC. */
10725 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
10727 rtx condition_rtx, loc_ref;
10729 condition_rtx = rs6000_generate_compare (code);
10730 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10731 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10732 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10733 loc_ref, pc_rtx)));
10736 /* Return the string to output a conditional branch to LABEL, which is
10737 the operand number of the label, or -1 if the branch is really a
10738 conditional return.
10740 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10741 condition code register and its mode specifies what kind of
10742 comparison we made.
10744 REVERSED is nonzero if we should reverse the sense of the comparison.
10746 INSN is the insn. */
10749 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
10751 static char string[64];
10752 enum rtx_code code = GET_CODE (op);
10753 rtx cc_reg = XEXP (op, 0);
10754 enum machine_mode mode = GET_MODE (cc_reg);
10755 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
10756 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
10757 int really_reversed = reversed ^ need_longbranch;
10763 validate_condition_mode (code, mode);
10765 /* Work out which way this really branches. We could use
10766 reverse_condition_maybe_unordered here always but this
10767 makes the resulting assembler clearer. */
10768 if (really_reversed)
10770 /* Reversal of FP compares takes care -- an ordered compare
10771 becomes an unordered compare and vice versa. */
10772 if (mode == CCFPmode)
10773 code = reverse_condition_maybe_unordered (code);
10775 code = reverse_condition (code);
10778 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
10780 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10785 /* Opposite of GT. */
10794 gcc_unreachable ();
10800 /* Not all of these are actually distinct opcodes, but
10801 we distinguish them for clarity of the resulting assembler. */
10802 case NE: case LTGT:
10803 ccode = "ne"; break;
10804 case EQ: case UNEQ:
10805 ccode = "eq"; break;
10807 ccode = "ge"; break;
10808 case GT: case GTU: case UNGT:
10809 ccode = "gt"; break;
10811 ccode = "le"; break;
10812 case LT: case LTU: case UNLT:
10813 ccode = "lt"; break;
10814 case UNORDERED: ccode = "un"; break;
10815 case ORDERED: ccode = "nu"; break;
10816 case UNGE: ccode = "nl"; break;
10817 case UNLE: ccode = "ng"; break;
10819 gcc_unreachable ();
10822 /* Maybe we have a guess as to how likely the branch is.
10823 The old mnemonics don't have a way to specify this information. */
10825 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10826 if (note != NULL_RTX)
10828 /* PROB is the difference from 50%. */
10829 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
10831 /* Only hint for highly probable/improbable branches on newer
10832 cpus as static prediction overrides processor dynamic
10833 prediction. For older cpus we may as well always hint, but
10834 assume not taken for branches that are very close to 50% as a
10835 mispredicted taken branch is more expensive than a
10836 mispredicted not-taken branch. */
10837 if (rs6000_always_hint
10838 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10840 if (abs (prob) > REG_BR_PROB_BASE / 20
10841 && ((prob > 0) ^ need_longbranch))
10849 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
10851 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
10853 /* We need to escape any '%' characters in the reg_names string.
10854 Assume they'd only be the first character.... */
10855 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10857 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
10861 /* If the branch distance was too far, we may have to use an
10862 unconditional branch to go the distance. */
10863 if (need_longbranch)
10864 s += sprintf (s, ",$+8\n\tb %s", label);
10866 s += sprintf (s, ",%s", label);
10872 /* Return the string to flip the GT bit on a CR. */
10874 output_e500_flip_gt_bit (rtx dst, rtx src)
10876 static char string[64];
10879 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
10880 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
10883 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
10884 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
10886 sprintf (string, "crnot %d,%d", a, b);
10890 /* Return insn index for the vector compare instruction for given CODE,
10891 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
10895 get_vec_cmp_insn (enum rtx_code code,
10896 enum machine_mode dest_mode,
10897 enum machine_mode op_mode)
10899 if (!TARGET_ALTIVEC)
10900 return INSN_NOT_AVAILABLE;
10905 if (dest_mode == V16QImode && op_mode == V16QImode)
10906 return UNSPEC_VCMPEQUB;
10907 if (dest_mode == V8HImode && op_mode == V8HImode)
10908 return UNSPEC_VCMPEQUH;
10909 if (dest_mode == V4SImode && op_mode == V4SImode)
10910 return UNSPEC_VCMPEQUW;
10911 if (dest_mode == V4SImode && op_mode == V4SFmode)
10912 return UNSPEC_VCMPEQFP;
10915 if (dest_mode == V4SImode && op_mode == V4SFmode)
10916 return UNSPEC_VCMPGEFP;
10918 if (dest_mode == V16QImode && op_mode == V16QImode)
10919 return UNSPEC_VCMPGTSB;
10920 if (dest_mode == V8HImode && op_mode == V8HImode)
10921 return UNSPEC_VCMPGTSH;
10922 if (dest_mode == V4SImode && op_mode == V4SImode)
10923 return UNSPEC_VCMPGTSW;
10924 if (dest_mode == V4SImode && op_mode == V4SFmode)
10925 return UNSPEC_VCMPGTFP;
10928 if (dest_mode == V16QImode && op_mode == V16QImode)
10929 return UNSPEC_VCMPGTUB;
10930 if (dest_mode == V8HImode && op_mode == V8HImode)
10931 return UNSPEC_VCMPGTUH;
10932 if (dest_mode == V4SImode && op_mode == V4SImode)
10933 return UNSPEC_VCMPGTUW;
10938 return INSN_NOT_AVAILABLE;
10941 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
10942 DMODE is expected destination mode. This is a recursive function. */
10945 rs6000_emit_vector_compare (enum rtx_code rcode,
10947 enum machine_mode dmode)
10951 enum machine_mode dest_mode;
10952 enum machine_mode op_mode = GET_MODE (op1);
10954 gcc_assert (TARGET_ALTIVEC);
10955 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
10957 /* Floating point vector compare instructions uses destination V4SImode.
10958 Move destination to appropriate mode later. */
10959 if (dmode == V4SFmode)
10960 dest_mode = V4SImode;
10964 mask = gen_reg_rtx (dest_mode);
10965 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10967 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10969 bool swap_operands = false;
10970 bool try_again = false;
10975 swap_operands = true;
10980 swap_operands = true;
10984 /* Treat A != B as ~(A==B). */
10986 enum insn_code nor_code;
10987 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10990 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
10991 gcc_assert (nor_code != CODE_FOR_nothing);
10992 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
10994 if (dmode != dest_mode)
10996 rtx temp = gen_reg_rtx (dest_mode);
10997 convert_move (temp, mask, 0);
11007 /* Try GT/GTU/LT/LTU OR EQ */
11010 enum insn_code ior_code;
11011 enum rtx_code new_code;
11032 gcc_unreachable ();
11035 c_rtx = rs6000_emit_vector_compare (new_code,
11036 op0, op1, dest_mode);
11037 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11040 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11041 gcc_assert (ior_code != CODE_FOR_nothing);
11042 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11043 if (dmode != dest_mode)
11045 rtx temp = gen_reg_rtx (dest_mode);
11046 convert_move (temp, mask, 0);
11053 gcc_unreachable ();
11058 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11059 /* You only get two chances. */
11060 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11072 emit_insn (gen_rtx_SET (VOIDmode, mask,
11073 gen_rtx_UNSPEC (dest_mode,
11074 gen_rtvec (2, op0, op1),
11076 if (dmode != dest_mode)
11078 rtx temp = gen_reg_rtx (dest_mode);
11079 convert_move (temp, mask, 0);
11085 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11086 valid insn doesn exist for given mode. */
11089 get_vsel_insn (enum machine_mode mode)
11094 return UNSPEC_VSEL4SI;
11097 return UNSPEC_VSEL4SF;
11100 return UNSPEC_VSEL8HI;
11103 return UNSPEC_VSEL16QI;
11106 return INSN_NOT_AVAILABLE;
11109 return INSN_NOT_AVAILABLE;
11112 /* Emit vector select insn where DEST is destination using
11113 operands OP1, OP2 and MASK. */
11116 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11119 enum machine_mode dest_mode = GET_MODE (dest);
11120 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11122 temp = gen_reg_rtx (dest_mode);
11124 /* For each vector element, select op1 when mask is 1 otherwise
11126 t = gen_rtx_SET (VOIDmode, temp,
11127 gen_rtx_UNSPEC (dest_mode,
11128 gen_rtvec (3, op2, op1, mask),
11131 emit_move_insn (dest, temp);
11135 /* Emit vector conditional expression.
11136 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11137 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11140 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11141 rtx cond, rtx cc_op0, rtx cc_op1)
11143 enum machine_mode dest_mode = GET_MODE (dest);
11144 enum rtx_code rcode = GET_CODE (cond);
11147 if (!TARGET_ALTIVEC)
11150 /* Get the vector mask for the given relational operations. */
11151 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11153 rs6000_emit_vector_select (dest, op1, op2, mask);
11158 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11159 operands of the last comparison is nonzero/true, FALSE_COND if it
11160 is zero/false. Return 0 if the hardware has no such operation. */
11163 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11165 enum rtx_code code = GET_CODE (op);
11166 rtx op0 = rs6000_compare_op0;
11167 rtx op1 = rs6000_compare_op1;
11168 REAL_VALUE_TYPE c1;
11169 enum machine_mode compare_mode = GET_MODE (op0);
11170 enum machine_mode result_mode = GET_MODE (dest);
11172 bool is_against_zero;
11174 /* These modes should always match. */
11175 if (GET_MODE (op1) != compare_mode
11176 /* In the isel case however, we can use a compare immediate, so
11177 op1 may be a small constant. */
11178 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11180 if (GET_MODE (true_cond) != result_mode)
11182 if (GET_MODE (false_cond) != result_mode)
11185 /* First, work out if the hardware can do this at all, or
11186 if it's too slow.... */
11187 if (! rs6000_compare_fp_p)
11190 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11193 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11194 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11197 is_against_zero = op1 == CONST0_RTX (compare_mode);
11199 /* A floating-point subtract might overflow, underflow, or produce
11200 an inexact result, thus changing the floating-point flags, so it
11201 can't be generated if we care about that. It's safe if one side
11202 of the construct is zero, since then no subtract will be
11204 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
11205 && flag_trapping_math && ! is_against_zero)
11208 /* Eliminate half of the comparisons by switching operands, this
11209 makes the remaining code simpler. */
11210 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11211 || code == LTGT || code == LT || code == UNLE)
11213 code = reverse_condition_maybe_unordered (code);
11215 true_cond = false_cond;
11219 /* UNEQ and LTGT take four instructions for a comparison with zero,
11220 it'll probably be faster to use a branch here too. */
11221 if (code == UNEQ && HONOR_NANS (compare_mode))
11224 if (GET_CODE (op1) == CONST_DOUBLE)
11225 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11227 /* We're going to try to implement comparisons by performing
11228 a subtract, then comparing against zero. Unfortunately,
11229 Inf - Inf is NaN which is not zero, and so if we don't
11230 know that the operand is finite and the comparison
11231 would treat EQ different to UNORDERED, we can't do it. */
11232 if (HONOR_INFINITIES (compare_mode)
11233 && code != GT && code != UNGE
11234 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11235 /* Constructs of the form (a OP b ? a : b) are safe. */
11236 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11237 || (! rtx_equal_p (op0, true_cond)
11238 && ! rtx_equal_p (op1, true_cond))))
11241 /* At this point we know we can use fsel. */
11243 /* Reduce the comparison to a comparison against zero. */
11244 if (! is_against_zero)
11246 temp = gen_reg_rtx (compare_mode);
11247 emit_insn (gen_rtx_SET (VOIDmode, temp,
11248 gen_rtx_MINUS (compare_mode, op0, op1)));
11250 op1 = CONST0_RTX (compare_mode);
11253 /* If we don't care about NaNs we can reduce some of the comparisons
11254 down to faster ones. */
11255 if (! HONOR_NANS (compare_mode))
11261 true_cond = false_cond;
11274 /* Now, reduce everything down to a GE. */
11281 temp = gen_reg_rtx (compare_mode);
11282 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11287 temp = gen_reg_rtx (compare_mode);
11288 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11293 temp = gen_reg_rtx (compare_mode);
11294 emit_insn (gen_rtx_SET (VOIDmode, temp,
11295 gen_rtx_NEG (compare_mode,
11296 gen_rtx_ABS (compare_mode, op0))));
11301 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11302 temp = gen_reg_rtx (result_mode);
11303 emit_insn (gen_rtx_SET (VOIDmode, temp,
11304 gen_rtx_IF_THEN_ELSE (result_mode,
11305 gen_rtx_GE (VOIDmode,
11307 true_cond, false_cond)));
11308 false_cond = true_cond;
11311 temp = gen_reg_rtx (compare_mode);
11312 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11317 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11318 temp = gen_reg_rtx (result_mode);
11319 emit_insn (gen_rtx_SET (VOIDmode, temp,
11320 gen_rtx_IF_THEN_ELSE (result_mode,
11321 gen_rtx_GE (VOIDmode,
11323 true_cond, false_cond)));
11324 true_cond = false_cond;
11327 temp = gen_reg_rtx (compare_mode);
11328 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11333 gcc_unreachable ();
11336 emit_insn (gen_rtx_SET (VOIDmode, dest,
11337 gen_rtx_IF_THEN_ELSE (result_mode,
11338 gen_rtx_GE (VOIDmode,
11340 true_cond, false_cond)));
11344 /* Same as above, but for ints (isel). */
11347 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11349 rtx condition_rtx, cr;
11351 /* All isel implementations thus far are 32-bits. */
11352 if (GET_MODE (rs6000_compare_op0) != SImode)
11355 /* We still have to do the compare, because isel doesn't do a
11356 compare, it just looks at the CRx bits set by a previous compare
11358 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11359 cr = XEXP (condition_rtx, 0);
11361 if (GET_MODE (cr) == CCmode)
11362 emit_insn (gen_isel_signed (dest, condition_rtx,
11363 true_cond, false_cond, cr));
11365 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11366 true_cond, false_cond, cr));
11372 output_isel (rtx *operands)
11374 enum rtx_code code;
11376 code = GET_CODE (operands[1]);
11377 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11379 PUT_CODE (operands[1], reverse_condition (code));
11380 return "isel %0,%3,%2,%j1";
11383 return "isel %0,%2,%3,%j1";
11387 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11389 enum machine_mode mode = GET_MODE (op0);
11393 if (code == SMAX || code == SMIN)
11398 if (code == SMAX || code == UMAX)
11399 target = emit_conditional_move (dest, c, op0, op1, mode,
11400 op0, op1, mode, 0);
11402 target = emit_conditional_move (dest, c, op0, op1, mode,
11403 op1, op0, mode, 0);
11404 gcc_assert (target);
11405 if (target != dest)
11406 emit_move_insn (dest, target);
11409 /* Emit instructions to perform a load-reserved/store-conditional operation.
11410 The operation performed is an atomic
11411 (set M (CODE:MODE M OP))
11412 If not NULL, BEFORE is atomically set to M before the operation, and
11413 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11414 If SYNC_P then a memory barrier is emitted before the operation.
11415 Either OP or M may be wrapped in a NOT operation. */
11418 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
11419 rtx m, rtx op, rtx before_param, rtx after_param,
11422 enum machine_mode used_mode;
11423 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
11426 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
11427 rtx shift = NULL_RTX;
11430 emit_insn (gen_memory_barrier ());
11432 if (GET_CODE (m) == NOT)
11433 used_m = XEXP (m, 0);
11437 /* If this is smaller than SImode, we'll have to use SImode with
11439 if (mode == QImode || mode == HImode)
11443 if (MEM_ALIGN (used_m) >= 32)
11446 if (BYTES_BIG_ENDIAN)
11447 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
11449 shift = GEN_INT (ishift);
11453 rtx addrSI, aligned_addr;
11454 int shift_mask = mode == QImode ? 0x18 : 0x10;
11456 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
11457 XEXP (used_m, 0)));
11458 shift = gen_reg_rtx (SImode);
11460 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
11461 GEN_INT (shift_mask)));
11462 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
11464 aligned_addr = expand_binop (Pmode, and_optab,
11466 GEN_INT (-4), NULL_RTX,
11467 1, OPTAB_LIB_WIDEN);
11468 used_m = change_address (used_m, SImode, aligned_addr);
11469 set_mem_align (used_m, 32);
11470 /* It's safe to keep the old alias set of USED_M, because
11471 the operation is atomic and only affects the original
11473 if (GET_CODE (m) == NOT)
11474 m = gen_rtx_NOT (SImode, used_m);
11479 if (GET_CODE (op) == NOT)
11481 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
11482 oldop = gen_rtx_NOT (SImode, oldop);
11485 oldop = lowpart_subreg (SImode, op, mode);
11490 newop = expand_binop (SImode, and_optab,
11491 oldop, GEN_INT (imask), NULL_RTX,
11492 1, OPTAB_LIB_WIDEN);
11493 emit_insn (gen_ashlsi3 (newop, newop, shift));
11497 newop = expand_binop (SImode, ior_optab,
11498 oldop, GEN_INT (~imask), NULL_RTX,
11499 1, OPTAB_LIB_WIDEN);
11500 emit_insn (gen_rotlsi3 (newop, newop, shift));
11507 newop = expand_binop (SImode, and_optab,
11508 oldop, GEN_INT (imask), NULL_RTX,
11509 1, OPTAB_LIB_WIDEN);
11510 emit_insn (gen_ashlsi3 (newop, newop, shift));
11512 mask = gen_reg_rtx (SImode);
11513 emit_move_insn (mask, GEN_INT (imask));
11514 emit_insn (gen_ashlsi3 (mask, mask, shift));
11516 newop = gen_rtx_AND (SImode, gen_rtx_PLUS (SImode, m, newop),
11518 newop = gen_rtx_IOR (SImode, newop,
11519 gen_rtx_AND (SImode,
11520 gen_rtx_NOT (SImode, mask),
11526 gcc_unreachable ();
11529 if (GET_CODE (m) == NOT)
11533 mask = gen_reg_rtx (SImode);
11534 emit_move_insn (mask, GEN_INT (imask));
11535 emit_insn (gen_ashlsi3 (mask, mask, shift));
11537 xorm = gen_rtx_XOR (SImode, used_m, mask);
11538 /* Depending on the value of 'op', the XOR or the operation might
11539 be able to be simplified away. */
11540 newop = simplify_gen_binary (code, SImode, xorm, newop);
11543 used_mode = SImode;
11544 before = gen_reg_rtx (used_mode);
11545 after = gen_reg_rtx (used_mode);
11550 before = before_param;
11551 after = after_param;
11553 if (before == NULL_RTX)
11554 before = gen_reg_rtx (used_mode);
11555 if (after == NULL_RTX)
11556 after = gen_reg_rtx (used_mode);
11559 if ((code == PLUS || GET_CODE (m) == NOT) && used_mode != mode)
11560 the_op = op; /* Computed above. */
11561 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
11562 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
11564 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
11566 set_after = gen_rtx_SET (VOIDmode, after, the_op);
11567 set_before = gen_rtx_SET (VOIDmode, before, used_m);
11568 set_atomic = gen_rtx_SET (VOIDmode, used_m,
11569 gen_rtx_UNSPEC (used_mode, gen_rtvec (1, the_op),
11571 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
11573 if (code == PLUS && used_mode != mode)
11574 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
11575 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
11577 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
11578 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
11580 /* Shift and mask the return values properly. */
11581 if (used_mode != mode && before_param)
11583 emit_insn (gen_lshrsi3 (before, before, shift));
11584 convert_move (before_param, before, 1);
11587 if (used_mode != mode && after_param)
11589 emit_insn (gen_lshrsi3 (after, after, shift));
11590 convert_move (after_param, after, 1);
11593 /* The previous sequence will end with a branch that's dependent on
11594 the conditional store, so placing an isync will ensure that no
11595 other instructions (especially, no load or store instructions)
11596 can start before the atomic operation completes. */
11598 emit_insn (gen_isync ());
11601 /* Emit instructions to move SRC to DST. Called by splitters for
11602 multi-register moves. It will emit at most one instruction for
11603 each register that is accessed; that is, it won't emit li/lis pairs
11604 (or equivalent for 64-bit code). One of SRC or DST must be a hard
11608 rs6000_split_multireg_move (rtx dst, rtx src)
11610 /* The register number of the first register being moved. */
11612 /* The mode that is to be moved. */
11613 enum machine_mode mode;
11614 /* The mode that the move is being done in, and its size. */
11615 enum machine_mode reg_mode;
11617 /* The number of registers that will be moved. */
11620 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
11621 mode = GET_MODE (dst);
11622 nregs = hard_regno_nregs[reg][mode];
11623 if (FP_REGNO_P (reg))
11625 else if (ALTIVEC_REGNO_P (reg))
11626 reg_mode = V16QImode;
11628 reg_mode = word_mode;
11629 reg_mode_size = GET_MODE_SIZE (reg_mode);
11631 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
11633 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
11635 /* Move register range backwards, if we might have destructive
11638 for (i = nregs - 1; i >= 0; i--)
11639 emit_insn (gen_rtx_SET (VOIDmode,
11640 simplify_gen_subreg (reg_mode, dst, mode,
11641 i * reg_mode_size),
11642 simplify_gen_subreg (reg_mode, src, mode,
11643 i * reg_mode_size)));
11649 bool used_update = false;
11651 if (MEM_P (src) && INT_REGNO_P (reg))
11655 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11656 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
11659 breg = XEXP (XEXP (src, 0), 0);
11660 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
11661 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11662 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
11663 emit_insn (TARGET_32BIT
11664 ? gen_addsi3 (breg, breg, delta_rtx)
11665 : gen_adddi3 (breg, breg, delta_rtx));
11666 src = gen_rtx_MEM (mode, breg);
11668 else if (! offsettable_memref_p (src))
11670 rtx newsrc, basereg;
11671 basereg = gen_rtx_REG (Pmode, reg);
11672 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11673 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11674 MEM_COPY_ATTRIBUTES (newsrc, src);
11678 breg = XEXP (src, 0);
11679 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11680 breg = XEXP (breg, 0);
11682 /* If the base register we are using to address memory is
11683 also a destination reg, then change that register last. */
11685 && REGNO (breg) >= REGNO (dst)
11686 && REGNO (breg) < REGNO (dst) + nregs)
11687 j = REGNO (breg) - REGNO (dst);
11690 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
11694 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11695 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
11698 breg = XEXP (XEXP (dst, 0), 0);
11699 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11700 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11701 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
11703 /* We have to update the breg before doing the store.
11704 Use store with update, if available. */
11708 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
11709 emit_insn (TARGET_32BIT
11710 ? (TARGET_POWERPC64
11711 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11712 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11713 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
11714 used_update = true;
11717 emit_insn (TARGET_32BIT
11718 ? gen_addsi3 (breg, breg, delta_rtx)
11719 : gen_adddi3 (breg, breg, delta_rtx));
11720 dst = gen_rtx_MEM (mode, breg);
11723 gcc_assert (offsettable_memref_p (dst));
11726 for (i = 0; i < nregs; i++)
11728 /* Calculate index to next subword. */
11733 /* If compiler already emitted move of first word by
11734 store with update, no need to do anything. */
11735 if (j == 0 && used_update)
11738 emit_insn (gen_rtx_SET (VOIDmode,
11739 simplify_gen_subreg (reg_mode, dst, mode,
11740 j * reg_mode_size),
11741 simplify_gen_subreg (reg_mode, src, mode,
11742 j * reg_mode_size)));
11748 /* This page contains routines that are used to determine what the
11749 function prologue and epilogue code will do and write them out. */
11751 /* Return the first fixed-point register that is required to be
11752 saved. 32 if none. */
11755 first_reg_to_save (void)
11759 /* Find lowest numbered live register. */
11760 for (first_reg = 13; first_reg <= 31; first_reg++)
11761 if (regs_ever_live[first_reg]
11762 && (! call_used_regs[first_reg]
11763 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
11764 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
11765 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
11766 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
11771 && current_function_uses_pic_offset_table
11772 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
11773 return RS6000_PIC_OFFSET_TABLE_REGNUM;
11779 /* Similar, for FP regs. */
11782 first_fp_reg_to_save (void)
11786 /* Find lowest numbered live register. */
11787 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
11788 if (regs_ever_live[first_reg])
11794 /* Similar, for AltiVec regs. */
11797 first_altivec_reg_to_save (void)
11801 /* Stack frame remains as is unless we are in AltiVec ABI. */
11802 if (! TARGET_ALTIVEC_ABI)
11803 return LAST_ALTIVEC_REGNO + 1;
11805 /* Find lowest numbered live register. */
11806 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
11807 if (regs_ever_live[i])
11813 /* Return a 32-bit mask of the AltiVec registers we need to set in
11814 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11815 the 32-bit word is 0. */
11817 static unsigned int
11818 compute_vrsave_mask (void)
11820 unsigned int i, mask = 0;
11822 /* First, find out if we use _any_ altivec registers. */
11823 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11824 if (regs_ever_live[i])
11825 mask |= ALTIVEC_REG_BIT (i);
11830 /* Next, remove the argument registers from the set. These must
11831 be in the VRSAVE mask set by the caller, so we don't need to add
11832 them in again. More importantly, the mask we compute here is
11833 used to generate CLOBBERs in the set_vrsave insn, and we do not
11834 wish the argument registers to die. */
11835 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
11836 mask &= ~ALTIVEC_REG_BIT (i);
11838 /* Similarly, remove the return value from the set. */
11841 diddle_return_value (is_altivec_return_reg, &yes);
11843 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
11849 /* For a very restricted set of circumstances, we can cut down the
11850 size of prologues/epilogues by calling our own save/restore-the-world
11854 compute_save_world_info (rs6000_stack_t *info_ptr)
11856 info_ptr->world_save_p = 1;
11857 info_ptr->world_save_p
11858 = (WORLD_SAVE_P (info_ptr)
11859 && DEFAULT_ABI == ABI_DARWIN
11860 && ! (current_function_calls_setjmp && flag_exceptions)
11861 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
11862 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
11863 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
11864 && info_ptr->cr_save_p);
11866 /* This will not work in conjunction with sibcalls. Make sure there
11867 are none. (This check is expensive, but seldom executed.) */
11868 if (WORLD_SAVE_P (info_ptr))
11871 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
11872 if ( GET_CODE (insn) == CALL_INSN
11873 && SIBLING_CALL_P (insn))
11875 info_ptr->world_save_p = 0;
11880 if (WORLD_SAVE_P (info_ptr))
11882 /* Even if we're not touching VRsave, make sure there's room on the
11883 stack for it, if it looks like we're calling SAVE_WORLD, which
11884 will attempt to save it. */
11885 info_ptr->vrsave_size = 4;
11887 /* "Save" the VRsave register too if we're saving the world. */
11888 if (info_ptr->vrsave_mask == 0)
11889 info_ptr->vrsave_mask = compute_vrsave_mask ();
11891 /* Because the Darwin register save/restore routines only handle
11892 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
11894 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
11895 && (info_ptr->first_altivec_reg_save
11896 >= FIRST_SAVED_ALTIVEC_REGNO));
11903 is_altivec_return_reg (rtx reg, void *xyes)
11905 bool *yes = (bool *) xyes;
11906 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
11911 /* Calculate the stack information for the current function. This is
11912 complicated by having two separate calling sequences, the AIX calling
11913 sequence and the V.4 calling sequence.
11915 AIX (and Darwin/Mac OS X) stack frames look like:
11917 SP----> +---------------------------------------+
11918 | back chain to caller | 0 0
11919 +---------------------------------------+
11920 | saved CR | 4 8 (8-11)
11921 +---------------------------------------+
11923 +---------------------------------------+
11924 | reserved for compilers | 12 24
11925 +---------------------------------------+
11926 | reserved for binders | 16 32
11927 +---------------------------------------+
11928 | saved TOC pointer | 20 40
11929 +---------------------------------------+
11930 | Parameter save area (P) | 24 48
11931 +---------------------------------------+
11932 | Alloca space (A) | 24+P etc.
11933 +---------------------------------------+
11934 | Local variable space (L) | 24+P+A
11935 +---------------------------------------+
11936 | Float/int conversion temporary (X) | 24+P+A+L
11937 +---------------------------------------+
11938 | Save area for AltiVec registers (W) | 24+P+A+L+X
11939 +---------------------------------------+
11940 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11941 +---------------------------------------+
11942 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
11943 +---------------------------------------+
11944 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11945 +---------------------------------------+
11946 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
11947 +---------------------------------------+
11948 old SP->| back chain to caller's caller |
11949 +---------------------------------------+
11951 The required alignment for AIX configurations is two words (i.e., 8
11955 V.4 stack frames look like:
11957 SP----> +---------------------------------------+
11958 | back chain to caller | 0
11959 +---------------------------------------+
11960 | caller's saved LR | 4
11961 +---------------------------------------+
11962 | Parameter save area (P) | 8
11963 +---------------------------------------+
11964 | Alloca space (A) | 8+P
11965 +---------------------------------------+
11966 | Varargs save area (V) | 8+P+A
11967 +---------------------------------------+
11968 | Local variable space (L) | 8+P+A+V
11969 +---------------------------------------+
11970 | Float/int conversion temporary (X) | 8+P+A+V+L
11971 +---------------------------------------+
11972 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11973 +---------------------------------------+
11974 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11975 +---------------------------------------+
11976 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11977 +---------------------------------------+
11978 | SPE: area for 64-bit GP registers |
11979 +---------------------------------------+
11980 | SPE alignment padding |
11981 +---------------------------------------+
11982 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
11983 +---------------------------------------+
11984 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
11985 +---------------------------------------+
11986 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
11987 +---------------------------------------+
11988 old SP->| back chain to caller's caller |
11989 +---------------------------------------+
11991 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11992 given. (But note below and in sysv4.h that we require only 8 and
11993 may round up the size of our stack frame anyways. The historical
11994 reason is early versions of powerpc-linux which didn't properly
11995 align the stack at program startup. A happy side-effect is that
11996 -mno-eabi libraries can be used with -meabi programs.)
11998 The EABI configuration defaults to the V.4 layout. However,
11999 the stack alignment requirements may differ. If -mno-eabi is not
12000 given, the required stack alignment is 8 bytes; if -mno-eabi is
12001 given, the required alignment is 16 bytes. (But see V.4 comment
12004 #ifndef ABI_STACK_BOUNDARY
12005 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12008 static rs6000_stack_t *
12009 rs6000_stack_info (void)
12011 static rs6000_stack_t info, zero_info;
12012 rs6000_stack_t *info_ptr = &info;
12013 int reg_size = TARGET_32BIT ? 4 : 8;
12016 HOST_WIDE_INT non_fixed_size;
12018 /* Zero all fields portably. */
12023 /* Cache value so we don't rescan instruction chain over and over. */
12024 if (cfun->machine->insn_chain_scanned_p == 0)
12025 cfun->machine->insn_chain_scanned_p
12026 = spe_func_has_64bit_regs_p () + 1;
12027 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12030 /* Select which calling sequence. */
12031 info_ptr->abi = DEFAULT_ABI;
12033 /* Calculate which registers need to be saved & save area size. */
12034 info_ptr->first_gp_reg_save = first_reg_to_save ();
12035 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12036 even if it currently looks like we won't. */
12037 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12038 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12039 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12040 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12041 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12043 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12045 /* For the SPE, we have an additional upper 32-bits on each GPR.
12046 Ideally we should save the entire 64-bits only when the upper
12047 half is used in SIMD instructions. Since we only record
12048 registers live (not the size they are used in), this proves
12049 difficult because we'd have to traverse the instruction chain at
12050 the right time, taking reload into account. This is a real pain,
12051 so we opt to save the GPRs in 64-bits always if but one register
12052 gets used in 64-bits. Otherwise, all the registers in the frame
12053 get saved in 32-bits.
12055 So... since when we save all GPRs (except the SP) in 64-bits, the
12056 traditional GP save area will be empty. */
12057 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12058 info_ptr->gp_size = 0;
12060 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12061 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12063 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12064 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12065 - info_ptr->first_altivec_reg_save);
12067 /* Does this function call anything? */
12068 info_ptr->calls_p = (! current_function_is_leaf
12069 || cfun->machine->ra_needs_full_frame);
12071 /* Determine if we need to save the link register. */
12072 if (rs6000_ra_ever_killed ()
12073 || (DEFAULT_ABI == ABI_AIX
12074 && current_function_profile
12075 && !TARGET_PROFILE_KERNEL)
12076 #ifdef TARGET_RELOCATABLE
12077 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12079 || (info_ptr->first_fp_reg_save != 64
12080 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12081 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12082 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12083 || info_ptr->calls_p)
12085 info_ptr->lr_save_p = 1;
12086 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12089 /* Determine if we need to save the condition code registers. */
12090 if (regs_ever_live[CR2_REGNO]
12091 || regs_ever_live[CR3_REGNO]
12092 || regs_ever_live[CR4_REGNO])
12094 info_ptr->cr_save_p = 1;
12095 if (DEFAULT_ABI == ABI_V4)
12096 info_ptr->cr_size = reg_size;
12099 /* If the current function calls __builtin_eh_return, then we need
12100 to allocate stack space for registers that will hold data for
12101 the exception handler. */
12102 if (current_function_calls_eh_return)
12105 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12108 /* SPE saves EH registers in 64-bits. */
12109 ehrd_size = i * (TARGET_SPE_ABI
12110 && info_ptr->spe_64bit_regs_used != 0
12111 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12116 /* Determine various sizes. */
12117 info_ptr->reg_size = reg_size;
12118 info_ptr->fixed_size = RS6000_SAVE_AREA;
12119 info_ptr->varargs_size = RS6000_VARARGS_AREA;
12120 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12121 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12122 TARGET_ALTIVEC ? 16 : 8);
12123 if (FRAME_GROWS_DOWNWARD)
12124 info_ptr->vars_size
12125 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->varargs_size
12126 + info_ptr->vars_size + info_ptr->parm_size,
12127 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
12128 - (info_ptr->fixed_size + info_ptr->varargs_size
12129 + info_ptr->vars_size + info_ptr->parm_size);
12131 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12132 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12134 info_ptr->spe_gp_size = 0;
12136 if (TARGET_ALTIVEC_ABI)
12137 info_ptr->vrsave_mask = compute_vrsave_mask ();
12139 info_ptr->vrsave_mask = 0;
12141 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12142 info_ptr->vrsave_size = 4;
12144 info_ptr->vrsave_size = 0;
12146 compute_save_world_info (info_ptr);
12148 /* Calculate the offsets. */
12149 switch (DEFAULT_ABI)
12153 gcc_unreachable ();
12157 info_ptr->fp_save_offset = - info_ptr->fp_size;
12158 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12160 if (TARGET_ALTIVEC_ABI)
12162 info_ptr->vrsave_save_offset
12163 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12165 /* Align stack so vector save area is on a quadword boundary. */
12166 if (info_ptr->altivec_size != 0)
12167 info_ptr->altivec_padding_size
12168 = 16 - (-info_ptr->vrsave_save_offset % 16);
12170 info_ptr->altivec_padding_size = 0;
12172 info_ptr->altivec_save_offset
12173 = info_ptr->vrsave_save_offset
12174 - info_ptr->altivec_padding_size
12175 - info_ptr->altivec_size;
12177 /* Adjust for AltiVec case. */
12178 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12181 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12182 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12183 info_ptr->lr_save_offset = 2*reg_size;
12187 info_ptr->fp_save_offset = - info_ptr->fp_size;
12188 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12189 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12191 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12193 /* Align stack so SPE GPR save area is aligned on a
12194 double-word boundary. */
12195 if (info_ptr->spe_gp_size != 0)
12196 info_ptr->spe_padding_size
12197 = 8 - (-info_ptr->cr_save_offset % 8);
12199 info_ptr->spe_padding_size = 0;
12201 info_ptr->spe_gp_save_offset
12202 = info_ptr->cr_save_offset
12203 - info_ptr->spe_padding_size
12204 - info_ptr->spe_gp_size;
12206 /* Adjust for SPE case. */
12207 info_ptr->toc_save_offset
12208 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12210 else if (TARGET_ALTIVEC_ABI)
12212 info_ptr->vrsave_save_offset
12213 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12215 /* Align stack so vector save area is on a quadword boundary. */
12216 if (info_ptr->altivec_size != 0)
12217 info_ptr->altivec_padding_size
12218 = 16 - (-info_ptr->vrsave_save_offset % 16);
12220 info_ptr->altivec_padding_size = 0;
12222 info_ptr->altivec_save_offset
12223 = info_ptr->vrsave_save_offset
12224 - info_ptr->altivec_padding_size
12225 - info_ptr->altivec_size;
12227 /* Adjust for AltiVec case. */
12228 info_ptr->toc_save_offset
12229 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12232 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
12233 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
12234 info_ptr->lr_save_offset = reg_size;
12238 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
12239 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12240 + info_ptr->gp_size
12241 + info_ptr->altivec_size
12242 + info_ptr->altivec_padding_size
12243 + info_ptr->spe_gp_size
12244 + info_ptr->spe_padding_size
12246 + info_ptr->cr_size
12247 + info_ptr->lr_size
12248 + info_ptr->vrsave_size
12249 + info_ptr->toc_size,
12252 non_fixed_size = (info_ptr->vars_size
12253 + info_ptr->parm_size
12254 + info_ptr->save_size
12255 + info_ptr->varargs_size);
12257 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12258 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
12260 /* Determine if we need to allocate any stack frame:
12262 For AIX we need to push the stack if a frame pointer is needed
12263 (because the stack might be dynamically adjusted), if we are
12264 debugging, if we make calls, or if the sum of fp_save, gp_save,
12265 and local variables are more than the space needed to save all
12266 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12267 + 18*8 = 288 (GPR13 reserved).
12269 For V.4 we don't have the stack cushion that AIX uses, but assume
12270 that the debugger can handle stackless frames. */
12272 if (info_ptr->calls_p)
12273 info_ptr->push_p = 1;
12275 else if (DEFAULT_ABI == ABI_V4)
12276 info_ptr->push_p = non_fixed_size != 0;
12278 else if (frame_pointer_needed)
12279 info_ptr->push_p = 1;
12281 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12282 info_ptr->push_p = 1;
12285 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
12287 /* Zero offsets if we're not saving those registers. */
12288 if (info_ptr->fp_size == 0)
12289 info_ptr->fp_save_offset = 0;
12291 if (info_ptr->gp_size == 0)
12292 info_ptr->gp_save_offset = 0;
12294 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12295 info_ptr->altivec_save_offset = 0;
12297 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12298 info_ptr->vrsave_save_offset = 0;
12300 if (! TARGET_SPE_ABI
12301 || info_ptr->spe_64bit_regs_used == 0
12302 || info_ptr->spe_gp_size == 0)
12303 info_ptr->spe_gp_save_offset = 0;
12305 if (! info_ptr->lr_save_p)
12306 info_ptr->lr_save_offset = 0;
12308 if (! info_ptr->cr_save_p)
12309 info_ptr->cr_save_offset = 0;
12311 if (! info_ptr->toc_save_p)
12312 info_ptr->toc_save_offset = 0;
12317 /* Return true if the current function uses any GPRs in 64-bit SIMD
12321 spe_func_has_64bit_regs_p (void)
12325 /* Functions that save and restore all the call-saved registers will
12326 need to save/restore the registers in 64-bits. */
12327 if (current_function_calls_eh_return
12328 || current_function_calls_setjmp
12329 || current_function_has_nonlocal_goto)
12332 insns = get_insns ();
12334 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12340 /* FIXME: This should be implemented with attributes...
12342 (set_attr "spe64" "true")....then,
12343 if (get_spe64(insn)) return true;
12345 It's the only reliable way to do the stuff below. */
12347 i = PATTERN (insn);
12348 if (GET_CODE (i) == SET)
12350 enum machine_mode mode = GET_MODE (SET_SRC (i));
12352 if (SPE_VECTOR_MODE (mode))
12354 if (TARGET_E500_DOUBLE && mode == DFmode)
12364 debug_stack_info (rs6000_stack_t *info)
12366 const char *abi_string;
12369 info = rs6000_stack_info ();
12371 fprintf (stderr, "\nStack information for function %s:\n",
12372 ((current_function_decl && DECL_NAME (current_function_decl))
12373 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
12378 default: abi_string = "Unknown"; break;
12379 case ABI_NONE: abi_string = "NONE"; break;
12380 case ABI_AIX: abi_string = "AIX"; break;
12381 case ABI_DARWIN: abi_string = "Darwin"; break;
12382 case ABI_V4: abi_string = "V.4"; break;
12385 fprintf (stderr, "\tABI = %5s\n", abi_string);
12387 if (TARGET_ALTIVEC_ABI)
12388 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
12390 if (TARGET_SPE_ABI)
12391 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
12393 if (info->first_gp_reg_save != 32)
12394 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
12396 if (info->first_fp_reg_save != 64)
12397 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
12399 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
12400 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
12401 info->first_altivec_reg_save);
12403 if (info->lr_save_p)
12404 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
12406 if (info->cr_save_p)
12407 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
12409 if (info->toc_save_p)
12410 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
12412 if (info->vrsave_mask)
12413 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
12416 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
12419 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
12421 if (info->gp_save_offset)
12422 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
12424 if (info->fp_save_offset)
12425 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
12427 if (info->altivec_save_offset)
12428 fprintf (stderr, "\taltivec_save_offset = %5d\n",
12429 info->altivec_save_offset);
12431 if (info->spe_gp_save_offset)
12432 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
12433 info->spe_gp_save_offset);
12435 if (info->vrsave_save_offset)
12436 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
12437 info->vrsave_save_offset);
12439 if (info->lr_save_offset)
12440 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
12442 if (info->cr_save_offset)
12443 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
12445 if (info->toc_save_offset)
12446 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
12448 if (info->varargs_save_offset)
12449 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
12451 if (info->total_size)
12452 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12455 if (info->varargs_size)
12456 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
12458 if (info->vars_size)
12459 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12462 if (info->parm_size)
12463 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
12465 if (info->fixed_size)
12466 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
12469 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
12471 if (info->spe_gp_size)
12472 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
12475 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
12477 if (info->altivec_size)
12478 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
12480 if (info->vrsave_size)
12481 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
12483 if (info->altivec_padding_size)
12484 fprintf (stderr, "\taltivec_padding_size= %5d\n",
12485 info->altivec_padding_size);
12487 if (info->spe_padding_size)
12488 fprintf (stderr, "\tspe_padding_size = %5d\n",
12489 info->spe_padding_size);
12492 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
12495 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
12497 if (info->toc_size)
12498 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
12500 if (info->save_size)
12501 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
12503 if (info->reg_size != 4)
12504 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
12506 fprintf (stderr, "\n");
12510 rs6000_return_addr (int count, rtx frame)
12512 /* Currently we don't optimize very well between prolog and body
12513 code and for PIC code the code can be actually quite bad, so
12514 don't try to be too clever here. */
12515 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
12517 cfun->machine->ra_needs_full_frame = 1;
12524 plus_constant (copy_to_reg
12525 (gen_rtx_MEM (Pmode,
12526 memory_address (Pmode, frame))),
12527 RETURN_ADDRESS_OFFSET)));
12530 cfun->machine->ra_need_lr = 1;
12531 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
12534 /* Say whether a function is a candidate for sibcall handling or not.
12535 We do not allow indirect calls to be optimized into sibling calls.
12536 Also, we can't do it if there are any vector parameters; there's
12537 nowhere to put the VRsave code so it works; note that functions with
12538 vector parameters are required to have a prototype, so the argument
12539 type info must be available here. (The tail recursion case can work
12540 with vector parameters, but there's no way to distinguish here.) */
12542 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
12547 if (TARGET_ALTIVEC_VRSAVE)
12549 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
12550 type; type = TREE_CHAIN (type))
12552 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
12556 if (DEFAULT_ABI == ABI_DARWIN
12557 || (*targetm.binds_local_p) (decl))
12559 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
12561 if (!lookup_attribute ("longcall", attr_list)
12562 || lookup_attribute ("shortcall", attr_list))
12569 /* NULL if INSN insn is valid within a low-overhead loop.
12570 Otherwise return why doloop cannot be applied.
12571 PowerPC uses the COUNT register for branch on table instructions. */
12573 static const char *
12574 rs6000_invalid_within_doloop (rtx insn)
12577 return "Function call in the loop.";
12580 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
12581 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
12582 return "Computed branch in the loop.";
12588 rs6000_ra_ever_killed (void)
12594 if (current_function_is_thunk)
12597 /* regs_ever_live has LR marked as used if any sibcalls are present,
12598 but this should not force saving and restoring in the
12599 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
12600 clobbers LR, so that is inappropriate. */
12602 /* Also, the prologue can generate a store into LR that
12603 doesn't really count, like this:
12606 bcl to set PIC register
12610 When we're called from the epilogue, we need to avoid counting
12611 this as a store. */
12613 push_topmost_sequence ();
12614 top = get_insns ();
12615 pop_topmost_sequence ();
12616 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
12618 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
12622 if (FIND_REG_INC_NOTE (insn, reg))
12624 else if (GET_CODE (insn) == CALL_INSN
12625 && !SIBLING_CALL_P (insn))
12627 else if (set_of (reg, insn) != NULL_RTX
12628 && !prologue_epilogue_contains (insn))
12635 /* Add a REG_MAYBE_DEAD note to the insn. */
12637 rs6000_maybe_dead (rtx insn)
12639 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
12644 /* Emit instructions needed to load the TOC register.
12645 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
12646 a constant pool; or for SVR4 -fpic. */
12649 rs6000_emit_load_toc_table (int fromprolog)
12652 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12654 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
12657 rtx lab, tmp1, tmp2, got, tempLR;
12659 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12660 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12662 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12664 got = rs6000_got_sym ();
12665 tmp1 = tmp2 = dest;
12668 tmp1 = gen_reg_rtx (Pmode);
12669 tmp2 = gen_reg_rtx (Pmode);
12671 tempLR = (fromprolog
12672 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12673 : gen_reg_rtx (Pmode));
12674 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
12676 rs6000_maybe_dead (insn);
12677 insn = emit_move_insn (tmp1, tempLR);
12679 rs6000_maybe_dead (insn);
12680 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
12682 rs6000_maybe_dead (insn);
12683 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
12685 rs6000_maybe_dead (insn);
12687 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12689 rtx tempLR = (fromprolog
12690 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12691 : gen_reg_rtx (Pmode));
12693 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
12695 rs6000_maybe_dead (insn);
12696 insn = emit_move_insn (dest, tempLR);
12698 rs6000_maybe_dead (insn);
12700 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
12703 rtx tempLR = (fromprolog
12704 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12705 : gen_reg_rtx (Pmode));
12706 rtx temp0 = (fromprolog
12707 ? gen_rtx_REG (Pmode, 0)
12708 : gen_reg_rtx (Pmode));
12714 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12715 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12717 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12718 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12720 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12722 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12723 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12731 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12732 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
12733 emit_move_insn (dest, tempLR);
12734 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
12736 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12738 rs6000_maybe_dead (insn);
12740 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12742 /* This is for AIX code running in non-PIC ELF32. */
12745 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12746 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12748 insn = emit_insn (gen_elf_high (dest, realsym));
12750 rs6000_maybe_dead (insn);
12751 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12753 rs6000_maybe_dead (insn);
12757 gcc_assert (DEFAULT_ABI == ABI_AIX);
12760 insn = emit_insn (gen_load_toc_aix_si (dest));
12762 insn = emit_insn (gen_load_toc_aix_di (dest));
12764 rs6000_maybe_dead (insn);
12768 /* Emit instructions to restore the link register after determining where
12769 its value has been stored. */
12772 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12774 rs6000_stack_t *info = rs6000_stack_info ();
12777 operands[0] = source;
12778 operands[1] = scratch;
12780 if (info->lr_save_p)
12782 rtx frame_rtx = stack_pointer_rtx;
12783 HOST_WIDE_INT sp_offset = 0;
12786 if (frame_pointer_needed
12787 || current_function_calls_alloca
12788 || info->total_size > 32767)
12790 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12791 frame_rtx = operands[1];
12793 else if (info->push_p)
12794 sp_offset = info->total_size;
12796 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12797 tmp = gen_rtx_MEM (Pmode, tmp);
12798 emit_move_insn (tmp, operands[0]);
12801 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12804 static GTY(()) int set = -1;
12807 get_TOC_alias_set (void)
12810 set = new_alias_set ();
12814 /* This returns nonzero if the current function uses the TOC. This is
12815 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12816 is generated by the ABI_V4 load_toc_* patterns. */
12823 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12826 rtx pat = PATTERN (insn);
12829 if (GET_CODE (pat) == PARALLEL)
12830 for (i = 0; i < XVECLEN (pat, 0); i++)
12832 rtx sub = XVECEXP (pat, 0, i);
12833 if (GET_CODE (sub) == USE)
12835 sub = XEXP (sub, 0);
12836 if (GET_CODE (sub) == UNSPEC
12837 && XINT (sub, 1) == UNSPEC_TOC)
12847 create_TOC_reference (rtx symbol)
12849 return gen_rtx_PLUS (Pmode,
12850 gen_rtx_REG (Pmode, TOC_REGISTER),
12851 gen_rtx_CONST (Pmode,
12852 gen_rtx_MINUS (Pmode, symbol,
12853 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
12856 /* If _Unwind_* has been called from within the same module,
12857 toc register is not guaranteed to be saved to 40(1) on function
12858 entry. Save it there in that case. */
12861 rs6000_aix_emit_builtin_unwind_init (void)
12864 rtx stack_top = gen_reg_rtx (Pmode);
12865 rtx opcode_addr = gen_reg_rtx (Pmode);
12866 rtx opcode = gen_reg_rtx (SImode);
12867 rtx tocompare = gen_reg_rtx (SImode);
12868 rtx no_toc_save_needed = gen_label_rtx ();
12870 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
12871 emit_move_insn (stack_top, mem);
12873 mem = gen_rtx_MEM (Pmode,
12874 gen_rtx_PLUS (Pmode, stack_top,
12875 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
12876 emit_move_insn (opcode_addr, mem);
12877 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
12878 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
12879 : 0xE8410028, SImode));
12881 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
12882 SImode, NULL_RTX, NULL_RTX,
12883 no_toc_save_needed);
12885 mem = gen_rtx_MEM (Pmode,
12886 gen_rtx_PLUS (Pmode, stack_top,
12887 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
12888 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
12889 emit_label (no_toc_save_needed);
12892 /* This ties together stack memory (MEM with an alias set of
12893 rs6000_sr_alias_set) and the change to the stack pointer. */
12896 rs6000_emit_stack_tie (void)
12898 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
12900 set_mem_alias_set (mem, rs6000_sr_alias_set);
12901 emit_insn (gen_stack_tie (mem));
12904 /* Emit the correct code for allocating stack space, as insns.
12905 If COPY_R12, make sure a copy of the old frame is left in r12.
12906 The generated code may use hard register 0 as a temporary. */
12909 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
12912 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12913 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
12914 rtx todec = gen_int_mode (-size, Pmode);
12916 if (INTVAL (todec) != -size)
12918 warning (0, "stack frame too large");
12919 emit_insn (gen_trap ());
12923 if (current_function_limit_stack)
12925 if (REG_P (stack_limit_rtx)
12926 && REGNO (stack_limit_rtx) > 1
12927 && REGNO (stack_limit_rtx) <= 31)
12929 emit_insn (TARGET_32BIT
12930 ? gen_addsi3 (tmp_reg,
12933 : gen_adddi3 (tmp_reg,
12937 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12940 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
12942 && DEFAULT_ABI == ABI_V4)
12944 rtx toload = gen_rtx_CONST (VOIDmode,
12945 gen_rtx_PLUS (Pmode,
12949 emit_insn (gen_elf_high (tmp_reg, toload));
12950 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
12951 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12955 warning (0, "stack limit expression is not supported");
12958 if (copy_r12 || ! TARGET_UPDATE)
12959 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
12965 /* Need a note here so that try_split doesn't get confused. */
12966 if (get_last_insn () == NULL_RTX)
12967 emit_note (NOTE_INSN_DELETED);
12968 insn = emit_move_insn (tmp_reg, todec);
12969 try_split (PATTERN (insn), insn, 0);
12973 insn = emit_insn (TARGET_32BIT
12974 ? gen_movsi_update (stack_reg, stack_reg,
12976 : gen_movdi_di_update (stack_reg, stack_reg,
12977 todec, stack_reg));
12981 insn = emit_insn (TARGET_32BIT
12982 ? gen_addsi3 (stack_reg, stack_reg, todec)
12983 : gen_adddi3 (stack_reg, stack_reg, todec));
12984 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
12985 gen_rtx_REG (Pmode, 12));
12988 RTX_FRAME_RELATED_P (insn) = 1;
12990 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12991 gen_rtx_SET (VOIDmode, stack_reg,
12992 gen_rtx_PLUS (Pmode, stack_reg,
12997 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12998 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12999 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13000 deduce these equivalences by itself so it wasn't necessary to hold
13001 its hand so much. */
13004 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13005 rtx reg2, rtx rreg)
13009 /* copy_rtx will not make unique copies of registers, so we need to
13010 ensure we don't have unwanted sharing here. */
13012 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13015 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13017 real = copy_rtx (PATTERN (insn));
13019 if (reg2 != NULL_RTX)
13020 real = replace_rtx (real, reg2, rreg);
13022 real = replace_rtx (real, reg,
13023 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13024 STACK_POINTER_REGNUM),
13027 /* We expect that 'real' is either a SET or a PARALLEL containing
13028 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13029 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13031 if (GET_CODE (real) == SET)
13035 temp = simplify_rtx (SET_SRC (set));
13037 SET_SRC (set) = temp;
13038 temp = simplify_rtx (SET_DEST (set));
13040 SET_DEST (set) = temp;
13041 if (GET_CODE (SET_DEST (set)) == MEM)
13043 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13045 XEXP (SET_DEST (set), 0) = temp;
13052 gcc_assert (GET_CODE (real) == PARALLEL);
13053 for (i = 0; i < XVECLEN (real, 0); i++)
13054 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13056 rtx set = XVECEXP (real, 0, i);
13058 temp = simplify_rtx (SET_SRC (set));
13060 SET_SRC (set) = temp;
13061 temp = simplify_rtx (SET_DEST (set));
13063 SET_DEST (set) = temp;
13064 if (GET_CODE (SET_DEST (set)) == MEM)
13066 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13068 XEXP (SET_DEST (set), 0) = temp;
13070 RTX_FRAME_RELATED_P (set) = 1;
13075 real = spe_synthesize_frame_save (real);
13077 RTX_FRAME_RELATED_P (insn) = 1;
13078 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13083 /* Given an SPE frame note, return a PARALLEL of SETs with the
13084 original note, plus a synthetic register save. */
13087 spe_synthesize_frame_save (rtx real)
13089 rtx synth, offset, reg, real2;
13091 if (GET_CODE (real) != SET
13092 || GET_MODE (SET_SRC (real)) != V2SImode)
13095 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13096 frame related note. The parallel contains a set of the register
13097 being saved, and another set to a synthetic register (n+1200).
13098 This is so we can differentiate between 64-bit and 32-bit saves.
13099 Words cannot describe this nastiness. */
13101 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13102 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13103 && GET_CODE (SET_SRC (real)) == REG);
13106 (set (mem (plus (reg x) (const y)))
13109 (set (mem (plus (reg x) (const y+4)))
13113 real2 = copy_rtx (real);
13114 PUT_MODE (SET_DEST (real2), SImode);
13115 reg = SET_SRC (real2);
13116 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13117 synth = copy_rtx (real2);
13119 if (BYTES_BIG_ENDIAN)
13121 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13122 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13125 reg = SET_SRC (synth);
13127 synth = replace_rtx (synth, reg,
13128 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13130 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13131 synth = replace_rtx (synth, offset,
13132 GEN_INT (INTVAL (offset)
13133 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13135 RTX_FRAME_RELATED_P (synth) = 1;
13136 RTX_FRAME_RELATED_P (real2) = 1;
13137 if (BYTES_BIG_ENDIAN)
13138 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13140 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13145 /* Returns an insn that has a vrsave set operation with the
13146 appropriate CLOBBERs. */
13149 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13152 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13153 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13156 = gen_rtx_SET (VOIDmode,
13158 gen_rtx_UNSPEC_VOLATILE (SImode,
13159 gen_rtvec (2, reg, vrsave),
13164 /* We need to clobber the registers in the mask so the scheduler
13165 does not move sets to VRSAVE before sets of AltiVec registers.
13167 However, if the function receives nonlocal gotos, reload will set
13168 all call saved registers live. We will end up with:
13170 (set (reg 999) (mem))
13171 (parallel [ (set (reg vrsave) (unspec blah))
13172 (clobber (reg 999))])
13174 The clobber will cause the store into reg 999 to be dead, and
13175 flow will attempt to delete an epilogue insn. In this case, we
13176 need an unspec use/set of the register. */
13178 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13179 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13181 if (!epiloguep || call_used_regs [i])
13182 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13183 gen_rtx_REG (V4SImode, i));
13186 rtx reg = gen_rtx_REG (V4SImode, i);
13189 = gen_rtx_SET (VOIDmode,
13191 gen_rtx_UNSPEC (V4SImode,
13192 gen_rtvec (1, reg), 27));
13196 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13198 for (i = 0; i < nclobs; ++i)
13199 XVECEXP (insn, 0, i) = clobs[i];
13204 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13205 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13208 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13209 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13211 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13212 rtx replacea, replaceb;
13214 int_rtx = GEN_INT (offset);
13216 /* Some cases that need register indexed addressing. */
13217 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13218 || (TARGET_E500_DOUBLE && mode == DFmode)
13220 && SPE_VECTOR_MODE (mode)
13221 && !SPE_CONST_OFFSET_OK (offset)))
13223 /* Whomever calls us must make sure r11 is available in the
13224 flow path of instructions in the prologue. */
13225 offset_rtx = gen_rtx_REG (Pmode, 11);
13226 emit_move_insn (offset_rtx, int_rtx);
13228 replacea = offset_rtx;
13229 replaceb = int_rtx;
13233 offset_rtx = int_rtx;
13234 replacea = NULL_RTX;
13235 replaceb = NULL_RTX;
13238 reg = gen_rtx_REG (mode, regno);
13239 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13240 mem = gen_rtx_MEM (mode, addr);
13241 set_mem_alias_set (mem, rs6000_sr_alias_set);
13243 insn = emit_move_insn (mem, reg);
13245 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13248 /* Emit an offset memory reference suitable for a frame store, while
13249 converting to a valid addressing mode. */
13252 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
13254 rtx int_rtx, offset_rtx;
13256 int_rtx = GEN_INT (offset);
13258 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13259 || (TARGET_E500_DOUBLE && mode == DFmode))
13261 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13262 emit_move_insn (offset_rtx, int_rtx);
13265 offset_rtx = int_rtx;
13267 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13270 /* Look for user-defined global regs. We should not save and restore these,
13271 and cannot use stmw/lmw if there are any in its range. */
13274 no_global_regs_above (int first_greg)
13277 for (i = 0; i < 32 - first_greg; i++)
13278 if (global_regs[first_greg + i])
13283 #ifndef TARGET_FIX_AND_CONTINUE
13284 #define TARGET_FIX_AND_CONTINUE 0
13287 /* Emit function prologue as insns. */
13290 rs6000_emit_prologue (void)
13292 rs6000_stack_t *info = rs6000_stack_info ();
13293 enum machine_mode reg_mode = Pmode;
13294 int reg_size = TARGET_32BIT ? 4 : 8;
13295 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13296 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13297 rtx frame_reg_rtx = sp_reg_rtx;
13298 rtx cr_save_rtx = NULL_RTX;
13300 int saving_FPRs_inline;
13301 int using_store_multiple;
13302 HOST_WIDE_INT sp_offset = 0;
13304 if (TARGET_FIX_AND_CONTINUE)
13306 /* gdb on darwin arranges to forward a function from the old
13307 address by modifying the first 5 instructions of the function
13308 to branch to the overriding function. This is necessary to
13309 permit function pointers that point to the old function to
13310 actually forward to the new function. */
13311 emit_insn (gen_nop ());
13312 emit_insn (gen_nop ());
13313 emit_insn (gen_nop ());
13314 emit_insn (gen_nop ());
13315 emit_insn (gen_nop ());
13318 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13320 reg_mode = V2SImode;
13324 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13325 && (!TARGET_SPE_ABI
13326 || info->spe_64bit_regs_used == 0)
13327 && info->first_gp_reg_save < 31
13328 && no_global_regs_above (info->first_gp_reg_save));
13329 saving_FPRs_inline = (info->first_fp_reg_save == 64
13330 || FP_SAVE_INLINE (info->first_fp_reg_save)
13331 || current_function_calls_eh_return
13332 || cfun->machine->ra_need_lr);
13334 /* For V.4, update stack before we do any saving and set back pointer. */
13336 && (DEFAULT_ABI == ABI_V4
13337 || current_function_calls_eh_return))
13339 if (info->total_size < 32767)
13340 sp_offset = info->total_size;
13342 frame_reg_rtx = frame_ptr_rtx;
13343 rs6000_emit_allocate_stack (info->total_size,
13344 (frame_reg_rtx != sp_reg_rtx
13345 && (info->cr_save_p
13347 || info->first_fp_reg_save < 64
13348 || info->first_gp_reg_save < 32
13350 if (frame_reg_rtx != sp_reg_rtx)
13351 rs6000_emit_stack_tie ();
13354 /* Handle world saves specially here. */
13355 if (WORLD_SAVE_P (info))
13361 /* save_world expects lr in r0. */
13362 if (info->lr_save_p)
13364 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13365 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13366 RTX_FRAME_RELATED_P (insn) = 1;
13369 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
13370 assumptions about the offsets of various bits of the stack
13372 gcc_assert (info->gp_save_offset == -220
13373 && info->fp_save_offset == -144
13374 && info->lr_save_offset == 8
13375 && info->cr_save_offset == 4
13378 && (!current_function_calls_eh_return
13379 || info->ehrd_offset == -432)
13380 && info->vrsave_save_offset == -224
13381 && info->altivec_save_offset == (-224 -16 -192));
13383 treg = gen_rtx_REG (SImode, 11);
13384 emit_move_insn (treg, GEN_INT (-info->total_size));
13386 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
13387 in R11. It also clobbers R12, so beware! */
13389 /* Preserve CR2 for save_world prologues */
13391 sz += 32 - info->first_gp_reg_save;
13392 sz += 64 - info->first_fp_reg_save;
13393 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
13394 p = rtvec_alloc (sz);
13396 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
13397 gen_rtx_REG (Pmode,
13398 LINK_REGISTER_REGNUM));
13399 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13400 gen_rtx_SYMBOL_REF (Pmode,
13402 /* We do floats first so that the instruction pattern matches
13404 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13406 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13407 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13408 GEN_INT (info->fp_save_offset
13409 + sp_offset + 8 * i));
13410 rtx mem = gen_rtx_MEM (DFmode, addr);
13411 set_mem_alias_set (mem, rs6000_sr_alias_set);
13413 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13415 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13417 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13418 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13419 GEN_INT (info->altivec_save_offset
13420 + sp_offset + 16 * i));
13421 rtx mem = gen_rtx_MEM (V4SImode, addr);
13422 set_mem_alias_set (mem, rs6000_sr_alias_set);
13424 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13426 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13428 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13429 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13430 GEN_INT (info->gp_save_offset
13431 + sp_offset + reg_size * i));
13432 rtx mem = gen_rtx_MEM (reg_mode, addr);
13433 set_mem_alias_set (mem, rs6000_sr_alias_set);
13435 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13439 /* CR register traditionally saved as CR2. */
13440 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13441 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13442 GEN_INT (info->cr_save_offset
13444 rtx mem = gen_rtx_MEM (reg_mode, addr);
13445 set_mem_alias_set (mem, rs6000_sr_alias_set);
13447 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13449 /* Prevent any attempt to delete the setting of r0 and treg! */
13450 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
13451 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
13452 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
13454 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13455 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13456 NULL_RTX, NULL_RTX);
13458 if (current_function_calls_eh_return)
13463 unsigned int regno = EH_RETURN_DATA_REGNO (i);
13464 if (regno == INVALID_REGNUM)
13466 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13467 info->ehrd_offset + sp_offset
13468 + reg_size * (int) i,
13474 /* Save AltiVec registers if needed. */
13475 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13479 /* There should be a non inline version of this, for when we
13480 are saving lots of vector registers. */
13481 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13482 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13484 rtx areg, savereg, mem;
13487 offset = info->altivec_save_offset + sp_offset
13488 + 16 * (i - info->first_altivec_reg_save);
13490 savereg = gen_rtx_REG (V4SImode, i);
13492 areg = gen_rtx_REG (Pmode, 0);
13493 emit_move_insn (areg, GEN_INT (offset));
13495 /* AltiVec addressing mode is [reg+reg]. */
13496 mem = gen_rtx_MEM (V4SImode,
13497 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
13499 set_mem_alias_set (mem, rs6000_sr_alias_set);
13501 insn = emit_move_insn (mem, savereg);
13503 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13504 areg, GEN_INT (offset));
13508 /* VRSAVE is a bit vector representing which AltiVec registers
13509 are used. The OS uses this to determine which vector
13510 registers to save on a context switch. We need to save
13511 VRSAVE on the stack frame, add whatever AltiVec registers we
13512 used in this function, and do the corresponding magic in the
13515 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
13516 && info->vrsave_mask != 0)
13518 rtx reg, mem, vrsave;
13521 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
13522 as frame_reg_rtx and r11 as the static chain pointer for
13523 nested functions. */
13524 reg = gen_rtx_REG (SImode, 0);
13525 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13527 emit_insn (gen_get_vrsave_internal (reg));
13529 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
13531 if (!WORLD_SAVE_P (info))
13534 offset = info->vrsave_save_offset + sp_offset;
13536 = gen_rtx_MEM (SImode,
13537 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
13538 set_mem_alias_set (mem, rs6000_sr_alias_set);
13539 insn = emit_move_insn (mem, reg);
13542 /* Include the registers in the mask. */
13543 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
13545 insn = emit_insn (generate_set_vrsave (reg, info, 0));
13548 /* If we use the link register, get it into r0. */
13549 if (!WORLD_SAVE_P (info) && info->lr_save_p)
13551 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13552 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13553 RTX_FRAME_RELATED_P (insn) = 1;
13556 /* If we need to save CR, put it into r12. */
13557 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
13561 cr_save_rtx = gen_rtx_REG (SImode, 12);
13562 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13563 RTX_FRAME_RELATED_P (insn) = 1;
13564 /* Now, there's no way that dwarf2out_frame_debug_expr is going
13565 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
13566 But that's OK. All we have to do is specify that _one_ condition
13567 code register is saved in this stack slot. The thrower's epilogue
13568 will then restore all the call-saved registers.
13569 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
13570 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
13571 gen_rtx_REG (SImode, CR2_REGNO));
13572 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13577 /* Do any required saving of fpr's. If only one or two to save, do
13578 it ourselves. Otherwise, call function. */
13579 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
13582 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13583 if ((regs_ever_live[info->first_fp_reg_save+i]
13584 && ! call_used_regs[info->first_fp_reg_save+i]))
13585 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
13586 info->first_fp_reg_save + i,
13587 info->fp_save_offset + sp_offset + 8 * i,
13590 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
13594 const char *alloc_rname;
13596 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
13598 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
13599 gen_rtx_REG (Pmode,
13600 LINK_REGISTER_REGNUM));
13601 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
13602 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
13603 alloc_rname = ggc_strdup (rname);
13604 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13605 gen_rtx_SYMBOL_REF (Pmode,
13607 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13609 rtx addr, reg, mem;
13610 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13611 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13612 GEN_INT (info->fp_save_offset
13613 + sp_offset + 8*i));
13614 mem = gen_rtx_MEM (DFmode, addr);
13615 set_mem_alias_set (mem, rs6000_sr_alias_set);
13617 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
13619 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13620 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13621 NULL_RTX, NULL_RTX);
13624 /* Save GPRs. This is done as a PARALLEL if we are using
13625 the store-multiple instructions. */
13626 if (!WORLD_SAVE_P (info) && using_store_multiple)
13630 p = rtvec_alloc (32 - info->first_gp_reg_save);
13631 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13633 rtx addr, reg, mem;
13634 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13635 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13636 GEN_INT (info->gp_save_offset
13639 mem = gen_rtx_MEM (reg_mode, addr);
13640 set_mem_alias_set (mem, rs6000_sr_alias_set);
13642 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
13644 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13645 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13646 NULL_RTX, NULL_RTX);
13648 else if (!WORLD_SAVE_P (info))
13651 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13652 if ((regs_ever_live[info->first_gp_reg_save + i]
13653 && (!call_used_regs[info->first_gp_reg_save + i]
13654 || (i + info->first_gp_reg_save
13655 == RS6000_PIC_OFFSET_TABLE_REGNUM
13656 && TARGET_TOC && TARGET_MINIMAL_TOC)))
13657 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13658 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13659 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
13661 rtx addr, reg, mem;
13662 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13664 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13666 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13669 if (!SPE_CONST_OFFSET_OK (offset))
13671 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13672 emit_move_insn (b, GEN_INT (offset));
13675 b = GEN_INT (offset);
13677 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13678 mem = gen_rtx_MEM (V2SImode, addr);
13679 set_mem_alias_set (mem, rs6000_sr_alias_set);
13680 insn = emit_move_insn (mem, reg);
13682 if (GET_CODE (b) == CONST_INT)
13683 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13684 NULL_RTX, NULL_RTX);
13686 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13687 b, GEN_INT (offset));
13691 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13692 GEN_INT (info->gp_save_offset
13695 mem = gen_rtx_MEM (reg_mode, addr);
13696 set_mem_alias_set (mem, rs6000_sr_alias_set);
13698 insn = emit_move_insn (mem, reg);
13699 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13700 NULL_RTX, NULL_RTX);
13705 /* ??? There's no need to emit actual instructions here, but it's the
13706 easiest way to get the frame unwind information emitted. */
13707 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
13709 unsigned int i, regno;
13711 /* In AIX ABI we need to pretend we save r2 here. */
13714 rtx addr, reg, mem;
13716 reg = gen_rtx_REG (reg_mode, 2);
13717 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13718 GEN_INT (sp_offset + 5 * reg_size));
13719 mem = gen_rtx_MEM (reg_mode, addr);
13720 set_mem_alias_set (mem, rs6000_sr_alias_set);
13722 insn = emit_move_insn (mem, reg);
13723 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13724 NULL_RTX, NULL_RTX);
13725 PATTERN (insn) = gen_blockage ();
13730 regno = EH_RETURN_DATA_REGNO (i);
13731 if (regno == INVALID_REGNUM)
13734 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13735 info->ehrd_offset + sp_offset
13736 + reg_size * (int) i,
13741 /* Save lr if we used it. */
13742 if (!WORLD_SAVE_P (info) && info->lr_save_p)
13744 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13745 GEN_INT (info->lr_save_offset + sp_offset));
13746 rtx reg = gen_rtx_REG (Pmode, 0);
13747 rtx mem = gen_rtx_MEM (Pmode, addr);
13748 /* This should not be of rs6000_sr_alias_set, because of
13749 __builtin_return_address. */
13751 insn = emit_move_insn (mem, reg);
13752 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13753 NULL_RTX, NULL_RTX);
13756 /* Save CR if we use any that must be preserved. */
13757 if (!WORLD_SAVE_P (info) && info->cr_save_p)
13759 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13760 GEN_INT (info->cr_save_offset + sp_offset));
13761 rtx mem = gen_rtx_MEM (SImode, addr);
13762 /* See the large comment above about why CR2_REGNO is used. */
13763 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
13765 set_mem_alias_set (mem, rs6000_sr_alias_set);
13767 /* If r12 was used to hold the original sp, copy cr into r0 now
13769 if (REGNO (frame_reg_rtx) == 12)
13773 cr_save_rtx = gen_rtx_REG (SImode, 0);
13774 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13775 RTX_FRAME_RELATED_P (insn) = 1;
13776 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13777 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13782 insn = emit_move_insn (mem, cr_save_rtx);
13784 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13785 NULL_RTX, NULL_RTX);
13788 /* Update stack and set back pointer unless this is V.4,
13789 for which it was done previously. */
13790 if (!WORLD_SAVE_P (info) && info->push_p
13791 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
13792 rs6000_emit_allocate_stack (info->total_size, FALSE);
13794 /* Set frame pointer, if needed. */
13795 if (frame_pointer_needed)
13797 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
13799 RTX_FRAME_RELATED_P (insn) = 1;
13802 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
13803 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
13804 || (DEFAULT_ABI == ABI_V4
13805 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
13806 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
13808 /* If emit_load_toc_table will use the link register, we need to save
13809 it. We use R12 for this purpose because emit_load_toc_table
13810 can use register 0. This allows us to use a plain 'blr' to return
13811 from the procedure more often. */
13812 int save_LR_around_toc_setup = (TARGET_ELF
13813 && DEFAULT_ABI != ABI_AIX
13815 && ! info->lr_save_p
13816 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
13817 if (save_LR_around_toc_setup)
13819 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13821 insn = emit_move_insn (frame_ptr_rtx, lr);
13822 rs6000_maybe_dead (insn);
13823 RTX_FRAME_RELATED_P (insn) = 1;
13825 rs6000_emit_load_toc_table (TRUE);
13827 insn = emit_move_insn (lr, frame_ptr_rtx);
13828 rs6000_maybe_dead (insn);
13829 RTX_FRAME_RELATED_P (insn) = 1;
13832 rs6000_emit_load_toc_table (TRUE);
13836 if (DEFAULT_ABI == ABI_DARWIN
13837 && flag_pic && current_function_uses_pic_offset_table)
13839 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13840 rtx src = machopic_function_base_sym ();
13842 /* Save and restore LR locally around this call (in R0). */
13843 if (!info->lr_save_p)
13844 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
13846 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
13848 insn = emit_move_insn (gen_rtx_REG (Pmode,
13849 RS6000_PIC_OFFSET_TABLE_REGNUM),
13851 rs6000_maybe_dead (insn);
13853 if (!info->lr_save_p)
13854 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
13859 /* Write function prologue. */
13862 rs6000_output_function_prologue (FILE *file,
13863 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13865 rs6000_stack_t *info = rs6000_stack_info ();
13867 if (TARGET_DEBUG_STACK)
13868 debug_stack_info (info);
13870 /* Write .extern for any function we will call to save and restore
13872 if (info->first_fp_reg_save < 64
13873 && !FP_SAVE_INLINE (info->first_fp_reg_save))
13874 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
13875 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
13876 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
13877 RESTORE_FP_SUFFIX);
13879 /* Write .extern for AIX common mode routines, if needed. */
13880 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
13882 fputs ("\t.extern __mulh\n", file);
13883 fputs ("\t.extern __mull\n", file);
13884 fputs ("\t.extern __divss\n", file);
13885 fputs ("\t.extern __divus\n", file);
13886 fputs ("\t.extern __quoss\n", file);
13887 fputs ("\t.extern __quous\n", file);
13888 common_mode_defined = 1;
13891 if (! HAVE_prologue)
13895 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13896 the "toplevel" insn chain. */
13897 emit_note (NOTE_INSN_DELETED);
13898 rs6000_emit_prologue ();
13899 emit_note (NOTE_INSN_DELETED);
13901 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13905 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13907 INSN_ADDRESSES_NEW (insn, addr);
13912 if (TARGET_DEBUG_STACK)
13913 debug_rtx_list (get_insns (), 100);
13914 final (get_insns (), file, FALSE);
13918 rs6000_pic_labelno++;
13921 /* Emit function epilogue as insns.
13923 At present, dwarf2out_frame_debug_expr doesn't understand
13924 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13925 anywhere in the epilogue. Most of the insns below would in any case
13926 need special notes to explain where r11 is in relation to the stack. */
13929 rs6000_emit_epilogue (int sibcall)
13931 rs6000_stack_t *info;
13932 int restoring_FPRs_inline;
13933 int using_load_multiple;
13934 int using_mfcr_multiple;
13935 int use_backchain_to_restore_sp;
13937 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
13938 rtx frame_reg_rtx = sp_reg_rtx;
13939 enum machine_mode reg_mode = Pmode;
13940 int reg_size = TARGET_32BIT ? 4 : 8;
13943 info = rs6000_stack_info ();
13945 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13947 reg_mode = V2SImode;
13951 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13952 && (!TARGET_SPE_ABI
13953 || info->spe_64bit_regs_used == 0)
13954 && info->first_gp_reg_save < 31
13955 && no_global_regs_above (info->first_gp_reg_save));
13956 restoring_FPRs_inline = (sibcall
13957 || current_function_calls_eh_return
13958 || info->first_fp_reg_save == 64
13959 || FP_SAVE_INLINE (info->first_fp_reg_save));
13960 use_backchain_to_restore_sp = (frame_pointer_needed
13961 || current_function_calls_alloca
13962 || info->total_size > 32767);
13963 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
13964 || rs6000_cpu == PROCESSOR_PPC603
13965 || rs6000_cpu == PROCESSOR_PPC750
13968 if (WORLD_SAVE_P (info))
13972 const char *alloc_rname;
13975 /* eh_rest_world_r10 will return to the location saved in the LR
13976 stack slot (which is not likely to be our caller.)
13977 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13978 rest_world is similar, except any R10 parameter is ignored.
13979 The exception-handling stuff that was here in 2.95 is no
13980 longer necessary. */
13984 + 32 - info->first_gp_reg_save
13985 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
13986 + 63 + 1 - info->first_fp_reg_save);
13988 strcpy (rname, ((current_function_calls_eh_return) ?
13989 "*eh_rest_world_r10" : "*rest_world"));
13990 alloc_rname = ggc_strdup (rname);
13993 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
13994 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13995 gen_rtx_REG (Pmode,
13996 LINK_REGISTER_REGNUM));
13998 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
13999 /* The instruction pattern requires a clobber here;
14000 it is shared with the restVEC helper. */
14002 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14005 /* CR register traditionally saved as CR2. */
14006 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14007 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14008 GEN_INT (info->cr_save_offset));
14009 rtx mem = gen_rtx_MEM (reg_mode, addr);
14010 set_mem_alias_set (mem, rs6000_sr_alias_set);
14012 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14015 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14017 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14018 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14019 GEN_INT (info->gp_save_offset
14021 rtx mem = gen_rtx_MEM (reg_mode, addr);
14022 set_mem_alias_set (mem, rs6000_sr_alias_set);
14024 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14026 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14028 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14029 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14030 GEN_INT (info->altivec_save_offset
14032 rtx mem = gen_rtx_MEM (V4SImode, addr);
14033 set_mem_alias_set (mem, rs6000_sr_alias_set);
14035 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14037 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14039 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14040 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14041 GEN_INT (info->fp_save_offset
14043 rtx mem = gen_rtx_MEM (DFmode, addr);
14044 set_mem_alias_set (mem, rs6000_sr_alias_set);
14046 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14049 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14051 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14053 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14055 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14057 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14058 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14063 /* If we have a frame pointer, a call to alloca, or a large stack
14064 frame, restore the old stack pointer using the backchain. Otherwise,
14065 we know what size to update it with. */
14066 if (use_backchain_to_restore_sp)
14068 /* Under V.4, don't reset the stack pointer until after we're done
14069 loading the saved registers. */
14070 if (DEFAULT_ABI == ABI_V4)
14071 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14073 emit_move_insn (frame_reg_rtx,
14074 gen_rtx_MEM (Pmode, sp_reg_rtx));
14077 else if (info->push_p)
14079 if (DEFAULT_ABI == ABI_V4
14080 || current_function_calls_eh_return)
14081 sp_offset = info->total_size;
14084 emit_insn (TARGET_32BIT
14085 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14086 GEN_INT (info->total_size))
14087 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14088 GEN_INT (info->total_size)));
14092 /* Restore AltiVec registers if needed. */
14093 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14097 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14098 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14100 rtx addr, areg, mem;
14102 areg = gen_rtx_REG (Pmode, 0);
14104 (areg, GEN_INT (info->altivec_save_offset
14106 + 16 * (i - info->first_altivec_reg_save)));
14108 /* AltiVec addressing mode is [reg+reg]. */
14109 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14110 mem = gen_rtx_MEM (V4SImode, addr);
14111 set_mem_alias_set (mem, rs6000_sr_alias_set);
14113 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14117 /* Restore VRSAVE if needed. */
14118 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14119 && info->vrsave_mask != 0)
14121 rtx addr, mem, reg;
14123 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14124 GEN_INT (info->vrsave_save_offset + sp_offset));
14125 mem = gen_rtx_MEM (SImode, addr);
14126 set_mem_alias_set (mem, rs6000_sr_alias_set);
14127 reg = gen_rtx_REG (SImode, 12);
14128 emit_move_insn (reg, mem);
14130 emit_insn (generate_set_vrsave (reg, info, 1));
14133 /* Get the old lr if we saved it. */
14134 if (info->lr_save_p)
14136 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14137 info->lr_save_offset + sp_offset);
14139 set_mem_alias_set (mem, rs6000_sr_alias_set);
14141 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14144 /* Get the old cr if we saved it. */
14145 if (info->cr_save_p)
14147 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14148 GEN_INT (info->cr_save_offset + sp_offset));
14149 rtx mem = gen_rtx_MEM (SImode, addr);
14151 set_mem_alias_set (mem, rs6000_sr_alias_set);
14153 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14156 /* Set LR here to try to overlap restores below. */
14157 if (info->lr_save_p)
14158 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14159 gen_rtx_REG (Pmode, 0));
14161 /* Load exception handler data registers, if needed. */
14162 if (current_function_calls_eh_return)
14164 unsigned int i, regno;
14168 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14169 GEN_INT (sp_offset + 5 * reg_size));
14170 rtx mem = gen_rtx_MEM (reg_mode, addr);
14172 set_mem_alias_set (mem, rs6000_sr_alias_set);
14174 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14181 regno = EH_RETURN_DATA_REGNO (i);
14182 if (regno == INVALID_REGNUM)
14185 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14186 info->ehrd_offset + sp_offset
14187 + reg_size * (int) i);
14188 set_mem_alias_set (mem, rs6000_sr_alias_set);
14190 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14194 /* Restore GPRs. This is done as a PARALLEL if we are using
14195 the load-multiple instructions. */
14196 if (using_load_multiple)
14199 p = rtvec_alloc (32 - info->first_gp_reg_save);
14200 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14202 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14203 GEN_INT (info->gp_save_offset
14206 rtx mem = gen_rtx_MEM (reg_mode, addr);
14208 set_mem_alias_set (mem, rs6000_sr_alias_set);
14211 gen_rtx_SET (VOIDmode,
14212 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14215 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14218 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14219 if ((regs_ever_live[info->first_gp_reg_save + i]
14220 && (!call_used_regs[info->first_gp_reg_save + i]
14221 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14222 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14223 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14224 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14225 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14227 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14228 GEN_INT (info->gp_save_offset
14231 rtx mem = gen_rtx_MEM (reg_mode, addr);
14233 /* Restore 64-bit quantities for SPE. */
14234 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14236 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14239 if (!SPE_CONST_OFFSET_OK (offset))
14241 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14242 emit_move_insn (b, GEN_INT (offset));
14245 b = GEN_INT (offset);
14247 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14248 mem = gen_rtx_MEM (V2SImode, addr);
14251 set_mem_alias_set (mem, rs6000_sr_alias_set);
14253 emit_move_insn (gen_rtx_REG (reg_mode,
14254 info->first_gp_reg_save + i), mem);
14257 /* Restore fpr's if we need to do it without calling a function. */
14258 if (restoring_FPRs_inline)
14259 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14260 if ((regs_ever_live[info->first_fp_reg_save+i]
14261 && ! call_used_regs[info->first_fp_reg_save+i]))
14264 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14265 GEN_INT (info->fp_save_offset
14268 mem = gen_rtx_MEM (DFmode, addr);
14269 set_mem_alias_set (mem, rs6000_sr_alias_set);
14271 emit_move_insn (gen_rtx_REG (DFmode,
14272 info->first_fp_reg_save + i),
14276 /* If we saved cr, restore it here. Just those that were used. */
14277 if (info->cr_save_p)
14279 rtx r12_rtx = gen_rtx_REG (SImode, 12);
14282 if (using_mfcr_multiple)
14284 for (i = 0; i < 8; i++)
14285 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14287 gcc_assert (count);
14290 if (using_mfcr_multiple && count > 1)
14295 p = rtvec_alloc (count);
14298 for (i = 0; i < 8; i++)
14299 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14301 rtvec r = rtvec_alloc (2);
14302 RTVEC_ELT (r, 0) = r12_rtx;
14303 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
14304 RTVEC_ELT (p, ndx) =
14305 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
14306 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
14309 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14310 gcc_assert (ndx == count);
14313 for (i = 0; i < 8; i++)
14314 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14316 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
14322 /* If this is V.4, unwind the stack pointer after all of the loads
14323 have been done. We need to emit a block here so that sched
14324 doesn't decide to move the sp change before the register restores
14325 (which may not have any obvious dependency on the stack). This
14326 doesn't hurt performance, because there is no scheduling that can
14327 be done after this point. */
14328 if (DEFAULT_ABI == ABI_V4
14329 || current_function_calls_eh_return)
14331 if (frame_reg_rtx != sp_reg_rtx)
14332 rs6000_emit_stack_tie ();
14334 if (use_backchain_to_restore_sp)
14336 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
14338 else if (sp_offset != 0)
14340 emit_insn (TARGET_32BIT
14341 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14342 GEN_INT (sp_offset))
14343 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14344 GEN_INT (sp_offset)));
14348 if (current_function_calls_eh_return)
14350 rtx sa = EH_RETURN_STACKADJ_RTX;
14351 emit_insn (TARGET_32BIT
14352 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14353 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14359 if (! restoring_FPRs_inline)
14360 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14362 p = rtvec_alloc (2);
14364 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
14365 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14366 gen_rtx_REG (Pmode,
14367 LINK_REGISTER_REGNUM));
14369 /* If we have to restore more than two FP registers, branch to the
14370 restore function. It will return to our caller. */
14371 if (! restoring_FPRs_inline)
14375 const char *alloc_rname;
14377 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
14378 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
14379 alloc_rname = ggc_strdup (rname);
14380 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14381 gen_rtx_SYMBOL_REF (Pmode,
14384 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14387 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14388 GEN_INT (info->fp_save_offset + 8*i));
14389 mem = gen_rtx_MEM (DFmode, addr);
14390 set_mem_alias_set (mem, rs6000_sr_alias_set);
14392 RTVEC_ELT (p, i+3) =
14393 gen_rtx_SET (VOIDmode,
14394 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
14399 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14403 /* Write function epilogue. */
14406 rs6000_output_function_epilogue (FILE *file,
14407 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14409 rs6000_stack_t *info = rs6000_stack_info ();
14411 if (! HAVE_epilogue)
14413 rtx insn = get_last_insn ();
14414 /* If the last insn was a BARRIER, we don't have to write anything except
14415 the trace table. */
14416 if (GET_CODE (insn) == NOTE)
14417 insn = prev_nonnote_insn (insn);
14418 if (insn == 0 || GET_CODE (insn) != BARRIER)
14420 /* This is slightly ugly, but at least we don't have two
14421 copies of the epilogue-emitting code. */
14424 /* A NOTE_INSN_DELETED is supposed to be at the start
14425 and end of the "toplevel" insn chain. */
14426 emit_note (NOTE_INSN_DELETED);
14427 rs6000_emit_epilogue (FALSE);
14428 emit_note (NOTE_INSN_DELETED);
14430 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14434 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14436 INSN_ADDRESSES_NEW (insn, addr);
14441 if (TARGET_DEBUG_STACK)
14442 debug_rtx_list (get_insns (), 100);
14443 final (get_insns (), file, FALSE);
14449 macho_branch_islands ();
14450 /* Mach-O doesn't support labels at the end of objects, so if
14451 it looks like we might want one, insert a NOP. */
14453 rtx insn = get_last_insn ();
14456 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
14457 insn = PREV_INSN (insn);
14461 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
14462 fputs ("\tnop\n", file);
14466 /* Output a traceback table here. See /usr/include/sys/debug.h for info
14469 We don't output a traceback table if -finhibit-size-directive was
14470 used. The documentation for -finhibit-size-directive reads
14471 ``don't output a @code{.size} assembler directive, or anything
14472 else that would cause trouble if the function is split in the
14473 middle, and the two halves are placed at locations far apart in
14474 memory.'' The traceback table has this property, since it
14475 includes the offset from the start of the function to the
14476 traceback table itself.
14478 System V.4 Powerpc's (and the embedded ABI derived from it) use a
14479 different traceback table. */
14480 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
14481 && rs6000_traceback != traceback_none)
14483 const char *fname = NULL;
14484 const char *language_string = lang_hooks.name;
14485 int fixed_parms = 0, float_parms = 0, parm_info = 0;
14487 int optional_tbtab;
14489 if (rs6000_traceback == traceback_full)
14490 optional_tbtab = 1;
14491 else if (rs6000_traceback == traceback_part)
14492 optional_tbtab = 0;
14494 optional_tbtab = !optimize_size && !TARGET_ELF;
14496 if (optional_tbtab)
14498 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14499 while (*fname == '.') /* V.4 encodes . in the name */
14502 /* Need label immediately before tbtab, so we can compute
14503 its offset from the function start. */
14504 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14505 ASM_OUTPUT_LABEL (file, fname);
14508 /* The .tbtab pseudo-op can only be used for the first eight
14509 expressions, since it can't handle the possibly variable
14510 length fields that follow. However, if you omit the optional
14511 fields, the assembler outputs zeros for all optional fields
14512 anyways, giving each variable length field is minimum length
14513 (as defined in sys/debug.h). Thus we can not use the .tbtab
14514 pseudo-op at all. */
14516 /* An all-zero word flags the start of the tbtab, for debuggers
14517 that have to find it by searching forward from the entry
14518 point or from the current pc. */
14519 fputs ("\t.long 0\n", file);
14521 /* Tbtab format type. Use format type 0. */
14522 fputs ("\t.byte 0,", file);
14524 /* Language type. Unfortunately, there does not seem to be any
14525 official way to discover the language being compiled, so we
14526 use language_string.
14527 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
14528 Java is 13. Objective-C is 14. */
14529 if (! strcmp (language_string, "GNU C"))
14531 else if (! strcmp (language_string, "GNU F77")
14532 || ! strcmp (language_string, "GNU F95"))
14534 else if (! strcmp (language_string, "GNU Pascal"))
14536 else if (! strcmp (language_string, "GNU Ada"))
14538 else if (! strcmp (language_string, "GNU C++"))
14540 else if (! strcmp (language_string, "GNU Java"))
14542 else if (! strcmp (language_string, "GNU Objective-C"))
14545 gcc_unreachable ();
14546 fprintf (file, "%d,", i);
14548 /* 8 single bit fields: global linkage (not set for C extern linkage,
14549 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
14550 from start of procedure stored in tbtab, internal function, function
14551 has controlled storage, function has no toc, function uses fp,
14552 function logs/aborts fp operations. */
14553 /* Assume that fp operations are used if any fp reg must be saved. */
14554 fprintf (file, "%d,",
14555 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
14557 /* 6 bitfields: function is interrupt handler, name present in
14558 proc table, function calls alloca, on condition directives
14559 (controls stack walks, 3 bits), saves condition reg, saves
14561 /* The `function calls alloca' bit seems to be set whenever reg 31 is
14562 set up as a frame pointer, even when there is no alloca call. */
14563 fprintf (file, "%d,",
14564 ((optional_tbtab << 6)
14565 | ((optional_tbtab & frame_pointer_needed) << 5)
14566 | (info->cr_save_p << 1)
14567 | (info->lr_save_p)));
14569 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
14571 fprintf (file, "%d,",
14572 (info->push_p << 7) | (64 - info->first_fp_reg_save));
14574 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
14575 fprintf (file, "%d,", (32 - first_reg_to_save ()));
14577 if (optional_tbtab)
14579 /* Compute the parameter info from the function decl argument
14582 int next_parm_info_bit = 31;
14584 for (decl = DECL_ARGUMENTS (current_function_decl);
14585 decl; decl = TREE_CHAIN (decl))
14587 rtx parameter = DECL_INCOMING_RTL (decl);
14588 enum machine_mode mode = GET_MODE (parameter);
14590 if (GET_CODE (parameter) == REG)
14592 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
14610 gcc_unreachable ();
14613 /* If only one bit will fit, don't or in this entry. */
14614 if (next_parm_info_bit > 0)
14615 parm_info |= (bits << (next_parm_info_bit - 1));
14616 next_parm_info_bit -= 2;
14620 fixed_parms += ((GET_MODE_SIZE (mode)
14621 + (UNITS_PER_WORD - 1))
14623 next_parm_info_bit -= 1;
14629 /* Number of fixed point parameters. */
14630 /* This is actually the number of words of fixed point parameters; thus
14631 an 8 byte struct counts as 2; and thus the maximum value is 8. */
14632 fprintf (file, "%d,", fixed_parms);
14634 /* 2 bitfields: number of floating point parameters (7 bits), parameters
14636 /* This is actually the number of fp registers that hold parameters;
14637 and thus the maximum value is 13. */
14638 /* Set parameters on stack bit if parameters are not in their original
14639 registers, regardless of whether they are on the stack? Xlc
14640 seems to set the bit when not optimizing. */
14641 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
14643 if (! optional_tbtab)
14646 /* Optional fields follow. Some are variable length. */
14648 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
14649 11 double float. */
14650 /* There is an entry for each parameter in a register, in the order that
14651 they occur in the parameter list. Any intervening arguments on the
14652 stack are ignored. If the list overflows a long (max possible length
14653 34 bits) then completely leave off all elements that don't fit. */
14654 /* Only emit this long if there was at least one parameter. */
14655 if (fixed_parms || float_parms)
14656 fprintf (file, "\t.long %d\n", parm_info);
14658 /* Offset from start of code to tb table. */
14659 fputs ("\t.long ", file);
14660 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14662 RS6000_OUTPUT_BASENAME (file, fname);
14664 assemble_name (file, fname);
14666 rs6000_output_function_entry (file, fname);
14669 /* Interrupt handler mask. */
14670 /* Omit this long, since we never set the interrupt handler bit
14673 /* Number of CTL (controlled storage) anchors. */
14674 /* Omit this long, since the has_ctl bit is never set above. */
14676 /* Displacement into stack of each CTL anchor. */
14677 /* Omit this list of longs, because there are no CTL anchors. */
14679 /* Length of function name. */
14682 fprintf (file, "\t.short %d\n", (int) strlen (fname));
14684 /* Function name. */
14685 assemble_string (fname, strlen (fname));
14687 /* Register for alloca automatic storage; this is always reg 31.
14688 Only emit this if the alloca bit was set above. */
14689 if (frame_pointer_needed)
14690 fputs ("\t.byte 31\n", file);
14692 fputs ("\t.align 2\n", file);
14696 /* A C compound statement that outputs the assembler code for a thunk
14697 function, used to implement C++ virtual function calls with
14698 multiple inheritance. The thunk acts as a wrapper around a virtual
14699 function, adjusting the implicit object parameter before handing
14700 control off to the real function.
14702 First, emit code to add the integer DELTA to the location that
14703 contains the incoming first argument. Assume that this argument
14704 contains a pointer, and is the one used to pass the `this' pointer
14705 in C++. This is the incoming argument *before* the function
14706 prologue, e.g. `%o0' on a sparc. The addition must preserve the
14707 values of all other incoming arguments.
14709 After the addition, emit code to jump to FUNCTION, which is a
14710 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14711 not touch the return address. Hence returning from FUNCTION will
14712 return to whoever called the current `thunk'.
14714 The effect must be as if FUNCTION had been called directly with the
14715 adjusted first argument. This macro is responsible for emitting
14716 all of the code for a thunk function; output_function_prologue()
14717 and output_function_epilogue() are not invoked.
14719 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14720 been extracted from it.) It might possibly be useful on some
14721 targets, but probably not.
14723 If you do not define this macro, the target-independent code in the
14724 C++ frontend will generate a less efficient heavyweight thunk that
14725 calls FUNCTION instead of jumping to it. The generic approach does
14726 not support varargs. */
14729 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14730 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14733 rtx this, insn, funexp;
14735 reload_completed = 1;
14736 epilogue_completed = 1;
14737 no_new_pseudos = 1;
14738 reset_block_changes ();
14740 /* Mark the end of the (empty) prologue. */
14741 emit_note (NOTE_INSN_PROLOGUE_END);
14743 /* Find the "this" pointer. If the function returns a structure,
14744 the structure return pointer is in r3. */
14745 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14746 this = gen_rtx_REG (Pmode, 4);
14748 this = gen_rtx_REG (Pmode, 3);
14750 /* Apply the constant offset, if required. */
14753 rtx delta_rtx = GEN_INT (delta);
14754 emit_insn (TARGET_32BIT
14755 ? gen_addsi3 (this, this, delta_rtx)
14756 : gen_adddi3 (this, this, delta_rtx));
14759 /* Apply the offset from the vtable, if required. */
14762 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14763 rtx tmp = gen_rtx_REG (Pmode, 12);
14765 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
14766 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14768 emit_insn (TARGET_32BIT
14769 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14770 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14771 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14775 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14777 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14779 emit_insn (TARGET_32BIT
14780 ? gen_addsi3 (this, this, tmp)
14781 : gen_adddi3 (this, this, tmp));
14784 /* Generate a tail call to the target function. */
14785 if (!TREE_USED (function))
14787 assemble_external (function);
14788 TREE_USED (function) = 1;
14790 funexp = XEXP (DECL_RTL (function), 0);
14791 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
14794 if (MACHOPIC_INDIRECT)
14795 funexp = machopic_indirect_call_target (funexp);
14798 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14799 generate sibcall RTL explicitly. */
14800 insn = emit_call_insn (
14801 gen_rtx_PARALLEL (VOIDmode,
14803 gen_rtx_CALL (VOIDmode,
14804 funexp, const0_rtx),
14805 gen_rtx_USE (VOIDmode, const0_rtx),
14806 gen_rtx_USE (VOIDmode,
14807 gen_rtx_REG (SImode,
14808 LINK_REGISTER_REGNUM)),
14809 gen_rtx_RETURN (VOIDmode))));
14810 SIBLING_CALL_P (insn) = 1;
14813 /* Run just enough of rest_of_compilation to get the insns emitted.
14814 There's not really enough bulk here to make other passes such as
14815 instruction scheduling worth while. Note that use_thunk calls
14816 assemble_start_function and assemble_end_function. */
14817 insn = get_insns ();
14818 insn_locators_initialize ();
14819 shorten_branches (insn);
14820 final_start_function (insn, file, 1);
14821 final (insn, file, 1);
14822 final_end_function ();
14824 reload_completed = 0;
14825 epilogue_completed = 0;
14826 no_new_pseudos = 0;
14829 /* A quick summary of the various types of 'constant-pool tables'
14832 Target Flags Name One table per
14833 AIX (none) AIX TOC object file
14834 AIX -mfull-toc AIX TOC object file
14835 AIX -mminimal-toc AIX minimal TOC translation unit
14836 SVR4/EABI (none) SVR4 SDATA object file
14837 SVR4/EABI -fpic SVR4 pic object file
14838 SVR4/EABI -fPIC SVR4 PIC translation unit
14839 SVR4/EABI -mrelocatable EABI TOC function
14840 SVR4/EABI -maix AIX TOC object file
14841 SVR4/EABI -maix -mminimal-toc
14842 AIX minimal TOC translation unit
14844 Name Reg. Set by entries contains:
14845 made by addrs? fp? sum?
14847 AIX TOC 2 crt0 as Y option option
14848 AIX minimal TOC 30 prolog gcc Y Y option
14849 SVR4 SDATA 13 crt0 gcc N Y N
14850 SVR4 pic 30 prolog ld Y not yet N
14851 SVR4 PIC 30 prolog gcc Y option option
14852 EABI TOC 30 prolog gcc Y option option
14856 /* Hash functions for the hash table. */
14859 rs6000_hash_constant (rtx k)
14861 enum rtx_code code = GET_CODE (k);
14862 enum machine_mode mode = GET_MODE (k);
14863 unsigned result = (code << 3) ^ mode;
14864 const char *format;
14867 format = GET_RTX_FORMAT (code);
14868 flen = strlen (format);
14874 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
14877 if (mode != VOIDmode)
14878 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
14890 for (; fidx < flen; fidx++)
14891 switch (format[fidx])
14896 const char *str = XSTR (k, fidx);
14897 len = strlen (str);
14898 result = result * 613 + len;
14899 for (i = 0; i < len; i++)
14900 result = result * 613 + (unsigned) str[i];
14905 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
14909 result = result * 613 + (unsigned) XINT (k, fidx);
14912 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
14913 result = result * 613 + (unsigned) XWINT (k, fidx);
14917 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
14918 result = result * 613 + (unsigned) (XWINT (k, fidx)
14925 gcc_unreachable ();
14932 toc_hash_function (const void *hash_entry)
14934 const struct toc_hash_struct *thc =
14935 (const struct toc_hash_struct *) hash_entry;
14936 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
14939 /* Compare H1 and H2 for equivalence. */
14942 toc_hash_eq (const void *h1, const void *h2)
14944 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
14945 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
14947 if (((const struct toc_hash_struct *) h1)->key_mode
14948 != ((const struct toc_hash_struct *) h2)->key_mode)
14951 return rtx_equal_p (r1, r2);
14954 /* These are the names given by the C++ front-end to vtables, and
14955 vtable-like objects. Ideally, this logic should not be here;
14956 instead, there should be some programmatic way of inquiring as
14957 to whether or not an object is a vtable. */
14959 #define VTABLE_NAME_P(NAME) \
14960 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
14961 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14962 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
14963 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
14964 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
14967 rs6000_output_symbol_ref (FILE *file, rtx x)
14969 /* Currently C++ toc references to vtables can be emitted before it
14970 is decided whether the vtable is public or private. If this is
14971 the case, then the linker will eventually complain that there is
14972 a reference to an unknown section. Thus, for vtables only,
14973 we emit the TOC reference to reference the symbol and not the
14975 const char *name = XSTR (x, 0);
14977 if (VTABLE_NAME_P (name))
14979 RS6000_OUTPUT_BASENAME (file, name);
14982 assemble_name (file, name);
14985 /* Output a TOC entry. We derive the entry name from what is being
14989 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
14992 const char *name = buf;
14993 const char *real_name;
14997 gcc_assert (!TARGET_NO_TOC);
14999 /* When the linker won't eliminate them, don't output duplicate
15000 TOC entries (this happens on AIX if there is any kind of TOC,
15001 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15003 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15005 struct toc_hash_struct *h;
15008 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15009 time because GGC is not initialized at that point. */
15010 if (toc_hash_table == NULL)
15011 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15012 toc_hash_eq, NULL);
15014 h = ggc_alloc (sizeof (*h));
15016 h->key_mode = mode;
15017 h->labelno = labelno;
15019 found = htab_find_slot (toc_hash_table, h, 1);
15020 if (*found == NULL)
15022 else /* This is indeed a duplicate.
15023 Set this label equal to that label. */
15025 fputs ("\t.set ", file);
15026 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15027 fprintf (file, "%d,", labelno);
15028 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15029 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15035 /* If we're going to put a double constant in the TOC, make sure it's
15036 aligned properly when strict alignment is on. */
15037 if (GET_CODE (x) == CONST_DOUBLE
15038 && STRICT_ALIGNMENT
15039 && GET_MODE_BITSIZE (mode) >= 64
15040 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15041 ASM_OUTPUT_ALIGN (file, 3);
15044 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15046 /* Handle FP constants specially. Note that if we have a minimal
15047 TOC, things we put here aren't actually in the TOC, so we can allow
15049 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15051 REAL_VALUE_TYPE rv;
15054 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15055 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15059 if (TARGET_MINIMAL_TOC)
15060 fputs (DOUBLE_INT_ASM_OP, file);
15062 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15063 k[0] & 0xffffffff, k[1] & 0xffffffff,
15064 k[2] & 0xffffffff, k[3] & 0xffffffff);
15065 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15066 k[0] & 0xffffffff, k[1] & 0xffffffff,
15067 k[2] & 0xffffffff, k[3] & 0xffffffff);
15072 if (TARGET_MINIMAL_TOC)
15073 fputs ("\t.long ", file);
15075 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15076 k[0] & 0xffffffff, k[1] & 0xffffffff,
15077 k[2] & 0xffffffff, k[3] & 0xffffffff);
15078 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15079 k[0] & 0xffffffff, k[1] & 0xffffffff,
15080 k[2] & 0xffffffff, k[3] & 0xffffffff);
15084 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
15086 REAL_VALUE_TYPE rv;
15089 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15090 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15094 if (TARGET_MINIMAL_TOC)
15095 fputs (DOUBLE_INT_ASM_OP, file);
15097 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15098 k[0] & 0xffffffff, k[1] & 0xffffffff);
15099 fprintf (file, "0x%lx%08lx\n",
15100 k[0] & 0xffffffff, k[1] & 0xffffffff);
15105 if (TARGET_MINIMAL_TOC)
15106 fputs ("\t.long ", file);
15108 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15109 k[0] & 0xffffffff, k[1] & 0xffffffff);
15110 fprintf (file, "0x%lx,0x%lx\n",
15111 k[0] & 0xffffffff, k[1] & 0xffffffff);
15115 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
15117 REAL_VALUE_TYPE rv;
15120 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15121 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15125 if (TARGET_MINIMAL_TOC)
15126 fputs (DOUBLE_INT_ASM_OP, file);
15128 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15129 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15134 if (TARGET_MINIMAL_TOC)
15135 fputs ("\t.long ", file);
15137 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15138 fprintf (file, "0x%lx\n", l & 0xffffffff);
15142 else if (GET_MODE (x) == VOIDmode
15143 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15145 unsigned HOST_WIDE_INT low;
15146 HOST_WIDE_INT high;
15148 if (GET_CODE (x) == CONST_DOUBLE)
15150 low = CONST_DOUBLE_LOW (x);
15151 high = CONST_DOUBLE_HIGH (x);
15154 #if HOST_BITS_PER_WIDE_INT == 32
15157 high = (low & 0x80000000) ? ~0 : 0;
15161 low = INTVAL (x) & 0xffffffff;
15162 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15166 /* TOC entries are always Pmode-sized, but since this
15167 is a bigendian machine then if we're putting smaller
15168 integer constants in the TOC we have to pad them.
15169 (This is still a win over putting the constants in
15170 a separate constant pool, because then we'd have
15171 to have both a TOC entry _and_ the actual constant.)
15173 For a 32-bit target, CONST_INT values are loaded and shifted
15174 entirely within `low' and can be stored in one TOC entry. */
15176 /* It would be easy to make this work, but it doesn't now. */
15177 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
15179 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15181 #if HOST_BITS_PER_WIDE_INT == 32
15182 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15183 POINTER_SIZE, &low, &high, 0);
15186 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15187 high = (HOST_WIDE_INT) low >> 32;
15194 if (TARGET_MINIMAL_TOC)
15195 fputs (DOUBLE_INT_ASM_OP, file);
15197 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15198 (long) high & 0xffffffff, (long) low & 0xffffffff);
15199 fprintf (file, "0x%lx%08lx\n",
15200 (long) high & 0xffffffff, (long) low & 0xffffffff);
15205 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15207 if (TARGET_MINIMAL_TOC)
15208 fputs ("\t.long ", file);
15210 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15211 (long) high & 0xffffffff, (long) low & 0xffffffff);
15212 fprintf (file, "0x%lx,0x%lx\n",
15213 (long) high & 0xffffffff, (long) low & 0xffffffff);
15217 if (TARGET_MINIMAL_TOC)
15218 fputs ("\t.long ", file);
15220 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15221 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15227 if (GET_CODE (x) == CONST)
15229 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
15231 base = XEXP (XEXP (x, 0), 0);
15232 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15235 switch (GET_CODE (base))
15238 name = XSTR (base, 0);
15242 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
15243 CODE_LABEL_NUMBER (XEXP (base, 0)));
15247 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15251 gcc_unreachable ();
15254 real_name = (*targetm.strip_name_encoding) (name);
15255 if (TARGET_MINIMAL_TOC)
15256 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15259 fprintf (file, "\t.tc %s", real_name);
15262 fprintf (file, ".N%d", - offset);
15264 fprintf (file, ".P%d", offset);
15266 fputs ("[TC],", file);
15269 /* Currently C++ toc references to vtables can be emitted before it
15270 is decided whether the vtable is public or private. If this is
15271 the case, then the linker will eventually complain that there is
15272 a TOC reference to an unknown section. Thus, for vtables only,
15273 we emit the TOC reference to reference the symbol and not the
15275 if (VTABLE_NAME_P (name))
15277 RS6000_OUTPUT_BASENAME (file, name);
15279 fprintf (file, "%d", offset);
15280 else if (offset > 0)
15281 fprintf (file, "+%d", offset);
15284 output_addr_const (file, x);
15288 /* Output an assembler pseudo-op to write an ASCII string of N characters
15289 starting at P to FILE.
15291 On the RS/6000, we have to do this using the .byte operation and
15292 write out special characters outside the quoted string.
15293 Also, the assembler is broken; very long strings are truncated,
15294 so we must artificially break them up early. */
15297 output_ascii (FILE *file, const char *p, int n)
15300 int i, count_string;
15301 const char *for_string = "\t.byte \"";
15302 const char *for_decimal = "\t.byte ";
15303 const char *to_close = NULL;
15306 for (i = 0; i < n; i++)
15309 if (c >= ' ' && c < 0177)
15312 fputs (for_string, file);
15315 /* Write two quotes to get one. */
15323 for_decimal = "\"\n\t.byte ";
15327 if (count_string >= 512)
15329 fputs (to_close, file);
15331 for_string = "\t.byte \"";
15332 for_decimal = "\t.byte ";
15340 fputs (for_decimal, file);
15341 fprintf (file, "%d", c);
15343 for_string = "\n\t.byte \"";
15344 for_decimal = ", ";
15350 /* Now close the string if we have written one. Then end the line. */
15352 fputs (to_close, file);
15355 /* Generate a unique section name for FILENAME for a section type
15356 represented by SECTION_DESC. Output goes into BUF.
15358 SECTION_DESC can be any string, as long as it is different for each
15359 possible section type.
15361 We name the section in the same manner as xlc. The name begins with an
15362 underscore followed by the filename (after stripping any leading directory
15363 names) with the last period replaced by the string SECTION_DESC. If
15364 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15368 rs6000_gen_section_name (char **buf, const char *filename,
15369 const char *section_desc)
15371 const char *q, *after_last_slash, *last_period = 0;
15375 after_last_slash = filename;
15376 for (q = filename; *q; q++)
15379 after_last_slash = q + 1;
15380 else if (*q == '.')
15384 len = strlen (after_last_slash) + strlen (section_desc) + 2;
15385 *buf = (char *) xmalloc (len);
15390 for (q = after_last_slash; *q; q++)
15392 if (q == last_period)
15394 strcpy (p, section_desc);
15395 p += strlen (section_desc);
15399 else if (ISALNUM (*q))
15403 if (last_period == 0)
15404 strcpy (p, section_desc);
15409 /* Emit profile function. */
15412 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
15414 /* Non-standard profiling for kernels, which just saves LR then calls
15415 _mcount without worrying about arg saves. The idea is to change
15416 the function prologue as little as possible as it isn't easy to
15417 account for arg save/restore code added just for _mcount. */
15418 if (TARGET_PROFILE_KERNEL)
15421 if (DEFAULT_ABI == ABI_AIX)
15423 #ifndef NO_PROFILE_COUNTERS
15424 # define NO_PROFILE_COUNTERS 0
15426 if (NO_PROFILE_COUNTERS)
15427 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
15431 const char *label_name;
15434 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15435 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
15436 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
15438 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
15442 else if (DEFAULT_ABI == ABI_DARWIN)
15444 const char *mcount_name = RS6000_MCOUNT;
15445 int caller_addr_regno = LINK_REGISTER_REGNUM;
15447 /* Be conservative and always set this, at least for now. */
15448 current_function_uses_pic_offset_table = 1;
15451 /* For PIC code, set up a stub and collect the caller's address
15452 from r0, which is where the prologue puts it. */
15453 if (MACHOPIC_INDIRECT
15454 && current_function_uses_pic_offset_table)
15455 caller_addr_regno = 0;
15457 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
15459 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
15463 /* Write function profiler code. */
15466 output_function_profiler (FILE *file, int labelno)
15470 switch (DEFAULT_ABI)
15473 gcc_unreachable ();
15478 warning (0, "no profiling of 64-bit code for this ABI");
15481 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15482 fprintf (file, "\tmflr %s\n", reg_names[0]);
15483 if (NO_PROFILE_COUNTERS)
15485 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
15486 reg_names[0], reg_names[1]);
15488 else if (TARGET_SECURE_PLT && flag_pic)
15490 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
15491 reg_names[0], reg_names[1]);
15492 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
15493 asm_fprintf (file, "\t{cau|addis} %s,%s,",
15494 reg_names[12], reg_names[12]);
15495 assemble_name (file, buf);
15496 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
15497 assemble_name (file, buf);
15498 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
15500 else if (flag_pic == 1)
15502 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
15503 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
15504 reg_names[0], reg_names[1]);
15505 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
15506 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
15507 assemble_name (file, buf);
15508 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
15510 else if (flag_pic > 1)
15512 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
15513 reg_names[0], reg_names[1]);
15514 /* Now, we need to get the address of the label. */
15515 fputs ("\tbcl 20,31,1f\n\t.long ", file);
15516 assemble_name (file, buf);
15517 fputs ("-.\n1:", file);
15518 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
15519 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
15520 reg_names[0], reg_names[11]);
15521 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
15522 reg_names[0], reg_names[0], reg_names[11]);
15526 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
15527 assemble_name (file, buf);
15528 fputs ("@ha\n", file);
15529 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
15530 reg_names[0], reg_names[1]);
15531 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
15532 assemble_name (file, buf);
15533 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
15536 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
15537 fprintf (file, "\tbl %s%s\n",
15538 RS6000_MCOUNT, flag_pic ? "@plt" : "");
15543 if (!TARGET_PROFILE_KERNEL)
15545 /* Don't do anything, done in output_profile_hook (). */
15549 gcc_assert (!TARGET_32BIT);
15551 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
15552 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
15554 if (cfun->static_chain_decl != NULL)
15556 asm_fprintf (file, "\tstd %s,24(%s)\n",
15557 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15558 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15559 asm_fprintf (file, "\tld %s,24(%s)\n",
15560 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15563 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15570 /* Power4 load update and store update instructions are cracked into a
15571 load or store and an integer insn which are executed in the same cycle.
15572 Branches have their own dispatch slot which does not count against the
15573 GCC issue rate, but it changes the program flow so there are no other
15574 instructions to issue in this cycle. */
15577 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
15578 int verbose ATTRIBUTE_UNUSED,
15579 rtx insn, int more)
15581 if (GET_CODE (PATTERN (insn)) == USE
15582 || GET_CODE (PATTERN (insn)) == CLOBBER)
15585 if (rs6000_sched_groups)
15587 if (is_microcoded_insn (insn))
15589 else if (is_cracked_insn (insn))
15590 return more > 2 ? more - 2 : 0;
15596 /* Adjust the cost of a scheduling dependency. Return the new cost of
15597 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
15600 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
15602 if (! recog_memoized (insn))
15605 if (REG_NOTE_KIND (link) != 0)
15608 if (REG_NOTE_KIND (link) == 0)
15610 /* Data dependency; DEP_INSN writes a register that INSN reads
15611 some cycles later. */
15613 /* Separate a load from a narrower, dependent store. */
15614 if (rs6000_sched_groups
15615 && GET_CODE (PATTERN (insn)) == SET
15616 && GET_CODE (PATTERN (dep_insn)) == SET
15617 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
15618 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
15619 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
15620 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
15623 switch (get_attr_type (insn))
15626 /* Tell the first scheduling pass about the latency between
15627 a mtctr and bctr (and mtlr and br/blr). The first
15628 scheduling pass will not know about this latency since
15629 the mtctr instruction, which has the latency associated
15630 to it, will be generated by reload. */
15631 return TARGET_POWER ? 5 : 4;
15633 /* Leave some extra cycles between a compare and its
15634 dependent branch, to inhibit expensive mispredicts. */
15635 if ((rs6000_cpu_attr == CPU_PPC603
15636 || rs6000_cpu_attr == CPU_PPC604
15637 || rs6000_cpu_attr == CPU_PPC604E
15638 || rs6000_cpu_attr == CPU_PPC620
15639 || rs6000_cpu_attr == CPU_PPC630
15640 || rs6000_cpu_attr == CPU_PPC750
15641 || rs6000_cpu_attr == CPU_PPC7400
15642 || rs6000_cpu_attr == CPU_PPC7450
15643 || rs6000_cpu_attr == CPU_POWER4
15644 || rs6000_cpu_attr == CPU_POWER5)
15645 && recog_memoized (dep_insn)
15646 && (INSN_CODE (dep_insn) >= 0)
15647 && (get_attr_type (dep_insn) == TYPE_CMP
15648 || get_attr_type (dep_insn) == TYPE_COMPARE
15649 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
15650 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
15651 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
15652 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
15653 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
15654 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
15659 /* Fall out to return default cost. */
15665 /* The function returns a true if INSN is microcoded.
15666 Return false otherwise. */
15669 is_microcoded_insn (rtx insn)
15671 if (!insn || !INSN_P (insn)
15672 || GET_CODE (PATTERN (insn)) == USE
15673 || GET_CODE (PATTERN (insn)) == CLOBBER)
15676 if (rs6000_sched_groups)
15678 enum attr_type type = get_attr_type (insn);
15679 if (type == TYPE_LOAD_EXT_U
15680 || type == TYPE_LOAD_EXT_UX
15681 || type == TYPE_LOAD_UX
15682 || type == TYPE_STORE_UX
15683 || type == TYPE_MFCR)
15690 /* The function returns a nonzero value if INSN can be scheduled only
15691 as the first insn in a dispatch group ("dispatch-slot restricted").
15692 In this case, the returned value indicates how many dispatch slots
15693 the insn occupies (at the beginning of the group).
15694 Return 0 otherwise. */
15697 is_dispatch_slot_restricted (rtx insn)
15699 enum attr_type type;
15701 if (!rs6000_sched_groups)
15705 || insn == NULL_RTX
15706 || GET_CODE (insn) == NOTE
15707 || GET_CODE (PATTERN (insn)) == USE
15708 || GET_CODE (PATTERN (insn)) == CLOBBER)
15711 type = get_attr_type (insn);
15718 case TYPE_DELAYED_CR:
15719 case TYPE_CR_LOGICAL:
15727 if (rs6000_cpu == PROCESSOR_POWER5
15728 && is_cracked_insn (insn))
15734 /* The function returns true if INSN is cracked into 2 instructions
15735 by the processor (and therefore occupies 2 issue slots). */
15738 is_cracked_insn (rtx insn)
15740 if (!insn || !INSN_P (insn)
15741 || GET_CODE (PATTERN (insn)) == USE
15742 || GET_CODE (PATTERN (insn)) == CLOBBER)
15745 if (rs6000_sched_groups)
15747 enum attr_type type = get_attr_type (insn);
15748 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
15749 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
15750 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
15751 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
15752 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
15753 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
15754 || type == TYPE_IDIV || type == TYPE_LDIV
15755 || type == TYPE_INSERT_WORD)
15762 /* The function returns true if INSN can be issued only from
15763 the branch slot. */
15766 is_branch_slot_insn (rtx insn)
15768 if (!insn || !INSN_P (insn)
15769 || GET_CODE (PATTERN (insn)) == USE
15770 || GET_CODE (PATTERN (insn)) == CLOBBER)
15773 if (rs6000_sched_groups)
15775 enum attr_type type = get_attr_type (insn);
15776 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
15784 /* A C statement (sans semicolon) to update the integer scheduling
15785 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15786 INSN earlier, reduce the priority to execute INSN later. Do not
15787 define this macro if you do not need to adjust the scheduling
15788 priorities of insns. */
15791 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
15793 /* On machines (like the 750) which have asymmetric integer units,
15794 where one integer unit can do multiply and divides and the other
15795 can't, reduce the priority of multiply/divide so it is scheduled
15796 before other integer operations. */
15799 if (! INSN_P (insn))
15802 if (GET_CODE (PATTERN (insn)) == USE)
15805 switch (rs6000_cpu_attr) {
15807 switch (get_attr_type (insn))
15814 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15815 priority, priority);
15816 if (priority >= 0 && priority < 0x01000000)
15823 if (is_dispatch_slot_restricted (insn)
15824 && reload_completed
15825 && current_sched_info->sched_max_insns_priority
15826 && rs6000_sched_restricted_insns_priority)
15829 /* Prioritize insns that can be dispatched only in the first
15831 if (rs6000_sched_restricted_insns_priority == 1)
15832 /* Attach highest priority to insn. This means that in
15833 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
15834 precede 'priority' (critical path) considerations. */
15835 return current_sched_info->sched_max_insns_priority;
15836 else if (rs6000_sched_restricted_insns_priority == 2)
15837 /* Increase priority of insn by a minimal amount. This means that in
15838 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15839 considerations precede dispatch-slot restriction considerations. */
15840 return (priority + 1);
15846 /* Return how many instructions the machine can issue per cycle. */
15849 rs6000_issue_rate (void)
15851 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15852 if (!reload_completed)
15855 switch (rs6000_cpu_attr) {
15856 case CPU_RIOS1: /* ? */
15858 case CPU_PPC601: /* ? */
15881 /* Return how many instructions to look ahead for better insn
15885 rs6000_use_sched_lookahead (void)
15887 if (rs6000_cpu_attr == CPU_PPC8540)
15892 /* Determine is PAT refers to memory. */
15895 is_mem_ref (rtx pat)
15901 if (GET_CODE (pat) == MEM)
15904 /* Recursively process the pattern. */
15905 fmt = GET_RTX_FORMAT (GET_CODE (pat));
15907 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
15910 ret |= is_mem_ref (XEXP (pat, i));
15911 else if (fmt[i] == 'E')
15912 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
15913 ret |= is_mem_ref (XVECEXP (pat, i, j));
15919 /* Determine if PAT is a PATTERN of a load insn. */
15922 is_load_insn1 (rtx pat)
15924 if (!pat || pat == NULL_RTX)
15927 if (GET_CODE (pat) == SET)
15928 return is_mem_ref (SET_SRC (pat));
15930 if (GET_CODE (pat) == PARALLEL)
15934 for (i = 0; i < XVECLEN (pat, 0); i++)
15935 if (is_load_insn1 (XVECEXP (pat, 0, i)))
15942 /* Determine if INSN loads from memory. */
15945 is_load_insn (rtx insn)
15947 if (!insn || !INSN_P (insn))
15950 if (GET_CODE (insn) == CALL_INSN)
15953 return is_load_insn1 (PATTERN (insn));
15956 /* Determine if PAT is a PATTERN of a store insn. */
15959 is_store_insn1 (rtx pat)
15961 if (!pat || pat == NULL_RTX)
15964 if (GET_CODE (pat) == SET)
15965 return is_mem_ref (SET_DEST (pat));
15967 if (GET_CODE (pat) == PARALLEL)
15971 for (i = 0; i < XVECLEN (pat, 0); i++)
15972 if (is_store_insn1 (XVECEXP (pat, 0, i)))
15979 /* Determine if INSN stores to memory. */
15982 is_store_insn (rtx insn)
15984 if (!insn || !INSN_P (insn))
15987 return is_store_insn1 (PATTERN (insn));
15990 /* Returns whether the dependence between INSN and NEXT is considered
15991 costly by the given target. */
15994 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
15997 /* If the flag is not enabled - no dependence is considered costly;
15998 allow all dependent insns in the same group.
15999 This is the most aggressive option. */
16000 if (rs6000_sched_costly_dep == no_dep_costly)
16003 /* If the flag is set to 1 - a dependence is always considered costly;
16004 do not allow dependent instructions in the same group.
16005 This is the most conservative option. */
16006 if (rs6000_sched_costly_dep == all_deps_costly)
16009 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16010 && is_load_insn (next)
16011 && is_store_insn (insn))
16012 /* Prevent load after store in the same group. */
16015 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16016 && is_load_insn (next)
16017 && is_store_insn (insn)
16018 && (!link || (int) REG_NOTE_KIND (link) == 0))
16019 /* Prevent load after store in the same group if it is a true
16023 /* The flag is set to X; dependences with latency >= X are considered costly,
16024 and will not be scheduled in the same group. */
16025 if (rs6000_sched_costly_dep <= max_dep_latency
16026 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16032 /* Return the next insn after INSN that is found before TAIL is reached,
16033 skipping any "non-active" insns - insns that will not actually occupy
16034 an issue slot. Return NULL_RTX if such an insn is not found. */
16037 get_next_active_insn (rtx insn, rtx tail)
16041 if (!insn || insn == tail)
16044 next_insn = NEXT_INSN (insn);
16047 && next_insn != tail
16048 && (GET_CODE (next_insn) == NOTE
16049 || GET_CODE (PATTERN (next_insn)) == USE
16050 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
16052 next_insn = NEXT_INSN (next_insn);
16055 if (!next_insn || next_insn == tail)
16061 /* Return whether the presence of INSN causes a dispatch group termination
16062 of group WHICH_GROUP.
16064 If WHICH_GROUP == current_group, this function will return true if INSN
16065 causes the termination of the current group (i.e, the dispatch group to
16066 which INSN belongs). This means that INSN will be the last insn in the
16067 group it belongs to.
16069 If WHICH_GROUP == previous_group, this function will return true if INSN
16070 causes the termination of the previous group (i.e, the dispatch group that
16071 precedes the group to which INSN belongs). This means that INSN will be
16072 the first insn in the group it belongs to). */
16075 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16077 enum attr_type type;
16082 type = get_attr_type (insn);
16084 if (is_microcoded_insn (insn))
16087 if (which_group == current_group)
16089 if (is_branch_slot_insn (insn))
16093 else if (which_group == previous_group)
16095 if (is_dispatch_slot_restricted (insn))
16103 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16104 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16107 is_costly_group (rtx *group_insns, rtx next_insn)
16112 int issue_rate = rs6000_issue_rate ();
16114 for (i = 0; i < issue_rate; i++)
16116 rtx insn = group_insns[i];
16119 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16121 rtx next = XEXP (link, 0);
16122 if (next == next_insn)
16124 cost = insn_cost (insn, link, next_insn);
16125 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16134 /* Utility of the function redefine_groups.
16135 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16136 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16137 to keep it "far" (in a separate group) from GROUP_INSNS, following
16138 one of the following schemes, depending on the value of the flag
16139 -minsert_sched_nops = X:
16140 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16141 in order to force NEXT_INSN into a separate group.
16142 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16143 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16144 insertion (has a group just ended, how many vacant issue slots remain in the
16145 last group, and how many dispatch groups were encountered so far). */
16148 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16149 rtx next_insn, bool *group_end, int can_issue_more,
16154 int issue_rate = rs6000_issue_rate ();
16155 bool end = *group_end;
16158 if (next_insn == NULL_RTX)
16159 return can_issue_more;
16161 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16162 return can_issue_more;
16164 force = is_costly_group (group_insns, next_insn);
16166 return can_issue_more;
16168 if (sched_verbose > 6)
16169 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16170 *group_count ,can_issue_more);
16172 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16175 can_issue_more = 0;
16177 /* Since only a branch can be issued in the last issue_slot, it is
16178 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16179 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16180 in this case the last nop will start a new group and the branch
16181 will be forced to the new group. */
16182 if (can_issue_more && !is_branch_slot_insn (next_insn))
16185 while (can_issue_more > 0)
16188 emit_insn_before (nop, next_insn);
16196 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16198 int n_nops = rs6000_sched_insert_nops;
16200 /* Nops can't be issued from the branch slot, so the effective
16201 issue_rate for nops is 'issue_rate - 1'. */
16202 if (can_issue_more == 0)
16203 can_issue_more = issue_rate;
16205 if (can_issue_more == 0)
16207 can_issue_more = issue_rate - 1;
16210 for (i = 0; i < issue_rate; i++)
16212 group_insns[i] = 0;
16219 emit_insn_before (nop, next_insn);
16220 if (can_issue_more == issue_rate - 1) /* new group begins */
16223 if (can_issue_more == 0)
16225 can_issue_more = issue_rate - 1;
16228 for (i = 0; i < issue_rate; i++)
16230 group_insns[i] = 0;
16236 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16239 /* Is next_insn going to start a new group? */
16242 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16243 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16244 || (can_issue_more < issue_rate &&
16245 insn_terminates_group_p (next_insn, previous_group)));
16246 if (*group_end && end)
16249 if (sched_verbose > 6)
16250 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16251 *group_count, can_issue_more);
16252 return can_issue_more;
16255 return can_issue_more;
16258 /* This function tries to synch the dispatch groups that the compiler "sees"
16259 with the dispatch groups that the processor dispatcher is expected to
16260 form in practice. It tries to achieve this synchronization by forcing the
16261 estimated processor grouping on the compiler (as opposed to the function
16262 'pad_goups' which tries to force the scheduler's grouping on the processor).
16264 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16265 examines the (estimated) dispatch groups that will be formed by the processor
16266 dispatcher. It marks these group boundaries to reflect the estimated
16267 processor grouping, overriding the grouping that the scheduler had marked.
16268 Depending on the value of the flag '-minsert-sched-nops' this function can
16269 force certain insns into separate groups or force a certain distance between
16270 them by inserting nops, for example, if there exists a "costly dependence"
16273 The function estimates the group boundaries that the processor will form as
16274 follows: It keeps track of how many vacant issue slots are available after
16275 each insn. A subsequent insn will start a new group if one of the following
16277 - no more vacant issue slots remain in the current dispatch group.
16278 - only the last issue slot, which is the branch slot, is vacant, but the next
16279 insn is not a branch.
16280 - only the last 2 or less issue slots, including the branch slot, are vacant,
16281 which means that a cracked insn (which occupies two issue slots) can't be
16282 issued in this group.
16283 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16284 start a new group. */
16287 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16289 rtx insn, next_insn;
16291 int can_issue_more;
16294 int group_count = 0;
16298 issue_rate = rs6000_issue_rate ();
16299 group_insns = alloca (issue_rate * sizeof (rtx));
16300 for (i = 0; i < issue_rate; i++)
16302 group_insns[i] = 0;
16304 can_issue_more = issue_rate;
16306 insn = get_next_active_insn (prev_head_insn, tail);
16309 while (insn != NULL_RTX)
16311 slot = (issue_rate - can_issue_more);
16312 group_insns[slot] = insn;
16314 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16315 if (insn_terminates_group_p (insn, current_group))
16316 can_issue_more = 0;
16318 next_insn = get_next_active_insn (insn, tail);
16319 if (next_insn == NULL_RTX)
16320 return group_count + 1;
16322 /* Is next_insn going to start a new group? */
16324 = (can_issue_more == 0
16325 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16326 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16327 || (can_issue_more < issue_rate &&
16328 insn_terminates_group_p (next_insn, previous_group)));
16330 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
16331 next_insn, &group_end, can_issue_more,
16337 can_issue_more = 0;
16338 for (i = 0; i < issue_rate; i++)
16340 group_insns[i] = 0;
16344 if (GET_MODE (next_insn) == TImode && can_issue_more)
16345 PUT_MODE (next_insn, VOIDmode);
16346 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
16347 PUT_MODE (next_insn, TImode);
16350 if (can_issue_more == 0)
16351 can_issue_more = issue_rate;
16354 return group_count;
16357 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16358 dispatch group boundaries that the scheduler had marked. Pad with nops
16359 any dispatch groups which have vacant issue slots, in order to force the
16360 scheduler's grouping on the processor dispatcher. The function
16361 returns the number of dispatch groups found. */
16364 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16366 rtx insn, next_insn;
16369 int can_issue_more;
16371 int group_count = 0;
16373 /* Initialize issue_rate. */
16374 issue_rate = rs6000_issue_rate ();
16375 can_issue_more = issue_rate;
16377 insn = get_next_active_insn (prev_head_insn, tail);
16378 next_insn = get_next_active_insn (insn, tail);
16380 while (insn != NULL_RTX)
16383 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16385 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16387 if (next_insn == NULL_RTX)
16392 /* If the scheduler had marked group termination at this location
16393 (between insn and next_indn), and neither insn nor next_insn will
16394 force group termination, pad the group with nops to force group
16397 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
16398 && !insn_terminates_group_p (insn, current_group)
16399 && !insn_terminates_group_p (next_insn, previous_group))
16401 if (!is_branch_slot_insn (next_insn))
16404 while (can_issue_more)
16407 emit_insn_before (nop, next_insn);
16412 can_issue_more = issue_rate;
16417 next_insn = get_next_active_insn (insn, tail);
16420 return group_count;
16423 /* The following function is called at the end of scheduling BB.
16424 After reload, it inserts nops at insn group bundling. */
16427 rs6000_sched_finish (FILE *dump, int sched_verbose)
16432 fprintf (dump, "=== Finishing schedule.\n");
16434 if (reload_completed && rs6000_sched_groups)
16436 if (rs6000_sched_insert_nops == sched_finish_none)
16439 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
16440 n_groups = pad_groups (dump, sched_verbose,
16441 current_sched_info->prev_head,
16442 current_sched_info->next_tail);
16444 n_groups = redefine_groups (dump, sched_verbose,
16445 current_sched_info->prev_head,
16446 current_sched_info->next_tail);
16448 if (sched_verbose >= 6)
16450 fprintf (dump, "ngroups = %d\n", n_groups);
16451 print_rtl (dump, current_sched_info->prev_head);
16452 fprintf (dump, "Done finish_sched\n");
16457 /* Length in units of the trampoline for entering a nested function. */
16460 rs6000_trampoline_size (void)
16464 switch (DEFAULT_ABI)
16467 gcc_unreachable ();
16470 ret = (TARGET_32BIT) ? 12 : 24;
16475 ret = (TARGET_32BIT) ? 40 : 48;
16482 /* Emit RTL insns to initialize the variable parts of a trampoline.
16483 FNADDR is an RTX for the address of the function's pure code.
16484 CXT is an RTX for the static chain value for the function. */
16487 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
16489 enum machine_mode pmode = Pmode;
16490 int regsize = (TARGET_32BIT) ? 4 : 8;
16491 rtx ctx_reg = force_reg (pmode, cxt);
16493 switch (DEFAULT_ABI)
16496 gcc_unreachable ();
16498 /* Macros to shorten the code expansions below. */
16499 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
16500 #define MEM_PLUS(addr,offset) \
16501 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
16503 /* Under AIX, just build the 3 word function descriptor */
16506 rtx fn_reg = gen_reg_rtx (pmode);
16507 rtx toc_reg = gen_reg_rtx (pmode);
16508 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
16509 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
16510 emit_move_insn (MEM_DEREF (addr), fn_reg);
16511 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
16512 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
16516 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
16519 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
16520 FALSE, VOIDmode, 4,
16522 GEN_INT (rs6000_trampoline_size ()), SImode,
16532 /* Table of valid machine attributes. */
16534 const struct attribute_spec rs6000_attribute_table[] =
16536 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
16537 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
16538 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16539 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16540 #ifdef SUBTARGET_ATTRIBUTE_TABLE
16541 SUBTARGET_ATTRIBUTE_TABLE,
16543 { NULL, 0, 0, false, false, false, NULL }
16546 /* Handle the "altivec" attribute. The attribute may have
16547 arguments as follows:
16549 __attribute__((altivec(vector__)))
16550 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
16551 __attribute__((altivec(bool__))) (always followed by 'unsigned')
16553 and may appear more than once (e.g., 'vector bool char') in a
16554 given declaration. */
16557 rs6000_handle_altivec_attribute (tree *node,
16558 tree name ATTRIBUTE_UNUSED,
16560 int flags ATTRIBUTE_UNUSED,
16561 bool *no_add_attrs)
16563 tree type = *node, result = NULL_TREE;
16564 enum machine_mode mode;
16567 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
16568 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
16569 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
16572 while (POINTER_TYPE_P (type)
16573 || TREE_CODE (type) == FUNCTION_TYPE
16574 || TREE_CODE (type) == METHOD_TYPE
16575 || TREE_CODE (type) == ARRAY_TYPE)
16576 type = TREE_TYPE (type);
16578 mode = TYPE_MODE (type);
16580 /* Check for invalid AltiVec type qualifiers. */
16581 if (type == long_unsigned_type_node || type == long_integer_type_node)
16584 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
16585 else if (rs6000_warn_altivec_long)
16586 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
16588 else if (type == long_long_unsigned_type_node
16589 || type == long_long_integer_type_node)
16590 error ("use of %<long long%> in AltiVec types is invalid");
16591 else if (type == double_type_node)
16592 error ("use of %<double%> in AltiVec types is invalid");
16593 else if (type == long_double_type_node)
16594 error ("use of %<long double%> in AltiVec types is invalid");
16595 else if (type == boolean_type_node)
16596 error ("use of boolean types in AltiVec types is invalid");
16597 else if (TREE_CODE (type) == COMPLEX_TYPE)
16598 error ("use of %<complex%> in AltiVec types is invalid");
16600 switch (altivec_type)
16603 unsigned_p = TYPE_UNSIGNED (type);
16607 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
16610 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
16613 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
16615 case SFmode: result = V4SF_type_node; break;
16616 /* If the user says 'vector int bool', we may be handed the 'bool'
16617 attribute _before_ the 'vector' attribute, and so select the
16618 proper type in the 'b' case below. */
16619 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
16627 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
16628 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
16629 case QImode: case V16QImode: result = bool_V16QI_type_node;
16636 case V8HImode: result = pixel_V8HI_type_node;
16642 if (result && result != type && TYPE_READONLY (type))
16643 result = build_qualified_type (result, TYPE_QUAL_CONST);
16645 *no_add_attrs = true; /* No need to hang on to the attribute. */
16648 *node = reconstruct_complex_type (*node, result);
16653 /* AltiVec defines four built-in scalar types that serve as vector
16654 elements; we must teach the compiler how to mangle them. */
16656 static const char *
16657 rs6000_mangle_fundamental_type (tree type)
16659 if (type == bool_char_type_node) return "U6__boolc";
16660 if (type == bool_short_type_node) return "U6__bools";
16661 if (type == pixel_type_node) return "u7__pixel";
16662 if (type == bool_int_type_node) return "U6__booli";
16664 /* For all other types, use normal C++ mangling. */
16668 /* Handle a "longcall" or "shortcall" attribute; arguments as in
16669 struct attribute_spec.handler. */
16672 rs6000_handle_longcall_attribute (tree *node, tree name,
16673 tree args ATTRIBUTE_UNUSED,
16674 int flags ATTRIBUTE_UNUSED,
16675 bool *no_add_attrs)
16677 if (TREE_CODE (*node) != FUNCTION_TYPE
16678 && TREE_CODE (*node) != FIELD_DECL
16679 && TREE_CODE (*node) != TYPE_DECL)
16681 warning (OPT_Wattributes, "%qs attribute only applies to functions",
16682 IDENTIFIER_POINTER (name));
16683 *no_add_attrs = true;
16689 /* Set longcall attributes on all functions declared when
16690 rs6000_default_long_calls is true. */
16692 rs6000_set_default_type_attributes (tree type)
16694 if (rs6000_default_long_calls
16695 && (TREE_CODE (type) == FUNCTION_TYPE
16696 || TREE_CODE (type) == METHOD_TYPE))
16697 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
16699 TYPE_ATTRIBUTES (type));
16702 /* Return a reference suitable for calling a function with the
16703 longcall attribute. */
16706 rs6000_longcall_ref (rtx call_ref)
16708 const char *call_name;
16711 if (GET_CODE (call_ref) != SYMBOL_REF)
16714 /* System V adds '.' to the internal name, so skip them. */
16715 call_name = XSTR (call_ref, 0);
16716 if (*call_name == '.')
16718 while (*call_name == '.')
16721 node = get_identifier (call_name);
16722 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
16725 return force_reg (Pmode, call_ref);
16728 #ifdef USING_ELFOS_H
16730 /* A C statement or statements to switch to the appropriate section
16731 for output of RTX in mode MODE. You can assume that RTX is some
16732 kind of constant in RTL. The argument MODE is redundant except in
16733 the case of a `const_int' rtx. Select the section by calling
16734 `text_section' or one of the alternatives for other sections.
16736 Do not define this macro if you put all constants in the read-only
16740 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
16741 unsigned HOST_WIDE_INT align)
16743 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16746 default_elf_select_rtx_section (mode, x, align);
16749 /* A C statement or statements to switch to the appropriate
16750 section for output of DECL. DECL is either a `VAR_DECL' node
16751 or a constant of some sort. RELOC indicates whether forming
16752 the initial value of DECL requires link-time relocations. */
16755 rs6000_elf_select_section (tree decl, int reloc,
16756 unsigned HOST_WIDE_INT align)
16758 /* Pretend that we're always building for a shared library when
16759 ABI_AIX, because otherwise we end up with dynamic relocations
16760 in read-only sections. This happens for function pointers,
16761 references to vtables in typeinfo, and probably other cases. */
16762 default_elf_select_section_1 (decl, reloc, align,
16763 flag_pic || DEFAULT_ABI == ABI_AIX);
16766 /* A C statement to build up a unique section name, expressed as a
16767 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16768 RELOC indicates whether the initial value of EXP requires
16769 link-time relocations. If you do not define this macro, GCC will use
16770 the symbol name prefixed by `.' as the section name. Note - this
16771 macro can now be called for uninitialized data items as well as
16772 initialized data and functions. */
16775 rs6000_elf_unique_section (tree decl, int reloc)
16777 /* As above, pretend that we're always building for a shared library
16778 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
16779 default_unique_section_1 (decl, reloc,
16780 flag_pic || DEFAULT_ABI == ABI_AIX);
16783 /* For a SYMBOL_REF, set generic flags and then perform some
16784 target-specific processing.
16786 When the AIX ABI is requested on a non-AIX system, replace the
16787 function name with the real name (with a leading .) rather than the
16788 function descriptor name. This saves a lot of overriding code to
16789 read the prefixes. */
16792 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
16794 default_encode_section_info (decl, rtl, first);
16797 && TREE_CODE (decl) == FUNCTION_DECL
16799 && DEFAULT_ABI == ABI_AIX)
16801 rtx sym_ref = XEXP (rtl, 0);
16802 size_t len = strlen (XSTR (sym_ref, 0));
16803 char *str = alloca (len + 2);
16805 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16806 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
16811 rs6000_elf_in_small_data_p (tree decl)
16813 if (rs6000_sdata == SDATA_NONE)
16816 /* We want to merge strings, so we never consider them small data. */
16817 if (TREE_CODE (decl) == STRING_CST)
16820 /* Functions are never in the small data area. */
16821 if (TREE_CODE (decl) == FUNCTION_DECL)
16824 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16826 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16827 if (strcmp (section, ".sdata") == 0
16828 || strcmp (section, ".sdata2") == 0
16829 || strcmp (section, ".sbss") == 0
16830 || strcmp (section, ".sbss2") == 0
16831 || strcmp (section, ".PPC.EMB.sdata0") == 0
16832 || strcmp (section, ".PPC.EMB.sbss0") == 0)
16837 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16840 && (unsigned HOST_WIDE_INT) size <= g_switch_value
16841 /* If it's not public, and we're not going to reference it there,
16842 there's no need to put it in the small data section. */
16843 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16850 #endif /* USING_ELFOS_H */
16853 /* Return a REG that occurs in ADDR with coefficient 1.
16854 ADDR can be effectively incremented by incrementing REG.
16856 r0 is special and we must not select it as an address
16857 register by this routine since our caller will try to
16858 increment the returned register via an "la" instruction. */
16861 find_addr_reg (rtx addr)
16863 while (GET_CODE (addr) == PLUS)
16865 if (GET_CODE (XEXP (addr, 0)) == REG
16866 && REGNO (XEXP (addr, 0)) != 0)
16867 addr = XEXP (addr, 0);
16868 else if (GET_CODE (XEXP (addr, 1)) == REG
16869 && REGNO (XEXP (addr, 1)) != 0)
16870 addr = XEXP (addr, 1);
16871 else if (CONSTANT_P (XEXP (addr, 0)))
16872 addr = XEXP (addr, 1);
16873 else if (CONSTANT_P (XEXP (addr, 1)))
16874 addr = XEXP (addr, 0);
16876 gcc_unreachable ();
16878 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
16883 rs6000_fatal_bad_address (rtx op)
16885 fatal_insn ("bad address", op);
16890 static tree branch_island_list = 0;
16892 /* Remember to generate a branch island for far calls to the given
16896 add_compiler_branch_island (tree label_name, tree function_name,
16899 tree branch_island = build_tree_list (function_name, label_name);
16900 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
16901 TREE_CHAIN (branch_island) = branch_island_list;
16902 branch_island_list = branch_island;
16905 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16906 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16907 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16908 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
16910 /* Generate far-jump branch islands for everything on the
16911 branch_island_list. Invoked immediately after the last instruction
16912 of the epilogue has been emitted; the branch-islands must be
16913 appended to, and contiguous with, the function body. Mach-O stubs
16914 are generated in machopic_output_stub(). */
16917 macho_branch_islands (void)
16920 tree branch_island;
16922 for (branch_island = branch_island_list;
16924 branch_island = TREE_CHAIN (branch_island))
16926 const char *label =
16927 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
16929 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
16930 char name_buf[512];
16931 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16932 if (name[0] == '*' || name[0] == '&')
16933 strcpy (name_buf, name+1);
16937 strcpy (name_buf+1, name);
16939 strcpy (tmp_buf, "\n");
16940 strcat (tmp_buf, label);
16941 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16942 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16943 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
16944 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16947 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
16948 strcat (tmp_buf, label);
16949 strcat (tmp_buf, "_pic\n");
16950 strcat (tmp_buf, label);
16951 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
16953 strcat (tmp_buf, "\taddis r11,r11,ha16(");
16954 strcat (tmp_buf, name_buf);
16955 strcat (tmp_buf, " - ");
16956 strcat (tmp_buf, label);
16957 strcat (tmp_buf, "_pic)\n");
16959 strcat (tmp_buf, "\tmtlr r0\n");
16961 strcat (tmp_buf, "\taddi r12,r11,lo16(");
16962 strcat (tmp_buf, name_buf);
16963 strcat (tmp_buf, " - ");
16964 strcat (tmp_buf, label);
16965 strcat (tmp_buf, "_pic)\n");
16967 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
16971 strcat (tmp_buf, ":\nlis r12,hi16(");
16972 strcat (tmp_buf, name_buf);
16973 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
16974 strcat (tmp_buf, name_buf);
16975 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
16977 output_asm_insn (tmp_buf, 0);
16978 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16979 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16980 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
16981 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16984 branch_island_list = 0;
16987 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
16988 already there or not. */
16991 no_previous_def (tree function_name)
16993 tree branch_island;
16994 for (branch_island = branch_island_list;
16996 branch_island = TREE_CHAIN (branch_island))
16997 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17002 /* GET_PREV_LABEL gets the label name from the previous definition of
17006 get_prev_label (tree function_name)
17008 tree branch_island;
17009 for (branch_island = branch_island_list;
17011 branch_island = TREE_CHAIN (branch_island))
17012 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17013 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17017 /* INSN is either a function call or a millicode call. It may have an
17018 unconditional jump in its delay slot.
17020 CALL_DEST is the routine we are calling. */
17023 output_call (rtx insn, rtx *operands, int dest_operand_number,
17024 int cookie_operand_number)
17026 static char buf[256];
17027 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17028 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17031 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17033 if (no_previous_def (funname))
17035 int line_number = 0;
17036 rtx label_rtx = gen_label_rtx ();
17037 char *label_buf, temp_buf[256];
17038 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17039 CODE_LABEL_NUMBER (label_rtx));
17040 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17041 labelname = get_identifier (label_buf);
17042 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17044 line_number = NOTE_LINE_NUMBER (insn);
17045 add_compiler_branch_island (labelname, funname, line_number);
17048 labelname = get_prev_label (funname);
17050 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17051 instruction will reach 'foo', otherwise link as 'bl L42'".
17052 "L42" should be a 'branch island', that will do a far jump to
17053 'foo'. Branch islands are generated in
17054 macho_branch_islands(). */
17055 sprintf (buf, "jbsr %%z%d,%.246s",
17056 dest_operand_number, IDENTIFIER_POINTER (labelname));
17059 sprintf (buf, "bl %%z%d", dest_operand_number);
17063 /* Generate PIC and indirect symbol stubs. */
17066 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17068 unsigned int length;
17069 char *symbol_name, *lazy_ptr_name;
17070 char *local_label_0;
17071 static int label = 0;
17073 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17074 symb = (*targetm.strip_name_encoding) (symb);
17077 length = strlen (symb);
17078 symbol_name = alloca (length + 32);
17079 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17081 lazy_ptr_name = alloca (length + 32);
17082 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17085 machopic_picsymbol_stub1_section ();
17087 machopic_symbol_stub1_section ();
17091 fprintf (file, "\t.align 5\n");
17093 fprintf (file, "%s:\n", stub);
17094 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17097 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
17098 sprintf (local_label_0, "\"L%011d$spb\"", label);
17100 fprintf (file, "\tmflr r0\n");
17101 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17102 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17103 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17104 lazy_ptr_name, local_label_0);
17105 fprintf (file, "\tmtlr r0\n");
17106 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17107 (TARGET_64BIT ? "ldu" : "lwzu"),
17108 lazy_ptr_name, local_label_0);
17109 fprintf (file, "\tmtctr r12\n");
17110 fprintf (file, "\tbctr\n");
17114 fprintf (file, "\t.align 4\n");
17116 fprintf (file, "%s:\n", stub);
17117 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17119 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17120 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17121 (TARGET_64BIT ? "ldu" : "lwzu"),
17123 fprintf (file, "\tmtctr r12\n");
17124 fprintf (file, "\tbctr\n");
17127 machopic_lazy_symbol_ptr_section ();
17128 fprintf (file, "%s:\n", lazy_ptr_name);
17129 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17130 fprintf (file, "%sdyld_stub_binding_helper\n",
17131 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17134 /* Legitimize PIC addresses. If the address is already
17135 position-independent, we return ORIG. Newly generated
17136 position-independent addresses go into a reg. This is REG if non
17137 zero, otherwise we allocate register(s) as necessary. */
17139 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
17142 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17147 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17148 reg = gen_reg_rtx (Pmode);
17150 if (GET_CODE (orig) == CONST)
17154 if (GET_CODE (XEXP (orig, 0)) == PLUS
17155 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17158 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
17160 /* Use a different reg for the intermediate value, as
17161 it will be marked UNCHANGING. */
17162 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17163 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17166 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17169 if (GET_CODE (offset) == CONST_INT)
17171 if (SMALL_INT (offset))
17172 return plus_constant (base, INTVAL (offset));
17173 else if (! reload_in_progress && ! reload_completed)
17174 offset = force_reg (Pmode, offset);
17177 rtx mem = force_const_mem (Pmode, orig);
17178 return machopic_legitimize_pic_address (mem, Pmode, reg);
17181 return gen_rtx_PLUS (Pmode, base, offset);
17184 /* Fall back on generic machopic code. */
17185 return machopic_legitimize_pic_address (orig, mode, reg);
17188 /* This is just a placeholder to make linking work without having to
17189 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17190 ever needed for Darwin (not too likely!) this would have to get a
17191 real definition. */
17198 /* Output a .machine directive for the Darwin assembler, and call
17199 the generic start_file routine. */
17202 rs6000_darwin_file_start (void)
17204 static const struct
17210 { "ppc64", "ppc64", MASK_64BIT },
17211 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17212 { "power4", "ppc970", 0 },
17213 { "G5", "ppc970", 0 },
17214 { "7450", "ppc7450", 0 },
17215 { "7400", "ppc7400", MASK_ALTIVEC },
17216 { "G4", "ppc7400", 0 },
17217 { "750", "ppc750", 0 },
17218 { "740", "ppc750", 0 },
17219 { "G3", "ppc750", 0 },
17220 { "604e", "ppc604e", 0 },
17221 { "604", "ppc604", 0 },
17222 { "603e", "ppc603", 0 },
17223 { "603", "ppc603", 0 },
17224 { "601", "ppc601", 0 },
17225 { NULL, "ppc", 0 } };
17226 const char *cpu_id = "";
17229 rs6000_file_start ();
17231 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17232 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17233 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17234 && rs6000_select[i].string[0] != '\0')
17235 cpu_id = rs6000_select[i].string;
17237 /* Look through the mapping array. Pick the first name that either
17238 matches the argument, has a bit set in IF_SET that is also set
17239 in the target flags, or has a NULL name. */
17242 while (mapping[i].arg != NULL
17243 && strcmp (mapping[i].arg, cpu_id) != 0
17244 && (mapping[i].if_set & target_flags) == 0)
17247 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17250 #endif /* TARGET_MACHO */
17253 static unsigned int
17254 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
17256 return default_section_type_flags_1 (decl, name, reloc,
17257 flag_pic || DEFAULT_ABI == ABI_AIX);
17260 /* Record an element in the table of global constructors. SYMBOL is
17261 a SYMBOL_REF of the function to be called; PRIORITY is a number
17262 between 0 and MAX_INIT_PRIORITY.
17264 This differs from default_named_section_asm_out_constructor in
17265 that we have special handling for -mrelocatable. */
17268 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
17270 const char *section = ".ctors";
17273 if (priority != DEFAULT_INIT_PRIORITY)
17275 sprintf (buf, ".ctors.%.5u",
17276 /* Invert the numbering so the linker puts us in the proper
17277 order; constructors are run from right to left, and the
17278 linker sorts in increasing order. */
17279 MAX_INIT_PRIORITY - priority);
17283 named_section_flags (section, SECTION_WRITE);
17284 assemble_align (POINTER_SIZE);
17286 if (TARGET_RELOCATABLE)
17288 fputs ("\t.long (", asm_out_file);
17289 output_addr_const (asm_out_file, symbol);
17290 fputs (")@fixup\n", asm_out_file);
17293 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17297 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
17299 const char *section = ".dtors";
17302 if (priority != DEFAULT_INIT_PRIORITY)
17304 sprintf (buf, ".dtors.%.5u",
17305 /* Invert the numbering so the linker puts us in the proper
17306 order; constructors are run from right to left, and the
17307 linker sorts in increasing order. */
17308 MAX_INIT_PRIORITY - priority);
17312 named_section_flags (section, SECTION_WRITE);
17313 assemble_align (POINTER_SIZE);
17315 if (TARGET_RELOCATABLE)
17317 fputs ("\t.long (", asm_out_file);
17318 output_addr_const (asm_out_file, symbol);
17319 fputs (")@fixup\n", asm_out_file);
17322 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17326 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
17330 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17331 ASM_OUTPUT_LABEL (file, name);
17332 fputs (DOUBLE_INT_ASM_OP, file);
17333 rs6000_output_function_entry (file, name);
17334 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17337 fputs ("\t.size\t", file);
17338 assemble_name (file, name);
17339 fputs (",24\n\t.type\t.", file);
17340 assemble_name (file, name);
17341 fputs (",@function\n", file);
17342 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17344 fputs ("\t.globl\t.", file);
17345 assemble_name (file, name);
17350 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17351 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17352 rs6000_output_function_entry (file, name);
17353 fputs (":\n", file);
17357 if (TARGET_RELOCATABLE
17358 && !TARGET_SECURE_PLT
17359 && (get_pool_size () != 0 || current_function_profile)
17364 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
17366 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
17367 fprintf (file, "\t.long ");
17368 assemble_name (file, buf);
17370 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
17371 assemble_name (file, buf);
17375 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17376 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17378 if (DEFAULT_ABI == ABI_AIX)
17380 const char *desc_name, *orig_name;
17382 orig_name = (*targetm.strip_name_encoding) (name);
17383 desc_name = orig_name;
17384 while (*desc_name == '.')
17387 if (TREE_PUBLIC (decl))
17388 fprintf (file, "\t.globl %s\n", desc_name);
17390 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17391 fprintf (file, "%s:\n", desc_name);
17392 fprintf (file, "\t.long %s\n", orig_name);
17393 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
17394 if (DEFAULT_ABI == ABI_AIX)
17395 fputs ("\t.long 0\n", file);
17396 fprintf (file, "\t.previous\n");
17398 ASM_OUTPUT_LABEL (file, name);
17402 rs6000_elf_end_indicate_exec_stack (void)
17405 file_end_indicate_exec_stack ();
17411 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
17413 fputs (GLOBAL_ASM_OP, stream);
17414 RS6000_OUTPUT_BASENAME (stream, name);
17415 putc ('\n', stream);
17419 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
17420 tree decl ATTRIBUTE_UNUSED)
17423 static const char * const suffix[3] = { "PR", "RO", "RW" };
17425 if (flags & SECTION_CODE)
17427 else if (flags & SECTION_WRITE)
17432 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
17433 (flags & SECTION_CODE) ? "." : "",
17434 name, suffix[smclass], flags & SECTION_ENTSIZE);
17438 rs6000_xcoff_select_section (tree decl, int reloc,
17439 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17441 if (decl_readonly_section_1 (decl, reloc, 1))
17443 if (TREE_PUBLIC (decl))
17444 read_only_data_section ();
17446 read_only_private_data_section ();
17450 if (TREE_PUBLIC (decl))
17453 private_data_section ();
17458 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
17462 /* Use select_section for private and uninitialized data. */
17463 if (!TREE_PUBLIC (decl)
17464 || DECL_COMMON (decl)
17465 || DECL_INITIAL (decl) == NULL_TREE
17466 || DECL_INITIAL (decl) == error_mark_node
17467 || (flag_zero_initialized_in_bss
17468 && initializer_zerop (DECL_INITIAL (decl))))
17471 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
17472 name = (*targetm.strip_name_encoding) (name);
17473 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
17476 /* Select section for constant in constant pool.
17478 On RS/6000, all constants are in the private read-only data area.
17479 However, if this is being placed in the TOC it must be output as a
17483 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
17484 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17486 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17489 read_only_private_data_section ();
17492 /* Remove any trailing [DS] or the like from the symbol name. */
17494 static const char *
17495 rs6000_xcoff_strip_name_encoding (const char *name)
17500 len = strlen (name);
17501 if (name[len - 1] == ']')
17502 return ggc_alloc_string (name, len - 4);
17507 /* Section attributes. AIX is always PIC. */
17509 static unsigned int
17510 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
17512 unsigned int align;
17513 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
17515 /* Align to at least UNIT size. */
17516 if (flags & SECTION_CODE)
17517 align = MIN_UNITS_PER_WORD;
17519 /* Increase alignment of large objects if not already stricter. */
17520 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
17521 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
17522 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
17524 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
17527 /* Output at beginning of assembler file.
17529 Initialize the section names for the RS/6000 at this point.
17531 Specify filename, including full path, to assembler.
17533 We want to go into the TOC section so at least one .toc will be emitted.
17534 Also, in order to output proper .bs/.es pairs, we need at least one static
17535 [RW] section emitted.
17537 Finally, declare mcount when profiling to make the assembler happy. */
17540 rs6000_xcoff_file_start (void)
17542 rs6000_gen_section_name (&xcoff_bss_section_name,
17543 main_input_filename, ".bss_");
17544 rs6000_gen_section_name (&xcoff_private_data_section_name,
17545 main_input_filename, ".rw_");
17546 rs6000_gen_section_name (&xcoff_read_only_section_name,
17547 main_input_filename, ".ro_");
17549 fputs ("\t.file\t", asm_out_file);
17550 output_quoted_string (asm_out_file, main_input_filename);
17551 fputc ('\n', asm_out_file);
17552 if (write_symbols != NO_DEBUG)
17553 private_data_section ();
17556 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
17557 rs6000_file_start ();
17560 /* Output at end of assembler file.
17561 On the RS/6000, referencing data should automatically pull in text. */
17564 rs6000_xcoff_file_end (void)
17567 fputs ("_section_.text:\n", asm_out_file);
17569 fputs (TARGET_32BIT
17570 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
17573 #endif /* TARGET_XCOFF */
17575 /* Compute a (partial) cost for rtx X. Return true if the complete
17576 cost has been computed, and false if subexpressions should be
17577 scanned. In either case, *TOTAL contains the cost result. */
17580 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
17582 enum machine_mode mode = GET_MODE (x);
17586 /* On the RS/6000, if it is valid in the insn, it is free. */
17588 if (((outer_code == SET
17589 || outer_code == PLUS
17590 || outer_code == MINUS)
17591 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17592 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
17593 || (outer_code == AND
17594 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17595 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17596 mode == SImode ? 'L' : 'J'))
17597 || mask_operand (x, VOIDmode)))
17598 || ((outer_code == IOR || outer_code == XOR)
17599 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17600 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17601 mode == SImode ? 'L' : 'J'))))
17602 || outer_code == ASHIFT
17603 || outer_code == ASHIFTRT
17604 || outer_code == LSHIFTRT
17605 || outer_code == ROTATE
17606 || outer_code == ROTATERT
17607 || outer_code == ZERO_EXTRACT
17608 || (outer_code == MULT
17609 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
17610 || ((outer_code == DIV || outer_code == UDIV
17611 || outer_code == MOD || outer_code == UMOD)
17612 && exact_log2 (INTVAL (x)) >= 0)
17613 || (outer_code == COMPARE
17614 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17615 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
17616 || (outer_code == EQ
17617 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17618 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17619 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17620 mode == SImode ? 'L' : 'J'))))
17621 || (outer_code == GTU
17622 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
17623 || (outer_code == LTU
17624 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
17629 else if ((outer_code == PLUS
17630 && reg_or_add_cint_operand (x, VOIDmode))
17631 || (outer_code == MINUS
17632 && reg_or_sub_cint_operand (x, VOIDmode))
17633 || ((outer_code == SET
17634 || outer_code == IOR
17635 || outer_code == XOR)
17637 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
17639 *total = COSTS_N_INSNS (1);
17646 && ((outer_code == AND
17647 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17648 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
17649 || mask_operand (x, DImode)))
17650 || ((outer_code == IOR || outer_code == XOR)
17651 && CONST_DOUBLE_HIGH (x) == 0
17652 && (CONST_DOUBLE_LOW (x)
17653 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
17658 else if (mode == DImode
17659 && (outer_code == SET
17660 || outer_code == IOR
17661 || outer_code == XOR)
17662 && CONST_DOUBLE_HIGH (x) == 0)
17664 *total = COSTS_N_INSNS (1);
17673 /* When optimizing for size, MEM should be slightly more expensive
17674 than generating address, e.g., (plus (reg) (const)).
17675 L1 cache latency is about two instructions. */
17676 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
17684 if (mode == DFmode)
17686 if (GET_CODE (XEXP (x, 0)) == MULT)
17688 /* FNMA accounted in outer NEG. */
17689 if (outer_code == NEG)
17690 *total = rs6000_cost->dmul - rs6000_cost->fp;
17692 *total = rs6000_cost->dmul;
17695 *total = rs6000_cost->fp;
17697 else if (mode == SFmode)
17699 /* FNMA accounted in outer NEG. */
17700 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17703 *total = rs6000_cost->fp;
17705 else if (GET_CODE (XEXP (x, 0)) == MULT)
17707 /* The rs6000 doesn't have shift-and-add instructions. */
17708 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
17709 *total += COSTS_N_INSNS (1);
17712 *total = COSTS_N_INSNS (1);
17716 if (mode == DFmode)
17718 if (GET_CODE (XEXP (x, 0)) == MULT)
17720 /* FNMA accounted in outer NEG. */
17721 if (outer_code == NEG)
17724 *total = rs6000_cost->dmul;
17727 *total = rs6000_cost->fp;
17729 else if (mode == SFmode)
17731 /* FNMA accounted in outer NEG. */
17732 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17735 *total = rs6000_cost->fp;
17737 else if (GET_CODE (XEXP (x, 0)) == MULT)
17739 /* The rs6000 doesn't have shift-and-sub instructions. */
17740 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
17741 *total += COSTS_N_INSNS (1);
17744 *total = COSTS_N_INSNS (1);
17748 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17749 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
17751 if (INTVAL (XEXP (x, 1)) >= -256
17752 && INTVAL (XEXP (x, 1)) <= 255)
17753 *total = rs6000_cost->mulsi_const9;
17755 *total = rs6000_cost->mulsi_const;
17757 /* FMA accounted in outer PLUS/MINUS. */
17758 else if ((mode == DFmode || mode == SFmode)
17759 && (outer_code == PLUS || outer_code == MINUS))
17761 else if (mode == DFmode)
17762 *total = rs6000_cost->dmul;
17763 else if (mode == SFmode)
17764 *total = rs6000_cost->fp;
17765 else if (mode == DImode)
17766 *total = rs6000_cost->muldi;
17768 *total = rs6000_cost->mulsi;
17773 if (FLOAT_MODE_P (mode))
17775 *total = mode == DFmode ? rs6000_cost->ddiv
17776 : rs6000_cost->sdiv;
17783 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17784 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17786 if (code == DIV || code == MOD)
17788 *total = COSTS_N_INSNS (2);
17791 *total = COSTS_N_INSNS (1);
17795 if (GET_MODE (XEXP (x, 1)) == DImode)
17796 *total = rs6000_cost->divdi;
17798 *total = rs6000_cost->divsi;
17800 /* Add in shift and subtract for MOD. */
17801 if (code == MOD || code == UMOD)
17802 *total += COSTS_N_INSNS (2);
17806 *total = COSTS_N_INSNS (4);
17810 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17821 *total = COSTS_N_INSNS (1);
17829 /* Handle mul_highpart. */
17830 if (outer_code == TRUNCATE
17831 && GET_CODE (XEXP (x, 0)) == MULT)
17833 if (mode == DImode)
17834 *total = rs6000_cost->muldi;
17836 *total = rs6000_cost->mulsi;
17839 else if (outer_code == AND)
17842 *total = COSTS_N_INSNS (1);
17847 if (GET_CODE (XEXP (x, 0)) == MEM)
17850 *total = COSTS_N_INSNS (1);
17856 if (!FLOAT_MODE_P (mode))
17858 *total = COSTS_N_INSNS (1);
17864 case UNSIGNED_FLOAT:
17868 case FLOAT_TRUNCATE:
17869 *total = rs6000_cost->fp;
17873 switch (XINT (x, 1))
17876 *total = rs6000_cost->fp;
17888 *total = COSTS_N_INSNS (1);
17891 else if (FLOAT_MODE_P (mode)
17892 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17894 *total = rs6000_cost->fp;
17902 /* Carry bit requires mode == Pmode.
17903 NEG or PLUS already counted so only add one. */
17905 && (outer_code == NEG || outer_code == PLUS))
17907 *total = COSTS_N_INSNS (1);
17910 if (outer_code == SET)
17912 if (XEXP (x, 1) == const0_rtx)
17914 *total = COSTS_N_INSNS (2);
17917 else if (mode == Pmode)
17919 *total = COSTS_N_INSNS (3);
17928 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
17930 *total = COSTS_N_INSNS (2);
17934 if (outer_code == COMPARE)
17948 /* A C expression returning the cost of moving data from a register of class
17949 CLASS1 to one of CLASS2. */
17952 rs6000_register_move_cost (enum machine_mode mode,
17953 enum reg_class from, enum reg_class to)
17955 /* Moves from/to GENERAL_REGS. */
17956 if (reg_classes_intersect_p (to, GENERAL_REGS)
17957 || reg_classes_intersect_p (from, GENERAL_REGS))
17959 if (! reg_classes_intersect_p (to, GENERAL_REGS))
17962 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
17963 return (rs6000_memory_move_cost (mode, from, 0)
17964 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
17966 /* It's more expensive to move CR_REGS than CR0_REGS because of the
17968 else if (from == CR_REGS)
17972 /* A move will cost one instruction per GPR moved. */
17973 return 2 * hard_regno_nregs[0][mode];
17976 /* Moving between two similar registers is just one instruction. */
17977 else if (reg_classes_intersect_p (to, from))
17978 return mode == TFmode ? 4 : 2;
17980 /* Everything else has to go through GENERAL_REGS. */
17982 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
17983 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
17986 /* A C expressions returning the cost of moving data of MODE from a register to
17990 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
17991 int in ATTRIBUTE_UNUSED)
17993 if (reg_classes_intersect_p (class, GENERAL_REGS))
17994 return 4 * hard_regno_nregs[0][mode];
17995 else if (reg_classes_intersect_p (class, FLOAT_REGS))
17996 return 4 * hard_regno_nregs[32][mode];
17997 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
17998 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
18000 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18003 /* Newton-Raphson approximation of single-precision floating point divide n/d.
18004 Assumes no trapping math and finite arguments. */
18007 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
18009 rtx x0, e0, e1, y1, u0, v0, one;
18011 x0 = gen_reg_rtx (SFmode);
18012 e0 = gen_reg_rtx (SFmode);
18013 e1 = gen_reg_rtx (SFmode);
18014 y1 = gen_reg_rtx (SFmode);
18015 u0 = gen_reg_rtx (SFmode);
18016 v0 = gen_reg_rtx (SFmode);
18017 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
18019 /* x0 = 1./d estimate */
18020 emit_insn (gen_rtx_SET (VOIDmode, x0,
18021 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
18023 /* e0 = 1. - d * x0 */
18024 emit_insn (gen_rtx_SET (VOIDmode, e0,
18025 gen_rtx_MINUS (SFmode, one,
18026 gen_rtx_MULT (SFmode, d, x0))));
18027 /* e1 = e0 + e0 * e0 */
18028 emit_insn (gen_rtx_SET (VOIDmode, e1,
18029 gen_rtx_PLUS (SFmode,
18030 gen_rtx_MULT (SFmode, e0, e0), e0)));
18031 /* y1 = x0 + e1 * x0 */
18032 emit_insn (gen_rtx_SET (VOIDmode, y1,
18033 gen_rtx_PLUS (SFmode,
18034 gen_rtx_MULT (SFmode, e1, x0), x0)));
18036 emit_insn (gen_rtx_SET (VOIDmode, u0,
18037 gen_rtx_MULT (SFmode, n, y1)));
18038 /* v0 = n - d * u0 */
18039 emit_insn (gen_rtx_SET (VOIDmode, v0,
18040 gen_rtx_MINUS (SFmode, n,
18041 gen_rtx_MULT (SFmode, d, u0))));
18042 /* res = u0 + v0 * y1 */
18043 emit_insn (gen_rtx_SET (VOIDmode, res,
18044 gen_rtx_PLUS (SFmode,
18045 gen_rtx_MULT (SFmode, v0, y1), u0)));
18048 /* Newton-Raphson approximation of double-precision floating point divide n/d.
18049 Assumes no trapping math and finite arguments. */
18052 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
18054 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
18056 x0 = gen_reg_rtx (DFmode);
18057 e0 = gen_reg_rtx (DFmode);
18058 e1 = gen_reg_rtx (DFmode);
18059 e2 = gen_reg_rtx (DFmode);
18060 y1 = gen_reg_rtx (DFmode);
18061 y2 = gen_reg_rtx (DFmode);
18062 y3 = gen_reg_rtx (DFmode);
18063 u0 = gen_reg_rtx (DFmode);
18064 v0 = gen_reg_rtx (DFmode);
18065 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
18067 /* x0 = 1./d estimate */
18068 emit_insn (gen_rtx_SET (VOIDmode, x0,
18069 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
18071 /* e0 = 1. - d * x0 */
18072 emit_insn (gen_rtx_SET (VOIDmode, e0,
18073 gen_rtx_MINUS (DFmode, one,
18074 gen_rtx_MULT (SFmode, d, x0))));
18075 /* y1 = x0 + e0 * x0 */
18076 emit_insn (gen_rtx_SET (VOIDmode, y1,
18077 gen_rtx_PLUS (DFmode,
18078 gen_rtx_MULT (DFmode, e0, x0), x0)));
18080 emit_insn (gen_rtx_SET (VOIDmode, e1,
18081 gen_rtx_MULT (DFmode, e0, e0)));
18082 /* y2 = y1 + e1 * y1 */
18083 emit_insn (gen_rtx_SET (VOIDmode, y2,
18084 gen_rtx_PLUS (DFmode,
18085 gen_rtx_MULT (DFmode, e1, y1), y1)));
18087 emit_insn (gen_rtx_SET (VOIDmode, e2,
18088 gen_rtx_MULT (DFmode, e1, e1)));
18089 /* y3 = y2 + e2 * y2 */
18090 emit_insn (gen_rtx_SET (VOIDmode, y3,
18091 gen_rtx_PLUS (DFmode,
18092 gen_rtx_MULT (DFmode, e2, y2), y2)));
18094 emit_insn (gen_rtx_SET (VOIDmode, u0,
18095 gen_rtx_MULT (DFmode, n, y3)));
18096 /* v0 = n - d * u0 */
18097 emit_insn (gen_rtx_SET (VOIDmode, v0,
18098 gen_rtx_MINUS (DFmode, n,
18099 gen_rtx_MULT (DFmode, d, u0))));
18100 /* res = u0 + v0 * y3 */
18101 emit_insn (gen_rtx_SET (VOIDmode, res,
18102 gen_rtx_PLUS (DFmode,
18103 gen_rtx_MULT (DFmode, v0, y3), u0)));
18106 /* Return an RTX representing where to find the function value of a
18107 function returning MODE. */
18109 rs6000_complex_function_value (enum machine_mode mode)
18111 unsigned int regno;
18113 enum machine_mode inner = GET_MODE_INNER (mode);
18114 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18116 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18117 regno = FP_ARG_RETURN;
18120 regno = GP_ARG_RETURN;
18122 /* 32-bit is OK since it'll go in r3/r4. */
18123 if (TARGET_32BIT && inner_bytes >= 4)
18124 return gen_rtx_REG (mode, regno);
18127 if (inner_bytes >= 8)
18128 return gen_rtx_REG (mode, regno);
18130 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18132 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18133 GEN_INT (inner_bytes));
18134 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18137 /* Define how to find the value returned by a function.
18138 VALTYPE is the data type of the value (as a tree).
18139 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18140 otherwise, FUNC is 0.
18142 On the SPE, both FPs and vectors are returned in r3.
18144 On RS/6000 an integer value is in r3 and a floating-point value is in
18145 fp1, unless -msoft-float. */
18148 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18150 enum machine_mode mode;
18151 unsigned int regno;
18153 /* Special handling for structs in darwin64. */
18154 if (rs6000_darwin64_abi
18155 && TYPE_MODE (valtype) == BLKmode
18156 && TREE_CODE (valtype) == RECORD_TYPE
18157 && int_size_in_bytes (valtype) > 0)
18159 CUMULATIVE_ARGS valcum;
18163 valcum.fregno = FP_ARG_MIN_REG;
18164 valcum.vregno = ALTIVEC_ARG_MIN_REG;
18165 /* Do a trial code generation as if this were going to be passed as
18166 an argument; if any part goes in memory, we return NULL. */
18167 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
18170 /* Otherwise fall through to standard ABI rules. */
18173 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18175 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18176 return gen_rtx_PARALLEL (DImode,
18178 gen_rtx_EXPR_LIST (VOIDmode,
18179 gen_rtx_REG (SImode, GP_ARG_RETURN),
18181 gen_rtx_EXPR_LIST (VOIDmode,
18182 gen_rtx_REG (SImode,
18183 GP_ARG_RETURN + 1),
18187 if ((INTEGRAL_TYPE_P (valtype)
18188 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18189 || POINTER_TYPE_P (valtype))
18190 mode = TARGET_32BIT ? SImode : DImode;
18192 mode = TYPE_MODE (valtype);
18194 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
18195 regno = FP_ARG_RETURN;
18196 else if (TREE_CODE (valtype) == COMPLEX_TYPE
18197 && targetm.calls.split_complex_arg)
18198 return rs6000_complex_function_value (mode);
18199 else if (TREE_CODE (valtype) == VECTOR_TYPE
18200 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
18201 && ALTIVEC_VECTOR_MODE (mode))
18202 regno = ALTIVEC_ARG_RETURN;
18203 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18204 && (mode == DFmode || mode == DCmode))
18205 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18207 regno = GP_ARG_RETURN;
18209 return gen_rtx_REG (mode, regno);
18212 /* Define how to find the value returned by a library function
18213 assuming the value has mode MODE. */
18215 rs6000_libcall_value (enum machine_mode mode)
18217 unsigned int regno;
18219 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18221 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18222 return gen_rtx_PARALLEL (DImode,
18224 gen_rtx_EXPR_LIST (VOIDmode,
18225 gen_rtx_REG (SImode, GP_ARG_RETURN),
18227 gen_rtx_EXPR_LIST (VOIDmode,
18228 gen_rtx_REG (SImode,
18229 GP_ARG_RETURN + 1),
18233 if (GET_MODE_CLASS (mode) == MODE_FLOAT
18234 && TARGET_HARD_FLOAT && TARGET_FPRS)
18235 regno = FP_ARG_RETURN;
18236 else if (ALTIVEC_VECTOR_MODE (mode)
18237 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
18238 regno = ALTIVEC_ARG_RETURN;
18239 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
18240 return rs6000_complex_function_value (mode);
18241 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18242 && (mode == DFmode || mode == DCmode))
18243 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18245 regno = GP_ARG_RETURN;
18247 return gen_rtx_REG (mode, regno);
18250 /* Define the offset between two registers, FROM to be eliminated and its
18251 replacement TO, at the start of a routine. */
18253 rs6000_initial_elimination_offset (int from, int to)
18255 rs6000_stack_t *info = rs6000_stack_info ();
18256 HOST_WIDE_INT offset;
18258 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18259 offset = info->push_p ? 0 : -info->total_size;
18260 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18262 offset = info->push_p ? 0 : -info->total_size;
18263 if (FRAME_GROWS_DOWNWARD)
18264 offset += info->fixed_size + info->varargs_size
18265 + info->vars_size + info->parm_size;
18267 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
18268 offset = FRAME_GROWS_DOWNWARD
18269 ? info->fixed_size + info->varargs_size
18270 + info->vars_size + info->parm_size
18272 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
18273 offset = info->total_size;
18274 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18275 offset = info->push_p ? info->total_size : 0;
18276 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
18279 gcc_unreachable ();
18284 /* Return true if TYPE is a SPE or AltiVec opaque type. */
18287 rs6000_is_opaque_type (tree type)
18289 return (type == opaque_V2SI_type_node
18290 || type == opaque_V2SF_type_node
18291 || type == opaque_p_V2SI_type_node
18292 || type == opaque_V4SI_type_node);
18296 rs6000_dwarf_register_span (rtx reg)
18301 && (SPE_VECTOR_MODE (GET_MODE (reg))
18302 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
18307 regno = REGNO (reg);
18309 /* The duality of the SPE register size wreaks all kinds of havoc.
18310 This is a way of distinguishing r0 in 32-bits from r0 in
18313 gen_rtx_PARALLEL (VOIDmode,
18316 gen_rtx_REG (SImode, regno + 1200),
18317 gen_rtx_REG (SImode, regno))
18319 gen_rtx_REG (SImode, regno),
18320 gen_rtx_REG (SImode, regno + 1200)));
18323 /* Map internal gcc register numbers to DWARF2 register numbers. */
18326 rs6000_dbx_register_number (unsigned int regno)
18328 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
18330 if (regno == MQ_REGNO)
18332 if (regno == LINK_REGISTER_REGNUM)
18334 if (regno == COUNT_REGISTER_REGNUM)
18336 if (CR_REGNO_P (regno))
18337 return regno - CR0_REGNO + 86;
18338 if (regno == XER_REGNO)
18340 if (ALTIVEC_REGNO_P (regno))
18341 return regno - FIRST_ALTIVEC_REGNO + 1124;
18342 if (regno == VRSAVE_REGNO)
18344 if (regno == VSCR_REGNO)
18346 if (regno == SPE_ACC_REGNO)
18348 if (regno == SPEFSCR_REGNO)
18350 /* SPE high reg number. We get these values of regno from
18351 rs6000_dwarf_register_span. */
18352 gcc_assert (regno >= 1200 && regno < 1232);
18356 /* target hook eh_return_filter_mode */
18357 static enum machine_mode
18358 rs6000_eh_return_filter_mode (void)
18360 return TARGET_32BIT ? SImode : word_mode;
18363 /* Target hook for vector_mode_supported_p. */
18365 rs6000_vector_mode_supported_p (enum machine_mode mode)
18368 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
18371 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
18378 /* Target hook for invalid_arg_for_unprototyped_fn. */
18379 static const char *
18380 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
18382 return (!rs6000_darwin64_abi
18384 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
18385 && (funcdecl == NULL_TREE
18386 || (TREE_CODE (funcdecl) == FUNCTION_DECL
18387 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
18388 ? N_("AltiVec argument passed to unprototyped function")
18392 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
18393 setup by using __stack_chk_fail_local hidden function instead of
18394 calling __stack_chk_fail directly. Otherwise it is better to call
18395 __stack_chk_fail directly. */
18398 rs6000_stack_protect_fail (void)
18400 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
18401 ? default_hidden_stack_protect_fail ()
18402 : default_external_stack_protect_fail ();
18405 #include "gt-rs6000.h"