1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "tm-constrs.h"
60 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
63 #include "gstab.h" /* for N_SLINE */
66 #ifndef TARGET_NO_PROTOTYPE
67 #define TARGET_NO_PROTOTYPE 0
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int push_p; /* true if we need to allocate stack space */
82 int calls_p; /* true if the function makes any calls */
83 int world_save_p; /* true if we're saving *everything*:
84 r13-r31, cr, f14-f31, vrsave, v20-v31 */
85 enum rs6000_abi abi; /* which ABI to use */
86 int gp_save_offset; /* offset to save GP regs from initial SP */
87 int fp_save_offset; /* offset to save FP regs from initial SP */
88 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
89 int lr_save_offset; /* offset to save LR from initial SP */
90 int cr_save_offset; /* offset to save CR from initial SP */
91 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
92 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 HOST_WIDE_INT vars_size; /* variable save area size */
97 int parm_size; /* outgoing parameter size */
98 int save_size; /* save area size */
99 int fixed_size; /* fixed size of stack frame */
100 int gp_size; /* size of saved GP registers */
101 int fp_size; /* size of saved FP registers */
102 int altivec_size; /* size of saved AltiVec registers */
103 int cr_size; /* size to hold CR if not in save_size */
104 int vrsave_size; /* size to hold VRSAVE if not in save_size */
105 int altivec_padding_size; /* size of altivec alignment padding if
107 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
108 int spe_padding_size;
109 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
110 int spe_64bit_regs_used;
113 /* A C structure for machine-specific, per-function data.
114 This is added to the cfun structure. */
115 typedef struct machine_function GTY(())
117 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
118 int ra_needs_full_frame;
119 /* Some local-dynamic symbol. */
120 const char *some_ld_name;
121 /* Whether the instruction chain has been scanned already. */
122 int insn_chain_scanned_p;
123 /* Flags if __builtin_return_address (0) was used. */
125 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
126 varargs save area. */
127 HOST_WIDE_INT varargs_save_offset;
130 /* Target cpu type */
132 enum processor_type rs6000_cpu;
133 struct rs6000_cpu_select rs6000_select[3] =
135 /* switch name, tune arch */
136 { (const char *)0, "--with-cpu=", 1, 1 },
137 { (const char *)0, "-mcpu=", 1, 1 },
138 { (const char *)0, "-mtune=", 1, 0 },
141 static GTY(()) bool rs6000_cell_dont_microcode;
143 /* Always emit branch hint bits. */
144 static GTY(()) bool rs6000_always_hint;
146 /* Schedule instructions for group formation. */
147 static GTY(()) bool rs6000_sched_groups;
149 /* Align branch targets. */
150 static GTY(()) bool rs6000_align_branch_targets;
152 /* Support for -msched-costly-dep option. */
153 const char *rs6000_sched_costly_dep_str;
154 enum rs6000_dependence_cost rs6000_sched_costly_dep;
156 /* Support for -minsert-sched-nops option. */
157 const char *rs6000_sched_insert_nops_str;
158 enum rs6000_nop_insertion rs6000_sched_insert_nops;
160 /* Support targetm.vectorize.builtin_mask_for_load. */
161 static GTY(()) tree altivec_builtin_mask_for_load;
163 /* Size of long double. */
164 int rs6000_long_double_type_size;
166 /* IEEE quad extended precision long double. */
169 /* Whether -mabi=altivec has appeared. */
170 int rs6000_altivec_abi;
172 /* Nonzero if we want SPE ABI extensions. */
175 /* Nonzero if floating point operations are done in the GPRs. */
176 int rs6000_float_gprs = 0;
178 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
179 int rs6000_darwin64_abi;
181 /* Set to nonzero once AIX common-mode calls have been defined. */
182 static GTY(()) int common_mode_defined;
184 /* Save information from a "cmpxx" operation until the branch or scc is
186 rtx rs6000_compare_op0, rs6000_compare_op1;
187 int rs6000_compare_fp_p;
189 /* Label number of label created for -mrelocatable, to call to so we can
190 get the address of the GOT section */
191 int rs6000_pic_labelno;
194 /* Which abi to adhere to */
195 const char *rs6000_abi_name;
197 /* Semantics of the small data area */
198 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
200 /* Which small data model to use */
201 const char *rs6000_sdata_name = (char *)0;
203 /* Counter for labels which are to be placed in .fixup. */
204 int fixuplabelno = 0;
207 /* Bit size of immediate TLS offsets and string from which it is decoded. */
208 int rs6000_tls_size = 32;
209 const char *rs6000_tls_size_string;
211 /* ABI enumeration available for subtarget to use. */
212 enum rs6000_abi rs6000_current_abi;
214 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
218 const char *rs6000_debug_name;
219 int rs6000_debug_stack; /* debug stack applications */
220 int rs6000_debug_arg; /* debug argument handling */
222 /* Value is TRUE if register/mode pair is acceptable. */
223 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
225 /* Built in types. */
227 tree rs6000_builtin_types[RS6000_BTI_MAX];
228 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
230 const char *rs6000_traceback_name;
232 traceback_default = 0,
238 /* Flag to say the TOC is initialized */
240 char toc_label_name[10];
242 /* Cached value of rs6000_variable_issue. This is cached in
243 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
244 static short cached_can_issue_more;
246 static GTY(()) section *read_only_data_section;
247 static GTY(()) section *private_data_section;
248 static GTY(()) section *read_only_private_data_section;
249 static GTY(()) section *sdata2_section;
250 static GTY(()) section *toc_section;
252 /* Control alignment for fields within structures. */
253 /* String from -malign-XXXXX. */
254 int rs6000_alignment_flags;
256 /* True for any options that were explicitly set. */
258 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
259 bool alignment; /* True if -malign- was used. */
260 bool abi; /* True if -mabi=spe/nospe was used. */
261 bool spe; /* True if -mspe= was used. */
262 bool float_gprs; /* True if -mfloat-gprs= was used. */
263 bool isel; /* True if -misel was used. */
264 bool long_double; /* True if -mlong-double- was used. */
265 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
266 } rs6000_explicit_options;
268 struct builtin_description
270 /* mask is not const because we're going to alter it below. This
271 nonsense will go away when we rewrite the -march infrastructure
272 to give us more target flag bits. */
274 const enum insn_code icode;
275 const char *const name;
276 const enum rs6000_builtins code;
279 /* Target cpu costs. */
281 struct processor_costs {
282 const int mulsi; /* cost of SImode multiplication. */
283 const int mulsi_const; /* cost of SImode multiplication by constant. */
284 const int mulsi_const9; /* cost of SImode mult by short constant. */
285 const int muldi; /* cost of DImode multiplication. */
286 const int divsi; /* cost of SImode division. */
287 const int divdi; /* cost of DImode division. */
288 const int fp; /* cost of simple SFmode and DFmode insns. */
289 const int dmul; /* cost of DFmode multiplication (and fmadd). */
290 const int sdiv; /* cost of SFmode division (fdivs). */
291 const int ddiv; /* cost of DFmode division (fdiv). */
292 const int cache_line_size; /* cache line size in bytes. */
293 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
294 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
295 const int simultaneous_prefetches; /* number of parallel prefetch
299 const struct processor_costs *rs6000_cost;
301 /* Processor costs (relative to an add) */
303 /* Instruction size costs on 32bit processors. */
305 struct processor_costs size32_cost = {
306 COSTS_N_INSNS (1), /* mulsi */
307 COSTS_N_INSNS (1), /* mulsi_const */
308 COSTS_N_INSNS (1), /* mulsi_const9 */
309 COSTS_N_INSNS (1), /* muldi */
310 COSTS_N_INSNS (1), /* divsi */
311 COSTS_N_INSNS (1), /* divdi */
312 COSTS_N_INSNS (1), /* fp */
313 COSTS_N_INSNS (1), /* dmul */
314 COSTS_N_INSNS (1), /* sdiv */
315 COSTS_N_INSNS (1), /* ddiv */
322 /* Instruction size costs on 64bit processors. */
324 struct processor_costs size64_cost = {
325 COSTS_N_INSNS (1), /* mulsi */
326 COSTS_N_INSNS (1), /* mulsi_const */
327 COSTS_N_INSNS (1), /* mulsi_const9 */
328 COSTS_N_INSNS (1), /* muldi */
329 COSTS_N_INSNS (1), /* divsi */
330 COSTS_N_INSNS (1), /* divdi */
331 COSTS_N_INSNS (1), /* fp */
332 COSTS_N_INSNS (1), /* dmul */
333 COSTS_N_INSNS (1), /* sdiv */
334 COSTS_N_INSNS (1), /* ddiv */
341 /* Instruction costs on RIOS1 processors. */
343 struct processor_costs rios1_cost = {
344 COSTS_N_INSNS (5), /* mulsi */
345 COSTS_N_INSNS (4), /* mulsi_const */
346 COSTS_N_INSNS (3), /* mulsi_const9 */
347 COSTS_N_INSNS (5), /* muldi */
348 COSTS_N_INSNS (19), /* divsi */
349 COSTS_N_INSNS (19), /* divdi */
350 COSTS_N_INSNS (2), /* fp */
351 COSTS_N_INSNS (2), /* dmul */
352 COSTS_N_INSNS (19), /* sdiv */
353 COSTS_N_INSNS (19), /* ddiv */
360 /* Instruction costs on RIOS2 processors. */
362 struct processor_costs rios2_cost = {
363 COSTS_N_INSNS (2), /* mulsi */
364 COSTS_N_INSNS (2), /* mulsi_const */
365 COSTS_N_INSNS (2), /* mulsi_const9 */
366 COSTS_N_INSNS (2), /* muldi */
367 COSTS_N_INSNS (13), /* divsi */
368 COSTS_N_INSNS (13), /* divdi */
369 COSTS_N_INSNS (2), /* fp */
370 COSTS_N_INSNS (2), /* dmul */
371 COSTS_N_INSNS (17), /* sdiv */
372 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on RS64A processors. */
381 struct processor_costs rs64a_cost = {
382 COSTS_N_INSNS (20), /* mulsi */
383 COSTS_N_INSNS (12), /* mulsi_const */
384 COSTS_N_INSNS (8), /* mulsi_const9 */
385 COSTS_N_INSNS (34), /* muldi */
386 COSTS_N_INSNS (65), /* divsi */
387 COSTS_N_INSNS (67), /* divdi */
388 COSTS_N_INSNS (4), /* fp */
389 COSTS_N_INSNS (4), /* dmul */
390 COSTS_N_INSNS (31), /* sdiv */
391 COSTS_N_INSNS (31), /* ddiv */
398 /* Instruction costs on MPCCORE processors. */
400 struct processor_costs mpccore_cost = {
401 COSTS_N_INSNS (2), /* mulsi */
402 COSTS_N_INSNS (2), /* mulsi_const */
403 COSTS_N_INSNS (2), /* mulsi_const9 */
404 COSTS_N_INSNS (2), /* muldi */
405 COSTS_N_INSNS (6), /* divsi */
406 COSTS_N_INSNS (6), /* divdi */
407 COSTS_N_INSNS (4), /* fp */
408 COSTS_N_INSNS (5), /* dmul */
409 COSTS_N_INSNS (10), /* sdiv */
410 COSTS_N_INSNS (17), /* ddiv */
417 /* Instruction costs on PPC403 processors. */
419 struct processor_costs ppc403_cost = {
420 COSTS_N_INSNS (4), /* mulsi */
421 COSTS_N_INSNS (4), /* mulsi_const */
422 COSTS_N_INSNS (4), /* mulsi_const9 */
423 COSTS_N_INSNS (4), /* muldi */
424 COSTS_N_INSNS (33), /* divsi */
425 COSTS_N_INSNS (33), /* divdi */
426 COSTS_N_INSNS (11), /* fp */
427 COSTS_N_INSNS (11), /* dmul */
428 COSTS_N_INSNS (11), /* sdiv */
429 COSTS_N_INSNS (11), /* ddiv */
436 /* Instruction costs on PPC405 processors. */
438 struct processor_costs ppc405_cost = {
439 COSTS_N_INSNS (5), /* mulsi */
440 COSTS_N_INSNS (4), /* mulsi_const */
441 COSTS_N_INSNS (3), /* mulsi_const9 */
442 COSTS_N_INSNS (5), /* muldi */
443 COSTS_N_INSNS (35), /* divsi */
444 COSTS_N_INSNS (35), /* divdi */
445 COSTS_N_INSNS (11), /* fp */
446 COSTS_N_INSNS (11), /* dmul */
447 COSTS_N_INSNS (11), /* sdiv */
448 COSTS_N_INSNS (11), /* ddiv */
455 /* Instruction costs on PPC440 processors. */
457 struct processor_costs ppc440_cost = {
458 COSTS_N_INSNS (3), /* mulsi */
459 COSTS_N_INSNS (2), /* mulsi_const */
460 COSTS_N_INSNS (2), /* mulsi_const9 */
461 COSTS_N_INSNS (3), /* muldi */
462 COSTS_N_INSNS (34), /* divsi */
463 COSTS_N_INSNS (34), /* divdi */
464 COSTS_N_INSNS (5), /* fp */
465 COSTS_N_INSNS (5), /* dmul */
466 COSTS_N_INSNS (19), /* sdiv */
467 COSTS_N_INSNS (33), /* ddiv */
474 /* Instruction costs on PPC601 processors. */
476 struct processor_costs ppc601_cost = {
477 COSTS_N_INSNS (5), /* mulsi */
478 COSTS_N_INSNS (5), /* mulsi_const */
479 COSTS_N_INSNS (5), /* mulsi_const9 */
480 COSTS_N_INSNS (5), /* muldi */
481 COSTS_N_INSNS (36), /* divsi */
482 COSTS_N_INSNS (36), /* divdi */
483 COSTS_N_INSNS (4), /* fp */
484 COSTS_N_INSNS (5), /* dmul */
485 COSTS_N_INSNS (17), /* sdiv */
486 COSTS_N_INSNS (31), /* ddiv */
493 /* Instruction costs on PPC603 processors. */
495 struct processor_costs ppc603_cost = {
496 COSTS_N_INSNS (5), /* mulsi */
497 COSTS_N_INSNS (3), /* mulsi_const */
498 COSTS_N_INSNS (2), /* mulsi_const9 */
499 COSTS_N_INSNS (5), /* muldi */
500 COSTS_N_INSNS (37), /* divsi */
501 COSTS_N_INSNS (37), /* divdi */
502 COSTS_N_INSNS (3), /* fp */
503 COSTS_N_INSNS (4), /* dmul */
504 COSTS_N_INSNS (18), /* sdiv */
505 COSTS_N_INSNS (33), /* ddiv */
512 /* Instruction costs on PPC604 processors. */
514 struct processor_costs ppc604_cost = {
515 COSTS_N_INSNS (4), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (4), /* mulsi_const9 */
518 COSTS_N_INSNS (4), /* muldi */
519 COSTS_N_INSNS (20), /* divsi */
520 COSTS_N_INSNS (20), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
531 /* Instruction costs on PPC604e processors. */
533 struct processor_costs ppc604e_cost = {
534 COSTS_N_INSNS (2), /* mulsi */
535 COSTS_N_INSNS (2), /* mulsi_const */
536 COSTS_N_INSNS (2), /* mulsi_const9 */
537 COSTS_N_INSNS (2), /* muldi */
538 COSTS_N_INSNS (20), /* divsi */
539 COSTS_N_INSNS (20), /* divdi */
540 COSTS_N_INSNS (3), /* fp */
541 COSTS_N_INSNS (3), /* dmul */
542 COSTS_N_INSNS (18), /* sdiv */
543 COSTS_N_INSNS (32), /* ddiv */
550 /* Instruction costs on PPC620 processors. */
552 struct processor_costs ppc620_cost = {
553 COSTS_N_INSNS (5), /* mulsi */
554 COSTS_N_INSNS (4), /* mulsi_const */
555 COSTS_N_INSNS (3), /* mulsi_const9 */
556 COSTS_N_INSNS (7), /* muldi */
557 COSTS_N_INSNS (21), /* divsi */
558 COSTS_N_INSNS (37), /* divdi */
559 COSTS_N_INSNS (3), /* fp */
560 COSTS_N_INSNS (3), /* dmul */
561 COSTS_N_INSNS (18), /* sdiv */
562 COSTS_N_INSNS (32), /* ddiv */
569 /* Instruction costs on PPC630 processors. */
571 struct processor_costs ppc630_cost = {
572 COSTS_N_INSNS (5), /* mulsi */
573 COSTS_N_INSNS (4), /* mulsi_const */
574 COSTS_N_INSNS (3), /* mulsi_const9 */
575 COSTS_N_INSNS (7), /* muldi */
576 COSTS_N_INSNS (21), /* divsi */
577 COSTS_N_INSNS (37), /* divdi */
578 COSTS_N_INSNS (3), /* fp */
579 COSTS_N_INSNS (3), /* dmul */
580 COSTS_N_INSNS (17), /* sdiv */
581 COSTS_N_INSNS (21), /* ddiv */
588 /* Instruction costs on Cell processor. */
589 /* COSTS_N_INSNS (1) ~ one add. */
591 struct processor_costs ppccell_cost = {
592 COSTS_N_INSNS (9/2)+2, /* mulsi */
593 COSTS_N_INSNS (6/2), /* mulsi_const */
594 COSTS_N_INSNS (6/2), /* mulsi_const9 */
595 COSTS_N_INSNS (15/2)+2, /* muldi */
596 COSTS_N_INSNS (38/2), /* divsi */
597 COSTS_N_INSNS (70/2), /* divdi */
598 COSTS_N_INSNS (10/2), /* fp */
599 COSTS_N_INSNS (10/2), /* dmul */
600 COSTS_N_INSNS (74/2), /* sdiv */
601 COSTS_N_INSNS (74/2), /* ddiv */
608 /* Instruction costs on PPC750 and PPC7400 processors. */
610 struct processor_costs ppc750_cost = {
611 COSTS_N_INSNS (5), /* mulsi */
612 COSTS_N_INSNS (3), /* mulsi_const */
613 COSTS_N_INSNS (2), /* mulsi_const9 */
614 COSTS_N_INSNS (5), /* muldi */
615 COSTS_N_INSNS (17), /* divsi */
616 COSTS_N_INSNS (17), /* divdi */
617 COSTS_N_INSNS (3), /* fp */
618 COSTS_N_INSNS (3), /* dmul */
619 COSTS_N_INSNS (17), /* sdiv */
620 COSTS_N_INSNS (31), /* ddiv */
627 /* Instruction costs on PPC7450 processors. */
629 struct processor_costs ppc7450_cost = {
630 COSTS_N_INSNS (4), /* mulsi */
631 COSTS_N_INSNS (3), /* mulsi_const */
632 COSTS_N_INSNS (3), /* mulsi_const9 */
633 COSTS_N_INSNS (4), /* muldi */
634 COSTS_N_INSNS (23), /* divsi */
635 COSTS_N_INSNS (23), /* divdi */
636 COSTS_N_INSNS (5), /* fp */
637 COSTS_N_INSNS (5), /* dmul */
638 COSTS_N_INSNS (21), /* sdiv */
639 COSTS_N_INSNS (35), /* ddiv */
646 /* Instruction costs on PPC8540 processors. */
648 struct processor_costs ppc8540_cost = {
649 COSTS_N_INSNS (4), /* mulsi */
650 COSTS_N_INSNS (4), /* mulsi_const */
651 COSTS_N_INSNS (4), /* mulsi_const9 */
652 COSTS_N_INSNS (4), /* muldi */
653 COSTS_N_INSNS (19), /* divsi */
654 COSTS_N_INSNS (19), /* divdi */
655 COSTS_N_INSNS (4), /* fp */
656 COSTS_N_INSNS (4), /* dmul */
657 COSTS_N_INSNS (29), /* sdiv */
658 COSTS_N_INSNS (29), /* ddiv */
662 1, /* prefetch streams /*/
665 /* Instruction costs on POWER4 and POWER5 processors. */
667 struct processor_costs power4_cost = {
668 COSTS_N_INSNS (3), /* mulsi */
669 COSTS_N_INSNS (2), /* mulsi_const */
670 COSTS_N_INSNS (2), /* mulsi_const9 */
671 COSTS_N_INSNS (4), /* muldi */
672 COSTS_N_INSNS (18), /* divsi */
673 COSTS_N_INSNS (34), /* divdi */
674 COSTS_N_INSNS (3), /* fp */
675 COSTS_N_INSNS (3), /* dmul */
676 COSTS_N_INSNS (17), /* sdiv */
677 COSTS_N_INSNS (17), /* ddiv */
681 8, /* prefetch streams /*/
684 /* Instruction costs on POWER6 processors. */
686 struct processor_costs power6_cost = {
687 COSTS_N_INSNS (8), /* mulsi */
688 COSTS_N_INSNS (8), /* mulsi_const */
689 COSTS_N_INSNS (8), /* mulsi_const9 */
690 COSTS_N_INSNS (8), /* muldi */
691 COSTS_N_INSNS (22), /* divsi */
692 COSTS_N_INSNS (28), /* divdi */
693 COSTS_N_INSNS (3), /* fp */
694 COSTS_N_INSNS (3), /* dmul */
695 COSTS_N_INSNS (13), /* sdiv */
696 COSTS_N_INSNS (16), /* ddiv */
700 16, /* prefetch streams */
704 static bool rs6000_function_ok_for_sibcall (tree, tree);
705 static const char *rs6000_invalid_within_doloop (const_rtx);
706 static rtx rs6000_generate_compare (enum rtx_code);
707 static void rs6000_emit_stack_tie (void);
708 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
709 static rtx spe_synthesize_frame_save (rtx);
710 static bool spe_func_has_64bit_regs_p (void);
711 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
713 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
714 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
715 static unsigned rs6000_hash_constant (rtx);
716 static unsigned toc_hash_function (const void *);
717 static int toc_hash_eq (const void *, const void *);
718 static int constant_pool_expr_1 (rtx, int *, int *);
719 static bool constant_pool_expr_p (rtx);
720 static bool legitimate_small_data_p (enum machine_mode, rtx);
721 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
722 static struct machine_function * rs6000_init_machine_status (void);
723 static bool rs6000_assemble_integer (rtx, unsigned int, int);
724 static bool no_global_regs_above (int);
725 #ifdef HAVE_GAS_HIDDEN
726 static void rs6000_assemble_visibility (tree, int);
728 static int rs6000_ra_ever_killed (void);
729 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
730 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
731 static bool rs6000_ms_bitfield_layout_p (const_tree);
732 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
733 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
734 static const char *rs6000_mangle_type (const_tree);
735 extern const struct attribute_spec rs6000_attribute_table[];
736 static void rs6000_set_default_type_attributes (tree);
737 static bool rs6000_reg_live_or_pic_offset_p (int);
738 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
739 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
740 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
742 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
743 static bool rs6000_return_in_memory (const_tree, const_tree);
744 static void rs6000_file_start (void);
746 static int rs6000_elf_reloc_rw_mask (void);
747 static void rs6000_elf_asm_out_constructor (rtx, int);
748 static void rs6000_elf_asm_out_destructor (rtx, int);
749 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
750 static void rs6000_elf_asm_init_sections (void);
751 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
752 unsigned HOST_WIDE_INT);
753 static void rs6000_elf_encode_section_info (tree, rtx, int)
756 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx);
758 static void rs6000_xcoff_asm_output_anchor (rtx);
759 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
760 static void rs6000_xcoff_asm_init_sections (void);
761 static int rs6000_xcoff_reloc_rw_mask (void);
762 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
763 static section *rs6000_xcoff_select_section (tree, int,
764 unsigned HOST_WIDE_INT);
765 static void rs6000_xcoff_unique_section (tree, int);
766 static section *rs6000_xcoff_select_rtx_section
767 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
768 static const char * rs6000_xcoff_strip_name_encoding (const char *);
769 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
770 static void rs6000_xcoff_file_start (void);
771 static void rs6000_xcoff_file_end (void);
773 static int rs6000_variable_issue (FILE *, int, rtx, int);
774 static bool rs6000_rtx_costs (rtx, int, int, int *);
775 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
776 static void rs6000_sched_init (FILE *, int, int);
777 static bool is_microcoded_insn (rtx);
778 static bool is_nonpipeline_insn (rtx);
779 static bool is_cracked_insn (rtx);
780 static bool is_branch_slot_insn (rtx);
781 static bool is_load_insn (rtx);
782 static rtx get_store_dest (rtx pat);
783 static bool is_store_insn (rtx);
784 static bool set_to_load_agen (rtx,rtx);
785 static bool adjacent_mem_locations (rtx,rtx);
786 static int rs6000_adjust_priority (rtx, int);
787 static int rs6000_issue_rate (void);
788 static bool rs6000_is_costly_dependence (dep_t, int, int);
789 static rtx get_next_active_insn (rtx, rtx);
790 static bool insn_terminates_group_p (rtx , enum group_termination);
791 static bool insn_must_be_first_in_group (rtx);
792 static bool insn_must_be_last_in_group (rtx);
793 static bool is_costly_group (rtx *, rtx);
794 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
795 static int redefine_groups (FILE *, int, rtx, rtx);
796 static int pad_groups (FILE *, int, rtx, rtx);
797 static void rs6000_sched_finish (FILE *, int);
798 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
799 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
800 static int rs6000_use_sched_lookahead (void);
801 static int rs6000_use_sched_lookahead_guard (rtx);
802 static tree rs6000_builtin_mask_for_load (void);
803 static tree rs6000_builtin_mul_widen_even (tree);
804 static tree rs6000_builtin_mul_widen_odd (tree);
805 static tree rs6000_builtin_conversion (enum tree_code, tree);
807 static void def_builtin (int, const char *, tree, int);
808 static bool rs6000_vector_alignment_reachable (const_tree, bool);
809 static void rs6000_init_builtins (void);
810 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
811 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
812 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
813 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
814 static void altivec_init_builtins (void);
815 static void rs6000_common_init_builtins (void);
816 static void rs6000_init_libfuncs (void);
818 static void paired_init_builtins (void);
819 static rtx paired_expand_builtin (tree, rtx, bool *);
820 static rtx paired_expand_lv_builtin (enum insn_code, tree, rtx);
821 static rtx paired_expand_stv_builtin (enum insn_code, tree);
822 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
824 static void enable_mask_for_builtins (struct builtin_description *, int,
825 enum rs6000_builtins,
826 enum rs6000_builtins);
827 static tree build_opaque_vector_type (tree, int);
828 static void spe_init_builtins (void);
829 static rtx spe_expand_builtin (tree, rtx, bool *);
830 static rtx spe_expand_stv_builtin (enum insn_code, tree);
831 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
832 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
833 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
834 static rs6000_stack_t *rs6000_stack_info (void);
835 static void debug_stack_info (rs6000_stack_t *);
837 static rtx altivec_expand_builtin (tree, rtx, bool *);
838 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
839 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
840 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
841 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
842 static rtx altivec_expand_predicate_builtin (enum insn_code,
843 const char *, tree, rtx);
844 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
845 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
846 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
847 static rtx altivec_expand_vec_set_builtin (tree);
848 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
849 static int get_element_number (tree, tree);
850 static bool rs6000_handle_option (size_t, const char *, int);
851 static void rs6000_parse_tls_size_option (void);
852 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
853 static int first_altivec_reg_to_save (void);
854 static unsigned int compute_vrsave_mask (void);
855 static void compute_save_world_info (rs6000_stack_t *info_ptr);
856 static void is_altivec_return_reg (rtx, void *);
857 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
858 int easy_vector_constant (rtx, enum machine_mode);
859 static bool rs6000_is_opaque_type (const_tree);
860 static rtx rs6000_dwarf_register_span (rtx);
861 static void rs6000_init_dwarf_reg_sizes_extra (tree);
862 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
863 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
864 static rtx rs6000_tls_get_addr (void);
865 static rtx rs6000_got_sym (void);
866 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
867 static const char *rs6000_get_some_local_dynamic_name (void);
868 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
869 static rtx rs6000_complex_function_value (enum machine_mode);
870 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
871 enum machine_mode, tree);
872 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
874 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
875 tree, HOST_WIDE_INT);
876 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
879 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
880 const_tree, HOST_WIDE_INT,
882 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree, int, bool);
883 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
884 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
885 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
886 enum machine_mode, tree,
888 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
890 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
892 static const char *invalid_arg_for_unprototyped_fn (const_tree, const_tree, const_tree);
894 static void macho_branch_islands (void);
895 static int no_previous_def (tree function_name);
896 static tree get_prev_label (tree function_name);
897 static void rs6000_darwin_file_start (void);
900 static tree rs6000_build_builtin_va_list (void);
901 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
902 static bool rs6000_must_pass_in_stack (enum machine_mode, const_tree);
903 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
904 static bool rs6000_vector_mode_supported_p (enum machine_mode);
905 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
907 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
909 static int get_vsel_insn (enum machine_mode);
910 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
911 static tree rs6000_stack_protect_fail (void);
913 const int INSN_NOT_AVAILABLE = -1;
914 static enum machine_mode rs6000_eh_return_filter_mode (void);
916 /* Hash table stuff for keeping track of TOC entries. */
918 struct toc_hash_struct GTY(())
920 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
921 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
923 enum machine_mode key_mode;
927 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
929 /* Default register names. */
930 char rs6000_reg_names[][8] =
932 "0", "1", "2", "3", "4", "5", "6", "7",
933 "8", "9", "10", "11", "12", "13", "14", "15",
934 "16", "17", "18", "19", "20", "21", "22", "23",
935 "24", "25", "26", "27", "28", "29", "30", "31",
936 "0", "1", "2", "3", "4", "5", "6", "7",
937 "8", "9", "10", "11", "12", "13", "14", "15",
938 "16", "17", "18", "19", "20", "21", "22", "23",
939 "24", "25", "26", "27", "28", "29", "30", "31",
940 "mq", "lr", "ctr","ap",
941 "0", "1", "2", "3", "4", "5", "6", "7",
943 /* AltiVec registers. */
944 "0", "1", "2", "3", "4", "5", "6", "7",
945 "8", "9", "10", "11", "12", "13", "14", "15",
946 "16", "17", "18", "19", "20", "21", "22", "23",
947 "24", "25", "26", "27", "28", "29", "30", "31",
950 "spe_acc", "spefscr",
951 /* Soft frame pointer. */
955 #ifdef TARGET_REGNAMES
956 static const char alt_reg_names[][8] =
958 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
959 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
960 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
961 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
962 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
963 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
964 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
965 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
966 "mq", "lr", "ctr", "ap",
967 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
969 /* AltiVec registers. */
970 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
971 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
972 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
973 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
976 "spe_acc", "spefscr",
977 /* Soft frame pointer. */
982 #ifndef MASK_STRICT_ALIGN
983 #define MASK_STRICT_ALIGN 0
985 #ifndef TARGET_PROFILE_KERNEL
986 #define TARGET_PROFILE_KERNEL 0
989 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
990 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
992 /* Initialize the GCC target structure. */
993 #undef TARGET_ATTRIBUTE_TABLE
994 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
995 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
996 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
998 #undef TARGET_ASM_ALIGNED_DI_OP
999 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1001 /* Default unaligned ops are only provided for ELF. Find the ops needed
1002 for non-ELF systems. */
1003 #ifndef OBJECT_FORMAT_ELF
1005 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1007 #undef TARGET_ASM_UNALIGNED_HI_OP
1008 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1009 #undef TARGET_ASM_UNALIGNED_SI_OP
1010 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1011 #undef TARGET_ASM_UNALIGNED_DI_OP
1012 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1015 #undef TARGET_ASM_UNALIGNED_HI_OP
1016 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1017 #undef TARGET_ASM_UNALIGNED_SI_OP
1018 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1019 #undef TARGET_ASM_UNALIGNED_DI_OP
1020 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1021 #undef TARGET_ASM_ALIGNED_DI_OP
1022 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1026 /* This hook deals with fixups for relocatable code and DI-mode objects
1028 #undef TARGET_ASM_INTEGER
1029 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1031 #ifdef HAVE_GAS_HIDDEN
1032 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1033 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1036 #undef TARGET_HAVE_TLS
1037 #define TARGET_HAVE_TLS HAVE_AS_TLS
1039 #undef TARGET_CANNOT_FORCE_CONST_MEM
1040 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1042 #undef TARGET_ASM_FUNCTION_PROLOGUE
1043 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1044 #undef TARGET_ASM_FUNCTION_EPILOGUE
1045 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1047 #undef TARGET_SCHED_VARIABLE_ISSUE
1048 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1050 #undef TARGET_SCHED_ISSUE_RATE
1051 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1052 #undef TARGET_SCHED_ADJUST_COST
1053 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1054 #undef TARGET_SCHED_ADJUST_PRIORITY
1055 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1056 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1057 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1058 #undef TARGET_SCHED_INIT
1059 #define TARGET_SCHED_INIT rs6000_sched_init
1060 #undef TARGET_SCHED_FINISH
1061 #define TARGET_SCHED_FINISH rs6000_sched_finish
1062 #undef TARGET_SCHED_REORDER
1063 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1064 #undef TARGET_SCHED_REORDER2
1065 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1067 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1068 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1070 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1071 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1073 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1074 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1075 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1076 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1077 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1078 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1079 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1080 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1082 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1083 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1085 #undef TARGET_INIT_BUILTINS
1086 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1088 #undef TARGET_EXPAND_BUILTIN
1089 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1091 #undef TARGET_MANGLE_TYPE
1092 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1094 #undef TARGET_INIT_LIBFUNCS
1095 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1098 #undef TARGET_BINDS_LOCAL_P
1099 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1102 #undef TARGET_MS_BITFIELD_LAYOUT_P
1103 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1105 #undef TARGET_ASM_OUTPUT_MI_THUNK
1106 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1108 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1109 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1111 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1112 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1114 #undef TARGET_INVALID_WITHIN_DOLOOP
1115 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1117 #undef TARGET_RTX_COSTS
1118 #define TARGET_RTX_COSTS rs6000_rtx_costs
1119 #undef TARGET_ADDRESS_COST
1120 #define TARGET_ADDRESS_COST hook_int_rtx_0
1122 #undef TARGET_VECTOR_OPAQUE_P
1123 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1125 #undef TARGET_DWARF_REGISTER_SPAN
1126 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1128 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1129 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1131 /* On rs6000, function arguments are promoted, as are function return
1133 #undef TARGET_PROMOTE_FUNCTION_ARGS
1134 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1135 #undef TARGET_PROMOTE_FUNCTION_RETURN
1136 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1138 #undef TARGET_RETURN_IN_MEMORY
1139 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1141 #undef TARGET_SETUP_INCOMING_VARARGS
1142 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1144 /* Always strict argument naming on rs6000. */
1145 #undef TARGET_STRICT_ARGUMENT_NAMING
1146 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1147 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1148 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1149 #undef TARGET_SPLIT_COMPLEX_ARG
1150 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1151 #undef TARGET_MUST_PASS_IN_STACK
1152 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1153 #undef TARGET_PASS_BY_REFERENCE
1154 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1155 #undef TARGET_ARG_PARTIAL_BYTES
1156 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1158 #undef TARGET_BUILD_BUILTIN_VA_LIST
1159 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1161 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1162 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1164 #undef TARGET_EH_RETURN_FILTER_MODE
1165 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1167 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1168 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1170 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1171 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1173 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1174 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1176 #undef TARGET_HANDLE_OPTION
1177 #define TARGET_HANDLE_OPTION rs6000_handle_option
1179 #undef TARGET_DEFAULT_TARGET_FLAGS
1180 #define TARGET_DEFAULT_TARGET_FLAGS \
1183 #undef TARGET_STACK_PROTECT_FAIL
1184 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1186 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1187 The PowerPC architecture requires only weak consistency among
1188 processors--that is, memory accesses between processors need not be
1189 sequentially consistent and memory accesses among processors can occur
1190 in any order. The ability to order memory accesses weakly provides
1191 opportunities for more efficient use of the system bus. Unless a
1192 dependency exists, the 604e allows read operations to precede store
1194 #undef TARGET_RELAXED_ORDERING
1195 #define TARGET_RELAXED_ORDERING true
1198 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1199 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1202 /* Use a 32-bit anchor range. This leads to sequences like:
1204 addis tmp,anchor,high
1207 where tmp itself acts as an anchor, and can be shared between
1208 accesses to the same 64k page. */
1209 #undef TARGET_MIN_ANCHOR_OFFSET
1210 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1211 #undef TARGET_MAX_ANCHOR_OFFSET
1212 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1213 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1214 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1216 struct gcc_target targetm = TARGET_INITIALIZER;
1219 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1222 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1224 /* The GPRs can hold any mode, but values bigger than one register
1225 cannot go past R31. */
1226 if (INT_REGNO_P (regno))
1227 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1229 /* The float registers can only hold floating modes and DImode.
1230 This excludes the 32-bit decimal float mode for now. */
1231 if (FP_REGNO_P (regno))
1233 ((SCALAR_FLOAT_MODE_P (mode)
1234 && (mode != TDmode || (regno % 2) == 0)
1236 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1237 || (GET_MODE_CLASS (mode) == MODE_INT
1238 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1239 || (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1240 && PAIRED_VECTOR_MODE (mode)));
1242 /* The CR register can only hold CC modes. */
1243 if (CR_REGNO_P (regno))
1244 return GET_MODE_CLASS (mode) == MODE_CC;
1246 if (XER_REGNO_P (regno))
1247 return mode == PSImode;
1249 /* AltiVec only in AldyVec registers. */
1250 if (ALTIVEC_REGNO_P (regno))
1251 return ALTIVEC_VECTOR_MODE (mode);
1253 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1254 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1257 /* We cannot put TImode anywhere except general register and it must be
1258 able to fit within the register set. */
1260 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1263 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1265 rs6000_init_hard_regno_mode_ok (void)
1269 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1270 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1271 if (rs6000_hard_regno_mode_ok (r, m))
1272 rs6000_hard_regno_mode_ok_p[m][r] = true;
1276 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1279 darwin_rs6000_override_options (void)
1281 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1283 rs6000_altivec_abi = 1;
1284 TARGET_ALTIVEC_VRSAVE = 1;
1285 if (DEFAULT_ABI == ABI_DARWIN)
1287 if (MACHO_DYNAMIC_NO_PIC_P)
1290 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1293 else if (flag_pic == 1)
1298 if (TARGET_64BIT && ! TARGET_POWERPC64)
1300 target_flags |= MASK_POWERPC64;
1301 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1305 rs6000_default_long_calls = 1;
1306 target_flags |= MASK_SOFT_FLOAT;
1309 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1311 if (!flag_mkernel && !flag_apple_kext
1313 && ! (target_flags_explicit & MASK_ALTIVEC))
1314 target_flags |= MASK_ALTIVEC;
1316 /* Unless the user (not the configurer) has explicitly overridden
1317 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1318 G4 unless targetting the kernel. */
1321 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1322 && ! (target_flags_explicit & MASK_ALTIVEC)
1323 && ! rs6000_select[1].string)
1325 target_flags |= MASK_ALTIVEC;
1330 /* If not otherwise specified by a target, make 'long double' equivalent to
1333 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1334 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1337 /* Override command line options. Mostly we process the processor
1338 type and sometimes adjust other TARGET_ options. */
1341 rs6000_override_options (const char *default_cpu)
1344 struct rs6000_cpu_select *ptr;
1347 /* Simplifications for entries below. */
1350 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1351 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1354 /* This table occasionally claims that a processor does not support
1355 a particular feature even though it does, but the feature is slower
1356 than the alternative. Thus, it shouldn't be relied on as a
1357 complete description of the processor's support.
1359 Please keep this list in order, and don't forget to update the
1360 documentation in invoke.texi when adding a new processor or
1364 const char *const name; /* Canonical processor name. */
1365 const enum processor_type processor; /* Processor type enum value. */
1366 const int target_enable; /* Target flags to enable. */
1367 } const processor_target_table[]
1368 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1369 {"403", PROCESSOR_PPC403,
1370 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1371 {"405", PROCESSOR_PPC405,
1372 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1373 {"405fp", PROCESSOR_PPC405,
1374 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1375 {"440", PROCESSOR_PPC440,
1376 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1377 {"440fp", PROCESSOR_PPC440,
1378 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1379 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1380 {"601", PROCESSOR_PPC601,
1381 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1382 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1383 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1384 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1385 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1386 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1387 {"620", PROCESSOR_PPC620,
1388 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1389 {"630", PROCESSOR_PPC630,
1390 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1391 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1392 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1393 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1394 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1395 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1396 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1397 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1398 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1399 /* 8548 has a dummy entry for now. */
1400 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1401 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1402 {"970", PROCESSOR_POWER4,
1403 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1404 {"cell", PROCESSOR_CELL,
1405 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1406 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1407 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1408 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1409 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1410 {"G5", PROCESSOR_POWER4,
1411 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1412 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1413 {"power2", PROCESSOR_POWER,
1414 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1415 {"power3", PROCESSOR_PPC630,
1416 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1417 {"power4", PROCESSOR_POWER4,
1418 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1419 {"power5", PROCESSOR_POWER5,
1420 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1421 | MASK_MFCRF | MASK_POPCNTB},
1422 {"power5+", PROCESSOR_POWER5,
1423 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1424 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1425 {"power6", PROCESSOR_POWER6,
1426 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1427 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1428 {"power6x", PROCESSOR_POWER6,
1429 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1430 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1431 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1432 {"powerpc64", PROCESSOR_POWERPC64,
1433 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1434 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1435 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1436 {"rios2", PROCESSOR_RIOS2,
1437 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1438 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1439 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1440 {"rs64", PROCESSOR_RS64A,
1441 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1444 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1446 /* Some OSs don't support saving the high part of 64-bit registers on
1447 context switch. Other OSs don't support saving Altivec registers.
1448 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1449 settings; if the user wants either, the user must explicitly specify
1450 them and we won't interfere with the user's specification. */
1453 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1454 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1455 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1456 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1457 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1460 rs6000_init_hard_regno_mode_ok ();
1462 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1463 #ifdef OS_MISSING_POWERPC64
1464 if (OS_MISSING_POWERPC64)
1465 set_masks &= ~MASK_POWERPC64;
1467 #ifdef OS_MISSING_ALTIVEC
1468 if (OS_MISSING_ALTIVEC)
1469 set_masks &= ~MASK_ALTIVEC;
1472 /* Don't override by the processor default if given explicitly. */
1473 set_masks &= ~target_flags_explicit;
1475 /* Identify the processor type. */
1476 rs6000_select[0].string = default_cpu;
1477 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1479 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1481 ptr = &rs6000_select[i];
1482 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1484 for (j = 0; j < ptt_size; j++)
1485 if (! strcmp (ptr->string, processor_target_table[j].name))
1487 if (ptr->set_tune_p)
1488 rs6000_cpu = processor_target_table[j].processor;
1490 if (ptr->set_arch_p)
1492 target_flags &= ~set_masks;
1493 target_flags |= (processor_target_table[j].target_enable
1500 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1507 /* If we are optimizing big endian systems for space, use the load/store
1508 multiple and string instructions. */
1509 if (BYTES_BIG_ENDIAN && optimize_size)
1510 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1512 /* Don't allow -mmultiple or -mstring on little endian systems
1513 unless the cpu is a 750, because the hardware doesn't support the
1514 instructions used in little endian mode, and causes an alignment
1515 trap. The 750 does not cause an alignment trap (except when the
1516 target is unaligned). */
1518 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1520 if (TARGET_MULTIPLE)
1522 target_flags &= ~MASK_MULTIPLE;
1523 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1524 warning (0, "-mmultiple is not supported on little endian systems");
1529 target_flags &= ~MASK_STRING;
1530 if ((target_flags_explicit & MASK_STRING) != 0)
1531 warning (0, "-mstring is not supported on little endian systems");
1535 /* Set debug flags */
1536 if (rs6000_debug_name)
1538 if (! strcmp (rs6000_debug_name, "all"))
1539 rs6000_debug_stack = rs6000_debug_arg = 1;
1540 else if (! strcmp (rs6000_debug_name, "stack"))
1541 rs6000_debug_stack = 1;
1542 else if (! strcmp (rs6000_debug_name, "arg"))
1543 rs6000_debug_arg = 1;
1545 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1548 if (rs6000_traceback_name)
1550 if (! strncmp (rs6000_traceback_name, "full", 4))
1551 rs6000_traceback = traceback_full;
1552 else if (! strncmp (rs6000_traceback_name, "part", 4))
1553 rs6000_traceback = traceback_part;
1554 else if (! strncmp (rs6000_traceback_name, "no", 2))
1555 rs6000_traceback = traceback_none;
1557 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1558 rs6000_traceback_name);
1561 if (!rs6000_explicit_options.long_double)
1562 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1564 #ifndef POWERPC_LINUX
1565 if (!rs6000_explicit_options.ieee)
1566 rs6000_ieeequad = 1;
1569 /* Set Altivec ABI as default for powerpc64 linux. */
1570 if (TARGET_ELF && TARGET_64BIT)
1572 rs6000_altivec_abi = 1;
1573 TARGET_ALTIVEC_VRSAVE = 1;
1576 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1577 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1579 rs6000_darwin64_abi = 1;
1581 darwin_one_byte_bool = 1;
1583 /* Default to natural alignment, for better performance. */
1584 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1587 /* Place FP constants in the constant pool instead of TOC
1588 if section anchors enabled. */
1589 if (flag_section_anchors)
1590 TARGET_NO_FP_IN_TOC = 1;
1592 /* Handle -mtls-size option. */
1593 rs6000_parse_tls_size_option ();
1595 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1596 SUBTARGET_OVERRIDE_OPTIONS;
1598 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1599 SUBSUBTARGET_OVERRIDE_OPTIONS;
1601 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1602 SUB3TARGET_OVERRIDE_OPTIONS;
1607 /* The e500 does not have string instructions, and we set
1608 MASK_STRING above when optimizing for size. */
1609 if ((target_flags & MASK_STRING) != 0)
1610 target_flags = target_flags & ~MASK_STRING;
1612 else if (rs6000_select[1].string != NULL)
1614 /* For the powerpc-eabispe configuration, we set all these by
1615 default, so let's unset them if we manually set another
1616 CPU that is not the E500. */
1617 if (!rs6000_explicit_options.abi)
1619 if (!rs6000_explicit_options.spe)
1621 if (!rs6000_explicit_options.float_gprs)
1622 rs6000_float_gprs = 0;
1623 if (!rs6000_explicit_options.isel)
1627 /* Detect invalid option combinations with E500. */
1630 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1631 && rs6000_cpu != PROCESSOR_POWER5
1632 && rs6000_cpu != PROCESSOR_POWER6
1633 && rs6000_cpu != PROCESSOR_CELL);
1634 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1635 || rs6000_cpu == PROCESSOR_POWER5);
1636 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1637 || rs6000_cpu == PROCESSOR_POWER5
1638 || rs6000_cpu == PROCESSOR_POWER6);
1640 rs6000_sched_restricted_insns_priority
1641 = (rs6000_sched_groups ? 1 : 0);
1643 /* Handle -msched-costly-dep option. */
1644 rs6000_sched_costly_dep
1645 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1647 if (rs6000_sched_costly_dep_str)
1649 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1650 rs6000_sched_costly_dep = no_dep_costly;
1651 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1652 rs6000_sched_costly_dep = all_deps_costly;
1653 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1654 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1655 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1656 rs6000_sched_costly_dep = store_to_load_dep_costly;
1658 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1661 /* Handle -minsert-sched-nops option. */
1662 rs6000_sched_insert_nops
1663 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1665 if (rs6000_sched_insert_nops_str)
1667 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1668 rs6000_sched_insert_nops = sched_finish_none;
1669 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1670 rs6000_sched_insert_nops = sched_finish_pad_groups;
1671 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1672 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1674 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1677 #ifdef TARGET_REGNAMES
1678 /* If the user desires alternate register names, copy in the
1679 alternate names now. */
1680 if (TARGET_REGNAMES)
1681 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1684 /* Set aix_struct_return last, after the ABI is determined.
1685 If -maix-struct-return or -msvr4-struct-return was explicitly
1686 used, don't override with the ABI default. */
1687 if (!rs6000_explicit_options.aix_struct_ret)
1688 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1690 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1691 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1694 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1696 /* We can only guarantee the availability of DI pseudo-ops when
1697 assembling for 64-bit targets. */
1700 targetm.asm_out.aligned_op.di = NULL;
1701 targetm.asm_out.unaligned_op.di = NULL;
1704 /* Set branch target alignment, if not optimizing for size. */
1707 /* Cell wants to be aligned 8byte for dual issue. */
1708 if (rs6000_cpu == PROCESSOR_CELL)
1710 if (align_functions <= 0)
1711 align_functions = 8;
1712 if (align_jumps <= 0)
1714 if (align_loops <= 0)
1717 if (rs6000_align_branch_targets)
1719 if (align_functions <= 0)
1720 align_functions = 16;
1721 if (align_jumps <= 0)
1723 if (align_loops <= 0)
1726 if (align_jumps_max_skip <= 0)
1727 align_jumps_max_skip = 15;
1728 if (align_loops_max_skip <= 0)
1729 align_loops_max_skip = 15;
1732 /* Arrange to save and restore machine status around nested functions. */
1733 init_machine_status = rs6000_init_machine_status;
1735 /* We should always be splitting complex arguments, but we can't break
1736 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1737 if (DEFAULT_ABI != ABI_AIX)
1738 targetm.calls.split_complex_arg = NULL;
1740 /* Initialize rs6000_cost with the appropriate target costs. */
1742 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1746 case PROCESSOR_RIOS1:
1747 rs6000_cost = &rios1_cost;
1750 case PROCESSOR_RIOS2:
1751 rs6000_cost = &rios2_cost;
1754 case PROCESSOR_RS64A:
1755 rs6000_cost = &rs64a_cost;
1758 case PROCESSOR_MPCCORE:
1759 rs6000_cost = &mpccore_cost;
1762 case PROCESSOR_PPC403:
1763 rs6000_cost = &ppc403_cost;
1766 case PROCESSOR_PPC405:
1767 rs6000_cost = &ppc405_cost;
1770 case PROCESSOR_PPC440:
1771 rs6000_cost = &ppc440_cost;
1774 case PROCESSOR_PPC601:
1775 rs6000_cost = &ppc601_cost;
1778 case PROCESSOR_PPC603:
1779 rs6000_cost = &ppc603_cost;
1782 case PROCESSOR_PPC604:
1783 rs6000_cost = &ppc604_cost;
1786 case PROCESSOR_PPC604e:
1787 rs6000_cost = &ppc604e_cost;
1790 case PROCESSOR_PPC620:
1791 rs6000_cost = &ppc620_cost;
1794 case PROCESSOR_PPC630:
1795 rs6000_cost = &ppc630_cost;
1798 case PROCESSOR_CELL:
1799 rs6000_cost = &ppccell_cost;
1802 case PROCESSOR_PPC750:
1803 case PROCESSOR_PPC7400:
1804 rs6000_cost = &ppc750_cost;
1807 case PROCESSOR_PPC7450:
1808 rs6000_cost = &ppc7450_cost;
1811 case PROCESSOR_PPC8540:
1812 rs6000_cost = &ppc8540_cost;
1815 case PROCESSOR_POWER4:
1816 case PROCESSOR_POWER5:
1817 rs6000_cost = &power4_cost;
1820 case PROCESSOR_POWER6:
1821 rs6000_cost = &power6_cost;
1828 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1829 set_param_value ("simultaneous-prefetches",
1830 rs6000_cost->simultaneous_prefetches);
1831 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1832 set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size);
1833 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
1834 set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
1835 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1836 set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size);
1839 /* Implement targetm.vectorize.builtin_mask_for_load. */
1841 rs6000_builtin_mask_for_load (void)
1844 return altivec_builtin_mask_for_load;
1849 /* Implement targetm.vectorize.builtin_conversion. */
1851 rs6000_builtin_conversion (enum tree_code code, tree type)
1853 if (!TARGET_ALTIVEC)
1859 switch (TYPE_MODE (type))
1862 return TYPE_UNSIGNED (type) ?
1863 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1864 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1873 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1875 rs6000_builtin_mul_widen_even (tree type)
1877 if (!TARGET_ALTIVEC)
1880 switch (TYPE_MODE (type))
1883 return TYPE_UNSIGNED (type) ?
1884 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1885 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1888 return TYPE_UNSIGNED (type) ?
1889 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1890 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1896 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1898 rs6000_builtin_mul_widen_odd (tree type)
1900 if (!TARGET_ALTIVEC)
1903 switch (TYPE_MODE (type))
1906 return TYPE_UNSIGNED (type) ?
1907 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1908 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1911 return TYPE_UNSIGNED (type) ?
1912 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1913 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1920 /* Return true iff, data reference of TYPE can reach vector alignment (16)
1921 after applying N number of iterations. This routine does not determine
1922 how may iterations are required to reach desired alignment. */
1925 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
1932 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
1935 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
1945 /* Assuming that all other types are naturally aligned. CHECKME! */
1950 /* Handle generic options of the form -mfoo=yes/no.
1951 NAME is the option name.
1952 VALUE is the option value.
1953 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1954 whether the option value is 'yes' or 'no' respectively. */
1956 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1960 else if (!strcmp (value, "yes"))
1962 else if (!strcmp (value, "no"))
1965 error ("unknown -m%s= option specified: '%s'", name, value);
1968 /* Validate and record the size specified with the -mtls-size option. */
1971 rs6000_parse_tls_size_option (void)
1973 if (rs6000_tls_size_string == 0)
1975 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1976 rs6000_tls_size = 16;
1977 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1978 rs6000_tls_size = 32;
1979 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1980 rs6000_tls_size = 64;
1982 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1986 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1988 if (DEFAULT_ABI == ABI_DARWIN)
1989 /* The Darwin libraries never set errno, so we might as well
1990 avoid calling them when that's the only reason we would. */
1991 flag_errno_math = 0;
1993 /* Double growth factor to counter reduced min jump length. */
1994 set_param_value ("max-grow-copy-bb-insns", 16);
1996 /* Enable section anchors by default.
1997 Skip section anchors for Objective C and Objective C++
1998 until front-ends fixed. */
1999 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
2000 flag_section_anchors = 1;
2003 /* Implement TARGET_HANDLE_OPTION. */
2006 rs6000_handle_option (size_t code, const char *arg, int value)
2011 target_flags &= ~(MASK_POWER | MASK_POWER2
2012 | MASK_MULTIPLE | MASK_STRING);
2013 target_flags_explicit |= (MASK_POWER | MASK_POWER2
2014 | MASK_MULTIPLE | MASK_STRING);
2016 case OPT_mno_powerpc:
2017 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
2018 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2019 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
2020 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2023 target_flags &= ~MASK_MINIMAL_TOC;
2024 TARGET_NO_FP_IN_TOC = 0;
2025 TARGET_NO_SUM_IN_TOC = 0;
2026 target_flags_explicit |= MASK_MINIMAL_TOC;
2027 #ifdef TARGET_USES_SYSV4_OPT
2028 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2029 just the same as -mminimal-toc. */
2030 target_flags |= MASK_MINIMAL_TOC;
2031 target_flags_explicit |= MASK_MINIMAL_TOC;
2035 #ifdef TARGET_USES_SYSV4_OPT
2037 /* Make -mtoc behave like -mminimal-toc. */
2038 target_flags |= MASK_MINIMAL_TOC;
2039 target_flags_explicit |= MASK_MINIMAL_TOC;
2043 #ifdef TARGET_USES_AIX64_OPT
2048 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
2049 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
2050 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
2053 #ifdef TARGET_USES_AIX64_OPT
2058 target_flags &= ~MASK_POWERPC64;
2059 target_flags_explicit |= MASK_POWERPC64;
2062 case OPT_minsert_sched_nops_:
2063 rs6000_sched_insert_nops_str = arg;
2066 case OPT_mminimal_toc:
2069 TARGET_NO_FP_IN_TOC = 0;
2070 TARGET_NO_SUM_IN_TOC = 0;
2077 target_flags |= (MASK_MULTIPLE | MASK_STRING);
2078 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
2085 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2086 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2090 case OPT_mpowerpc_gpopt:
2091 case OPT_mpowerpc_gfxopt:
2094 target_flags |= MASK_POWERPC;
2095 target_flags_explicit |= MASK_POWERPC;
2099 case OPT_maix_struct_return:
2100 case OPT_msvr4_struct_return:
2101 rs6000_explicit_options.aix_struct_ret = true;
2105 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
2109 rs6000_explicit_options.isel = true;
2110 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
2114 rs6000_explicit_options.spe = true;
2115 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
2119 rs6000_debug_name = arg;
2122 #ifdef TARGET_USES_SYSV4_OPT
2124 rs6000_abi_name = arg;
2128 rs6000_sdata_name = arg;
2131 case OPT_mtls_size_:
2132 rs6000_tls_size_string = arg;
2135 case OPT_mrelocatable:
2138 target_flags |= MASK_MINIMAL_TOC;
2139 target_flags_explicit |= MASK_MINIMAL_TOC;
2140 TARGET_NO_FP_IN_TOC = 1;
2144 case OPT_mrelocatable_lib:
2147 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2148 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2149 TARGET_NO_FP_IN_TOC = 1;
2153 target_flags &= ~MASK_RELOCATABLE;
2154 target_flags_explicit |= MASK_RELOCATABLE;
2160 if (!strcmp (arg, "altivec"))
2162 rs6000_explicit_options.abi = true;
2163 rs6000_altivec_abi = 1;
2166 else if (! strcmp (arg, "no-altivec"))
2168 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2169 the default for rs6000_spe_abi to be chosen later. */
2170 rs6000_altivec_abi = 0;
2172 else if (! strcmp (arg, "spe"))
2174 rs6000_explicit_options.abi = true;
2176 rs6000_altivec_abi = 0;
2177 if (!TARGET_SPE_ABI)
2178 error ("not configured for ABI: '%s'", arg);
2180 else if (! strcmp (arg, "no-spe"))
2182 rs6000_explicit_options.abi = true;
2186 /* These are here for testing during development only, do not
2187 document in the manual please. */
2188 else if (! strcmp (arg, "d64"))
2190 rs6000_darwin64_abi = 1;
2191 warning (0, "Using darwin64 ABI");
2193 else if (! strcmp (arg, "d32"))
2195 rs6000_darwin64_abi = 0;
2196 warning (0, "Using old darwin ABI");
2199 else if (! strcmp (arg, "ibmlongdouble"))
2201 rs6000_explicit_options.ieee = true;
2202 rs6000_ieeequad = 0;
2203 warning (0, "Using IBM extended precision long double");
2205 else if (! strcmp (arg, "ieeelongdouble"))
2207 rs6000_explicit_options.ieee = true;
2208 rs6000_ieeequad = 1;
2209 warning (0, "Using IEEE extended precision long double");
2214 error ("unknown ABI specified: '%s'", arg);
2220 rs6000_select[1].string = arg;
2224 rs6000_select[2].string = arg;
2227 case OPT_mtraceback_:
2228 rs6000_traceback_name = arg;
2231 case OPT_mfloat_gprs_:
2232 rs6000_explicit_options.float_gprs = true;
2233 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2234 rs6000_float_gprs = 1;
2235 else if (! strcmp (arg, "double"))
2236 rs6000_float_gprs = 2;
2237 else if (! strcmp (arg, "no"))
2238 rs6000_float_gprs = 0;
2241 error ("invalid option for -mfloat-gprs: '%s'", arg);
2246 case OPT_mlong_double_:
2247 rs6000_explicit_options.long_double = true;
2248 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2249 if (value != 64 && value != 128)
2251 error ("Unknown switch -mlong-double-%s", arg);
2252 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2256 rs6000_long_double_type_size = value;
2259 case OPT_msched_costly_dep_:
2260 rs6000_sched_costly_dep_str = arg;
2264 rs6000_explicit_options.alignment = true;
2265 if (! strcmp (arg, "power"))
2267 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2268 some C library functions, so warn about it. The flag may be
2269 useful for performance studies from time to time though, so
2270 don't disable it entirely. */
2271 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2272 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2273 " it is incompatible with the installed C and C++ libraries");
2274 rs6000_alignment_flags = MASK_ALIGN_POWER;
2276 else if (! strcmp (arg, "natural"))
2277 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2280 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2288 /* Do anything needed at the start of the asm file. */
2291 rs6000_file_start (void)
2295 const char *start = buffer;
2296 struct rs6000_cpu_select *ptr;
2297 const char *default_cpu = TARGET_CPU_DEFAULT;
2298 FILE *file = asm_out_file;
2300 default_file_start ();
2302 #ifdef TARGET_BI_ARCH
2303 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2307 if (flag_verbose_asm)
2309 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2310 rs6000_select[0].string = default_cpu;
2312 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2314 ptr = &rs6000_select[i];
2315 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2317 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2322 if (PPC405_ERRATUM77)
2324 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2328 #ifdef USING_ELFOS_H
2329 switch (rs6000_sdata)
2331 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2332 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2333 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2334 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2337 if (rs6000_sdata && g_switch_value)
2339 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2349 #ifdef HAVE_AS_GNU_ATTRIBUTE
2350 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2352 fprintf (file, "\t.gnu_attribute 4, %d\n",
2353 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
2354 fprintf (file, "\t.gnu_attribute 8, %d\n",
2355 (TARGET_ALTIVEC_ABI ? 2
2356 : TARGET_SPE_ABI ? 3
2361 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2363 switch_to_section (toc_section);
2364 switch_to_section (text_section);
2369 /* Return nonzero if this function is known to have a null epilogue. */
2372 direct_return (void)
2374 if (reload_completed)
2376 rs6000_stack_t *info = rs6000_stack_info ();
2378 if (info->first_gp_reg_save == 32
2379 && info->first_fp_reg_save == 64
2380 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2381 && ! info->lr_save_p
2382 && ! info->cr_save_p
2383 && info->vrsave_mask == 0
2391 /* Return the number of instructions it takes to form a constant in an
2392 integer register. */
2395 num_insns_constant_wide (HOST_WIDE_INT value)
2397 /* signed constant loadable with {cal|addi} */
2398 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2401 /* constant loadable with {cau|addis} */
2402 else if ((value & 0xffff) == 0
2403 && (value >> 31 == -1 || value >> 31 == 0))
2406 #if HOST_BITS_PER_WIDE_INT == 64
2407 else if (TARGET_POWERPC64)
2409 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2410 HOST_WIDE_INT high = value >> 31;
2412 if (high == 0 || high == -1)
2418 return num_insns_constant_wide (high) + 1;
2420 return (num_insns_constant_wide (high)
2421 + num_insns_constant_wide (low) + 1);
2430 num_insns_constant (rtx op, enum machine_mode mode)
2432 HOST_WIDE_INT low, high;
2434 switch (GET_CODE (op))
2437 #if HOST_BITS_PER_WIDE_INT == 64
2438 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2439 && mask64_operand (op, mode))
2443 return num_insns_constant_wide (INTVAL (op));
2451 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2452 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2453 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2456 if (mode == VOIDmode || mode == DImode)
2458 high = CONST_DOUBLE_HIGH (op);
2459 low = CONST_DOUBLE_LOW (op);
2466 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2467 if (DECIMAL_FLOAT_MODE_P (mode))
2468 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2470 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2471 high = l[WORDS_BIG_ENDIAN == 0];
2472 low = l[WORDS_BIG_ENDIAN != 0];
2476 return (num_insns_constant_wide (low)
2477 + num_insns_constant_wide (high));
2480 if ((high == 0 && low >= 0)
2481 || (high == -1 && low < 0))
2482 return num_insns_constant_wide (low);
2484 else if (mask64_operand (op, mode))
2488 return num_insns_constant_wide (high) + 1;
2491 return (num_insns_constant_wide (high)
2492 + num_insns_constant_wide (low) + 1);
2500 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2501 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2502 corresponding element of the vector, but for V4SFmode and V2SFmode,
2503 the corresponding "float" is interpreted as an SImode integer. */
2505 static HOST_WIDE_INT
2506 const_vector_elt_as_int (rtx op, unsigned int elt)
2508 rtx tmp = CONST_VECTOR_ELT (op, elt);
2509 if (GET_MODE (op) == V4SFmode
2510 || GET_MODE (op) == V2SFmode)
2511 tmp = gen_lowpart (SImode, tmp);
2512 return INTVAL (tmp);
2515 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2516 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2517 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2518 all items are set to the same value and contain COPIES replicas of the
2519 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2520 operand and the others are set to the value of the operand's msb. */
2523 vspltis_constant (rtx op, unsigned step, unsigned copies)
2525 enum machine_mode mode = GET_MODE (op);
2526 enum machine_mode inner = GET_MODE_INNER (mode);
2529 unsigned nunits = GET_MODE_NUNITS (mode);
2530 unsigned bitsize = GET_MODE_BITSIZE (inner);
2531 unsigned mask = GET_MODE_MASK (inner);
2533 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2534 HOST_WIDE_INT splat_val = val;
2535 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2537 /* Construct the value to be splatted, if possible. If not, return 0. */
2538 for (i = 2; i <= copies; i *= 2)
2540 HOST_WIDE_INT small_val;
2542 small_val = splat_val >> bitsize;
2544 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2546 splat_val = small_val;
2549 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2550 if (EASY_VECTOR_15 (splat_val))
2553 /* Also check if we can splat, and then add the result to itself. Do so if
2554 the value is positive, of if the splat instruction is using OP's mode;
2555 for splat_val < 0, the splat and the add should use the same mode. */
2556 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2557 && (splat_val >= 0 || (step == 1 && copies == 1)))
2563 /* Check if VAL is present in every STEP-th element, and the
2564 other elements are filled with its most significant bit. */
2565 for (i = 0; i < nunits - 1; ++i)
2567 HOST_WIDE_INT desired_val;
2568 if (((i + 1) & (step - 1)) == 0)
2571 desired_val = msb_val;
2573 if (desired_val != const_vector_elt_as_int (op, i))
2581 /* Return true if OP is of the given MODE and can be synthesized
2582 with a vspltisb, vspltish or vspltisw. */
2585 easy_altivec_constant (rtx op, enum machine_mode mode)
2587 unsigned step, copies;
2589 if (mode == VOIDmode)
2590 mode = GET_MODE (op);
2591 else if (mode != GET_MODE (op))
2594 /* Start with a vspltisw. */
2595 step = GET_MODE_NUNITS (mode) / 4;
2598 if (vspltis_constant (op, step, copies))
2601 /* Then try with a vspltish. */
2607 if (vspltis_constant (op, step, copies))
2610 /* And finally a vspltisb. */
2616 if (vspltis_constant (op, step, copies))
2622 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2623 result is OP. Abort if it is not possible. */
2626 gen_easy_altivec_constant (rtx op)
2628 enum machine_mode mode = GET_MODE (op);
2629 int nunits = GET_MODE_NUNITS (mode);
2630 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2631 unsigned step = nunits / 4;
2632 unsigned copies = 1;
2634 /* Start with a vspltisw. */
2635 if (vspltis_constant (op, step, copies))
2636 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2638 /* Then try with a vspltish. */
2644 if (vspltis_constant (op, step, copies))
2645 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2647 /* And finally a vspltisb. */
2653 if (vspltis_constant (op, step, copies))
2654 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2660 output_vec_const_move (rtx *operands)
2663 enum machine_mode mode;
2668 mode = GET_MODE (dest);
2673 if (zero_constant (vec, mode))
2674 return "vxor %0,%0,%0";
2676 splat_vec = gen_easy_altivec_constant (vec);
2677 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2678 operands[1] = XEXP (splat_vec, 0);
2679 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2682 switch (GET_MODE (splat_vec))
2685 return "vspltisw %0,%1";
2688 return "vspltish %0,%1";
2691 return "vspltisb %0,%1";
2698 gcc_assert (TARGET_SPE);
2700 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2701 pattern of V1DI, V4HI, and V2SF.
2703 FIXME: We should probably return # and add post reload
2704 splitters for these, but this way is so easy ;-). */
2705 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2706 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2707 operands[1] = CONST_VECTOR_ELT (vec, 0);
2708 operands[2] = CONST_VECTOR_ELT (vec, 1);
2710 return "li %0,%1\n\tevmergelo %0,%0,%0";
2712 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2715 /* Initialize vector TARGET to VALS. */
2718 rs6000_expand_vector_init (rtx target, rtx vals)
2720 enum machine_mode mode = GET_MODE (target);
2721 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2722 int n_elts = GET_MODE_NUNITS (mode);
2723 int n_var = 0, one_var = -1;
2724 bool all_same = true, all_const_zero = true;
2728 for (i = 0; i < n_elts; ++i)
2730 x = XVECEXP (vals, 0, i);
2731 if (!CONSTANT_P (x))
2732 ++n_var, one_var = i;
2733 else if (x != CONST0_RTX (inner_mode))
2734 all_const_zero = false;
2736 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2742 if (mode != V4SFmode && all_const_zero)
2744 /* Zero register. */
2745 emit_insn (gen_rtx_SET (VOIDmode, target,
2746 gen_rtx_XOR (mode, target, target)));
2749 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2751 /* Splat immediate. */
2752 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2756 ; /* Splat vector element. */
2759 /* Load from constant pool. */
2760 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2765 /* Store value to stack temp. Load vector element. Splat. */
2768 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2769 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2770 XVECEXP (vals, 0, 0));
2771 x = gen_rtx_UNSPEC (VOIDmode,
2772 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2773 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2775 gen_rtx_SET (VOIDmode,
2778 x = gen_rtx_VEC_SELECT (inner_mode, target,
2779 gen_rtx_PARALLEL (VOIDmode,
2780 gen_rtvec (1, const0_rtx)));
2781 emit_insn (gen_rtx_SET (VOIDmode, target,
2782 gen_rtx_VEC_DUPLICATE (mode, x)));
2786 /* One field is non-constant. Load constant then overwrite
2790 rtx copy = copy_rtx (vals);
2792 /* Load constant part of vector, substitute neighboring value for
2794 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2795 rs6000_expand_vector_init (target, copy);
2797 /* Insert variable. */
2798 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2802 /* Construct the vector in memory one field at a time
2803 and load the whole vector. */
2804 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2805 for (i = 0; i < n_elts; i++)
2806 emit_move_insn (adjust_address_nv (mem, inner_mode,
2807 i * GET_MODE_SIZE (inner_mode)),
2808 XVECEXP (vals, 0, i));
2809 emit_move_insn (target, mem);
2812 /* Set field ELT of TARGET to VAL. */
2815 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2817 enum machine_mode mode = GET_MODE (target);
2818 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2819 rtx reg = gen_reg_rtx (mode);
2821 int width = GET_MODE_SIZE (inner_mode);
2824 /* Load single variable value. */
2825 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2826 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2827 x = gen_rtx_UNSPEC (VOIDmode,
2828 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2829 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2831 gen_rtx_SET (VOIDmode,
2835 /* Linear sequence. */
2836 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2837 for (i = 0; i < 16; ++i)
2838 XVECEXP (mask, 0, i) = GEN_INT (i);
2840 /* Set permute mask to insert element into target. */
2841 for (i = 0; i < width; ++i)
2842 XVECEXP (mask, 0, elt*width + i)
2843 = GEN_INT (i + 0x10);
2844 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2845 x = gen_rtx_UNSPEC (mode,
2846 gen_rtvec (3, target, reg,
2847 force_reg (V16QImode, x)),
2849 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2852 /* Extract field ELT from VEC into TARGET. */
2855 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2857 enum machine_mode mode = GET_MODE (vec);
2858 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2861 /* Allocate mode-sized buffer. */
2862 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2864 /* Add offset to field within buffer matching vector element. */
2865 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2867 /* Store single field into mode-sized buffer. */
2868 x = gen_rtx_UNSPEC (VOIDmode,
2869 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2870 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2872 gen_rtx_SET (VOIDmode,
2875 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2878 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2879 implement ANDing by the mask IN. */
2881 build_mask64_2_operands (rtx in, rtx *out)
2883 #if HOST_BITS_PER_WIDE_INT >= 64
2884 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2887 gcc_assert (GET_CODE (in) == CONST_INT);
2892 /* Assume c initially something like 0x00fff000000fffff. The idea
2893 is to rotate the word so that the middle ^^^^^^ group of zeros
2894 is at the MS end and can be cleared with an rldicl mask. We then
2895 rotate back and clear off the MS ^^ group of zeros with a
2897 c = ~c; /* c == 0xff000ffffff00000 */
2898 lsb = c & -c; /* lsb == 0x0000000000100000 */
2899 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2900 c = ~c; /* c == 0x00fff000000fffff */
2901 c &= -lsb; /* c == 0x00fff00000000000 */
2902 lsb = c & -c; /* lsb == 0x0000100000000000 */
2903 c = ~c; /* c == 0xff000fffffffffff */
2904 c &= -lsb; /* c == 0xff00000000000000 */
2906 while ((lsb >>= 1) != 0)
2907 shift++; /* shift == 44 on exit from loop */
2908 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2909 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2910 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2914 /* Assume c initially something like 0xff000f0000000000. The idea
2915 is to rotate the word so that the ^^^ middle group of zeros
2916 is at the LS end and can be cleared with an rldicr mask. We then
2917 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2919 lsb = c & -c; /* lsb == 0x0000010000000000 */
2920 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2921 c = ~c; /* c == 0x00fff0ffffffffff */
2922 c &= -lsb; /* c == 0x00fff00000000000 */
2923 lsb = c & -c; /* lsb == 0x0000100000000000 */
2924 c = ~c; /* c == 0xff000fffffffffff */
2925 c &= -lsb; /* c == 0xff00000000000000 */
2927 while ((lsb >>= 1) != 0)
2928 shift++; /* shift == 44 on exit from loop */
2929 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2930 m1 >>= shift; /* m1 == 0x0000000000000fff */
2931 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2934 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2935 masks will be all 1's. We are guaranteed more than one transition. */
2936 out[0] = GEN_INT (64 - shift);
2937 out[1] = GEN_INT (m1);
2938 out[2] = GEN_INT (shift);
2939 out[3] = GEN_INT (m2);
2947 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2950 invalid_e500_subreg (rtx op, enum machine_mode mode)
2952 if (TARGET_E500_DOUBLE)
2954 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
2955 subreg:TI and reg:TF. */
2956 if (GET_CODE (op) == SUBREG
2957 && (mode == SImode || mode == DImode || mode == TImode)
2958 && REG_P (SUBREG_REG (op))
2959 && (GET_MODE (SUBREG_REG (op)) == DFmode
2960 || GET_MODE (SUBREG_REG (op)) == TFmode))
2963 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
2965 if (GET_CODE (op) == SUBREG
2966 && (mode == DFmode || mode == TFmode)
2967 && REG_P (SUBREG_REG (op))
2968 && (GET_MODE (SUBREG_REG (op)) == DImode
2969 || GET_MODE (SUBREG_REG (op)) == TImode))
2974 && GET_CODE (op) == SUBREG
2976 && REG_P (SUBREG_REG (op))
2977 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2983 /* AIX increases natural record alignment to doubleword if the first
2984 field is an FP double while the FP fields remain word aligned. */
2987 rs6000_special_round_type_align (tree type, unsigned int computed,
2988 unsigned int specified)
2990 unsigned int align = MAX (computed, specified);
2991 tree field = TYPE_FIELDS (type);
2993 /* Skip all non field decls */
2994 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2995 field = TREE_CHAIN (field);
2997 if (field != NULL && field != type)
2999 type = TREE_TYPE (field);
3000 while (TREE_CODE (type) == ARRAY_TYPE)
3001 type = TREE_TYPE (type);
3003 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
3004 align = MAX (align, 64);
3010 /* Darwin increases record alignment to the natural alignment of
3014 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
3015 unsigned int specified)
3017 unsigned int align = MAX (computed, specified);
3019 if (TYPE_PACKED (type))
3022 /* Find the first field, looking down into aggregates. */
3024 tree field = TYPE_FIELDS (type);
3025 /* Skip all non field decls */
3026 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3027 field = TREE_CHAIN (field);
3030 type = TREE_TYPE (field);
3031 while (TREE_CODE (type) == ARRAY_TYPE)
3032 type = TREE_TYPE (type);
3033 } while (AGGREGATE_TYPE_P (type));
3035 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
3036 align = MAX (align, TYPE_ALIGN (type));
3041 /* Return 1 for an operand in small memory on V.4/eabi. */
3044 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3045 enum machine_mode mode ATTRIBUTE_UNUSED)
3050 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3053 if (DEFAULT_ABI != ABI_V4)
3056 if (GET_CODE (op) == SYMBOL_REF)
3059 else if (GET_CODE (op) != CONST
3060 || GET_CODE (XEXP (op, 0)) != PLUS
3061 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3062 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3067 rtx sum = XEXP (op, 0);
3068 HOST_WIDE_INT summand;
3070 /* We have to be careful here, because it is the referenced address
3071 that must be 32k from _SDA_BASE_, not just the symbol. */
3072 summand = INTVAL (XEXP (sum, 1));
3073 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3076 sym_ref = XEXP (sum, 0);
3079 return SYMBOL_REF_SMALL_P (sym_ref);
3085 /* Return true if either operand is a general purpose register. */
3088 gpr_or_gpr_p (rtx op0, rtx op1)
3090 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3091 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3095 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3098 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3100 switch (GET_CODE (op))
3103 if (RS6000_SYMBOL_REF_TLS_P (op))
3105 else if (CONSTANT_POOL_ADDRESS_P (op))
3107 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3115 else if (! strcmp (XSTR (op, 0), toc_label_name))
3124 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3125 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3127 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3136 constant_pool_expr_p (rtx op)
3140 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3144 toc_relative_expr_p (rtx op)
3148 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3152 legitimate_constant_pool_address_p (rtx x)
3155 && GET_CODE (x) == PLUS
3156 && GET_CODE (XEXP (x, 0)) == REG
3157 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3158 && constant_pool_expr_p (XEXP (x, 1)));
3162 legitimate_small_data_p (enum machine_mode mode, rtx x)
3164 return (DEFAULT_ABI == ABI_V4
3165 && !flag_pic && !TARGET_TOC
3166 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3167 && small_data_operand (x, mode));
3170 /* SPE offset addressing is limited to 5-bits worth of double words. */
3171 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3174 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3176 unsigned HOST_WIDE_INT offset, extra;
3178 if (GET_CODE (x) != PLUS)
3180 if (GET_CODE (XEXP (x, 0)) != REG)
3182 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3184 if (legitimate_constant_pool_address_p (x))
3186 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3189 offset = INTVAL (XEXP (x, 1));
3197 /* AltiVec vector modes. Only reg+reg addressing is valid and
3198 constant offset zero should not occur due to canonicalization.
3199 Allow any offset when not strict before reload. */
3206 /* SPE vector modes. */
3207 return SPE_CONST_OFFSET_OK (offset);
3211 if (TARGET_E500_DOUBLE)
3212 return SPE_CONST_OFFSET_OK (offset);
3215 /* On e500v2, we may have:
3217 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3219 Which gets addressed with evldd instructions. */
3220 if (TARGET_E500_DOUBLE)
3221 return SPE_CONST_OFFSET_OK (offset);
3223 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3225 else if (offset & 3)
3230 if (TARGET_E500_DOUBLE)
3231 return (SPE_CONST_OFFSET_OK (offset)
3232 && SPE_CONST_OFFSET_OK (offset + 8));
3236 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3238 else if (offset & 3)
3249 return (offset < 0x10000) && (offset + extra < 0x10000);
3253 legitimate_indexed_address_p (rtx x, int strict)
3257 if (GET_CODE (x) != PLUS)
3263 /* Recognize the rtl generated by reload which we know will later be
3264 replaced with proper base and index regs. */
3266 && reload_in_progress
3267 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3271 return (REG_P (op0) && REG_P (op1)
3272 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3273 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3274 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3275 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3279 legitimate_indirect_address_p (rtx x, int strict)
3281 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3285 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3287 if (!TARGET_MACHO || !flag_pic
3288 || mode != SImode || GET_CODE (x) != MEM)
3292 if (GET_CODE (x) != LO_SUM)
3294 if (GET_CODE (XEXP (x, 0)) != REG)
3296 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3300 return CONSTANT_P (x);
3304 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3306 if (GET_CODE (x) != LO_SUM)
3308 if (GET_CODE (XEXP (x, 0)) != REG)
3310 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3312 /* Restrict addressing for DI because of our SUBREG hackery. */
3313 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3318 if (TARGET_ELF || TARGET_MACHO)
3320 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3324 if (GET_MODE_NUNITS (mode) != 1)
3326 if (GET_MODE_BITSIZE (mode) > 64
3327 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3328 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3331 return CONSTANT_P (x);
3338 /* Try machine-dependent ways of modifying an illegitimate address
3339 to be legitimate. If we find one, return the new, valid address.
3340 This is used from only one place: `memory_address' in explow.c.
3342 OLDX is the address as it was before break_out_memory_refs was
3343 called. In some cases it is useful to look at this to decide what
3346 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3348 It is always safe for this function to do nothing. It exists to
3349 recognize opportunities to optimize the output.
3351 On RS/6000, first check for the sum of a register with a constant
3352 integer that is out of range. If so, generate code to add the
3353 constant with the low-order 16 bits masked to the register and force
3354 this result into another register (this can be done with `cau').
3355 Then generate an address of REG+(CONST&0xffff), allowing for the
3356 possibility of bit 16 being a one.
3358 Then check for the sum of a register and something not constant, try to
3359 load the other things into a register and return the sum. */
3362 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3363 enum machine_mode mode)
3365 if (GET_CODE (x) == SYMBOL_REF)
3367 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3369 return rs6000_legitimize_tls_address (x, model);
3372 if (GET_CODE (x) == PLUS
3373 && GET_CODE (XEXP (x, 0)) == REG
3374 && GET_CODE (XEXP (x, 1)) == CONST_INT
3375 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3377 HOST_WIDE_INT high_int, low_int;
3379 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3380 high_int = INTVAL (XEXP (x, 1)) - low_int;
3381 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3382 GEN_INT (high_int)), 0);
3383 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3385 else if (GET_CODE (x) == PLUS
3386 && GET_CODE (XEXP (x, 0)) == REG
3387 && GET_CODE (XEXP (x, 1)) != CONST_INT
3388 && GET_MODE_NUNITS (mode) == 1
3389 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3391 || (((mode != DImode && mode != DFmode && mode != DDmode)
3392 || TARGET_E500_DOUBLE)
3393 && mode != TFmode && mode != TDmode))
3394 && (TARGET_POWERPC64 || mode != DImode)
3397 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3398 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3400 else if (ALTIVEC_VECTOR_MODE (mode))
3404 /* Make sure both operands are registers. */
3405 if (GET_CODE (x) == PLUS)
3406 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3407 force_reg (Pmode, XEXP (x, 1)));
3409 reg = force_reg (Pmode, x);
3412 else if (SPE_VECTOR_MODE (mode)
3413 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3414 || mode == DDmode || mode == TDmode
3415 || mode == DImode)))
3419 /* We accept [reg + reg] and [reg + OFFSET]. */
3421 if (GET_CODE (x) == PLUS)
3423 rtx op1 = XEXP (x, 0);
3424 rtx op2 = XEXP (x, 1);
3426 op1 = force_reg (Pmode, op1);
3428 if (GET_CODE (op2) != REG
3429 && (GET_CODE (op2) != CONST_INT
3430 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3431 op2 = force_reg (Pmode, op2);
3433 return gen_rtx_PLUS (Pmode, op1, op2);
3436 return force_reg (Pmode, x);
3442 && GET_CODE (x) != CONST_INT
3443 && GET_CODE (x) != CONST_DOUBLE
3445 && GET_MODE_NUNITS (mode) == 1
3446 && (GET_MODE_BITSIZE (mode) <= 32
3447 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3449 rtx reg = gen_reg_rtx (Pmode);
3450 emit_insn (gen_elf_high (reg, x));
3451 return gen_rtx_LO_SUM (Pmode, reg, x);
3453 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3456 && ! MACHO_DYNAMIC_NO_PIC_P
3458 && GET_CODE (x) != CONST_INT
3459 && GET_CODE (x) != CONST_DOUBLE
3461 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3465 rtx reg = gen_reg_rtx (Pmode);
3466 emit_insn (gen_macho_high (reg, x));
3467 return gen_rtx_LO_SUM (Pmode, reg, x);
3470 && constant_pool_expr_p (x)
3471 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3473 return create_TOC_reference (x);
3479 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3480 We need to emit DTP-relative relocations. */
3483 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3488 fputs ("\t.long\t", file);
3491 fputs (DOUBLE_INT_ASM_OP, file);
3496 output_addr_const (file, x);
3497 fputs ("@dtprel+0x8000", file);
3500 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3502 static GTY(()) rtx rs6000_tls_symbol;
3504 rs6000_tls_get_addr (void)
3506 if (!rs6000_tls_symbol)
3507 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3509 return rs6000_tls_symbol;
3512 /* Construct the SYMBOL_REF for TLS GOT references. */
3514 static GTY(()) rtx rs6000_got_symbol;
3516 rs6000_got_sym (void)
3518 if (!rs6000_got_symbol)
3520 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3521 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3522 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3525 return rs6000_got_symbol;
3528 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3529 this (thread-local) address. */
3532 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3536 dest = gen_reg_rtx (Pmode);
3537 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3543 tlsreg = gen_rtx_REG (Pmode, 13);
3544 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3548 tlsreg = gen_rtx_REG (Pmode, 2);
3549 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3553 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3557 tmp = gen_reg_rtx (Pmode);
3560 tlsreg = gen_rtx_REG (Pmode, 13);
3561 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3565 tlsreg = gen_rtx_REG (Pmode, 2);
3566 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3570 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3572 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3577 rtx r3, got, tga, tmp1, tmp2, eqv;
3579 /* We currently use relocations like @got@tlsgd for tls, which
3580 means the linker will handle allocation of tls entries, placing
3581 them in the .got section. So use a pointer to the .got section,
3582 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3583 or to secondary GOT sections used by 32-bit -fPIC. */
3585 got = gen_rtx_REG (Pmode, 2);
3589 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3592 rtx gsym = rs6000_got_sym ();
3593 got = gen_reg_rtx (Pmode);
3595 rs6000_emit_move (got, gsym, Pmode);
3601 tmp1 = gen_reg_rtx (Pmode);
3602 tmp2 = gen_reg_rtx (Pmode);
3603 tmp3 = gen_reg_rtx (Pmode);
3604 mem = gen_const_mem (Pmode, tmp1);
3606 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3607 emit_move_insn (tmp1,
3608 gen_rtx_REG (Pmode, LR_REGNO));
3609 emit_move_insn (tmp2, mem);
3610 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3611 last = emit_move_insn (got, tmp3);
3612 set_unique_reg_note (last, REG_EQUAL, gsym);
3613 maybe_encapsulate_block (first, last, gsym);
3618 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3620 r3 = gen_rtx_REG (Pmode, 3);
3622 insn = gen_tls_gd_64 (r3, got, addr);
3624 insn = gen_tls_gd_32 (r3, got, addr);
3627 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3628 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3629 insn = emit_call_insn (insn);
3630 CONST_OR_PURE_CALL_P (insn) = 1;
3631 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3632 insn = get_insns ();
3634 emit_libcall_block (insn, dest, r3, addr);
3636 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3638 r3 = gen_rtx_REG (Pmode, 3);
3640 insn = gen_tls_ld_64 (r3, got);
3642 insn = gen_tls_ld_32 (r3, got);
3645 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3646 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3647 insn = emit_call_insn (insn);
3648 CONST_OR_PURE_CALL_P (insn) = 1;
3649 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3650 insn = get_insns ();
3652 tmp1 = gen_reg_rtx (Pmode);
3653 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3655 emit_libcall_block (insn, tmp1, r3, eqv);
3656 if (rs6000_tls_size == 16)
3659 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3661 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3663 else if (rs6000_tls_size == 32)
3665 tmp2 = gen_reg_rtx (Pmode);
3667 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3669 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3672 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3674 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3678 tmp2 = gen_reg_rtx (Pmode);
3680 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3682 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3684 insn = gen_rtx_SET (Pmode, dest,
3685 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3691 /* IE, or 64-bit offset LE. */
3692 tmp2 = gen_reg_rtx (Pmode);
3694 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3696 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3699 insn = gen_tls_tls_64 (dest, tmp2, addr);
3701 insn = gen_tls_tls_32 (dest, tmp2, addr);
3709 /* Return 1 if X contains a thread-local symbol. */
3712 rs6000_tls_referenced_p (rtx x)
3714 if (! TARGET_HAVE_TLS)
3717 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3720 /* Return 1 if *X is a thread-local symbol. This is the same as
3721 rs6000_tls_symbol_ref except for the type of the unused argument. */
3724 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3726 return RS6000_SYMBOL_REF_TLS_P (*x);
3729 /* The convention appears to be to define this wherever it is used.
3730 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3731 is now used here. */
3732 #ifndef REG_MODE_OK_FOR_BASE_P
3733 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3736 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3737 replace the input X, or the original X if no replacement is called for.
3738 The output parameter *WIN is 1 if the calling macro should goto WIN,
3741 For RS/6000, we wish to handle large displacements off a base
3742 register by splitting the addend across an addiu/addis and the mem insn.
3743 This cuts number of extra insns needed from 3 to 1.
3745 On Darwin, we use this to generate code for floating point constants.
3746 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3747 The Darwin code is inside #if TARGET_MACHO because only then is
3748 machopic_function_base_name() defined. */
3750 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3751 int opnum, int type,
3752 int ind_levels ATTRIBUTE_UNUSED, int *win)
3754 /* We must recognize output that we have already generated ourselves. */
3755 if (GET_CODE (x) == PLUS
3756 && GET_CODE (XEXP (x, 0)) == PLUS
3757 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3758 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3759 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3761 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3762 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3763 opnum, (enum reload_type)type);
3769 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3770 && GET_CODE (x) == LO_SUM
3771 && GET_CODE (XEXP (x, 0)) == PLUS
3772 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3773 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3774 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3775 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3776 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3777 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3778 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3780 /* Result of previous invocation of this function on Darwin
3781 floating point constant. */
3782 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3783 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3784 opnum, (enum reload_type)type);
3790 /* Force ld/std non-word aligned offset into base register by wrapping
3792 if (GET_CODE (x) == PLUS
3793 && GET_CODE (XEXP (x, 0)) == REG
3794 && REGNO (XEXP (x, 0)) < 32
3795 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3796 && GET_CODE (XEXP (x, 1)) == CONST_INT
3797 && (INTVAL (XEXP (x, 1)) & 3) != 0
3798 && !ALTIVEC_VECTOR_MODE (mode)
3799 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3800 && TARGET_POWERPC64)
3802 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3803 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3804 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3805 opnum, (enum reload_type) type);
3810 if (GET_CODE (x) == PLUS
3811 && GET_CODE (XEXP (x, 0)) == REG
3812 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3813 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3814 && GET_CODE (XEXP (x, 1)) == CONST_INT
3815 && !SPE_VECTOR_MODE (mode)
3816 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3818 && !ALTIVEC_VECTOR_MODE (mode))
3820 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3821 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3823 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3825 /* Check for 32-bit overflow. */
3826 if (high + low != val)
3832 /* Reload the high part into a base reg; leave the low part
3833 in the mem directly. */
3835 x = gen_rtx_PLUS (GET_MODE (x),
3836 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3840 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3841 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3842 opnum, (enum reload_type)type);
3847 if (GET_CODE (x) == SYMBOL_REF
3848 && !ALTIVEC_VECTOR_MODE (mode)
3849 && !SPE_VECTOR_MODE (mode)
3851 && DEFAULT_ABI == ABI_DARWIN
3852 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3854 && DEFAULT_ABI == ABI_V4
3857 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
3858 The same goes for DImode without 64-bit gprs and DFmode
3862 && (mode != DImode || TARGET_POWERPC64)
3863 && (mode != DFmode || TARGET_POWERPC64
3864 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3869 rtx offset = gen_rtx_CONST (Pmode,
3870 gen_rtx_MINUS (Pmode, x,
3871 machopic_function_base_sym ()));
3872 x = gen_rtx_LO_SUM (GET_MODE (x),
3873 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3874 gen_rtx_HIGH (Pmode, offset)), offset);
3878 x = gen_rtx_LO_SUM (GET_MODE (x),
3879 gen_rtx_HIGH (Pmode, x), x);
3881 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3882 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3883 opnum, (enum reload_type)type);
3888 /* Reload an offset address wrapped by an AND that represents the
3889 masking of the lower bits. Strip the outer AND and let reload
3890 convert the offset address into an indirect address. */
3892 && ALTIVEC_VECTOR_MODE (mode)
3893 && GET_CODE (x) == AND
3894 && GET_CODE (XEXP (x, 0)) == PLUS
3895 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3896 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3897 && GET_CODE (XEXP (x, 1)) == CONST_INT
3898 && INTVAL (XEXP (x, 1)) == -16)
3906 && constant_pool_expr_p (x)
3907 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3909 x = create_TOC_reference (x);
3917 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3918 that is a valid memory address for an instruction.
3919 The MODE argument is the machine mode for the MEM expression
3920 that wants to use this address.
3922 On the RS/6000, there are four valid address: a SYMBOL_REF that
3923 refers to a constant pool entry of an address (or the sum of it
3924 plus a constant), a short (16-bit signed) constant plus a register,
3925 the sum of two registers, or a register indirect, possibly with an
3926 auto-increment. For DFmode and DImode with a constant plus register,
3927 we must ensure that both words are addressable or PowerPC64 with offset
3930 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3931 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
3932 because adjacent memory cells are accessed by adding word-sized offsets
3933 during assembly output. */
3935 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3937 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3939 && ALTIVEC_VECTOR_MODE (mode)
3940 && GET_CODE (x) == AND
3941 && GET_CODE (XEXP (x, 1)) == CONST_INT
3942 && INTVAL (XEXP (x, 1)) == -16)
3945 if (RS6000_SYMBOL_REF_TLS_P (x))
3947 if (legitimate_indirect_address_p (x, reg_ok_strict))
3949 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3950 && !ALTIVEC_VECTOR_MODE (mode)
3951 && !SPE_VECTOR_MODE (mode)
3954 /* Restrict addressing for DI because of our SUBREG hackery. */
3955 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3958 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3960 if (legitimate_small_data_p (mode, x))
3962 if (legitimate_constant_pool_address_p (x))
3964 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3966 && GET_CODE (x) == PLUS
3967 && GET_CODE (XEXP (x, 0)) == REG
3968 && (XEXP (x, 0) == virtual_stack_vars_rtx
3969 || XEXP (x, 0) == arg_pointer_rtx)
3970 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3972 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3977 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3979 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3980 && (TARGET_POWERPC64 || mode != DImode)
3981 && legitimate_indexed_address_p (x, reg_ok_strict))
3983 if (GET_CODE (x) == PRE_MODIFY
3987 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3989 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3990 && (TARGET_POWERPC64 || mode != DImode)
3991 && !ALTIVEC_VECTOR_MODE (mode)
3992 && !SPE_VECTOR_MODE (mode)
3993 /* Restrict addressing for DI because of our SUBREG hackery. */
3994 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3996 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
3997 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
3998 || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
3999 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4001 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
4006 /* Go to LABEL if ADDR (a legitimate address expression)
4007 has an effect that depends on the machine mode it is used for.
4009 On the RS/6000 this is true of all integral offsets (since AltiVec
4010 modes don't allow them) or is a pre-increment or decrement.
4012 ??? Except that due to conceptual problems in offsettable_address_p
4013 we can't really report the problems of integral offsets. So leave
4014 this assuming that the adjustable offset must be valid for the
4015 sub-words of a TFmode operand, which is what we had before. */
4018 rs6000_mode_dependent_address (rtx addr)
4020 switch (GET_CODE (addr))
4023 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4025 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
4026 return val + 12 + 0x8000 >= 0x10000;
4036 return TARGET_UPDATE;
4045 /* More elaborate version of recog's offsettable_memref_p predicate
4046 that works around the ??? note of rs6000_mode_dependent_address.
4047 In particular it accepts
4049 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4051 in 32-bit mode, that the recog predicate rejects. */
4054 rs6000_offsettable_memref_p (rtx op)
4059 /* First mimic offsettable_memref_p. */
4060 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
4063 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4064 the latter predicate knows nothing about the mode of the memory
4065 reference and, therefore, assumes that it is the largest supported
4066 mode (TFmode). As a consequence, legitimate offsettable memory
4067 references are rejected. rs6000_legitimate_offset_address_p contains
4068 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4069 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
4072 /* Return number of consecutive hard regs needed starting at reg REGNO
4073 to hold something of mode MODE.
4074 This is ordinarily the length in words of a value of mode MODE
4075 but can be less for certain modes in special long registers.
4077 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4078 scalar instructions. The upper 32 bits are only available to the
4081 POWER and PowerPC GPRs hold 32 bits worth;
4082 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4085 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4087 if (FP_REGNO_P (regno))
4088 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4090 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4091 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4093 if (ALTIVEC_REGNO_P (regno))
4095 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4097 /* The value returned for SCmode in the E500 double case is 2 for
4098 ABI compatibility; storing an SCmode value in a single register
4099 would require function_arg and rs6000_spe_function_arg to handle
4100 SCmode so as to pass the value correctly in a pair of
4102 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
4103 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4105 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4108 /* Change register usage conditional on target flags. */
4110 rs6000_conditional_register_usage (void)
4114 /* Set MQ register fixed (already call_used) if not POWER
4115 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4120 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4122 fixed_regs[13] = call_used_regs[13]
4123 = call_really_used_regs[13] = 1;
4125 /* Conditionally disable FPRs. */
4126 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4127 for (i = 32; i < 64; i++)
4128 fixed_regs[i] = call_used_regs[i]
4129 = call_really_used_regs[i] = 1;
4131 /* The TOC register is not killed across calls in a way that is
4132 visible to the compiler. */
4133 if (DEFAULT_ABI == ABI_AIX)
4134 call_really_used_regs[2] = 0;
4136 if (DEFAULT_ABI == ABI_V4
4137 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4139 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4141 if (DEFAULT_ABI == ABI_V4
4142 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4144 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4145 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4146 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4148 if (DEFAULT_ABI == ABI_DARWIN
4149 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4150 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4151 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4152 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4154 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4155 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4156 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4159 global_regs[VSCR_REGNO] = 1;
4163 global_regs[SPEFSCR_REGNO] = 1;
4164 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4165 registers in prologues and epilogues. We no longer use r14
4166 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4167 pool for link-compatibility with older versions of GCC. Once
4168 "old" code has died out, we can return r14 to the allocation
4171 = call_used_regs[14]
4172 = call_really_used_regs[14] = 1;
4175 if (! TARGET_ALTIVEC)
4177 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4178 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4179 call_really_used_regs[VRSAVE_REGNO] = 1;
4182 if (TARGET_ALTIVEC_ABI)
4183 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4184 call_used_regs[i] = call_really_used_regs[i] = 1;
4187 /* Try to output insns to set TARGET equal to the constant C if it can
4188 be done in less than N insns. Do all computations in MODE.
4189 Returns the place where the output has been placed if it can be
4190 done and the insns have been emitted. If it would take more than N
4191 insns, zero is returned and no insns and emitted. */
4194 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4195 rtx source, int n ATTRIBUTE_UNUSED)
4197 rtx result, insn, set;
4198 HOST_WIDE_INT c0, c1;
4205 dest = gen_reg_rtx (mode);
4206 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4210 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4212 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4213 GEN_INT (INTVAL (source)
4214 & (~ (HOST_WIDE_INT) 0xffff))));
4215 emit_insn (gen_rtx_SET (VOIDmode, dest,
4216 gen_rtx_IOR (SImode, copy_rtx (result),
4217 GEN_INT (INTVAL (source) & 0xffff))));
4222 switch (GET_CODE (source))
4225 c0 = INTVAL (source);
4230 #if HOST_BITS_PER_WIDE_INT >= 64
4231 c0 = CONST_DOUBLE_LOW (source);
4234 c0 = CONST_DOUBLE_LOW (source);
4235 c1 = CONST_DOUBLE_HIGH (source);
4243 result = rs6000_emit_set_long_const (dest, c0, c1);
4250 insn = get_last_insn ();
4251 set = single_set (insn);
4252 if (! CONSTANT_P (SET_SRC (set)))
4253 set_unique_reg_note (insn, REG_EQUAL, source);
4258 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4259 fall back to a straight forward decomposition. We do this to avoid
4260 exponential run times encountered when looking for longer sequences
4261 with rs6000_emit_set_const. */
4263 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4265 if (!TARGET_POWERPC64)
4267 rtx operand1, operand2;
4269 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4271 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4273 emit_move_insn (operand1, GEN_INT (c1));
4274 emit_move_insn (operand2, GEN_INT (c2));
4278 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4281 ud2 = (c1 & 0xffff0000) >> 16;
4282 #if HOST_BITS_PER_WIDE_INT >= 64
4286 ud4 = (c2 & 0xffff0000) >> 16;
4288 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4289 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4292 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4294 emit_move_insn (dest, GEN_INT (ud1));
4297 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4298 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4301 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4304 emit_move_insn (dest, GEN_INT (ud2 << 16));
4306 emit_move_insn (copy_rtx (dest),
4307 gen_rtx_IOR (DImode, copy_rtx (dest),
4310 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4311 || (ud4 == 0 && ! (ud3 & 0x8000)))
4314 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4317 emit_move_insn (dest, GEN_INT (ud3 << 16));
4320 emit_move_insn (copy_rtx (dest),
4321 gen_rtx_IOR (DImode, copy_rtx (dest),
4323 emit_move_insn (copy_rtx (dest),
4324 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4327 emit_move_insn (copy_rtx (dest),
4328 gen_rtx_IOR (DImode, copy_rtx (dest),
4334 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4337 emit_move_insn (dest, GEN_INT (ud4 << 16));
4340 emit_move_insn (copy_rtx (dest),
4341 gen_rtx_IOR (DImode, copy_rtx (dest),
4344 emit_move_insn (copy_rtx (dest),
4345 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4348 emit_move_insn (copy_rtx (dest),
4349 gen_rtx_IOR (DImode, copy_rtx (dest),
4350 GEN_INT (ud2 << 16)));
4352 emit_move_insn (copy_rtx (dest),
4353 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4359 /* Helper for the following. Get rid of [r+r] memory refs
4360 in cases where it won't work (TImode, TFmode, TDmode). */
4363 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4365 if (GET_CODE (operands[0]) == MEM
4366 && GET_CODE (XEXP (operands[0], 0)) != REG
4367 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4368 && ! reload_in_progress)
4370 = replace_equiv_address (operands[0],
4371 copy_addr_to_reg (XEXP (operands[0], 0)));
4373 if (GET_CODE (operands[1]) == MEM
4374 && GET_CODE (XEXP (operands[1], 0)) != REG
4375 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4376 && ! reload_in_progress)
4378 = replace_equiv_address (operands[1],
4379 copy_addr_to_reg (XEXP (operands[1], 0)));
4382 /* Emit a move from SOURCE to DEST in mode MODE. */
4384 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4388 operands[1] = source;
4390 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4391 if (GET_CODE (operands[1]) == CONST_DOUBLE
4392 && ! FLOAT_MODE_P (mode)
4393 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4395 /* FIXME. This should never happen. */
4396 /* Since it seems that it does, do the safe thing and convert
4398 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4400 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4401 || FLOAT_MODE_P (mode)
4402 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4403 || CONST_DOUBLE_LOW (operands[1]) < 0)
4404 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4405 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4407 /* Check if GCC is setting up a block move that will end up using FP
4408 registers as temporaries. We must make sure this is acceptable. */
4409 if (GET_CODE (operands[0]) == MEM
4410 && GET_CODE (operands[1]) == MEM
4412 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4413 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4414 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4415 ? 32 : MEM_ALIGN (operands[0])))
4416 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4418 : MEM_ALIGN (operands[1]))))
4419 && ! MEM_VOLATILE_P (operands [0])
4420 && ! MEM_VOLATILE_P (operands [1]))
4422 emit_move_insn (adjust_address (operands[0], SImode, 0),
4423 adjust_address (operands[1], SImode, 0));
4424 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4425 adjust_address (copy_rtx (operands[1]), SImode, 4));
4429 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4430 && !gpc_reg_operand (operands[1], mode))
4431 operands[1] = force_reg (mode, operands[1]);
4433 if (mode == SFmode && ! TARGET_POWERPC
4434 && TARGET_HARD_FLOAT && TARGET_FPRS
4435 && GET_CODE (operands[0]) == MEM)
4439 if (reload_in_progress || reload_completed)
4440 regnum = true_regnum (operands[1]);
4441 else if (GET_CODE (operands[1]) == REG)
4442 regnum = REGNO (operands[1]);
4446 /* If operands[1] is a register, on POWER it may have
4447 double-precision data in it, so truncate it to single
4449 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4452 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4453 : gen_reg_rtx (mode));
4454 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4455 operands[1] = newreg;
4459 /* Recognize the case where operand[1] is a reference to thread-local
4460 data and load its address to a register. */
4461 if (rs6000_tls_referenced_p (operands[1]))
4463 enum tls_model model;
4464 rtx tmp = operands[1];
4467 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4469 addend = XEXP (XEXP (tmp, 0), 1);
4470 tmp = XEXP (XEXP (tmp, 0), 0);
4473 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4474 model = SYMBOL_REF_TLS_MODEL (tmp);
4475 gcc_assert (model != 0);
4477 tmp = rs6000_legitimize_tls_address (tmp, model);
4480 tmp = gen_rtx_PLUS (mode, tmp, addend);
4481 tmp = force_operand (tmp, operands[0]);
4486 /* Handle the case where reload calls us with an invalid address. */
4487 if (reload_in_progress && mode == Pmode
4488 && (! general_operand (operands[1], mode)
4489 || ! nonimmediate_operand (operands[0], mode)))
4492 /* 128-bit constant floating-point values on Darwin should really be
4493 loaded as two parts. */
4494 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4495 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4497 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4498 know how to get a DFmode SUBREG of a TFmode. */
4499 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4500 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4501 simplify_gen_subreg (imode, operands[1], mode, 0),
4503 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4504 GET_MODE_SIZE (imode)),
4505 simplify_gen_subreg (imode, operands[1], mode,
4506 GET_MODE_SIZE (imode)),
4511 /* FIXME: In the long term, this switch statement should go away
4512 and be replaced by a sequence of tests based on things like
4518 if (CONSTANT_P (operands[1])
4519 && GET_CODE (operands[1]) != CONST_INT)
4520 operands[1] = force_const_mem (mode, operands[1]);
4525 rs6000_eliminate_indexed_memrefs (operands);
4531 if (CONSTANT_P (operands[1])
4532 && ! easy_fp_constant (operands[1], mode))
4533 operands[1] = force_const_mem (mode, operands[1]);
4544 if (CONSTANT_P (operands[1])
4545 && !easy_vector_constant (operands[1], mode))
4546 operands[1] = force_const_mem (mode, operands[1]);
4551 /* Use default pattern for address of ELF small data */
4554 && DEFAULT_ABI == ABI_V4
4555 && (GET_CODE (operands[1]) == SYMBOL_REF
4556 || GET_CODE (operands[1]) == CONST)
4557 && small_data_operand (operands[1], mode))
4559 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4563 if (DEFAULT_ABI == ABI_V4
4564 && mode == Pmode && mode == SImode
4565 && flag_pic == 1 && got_operand (operands[1], mode))
4567 emit_insn (gen_movsi_got (operands[0], operands[1]));
4571 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4575 && CONSTANT_P (operands[1])
4576 && GET_CODE (operands[1]) != HIGH
4577 && GET_CODE (operands[1]) != CONST_INT)
4579 rtx target = (!can_create_pseudo_p ()
4581 : gen_reg_rtx (mode));
4583 /* If this is a function address on -mcall-aixdesc,
4584 convert it to the address of the descriptor. */
4585 if (DEFAULT_ABI == ABI_AIX
4586 && GET_CODE (operands[1]) == SYMBOL_REF
4587 && XSTR (operands[1], 0)[0] == '.')
4589 const char *name = XSTR (operands[1], 0);
4591 while (*name == '.')
4593 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4594 CONSTANT_POOL_ADDRESS_P (new_ref)
4595 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4596 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4597 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4598 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4599 operands[1] = new_ref;
4602 if (DEFAULT_ABI == ABI_DARWIN)
4605 if (MACHO_DYNAMIC_NO_PIC_P)
4607 /* Take care of any required data indirection. */
4608 operands[1] = rs6000_machopic_legitimize_pic_address (
4609 operands[1], mode, operands[0]);
4610 if (operands[0] != operands[1])
4611 emit_insn (gen_rtx_SET (VOIDmode,
4612 operands[0], operands[1]));
4616 emit_insn (gen_macho_high (target, operands[1]));
4617 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4621 emit_insn (gen_elf_high (target, operands[1]));
4622 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4626 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4627 and we have put it in the TOC, we just need to make a TOC-relative
4630 && GET_CODE (operands[1]) == SYMBOL_REF
4631 && constant_pool_expr_p (operands[1])
4632 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4633 get_pool_mode (operands[1])))
4635 operands[1] = create_TOC_reference (operands[1]);
4637 else if (mode == Pmode
4638 && CONSTANT_P (operands[1])
4639 && ((GET_CODE (operands[1]) != CONST_INT
4640 && ! easy_fp_constant (operands[1], mode))
4641 || (GET_CODE (operands[1]) == CONST_INT
4642 && num_insns_constant (operands[1], mode) > 2)
4643 || (GET_CODE (operands[0]) == REG
4644 && FP_REGNO_P (REGNO (operands[0]))))
4645 && GET_CODE (operands[1]) != HIGH
4646 && ! legitimate_constant_pool_address_p (operands[1])
4647 && ! toc_relative_expr_p (operands[1]))
4649 /* Emit a USE operation so that the constant isn't deleted if
4650 expensive optimizations are turned on because nobody
4651 references it. This should only be done for operands that
4652 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4653 This should not be done for operands that contain LABEL_REFs.
4654 For now, we just handle the obvious case. */
4655 if (GET_CODE (operands[1]) != LABEL_REF)
4656 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4659 /* Darwin uses a special PIC legitimizer. */
4660 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4663 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4665 if (operands[0] != operands[1])
4666 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4671 /* If we are to limit the number of things we put in the TOC and
4672 this is a symbol plus a constant we can add in one insn,
4673 just put the symbol in the TOC and add the constant. Don't do
4674 this if reload is in progress. */
4675 if (GET_CODE (operands[1]) == CONST
4676 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4677 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4678 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4679 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4680 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4681 && ! side_effects_p (operands[0]))
4684 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4685 rtx other = XEXP (XEXP (operands[1], 0), 1);
4687 sym = force_reg (mode, sym);
4689 emit_insn (gen_addsi3 (operands[0], sym, other));
4691 emit_insn (gen_adddi3 (operands[0], sym, other));
4695 operands[1] = force_const_mem (mode, operands[1]);
4698 && constant_pool_expr_p (XEXP (operands[1], 0))
4699 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4700 get_pool_constant (XEXP (operands[1], 0)),
4701 get_pool_mode (XEXP (operands[1], 0))))
4704 = gen_const_mem (mode,
4705 create_TOC_reference (XEXP (operands[1], 0)));
4706 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4712 rs6000_eliminate_indexed_memrefs (operands);
4716 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4718 gen_rtx_SET (VOIDmode,
4719 operands[0], operands[1]),
4720 gen_rtx_CLOBBER (VOIDmode,
4721 gen_rtx_SCRATCH (SImode)))));
4730 /* Above, we may have called force_const_mem which may have returned
4731 an invalid address. If we can, fix this up; otherwise, reload will
4732 have to deal with it. */
4733 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4734 operands[1] = validize_mem (operands[1]);
4737 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4740 /* Nonzero if we can use a floating-point register to pass this arg. */
4741 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4742 (SCALAR_FLOAT_MODE_P (MODE) \
4743 && (MODE) != SDmode \
4744 && (CUM)->fregno <= FP_ARG_MAX_REG \
4745 && TARGET_HARD_FLOAT && TARGET_FPRS)
4747 /* Nonzero if we can use an AltiVec register to pass this arg. */
4748 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4749 (ALTIVEC_VECTOR_MODE (MODE) \
4750 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4751 && TARGET_ALTIVEC_ABI \
4754 /* Return a nonzero value to say to return the function value in
4755 memory, just as large structures are always returned. TYPE will be
4756 the data type of the value, and FNTYPE will be the type of the
4757 function doing the returning, or @code{NULL} for libcalls.
4759 The AIX ABI for the RS/6000 specifies that all structures are
4760 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4761 specifies that structures <= 8 bytes are returned in r3/r4, but a
4762 draft put them in memory, and GCC used to implement the draft
4763 instead of the final standard. Therefore, aix_struct_return
4764 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4765 compatibility can change DRAFT_V4_STRUCT_RET to override the
4766 default, and -m switches get the final word. See
4767 rs6000_override_options for more details.
4769 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4770 long double support is enabled. These values are returned in memory.
4772 int_size_in_bytes returns -1 for variable size objects, which go in
4773 memory always. The cast to unsigned makes -1 > 8. */
4776 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
4778 /* In the darwin64 abi, try to use registers for larger structs
4780 if (rs6000_darwin64_abi
4781 && TREE_CODE (type) == RECORD_TYPE
4782 && int_size_in_bytes (type) > 0)
4784 CUMULATIVE_ARGS valcum;
4788 valcum.fregno = FP_ARG_MIN_REG;
4789 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4790 /* Do a trial code generation as if this were going to be passed
4791 as an argument; if any part goes in memory, we return NULL. */
4792 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4795 /* Otherwise fall through to more conventional ABI rules. */
4798 if (AGGREGATE_TYPE_P (type)
4799 && (aix_struct_return
4800 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4803 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4804 modes only exist for GCC vector types if -maltivec. */
4805 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4806 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4809 /* Return synthetic vectors in memory. */
4810 if (TREE_CODE (type) == VECTOR_TYPE
4811 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4813 static bool warned_for_return_big_vectors = false;
4814 if (!warned_for_return_big_vectors)
4816 warning (0, "GCC vector returned by reference: "
4817 "non-standard ABI extension with no compatibility guarantee");
4818 warned_for_return_big_vectors = true;
4823 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4829 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4830 for a call to a function whose data type is FNTYPE.
4831 For a library call, FNTYPE is 0.
4833 For incoming args we set the number of arguments in the prototype large
4834 so we never return a PARALLEL. */
4837 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4838 rtx libname ATTRIBUTE_UNUSED, int incoming,
4839 int libcall, int n_named_args)
4841 static CUMULATIVE_ARGS zero_cumulative;
4843 *cum = zero_cumulative;
4845 cum->fregno = FP_ARG_MIN_REG;
4846 cum->vregno = ALTIVEC_ARG_MIN_REG;
4847 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4848 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4849 ? CALL_LIBCALL : CALL_NORMAL);
4850 cum->sysv_gregno = GP_ARG_MIN_REG;
4851 cum->stdarg = fntype
4852 && (TYPE_ARG_TYPES (fntype) != 0
4853 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4854 != void_type_node));
4856 cum->nargs_prototype = 0;
4857 if (incoming || cum->prototype)
4858 cum->nargs_prototype = n_named_args;
4860 /* Check for a longcall attribute. */
4861 if ((!fntype && rs6000_default_long_calls)
4863 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4864 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4865 cum->call_cookie |= CALL_LONG;
4867 if (TARGET_DEBUG_ARG)
4869 fprintf (stderr, "\ninit_cumulative_args:");
4872 tree ret_type = TREE_TYPE (fntype);
4873 fprintf (stderr, " ret code = %s,",
4874 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4877 if (cum->call_cookie & CALL_LONG)
4878 fprintf (stderr, " longcall,");
4880 fprintf (stderr, " proto = %d, nargs = %d\n",
4881 cum->prototype, cum->nargs_prototype);
4886 && TARGET_ALTIVEC_ABI
4887 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4889 error ("cannot return value in vector register because"
4890 " altivec instructions are disabled, use -maltivec"
4895 /* Return true if TYPE must be passed on the stack and not in registers. */
4898 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
4900 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4901 return must_pass_in_stack_var_size (mode, type);
4903 return must_pass_in_stack_var_size_or_pad (mode, type);
4906 /* If defined, a C expression which determines whether, and in which
4907 direction, to pad out an argument with extra space. The value
4908 should be of type `enum direction': either `upward' to pad above
4909 the argument, `downward' to pad below, or `none' to inhibit
4912 For the AIX ABI structs are always stored left shifted in their
4916 function_arg_padding (enum machine_mode mode, const_tree type)
4918 #ifndef AGGREGATE_PADDING_FIXED
4919 #define AGGREGATE_PADDING_FIXED 0
4921 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4922 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4925 if (!AGGREGATE_PADDING_FIXED)
4927 /* GCC used to pass structures of the same size as integer types as
4928 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4929 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4930 passed padded downward, except that -mstrict-align further
4931 muddied the water in that multi-component structures of 2 and 4
4932 bytes in size were passed padded upward.
4934 The following arranges for best compatibility with previous
4935 versions of gcc, but removes the -mstrict-align dependency. */
4936 if (BYTES_BIG_ENDIAN)
4938 HOST_WIDE_INT size = 0;
4940 if (mode == BLKmode)
4942 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4943 size = int_size_in_bytes (type);
4946 size = GET_MODE_SIZE (mode);
4948 if (size == 1 || size == 2 || size == 4)
4954 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4956 if (type != 0 && AGGREGATE_TYPE_P (type))
4960 /* Fall back to the default. */
4961 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4964 /* If defined, a C expression that gives the alignment boundary, in bits,
4965 of an argument with the specified mode and type. If it is not defined,
4966 PARM_BOUNDARY is used for all arguments.
4968 V.4 wants long longs and doubles to be double word aligned. Just
4969 testing the mode size is a boneheaded way to do this as it means
4970 that other types such as complex int are also double word aligned.
4971 However, we're stuck with this because changing the ABI might break
4972 existing library interfaces.
4974 Doubleword align SPE vectors.
4975 Quadword align Altivec vectors.
4976 Quadword align large synthetic vector types. */
4979 function_arg_boundary (enum machine_mode mode, tree type)
4981 if (DEFAULT_ABI == ABI_V4
4982 && (GET_MODE_SIZE (mode) == 8
4983 || (TARGET_HARD_FLOAT
4985 && (mode == TFmode || mode == TDmode))))
4987 else if (SPE_VECTOR_MODE (mode)
4988 || (type && TREE_CODE (type) == VECTOR_TYPE
4989 && int_size_in_bytes (type) >= 8
4990 && int_size_in_bytes (type) < 16))
4992 else if (ALTIVEC_VECTOR_MODE (mode)
4993 || (type && TREE_CODE (type) == VECTOR_TYPE
4994 && int_size_in_bytes (type) >= 16))
4996 else if (rs6000_darwin64_abi && mode == BLKmode
4997 && type && TYPE_ALIGN (type) > 64)
5000 return PARM_BOUNDARY;
5003 /* For a function parm of MODE and TYPE, return the starting word in
5004 the parameter area. NWORDS of the parameter area are already used. */
5007 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
5010 unsigned int parm_offset;
5012 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5013 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
5014 return nwords + (-(parm_offset + nwords) & align);
5017 /* Compute the size (in words) of a function argument. */
5019 static unsigned long
5020 rs6000_arg_size (enum machine_mode mode, tree type)
5024 if (mode != BLKmode)
5025 size = GET_MODE_SIZE (mode);
5027 size = int_size_in_bytes (type);
5030 return (size + 3) >> 2;
5032 return (size + 7) >> 3;
5035 /* Use this to flush pending int fields. */
5038 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
5039 HOST_WIDE_INT bitpos)
5041 unsigned int startbit, endbit;
5042 int intregs, intoffset;
5043 enum machine_mode mode;
5045 if (cum->intoffset == -1)
5048 intoffset = cum->intoffset;
5049 cum->intoffset = -1;
5051 if (intoffset % BITS_PER_WORD != 0)
5053 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5055 if (mode == BLKmode)
5057 /* We couldn't find an appropriate mode, which happens,
5058 e.g., in packed structs when there are 3 bytes to load.
5059 Back intoffset back to the beginning of the word in this
5061 intoffset = intoffset & -BITS_PER_WORD;
5065 startbit = intoffset & -BITS_PER_WORD;
5066 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5067 intregs = (endbit - startbit) / BITS_PER_WORD;
5068 cum->words += intregs;
5071 /* The darwin64 ABI calls for us to recurse down through structs,
5072 looking for elements passed in registers. Unfortunately, we have
5073 to track int register count here also because of misalignments
5074 in powerpc alignment mode. */
5077 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
5079 HOST_WIDE_INT startbitpos)
5083 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5084 if (TREE_CODE (f) == FIELD_DECL)
5086 HOST_WIDE_INT bitpos = startbitpos;
5087 tree ftype = TREE_TYPE (f);
5088 enum machine_mode mode;
5089 if (ftype == error_mark_node)
5091 mode = TYPE_MODE (ftype);
5093 if (DECL_SIZE (f) != 0
5094 && host_integerp (bit_position (f), 1))
5095 bitpos += int_bit_position (f);
5097 /* ??? FIXME: else assume zero offset. */
5099 if (TREE_CODE (ftype) == RECORD_TYPE)
5100 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
5101 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
5103 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5104 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5105 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
5107 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
5109 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5113 else if (cum->intoffset == -1)
5114 cum->intoffset = bitpos;
5118 /* Update the data in CUM to advance over an argument
5119 of mode MODE and data type TYPE.
5120 (TYPE is null for libcalls where that information may not be available.)
5122 Note that for args passed by reference, function_arg will be called
5123 with MODE and TYPE set to that of the pointer to the arg, not the arg
5127 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5128 tree type, int named, int depth)
5132 /* Only tick off an argument if we're not recursing. */
5134 cum->nargs_prototype--;
5136 if (TARGET_ALTIVEC_ABI
5137 && (ALTIVEC_VECTOR_MODE (mode)
5138 || (type && TREE_CODE (type) == VECTOR_TYPE
5139 && int_size_in_bytes (type) == 16)))
5143 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5146 if (!TARGET_ALTIVEC)
5147 error ("cannot pass argument in vector register because"
5148 " altivec instructions are disabled, use -maltivec"
5151 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5152 even if it is going to be passed in a vector register.
5153 Darwin does the same for variable-argument functions. */
5154 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5155 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5165 /* Vector parameters must be 16-byte aligned. This places
5166 them at 2 mod 4 in terms of words in 32-bit mode, since
5167 the parameter save area starts at offset 24 from the
5168 stack. In 64-bit mode, they just have to start on an
5169 even word, since the parameter save area is 16-byte
5170 aligned. Space for GPRs is reserved even if the argument
5171 will be passed in memory. */
5173 align = (2 - cum->words) & 3;
5175 align = cum->words & 1;
5176 cum->words += align + rs6000_arg_size (mode, type);
5178 if (TARGET_DEBUG_ARG)
5180 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5182 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5183 cum->nargs_prototype, cum->prototype,
5184 GET_MODE_NAME (mode));
5188 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5190 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5193 else if (rs6000_darwin64_abi
5195 && TREE_CODE (type) == RECORD_TYPE
5196 && (size = int_size_in_bytes (type)) > 0)
5198 /* Variable sized types have size == -1 and are
5199 treated as if consisting entirely of ints.
5200 Pad to 16 byte boundary if needed. */
5201 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5202 && (cum->words % 2) != 0)
5204 /* For varargs, we can just go up by the size of the struct. */
5206 cum->words += (size + 7) / 8;
5209 /* It is tempting to say int register count just goes up by
5210 sizeof(type)/8, but this is wrong in a case such as
5211 { int; double; int; } [powerpc alignment]. We have to
5212 grovel through the fields for these too. */
5214 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5215 rs6000_darwin64_record_arg_advance_flush (cum,
5216 size * BITS_PER_UNIT);
5219 else if (DEFAULT_ABI == ABI_V4)
5221 if (TARGET_HARD_FLOAT && TARGET_FPRS
5222 && (mode == SFmode || mode == DFmode
5223 || mode == DDmode || mode == TDmode
5224 || (mode == TFmode && !TARGET_IEEEQUAD)))
5226 /* _Decimal128 must use an even/odd register pair. This assumes
5227 that the register number is odd when fregno is odd. */
5228 if (mode == TDmode && (cum->fregno % 2) == 1)
5231 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5232 <= FP_ARG_V4_MAX_REG)
5233 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5236 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5237 if (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode)
5238 cum->words += cum->words & 1;
5239 cum->words += rs6000_arg_size (mode, type);
5244 int n_words = rs6000_arg_size (mode, type);
5245 int gregno = cum->sysv_gregno;
5247 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5248 (r7,r8) or (r9,r10). As does any other 2 word item such
5249 as complex int due to a historical mistake. */
5251 gregno += (1 - gregno) & 1;
5253 /* Multi-reg args are not split between registers and stack. */
5254 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5256 /* Long long and SPE vectors are aligned on the stack.
5257 So are other 2 word items such as complex int due to
5258 a historical mistake. */
5260 cum->words += cum->words & 1;
5261 cum->words += n_words;
5264 /* Note: continuing to accumulate gregno past when we've started
5265 spilling to the stack indicates the fact that we've started
5266 spilling to the stack to expand_builtin_saveregs. */
5267 cum->sysv_gregno = gregno + n_words;
5270 if (TARGET_DEBUG_ARG)
5272 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5273 cum->words, cum->fregno);
5274 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5275 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5276 fprintf (stderr, "mode = %4s, named = %d\n",
5277 GET_MODE_NAME (mode), named);
5282 int n_words = rs6000_arg_size (mode, type);
5283 int start_words = cum->words;
5284 int align_words = rs6000_parm_start (mode, type, start_words);
5286 cum->words = align_words + n_words;
5288 if (SCALAR_FLOAT_MODE_P (mode)
5290 && TARGET_HARD_FLOAT && TARGET_FPRS)
5292 /* _Decimal128 must be passed in an even/odd float register pair.
5293 This assumes that the register number is odd when fregno is
5295 if (mode == TDmode && (cum->fregno % 2) == 1)
5297 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5300 if (TARGET_DEBUG_ARG)
5302 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5303 cum->words, cum->fregno);
5304 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5305 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5306 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5307 named, align_words - start_words, depth);
5313 spe_build_register_parallel (enum machine_mode mode, int gregno)
5320 r1 = gen_rtx_REG (DImode, gregno);
5321 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5322 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5326 r1 = gen_rtx_REG (DImode, gregno);
5327 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5328 r3 = gen_rtx_REG (DImode, gregno + 2);
5329 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5330 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5333 r1 = gen_rtx_REG (DImode, gregno);
5334 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5335 r3 = gen_rtx_REG (DImode, gregno + 2);
5336 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5337 r5 = gen_rtx_REG (DImode, gregno + 4);
5338 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5339 r7 = gen_rtx_REG (DImode, gregno + 6);
5340 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5341 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5348 /* Determine where to put a SIMD argument on the SPE. */
5350 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5353 int gregno = cum->sysv_gregno;
5355 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5356 are passed and returned in a pair of GPRs for ABI compatibility. */
5357 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode
5358 || mode == TFmode || mode == TCmode))
5360 int n_words = rs6000_arg_size (mode, type);
5362 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5364 gregno += (1 - gregno) & 1;
5366 /* Multi-reg args are not split between registers and stack. */
5367 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5370 return spe_build_register_parallel (mode, gregno);
5374 int n_words = rs6000_arg_size (mode, type);
5376 /* SPE vectors are put in odd registers. */
5377 if (n_words == 2 && (gregno & 1) == 0)
5380 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5383 enum machine_mode m = SImode;
5385 r1 = gen_rtx_REG (m, gregno);
5386 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5387 r2 = gen_rtx_REG (m, gregno + 1);
5388 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5389 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5396 if (gregno <= GP_ARG_MAX_REG)
5397 return gen_rtx_REG (mode, gregno);
5403 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5404 structure between cum->intoffset and bitpos to integer registers. */
5407 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5408 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5410 enum machine_mode mode;
5412 unsigned int startbit, endbit;
5413 int this_regno, intregs, intoffset;
5416 if (cum->intoffset == -1)
5419 intoffset = cum->intoffset;
5420 cum->intoffset = -1;
5422 /* If this is the trailing part of a word, try to only load that
5423 much into the register. Otherwise load the whole register. Note
5424 that in the latter case we may pick up unwanted bits. It's not a
5425 problem at the moment but may wish to revisit. */
5427 if (intoffset % BITS_PER_WORD != 0)
5429 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5431 if (mode == BLKmode)
5433 /* We couldn't find an appropriate mode, which happens,
5434 e.g., in packed structs when there are 3 bytes to load.
5435 Back intoffset back to the beginning of the word in this
5437 intoffset = intoffset & -BITS_PER_WORD;
5444 startbit = intoffset & -BITS_PER_WORD;
5445 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5446 intregs = (endbit - startbit) / BITS_PER_WORD;
5447 this_regno = cum->words + intoffset / BITS_PER_WORD;
5449 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5452 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5456 intoffset /= BITS_PER_UNIT;
5459 regno = GP_ARG_MIN_REG + this_regno;
5460 reg = gen_rtx_REG (mode, regno);
5462 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5465 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5469 while (intregs > 0);
5472 /* Recursive workhorse for the following. */
5475 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
5476 HOST_WIDE_INT startbitpos, rtx rvec[],
5481 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5482 if (TREE_CODE (f) == FIELD_DECL)
5484 HOST_WIDE_INT bitpos = startbitpos;
5485 tree ftype = TREE_TYPE (f);
5486 enum machine_mode mode;
5487 if (ftype == error_mark_node)
5489 mode = TYPE_MODE (ftype);
5491 if (DECL_SIZE (f) != 0
5492 && host_integerp (bit_position (f), 1))
5493 bitpos += int_bit_position (f);
5495 /* ??? FIXME: else assume zero offset. */
5497 if (TREE_CODE (ftype) == RECORD_TYPE)
5498 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5499 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5504 case SCmode: mode = SFmode; break;
5505 case DCmode: mode = DFmode; break;
5506 case TCmode: mode = TFmode; break;
5510 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5512 = gen_rtx_EXPR_LIST (VOIDmode,
5513 gen_rtx_REG (mode, cum->fregno++),
5514 GEN_INT (bitpos / BITS_PER_UNIT));
5515 if (mode == TFmode || mode == TDmode)
5518 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5520 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5522 = gen_rtx_EXPR_LIST (VOIDmode,
5523 gen_rtx_REG (mode, cum->vregno++),
5524 GEN_INT (bitpos / BITS_PER_UNIT));
5526 else if (cum->intoffset == -1)
5527 cum->intoffset = bitpos;
5531 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5532 the register(s) to be used for each field and subfield of a struct
5533 being passed by value, along with the offset of where the
5534 register's value may be found in the block. FP fields go in FP
5535 register, vector fields go in vector registers, and everything
5536 else goes in int registers, packed as in memory.
5538 This code is also used for function return values. RETVAL indicates
5539 whether this is the case.
5541 Much of this is taken from the SPARC V9 port, which has a similar
5542 calling convention. */
5545 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
5546 int named, bool retval)
5548 rtx rvec[FIRST_PSEUDO_REGISTER];
5549 int k = 1, kbase = 1;
5550 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5551 /* This is a copy; modifications are not visible to our caller. */
5552 CUMULATIVE_ARGS copy_cum = *orig_cum;
5553 CUMULATIVE_ARGS *cum = ©_cum;
5555 /* Pad to 16 byte boundary if needed. */
5556 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5557 && (cum->words % 2) != 0)
5564 /* Put entries into rvec[] for individual FP and vector fields, and
5565 for the chunks of memory that go in int regs. Note we start at
5566 element 1; 0 is reserved for an indication of using memory, and
5567 may or may not be filled in below. */
5568 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5569 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5571 /* If any part of the struct went on the stack put all of it there.
5572 This hack is because the generic code for
5573 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5574 parts of the struct are not at the beginning. */
5578 return NULL_RTX; /* doesn't go in registers at all */
5580 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5582 if (k > 1 || cum->use_stack)
5583 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5588 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5591 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5595 rtx rvec[GP_ARG_NUM_REG + 1];
5597 if (align_words >= GP_ARG_NUM_REG)
5600 n_units = rs6000_arg_size (mode, type);
5602 /* Optimize the simple case where the arg fits in one gpr, except in
5603 the case of BLKmode due to assign_parms assuming that registers are
5604 BITS_PER_WORD wide. */
5606 || (n_units == 1 && mode != BLKmode))
5607 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5610 if (align_words + n_units > GP_ARG_NUM_REG)
5611 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5612 using a magic NULL_RTX component.
5613 This is not strictly correct. Only some of the arg belongs in
5614 memory, not all of it. However, the normal scheme using
5615 function_arg_partial_nregs can result in unusual subregs, eg.
5616 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5617 store the whole arg to memory is often more efficient than code
5618 to store pieces, and we know that space is available in the right
5619 place for the whole arg. */
5620 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5625 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5626 rtx off = GEN_INT (i++ * 4);
5627 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5629 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5631 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5634 /* Determine where to put an argument to a function.
5635 Value is zero to push the argument on the stack,
5636 or a hard register in which to store the argument.
5638 MODE is the argument's machine mode.
5639 TYPE is the data type of the argument (as a tree).
5640 This is null for libcalls where that information may
5642 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5643 the preceding args and about the function being called. It is
5644 not modified in this routine.
5645 NAMED is nonzero if this argument is a named parameter
5646 (otherwise it is an extra parameter matching an ellipsis).
5648 On RS/6000 the first eight words of non-FP are normally in registers
5649 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5650 Under V.4, the first 8 FP args are in registers.
5652 If this is floating-point and no prototype is specified, we use
5653 both an FP and integer register (or possibly FP reg and stack). Library
5654 functions (when CALL_LIBCALL is set) always have the proper types for args,
5655 so we can pass the FP value just in one register. emit_library_function
5656 doesn't support PARALLEL anyway.
5658 Note that for args passed by reference, function_arg will be called
5659 with MODE and TYPE set to that of the pointer to the arg, not the arg
5663 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5664 tree type, int named)
5666 enum rs6000_abi abi = DEFAULT_ABI;
5668 /* Return a marker to indicate whether CR1 needs to set or clear the
5669 bit that V.4 uses to say fp args were passed in registers.
5670 Assume that we don't need the marker for software floating point,
5671 or compiler generated library calls. */
5672 if (mode == VOIDmode)
5675 && (cum->call_cookie & CALL_LIBCALL) == 0
5677 || (cum->nargs_prototype < 0
5678 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5680 /* For the SPE, we need to crxor CR6 always. */
5682 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5683 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5684 return GEN_INT (cum->call_cookie
5685 | ((cum->fregno == FP_ARG_MIN_REG)
5686 ? CALL_V4_SET_FP_ARGS
5687 : CALL_V4_CLEAR_FP_ARGS));
5690 return GEN_INT (cum->call_cookie);
5693 if (rs6000_darwin64_abi && mode == BLKmode
5694 && TREE_CODE (type) == RECORD_TYPE)
5696 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5697 if (rslt != NULL_RTX)
5699 /* Else fall through to usual handling. */
5702 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5703 if (TARGET_64BIT && ! cum->prototype)
5705 /* Vector parameters get passed in vector register
5706 and also in GPRs or memory, in absence of prototype. */
5709 align_words = (cum->words + 1) & ~1;
5711 if (align_words >= GP_ARG_NUM_REG)
5717 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5719 return gen_rtx_PARALLEL (mode,
5721 gen_rtx_EXPR_LIST (VOIDmode,
5723 gen_rtx_EXPR_LIST (VOIDmode,
5724 gen_rtx_REG (mode, cum->vregno),
5728 return gen_rtx_REG (mode, cum->vregno);
5729 else if (TARGET_ALTIVEC_ABI
5730 && (ALTIVEC_VECTOR_MODE (mode)
5731 || (type && TREE_CODE (type) == VECTOR_TYPE
5732 && int_size_in_bytes (type) == 16)))
5734 if (named || abi == ABI_V4)
5738 /* Vector parameters to varargs functions under AIX or Darwin
5739 get passed in memory and possibly also in GPRs. */
5740 int align, align_words, n_words;
5741 enum machine_mode part_mode;
5743 /* Vector parameters must be 16-byte aligned. This places them at
5744 2 mod 4 in terms of words in 32-bit mode, since the parameter
5745 save area starts at offset 24 from the stack. In 64-bit mode,
5746 they just have to start on an even word, since the parameter
5747 save area is 16-byte aligned. */
5749 align = (2 - cum->words) & 3;
5751 align = cum->words & 1;
5752 align_words = cum->words + align;
5754 /* Out of registers? Memory, then. */
5755 if (align_words >= GP_ARG_NUM_REG)
5758 if (TARGET_32BIT && TARGET_POWERPC64)
5759 return rs6000_mixed_function_arg (mode, type, align_words);
5761 /* The vector value goes in GPRs. Only the part of the
5762 value in GPRs is reported here. */
5764 n_words = rs6000_arg_size (mode, type);
5765 if (align_words + n_words > GP_ARG_NUM_REG)
5766 /* Fortunately, there are only two possibilities, the value
5767 is either wholly in GPRs or half in GPRs and half not. */
5770 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5773 else if (TARGET_SPE_ABI && TARGET_SPE
5774 && (SPE_VECTOR_MODE (mode)
5775 || (TARGET_E500_DOUBLE && (mode == DFmode
5780 || mode == TCmode))))
5781 return rs6000_spe_function_arg (cum, mode, type);
5783 else if (abi == ABI_V4)
5785 if (TARGET_HARD_FLOAT && TARGET_FPRS
5786 && (mode == SFmode || mode == DFmode
5787 || (mode == TFmode && !TARGET_IEEEQUAD)
5788 || mode == DDmode || mode == TDmode))
5790 /* _Decimal128 must use an even/odd register pair. This assumes
5791 that the register number is odd when fregno is odd. */
5792 if (mode == TDmode && (cum->fregno % 2) == 1)
5795 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5796 <= FP_ARG_V4_MAX_REG)
5797 return gen_rtx_REG (mode, cum->fregno);
5803 int n_words = rs6000_arg_size (mode, type);
5804 int gregno = cum->sysv_gregno;
5806 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5807 (r7,r8) or (r9,r10). As does any other 2 word item such
5808 as complex int due to a historical mistake. */
5810 gregno += (1 - gregno) & 1;
5812 /* Multi-reg args are not split between registers and stack. */
5813 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5816 if (TARGET_32BIT && TARGET_POWERPC64)
5817 return rs6000_mixed_function_arg (mode, type,
5818 gregno - GP_ARG_MIN_REG);
5819 return gen_rtx_REG (mode, gregno);
5824 int align_words = rs6000_parm_start (mode, type, cum->words);
5826 /* _Decimal128 must be passed in an even/odd float register pair.
5827 This assumes that the register number is odd when fregno is odd. */
5828 if (mode == TDmode && (cum->fregno % 2) == 1)
5831 if (USE_FP_FOR_ARG_P (cum, mode, type))
5833 rtx rvec[GP_ARG_NUM_REG + 1];
5837 enum machine_mode fmode = mode;
5838 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5840 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5842 /* Currently, we only ever need one reg here because complex
5843 doubles are split. */
5844 gcc_assert (cum->fregno == FP_ARG_MAX_REG
5845 && (fmode == TFmode || fmode == TDmode));
5847 /* Long double or _Decimal128 split over regs and memory. */
5848 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
5851 /* Do we also need to pass this arg in the parameter save
5854 && (cum->nargs_prototype <= 0
5855 || (DEFAULT_ABI == ABI_AIX
5857 && align_words >= GP_ARG_NUM_REG)));
5859 if (!needs_psave && mode == fmode)
5860 return gen_rtx_REG (fmode, cum->fregno);
5865 /* Describe the part that goes in gprs or the stack.
5866 This piece must come first, before the fprs. */
5867 if (align_words < GP_ARG_NUM_REG)
5869 unsigned long n_words = rs6000_arg_size (mode, type);
5871 if (align_words + n_words > GP_ARG_NUM_REG
5872 || (TARGET_32BIT && TARGET_POWERPC64))
5874 /* If this is partially on the stack, then we only
5875 include the portion actually in registers here. */
5876 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5879 if (align_words + n_words > GP_ARG_NUM_REG)
5880 /* Not all of the arg fits in gprs. Say that it
5881 goes in memory too, using a magic NULL_RTX
5882 component. Also see comment in
5883 rs6000_mixed_function_arg for why the normal
5884 function_arg_partial_nregs scheme doesn't work
5886 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5890 r = gen_rtx_REG (rmode,
5891 GP_ARG_MIN_REG + align_words);
5892 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5893 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5895 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5899 /* The whole arg fits in gprs. */
5900 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5901 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5905 /* It's entirely in memory. */
5906 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5909 /* Describe where this piece goes in the fprs. */
5910 r = gen_rtx_REG (fmode, cum->fregno);
5911 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5913 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5915 else if (align_words < GP_ARG_NUM_REG)
5917 if (TARGET_32BIT && TARGET_POWERPC64)
5918 return rs6000_mixed_function_arg (mode, type, align_words);
5920 if (mode == BLKmode)
5923 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5930 /* For an arg passed partly in registers and partly in memory, this is
5931 the number of bytes passed in registers. For args passed entirely in
5932 registers or entirely in memory, zero. When an arg is described by a
5933 PARALLEL, perhaps using more than one register type, this function
5934 returns the number of bytes used by the first element of the PARALLEL. */
5937 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5938 tree type, bool named)
5943 if (DEFAULT_ABI == ABI_V4)
5946 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5947 && cum->nargs_prototype >= 0)
5950 /* In this complicated case we just disable the partial_nregs code. */
5951 if (rs6000_darwin64_abi && mode == BLKmode
5952 && TREE_CODE (type) == RECORD_TYPE
5953 && int_size_in_bytes (type) > 0)
5956 align_words = rs6000_parm_start (mode, type, cum->words);
5958 if (USE_FP_FOR_ARG_P (cum, mode, type))
5960 /* If we are passing this arg in the fixed parameter save area
5961 (gprs or memory) as well as fprs, then this function should
5962 return the number of partial bytes passed in the parameter
5963 save area rather than partial bytes passed in fprs. */
5965 && (cum->nargs_prototype <= 0
5966 || (DEFAULT_ABI == ABI_AIX
5968 && align_words >= GP_ARG_NUM_REG)))
5970 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5971 > FP_ARG_MAX_REG + 1)
5972 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5973 else if (cum->nargs_prototype >= 0)
5977 if (align_words < GP_ARG_NUM_REG
5978 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5979 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5981 if (ret != 0 && TARGET_DEBUG_ARG)
5982 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5987 /* A C expression that indicates when an argument must be passed by
5988 reference. If nonzero for an argument, a copy of that argument is
5989 made in memory and a pointer to the argument is passed instead of
5990 the argument itself. The pointer is passed in whatever way is
5991 appropriate for passing a pointer to that type.
5993 Under V.4, aggregates and long double are passed by reference.
5995 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5996 reference unless the AltiVec vector extension ABI is in force.
5998 As an extension to all ABIs, variable sized types are passed by
6002 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6003 enum machine_mode mode, const_tree type,
6004 bool named ATTRIBUTE_UNUSED)
6006 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
6008 if (TARGET_DEBUG_ARG)
6009 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
6016 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
6018 if (TARGET_DEBUG_ARG)
6019 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
6023 if (int_size_in_bytes (type) < 0)
6025 if (TARGET_DEBUG_ARG)
6026 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
6030 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6031 modes only exist for GCC vector types if -maltivec. */
6032 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
6034 if (TARGET_DEBUG_ARG)
6035 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
6039 /* Pass synthetic vectors in memory. */
6040 if (TREE_CODE (type) == VECTOR_TYPE
6041 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6043 static bool warned_for_pass_big_vectors = false;
6044 if (TARGET_DEBUG_ARG)
6045 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
6046 if (!warned_for_pass_big_vectors)
6048 warning (0, "GCC vector passed by reference: "
6049 "non-standard ABI extension with no compatibility guarantee");
6050 warned_for_pass_big_vectors = true;
6059 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
6062 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
6067 for (i = 0; i < nregs; i++)
6069 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
6070 if (reload_completed)
6072 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
6075 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
6076 i * GET_MODE_SIZE (reg_mode));
6079 tem = replace_equiv_address (tem, XEXP (tem, 0));
6083 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
6087 /* Perform any needed actions needed for a function that is receiving a
6088 variable number of arguments.
6092 MODE and TYPE are the mode and type of the current parameter.
6094 PRETEND_SIZE is a variable that should be set to the amount of stack
6095 that must be pushed by the prolog to pretend that our caller pushed
6098 Normally, this macro will push all remaining incoming registers on the
6099 stack and set PRETEND_SIZE to the length of the registers pushed. */
6102 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6103 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6106 CUMULATIVE_ARGS next_cum;
6107 int reg_size = TARGET_32BIT ? 4 : 8;
6108 rtx save_area = NULL_RTX, mem;
6109 int first_reg_offset;
6112 /* Skip the last named argument. */
6114 function_arg_advance (&next_cum, mode, type, 1, 0);
6116 if (DEFAULT_ABI == ABI_V4)
6118 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
6122 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
6123 HOST_WIDE_INT offset = 0;
6125 /* Try to optimize the size of the varargs save area.
6126 The ABI requires that ap.reg_save_area is doubleword
6127 aligned, but we don't need to allocate space for all
6128 the bytes, only those to which we actually will save
6130 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
6131 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
6132 if (TARGET_HARD_FLOAT && TARGET_FPRS
6133 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6134 && cfun->va_list_fpr_size)
6137 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
6138 * UNITS_PER_FP_WORD;
6139 if (cfun->va_list_fpr_size
6140 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6141 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
6143 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6144 * UNITS_PER_FP_WORD;
6148 offset = -((first_reg_offset * reg_size) & ~7);
6149 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6151 gpr_reg_num = cfun->va_list_gpr_size;
6152 if (reg_size == 4 && (first_reg_offset & 1))
6155 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6158 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6160 - (int) (GP_ARG_NUM_REG * reg_size);
6162 if (gpr_size + fpr_size)
6165 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6166 gcc_assert (GET_CODE (reg_save_area) == MEM);
6167 reg_save_area = XEXP (reg_save_area, 0);
6168 if (GET_CODE (reg_save_area) == PLUS)
6170 gcc_assert (XEXP (reg_save_area, 0)
6171 == virtual_stack_vars_rtx);
6172 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6173 offset += INTVAL (XEXP (reg_save_area, 1));
6176 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6179 cfun->machine->varargs_save_offset = offset;
6180 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6185 first_reg_offset = next_cum.words;
6186 save_area = virtual_incoming_args_rtx;
6188 if (targetm.calls.must_pass_in_stack (mode, type))
6189 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6192 set = get_varargs_alias_set ();
6193 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6194 && cfun->va_list_gpr_size)
6196 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6198 if (va_list_gpr_counter_field)
6200 /* V4 va_list_gpr_size counts number of registers needed. */
6201 if (nregs > cfun->va_list_gpr_size)
6202 nregs = cfun->va_list_gpr_size;
6206 /* char * va_list instead counts number of bytes needed. */
6207 if (nregs > cfun->va_list_gpr_size / reg_size)
6208 nregs = cfun->va_list_gpr_size / reg_size;
6211 mem = gen_rtx_MEM (BLKmode,
6212 plus_constant (save_area,
6213 first_reg_offset * reg_size));
6214 MEM_NOTRAP_P (mem) = 1;
6215 set_mem_alias_set (mem, set);
6216 set_mem_align (mem, BITS_PER_WORD);
6218 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6222 /* Save FP registers if needed. */
6223 if (DEFAULT_ABI == ABI_V4
6224 && TARGET_HARD_FLOAT && TARGET_FPRS
6226 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6227 && cfun->va_list_fpr_size)
6229 int fregno = next_cum.fregno, nregs;
6230 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6231 rtx lab = gen_label_rtx ();
6232 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6233 * UNITS_PER_FP_WORD);
6236 (gen_rtx_SET (VOIDmode,
6238 gen_rtx_IF_THEN_ELSE (VOIDmode,
6239 gen_rtx_NE (VOIDmode, cr1,
6241 gen_rtx_LABEL_REF (VOIDmode, lab),
6245 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6246 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6248 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6249 MEM_NOTRAP_P (mem) = 1;
6250 set_mem_alias_set (mem, set);
6251 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6252 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6259 /* Create the va_list data type. */
6262 rs6000_build_builtin_va_list (void)
6264 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6266 /* For AIX, prefer 'char *' because that's what the system
6267 header files like. */
6268 if (DEFAULT_ABI != ABI_V4)
6269 return build_pointer_type (char_type_node);
6271 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6272 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6274 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6275 unsigned_char_type_node);
6276 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6277 unsigned_char_type_node);
6278 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6280 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6281 short_unsigned_type_node);
6282 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6284 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6287 va_list_gpr_counter_field = f_gpr;
6288 va_list_fpr_counter_field = f_fpr;
6290 DECL_FIELD_CONTEXT (f_gpr) = record;
6291 DECL_FIELD_CONTEXT (f_fpr) = record;
6292 DECL_FIELD_CONTEXT (f_res) = record;
6293 DECL_FIELD_CONTEXT (f_ovf) = record;
6294 DECL_FIELD_CONTEXT (f_sav) = record;
6296 TREE_CHAIN (record) = type_decl;
6297 TYPE_NAME (record) = type_decl;
6298 TYPE_FIELDS (record) = f_gpr;
6299 TREE_CHAIN (f_gpr) = f_fpr;
6300 TREE_CHAIN (f_fpr) = f_res;
6301 TREE_CHAIN (f_res) = f_ovf;
6302 TREE_CHAIN (f_ovf) = f_sav;
6304 layout_type (record);
6306 /* The correct type is an array type of one element. */
6307 return build_array_type (record, build_index_type (size_zero_node));
6310 /* Implement va_start. */
6313 rs6000_va_start (tree valist, rtx nextarg)
6315 HOST_WIDE_INT words, n_gpr, n_fpr;
6316 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6317 tree gpr, fpr, ovf, sav, t;
6319 /* Only SVR4 needs something special. */
6320 if (DEFAULT_ABI != ABI_V4)
6322 std_expand_builtin_va_start (valist, nextarg);
6326 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6327 f_fpr = TREE_CHAIN (f_gpr);
6328 f_res = TREE_CHAIN (f_fpr);
6329 f_ovf = TREE_CHAIN (f_res);
6330 f_sav = TREE_CHAIN (f_ovf);
6332 valist = build_va_arg_indirect_ref (valist);
6333 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6334 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6335 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6336 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6338 /* Count number of gp and fp argument registers used. */
6339 words = current_function_args_info.words;
6340 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6342 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6345 if (TARGET_DEBUG_ARG)
6346 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6347 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6348 words, n_gpr, n_fpr);
6350 if (cfun->va_list_gpr_size)
6352 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6353 build_int_cst (NULL_TREE, n_gpr));
6354 TREE_SIDE_EFFECTS (t) = 1;
6355 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6358 if (cfun->va_list_fpr_size)
6360 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6361 build_int_cst (NULL_TREE, n_fpr));
6362 TREE_SIDE_EFFECTS (t) = 1;
6363 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6366 /* Find the overflow area. */
6367 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6369 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6370 size_int (words * UNITS_PER_WORD));
6371 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6372 TREE_SIDE_EFFECTS (t) = 1;
6373 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6375 /* If there were no va_arg invocations, don't set up the register
6377 if (!cfun->va_list_gpr_size
6378 && !cfun->va_list_fpr_size
6379 && n_gpr < GP_ARG_NUM_REG
6380 && n_fpr < FP_ARG_V4_MAX_REG)
6383 /* Find the register save area. */
6384 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6385 if (cfun->machine->varargs_save_offset)
6386 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6387 size_int (cfun->machine->varargs_save_offset));
6388 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6389 TREE_SIDE_EFFECTS (t) = 1;
6390 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6393 /* Implement va_arg. */
6396 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6398 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6399 tree gpr, fpr, ovf, sav, reg, t, u;
6400 int size, rsize, n_reg, sav_ofs, sav_scale;
6401 tree lab_false, lab_over, addr;
6403 tree ptrtype = build_pointer_type (type);
6406 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6408 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6409 return build_va_arg_indirect_ref (t);
6412 if (DEFAULT_ABI != ABI_V4)
6414 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6416 tree elem_type = TREE_TYPE (type);
6417 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6418 int elem_size = GET_MODE_SIZE (elem_mode);
6420 if (elem_size < UNITS_PER_WORD)
6422 tree real_part, imag_part;
6423 tree post = NULL_TREE;
6425 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6427 /* Copy the value into a temporary, lest the formal temporary
6428 be reused out from under us. */
6429 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6430 append_to_statement_list (post, pre_p);
6432 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6435 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6439 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6442 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6443 f_fpr = TREE_CHAIN (f_gpr);
6444 f_res = TREE_CHAIN (f_fpr);
6445 f_ovf = TREE_CHAIN (f_res);
6446 f_sav = TREE_CHAIN (f_ovf);
6448 valist = build_va_arg_indirect_ref (valist);
6449 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6450 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6451 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6452 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6454 size = int_size_in_bytes (type);
6455 rsize = (size + 3) / 4;
6458 if (TARGET_HARD_FLOAT && TARGET_FPRS
6459 && (TYPE_MODE (type) == SFmode
6460 || TYPE_MODE (type) == DFmode
6461 || TYPE_MODE (type) == TFmode
6462 || TYPE_MODE (type) == DDmode
6463 || TYPE_MODE (type) == TDmode))
6465 /* FP args go in FP registers, if present. */
6467 n_reg = (size + 7) / 8;
6470 if (TYPE_MODE (type) != SFmode)
6475 /* Otherwise into GP registers. */
6484 /* Pull the value out of the saved registers.... */
6487 addr = create_tmp_var (ptr_type_node, "addr");
6488 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6490 /* AltiVec vectors never go in registers when -mabi=altivec. */
6491 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6495 lab_false = create_artificial_label ();
6496 lab_over = create_artificial_label ();
6498 /* Long long and SPE vectors are aligned in the registers.
6499 As are any other 2 gpr item such as complex int due to a
6500 historical mistake. */
6502 if (n_reg == 2 && reg == gpr)
6505 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6506 build_int_cst (TREE_TYPE (reg), n_reg - 1));
6507 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6509 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6510 reg number is 0 for f1, so we want to make it odd. */
6511 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6514 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg, size_int (1));
6515 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6518 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6519 t = build2 (GE_EXPR, boolean_type_node, u, t);
6520 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6521 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6522 gimplify_and_add (t, pre_p);
6526 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6528 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
6529 build_int_cst (TREE_TYPE (reg), n_reg));
6530 u = fold_convert (sizetype, u);
6531 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
6532 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
6534 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6535 gimplify_and_add (t, pre_p);
6537 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6538 gimplify_and_add (t, pre_p);
6540 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6541 append_to_statement_list (t, pre_p);
6543 if ((n_reg == 2 && !regalign) || n_reg > 2)
6545 /* Ensure that we don't find any more args in regs.
6546 Alignment has taken care of for special cases. */
6547 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6548 gimplify_and_add (t, pre_p);
6552 /* ... otherwise out of the overflow area. */
6554 /* Care for on-stack alignment if needed. */
6558 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6559 t = fold_convert (sizetype, t);
6560 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6562 t = fold_convert (TREE_TYPE (ovf), t);
6564 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6566 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6567 gimplify_and_add (u, pre_p);
6569 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6570 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6571 gimplify_and_add (t, pre_p);
6575 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6576 append_to_statement_list (t, pre_p);
6579 if (STRICT_ALIGNMENT
6580 && (TYPE_ALIGN (type)
6581 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6583 /* The value (of type complex double, for example) may not be
6584 aligned in memory in the saved registers, so copy via a
6585 temporary. (This is the same code as used for SPARC.) */
6586 tree tmp = create_tmp_var (type, "va_arg_tmp");
6587 tree dest_addr = build_fold_addr_expr (tmp);
6589 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6590 3, dest_addr, addr, size_int (rsize * 4));
6592 gimplify_and_add (copy, pre_p);
6596 addr = fold_convert (ptrtype, addr);
6597 return build_va_arg_indirect_ref (addr);
6603 def_builtin (int mask, const char *name, tree type, int code)
6605 if ((mask & target_flags) || TARGET_PAIRED_FLOAT)
6607 if (rs6000_builtin_decls[code])
6610 rs6000_builtin_decls[code] =
6611 add_builtin_function (name, type, code, BUILT_IN_MD,
6616 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6618 static const struct builtin_description bdesc_3arg[] =
6620 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6621 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6622 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6623 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6624 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6625 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6626 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6627 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6628 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6629 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6630 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6631 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6632 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6633 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6634 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6635 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6636 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6637 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6638 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6639 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6640 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6641 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6642 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6644 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6645 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6646 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6647 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6648 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6649 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6650 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6651 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6652 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6653 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6654 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6655 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6656 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6657 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6658 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6660 { 0, CODE_FOR_paired_msub, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB },
6661 { 0, CODE_FOR_paired_madd, "__builtin_paired_madd", PAIRED_BUILTIN_MADD },
6662 { 0, CODE_FOR_paired_madds0, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0 },
6663 { 0, CODE_FOR_paired_madds1, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1 },
6664 { 0, CODE_FOR_paired_nmsub, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB },
6665 { 0, CODE_FOR_paired_nmadd, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD },
6666 { 0, CODE_FOR_paired_sum0, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0 },
6667 { 0, CODE_FOR_paired_sum1, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1 },
6670 /* DST operations: void foo (void *, const int, const char). */
6672 static const struct builtin_description bdesc_dst[] =
6674 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6675 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6676 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6677 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6679 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6680 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6681 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6682 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6685 /* Simple binary operations: VECc = foo (VECa, VECb). */
6687 static struct builtin_description bdesc_2arg[] =
6689 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6690 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6691 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6692 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6693 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6694 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6695 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6696 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6697 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6698 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6699 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6700 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6701 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6702 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6703 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6704 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6705 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6706 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6707 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6708 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6709 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6710 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6711 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6712 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6713 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6714 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6715 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6716 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6717 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6718 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6719 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6720 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6721 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6722 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6723 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6724 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6725 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6726 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6727 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6728 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6729 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6730 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6731 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6732 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6733 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6734 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6735 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6736 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6737 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6738 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6739 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6740 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6741 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6742 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6743 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6744 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6745 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6746 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6747 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6748 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6749 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6750 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6751 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6752 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6753 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6754 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6755 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6756 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6757 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6758 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6759 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6760 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6761 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6762 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6763 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6764 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6765 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6766 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6767 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6768 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6769 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6770 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6771 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6772 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6773 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6774 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6775 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6776 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6777 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6778 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6779 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6780 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6781 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6782 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6783 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6784 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6785 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6786 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6787 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6788 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6789 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6790 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6791 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6792 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6793 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6794 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6795 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6796 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6797 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6798 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6799 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6801 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6802 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6803 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6804 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6805 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6806 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6807 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6808 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6809 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6810 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6811 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6812 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6813 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6814 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6815 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6816 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6817 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6818 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6819 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6820 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6821 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6822 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6823 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6824 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6825 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6826 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6827 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6828 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6829 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6830 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6831 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6832 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6833 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6834 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6835 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6836 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6837 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6838 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6839 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6840 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6841 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6842 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6843 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6844 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6845 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6846 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6847 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6848 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6849 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6850 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6851 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6852 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6853 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6854 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6855 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6856 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6857 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6858 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6859 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6860 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6861 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6862 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6863 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6864 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6865 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6866 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6867 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6868 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6869 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6870 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6871 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6872 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6873 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6874 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6875 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6876 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6877 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6878 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6879 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6880 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6881 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6882 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6883 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6884 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6885 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6886 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6887 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6888 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6889 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6890 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6891 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6892 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6893 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6894 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6895 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6896 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6897 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6898 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6899 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6900 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6901 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6902 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6903 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6904 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6905 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6906 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6907 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6908 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6909 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6910 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6911 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6912 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6913 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6914 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6915 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6916 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6917 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6918 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6919 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6920 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6921 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6922 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6923 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6924 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6925 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6926 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6927 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6929 { 0, CODE_FOR_divv2sf3, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3 },
6930 { 0, CODE_FOR_addv2sf3, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3 },
6931 { 0, CODE_FOR_subv2sf3, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3 },
6932 { 0, CODE_FOR_mulv2sf3, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3 },
6933 { 0, CODE_FOR_paired_muls0, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0 },
6934 { 0, CODE_FOR_paired_muls1, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1 },
6935 { 0, CODE_FOR_paired_merge00, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00 },
6936 { 0, CODE_FOR_paired_merge01, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01 },
6937 { 0, CODE_FOR_paired_merge10, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10 },
6938 { 0, CODE_FOR_paired_merge11, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11 },
6940 /* Place holder, leave as first spe builtin. */
6941 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6942 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6943 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6944 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6945 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6946 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6947 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6948 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6949 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6950 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6951 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6952 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6953 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6954 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6955 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6956 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6957 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6958 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6959 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6960 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6961 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6962 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6963 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6964 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6965 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6966 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6967 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6968 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6969 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6970 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6971 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6972 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6973 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6974 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6975 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6976 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6977 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6978 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6979 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6980 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6981 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6982 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6983 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6984 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6985 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6986 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6987 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6988 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6989 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6990 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6991 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6992 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6993 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6994 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6995 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6996 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6997 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6998 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6999 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
7000 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
7001 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
7002 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
7003 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
7004 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
7005 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
7006 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
7007 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
7008 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
7009 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
7010 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
7011 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
7012 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
7013 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
7014 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
7015 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
7016 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
7017 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
7018 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
7019 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
7020 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
7021 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
7022 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
7023 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
7024 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
7025 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
7026 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
7027 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
7028 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
7029 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
7030 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
7031 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
7032 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
7033 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
7034 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
7035 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
7036 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
7037 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
7038 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
7039 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
7040 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
7041 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
7042 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
7043 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
7044 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
7045 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
7046 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
7047 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
7048 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
7049 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
7051 /* SPE binary operations expecting a 5-bit unsigned literal. */
7052 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
7054 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
7055 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
7056 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
7057 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
7058 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
7059 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
7060 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
7061 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
7062 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
7063 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
7064 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
7065 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
7066 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
7067 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
7068 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
7069 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
7070 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
7071 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
7072 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
7073 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
7074 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
7075 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
7076 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
7077 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
7078 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
7079 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
7081 /* Place-holder. Leave as last binary SPE builtin. */
7082 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
7085 /* AltiVec predicates. */
7087 struct builtin_description_predicates
7089 const unsigned int mask;
7090 const enum insn_code icode;
7092 const char *const name;
7093 const enum rs6000_builtins code;
7096 static const struct builtin_description_predicates bdesc_altivec_preds[] =
7098 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
7099 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
7100 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
7101 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
7102 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
7103 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
7104 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
7105 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
7106 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
7107 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
7108 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
7109 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
7110 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
7112 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
7113 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
7114 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
7117 /* SPE predicates. */
7118 static struct builtin_description bdesc_spe_predicates[] =
7120 /* Place-holder. Leave as first. */
7121 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
7122 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
7123 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
7124 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
7125 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
7126 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
7127 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
7128 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
7129 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
7130 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
7131 /* Place-holder. Leave as last. */
7132 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
7135 /* SPE evsel predicates. */
7136 static struct builtin_description bdesc_spe_evsel[] =
7138 /* Place-holder. Leave as first. */
7139 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
7140 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
7141 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
7142 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
7143 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
7144 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
7145 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
7146 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
7147 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
7148 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
7149 /* Place-holder. Leave as last. */
7150 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
7153 /* PAIRED predicates. */
7154 static const struct builtin_description bdesc_paired_preds[] =
7156 /* Place-holder. Leave as first. */
7157 { 0, CODE_FOR_paired_cmpu0, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0 },
7158 /* Place-holder. Leave as last. */
7159 { 0, CODE_FOR_paired_cmpu1, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1 },
7162 /* ABS* operations. */
7164 static const struct builtin_description bdesc_abs[] =
7166 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
7167 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
7168 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
7169 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
7170 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
7171 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
7172 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
7175 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7178 static struct builtin_description bdesc_1arg[] =
7180 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7181 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7182 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7183 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7184 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7185 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7186 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7187 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7188 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7189 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7190 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7191 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7192 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7193 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7194 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7195 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7196 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7218 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7219 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7220 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7221 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7222 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7223 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7224 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7225 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7226 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7227 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7228 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7229 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7230 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7231 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7232 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7233 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7234 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7235 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7236 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7237 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7238 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7239 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7240 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7241 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7242 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7243 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7244 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7245 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7246 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7247 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7249 /* Place-holder. Leave as last unary SPE builtin. */
7250 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
7252 { 0, CODE_FOR_absv2sf2, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2 },
7253 { 0, CODE_FOR_nabsv2sf2, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2 },
7254 { 0, CODE_FOR_negv2sf2, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2 },
7255 { 0, CODE_FOR_sqrtv2sf2, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2 },
7256 { 0, CODE_FOR_resv2sf2, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2 }
7260 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7263 tree arg0 = CALL_EXPR_ARG (exp, 0);
7264 rtx op0 = expand_normal (arg0);
7265 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7266 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7268 if (icode == CODE_FOR_nothing)
7269 /* Builtin not supported on this processor. */
7272 /* If we got invalid arguments bail out before generating bad rtl. */
7273 if (arg0 == error_mark_node)
7276 if (icode == CODE_FOR_altivec_vspltisb
7277 || icode == CODE_FOR_altivec_vspltish
7278 || icode == CODE_FOR_altivec_vspltisw
7279 || icode == CODE_FOR_spe_evsplatfi
7280 || icode == CODE_FOR_spe_evsplati)
7282 /* Only allow 5-bit *signed* literals. */
7283 if (GET_CODE (op0) != CONST_INT
7284 || INTVAL (op0) > 15
7285 || INTVAL (op0) < -16)
7287 error ("argument 1 must be a 5-bit signed literal");
7293 || GET_MODE (target) != tmode
7294 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7295 target = gen_reg_rtx (tmode);
7297 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7298 op0 = copy_to_mode_reg (mode0, op0);
7300 pat = GEN_FCN (icode) (target, op0);
7309 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7311 rtx pat, scratch1, scratch2;
7312 tree arg0 = CALL_EXPR_ARG (exp, 0);
7313 rtx op0 = expand_normal (arg0);
7314 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7315 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7317 /* If we have invalid arguments, bail out before generating bad rtl. */
7318 if (arg0 == error_mark_node)
7322 || GET_MODE (target) != tmode
7323 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7324 target = gen_reg_rtx (tmode);
7326 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7327 op0 = copy_to_mode_reg (mode0, op0);
7329 scratch1 = gen_reg_rtx (mode0);
7330 scratch2 = gen_reg_rtx (mode0);
7332 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7341 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7344 tree arg0 = CALL_EXPR_ARG (exp, 0);
7345 tree arg1 = CALL_EXPR_ARG (exp, 1);
7346 rtx op0 = expand_normal (arg0);
7347 rtx op1 = expand_normal (arg1);
7348 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7349 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7350 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7352 if (icode == CODE_FOR_nothing)
7353 /* Builtin not supported on this processor. */
7356 /* If we got invalid arguments bail out before generating bad rtl. */
7357 if (arg0 == error_mark_node || arg1 == error_mark_node)
7360 if (icode == CODE_FOR_altivec_vcfux
7361 || icode == CODE_FOR_altivec_vcfsx
7362 || icode == CODE_FOR_altivec_vctsxs
7363 || icode == CODE_FOR_altivec_vctuxs
7364 || icode == CODE_FOR_altivec_vspltb
7365 || icode == CODE_FOR_altivec_vsplth
7366 || icode == CODE_FOR_altivec_vspltw
7367 || icode == CODE_FOR_spe_evaddiw
7368 || icode == CODE_FOR_spe_evldd
7369 || icode == CODE_FOR_spe_evldh
7370 || icode == CODE_FOR_spe_evldw
7371 || icode == CODE_FOR_spe_evlhhesplat
7372 || icode == CODE_FOR_spe_evlhhossplat
7373 || icode == CODE_FOR_spe_evlhhousplat
7374 || icode == CODE_FOR_spe_evlwhe
7375 || icode == CODE_FOR_spe_evlwhos
7376 || icode == CODE_FOR_spe_evlwhou
7377 || icode == CODE_FOR_spe_evlwhsplat
7378 || icode == CODE_FOR_spe_evlwwsplat
7379 || icode == CODE_FOR_spe_evrlwi
7380 || icode == CODE_FOR_spe_evslwi
7381 || icode == CODE_FOR_spe_evsrwis
7382 || icode == CODE_FOR_spe_evsubifw
7383 || icode == CODE_FOR_spe_evsrwiu)
7385 /* Only allow 5-bit unsigned literals. */
7387 if (TREE_CODE (arg1) != INTEGER_CST
7388 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7390 error ("argument 2 must be a 5-bit unsigned literal");
7396 || GET_MODE (target) != tmode
7397 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7398 target = gen_reg_rtx (tmode);
7400 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7401 op0 = copy_to_mode_reg (mode0, op0);
7402 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7403 op1 = copy_to_mode_reg (mode1, op1);
7405 pat = GEN_FCN (icode) (target, op0, op1);
7414 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7415 tree exp, rtx target)
7418 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7419 tree arg0 = CALL_EXPR_ARG (exp, 1);
7420 tree arg1 = CALL_EXPR_ARG (exp, 2);
7421 rtx op0 = expand_normal (arg0);
7422 rtx op1 = expand_normal (arg1);
7423 enum machine_mode tmode = SImode;
7424 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7425 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7428 if (TREE_CODE (cr6_form) != INTEGER_CST)
7430 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7434 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7436 gcc_assert (mode0 == mode1);
7438 /* If we have invalid arguments, bail out before generating bad rtl. */
7439 if (arg0 == error_mark_node || arg1 == error_mark_node)
7443 || GET_MODE (target) != tmode
7444 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7445 target = gen_reg_rtx (tmode);
7447 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7448 op0 = copy_to_mode_reg (mode0, op0);
7449 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7450 op1 = copy_to_mode_reg (mode1, op1);
7452 scratch = gen_reg_rtx (mode0);
7454 pat = GEN_FCN (icode) (scratch, op0, op1,
7455 gen_rtx_SYMBOL_REF (Pmode, opcode));
7460 /* The vec_any* and vec_all* predicates use the same opcodes for two
7461 different operations, but the bits in CR6 will be different
7462 depending on what information we want. So we have to play tricks
7463 with CR6 to get the right bits out.
7465 If you think this is disgusting, look at the specs for the
7466 AltiVec predicates. */
7468 switch (cr6_form_int)
7471 emit_insn (gen_cr6_test_for_zero (target));
7474 emit_insn (gen_cr6_test_for_zero_reverse (target));
7477 emit_insn (gen_cr6_test_for_lt (target));
7480 emit_insn (gen_cr6_test_for_lt_reverse (target));
7483 error ("argument 1 of __builtin_altivec_predicate is out of range");
7491 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7494 tree arg0 = CALL_EXPR_ARG (exp, 0);
7495 tree arg1 = CALL_EXPR_ARG (exp, 1);
7496 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7497 enum machine_mode mode0 = Pmode;
7498 enum machine_mode mode1 = Pmode;
7499 rtx op0 = expand_normal (arg0);
7500 rtx op1 = expand_normal (arg1);
7502 if (icode == CODE_FOR_nothing)
7503 /* Builtin not supported on this processor. */
7506 /* If we got invalid arguments bail out before generating bad rtl. */
7507 if (arg0 == error_mark_node || arg1 == error_mark_node)
7511 || GET_MODE (target) != tmode
7512 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7513 target = gen_reg_rtx (tmode);
7515 op1 = copy_to_mode_reg (mode1, op1);
7517 if (op0 == const0_rtx)
7519 addr = gen_rtx_MEM (tmode, op1);
7523 op0 = copy_to_mode_reg (mode0, op0);
7524 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7527 pat = GEN_FCN (icode) (target, addr);
7537 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7540 tree arg0 = CALL_EXPR_ARG (exp, 0);
7541 tree arg1 = CALL_EXPR_ARG (exp, 1);
7542 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7543 enum machine_mode mode0 = Pmode;
7544 enum machine_mode mode1 = Pmode;
7545 rtx op0 = expand_normal (arg0);
7546 rtx op1 = expand_normal (arg1);
7548 if (icode == CODE_FOR_nothing)
7549 /* Builtin not supported on this processor. */
7552 /* If we got invalid arguments bail out before generating bad rtl. */
7553 if (arg0 == error_mark_node || arg1 == error_mark_node)
7557 || GET_MODE (target) != tmode
7558 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7559 target = gen_reg_rtx (tmode);
7561 op1 = copy_to_mode_reg (mode1, op1);
7563 if (op0 == const0_rtx)
7565 addr = gen_rtx_MEM (tmode, op1);
7569 op0 = copy_to_mode_reg (mode0, op0);
7570 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7573 pat = GEN_FCN (icode) (target, addr);
7583 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7585 tree arg0 = CALL_EXPR_ARG (exp, 0);
7586 tree arg1 = CALL_EXPR_ARG (exp, 1);
7587 tree arg2 = CALL_EXPR_ARG (exp, 2);
7588 rtx op0 = expand_normal (arg0);
7589 rtx op1 = expand_normal (arg1);
7590 rtx op2 = expand_normal (arg2);
7592 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7593 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7594 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7596 /* Invalid arguments. Bail before doing anything stoopid! */
7597 if (arg0 == error_mark_node
7598 || arg1 == error_mark_node
7599 || arg2 == error_mark_node)
7602 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7603 op0 = copy_to_mode_reg (mode2, op0);
7604 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7605 op1 = copy_to_mode_reg (mode0, op1);
7606 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7607 op2 = copy_to_mode_reg (mode1, op2);
7609 pat = GEN_FCN (icode) (op1, op2, op0);
7616 paired_expand_stv_builtin (enum insn_code icode, tree exp)
7618 tree arg0 = CALL_EXPR_ARG (exp, 0);
7619 tree arg1 = CALL_EXPR_ARG (exp, 1);
7620 tree arg2 = CALL_EXPR_ARG (exp, 2);
7621 rtx op0 = expand_normal (arg0);
7622 rtx op1 = expand_normal (arg1);
7623 rtx op2 = expand_normal (arg2);
7625 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7626 enum machine_mode mode1 = Pmode;
7627 enum machine_mode mode2 = Pmode;
7629 /* Invalid arguments. Bail before doing anything stoopid! */
7630 if (arg0 == error_mark_node
7631 || arg1 == error_mark_node
7632 || arg2 == error_mark_node)
7635 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7636 op0 = copy_to_mode_reg (tmode, op0);
7638 op2 = copy_to_mode_reg (mode2, op2);
7640 if (op1 == const0_rtx)
7642 addr = gen_rtx_MEM (tmode, op2);
7646 op1 = copy_to_mode_reg (mode1, op1);
7647 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7650 pat = GEN_FCN (icode) (addr, op0);
7657 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7659 tree arg0 = CALL_EXPR_ARG (exp, 0);
7660 tree arg1 = CALL_EXPR_ARG (exp, 1);
7661 tree arg2 = CALL_EXPR_ARG (exp, 2);
7662 rtx op0 = expand_normal (arg0);
7663 rtx op1 = expand_normal (arg1);
7664 rtx op2 = expand_normal (arg2);
7666 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7667 enum machine_mode mode1 = Pmode;
7668 enum machine_mode mode2 = Pmode;
7670 /* Invalid arguments. Bail before doing anything stoopid! */
7671 if (arg0 == error_mark_node
7672 || arg1 == error_mark_node
7673 || arg2 == error_mark_node)
7676 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7677 op0 = copy_to_mode_reg (tmode, op0);
7679 op2 = copy_to_mode_reg (mode2, op2);
7681 if (op1 == const0_rtx)
7683 addr = gen_rtx_MEM (tmode, op2);
7687 op1 = copy_to_mode_reg (mode1, op1);
7688 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7691 pat = GEN_FCN (icode) (addr, op0);
7698 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
7701 tree arg0 = CALL_EXPR_ARG (exp, 0);
7702 tree arg1 = CALL_EXPR_ARG (exp, 1);
7703 tree arg2 = CALL_EXPR_ARG (exp, 2);
7704 rtx op0 = expand_normal (arg0);
7705 rtx op1 = expand_normal (arg1);
7706 rtx op2 = expand_normal (arg2);
7707 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7708 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7709 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7710 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7712 if (icode == CODE_FOR_nothing)
7713 /* Builtin not supported on this processor. */
7716 /* If we got invalid arguments bail out before generating bad rtl. */
7717 if (arg0 == error_mark_node
7718 || arg1 == error_mark_node
7719 || arg2 == error_mark_node)
7722 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7723 || icode == CODE_FOR_altivec_vsldoi_v4si
7724 || icode == CODE_FOR_altivec_vsldoi_v8hi
7725 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7727 /* Only allow 4-bit unsigned literals. */
7729 if (TREE_CODE (arg2) != INTEGER_CST
7730 || TREE_INT_CST_LOW (arg2) & ~0xf)
7732 error ("argument 3 must be a 4-bit unsigned literal");
7738 || GET_MODE (target) != tmode
7739 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7740 target = gen_reg_rtx (tmode);
7742 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7743 op0 = copy_to_mode_reg (mode0, op0);
7744 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7745 op1 = copy_to_mode_reg (mode1, op1);
7746 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7747 op2 = copy_to_mode_reg (mode2, op2);
7749 pat = GEN_FCN (icode) (target, op0, op1, op2);
7757 /* Expand the lvx builtins. */
7759 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7761 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7762 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7764 enum machine_mode tmode, mode0;
7766 enum insn_code icode;
7770 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7771 icode = CODE_FOR_altivec_lvx_v16qi;
7773 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7774 icode = CODE_FOR_altivec_lvx_v8hi;
7776 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7777 icode = CODE_FOR_altivec_lvx_v4si;
7779 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7780 icode = CODE_FOR_altivec_lvx_v4sf;
7789 arg0 = CALL_EXPR_ARG (exp, 0);
7790 op0 = expand_normal (arg0);
7791 tmode = insn_data[icode].operand[0].mode;
7792 mode0 = insn_data[icode].operand[1].mode;
7795 || GET_MODE (target) != tmode
7796 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7797 target = gen_reg_rtx (tmode);
7799 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7800 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7802 pat = GEN_FCN (icode) (target, op0);
7809 /* Expand the stvx builtins. */
7811 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7814 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7815 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7817 enum machine_mode mode0, mode1;
7819 enum insn_code icode;
7823 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7824 icode = CODE_FOR_altivec_stvx_v16qi;
7826 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7827 icode = CODE_FOR_altivec_stvx_v8hi;
7829 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7830 icode = CODE_FOR_altivec_stvx_v4si;
7832 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7833 icode = CODE_FOR_altivec_stvx_v4sf;
7840 arg0 = CALL_EXPR_ARG (exp, 0);
7841 arg1 = CALL_EXPR_ARG (exp, 1);
7842 op0 = expand_normal (arg0);
7843 op1 = expand_normal (arg1);
7844 mode0 = insn_data[icode].operand[0].mode;
7845 mode1 = insn_data[icode].operand[1].mode;
7847 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7848 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7849 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7850 op1 = copy_to_mode_reg (mode1, op1);
7852 pat = GEN_FCN (icode) (op0, op1);
7860 /* Expand the dst builtins. */
7862 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7865 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7866 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7867 tree arg0, arg1, arg2;
7868 enum machine_mode mode0, mode1, mode2;
7869 rtx pat, op0, op1, op2;
7870 const struct builtin_description *d;
7875 /* Handle DST variants. */
7877 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7878 if (d->code == fcode)
7880 arg0 = CALL_EXPR_ARG (exp, 0);
7881 arg1 = CALL_EXPR_ARG (exp, 1);
7882 arg2 = CALL_EXPR_ARG (exp, 2);
7883 op0 = expand_normal (arg0);
7884 op1 = expand_normal (arg1);
7885 op2 = expand_normal (arg2);
7886 mode0 = insn_data[d->icode].operand[0].mode;
7887 mode1 = insn_data[d->icode].operand[1].mode;
7888 mode2 = insn_data[d->icode].operand[2].mode;
7890 /* Invalid arguments, bail out before generating bad rtl. */
7891 if (arg0 == error_mark_node
7892 || arg1 == error_mark_node
7893 || arg2 == error_mark_node)
7898 if (TREE_CODE (arg2) != INTEGER_CST
7899 || TREE_INT_CST_LOW (arg2) & ~0x3)
7901 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7905 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7906 op0 = copy_to_mode_reg (Pmode, op0);
7907 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7908 op1 = copy_to_mode_reg (mode1, op1);
7910 pat = GEN_FCN (d->icode) (op0, op1, op2);
7920 /* Expand vec_init builtin. */
7922 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
7924 enum machine_mode tmode = TYPE_MODE (type);
7925 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7926 int i, n_elt = GET_MODE_NUNITS (tmode);
7927 rtvec v = rtvec_alloc (n_elt);
7929 gcc_assert (VECTOR_MODE_P (tmode));
7930 gcc_assert (n_elt == call_expr_nargs (exp));
7932 for (i = 0; i < n_elt; ++i)
7934 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
7935 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7938 if (!target || !register_operand (target, tmode))
7939 target = gen_reg_rtx (tmode);
7941 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7945 /* Return the integer constant in ARG. Constrain it to be in the range
7946 of the subparts of VEC_TYPE; issue an error if not. */
7949 get_element_number (tree vec_type, tree arg)
7951 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7953 if (!host_integerp (arg, 1)
7954 || (elt = tree_low_cst (arg, 1), elt > max))
7956 error ("selector must be an integer constant in the range 0..%wi", max);
7963 /* Expand vec_set builtin. */
7965 altivec_expand_vec_set_builtin (tree exp)
7967 enum machine_mode tmode, mode1;
7968 tree arg0, arg1, arg2;
7972 arg0 = CALL_EXPR_ARG (exp, 0);
7973 arg1 = CALL_EXPR_ARG (exp, 1);
7974 arg2 = CALL_EXPR_ARG (exp, 2);
7976 tmode = TYPE_MODE (TREE_TYPE (arg0));
7977 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7978 gcc_assert (VECTOR_MODE_P (tmode));
7980 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7981 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7982 elt = get_element_number (TREE_TYPE (arg0), arg2);
7984 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7985 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7987 op0 = force_reg (tmode, op0);
7988 op1 = force_reg (mode1, op1);
7990 rs6000_expand_vector_set (op0, op1, elt);
7995 /* Expand vec_ext builtin. */
7997 altivec_expand_vec_ext_builtin (tree exp, rtx target)
7999 enum machine_mode tmode, mode0;
8004 arg0 = CALL_EXPR_ARG (exp, 0);
8005 arg1 = CALL_EXPR_ARG (exp, 1);
8007 op0 = expand_normal (arg0);
8008 elt = get_element_number (TREE_TYPE (arg0), arg1);
8010 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
8011 mode0 = TYPE_MODE (TREE_TYPE (arg0));
8012 gcc_assert (VECTOR_MODE_P (mode0));
8014 op0 = force_reg (mode0, op0);
8016 if (optimize || !target || !register_operand (target, tmode))
8017 target = gen_reg_rtx (tmode);
8019 rs6000_expand_vector_extract (target, op0, elt);
8024 /* Expand the builtin in EXP and store the result in TARGET. Store
8025 true in *EXPANDEDP if we found a builtin to expand. */
8027 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
8029 const struct builtin_description *d;
8030 const struct builtin_description_predicates *dp;
8032 enum insn_code icode;
8033 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8036 enum machine_mode tmode, mode0;
8037 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8039 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8040 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
8043 error ("unresolved overload for Altivec builtin %qF", fndecl);
8047 target = altivec_expand_ld_builtin (exp, target, expandedp);
8051 target = altivec_expand_st_builtin (exp, target, expandedp);
8055 target = altivec_expand_dst_builtin (exp, target, expandedp);
8063 case ALTIVEC_BUILTIN_STVX:
8064 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
8065 case ALTIVEC_BUILTIN_STVEBX:
8066 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
8067 case ALTIVEC_BUILTIN_STVEHX:
8068 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
8069 case ALTIVEC_BUILTIN_STVEWX:
8070 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
8071 case ALTIVEC_BUILTIN_STVXL:
8072 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
8074 case ALTIVEC_BUILTIN_MFVSCR:
8075 icode = CODE_FOR_altivec_mfvscr;
8076 tmode = insn_data[icode].operand[0].mode;
8079 || GET_MODE (target) != tmode
8080 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8081 target = gen_reg_rtx (tmode);
8083 pat = GEN_FCN (icode) (target);
8089 case ALTIVEC_BUILTIN_MTVSCR:
8090 icode = CODE_FOR_altivec_mtvscr;
8091 arg0 = CALL_EXPR_ARG (exp, 0);
8092 op0 = expand_normal (arg0);
8093 mode0 = insn_data[icode].operand[0].mode;
8095 /* If we got invalid arguments bail out before generating bad rtl. */
8096 if (arg0 == error_mark_node)
8099 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8100 op0 = copy_to_mode_reg (mode0, op0);
8102 pat = GEN_FCN (icode) (op0);
8107 case ALTIVEC_BUILTIN_DSSALL:
8108 emit_insn (gen_altivec_dssall ());
8111 case ALTIVEC_BUILTIN_DSS:
8112 icode = CODE_FOR_altivec_dss;
8113 arg0 = CALL_EXPR_ARG (exp, 0);
8115 op0 = expand_normal (arg0);
8116 mode0 = insn_data[icode].operand[0].mode;
8118 /* If we got invalid arguments bail out before generating bad rtl. */
8119 if (arg0 == error_mark_node)
8122 if (TREE_CODE (arg0) != INTEGER_CST
8123 || TREE_INT_CST_LOW (arg0) & ~0x3)
8125 error ("argument to dss must be a 2-bit unsigned literal");
8129 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8130 op0 = copy_to_mode_reg (mode0, op0);
8132 emit_insn (gen_altivec_dss (op0));
8135 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
8136 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
8137 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
8138 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
8139 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
8141 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
8142 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
8143 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
8144 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
8145 return altivec_expand_vec_set_builtin (exp);
8147 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
8148 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
8149 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
8150 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
8151 return altivec_expand_vec_ext_builtin (exp, target);
8158 /* Expand abs* operations. */
8160 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8161 if (d->code == fcode)
8162 return altivec_expand_abs_builtin (d->icode, exp, target);
8164 /* Expand the AltiVec predicates. */
8165 dp = bdesc_altivec_preds;
8166 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8167 if (dp->code == fcode)
8168 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
8171 /* LV* are funky. We initialized them differently. */
8174 case ALTIVEC_BUILTIN_LVSL:
8175 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
8177 case ALTIVEC_BUILTIN_LVSR:
8178 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
8180 case ALTIVEC_BUILTIN_LVEBX:
8181 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
8183 case ALTIVEC_BUILTIN_LVEHX:
8184 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
8186 case ALTIVEC_BUILTIN_LVEWX:
8187 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
8189 case ALTIVEC_BUILTIN_LVXL:
8190 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
8192 case ALTIVEC_BUILTIN_LVX:
8193 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
8204 /* Expand the builtin in EXP and store the result in TARGET. Store
8205 true in *EXPANDEDP if we found a builtin to expand. */
8207 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
8209 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8210 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8211 struct builtin_description *d;
8218 case PAIRED_BUILTIN_STX:
8219 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
8220 case PAIRED_BUILTIN_LX:
8221 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
8227 /* Expand the paired predicates. */
8228 d = (struct builtin_description *) bdesc_paired_preds;
8229 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
8230 if (d->code == fcode)
8231 return paired_expand_predicate_builtin (d->icode, exp, target);
8237 /* Binops that need to be initialized manually, but can be expanded
8238 automagically by rs6000_expand_binop_builtin. */
8239 static struct builtin_description bdesc_2arg_spe[] =
8241 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
8242 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
8243 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
8244 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
8245 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
8246 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
8247 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
8248 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
8249 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
8250 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
8251 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
8252 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
8253 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
8254 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
8255 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
8256 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
8257 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
8258 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
8259 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
8260 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
8261 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
8262 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
8265 /* Expand the builtin in EXP and store the result in TARGET. Store
8266 true in *EXPANDEDP if we found a builtin to expand.
8268 This expands the SPE builtins that are not simple unary and binary
8271 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
8273 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8275 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8276 enum insn_code icode;
8277 enum machine_mode tmode, mode0;
8279 struct builtin_description *d;
8284 /* Syntax check for a 5-bit unsigned immediate. */
8287 case SPE_BUILTIN_EVSTDD:
8288 case SPE_BUILTIN_EVSTDH:
8289 case SPE_BUILTIN_EVSTDW:
8290 case SPE_BUILTIN_EVSTWHE:
8291 case SPE_BUILTIN_EVSTWHO:
8292 case SPE_BUILTIN_EVSTWWE:
8293 case SPE_BUILTIN_EVSTWWO:
8294 arg1 = CALL_EXPR_ARG (exp, 2);
8295 if (TREE_CODE (arg1) != INTEGER_CST
8296 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8298 error ("argument 2 must be a 5-bit unsigned literal");
8306 /* The evsplat*i instructions are not quite generic. */
8309 case SPE_BUILTIN_EVSPLATFI:
8310 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8312 case SPE_BUILTIN_EVSPLATI:
8313 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8319 d = (struct builtin_description *) bdesc_2arg_spe;
8320 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8321 if (d->code == fcode)
8322 return rs6000_expand_binop_builtin (d->icode, exp, target);
8324 d = (struct builtin_description *) bdesc_spe_predicates;
8325 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8326 if (d->code == fcode)
8327 return spe_expand_predicate_builtin (d->icode, exp, target);
8329 d = (struct builtin_description *) bdesc_spe_evsel;
8330 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8331 if (d->code == fcode)
8332 return spe_expand_evsel_builtin (d->icode, exp, target);
8336 case SPE_BUILTIN_EVSTDDX:
8337 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8338 case SPE_BUILTIN_EVSTDHX:
8339 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8340 case SPE_BUILTIN_EVSTDWX:
8341 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8342 case SPE_BUILTIN_EVSTWHEX:
8343 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8344 case SPE_BUILTIN_EVSTWHOX:
8345 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8346 case SPE_BUILTIN_EVSTWWEX:
8347 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8348 case SPE_BUILTIN_EVSTWWOX:
8349 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8350 case SPE_BUILTIN_EVSTDD:
8351 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8352 case SPE_BUILTIN_EVSTDH:
8353 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8354 case SPE_BUILTIN_EVSTDW:
8355 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8356 case SPE_BUILTIN_EVSTWHE:
8357 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8358 case SPE_BUILTIN_EVSTWHO:
8359 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8360 case SPE_BUILTIN_EVSTWWE:
8361 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8362 case SPE_BUILTIN_EVSTWWO:
8363 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8364 case SPE_BUILTIN_MFSPEFSCR:
8365 icode = CODE_FOR_spe_mfspefscr;
8366 tmode = insn_data[icode].operand[0].mode;
8369 || GET_MODE (target) != tmode
8370 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8371 target = gen_reg_rtx (tmode);
8373 pat = GEN_FCN (icode) (target);
8378 case SPE_BUILTIN_MTSPEFSCR:
8379 icode = CODE_FOR_spe_mtspefscr;
8380 arg0 = CALL_EXPR_ARG (exp, 0);
8381 op0 = expand_normal (arg0);
8382 mode0 = insn_data[icode].operand[0].mode;
8384 if (arg0 == error_mark_node)
8387 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8388 op0 = copy_to_mode_reg (mode0, op0);
8390 pat = GEN_FCN (icode) (op0);
8403 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8405 rtx pat, scratch, tmp;
8406 tree form = CALL_EXPR_ARG (exp, 0);
8407 tree arg0 = CALL_EXPR_ARG (exp, 1);
8408 tree arg1 = CALL_EXPR_ARG (exp, 2);
8409 rtx op0 = expand_normal (arg0);
8410 rtx op1 = expand_normal (arg1);
8411 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8412 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8416 if (TREE_CODE (form) != INTEGER_CST)
8418 error ("argument 1 of __builtin_paired_predicate must be a constant");
8422 form_int = TREE_INT_CST_LOW (form);
8424 gcc_assert (mode0 == mode1);
8426 if (arg0 == error_mark_node || arg1 == error_mark_node)
8430 || GET_MODE (target) != SImode
8431 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
8432 target = gen_reg_rtx (SImode);
8433 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
8434 op0 = copy_to_mode_reg (mode0, op0);
8435 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
8436 op1 = copy_to_mode_reg (mode1, op1);
8438 scratch = gen_reg_rtx (CCFPmode);
8440 pat = GEN_FCN (icode) (scratch, op0, op1);
8462 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8465 error ("argument 1 of __builtin_paired_predicate is out of range");
8469 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8470 emit_move_insn (target, tmp);
8475 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8477 rtx pat, scratch, tmp;
8478 tree form = CALL_EXPR_ARG (exp, 0);
8479 tree arg0 = CALL_EXPR_ARG (exp, 1);
8480 tree arg1 = CALL_EXPR_ARG (exp, 2);
8481 rtx op0 = expand_normal (arg0);
8482 rtx op1 = expand_normal (arg1);
8483 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8484 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8488 if (TREE_CODE (form) != INTEGER_CST)
8490 error ("argument 1 of __builtin_spe_predicate must be a constant");
8494 form_int = TREE_INT_CST_LOW (form);
8496 gcc_assert (mode0 == mode1);
8498 if (arg0 == error_mark_node || arg1 == error_mark_node)
8502 || GET_MODE (target) != SImode
8503 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8504 target = gen_reg_rtx (SImode);
8506 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8507 op0 = copy_to_mode_reg (mode0, op0);
8508 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8509 op1 = copy_to_mode_reg (mode1, op1);
8511 scratch = gen_reg_rtx (CCmode);
8513 pat = GEN_FCN (icode) (scratch, op0, op1);
8518 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8519 _lower_. We use one compare, but look in different bits of the
8520 CR for each variant.
8522 There are 2 elements in each SPE simd type (upper/lower). The CR
8523 bits are set as follows:
8525 BIT0 | BIT 1 | BIT 2 | BIT 3
8526 U | L | (U | L) | (U & L)
8528 So, for an "all" relationship, BIT 3 would be set.
8529 For an "any" relationship, BIT 2 would be set. Etc.
8531 Following traditional nomenclature, these bits map to:
8533 BIT0 | BIT 1 | BIT 2 | BIT 3
8536 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8541 /* All variant. OV bit. */
8543 /* We need to get to the OV bit, which is the ORDERED bit. We
8544 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8545 that's ugly and will make validate_condition_mode die.
8546 So let's just use another pattern. */
8547 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8549 /* Any variant. EQ bit. */
8553 /* Upper variant. LT bit. */
8557 /* Lower variant. GT bit. */
8562 error ("argument 1 of __builtin_spe_predicate is out of range");
8566 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8567 emit_move_insn (target, tmp);
8572 /* The evsel builtins look like this:
8574 e = __builtin_spe_evsel_OP (a, b, c, d);
8578 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8579 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8583 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8586 tree arg0 = CALL_EXPR_ARG (exp, 0);
8587 tree arg1 = CALL_EXPR_ARG (exp, 1);
8588 tree arg2 = CALL_EXPR_ARG (exp, 2);
8589 tree arg3 = CALL_EXPR_ARG (exp, 3);
8590 rtx op0 = expand_normal (arg0);
8591 rtx op1 = expand_normal (arg1);
8592 rtx op2 = expand_normal (arg2);
8593 rtx op3 = expand_normal (arg3);
8594 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8595 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8597 gcc_assert (mode0 == mode1);
8599 if (arg0 == error_mark_node || arg1 == error_mark_node
8600 || arg2 == error_mark_node || arg3 == error_mark_node)
8604 || GET_MODE (target) != mode0
8605 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8606 target = gen_reg_rtx (mode0);
8608 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8609 op0 = copy_to_mode_reg (mode0, op0);
8610 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8611 op1 = copy_to_mode_reg (mode0, op1);
8612 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8613 op2 = copy_to_mode_reg (mode0, op2);
8614 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8615 op3 = copy_to_mode_reg (mode0, op3);
8617 /* Generate the compare. */
8618 scratch = gen_reg_rtx (CCmode);
8619 pat = GEN_FCN (icode) (scratch, op0, op1);
8624 if (mode0 == V2SImode)
8625 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8627 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8632 /* Expand an expression EXP that calls a built-in function,
8633 with result going to TARGET if that's convenient
8634 (and in mode MODE if that's convenient).
8635 SUBTARGET may be used as the target for computing one of EXP's operands.
8636 IGNORE is nonzero if the value is to be ignored. */
8639 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8640 enum machine_mode mode ATTRIBUTE_UNUSED,
8641 int ignore ATTRIBUTE_UNUSED)
8643 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8644 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8645 const struct builtin_description *d;
8650 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8651 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8653 int icode = (int) CODE_FOR_altivec_lvsr;
8654 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8655 enum machine_mode mode = insn_data[icode].operand[1].mode;
8659 gcc_assert (TARGET_ALTIVEC);
8661 arg = CALL_EXPR_ARG (exp, 0);
8662 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8663 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8664 addr = memory_address (mode, op);
8665 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8669 /* For the load case need to negate the address. */
8670 op = gen_reg_rtx (GET_MODE (addr));
8671 emit_insn (gen_rtx_SET (VOIDmode, op,
8672 gen_rtx_NEG (GET_MODE (addr), addr)));
8674 op = gen_rtx_MEM (mode, op);
8677 || GET_MODE (target) != tmode
8678 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8679 target = gen_reg_rtx (tmode);
8681 /*pat = gen_altivec_lvsr (target, op);*/
8682 pat = GEN_FCN (icode) (target, op);
8690 /* FIXME: There's got to be a nicer way to handle this case than
8691 constructing a new CALL_EXPR. */
8692 if (fcode == ALTIVEC_BUILTIN_VCFUX
8693 || fcode == ALTIVEC_BUILTIN_VCFSX)
8695 if (call_expr_nargs (exp) == 1)
8696 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
8697 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
8702 ret = altivec_expand_builtin (exp, target, &success);
8709 ret = spe_expand_builtin (exp, target, &success);
8714 if (TARGET_PAIRED_FLOAT)
8716 ret = paired_expand_builtin (exp, target, &success);
8722 gcc_assert (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT);
8724 /* Handle simple unary operations. */
8725 d = (struct builtin_description *) bdesc_1arg;
8726 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8727 if (d->code == fcode)
8728 return rs6000_expand_unop_builtin (d->icode, exp, target);
8730 /* Handle simple binary operations. */
8731 d = (struct builtin_description *) bdesc_2arg;
8732 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8733 if (d->code == fcode)
8734 return rs6000_expand_binop_builtin (d->icode, exp, target);
8736 /* Handle simple ternary operations. */
8738 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8739 if (d->code == fcode)
8740 return rs6000_expand_ternop_builtin (d->icode, exp, target);
8746 build_opaque_vector_type (tree node, int nunits)
8748 node = copy_node (node);
8749 TYPE_MAIN_VARIANT (node) = node;
8750 return build_vector_type (node, nunits);
8754 rs6000_init_builtins (void)
8756 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8757 V2SF_type_node = build_vector_type (float_type_node, 2);
8758 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8759 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8760 V4SF_type_node = build_vector_type (float_type_node, 4);
8761 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8762 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8764 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8765 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8766 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8768 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8769 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8770 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8771 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8773 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8774 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8775 'vector unsigned short'. */
8777 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8778 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8779 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8780 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8782 long_integer_type_internal_node = long_integer_type_node;
8783 long_unsigned_type_internal_node = long_unsigned_type_node;
8784 intQI_type_internal_node = intQI_type_node;
8785 uintQI_type_internal_node = unsigned_intQI_type_node;
8786 intHI_type_internal_node = intHI_type_node;
8787 uintHI_type_internal_node = unsigned_intHI_type_node;
8788 intSI_type_internal_node = intSI_type_node;
8789 uintSI_type_internal_node = unsigned_intSI_type_node;
8790 float_type_internal_node = float_type_node;
8791 void_type_internal_node = void_type_node;
8793 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8794 get_identifier ("__bool char"),
8795 bool_char_type_node));
8796 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8797 get_identifier ("__bool short"),
8798 bool_short_type_node));
8799 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8800 get_identifier ("__bool int"),
8801 bool_int_type_node));
8802 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8803 get_identifier ("__pixel"),
8806 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8807 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8808 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8809 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8811 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8812 get_identifier ("__vector unsigned char"),
8813 unsigned_V16QI_type_node));
8814 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8815 get_identifier ("__vector signed char"),
8817 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8818 get_identifier ("__vector __bool char"),
8819 bool_V16QI_type_node));
8821 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8822 get_identifier ("__vector unsigned short"),
8823 unsigned_V8HI_type_node));
8824 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8825 get_identifier ("__vector signed short"),
8827 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8828 get_identifier ("__vector __bool short"),
8829 bool_V8HI_type_node));
8831 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8832 get_identifier ("__vector unsigned int"),
8833 unsigned_V4SI_type_node));
8834 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8835 get_identifier ("__vector signed int"),
8837 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8838 get_identifier ("__vector __bool int"),
8839 bool_V4SI_type_node));
8841 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8842 get_identifier ("__vector float"),
8844 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8845 get_identifier ("__vector __pixel"),
8846 pixel_V8HI_type_node));
8848 if (TARGET_PAIRED_FLOAT)
8849 paired_init_builtins ();
8851 spe_init_builtins ();
8853 altivec_init_builtins ();
8854 if (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT)
8855 rs6000_common_init_builtins ();
8858 /* AIX libm provides clog as __clog. */
8859 if (built_in_decls [BUILT_IN_CLOG])
8860 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8864 /* Search through a set of builtins and enable the mask bits.
8865 DESC is an array of builtins.
8866 SIZE is the total number of builtins.
8867 START is the builtin enum at which to start.
8868 END is the builtin enum at which to end. */
8870 enable_mask_for_builtins (struct builtin_description *desc, int size,
8871 enum rs6000_builtins start,
8872 enum rs6000_builtins end)
8876 for (i = 0; i < size; ++i)
8877 if (desc[i].code == start)
8883 for (; i < size; ++i)
8885 /* Flip all the bits on. */
8886 desc[i].mask = target_flags;
8887 if (desc[i].code == end)
8893 spe_init_builtins (void)
8895 tree endlink = void_list_node;
8896 tree puint_type_node = build_pointer_type (unsigned_type_node);
8897 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8898 struct builtin_description *d;
8901 tree v2si_ftype_4_v2si
8902 = build_function_type
8903 (opaque_V2SI_type_node,
8904 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8905 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8906 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8907 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8910 tree v2sf_ftype_4_v2sf
8911 = build_function_type
8912 (opaque_V2SF_type_node,
8913 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8914 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8915 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8916 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8919 tree int_ftype_int_v2si_v2si
8920 = build_function_type
8922 tree_cons (NULL_TREE, integer_type_node,
8923 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8924 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8927 tree int_ftype_int_v2sf_v2sf
8928 = build_function_type
8930 tree_cons (NULL_TREE, integer_type_node,
8931 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8932 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8935 tree void_ftype_v2si_puint_int
8936 = build_function_type (void_type_node,
8937 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8938 tree_cons (NULL_TREE, puint_type_node,
8939 tree_cons (NULL_TREE,
8943 tree void_ftype_v2si_puint_char
8944 = build_function_type (void_type_node,
8945 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8946 tree_cons (NULL_TREE, puint_type_node,
8947 tree_cons (NULL_TREE,
8951 tree void_ftype_v2si_pv2si_int
8952 = build_function_type (void_type_node,
8953 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8954 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8955 tree_cons (NULL_TREE,
8959 tree void_ftype_v2si_pv2si_char
8960 = build_function_type (void_type_node,
8961 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8962 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8963 tree_cons (NULL_TREE,
8968 = build_function_type (void_type_node,
8969 tree_cons (NULL_TREE, integer_type_node, endlink));
8972 = build_function_type (integer_type_node, endlink);
8974 tree v2si_ftype_pv2si_int
8975 = build_function_type (opaque_V2SI_type_node,
8976 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8977 tree_cons (NULL_TREE, integer_type_node,
8980 tree v2si_ftype_puint_int
8981 = build_function_type (opaque_V2SI_type_node,
8982 tree_cons (NULL_TREE, puint_type_node,
8983 tree_cons (NULL_TREE, integer_type_node,
8986 tree v2si_ftype_pushort_int
8987 = build_function_type (opaque_V2SI_type_node,
8988 tree_cons (NULL_TREE, pushort_type_node,
8989 tree_cons (NULL_TREE, integer_type_node,
8992 tree v2si_ftype_signed_char
8993 = build_function_type (opaque_V2SI_type_node,
8994 tree_cons (NULL_TREE, signed_char_type_node,
8997 /* The initialization of the simple binary and unary builtins is
8998 done in rs6000_common_init_builtins, but we have to enable the
8999 mask bits here manually because we have run out of `target_flags'
9000 bits. We really need to redesign this mask business. */
9002 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
9003 ARRAY_SIZE (bdesc_2arg),
9006 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
9007 ARRAY_SIZE (bdesc_1arg),
9009 SPE_BUILTIN_EVSUBFUSIAAW);
9010 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
9011 ARRAY_SIZE (bdesc_spe_predicates),
9012 SPE_BUILTIN_EVCMPEQ,
9013 SPE_BUILTIN_EVFSTSTLT);
9014 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
9015 ARRAY_SIZE (bdesc_spe_evsel),
9016 SPE_BUILTIN_EVSEL_CMPGTS,
9017 SPE_BUILTIN_EVSEL_FSTSTEQ);
9019 (*lang_hooks.decls.pushdecl)
9020 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
9021 opaque_V2SI_type_node));
9023 /* Initialize irregular SPE builtins. */
9025 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
9026 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
9027 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
9028 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
9029 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
9030 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
9031 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
9032 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
9033 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
9034 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
9035 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
9036 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
9037 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
9038 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
9039 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
9040 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
9041 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
9042 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
9045 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
9046 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
9047 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
9048 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
9049 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
9050 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
9051 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
9052 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
9053 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
9054 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
9055 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
9056 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
9057 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
9058 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
9059 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
9060 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
9061 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
9062 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
9063 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
9064 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
9065 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
9066 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
9069 d = (struct builtin_description *) bdesc_spe_predicates;
9070 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
9074 switch (insn_data[d->icode].operand[1].mode)
9077 type = int_ftype_int_v2si_v2si;
9080 type = int_ftype_int_v2sf_v2sf;
9086 def_builtin (d->mask, d->name, type, d->code);
9089 /* Evsel predicates. */
9090 d = (struct builtin_description *) bdesc_spe_evsel;
9091 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
9095 switch (insn_data[d->icode].operand[1].mode)
9098 type = v2si_ftype_4_v2si;
9101 type = v2sf_ftype_4_v2sf;
9107 def_builtin (d->mask, d->name, type, d->code);
9112 paired_init_builtins (void)
9114 struct builtin_description *d;
9116 tree endlink = void_list_node;
9118 tree int_ftype_int_v2sf_v2sf
9119 = build_function_type
9121 tree_cons (NULL_TREE, integer_type_node,
9122 tree_cons (NULL_TREE, V2SF_type_node,
9123 tree_cons (NULL_TREE, V2SF_type_node,
9125 tree pcfloat_type_node =
9126 build_pointer_type (build_qualified_type
9127 (float_type_node, TYPE_QUAL_CONST));
9129 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
9130 long_integer_type_node,
9133 tree void_ftype_v2sf_long_pcfloat =
9134 build_function_type_list (void_type_node,
9136 long_integer_type_node,
9141 def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat,
9145 def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
9146 PAIRED_BUILTIN_STX);
9149 d = (struct builtin_description *) bdesc_paired_preds;
9150 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
9154 switch (insn_data[d->icode].operand[1].mode)
9157 type = int_ftype_int_v2sf_v2sf;
9163 def_builtin (d->mask, d->name, type, d->code);
9168 altivec_init_builtins (void)
9170 const struct builtin_description *d;
9171 const struct builtin_description_predicates *dp;
9175 tree pfloat_type_node = build_pointer_type (float_type_node);
9176 tree pint_type_node = build_pointer_type (integer_type_node);
9177 tree pshort_type_node = build_pointer_type (short_integer_type_node);
9178 tree pchar_type_node = build_pointer_type (char_type_node);
9180 tree pvoid_type_node = build_pointer_type (void_type_node);
9182 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
9183 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
9184 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
9185 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
9187 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
9189 tree int_ftype_opaque
9190 = build_function_type_list (integer_type_node,
9191 opaque_V4SI_type_node, NULL_TREE);
9193 tree opaque_ftype_opaque_int
9194 = build_function_type_list (opaque_V4SI_type_node,
9195 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
9196 tree opaque_ftype_opaque_opaque_int
9197 = build_function_type_list (opaque_V4SI_type_node,
9198 opaque_V4SI_type_node, opaque_V4SI_type_node,
9199 integer_type_node, NULL_TREE);
9200 tree int_ftype_int_opaque_opaque
9201 = build_function_type_list (integer_type_node,
9202 integer_type_node, opaque_V4SI_type_node,
9203 opaque_V4SI_type_node, NULL_TREE);
9204 tree int_ftype_int_v4si_v4si
9205 = build_function_type_list (integer_type_node,
9206 integer_type_node, V4SI_type_node,
9207 V4SI_type_node, NULL_TREE);
9208 tree v4sf_ftype_pcfloat
9209 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
9210 tree void_ftype_pfloat_v4sf
9211 = build_function_type_list (void_type_node,
9212 pfloat_type_node, V4SF_type_node, NULL_TREE);
9213 tree v4si_ftype_pcint
9214 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
9215 tree void_ftype_pint_v4si
9216 = build_function_type_list (void_type_node,
9217 pint_type_node, V4SI_type_node, NULL_TREE);
9218 tree v8hi_ftype_pcshort
9219 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
9220 tree void_ftype_pshort_v8hi
9221 = build_function_type_list (void_type_node,
9222 pshort_type_node, V8HI_type_node, NULL_TREE);
9223 tree v16qi_ftype_pcchar
9224 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
9225 tree void_ftype_pchar_v16qi
9226 = build_function_type_list (void_type_node,
9227 pchar_type_node, V16QI_type_node, NULL_TREE);
9228 tree void_ftype_v4si
9229 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
9230 tree v8hi_ftype_void
9231 = build_function_type (V8HI_type_node, void_list_node);
9232 tree void_ftype_void
9233 = build_function_type (void_type_node, void_list_node);
9235 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
9237 tree opaque_ftype_long_pcvoid
9238 = build_function_type_list (opaque_V4SI_type_node,
9239 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9240 tree v16qi_ftype_long_pcvoid
9241 = build_function_type_list (V16QI_type_node,
9242 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9243 tree v8hi_ftype_long_pcvoid
9244 = build_function_type_list (V8HI_type_node,
9245 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9246 tree v4si_ftype_long_pcvoid
9247 = build_function_type_list (V4SI_type_node,
9248 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9250 tree void_ftype_opaque_long_pvoid
9251 = build_function_type_list (void_type_node,
9252 opaque_V4SI_type_node, long_integer_type_node,
9253 pvoid_type_node, NULL_TREE);
9254 tree void_ftype_v4si_long_pvoid
9255 = build_function_type_list (void_type_node,
9256 V4SI_type_node, long_integer_type_node,
9257 pvoid_type_node, NULL_TREE);
9258 tree void_ftype_v16qi_long_pvoid
9259 = build_function_type_list (void_type_node,
9260 V16QI_type_node, long_integer_type_node,
9261 pvoid_type_node, NULL_TREE);
9262 tree void_ftype_v8hi_long_pvoid
9263 = build_function_type_list (void_type_node,
9264 V8HI_type_node, long_integer_type_node,
9265 pvoid_type_node, NULL_TREE);
9266 tree int_ftype_int_v8hi_v8hi
9267 = build_function_type_list (integer_type_node,
9268 integer_type_node, V8HI_type_node,
9269 V8HI_type_node, NULL_TREE);
9270 tree int_ftype_int_v16qi_v16qi
9271 = build_function_type_list (integer_type_node,
9272 integer_type_node, V16QI_type_node,
9273 V16QI_type_node, NULL_TREE);
9274 tree int_ftype_int_v4sf_v4sf
9275 = build_function_type_list (integer_type_node,
9276 integer_type_node, V4SF_type_node,
9277 V4SF_type_node, NULL_TREE);
9278 tree v4si_ftype_v4si
9279 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
9280 tree v8hi_ftype_v8hi
9281 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
9282 tree v16qi_ftype_v16qi
9283 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
9284 tree v4sf_ftype_v4sf
9285 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9286 tree void_ftype_pcvoid_int_int
9287 = build_function_type_list (void_type_node,
9288 pcvoid_type_node, integer_type_node,
9289 integer_type_node, NULL_TREE);
9291 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
9292 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
9293 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
9294 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
9295 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
9296 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
9297 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
9298 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
9299 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
9300 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
9301 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
9302 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
9303 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
9304 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
9305 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
9306 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
9307 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
9308 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
9309 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
9310 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
9311 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
9312 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
9313 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
9314 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
9315 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
9316 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
9317 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
9318 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
9319 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
9320 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
9321 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
9322 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
9323 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
9324 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
9325 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
9326 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
9327 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
9328 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
9329 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
9330 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
9331 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
9332 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
9333 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
9334 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
9335 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
9336 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
9338 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
9340 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
9341 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
9342 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
9343 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
9344 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
9345 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
9346 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
9347 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
9348 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
9349 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
9351 /* Add the DST variants. */
9353 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
9354 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
9356 /* Initialize the predicates. */
9357 dp = bdesc_altivec_preds;
9358 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
9360 enum machine_mode mode1;
9362 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9363 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9368 mode1 = insn_data[dp->icode].operand[1].mode;
9373 type = int_ftype_int_opaque_opaque;
9376 type = int_ftype_int_v4si_v4si;
9379 type = int_ftype_int_v8hi_v8hi;
9382 type = int_ftype_int_v16qi_v16qi;
9385 type = int_ftype_int_v4sf_v4sf;
9391 def_builtin (dp->mask, dp->name, type, dp->code);
9394 /* Initialize the abs* operators. */
9396 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
9398 enum machine_mode mode0;
9401 mode0 = insn_data[d->icode].operand[0].mode;
9406 type = v4si_ftype_v4si;
9409 type = v8hi_ftype_v8hi;
9412 type = v16qi_ftype_v16qi;
9415 type = v4sf_ftype_v4sf;
9421 def_builtin (d->mask, d->name, type, d->code);
9428 /* Initialize target builtin that implements
9429 targetm.vectorize.builtin_mask_for_load. */
9431 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
9432 v16qi_ftype_long_pcvoid,
9433 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
9434 BUILT_IN_MD, NULL, NULL_TREE);
9435 TREE_READONLY (decl) = 1;
9436 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9437 altivec_builtin_mask_for_load = decl;
9440 /* Access to the vec_init patterns. */
9441 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
9442 integer_type_node, integer_type_node,
9443 integer_type_node, NULL_TREE);
9444 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
9445 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
9447 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
9448 short_integer_type_node,
9449 short_integer_type_node,
9450 short_integer_type_node,
9451 short_integer_type_node,
9452 short_integer_type_node,
9453 short_integer_type_node,
9454 short_integer_type_node, NULL_TREE);
9455 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
9456 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
9458 ftype = build_function_type_list (V16QI_type_node, char_type_node,
9459 char_type_node, char_type_node,
9460 char_type_node, char_type_node,
9461 char_type_node, char_type_node,
9462 char_type_node, char_type_node,
9463 char_type_node, char_type_node,
9464 char_type_node, char_type_node,
9465 char_type_node, char_type_node,
9466 char_type_node, NULL_TREE);
9467 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9468 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9470 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9471 float_type_node, float_type_node,
9472 float_type_node, NULL_TREE);
9473 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9474 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9476 /* Access to the vec_set patterns. */
9477 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9479 integer_type_node, NULL_TREE);
9480 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9481 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9483 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9485 integer_type_node, NULL_TREE);
9486 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9487 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9489 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9491 integer_type_node, NULL_TREE);
9492 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9493 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9495 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9497 integer_type_node, NULL_TREE);
9498 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9499 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9501 /* Access to the vec_extract patterns. */
9502 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9503 integer_type_node, NULL_TREE);
9504 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9505 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9507 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9508 integer_type_node, NULL_TREE);
9509 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9510 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9512 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9513 integer_type_node, NULL_TREE);
9514 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9515 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9517 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9518 integer_type_node, NULL_TREE);
9519 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9520 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9524 rs6000_common_init_builtins (void)
9526 const struct builtin_description *d;
9529 tree v2sf_ftype_v2sf_v2sf_v2sf
9530 = build_function_type_list (V2SF_type_node,
9531 V2SF_type_node, V2SF_type_node,
9532 V2SF_type_node, NULL_TREE);
9534 tree v4sf_ftype_v4sf_v4sf_v16qi
9535 = build_function_type_list (V4SF_type_node,
9536 V4SF_type_node, V4SF_type_node,
9537 V16QI_type_node, NULL_TREE);
9538 tree v4si_ftype_v4si_v4si_v16qi
9539 = build_function_type_list (V4SI_type_node,
9540 V4SI_type_node, V4SI_type_node,
9541 V16QI_type_node, NULL_TREE);
9542 tree v8hi_ftype_v8hi_v8hi_v16qi
9543 = build_function_type_list (V8HI_type_node,
9544 V8HI_type_node, V8HI_type_node,
9545 V16QI_type_node, NULL_TREE);
9546 tree v16qi_ftype_v16qi_v16qi_v16qi
9547 = build_function_type_list (V16QI_type_node,
9548 V16QI_type_node, V16QI_type_node,
9549 V16QI_type_node, NULL_TREE);
9551 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9553 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9554 tree v16qi_ftype_int
9555 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9556 tree v8hi_ftype_v16qi
9557 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9558 tree v4sf_ftype_v4sf
9559 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9561 tree v2si_ftype_v2si_v2si
9562 = build_function_type_list (opaque_V2SI_type_node,
9563 opaque_V2SI_type_node,
9564 opaque_V2SI_type_node, NULL_TREE);
9566 tree v2sf_ftype_v2sf_v2sf_spe
9567 = build_function_type_list (opaque_V2SF_type_node,
9568 opaque_V2SF_type_node,
9569 opaque_V2SF_type_node, NULL_TREE);
9571 tree v2sf_ftype_v2sf_v2sf
9572 = build_function_type_list (V2SF_type_node,
9574 V2SF_type_node, NULL_TREE);
9577 tree v2si_ftype_int_int
9578 = build_function_type_list (opaque_V2SI_type_node,
9579 integer_type_node, integer_type_node,
9582 tree opaque_ftype_opaque
9583 = build_function_type_list (opaque_V4SI_type_node,
9584 opaque_V4SI_type_node, NULL_TREE);
9586 tree v2si_ftype_v2si
9587 = build_function_type_list (opaque_V2SI_type_node,
9588 opaque_V2SI_type_node, NULL_TREE);
9590 tree v2sf_ftype_v2sf_spe
9591 = build_function_type_list (opaque_V2SF_type_node,
9592 opaque_V2SF_type_node, NULL_TREE);
9594 tree v2sf_ftype_v2sf
9595 = build_function_type_list (V2SF_type_node,
9596 V2SF_type_node, NULL_TREE);
9598 tree v2sf_ftype_v2si
9599 = build_function_type_list (opaque_V2SF_type_node,
9600 opaque_V2SI_type_node, NULL_TREE);
9602 tree v2si_ftype_v2sf
9603 = build_function_type_list (opaque_V2SI_type_node,
9604 opaque_V2SF_type_node, NULL_TREE);
9606 tree v2si_ftype_v2si_char
9607 = build_function_type_list (opaque_V2SI_type_node,
9608 opaque_V2SI_type_node,
9609 char_type_node, NULL_TREE);
9611 tree v2si_ftype_int_char
9612 = build_function_type_list (opaque_V2SI_type_node,
9613 integer_type_node, char_type_node, NULL_TREE);
9615 tree v2si_ftype_char
9616 = build_function_type_list (opaque_V2SI_type_node,
9617 char_type_node, NULL_TREE);
9619 tree int_ftype_int_int
9620 = build_function_type_list (integer_type_node,
9621 integer_type_node, integer_type_node,
9624 tree opaque_ftype_opaque_opaque
9625 = build_function_type_list (opaque_V4SI_type_node,
9626 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9627 tree v4si_ftype_v4si_v4si
9628 = build_function_type_list (V4SI_type_node,
9629 V4SI_type_node, V4SI_type_node, NULL_TREE);
9630 tree v4sf_ftype_v4si_int
9631 = build_function_type_list (V4SF_type_node,
9632 V4SI_type_node, integer_type_node, NULL_TREE);
9633 tree v4si_ftype_v4sf_int
9634 = build_function_type_list (V4SI_type_node,
9635 V4SF_type_node, integer_type_node, NULL_TREE);
9636 tree v4si_ftype_v4si_int
9637 = build_function_type_list (V4SI_type_node,
9638 V4SI_type_node, integer_type_node, NULL_TREE);
9639 tree v8hi_ftype_v8hi_int
9640 = build_function_type_list (V8HI_type_node,
9641 V8HI_type_node, integer_type_node, NULL_TREE);
9642 tree v16qi_ftype_v16qi_int
9643 = build_function_type_list (V16QI_type_node,
9644 V16QI_type_node, integer_type_node, NULL_TREE);
9645 tree v16qi_ftype_v16qi_v16qi_int
9646 = build_function_type_list (V16QI_type_node,
9647 V16QI_type_node, V16QI_type_node,
9648 integer_type_node, NULL_TREE);
9649 tree v8hi_ftype_v8hi_v8hi_int
9650 = build_function_type_list (V8HI_type_node,
9651 V8HI_type_node, V8HI_type_node,
9652 integer_type_node, NULL_TREE);
9653 tree v4si_ftype_v4si_v4si_int
9654 = build_function_type_list (V4SI_type_node,
9655 V4SI_type_node, V4SI_type_node,
9656 integer_type_node, NULL_TREE);
9657 tree v4sf_ftype_v4sf_v4sf_int
9658 = build_function_type_list (V4SF_type_node,
9659 V4SF_type_node, V4SF_type_node,
9660 integer_type_node, NULL_TREE);
9661 tree v4sf_ftype_v4sf_v4sf
9662 = build_function_type_list (V4SF_type_node,
9663 V4SF_type_node, V4SF_type_node, NULL_TREE);
9664 tree opaque_ftype_opaque_opaque_opaque
9665 = build_function_type_list (opaque_V4SI_type_node,
9666 opaque_V4SI_type_node, opaque_V4SI_type_node,
9667 opaque_V4SI_type_node, NULL_TREE);
9668 tree v4sf_ftype_v4sf_v4sf_v4si
9669 = build_function_type_list (V4SF_type_node,
9670 V4SF_type_node, V4SF_type_node,
9671 V4SI_type_node, NULL_TREE);
9672 tree v4sf_ftype_v4sf_v4sf_v4sf
9673 = build_function_type_list (V4SF_type_node,
9674 V4SF_type_node, V4SF_type_node,
9675 V4SF_type_node, NULL_TREE);
9676 tree v4si_ftype_v4si_v4si_v4si
9677 = build_function_type_list (V4SI_type_node,
9678 V4SI_type_node, V4SI_type_node,
9679 V4SI_type_node, NULL_TREE);
9680 tree v8hi_ftype_v8hi_v8hi
9681 = build_function_type_list (V8HI_type_node,
9682 V8HI_type_node, V8HI_type_node, NULL_TREE);
9683 tree v8hi_ftype_v8hi_v8hi_v8hi
9684 = build_function_type_list (V8HI_type_node,
9685 V8HI_type_node, V8HI_type_node,
9686 V8HI_type_node, NULL_TREE);
9687 tree v4si_ftype_v8hi_v8hi_v4si
9688 = build_function_type_list (V4SI_type_node,
9689 V8HI_type_node, V8HI_type_node,
9690 V4SI_type_node, NULL_TREE);
9691 tree v4si_ftype_v16qi_v16qi_v4si
9692 = build_function_type_list (V4SI_type_node,
9693 V16QI_type_node, V16QI_type_node,
9694 V4SI_type_node, NULL_TREE);
9695 tree v16qi_ftype_v16qi_v16qi
9696 = build_function_type_list (V16QI_type_node,
9697 V16QI_type_node, V16QI_type_node, NULL_TREE);
9698 tree v4si_ftype_v4sf_v4sf
9699 = build_function_type_list (V4SI_type_node,
9700 V4SF_type_node, V4SF_type_node, NULL_TREE);
9701 tree v8hi_ftype_v16qi_v16qi
9702 = build_function_type_list (V8HI_type_node,
9703 V16QI_type_node, V16QI_type_node, NULL_TREE);
9704 tree v4si_ftype_v8hi_v8hi
9705 = build_function_type_list (V4SI_type_node,
9706 V8HI_type_node, V8HI_type_node, NULL_TREE);
9707 tree v8hi_ftype_v4si_v4si
9708 = build_function_type_list (V8HI_type_node,
9709 V4SI_type_node, V4SI_type_node, NULL_TREE);
9710 tree v16qi_ftype_v8hi_v8hi
9711 = build_function_type_list (V16QI_type_node,
9712 V8HI_type_node, V8HI_type_node, NULL_TREE);
9713 tree v4si_ftype_v16qi_v4si
9714 = build_function_type_list (V4SI_type_node,
9715 V16QI_type_node, V4SI_type_node, NULL_TREE);
9716 tree v4si_ftype_v16qi_v16qi
9717 = build_function_type_list (V4SI_type_node,
9718 V16QI_type_node, V16QI_type_node, NULL_TREE);
9719 tree v4si_ftype_v8hi_v4si
9720 = build_function_type_list (V4SI_type_node,
9721 V8HI_type_node, V4SI_type_node, NULL_TREE);
9722 tree v4si_ftype_v8hi
9723 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9724 tree int_ftype_v4si_v4si
9725 = build_function_type_list (integer_type_node,
9726 V4SI_type_node, V4SI_type_node, NULL_TREE);
9727 tree int_ftype_v4sf_v4sf
9728 = build_function_type_list (integer_type_node,
9729 V4SF_type_node, V4SF_type_node, NULL_TREE);
9730 tree int_ftype_v16qi_v16qi
9731 = build_function_type_list (integer_type_node,
9732 V16QI_type_node, V16QI_type_node, NULL_TREE);
9733 tree int_ftype_v8hi_v8hi
9734 = build_function_type_list (integer_type_node,
9735 V8HI_type_node, V8HI_type_node, NULL_TREE);
9737 /* Add the simple ternary operators. */
9739 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9741 enum machine_mode mode0, mode1, mode2, mode3;
9743 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9744 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9755 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9758 mode0 = insn_data[d->icode].operand[0].mode;
9759 mode1 = insn_data[d->icode].operand[1].mode;
9760 mode2 = insn_data[d->icode].operand[2].mode;
9761 mode3 = insn_data[d->icode].operand[3].mode;
9764 /* When all four are of the same mode. */
9765 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9770 type = opaque_ftype_opaque_opaque_opaque;
9773 type = v4si_ftype_v4si_v4si_v4si;
9776 type = v4sf_ftype_v4sf_v4sf_v4sf;
9779 type = v8hi_ftype_v8hi_v8hi_v8hi;
9782 type = v16qi_ftype_v16qi_v16qi_v16qi;
9785 type = v2sf_ftype_v2sf_v2sf_v2sf;
9791 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9796 type = v4si_ftype_v4si_v4si_v16qi;
9799 type = v4sf_ftype_v4sf_v4sf_v16qi;
9802 type = v8hi_ftype_v8hi_v8hi_v16qi;
9805 type = v16qi_ftype_v16qi_v16qi_v16qi;
9811 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9812 && mode3 == V4SImode)
9813 type = v4si_ftype_v16qi_v16qi_v4si;
9814 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9815 && mode3 == V4SImode)
9816 type = v4si_ftype_v8hi_v8hi_v4si;
9817 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9818 && mode3 == V4SImode)
9819 type = v4sf_ftype_v4sf_v4sf_v4si;
9821 /* vchar, vchar, vchar, 4-bit literal. */
9822 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9824 type = v16qi_ftype_v16qi_v16qi_int;
9826 /* vshort, vshort, vshort, 4-bit literal. */
9827 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9829 type = v8hi_ftype_v8hi_v8hi_int;
9831 /* vint, vint, vint, 4-bit literal. */
9832 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9834 type = v4si_ftype_v4si_v4si_int;
9836 /* vfloat, vfloat, vfloat, 4-bit literal. */
9837 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9839 type = v4sf_ftype_v4sf_v4sf_int;
9844 def_builtin (d->mask, d->name, type, d->code);
9847 /* Add the simple binary operators. */
9848 d = (struct builtin_description *) bdesc_2arg;
9849 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9851 enum machine_mode mode0, mode1, mode2;
9853 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9854 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9864 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9867 mode0 = insn_data[d->icode].operand[0].mode;
9868 mode1 = insn_data[d->icode].operand[1].mode;
9869 mode2 = insn_data[d->icode].operand[2].mode;
9872 /* When all three operands are of the same mode. */
9873 if (mode0 == mode1 && mode1 == mode2)
9878 type = opaque_ftype_opaque_opaque;
9881 type = v4sf_ftype_v4sf_v4sf;
9884 type = v4si_ftype_v4si_v4si;
9887 type = v16qi_ftype_v16qi_v16qi;
9890 type = v8hi_ftype_v8hi_v8hi;
9893 type = v2si_ftype_v2si_v2si;
9896 if (TARGET_PAIRED_FLOAT)
9897 type = v2sf_ftype_v2sf_v2sf;
9899 type = v2sf_ftype_v2sf_v2sf_spe;
9902 type = int_ftype_int_int;
9909 /* A few other combos we really don't want to do manually. */
9911 /* vint, vfloat, vfloat. */
9912 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9913 type = v4si_ftype_v4sf_v4sf;
9915 /* vshort, vchar, vchar. */
9916 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9917 type = v8hi_ftype_v16qi_v16qi;
9919 /* vint, vshort, vshort. */
9920 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9921 type = v4si_ftype_v8hi_v8hi;
9923 /* vshort, vint, vint. */
9924 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9925 type = v8hi_ftype_v4si_v4si;
9927 /* vchar, vshort, vshort. */
9928 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9929 type = v16qi_ftype_v8hi_v8hi;
9931 /* vint, vchar, vint. */
9932 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9933 type = v4si_ftype_v16qi_v4si;
9935 /* vint, vchar, vchar. */
9936 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9937 type = v4si_ftype_v16qi_v16qi;
9939 /* vint, vshort, vint. */
9940 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9941 type = v4si_ftype_v8hi_v4si;
9943 /* vint, vint, 5-bit literal. */
9944 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9945 type = v4si_ftype_v4si_int;
9947 /* vshort, vshort, 5-bit literal. */
9948 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9949 type = v8hi_ftype_v8hi_int;
9951 /* vchar, vchar, 5-bit literal. */
9952 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9953 type = v16qi_ftype_v16qi_int;
9955 /* vfloat, vint, 5-bit literal. */
9956 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9957 type = v4sf_ftype_v4si_int;
9959 /* vint, vfloat, 5-bit literal. */
9960 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9961 type = v4si_ftype_v4sf_int;
9963 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9964 type = v2si_ftype_int_int;
9966 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9967 type = v2si_ftype_v2si_char;
9969 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9970 type = v2si_ftype_int_char;
9975 gcc_assert (mode0 == SImode);
9979 type = int_ftype_v4si_v4si;
9982 type = int_ftype_v4sf_v4sf;
9985 type = int_ftype_v16qi_v16qi;
9988 type = int_ftype_v8hi_v8hi;
9995 def_builtin (d->mask, d->name, type, d->code);
9998 /* Add the simple unary operators. */
9999 d = (struct builtin_description *) bdesc_1arg;
10000 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
10002 enum machine_mode mode0, mode1;
10004 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10005 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10014 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10017 mode0 = insn_data[d->icode].operand[0].mode;
10018 mode1 = insn_data[d->icode].operand[1].mode;
10021 if (mode0 == V4SImode && mode1 == QImode)
10022 type = v4si_ftype_int;
10023 else if (mode0 == V8HImode && mode1 == QImode)
10024 type = v8hi_ftype_int;
10025 else if (mode0 == V16QImode && mode1 == QImode)
10026 type = v16qi_ftype_int;
10027 else if (mode0 == VOIDmode && mode1 == VOIDmode)
10028 type = opaque_ftype_opaque;
10029 else if (mode0 == V4SFmode && mode1 == V4SFmode)
10030 type = v4sf_ftype_v4sf;
10031 else if (mode0 == V8HImode && mode1 == V16QImode)
10032 type = v8hi_ftype_v16qi;
10033 else if (mode0 == V4SImode && mode1 == V8HImode)
10034 type = v4si_ftype_v8hi;
10035 else if (mode0 == V2SImode && mode1 == V2SImode)
10036 type = v2si_ftype_v2si;
10037 else if (mode0 == V2SFmode && mode1 == V2SFmode)
10039 if (TARGET_PAIRED_FLOAT)
10040 type = v2sf_ftype_v2sf;
10042 type = v2sf_ftype_v2sf_spe;
10044 else if (mode0 == V2SFmode && mode1 == V2SImode)
10045 type = v2sf_ftype_v2si;
10046 else if (mode0 == V2SImode && mode1 == V2SFmode)
10047 type = v2si_ftype_v2sf;
10048 else if (mode0 == V2SImode && mode1 == QImode)
10049 type = v2si_ftype_char;
10051 gcc_unreachable ();
10053 def_builtin (d->mask, d->name, type, d->code);
10058 rs6000_init_libfuncs (void)
10060 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
10061 && !TARGET_POWER2 && !TARGET_POWERPC)
10063 /* AIX library routines for float->int conversion. */
10064 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
10065 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
10066 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
10067 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
10070 if (!TARGET_IEEEQUAD)
10071 /* AIX/Darwin/64-bit Linux quad floating point routines. */
10072 if (!TARGET_XL_COMPAT)
10074 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
10075 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
10076 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
10077 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
10079 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
10081 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
10082 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
10083 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
10084 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
10085 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
10086 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
10087 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
10089 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
10090 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
10091 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
10092 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
10093 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
10094 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
10095 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
10096 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
10099 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
10100 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
10104 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
10105 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
10106 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
10107 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
10111 /* 32-bit SVR4 quad floating point routines. */
10113 set_optab_libfunc (add_optab, TFmode, "_q_add");
10114 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
10115 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
10116 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
10117 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
10118 if (TARGET_PPC_GPOPT || TARGET_POWER2)
10119 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
10121 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
10122 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
10123 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
10124 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
10125 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
10126 set_optab_libfunc (le_optab, TFmode, "_q_fle");
10128 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
10129 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
10130 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
10131 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
10132 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
10133 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
10134 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
10135 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
10140 /* Expand a block clear operation, and return 1 if successful. Return 0
10141 if we should let the compiler generate normal code.
10143 operands[0] is the destination
10144 operands[1] is the length
10145 operands[3] is the alignment */
10148 expand_block_clear (rtx operands[])
10150 rtx orig_dest = operands[0];
10151 rtx bytes_rtx = operands[1];
10152 rtx align_rtx = operands[3];
10153 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
10154 HOST_WIDE_INT align;
10155 HOST_WIDE_INT bytes;
10160 /* If this is not a fixed size move, just call memcpy */
10164 /* This must be a fixed size alignment */
10165 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10166 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10168 /* Anything to clear? */
10169 bytes = INTVAL (bytes_rtx);
10173 /* Use the builtin memset after a point, to avoid huge code bloat.
10174 When optimize_size, avoid any significant code bloat; calling
10175 memset is about 4 instructions, so allow for one instruction to
10176 load zero and three to do clearing. */
10177 if (TARGET_ALTIVEC && align >= 128)
10179 else if (TARGET_POWERPC64 && align >= 32)
10181 else if (TARGET_SPE && align >= 64)
10186 if (optimize_size && bytes > 3 * clear_step)
10188 if (! optimize_size && bytes > 8 * clear_step)
10191 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
10193 enum machine_mode mode = BLKmode;
10196 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
10201 else if (bytes >= 8 && TARGET_SPE && align >= 64)
10206 else if (bytes >= 8 && TARGET_POWERPC64
10207 /* 64-bit loads and stores require word-aligned
10209 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10214 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10215 { /* move 4 bytes */
10219 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10220 { /* move 2 bytes */
10224 else /* move 1 byte at a time */
10230 dest = adjust_address (orig_dest, mode, offset);
10232 emit_move_insn (dest, CONST0_RTX (mode));
10239 /* Expand a block move operation, and return 1 if successful. Return 0
10240 if we should let the compiler generate normal code.
10242 operands[0] is the destination
10243 operands[1] is the source
10244 operands[2] is the length
10245 operands[3] is the alignment */
10247 #define MAX_MOVE_REG 4
10250 expand_block_move (rtx operands[])
10252 rtx orig_dest = operands[0];
10253 rtx orig_src = operands[1];
10254 rtx bytes_rtx = operands[2];
10255 rtx align_rtx = operands[3];
10256 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
10261 rtx stores[MAX_MOVE_REG];
10264 /* If this is not a fixed size move, just call memcpy */
10268 /* This must be a fixed size alignment */
10269 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10270 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10272 /* Anything to move? */
10273 bytes = INTVAL (bytes_rtx);
10277 /* store_one_arg depends on expand_block_move to handle at least the size of
10278 reg_parm_stack_space. */
10279 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
10282 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
10285 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
10286 rtx (*mov) (rtx, rtx);
10288 enum machine_mode mode = BLKmode;
10291 /* Altivec first, since it will be faster than a string move
10292 when it applies, and usually not significantly larger. */
10293 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
10297 gen_func.mov = gen_movv4si;
10299 else if (TARGET_SPE && bytes >= 8 && align >= 64)
10303 gen_func.mov = gen_movv2si;
10305 else if (TARGET_STRING
10306 && bytes > 24 /* move up to 32 bytes at a time */
10312 && ! fixed_regs[10]
10313 && ! fixed_regs[11]
10314 && ! fixed_regs[12])
10316 move_bytes = (bytes > 32) ? 32 : bytes;
10317 gen_func.movmemsi = gen_movmemsi_8reg;
10319 else if (TARGET_STRING
10320 && bytes > 16 /* move up to 24 bytes at a time */
10326 && ! fixed_regs[10])
10328 move_bytes = (bytes > 24) ? 24 : bytes;
10329 gen_func.movmemsi = gen_movmemsi_6reg;
10331 else if (TARGET_STRING
10332 && bytes > 8 /* move up to 16 bytes at a time */
10336 && ! fixed_regs[8])
10338 move_bytes = (bytes > 16) ? 16 : bytes;
10339 gen_func.movmemsi = gen_movmemsi_4reg;
10341 else if (bytes >= 8 && TARGET_POWERPC64
10342 /* 64-bit loads and stores require word-aligned
10344 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10348 gen_func.mov = gen_movdi;
10350 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
10351 { /* move up to 8 bytes at a time */
10352 move_bytes = (bytes > 8) ? 8 : bytes;
10353 gen_func.movmemsi = gen_movmemsi_2reg;
10355 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10356 { /* move 4 bytes */
10359 gen_func.mov = gen_movsi;
10361 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10362 { /* move 2 bytes */
10365 gen_func.mov = gen_movhi;
10367 else if (TARGET_STRING && bytes > 1)
10368 { /* move up to 4 bytes at a time */
10369 move_bytes = (bytes > 4) ? 4 : bytes;
10370 gen_func.movmemsi = gen_movmemsi_1reg;
10372 else /* move 1 byte at a time */
10376 gen_func.mov = gen_movqi;
10379 src = adjust_address (orig_src, mode, offset);
10380 dest = adjust_address (orig_dest, mode, offset);
10382 if (mode != BLKmode)
10384 rtx tmp_reg = gen_reg_rtx (mode);
10386 emit_insn ((*gen_func.mov) (tmp_reg, src));
10387 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
10390 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
10393 for (i = 0; i < num_reg; i++)
10394 emit_insn (stores[i]);
10398 if (mode == BLKmode)
10400 /* Move the address into scratch registers. The movmemsi
10401 patterns require zero offset. */
10402 if (!REG_P (XEXP (src, 0)))
10404 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
10405 src = replace_equiv_address (src, src_reg);
10407 set_mem_size (src, GEN_INT (move_bytes));
10409 if (!REG_P (XEXP (dest, 0)))
10411 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
10412 dest = replace_equiv_address (dest, dest_reg);
10414 set_mem_size (dest, GEN_INT (move_bytes));
10416 emit_insn ((*gen_func.movmemsi) (dest, src,
10417 GEN_INT (move_bytes & 31),
10426 /* Return a string to perform a load_multiple operation.
10427 operands[0] is the vector.
10428 operands[1] is the source address.
10429 operands[2] is the first destination register. */
10432 rs6000_output_load_multiple (rtx operands[3])
10434 /* We have to handle the case where the pseudo used to contain the address
10435 is assigned to one of the output registers. */
10437 int words = XVECLEN (operands[0], 0);
10440 if (XVECLEN (operands[0], 0) == 1)
10441 return "{l|lwz} %2,0(%1)";
10443 for (i = 0; i < words; i++)
10444 if (refers_to_regno_p (REGNO (operands[2]) + i,
10445 REGNO (operands[2]) + i + 1, operands[1], 0))
10449 xop[0] = GEN_INT (4 * (words-1));
10450 xop[1] = operands[1];
10451 xop[2] = operands[2];
10452 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
10457 xop[0] = GEN_INT (4 * (words-1));
10458 xop[1] = operands[1];
10459 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
10460 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
10465 for (j = 0; j < words; j++)
10468 xop[0] = GEN_INT (j * 4);
10469 xop[1] = operands[1];
10470 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
10471 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
10473 xop[0] = GEN_INT (i * 4);
10474 xop[1] = operands[1];
10475 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
10480 return "{lsi|lswi} %2,%1,%N0";
10484 /* A validation routine: say whether CODE, a condition code, and MODE
10485 match. The other alternatives either don't make sense or should
10486 never be generated. */
10489 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
10491 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
10492 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
10493 && GET_MODE_CLASS (mode) == MODE_CC);
10495 /* These don't make sense. */
10496 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
10497 || mode != CCUNSmode);
10499 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
10500 || mode == CCUNSmode);
10502 gcc_assert (mode == CCFPmode
10503 || (code != ORDERED && code != UNORDERED
10504 && code != UNEQ && code != LTGT
10505 && code != UNGT && code != UNLT
10506 && code != UNGE && code != UNLE));
10508 /* These should never be generated except for
10509 flag_finite_math_only. */
10510 gcc_assert (mode != CCFPmode
10511 || flag_finite_math_only
10512 || (code != LE && code != GE
10513 && code != UNEQ && code != LTGT
10514 && code != UNGT && code != UNLT));
10516 /* These are invalid; the information is not there. */
10517 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10521 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10522 mask required to convert the result of a rotate insn into a shift
10523 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10526 includes_lshift_p (rtx shiftop, rtx andop)
10528 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10530 shift_mask <<= INTVAL (shiftop);
10532 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10535 /* Similar, but for right shift. */
10538 includes_rshift_p (rtx shiftop, rtx andop)
10540 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10542 shift_mask >>= INTVAL (shiftop);
10544 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10547 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10548 to perform a left shift. It must have exactly SHIFTOP least
10549 significant 0's, then one or more 1's, then zero or more 0's. */
10552 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10554 if (GET_CODE (andop) == CONST_INT)
10556 HOST_WIDE_INT c, lsb, shift_mask;
10558 c = INTVAL (andop);
10559 if (c == 0 || c == ~0)
10563 shift_mask <<= INTVAL (shiftop);
10565 /* Find the least significant one bit. */
10568 /* It must coincide with the LSB of the shift mask. */
10569 if (-lsb != shift_mask)
10572 /* Invert to look for the next transition (if any). */
10575 /* Remove the low group of ones (originally low group of zeros). */
10578 /* Again find the lsb, and check we have all 1's above. */
10582 else if (GET_CODE (andop) == CONST_DOUBLE
10583 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10585 HOST_WIDE_INT low, high, lsb;
10586 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10588 low = CONST_DOUBLE_LOW (andop);
10589 if (HOST_BITS_PER_WIDE_INT < 64)
10590 high = CONST_DOUBLE_HIGH (andop);
10592 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10593 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10596 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10598 shift_mask_high = ~0;
10599 if (INTVAL (shiftop) > 32)
10600 shift_mask_high <<= INTVAL (shiftop) - 32;
10602 lsb = high & -high;
10604 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10610 lsb = high & -high;
10611 return high == -lsb;
10614 shift_mask_low = ~0;
10615 shift_mask_low <<= INTVAL (shiftop);
10619 if (-lsb != shift_mask_low)
10622 if (HOST_BITS_PER_WIDE_INT < 64)
10627 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10629 lsb = high & -high;
10630 return high == -lsb;
10634 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
10640 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10641 to perform a left shift. It must have SHIFTOP or more least
10642 significant 0's, with the remainder of the word 1's. */
10645 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
10647 if (GET_CODE (andop) == CONST_INT)
10649 HOST_WIDE_INT c, lsb, shift_mask;
10652 shift_mask <<= INTVAL (shiftop);
10653 c = INTVAL (andop);
10655 /* Find the least significant one bit. */
10658 /* It must be covered by the shift mask.
10659 This test also rejects c == 0. */
10660 if ((lsb & shift_mask) == 0)
10663 /* Check we have all 1's above the transition, and reject all 1's. */
10664 return c == -lsb && lsb != 1;
10666 else if (GET_CODE (andop) == CONST_DOUBLE
10667 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10669 HOST_WIDE_INT low, lsb, shift_mask_low;
10671 low = CONST_DOUBLE_LOW (andop);
10673 if (HOST_BITS_PER_WIDE_INT < 64)
10675 HOST_WIDE_INT high, shift_mask_high;
10677 high = CONST_DOUBLE_HIGH (andop);
10681 shift_mask_high = ~0;
10682 if (INTVAL (shiftop) > 32)
10683 shift_mask_high <<= INTVAL (shiftop) - 32;
10685 lsb = high & -high;
10687 if ((lsb & shift_mask_high) == 0)
10690 return high == -lsb;
10696 shift_mask_low = ~0;
10697 shift_mask_low <<= INTVAL (shiftop);
10701 if ((lsb & shift_mask_low) == 0)
10704 return low == -lsb && lsb != 1;
10710 /* Return 1 if operands will generate a valid arguments to rlwimi
10711 instruction for insert with right shift in 64-bit mode. The mask may
10712 not start on the first bit or stop on the last bit because wrap-around
10713 effects of instruction do not correspond to semantics of RTL insn. */
10716 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10718 if (INTVAL (startop) > 32
10719 && INTVAL (startop) < 64
10720 && INTVAL (sizeop) > 1
10721 && INTVAL (sizeop) + INTVAL (startop) < 64
10722 && INTVAL (shiftop) > 0
10723 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10724 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10730 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10731 for lfq and stfq insns iff the registers are hard registers. */
10734 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10736 /* We might have been passed a SUBREG. */
10737 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10740 /* We might have been passed non floating point registers. */
10741 if (!FP_REGNO_P (REGNO (reg1))
10742 || !FP_REGNO_P (REGNO (reg2)))
10745 return (REGNO (reg1) == REGNO (reg2) - 1);
10748 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10749 addr1 and addr2 must be in consecutive memory locations
10750 (addr2 == addr1 + 8). */
10753 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10756 unsigned int reg1, reg2;
10757 int offset1, offset2;
10759 /* The mems cannot be volatile. */
10760 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10763 addr1 = XEXP (mem1, 0);
10764 addr2 = XEXP (mem2, 0);
10766 /* Extract an offset (if used) from the first addr. */
10767 if (GET_CODE (addr1) == PLUS)
10769 /* If not a REG, return zero. */
10770 if (GET_CODE (XEXP (addr1, 0)) != REG)
10774 reg1 = REGNO (XEXP (addr1, 0));
10775 /* The offset must be constant! */
10776 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10778 offset1 = INTVAL (XEXP (addr1, 1));
10781 else if (GET_CODE (addr1) != REG)
10785 reg1 = REGNO (addr1);
10786 /* This was a simple (mem (reg)) expression. Offset is 0. */
10790 /* And now for the second addr. */
10791 if (GET_CODE (addr2) == PLUS)
10793 /* If not a REG, return zero. */
10794 if (GET_CODE (XEXP (addr2, 0)) != REG)
10798 reg2 = REGNO (XEXP (addr2, 0));
10799 /* The offset must be constant. */
10800 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10802 offset2 = INTVAL (XEXP (addr2, 1));
10805 else if (GET_CODE (addr2) != REG)
10809 reg2 = REGNO (addr2);
10810 /* This was a simple (mem (reg)) expression. Offset is 0. */
10814 /* Both of these must have the same base register. */
10818 /* The offset for the second addr must be 8 more than the first addr. */
10819 if (offset2 != offset1 + 8)
10822 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10827 /* Return the register class of a scratch register needed to copy IN into
10828 or out of a register in CLASS in MODE. If it can be done directly,
10829 NO_REGS is returned. */
10832 rs6000_secondary_reload_class (enum reg_class class,
10833 enum machine_mode mode ATTRIBUTE_UNUSED,
10838 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10840 && MACHOPIC_INDIRECT
10844 /* We cannot copy a symbolic operand directly into anything
10845 other than BASE_REGS for TARGET_ELF. So indicate that a
10846 register from BASE_REGS is needed as an intermediate
10849 On Darwin, pic addresses require a load from memory, which
10850 needs a base register. */
10851 if (class != BASE_REGS
10852 && (GET_CODE (in) == SYMBOL_REF
10853 || GET_CODE (in) == HIGH
10854 || GET_CODE (in) == LABEL_REF
10855 || GET_CODE (in) == CONST))
10859 if (GET_CODE (in) == REG)
10861 regno = REGNO (in);
10862 if (regno >= FIRST_PSEUDO_REGISTER)
10864 regno = true_regnum (in);
10865 if (regno >= FIRST_PSEUDO_REGISTER)
10869 else if (GET_CODE (in) == SUBREG)
10871 regno = true_regnum (in);
10872 if (regno >= FIRST_PSEUDO_REGISTER)
10878 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10880 if (class == GENERAL_REGS || class == BASE_REGS
10881 || (regno >= 0 && INT_REGNO_P (regno)))
10884 /* Constants, memory, and FP registers can go into FP registers. */
10885 if ((regno == -1 || FP_REGNO_P (regno))
10886 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10889 /* Memory, and AltiVec registers can go into AltiVec registers. */
10890 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10891 && class == ALTIVEC_REGS)
10894 /* We can copy among the CR registers. */
10895 if ((class == CR_REGS || class == CR0_REGS)
10896 && regno >= 0 && CR_REGNO_P (regno))
10899 /* Otherwise, we need GENERAL_REGS. */
10900 return GENERAL_REGS;
10903 /* Given a comparison operation, return the bit number in CCR to test. We
10904 know this is a valid comparison.
10906 SCC_P is 1 if this is for an scc. That means that %D will have been
10907 used instead of %C, so the bits will be in different places.
10909 Return -1 if OP isn't a valid comparison for some reason. */
10912 ccr_bit (rtx op, int scc_p)
10914 enum rtx_code code = GET_CODE (op);
10915 enum machine_mode cc_mode;
10920 if (!COMPARISON_P (op))
10923 reg = XEXP (op, 0);
10925 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10927 cc_mode = GET_MODE (reg);
10928 cc_regnum = REGNO (reg);
10929 base_bit = 4 * (cc_regnum - CR0_REGNO);
10931 validate_condition_mode (code, cc_mode);
10933 /* When generating a sCOND operation, only positive conditions are
10936 || code == EQ || code == GT || code == LT || code == UNORDERED
10937 || code == GTU || code == LTU);
10942 return scc_p ? base_bit + 3 : base_bit + 2;
10944 return base_bit + 2;
10945 case GT: case GTU: case UNLE:
10946 return base_bit + 1;
10947 case LT: case LTU: case UNGE:
10949 case ORDERED: case UNORDERED:
10950 return base_bit + 3;
10953 /* If scc, we will have done a cror to put the bit in the
10954 unordered position. So test that bit. For integer, this is ! LT
10955 unless this is an scc insn. */
10956 return scc_p ? base_bit + 3 : base_bit;
10959 return scc_p ? base_bit + 3 : base_bit + 1;
10962 gcc_unreachable ();
10966 /* Return the GOT register. */
10969 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10971 /* The second flow pass currently (June 1999) can't update
10972 regs_ever_live without disturbing other parts of the compiler, so
10973 update it here to make the prolog/epilogue code happy. */
10974 if (!can_create_pseudo_p ()
10975 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
10976 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
10978 current_function_uses_pic_offset_table = 1;
10980 return pic_offset_table_rtx;
10983 /* Function to init struct machine_function.
10984 This will be called, via a pointer variable,
10985 from push_function_context. */
10987 static struct machine_function *
10988 rs6000_init_machine_status (void)
10990 return ggc_alloc_cleared (sizeof (machine_function));
10993 /* These macros test for integers and extract the low-order bits. */
10995 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10996 && GET_MODE (X) == VOIDmode)
10998 #define INT_LOWPART(X) \
10999 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
11002 extract_MB (rtx op)
11005 unsigned long val = INT_LOWPART (op);
11007 /* If the high bit is zero, the value is the first 1 bit we find
11009 if ((val & 0x80000000) == 0)
11011 gcc_assert (val & 0xffffffff);
11014 while (((val <<= 1) & 0x80000000) == 0)
11019 /* If the high bit is set and the low bit is not, or the mask is all
11020 1's, the value is zero. */
11021 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
11024 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11027 while (((val >>= 1) & 1) != 0)
11034 extract_ME (rtx op)
11037 unsigned long val = INT_LOWPART (op);
11039 /* If the low bit is zero, the value is the first 1 bit we find from
11041 if ((val & 1) == 0)
11043 gcc_assert (val & 0xffffffff);
11046 while (((val >>= 1) & 1) == 0)
11052 /* If the low bit is set and the high bit is not, or the mask is all
11053 1's, the value is 31. */
11054 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
11057 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11060 while (((val <<= 1) & 0x80000000) != 0)
11066 /* Locate some local-dynamic symbol still in use by this function
11067 so that we can print its name in some tls_ld pattern. */
11069 static const char *
11070 rs6000_get_some_local_dynamic_name (void)
11074 if (cfun->machine->some_ld_name)
11075 return cfun->machine->some_ld_name;
11077 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11079 && for_each_rtx (&PATTERN (insn),
11080 rs6000_get_some_local_dynamic_name_1, 0))
11081 return cfun->machine->some_ld_name;
11083 gcc_unreachable ();
11086 /* Helper function for rs6000_get_some_local_dynamic_name. */
11089 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11093 if (GET_CODE (x) == SYMBOL_REF)
11095 const char *str = XSTR (x, 0);
11096 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11098 cfun->machine->some_ld_name = str;
11106 /* Write out a function code label. */
11109 rs6000_output_function_entry (FILE *file, const char *fname)
11111 if (fname[0] != '.')
11113 switch (DEFAULT_ABI)
11116 gcc_unreachable ();
11122 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
11131 RS6000_OUTPUT_BASENAME (file, fname);
11133 assemble_name (file, fname);
11136 /* Print an operand. Recognize special options, documented below. */
11139 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
11140 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
11142 #define SMALL_DATA_RELOC "sda21"
11143 #define SMALL_DATA_REG 0
11147 print_operand (FILE *file, rtx x, int code)
11151 unsigned HOST_WIDE_INT uval;
11156 /* Write out an instruction after the call which may be replaced
11157 with glue code by the loader. This depends on the AIX version. */
11158 asm_fprintf (file, RS6000_CALL_GLUE);
11161 /* %a is output_address. */
11164 /* If X is a constant integer whose low-order 5 bits are zero,
11165 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
11166 in the AIX assembler where "sri" with a zero shift count
11167 writes a trash instruction. */
11168 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
11175 /* If constant, low-order 16 bits of constant, unsigned.
11176 Otherwise, write normally. */
11178 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
11180 print_operand (file, x, 0);
11184 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
11185 for 64-bit mask direction. */
11186 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
11189 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
11193 /* X is a CR register. Print the number of the GT bit of the CR. */
11194 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11195 output_operand_lossage ("invalid %%E value");
11197 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
11201 /* Like 'J' but get to the GT bit only. */
11202 gcc_assert (GET_CODE (x) == REG);
11204 /* Bit 1 is GT bit. */
11205 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
11207 /* Add one for shift count in rlinm for scc. */
11208 fprintf (file, "%d", i + 1);
11212 /* X is a CR register. Print the number of the EQ bit of the CR */
11213 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11214 output_operand_lossage ("invalid %%E value");
11216 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
11220 /* X is a CR register. Print the shift count needed to move it
11221 to the high-order four bits. */
11222 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11223 output_operand_lossage ("invalid %%f value");
11225 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
11229 /* Similar, but print the count for the rotate in the opposite
11231 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11232 output_operand_lossage ("invalid %%F value");
11234 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
11238 /* X is a constant integer. If it is negative, print "m",
11239 otherwise print "z". This is to make an aze or ame insn. */
11240 if (GET_CODE (x) != CONST_INT)
11241 output_operand_lossage ("invalid %%G value");
11242 else if (INTVAL (x) >= 0)
11249 /* If constant, output low-order five bits. Otherwise, write
11252 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
11254 print_operand (file, x, 0);
11258 /* If constant, output low-order six bits. Otherwise, write
11261 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
11263 print_operand (file, x, 0);
11267 /* Print `i' if this is a constant, else nothing. */
11273 /* Write the bit number in CCR for jump. */
11274 i = ccr_bit (x, 0);
11276 output_operand_lossage ("invalid %%j code");
11278 fprintf (file, "%d", i);
11282 /* Similar, but add one for shift count in rlinm for scc and pass
11283 scc flag to `ccr_bit'. */
11284 i = ccr_bit (x, 1);
11286 output_operand_lossage ("invalid %%J code");
11288 /* If we want bit 31, write a shift count of zero, not 32. */
11289 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11293 /* X must be a constant. Write the 1's complement of the
11296 output_operand_lossage ("invalid %%k value");
11298 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
11302 /* X must be a symbolic constant on ELF. Write an
11303 expression suitable for an 'addi' that adds in the low 16
11304 bits of the MEM. */
11305 if (GET_CODE (x) != CONST)
11307 print_operand_address (file, x);
11308 fputs ("@l", file);
11312 if (GET_CODE (XEXP (x, 0)) != PLUS
11313 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
11314 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
11315 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
11316 output_operand_lossage ("invalid %%K value");
11317 print_operand_address (file, XEXP (XEXP (x, 0), 0));
11318 fputs ("@l", file);
11319 /* For GNU as, there must be a non-alphanumeric character
11320 between 'l' and the number. The '-' is added by
11321 print_operand() already. */
11322 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
11324 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
11328 /* %l is output_asm_label. */
11331 /* Write second word of DImode or DFmode reference. Works on register
11332 or non-indexed memory only. */
11333 if (GET_CODE (x) == REG)
11334 fputs (reg_names[REGNO (x) + 1], file);
11335 else if (GET_CODE (x) == MEM)
11337 /* Handle possible auto-increment. Since it is pre-increment and
11338 we have already done it, we can just use an offset of word. */
11339 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11340 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11341 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11343 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11344 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11347 output_address (XEXP (adjust_address_nv (x, SImode,
11351 if (small_data_operand (x, GET_MODE (x)))
11352 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11353 reg_names[SMALL_DATA_REG]);
11358 /* MB value for a mask operand. */
11359 if (! mask_operand (x, SImode))
11360 output_operand_lossage ("invalid %%m value");
11362 fprintf (file, "%d", extract_MB (x));
11366 /* ME value for a mask operand. */
11367 if (! mask_operand (x, SImode))
11368 output_operand_lossage ("invalid %%M value");
11370 fprintf (file, "%d", extract_ME (x));
11373 /* %n outputs the negative of its operand. */
11376 /* Write the number of elements in the vector times 4. */
11377 if (GET_CODE (x) != PARALLEL)
11378 output_operand_lossage ("invalid %%N value");
11380 fprintf (file, "%d", XVECLEN (x, 0) * 4);
11384 /* Similar, but subtract 1 first. */
11385 if (GET_CODE (x) != PARALLEL)
11386 output_operand_lossage ("invalid %%O value");
11388 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
11392 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11394 || INT_LOWPART (x) < 0
11395 || (i = exact_log2 (INT_LOWPART (x))) < 0)
11396 output_operand_lossage ("invalid %%p value");
11398 fprintf (file, "%d", i);
11402 /* The operand must be an indirect memory reference. The result
11403 is the register name. */
11404 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
11405 || REGNO (XEXP (x, 0)) >= 32)
11406 output_operand_lossage ("invalid %%P value");
11408 fputs (reg_names[REGNO (XEXP (x, 0))], file);
11412 /* This outputs the logical code corresponding to a boolean
11413 expression. The expression may have one or both operands
11414 negated (if one, only the first one). For condition register
11415 logical operations, it will also treat the negated
11416 CR codes as NOTs, but not handle NOTs of them. */
11418 const char *const *t = 0;
11420 enum rtx_code code = GET_CODE (x);
11421 static const char * const tbl[3][3] = {
11422 { "and", "andc", "nor" },
11423 { "or", "orc", "nand" },
11424 { "xor", "eqv", "xor" } };
11428 else if (code == IOR)
11430 else if (code == XOR)
11433 output_operand_lossage ("invalid %%q value");
11435 if (GET_CODE (XEXP (x, 0)) != NOT)
11439 if (GET_CODE (XEXP (x, 1)) == NOT)
11457 /* X is a CR register. Print the mask for `mtcrf'. */
11458 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11459 output_operand_lossage ("invalid %%R value");
11461 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
11465 /* Low 5 bits of 32 - value */
11467 output_operand_lossage ("invalid %%s value");
11469 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
11473 /* PowerPC64 mask position. All 0's is excluded.
11474 CONST_INT 32-bit mask is considered sign-extended so any
11475 transition must occur within the CONST_INT, not on the boundary. */
11476 if (! mask64_operand (x, DImode))
11477 output_operand_lossage ("invalid %%S value");
11479 uval = INT_LOWPART (x);
11481 if (uval & 1) /* Clear Left */
11483 #if HOST_BITS_PER_WIDE_INT > 64
11484 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11488 else /* Clear Right */
11491 #if HOST_BITS_PER_WIDE_INT > 64
11492 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11498 gcc_assert (i >= 0);
11499 fprintf (file, "%d", i);
11503 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
11504 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
11506 /* Bit 3 is OV bit. */
11507 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
11509 /* If we want bit 31, write a shift count of zero, not 32. */
11510 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11514 /* Print the symbolic name of a branch target register. */
11515 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
11516 && REGNO (x) != CTR_REGNO))
11517 output_operand_lossage ("invalid %%T value");
11518 else if (REGNO (x) == LR_REGNO)
11519 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
11521 fputs ("ctr", file);
11525 /* High-order 16 bits of constant for use in unsigned operand. */
11527 output_operand_lossage ("invalid %%u value");
11529 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11530 (INT_LOWPART (x) >> 16) & 0xffff);
11534 /* High-order 16 bits of constant for use in signed operand. */
11536 output_operand_lossage ("invalid %%v value");
11538 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11539 (INT_LOWPART (x) >> 16) & 0xffff);
11543 /* Print `u' if this has an auto-increment or auto-decrement. */
11544 if (GET_CODE (x) == MEM
11545 && (GET_CODE (XEXP (x, 0)) == PRE_INC
11546 || GET_CODE (XEXP (x, 0)) == PRE_DEC
11547 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
11552 /* Print the trap code for this operand. */
11553 switch (GET_CODE (x))
11556 fputs ("eq", file); /* 4 */
11559 fputs ("ne", file); /* 24 */
11562 fputs ("lt", file); /* 16 */
11565 fputs ("le", file); /* 20 */
11568 fputs ("gt", file); /* 8 */
11571 fputs ("ge", file); /* 12 */
11574 fputs ("llt", file); /* 2 */
11577 fputs ("lle", file); /* 6 */
11580 fputs ("lgt", file); /* 1 */
11583 fputs ("lge", file); /* 5 */
11586 gcc_unreachable ();
11591 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11594 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
11595 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
11597 print_operand (file, x, 0);
11601 /* MB value for a PowerPC64 rldic operand. */
11602 val = (GET_CODE (x) == CONST_INT
11603 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
11608 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
11609 if ((val <<= 1) < 0)
11612 #if HOST_BITS_PER_WIDE_INT == 32
11613 if (GET_CODE (x) == CONST_INT && i >= 0)
11614 i += 32; /* zero-extend high-part was all 0's */
11615 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
11617 val = CONST_DOUBLE_LOW (x);
11623 for ( ; i < 64; i++)
11624 if ((val <<= 1) < 0)
11629 fprintf (file, "%d", i + 1);
11633 if (GET_CODE (x) == MEM
11634 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
11635 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
11636 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
11641 /* Like 'L', for third word of TImode */
11642 if (GET_CODE (x) == REG)
11643 fputs (reg_names[REGNO (x) + 2], file);
11644 else if (GET_CODE (x) == MEM)
11646 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11647 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11648 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11649 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11650 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11652 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
11653 if (small_data_operand (x, GET_MODE (x)))
11654 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11655 reg_names[SMALL_DATA_REG]);
11660 /* X is a SYMBOL_REF. Write out the name preceded by a
11661 period and without any trailing data in brackets. Used for function
11662 names. If we are configured for System V (or the embedded ABI) on
11663 the PowerPC, do not emit the period, since those systems do not use
11664 TOCs and the like. */
11665 gcc_assert (GET_CODE (x) == SYMBOL_REF);
11667 /* Mark the decl as referenced so that cgraph will output the
11669 if (SYMBOL_REF_DECL (x))
11670 mark_decl_referenced (SYMBOL_REF_DECL (x));
11672 /* For macho, check to see if we need a stub. */
11675 const char *name = XSTR (x, 0);
11677 if (MACHOPIC_INDIRECT
11678 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11679 name = machopic_indirection_name (x, /*stub_p=*/true);
11681 assemble_name (file, name);
11683 else if (!DOT_SYMBOLS)
11684 assemble_name (file, XSTR (x, 0));
11686 rs6000_output_function_entry (file, XSTR (x, 0));
11690 /* Like 'L', for last word of TImode. */
11691 if (GET_CODE (x) == REG)
11692 fputs (reg_names[REGNO (x) + 3], file);
11693 else if (GET_CODE (x) == MEM)
11695 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11696 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11697 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11698 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11699 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11701 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11702 if (small_data_operand (x, GET_MODE (x)))
11703 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11704 reg_names[SMALL_DATA_REG]);
11708 /* Print AltiVec or SPE memory operand. */
11713 gcc_assert (GET_CODE (x) == MEM);
11717 /* Ugly hack because %y is overloaded. */
11718 if ((TARGET_SPE || TARGET_E500_DOUBLE)
11719 && (GET_MODE_SIZE (GET_MODE (x)) == 8
11720 || GET_MODE (x) == TFmode
11721 || GET_MODE (x) == TImode))
11723 /* Handle [reg]. */
11724 if (GET_CODE (tmp) == REG)
11726 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11729 /* Handle [reg+UIMM]. */
11730 else if (GET_CODE (tmp) == PLUS &&
11731 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11735 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11737 x = INTVAL (XEXP (tmp, 1));
11738 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11742 /* Fall through. Must be [reg+reg]. */
11745 && GET_CODE (tmp) == AND
11746 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11747 && INTVAL (XEXP (tmp, 1)) == -16)
11748 tmp = XEXP (tmp, 0);
11749 if (GET_CODE (tmp) == REG)
11750 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11753 gcc_assert (GET_CODE (tmp) == PLUS
11754 && REG_P (XEXP (tmp, 0))
11755 && REG_P (XEXP (tmp, 1)));
11757 if (REGNO (XEXP (tmp, 0)) == 0)
11758 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11759 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11761 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11762 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11768 if (GET_CODE (x) == REG)
11769 fprintf (file, "%s", reg_names[REGNO (x)]);
11770 else if (GET_CODE (x) == MEM)
11772 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11773 know the width from the mode. */
11774 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11775 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11776 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11777 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11778 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11779 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11780 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11781 output_address (XEXP (XEXP (x, 0), 1));
11783 output_address (XEXP (x, 0));
11786 output_addr_const (file, x);
11790 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11794 output_operand_lossage ("invalid %%xn code");
11798 /* Print the address of an operand. */
11801 print_operand_address (FILE *file, rtx x)
11803 if (GET_CODE (x) == REG)
11804 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11805 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11806 || GET_CODE (x) == LABEL_REF)
11808 output_addr_const (file, x);
11809 if (small_data_operand (x, GET_MODE (x)))
11810 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11811 reg_names[SMALL_DATA_REG]);
11813 gcc_assert (!TARGET_TOC);
11815 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11817 gcc_assert (REG_P (XEXP (x, 0)));
11818 if (REGNO (XEXP (x, 0)) == 0)
11819 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11820 reg_names[ REGNO (XEXP (x, 0)) ]);
11822 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11823 reg_names[ REGNO (XEXP (x, 1)) ]);
11825 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11826 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11827 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11829 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11830 && CONSTANT_P (XEXP (x, 1)))
11832 output_addr_const (file, XEXP (x, 1));
11833 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11837 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11838 && CONSTANT_P (XEXP (x, 1)))
11840 fprintf (file, "lo16(");
11841 output_addr_const (file, XEXP (x, 1));
11842 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11845 else if (legitimate_constant_pool_address_p (x))
11847 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11849 rtx contains_minus = XEXP (x, 1);
11853 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11854 turn it into (sym) for output_addr_const. */
11855 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11856 contains_minus = XEXP (contains_minus, 0);
11858 minus = XEXP (contains_minus, 0);
11859 symref = XEXP (minus, 0);
11860 XEXP (contains_minus, 0) = symref;
11865 name = XSTR (symref, 0);
11866 newname = alloca (strlen (name) + sizeof ("@toc"));
11867 strcpy (newname, name);
11868 strcat (newname, "@toc");
11869 XSTR (symref, 0) = newname;
11871 output_addr_const (file, XEXP (x, 1));
11873 XSTR (symref, 0) = name;
11874 XEXP (contains_minus, 0) = minus;
11877 output_addr_const (file, XEXP (x, 1));
11879 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11882 gcc_unreachable ();
11885 /* Target hook for assembling integer objects. The PowerPC version has
11886 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11887 is defined. It also needs to handle DI-mode objects on 64-bit
11891 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11893 #ifdef RELOCATABLE_NEEDS_FIXUP
11894 /* Special handling for SI values. */
11895 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11897 static int recurse = 0;
11899 /* For -mrelocatable, we mark all addresses that need to be fixed up
11900 in the .fixup section. */
11901 if (TARGET_RELOCATABLE
11902 && in_section != toc_section
11903 && in_section != text_section
11904 && !unlikely_text_section_p (in_section)
11906 && GET_CODE (x) != CONST_INT
11907 && GET_CODE (x) != CONST_DOUBLE
11913 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11915 ASM_OUTPUT_LABEL (asm_out_file, buf);
11916 fprintf (asm_out_file, "\t.long\t(");
11917 output_addr_const (asm_out_file, x);
11918 fprintf (asm_out_file, ")@fixup\n");
11919 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11920 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11921 fprintf (asm_out_file, "\t.long\t");
11922 assemble_name (asm_out_file, buf);
11923 fprintf (asm_out_file, "\n\t.previous\n");
11927 /* Remove initial .'s to turn a -mcall-aixdesc function
11928 address into the address of the descriptor, not the function
11930 else if (GET_CODE (x) == SYMBOL_REF
11931 && XSTR (x, 0)[0] == '.'
11932 && DEFAULT_ABI == ABI_AIX)
11934 const char *name = XSTR (x, 0);
11935 while (*name == '.')
11938 fprintf (asm_out_file, "\t.long\t%s\n", name);
11942 #endif /* RELOCATABLE_NEEDS_FIXUP */
11943 return default_assemble_integer (x, size, aligned_p);
11946 #ifdef HAVE_GAS_HIDDEN
11947 /* Emit an assembler directive to set symbol visibility for DECL to
11948 VISIBILITY_TYPE. */
11951 rs6000_assemble_visibility (tree decl, int vis)
11953 /* Functions need to have their entry point symbol visibility set as
11954 well as their descriptor symbol visibility. */
11955 if (DEFAULT_ABI == ABI_AIX
11957 && TREE_CODE (decl) == FUNCTION_DECL)
11959 static const char * const visibility_types[] = {
11960 NULL, "internal", "hidden", "protected"
11963 const char *name, *type;
11965 name = ((* targetm.strip_name_encoding)
11966 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11967 type = visibility_types[vis];
11969 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11970 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11973 default_assemble_visibility (decl, vis);
11978 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11980 /* Reversal of FP compares takes care -- an ordered compare
11981 becomes an unordered compare and vice versa. */
11982 if (mode == CCFPmode
11983 && (!flag_finite_math_only
11984 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11985 || code == UNEQ || code == LTGT))
11986 return reverse_condition_maybe_unordered (code);
11988 return reverse_condition (code);
11991 /* Generate a compare for CODE. Return a brand-new rtx that
11992 represents the result of the compare. */
11995 rs6000_generate_compare (enum rtx_code code)
11997 enum machine_mode comp_mode;
11998 rtx compare_result;
12000 if (rs6000_compare_fp_p)
12001 comp_mode = CCFPmode;
12002 else if (code == GTU || code == LTU
12003 || code == GEU || code == LEU)
12004 comp_mode = CCUNSmode;
12005 else if ((code == EQ || code == NE)
12006 && GET_CODE (rs6000_compare_op0) == SUBREG
12007 && GET_CODE (rs6000_compare_op1) == SUBREG
12008 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
12009 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
12010 /* These are unsigned values, perhaps there will be a later
12011 ordering compare that can be shared with this one.
12012 Unfortunately we cannot detect the signedness of the operands
12013 for non-subregs. */
12014 comp_mode = CCUNSmode;
12016 comp_mode = CCmode;
12018 /* First, the compare. */
12019 compare_result = gen_reg_rtx (comp_mode);
12021 /* E500 FP compare instructions on the GPRs. Yuck! */
12022 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
12023 && rs6000_compare_fp_p)
12025 rtx cmp, or_result, compare_result2;
12026 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
12028 if (op_mode == VOIDmode)
12029 op_mode = GET_MODE (rs6000_compare_op1);
12031 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
12032 This explains the following mess. */
12036 case EQ: case UNEQ: case NE: case LTGT:
12040 cmp = flag_unsafe_math_optimizations
12041 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
12042 rs6000_compare_op1)
12043 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
12044 rs6000_compare_op1);
12048 cmp = flag_unsafe_math_optimizations
12049 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
12050 rs6000_compare_op1)
12051 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
12052 rs6000_compare_op1);
12056 cmp = flag_unsafe_math_optimizations
12057 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
12058 rs6000_compare_op1)
12059 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
12060 rs6000_compare_op1);
12064 gcc_unreachable ();
12068 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
12072 cmp = flag_unsafe_math_optimizations
12073 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
12074 rs6000_compare_op1)
12075 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
12076 rs6000_compare_op1);
12080 cmp = flag_unsafe_math_optimizations
12081 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
12082 rs6000_compare_op1)
12083 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
12084 rs6000_compare_op1);
12088 cmp = flag_unsafe_math_optimizations
12089 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
12090 rs6000_compare_op1)
12091 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
12092 rs6000_compare_op1);
12096 gcc_unreachable ();
12100 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
12104 cmp = flag_unsafe_math_optimizations
12105 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
12106 rs6000_compare_op1)
12107 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
12108 rs6000_compare_op1);
12112 cmp = flag_unsafe_math_optimizations
12113 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
12114 rs6000_compare_op1)
12115 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
12116 rs6000_compare_op1);
12120 cmp = flag_unsafe_math_optimizations
12121 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
12122 rs6000_compare_op1)
12123 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
12124 rs6000_compare_op1);
12128 gcc_unreachable ();
12132 gcc_unreachable ();
12135 /* Synthesize LE and GE from LT/GT || EQ. */
12136 if (code == LE || code == GE || code == LEU || code == GEU)
12142 case LE: code = LT; break;
12143 case GE: code = GT; break;
12144 case LEU: code = LT; break;
12145 case GEU: code = GT; break;
12146 default: gcc_unreachable ();
12149 compare_result2 = gen_reg_rtx (CCFPmode);
12155 cmp = flag_unsafe_math_optimizations
12156 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
12157 rs6000_compare_op1)
12158 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
12159 rs6000_compare_op1);
12163 cmp = flag_unsafe_math_optimizations
12164 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
12165 rs6000_compare_op1)
12166 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
12167 rs6000_compare_op1);
12171 cmp = flag_unsafe_math_optimizations
12172 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
12173 rs6000_compare_op1)
12174 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
12175 rs6000_compare_op1);
12179 gcc_unreachable ();
12183 /* OR them together. */
12184 or_result = gen_reg_rtx (CCFPmode);
12185 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
12187 compare_result = or_result;
12192 if (code == NE || code == LTGT)
12202 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
12203 CLOBBERs to match cmptf_internal2 pattern. */
12204 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
12205 && GET_MODE (rs6000_compare_op0) == TFmode
12206 && !TARGET_IEEEQUAD
12207 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
12208 emit_insn (gen_rtx_PARALLEL (VOIDmode,
12210 gen_rtx_SET (VOIDmode,
12212 gen_rtx_COMPARE (comp_mode,
12213 rs6000_compare_op0,
12214 rs6000_compare_op1)),
12215 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12216 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12217 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12218 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12219 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12220 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12221 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12222 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
12223 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
12224 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
12226 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
12227 comp_mode = CCEQmode;
12228 compare_result = gen_reg_rtx (CCEQmode);
12230 emit_insn (gen_stack_protect_testdi (compare_result,
12231 rs6000_compare_op0, op1));
12233 emit_insn (gen_stack_protect_testsi (compare_result,
12234 rs6000_compare_op0, op1));
12237 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
12238 gen_rtx_COMPARE (comp_mode,
12239 rs6000_compare_op0,
12240 rs6000_compare_op1)));
12243 /* Some kinds of FP comparisons need an OR operation;
12244 under flag_finite_math_only we don't bother. */
12245 if (rs6000_compare_fp_p
12246 && !flag_finite_math_only
12247 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
12248 && (code == LE || code == GE
12249 || code == UNEQ || code == LTGT
12250 || code == UNGT || code == UNLT))
12252 enum rtx_code or1, or2;
12253 rtx or1_rtx, or2_rtx, compare2_rtx;
12254 rtx or_result = gen_reg_rtx (CCEQmode);
12258 case LE: or1 = LT; or2 = EQ; break;
12259 case GE: or1 = GT; or2 = EQ; break;
12260 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
12261 case LTGT: or1 = LT; or2 = GT; break;
12262 case UNGT: or1 = UNORDERED; or2 = GT; break;
12263 case UNLT: or1 = UNORDERED; or2 = LT; break;
12264 default: gcc_unreachable ();
12266 validate_condition_mode (or1, comp_mode);
12267 validate_condition_mode (or2, comp_mode);
12268 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
12269 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
12270 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
12271 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
12273 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
12275 compare_result = or_result;
12279 validate_condition_mode (code, GET_MODE (compare_result));
12281 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
12285 /* Emit the RTL for an sCOND pattern. */
12288 rs6000_emit_sCOND (enum rtx_code code, rtx result)
12291 enum machine_mode op_mode;
12292 enum rtx_code cond_code;
12294 condition_rtx = rs6000_generate_compare (code);
12295 cond_code = GET_CODE (condition_rtx);
12297 if (rs6000_compare_fp_p
12298 && !TARGET_FPRS && TARGET_HARD_FLOAT)
12302 PUT_MODE (condition_rtx, SImode);
12303 t = XEXP (condition_rtx, 0);
12305 gcc_assert (cond_code == NE || cond_code == EQ);
12307 if (cond_code == NE)
12308 emit_insn (gen_e500_flip_gt_bit (t, t));
12310 emit_insn (gen_move_from_CR_gt_bit (result, t));
12314 if (cond_code == NE
12315 || cond_code == GE || cond_code == LE
12316 || cond_code == GEU || cond_code == LEU
12317 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
12319 rtx not_result = gen_reg_rtx (CCEQmode);
12320 rtx not_op, rev_cond_rtx;
12321 enum machine_mode cc_mode;
12323 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
12325 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
12326 SImode, XEXP (condition_rtx, 0), const0_rtx);
12327 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
12328 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
12329 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
12332 op_mode = GET_MODE (rs6000_compare_op0);
12333 if (op_mode == VOIDmode)
12334 op_mode = GET_MODE (rs6000_compare_op1);
12336 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
12338 PUT_MODE (condition_rtx, DImode);
12339 convert_move (result, condition_rtx, 0);
12343 PUT_MODE (condition_rtx, SImode);
12344 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
12348 /* Emit a branch of kind CODE to location LOC. */
12351 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
12353 rtx condition_rtx, loc_ref;
12355 condition_rtx = rs6000_generate_compare (code);
12356 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
12357 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
12358 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
12359 loc_ref, pc_rtx)));
12362 /* Return the string to output a conditional branch to LABEL, which is
12363 the operand number of the label, or -1 if the branch is really a
12364 conditional return.
12366 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12367 condition code register and its mode specifies what kind of
12368 comparison we made.
12370 REVERSED is nonzero if we should reverse the sense of the comparison.
12372 INSN is the insn. */
12375 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12377 static char string[64];
12378 enum rtx_code code = GET_CODE (op);
12379 rtx cc_reg = XEXP (op, 0);
12380 enum machine_mode mode = GET_MODE (cc_reg);
12381 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
12382 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12383 int really_reversed = reversed ^ need_longbranch;
12389 validate_condition_mode (code, mode);
12391 /* Work out which way this really branches. We could use
12392 reverse_condition_maybe_unordered here always but this
12393 makes the resulting assembler clearer. */
12394 if (really_reversed)
12396 /* Reversal of FP compares takes care -- an ordered compare
12397 becomes an unordered compare and vice versa. */
12398 if (mode == CCFPmode)
12399 code = reverse_condition_maybe_unordered (code);
12401 code = reverse_condition (code);
12404 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
12406 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12411 /* Opposite of GT. */
12420 gcc_unreachable ();
12426 /* Not all of these are actually distinct opcodes, but
12427 we distinguish them for clarity of the resulting assembler. */
12428 case NE: case LTGT:
12429 ccode = "ne"; break;
12430 case EQ: case UNEQ:
12431 ccode = "eq"; break;
12433 ccode = "ge"; break;
12434 case GT: case GTU: case UNGT:
12435 ccode = "gt"; break;
12437 ccode = "le"; break;
12438 case LT: case LTU: case UNLT:
12439 ccode = "lt"; break;
12440 case UNORDERED: ccode = "un"; break;
12441 case ORDERED: ccode = "nu"; break;
12442 case UNGE: ccode = "nl"; break;
12443 case UNLE: ccode = "ng"; break;
12445 gcc_unreachable ();
12448 /* Maybe we have a guess as to how likely the branch is.
12449 The old mnemonics don't have a way to specify this information. */
12451 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
12452 if (note != NULL_RTX)
12454 /* PROB is the difference from 50%. */
12455 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
12457 /* Only hint for highly probable/improbable branches on newer
12458 cpus as static prediction overrides processor dynamic
12459 prediction. For older cpus we may as well always hint, but
12460 assume not taken for branches that are very close to 50% as a
12461 mispredicted taken branch is more expensive than a
12462 mispredicted not-taken branch. */
12463 if (rs6000_always_hint
12464 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
12465 && br_prob_note_reliable_p (note)))
12467 if (abs (prob) > REG_BR_PROB_BASE / 20
12468 && ((prob > 0) ^ need_longbranch))
12476 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12478 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12480 /* We need to escape any '%' characters in the reg_names string.
12481 Assume they'd only be the first character.... */
12482 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
12484 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12488 /* If the branch distance was too far, we may have to use an
12489 unconditional branch to go the distance. */
12490 if (need_longbranch)
12491 s += sprintf (s, ",$+8\n\tb %s", label);
12493 s += sprintf (s, ",%s", label);
12499 /* Return the string to flip the GT bit on a CR. */
12501 output_e500_flip_gt_bit (rtx dst, rtx src)
12503 static char string[64];
12506 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
12507 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
12510 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
12511 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
12513 sprintf (string, "crnot %d,%d", a, b);
12517 /* Return insn index for the vector compare instruction for given CODE,
12518 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12522 get_vec_cmp_insn (enum rtx_code code,
12523 enum machine_mode dest_mode,
12524 enum machine_mode op_mode)
12526 if (!TARGET_ALTIVEC)
12527 return INSN_NOT_AVAILABLE;
12532 if (dest_mode == V16QImode && op_mode == V16QImode)
12533 return UNSPEC_VCMPEQUB;
12534 if (dest_mode == V8HImode && op_mode == V8HImode)
12535 return UNSPEC_VCMPEQUH;
12536 if (dest_mode == V4SImode && op_mode == V4SImode)
12537 return UNSPEC_VCMPEQUW;
12538 if (dest_mode == V4SImode && op_mode == V4SFmode)
12539 return UNSPEC_VCMPEQFP;
12542 if (dest_mode == V4SImode && op_mode == V4SFmode)
12543 return UNSPEC_VCMPGEFP;
12545 if (dest_mode == V16QImode && op_mode == V16QImode)
12546 return UNSPEC_VCMPGTSB;
12547 if (dest_mode == V8HImode && op_mode == V8HImode)
12548 return UNSPEC_VCMPGTSH;
12549 if (dest_mode == V4SImode && op_mode == V4SImode)
12550 return UNSPEC_VCMPGTSW;
12551 if (dest_mode == V4SImode && op_mode == V4SFmode)
12552 return UNSPEC_VCMPGTFP;
12555 if (dest_mode == V16QImode && op_mode == V16QImode)
12556 return UNSPEC_VCMPGTUB;
12557 if (dest_mode == V8HImode && op_mode == V8HImode)
12558 return UNSPEC_VCMPGTUH;
12559 if (dest_mode == V4SImode && op_mode == V4SImode)
12560 return UNSPEC_VCMPGTUW;
12565 return INSN_NOT_AVAILABLE;
12568 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12569 DMODE is expected destination mode. This is a recursive function. */
12572 rs6000_emit_vector_compare (enum rtx_code rcode,
12574 enum machine_mode dmode)
12578 enum machine_mode dest_mode;
12579 enum machine_mode op_mode = GET_MODE (op1);
12581 gcc_assert (TARGET_ALTIVEC);
12582 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
12584 /* Floating point vector compare instructions uses destination V4SImode.
12585 Move destination to appropriate mode later. */
12586 if (dmode == V4SFmode)
12587 dest_mode = V4SImode;
12591 mask = gen_reg_rtx (dest_mode);
12592 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12594 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
12596 bool swap_operands = false;
12597 bool try_again = false;
12602 swap_operands = true;
12607 swap_operands = true;
12615 /* Invert condition and try again.
12616 e.g., A != B becomes ~(A==B). */
12618 enum rtx_code rev_code;
12619 enum insn_code nor_code;
12622 rev_code = reverse_condition_maybe_unordered (rcode);
12623 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
12626 nor_code = optab_handler (one_cmpl_optab, (int)dest_mode)->insn_code;
12627 gcc_assert (nor_code != CODE_FOR_nothing);
12628 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
12630 if (dmode != dest_mode)
12632 rtx temp = gen_reg_rtx (dest_mode);
12633 convert_move (temp, mask, 0);
12643 /* Try GT/GTU/LT/LTU OR EQ */
12646 enum insn_code ior_code;
12647 enum rtx_code new_code;
12668 gcc_unreachable ();
12671 c_rtx = rs6000_emit_vector_compare (new_code,
12672 op0, op1, dest_mode);
12673 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
12676 ior_code = optab_handler (ior_optab, (int)dest_mode)->insn_code;
12677 gcc_assert (ior_code != CODE_FOR_nothing);
12678 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
12679 if (dmode != dest_mode)
12681 rtx temp = gen_reg_rtx (dest_mode);
12682 convert_move (temp, mask, 0);
12689 gcc_unreachable ();
12694 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12695 /* You only get two chances. */
12696 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
12708 emit_insn (gen_rtx_SET (VOIDmode, mask,
12709 gen_rtx_UNSPEC (dest_mode,
12710 gen_rtvec (2, op0, op1),
12712 if (dmode != dest_mode)
12714 rtx temp = gen_reg_rtx (dest_mode);
12715 convert_move (temp, mask, 0);
12721 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12722 valid insn doesn exist for given mode. */
12725 get_vsel_insn (enum machine_mode mode)
12730 return UNSPEC_VSEL4SI;
12733 return UNSPEC_VSEL4SF;
12736 return UNSPEC_VSEL8HI;
12739 return UNSPEC_VSEL16QI;
12742 return INSN_NOT_AVAILABLE;
12745 return INSN_NOT_AVAILABLE;
12748 /* Emit vector select insn where DEST is destination using
12749 operands OP1, OP2 and MASK. */
12752 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
12755 enum machine_mode dest_mode = GET_MODE (dest);
12756 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12758 temp = gen_reg_rtx (dest_mode);
12760 /* For each vector element, select op1 when mask is 1 otherwise
12762 t = gen_rtx_SET (VOIDmode, temp,
12763 gen_rtx_UNSPEC (dest_mode,
12764 gen_rtvec (3, op2, op1, mask),
12767 emit_move_insn (dest, temp);
12771 /* Emit vector conditional expression.
12772 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12773 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12776 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12777 rtx cond, rtx cc_op0, rtx cc_op1)
12779 enum machine_mode dest_mode = GET_MODE (dest);
12780 enum rtx_code rcode = GET_CODE (cond);
12783 if (!TARGET_ALTIVEC)
12786 /* Get the vector mask for the given relational operations. */
12787 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12789 rs6000_emit_vector_select (dest, op1, op2, mask);
12794 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12795 operands of the last comparison is nonzero/true, FALSE_COND if it
12796 is zero/false. Return 0 if the hardware has no such operation. */
12799 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12801 enum rtx_code code = GET_CODE (op);
12802 rtx op0 = rs6000_compare_op0;
12803 rtx op1 = rs6000_compare_op1;
12804 REAL_VALUE_TYPE c1;
12805 enum machine_mode compare_mode = GET_MODE (op0);
12806 enum machine_mode result_mode = GET_MODE (dest);
12808 bool is_against_zero;
12810 /* These modes should always match. */
12811 if (GET_MODE (op1) != compare_mode
12812 /* In the isel case however, we can use a compare immediate, so
12813 op1 may be a small constant. */
12814 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12816 if (GET_MODE (true_cond) != result_mode)
12818 if (GET_MODE (false_cond) != result_mode)
12821 /* First, work out if the hardware can do this at all, or
12822 if it's too slow.... */
12823 if (! rs6000_compare_fp_p)
12826 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12829 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
12830 && SCALAR_FLOAT_MODE_P (compare_mode))
12833 is_against_zero = op1 == CONST0_RTX (compare_mode);
12835 /* A floating-point subtract might overflow, underflow, or produce
12836 an inexact result, thus changing the floating-point flags, so it
12837 can't be generated if we care about that. It's safe if one side
12838 of the construct is zero, since then no subtract will be
12840 if (SCALAR_FLOAT_MODE_P (compare_mode)
12841 && flag_trapping_math && ! is_against_zero)
12844 /* Eliminate half of the comparisons by switching operands, this
12845 makes the remaining code simpler. */
12846 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12847 || code == LTGT || code == LT || code == UNLE)
12849 code = reverse_condition_maybe_unordered (code);
12851 true_cond = false_cond;
12855 /* UNEQ and LTGT take four instructions for a comparison with zero,
12856 it'll probably be faster to use a branch here too. */
12857 if (code == UNEQ && HONOR_NANS (compare_mode))
12860 if (GET_CODE (op1) == CONST_DOUBLE)
12861 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12863 /* We're going to try to implement comparisons by performing
12864 a subtract, then comparing against zero. Unfortunately,
12865 Inf - Inf is NaN which is not zero, and so if we don't
12866 know that the operand is finite and the comparison
12867 would treat EQ different to UNORDERED, we can't do it. */
12868 if (HONOR_INFINITIES (compare_mode)
12869 && code != GT && code != UNGE
12870 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12871 /* Constructs of the form (a OP b ? a : b) are safe. */
12872 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12873 || (! rtx_equal_p (op0, true_cond)
12874 && ! rtx_equal_p (op1, true_cond))))
12877 /* At this point we know we can use fsel. */
12879 /* Reduce the comparison to a comparison against zero. */
12880 if (! is_against_zero)
12882 temp = gen_reg_rtx (compare_mode);
12883 emit_insn (gen_rtx_SET (VOIDmode, temp,
12884 gen_rtx_MINUS (compare_mode, op0, op1)));
12886 op1 = CONST0_RTX (compare_mode);
12889 /* If we don't care about NaNs we can reduce some of the comparisons
12890 down to faster ones. */
12891 if (! HONOR_NANS (compare_mode))
12897 true_cond = false_cond;
12910 /* Now, reduce everything down to a GE. */
12917 temp = gen_reg_rtx (compare_mode);
12918 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12923 temp = gen_reg_rtx (compare_mode);
12924 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12929 temp = gen_reg_rtx (compare_mode);
12930 emit_insn (gen_rtx_SET (VOIDmode, temp,
12931 gen_rtx_NEG (compare_mode,
12932 gen_rtx_ABS (compare_mode, op0))));
12937 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12938 temp = gen_reg_rtx (result_mode);
12939 emit_insn (gen_rtx_SET (VOIDmode, temp,
12940 gen_rtx_IF_THEN_ELSE (result_mode,
12941 gen_rtx_GE (VOIDmode,
12943 true_cond, false_cond)));
12944 false_cond = true_cond;
12947 temp = gen_reg_rtx (compare_mode);
12948 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12953 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12954 temp = gen_reg_rtx (result_mode);
12955 emit_insn (gen_rtx_SET (VOIDmode, temp,
12956 gen_rtx_IF_THEN_ELSE (result_mode,
12957 gen_rtx_GE (VOIDmode,
12959 true_cond, false_cond)));
12960 true_cond = false_cond;
12963 temp = gen_reg_rtx (compare_mode);
12964 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12969 gcc_unreachable ();
12972 emit_insn (gen_rtx_SET (VOIDmode, dest,
12973 gen_rtx_IF_THEN_ELSE (result_mode,
12974 gen_rtx_GE (VOIDmode,
12976 true_cond, false_cond)));
12980 /* Same as above, but for ints (isel). */
12983 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12985 rtx condition_rtx, cr;
12987 /* All isel implementations thus far are 32-bits. */
12988 if (GET_MODE (rs6000_compare_op0) != SImode)
12991 /* We still have to do the compare, because isel doesn't do a
12992 compare, it just looks at the CRx bits set by a previous compare
12994 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12995 cr = XEXP (condition_rtx, 0);
12997 if (GET_MODE (cr) == CCmode)
12998 emit_insn (gen_isel_signed (dest, condition_rtx,
12999 true_cond, false_cond, cr));
13001 emit_insn (gen_isel_unsigned (dest, condition_rtx,
13002 true_cond, false_cond, cr));
13008 output_isel (rtx *operands)
13010 enum rtx_code code;
13012 code = GET_CODE (operands[1]);
13013 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
13015 PUT_CODE (operands[1], reverse_condition (code));
13016 return "isel %0,%3,%2,%j1";
13019 return "isel %0,%2,%3,%j1";
13023 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
13025 enum machine_mode mode = GET_MODE (op0);
13029 if (code == SMAX || code == SMIN)
13034 if (code == SMAX || code == UMAX)
13035 target = emit_conditional_move (dest, c, op0, op1, mode,
13036 op0, op1, mode, 0);
13038 target = emit_conditional_move (dest, c, op0, op1, mode,
13039 op1, op0, mode, 0);
13040 gcc_assert (target);
13041 if (target != dest)
13042 emit_move_insn (dest, target);
13045 /* Emit instructions to perform a load-reserved/store-conditional operation.
13046 The operation performed is an atomic
13047 (set M (CODE:MODE M OP))
13048 If not NULL, BEFORE is atomically set to M before the operation, and
13049 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
13050 If SYNC_P then a memory barrier is emitted before the operation.
13051 Either OP or M may be wrapped in a NOT operation. */
13054 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
13055 rtx m, rtx op, rtx before_param, rtx after_param,
13058 enum machine_mode used_mode;
13059 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
13062 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13063 rtx shift = NULL_RTX;
13066 emit_insn (gen_memory_barrier ());
13068 if (GET_CODE (m) == NOT)
13069 used_m = XEXP (m, 0);
13073 /* If this is smaller than SImode, we'll have to use SImode with
13075 if (mode == QImode || mode == HImode)
13079 if (MEM_ALIGN (used_m) >= 32)
13082 if (BYTES_BIG_ENDIAN)
13083 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
13085 shift = GEN_INT (ishift);
13086 used_m = change_address (used_m, SImode, 0);
13090 rtx addrSI, aligned_addr;
13091 int shift_mask = mode == QImode ? 0x18 : 0x10;
13093 addrSI = gen_lowpart_common (SImode,
13094 force_reg (Pmode, XEXP (used_m, 0)));
13095 addrSI = force_reg (SImode, addrSI);
13096 shift = gen_reg_rtx (SImode);
13098 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13099 GEN_INT (shift_mask)));
13100 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13102 aligned_addr = expand_binop (Pmode, and_optab,
13104 GEN_INT (-4), NULL_RTX,
13105 1, OPTAB_LIB_WIDEN);
13106 used_m = change_address (used_m, SImode, aligned_addr);
13107 set_mem_align (used_m, 32);
13109 /* It's safe to keep the old alias set of USED_M, because
13110 the operation is atomic and only affects the original
13112 if (GET_CODE (m) == NOT)
13113 m = gen_rtx_NOT (SImode, used_m);
13117 if (GET_CODE (op) == NOT)
13119 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
13120 oldop = gen_rtx_NOT (SImode, oldop);
13123 oldop = lowpart_subreg (SImode, op, mode);
13129 newop = expand_binop (SImode, and_optab,
13130 oldop, GEN_INT (imask), NULL_RTX,
13131 1, OPTAB_LIB_WIDEN);
13132 emit_insn (gen_ashlsi3 (newop, newop, shift));
13136 newop = expand_binop (SImode, ior_optab,
13137 oldop, GEN_INT (~imask), NULL_RTX,
13138 1, OPTAB_LIB_WIDEN);
13139 emit_insn (gen_rotlsi3 (newop, newop, shift));
13147 newop = expand_binop (SImode, and_optab,
13148 oldop, GEN_INT (imask), NULL_RTX,
13149 1, OPTAB_LIB_WIDEN);
13150 emit_insn (gen_ashlsi3 (newop, newop, shift));
13152 mask = gen_reg_rtx (SImode);
13153 emit_move_insn (mask, GEN_INT (imask));
13154 emit_insn (gen_ashlsi3 (mask, mask, shift));
13157 newop = gen_rtx_PLUS (SImode, m, newop);
13159 newop = gen_rtx_MINUS (SImode, m, newop);
13160 newop = gen_rtx_AND (SImode, newop, mask);
13161 newop = gen_rtx_IOR (SImode, newop,
13162 gen_rtx_AND (SImode,
13163 gen_rtx_NOT (SImode, mask),
13169 gcc_unreachable ();
13172 if (GET_CODE (m) == NOT)
13176 mask = gen_reg_rtx (SImode);
13177 emit_move_insn (mask, GEN_INT (imask));
13178 emit_insn (gen_ashlsi3 (mask, mask, shift));
13180 xorm = gen_rtx_XOR (SImode, used_m, mask);
13181 /* Depending on the value of 'op', the XOR or the operation might
13182 be able to be simplified away. */
13183 newop = simplify_gen_binary (code, SImode, xorm, newop);
13186 used_mode = SImode;
13187 before = gen_reg_rtx (used_mode);
13188 after = gen_reg_rtx (used_mode);
13193 before = before_param;
13194 after = after_param;
13196 if (before == NULL_RTX)
13197 before = gen_reg_rtx (used_mode);
13198 if (after == NULL_RTX)
13199 after = gen_reg_rtx (used_mode);
13202 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
13203 && used_mode != mode)
13204 the_op = op; /* Computed above. */
13205 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
13206 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
13208 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
13210 set_after = gen_rtx_SET (VOIDmode, after, the_op);
13211 set_before = gen_rtx_SET (VOIDmode, before, used_m);
13212 set_atomic = gen_rtx_SET (VOIDmode, used_m,
13213 gen_rtx_UNSPEC (used_mode,
13214 gen_rtvec (1, the_op),
13216 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
13218 if ((code == PLUS || code == MINUS) && used_mode != mode)
13219 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
13220 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
13222 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
13223 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
13225 /* Shift and mask the return values properly. */
13226 if (used_mode != mode && before_param)
13228 emit_insn (gen_lshrsi3 (before, before, shift));
13229 convert_move (before_param, before, 1);
13232 if (used_mode != mode && after_param)
13234 emit_insn (gen_lshrsi3 (after, after, shift));
13235 convert_move (after_param, after, 1);
13238 /* The previous sequence will end with a branch that's dependent on
13239 the conditional store, so placing an isync will ensure that no
13240 other instructions (especially, no load or store instructions)
13241 can start before the atomic operation completes. */
13243 emit_insn (gen_isync ());
13246 /* A subroutine of the atomic operation splitters. Jump to LABEL if
13247 COND is true. Mark the jump as unlikely to be taken. */
13250 emit_unlikely_jump (rtx cond, rtx label)
13252 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
13255 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
13256 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
13257 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
13260 /* A subroutine of the atomic operation splitters. Emit a load-locked
13261 instruction in MODE. */
13264 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
13266 rtx (*fn) (rtx, rtx) = NULL;
13267 if (mode == SImode)
13268 fn = gen_load_locked_si;
13269 else if (mode == DImode)
13270 fn = gen_load_locked_di;
13271 emit_insn (fn (reg, mem));
13274 /* A subroutine of the atomic operation splitters. Emit a store-conditional
13275 instruction in MODE. */
13278 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
13280 rtx (*fn) (rtx, rtx, rtx) = NULL;
13281 if (mode == SImode)
13282 fn = gen_store_conditional_si;
13283 else if (mode == DImode)
13284 fn = gen_store_conditional_di;
13286 /* Emit sync before stwcx. to address PPC405 Erratum. */
13287 if (PPC405_ERRATUM77)
13288 emit_insn (gen_memory_barrier ());
13290 emit_insn (fn (res, mem, val));
13293 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
13294 to perform. MEM is the memory on which to operate. VAL is the second
13295 operand of the binary operator. BEFORE and AFTER are optional locations to
13296 return the value of MEM either before of after the operation. SCRATCH is
13297 a scratch register. */
13300 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
13301 rtx before, rtx after, rtx scratch)
13303 enum machine_mode mode = GET_MODE (mem);
13304 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13306 emit_insn (gen_memory_barrier ());
13308 label = gen_label_rtx ();
13309 emit_label (label);
13310 label = gen_rtx_LABEL_REF (VOIDmode, label);
13312 if (before == NULL_RTX)
13314 emit_load_locked (mode, before, mem);
13317 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
13318 else if (code == AND)
13319 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
13321 x = gen_rtx_fmt_ee (code, mode, before, val);
13323 if (after != NULL_RTX)
13324 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
13325 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13327 emit_store_conditional (mode, cond, mem, scratch);
13329 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13330 emit_unlikely_jump (x, label);
13332 emit_insn (gen_isync ());
13335 /* Expand an atomic compare and swap operation. MEM is the memory on which
13336 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
13337 value to be stored. SCRATCH is a scratch GPR. */
13340 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
13343 enum machine_mode mode = GET_MODE (mem);
13344 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13346 emit_insn (gen_memory_barrier ());
13348 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13349 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13350 emit_label (XEXP (label1, 0));
13352 emit_load_locked (mode, retval, mem);
13354 x = gen_rtx_COMPARE (CCmode, retval, oldval);
13355 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13357 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13358 emit_unlikely_jump (x, label2);
13360 emit_move_insn (scratch, newval);
13361 emit_store_conditional (mode, cond, mem, scratch);
13363 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13364 emit_unlikely_jump (x, label1);
13366 emit_insn (gen_isync ());
13367 emit_label (XEXP (label2, 0));
13370 /* Expand an atomic test and set operation. MEM is the memory on which
13371 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13374 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
13376 enum machine_mode mode = GET_MODE (mem);
13377 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13379 emit_insn (gen_memory_barrier ());
13381 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13382 emit_label (XEXP (label, 0));
13384 emit_load_locked (mode, retval, mem);
13385 emit_move_insn (scratch, val);
13386 emit_store_conditional (mode, cond, mem, scratch);
13388 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13389 emit_unlikely_jump (x, label);
13391 emit_insn (gen_isync ());
13395 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
13397 enum machine_mode mode = GET_MODE (mem);
13398 rtx addrSI, align, wdst, shift, mask;
13399 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
13400 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13402 /* Shift amount for subword relative to aligned word. */
13403 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
13404 shift = gen_reg_rtx (SImode);
13405 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13406 GEN_INT (shift_mask)));
13407 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13409 /* Shift and mask old value into position within word. */
13410 oldval = convert_modes (SImode, mode, oldval, 1);
13411 oldval = expand_binop (SImode, and_optab,
13412 oldval, GEN_INT (imask), NULL_RTX,
13413 1, OPTAB_LIB_WIDEN);
13414 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
13416 /* Shift and mask new value into position within word. */
13417 newval = convert_modes (SImode, mode, newval, 1);
13418 newval = expand_binop (SImode, and_optab,
13419 newval, GEN_INT (imask), NULL_RTX,
13420 1, OPTAB_LIB_WIDEN);
13421 emit_insn (gen_ashlsi3 (newval, newval, shift));
13423 /* Mask for insertion. */
13424 mask = gen_reg_rtx (SImode);
13425 emit_move_insn (mask, GEN_INT (imask));
13426 emit_insn (gen_ashlsi3 (mask, mask, shift));
13428 /* Address of aligned word containing subword. */
13429 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
13430 NULL_RTX, 1, OPTAB_LIB_WIDEN);
13431 mem = change_address (mem, SImode, align);
13432 set_mem_align (mem, 32);
13433 MEM_VOLATILE_P (mem) = 1;
13435 wdst = gen_reg_rtx (SImode);
13436 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
13437 oldval, newval, mem));
13439 emit_move_insn (dst, gen_lowpart (mode, wdst));
13443 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
13444 rtx oldval, rtx newval, rtx mem,
13447 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13449 emit_insn (gen_memory_barrier ());
13450 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13451 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13452 emit_label (XEXP (label1, 0));
13454 emit_load_locked (SImode, scratch, mem);
13456 /* Mask subword within loaded value for comparison with oldval.
13457 Use UNSPEC_AND to avoid clobber.*/
13458 emit_insn (gen_rtx_SET (SImode, dest,
13459 gen_rtx_UNSPEC (SImode,
13460 gen_rtvec (2, scratch, mask),
13463 x = gen_rtx_COMPARE (CCmode, dest, oldval);
13464 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13466 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13467 emit_unlikely_jump (x, label2);
13469 /* Clear subword within loaded value for insertion of new value. */
13470 emit_insn (gen_rtx_SET (SImode, scratch,
13471 gen_rtx_AND (SImode,
13472 gen_rtx_NOT (SImode, mask), scratch)));
13473 emit_insn (gen_iorsi3 (scratch, scratch, newval));
13474 emit_store_conditional (SImode, cond, mem, scratch);
13476 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13477 emit_unlikely_jump (x, label1);
13479 emit_insn (gen_isync ());
13480 emit_label (XEXP (label2, 0));
13484 /* Emit instructions to move SRC to DST. Called by splitters for
13485 multi-register moves. It will emit at most one instruction for
13486 each register that is accessed; that is, it won't emit li/lis pairs
13487 (or equivalent for 64-bit code). One of SRC or DST must be a hard
13491 rs6000_split_multireg_move (rtx dst, rtx src)
13493 /* The register number of the first register being moved. */
13495 /* The mode that is to be moved. */
13496 enum machine_mode mode;
13497 /* The mode that the move is being done in, and its size. */
13498 enum machine_mode reg_mode;
13500 /* The number of registers that will be moved. */
13503 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
13504 mode = GET_MODE (dst);
13505 nregs = hard_regno_nregs[reg][mode];
13506 if (FP_REGNO_P (reg))
13507 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
13508 else if (ALTIVEC_REGNO_P (reg))
13509 reg_mode = V16QImode;
13510 else if (TARGET_E500_DOUBLE && mode == TFmode)
13513 reg_mode = word_mode;
13514 reg_mode_size = GET_MODE_SIZE (reg_mode);
13516 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
13518 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
13520 /* Move register range backwards, if we might have destructive
13523 for (i = nregs - 1; i >= 0; i--)
13524 emit_insn (gen_rtx_SET (VOIDmode,
13525 simplify_gen_subreg (reg_mode, dst, mode,
13526 i * reg_mode_size),
13527 simplify_gen_subreg (reg_mode, src, mode,
13528 i * reg_mode_size)));
13534 bool used_update = false;
13536 if (MEM_P (src) && INT_REGNO_P (reg))
13540 if (GET_CODE (XEXP (src, 0)) == PRE_INC
13541 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
13544 breg = XEXP (XEXP (src, 0), 0);
13545 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
13546 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
13547 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
13548 emit_insn (TARGET_32BIT
13549 ? gen_addsi3 (breg, breg, delta_rtx)
13550 : gen_adddi3 (breg, breg, delta_rtx));
13551 src = replace_equiv_address (src, breg);
13553 else if (! rs6000_offsettable_memref_p (src))
13556 basereg = gen_rtx_REG (Pmode, reg);
13557 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
13558 src = replace_equiv_address (src, basereg);
13561 breg = XEXP (src, 0);
13562 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
13563 breg = XEXP (breg, 0);
13565 /* If the base register we are using to address memory is
13566 also a destination reg, then change that register last. */
13568 && REGNO (breg) >= REGNO (dst)
13569 && REGNO (breg) < REGNO (dst) + nregs)
13570 j = REGNO (breg) - REGNO (dst);
13573 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
13577 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
13578 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
13581 breg = XEXP (XEXP (dst, 0), 0);
13582 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
13583 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
13584 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
13586 /* We have to update the breg before doing the store.
13587 Use store with update, if available. */
13591 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
13592 emit_insn (TARGET_32BIT
13593 ? (TARGET_POWERPC64
13594 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
13595 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
13596 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
13597 used_update = true;
13600 emit_insn (TARGET_32BIT
13601 ? gen_addsi3 (breg, breg, delta_rtx)
13602 : gen_adddi3 (breg, breg, delta_rtx));
13603 dst = replace_equiv_address (dst, breg);
13606 gcc_assert (rs6000_offsettable_memref_p (dst));
13609 for (i = 0; i < nregs; i++)
13611 /* Calculate index to next subword. */
13616 /* If compiler already emitted move of first word by
13617 store with update, no need to do anything. */
13618 if (j == 0 && used_update)
13621 emit_insn (gen_rtx_SET (VOIDmode,
13622 simplify_gen_subreg (reg_mode, dst, mode,
13623 j * reg_mode_size),
13624 simplify_gen_subreg (reg_mode, src, mode,
13625 j * reg_mode_size)));
13631 /* This page contains routines that are used to determine what the
13632 function prologue and epilogue code will do and write them out. */
13634 /* Return the first fixed-point register that is required to be
13635 saved. 32 if none. */
13638 first_reg_to_save (void)
13642 /* Find lowest numbered live register. */
13643 for (first_reg = 13; first_reg <= 31; first_reg++)
13644 if (df_regs_ever_live_p (first_reg)
13645 && (! call_used_regs[first_reg]
13646 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
13647 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13648 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
13649 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
13654 && current_function_uses_pic_offset_table
13655 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
13656 return RS6000_PIC_OFFSET_TABLE_REGNUM;
13662 /* Similar, for FP regs. */
13665 first_fp_reg_to_save (void)
13669 /* Find lowest numbered live register. */
13670 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
13671 if (df_regs_ever_live_p (first_reg))
13677 /* Similar, for AltiVec regs. */
13680 first_altivec_reg_to_save (void)
13684 /* Stack frame remains as is unless we are in AltiVec ABI. */
13685 if (! TARGET_ALTIVEC_ABI)
13686 return LAST_ALTIVEC_REGNO + 1;
13688 /* On Darwin, the unwind routines are compiled without
13689 TARGET_ALTIVEC, and use save_world to save/restore the
13690 altivec registers when necessary. */
13691 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13692 && ! TARGET_ALTIVEC)
13693 return FIRST_ALTIVEC_REGNO + 20;
13695 /* Find lowest numbered live register. */
13696 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
13697 if (df_regs_ever_live_p (i))
13703 /* Return a 32-bit mask of the AltiVec registers we need to set in
13704 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13705 the 32-bit word is 0. */
13707 static unsigned int
13708 compute_vrsave_mask (void)
13710 unsigned int i, mask = 0;
13712 /* On Darwin, the unwind routines are compiled without
13713 TARGET_ALTIVEC, and use save_world to save/restore the
13714 call-saved altivec registers when necessary. */
13715 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13716 && ! TARGET_ALTIVEC)
13719 /* First, find out if we use _any_ altivec registers. */
13720 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13721 if (df_regs_ever_live_p (i))
13722 mask |= ALTIVEC_REG_BIT (i);
13727 /* Next, remove the argument registers from the set. These must
13728 be in the VRSAVE mask set by the caller, so we don't need to add
13729 them in again. More importantly, the mask we compute here is
13730 used to generate CLOBBERs in the set_vrsave insn, and we do not
13731 wish the argument registers to die. */
13732 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
13733 mask &= ~ALTIVEC_REG_BIT (i);
13735 /* Similarly, remove the return value from the set. */
13738 diddle_return_value (is_altivec_return_reg, &yes);
13740 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
13746 /* For a very restricted set of circumstances, we can cut down the
13747 size of prologues/epilogues by calling our own save/restore-the-world
13751 compute_save_world_info (rs6000_stack_t *info_ptr)
13753 info_ptr->world_save_p = 1;
13754 info_ptr->world_save_p
13755 = (WORLD_SAVE_P (info_ptr)
13756 && DEFAULT_ABI == ABI_DARWIN
13757 && ! (current_function_calls_setjmp && flag_exceptions)
13758 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
13759 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
13760 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
13761 && info_ptr->cr_save_p);
13763 /* This will not work in conjunction with sibcalls. Make sure there
13764 are none. (This check is expensive, but seldom executed.) */
13765 if (WORLD_SAVE_P (info_ptr))
13768 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
13769 if ( GET_CODE (insn) == CALL_INSN
13770 && SIBLING_CALL_P (insn))
13772 info_ptr->world_save_p = 0;
13777 if (WORLD_SAVE_P (info_ptr))
13779 /* Even if we're not touching VRsave, make sure there's room on the
13780 stack for it, if it looks like we're calling SAVE_WORLD, which
13781 will attempt to save it. */
13782 info_ptr->vrsave_size = 4;
13784 /* "Save" the VRsave register too if we're saving the world. */
13785 if (info_ptr->vrsave_mask == 0)
13786 info_ptr->vrsave_mask = compute_vrsave_mask ();
13788 /* Because the Darwin register save/restore routines only handle
13789 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13791 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13792 && (info_ptr->first_altivec_reg_save
13793 >= FIRST_SAVED_ALTIVEC_REGNO));
13800 is_altivec_return_reg (rtx reg, void *xyes)
13802 bool *yes = (bool *) xyes;
13803 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13808 /* Calculate the stack information for the current function. This is
13809 complicated by having two separate calling sequences, the AIX calling
13810 sequence and the V.4 calling sequence.
13812 AIX (and Darwin/Mac OS X) stack frames look like:
13814 SP----> +---------------------------------------+
13815 | back chain to caller | 0 0
13816 +---------------------------------------+
13817 | saved CR | 4 8 (8-11)
13818 +---------------------------------------+
13820 +---------------------------------------+
13821 | reserved for compilers | 12 24
13822 +---------------------------------------+
13823 | reserved for binders | 16 32
13824 +---------------------------------------+
13825 | saved TOC pointer | 20 40
13826 +---------------------------------------+
13827 | Parameter save area (P) | 24 48
13828 +---------------------------------------+
13829 | Alloca space (A) | 24+P etc.
13830 +---------------------------------------+
13831 | Local variable space (L) | 24+P+A
13832 +---------------------------------------+
13833 | Float/int conversion temporary (X) | 24+P+A+L
13834 +---------------------------------------+
13835 | Save area for AltiVec registers (W) | 24+P+A+L+X
13836 +---------------------------------------+
13837 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13838 +---------------------------------------+
13839 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13840 +---------------------------------------+
13841 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13842 +---------------------------------------+
13843 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13844 +---------------------------------------+
13845 old SP->| back chain to caller's caller |
13846 +---------------------------------------+
13848 The required alignment for AIX configurations is two words (i.e., 8
13852 V.4 stack frames look like:
13854 SP----> +---------------------------------------+
13855 | back chain to caller | 0
13856 +---------------------------------------+
13857 | caller's saved LR | 4
13858 +---------------------------------------+
13859 | Parameter save area (P) | 8
13860 +---------------------------------------+
13861 | Alloca space (A) | 8+P
13862 +---------------------------------------+
13863 | Varargs save area (V) | 8+P+A
13864 +---------------------------------------+
13865 | Local variable space (L) | 8+P+A+V
13866 +---------------------------------------+
13867 | Float/int conversion temporary (X) | 8+P+A+V+L
13868 +---------------------------------------+
13869 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13870 +---------------------------------------+
13871 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13872 +---------------------------------------+
13873 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13874 +---------------------------------------+
13875 | SPE: area for 64-bit GP registers |
13876 +---------------------------------------+
13877 | SPE alignment padding |
13878 +---------------------------------------+
13879 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13880 +---------------------------------------+
13881 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13882 +---------------------------------------+
13883 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13884 +---------------------------------------+
13885 old SP->| back chain to caller's caller |
13886 +---------------------------------------+
13888 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13889 given. (But note below and in sysv4.h that we require only 8 and
13890 may round up the size of our stack frame anyways. The historical
13891 reason is early versions of powerpc-linux which didn't properly
13892 align the stack at program startup. A happy side-effect is that
13893 -mno-eabi libraries can be used with -meabi programs.)
13895 The EABI configuration defaults to the V.4 layout. However,
13896 the stack alignment requirements may differ. If -mno-eabi is not
13897 given, the required stack alignment is 8 bytes; if -mno-eabi is
13898 given, the required alignment is 16 bytes. (But see V.4 comment
13901 #ifndef ABI_STACK_BOUNDARY
13902 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13905 static rs6000_stack_t *
13906 rs6000_stack_info (void)
13908 static rs6000_stack_t info;
13909 rs6000_stack_t *info_ptr = &info;
13910 int reg_size = TARGET_32BIT ? 4 : 8;
13914 HOST_WIDE_INT non_fixed_size;
13916 memset (&info, 0, sizeof (info));
13920 /* Cache value so we don't rescan instruction chain over and over. */
13921 if (cfun->machine->insn_chain_scanned_p == 0)
13922 cfun->machine->insn_chain_scanned_p
13923 = spe_func_has_64bit_regs_p () + 1;
13924 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13927 /* Select which calling sequence. */
13928 info_ptr->abi = DEFAULT_ABI;
13930 /* Calculate which registers need to be saved & save area size. */
13931 info_ptr->first_gp_reg_save = first_reg_to_save ();
13932 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13933 even if it currently looks like we won't. Reload may need it to
13934 get at a constant; if so, it will have already created a constant
13935 pool entry for it. */
13936 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13937 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13938 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13939 && current_function_uses_const_pool
13940 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13941 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
13943 first_gp = info_ptr->first_gp_reg_save;
13945 info_ptr->gp_size = reg_size * (32 - first_gp);
13947 /* For the SPE, we have an additional upper 32-bits on each GPR.
13948 Ideally we should save the entire 64-bits only when the upper
13949 half is used in SIMD instructions. Since we only record
13950 registers live (not the size they are used in), this proves
13951 difficult because we'd have to traverse the instruction chain at
13952 the right time, taking reload into account. This is a real pain,
13953 so we opt to save the GPRs in 64-bits always if but one register
13954 gets used in 64-bits. Otherwise, all the registers in the frame
13955 get saved in 32-bits.
13957 So... since when we save all GPRs (except the SP) in 64-bits, the
13958 traditional GP save area will be empty. */
13959 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13960 info_ptr->gp_size = 0;
13962 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13963 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13965 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13966 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13967 - info_ptr->first_altivec_reg_save);
13969 /* Does this function call anything? */
13970 info_ptr->calls_p = (! current_function_is_leaf
13971 || cfun->machine->ra_needs_full_frame);
13973 /* Determine if we need to save the link register. */
13974 if ((DEFAULT_ABI == ABI_AIX
13975 && current_function_profile
13976 && !TARGET_PROFILE_KERNEL)
13977 #ifdef TARGET_RELOCATABLE
13978 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13980 || (info_ptr->first_fp_reg_save != 64
13981 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13982 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13983 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13984 || info_ptr->calls_p
13985 || rs6000_ra_ever_killed ())
13987 info_ptr->lr_save_p = 1;
13988 df_set_regs_ever_live (LR_REGNO, true);
13991 /* Determine if we need to save the condition code registers. */
13992 if (df_regs_ever_live_p (CR2_REGNO)
13993 || df_regs_ever_live_p (CR3_REGNO)
13994 || df_regs_ever_live_p (CR4_REGNO))
13996 info_ptr->cr_save_p = 1;
13997 if (DEFAULT_ABI == ABI_V4)
13998 info_ptr->cr_size = reg_size;
14001 /* If the current function calls __builtin_eh_return, then we need
14002 to allocate stack space for registers that will hold data for
14003 the exception handler. */
14004 if (current_function_calls_eh_return)
14007 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
14010 /* SPE saves EH registers in 64-bits. */
14011 ehrd_size = i * (TARGET_SPE_ABI
14012 && info_ptr->spe_64bit_regs_used != 0
14013 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
14018 /* Determine various sizes. */
14019 info_ptr->reg_size = reg_size;
14020 info_ptr->fixed_size = RS6000_SAVE_AREA;
14021 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
14022 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
14023 TARGET_ALTIVEC ? 16 : 8);
14024 if (FRAME_GROWS_DOWNWARD)
14025 info_ptr->vars_size
14026 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
14027 + info_ptr->parm_size,
14028 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
14029 - (info_ptr->fixed_size + info_ptr->vars_size
14030 + info_ptr->parm_size);
14032 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14033 info_ptr->spe_gp_size = 8 * (32 - first_gp);
14035 info_ptr->spe_gp_size = 0;
14037 if (TARGET_ALTIVEC_ABI)
14038 info_ptr->vrsave_mask = compute_vrsave_mask ();
14040 info_ptr->vrsave_mask = 0;
14042 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
14043 info_ptr->vrsave_size = 4;
14045 info_ptr->vrsave_size = 0;
14047 compute_save_world_info (info_ptr);
14049 /* Calculate the offsets. */
14050 switch (DEFAULT_ABI)
14054 gcc_unreachable ();
14058 info_ptr->fp_save_offset = - info_ptr->fp_size;
14059 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14061 if (TARGET_ALTIVEC_ABI)
14063 info_ptr->vrsave_save_offset
14064 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
14066 /* Align stack so vector save area is on a quadword boundary.
14067 The padding goes above the vectors. */
14068 if (info_ptr->altivec_size != 0)
14069 info_ptr->altivec_padding_size
14070 = info_ptr->vrsave_save_offset & 0xF;
14072 info_ptr->altivec_padding_size = 0;
14074 info_ptr->altivec_save_offset
14075 = info_ptr->vrsave_save_offset
14076 - info_ptr->altivec_padding_size
14077 - info_ptr->altivec_size;
14078 gcc_assert (info_ptr->altivec_size == 0
14079 || info_ptr->altivec_save_offset % 16 == 0);
14081 /* Adjust for AltiVec case. */
14082 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
14085 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
14086 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
14087 info_ptr->lr_save_offset = 2*reg_size;
14091 info_ptr->fp_save_offset = - info_ptr->fp_size;
14092 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14093 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
14095 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14097 /* Align stack so SPE GPR save area is aligned on a
14098 double-word boundary. */
14099 if (info_ptr->spe_gp_size != 0)
14100 info_ptr->spe_padding_size
14101 = 8 - (-info_ptr->cr_save_offset % 8);
14103 info_ptr->spe_padding_size = 0;
14105 info_ptr->spe_gp_save_offset
14106 = info_ptr->cr_save_offset
14107 - info_ptr->spe_padding_size
14108 - info_ptr->spe_gp_size;
14110 /* Adjust for SPE case. */
14111 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
14113 else if (TARGET_ALTIVEC_ABI)
14115 info_ptr->vrsave_save_offset
14116 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
14118 /* Align stack so vector save area is on a quadword boundary. */
14119 if (info_ptr->altivec_size != 0)
14120 info_ptr->altivec_padding_size
14121 = 16 - (-info_ptr->vrsave_save_offset % 16);
14123 info_ptr->altivec_padding_size = 0;
14125 info_ptr->altivec_save_offset
14126 = info_ptr->vrsave_save_offset
14127 - info_ptr->altivec_padding_size
14128 - info_ptr->altivec_size;
14130 /* Adjust for AltiVec case. */
14131 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
14134 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
14135 info_ptr->ehrd_offset -= ehrd_size;
14136 info_ptr->lr_save_offset = reg_size;
14140 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
14141 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
14142 + info_ptr->gp_size
14143 + info_ptr->altivec_size
14144 + info_ptr->altivec_padding_size
14145 + info_ptr->spe_gp_size
14146 + info_ptr->spe_padding_size
14148 + info_ptr->cr_size
14149 + info_ptr->vrsave_size,
14152 non_fixed_size = (info_ptr->vars_size
14153 + info_ptr->parm_size
14154 + info_ptr->save_size);
14156 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
14157 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
14159 /* Determine if we need to allocate any stack frame:
14161 For AIX we need to push the stack if a frame pointer is needed
14162 (because the stack might be dynamically adjusted), if we are
14163 debugging, if we make calls, or if the sum of fp_save, gp_save,
14164 and local variables are more than the space needed to save all
14165 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
14166 + 18*8 = 288 (GPR13 reserved).
14168 For V.4 we don't have the stack cushion that AIX uses, but assume
14169 that the debugger can handle stackless frames. */
14171 if (info_ptr->calls_p)
14172 info_ptr->push_p = 1;
14174 else if (DEFAULT_ABI == ABI_V4)
14175 info_ptr->push_p = non_fixed_size != 0;
14177 else if (frame_pointer_needed)
14178 info_ptr->push_p = 1;
14180 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
14181 info_ptr->push_p = 1;
14184 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
14186 /* Zero offsets if we're not saving those registers. */
14187 if (info_ptr->fp_size == 0)
14188 info_ptr->fp_save_offset = 0;
14190 if (info_ptr->gp_size == 0)
14191 info_ptr->gp_save_offset = 0;
14193 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
14194 info_ptr->altivec_save_offset = 0;
14196 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
14197 info_ptr->vrsave_save_offset = 0;
14199 if (! TARGET_SPE_ABI
14200 || info_ptr->spe_64bit_regs_used == 0
14201 || info_ptr->spe_gp_size == 0)
14202 info_ptr->spe_gp_save_offset = 0;
14204 if (! info_ptr->lr_save_p)
14205 info_ptr->lr_save_offset = 0;
14207 if (! info_ptr->cr_save_p)
14208 info_ptr->cr_save_offset = 0;
14213 /* Return true if the current function uses any GPRs in 64-bit SIMD
14217 spe_func_has_64bit_regs_p (void)
14221 /* Functions that save and restore all the call-saved registers will
14222 need to save/restore the registers in 64-bits. */
14223 if (current_function_calls_eh_return
14224 || current_function_calls_setjmp
14225 || current_function_has_nonlocal_goto)
14228 insns = get_insns ();
14230 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
14236 /* FIXME: This should be implemented with attributes...
14238 (set_attr "spe64" "true")....then,
14239 if (get_spe64(insn)) return true;
14241 It's the only reliable way to do the stuff below. */
14243 i = PATTERN (insn);
14244 if (GET_CODE (i) == SET)
14246 enum machine_mode mode = GET_MODE (SET_SRC (i));
14248 if (SPE_VECTOR_MODE (mode))
14250 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
14260 debug_stack_info (rs6000_stack_t *info)
14262 const char *abi_string;
14265 info = rs6000_stack_info ();
14267 fprintf (stderr, "\nStack information for function %s:\n",
14268 ((current_function_decl && DECL_NAME (current_function_decl))
14269 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
14274 default: abi_string = "Unknown"; break;
14275 case ABI_NONE: abi_string = "NONE"; break;
14276 case ABI_AIX: abi_string = "AIX"; break;
14277 case ABI_DARWIN: abi_string = "Darwin"; break;
14278 case ABI_V4: abi_string = "V.4"; break;
14281 fprintf (stderr, "\tABI = %5s\n", abi_string);
14283 if (TARGET_ALTIVEC_ABI)
14284 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
14286 if (TARGET_SPE_ABI)
14287 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
14289 if (info->first_gp_reg_save != 32)
14290 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
14292 if (info->first_fp_reg_save != 64)
14293 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
14295 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
14296 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
14297 info->first_altivec_reg_save);
14299 if (info->lr_save_p)
14300 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
14302 if (info->cr_save_p)
14303 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
14305 if (info->vrsave_mask)
14306 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
14309 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
14312 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
14314 if (info->gp_save_offset)
14315 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
14317 if (info->fp_save_offset)
14318 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
14320 if (info->altivec_save_offset)
14321 fprintf (stderr, "\taltivec_save_offset = %5d\n",
14322 info->altivec_save_offset);
14324 if (info->spe_gp_save_offset)
14325 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
14326 info->spe_gp_save_offset);
14328 if (info->vrsave_save_offset)
14329 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
14330 info->vrsave_save_offset);
14332 if (info->lr_save_offset)
14333 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
14335 if (info->cr_save_offset)
14336 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
14338 if (info->varargs_save_offset)
14339 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
14341 if (info->total_size)
14342 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14345 if (info->vars_size)
14346 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14349 if (info->parm_size)
14350 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
14352 if (info->fixed_size)
14353 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
14356 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
14358 if (info->spe_gp_size)
14359 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
14362 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
14364 if (info->altivec_size)
14365 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
14367 if (info->vrsave_size)
14368 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
14370 if (info->altivec_padding_size)
14371 fprintf (stderr, "\taltivec_padding_size= %5d\n",
14372 info->altivec_padding_size);
14374 if (info->spe_padding_size)
14375 fprintf (stderr, "\tspe_padding_size = %5d\n",
14376 info->spe_padding_size);
14379 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
14381 if (info->save_size)
14382 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
14384 if (info->reg_size != 4)
14385 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
14387 fprintf (stderr, "\n");
14391 rs6000_return_addr (int count, rtx frame)
14393 /* Currently we don't optimize very well between prolog and body
14394 code and for PIC code the code can be actually quite bad, so
14395 don't try to be too clever here. */
14396 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
14398 cfun->machine->ra_needs_full_frame = 1;
14405 plus_constant (copy_to_reg
14406 (gen_rtx_MEM (Pmode,
14407 memory_address (Pmode, frame))),
14408 RETURN_ADDRESS_OFFSET)));
14411 cfun->machine->ra_need_lr = 1;
14412 return get_hard_reg_initial_val (Pmode, LR_REGNO);
14415 /* Say whether a function is a candidate for sibcall handling or not.
14416 We do not allow indirect calls to be optimized into sibling calls.
14417 Also, we can't do it if there are any vector parameters; there's
14418 nowhere to put the VRsave code so it works; note that functions with
14419 vector parameters are required to have a prototype, so the argument
14420 type info must be available here. (The tail recursion case can work
14421 with vector parameters, but there's no way to distinguish here.) */
14423 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
14428 if (TARGET_ALTIVEC_VRSAVE)
14430 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
14431 type; type = TREE_CHAIN (type))
14433 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
14437 if (DEFAULT_ABI == ABI_DARWIN
14438 || ((*targetm.binds_local_p) (decl)
14439 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
14441 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
14443 if (!lookup_attribute ("longcall", attr_list)
14444 || lookup_attribute ("shortcall", attr_list))
14451 /* NULL if INSN insn is valid within a low-overhead loop.
14452 Otherwise return why doloop cannot be applied.
14453 PowerPC uses the COUNT register for branch on table instructions. */
14455 static const char *
14456 rs6000_invalid_within_doloop (const_rtx insn)
14459 return "Function call in the loop.";
14462 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
14463 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
14464 return "Computed branch in the loop.";
14470 rs6000_ra_ever_killed (void)
14476 if (current_function_is_thunk)
14479 /* regs_ever_live has LR marked as used if any sibcalls are present,
14480 but this should not force saving and restoring in the
14481 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
14482 clobbers LR, so that is inappropriate. */
14484 /* Also, the prologue can generate a store into LR that
14485 doesn't really count, like this:
14488 bcl to set PIC register
14492 When we're called from the epilogue, we need to avoid counting
14493 this as a store. */
14495 push_topmost_sequence ();
14496 top = get_insns ();
14497 pop_topmost_sequence ();
14498 reg = gen_rtx_REG (Pmode, LR_REGNO);
14500 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
14506 if (!SIBLING_CALL_P (insn))
14509 else if (find_regno_note (insn, REG_INC, LR_REGNO))
14511 else if (set_of (reg, insn) != NULL_RTX
14512 && !prologue_epilogue_contains (insn))
14519 /* Emit instructions needed to load the TOC register.
14520 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14521 a constant pool; or for SVR4 -fpic. */
14524 rs6000_emit_load_toc_table (int fromprolog)
14527 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
14529 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
14532 rtx lab, tmp1, tmp2, got;
14534 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14535 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14537 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14539 got = rs6000_got_sym ();
14540 tmp1 = tmp2 = dest;
14543 tmp1 = gen_reg_rtx (Pmode);
14544 tmp2 = gen_reg_rtx (Pmode);
14546 emit_insn (gen_load_toc_v4_PIC_1 (lab));
14547 emit_move_insn (tmp1,
14548 gen_rtx_REG (Pmode, LR_REGNO));
14549 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
14550 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
14552 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
14554 emit_insn (gen_load_toc_v4_pic_si ());
14555 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
14557 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
14560 rtx temp0 = (fromprolog
14561 ? gen_rtx_REG (Pmode, 0)
14562 : gen_reg_rtx (Pmode));
14568 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14569 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14571 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
14572 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14574 emit_insn (gen_load_toc_v4_PIC_1 (symF));
14575 emit_move_insn (dest,
14576 gen_rtx_REG (Pmode, LR_REGNO));
14577 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
14583 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14584 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
14585 emit_move_insn (dest,
14586 gen_rtx_REG (Pmode, LR_REGNO));
14587 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
14589 emit_insn (gen_addsi3 (dest, temp0, dest));
14591 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
14593 /* This is for AIX code running in non-PIC ELF32. */
14596 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
14597 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14599 emit_insn (gen_elf_high (dest, realsym));
14600 emit_insn (gen_elf_low (dest, dest, realsym));
14604 gcc_assert (DEFAULT_ABI == ABI_AIX);
14607 emit_insn (gen_load_toc_aix_si (dest));
14609 emit_insn (gen_load_toc_aix_di (dest));
14613 /* Emit instructions to restore the link register after determining where
14614 its value has been stored. */
14617 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
14619 rs6000_stack_t *info = rs6000_stack_info ();
14622 operands[0] = source;
14623 operands[1] = scratch;
14625 if (info->lr_save_p)
14627 rtx frame_rtx = stack_pointer_rtx;
14628 HOST_WIDE_INT sp_offset = 0;
14631 if (frame_pointer_needed
14632 || current_function_calls_alloca
14633 || info->total_size > 32767)
14635 tmp = gen_frame_mem (Pmode, frame_rtx);
14636 emit_move_insn (operands[1], tmp);
14637 frame_rtx = operands[1];
14639 else if (info->push_p)
14640 sp_offset = info->total_size;
14642 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14643 tmp = gen_frame_mem (Pmode, tmp);
14644 emit_move_insn (tmp, operands[0]);
14647 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
14650 static GTY(()) alias_set_type set = -1;
14653 get_TOC_alias_set (void)
14656 set = new_alias_set ();
14660 /* This returns nonzero if the current function uses the TOC. This is
14661 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14662 is generated by the ABI_V4 load_toc_* patterns. */
14669 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14672 rtx pat = PATTERN (insn);
14675 if (GET_CODE (pat) == PARALLEL)
14676 for (i = 0; i < XVECLEN (pat, 0); i++)
14678 rtx sub = XVECEXP (pat, 0, i);
14679 if (GET_CODE (sub) == USE)
14681 sub = XEXP (sub, 0);
14682 if (GET_CODE (sub) == UNSPEC
14683 && XINT (sub, 1) == UNSPEC_TOC)
14693 create_TOC_reference (rtx symbol)
14695 if (!can_create_pseudo_p ())
14696 df_set_regs_ever_live (TOC_REGISTER, true);
14697 return gen_rtx_PLUS (Pmode,
14698 gen_rtx_REG (Pmode, TOC_REGISTER),
14699 gen_rtx_CONST (Pmode,
14700 gen_rtx_MINUS (Pmode, symbol,
14701 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
14704 /* If _Unwind_* has been called from within the same module,
14705 toc register is not guaranteed to be saved to 40(1) on function
14706 entry. Save it there in that case. */
14709 rs6000_aix_emit_builtin_unwind_init (void)
14712 rtx stack_top = gen_reg_rtx (Pmode);
14713 rtx opcode_addr = gen_reg_rtx (Pmode);
14714 rtx opcode = gen_reg_rtx (SImode);
14715 rtx tocompare = gen_reg_rtx (SImode);
14716 rtx no_toc_save_needed = gen_label_rtx ();
14718 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
14719 emit_move_insn (stack_top, mem);
14721 mem = gen_frame_mem (Pmode,
14722 gen_rtx_PLUS (Pmode, stack_top,
14723 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
14724 emit_move_insn (opcode_addr, mem);
14725 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
14726 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
14727 : 0xE8410028, SImode));
14729 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
14730 SImode, NULL_RTX, NULL_RTX,
14731 no_toc_save_needed);
14733 mem = gen_frame_mem (Pmode,
14734 gen_rtx_PLUS (Pmode, stack_top,
14735 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
14736 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
14737 emit_label (no_toc_save_needed);
14740 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14741 and the change to the stack pointer. */
14744 rs6000_emit_stack_tie (void)
14746 rtx mem = gen_frame_mem (BLKmode,
14747 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14749 emit_insn (gen_stack_tie (mem));
14752 /* Emit the correct code for allocating stack space, as insns.
14753 If COPY_R12, make sure a copy of the old frame is left in r12.
14754 The generated code may use hard register 0 as a temporary. */
14757 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14760 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14761 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14762 rtx todec = gen_int_mode (-size, Pmode);
14764 if (INTVAL (todec) != -size)
14766 warning (0, "stack frame too large");
14767 emit_insn (gen_trap ());
14771 if (current_function_limit_stack)
14773 if (REG_P (stack_limit_rtx)
14774 && REGNO (stack_limit_rtx) > 1
14775 && REGNO (stack_limit_rtx) <= 31)
14777 emit_insn (TARGET_32BIT
14778 ? gen_addsi3 (tmp_reg,
14781 : gen_adddi3 (tmp_reg,
14785 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14788 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14790 && DEFAULT_ABI == ABI_V4)
14792 rtx toload = gen_rtx_CONST (VOIDmode,
14793 gen_rtx_PLUS (Pmode,
14797 emit_insn (gen_elf_high (tmp_reg, toload));
14798 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14799 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14803 warning (0, "stack limit expression is not supported");
14806 if (copy_r12 || ! TARGET_UPDATE)
14807 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14813 /* Need a note here so that try_split doesn't get confused. */
14814 if (get_last_insn () == NULL_RTX)
14815 emit_note (NOTE_INSN_DELETED);
14816 insn = emit_move_insn (tmp_reg, todec);
14817 try_split (PATTERN (insn), insn, 0);
14821 insn = emit_insn (TARGET_32BIT
14822 ? gen_movsi_update (stack_reg, stack_reg,
14824 : gen_movdi_di_update (stack_reg, stack_reg,
14825 todec, stack_reg));
14829 insn = emit_insn (TARGET_32BIT
14830 ? gen_addsi3 (stack_reg, stack_reg, todec)
14831 : gen_adddi3 (stack_reg, stack_reg, todec));
14832 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14833 gen_rtx_REG (Pmode, 12));
14836 RTX_FRAME_RELATED_P (insn) = 1;
14838 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14839 gen_rtx_SET (VOIDmode, stack_reg,
14840 gen_rtx_PLUS (Pmode, stack_reg,
14845 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14846 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14847 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14848 deduce these equivalences by itself so it wasn't necessary to hold
14849 its hand so much. */
14852 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14853 rtx reg2, rtx rreg)
14857 /* copy_rtx will not make unique copies of registers, so we need to
14858 ensure we don't have unwanted sharing here. */
14860 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14863 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14865 real = copy_rtx (PATTERN (insn));
14867 if (reg2 != NULL_RTX)
14868 real = replace_rtx (real, reg2, rreg);
14870 real = replace_rtx (real, reg,
14871 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14872 STACK_POINTER_REGNUM),
14875 /* We expect that 'real' is either a SET or a PARALLEL containing
14876 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14877 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14879 if (GET_CODE (real) == SET)
14883 temp = simplify_rtx (SET_SRC (set));
14885 SET_SRC (set) = temp;
14886 temp = simplify_rtx (SET_DEST (set));
14888 SET_DEST (set) = temp;
14889 if (GET_CODE (SET_DEST (set)) == MEM)
14891 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14893 XEXP (SET_DEST (set), 0) = temp;
14900 gcc_assert (GET_CODE (real) == PARALLEL);
14901 for (i = 0; i < XVECLEN (real, 0); i++)
14902 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14904 rtx set = XVECEXP (real, 0, i);
14906 temp = simplify_rtx (SET_SRC (set));
14908 SET_SRC (set) = temp;
14909 temp = simplify_rtx (SET_DEST (set));
14911 SET_DEST (set) = temp;
14912 if (GET_CODE (SET_DEST (set)) == MEM)
14914 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14916 XEXP (SET_DEST (set), 0) = temp;
14918 RTX_FRAME_RELATED_P (set) = 1;
14923 real = spe_synthesize_frame_save (real);
14925 RTX_FRAME_RELATED_P (insn) = 1;
14926 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14931 /* Given an SPE frame note, return a PARALLEL of SETs with the
14932 original note, plus a synthetic register save. */
14935 spe_synthesize_frame_save (rtx real)
14937 rtx synth, offset, reg, real2;
14939 if (GET_CODE (real) != SET
14940 || GET_MODE (SET_SRC (real)) != V2SImode)
14943 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14944 frame related note. The parallel contains a set of the register
14945 being saved, and another set to a synthetic register (n+1200).
14946 This is so we can differentiate between 64-bit and 32-bit saves.
14947 Words cannot describe this nastiness. */
14949 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14950 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14951 && GET_CODE (SET_SRC (real)) == REG);
14954 (set (mem (plus (reg x) (const y)))
14957 (set (mem (plus (reg x) (const y+4)))
14961 real2 = copy_rtx (real);
14962 PUT_MODE (SET_DEST (real2), SImode);
14963 reg = SET_SRC (real2);
14964 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14965 synth = copy_rtx (real2);
14967 if (BYTES_BIG_ENDIAN)
14969 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14970 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14973 reg = SET_SRC (synth);
14975 synth = replace_rtx (synth, reg,
14976 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14978 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14979 synth = replace_rtx (synth, offset,
14980 GEN_INT (INTVAL (offset)
14981 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14983 RTX_FRAME_RELATED_P (synth) = 1;
14984 RTX_FRAME_RELATED_P (real2) = 1;
14985 if (BYTES_BIG_ENDIAN)
14986 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14988 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14993 /* Returns an insn that has a vrsave set operation with the
14994 appropriate CLOBBERs. */
14997 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
15000 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
15001 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15004 = gen_rtx_SET (VOIDmode,
15006 gen_rtx_UNSPEC_VOLATILE (SImode,
15007 gen_rtvec (2, reg, vrsave),
15008 UNSPECV_SET_VRSAVE));
15012 /* We need to clobber the registers in the mask so the scheduler
15013 does not move sets to VRSAVE before sets of AltiVec registers.
15015 However, if the function receives nonlocal gotos, reload will set
15016 all call saved registers live. We will end up with:
15018 (set (reg 999) (mem))
15019 (parallel [ (set (reg vrsave) (unspec blah))
15020 (clobber (reg 999))])
15022 The clobber will cause the store into reg 999 to be dead, and
15023 flow will attempt to delete an epilogue insn. In this case, we
15024 need an unspec use/set of the register. */
15026 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
15027 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15029 if (!epiloguep || call_used_regs [i])
15030 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
15031 gen_rtx_REG (V4SImode, i));
15034 rtx reg = gen_rtx_REG (V4SImode, i);
15037 = gen_rtx_SET (VOIDmode,
15039 gen_rtx_UNSPEC (V4SImode,
15040 gen_rtvec (1, reg), 27));
15044 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
15046 for (i = 0; i < nclobs; ++i)
15047 XVECEXP (insn, 0, i) = clobs[i];
15052 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
15053 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
15056 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
15057 unsigned int regno, int offset, HOST_WIDE_INT total_size)
15059 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
15060 rtx replacea, replaceb;
15062 int_rtx = GEN_INT (offset);
15064 /* Some cases that need register indexed addressing. */
15065 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
15066 || (TARGET_E500_DOUBLE && mode == DFmode)
15068 && SPE_VECTOR_MODE (mode)
15069 && !SPE_CONST_OFFSET_OK (offset)))
15071 /* Whomever calls us must make sure r11 is available in the
15072 flow path of instructions in the prologue. */
15073 offset_rtx = gen_rtx_REG (Pmode, 11);
15074 emit_move_insn (offset_rtx, int_rtx);
15076 replacea = offset_rtx;
15077 replaceb = int_rtx;
15081 offset_rtx = int_rtx;
15082 replacea = NULL_RTX;
15083 replaceb = NULL_RTX;
15086 reg = gen_rtx_REG (mode, regno);
15087 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
15088 mem = gen_frame_mem (mode, addr);
15090 insn = emit_move_insn (mem, reg);
15092 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
15095 /* Emit an offset memory reference suitable for a frame store, while
15096 converting to a valid addressing mode. */
15099 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
15101 rtx int_rtx, offset_rtx;
15103 int_rtx = GEN_INT (offset);
15105 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
15106 || (TARGET_E500_DOUBLE && mode == DFmode))
15108 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15109 emit_move_insn (offset_rtx, int_rtx);
15112 offset_rtx = int_rtx;
15114 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
15117 /* Look for user-defined global regs. We should not save and restore these,
15118 and cannot use stmw/lmw if there are any in its range. */
15121 no_global_regs_above (int first_greg)
15124 for (i = 0; i < 32 - first_greg; i++)
15125 if (global_regs[first_greg + i])
15130 #ifndef TARGET_FIX_AND_CONTINUE
15131 #define TARGET_FIX_AND_CONTINUE 0
15134 /* Determine whether the gp REG is really used. */
15137 rs6000_reg_live_or_pic_offset_p (int reg)
15139 return ((df_regs_ever_live_p (reg)
15140 && (!call_used_regs[reg]
15141 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
15142 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15143 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
15144 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15145 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
15148 /* Emit function prologue as insns. */
15151 rs6000_emit_prologue (void)
15153 rs6000_stack_t *info = rs6000_stack_info ();
15154 enum machine_mode reg_mode = Pmode;
15155 int reg_size = TARGET_32BIT ? 4 : 8;
15156 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
15157 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
15158 rtx frame_reg_rtx = sp_reg_rtx;
15159 rtx cr_save_rtx = NULL_RTX;
15161 int saving_FPRs_inline;
15162 int using_store_multiple;
15163 HOST_WIDE_INT sp_offset = 0;
15165 if (TARGET_FIX_AND_CONTINUE)
15167 /* gdb on darwin arranges to forward a function from the old
15168 address by modifying the first 5 instructions of the function
15169 to branch to the overriding function. This is necessary to
15170 permit function pointers that point to the old function to
15171 actually forward to the new function. */
15172 emit_insn (gen_nop ());
15173 emit_insn (gen_nop ());
15174 emit_insn (gen_nop ());
15175 emit_insn (gen_nop ());
15176 emit_insn (gen_nop ());
15179 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15181 reg_mode = V2SImode;
15185 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15186 && (!TARGET_SPE_ABI
15187 || info->spe_64bit_regs_used == 0)
15188 && info->first_gp_reg_save < 31
15189 && no_global_regs_above (info->first_gp_reg_save));
15190 saving_FPRs_inline = (info->first_fp_reg_save == 64
15191 || FP_SAVE_INLINE (info->first_fp_reg_save)
15192 || current_function_calls_eh_return
15193 || cfun->machine->ra_need_lr);
15195 /* For V.4, update stack before we do any saving and set back pointer. */
15196 if (! WORLD_SAVE_P (info)
15198 && (DEFAULT_ABI == ABI_V4
15199 || current_function_calls_eh_return))
15201 if (info->total_size < 32767)
15202 sp_offset = info->total_size;
15204 frame_reg_rtx = frame_ptr_rtx;
15205 rs6000_emit_allocate_stack (info->total_size,
15206 (frame_reg_rtx != sp_reg_rtx
15207 && (info->cr_save_p
15209 || info->first_fp_reg_save < 64
15210 || info->first_gp_reg_save < 32
15212 if (frame_reg_rtx != sp_reg_rtx)
15213 rs6000_emit_stack_tie ();
15216 /* Handle world saves specially here. */
15217 if (WORLD_SAVE_P (info))
15224 /* save_world expects lr in r0. */
15225 reg0 = gen_rtx_REG (Pmode, 0);
15226 if (info->lr_save_p)
15228 insn = emit_move_insn (reg0,
15229 gen_rtx_REG (Pmode, LR_REGNO));
15230 RTX_FRAME_RELATED_P (insn) = 1;
15233 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
15234 assumptions about the offsets of various bits of the stack
15236 gcc_assert (info->gp_save_offset == -220
15237 && info->fp_save_offset == -144
15238 && info->lr_save_offset == 8
15239 && info->cr_save_offset == 4
15242 && (!current_function_calls_eh_return
15243 || info->ehrd_offset == -432)
15244 && info->vrsave_save_offset == -224
15245 && info->altivec_save_offset == -416);
15247 treg = gen_rtx_REG (SImode, 11);
15248 emit_move_insn (treg, GEN_INT (-info->total_size));
15250 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
15251 in R11. It also clobbers R12, so beware! */
15253 /* Preserve CR2 for save_world prologues */
15255 sz += 32 - info->first_gp_reg_save;
15256 sz += 64 - info->first_fp_reg_save;
15257 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
15258 p = rtvec_alloc (sz);
15260 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
15261 gen_rtx_REG (SImode,
15263 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15264 gen_rtx_SYMBOL_REF (Pmode,
15266 /* We do floats first so that the instruction pattern matches
15268 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15270 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15271 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15272 GEN_INT (info->fp_save_offset
15273 + sp_offset + 8 * i));
15274 rtx mem = gen_frame_mem (DFmode, addr);
15276 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15278 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15280 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15281 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15282 GEN_INT (info->altivec_save_offset
15283 + sp_offset + 16 * i));
15284 rtx mem = gen_frame_mem (V4SImode, addr);
15286 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15288 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15290 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15291 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15292 GEN_INT (info->gp_save_offset
15293 + sp_offset + reg_size * i));
15294 rtx mem = gen_frame_mem (reg_mode, addr);
15296 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15300 /* CR register traditionally saved as CR2. */
15301 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15302 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15303 GEN_INT (info->cr_save_offset
15305 rtx mem = gen_frame_mem (reg_mode, addr);
15307 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15309 /* Explain about use of R0. */
15310 if (info->lr_save_p)
15312 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15313 GEN_INT (info->lr_save_offset
15315 rtx mem = gen_frame_mem (reg_mode, addr);
15317 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
15319 /* Explain what happens to the stack pointer. */
15321 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
15322 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
15325 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15326 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15327 treg, GEN_INT (-info->total_size));
15328 sp_offset = info->total_size;
15331 /* If we use the link register, get it into r0. */
15332 if (!WORLD_SAVE_P (info) && info->lr_save_p)
15334 rtx addr, reg, mem;
15336 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
15337 gen_rtx_REG (Pmode, LR_REGNO));
15338 RTX_FRAME_RELATED_P (insn) = 1;
15340 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15341 GEN_INT (info->lr_save_offset + sp_offset));
15342 reg = gen_rtx_REG (Pmode, 0);
15343 mem = gen_rtx_MEM (Pmode, addr);
15344 /* This should not be of rs6000_sr_alias_set, because of
15345 __builtin_return_address. */
15347 insn = emit_move_insn (mem, reg);
15348 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15349 NULL_RTX, NULL_RTX);
15352 /* If we need to save CR, put it into r12. */
15353 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
15357 cr_save_rtx = gen_rtx_REG (SImode, 12);
15358 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15359 RTX_FRAME_RELATED_P (insn) = 1;
15360 /* Now, there's no way that dwarf2out_frame_debug_expr is going
15361 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
15362 But that's OK. All we have to do is specify that _one_ condition
15363 code register is saved in this stack slot. The thrower's epilogue
15364 will then restore all the call-saved registers.
15365 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
15366 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
15367 gen_rtx_REG (SImode, CR2_REGNO));
15368 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15373 /* Do any required saving of fpr's. If only one or two to save, do
15374 it ourselves. Otherwise, call function. */
15375 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
15378 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15379 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15380 && ! call_used_regs[info->first_fp_reg_save+i]))
15381 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
15382 info->first_fp_reg_save + i,
15383 info->fp_save_offset + sp_offset + 8 * i,
15386 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
15390 const char *alloc_rname;
15392 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
15394 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
15395 gen_rtx_REG (Pmode,
15397 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
15398 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
15399 alloc_rname = ggc_strdup (rname);
15400 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15401 gen_rtx_SYMBOL_REF (Pmode,
15403 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15405 rtx addr, reg, mem;
15406 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15407 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15408 GEN_INT (info->fp_save_offset
15409 + sp_offset + 8*i));
15410 mem = gen_frame_mem (DFmode, addr);
15412 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
15414 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15415 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15416 NULL_RTX, NULL_RTX);
15419 /* Save GPRs. This is done as a PARALLEL if we are using
15420 the store-multiple instructions. */
15421 if (!WORLD_SAVE_P (info) && using_store_multiple)
15425 p = rtvec_alloc (32 - info->first_gp_reg_save);
15426 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15428 rtx addr, reg, mem;
15429 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15430 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15431 GEN_INT (info->gp_save_offset
15434 mem = gen_frame_mem (reg_mode, addr);
15436 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
15438 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15439 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15440 NULL_RTX, NULL_RTX);
15442 else if (!WORLD_SAVE_P (info)
15444 && info->spe_64bit_regs_used != 0
15445 && info->first_gp_reg_save != 32)
15448 rtx spe_save_area_ptr;
15449 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
15450 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
15451 && !call_used_regs[STATIC_CHAIN_REGNUM]);
15453 /* Determine whether we can address all of the registers that need
15454 to be saved with an offset from the stack pointer that fits in
15455 the small const field for SPE memory instructions. */
15456 int spe_regs_addressable_via_sp
15457 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15458 + (32 - info->first_gp_reg_save - 1) * reg_size);
15461 if (spe_regs_addressable_via_sp)
15463 spe_save_area_ptr = sp_reg_rtx;
15464 spe_offset = info->spe_gp_save_offset + sp_offset;
15468 /* Make r11 point to the start of the SPE save area. We need
15469 to be careful here if r11 is holding the static chain. If
15470 it is, then temporarily save it in r0. We would use r0 as
15471 our base register here, but using r0 as a base register in
15472 loads and stores means something different from what we
15474 if (using_static_chain_p)
15476 rtx r0 = gen_rtx_REG (Pmode, 0);
15478 gcc_assert (info->first_gp_reg_save > 11);
15480 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
15483 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15484 emit_insn (gen_addsi3 (spe_save_area_ptr, sp_reg_rtx,
15485 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15490 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15491 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15493 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15494 rtx offset, addr, mem;
15496 /* We're doing all this to ensure that the offset fits into
15497 the immediate offset of 'evstdd'. */
15498 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
15500 offset = GEN_INT (reg_size * i + spe_offset);
15501 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15502 mem = gen_rtx_MEM (V2SImode, addr);
15504 insn = emit_move_insn (mem, reg);
15506 rs6000_frame_related (insn, spe_save_area_ptr,
15507 info->spe_gp_save_offset
15508 + sp_offset + reg_size * i,
15509 offset, const0_rtx);
15512 /* Move the static chain pointer back. */
15513 if (using_static_chain_p && !spe_regs_addressable_via_sp)
15514 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
15516 else if (!WORLD_SAVE_P (info))
15519 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15520 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15522 rtx addr, reg, mem;
15523 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15525 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15526 GEN_INT (info->gp_save_offset
15529 mem = gen_frame_mem (reg_mode, addr);
15531 insn = emit_move_insn (mem, reg);
15532 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15533 NULL_RTX, NULL_RTX);
15537 /* ??? There's no need to emit actual instructions here, but it's the
15538 easiest way to get the frame unwind information emitted. */
15539 if (current_function_calls_eh_return)
15541 unsigned int i, regno;
15543 /* In AIX ABI we need to pretend we save r2 here. */
15546 rtx addr, reg, mem;
15548 reg = gen_rtx_REG (reg_mode, 2);
15549 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15550 GEN_INT (sp_offset + 5 * reg_size));
15551 mem = gen_frame_mem (reg_mode, addr);
15553 insn = emit_move_insn (mem, reg);
15554 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15555 NULL_RTX, NULL_RTX);
15556 PATTERN (insn) = gen_blockage ();
15561 regno = EH_RETURN_DATA_REGNO (i);
15562 if (regno == INVALID_REGNUM)
15565 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
15566 info->ehrd_offset + sp_offset
15567 + reg_size * (int) i,
15572 /* Save CR if we use any that must be preserved. */
15573 if (!WORLD_SAVE_P (info) && info->cr_save_p)
15575 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15576 GEN_INT (info->cr_save_offset + sp_offset));
15577 rtx mem = gen_frame_mem (SImode, addr);
15578 /* See the large comment above about why CR2_REGNO is used. */
15579 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
15581 /* If r12 was used to hold the original sp, copy cr into r0 now
15583 if (REGNO (frame_reg_rtx) == 12)
15587 cr_save_rtx = gen_rtx_REG (SImode, 0);
15588 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15589 RTX_FRAME_RELATED_P (insn) = 1;
15590 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
15591 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15596 insn = emit_move_insn (mem, cr_save_rtx);
15598 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15599 NULL_RTX, NULL_RTX);
15602 /* Update stack and set back pointer unless this is V.4,
15603 for which it was done previously. */
15604 if (!WORLD_SAVE_P (info) && info->push_p
15605 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
15607 if (info->total_size < 32767)
15608 sp_offset = info->total_size;
15610 frame_reg_rtx = frame_ptr_rtx;
15611 rs6000_emit_allocate_stack (info->total_size,
15612 (frame_reg_rtx != sp_reg_rtx
15613 && ((info->altivec_size != 0)
15614 || (info->vrsave_mask != 0)
15616 if (frame_reg_rtx != sp_reg_rtx)
15617 rs6000_emit_stack_tie ();
15620 /* Set frame pointer, if needed. */
15621 if (frame_pointer_needed)
15623 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
15625 RTX_FRAME_RELATED_P (insn) = 1;
15628 /* Save AltiVec registers if needed. Save here because the red zone does
15629 not include AltiVec registers. */
15630 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15634 /* There should be a non inline version of this, for when we
15635 are saving lots of vector registers. */
15636 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15637 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15639 rtx areg, savereg, mem;
15642 offset = info->altivec_save_offset + sp_offset
15643 + 16 * (i - info->first_altivec_reg_save);
15645 savereg = gen_rtx_REG (V4SImode, i);
15647 areg = gen_rtx_REG (Pmode, 0);
15648 emit_move_insn (areg, GEN_INT (offset));
15650 /* AltiVec addressing mode is [reg+reg]. */
15651 mem = gen_frame_mem (V4SImode,
15652 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
15654 insn = emit_move_insn (mem, savereg);
15656 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15657 areg, GEN_INT (offset));
15661 /* VRSAVE is a bit vector representing which AltiVec registers
15662 are used. The OS uses this to determine which vector
15663 registers to save on a context switch. We need to save
15664 VRSAVE on the stack frame, add whatever AltiVec registers we
15665 used in this function, and do the corresponding magic in the
15668 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15669 && info->vrsave_mask != 0)
15671 rtx reg, mem, vrsave;
15674 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
15675 as frame_reg_rtx and r11 as the static chain pointer for
15676 nested functions. */
15677 reg = gen_rtx_REG (SImode, 0);
15678 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15680 emit_insn (gen_get_vrsave_internal (reg));
15682 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
15684 if (!WORLD_SAVE_P (info))
15687 offset = info->vrsave_save_offset + sp_offset;
15688 mem = gen_frame_mem (SImode,
15689 gen_rtx_PLUS (Pmode, frame_reg_rtx,
15690 GEN_INT (offset)));
15691 insn = emit_move_insn (mem, reg);
15694 /* Include the registers in the mask. */
15695 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
15697 insn = emit_insn (generate_set_vrsave (reg, info, 0));
15700 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15701 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
15702 || (DEFAULT_ABI == ABI_V4
15703 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
15704 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
15706 /* If emit_load_toc_table will use the link register, we need to save
15707 it. We use R12 for this purpose because emit_load_toc_table
15708 can use register 0. This allows us to use a plain 'blr' to return
15709 from the procedure more often. */
15710 int save_LR_around_toc_setup = (TARGET_ELF
15711 && DEFAULT_ABI != ABI_AIX
15713 && ! info->lr_save_p
15714 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
15715 if (save_LR_around_toc_setup)
15717 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15719 insn = emit_move_insn (frame_ptr_rtx, lr);
15720 RTX_FRAME_RELATED_P (insn) = 1;
15722 rs6000_emit_load_toc_table (TRUE);
15724 insn = emit_move_insn (lr, frame_ptr_rtx);
15725 RTX_FRAME_RELATED_P (insn) = 1;
15728 rs6000_emit_load_toc_table (TRUE);
15732 if (DEFAULT_ABI == ABI_DARWIN
15733 && flag_pic && current_function_uses_pic_offset_table)
15735 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15736 rtx src = machopic_function_base_sym ();
15738 /* Save and restore LR locally around this call (in R0). */
15739 if (!info->lr_save_p)
15740 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
15742 emit_insn (gen_load_macho_picbase (src));
15744 emit_move_insn (gen_rtx_REG (Pmode,
15745 RS6000_PIC_OFFSET_TABLE_REGNUM),
15748 if (!info->lr_save_p)
15749 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
15754 /* Write function prologue. */
15757 rs6000_output_function_prologue (FILE *file,
15758 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15760 rs6000_stack_t *info = rs6000_stack_info ();
15762 if (TARGET_DEBUG_STACK)
15763 debug_stack_info (info);
15765 /* Write .extern for any function we will call to save and restore
15767 if (info->first_fp_reg_save < 64
15768 && !FP_SAVE_INLINE (info->first_fp_reg_save))
15769 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15770 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
15771 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
15772 RESTORE_FP_SUFFIX);
15774 /* Write .extern for AIX common mode routines, if needed. */
15775 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
15777 fputs ("\t.extern __mulh\n", file);
15778 fputs ("\t.extern __mull\n", file);
15779 fputs ("\t.extern __divss\n", file);
15780 fputs ("\t.extern __divus\n", file);
15781 fputs ("\t.extern __quoss\n", file);
15782 fputs ("\t.extern __quous\n", file);
15783 common_mode_defined = 1;
15786 if (! HAVE_prologue)
15790 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15791 the "toplevel" insn chain. */
15792 emit_note (NOTE_INSN_DELETED);
15793 rs6000_emit_prologue ();
15794 emit_note (NOTE_INSN_DELETED);
15796 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15800 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15802 INSN_ADDRESSES_NEW (insn, addr);
15807 if (TARGET_DEBUG_STACK)
15808 debug_rtx_list (get_insns (), 100);
15809 final (get_insns (), file, FALSE);
15813 rs6000_pic_labelno++;
15816 /* Emit function epilogue as insns.
15818 At present, dwarf2out_frame_debug_expr doesn't understand
15819 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15820 anywhere in the epilogue. Most of the insns below would in any case
15821 need special notes to explain where r11 is in relation to the stack. */
15824 rs6000_emit_epilogue (int sibcall)
15826 rs6000_stack_t *info;
15827 int restoring_FPRs_inline;
15828 int using_load_multiple;
15829 int using_mtcr_multiple;
15830 int use_backchain_to_restore_sp;
15832 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15833 rtx frame_reg_rtx = sp_reg_rtx;
15834 enum machine_mode reg_mode = Pmode;
15835 int reg_size = TARGET_32BIT ? 4 : 8;
15838 info = rs6000_stack_info ();
15840 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15842 reg_mode = V2SImode;
15846 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15847 && (!TARGET_SPE_ABI
15848 || info->spe_64bit_regs_used == 0)
15849 && info->first_gp_reg_save < 31
15850 && no_global_regs_above (info->first_gp_reg_save));
15851 restoring_FPRs_inline = (sibcall
15852 || current_function_calls_eh_return
15853 || info->first_fp_reg_save == 64
15854 || FP_SAVE_INLINE (info->first_fp_reg_save));
15855 use_backchain_to_restore_sp = (frame_pointer_needed
15856 || current_function_calls_alloca
15857 || info->total_size > 32767);
15858 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15859 || rs6000_cpu == PROCESSOR_PPC603
15860 || rs6000_cpu == PROCESSOR_PPC750
15863 if (WORLD_SAVE_P (info))
15867 const char *alloc_rname;
15870 /* eh_rest_world_r10 will return to the location saved in the LR
15871 stack slot (which is not likely to be our caller.)
15872 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15873 rest_world is similar, except any R10 parameter is ignored.
15874 The exception-handling stuff that was here in 2.95 is no
15875 longer necessary. */
15879 + 32 - info->first_gp_reg_save
15880 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15881 + 63 + 1 - info->first_fp_reg_save);
15883 strcpy (rname, ((current_function_calls_eh_return) ?
15884 "*eh_rest_world_r10" : "*rest_world"));
15885 alloc_rname = ggc_strdup (rname);
15888 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15889 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15890 gen_rtx_REG (Pmode,
15893 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15894 /* The instruction pattern requires a clobber here;
15895 it is shared with the restVEC helper. */
15897 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
15900 /* CR register traditionally saved as CR2. */
15901 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15902 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15903 GEN_INT (info->cr_save_offset));
15904 rtx mem = gen_frame_mem (reg_mode, addr);
15906 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15909 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15911 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15912 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15913 GEN_INT (info->gp_save_offset
15915 rtx mem = gen_frame_mem (reg_mode, addr);
15917 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15919 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15921 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15922 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15923 GEN_INT (info->altivec_save_offset
15925 rtx mem = gen_frame_mem (V4SImode, addr);
15927 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15929 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
15931 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15932 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15933 GEN_INT (info->fp_save_offset
15935 rtx mem = gen_frame_mem (DFmode, addr);
15937 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15940 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15942 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15944 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15946 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15948 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15949 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15954 /* Set sp_offset based on the stack push from the prologue. */
15955 if (info->total_size < 32767)
15956 sp_offset = info->total_size;
15958 /* Restore AltiVec registers if needed. */
15959 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15963 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15964 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15966 rtx addr, areg, mem;
15968 areg = gen_rtx_REG (Pmode, 0);
15970 (areg, GEN_INT (info->altivec_save_offset
15972 + 16 * (i - info->first_altivec_reg_save)));
15974 /* AltiVec addressing mode is [reg+reg]. */
15975 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15976 mem = gen_frame_mem (V4SImode, addr);
15978 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15982 /* Restore VRSAVE if needed. */
15983 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15984 && info->vrsave_mask != 0)
15986 rtx addr, mem, reg;
15988 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15989 GEN_INT (info->vrsave_save_offset + sp_offset));
15990 mem = gen_frame_mem (SImode, addr);
15991 reg = gen_rtx_REG (SImode, 12);
15992 emit_move_insn (reg, mem);
15994 emit_insn (generate_set_vrsave (reg, info, 1));
15999 /* If we have a frame pointer, a call to alloca, or a large stack
16000 frame, restore the old stack pointer using the backchain. Otherwise,
16001 we know what size to update it with. */
16002 if (use_backchain_to_restore_sp)
16004 /* Under V.4, don't reset the stack pointer until after we're done
16005 loading the saved registers. */
16006 if (DEFAULT_ABI == ABI_V4)
16007 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16009 emit_move_insn (frame_reg_rtx,
16010 gen_rtx_MEM (Pmode, sp_reg_rtx));
16012 else if (info->push_p)
16014 if (DEFAULT_ABI == ABI_V4
16015 || current_function_calls_eh_return)
16016 sp_offset = info->total_size;
16019 emit_insn (TARGET_32BIT
16020 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
16021 GEN_INT (info->total_size))
16022 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
16023 GEN_INT (info->total_size)));
16027 /* Get the old lr if we saved it. */
16028 if (info->lr_save_p)
16030 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
16031 info->lr_save_offset + sp_offset);
16033 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
16036 /* Get the old cr if we saved it. */
16037 if (info->cr_save_p)
16039 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16040 GEN_INT (info->cr_save_offset + sp_offset));
16041 rtx mem = gen_frame_mem (SImode, addr);
16043 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
16046 /* Set LR here to try to overlap restores below. */
16047 if (info->lr_save_p)
16048 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
16049 gen_rtx_REG (Pmode, 0));
16051 /* Load exception handler data registers, if needed. */
16052 if (current_function_calls_eh_return)
16054 unsigned int i, regno;
16058 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16059 GEN_INT (sp_offset + 5 * reg_size));
16060 rtx mem = gen_frame_mem (reg_mode, addr);
16062 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
16069 regno = EH_RETURN_DATA_REGNO (i);
16070 if (regno == INVALID_REGNUM)
16073 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
16074 info->ehrd_offset + sp_offset
16075 + reg_size * (int) i);
16077 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
16081 /* Restore GPRs. This is done as a PARALLEL if we are using
16082 the load-multiple instructions. */
16083 if (using_load_multiple)
16086 p = rtvec_alloc (32 - info->first_gp_reg_save);
16087 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16089 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16090 GEN_INT (info->gp_save_offset
16093 rtx mem = gen_frame_mem (reg_mode, addr);
16096 gen_rtx_SET (VOIDmode,
16097 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
16100 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16102 else if (TARGET_SPE_ABI
16103 && info->spe_64bit_regs_used != 0
16104 && info->first_gp_reg_save != 32)
16106 rtx spe_save_area_ptr;
16107 /* Determine whether we can address all of the registers that need
16108 to be saved with an offset from the stack pointer that fits in
16109 the small const field for SPE memory instructions. */
16110 int spe_regs_addressable_via_sp
16111 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
16112 + (32 - info->first_gp_reg_save - 1) * reg_size);
16115 if (spe_regs_addressable_via_sp)
16117 spe_save_area_ptr = frame_reg_rtx;
16118 spe_offset = info->spe_gp_save_offset + sp_offset;
16122 /* Make r11 point to the start of the SPE save area. We worried about
16123 not clobbering it when we were saving registers in the prologue.
16124 There's no need to worry here because the static chain is passed
16125 anew to every function. */
16126 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
16128 emit_insn (gen_addsi3 (spe_save_area_ptr, frame_reg_rtx,
16129 GEN_INT (info->spe_gp_save_offset + sp_offset)));
16134 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16135 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16137 rtx offset, addr, mem;
16139 /* We're doing all this to ensure that the immediate offset
16140 fits into the immediate field of 'evldd'. */
16141 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
16143 offset = GEN_INT (spe_offset + reg_size * i);
16144 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
16145 mem = gen_rtx_MEM (V2SImode, addr);
16147 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
16152 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16153 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16155 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16156 GEN_INT (info->gp_save_offset
16159 rtx mem = gen_frame_mem (reg_mode, addr);
16161 emit_move_insn (gen_rtx_REG (reg_mode,
16162 info->first_gp_reg_save + i), mem);
16165 /* Restore fpr's if we need to do it without calling a function. */
16166 if (restoring_FPRs_inline)
16167 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16168 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
16169 && ! call_used_regs[info->first_fp_reg_save+i]))
16172 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16173 GEN_INT (info->fp_save_offset
16176 mem = gen_frame_mem (DFmode, addr);
16178 emit_move_insn (gen_rtx_REG (DFmode,
16179 info->first_fp_reg_save + i),
16183 /* If we saved cr, restore it here. Just those that were used. */
16184 if (info->cr_save_p)
16186 rtx r12_rtx = gen_rtx_REG (SImode, 12);
16189 if (using_mtcr_multiple)
16191 for (i = 0; i < 8; i++)
16192 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16194 gcc_assert (count);
16197 if (using_mtcr_multiple && count > 1)
16202 p = rtvec_alloc (count);
16205 for (i = 0; i < 8; i++)
16206 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16208 rtvec r = rtvec_alloc (2);
16209 RTVEC_ELT (r, 0) = r12_rtx;
16210 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
16211 RTVEC_ELT (p, ndx) =
16212 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
16213 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
16216 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16217 gcc_assert (ndx == count);
16220 for (i = 0; i < 8; i++)
16221 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16223 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
16229 /* If this is V.4, unwind the stack pointer after all of the loads
16231 if (frame_reg_rtx != sp_reg_rtx)
16233 /* This blockage is needed so that sched doesn't decide to move
16234 the sp change before the register restores. */
16235 rs6000_emit_stack_tie ();
16237 && info->spe_64bit_regs_used != 0
16238 && info->first_gp_reg_save != 32)
16239 emit_insn (gen_addsi3 (sp_reg_rtx, gen_rtx_REG (Pmode, 11),
16240 GEN_INT (-(info->spe_gp_save_offset + sp_offset))));
16242 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
16244 else if (sp_offset != 0)
16245 emit_insn (TARGET_32BIT
16246 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
16247 GEN_INT (sp_offset))
16248 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
16249 GEN_INT (sp_offset)));
16251 if (current_function_calls_eh_return)
16253 rtx sa = EH_RETURN_STACKADJ_RTX;
16254 emit_insn (TARGET_32BIT
16255 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
16256 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
16262 if (! restoring_FPRs_inline)
16263 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
16265 p = rtvec_alloc (2);
16267 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
16268 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
16269 gen_rtx_REG (Pmode,
16272 /* If we have to restore more than two FP registers, branch to the
16273 restore function. It will return to our caller. */
16274 if (! restoring_FPRs_inline)
16278 const char *alloc_rname;
16280 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
16281 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
16282 alloc_rname = ggc_strdup (rname);
16283 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
16284 gen_rtx_SYMBOL_REF (Pmode,
16287 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16290 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
16291 GEN_INT (info->fp_save_offset + 8*i));
16292 mem = gen_frame_mem (DFmode, addr);
16294 RTVEC_ELT (p, i+3) =
16295 gen_rtx_SET (VOIDmode,
16296 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
16301 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
16305 /* Write function epilogue. */
16308 rs6000_output_function_epilogue (FILE *file,
16309 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
16311 if (! HAVE_epilogue)
16313 rtx insn = get_last_insn ();
16314 /* If the last insn was a BARRIER, we don't have to write anything except
16315 the trace table. */
16316 if (GET_CODE (insn) == NOTE)
16317 insn = prev_nonnote_insn (insn);
16318 if (insn == 0 || GET_CODE (insn) != BARRIER)
16320 /* This is slightly ugly, but at least we don't have two
16321 copies of the epilogue-emitting code. */
16324 /* A NOTE_INSN_DELETED is supposed to be at the start
16325 and end of the "toplevel" insn chain. */
16326 emit_note (NOTE_INSN_DELETED);
16327 rs6000_emit_epilogue (FALSE);
16328 emit_note (NOTE_INSN_DELETED);
16330 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16334 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16336 INSN_ADDRESSES_NEW (insn, addr);
16341 if (TARGET_DEBUG_STACK)
16342 debug_rtx_list (get_insns (), 100);
16343 final (get_insns (), file, FALSE);
16349 macho_branch_islands ();
16350 /* Mach-O doesn't support labels at the end of objects, so if
16351 it looks like we might want one, insert a NOP. */
16353 rtx insn = get_last_insn ();
16356 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
16357 insn = PREV_INSN (insn);
16361 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
16362 fputs ("\tnop\n", file);
16366 /* Output a traceback table here. See /usr/include/sys/debug.h for info
16369 We don't output a traceback table if -finhibit-size-directive was
16370 used. The documentation for -finhibit-size-directive reads
16371 ``don't output a @code{.size} assembler directive, or anything
16372 else that would cause trouble if the function is split in the
16373 middle, and the two halves are placed at locations far apart in
16374 memory.'' The traceback table has this property, since it
16375 includes the offset from the start of the function to the
16376 traceback table itself.
16378 System V.4 Powerpc's (and the embedded ABI derived from it) use a
16379 different traceback table. */
16380 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
16381 && rs6000_traceback != traceback_none && !current_function_is_thunk)
16383 const char *fname = NULL;
16384 const char *language_string = lang_hooks.name;
16385 int fixed_parms = 0, float_parms = 0, parm_info = 0;
16387 int optional_tbtab;
16388 rs6000_stack_t *info = rs6000_stack_info ();
16390 if (rs6000_traceback == traceback_full)
16391 optional_tbtab = 1;
16392 else if (rs6000_traceback == traceback_part)
16393 optional_tbtab = 0;
16395 optional_tbtab = !optimize_size && !TARGET_ELF;
16397 if (optional_tbtab)
16399 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
16400 while (*fname == '.') /* V.4 encodes . in the name */
16403 /* Need label immediately before tbtab, so we can compute
16404 its offset from the function start. */
16405 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16406 ASM_OUTPUT_LABEL (file, fname);
16409 /* The .tbtab pseudo-op can only be used for the first eight
16410 expressions, since it can't handle the possibly variable
16411 length fields that follow. However, if you omit the optional
16412 fields, the assembler outputs zeros for all optional fields
16413 anyways, giving each variable length field is minimum length
16414 (as defined in sys/debug.h). Thus we can not use the .tbtab
16415 pseudo-op at all. */
16417 /* An all-zero word flags the start of the tbtab, for debuggers
16418 that have to find it by searching forward from the entry
16419 point or from the current pc. */
16420 fputs ("\t.long 0\n", file);
16422 /* Tbtab format type. Use format type 0. */
16423 fputs ("\t.byte 0,", file);
16425 /* Language type. Unfortunately, there does not seem to be any
16426 official way to discover the language being compiled, so we
16427 use language_string.
16428 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
16429 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
16430 a number, so for now use 9. */
16431 if (! strcmp (language_string, "GNU C"))
16433 else if (! strcmp (language_string, "GNU F77")
16434 || ! strcmp (language_string, "GNU F95"))
16436 else if (! strcmp (language_string, "GNU Pascal"))
16438 else if (! strcmp (language_string, "GNU Ada"))
16440 else if (! strcmp (language_string, "GNU C++")
16441 || ! strcmp (language_string, "GNU Objective-C++"))
16443 else if (! strcmp (language_string, "GNU Java"))
16445 else if (! strcmp (language_string, "GNU Objective-C"))
16448 gcc_unreachable ();
16449 fprintf (file, "%d,", i);
16451 /* 8 single bit fields: global linkage (not set for C extern linkage,
16452 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
16453 from start of procedure stored in tbtab, internal function, function
16454 has controlled storage, function has no toc, function uses fp,
16455 function logs/aborts fp operations. */
16456 /* Assume that fp operations are used if any fp reg must be saved. */
16457 fprintf (file, "%d,",
16458 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
16460 /* 6 bitfields: function is interrupt handler, name present in
16461 proc table, function calls alloca, on condition directives
16462 (controls stack walks, 3 bits), saves condition reg, saves
16464 /* The `function calls alloca' bit seems to be set whenever reg 31 is
16465 set up as a frame pointer, even when there is no alloca call. */
16466 fprintf (file, "%d,",
16467 ((optional_tbtab << 6)
16468 | ((optional_tbtab & frame_pointer_needed) << 5)
16469 | (info->cr_save_p << 1)
16470 | (info->lr_save_p)));
16472 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
16474 fprintf (file, "%d,",
16475 (info->push_p << 7) | (64 - info->first_fp_reg_save));
16477 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
16478 fprintf (file, "%d,", (32 - first_reg_to_save ()));
16480 if (optional_tbtab)
16482 /* Compute the parameter info from the function decl argument
16485 int next_parm_info_bit = 31;
16487 for (decl = DECL_ARGUMENTS (current_function_decl);
16488 decl; decl = TREE_CHAIN (decl))
16490 rtx parameter = DECL_INCOMING_RTL (decl);
16491 enum machine_mode mode = GET_MODE (parameter);
16493 if (GET_CODE (parameter) == REG)
16495 if (SCALAR_FLOAT_MODE_P (mode))
16515 gcc_unreachable ();
16518 /* If only one bit will fit, don't or in this entry. */
16519 if (next_parm_info_bit > 0)
16520 parm_info |= (bits << (next_parm_info_bit - 1));
16521 next_parm_info_bit -= 2;
16525 fixed_parms += ((GET_MODE_SIZE (mode)
16526 + (UNITS_PER_WORD - 1))
16528 next_parm_info_bit -= 1;
16534 /* Number of fixed point parameters. */
16535 /* This is actually the number of words of fixed point parameters; thus
16536 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16537 fprintf (file, "%d,", fixed_parms);
16539 /* 2 bitfields: number of floating point parameters (7 bits), parameters
16541 /* This is actually the number of fp registers that hold parameters;
16542 and thus the maximum value is 13. */
16543 /* Set parameters on stack bit if parameters are not in their original
16544 registers, regardless of whether they are on the stack? Xlc
16545 seems to set the bit when not optimizing. */
16546 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
16548 if (! optional_tbtab)
16551 /* Optional fields follow. Some are variable length. */
16553 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
16554 11 double float. */
16555 /* There is an entry for each parameter in a register, in the order that
16556 they occur in the parameter list. Any intervening arguments on the
16557 stack are ignored. If the list overflows a long (max possible length
16558 34 bits) then completely leave off all elements that don't fit. */
16559 /* Only emit this long if there was at least one parameter. */
16560 if (fixed_parms || float_parms)
16561 fprintf (file, "\t.long %d\n", parm_info);
16563 /* Offset from start of code to tb table. */
16564 fputs ("\t.long ", file);
16565 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16567 RS6000_OUTPUT_BASENAME (file, fname);
16569 assemble_name (file, fname);
16571 rs6000_output_function_entry (file, fname);
16574 /* Interrupt handler mask. */
16575 /* Omit this long, since we never set the interrupt handler bit
16578 /* Number of CTL (controlled storage) anchors. */
16579 /* Omit this long, since the has_ctl bit is never set above. */
16581 /* Displacement into stack of each CTL anchor. */
16582 /* Omit this list of longs, because there are no CTL anchors. */
16584 /* Length of function name. */
16587 fprintf (file, "\t.short %d\n", (int) strlen (fname));
16589 /* Function name. */
16590 assemble_string (fname, strlen (fname));
16592 /* Register for alloca automatic storage; this is always reg 31.
16593 Only emit this if the alloca bit was set above. */
16594 if (frame_pointer_needed)
16595 fputs ("\t.byte 31\n", file);
16597 fputs ("\t.align 2\n", file);
16601 /* A C compound statement that outputs the assembler code for a thunk
16602 function, used to implement C++ virtual function calls with
16603 multiple inheritance. The thunk acts as a wrapper around a virtual
16604 function, adjusting the implicit object parameter before handing
16605 control off to the real function.
16607 First, emit code to add the integer DELTA to the location that
16608 contains the incoming first argument. Assume that this argument
16609 contains a pointer, and is the one used to pass the `this' pointer
16610 in C++. This is the incoming argument *before* the function
16611 prologue, e.g. `%o0' on a sparc. The addition must preserve the
16612 values of all other incoming arguments.
16614 After the addition, emit code to jump to FUNCTION, which is a
16615 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
16616 not touch the return address. Hence returning from FUNCTION will
16617 return to whoever called the current `thunk'.
16619 The effect must be as if FUNCTION had been called directly with the
16620 adjusted first argument. This macro is responsible for emitting
16621 all of the code for a thunk function; output_function_prologue()
16622 and output_function_epilogue() are not invoked.
16624 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
16625 been extracted from it.) It might possibly be useful on some
16626 targets, but probably not.
16628 If you do not define this macro, the target-independent code in the
16629 C++ frontend will generate a less efficient heavyweight thunk that
16630 calls FUNCTION instead of jumping to it. The generic approach does
16631 not support varargs. */
16634 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16635 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16638 rtx this, insn, funexp;
16640 reload_completed = 1;
16641 epilogue_completed = 1;
16643 /* Mark the end of the (empty) prologue. */
16644 emit_note (NOTE_INSN_PROLOGUE_END);
16646 /* Find the "this" pointer. If the function returns a structure,
16647 the structure return pointer is in r3. */
16648 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16649 this = gen_rtx_REG (Pmode, 4);
16651 this = gen_rtx_REG (Pmode, 3);
16653 /* Apply the constant offset, if required. */
16656 rtx delta_rtx = GEN_INT (delta);
16657 emit_insn (TARGET_32BIT
16658 ? gen_addsi3 (this, this, delta_rtx)
16659 : gen_adddi3 (this, this, delta_rtx));
16662 /* Apply the offset from the vtable, if required. */
16665 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
16666 rtx tmp = gen_rtx_REG (Pmode, 12);
16668 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
16669 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
16671 emit_insn (TARGET_32BIT
16672 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
16673 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
16674 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
16678 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
16680 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
16682 emit_insn (TARGET_32BIT
16683 ? gen_addsi3 (this, this, tmp)
16684 : gen_adddi3 (this, this, tmp));
16687 /* Generate a tail call to the target function. */
16688 if (!TREE_USED (function))
16690 assemble_external (function);
16691 TREE_USED (function) = 1;
16693 funexp = XEXP (DECL_RTL (function), 0);
16694 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
16697 if (MACHOPIC_INDIRECT)
16698 funexp = machopic_indirect_call_target (funexp);
16701 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16702 generate sibcall RTL explicitly. */
16703 insn = emit_call_insn (
16704 gen_rtx_PARALLEL (VOIDmode,
16706 gen_rtx_CALL (VOIDmode,
16707 funexp, const0_rtx),
16708 gen_rtx_USE (VOIDmode, const0_rtx),
16709 gen_rtx_USE (VOIDmode,
16710 gen_rtx_REG (SImode,
16712 gen_rtx_RETURN (VOIDmode))));
16713 SIBLING_CALL_P (insn) = 1;
16716 /* Run just enough of rest_of_compilation to get the insns emitted.
16717 There's not really enough bulk here to make other passes such as
16718 instruction scheduling worth while. Note that use_thunk calls
16719 assemble_start_function and assemble_end_function. */
16720 insn = get_insns ();
16721 insn_locators_alloc ();
16722 shorten_branches (insn);
16723 final_start_function (insn, file, 1);
16724 final (insn, file, 1);
16725 final_end_function ();
16727 reload_completed = 0;
16728 epilogue_completed = 0;
16731 /* A quick summary of the various types of 'constant-pool tables'
16734 Target Flags Name One table per
16735 AIX (none) AIX TOC object file
16736 AIX -mfull-toc AIX TOC object file
16737 AIX -mminimal-toc AIX minimal TOC translation unit
16738 SVR4/EABI (none) SVR4 SDATA object file
16739 SVR4/EABI -fpic SVR4 pic object file
16740 SVR4/EABI -fPIC SVR4 PIC translation unit
16741 SVR4/EABI -mrelocatable EABI TOC function
16742 SVR4/EABI -maix AIX TOC object file
16743 SVR4/EABI -maix -mminimal-toc
16744 AIX minimal TOC translation unit
16746 Name Reg. Set by entries contains:
16747 made by addrs? fp? sum?
16749 AIX TOC 2 crt0 as Y option option
16750 AIX minimal TOC 30 prolog gcc Y Y option
16751 SVR4 SDATA 13 crt0 gcc N Y N
16752 SVR4 pic 30 prolog ld Y not yet N
16753 SVR4 PIC 30 prolog gcc Y option option
16754 EABI TOC 30 prolog gcc Y option option
16758 /* Hash functions for the hash table. */
16761 rs6000_hash_constant (rtx k)
16763 enum rtx_code code = GET_CODE (k);
16764 enum machine_mode mode = GET_MODE (k);
16765 unsigned result = (code << 3) ^ mode;
16766 const char *format;
16769 format = GET_RTX_FORMAT (code);
16770 flen = strlen (format);
16776 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
16779 if (mode != VOIDmode)
16780 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
16792 for (; fidx < flen; fidx++)
16793 switch (format[fidx])
16798 const char *str = XSTR (k, fidx);
16799 len = strlen (str);
16800 result = result * 613 + len;
16801 for (i = 0; i < len; i++)
16802 result = result * 613 + (unsigned) str[i];
16807 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
16811 result = result * 613 + (unsigned) XINT (k, fidx);
16814 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
16815 result = result * 613 + (unsigned) XWINT (k, fidx);
16819 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
16820 result = result * 613 + (unsigned) (XWINT (k, fidx)
16827 gcc_unreachable ();
16834 toc_hash_function (const void *hash_entry)
16836 const struct toc_hash_struct *thc =
16837 (const struct toc_hash_struct *) hash_entry;
16838 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
16841 /* Compare H1 and H2 for equivalence. */
16844 toc_hash_eq (const void *h1, const void *h2)
16846 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16847 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16849 if (((const struct toc_hash_struct *) h1)->key_mode
16850 != ((const struct toc_hash_struct *) h2)->key_mode)
16853 return rtx_equal_p (r1, r2);
16856 /* These are the names given by the C++ front-end to vtables, and
16857 vtable-like objects. Ideally, this logic should not be here;
16858 instead, there should be some programmatic way of inquiring as
16859 to whether or not an object is a vtable. */
16861 #define VTABLE_NAME_P(NAME) \
16862 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16863 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16864 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16865 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16866 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16869 rs6000_output_symbol_ref (FILE *file, rtx x)
16871 /* Currently C++ toc references to vtables can be emitted before it
16872 is decided whether the vtable is public or private. If this is
16873 the case, then the linker will eventually complain that there is
16874 a reference to an unknown section. Thus, for vtables only,
16875 we emit the TOC reference to reference the symbol and not the
16877 const char *name = XSTR (x, 0);
16879 if (VTABLE_NAME_P (name))
16881 RS6000_OUTPUT_BASENAME (file, name);
16884 assemble_name (file, name);
16887 /* Output a TOC entry. We derive the entry name from what is being
16891 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16894 const char *name = buf;
16895 const char *real_name;
16897 HOST_WIDE_INT offset = 0;
16899 gcc_assert (!TARGET_NO_TOC);
16901 /* When the linker won't eliminate them, don't output duplicate
16902 TOC entries (this happens on AIX if there is any kind of TOC,
16903 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16905 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
16907 struct toc_hash_struct *h;
16910 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16911 time because GGC is not initialized at that point. */
16912 if (toc_hash_table == NULL)
16913 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
16914 toc_hash_eq, NULL);
16916 h = ggc_alloc (sizeof (*h));
16918 h->key_mode = mode;
16919 h->labelno = labelno;
16921 found = htab_find_slot (toc_hash_table, h, 1);
16922 if (*found == NULL)
16924 else /* This is indeed a duplicate.
16925 Set this label equal to that label. */
16927 fputs ("\t.set ", file);
16928 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16929 fprintf (file, "%d,", labelno);
16930 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16931 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
16937 /* If we're going to put a double constant in the TOC, make sure it's
16938 aligned properly when strict alignment is on. */
16939 if (GET_CODE (x) == CONST_DOUBLE
16940 && STRICT_ALIGNMENT
16941 && GET_MODE_BITSIZE (mode) >= 64
16942 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
16943 ASM_OUTPUT_ALIGN (file, 3);
16946 (*targetm.asm_out.internal_label) (file, "LC", labelno);
16948 /* Handle FP constants specially. Note that if we have a minimal
16949 TOC, things we put here aren't actually in the TOC, so we can allow
16951 if (GET_CODE (x) == CONST_DOUBLE &&
16952 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
16954 REAL_VALUE_TYPE rv;
16957 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16958 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16959 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
16961 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
16965 if (TARGET_MINIMAL_TOC)
16966 fputs (DOUBLE_INT_ASM_OP, file);
16968 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16969 k[0] & 0xffffffff, k[1] & 0xffffffff,
16970 k[2] & 0xffffffff, k[3] & 0xffffffff);
16971 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
16972 k[0] & 0xffffffff, k[1] & 0xffffffff,
16973 k[2] & 0xffffffff, k[3] & 0xffffffff);
16978 if (TARGET_MINIMAL_TOC)
16979 fputs ("\t.long ", file);
16981 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16982 k[0] & 0xffffffff, k[1] & 0xffffffff,
16983 k[2] & 0xffffffff, k[3] & 0xffffffff);
16984 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16985 k[0] & 0xffffffff, k[1] & 0xffffffff,
16986 k[2] & 0xffffffff, k[3] & 0xffffffff);
16990 else if (GET_CODE (x) == CONST_DOUBLE &&
16991 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16993 REAL_VALUE_TYPE rv;
16996 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16998 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16999 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
17001 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
17005 if (TARGET_MINIMAL_TOC)
17006 fputs (DOUBLE_INT_ASM_OP, file);
17008 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
17009 k[0] & 0xffffffff, k[1] & 0xffffffff);
17010 fprintf (file, "0x%lx%08lx\n",
17011 k[0] & 0xffffffff, k[1] & 0xffffffff);
17016 if (TARGET_MINIMAL_TOC)
17017 fputs ("\t.long ", file);
17019 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
17020 k[0] & 0xffffffff, k[1] & 0xffffffff);
17021 fprintf (file, "0x%lx,0x%lx\n",
17022 k[0] & 0xffffffff, k[1] & 0xffffffff);
17026 else if (GET_CODE (x) == CONST_DOUBLE &&
17027 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
17029 REAL_VALUE_TYPE rv;
17032 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17033 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17034 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
17036 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
17040 if (TARGET_MINIMAL_TOC)
17041 fputs (DOUBLE_INT_ASM_OP, file);
17043 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
17044 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
17049 if (TARGET_MINIMAL_TOC)
17050 fputs ("\t.long ", file);
17052 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
17053 fprintf (file, "0x%lx\n", l & 0xffffffff);
17057 else if (GET_MODE (x) == VOIDmode
17058 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
17060 unsigned HOST_WIDE_INT low;
17061 HOST_WIDE_INT high;
17063 if (GET_CODE (x) == CONST_DOUBLE)
17065 low = CONST_DOUBLE_LOW (x);
17066 high = CONST_DOUBLE_HIGH (x);
17069 #if HOST_BITS_PER_WIDE_INT == 32
17072 high = (low & 0x80000000) ? ~0 : 0;
17076 low = INTVAL (x) & 0xffffffff;
17077 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
17081 /* TOC entries are always Pmode-sized, but since this
17082 is a bigendian machine then if we're putting smaller
17083 integer constants in the TOC we have to pad them.
17084 (This is still a win over putting the constants in
17085 a separate constant pool, because then we'd have
17086 to have both a TOC entry _and_ the actual constant.)
17088 For a 32-bit target, CONST_INT values are loaded and shifted
17089 entirely within `low' and can be stored in one TOC entry. */
17091 /* It would be easy to make this work, but it doesn't now. */
17092 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
17094 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
17096 #if HOST_BITS_PER_WIDE_INT == 32
17097 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
17098 POINTER_SIZE, &low, &high, 0);
17101 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
17102 high = (HOST_WIDE_INT) low >> 32;
17109 if (TARGET_MINIMAL_TOC)
17110 fputs (DOUBLE_INT_ASM_OP, file);
17112 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
17113 (long) high & 0xffffffff, (long) low & 0xffffffff);
17114 fprintf (file, "0x%lx%08lx\n",
17115 (long) high & 0xffffffff, (long) low & 0xffffffff);
17120 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
17122 if (TARGET_MINIMAL_TOC)
17123 fputs ("\t.long ", file);
17125 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
17126 (long) high & 0xffffffff, (long) low & 0xffffffff);
17127 fprintf (file, "0x%lx,0x%lx\n",
17128 (long) high & 0xffffffff, (long) low & 0xffffffff);
17132 if (TARGET_MINIMAL_TOC)
17133 fputs ("\t.long ", file);
17135 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
17136 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
17142 if (GET_CODE (x) == CONST)
17144 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
17146 base = XEXP (XEXP (x, 0), 0);
17147 offset = INTVAL (XEXP (XEXP (x, 0), 1));
17150 switch (GET_CODE (base))
17153 name = XSTR (base, 0);
17157 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
17158 CODE_LABEL_NUMBER (XEXP (base, 0)));
17162 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
17166 gcc_unreachable ();
17169 real_name = (*targetm.strip_name_encoding) (name);
17170 if (TARGET_MINIMAL_TOC)
17171 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
17174 fprintf (file, "\t.tc %s", real_name);
17177 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
17179 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
17181 fputs ("[TC],", file);
17184 /* Currently C++ toc references to vtables can be emitted before it
17185 is decided whether the vtable is public or private. If this is
17186 the case, then the linker will eventually complain that there is
17187 a TOC reference to an unknown section. Thus, for vtables only,
17188 we emit the TOC reference to reference the symbol and not the
17190 if (VTABLE_NAME_P (name))
17192 RS6000_OUTPUT_BASENAME (file, name);
17194 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
17195 else if (offset > 0)
17196 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
17199 output_addr_const (file, x);
17203 /* Output an assembler pseudo-op to write an ASCII string of N characters
17204 starting at P to FILE.
17206 On the RS/6000, we have to do this using the .byte operation and
17207 write out special characters outside the quoted string.
17208 Also, the assembler is broken; very long strings are truncated,
17209 so we must artificially break them up early. */
17212 output_ascii (FILE *file, const char *p, int n)
17215 int i, count_string;
17216 const char *for_string = "\t.byte \"";
17217 const char *for_decimal = "\t.byte ";
17218 const char *to_close = NULL;
17221 for (i = 0; i < n; i++)
17224 if (c >= ' ' && c < 0177)
17227 fputs (for_string, file);
17230 /* Write two quotes to get one. */
17238 for_decimal = "\"\n\t.byte ";
17242 if (count_string >= 512)
17244 fputs (to_close, file);
17246 for_string = "\t.byte \"";
17247 for_decimal = "\t.byte ";
17255 fputs (for_decimal, file);
17256 fprintf (file, "%d", c);
17258 for_string = "\n\t.byte \"";
17259 for_decimal = ", ";
17265 /* Now close the string if we have written one. Then end the line. */
17267 fputs (to_close, file);
17270 /* Generate a unique section name for FILENAME for a section type
17271 represented by SECTION_DESC. Output goes into BUF.
17273 SECTION_DESC can be any string, as long as it is different for each
17274 possible section type.
17276 We name the section in the same manner as xlc. The name begins with an
17277 underscore followed by the filename (after stripping any leading directory
17278 names) with the last period replaced by the string SECTION_DESC. If
17279 FILENAME does not contain a period, SECTION_DESC is appended to the end of
17283 rs6000_gen_section_name (char **buf, const char *filename,
17284 const char *section_desc)
17286 const char *q, *after_last_slash, *last_period = 0;
17290 after_last_slash = filename;
17291 for (q = filename; *q; q++)
17294 after_last_slash = q + 1;
17295 else if (*q == '.')
17299 len = strlen (after_last_slash) + strlen (section_desc) + 2;
17300 *buf = (char *) xmalloc (len);
17305 for (q = after_last_slash; *q; q++)
17307 if (q == last_period)
17309 strcpy (p, section_desc);
17310 p += strlen (section_desc);
17314 else if (ISALNUM (*q))
17318 if (last_period == 0)
17319 strcpy (p, section_desc);
17324 /* Emit profile function. */
17327 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
17329 /* Non-standard profiling for kernels, which just saves LR then calls
17330 _mcount without worrying about arg saves. The idea is to change
17331 the function prologue as little as possible as it isn't easy to
17332 account for arg save/restore code added just for _mcount. */
17333 if (TARGET_PROFILE_KERNEL)
17336 if (DEFAULT_ABI == ABI_AIX)
17338 #ifndef NO_PROFILE_COUNTERS
17339 # define NO_PROFILE_COUNTERS 0
17341 if (NO_PROFILE_COUNTERS)
17342 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
17346 const char *label_name;
17349 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
17350 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
17351 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
17353 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
17357 else if (DEFAULT_ABI == ABI_DARWIN)
17359 const char *mcount_name = RS6000_MCOUNT;
17360 int caller_addr_regno = LR_REGNO;
17362 /* Be conservative and always set this, at least for now. */
17363 current_function_uses_pic_offset_table = 1;
17366 /* For PIC code, set up a stub and collect the caller's address
17367 from r0, which is where the prologue puts it. */
17368 if (MACHOPIC_INDIRECT
17369 && current_function_uses_pic_offset_table)
17370 caller_addr_regno = 0;
17372 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
17374 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
17378 /* Write function profiler code. */
17381 output_function_profiler (FILE *file, int labelno)
17385 switch (DEFAULT_ABI)
17388 gcc_unreachable ();
17393 warning (0, "no profiling of 64-bit code for this ABI");
17396 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
17397 fprintf (file, "\tmflr %s\n", reg_names[0]);
17398 if (NO_PROFILE_COUNTERS)
17400 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17401 reg_names[0], reg_names[1]);
17403 else if (TARGET_SECURE_PLT && flag_pic)
17405 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
17406 reg_names[0], reg_names[1]);
17407 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17408 asm_fprintf (file, "\t{cau|addis} %s,%s,",
17409 reg_names[12], reg_names[12]);
17410 assemble_name (file, buf);
17411 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
17412 assemble_name (file, buf);
17413 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
17415 else if (flag_pic == 1)
17417 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
17418 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17419 reg_names[0], reg_names[1]);
17420 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17421 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
17422 assemble_name (file, buf);
17423 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
17425 else if (flag_pic > 1)
17427 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17428 reg_names[0], reg_names[1]);
17429 /* Now, we need to get the address of the label. */
17430 fputs ("\tbcl 20,31,1f\n\t.long ", file);
17431 assemble_name (file, buf);
17432 fputs ("-.\n1:", file);
17433 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
17434 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
17435 reg_names[0], reg_names[11]);
17436 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
17437 reg_names[0], reg_names[0], reg_names[11]);
17441 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
17442 assemble_name (file, buf);
17443 fputs ("@ha\n", file);
17444 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17445 reg_names[0], reg_names[1]);
17446 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
17447 assemble_name (file, buf);
17448 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
17451 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
17452 fprintf (file, "\tbl %s%s\n",
17453 RS6000_MCOUNT, flag_pic ? "@plt" : "");
17458 if (!TARGET_PROFILE_KERNEL)
17460 /* Don't do anything, done in output_profile_hook (). */
17464 gcc_assert (!TARGET_32BIT);
17466 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
17467 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
17469 if (cfun->static_chain_decl != NULL)
17471 asm_fprintf (file, "\tstd %s,24(%s)\n",
17472 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17473 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17474 asm_fprintf (file, "\tld %s,24(%s)\n",
17475 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17478 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17486 /* The following variable value is the last issued insn. */
17488 static rtx last_scheduled_insn;
17490 /* The following variable helps to balance issuing of load and
17491 store instructions */
17493 static int load_store_pendulum;
17495 /* Power4 load update and store update instructions are cracked into a
17496 load or store and an integer insn which are executed in the same cycle.
17497 Branches have their own dispatch slot which does not count against the
17498 GCC issue rate, but it changes the program flow so there are no other
17499 instructions to issue in this cycle. */
17502 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
17503 int verbose ATTRIBUTE_UNUSED,
17504 rtx insn, int more)
17506 last_scheduled_insn = insn;
17507 if (GET_CODE (PATTERN (insn)) == USE
17508 || GET_CODE (PATTERN (insn)) == CLOBBER)
17510 cached_can_issue_more = more;
17511 return cached_can_issue_more;
17514 if (insn_terminates_group_p (insn, current_group))
17516 cached_can_issue_more = 0;
17517 return cached_can_issue_more;
17520 /* If no reservation, but reach here */
17521 if (recog_memoized (insn) < 0)
17524 if (rs6000_sched_groups)
17526 if (is_microcoded_insn (insn))
17527 cached_can_issue_more = 0;
17528 else if (is_cracked_insn (insn))
17529 cached_can_issue_more = more > 2 ? more - 2 : 0;
17531 cached_can_issue_more = more - 1;
17533 return cached_can_issue_more;
17536 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
17539 cached_can_issue_more = more - 1;
17540 return cached_can_issue_more;
17543 /* Adjust the cost of a scheduling dependency. Return the new cost of
17544 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
17547 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
17549 enum attr_type attr_type;
17551 if (! recog_memoized (insn))
17554 switch (REG_NOTE_KIND (link))
17558 /* Data dependency; DEP_INSN writes a register that INSN reads
17559 some cycles later. */
17561 /* Separate a load from a narrower, dependent store. */
17562 if (rs6000_sched_groups
17563 && GET_CODE (PATTERN (insn)) == SET
17564 && GET_CODE (PATTERN (dep_insn)) == SET
17565 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
17566 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
17567 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
17568 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
17571 attr_type = get_attr_type (insn);
17576 /* Tell the first scheduling pass about the latency between
17577 a mtctr and bctr (and mtlr and br/blr). The first
17578 scheduling pass will not know about this latency since
17579 the mtctr instruction, which has the latency associated
17580 to it, will be generated by reload. */
17581 return TARGET_POWER ? 5 : 4;
17583 /* Leave some extra cycles between a compare and its
17584 dependent branch, to inhibit expensive mispredicts. */
17585 if ((rs6000_cpu_attr == CPU_PPC603
17586 || rs6000_cpu_attr == CPU_PPC604
17587 || rs6000_cpu_attr == CPU_PPC604E
17588 || rs6000_cpu_attr == CPU_PPC620
17589 || rs6000_cpu_attr == CPU_PPC630
17590 || rs6000_cpu_attr == CPU_PPC750
17591 || rs6000_cpu_attr == CPU_PPC7400
17592 || rs6000_cpu_attr == CPU_PPC7450
17593 || rs6000_cpu_attr == CPU_POWER4
17594 || rs6000_cpu_attr == CPU_POWER5
17595 || rs6000_cpu_attr == CPU_CELL)
17596 && recog_memoized (dep_insn)
17597 && (INSN_CODE (dep_insn) >= 0))
17599 switch (get_attr_type (dep_insn))
17603 case TYPE_DELAYED_COMPARE:
17604 case TYPE_IMUL_COMPARE:
17605 case TYPE_LMUL_COMPARE:
17606 case TYPE_FPCOMPARE:
17607 case TYPE_CR_LOGICAL:
17608 case TYPE_DELAYED_CR:
17617 case TYPE_STORE_UX:
17619 case TYPE_FPSTORE_U:
17620 case TYPE_FPSTORE_UX:
17621 if ((rs6000_cpu == PROCESSOR_POWER6)
17622 && recog_memoized (dep_insn)
17623 && (INSN_CODE (dep_insn) >= 0))
17626 if (GET_CODE (PATTERN (insn)) != SET)
17627 /* If this happens, we have to extend this to schedule
17628 optimally. Return default for now. */
17631 /* Adjust the cost for the case where the value written
17632 by a fixed point operation is used as the address
17633 gen value on a store. */
17634 switch (get_attr_type (dep_insn))
17641 if (! store_data_bypass_p (dep_insn, insn))
17645 case TYPE_LOAD_EXT:
17646 case TYPE_LOAD_EXT_U:
17647 case TYPE_LOAD_EXT_UX:
17648 case TYPE_VAR_SHIFT_ROTATE:
17649 case TYPE_VAR_DELAYED_COMPARE:
17651 if (! store_data_bypass_p (dep_insn, insn))
17657 case TYPE_FAST_COMPARE:
17660 case TYPE_INSERT_WORD:
17661 case TYPE_INSERT_DWORD:
17662 case TYPE_FPLOAD_U:
17663 case TYPE_FPLOAD_UX:
17665 case TYPE_STORE_UX:
17666 case TYPE_FPSTORE_U:
17667 case TYPE_FPSTORE_UX:
17669 if (! store_data_bypass_p (dep_insn, insn))
17677 case TYPE_IMUL_COMPARE:
17678 case TYPE_LMUL_COMPARE:
17680 if (! store_data_bypass_p (dep_insn, insn))
17686 if (! store_data_bypass_p (dep_insn, insn))
17692 if (! store_data_bypass_p (dep_insn, insn))
17705 case TYPE_LOAD_EXT:
17706 case TYPE_LOAD_EXT_U:
17707 case TYPE_LOAD_EXT_UX:
17708 if ((rs6000_cpu == PROCESSOR_POWER6)
17709 && recog_memoized (dep_insn)
17710 && (INSN_CODE (dep_insn) >= 0))
17713 /* Adjust the cost for the case where the value written
17714 by a fixed point instruction is used within the address
17715 gen portion of a subsequent load(u)(x) */
17716 switch (get_attr_type (dep_insn))
17723 if (set_to_load_agen (dep_insn, insn))
17727 case TYPE_LOAD_EXT:
17728 case TYPE_LOAD_EXT_U:
17729 case TYPE_LOAD_EXT_UX:
17730 case TYPE_VAR_SHIFT_ROTATE:
17731 case TYPE_VAR_DELAYED_COMPARE:
17733 if (set_to_load_agen (dep_insn, insn))
17739 case TYPE_FAST_COMPARE:
17742 case TYPE_INSERT_WORD:
17743 case TYPE_INSERT_DWORD:
17744 case TYPE_FPLOAD_U:
17745 case TYPE_FPLOAD_UX:
17747 case TYPE_STORE_UX:
17748 case TYPE_FPSTORE_U:
17749 case TYPE_FPSTORE_UX:
17751 if (set_to_load_agen (dep_insn, insn))
17759 case TYPE_IMUL_COMPARE:
17760 case TYPE_LMUL_COMPARE:
17762 if (set_to_load_agen (dep_insn, insn))
17768 if (set_to_load_agen (dep_insn, insn))
17774 if (set_to_load_agen (dep_insn, insn))
17785 if ((rs6000_cpu == PROCESSOR_POWER6)
17786 && recog_memoized (dep_insn)
17787 && (INSN_CODE (dep_insn) >= 0)
17788 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
17795 /* Fall out to return default cost. */
17799 case REG_DEP_OUTPUT:
17800 /* Output dependency; DEP_INSN writes a register that INSN writes some
17802 if ((rs6000_cpu == PROCESSOR_POWER6)
17803 && recog_memoized (dep_insn)
17804 && (INSN_CODE (dep_insn) >= 0))
17806 attr_type = get_attr_type (insn);
17811 if (get_attr_type (dep_insn) == TYPE_FP)
17815 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
17823 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17828 gcc_unreachable ();
17834 /* The function returns a true if INSN is microcoded.
17835 Return false otherwise. */
17838 is_microcoded_insn (rtx insn)
17840 if (!insn || !INSN_P (insn)
17841 || GET_CODE (PATTERN (insn)) == USE
17842 || GET_CODE (PATTERN (insn)) == CLOBBER)
17845 if (rs6000_cpu_attr == CPU_CELL)
17846 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17848 if (rs6000_sched_groups)
17850 enum attr_type type = get_attr_type (insn);
17851 if (type == TYPE_LOAD_EXT_U
17852 || type == TYPE_LOAD_EXT_UX
17853 || type == TYPE_LOAD_UX
17854 || type == TYPE_STORE_UX
17855 || type == TYPE_MFCR)
17862 /* The function returns true if INSN is cracked into 2 instructions
17863 by the processor (and therefore occupies 2 issue slots). */
17866 is_cracked_insn (rtx insn)
17868 if (!insn || !INSN_P (insn)
17869 || GET_CODE (PATTERN (insn)) == USE
17870 || GET_CODE (PATTERN (insn)) == CLOBBER)
17873 if (rs6000_sched_groups)
17875 enum attr_type type = get_attr_type (insn);
17876 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17877 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17878 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17879 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17880 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17881 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17882 || type == TYPE_IDIV || type == TYPE_LDIV
17883 || type == TYPE_INSERT_WORD)
17890 /* The function returns true if INSN can be issued only from
17891 the branch slot. */
17894 is_branch_slot_insn (rtx insn)
17896 if (!insn || !INSN_P (insn)
17897 || GET_CODE (PATTERN (insn)) == USE
17898 || GET_CODE (PATTERN (insn)) == CLOBBER)
17901 if (rs6000_sched_groups)
17903 enum attr_type type = get_attr_type (insn);
17904 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
17912 /* The function returns true if out_inst sets a value that is
17913 used in the address generation computation of in_insn */
17915 set_to_load_agen (rtx out_insn, rtx in_insn)
17917 rtx out_set, in_set;
17919 /* For performance reasons, only handle the simple case where
17920 both loads are a single_set. */
17921 out_set = single_set (out_insn);
17924 in_set = single_set (in_insn);
17926 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
17932 /* The function returns true if the target storage location of
17933 out_insn is adjacent to the target storage location of in_insn */
17934 /* Return 1 if memory locations are adjacent. */
17937 adjacent_mem_locations (rtx insn1, rtx insn2)
17940 rtx a = get_store_dest (PATTERN (insn1));
17941 rtx b = get_store_dest (PATTERN (insn2));
17943 if ((GET_CODE (XEXP (a, 0)) == REG
17944 || (GET_CODE (XEXP (a, 0)) == PLUS
17945 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
17946 && (GET_CODE (XEXP (b, 0)) == REG
17947 || (GET_CODE (XEXP (b, 0)) == PLUS
17948 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
17950 HOST_WIDE_INT val0 = 0, val1 = 0;
17954 if (GET_CODE (XEXP (a, 0)) == PLUS)
17956 reg0 = XEXP (XEXP (a, 0), 0);
17957 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
17960 reg0 = XEXP (a, 0);
17962 if (GET_CODE (XEXP (b, 0)) == PLUS)
17964 reg1 = XEXP (XEXP (b, 0), 0);
17965 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
17968 reg1 = XEXP (b, 0);
17970 val_diff = val1 - val0;
17972 return ((REGNO (reg0) == REGNO (reg1))
17973 && (val_diff == INTVAL (MEM_SIZE (a))
17974 || val_diff == -INTVAL (MEM_SIZE (b))));
17980 /* A C statement (sans semicolon) to update the integer scheduling
17981 priority INSN_PRIORITY (INSN). Increase the priority to execute the
17982 INSN earlier, reduce the priority to execute INSN later. Do not
17983 define this macro if you do not need to adjust the scheduling
17984 priorities of insns. */
17987 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
17989 /* On machines (like the 750) which have asymmetric integer units,
17990 where one integer unit can do multiply and divides and the other
17991 can't, reduce the priority of multiply/divide so it is scheduled
17992 before other integer operations. */
17995 if (! INSN_P (insn))
17998 if (GET_CODE (PATTERN (insn)) == USE)
18001 switch (rs6000_cpu_attr) {
18003 switch (get_attr_type (insn))
18010 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
18011 priority, priority);
18012 if (priority >= 0 && priority < 0x01000000)
18019 if (insn_must_be_first_in_group (insn)
18020 && reload_completed
18021 && current_sched_info->sched_max_insns_priority
18022 && rs6000_sched_restricted_insns_priority)
18025 /* Prioritize insns that can be dispatched only in the first
18027 if (rs6000_sched_restricted_insns_priority == 1)
18028 /* Attach highest priority to insn. This means that in
18029 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
18030 precede 'priority' (critical path) considerations. */
18031 return current_sched_info->sched_max_insns_priority;
18032 else if (rs6000_sched_restricted_insns_priority == 2)
18033 /* Increase priority of insn by a minimal amount. This means that in
18034 haifa-sched.c:ready_sort(), only 'priority' (critical path)
18035 considerations precede dispatch-slot restriction considerations. */
18036 return (priority + 1);
18039 if (rs6000_cpu == PROCESSOR_POWER6
18040 && ((load_store_pendulum == -2 && is_load_insn (insn))
18041 || (load_store_pendulum == 2 && is_store_insn (insn))))
18042 /* Attach highest priority to insn if the scheduler has just issued two
18043 stores and this instruction is a load, or two loads and this instruction
18044 is a store. Power6 wants loads and stores scheduled alternately
18046 return current_sched_info->sched_max_insns_priority;
18051 /* Return true if the instruction is nonpipelined on the Cell. */
18053 is_nonpipeline_insn (rtx insn)
18055 enum attr_type type;
18056 if (!insn || !INSN_P (insn)
18057 || GET_CODE (PATTERN (insn)) == USE
18058 || GET_CODE (PATTERN (insn)) == CLOBBER)
18061 type = get_attr_type (insn);
18062 if (type == TYPE_IMUL
18063 || type == TYPE_IMUL2
18064 || type == TYPE_IMUL3
18065 || type == TYPE_LMUL
18066 || type == TYPE_IDIV
18067 || type == TYPE_LDIV
18068 || type == TYPE_SDIV
18069 || type == TYPE_DDIV
18070 || type == TYPE_SSQRT
18071 || type == TYPE_DSQRT
18072 || type == TYPE_MFCR
18073 || type == TYPE_MFCRF
18074 || type == TYPE_MFJMPR)
18082 /* Return how many instructions the machine can issue per cycle. */
18085 rs6000_issue_rate (void)
18087 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
18088 if (!reload_completed)
18091 switch (rs6000_cpu_attr) {
18092 case CPU_RIOS1: /* ? */
18094 case CPU_PPC601: /* ? */
18119 /* Return how many instructions to look ahead for better insn
18123 rs6000_use_sched_lookahead (void)
18125 if (rs6000_cpu_attr == CPU_PPC8540)
18127 if (rs6000_cpu_attr == CPU_CELL)
18128 return (reload_completed ? 8 : 0);
18132 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
18134 rs6000_use_sched_lookahead_guard (rtx insn)
18136 if (rs6000_cpu_attr != CPU_CELL)
18139 if (insn == NULL_RTX || !INSN_P (insn))
18142 if (!reload_completed
18143 || is_nonpipeline_insn (insn)
18144 || is_microcoded_insn (insn))
18150 /* Determine is PAT refers to memory. */
18153 is_mem_ref (rtx pat)
18159 if (GET_CODE (pat) == MEM)
18162 /* Recursively process the pattern. */
18163 fmt = GET_RTX_FORMAT (GET_CODE (pat));
18165 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
18168 ret |= is_mem_ref (XEXP (pat, i));
18169 else if (fmt[i] == 'E')
18170 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
18171 ret |= is_mem_ref (XVECEXP (pat, i, j));
18177 /* Determine if PAT is a PATTERN of a load insn. */
18180 is_load_insn1 (rtx pat)
18182 if (!pat || pat == NULL_RTX)
18185 if (GET_CODE (pat) == SET)
18186 return is_mem_ref (SET_SRC (pat));
18188 if (GET_CODE (pat) == PARALLEL)
18192 for (i = 0; i < XVECLEN (pat, 0); i++)
18193 if (is_load_insn1 (XVECEXP (pat, 0, i)))
18200 /* Determine if INSN loads from memory. */
18203 is_load_insn (rtx insn)
18205 if (!insn || !INSN_P (insn))
18208 if (GET_CODE (insn) == CALL_INSN)
18211 return is_load_insn1 (PATTERN (insn));
18214 /* Determine if PAT is a PATTERN of a store insn. */
18217 is_store_insn1 (rtx pat)
18219 if (!pat || pat == NULL_RTX)
18222 if (GET_CODE (pat) == SET)
18223 return is_mem_ref (SET_DEST (pat));
18225 if (GET_CODE (pat) == PARALLEL)
18229 for (i = 0; i < XVECLEN (pat, 0); i++)
18230 if (is_store_insn1 (XVECEXP (pat, 0, i)))
18237 /* Determine if INSN stores to memory. */
18240 is_store_insn (rtx insn)
18242 if (!insn || !INSN_P (insn))
18245 return is_store_insn1 (PATTERN (insn));
18248 /* Return the dest of a store insn. */
18251 get_store_dest (rtx pat)
18253 gcc_assert (is_store_insn1 (pat));
18255 if (GET_CODE (pat) == SET)
18256 return SET_DEST (pat);
18257 else if (GET_CODE (pat) == PARALLEL)
18261 for (i = 0; i < XVECLEN (pat, 0); i++)
18263 rtx inner_pat = XVECEXP (pat, 0, i);
18264 if (GET_CODE (inner_pat) == SET
18265 && is_mem_ref (SET_DEST (inner_pat)))
18269 /* We shouldn't get here, because we should have either a simple
18270 store insn or a store with update which are covered above. */
18274 /* Returns whether the dependence between INSN and NEXT is considered
18275 costly by the given target. */
18278 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
18283 /* If the flag is not enabled - no dependence is considered costly;
18284 allow all dependent insns in the same group.
18285 This is the most aggressive option. */
18286 if (rs6000_sched_costly_dep == no_dep_costly)
18289 /* If the flag is set to 1 - a dependence is always considered costly;
18290 do not allow dependent instructions in the same group.
18291 This is the most conservative option. */
18292 if (rs6000_sched_costly_dep == all_deps_costly)
18295 insn = DEP_PRO (dep);
18296 next = DEP_CON (dep);
18298 if (rs6000_sched_costly_dep == store_to_load_dep_costly
18299 && is_load_insn (next)
18300 && is_store_insn (insn))
18301 /* Prevent load after store in the same group. */
18304 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
18305 && is_load_insn (next)
18306 && is_store_insn (insn)
18307 && DEP_TYPE (dep) == REG_DEP_TRUE)
18308 /* Prevent load after store in the same group if it is a true
18312 /* The flag is set to X; dependences with latency >= X are considered costly,
18313 and will not be scheduled in the same group. */
18314 if (rs6000_sched_costly_dep <= max_dep_latency
18315 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
18321 /* Return the next insn after INSN that is found before TAIL is reached,
18322 skipping any "non-active" insns - insns that will not actually occupy
18323 an issue slot. Return NULL_RTX if such an insn is not found. */
18326 get_next_active_insn (rtx insn, rtx tail)
18328 if (insn == NULL_RTX || insn == tail)
18333 insn = NEXT_INSN (insn);
18334 if (insn == NULL_RTX || insn == tail)
18339 || (NONJUMP_INSN_P (insn)
18340 && GET_CODE (PATTERN (insn)) != USE
18341 && GET_CODE (PATTERN (insn)) != CLOBBER
18342 && INSN_CODE (insn) != CODE_FOR_stack_tie))
18348 /* We are about to begin issuing insns for this clock cycle. */
18351 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
18352 rtx *ready ATTRIBUTE_UNUSED,
18353 int *pn_ready ATTRIBUTE_UNUSED,
18354 int clock_var ATTRIBUTE_UNUSED)
18356 int n_ready = *pn_ready;
18359 fprintf (dump, "// rs6000_sched_reorder :\n");
18361 /* Reorder the ready list, if the second to last ready insn
18362 is a nonepipeline insn. */
18363 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
18365 if (is_nonpipeline_insn (ready[n_ready - 1])
18366 && (recog_memoized (ready[n_ready - 2]) > 0))
18367 /* Simply swap first two insns. */
18369 rtx tmp = ready[n_ready - 1];
18370 ready[n_ready - 1] = ready[n_ready - 2];
18371 ready[n_ready - 2] = tmp;
18375 if (rs6000_cpu == PROCESSOR_POWER6)
18376 load_store_pendulum = 0;
18378 return rs6000_issue_rate ();
18381 /* Like rs6000_sched_reorder, but called after issuing each insn. */
18384 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
18385 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
18388 fprintf (dump, "// rs6000_sched_reorder2 :\n");
18390 /* For Power6, we need to handle some special cases to try and keep the
18391 store queue from overflowing and triggering expensive flushes.
18393 This code monitors how load and store instructions are being issued
18394 and skews the ready list one way or the other to increase the likelihood
18395 that a desired instruction is issued at the proper time.
18397 A couple of things are done. First, we maintain a "load_store_pendulum"
18398 to track the current state of load/store issue.
18400 - If the pendulum is at zero, then no loads or stores have been
18401 issued in the current cycle so we do nothing.
18403 - If the pendulum is 1, then a single load has been issued in this
18404 cycle and we attempt to locate another load in the ready list to
18407 - If the pendulum is -2, then two stores have already been
18408 issued in this cycle, so we increase the priority of the first load
18409 in the ready list to increase it's likelihood of being chosen first
18412 - If the pendulum is -1, then a single store has been issued in this
18413 cycle and we attempt to locate another store in the ready list to
18414 issue with it, preferring a store to an adjacent memory location to
18415 facilitate store pairing in the store queue.
18417 - If the pendulum is 2, then two loads have already been
18418 issued in this cycle, so we increase the priority of the first store
18419 in the ready list to increase it's likelihood of being chosen first
18422 - If the pendulum < -2 or > 2, then do nothing.
18424 Note: This code covers the most common scenarios. There exist non
18425 load/store instructions which make use of the LSU and which
18426 would need to be accounted for to strictly model the behavior
18427 of the machine. Those instructions are currently unaccounted
18428 for to help minimize compile time overhead of this code.
18430 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
18436 if (is_store_insn (last_scheduled_insn))
18437 /* Issuing a store, swing the load_store_pendulum to the left */
18438 load_store_pendulum--;
18439 else if (is_load_insn (last_scheduled_insn))
18440 /* Issuing a load, swing the load_store_pendulum to the right */
18441 load_store_pendulum++;
18443 return cached_can_issue_more;
18445 /* If the pendulum is balanced, or there is only one instruction on
18446 the ready list, then all is well, so return. */
18447 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
18448 return cached_can_issue_more;
18450 if (load_store_pendulum == 1)
18452 /* A load has been issued in this cycle. Scan the ready list
18453 for another load to issue with it */
18458 if (is_load_insn (ready[pos]))
18460 /* Found a load. Move it to the head of the ready list,
18461 and adjust it's priority so that it is more likely to
18464 for (i=pos; i<*pn_ready-1; i++)
18465 ready[i] = ready[i + 1];
18466 ready[*pn_ready-1] = tmp;
18467 if INSN_PRIORITY_KNOWN (tmp)
18468 INSN_PRIORITY (tmp)++;
18474 else if (load_store_pendulum == -2)
18476 /* Two stores have been issued in this cycle. Increase the
18477 priority of the first load in the ready list to favor it for
18478 issuing in the next cycle. */
18483 if (is_load_insn (ready[pos])
18484 && INSN_PRIORITY_KNOWN (ready[pos]))
18486 INSN_PRIORITY (ready[pos])++;
18488 /* Adjust the pendulum to account for the fact that a load
18489 was found and increased in priority. This is to prevent
18490 increasing the priority of multiple loads */
18491 load_store_pendulum--;
18498 else if (load_store_pendulum == -1)
18500 /* A store has been issued in this cycle. Scan the ready list for
18501 another store to issue with it, preferring a store to an adjacent
18503 int first_store_pos = -1;
18509 if (is_store_insn (ready[pos]))
18511 /* Maintain the index of the first store found on the
18513 if (first_store_pos == -1)
18514 first_store_pos = pos;
18516 if (is_store_insn (last_scheduled_insn)
18517 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
18519 /* Found an adjacent store. Move it to the head of the
18520 ready list, and adjust it's priority so that it is
18521 more likely to stay there */
18523 for (i=pos; i<*pn_ready-1; i++)
18524 ready[i] = ready[i + 1];
18525 ready[*pn_ready-1] = tmp;
18526 if INSN_PRIORITY_KNOWN (tmp)
18527 INSN_PRIORITY (tmp)++;
18528 first_store_pos = -1;
18536 if (first_store_pos >= 0)
18538 /* An adjacent store wasn't found, but a non-adjacent store was,
18539 so move the non-adjacent store to the front of the ready
18540 list, and adjust its priority so that it is more likely to
18542 tmp = ready[first_store_pos];
18543 for (i=first_store_pos; i<*pn_ready-1; i++)
18544 ready[i] = ready[i + 1];
18545 ready[*pn_ready-1] = tmp;
18546 if INSN_PRIORITY_KNOWN (tmp)
18547 INSN_PRIORITY (tmp)++;
18550 else if (load_store_pendulum == 2)
18552 /* Two loads have been issued in this cycle. Increase the priority
18553 of the first store in the ready list to favor it for issuing in
18559 if (is_store_insn (ready[pos])
18560 && INSN_PRIORITY_KNOWN (ready[pos]))
18562 INSN_PRIORITY (ready[pos])++;
18564 /* Adjust the pendulum to account for the fact that a store
18565 was found and increased in priority. This is to prevent
18566 increasing the priority of multiple stores */
18567 load_store_pendulum++;
18576 return cached_can_issue_more;
18579 /* Return whether the presence of INSN causes a dispatch group termination
18580 of group WHICH_GROUP.
18582 If WHICH_GROUP == current_group, this function will return true if INSN
18583 causes the termination of the current group (i.e, the dispatch group to
18584 which INSN belongs). This means that INSN will be the last insn in the
18585 group it belongs to.
18587 If WHICH_GROUP == previous_group, this function will return true if INSN
18588 causes the termination of the previous group (i.e, the dispatch group that
18589 precedes the group to which INSN belongs). This means that INSN will be
18590 the first insn in the group it belongs to). */
18593 insn_terminates_group_p (rtx insn, enum group_termination which_group)
18600 first = insn_must_be_first_in_group (insn);
18601 last = insn_must_be_last_in_group (insn);
18606 if (which_group == current_group)
18608 else if (which_group == previous_group)
18616 insn_must_be_first_in_group (rtx insn)
18618 enum attr_type type;
18621 || insn == NULL_RTX
18622 || GET_CODE (insn) == NOTE
18623 || GET_CODE (PATTERN (insn)) == USE
18624 || GET_CODE (PATTERN (insn)) == CLOBBER)
18627 switch (rs6000_cpu)
18629 case PROCESSOR_POWER5:
18630 if (is_cracked_insn (insn))
18632 case PROCESSOR_POWER4:
18633 if (is_microcoded_insn (insn))
18636 if (!rs6000_sched_groups)
18639 type = get_attr_type (insn);
18646 case TYPE_DELAYED_CR:
18647 case TYPE_CR_LOGICAL:
18661 case PROCESSOR_POWER6:
18662 type = get_attr_type (insn);
18666 case TYPE_INSERT_DWORD:
18670 case TYPE_VAR_SHIFT_ROTATE:
18677 case TYPE_INSERT_WORD:
18678 case TYPE_DELAYED_COMPARE:
18679 case TYPE_IMUL_COMPARE:
18680 case TYPE_LMUL_COMPARE:
18681 case TYPE_FPCOMPARE:
18692 case TYPE_LOAD_EXT_UX:
18694 case TYPE_STORE_UX:
18695 case TYPE_FPLOAD_U:
18696 case TYPE_FPLOAD_UX:
18697 case TYPE_FPSTORE_U:
18698 case TYPE_FPSTORE_UX:
18712 insn_must_be_last_in_group (rtx insn)
18714 enum attr_type type;
18717 || insn == NULL_RTX
18718 || GET_CODE (insn) == NOTE
18719 || GET_CODE (PATTERN (insn)) == USE
18720 || GET_CODE (PATTERN (insn)) == CLOBBER)
18723 switch (rs6000_cpu) {
18724 case PROCESSOR_POWER4:
18725 case PROCESSOR_POWER5:
18726 if (is_microcoded_insn (insn))
18729 if (is_branch_slot_insn (insn))
18733 case PROCESSOR_POWER6:
18734 type = get_attr_type (insn);
18741 case TYPE_VAR_SHIFT_ROTATE:
18748 case TYPE_DELAYED_COMPARE:
18749 case TYPE_IMUL_COMPARE:
18750 case TYPE_LMUL_COMPARE:
18751 case TYPE_FPCOMPARE:
18772 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18773 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18776 is_costly_group (rtx *group_insns, rtx next_insn)
18779 int issue_rate = rs6000_issue_rate ();
18781 for (i = 0; i < issue_rate; i++)
18783 sd_iterator_def sd_it;
18785 rtx insn = group_insns[i];
18790 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
18792 rtx next = DEP_CON (dep);
18794 if (next == next_insn
18795 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
18803 /* Utility of the function redefine_groups.
18804 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18805 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18806 to keep it "far" (in a separate group) from GROUP_INSNS, following
18807 one of the following schemes, depending on the value of the flag
18808 -minsert_sched_nops = X:
18809 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18810 in order to force NEXT_INSN into a separate group.
18811 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18812 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18813 insertion (has a group just ended, how many vacant issue slots remain in the
18814 last group, and how many dispatch groups were encountered so far). */
18817 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
18818 rtx next_insn, bool *group_end, int can_issue_more,
18823 int issue_rate = rs6000_issue_rate ();
18824 bool end = *group_end;
18827 if (next_insn == NULL_RTX)
18828 return can_issue_more;
18830 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
18831 return can_issue_more;
18833 force = is_costly_group (group_insns, next_insn);
18835 return can_issue_more;
18837 if (sched_verbose > 6)
18838 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
18839 *group_count ,can_issue_more);
18841 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
18844 can_issue_more = 0;
18846 /* Since only a branch can be issued in the last issue_slot, it is
18847 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18848 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18849 in this case the last nop will start a new group and the branch
18850 will be forced to the new group. */
18851 if (can_issue_more && !is_branch_slot_insn (next_insn))
18854 while (can_issue_more > 0)
18857 emit_insn_before (nop, next_insn);
18865 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18867 int n_nops = rs6000_sched_insert_nops;
18869 /* Nops can't be issued from the branch slot, so the effective
18870 issue_rate for nops is 'issue_rate - 1'. */
18871 if (can_issue_more == 0)
18872 can_issue_more = issue_rate;
18874 if (can_issue_more == 0)
18876 can_issue_more = issue_rate - 1;
18879 for (i = 0; i < issue_rate; i++)
18881 group_insns[i] = 0;
18888 emit_insn_before (nop, next_insn);
18889 if (can_issue_more == issue_rate - 1) /* new group begins */
18892 if (can_issue_more == 0)
18894 can_issue_more = issue_rate - 1;
18897 for (i = 0; i < issue_rate; i++)
18899 group_insns[i] = 0;
18905 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18908 /* Is next_insn going to start a new group? */
18911 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18912 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18913 || (can_issue_more < issue_rate &&
18914 insn_terminates_group_p (next_insn, previous_group)));
18915 if (*group_end && end)
18918 if (sched_verbose > 6)
18919 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
18920 *group_count, can_issue_more);
18921 return can_issue_more;
18924 return can_issue_more;
18927 /* This function tries to synch the dispatch groups that the compiler "sees"
18928 with the dispatch groups that the processor dispatcher is expected to
18929 form in practice. It tries to achieve this synchronization by forcing the
18930 estimated processor grouping on the compiler (as opposed to the function
18931 'pad_goups' which tries to force the scheduler's grouping on the processor).
18933 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18934 examines the (estimated) dispatch groups that will be formed by the processor
18935 dispatcher. It marks these group boundaries to reflect the estimated
18936 processor grouping, overriding the grouping that the scheduler had marked.
18937 Depending on the value of the flag '-minsert-sched-nops' this function can
18938 force certain insns into separate groups or force a certain distance between
18939 them by inserting nops, for example, if there exists a "costly dependence"
18942 The function estimates the group boundaries that the processor will form as
18943 follows: It keeps track of how many vacant issue slots are available after
18944 each insn. A subsequent insn will start a new group if one of the following
18946 - no more vacant issue slots remain in the current dispatch group.
18947 - only the last issue slot, which is the branch slot, is vacant, but the next
18948 insn is not a branch.
18949 - only the last 2 or less issue slots, including the branch slot, are vacant,
18950 which means that a cracked insn (which occupies two issue slots) can't be
18951 issued in this group.
18952 - less than 'issue_rate' slots are vacant, and the next insn always needs to
18953 start a new group. */
18956 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18958 rtx insn, next_insn;
18960 int can_issue_more;
18963 int group_count = 0;
18967 issue_rate = rs6000_issue_rate ();
18968 group_insns = alloca (issue_rate * sizeof (rtx));
18969 for (i = 0; i < issue_rate; i++)
18971 group_insns[i] = 0;
18973 can_issue_more = issue_rate;
18975 insn = get_next_active_insn (prev_head_insn, tail);
18978 while (insn != NULL_RTX)
18980 slot = (issue_rate - can_issue_more);
18981 group_insns[slot] = insn;
18983 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18984 if (insn_terminates_group_p (insn, current_group))
18985 can_issue_more = 0;
18987 next_insn = get_next_active_insn (insn, tail);
18988 if (next_insn == NULL_RTX)
18989 return group_count + 1;
18991 /* Is next_insn going to start a new group? */
18993 = (can_issue_more == 0
18994 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18995 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18996 || (can_issue_more < issue_rate &&
18997 insn_terminates_group_p (next_insn, previous_group)));
18999 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
19000 next_insn, &group_end, can_issue_more,
19006 can_issue_more = 0;
19007 for (i = 0; i < issue_rate; i++)
19009 group_insns[i] = 0;
19013 if (GET_MODE (next_insn) == TImode && can_issue_more)
19014 PUT_MODE (next_insn, VOIDmode);
19015 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
19016 PUT_MODE (next_insn, TImode);
19019 if (can_issue_more == 0)
19020 can_issue_more = issue_rate;
19023 return group_count;
19026 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
19027 dispatch group boundaries that the scheduler had marked. Pad with nops
19028 any dispatch groups which have vacant issue slots, in order to force the
19029 scheduler's grouping on the processor dispatcher. The function
19030 returns the number of dispatch groups found. */
19033 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
19035 rtx insn, next_insn;
19038 int can_issue_more;
19040 int group_count = 0;
19042 /* Initialize issue_rate. */
19043 issue_rate = rs6000_issue_rate ();
19044 can_issue_more = issue_rate;
19046 insn = get_next_active_insn (prev_head_insn, tail);
19047 next_insn = get_next_active_insn (insn, tail);
19049 while (insn != NULL_RTX)
19052 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
19054 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
19056 if (next_insn == NULL_RTX)
19061 /* If the scheduler had marked group termination at this location
19062 (between insn and next_indn), and neither insn nor next_insn will
19063 force group termination, pad the group with nops to force group
19066 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
19067 && !insn_terminates_group_p (insn, current_group)
19068 && !insn_terminates_group_p (next_insn, previous_group))
19070 if (!is_branch_slot_insn (next_insn))
19073 while (can_issue_more)
19076 emit_insn_before (nop, next_insn);
19081 can_issue_more = issue_rate;
19086 next_insn = get_next_active_insn (insn, tail);
19089 return group_count;
19092 /* We're beginning a new block. Initialize data structures as necessary. */
19095 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
19096 int sched_verbose ATTRIBUTE_UNUSED,
19097 int max_ready ATTRIBUTE_UNUSED)
19099 last_scheduled_insn = NULL_RTX;
19100 load_store_pendulum = 0;
19103 /* The following function is called at the end of scheduling BB.
19104 After reload, it inserts nops at insn group bundling. */
19107 rs6000_sched_finish (FILE *dump, int sched_verbose)
19112 fprintf (dump, "=== Finishing schedule.\n");
19114 if (reload_completed && rs6000_sched_groups)
19116 if (rs6000_sched_insert_nops == sched_finish_none)
19119 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
19120 n_groups = pad_groups (dump, sched_verbose,
19121 current_sched_info->prev_head,
19122 current_sched_info->next_tail);
19124 n_groups = redefine_groups (dump, sched_verbose,
19125 current_sched_info->prev_head,
19126 current_sched_info->next_tail);
19128 if (sched_verbose >= 6)
19130 fprintf (dump, "ngroups = %d\n", n_groups);
19131 print_rtl (dump, current_sched_info->prev_head);
19132 fprintf (dump, "Done finish_sched\n");
19137 /* Length in units of the trampoline for entering a nested function. */
19140 rs6000_trampoline_size (void)
19144 switch (DEFAULT_ABI)
19147 gcc_unreachable ();
19150 ret = (TARGET_32BIT) ? 12 : 24;
19155 ret = (TARGET_32BIT) ? 40 : 48;
19162 /* Emit RTL insns to initialize the variable parts of a trampoline.
19163 FNADDR is an RTX for the address of the function's pure code.
19164 CXT is an RTX for the static chain value for the function. */
19167 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
19169 int regsize = (TARGET_32BIT) ? 4 : 8;
19170 rtx ctx_reg = force_reg (Pmode, cxt);
19172 switch (DEFAULT_ABI)
19175 gcc_unreachable ();
19177 /* Macros to shorten the code expansions below. */
19178 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
19179 #define MEM_PLUS(addr,offset) \
19180 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
19182 /* Under AIX, just build the 3 word function descriptor */
19185 rtx fn_reg = gen_reg_rtx (Pmode);
19186 rtx toc_reg = gen_reg_rtx (Pmode);
19187 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
19188 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
19189 emit_move_insn (MEM_DEREF (addr), fn_reg);
19190 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
19191 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
19195 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
19198 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
19199 FALSE, VOIDmode, 4,
19201 GEN_INT (rs6000_trampoline_size ()), SImode,
19211 /* Table of valid machine attributes. */
19213 const struct attribute_spec rs6000_attribute_table[] =
19215 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
19216 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
19217 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
19218 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
19219 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
19220 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
19221 #ifdef SUBTARGET_ATTRIBUTE_TABLE
19222 SUBTARGET_ATTRIBUTE_TABLE,
19224 { NULL, 0, 0, false, false, false, NULL }
19227 /* Handle the "altivec" attribute. The attribute may have
19228 arguments as follows:
19230 __attribute__((altivec(vector__)))
19231 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
19232 __attribute__((altivec(bool__))) (always followed by 'unsigned')
19234 and may appear more than once (e.g., 'vector bool char') in a
19235 given declaration. */
19238 rs6000_handle_altivec_attribute (tree *node,
19239 tree name ATTRIBUTE_UNUSED,
19241 int flags ATTRIBUTE_UNUSED,
19242 bool *no_add_attrs)
19244 tree type = *node, result = NULL_TREE;
19245 enum machine_mode mode;
19248 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
19249 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
19250 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
19253 while (POINTER_TYPE_P (type)
19254 || TREE_CODE (type) == FUNCTION_TYPE
19255 || TREE_CODE (type) == METHOD_TYPE
19256 || TREE_CODE (type) == ARRAY_TYPE)
19257 type = TREE_TYPE (type);
19259 mode = TYPE_MODE (type);
19261 /* Check for invalid AltiVec type qualifiers. */
19262 if (type == long_unsigned_type_node || type == long_integer_type_node)
19265 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
19266 else if (rs6000_warn_altivec_long)
19267 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
19269 else if (type == long_long_unsigned_type_node
19270 || type == long_long_integer_type_node)
19271 error ("use of %<long long%> in AltiVec types is invalid");
19272 else if (type == double_type_node)
19273 error ("use of %<double%> in AltiVec types is invalid");
19274 else if (type == long_double_type_node)
19275 error ("use of %<long double%> in AltiVec types is invalid");
19276 else if (type == boolean_type_node)
19277 error ("use of boolean types in AltiVec types is invalid");
19278 else if (TREE_CODE (type) == COMPLEX_TYPE)
19279 error ("use of %<complex%> in AltiVec types is invalid");
19280 else if (DECIMAL_FLOAT_MODE_P (mode))
19281 error ("use of decimal floating point types in AltiVec types is invalid");
19283 switch (altivec_type)
19286 unsigned_p = TYPE_UNSIGNED (type);
19290 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
19293 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
19296 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
19298 case SFmode: result = V4SF_type_node; break;
19299 /* If the user says 'vector int bool', we may be handed the 'bool'
19300 attribute _before_ the 'vector' attribute, and so select the
19301 proper type in the 'b' case below. */
19302 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
19310 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
19311 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
19312 case QImode: case V16QImode: result = bool_V16QI_type_node;
19319 case V8HImode: result = pixel_V8HI_type_node;
19325 if (result && result != type && TYPE_READONLY (type))
19326 result = build_qualified_type (result, TYPE_QUAL_CONST);
19328 *no_add_attrs = true; /* No need to hang on to the attribute. */
19331 *node = reconstruct_complex_type (*node, result);
19336 /* AltiVec defines four built-in scalar types that serve as vector
19337 elements; we must teach the compiler how to mangle them. */
19339 static const char *
19340 rs6000_mangle_type (const_tree type)
19342 type = TYPE_MAIN_VARIANT (type);
19344 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
19345 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
19348 if (type == bool_char_type_node) return "U6__boolc";
19349 if (type == bool_short_type_node) return "U6__bools";
19350 if (type == pixel_type_node) return "u7__pixel";
19351 if (type == bool_int_type_node) return "U6__booli";
19353 /* Mangle IBM extended float long double as `g' (__float128) on
19354 powerpc*-linux where long-double-64 previously was the default. */
19355 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
19357 && TARGET_LONG_DOUBLE_128
19358 && !TARGET_IEEEQUAD)
19361 /* For all other types, use normal C++ mangling. */
19365 /* Handle a "longcall" or "shortcall" attribute; arguments as in
19366 struct attribute_spec.handler. */
19369 rs6000_handle_longcall_attribute (tree *node, tree name,
19370 tree args ATTRIBUTE_UNUSED,
19371 int flags ATTRIBUTE_UNUSED,
19372 bool *no_add_attrs)
19374 if (TREE_CODE (*node) != FUNCTION_TYPE
19375 && TREE_CODE (*node) != FIELD_DECL
19376 && TREE_CODE (*node) != TYPE_DECL)
19378 warning (OPT_Wattributes, "%qs attribute only applies to functions",
19379 IDENTIFIER_POINTER (name));
19380 *no_add_attrs = true;
19386 /* Set longcall attributes on all functions declared when
19387 rs6000_default_long_calls is true. */
19389 rs6000_set_default_type_attributes (tree type)
19391 if (rs6000_default_long_calls
19392 && (TREE_CODE (type) == FUNCTION_TYPE
19393 || TREE_CODE (type) == METHOD_TYPE))
19394 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
19396 TYPE_ATTRIBUTES (type));
19399 darwin_set_default_type_attributes (type);
19403 /* Return a reference suitable for calling a function with the
19404 longcall attribute. */
19407 rs6000_longcall_ref (rtx call_ref)
19409 const char *call_name;
19412 if (GET_CODE (call_ref) != SYMBOL_REF)
19415 /* System V adds '.' to the internal name, so skip them. */
19416 call_name = XSTR (call_ref, 0);
19417 if (*call_name == '.')
19419 while (*call_name == '.')
19422 node = get_identifier (call_name);
19423 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
19426 return force_reg (Pmode, call_ref);
19429 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
19430 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
19433 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
19434 struct attribute_spec.handler. */
19436 rs6000_handle_struct_attribute (tree *node, tree name,
19437 tree args ATTRIBUTE_UNUSED,
19438 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
19441 if (DECL_P (*node))
19443 if (TREE_CODE (*node) == TYPE_DECL)
19444 type = &TREE_TYPE (*node);
19449 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
19450 || TREE_CODE (*type) == UNION_TYPE)))
19452 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
19453 *no_add_attrs = true;
19456 else if ((is_attribute_p ("ms_struct", name)
19457 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
19458 || ((is_attribute_p ("gcc_struct", name)
19459 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
19461 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
19462 IDENTIFIER_POINTER (name));
19463 *no_add_attrs = true;
19470 rs6000_ms_bitfield_layout_p (const_tree record_type)
19472 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
19473 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
19474 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
19477 #ifdef USING_ELFOS_H
19479 /* A get_unnamed_section callback, used for switching to toc_section. */
19482 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19484 if (DEFAULT_ABI == ABI_AIX
19485 && TARGET_MINIMAL_TOC
19486 && !TARGET_RELOCATABLE)
19488 if (!toc_initialized)
19490 toc_initialized = 1;
19491 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19492 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
19493 fprintf (asm_out_file, "\t.tc ");
19494 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
19495 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19496 fprintf (asm_out_file, "\n");
19498 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19499 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19500 fprintf (asm_out_file, " = .+32768\n");
19503 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19505 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
19506 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19509 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19510 if (!toc_initialized)
19512 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19513 fprintf (asm_out_file, " = .+32768\n");
19514 toc_initialized = 1;
19519 /* Implement TARGET_ASM_INIT_SECTIONS. */
19522 rs6000_elf_asm_init_sections (void)
19525 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
19528 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
19529 SDATA2_SECTION_ASM_OP);
19532 /* Implement TARGET_SELECT_RTX_SECTION. */
19535 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
19536 unsigned HOST_WIDE_INT align)
19538 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19539 return toc_section;
19541 return default_elf_select_rtx_section (mode, x, align);
19544 /* For a SYMBOL_REF, set generic flags and then perform some
19545 target-specific processing.
19547 When the AIX ABI is requested on a non-AIX system, replace the
19548 function name with the real name (with a leading .) rather than the
19549 function descriptor name. This saves a lot of overriding code to
19550 read the prefixes. */
19553 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
19555 default_encode_section_info (decl, rtl, first);
19558 && TREE_CODE (decl) == FUNCTION_DECL
19560 && DEFAULT_ABI == ABI_AIX)
19562 rtx sym_ref = XEXP (rtl, 0);
19563 size_t len = strlen (XSTR (sym_ref, 0));
19564 char *str = alloca (len + 2);
19566 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
19567 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
19572 compare_section_name (const char *section, const char *template)
19576 len = strlen (template);
19577 return (strncmp (section, template, len) == 0
19578 && (section[len] == 0 || section[len] == '.'));
19582 rs6000_elf_in_small_data_p (const_tree decl)
19584 if (rs6000_sdata == SDATA_NONE)
19587 /* We want to merge strings, so we never consider them small data. */
19588 if (TREE_CODE (decl) == STRING_CST)
19591 /* Functions are never in the small data area. */
19592 if (TREE_CODE (decl) == FUNCTION_DECL)
19595 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
19597 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
19598 if (compare_section_name (section, ".sdata")
19599 || compare_section_name (section, ".sdata2")
19600 || compare_section_name (section, ".gnu.linkonce.s")
19601 || compare_section_name (section, ".sbss")
19602 || compare_section_name (section, ".sbss2")
19603 || compare_section_name (section, ".gnu.linkonce.sb")
19604 || strcmp (section, ".PPC.EMB.sdata0") == 0
19605 || strcmp (section, ".PPC.EMB.sbss0") == 0)
19610 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
19613 && (unsigned HOST_WIDE_INT) size <= g_switch_value
19614 /* If it's not public, and we're not going to reference it there,
19615 there's no need to put it in the small data section. */
19616 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
19623 #endif /* USING_ELFOS_H */
19625 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
19628 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
19630 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
19633 /* Return a REG that occurs in ADDR with coefficient 1.
19634 ADDR can be effectively incremented by incrementing REG.
19636 r0 is special and we must not select it as an address
19637 register by this routine since our caller will try to
19638 increment the returned register via an "la" instruction. */
19641 find_addr_reg (rtx addr)
19643 while (GET_CODE (addr) == PLUS)
19645 if (GET_CODE (XEXP (addr, 0)) == REG
19646 && REGNO (XEXP (addr, 0)) != 0)
19647 addr = XEXP (addr, 0);
19648 else if (GET_CODE (XEXP (addr, 1)) == REG
19649 && REGNO (XEXP (addr, 1)) != 0)
19650 addr = XEXP (addr, 1);
19651 else if (CONSTANT_P (XEXP (addr, 0)))
19652 addr = XEXP (addr, 1);
19653 else if (CONSTANT_P (XEXP (addr, 1)))
19654 addr = XEXP (addr, 0);
19656 gcc_unreachable ();
19658 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
19663 rs6000_fatal_bad_address (rtx op)
19665 fatal_insn ("bad address", op);
19670 static tree branch_island_list = 0;
19672 /* Remember to generate a branch island for far calls to the given
19676 add_compiler_branch_island (tree label_name, tree function_name,
19679 tree branch_island = build_tree_list (function_name, label_name);
19680 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
19681 TREE_CHAIN (branch_island) = branch_island_list;
19682 branch_island_list = branch_island;
19685 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19686 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19687 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19688 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19690 /* Generate far-jump branch islands for everything on the
19691 branch_island_list. Invoked immediately after the last instruction
19692 of the epilogue has been emitted; the branch-islands must be
19693 appended to, and contiguous with, the function body. Mach-O stubs
19694 are generated in machopic_output_stub(). */
19697 macho_branch_islands (void)
19700 tree branch_island;
19702 for (branch_island = branch_island_list;
19704 branch_island = TREE_CHAIN (branch_island))
19706 const char *label =
19707 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
19709 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
19710 char name_buf[512];
19711 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19712 if (name[0] == '*' || name[0] == '&')
19713 strcpy (name_buf, name+1);
19717 strcpy (name_buf+1, name);
19719 strcpy (tmp_buf, "\n");
19720 strcat (tmp_buf, label);
19721 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19722 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19723 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19724 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19727 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
19728 strcat (tmp_buf, label);
19729 strcat (tmp_buf, "_pic\n");
19730 strcat (tmp_buf, label);
19731 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
19733 strcat (tmp_buf, "\taddis r11,r11,ha16(");
19734 strcat (tmp_buf, name_buf);
19735 strcat (tmp_buf, " - ");
19736 strcat (tmp_buf, label);
19737 strcat (tmp_buf, "_pic)\n");
19739 strcat (tmp_buf, "\tmtlr r0\n");
19741 strcat (tmp_buf, "\taddi r12,r11,lo16(");
19742 strcat (tmp_buf, name_buf);
19743 strcat (tmp_buf, " - ");
19744 strcat (tmp_buf, label);
19745 strcat (tmp_buf, "_pic)\n");
19747 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
19751 strcat (tmp_buf, ":\nlis r12,hi16(");
19752 strcat (tmp_buf, name_buf);
19753 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
19754 strcat (tmp_buf, name_buf);
19755 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
19757 output_asm_insn (tmp_buf, 0);
19758 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19759 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19760 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19761 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19764 branch_island_list = 0;
19767 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19768 already there or not. */
19771 no_previous_def (tree function_name)
19773 tree branch_island;
19774 for (branch_island = branch_island_list;
19776 branch_island = TREE_CHAIN (branch_island))
19777 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19782 /* GET_PREV_LABEL gets the label name from the previous definition of
19786 get_prev_label (tree function_name)
19788 tree branch_island;
19789 for (branch_island = branch_island_list;
19791 branch_island = TREE_CHAIN (branch_island))
19792 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19793 return BRANCH_ISLAND_LABEL_NAME (branch_island);
19797 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19798 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19801 /* KEXTs still need branch islands. */
19802 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19803 || flag_mkernel || flag_apple_kext)
19805 /* INSN is either a function call or a millicode call. It may have an
19806 unconditional jump in its delay slot.
19808 CALL_DEST is the routine we are calling. */
19811 output_call (rtx insn, rtx *operands, int dest_operand_number,
19812 int cookie_operand_number)
19814 static char buf[256];
19815 if (DARWIN_GENERATE_ISLANDS
19816 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
19817 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
19820 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
19822 if (no_previous_def (funname))
19824 rtx label_rtx = gen_label_rtx ();
19825 char *label_buf, temp_buf[256];
19826 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
19827 CODE_LABEL_NUMBER (label_rtx));
19828 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
19829 labelname = get_identifier (label_buf);
19830 add_compiler_branch_island (labelname, funname, insn_line (insn));
19833 labelname = get_prev_label (funname);
19835 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19836 instruction will reach 'foo', otherwise link as 'bl L42'".
19837 "L42" should be a 'branch island', that will do a far jump to
19838 'foo'. Branch islands are generated in
19839 macho_branch_islands(). */
19840 sprintf (buf, "jbsr %%z%d,%.246s",
19841 dest_operand_number, IDENTIFIER_POINTER (labelname));
19844 sprintf (buf, "bl %%z%d", dest_operand_number);
19848 /* Generate PIC and indirect symbol stubs. */
19851 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19853 unsigned int length;
19854 char *symbol_name, *lazy_ptr_name;
19855 char *local_label_0;
19856 static int label = 0;
19858 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19859 symb = (*targetm.strip_name_encoding) (symb);
19862 length = strlen (symb);
19863 symbol_name = alloca (length + 32);
19864 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19866 lazy_ptr_name = alloca (length + 32);
19867 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19870 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19872 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19876 fprintf (file, "\t.align 5\n");
19878 fprintf (file, "%s:\n", stub);
19879 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19882 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19883 sprintf (local_label_0, "\"L%011d$spb\"", label);
19885 fprintf (file, "\tmflr r0\n");
19886 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19887 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19888 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19889 lazy_ptr_name, local_label_0);
19890 fprintf (file, "\tmtlr r0\n");
19891 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19892 (TARGET_64BIT ? "ldu" : "lwzu"),
19893 lazy_ptr_name, local_label_0);
19894 fprintf (file, "\tmtctr r12\n");
19895 fprintf (file, "\tbctr\n");
19899 fprintf (file, "\t.align 4\n");
19901 fprintf (file, "%s:\n", stub);
19902 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19904 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
19905 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
19906 (TARGET_64BIT ? "ldu" : "lwzu"),
19908 fprintf (file, "\tmtctr r12\n");
19909 fprintf (file, "\tbctr\n");
19912 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
19913 fprintf (file, "%s:\n", lazy_ptr_name);
19914 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19915 fprintf (file, "%sdyld_stub_binding_helper\n",
19916 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
19919 /* Legitimize PIC addresses. If the address is already
19920 position-independent, we return ORIG. Newly generated
19921 position-independent addresses go into a reg. This is REG if non
19922 zero, otherwise we allocate register(s) as necessary. */
19924 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19927 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
19932 if (reg == NULL && ! reload_in_progress && ! reload_completed)
19933 reg = gen_reg_rtx (Pmode);
19935 if (GET_CODE (orig) == CONST)
19939 if (GET_CODE (XEXP (orig, 0)) == PLUS
19940 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
19943 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
19945 /* Use a different reg for the intermediate value, as
19946 it will be marked UNCHANGING. */
19947 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
19948 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
19951 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
19954 if (GET_CODE (offset) == CONST_INT)
19956 if (SMALL_INT (offset))
19957 return plus_constant (base, INTVAL (offset));
19958 else if (! reload_in_progress && ! reload_completed)
19959 offset = force_reg (Pmode, offset);
19962 rtx mem = force_const_mem (Pmode, orig);
19963 return machopic_legitimize_pic_address (mem, Pmode, reg);
19966 return gen_rtx_PLUS (Pmode, base, offset);
19969 /* Fall back on generic machopic code. */
19970 return machopic_legitimize_pic_address (orig, mode, reg);
19973 /* Output a .machine directive for the Darwin assembler, and call
19974 the generic start_file routine. */
19977 rs6000_darwin_file_start (void)
19979 static const struct
19985 { "ppc64", "ppc64", MASK_64BIT },
19986 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
19987 { "power4", "ppc970", 0 },
19988 { "G5", "ppc970", 0 },
19989 { "7450", "ppc7450", 0 },
19990 { "7400", "ppc7400", MASK_ALTIVEC },
19991 { "G4", "ppc7400", 0 },
19992 { "750", "ppc750", 0 },
19993 { "740", "ppc750", 0 },
19994 { "G3", "ppc750", 0 },
19995 { "604e", "ppc604e", 0 },
19996 { "604", "ppc604", 0 },
19997 { "603e", "ppc603", 0 },
19998 { "603", "ppc603", 0 },
19999 { "601", "ppc601", 0 },
20000 { NULL, "ppc", 0 } };
20001 const char *cpu_id = "";
20004 rs6000_file_start ();
20005 darwin_file_start ();
20007 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
20008 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
20009 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
20010 && rs6000_select[i].string[0] != '\0')
20011 cpu_id = rs6000_select[i].string;
20013 /* Look through the mapping array. Pick the first name that either
20014 matches the argument, has a bit set in IF_SET that is also set
20015 in the target flags, or has a NULL name. */
20018 while (mapping[i].arg != NULL
20019 && strcmp (mapping[i].arg, cpu_id) != 0
20020 && (mapping[i].if_set & target_flags) == 0)
20023 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
20026 #endif /* TARGET_MACHO */
20030 rs6000_elf_reloc_rw_mask (void)
20034 else if (DEFAULT_ABI == ABI_AIX)
20040 /* Record an element in the table of global constructors. SYMBOL is
20041 a SYMBOL_REF of the function to be called; PRIORITY is a number
20042 between 0 and MAX_INIT_PRIORITY.
20044 This differs from default_named_section_asm_out_constructor in
20045 that we have special handling for -mrelocatable. */
20048 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
20050 const char *section = ".ctors";
20053 if (priority != DEFAULT_INIT_PRIORITY)
20055 sprintf (buf, ".ctors.%.5u",
20056 /* Invert the numbering so the linker puts us in the proper
20057 order; constructors are run from right to left, and the
20058 linker sorts in increasing order. */
20059 MAX_INIT_PRIORITY - priority);
20063 switch_to_section (get_section (section, SECTION_WRITE, NULL));
20064 assemble_align (POINTER_SIZE);
20066 if (TARGET_RELOCATABLE)
20068 fputs ("\t.long (", asm_out_file);
20069 output_addr_const (asm_out_file, symbol);
20070 fputs (")@fixup\n", asm_out_file);
20073 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
20077 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
20079 const char *section = ".dtors";
20082 if (priority != DEFAULT_INIT_PRIORITY)
20084 sprintf (buf, ".dtors.%.5u",
20085 /* Invert the numbering so the linker puts us in the proper
20086 order; constructors are run from right to left, and the
20087 linker sorts in increasing order. */
20088 MAX_INIT_PRIORITY - priority);
20092 switch_to_section (get_section (section, SECTION_WRITE, NULL));
20093 assemble_align (POINTER_SIZE);
20095 if (TARGET_RELOCATABLE)
20097 fputs ("\t.long (", asm_out_file);
20098 output_addr_const (asm_out_file, symbol);
20099 fputs (")@fixup\n", asm_out_file);
20102 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
20106 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
20110 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
20111 ASM_OUTPUT_LABEL (file, name);
20112 fputs (DOUBLE_INT_ASM_OP, file);
20113 rs6000_output_function_entry (file, name);
20114 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
20117 fputs ("\t.size\t", file);
20118 assemble_name (file, name);
20119 fputs (",24\n\t.type\t.", file);
20120 assemble_name (file, name);
20121 fputs (",@function\n", file);
20122 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
20124 fputs ("\t.globl\t.", file);
20125 assemble_name (file, name);
20130 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
20131 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
20132 rs6000_output_function_entry (file, name);
20133 fputs (":\n", file);
20137 if (TARGET_RELOCATABLE
20138 && !TARGET_SECURE_PLT
20139 && (get_pool_size () != 0 || current_function_profile)
20144 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
20146 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
20147 fprintf (file, "\t.long ");
20148 assemble_name (file, buf);
20150 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
20151 assemble_name (file, buf);
20155 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
20156 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
20158 if (DEFAULT_ABI == ABI_AIX)
20160 const char *desc_name, *orig_name;
20162 orig_name = (*targetm.strip_name_encoding) (name);
20163 desc_name = orig_name;
20164 while (*desc_name == '.')
20167 if (TREE_PUBLIC (decl))
20168 fprintf (file, "\t.globl %s\n", desc_name);
20170 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20171 fprintf (file, "%s:\n", desc_name);
20172 fprintf (file, "\t.long %s\n", orig_name);
20173 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
20174 if (DEFAULT_ABI == ABI_AIX)
20175 fputs ("\t.long 0\n", file);
20176 fprintf (file, "\t.previous\n");
20178 ASM_OUTPUT_LABEL (file, name);
20182 rs6000_elf_end_indicate_exec_stack (void)
20185 file_end_indicate_exec_stack ();
20191 rs6000_xcoff_asm_output_anchor (rtx symbol)
20195 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
20196 SYMBOL_REF_BLOCK_OFFSET (symbol));
20197 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
20201 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
20203 fputs (GLOBAL_ASM_OP, stream);
20204 RS6000_OUTPUT_BASENAME (stream, name);
20205 putc ('\n', stream);
20208 /* A get_unnamed_decl callback, used for read-only sections. PTR
20209 points to the section string variable. */
20212 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
20214 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
20215 *(const char *const *) directive,
20216 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
20219 /* Likewise for read-write sections. */
20222 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
20224 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
20225 *(const char *const *) directive,
20226 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
20229 /* A get_unnamed_section callback, used for switching to toc_section. */
20232 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
20234 if (TARGET_MINIMAL_TOC)
20236 /* toc_section is always selected at least once from
20237 rs6000_xcoff_file_start, so this is guaranteed to
20238 always be defined once and only once in each file. */
20239 if (!toc_initialized)
20241 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
20242 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
20243 toc_initialized = 1;
20245 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
20246 (TARGET_32BIT ? "" : ",3"));
20249 fputs ("\t.toc\n", asm_out_file);
20252 /* Implement TARGET_ASM_INIT_SECTIONS. */
20255 rs6000_xcoff_asm_init_sections (void)
20257 read_only_data_section
20258 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
20259 &xcoff_read_only_section_name);
20261 private_data_section
20262 = get_unnamed_section (SECTION_WRITE,
20263 rs6000_xcoff_output_readwrite_section_asm_op,
20264 &xcoff_private_data_section_name);
20266 read_only_private_data_section
20267 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
20268 &xcoff_private_data_section_name);
20271 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
20273 readonly_data_section = read_only_data_section;
20274 exception_section = data_section;
20278 rs6000_xcoff_reloc_rw_mask (void)
20284 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
20285 tree decl ATTRIBUTE_UNUSED)
20288 static const char * const suffix[3] = { "PR", "RO", "RW" };
20290 if (flags & SECTION_CODE)
20292 else if (flags & SECTION_WRITE)
20297 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
20298 (flags & SECTION_CODE) ? "." : "",
20299 name, suffix[smclass], flags & SECTION_ENTSIZE);
20303 rs6000_xcoff_select_section (tree decl, int reloc,
20304 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
20306 if (decl_readonly_section (decl, reloc))
20308 if (TREE_PUBLIC (decl))
20309 return read_only_data_section;
20311 return read_only_private_data_section;
20315 if (TREE_PUBLIC (decl))
20316 return data_section;
20318 return private_data_section;
20323 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
20327 /* Use select_section for private and uninitialized data. */
20328 if (!TREE_PUBLIC (decl)
20329 || DECL_COMMON (decl)
20330 || DECL_INITIAL (decl) == NULL_TREE
20331 || DECL_INITIAL (decl) == error_mark_node
20332 || (flag_zero_initialized_in_bss
20333 && initializer_zerop (DECL_INITIAL (decl))))
20336 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
20337 name = (*targetm.strip_name_encoding) (name);
20338 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
20341 /* Select section for constant in constant pool.
20343 On RS/6000, all constants are in the private read-only data area.
20344 However, if this is being placed in the TOC it must be output as a
20348 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
20349 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
20351 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
20352 return toc_section;
20354 return read_only_private_data_section;
20357 /* Remove any trailing [DS] or the like from the symbol name. */
20359 static const char *
20360 rs6000_xcoff_strip_name_encoding (const char *name)
20365 len = strlen (name);
20366 if (name[len - 1] == ']')
20367 return ggc_alloc_string (name, len - 4);
20372 /* Section attributes. AIX is always PIC. */
20374 static unsigned int
20375 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
20377 unsigned int align;
20378 unsigned int flags = default_section_type_flags (decl, name, reloc);
20380 /* Align to at least UNIT size. */
20381 if (flags & SECTION_CODE)
20382 align = MIN_UNITS_PER_WORD;
20384 /* Increase alignment of large objects if not already stricter. */
20385 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
20386 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
20387 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
20389 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
20392 /* Output at beginning of assembler file.
20394 Initialize the section names for the RS/6000 at this point.
20396 Specify filename, including full path, to assembler.
20398 We want to go into the TOC section so at least one .toc will be emitted.
20399 Also, in order to output proper .bs/.es pairs, we need at least one static
20400 [RW] section emitted.
20402 Finally, declare mcount when profiling to make the assembler happy. */
20405 rs6000_xcoff_file_start (void)
20407 rs6000_gen_section_name (&xcoff_bss_section_name,
20408 main_input_filename, ".bss_");
20409 rs6000_gen_section_name (&xcoff_private_data_section_name,
20410 main_input_filename, ".rw_");
20411 rs6000_gen_section_name (&xcoff_read_only_section_name,
20412 main_input_filename, ".ro_");
20414 fputs ("\t.file\t", asm_out_file);
20415 output_quoted_string (asm_out_file, main_input_filename);
20416 fputc ('\n', asm_out_file);
20417 if (write_symbols != NO_DEBUG)
20418 switch_to_section (private_data_section);
20419 switch_to_section (text_section);
20421 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
20422 rs6000_file_start ();
20425 /* Output at end of assembler file.
20426 On the RS/6000, referencing data should automatically pull in text. */
20429 rs6000_xcoff_file_end (void)
20431 switch_to_section (text_section);
20432 fputs ("_section_.text:\n", asm_out_file);
20433 switch_to_section (data_section);
20434 fputs (TARGET_32BIT
20435 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
20438 #endif /* TARGET_XCOFF */
20440 /* Compute a (partial) cost for rtx X. Return true if the complete
20441 cost has been computed, and false if subexpressions should be
20442 scanned. In either case, *TOTAL contains the cost result. */
20445 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
20447 enum machine_mode mode = GET_MODE (x);
20451 /* On the RS/6000, if it is valid in the insn, it is free. */
20453 if (((outer_code == SET
20454 || outer_code == PLUS
20455 || outer_code == MINUS)
20456 && (satisfies_constraint_I (x)
20457 || satisfies_constraint_L (x)))
20458 || (outer_code == AND
20459 && (satisfies_constraint_K (x)
20461 ? satisfies_constraint_L (x)
20462 : satisfies_constraint_J (x))
20463 || mask_operand (x, mode)
20465 && mask64_operand (x, DImode))))
20466 || ((outer_code == IOR || outer_code == XOR)
20467 && (satisfies_constraint_K (x)
20469 ? satisfies_constraint_L (x)
20470 : satisfies_constraint_J (x))))
20471 || outer_code == ASHIFT
20472 || outer_code == ASHIFTRT
20473 || outer_code == LSHIFTRT
20474 || outer_code == ROTATE
20475 || outer_code == ROTATERT
20476 || outer_code == ZERO_EXTRACT
20477 || (outer_code == MULT
20478 && satisfies_constraint_I (x))
20479 || ((outer_code == DIV || outer_code == UDIV
20480 || outer_code == MOD || outer_code == UMOD)
20481 && exact_log2 (INTVAL (x)) >= 0)
20482 || (outer_code == COMPARE
20483 && (satisfies_constraint_I (x)
20484 || satisfies_constraint_K (x)))
20485 || (outer_code == EQ
20486 && (satisfies_constraint_I (x)
20487 || satisfies_constraint_K (x)
20489 ? satisfies_constraint_L (x)
20490 : satisfies_constraint_J (x))))
20491 || (outer_code == GTU
20492 && satisfies_constraint_I (x))
20493 || (outer_code == LTU
20494 && satisfies_constraint_P (x)))
20499 else if ((outer_code == PLUS
20500 && reg_or_add_cint_operand (x, VOIDmode))
20501 || (outer_code == MINUS
20502 && reg_or_sub_cint_operand (x, VOIDmode))
20503 || ((outer_code == SET
20504 || outer_code == IOR
20505 || outer_code == XOR)
20507 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
20509 *total = COSTS_N_INSNS (1);
20515 if (mode == DImode && code == CONST_DOUBLE)
20517 if ((outer_code == IOR || outer_code == XOR)
20518 && CONST_DOUBLE_HIGH (x) == 0
20519 && (CONST_DOUBLE_LOW (x)
20520 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
20525 else if ((outer_code == AND && and64_2_operand (x, DImode))
20526 || ((outer_code == SET
20527 || outer_code == IOR
20528 || outer_code == XOR)
20529 && CONST_DOUBLE_HIGH (x) == 0))
20531 *total = COSTS_N_INSNS (1);
20541 /* When optimizing for size, MEM should be slightly more expensive
20542 than generating address, e.g., (plus (reg) (const)).
20543 L1 cache latency is about two instructions. */
20544 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
20552 if (mode == DFmode)
20554 if (GET_CODE (XEXP (x, 0)) == MULT)
20556 /* FNMA accounted in outer NEG. */
20557 if (outer_code == NEG)
20558 *total = rs6000_cost->dmul - rs6000_cost->fp;
20560 *total = rs6000_cost->dmul;
20563 *total = rs6000_cost->fp;
20565 else if (mode == SFmode)
20567 /* FNMA accounted in outer NEG. */
20568 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20571 *total = rs6000_cost->fp;
20574 *total = COSTS_N_INSNS (1);
20578 if (mode == DFmode)
20580 if (GET_CODE (XEXP (x, 0)) == MULT
20581 || GET_CODE (XEXP (x, 1)) == MULT)
20583 /* FNMA accounted in outer NEG. */
20584 if (outer_code == NEG)
20585 *total = rs6000_cost->dmul - rs6000_cost->fp;
20587 *total = rs6000_cost->dmul;
20590 *total = rs6000_cost->fp;
20592 else if (mode == SFmode)
20594 /* FNMA accounted in outer NEG. */
20595 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20598 *total = rs6000_cost->fp;
20601 *total = COSTS_N_INSNS (1);
20605 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20606 && satisfies_constraint_I (XEXP (x, 1)))
20608 if (INTVAL (XEXP (x, 1)) >= -256
20609 && INTVAL (XEXP (x, 1)) <= 255)
20610 *total = rs6000_cost->mulsi_const9;
20612 *total = rs6000_cost->mulsi_const;
20614 /* FMA accounted in outer PLUS/MINUS. */
20615 else if ((mode == DFmode || mode == SFmode)
20616 && (outer_code == PLUS || outer_code == MINUS))
20618 else if (mode == DFmode)
20619 *total = rs6000_cost->dmul;
20620 else if (mode == SFmode)
20621 *total = rs6000_cost->fp;
20622 else if (mode == DImode)
20623 *total = rs6000_cost->muldi;
20625 *total = rs6000_cost->mulsi;
20630 if (FLOAT_MODE_P (mode))
20632 *total = mode == DFmode ? rs6000_cost->ddiv
20633 : rs6000_cost->sdiv;
20640 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20641 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
20643 if (code == DIV || code == MOD)
20645 *total = COSTS_N_INSNS (2);
20648 *total = COSTS_N_INSNS (1);
20652 if (GET_MODE (XEXP (x, 1)) == DImode)
20653 *total = rs6000_cost->divdi;
20655 *total = rs6000_cost->divsi;
20657 /* Add in shift and subtract for MOD. */
20658 if (code == MOD || code == UMOD)
20659 *total += COSTS_N_INSNS (2);
20664 *total = COSTS_N_INSNS (4);
20668 *total = COSTS_N_INSNS (6);
20672 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
20684 *total = COSTS_N_INSNS (1);
20692 /* Handle mul_highpart. */
20693 if (outer_code == TRUNCATE
20694 && GET_CODE (XEXP (x, 0)) == MULT)
20696 if (mode == DImode)
20697 *total = rs6000_cost->muldi;
20699 *total = rs6000_cost->mulsi;
20702 else if (outer_code == AND)
20705 *total = COSTS_N_INSNS (1);
20710 if (GET_CODE (XEXP (x, 0)) == MEM)
20713 *total = COSTS_N_INSNS (1);
20719 if (!FLOAT_MODE_P (mode))
20721 *total = COSTS_N_INSNS (1);
20727 case UNSIGNED_FLOAT:
20730 case FLOAT_TRUNCATE:
20731 *total = rs6000_cost->fp;
20735 if (mode == DFmode)
20738 *total = rs6000_cost->fp;
20742 switch (XINT (x, 1))
20745 *total = rs6000_cost->fp;
20757 *total = COSTS_N_INSNS (1);
20760 else if (FLOAT_MODE_P (mode)
20761 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
20763 *total = rs6000_cost->fp;
20771 /* Carry bit requires mode == Pmode.
20772 NEG or PLUS already counted so only add one. */
20774 && (outer_code == NEG || outer_code == PLUS))
20776 *total = COSTS_N_INSNS (1);
20779 if (outer_code == SET)
20781 if (XEXP (x, 1) == const0_rtx)
20783 *total = COSTS_N_INSNS (2);
20786 else if (mode == Pmode)
20788 *total = COSTS_N_INSNS (3);
20797 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
20799 *total = COSTS_N_INSNS (2);
20803 if (outer_code == COMPARE)
20817 /* A C expression returning the cost of moving data from a register of class
20818 CLASS1 to one of CLASS2. */
20821 rs6000_register_move_cost (enum machine_mode mode,
20822 enum reg_class from, enum reg_class to)
20824 /* Moves from/to GENERAL_REGS. */
20825 if (reg_classes_intersect_p (to, GENERAL_REGS)
20826 || reg_classes_intersect_p (from, GENERAL_REGS))
20828 if (! reg_classes_intersect_p (to, GENERAL_REGS))
20831 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
20832 return (rs6000_memory_move_cost (mode, from, 0)
20833 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
20835 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20837 else if (from == CR_REGS)
20841 /* A move will cost one instruction per GPR moved. */
20842 return 2 * hard_regno_nregs[0][mode];
20845 /* Moving between two similar registers is just one instruction. */
20846 else if (reg_classes_intersect_p (to, from))
20847 return (mode == TFmode || mode == TDmode) ? 4 : 2;
20849 /* Everything else has to go through GENERAL_REGS. */
20851 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
20852 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
20855 /* A C expressions returning the cost of moving data of MODE from a register to
20859 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20860 int in ATTRIBUTE_UNUSED)
20862 if (reg_classes_intersect_p (class, GENERAL_REGS))
20863 return 4 * hard_regno_nregs[0][mode];
20864 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20865 return 4 * hard_regno_nregs[32][mode];
20866 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20867 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20869 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20872 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20873 Assumes no trapping math and finite arguments. */
20876 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
20878 rtx x0, e0, e1, y1, u0, v0, one;
20880 x0 = gen_reg_rtx (SFmode);
20881 e0 = gen_reg_rtx (SFmode);
20882 e1 = gen_reg_rtx (SFmode);
20883 y1 = gen_reg_rtx (SFmode);
20884 u0 = gen_reg_rtx (SFmode);
20885 v0 = gen_reg_rtx (SFmode);
20886 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
20888 /* x0 = 1./d estimate */
20889 emit_insn (gen_rtx_SET (VOIDmode, x0,
20890 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
20892 /* e0 = 1. - d * x0 */
20893 emit_insn (gen_rtx_SET (VOIDmode, e0,
20894 gen_rtx_MINUS (SFmode, one,
20895 gen_rtx_MULT (SFmode, d, x0))));
20896 /* e1 = e0 + e0 * e0 */
20897 emit_insn (gen_rtx_SET (VOIDmode, e1,
20898 gen_rtx_PLUS (SFmode,
20899 gen_rtx_MULT (SFmode, e0, e0), e0)));
20900 /* y1 = x0 + e1 * x0 */
20901 emit_insn (gen_rtx_SET (VOIDmode, y1,
20902 gen_rtx_PLUS (SFmode,
20903 gen_rtx_MULT (SFmode, e1, x0), x0)));
20905 emit_insn (gen_rtx_SET (VOIDmode, u0,
20906 gen_rtx_MULT (SFmode, n, y1)));
20907 /* v0 = n - d * u0 */
20908 emit_insn (gen_rtx_SET (VOIDmode, v0,
20909 gen_rtx_MINUS (SFmode, n,
20910 gen_rtx_MULT (SFmode, d, u0))));
20911 /* res = u0 + v0 * y1 */
20912 emit_insn (gen_rtx_SET (VOIDmode, res,
20913 gen_rtx_PLUS (SFmode,
20914 gen_rtx_MULT (SFmode, v0, y1), u0)));
20917 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20918 Assumes no trapping math and finite arguments. */
20921 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
20923 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
20925 x0 = gen_reg_rtx (DFmode);
20926 e0 = gen_reg_rtx (DFmode);
20927 e1 = gen_reg_rtx (DFmode);
20928 e2 = gen_reg_rtx (DFmode);
20929 y1 = gen_reg_rtx (DFmode);
20930 y2 = gen_reg_rtx (DFmode);
20931 y3 = gen_reg_rtx (DFmode);
20932 u0 = gen_reg_rtx (DFmode);
20933 v0 = gen_reg_rtx (DFmode);
20934 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
20936 /* x0 = 1./d estimate */
20937 emit_insn (gen_rtx_SET (VOIDmode, x0,
20938 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
20940 /* e0 = 1. - d * x0 */
20941 emit_insn (gen_rtx_SET (VOIDmode, e0,
20942 gen_rtx_MINUS (DFmode, one,
20943 gen_rtx_MULT (SFmode, d, x0))));
20944 /* y1 = x0 + e0 * x0 */
20945 emit_insn (gen_rtx_SET (VOIDmode, y1,
20946 gen_rtx_PLUS (DFmode,
20947 gen_rtx_MULT (DFmode, e0, x0), x0)));
20949 emit_insn (gen_rtx_SET (VOIDmode, e1,
20950 gen_rtx_MULT (DFmode, e0, e0)));
20951 /* y2 = y1 + e1 * y1 */
20952 emit_insn (gen_rtx_SET (VOIDmode, y2,
20953 gen_rtx_PLUS (DFmode,
20954 gen_rtx_MULT (DFmode, e1, y1), y1)));
20956 emit_insn (gen_rtx_SET (VOIDmode, e2,
20957 gen_rtx_MULT (DFmode, e1, e1)));
20958 /* y3 = y2 + e2 * y2 */
20959 emit_insn (gen_rtx_SET (VOIDmode, y3,
20960 gen_rtx_PLUS (DFmode,
20961 gen_rtx_MULT (DFmode, e2, y2), y2)));
20963 emit_insn (gen_rtx_SET (VOIDmode, u0,
20964 gen_rtx_MULT (DFmode, n, y3)));
20965 /* v0 = n - d * u0 */
20966 emit_insn (gen_rtx_SET (VOIDmode, v0,
20967 gen_rtx_MINUS (DFmode, n,
20968 gen_rtx_MULT (DFmode, d, u0))));
20969 /* res = u0 + v0 * y3 */
20970 emit_insn (gen_rtx_SET (VOIDmode, res,
20971 gen_rtx_PLUS (DFmode,
20972 gen_rtx_MULT (DFmode, v0, y3), u0)));
20976 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
20977 target, and SRC is the argument operand. */
20980 rs6000_emit_popcount (rtx dst, rtx src)
20982 enum machine_mode mode = GET_MODE (dst);
20985 tmp1 = gen_reg_rtx (mode);
20987 if (mode == SImode)
20989 emit_insn (gen_popcntbsi2 (tmp1, src));
20990 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
20992 tmp2 = force_reg (SImode, tmp2);
20993 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
20997 emit_insn (gen_popcntbdi2 (tmp1, src));
20998 tmp2 = expand_mult (DImode, tmp1,
20999 GEN_INT ((HOST_WIDE_INT)
21000 0x01010101 << 32 | 0x01010101),
21002 tmp2 = force_reg (DImode, tmp2);
21003 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
21008 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
21009 target, and SRC is the argument operand. */
21012 rs6000_emit_parity (rtx dst, rtx src)
21014 enum machine_mode mode = GET_MODE (dst);
21017 tmp = gen_reg_rtx (mode);
21018 if (mode == SImode)
21020 /* Is mult+shift >= shift+xor+shift+xor? */
21021 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
21023 rtx tmp1, tmp2, tmp3, tmp4;
21025 tmp1 = gen_reg_rtx (SImode);
21026 emit_insn (gen_popcntbsi2 (tmp1, src));
21028 tmp2 = gen_reg_rtx (SImode);
21029 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
21030 tmp3 = gen_reg_rtx (SImode);
21031 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
21033 tmp4 = gen_reg_rtx (SImode);
21034 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
21035 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
21038 rs6000_emit_popcount (tmp, src);
21039 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
21043 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
21044 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
21046 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
21048 tmp1 = gen_reg_rtx (DImode);
21049 emit_insn (gen_popcntbdi2 (tmp1, src));
21051 tmp2 = gen_reg_rtx (DImode);
21052 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
21053 tmp3 = gen_reg_rtx (DImode);
21054 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
21056 tmp4 = gen_reg_rtx (DImode);
21057 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
21058 tmp5 = gen_reg_rtx (DImode);
21059 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
21061 tmp6 = gen_reg_rtx (DImode);
21062 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
21063 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
21066 rs6000_emit_popcount (tmp, src);
21067 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
21071 /* Return an RTX representing where to find the function value of a
21072 function returning MODE. */
21074 rs6000_complex_function_value (enum machine_mode mode)
21076 unsigned int regno;
21078 enum machine_mode inner = GET_MODE_INNER (mode);
21079 unsigned int inner_bytes = GET_MODE_SIZE (inner);
21081 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
21082 regno = FP_ARG_RETURN;
21085 regno = GP_ARG_RETURN;
21087 /* 32-bit is OK since it'll go in r3/r4. */
21088 if (TARGET_32BIT && inner_bytes >= 4)
21089 return gen_rtx_REG (mode, regno);
21092 if (inner_bytes >= 8)
21093 return gen_rtx_REG (mode, regno);
21095 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
21097 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
21098 GEN_INT (inner_bytes));
21099 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
21102 /* Define how to find the value returned by a function.
21103 VALTYPE is the data type of the value (as a tree).
21104 If the precise function being called is known, FUNC is its FUNCTION_DECL;
21105 otherwise, FUNC is 0.
21107 On the SPE, both FPs and vectors are returned in r3.
21109 On RS/6000 an integer value is in r3 and a floating-point value is in
21110 fp1, unless -msoft-float. */
21113 rs6000_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
21115 enum machine_mode mode;
21116 unsigned int regno;
21118 /* Special handling for structs in darwin64. */
21119 if (rs6000_darwin64_abi
21120 && TYPE_MODE (valtype) == BLKmode
21121 && TREE_CODE (valtype) == RECORD_TYPE
21122 && int_size_in_bytes (valtype) > 0)
21124 CUMULATIVE_ARGS valcum;
21128 valcum.fregno = FP_ARG_MIN_REG;
21129 valcum.vregno = ALTIVEC_ARG_MIN_REG;
21130 /* Do a trial code generation as if this were going to be passed as
21131 an argument; if any part goes in memory, we return NULL. */
21132 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
21135 /* Otherwise fall through to standard ABI rules. */
21138 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
21140 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
21141 return gen_rtx_PARALLEL (DImode,
21143 gen_rtx_EXPR_LIST (VOIDmode,
21144 gen_rtx_REG (SImode, GP_ARG_RETURN),
21146 gen_rtx_EXPR_LIST (VOIDmode,
21147 gen_rtx_REG (SImode,
21148 GP_ARG_RETURN + 1),
21151 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
21153 return gen_rtx_PARALLEL (DCmode,
21155 gen_rtx_EXPR_LIST (VOIDmode,
21156 gen_rtx_REG (SImode, GP_ARG_RETURN),
21158 gen_rtx_EXPR_LIST (VOIDmode,
21159 gen_rtx_REG (SImode,
21160 GP_ARG_RETURN + 1),
21162 gen_rtx_EXPR_LIST (VOIDmode,
21163 gen_rtx_REG (SImode,
21164 GP_ARG_RETURN + 2),
21166 gen_rtx_EXPR_LIST (VOIDmode,
21167 gen_rtx_REG (SImode,
21168 GP_ARG_RETURN + 3),
21172 mode = TYPE_MODE (valtype);
21173 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
21174 || POINTER_TYPE_P (valtype))
21175 mode = TARGET_32BIT ? SImode : DImode;
21177 if (DECIMAL_FLOAT_MODE_P (mode))
21179 if (TARGET_HARD_FLOAT && TARGET_FPRS)
21184 gcc_unreachable ();
21186 regno = GP_ARG_RETURN;
21189 regno = FP_ARG_RETURN;
21192 /* Use f2:f3 specified by the ABI. */
21193 regno = FP_ARG_RETURN + 1;
21198 regno = GP_ARG_RETURN;
21200 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
21201 regno = FP_ARG_RETURN;
21202 else if (TREE_CODE (valtype) == COMPLEX_TYPE
21203 && targetm.calls.split_complex_arg)
21204 return rs6000_complex_function_value (mode);
21205 else if (TREE_CODE (valtype) == VECTOR_TYPE
21206 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
21207 && ALTIVEC_VECTOR_MODE (mode))
21208 regno = ALTIVEC_ARG_RETURN;
21209 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
21210 && (mode == DFmode || mode == DCmode
21211 || mode == TFmode || mode == TCmode))
21212 return spe_build_register_parallel (mode, GP_ARG_RETURN);
21214 regno = GP_ARG_RETURN;
21216 return gen_rtx_REG (mode, regno);
21219 /* Define how to find the value returned by a library function
21220 assuming the value has mode MODE. */
21222 rs6000_libcall_value (enum machine_mode mode)
21224 unsigned int regno;
21226 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
21228 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
21229 return gen_rtx_PARALLEL (DImode,
21231 gen_rtx_EXPR_LIST (VOIDmode,
21232 gen_rtx_REG (SImode, GP_ARG_RETURN),
21234 gen_rtx_EXPR_LIST (VOIDmode,
21235 gen_rtx_REG (SImode,
21236 GP_ARG_RETURN + 1),
21240 if (DECIMAL_FLOAT_MODE_P (mode))
21242 if (TARGET_HARD_FLOAT && TARGET_FPRS)
21247 gcc_unreachable ();
21249 regno = GP_ARG_RETURN;
21252 regno = FP_ARG_RETURN;
21255 /* Use f2:f3 specified by the ABI. */
21256 regno = FP_ARG_RETURN + 1;
21261 regno = GP_ARG_RETURN;
21263 else if (SCALAR_FLOAT_MODE_P (mode)
21264 && TARGET_HARD_FLOAT && TARGET_FPRS)
21265 regno = FP_ARG_RETURN;
21266 else if (ALTIVEC_VECTOR_MODE (mode)
21267 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
21268 regno = ALTIVEC_ARG_RETURN;
21269 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
21270 return rs6000_complex_function_value (mode);
21271 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
21272 && (mode == DFmode || mode == DCmode
21273 || mode == TFmode || mode == TCmode))
21274 return spe_build_register_parallel (mode, GP_ARG_RETURN);
21276 regno = GP_ARG_RETURN;
21278 return gen_rtx_REG (mode, regno);
21281 /* Define the offset between two registers, FROM to be eliminated and its
21282 replacement TO, at the start of a routine. */
21284 rs6000_initial_elimination_offset (int from, int to)
21286 rs6000_stack_t *info = rs6000_stack_info ();
21287 HOST_WIDE_INT offset;
21289 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
21290 offset = info->push_p ? 0 : -info->total_size;
21291 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
21293 offset = info->push_p ? 0 : -info->total_size;
21294 if (FRAME_GROWS_DOWNWARD)
21295 offset += info->fixed_size + info->vars_size + info->parm_size;
21297 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
21298 offset = FRAME_GROWS_DOWNWARD
21299 ? info->fixed_size + info->vars_size + info->parm_size
21301 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
21302 offset = info->total_size;
21303 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
21304 offset = info->push_p ? info->total_size : 0;
21305 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
21308 gcc_unreachable ();
21313 /* Return true if TYPE is a SPE or AltiVec opaque type. */
21316 rs6000_is_opaque_type (const_tree type)
21318 return (type == opaque_V2SI_type_node
21319 || type == opaque_V2SF_type_node
21320 || type == opaque_p_V2SI_type_node
21321 || type == opaque_V4SI_type_node);
21325 rs6000_dwarf_register_span (rtx reg)
21330 && (SPE_VECTOR_MODE (GET_MODE (reg))
21331 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
21336 regno = REGNO (reg);
21338 /* The duality of the SPE register size wreaks all kinds of havoc.
21339 This is a way of distinguishing r0 in 32-bits from r0 in
21342 gen_rtx_PARALLEL (VOIDmode,
21345 gen_rtx_REG (SImode, regno + 1200),
21346 gen_rtx_REG (SImode, regno))
21348 gen_rtx_REG (SImode, regno),
21349 gen_rtx_REG (SImode, regno + 1200)));
21352 /* Fill in sizes for SPE register high parts in table used by unwinder. */
21355 rs6000_init_dwarf_reg_sizes_extra (tree address)
21360 enum machine_mode mode = TYPE_MODE (char_type_node);
21361 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
21362 rtx mem = gen_rtx_MEM (BLKmode, addr);
21363 rtx value = gen_int_mode (4, mode);
21365 for (i = 1201; i < 1232; i++)
21367 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
21368 HOST_WIDE_INT offset
21369 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
21371 emit_move_insn (adjust_address (mem, mode, offset), value);
21376 /* Map internal gcc register numbers to DWARF2 register numbers. */
21379 rs6000_dbx_register_number (unsigned int regno)
21381 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
21383 if (regno == MQ_REGNO)
21385 if (regno == LR_REGNO)
21387 if (regno == CTR_REGNO)
21389 if (CR_REGNO_P (regno))
21390 return regno - CR0_REGNO + 86;
21391 if (regno == XER_REGNO)
21393 if (ALTIVEC_REGNO_P (regno))
21394 return regno - FIRST_ALTIVEC_REGNO + 1124;
21395 if (regno == VRSAVE_REGNO)
21397 if (regno == VSCR_REGNO)
21399 if (regno == SPE_ACC_REGNO)
21401 if (regno == SPEFSCR_REGNO)
21403 /* SPE high reg number. We get these values of regno from
21404 rs6000_dwarf_register_span. */
21405 gcc_assert (regno >= 1200 && regno < 1232);
21409 /* target hook eh_return_filter_mode */
21410 static enum machine_mode
21411 rs6000_eh_return_filter_mode (void)
21413 return TARGET_32BIT ? SImode : word_mode;
21416 /* Target hook for scalar_mode_supported_p. */
21418 rs6000_scalar_mode_supported_p (enum machine_mode mode)
21420 if (DECIMAL_FLOAT_MODE_P (mode))
21423 return default_scalar_mode_supported_p (mode);
21426 /* Target hook for vector_mode_supported_p. */
21428 rs6000_vector_mode_supported_p (enum machine_mode mode)
21431 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
21434 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
21437 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
21444 /* Target hook for invalid_arg_for_unprototyped_fn. */
21445 static const char *
21446 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
21448 return (!rs6000_darwin64_abi
21450 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
21451 && (funcdecl == NULL_TREE
21452 || (TREE_CODE (funcdecl) == FUNCTION_DECL
21453 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
21454 ? N_("AltiVec argument passed to unprototyped function")
21458 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
21459 setup by using __stack_chk_fail_local hidden function instead of
21460 calling __stack_chk_fail directly. Otherwise it is better to call
21461 __stack_chk_fail directly. */
21464 rs6000_stack_protect_fail (void)
21466 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
21467 ? default_hidden_stack_protect_fail ()
21468 : default_external_stack_protect_fail ();
21471 #include "gt-rs6000.h"