1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "tm-constrs.h"
60 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
63 #include "gstab.h" /* for N_SLINE */
66 #ifndef TARGET_NO_PROTOTYPE
67 #define TARGET_NO_PROTOTYPE 0
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int push_p; /* true if we need to allocate stack space */
82 int calls_p; /* true if the function makes any calls */
83 int world_save_p; /* true if we're saving *everything*:
84 r13-r31, cr, f14-f31, vrsave, v20-v31 */
85 enum rs6000_abi abi; /* which ABI to use */
86 int gp_save_offset; /* offset to save GP regs from initial SP */
87 int fp_save_offset; /* offset to save FP regs from initial SP */
88 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
89 int lr_save_offset; /* offset to save LR from initial SP */
90 int cr_save_offset; /* offset to save CR from initial SP */
91 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
92 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 HOST_WIDE_INT vars_size; /* variable save area size */
97 int parm_size; /* outgoing parameter size */
98 int save_size; /* save area size */
99 int fixed_size; /* fixed size of stack frame */
100 int gp_size; /* size of saved GP registers */
101 int fp_size; /* size of saved FP registers */
102 int altivec_size; /* size of saved AltiVec registers */
103 int cr_size; /* size to hold CR if not in save_size */
104 int vrsave_size; /* size to hold VRSAVE if not in save_size */
105 int altivec_padding_size; /* size of altivec alignment padding if
107 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
108 int spe_padding_size;
109 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
110 int spe_64bit_regs_used;
113 /* A C structure for machine-specific, per-function data.
114 This is added to the cfun structure. */
115 typedef struct machine_function GTY(())
117 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
118 int ra_needs_full_frame;
119 /* Some local-dynamic symbol. */
120 const char *some_ld_name;
121 /* Whether the instruction chain has been scanned already. */
122 int insn_chain_scanned_p;
123 /* Flags if __builtin_return_address (0) was used. */
125 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
126 varargs save area. */
127 HOST_WIDE_INT varargs_save_offset;
130 /* Target cpu type */
132 enum processor_type rs6000_cpu;
133 struct rs6000_cpu_select rs6000_select[3] =
135 /* switch name, tune arch */
136 { (const char *)0, "--with-cpu=", 1, 1 },
137 { (const char *)0, "-mcpu=", 1, 1 },
138 { (const char *)0, "-mtune=", 1, 0 },
141 static GTY(()) bool rs6000_cell_dont_microcode;
143 /* Always emit branch hint bits. */
144 static GTY(()) bool rs6000_always_hint;
146 /* Schedule instructions for group formation. */
147 static GTY(()) bool rs6000_sched_groups;
149 /* Align branch targets. */
150 static GTY(()) bool rs6000_align_branch_targets;
152 /* Support for -msched-costly-dep option. */
153 const char *rs6000_sched_costly_dep_str;
154 enum rs6000_dependence_cost rs6000_sched_costly_dep;
156 /* Support for -minsert-sched-nops option. */
157 const char *rs6000_sched_insert_nops_str;
158 enum rs6000_nop_insertion rs6000_sched_insert_nops;
160 /* Support targetm.vectorize.builtin_mask_for_load. */
161 static GTY(()) tree altivec_builtin_mask_for_load;
163 /* Size of long double. */
164 int rs6000_long_double_type_size;
166 /* IEEE quad extended precision long double. */
169 /* Whether -mabi=altivec has appeared. */
170 int rs6000_altivec_abi;
172 /* Nonzero if we want SPE ABI extensions. */
175 /* Nonzero if floating point operations are done in the GPRs. */
176 int rs6000_float_gprs = 0;
178 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
179 int rs6000_darwin64_abi;
181 /* Set to nonzero once AIX common-mode calls have been defined. */
182 static GTY(()) int common_mode_defined;
184 /* Save information from a "cmpxx" operation until the branch or scc is
186 rtx rs6000_compare_op0, rs6000_compare_op1;
187 int rs6000_compare_fp_p;
189 /* Label number of label created for -mrelocatable, to call to so we can
190 get the address of the GOT section */
191 int rs6000_pic_labelno;
194 /* Which abi to adhere to */
195 const char *rs6000_abi_name;
197 /* Semantics of the small data area */
198 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
200 /* Which small data model to use */
201 const char *rs6000_sdata_name = (char *)0;
203 /* Counter for labels which are to be placed in .fixup. */
204 int fixuplabelno = 0;
207 /* Bit size of immediate TLS offsets and string from which it is decoded. */
208 int rs6000_tls_size = 32;
209 const char *rs6000_tls_size_string;
211 /* ABI enumeration available for subtarget to use. */
212 enum rs6000_abi rs6000_current_abi;
214 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
218 const char *rs6000_debug_name;
219 int rs6000_debug_stack; /* debug stack applications */
220 int rs6000_debug_arg; /* debug argument handling */
222 /* Value is TRUE if register/mode pair is acceptable. */
223 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
225 /* Built in types. */
227 tree rs6000_builtin_types[RS6000_BTI_MAX];
228 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
230 const char *rs6000_traceback_name;
232 traceback_default = 0,
238 /* Flag to say the TOC is initialized */
240 char toc_label_name[10];
242 /* Cached value of rs6000_variable_issue. This is cached in
243 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
244 static short cached_can_issue_more;
246 static GTY(()) section *read_only_data_section;
247 static GTY(()) section *private_data_section;
248 static GTY(()) section *read_only_private_data_section;
249 static GTY(()) section *sdata2_section;
250 static GTY(()) section *toc_section;
252 /* Control alignment for fields within structures. */
253 /* String from -malign-XXXXX. */
254 int rs6000_alignment_flags;
256 /* True for any options that were explicitly set. */
258 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
259 bool alignment; /* True if -malign- was used. */
260 bool abi; /* True if -mabi=spe/nospe was used. */
261 bool spe; /* True if -mspe= was used. */
262 bool float_gprs; /* True if -mfloat-gprs= was used. */
263 bool isel; /* True if -misel was used. */
264 bool long_double; /* True if -mlong-double- was used. */
265 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
266 } rs6000_explicit_options;
268 struct builtin_description
270 /* mask is not const because we're going to alter it below. This
271 nonsense will go away when we rewrite the -march infrastructure
272 to give us more target flag bits. */
274 const enum insn_code icode;
275 const char *const name;
276 const enum rs6000_builtins code;
279 /* Target cpu costs. */
281 struct processor_costs {
282 const int mulsi; /* cost of SImode multiplication. */
283 const int mulsi_const; /* cost of SImode multiplication by constant. */
284 const int mulsi_const9; /* cost of SImode mult by short constant. */
285 const int muldi; /* cost of DImode multiplication. */
286 const int divsi; /* cost of SImode division. */
287 const int divdi; /* cost of DImode division. */
288 const int fp; /* cost of simple SFmode and DFmode insns. */
289 const int dmul; /* cost of DFmode multiplication (and fmadd). */
290 const int sdiv; /* cost of SFmode division (fdivs). */
291 const int ddiv; /* cost of DFmode division (fdiv). */
292 const int cache_line_size; /* cache line size in bytes. */
293 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
294 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
295 const int simultaneous_prefetches; /* number of parallel prefetch
299 const struct processor_costs *rs6000_cost;
301 /* Processor costs (relative to an add) */
303 /* Instruction size costs on 32bit processors. */
305 struct processor_costs size32_cost = {
306 COSTS_N_INSNS (1), /* mulsi */
307 COSTS_N_INSNS (1), /* mulsi_const */
308 COSTS_N_INSNS (1), /* mulsi_const9 */
309 COSTS_N_INSNS (1), /* muldi */
310 COSTS_N_INSNS (1), /* divsi */
311 COSTS_N_INSNS (1), /* divdi */
312 COSTS_N_INSNS (1), /* fp */
313 COSTS_N_INSNS (1), /* dmul */
314 COSTS_N_INSNS (1), /* sdiv */
315 COSTS_N_INSNS (1), /* ddiv */
322 /* Instruction size costs on 64bit processors. */
324 struct processor_costs size64_cost = {
325 COSTS_N_INSNS (1), /* mulsi */
326 COSTS_N_INSNS (1), /* mulsi_const */
327 COSTS_N_INSNS (1), /* mulsi_const9 */
328 COSTS_N_INSNS (1), /* muldi */
329 COSTS_N_INSNS (1), /* divsi */
330 COSTS_N_INSNS (1), /* divdi */
331 COSTS_N_INSNS (1), /* fp */
332 COSTS_N_INSNS (1), /* dmul */
333 COSTS_N_INSNS (1), /* sdiv */
334 COSTS_N_INSNS (1), /* ddiv */
341 /* Instruction costs on RIOS1 processors. */
343 struct processor_costs rios1_cost = {
344 COSTS_N_INSNS (5), /* mulsi */
345 COSTS_N_INSNS (4), /* mulsi_const */
346 COSTS_N_INSNS (3), /* mulsi_const9 */
347 COSTS_N_INSNS (5), /* muldi */
348 COSTS_N_INSNS (19), /* divsi */
349 COSTS_N_INSNS (19), /* divdi */
350 COSTS_N_INSNS (2), /* fp */
351 COSTS_N_INSNS (2), /* dmul */
352 COSTS_N_INSNS (19), /* sdiv */
353 COSTS_N_INSNS (19), /* ddiv */
360 /* Instruction costs on RIOS2 processors. */
362 struct processor_costs rios2_cost = {
363 COSTS_N_INSNS (2), /* mulsi */
364 COSTS_N_INSNS (2), /* mulsi_const */
365 COSTS_N_INSNS (2), /* mulsi_const9 */
366 COSTS_N_INSNS (2), /* muldi */
367 COSTS_N_INSNS (13), /* divsi */
368 COSTS_N_INSNS (13), /* divdi */
369 COSTS_N_INSNS (2), /* fp */
370 COSTS_N_INSNS (2), /* dmul */
371 COSTS_N_INSNS (17), /* sdiv */
372 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on RS64A processors. */
381 struct processor_costs rs64a_cost = {
382 COSTS_N_INSNS (20), /* mulsi */
383 COSTS_N_INSNS (12), /* mulsi_const */
384 COSTS_N_INSNS (8), /* mulsi_const9 */
385 COSTS_N_INSNS (34), /* muldi */
386 COSTS_N_INSNS (65), /* divsi */
387 COSTS_N_INSNS (67), /* divdi */
388 COSTS_N_INSNS (4), /* fp */
389 COSTS_N_INSNS (4), /* dmul */
390 COSTS_N_INSNS (31), /* sdiv */
391 COSTS_N_INSNS (31), /* ddiv */
398 /* Instruction costs on MPCCORE processors. */
400 struct processor_costs mpccore_cost = {
401 COSTS_N_INSNS (2), /* mulsi */
402 COSTS_N_INSNS (2), /* mulsi_const */
403 COSTS_N_INSNS (2), /* mulsi_const9 */
404 COSTS_N_INSNS (2), /* muldi */
405 COSTS_N_INSNS (6), /* divsi */
406 COSTS_N_INSNS (6), /* divdi */
407 COSTS_N_INSNS (4), /* fp */
408 COSTS_N_INSNS (5), /* dmul */
409 COSTS_N_INSNS (10), /* sdiv */
410 COSTS_N_INSNS (17), /* ddiv */
417 /* Instruction costs on PPC403 processors. */
419 struct processor_costs ppc403_cost = {
420 COSTS_N_INSNS (4), /* mulsi */
421 COSTS_N_INSNS (4), /* mulsi_const */
422 COSTS_N_INSNS (4), /* mulsi_const9 */
423 COSTS_N_INSNS (4), /* muldi */
424 COSTS_N_INSNS (33), /* divsi */
425 COSTS_N_INSNS (33), /* divdi */
426 COSTS_N_INSNS (11), /* fp */
427 COSTS_N_INSNS (11), /* dmul */
428 COSTS_N_INSNS (11), /* sdiv */
429 COSTS_N_INSNS (11), /* ddiv */
436 /* Instruction costs on PPC405 processors. */
438 struct processor_costs ppc405_cost = {
439 COSTS_N_INSNS (5), /* mulsi */
440 COSTS_N_INSNS (4), /* mulsi_const */
441 COSTS_N_INSNS (3), /* mulsi_const9 */
442 COSTS_N_INSNS (5), /* muldi */
443 COSTS_N_INSNS (35), /* divsi */
444 COSTS_N_INSNS (35), /* divdi */
445 COSTS_N_INSNS (11), /* fp */
446 COSTS_N_INSNS (11), /* dmul */
447 COSTS_N_INSNS (11), /* sdiv */
448 COSTS_N_INSNS (11), /* ddiv */
455 /* Instruction costs on PPC440 processors. */
457 struct processor_costs ppc440_cost = {
458 COSTS_N_INSNS (3), /* mulsi */
459 COSTS_N_INSNS (2), /* mulsi_const */
460 COSTS_N_INSNS (2), /* mulsi_const9 */
461 COSTS_N_INSNS (3), /* muldi */
462 COSTS_N_INSNS (34), /* divsi */
463 COSTS_N_INSNS (34), /* divdi */
464 COSTS_N_INSNS (5), /* fp */
465 COSTS_N_INSNS (5), /* dmul */
466 COSTS_N_INSNS (19), /* sdiv */
467 COSTS_N_INSNS (33), /* ddiv */
474 /* Instruction costs on PPC601 processors. */
476 struct processor_costs ppc601_cost = {
477 COSTS_N_INSNS (5), /* mulsi */
478 COSTS_N_INSNS (5), /* mulsi_const */
479 COSTS_N_INSNS (5), /* mulsi_const9 */
480 COSTS_N_INSNS (5), /* muldi */
481 COSTS_N_INSNS (36), /* divsi */
482 COSTS_N_INSNS (36), /* divdi */
483 COSTS_N_INSNS (4), /* fp */
484 COSTS_N_INSNS (5), /* dmul */
485 COSTS_N_INSNS (17), /* sdiv */
486 COSTS_N_INSNS (31), /* ddiv */
493 /* Instruction costs on PPC603 processors. */
495 struct processor_costs ppc603_cost = {
496 COSTS_N_INSNS (5), /* mulsi */
497 COSTS_N_INSNS (3), /* mulsi_const */
498 COSTS_N_INSNS (2), /* mulsi_const9 */
499 COSTS_N_INSNS (5), /* muldi */
500 COSTS_N_INSNS (37), /* divsi */
501 COSTS_N_INSNS (37), /* divdi */
502 COSTS_N_INSNS (3), /* fp */
503 COSTS_N_INSNS (4), /* dmul */
504 COSTS_N_INSNS (18), /* sdiv */
505 COSTS_N_INSNS (33), /* ddiv */
512 /* Instruction costs on PPC604 processors. */
514 struct processor_costs ppc604_cost = {
515 COSTS_N_INSNS (4), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (4), /* mulsi_const9 */
518 COSTS_N_INSNS (4), /* muldi */
519 COSTS_N_INSNS (20), /* divsi */
520 COSTS_N_INSNS (20), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
531 /* Instruction costs on PPC604e processors. */
533 struct processor_costs ppc604e_cost = {
534 COSTS_N_INSNS (2), /* mulsi */
535 COSTS_N_INSNS (2), /* mulsi_const */
536 COSTS_N_INSNS (2), /* mulsi_const9 */
537 COSTS_N_INSNS (2), /* muldi */
538 COSTS_N_INSNS (20), /* divsi */
539 COSTS_N_INSNS (20), /* divdi */
540 COSTS_N_INSNS (3), /* fp */
541 COSTS_N_INSNS (3), /* dmul */
542 COSTS_N_INSNS (18), /* sdiv */
543 COSTS_N_INSNS (32), /* ddiv */
550 /* Instruction costs on PPC620 processors. */
552 struct processor_costs ppc620_cost = {
553 COSTS_N_INSNS (5), /* mulsi */
554 COSTS_N_INSNS (4), /* mulsi_const */
555 COSTS_N_INSNS (3), /* mulsi_const9 */
556 COSTS_N_INSNS (7), /* muldi */
557 COSTS_N_INSNS (21), /* divsi */
558 COSTS_N_INSNS (37), /* divdi */
559 COSTS_N_INSNS (3), /* fp */
560 COSTS_N_INSNS (3), /* dmul */
561 COSTS_N_INSNS (18), /* sdiv */
562 COSTS_N_INSNS (32), /* ddiv */
569 /* Instruction costs on PPC630 processors. */
571 struct processor_costs ppc630_cost = {
572 COSTS_N_INSNS (5), /* mulsi */
573 COSTS_N_INSNS (4), /* mulsi_const */
574 COSTS_N_INSNS (3), /* mulsi_const9 */
575 COSTS_N_INSNS (7), /* muldi */
576 COSTS_N_INSNS (21), /* divsi */
577 COSTS_N_INSNS (37), /* divdi */
578 COSTS_N_INSNS (3), /* fp */
579 COSTS_N_INSNS (3), /* dmul */
580 COSTS_N_INSNS (17), /* sdiv */
581 COSTS_N_INSNS (21), /* ddiv */
588 /* Instruction costs on Cell processor. */
589 /* COSTS_N_INSNS (1) ~ one add. */
591 struct processor_costs ppccell_cost = {
592 COSTS_N_INSNS (9/2)+2, /* mulsi */
593 COSTS_N_INSNS (6/2), /* mulsi_const */
594 COSTS_N_INSNS (6/2), /* mulsi_const9 */
595 COSTS_N_INSNS (15/2)+2, /* muldi */
596 COSTS_N_INSNS (38/2), /* divsi */
597 COSTS_N_INSNS (70/2), /* divdi */
598 COSTS_N_INSNS (10/2), /* fp */
599 COSTS_N_INSNS (10/2), /* dmul */
600 COSTS_N_INSNS (74/2), /* sdiv */
601 COSTS_N_INSNS (74/2), /* ddiv */
608 /* Instruction costs on PPC750 and PPC7400 processors. */
610 struct processor_costs ppc750_cost = {
611 COSTS_N_INSNS (5), /* mulsi */
612 COSTS_N_INSNS (3), /* mulsi_const */
613 COSTS_N_INSNS (2), /* mulsi_const9 */
614 COSTS_N_INSNS (5), /* muldi */
615 COSTS_N_INSNS (17), /* divsi */
616 COSTS_N_INSNS (17), /* divdi */
617 COSTS_N_INSNS (3), /* fp */
618 COSTS_N_INSNS (3), /* dmul */
619 COSTS_N_INSNS (17), /* sdiv */
620 COSTS_N_INSNS (31), /* ddiv */
627 /* Instruction costs on PPC7450 processors. */
629 struct processor_costs ppc7450_cost = {
630 COSTS_N_INSNS (4), /* mulsi */
631 COSTS_N_INSNS (3), /* mulsi_const */
632 COSTS_N_INSNS (3), /* mulsi_const9 */
633 COSTS_N_INSNS (4), /* muldi */
634 COSTS_N_INSNS (23), /* divsi */
635 COSTS_N_INSNS (23), /* divdi */
636 COSTS_N_INSNS (5), /* fp */
637 COSTS_N_INSNS (5), /* dmul */
638 COSTS_N_INSNS (21), /* sdiv */
639 COSTS_N_INSNS (35), /* ddiv */
646 /* Instruction costs on PPC8540 processors. */
648 struct processor_costs ppc8540_cost = {
649 COSTS_N_INSNS (4), /* mulsi */
650 COSTS_N_INSNS (4), /* mulsi_const */
651 COSTS_N_INSNS (4), /* mulsi_const9 */
652 COSTS_N_INSNS (4), /* muldi */
653 COSTS_N_INSNS (19), /* divsi */
654 COSTS_N_INSNS (19), /* divdi */
655 COSTS_N_INSNS (4), /* fp */
656 COSTS_N_INSNS (4), /* dmul */
657 COSTS_N_INSNS (29), /* sdiv */
658 COSTS_N_INSNS (29), /* ddiv */
662 1, /* prefetch streams /*/
665 /* Instruction costs on POWER4 and POWER5 processors. */
667 struct processor_costs power4_cost = {
668 COSTS_N_INSNS (3), /* mulsi */
669 COSTS_N_INSNS (2), /* mulsi_const */
670 COSTS_N_INSNS (2), /* mulsi_const9 */
671 COSTS_N_INSNS (4), /* muldi */
672 COSTS_N_INSNS (18), /* divsi */
673 COSTS_N_INSNS (34), /* divdi */
674 COSTS_N_INSNS (3), /* fp */
675 COSTS_N_INSNS (3), /* dmul */
676 COSTS_N_INSNS (17), /* sdiv */
677 COSTS_N_INSNS (17), /* ddiv */
681 8, /* prefetch streams /*/
684 /* Instruction costs on POWER6 processors. */
686 struct processor_costs power6_cost = {
687 COSTS_N_INSNS (8), /* mulsi */
688 COSTS_N_INSNS (8), /* mulsi_const */
689 COSTS_N_INSNS (8), /* mulsi_const9 */
690 COSTS_N_INSNS (8), /* muldi */
691 COSTS_N_INSNS (22), /* divsi */
692 COSTS_N_INSNS (28), /* divdi */
693 COSTS_N_INSNS (3), /* fp */
694 COSTS_N_INSNS (3), /* dmul */
695 COSTS_N_INSNS (13), /* sdiv */
696 COSTS_N_INSNS (16), /* ddiv */
700 16, /* prefetch streams */
704 static bool rs6000_function_ok_for_sibcall (tree, tree);
705 static const char *rs6000_invalid_within_doloop (const_rtx);
706 static rtx rs6000_generate_compare (enum rtx_code);
707 static void rs6000_emit_stack_tie (void);
708 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
709 static rtx spe_synthesize_frame_save (rtx);
710 static bool spe_func_has_64bit_regs_p (void);
711 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
713 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
714 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
715 static unsigned rs6000_hash_constant (rtx);
716 static unsigned toc_hash_function (const void *);
717 static int toc_hash_eq (const void *, const void *);
718 static int constant_pool_expr_1 (rtx, int *, int *);
719 static bool constant_pool_expr_p (rtx);
720 static bool legitimate_small_data_p (enum machine_mode, rtx);
721 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
722 static struct machine_function * rs6000_init_machine_status (void);
723 static bool rs6000_assemble_integer (rtx, unsigned int, int);
724 static bool no_global_regs_above (int);
725 #ifdef HAVE_GAS_HIDDEN
726 static void rs6000_assemble_visibility (tree, int);
728 static int rs6000_ra_ever_killed (void);
729 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
730 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
731 static bool rs6000_ms_bitfield_layout_p (const_tree);
732 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
733 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
734 static const char *rs6000_mangle_type (const_tree);
735 extern const struct attribute_spec rs6000_attribute_table[];
736 static void rs6000_set_default_type_attributes (tree);
737 static bool rs6000_reg_live_or_pic_offset_p (int);
738 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
739 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
740 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
742 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
743 static bool rs6000_return_in_memory (const_tree, const_tree);
744 static void rs6000_file_start (void);
746 static int rs6000_elf_reloc_rw_mask (void);
747 static void rs6000_elf_asm_out_constructor (rtx, int);
748 static void rs6000_elf_asm_out_destructor (rtx, int);
749 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
750 static void rs6000_elf_asm_init_sections (void);
751 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
752 unsigned HOST_WIDE_INT);
753 static void rs6000_elf_encode_section_info (tree, rtx, int)
756 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx);
758 static void rs6000_xcoff_asm_output_anchor (rtx);
759 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
760 static void rs6000_xcoff_asm_init_sections (void);
761 static int rs6000_xcoff_reloc_rw_mask (void);
762 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
763 static section *rs6000_xcoff_select_section (tree, int,
764 unsigned HOST_WIDE_INT);
765 static void rs6000_xcoff_unique_section (tree, int);
766 static section *rs6000_xcoff_select_rtx_section
767 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
768 static const char * rs6000_xcoff_strip_name_encoding (const char *);
769 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
770 static void rs6000_xcoff_file_start (void);
771 static void rs6000_xcoff_file_end (void);
773 static int rs6000_variable_issue (FILE *, int, rtx, int);
774 static bool rs6000_rtx_costs (rtx, int, int, int *);
775 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
776 static void rs6000_sched_init (FILE *, int, int);
777 static bool is_microcoded_insn (rtx);
778 static bool is_nonpipeline_insn (rtx);
779 static bool is_cracked_insn (rtx);
780 static bool is_branch_slot_insn (rtx);
781 static bool is_load_insn (rtx);
782 static rtx get_store_dest (rtx pat);
783 static bool is_store_insn (rtx);
784 static bool set_to_load_agen (rtx,rtx);
785 static bool adjacent_mem_locations (rtx,rtx);
786 static int rs6000_adjust_priority (rtx, int);
787 static int rs6000_issue_rate (void);
788 static bool rs6000_is_costly_dependence (dep_t, int, int);
789 static rtx get_next_active_insn (rtx, rtx);
790 static bool insn_terminates_group_p (rtx , enum group_termination);
791 static bool insn_must_be_first_in_group (rtx);
792 static bool insn_must_be_last_in_group (rtx);
793 static bool is_costly_group (rtx *, rtx);
794 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
795 static int redefine_groups (FILE *, int, rtx, rtx);
796 static int pad_groups (FILE *, int, rtx, rtx);
797 static void rs6000_sched_finish (FILE *, int);
798 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
799 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
800 static int rs6000_use_sched_lookahead (void);
801 static int rs6000_use_sched_lookahead_guard (rtx);
802 static tree rs6000_builtin_mask_for_load (void);
803 static tree rs6000_builtin_mul_widen_even (tree);
804 static tree rs6000_builtin_mul_widen_odd (tree);
805 static tree rs6000_builtin_conversion (enum tree_code, tree);
807 static void def_builtin (int, const char *, tree, int);
808 static bool rs6000_vector_alignment_reachable (const_tree, bool);
809 static void rs6000_init_builtins (void);
810 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
811 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
812 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
813 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
814 static void altivec_init_builtins (void);
815 static void rs6000_common_init_builtins (void);
816 static void rs6000_init_libfuncs (void);
818 static void enable_mask_for_builtins (struct builtin_description *, int,
819 enum rs6000_builtins,
820 enum rs6000_builtins);
821 static tree build_opaque_vector_type (tree, int);
822 static void spe_init_builtins (void);
823 static rtx spe_expand_builtin (tree, rtx, bool *);
824 static rtx spe_expand_stv_builtin (enum insn_code, tree);
825 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
826 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
827 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
828 static rs6000_stack_t *rs6000_stack_info (void);
829 static void debug_stack_info (rs6000_stack_t *);
831 static rtx altivec_expand_builtin (tree, rtx, bool *);
832 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
833 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
834 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
835 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
836 static rtx altivec_expand_predicate_builtin (enum insn_code,
837 const char *, tree, rtx);
838 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
839 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
840 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
841 static rtx altivec_expand_vec_set_builtin (tree);
842 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
843 static int get_element_number (tree, tree);
844 static bool rs6000_handle_option (size_t, const char *, int);
845 static void rs6000_parse_tls_size_option (void);
846 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
847 static int first_altivec_reg_to_save (void);
848 static unsigned int compute_vrsave_mask (void);
849 static void compute_save_world_info (rs6000_stack_t *info_ptr);
850 static void is_altivec_return_reg (rtx, void *);
851 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
852 int easy_vector_constant (rtx, enum machine_mode);
853 static bool rs6000_is_opaque_type (const_tree);
854 static rtx rs6000_dwarf_register_span (rtx);
855 static void rs6000_init_dwarf_reg_sizes_extra (tree);
856 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
857 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
858 static rtx rs6000_tls_get_addr (void);
859 static rtx rs6000_got_sym (void);
860 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
861 static const char *rs6000_get_some_local_dynamic_name (void);
862 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
863 static rtx rs6000_complex_function_value (enum machine_mode);
864 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
865 enum machine_mode, tree);
866 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
868 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
869 tree, HOST_WIDE_INT);
870 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
873 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
874 const_tree, HOST_WIDE_INT,
876 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree, int, bool);
877 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
878 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
879 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
880 enum machine_mode, tree,
882 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
884 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
886 static const char *invalid_arg_for_unprototyped_fn (const_tree, const_tree, const_tree);
888 static void macho_branch_islands (void);
889 static int no_previous_def (tree function_name);
890 static tree get_prev_label (tree function_name);
891 static void rs6000_darwin_file_start (void);
894 static tree rs6000_build_builtin_va_list (void);
895 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
896 static bool rs6000_must_pass_in_stack (enum machine_mode, const_tree);
897 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
898 static bool rs6000_vector_mode_supported_p (enum machine_mode);
899 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
901 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
903 static int get_vsel_insn (enum machine_mode);
904 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
905 static tree rs6000_stack_protect_fail (void);
907 const int INSN_NOT_AVAILABLE = -1;
908 static enum machine_mode rs6000_eh_return_filter_mode (void);
910 /* Hash table stuff for keeping track of TOC entries. */
912 struct toc_hash_struct GTY(())
914 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
915 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
917 enum machine_mode key_mode;
921 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
923 /* Default register names. */
924 char rs6000_reg_names[][8] =
926 "0", "1", "2", "3", "4", "5", "6", "7",
927 "8", "9", "10", "11", "12", "13", "14", "15",
928 "16", "17", "18", "19", "20", "21", "22", "23",
929 "24", "25", "26", "27", "28", "29", "30", "31",
930 "0", "1", "2", "3", "4", "5", "6", "7",
931 "8", "9", "10", "11", "12", "13", "14", "15",
932 "16", "17", "18", "19", "20", "21", "22", "23",
933 "24", "25", "26", "27", "28", "29", "30", "31",
934 "mq", "lr", "ctr","ap",
935 "0", "1", "2", "3", "4", "5", "6", "7",
937 /* AltiVec registers. */
938 "0", "1", "2", "3", "4", "5", "6", "7",
939 "8", "9", "10", "11", "12", "13", "14", "15",
940 "16", "17", "18", "19", "20", "21", "22", "23",
941 "24", "25", "26", "27", "28", "29", "30", "31",
944 "spe_acc", "spefscr",
945 /* Soft frame pointer. */
949 #ifdef TARGET_REGNAMES
950 static const char alt_reg_names[][8] =
952 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
953 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
954 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
955 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
956 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
957 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
958 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
959 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
960 "mq", "lr", "ctr", "ap",
961 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
963 /* AltiVec registers. */
964 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
965 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
966 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
967 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
970 "spe_acc", "spefscr",
971 /* Soft frame pointer. */
976 #ifndef MASK_STRICT_ALIGN
977 #define MASK_STRICT_ALIGN 0
979 #ifndef TARGET_PROFILE_KERNEL
980 #define TARGET_PROFILE_KERNEL 0
983 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
984 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
986 /* Initialize the GCC target structure. */
987 #undef TARGET_ATTRIBUTE_TABLE
988 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
989 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
990 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
992 #undef TARGET_ASM_ALIGNED_DI_OP
993 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
995 /* Default unaligned ops are only provided for ELF. Find the ops needed
996 for non-ELF systems. */
997 #ifndef OBJECT_FORMAT_ELF
999 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1001 #undef TARGET_ASM_UNALIGNED_HI_OP
1002 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1003 #undef TARGET_ASM_UNALIGNED_SI_OP
1004 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1005 #undef TARGET_ASM_UNALIGNED_DI_OP
1006 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1009 #undef TARGET_ASM_UNALIGNED_HI_OP
1010 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1011 #undef TARGET_ASM_UNALIGNED_SI_OP
1012 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1013 #undef TARGET_ASM_UNALIGNED_DI_OP
1014 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1015 #undef TARGET_ASM_ALIGNED_DI_OP
1016 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1020 /* This hook deals with fixups for relocatable code and DI-mode objects
1022 #undef TARGET_ASM_INTEGER
1023 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1025 #ifdef HAVE_GAS_HIDDEN
1026 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1027 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1030 #undef TARGET_HAVE_TLS
1031 #define TARGET_HAVE_TLS HAVE_AS_TLS
1033 #undef TARGET_CANNOT_FORCE_CONST_MEM
1034 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1036 #undef TARGET_ASM_FUNCTION_PROLOGUE
1037 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1038 #undef TARGET_ASM_FUNCTION_EPILOGUE
1039 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1041 #undef TARGET_SCHED_VARIABLE_ISSUE
1042 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1044 #undef TARGET_SCHED_ISSUE_RATE
1045 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1046 #undef TARGET_SCHED_ADJUST_COST
1047 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1048 #undef TARGET_SCHED_ADJUST_PRIORITY
1049 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1050 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1051 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1052 #undef TARGET_SCHED_INIT
1053 #define TARGET_SCHED_INIT rs6000_sched_init
1054 #undef TARGET_SCHED_FINISH
1055 #define TARGET_SCHED_FINISH rs6000_sched_finish
1056 #undef TARGET_SCHED_REORDER
1057 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1058 #undef TARGET_SCHED_REORDER2
1059 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1061 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1062 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1064 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1065 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1067 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1068 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1069 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1070 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1071 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1072 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1073 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1074 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1076 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1077 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1079 #undef TARGET_INIT_BUILTINS
1080 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1082 #undef TARGET_EXPAND_BUILTIN
1083 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1085 #undef TARGET_MANGLE_TYPE
1086 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1088 #undef TARGET_INIT_LIBFUNCS
1089 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1092 #undef TARGET_BINDS_LOCAL_P
1093 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1096 #undef TARGET_MS_BITFIELD_LAYOUT_P
1097 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1099 #undef TARGET_ASM_OUTPUT_MI_THUNK
1100 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1102 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1103 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1105 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1106 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1108 #undef TARGET_INVALID_WITHIN_DOLOOP
1109 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1111 #undef TARGET_RTX_COSTS
1112 #define TARGET_RTX_COSTS rs6000_rtx_costs
1113 #undef TARGET_ADDRESS_COST
1114 #define TARGET_ADDRESS_COST hook_int_rtx_0
1116 #undef TARGET_VECTOR_OPAQUE_P
1117 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1119 #undef TARGET_DWARF_REGISTER_SPAN
1120 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1122 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1123 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1125 /* On rs6000, function arguments are promoted, as are function return
1127 #undef TARGET_PROMOTE_FUNCTION_ARGS
1128 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1129 #undef TARGET_PROMOTE_FUNCTION_RETURN
1130 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1132 #undef TARGET_RETURN_IN_MEMORY
1133 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1135 #undef TARGET_SETUP_INCOMING_VARARGS
1136 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1138 /* Always strict argument naming on rs6000. */
1139 #undef TARGET_STRICT_ARGUMENT_NAMING
1140 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1141 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1142 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1143 #undef TARGET_SPLIT_COMPLEX_ARG
1144 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1145 #undef TARGET_MUST_PASS_IN_STACK
1146 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1147 #undef TARGET_PASS_BY_REFERENCE
1148 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1149 #undef TARGET_ARG_PARTIAL_BYTES
1150 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1152 #undef TARGET_BUILD_BUILTIN_VA_LIST
1153 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1155 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1156 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1158 #undef TARGET_EH_RETURN_FILTER_MODE
1159 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1161 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1162 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1164 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1165 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1167 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1168 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1170 #undef TARGET_HANDLE_OPTION
1171 #define TARGET_HANDLE_OPTION rs6000_handle_option
1173 #undef TARGET_DEFAULT_TARGET_FLAGS
1174 #define TARGET_DEFAULT_TARGET_FLAGS \
1177 #undef TARGET_STACK_PROTECT_FAIL
1178 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1180 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1181 The PowerPC architecture requires only weak consistency among
1182 processors--that is, memory accesses between processors need not be
1183 sequentially consistent and memory accesses among processors can occur
1184 in any order. The ability to order memory accesses weakly provides
1185 opportunities for more efficient use of the system bus. Unless a
1186 dependency exists, the 604e allows read operations to precede store
1188 #undef TARGET_RELAXED_ORDERING
1189 #define TARGET_RELAXED_ORDERING true
1192 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1193 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1196 /* Use a 32-bit anchor range. This leads to sequences like:
1198 addis tmp,anchor,high
1201 where tmp itself acts as an anchor, and can be shared between
1202 accesses to the same 64k page. */
1203 #undef TARGET_MIN_ANCHOR_OFFSET
1204 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1205 #undef TARGET_MAX_ANCHOR_OFFSET
1206 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1207 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1208 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1210 struct gcc_target targetm = TARGET_INITIALIZER;
1213 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1216 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1218 /* The GPRs can hold any mode, but values bigger than one register
1219 cannot go past R31. */
1220 if (INT_REGNO_P (regno))
1221 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1223 /* The float registers can only hold floating modes and DImode.
1224 This excludes the 32-bit decimal float mode for now. */
1225 if (FP_REGNO_P (regno))
1227 (SCALAR_FLOAT_MODE_P (mode)
1228 && (mode != TDmode || (regno % 2) == 0)
1230 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1231 || (GET_MODE_CLASS (mode) == MODE_INT
1232 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1234 /* The CR register can only hold CC modes. */
1235 if (CR_REGNO_P (regno))
1236 return GET_MODE_CLASS (mode) == MODE_CC;
1238 if (XER_REGNO_P (regno))
1239 return mode == PSImode;
1241 /* AltiVec only in AldyVec registers. */
1242 if (ALTIVEC_REGNO_P (regno))
1243 return ALTIVEC_VECTOR_MODE (mode);
1245 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1246 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1249 /* We cannot put TImode anywhere except general register and it must be
1250 able to fit within the register set. */
1252 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1255 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1257 rs6000_init_hard_regno_mode_ok (void)
1261 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1262 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1263 if (rs6000_hard_regno_mode_ok (r, m))
1264 rs6000_hard_regno_mode_ok_p[m][r] = true;
1268 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1271 darwin_rs6000_override_options (void)
1273 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1275 rs6000_altivec_abi = 1;
1276 TARGET_ALTIVEC_VRSAVE = 1;
1277 if (DEFAULT_ABI == ABI_DARWIN)
1279 if (MACHO_DYNAMIC_NO_PIC_P)
1282 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1285 else if (flag_pic == 1)
1290 if (TARGET_64BIT && ! TARGET_POWERPC64)
1292 target_flags |= MASK_POWERPC64;
1293 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1297 rs6000_default_long_calls = 1;
1298 target_flags |= MASK_SOFT_FLOAT;
1301 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1303 if (!flag_mkernel && !flag_apple_kext
1305 && ! (target_flags_explicit & MASK_ALTIVEC))
1306 target_flags |= MASK_ALTIVEC;
1308 /* Unless the user (not the configurer) has explicitly overridden
1309 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1310 G4 unless targetting the kernel. */
1313 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1314 && ! (target_flags_explicit & MASK_ALTIVEC)
1315 && ! rs6000_select[1].string)
1317 target_flags |= MASK_ALTIVEC;
1322 /* If not otherwise specified by a target, make 'long double' equivalent to
1325 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1326 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1329 /* Override command line options. Mostly we process the processor
1330 type and sometimes adjust other TARGET_ options. */
1333 rs6000_override_options (const char *default_cpu)
1336 struct rs6000_cpu_select *ptr;
1339 /* Simplifications for entries below. */
1342 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1343 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1346 /* This table occasionally claims that a processor does not support
1347 a particular feature even though it does, but the feature is slower
1348 than the alternative. Thus, it shouldn't be relied on as a
1349 complete description of the processor's support.
1351 Please keep this list in order, and don't forget to update the
1352 documentation in invoke.texi when adding a new processor or
1356 const char *const name; /* Canonical processor name. */
1357 const enum processor_type processor; /* Processor type enum value. */
1358 const int target_enable; /* Target flags to enable. */
1359 } const processor_target_table[]
1360 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1361 {"403", PROCESSOR_PPC403,
1362 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1363 {"405", PROCESSOR_PPC405,
1364 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1365 {"405fp", PROCESSOR_PPC405,
1366 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1367 {"440", PROCESSOR_PPC440,
1368 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1369 {"440fp", PROCESSOR_PPC440,
1370 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1371 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1372 {"601", PROCESSOR_PPC601,
1373 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1374 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1375 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1376 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1377 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1378 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1379 {"620", PROCESSOR_PPC620,
1380 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1381 {"630", PROCESSOR_PPC630,
1382 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1383 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1384 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1385 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1386 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1387 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1388 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1389 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1390 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1391 /* 8548 has a dummy entry for now. */
1392 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1393 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1394 {"970", PROCESSOR_POWER4,
1395 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1396 {"cell", PROCESSOR_CELL,
1397 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1398 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1399 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1400 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1401 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1402 {"G5", PROCESSOR_POWER4,
1403 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1404 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1405 {"power2", PROCESSOR_POWER,
1406 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1407 {"power3", PROCESSOR_PPC630,
1408 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1409 {"power4", PROCESSOR_POWER4,
1410 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1411 {"power5", PROCESSOR_POWER5,
1412 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1413 | MASK_MFCRF | MASK_POPCNTB},
1414 {"power5+", PROCESSOR_POWER5,
1415 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1416 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1417 {"power6", PROCESSOR_POWER6,
1418 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1419 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1420 {"power6x", PROCESSOR_POWER6,
1421 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1422 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1423 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1424 {"powerpc64", PROCESSOR_POWERPC64,
1425 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1426 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1427 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1428 {"rios2", PROCESSOR_RIOS2,
1429 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1430 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1431 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1432 {"rs64", PROCESSOR_RS64A,
1433 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1436 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1438 /* Some OSs don't support saving the high part of 64-bit registers on
1439 context switch. Other OSs don't support saving Altivec registers.
1440 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1441 settings; if the user wants either, the user must explicitly specify
1442 them and we won't interfere with the user's specification. */
1445 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1446 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1447 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1448 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1449 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1452 rs6000_init_hard_regno_mode_ok ();
1454 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1455 #ifdef OS_MISSING_POWERPC64
1456 if (OS_MISSING_POWERPC64)
1457 set_masks &= ~MASK_POWERPC64;
1459 #ifdef OS_MISSING_ALTIVEC
1460 if (OS_MISSING_ALTIVEC)
1461 set_masks &= ~MASK_ALTIVEC;
1464 /* Don't override by the processor default if given explicitly. */
1465 set_masks &= ~target_flags_explicit;
1467 /* Identify the processor type. */
1468 rs6000_select[0].string = default_cpu;
1469 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1471 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1473 ptr = &rs6000_select[i];
1474 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1476 for (j = 0; j < ptt_size; j++)
1477 if (! strcmp (ptr->string, processor_target_table[j].name))
1479 if (ptr->set_tune_p)
1480 rs6000_cpu = processor_target_table[j].processor;
1482 if (ptr->set_arch_p)
1484 target_flags &= ~set_masks;
1485 target_flags |= (processor_target_table[j].target_enable
1492 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1499 /* If we are optimizing big endian systems for space, use the load/store
1500 multiple and string instructions. */
1501 if (BYTES_BIG_ENDIAN && optimize_size)
1502 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1504 /* Don't allow -mmultiple or -mstring on little endian systems
1505 unless the cpu is a 750, because the hardware doesn't support the
1506 instructions used in little endian mode, and causes an alignment
1507 trap. The 750 does not cause an alignment trap (except when the
1508 target is unaligned). */
1510 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1512 if (TARGET_MULTIPLE)
1514 target_flags &= ~MASK_MULTIPLE;
1515 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1516 warning (0, "-mmultiple is not supported on little endian systems");
1521 target_flags &= ~MASK_STRING;
1522 if ((target_flags_explicit & MASK_STRING) != 0)
1523 warning (0, "-mstring is not supported on little endian systems");
1527 /* Set debug flags */
1528 if (rs6000_debug_name)
1530 if (! strcmp (rs6000_debug_name, "all"))
1531 rs6000_debug_stack = rs6000_debug_arg = 1;
1532 else if (! strcmp (rs6000_debug_name, "stack"))
1533 rs6000_debug_stack = 1;
1534 else if (! strcmp (rs6000_debug_name, "arg"))
1535 rs6000_debug_arg = 1;
1537 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1540 if (rs6000_traceback_name)
1542 if (! strncmp (rs6000_traceback_name, "full", 4))
1543 rs6000_traceback = traceback_full;
1544 else if (! strncmp (rs6000_traceback_name, "part", 4))
1545 rs6000_traceback = traceback_part;
1546 else if (! strncmp (rs6000_traceback_name, "no", 2))
1547 rs6000_traceback = traceback_none;
1549 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1550 rs6000_traceback_name);
1553 if (!rs6000_explicit_options.long_double)
1554 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1556 #ifndef POWERPC_LINUX
1557 if (!rs6000_explicit_options.ieee)
1558 rs6000_ieeequad = 1;
1561 /* Set Altivec ABI as default for powerpc64 linux. */
1562 if (TARGET_ELF && TARGET_64BIT)
1564 rs6000_altivec_abi = 1;
1565 TARGET_ALTIVEC_VRSAVE = 1;
1568 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1569 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1571 rs6000_darwin64_abi = 1;
1573 darwin_one_byte_bool = 1;
1575 /* Default to natural alignment, for better performance. */
1576 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1579 /* Place FP constants in the constant pool instead of TOC
1580 if section anchors enabled. */
1581 if (flag_section_anchors)
1582 TARGET_NO_FP_IN_TOC = 1;
1584 /* Handle -mtls-size option. */
1585 rs6000_parse_tls_size_option ();
1587 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1588 SUBTARGET_OVERRIDE_OPTIONS;
1590 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1591 SUBSUBTARGET_OVERRIDE_OPTIONS;
1593 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1594 SUB3TARGET_OVERRIDE_OPTIONS;
1599 /* The e500 does not have string instructions, and we set
1600 MASK_STRING above when optimizing for size. */
1601 if ((target_flags & MASK_STRING) != 0)
1602 target_flags = target_flags & ~MASK_STRING;
1604 else if (rs6000_select[1].string != NULL)
1606 /* For the powerpc-eabispe configuration, we set all these by
1607 default, so let's unset them if we manually set another
1608 CPU that is not the E500. */
1609 if (!rs6000_explicit_options.abi)
1611 if (!rs6000_explicit_options.spe)
1613 if (!rs6000_explicit_options.float_gprs)
1614 rs6000_float_gprs = 0;
1615 if (!rs6000_explicit_options.isel)
1619 /* Detect invalid option combinations with E500. */
1622 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1623 && rs6000_cpu != PROCESSOR_POWER5
1624 && rs6000_cpu != PROCESSOR_POWER6
1625 && rs6000_cpu != PROCESSOR_CELL);
1626 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1627 || rs6000_cpu == PROCESSOR_POWER5);
1628 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1629 || rs6000_cpu == PROCESSOR_POWER5
1630 || rs6000_cpu == PROCESSOR_POWER6);
1632 rs6000_sched_restricted_insns_priority
1633 = (rs6000_sched_groups ? 1 : 0);
1635 /* Handle -msched-costly-dep option. */
1636 rs6000_sched_costly_dep
1637 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1639 if (rs6000_sched_costly_dep_str)
1641 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1642 rs6000_sched_costly_dep = no_dep_costly;
1643 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1644 rs6000_sched_costly_dep = all_deps_costly;
1645 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1646 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1647 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1648 rs6000_sched_costly_dep = store_to_load_dep_costly;
1650 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1653 /* Handle -minsert-sched-nops option. */
1654 rs6000_sched_insert_nops
1655 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1657 if (rs6000_sched_insert_nops_str)
1659 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1660 rs6000_sched_insert_nops = sched_finish_none;
1661 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1662 rs6000_sched_insert_nops = sched_finish_pad_groups;
1663 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1664 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1666 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1669 #ifdef TARGET_REGNAMES
1670 /* If the user desires alternate register names, copy in the
1671 alternate names now. */
1672 if (TARGET_REGNAMES)
1673 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1676 /* Set aix_struct_return last, after the ABI is determined.
1677 If -maix-struct-return or -msvr4-struct-return was explicitly
1678 used, don't override with the ABI default. */
1679 if (!rs6000_explicit_options.aix_struct_ret)
1680 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1682 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1683 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1686 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1688 /* We can only guarantee the availability of DI pseudo-ops when
1689 assembling for 64-bit targets. */
1692 targetm.asm_out.aligned_op.di = NULL;
1693 targetm.asm_out.unaligned_op.di = NULL;
1696 /* Set branch target alignment, if not optimizing for size. */
1699 /* Cell wants to be aligned 8byte for dual issue. */
1700 if (rs6000_cpu == PROCESSOR_CELL)
1702 if (align_functions <= 0)
1703 align_functions = 8;
1704 if (align_jumps <= 0)
1706 if (align_loops <= 0)
1709 if (rs6000_align_branch_targets)
1711 if (align_functions <= 0)
1712 align_functions = 16;
1713 if (align_jumps <= 0)
1715 if (align_loops <= 0)
1718 if (align_jumps_max_skip <= 0)
1719 align_jumps_max_skip = 15;
1720 if (align_loops_max_skip <= 0)
1721 align_loops_max_skip = 15;
1724 /* Arrange to save and restore machine status around nested functions. */
1725 init_machine_status = rs6000_init_machine_status;
1727 /* We should always be splitting complex arguments, but we can't break
1728 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1729 if (DEFAULT_ABI != ABI_AIX)
1730 targetm.calls.split_complex_arg = NULL;
1732 /* Initialize rs6000_cost with the appropriate target costs. */
1734 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1738 case PROCESSOR_RIOS1:
1739 rs6000_cost = &rios1_cost;
1742 case PROCESSOR_RIOS2:
1743 rs6000_cost = &rios2_cost;
1746 case PROCESSOR_RS64A:
1747 rs6000_cost = &rs64a_cost;
1750 case PROCESSOR_MPCCORE:
1751 rs6000_cost = &mpccore_cost;
1754 case PROCESSOR_PPC403:
1755 rs6000_cost = &ppc403_cost;
1758 case PROCESSOR_PPC405:
1759 rs6000_cost = &ppc405_cost;
1762 case PROCESSOR_PPC440:
1763 rs6000_cost = &ppc440_cost;
1766 case PROCESSOR_PPC601:
1767 rs6000_cost = &ppc601_cost;
1770 case PROCESSOR_PPC603:
1771 rs6000_cost = &ppc603_cost;
1774 case PROCESSOR_PPC604:
1775 rs6000_cost = &ppc604_cost;
1778 case PROCESSOR_PPC604e:
1779 rs6000_cost = &ppc604e_cost;
1782 case PROCESSOR_PPC620:
1783 rs6000_cost = &ppc620_cost;
1786 case PROCESSOR_PPC630:
1787 rs6000_cost = &ppc630_cost;
1790 case PROCESSOR_CELL:
1791 rs6000_cost = &ppccell_cost;
1794 case PROCESSOR_PPC750:
1795 case PROCESSOR_PPC7400:
1796 rs6000_cost = &ppc750_cost;
1799 case PROCESSOR_PPC7450:
1800 rs6000_cost = &ppc7450_cost;
1803 case PROCESSOR_PPC8540:
1804 rs6000_cost = &ppc8540_cost;
1807 case PROCESSOR_POWER4:
1808 case PROCESSOR_POWER5:
1809 rs6000_cost = &power4_cost;
1812 case PROCESSOR_POWER6:
1813 rs6000_cost = &power6_cost;
1820 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1821 set_param_value ("simultaneous-prefetches",
1822 rs6000_cost->simultaneous_prefetches);
1823 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1824 set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size);
1825 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
1826 set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
1827 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1828 set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size);
1831 /* Implement targetm.vectorize.builtin_mask_for_load. */
1833 rs6000_builtin_mask_for_load (void)
1836 return altivec_builtin_mask_for_load;
1841 /* Implement targetm.vectorize.builtin_conversion. */
1843 rs6000_builtin_conversion (enum tree_code code, tree type)
1845 if (!TARGET_ALTIVEC)
1851 switch (TYPE_MODE (type))
1854 return TYPE_UNSIGNED (type) ?
1855 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1856 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1865 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1867 rs6000_builtin_mul_widen_even (tree type)
1869 if (!TARGET_ALTIVEC)
1872 switch (TYPE_MODE (type))
1875 return TYPE_UNSIGNED (type) ?
1876 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1877 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1880 return TYPE_UNSIGNED (type) ?
1881 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1882 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1888 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1890 rs6000_builtin_mul_widen_odd (tree type)
1892 if (!TARGET_ALTIVEC)
1895 switch (TYPE_MODE (type))
1898 return TYPE_UNSIGNED (type) ?
1899 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1900 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1903 return TYPE_UNSIGNED (type) ?
1904 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1905 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1912 /* Return true iff, data reference of TYPE can reach vector alignment (16)
1913 after applying N number of iterations. This routine does not determine
1914 how may iterations are required to reach desired alignment. */
1917 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
1924 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
1927 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
1937 /* Assuming that all other types are naturally aligned. CHECKME! */
1942 /* Handle generic options of the form -mfoo=yes/no.
1943 NAME is the option name.
1944 VALUE is the option value.
1945 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1946 whether the option value is 'yes' or 'no' respectively. */
1948 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1952 else if (!strcmp (value, "yes"))
1954 else if (!strcmp (value, "no"))
1957 error ("unknown -m%s= option specified: '%s'", name, value);
1960 /* Validate and record the size specified with the -mtls-size option. */
1963 rs6000_parse_tls_size_option (void)
1965 if (rs6000_tls_size_string == 0)
1967 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1968 rs6000_tls_size = 16;
1969 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1970 rs6000_tls_size = 32;
1971 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1972 rs6000_tls_size = 64;
1974 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1978 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1980 if (DEFAULT_ABI == ABI_DARWIN)
1981 /* The Darwin libraries never set errno, so we might as well
1982 avoid calling them when that's the only reason we would. */
1983 flag_errno_math = 0;
1985 /* Double growth factor to counter reduced min jump length. */
1986 set_param_value ("max-grow-copy-bb-insns", 16);
1988 /* Enable section anchors by default.
1989 Skip section anchors for Objective C and Objective C++
1990 until front-ends fixed. */
1991 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1992 flag_section_anchors = 1;
1995 /* Implement TARGET_HANDLE_OPTION. */
1998 rs6000_handle_option (size_t code, const char *arg, int value)
2003 target_flags &= ~(MASK_POWER | MASK_POWER2
2004 | MASK_MULTIPLE | MASK_STRING);
2005 target_flags_explicit |= (MASK_POWER | MASK_POWER2
2006 | MASK_MULTIPLE | MASK_STRING);
2008 case OPT_mno_powerpc:
2009 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
2010 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2011 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
2012 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2015 target_flags &= ~MASK_MINIMAL_TOC;
2016 TARGET_NO_FP_IN_TOC = 0;
2017 TARGET_NO_SUM_IN_TOC = 0;
2018 target_flags_explicit |= MASK_MINIMAL_TOC;
2019 #ifdef TARGET_USES_SYSV4_OPT
2020 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2021 just the same as -mminimal-toc. */
2022 target_flags |= MASK_MINIMAL_TOC;
2023 target_flags_explicit |= MASK_MINIMAL_TOC;
2027 #ifdef TARGET_USES_SYSV4_OPT
2029 /* Make -mtoc behave like -mminimal-toc. */
2030 target_flags |= MASK_MINIMAL_TOC;
2031 target_flags_explicit |= MASK_MINIMAL_TOC;
2035 #ifdef TARGET_USES_AIX64_OPT
2040 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
2041 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
2042 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
2045 #ifdef TARGET_USES_AIX64_OPT
2050 target_flags &= ~MASK_POWERPC64;
2051 target_flags_explicit |= MASK_POWERPC64;
2054 case OPT_minsert_sched_nops_:
2055 rs6000_sched_insert_nops_str = arg;
2058 case OPT_mminimal_toc:
2061 TARGET_NO_FP_IN_TOC = 0;
2062 TARGET_NO_SUM_IN_TOC = 0;
2069 target_flags |= (MASK_MULTIPLE | MASK_STRING);
2070 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
2077 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2078 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2082 case OPT_mpowerpc_gpopt:
2083 case OPT_mpowerpc_gfxopt:
2086 target_flags |= MASK_POWERPC;
2087 target_flags_explicit |= MASK_POWERPC;
2091 case OPT_maix_struct_return:
2092 case OPT_msvr4_struct_return:
2093 rs6000_explicit_options.aix_struct_ret = true;
2097 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
2101 rs6000_explicit_options.isel = true;
2102 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
2106 rs6000_explicit_options.spe = true;
2107 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
2111 rs6000_debug_name = arg;
2114 #ifdef TARGET_USES_SYSV4_OPT
2116 rs6000_abi_name = arg;
2120 rs6000_sdata_name = arg;
2123 case OPT_mtls_size_:
2124 rs6000_tls_size_string = arg;
2127 case OPT_mrelocatable:
2130 target_flags |= MASK_MINIMAL_TOC;
2131 target_flags_explicit |= MASK_MINIMAL_TOC;
2132 TARGET_NO_FP_IN_TOC = 1;
2136 case OPT_mrelocatable_lib:
2139 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2140 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2141 TARGET_NO_FP_IN_TOC = 1;
2145 target_flags &= ~MASK_RELOCATABLE;
2146 target_flags_explicit |= MASK_RELOCATABLE;
2152 if (!strcmp (arg, "altivec"))
2154 rs6000_explicit_options.abi = true;
2155 rs6000_altivec_abi = 1;
2158 else if (! strcmp (arg, "no-altivec"))
2160 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2161 the default for rs6000_spe_abi to be chosen later. */
2162 rs6000_altivec_abi = 0;
2164 else if (! strcmp (arg, "spe"))
2166 rs6000_explicit_options.abi = true;
2168 rs6000_altivec_abi = 0;
2169 if (!TARGET_SPE_ABI)
2170 error ("not configured for ABI: '%s'", arg);
2172 else if (! strcmp (arg, "no-spe"))
2174 rs6000_explicit_options.abi = true;
2178 /* These are here for testing during development only, do not
2179 document in the manual please. */
2180 else if (! strcmp (arg, "d64"))
2182 rs6000_darwin64_abi = 1;
2183 warning (0, "Using darwin64 ABI");
2185 else if (! strcmp (arg, "d32"))
2187 rs6000_darwin64_abi = 0;
2188 warning (0, "Using old darwin ABI");
2191 else if (! strcmp (arg, "ibmlongdouble"))
2193 rs6000_explicit_options.ieee = true;
2194 rs6000_ieeequad = 0;
2195 warning (0, "Using IBM extended precision long double");
2197 else if (! strcmp (arg, "ieeelongdouble"))
2199 rs6000_explicit_options.ieee = true;
2200 rs6000_ieeequad = 1;
2201 warning (0, "Using IEEE extended precision long double");
2206 error ("unknown ABI specified: '%s'", arg);
2212 rs6000_select[1].string = arg;
2216 rs6000_select[2].string = arg;
2219 case OPT_mtraceback_:
2220 rs6000_traceback_name = arg;
2223 case OPT_mfloat_gprs_:
2224 rs6000_explicit_options.float_gprs = true;
2225 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2226 rs6000_float_gprs = 1;
2227 else if (! strcmp (arg, "double"))
2228 rs6000_float_gprs = 2;
2229 else if (! strcmp (arg, "no"))
2230 rs6000_float_gprs = 0;
2233 error ("invalid option for -mfloat-gprs: '%s'", arg);
2238 case OPT_mlong_double_:
2239 rs6000_explicit_options.long_double = true;
2240 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2241 if (value != 64 && value != 128)
2243 error ("Unknown switch -mlong-double-%s", arg);
2244 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2248 rs6000_long_double_type_size = value;
2251 case OPT_msched_costly_dep_:
2252 rs6000_sched_costly_dep_str = arg;
2256 rs6000_explicit_options.alignment = true;
2257 if (! strcmp (arg, "power"))
2259 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2260 some C library functions, so warn about it. The flag may be
2261 useful for performance studies from time to time though, so
2262 don't disable it entirely. */
2263 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2264 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2265 " it is incompatible with the installed C and C++ libraries");
2266 rs6000_alignment_flags = MASK_ALIGN_POWER;
2268 else if (! strcmp (arg, "natural"))
2269 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2272 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2280 /* Do anything needed at the start of the asm file. */
2283 rs6000_file_start (void)
2287 const char *start = buffer;
2288 struct rs6000_cpu_select *ptr;
2289 const char *default_cpu = TARGET_CPU_DEFAULT;
2290 FILE *file = asm_out_file;
2292 default_file_start ();
2294 #ifdef TARGET_BI_ARCH
2295 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2299 if (flag_verbose_asm)
2301 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2302 rs6000_select[0].string = default_cpu;
2304 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2306 ptr = &rs6000_select[i];
2307 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2309 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2314 if (PPC405_ERRATUM77)
2316 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2320 #ifdef USING_ELFOS_H
2321 switch (rs6000_sdata)
2323 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2324 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2325 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2326 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2329 if (rs6000_sdata && g_switch_value)
2331 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2341 #ifdef HAVE_AS_GNU_ATTRIBUTE
2342 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2344 fprintf (file, "\t.gnu_attribute 4, %d\n",
2345 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
2346 fprintf (file, "\t.gnu_attribute 8, %d\n",
2347 (TARGET_ALTIVEC_ABI ? 2
2348 : TARGET_SPE_ABI ? 3
2353 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2355 switch_to_section (toc_section);
2356 switch_to_section (text_section);
2361 /* Return nonzero if this function is known to have a null epilogue. */
2364 direct_return (void)
2366 if (reload_completed)
2368 rs6000_stack_t *info = rs6000_stack_info ();
2370 if (info->first_gp_reg_save == 32
2371 && info->first_fp_reg_save == 64
2372 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2373 && ! info->lr_save_p
2374 && ! info->cr_save_p
2375 && info->vrsave_mask == 0
2383 /* Return the number of instructions it takes to form a constant in an
2384 integer register. */
2387 num_insns_constant_wide (HOST_WIDE_INT value)
2389 /* signed constant loadable with {cal|addi} */
2390 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2393 /* constant loadable with {cau|addis} */
2394 else if ((value & 0xffff) == 0
2395 && (value >> 31 == -1 || value >> 31 == 0))
2398 #if HOST_BITS_PER_WIDE_INT == 64
2399 else if (TARGET_POWERPC64)
2401 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2402 HOST_WIDE_INT high = value >> 31;
2404 if (high == 0 || high == -1)
2410 return num_insns_constant_wide (high) + 1;
2412 return (num_insns_constant_wide (high)
2413 + num_insns_constant_wide (low) + 1);
2422 num_insns_constant (rtx op, enum machine_mode mode)
2424 HOST_WIDE_INT low, high;
2426 switch (GET_CODE (op))
2429 #if HOST_BITS_PER_WIDE_INT == 64
2430 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2431 && mask64_operand (op, mode))
2435 return num_insns_constant_wide (INTVAL (op));
2443 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2444 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2445 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2448 if (mode == VOIDmode || mode == DImode)
2450 high = CONST_DOUBLE_HIGH (op);
2451 low = CONST_DOUBLE_LOW (op);
2458 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2459 if (DECIMAL_FLOAT_MODE_P (mode))
2460 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2462 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2463 high = l[WORDS_BIG_ENDIAN == 0];
2464 low = l[WORDS_BIG_ENDIAN != 0];
2468 return (num_insns_constant_wide (low)
2469 + num_insns_constant_wide (high));
2472 if ((high == 0 && low >= 0)
2473 || (high == -1 && low < 0))
2474 return num_insns_constant_wide (low);
2476 else if (mask64_operand (op, mode))
2480 return num_insns_constant_wide (high) + 1;
2483 return (num_insns_constant_wide (high)
2484 + num_insns_constant_wide (low) + 1);
2492 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2493 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2494 corresponding element of the vector, but for V4SFmode and V2SFmode,
2495 the corresponding "float" is interpreted as an SImode integer. */
2497 static HOST_WIDE_INT
2498 const_vector_elt_as_int (rtx op, unsigned int elt)
2500 rtx tmp = CONST_VECTOR_ELT (op, elt);
2501 if (GET_MODE (op) == V4SFmode
2502 || GET_MODE (op) == V2SFmode)
2503 tmp = gen_lowpart (SImode, tmp);
2504 return INTVAL (tmp);
2507 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2508 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2509 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2510 all items are set to the same value and contain COPIES replicas of the
2511 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2512 operand and the others are set to the value of the operand's msb. */
2515 vspltis_constant (rtx op, unsigned step, unsigned copies)
2517 enum machine_mode mode = GET_MODE (op);
2518 enum machine_mode inner = GET_MODE_INNER (mode);
2521 unsigned nunits = GET_MODE_NUNITS (mode);
2522 unsigned bitsize = GET_MODE_BITSIZE (inner);
2523 unsigned mask = GET_MODE_MASK (inner);
2525 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2526 HOST_WIDE_INT splat_val = val;
2527 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2529 /* Construct the value to be splatted, if possible. If not, return 0. */
2530 for (i = 2; i <= copies; i *= 2)
2532 HOST_WIDE_INT small_val;
2534 small_val = splat_val >> bitsize;
2536 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2538 splat_val = small_val;
2541 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2542 if (EASY_VECTOR_15 (splat_val))
2545 /* Also check if we can splat, and then add the result to itself. Do so if
2546 the value is positive, of if the splat instruction is using OP's mode;
2547 for splat_val < 0, the splat and the add should use the same mode. */
2548 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2549 && (splat_val >= 0 || (step == 1 && copies == 1)))
2555 /* Check if VAL is present in every STEP-th element, and the
2556 other elements are filled with its most significant bit. */
2557 for (i = 0; i < nunits - 1; ++i)
2559 HOST_WIDE_INT desired_val;
2560 if (((i + 1) & (step - 1)) == 0)
2563 desired_val = msb_val;
2565 if (desired_val != const_vector_elt_as_int (op, i))
2573 /* Return true if OP is of the given MODE and can be synthesized
2574 with a vspltisb, vspltish or vspltisw. */
2577 easy_altivec_constant (rtx op, enum machine_mode mode)
2579 unsigned step, copies;
2581 if (mode == VOIDmode)
2582 mode = GET_MODE (op);
2583 else if (mode != GET_MODE (op))
2586 /* Start with a vspltisw. */
2587 step = GET_MODE_NUNITS (mode) / 4;
2590 if (vspltis_constant (op, step, copies))
2593 /* Then try with a vspltish. */
2599 if (vspltis_constant (op, step, copies))
2602 /* And finally a vspltisb. */
2608 if (vspltis_constant (op, step, copies))
2614 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2615 result is OP. Abort if it is not possible. */
2618 gen_easy_altivec_constant (rtx op)
2620 enum machine_mode mode = GET_MODE (op);
2621 int nunits = GET_MODE_NUNITS (mode);
2622 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2623 unsigned step = nunits / 4;
2624 unsigned copies = 1;
2626 /* Start with a vspltisw. */
2627 if (vspltis_constant (op, step, copies))
2628 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2630 /* Then try with a vspltish. */
2636 if (vspltis_constant (op, step, copies))
2637 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2639 /* And finally a vspltisb. */
2645 if (vspltis_constant (op, step, copies))
2646 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2652 output_vec_const_move (rtx *operands)
2655 enum machine_mode mode;
2660 mode = GET_MODE (dest);
2665 if (zero_constant (vec, mode))
2666 return "vxor %0,%0,%0";
2668 splat_vec = gen_easy_altivec_constant (vec);
2669 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2670 operands[1] = XEXP (splat_vec, 0);
2671 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2674 switch (GET_MODE (splat_vec))
2677 return "vspltisw %0,%1";
2680 return "vspltish %0,%1";
2683 return "vspltisb %0,%1";
2690 gcc_assert (TARGET_SPE);
2692 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2693 pattern of V1DI, V4HI, and V2SF.
2695 FIXME: We should probably return # and add post reload
2696 splitters for these, but this way is so easy ;-). */
2697 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2698 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2699 operands[1] = CONST_VECTOR_ELT (vec, 0);
2700 operands[2] = CONST_VECTOR_ELT (vec, 1);
2702 return "li %0,%1\n\tevmergelo %0,%0,%0";
2704 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2707 /* Initialize vector TARGET to VALS. */
2710 rs6000_expand_vector_init (rtx target, rtx vals)
2712 enum machine_mode mode = GET_MODE (target);
2713 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2714 int n_elts = GET_MODE_NUNITS (mode);
2715 int n_var = 0, one_var = -1;
2716 bool all_same = true, all_const_zero = true;
2720 for (i = 0; i < n_elts; ++i)
2722 x = XVECEXP (vals, 0, i);
2723 if (!CONSTANT_P (x))
2724 ++n_var, one_var = i;
2725 else if (x != CONST0_RTX (inner_mode))
2726 all_const_zero = false;
2728 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2734 if (mode != V4SFmode && all_const_zero)
2736 /* Zero register. */
2737 emit_insn (gen_rtx_SET (VOIDmode, target,
2738 gen_rtx_XOR (mode, target, target)));
2741 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2743 /* Splat immediate. */
2744 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2748 ; /* Splat vector element. */
2751 /* Load from constant pool. */
2752 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2757 /* Store value to stack temp. Load vector element. Splat. */
2760 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2761 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2762 XVECEXP (vals, 0, 0));
2763 x = gen_rtx_UNSPEC (VOIDmode,
2764 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2765 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2767 gen_rtx_SET (VOIDmode,
2770 x = gen_rtx_VEC_SELECT (inner_mode, target,
2771 gen_rtx_PARALLEL (VOIDmode,
2772 gen_rtvec (1, const0_rtx)));
2773 emit_insn (gen_rtx_SET (VOIDmode, target,
2774 gen_rtx_VEC_DUPLICATE (mode, x)));
2778 /* One field is non-constant. Load constant then overwrite
2782 rtx copy = copy_rtx (vals);
2784 /* Load constant part of vector, substitute neighboring value for
2786 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2787 rs6000_expand_vector_init (target, copy);
2789 /* Insert variable. */
2790 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2794 /* Construct the vector in memory one field at a time
2795 and load the whole vector. */
2796 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2797 for (i = 0; i < n_elts; i++)
2798 emit_move_insn (adjust_address_nv (mem, inner_mode,
2799 i * GET_MODE_SIZE (inner_mode)),
2800 XVECEXP (vals, 0, i));
2801 emit_move_insn (target, mem);
2804 /* Set field ELT of TARGET to VAL. */
2807 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2809 enum machine_mode mode = GET_MODE (target);
2810 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2811 rtx reg = gen_reg_rtx (mode);
2813 int width = GET_MODE_SIZE (inner_mode);
2816 /* Load single variable value. */
2817 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2818 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2819 x = gen_rtx_UNSPEC (VOIDmode,
2820 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2821 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2823 gen_rtx_SET (VOIDmode,
2827 /* Linear sequence. */
2828 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2829 for (i = 0; i < 16; ++i)
2830 XVECEXP (mask, 0, i) = GEN_INT (i);
2832 /* Set permute mask to insert element into target. */
2833 for (i = 0; i < width; ++i)
2834 XVECEXP (mask, 0, elt*width + i)
2835 = GEN_INT (i + 0x10);
2836 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2837 x = gen_rtx_UNSPEC (mode,
2838 gen_rtvec (3, target, reg,
2839 force_reg (V16QImode, x)),
2841 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2844 /* Extract field ELT from VEC into TARGET. */
2847 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2849 enum machine_mode mode = GET_MODE (vec);
2850 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2853 /* Allocate mode-sized buffer. */
2854 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2856 /* Add offset to field within buffer matching vector element. */
2857 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2859 /* Store single field into mode-sized buffer. */
2860 x = gen_rtx_UNSPEC (VOIDmode,
2861 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2862 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2864 gen_rtx_SET (VOIDmode,
2867 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2870 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2871 implement ANDing by the mask IN. */
2873 build_mask64_2_operands (rtx in, rtx *out)
2875 #if HOST_BITS_PER_WIDE_INT >= 64
2876 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2879 gcc_assert (GET_CODE (in) == CONST_INT);
2884 /* Assume c initially something like 0x00fff000000fffff. The idea
2885 is to rotate the word so that the middle ^^^^^^ group of zeros
2886 is at the MS end and can be cleared with an rldicl mask. We then
2887 rotate back and clear off the MS ^^ group of zeros with a
2889 c = ~c; /* c == 0xff000ffffff00000 */
2890 lsb = c & -c; /* lsb == 0x0000000000100000 */
2891 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2892 c = ~c; /* c == 0x00fff000000fffff */
2893 c &= -lsb; /* c == 0x00fff00000000000 */
2894 lsb = c & -c; /* lsb == 0x0000100000000000 */
2895 c = ~c; /* c == 0xff000fffffffffff */
2896 c &= -lsb; /* c == 0xff00000000000000 */
2898 while ((lsb >>= 1) != 0)
2899 shift++; /* shift == 44 on exit from loop */
2900 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2901 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2902 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2906 /* Assume c initially something like 0xff000f0000000000. The idea
2907 is to rotate the word so that the ^^^ middle group of zeros
2908 is at the LS end and can be cleared with an rldicr mask. We then
2909 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2911 lsb = c & -c; /* lsb == 0x0000010000000000 */
2912 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2913 c = ~c; /* c == 0x00fff0ffffffffff */
2914 c &= -lsb; /* c == 0x00fff00000000000 */
2915 lsb = c & -c; /* lsb == 0x0000100000000000 */
2916 c = ~c; /* c == 0xff000fffffffffff */
2917 c &= -lsb; /* c == 0xff00000000000000 */
2919 while ((lsb >>= 1) != 0)
2920 shift++; /* shift == 44 on exit from loop */
2921 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2922 m1 >>= shift; /* m1 == 0x0000000000000fff */
2923 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2926 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2927 masks will be all 1's. We are guaranteed more than one transition. */
2928 out[0] = GEN_INT (64 - shift);
2929 out[1] = GEN_INT (m1);
2930 out[2] = GEN_INT (shift);
2931 out[3] = GEN_INT (m2);
2939 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2942 invalid_e500_subreg (rtx op, enum machine_mode mode)
2944 if (TARGET_E500_DOUBLE)
2946 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
2947 subreg:TI and reg:TF. */
2948 if (GET_CODE (op) == SUBREG
2949 && (mode == SImode || mode == DImode || mode == TImode)
2950 && REG_P (SUBREG_REG (op))
2951 && (GET_MODE (SUBREG_REG (op)) == DFmode
2952 || GET_MODE (SUBREG_REG (op)) == TFmode))
2955 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
2957 if (GET_CODE (op) == SUBREG
2958 && (mode == DFmode || mode == TFmode)
2959 && REG_P (SUBREG_REG (op))
2960 && (GET_MODE (SUBREG_REG (op)) == DImode
2961 || GET_MODE (SUBREG_REG (op)) == TImode))
2966 && GET_CODE (op) == SUBREG
2968 && REG_P (SUBREG_REG (op))
2969 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2975 /* AIX increases natural record alignment to doubleword if the first
2976 field is an FP double while the FP fields remain word aligned. */
2979 rs6000_special_round_type_align (tree type, unsigned int computed,
2980 unsigned int specified)
2982 unsigned int align = MAX (computed, specified);
2983 tree field = TYPE_FIELDS (type);
2985 /* Skip all non field decls */
2986 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2987 field = TREE_CHAIN (field);
2989 if (field != NULL && field != type)
2991 type = TREE_TYPE (field);
2992 while (TREE_CODE (type) == ARRAY_TYPE)
2993 type = TREE_TYPE (type);
2995 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2996 align = MAX (align, 64);
3002 /* Darwin increases record alignment to the natural alignment of
3006 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
3007 unsigned int specified)
3009 unsigned int align = MAX (computed, specified);
3011 if (TYPE_PACKED (type))
3014 /* Find the first field, looking down into aggregates. */
3016 tree field = TYPE_FIELDS (type);
3017 /* Skip all non field decls */
3018 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3019 field = TREE_CHAIN (field);
3022 type = TREE_TYPE (field);
3023 while (TREE_CODE (type) == ARRAY_TYPE)
3024 type = TREE_TYPE (type);
3025 } while (AGGREGATE_TYPE_P (type));
3027 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
3028 align = MAX (align, TYPE_ALIGN (type));
3033 /* Return 1 for an operand in small memory on V.4/eabi. */
3036 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3037 enum machine_mode mode ATTRIBUTE_UNUSED)
3042 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3045 if (DEFAULT_ABI != ABI_V4)
3048 if (GET_CODE (op) == SYMBOL_REF)
3051 else if (GET_CODE (op) != CONST
3052 || GET_CODE (XEXP (op, 0)) != PLUS
3053 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3054 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3059 rtx sum = XEXP (op, 0);
3060 HOST_WIDE_INT summand;
3062 /* We have to be careful here, because it is the referenced address
3063 that must be 32k from _SDA_BASE_, not just the symbol. */
3064 summand = INTVAL (XEXP (sum, 1));
3065 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3068 sym_ref = XEXP (sum, 0);
3071 return SYMBOL_REF_SMALL_P (sym_ref);
3077 /* Return true if either operand is a general purpose register. */
3080 gpr_or_gpr_p (rtx op0, rtx op1)
3082 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3083 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3087 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3090 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3092 switch (GET_CODE (op))
3095 if (RS6000_SYMBOL_REF_TLS_P (op))
3097 else if (CONSTANT_POOL_ADDRESS_P (op))
3099 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3107 else if (! strcmp (XSTR (op, 0), toc_label_name))
3116 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3117 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3119 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3128 constant_pool_expr_p (rtx op)
3132 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3136 toc_relative_expr_p (rtx op)
3140 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3144 legitimate_constant_pool_address_p (rtx x)
3147 && GET_CODE (x) == PLUS
3148 && GET_CODE (XEXP (x, 0)) == REG
3149 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3150 && constant_pool_expr_p (XEXP (x, 1)));
3154 legitimate_small_data_p (enum machine_mode mode, rtx x)
3156 return (DEFAULT_ABI == ABI_V4
3157 && !flag_pic && !TARGET_TOC
3158 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3159 && small_data_operand (x, mode));
3162 /* SPE offset addressing is limited to 5-bits worth of double words. */
3163 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3166 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3168 unsigned HOST_WIDE_INT offset, extra;
3170 if (GET_CODE (x) != PLUS)
3172 if (GET_CODE (XEXP (x, 0)) != REG)
3174 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3176 if (legitimate_constant_pool_address_p (x))
3178 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3181 offset = INTVAL (XEXP (x, 1));
3189 /* AltiVec vector modes. Only reg+reg addressing is valid and
3190 constant offset zero should not occur due to canonicalization.
3191 Allow any offset when not strict before reload. */
3198 /* SPE vector modes. */
3199 return SPE_CONST_OFFSET_OK (offset);
3203 if (TARGET_E500_DOUBLE)
3204 return SPE_CONST_OFFSET_OK (offset);
3207 /* On e500v2, we may have:
3209 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3211 Which gets addressed with evldd instructions. */
3212 if (TARGET_E500_DOUBLE)
3213 return SPE_CONST_OFFSET_OK (offset);
3215 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3217 else if (offset & 3)
3222 if (TARGET_E500_DOUBLE)
3223 return (SPE_CONST_OFFSET_OK (offset)
3224 && SPE_CONST_OFFSET_OK (offset + 8));
3228 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3230 else if (offset & 3)
3241 return (offset < 0x10000) && (offset + extra < 0x10000);
3245 legitimate_indexed_address_p (rtx x, int strict)
3249 if (GET_CODE (x) != PLUS)
3255 /* Recognize the rtl generated by reload which we know will later be
3256 replaced with proper base and index regs. */
3258 && reload_in_progress
3259 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3263 return (REG_P (op0) && REG_P (op1)
3264 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3265 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3266 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3267 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3271 legitimate_indirect_address_p (rtx x, int strict)
3273 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3277 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3279 if (!TARGET_MACHO || !flag_pic
3280 || mode != SImode || GET_CODE (x) != MEM)
3284 if (GET_CODE (x) != LO_SUM)
3286 if (GET_CODE (XEXP (x, 0)) != REG)
3288 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3292 return CONSTANT_P (x);
3296 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3298 if (GET_CODE (x) != LO_SUM)
3300 if (GET_CODE (XEXP (x, 0)) != REG)
3302 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3304 /* Restrict addressing for DI because of our SUBREG hackery. */
3305 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3310 if (TARGET_ELF || TARGET_MACHO)
3312 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3316 if (GET_MODE_NUNITS (mode) != 1)
3318 if (GET_MODE_BITSIZE (mode) > 64
3319 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3320 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3323 return CONSTANT_P (x);
3330 /* Try machine-dependent ways of modifying an illegitimate address
3331 to be legitimate. If we find one, return the new, valid address.
3332 This is used from only one place: `memory_address' in explow.c.
3334 OLDX is the address as it was before break_out_memory_refs was
3335 called. In some cases it is useful to look at this to decide what
3338 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3340 It is always safe for this function to do nothing. It exists to
3341 recognize opportunities to optimize the output.
3343 On RS/6000, first check for the sum of a register with a constant
3344 integer that is out of range. If so, generate code to add the
3345 constant with the low-order 16 bits masked to the register and force
3346 this result into another register (this can be done with `cau').
3347 Then generate an address of REG+(CONST&0xffff), allowing for the
3348 possibility of bit 16 being a one.
3350 Then check for the sum of a register and something not constant, try to
3351 load the other things into a register and return the sum. */
3354 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3355 enum machine_mode mode)
3357 if (GET_CODE (x) == SYMBOL_REF)
3359 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3361 return rs6000_legitimize_tls_address (x, model);
3364 if (GET_CODE (x) == PLUS
3365 && GET_CODE (XEXP (x, 0)) == REG
3366 && GET_CODE (XEXP (x, 1)) == CONST_INT
3367 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3369 HOST_WIDE_INT high_int, low_int;
3371 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3372 high_int = INTVAL (XEXP (x, 1)) - low_int;
3373 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3374 GEN_INT (high_int)), 0);
3375 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3377 else if (GET_CODE (x) == PLUS
3378 && GET_CODE (XEXP (x, 0)) == REG
3379 && GET_CODE (XEXP (x, 1)) != CONST_INT
3380 && GET_MODE_NUNITS (mode) == 1
3381 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3383 || (((mode != DImode && mode != DFmode && mode != DDmode)
3384 || TARGET_E500_DOUBLE)
3385 && mode != TFmode && mode != TDmode))
3386 && (TARGET_POWERPC64 || mode != DImode)
3389 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3390 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3392 else if (ALTIVEC_VECTOR_MODE (mode))
3396 /* Make sure both operands are registers. */
3397 if (GET_CODE (x) == PLUS)
3398 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3399 force_reg (Pmode, XEXP (x, 1)));
3401 reg = force_reg (Pmode, x);
3404 else if (SPE_VECTOR_MODE (mode)
3405 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3406 || mode == DDmode || mode == TDmode
3407 || mode == DImode)))
3411 /* We accept [reg + reg] and [reg + OFFSET]. */
3413 if (GET_CODE (x) == PLUS)
3415 rtx op1 = XEXP (x, 0);
3416 rtx op2 = XEXP (x, 1);
3418 op1 = force_reg (Pmode, op1);
3420 if (GET_CODE (op2) != REG
3421 && (GET_CODE (op2) != CONST_INT
3422 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3423 op2 = force_reg (Pmode, op2);
3425 return gen_rtx_PLUS (Pmode, op1, op2);
3428 return force_reg (Pmode, x);
3434 && GET_CODE (x) != CONST_INT
3435 && GET_CODE (x) != CONST_DOUBLE
3437 && GET_MODE_NUNITS (mode) == 1
3438 && (GET_MODE_BITSIZE (mode) <= 32
3439 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3441 rtx reg = gen_reg_rtx (Pmode);
3442 emit_insn (gen_elf_high (reg, x));
3443 return gen_rtx_LO_SUM (Pmode, reg, x);
3445 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3448 && ! MACHO_DYNAMIC_NO_PIC_P
3450 && GET_CODE (x) != CONST_INT
3451 && GET_CODE (x) != CONST_DOUBLE
3453 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3457 rtx reg = gen_reg_rtx (Pmode);
3458 emit_insn (gen_macho_high (reg, x));
3459 return gen_rtx_LO_SUM (Pmode, reg, x);
3462 && constant_pool_expr_p (x)
3463 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3465 return create_TOC_reference (x);
3471 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3472 We need to emit DTP-relative relocations. */
3475 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3480 fputs ("\t.long\t", file);
3483 fputs (DOUBLE_INT_ASM_OP, file);
3488 output_addr_const (file, x);
3489 fputs ("@dtprel+0x8000", file);
3492 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3494 static GTY(()) rtx rs6000_tls_symbol;
3496 rs6000_tls_get_addr (void)
3498 if (!rs6000_tls_symbol)
3499 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3501 return rs6000_tls_symbol;
3504 /* Construct the SYMBOL_REF for TLS GOT references. */
3506 static GTY(()) rtx rs6000_got_symbol;
3508 rs6000_got_sym (void)
3510 if (!rs6000_got_symbol)
3512 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3513 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3514 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3517 return rs6000_got_symbol;
3520 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3521 this (thread-local) address. */
3524 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3528 dest = gen_reg_rtx (Pmode);
3529 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3535 tlsreg = gen_rtx_REG (Pmode, 13);
3536 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3540 tlsreg = gen_rtx_REG (Pmode, 2);
3541 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3545 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3549 tmp = gen_reg_rtx (Pmode);
3552 tlsreg = gen_rtx_REG (Pmode, 13);
3553 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3557 tlsreg = gen_rtx_REG (Pmode, 2);
3558 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3562 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3564 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3569 rtx r3, got, tga, tmp1, tmp2, eqv;
3571 /* We currently use relocations like @got@tlsgd for tls, which
3572 means the linker will handle allocation of tls entries, placing
3573 them in the .got section. So use a pointer to the .got section,
3574 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3575 or to secondary GOT sections used by 32-bit -fPIC. */
3577 got = gen_rtx_REG (Pmode, 2);
3581 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3584 rtx gsym = rs6000_got_sym ();
3585 got = gen_reg_rtx (Pmode);
3587 rs6000_emit_move (got, gsym, Pmode);
3593 tmp1 = gen_reg_rtx (Pmode);
3594 tmp2 = gen_reg_rtx (Pmode);
3595 tmp3 = gen_reg_rtx (Pmode);
3596 mem = gen_const_mem (Pmode, tmp1);
3598 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3599 emit_move_insn (tmp1,
3600 gen_rtx_REG (Pmode, LR_REGNO));
3601 emit_move_insn (tmp2, mem);
3602 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3603 last = emit_move_insn (got, tmp3);
3604 set_unique_reg_note (last, REG_EQUAL, gsym);
3605 maybe_encapsulate_block (first, last, gsym);
3610 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3612 r3 = gen_rtx_REG (Pmode, 3);
3614 insn = gen_tls_gd_64 (r3, got, addr);
3616 insn = gen_tls_gd_32 (r3, got, addr);
3619 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3620 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3621 insn = emit_call_insn (insn);
3622 CONST_OR_PURE_CALL_P (insn) = 1;
3623 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3624 insn = get_insns ();
3626 emit_libcall_block (insn, dest, r3, addr);
3628 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3630 r3 = gen_rtx_REG (Pmode, 3);
3632 insn = gen_tls_ld_64 (r3, got);
3634 insn = gen_tls_ld_32 (r3, got);
3637 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3638 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3639 insn = emit_call_insn (insn);
3640 CONST_OR_PURE_CALL_P (insn) = 1;
3641 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3642 insn = get_insns ();
3644 tmp1 = gen_reg_rtx (Pmode);
3645 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3647 emit_libcall_block (insn, tmp1, r3, eqv);
3648 if (rs6000_tls_size == 16)
3651 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3653 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3655 else if (rs6000_tls_size == 32)
3657 tmp2 = gen_reg_rtx (Pmode);
3659 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3661 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3664 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3666 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3670 tmp2 = gen_reg_rtx (Pmode);
3672 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3674 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3676 insn = gen_rtx_SET (Pmode, dest,
3677 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3683 /* IE, or 64-bit offset LE. */
3684 tmp2 = gen_reg_rtx (Pmode);
3686 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3688 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3691 insn = gen_tls_tls_64 (dest, tmp2, addr);
3693 insn = gen_tls_tls_32 (dest, tmp2, addr);
3701 /* Return 1 if X contains a thread-local symbol. */
3704 rs6000_tls_referenced_p (rtx x)
3706 if (! TARGET_HAVE_TLS)
3709 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3712 /* Return 1 if *X is a thread-local symbol. This is the same as
3713 rs6000_tls_symbol_ref except for the type of the unused argument. */
3716 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3718 return RS6000_SYMBOL_REF_TLS_P (*x);
3721 /* The convention appears to be to define this wherever it is used.
3722 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3723 is now used here. */
3724 #ifndef REG_MODE_OK_FOR_BASE_P
3725 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3728 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3729 replace the input X, or the original X if no replacement is called for.
3730 The output parameter *WIN is 1 if the calling macro should goto WIN,
3733 For RS/6000, we wish to handle large displacements off a base
3734 register by splitting the addend across an addiu/addis and the mem insn.
3735 This cuts number of extra insns needed from 3 to 1.
3737 On Darwin, we use this to generate code for floating point constants.
3738 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3739 The Darwin code is inside #if TARGET_MACHO because only then is
3740 machopic_function_base_name() defined. */
3742 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3743 int opnum, int type,
3744 int ind_levels ATTRIBUTE_UNUSED, int *win)
3746 /* We must recognize output that we have already generated ourselves. */
3747 if (GET_CODE (x) == PLUS
3748 && GET_CODE (XEXP (x, 0)) == PLUS
3749 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3750 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3751 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3753 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3754 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3755 opnum, (enum reload_type)type);
3761 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3762 && GET_CODE (x) == LO_SUM
3763 && GET_CODE (XEXP (x, 0)) == PLUS
3764 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3765 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3766 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3767 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3768 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3769 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3770 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3772 /* Result of previous invocation of this function on Darwin
3773 floating point constant. */
3774 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3775 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3776 opnum, (enum reload_type)type);
3782 /* Force ld/std non-word aligned offset into base register by wrapping
3784 if (GET_CODE (x) == PLUS
3785 && GET_CODE (XEXP (x, 0)) == REG
3786 && REGNO (XEXP (x, 0)) < 32
3787 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3788 && GET_CODE (XEXP (x, 1)) == CONST_INT
3789 && (INTVAL (XEXP (x, 1)) & 3) != 0
3790 && !ALTIVEC_VECTOR_MODE (mode)
3791 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3792 && TARGET_POWERPC64)
3794 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3795 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3796 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3797 opnum, (enum reload_type) type);
3802 if (GET_CODE (x) == PLUS
3803 && GET_CODE (XEXP (x, 0)) == REG
3804 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3805 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3806 && GET_CODE (XEXP (x, 1)) == CONST_INT
3807 && !SPE_VECTOR_MODE (mode)
3808 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3810 && !ALTIVEC_VECTOR_MODE (mode))
3812 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3813 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3815 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3817 /* Check for 32-bit overflow. */
3818 if (high + low != val)
3824 /* Reload the high part into a base reg; leave the low part
3825 in the mem directly. */
3827 x = gen_rtx_PLUS (GET_MODE (x),
3828 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3832 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3833 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3834 opnum, (enum reload_type)type);
3839 if (GET_CODE (x) == SYMBOL_REF
3840 && !ALTIVEC_VECTOR_MODE (mode)
3841 && !SPE_VECTOR_MODE (mode)
3843 && DEFAULT_ABI == ABI_DARWIN
3844 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3846 && DEFAULT_ABI == ABI_V4
3849 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
3850 The same goes for DImode without 64-bit gprs and DFmode
3854 && (mode != DImode || TARGET_POWERPC64)
3855 && (mode != DFmode || TARGET_POWERPC64
3856 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3861 rtx offset = gen_rtx_CONST (Pmode,
3862 gen_rtx_MINUS (Pmode, x,
3863 machopic_function_base_sym ()));
3864 x = gen_rtx_LO_SUM (GET_MODE (x),
3865 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3866 gen_rtx_HIGH (Pmode, offset)), offset);
3870 x = gen_rtx_LO_SUM (GET_MODE (x),
3871 gen_rtx_HIGH (Pmode, x), x);
3873 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3874 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3875 opnum, (enum reload_type)type);
3880 /* Reload an offset address wrapped by an AND that represents the
3881 masking of the lower bits. Strip the outer AND and let reload
3882 convert the offset address into an indirect address. */
3884 && ALTIVEC_VECTOR_MODE (mode)
3885 && GET_CODE (x) == AND
3886 && GET_CODE (XEXP (x, 0)) == PLUS
3887 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3888 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3889 && GET_CODE (XEXP (x, 1)) == CONST_INT
3890 && INTVAL (XEXP (x, 1)) == -16)
3898 && constant_pool_expr_p (x)
3899 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3901 x = create_TOC_reference (x);
3909 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3910 that is a valid memory address for an instruction.
3911 The MODE argument is the machine mode for the MEM expression
3912 that wants to use this address.
3914 On the RS/6000, there are four valid address: a SYMBOL_REF that
3915 refers to a constant pool entry of an address (or the sum of it
3916 plus a constant), a short (16-bit signed) constant plus a register,
3917 the sum of two registers, or a register indirect, possibly with an
3918 auto-increment. For DFmode and DImode with a constant plus register,
3919 we must ensure that both words are addressable or PowerPC64 with offset
3922 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3923 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
3924 because adjacent memory cells are accessed by adding word-sized offsets
3925 during assembly output. */
3927 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3929 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3931 && ALTIVEC_VECTOR_MODE (mode)
3932 && GET_CODE (x) == AND
3933 && GET_CODE (XEXP (x, 1)) == CONST_INT
3934 && INTVAL (XEXP (x, 1)) == -16)
3937 if (RS6000_SYMBOL_REF_TLS_P (x))
3939 if (legitimate_indirect_address_p (x, reg_ok_strict))
3941 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3942 && !ALTIVEC_VECTOR_MODE (mode)
3943 && !SPE_VECTOR_MODE (mode)
3946 /* Restrict addressing for DI because of our SUBREG hackery. */
3947 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3950 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3952 if (legitimate_small_data_p (mode, x))
3954 if (legitimate_constant_pool_address_p (x))
3956 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3958 && GET_CODE (x) == PLUS
3959 && GET_CODE (XEXP (x, 0)) == REG
3960 && (XEXP (x, 0) == virtual_stack_vars_rtx
3961 || XEXP (x, 0) == arg_pointer_rtx)
3962 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3964 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3969 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3971 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3972 && (TARGET_POWERPC64 || mode != DImode)
3973 && legitimate_indexed_address_p (x, reg_ok_strict))
3975 if (GET_CODE (x) == PRE_MODIFY
3979 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3981 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3982 && (TARGET_POWERPC64 || mode != DImode)
3983 && !ALTIVEC_VECTOR_MODE (mode)
3984 && !SPE_VECTOR_MODE (mode)
3985 /* Restrict addressing for DI because of our SUBREG hackery. */
3986 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3988 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
3989 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
3990 || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
3991 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3993 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3998 /* Go to LABEL if ADDR (a legitimate address expression)
3999 has an effect that depends on the machine mode it is used for.
4001 On the RS/6000 this is true of all integral offsets (since AltiVec
4002 modes don't allow them) or is a pre-increment or decrement.
4004 ??? Except that due to conceptual problems in offsettable_address_p
4005 we can't really report the problems of integral offsets. So leave
4006 this assuming that the adjustable offset must be valid for the
4007 sub-words of a TFmode operand, which is what we had before. */
4010 rs6000_mode_dependent_address (rtx addr)
4012 switch (GET_CODE (addr))
4015 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4017 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
4018 return val + 12 + 0x8000 >= 0x10000;
4028 return TARGET_UPDATE;
4037 /* More elaborate version of recog's offsettable_memref_p predicate
4038 that works around the ??? note of rs6000_mode_dependent_address.
4039 In particular it accepts
4041 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4043 in 32-bit mode, that the recog predicate rejects. */
4046 rs6000_offsettable_memref_p (rtx op)
4051 /* First mimic offsettable_memref_p. */
4052 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
4055 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4056 the latter predicate knows nothing about the mode of the memory
4057 reference and, therefore, assumes that it is the largest supported
4058 mode (TFmode). As a consequence, legitimate offsettable memory
4059 references are rejected. rs6000_legitimate_offset_address_p contains
4060 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4061 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
4064 /* Return number of consecutive hard regs needed starting at reg REGNO
4065 to hold something of mode MODE.
4066 This is ordinarily the length in words of a value of mode MODE
4067 but can be less for certain modes in special long registers.
4069 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4070 scalar instructions. The upper 32 bits are only available to the
4073 POWER and PowerPC GPRs hold 32 bits worth;
4074 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4077 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4079 if (FP_REGNO_P (regno))
4080 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4082 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4083 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4085 if (ALTIVEC_REGNO_P (regno))
4087 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4089 /* The value returned for SCmode in the E500 double case is 2 for
4090 ABI compatibility; storing an SCmode value in a single register
4091 would require function_arg and rs6000_spe_function_arg to handle
4092 SCmode so as to pass the value correctly in a pair of
4094 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
4095 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4097 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4100 /* Change register usage conditional on target flags. */
4102 rs6000_conditional_register_usage (void)
4106 /* Set MQ register fixed (already call_used) if not POWER
4107 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4112 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4114 fixed_regs[13] = call_used_regs[13]
4115 = call_really_used_regs[13] = 1;
4117 /* Conditionally disable FPRs. */
4118 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4119 for (i = 32; i < 64; i++)
4120 fixed_regs[i] = call_used_regs[i]
4121 = call_really_used_regs[i] = 1;
4123 /* The TOC register is not killed across calls in a way that is
4124 visible to the compiler. */
4125 if (DEFAULT_ABI == ABI_AIX)
4126 call_really_used_regs[2] = 0;
4128 if (DEFAULT_ABI == ABI_V4
4129 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4131 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4133 if (DEFAULT_ABI == ABI_V4
4134 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4136 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4137 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4138 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4140 if (DEFAULT_ABI == ABI_DARWIN
4141 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4142 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4143 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4144 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4146 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4147 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4148 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4151 global_regs[VSCR_REGNO] = 1;
4155 global_regs[SPEFSCR_REGNO] = 1;
4156 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4157 registers in prologues and epilogues. We no longer use r14
4158 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4159 pool for link-compatibility with older versions of GCC. Once
4160 "old" code has died out, we can return r14 to the allocation
4163 = call_used_regs[14]
4164 = call_really_used_regs[14] = 1;
4167 if (! TARGET_ALTIVEC)
4169 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4170 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4171 call_really_used_regs[VRSAVE_REGNO] = 1;
4174 if (TARGET_ALTIVEC_ABI)
4175 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4176 call_used_regs[i] = call_really_used_regs[i] = 1;
4179 /* Try to output insns to set TARGET equal to the constant C if it can
4180 be done in less than N insns. Do all computations in MODE.
4181 Returns the place where the output has been placed if it can be
4182 done and the insns have been emitted. If it would take more than N
4183 insns, zero is returned and no insns and emitted. */
4186 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4187 rtx source, int n ATTRIBUTE_UNUSED)
4189 rtx result, insn, set;
4190 HOST_WIDE_INT c0, c1;
4197 dest = gen_reg_rtx (mode);
4198 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4202 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4204 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4205 GEN_INT (INTVAL (source)
4206 & (~ (HOST_WIDE_INT) 0xffff))));
4207 emit_insn (gen_rtx_SET (VOIDmode, dest,
4208 gen_rtx_IOR (SImode, copy_rtx (result),
4209 GEN_INT (INTVAL (source) & 0xffff))));
4214 switch (GET_CODE (source))
4217 c0 = INTVAL (source);
4222 #if HOST_BITS_PER_WIDE_INT >= 64
4223 c0 = CONST_DOUBLE_LOW (source);
4226 c0 = CONST_DOUBLE_LOW (source);
4227 c1 = CONST_DOUBLE_HIGH (source);
4235 result = rs6000_emit_set_long_const (dest, c0, c1);
4242 insn = get_last_insn ();
4243 set = single_set (insn);
4244 if (! CONSTANT_P (SET_SRC (set)))
4245 set_unique_reg_note (insn, REG_EQUAL, source);
4250 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4251 fall back to a straight forward decomposition. We do this to avoid
4252 exponential run times encountered when looking for longer sequences
4253 with rs6000_emit_set_const. */
4255 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4257 if (!TARGET_POWERPC64)
4259 rtx operand1, operand2;
4261 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4263 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4265 emit_move_insn (operand1, GEN_INT (c1));
4266 emit_move_insn (operand2, GEN_INT (c2));
4270 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4273 ud2 = (c1 & 0xffff0000) >> 16;
4274 #if HOST_BITS_PER_WIDE_INT >= 64
4278 ud4 = (c2 & 0xffff0000) >> 16;
4280 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4281 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4284 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4286 emit_move_insn (dest, GEN_INT (ud1));
4289 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4290 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4293 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4296 emit_move_insn (dest, GEN_INT (ud2 << 16));
4298 emit_move_insn (copy_rtx (dest),
4299 gen_rtx_IOR (DImode, copy_rtx (dest),
4302 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4303 || (ud4 == 0 && ! (ud3 & 0x8000)))
4306 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4309 emit_move_insn (dest, GEN_INT (ud3 << 16));
4312 emit_move_insn (copy_rtx (dest),
4313 gen_rtx_IOR (DImode, copy_rtx (dest),
4315 emit_move_insn (copy_rtx (dest),
4316 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4319 emit_move_insn (copy_rtx (dest),
4320 gen_rtx_IOR (DImode, copy_rtx (dest),
4326 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4329 emit_move_insn (dest, GEN_INT (ud4 << 16));
4332 emit_move_insn (copy_rtx (dest),
4333 gen_rtx_IOR (DImode, copy_rtx (dest),
4336 emit_move_insn (copy_rtx (dest),
4337 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4340 emit_move_insn (copy_rtx (dest),
4341 gen_rtx_IOR (DImode, copy_rtx (dest),
4342 GEN_INT (ud2 << 16)));
4344 emit_move_insn (copy_rtx (dest),
4345 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4351 /* Helper for the following. Get rid of [r+r] memory refs
4352 in cases where it won't work (TImode, TFmode, TDmode). */
4355 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4357 if (GET_CODE (operands[0]) == MEM
4358 && GET_CODE (XEXP (operands[0], 0)) != REG
4359 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4360 && ! reload_in_progress)
4362 = replace_equiv_address (operands[0],
4363 copy_addr_to_reg (XEXP (operands[0], 0)));
4365 if (GET_CODE (operands[1]) == MEM
4366 && GET_CODE (XEXP (operands[1], 0)) != REG
4367 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4368 && ! reload_in_progress)
4370 = replace_equiv_address (operands[1],
4371 copy_addr_to_reg (XEXP (operands[1], 0)));
4374 /* Emit a move from SOURCE to DEST in mode MODE. */
4376 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4380 operands[1] = source;
4382 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4383 if (GET_CODE (operands[1]) == CONST_DOUBLE
4384 && ! FLOAT_MODE_P (mode)
4385 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4387 /* FIXME. This should never happen. */
4388 /* Since it seems that it does, do the safe thing and convert
4390 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4392 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4393 || FLOAT_MODE_P (mode)
4394 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4395 || CONST_DOUBLE_LOW (operands[1]) < 0)
4396 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4397 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4399 /* Check if GCC is setting up a block move that will end up using FP
4400 registers as temporaries. We must make sure this is acceptable. */
4401 if (GET_CODE (operands[0]) == MEM
4402 && GET_CODE (operands[1]) == MEM
4404 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4405 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4406 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4407 ? 32 : MEM_ALIGN (operands[0])))
4408 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4410 : MEM_ALIGN (operands[1]))))
4411 && ! MEM_VOLATILE_P (operands [0])
4412 && ! MEM_VOLATILE_P (operands [1]))
4414 emit_move_insn (adjust_address (operands[0], SImode, 0),
4415 adjust_address (operands[1], SImode, 0));
4416 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4417 adjust_address (copy_rtx (operands[1]), SImode, 4));
4421 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4422 && !gpc_reg_operand (operands[1], mode))
4423 operands[1] = force_reg (mode, operands[1]);
4425 if (mode == SFmode && ! TARGET_POWERPC
4426 && TARGET_HARD_FLOAT && TARGET_FPRS
4427 && GET_CODE (operands[0]) == MEM)
4431 if (reload_in_progress || reload_completed)
4432 regnum = true_regnum (operands[1]);
4433 else if (GET_CODE (operands[1]) == REG)
4434 regnum = REGNO (operands[1]);
4438 /* If operands[1] is a register, on POWER it may have
4439 double-precision data in it, so truncate it to single
4441 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4444 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4445 : gen_reg_rtx (mode));
4446 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4447 operands[1] = newreg;
4451 /* Recognize the case where operand[1] is a reference to thread-local
4452 data and load its address to a register. */
4453 if (rs6000_tls_referenced_p (operands[1]))
4455 enum tls_model model;
4456 rtx tmp = operands[1];
4459 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4461 addend = XEXP (XEXP (tmp, 0), 1);
4462 tmp = XEXP (XEXP (tmp, 0), 0);
4465 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4466 model = SYMBOL_REF_TLS_MODEL (tmp);
4467 gcc_assert (model != 0);
4469 tmp = rs6000_legitimize_tls_address (tmp, model);
4472 tmp = gen_rtx_PLUS (mode, tmp, addend);
4473 tmp = force_operand (tmp, operands[0]);
4478 /* Handle the case where reload calls us with an invalid address. */
4479 if (reload_in_progress && mode == Pmode
4480 && (! general_operand (operands[1], mode)
4481 || ! nonimmediate_operand (operands[0], mode)))
4484 /* 128-bit constant floating-point values on Darwin should really be
4485 loaded as two parts. */
4486 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4487 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4489 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4490 know how to get a DFmode SUBREG of a TFmode. */
4491 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4492 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4493 simplify_gen_subreg (imode, operands[1], mode, 0),
4495 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4496 GET_MODE_SIZE (imode)),
4497 simplify_gen_subreg (imode, operands[1], mode,
4498 GET_MODE_SIZE (imode)),
4503 /* FIXME: In the long term, this switch statement should go away
4504 and be replaced by a sequence of tests based on things like
4510 if (CONSTANT_P (operands[1])
4511 && GET_CODE (operands[1]) != CONST_INT)
4512 operands[1] = force_const_mem (mode, operands[1]);
4517 rs6000_eliminate_indexed_memrefs (operands);
4523 if (CONSTANT_P (operands[1])
4524 && ! easy_fp_constant (operands[1], mode))
4525 operands[1] = force_const_mem (mode, operands[1]);
4536 if (CONSTANT_P (operands[1])
4537 && !easy_vector_constant (operands[1], mode))
4538 operands[1] = force_const_mem (mode, operands[1]);
4543 /* Use default pattern for address of ELF small data */
4546 && DEFAULT_ABI == ABI_V4
4547 && (GET_CODE (operands[1]) == SYMBOL_REF
4548 || GET_CODE (operands[1]) == CONST)
4549 && small_data_operand (operands[1], mode))
4551 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4555 if (DEFAULT_ABI == ABI_V4
4556 && mode == Pmode && mode == SImode
4557 && flag_pic == 1 && got_operand (operands[1], mode))
4559 emit_insn (gen_movsi_got (operands[0], operands[1]));
4563 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4567 && CONSTANT_P (operands[1])
4568 && GET_CODE (operands[1]) != HIGH
4569 && GET_CODE (operands[1]) != CONST_INT)
4571 rtx target = (!can_create_pseudo_p ()
4573 : gen_reg_rtx (mode));
4575 /* If this is a function address on -mcall-aixdesc,
4576 convert it to the address of the descriptor. */
4577 if (DEFAULT_ABI == ABI_AIX
4578 && GET_CODE (operands[1]) == SYMBOL_REF
4579 && XSTR (operands[1], 0)[0] == '.')
4581 const char *name = XSTR (operands[1], 0);
4583 while (*name == '.')
4585 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4586 CONSTANT_POOL_ADDRESS_P (new_ref)
4587 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4588 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4589 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4590 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4591 operands[1] = new_ref;
4594 if (DEFAULT_ABI == ABI_DARWIN)
4597 if (MACHO_DYNAMIC_NO_PIC_P)
4599 /* Take care of any required data indirection. */
4600 operands[1] = rs6000_machopic_legitimize_pic_address (
4601 operands[1], mode, operands[0]);
4602 if (operands[0] != operands[1])
4603 emit_insn (gen_rtx_SET (VOIDmode,
4604 operands[0], operands[1]));
4608 emit_insn (gen_macho_high (target, operands[1]));
4609 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4613 emit_insn (gen_elf_high (target, operands[1]));
4614 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4618 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4619 and we have put it in the TOC, we just need to make a TOC-relative
4622 && GET_CODE (operands[1]) == SYMBOL_REF
4623 && constant_pool_expr_p (operands[1])
4624 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4625 get_pool_mode (operands[1])))
4627 operands[1] = create_TOC_reference (operands[1]);
4629 else if (mode == Pmode
4630 && CONSTANT_P (operands[1])
4631 && ((GET_CODE (operands[1]) != CONST_INT
4632 && ! easy_fp_constant (operands[1], mode))
4633 || (GET_CODE (operands[1]) == CONST_INT
4634 && num_insns_constant (operands[1], mode) > 2)
4635 || (GET_CODE (operands[0]) == REG
4636 && FP_REGNO_P (REGNO (operands[0]))))
4637 && GET_CODE (operands[1]) != HIGH
4638 && ! legitimate_constant_pool_address_p (operands[1])
4639 && ! toc_relative_expr_p (operands[1]))
4641 /* Emit a USE operation so that the constant isn't deleted if
4642 expensive optimizations are turned on because nobody
4643 references it. This should only be done for operands that
4644 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4645 This should not be done for operands that contain LABEL_REFs.
4646 For now, we just handle the obvious case. */
4647 if (GET_CODE (operands[1]) != LABEL_REF)
4648 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4651 /* Darwin uses a special PIC legitimizer. */
4652 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4655 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4657 if (operands[0] != operands[1])
4658 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4663 /* If we are to limit the number of things we put in the TOC and
4664 this is a symbol plus a constant we can add in one insn,
4665 just put the symbol in the TOC and add the constant. Don't do
4666 this if reload is in progress. */
4667 if (GET_CODE (operands[1]) == CONST
4668 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4669 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4670 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4671 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4672 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4673 && ! side_effects_p (operands[0]))
4676 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4677 rtx other = XEXP (XEXP (operands[1], 0), 1);
4679 sym = force_reg (mode, sym);
4681 emit_insn (gen_addsi3 (operands[0], sym, other));
4683 emit_insn (gen_adddi3 (operands[0], sym, other));
4687 operands[1] = force_const_mem (mode, operands[1]);
4690 && constant_pool_expr_p (XEXP (operands[1], 0))
4691 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4692 get_pool_constant (XEXP (operands[1], 0)),
4693 get_pool_mode (XEXP (operands[1], 0))))
4696 = gen_const_mem (mode,
4697 create_TOC_reference (XEXP (operands[1], 0)));
4698 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4704 rs6000_eliminate_indexed_memrefs (operands);
4708 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4710 gen_rtx_SET (VOIDmode,
4711 operands[0], operands[1]),
4712 gen_rtx_CLOBBER (VOIDmode,
4713 gen_rtx_SCRATCH (SImode)))));
4722 /* Above, we may have called force_const_mem which may have returned
4723 an invalid address. If we can, fix this up; otherwise, reload will
4724 have to deal with it. */
4725 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4726 operands[1] = validize_mem (operands[1]);
4729 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4732 /* Nonzero if we can use a floating-point register to pass this arg. */
4733 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4734 (SCALAR_FLOAT_MODE_P (MODE) \
4735 && (MODE) != SDmode \
4736 && (CUM)->fregno <= FP_ARG_MAX_REG \
4737 && TARGET_HARD_FLOAT && TARGET_FPRS)
4739 /* Nonzero if we can use an AltiVec register to pass this arg. */
4740 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4741 (ALTIVEC_VECTOR_MODE (MODE) \
4742 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4743 && TARGET_ALTIVEC_ABI \
4746 /* Return a nonzero value to say to return the function value in
4747 memory, just as large structures are always returned. TYPE will be
4748 the data type of the value, and FNTYPE will be the type of the
4749 function doing the returning, or @code{NULL} for libcalls.
4751 The AIX ABI for the RS/6000 specifies that all structures are
4752 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4753 specifies that structures <= 8 bytes are returned in r3/r4, but a
4754 draft put them in memory, and GCC used to implement the draft
4755 instead of the final standard. Therefore, aix_struct_return
4756 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4757 compatibility can change DRAFT_V4_STRUCT_RET to override the
4758 default, and -m switches get the final word. See
4759 rs6000_override_options for more details.
4761 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4762 long double support is enabled. These values are returned in memory.
4764 int_size_in_bytes returns -1 for variable size objects, which go in
4765 memory always. The cast to unsigned makes -1 > 8. */
4768 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
4770 /* In the darwin64 abi, try to use registers for larger structs
4772 if (rs6000_darwin64_abi
4773 && TREE_CODE (type) == RECORD_TYPE
4774 && int_size_in_bytes (type) > 0)
4776 CUMULATIVE_ARGS valcum;
4780 valcum.fregno = FP_ARG_MIN_REG;
4781 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4782 /* Do a trial code generation as if this were going to be passed
4783 as an argument; if any part goes in memory, we return NULL. */
4784 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4787 /* Otherwise fall through to more conventional ABI rules. */
4790 if (AGGREGATE_TYPE_P (type)
4791 && (aix_struct_return
4792 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4795 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4796 modes only exist for GCC vector types if -maltivec. */
4797 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4798 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4801 /* Return synthetic vectors in memory. */
4802 if (TREE_CODE (type) == VECTOR_TYPE
4803 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4805 static bool warned_for_return_big_vectors = false;
4806 if (!warned_for_return_big_vectors)
4808 warning (0, "GCC vector returned by reference: "
4809 "non-standard ABI extension with no compatibility guarantee");
4810 warned_for_return_big_vectors = true;
4815 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4821 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4822 for a call to a function whose data type is FNTYPE.
4823 For a library call, FNTYPE is 0.
4825 For incoming args we set the number of arguments in the prototype large
4826 so we never return a PARALLEL. */
4829 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4830 rtx libname ATTRIBUTE_UNUSED, int incoming,
4831 int libcall, int n_named_args)
4833 static CUMULATIVE_ARGS zero_cumulative;
4835 *cum = zero_cumulative;
4837 cum->fregno = FP_ARG_MIN_REG;
4838 cum->vregno = ALTIVEC_ARG_MIN_REG;
4839 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4840 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4841 ? CALL_LIBCALL : CALL_NORMAL);
4842 cum->sysv_gregno = GP_ARG_MIN_REG;
4843 cum->stdarg = fntype
4844 && (TYPE_ARG_TYPES (fntype) != 0
4845 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4846 != void_type_node));
4848 cum->nargs_prototype = 0;
4849 if (incoming || cum->prototype)
4850 cum->nargs_prototype = n_named_args;
4852 /* Check for a longcall attribute. */
4853 if ((!fntype && rs6000_default_long_calls)
4855 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4856 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4857 cum->call_cookie |= CALL_LONG;
4859 if (TARGET_DEBUG_ARG)
4861 fprintf (stderr, "\ninit_cumulative_args:");
4864 tree ret_type = TREE_TYPE (fntype);
4865 fprintf (stderr, " ret code = %s,",
4866 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4869 if (cum->call_cookie & CALL_LONG)
4870 fprintf (stderr, " longcall,");
4872 fprintf (stderr, " proto = %d, nargs = %d\n",
4873 cum->prototype, cum->nargs_prototype);
4878 && TARGET_ALTIVEC_ABI
4879 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4881 error ("cannot return value in vector register because"
4882 " altivec instructions are disabled, use -maltivec"
4887 /* Return true if TYPE must be passed on the stack and not in registers. */
4890 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
4892 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4893 return must_pass_in_stack_var_size (mode, type);
4895 return must_pass_in_stack_var_size_or_pad (mode, type);
4898 /* If defined, a C expression which determines whether, and in which
4899 direction, to pad out an argument with extra space. The value
4900 should be of type `enum direction': either `upward' to pad above
4901 the argument, `downward' to pad below, or `none' to inhibit
4904 For the AIX ABI structs are always stored left shifted in their
4908 function_arg_padding (enum machine_mode mode, const_tree type)
4910 #ifndef AGGREGATE_PADDING_FIXED
4911 #define AGGREGATE_PADDING_FIXED 0
4913 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4914 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4917 if (!AGGREGATE_PADDING_FIXED)
4919 /* GCC used to pass structures of the same size as integer types as
4920 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4921 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4922 passed padded downward, except that -mstrict-align further
4923 muddied the water in that multi-component structures of 2 and 4
4924 bytes in size were passed padded upward.
4926 The following arranges for best compatibility with previous
4927 versions of gcc, but removes the -mstrict-align dependency. */
4928 if (BYTES_BIG_ENDIAN)
4930 HOST_WIDE_INT size = 0;
4932 if (mode == BLKmode)
4934 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4935 size = int_size_in_bytes (type);
4938 size = GET_MODE_SIZE (mode);
4940 if (size == 1 || size == 2 || size == 4)
4946 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4948 if (type != 0 && AGGREGATE_TYPE_P (type))
4952 /* Fall back to the default. */
4953 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4956 /* If defined, a C expression that gives the alignment boundary, in bits,
4957 of an argument with the specified mode and type. If it is not defined,
4958 PARM_BOUNDARY is used for all arguments.
4960 V.4 wants long longs and doubles to be double word aligned. Just
4961 testing the mode size is a boneheaded way to do this as it means
4962 that other types such as complex int are also double word aligned.
4963 However, we're stuck with this because changing the ABI might break
4964 existing library interfaces.
4966 Doubleword align SPE vectors.
4967 Quadword align Altivec vectors.
4968 Quadword align large synthetic vector types. */
4971 function_arg_boundary (enum machine_mode mode, tree type)
4973 if (DEFAULT_ABI == ABI_V4
4974 && (GET_MODE_SIZE (mode) == 8
4975 || (TARGET_HARD_FLOAT
4977 && (mode == TFmode || mode == TDmode))))
4979 else if (SPE_VECTOR_MODE (mode)
4980 || (type && TREE_CODE (type) == VECTOR_TYPE
4981 && int_size_in_bytes (type) >= 8
4982 && int_size_in_bytes (type) < 16))
4984 else if (ALTIVEC_VECTOR_MODE (mode)
4985 || (type && TREE_CODE (type) == VECTOR_TYPE
4986 && int_size_in_bytes (type) >= 16))
4988 else if (rs6000_darwin64_abi && mode == BLKmode
4989 && type && TYPE_ALIGN (type) > 64)
4992 return PARM_BOUNDARY;
4995 /* For a function parm of MODE and TYPE, return the starting word in
4996 the parameter area. NWORDS of the parameter area are already used. */
4999 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
5002 unsigned int parm_offset;
5004 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5005 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
5006 return nwords + (-(parm_offset + nwords) & align);
5009 /* Compute the size (in words) of a function argument. */
5011 static unsigned long
5012 rs6000_arg_size (enum machine_mode mode, tree type)
5016 if (mode != BLKmode)
5017 size = GET_MODE_SIZE (mode);
5019 size = int_size_in_bytes (type);
5022 return (size + 3) >> 2;
5024 return (size + 7) >> 3;
5027 /* Use this to flush pending int fields. */
5030 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
5031 HOST_WIDE_INT bitpos)
5033 unsigned int startbit, endbit;
5034 int intregs, intoffset;
5035 enum machine_mode mode;
5037 if (cum->intoffset == -1)
5040 intoffset = cum->intoffset;
5041 cum->intoffset = -1;
5043 if (intoffset % BITS_PER_WORD != 0)
5045 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5047 if (mode == BLKmode)
5049 /* We couldn't find an appropriate mode, which happens,
5050 e.g., in packed structs when there are 3 bytes to load.
5051 Back intoffset back to the beginning of the word in this
5053 intoffset = intoffset & -BITS_PER_WORD;
5057 startbit = intoffset & -BITS_PER_WORD;
5058 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5059 intregs = (endbit - startbit) / BITS_PER_WORD;
5060 cum->words += intregs;
5063 /* The darwin64 ABI calls for us to recurse down through structs,
5064 looking for elements passed in registers. Unfortunately, we have
5065 to track int register count here also because of misalignments
5066 in powerpc alignment mode. */
5069 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
5071 HOST_WIDE_INT startbitpos)
5075 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5076 if (TREE_CODE (f) == FIELD_DECL)
5078 HOST_WIDE_INT bitpos = startbitpos;
5079 tree ftype = TREE_TYPE (f);
5080 enum machine_mode mode;
5081 if (ftype == error_mark_node)
5083 mode = TYPE_MODE (ftype);
5085 if (DECL_SIZE (f) != 0
5086 && host_integerp (bit_position (f), 1))
5087 bitpos += int_bit_position (f);
5089 /* ??? FIXME: else assume zero offset. */
5091 if (TREE_CODE (ftype) == RECORD_TYPE)
5092 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
5093 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
5095 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5096 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5097 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
5099 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
5101 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5105 else if (cum->intoffset == -1)
5106 cum->intoffset = bitpos;
5110 /* Update the data in CUM to advance over an argument
5111 of mode MODE and data type TYPE.
5112 (TYPE is null for libcalls where that information may not be available.)
5114 Note that for args passed by reference, function_arg will be called
5115 with MODE and TYPE set to that of the pointer to the arg, not the arg
5119 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5120 tree type, int named, int depth)
5124 /* Only tick off an argument if we're not recursing. */
5126 cum->nargs_prototype--;
5128 if (TARGET_ALTIVEC_ABI
5129 && (ALTIVEC_VECTOR_MODE (mode)
5130 || (type && TREE_CODE (type) == VECTOR_TYPE
5131 && int_size_in_bytes (type) == 16)))
5135 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5138 if (!TARGET_ALTIVEC)
5139 error ("cannot pass argument in vector register because"
5140 " altivec instructions are disabled, use -maltivec"
5143 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5144 even if it is going to be passed in a vector register.
5145 Darwin does the same for variable-argument functions. */
5146 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5147 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5157 /* Vector parameters must be 16-byte aligned. This places
5158 them at 2 mod 4 in terms of words in 32-bit mode, since
5159 the parameter save area starts at offset 24 from the
5160 stack. In 64-bit mode, they just have to start on an
5161 even word, since the parameter save area is 16-byte
5162 aligned. Space for GPRs is reserved even if the argument
5163 will be passed in memory. */
5165 align = (2 - cum->words) & 3;
5167 align = cum->words & 1;
5168 cum->words += align + rs6000_arg_size (mode, type);
5170 if (TARGET_DEBUG_ARG)
5172 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5174 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5175 cum->nargs_prototype, cum->prototype,
5176 GET_MODE_NAME (mode));
5180 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5182 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5185 else if (rs6000_darwin64_abi
5187 && TREE_CODE (type) == RECORD_TYPE
5188 && (size = int_size_in_bytes (type)) > 0)
5190 /* Variable sized types have size == -1 and are
5191 treated as if consisting entirely of ints.
5192 Pad to 16 byte boundary if needed. */
5193 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5194 && (cum->words % 2) != 0)
5196 /* For varargs, we can just go up by the size of the struct. */
5198 cum->words += (size + 7) / 8;
5201 /* It is tempting to say int register count just goes up by
5202 sizeof(type)/8, but this is wrong in a case such as
5203 { int; double; int; } [powerpc alignment]. We have to
5204 grovel through the fields for these too. */
5206 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5207 rs6000_darwin64_record_arg_advance_flush (cum,
5208 size * BITS_PER_UNIT);
5211 else if (DEFAULT_ABI == ABI_V4)
5213 if (TARGET_HARD_FLOAT && TARGET_FPRS
5214 && (mode == SFmode || mode == DFmode
5215 || mode == DDmode || mode == TDmode
5216 || (mode == TFmode && !TARGET_IEEEQUAD)))
5218 /* _Decimal128 must use an even/odd register pair. This assumes
5219 that the register number is odd when fregno is odd. */
5220 if (mode == TDmode && (cum->fregno % 2) == 1)
5223 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5224 <= FP_ARG_V4_MAX_REG)
5225 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5228 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5229 if (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode)
5230 cum->words += cum->words & 1;
5231 cum->words += rs6000_arg_size (mode, type);
5236 int n_words = rs6000_arg_size (mode, type);
5237 int gregno = cum->sysv_gregno;
5239 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5240 (r7,r8) or (r9,r10). As does any other 2 word item such
5241 as complex int due to a historical mistake. */
5243 gregno += (1 - gregno) & 1;
5245 /* Multi-reg args are not split between registers and stack. */
5246 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5248 /* Long long and SPE vectors are aligned on the stack.
5249 So are other 2 word items such as complex int due to
5250 a historical mistake. */
5252 cum->words += cum->words & 1;
5253 cum->words += n_words;
5256 /* Note: continuing to accumulate gregno past when we've started
5257 spilling to the stack indicates the fact that we've started
5258 spilling to the stack to expand_builtin_saveregs. */
5259 cum->sysv_gregno = gregno + n_words;
5262 if (TARGET_DEBUG_ARG)
5264 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5265 cum->words, cum->fregno);
5266 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5267 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5268 fprintf (stderr, "mode = %4s, named = %d\n",
5269 GET_MODE_NAME (mode), named);
5274 int n_words = rs6000_arg_size (mode, type);
5275 int start_words = cum->words;
5276 int align_words = rs6000_parm_start (mode, type, start_words);
5278 cum->words = align_words + n_words;
5280 if (SCALAR_FLOAT_MODE_P (mode)
5282 && TARGET_HARD_FLOAT && TARGET_FPRS)
5284 /* _Decimal128 must be passed in an even/odd float register pair.
5285 This assumes that the register number is odd when fregno is
5287 if (mode == TDmode && (cum->fregno % 2) == 1)
5289 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5292 if (TARGET_DEBUG_ARG)
5294 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5295 cum->words, cum->fregno);
5296 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5297 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5298 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5299 named, align_words - start_words, depth);
5305 spe_build_register_parallel (enum machine_mode mode, int gregno)
5312 r1 = gen_rtx_REG (DImode, gregno);
5313 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5314 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5318 r1 = gen_rtx_REG (DImode, gregno);
5319 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5320 r3 = gen_rtx_REG (DImode, gregno + 2);
5321 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5322 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5325 r1 = gen_rtx_REG (DImode, gregno);
5326 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5327 r3 = gen_rtx_REG (DImode, gregno + 2);
5328 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5329 r5 = gen_rtx_REG (DImode, gregno + 4);
5330 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5331 r7 = gen_rtx_REG (DImode, gregno + 6);
5332 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5333 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5340 /* Determine where to put a SIMD argument on the SPE. */
5342 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5345 int gregno = cum->sysv_gregno;
5347 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5348 are passed and returned in a pair of GPRs for ABI compatibility. */
5349 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode
5350 || mode == TFmode || mode == TCmode))
5352 int n_words = rs6000_arg_size (mode, type);
5354 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5356 gregno += (1 - gregno) & 1;
5358 /* Multi-reg args are not split between registers and stack. */
5359 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5362 return spe_build_register_parallel (mode, gregno);
5366 int n_words = rs6000_arg_size (mode, type);
5368 /* SPE vectors are put in odd registers. */
5369 if (n_words == 2 && (gregno & 1) == 0)
5372 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5375 enum machine_mode m = SImode;
5377 r1 = gen_rtx_REG (m, gregno);
5378 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5379 r2 = gen_rtx_REG (m, gregno + 1);
5380 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5381 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5388 if (gregno <= GP_ARG_MAX_REG)
5389 return gen_rtx_REG (mode, gregno);
5395 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5396 structure between cum->intoffset and bitpos to integer registers. */
5399 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5400 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5402 enum machine_mode mode;
5404 unsigned int startbit, endbit;
5405 int this_regno, intregs, intoffset;
5408 if (cum->intoffset == -1)
5411 intoffset = cum->intoffset;
5412 cum->intoffset = -1;
5414 /* If this is the trailing part of a word, try to only load that
5415 much into the register. Otherwise load the whole register. Note
5416 that in the latter case we may pick up unwanted bits. It's not a
5417 problem at the moment but may wish to revisit. */
5419 if (intoffset % BITS_PER_WORD != 0)
5421 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5423 if (mode == BLKmode)
5425 /* We couldn't find an appropriate mode, which happens,
5426 e.g., in packed structs when there are 3 bytes to load.
5427 Back intoffset back to the beginning of the word in this
5429 intoffset = intoffset & -BITS_PER_WORD;
5436 startbit = intoffset & -BITS_PER_WORD;
5437 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5438 intregs = (endbit - startbit) / BITS_PER_WORD;
5439 this_regno = cum->words + intoffset / BITS_PER_WORD;
5441 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5444 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5448 intoffset /= BITS_PER_UNIT;
5451 regno = GP_ARG_MIN_REG + this_regno;
5452 reg = gen_rtx_REG (mode, regno);
5454 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5457 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5461 while (intregs > 0);
5464 /* Recursive workhorse for the following. */
5467 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
5468 HOST_WIDE_INT startbitpos, rtx rvec[],
5473 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5474 if (TREE_CODE (f) == FIELD_DECL)
5476 HOST_WIDE_INT bitpos = startbitpos;
5477 tree ftype = TREE_TYPE (f);
5478 enum machine_mode mode;
5479 if (ftype == error_mark_node)
5481 mode = TYPE_MODE (ftype);
5483 if (DECL_SIZE (f) != 0
5484 && host_integerp (bit_position (f), 1))
5485 bitpos += int_bit_position (f);
5487 /* ??? FIXME: else assume zero offset. */
5489 if (TREE_CODE (ftype) == RECORD_TYPE)
5490 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5491 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5496 case SCmode: mode = SFmode; break;
5497 case DCmode: mode = DFmode; break;
5498 case TCmode: mode = TFmode; break;
5502 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5504 = gen_rtx_EXPR_LIST (VOIDmode,
5505 gen_rtx_REG (mode, cum->fregno++),
5506 GEN_INT (bitpos / BITS_PER_UNIT));
5507 if (mode == TFmode || mode == TDmode)
5510 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5512 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5514 = gen_rtx_EXPR_LIST (VOIDmode,
5515 gen_rtx_REG (mode, cum->vregno++),
5516 GEN_INT (bitpos / BITS_PER_UNIT));
5518 else if (cum->intoffset == -1)
5519 cum->intoffset = bitpos;
5523 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5524 the register(s) to be used for each field and subfield of a struct
5525 being passed by value, along with the offset of where the
5526 register's value may be found in the block. FP fields go in FP
5527 register, vector fields go in vector registers, and everything
5528 else goes in int registers, packed as in memory.
5530 This code is also used for function return values. RETVAL indicates
5531 whether this is the case.
5533 Much of this is taken from the SPARC V9 port, which has a similar
5534 calling convention. */
5537 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
5538 int named, bool retval)
5540 rtx rvec[FIRST_PSEUDO_REGISTER];
5541 int k = 1, kbase = 1;
5542 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5543 /* This is a copy; modifications are not visible to our caller. */
5544 CUMULATIVE_ARGS copy_cum = *orig_cum;
5545 CUMULATIVE_ARGS *cum = ©_cum;
5547 /* Pad to 16 byte boundary if needed. */
5548 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5549 && (cum->words % 2) != 0)
5556 /* Put entries into rvec[] for individual FP and vector fields, and
5557 for the chunks of memory that go in int regs. Note we start at
5558 element 1; 0 is reserved for an indication of using memory, and
5559 may or may not be filled in below. */
5560 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5561 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5563 /* If any part of the struct went on the stack put all of it there.
5564 This hack is because the generic code for
5565 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5566 parts of the struct are not at the beginning. */
5570 return NULL_RTX; /* doesn't go in registers at all */
5572 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5574 if (k > 1 || cum->use_stack)
5575 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5580 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5583 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5587 rtx rvec[GP_ARG_NUM_REG + 1];
5589 if (align_words >= GP_ARG_NUM_REG)
5592 n_units = rs6000_arg_size (mode, type);
5594 /* Optimize the simple case where the arg fits in one gpr, except in
5595 the case of BLKmode due to assign_parms assuming that registers are
5596 BITS_PER_WORD wide. */
5598 || (n_units == 1 && mode != BLKmode))
5599 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5602 if (align_words + n_units > GP_ARG_NUM_REG)
5603 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5604 using a magic NULL_RTX component.
5605 This is not strictly correct. Only some of the arg belongs in
5606 memory, not all of it. However, the normal scheme using
5607 function_arg_partial_nregs can result in unusual subregs, eg.
5608 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5609 store the whole arg to memory is often more efficient than code
5610 to store pieces, and we know that space is available in the right
5611 place for the whole arg. */
5612 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5617 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5618 rtx off = GEN_INT (i++ * 4);
5619 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5621 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5623 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5626 /* Determine where to put an argument to a function.
5627 Value is zero to push the argument on the stack,
5628 or a hard register in which to store the argument.
5630 MODE is the argument's machine mode.
5631 TYPE is the data type of the argument (as a tree).
5632 This is null for libcalls where that information may
5634 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5635 the preceding args and about the function being called. It is
5636 not modified in this routine.
5637 NAMED is nonzero if this argument is a named parameter
5638 (otherwise it is an extra parameter matching an ellipsis).
5640 On RS/6000 the first eight words of non-FP are normally in registers
5641 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5642 Under V.4, the first 8 FP args are in registers.
5644 If this is floating-point and no prototype is specified, we use
5645 both an FP and integer register (or possibly FP reg and stack). Library
5646 functions (when CALL_LIBCALL is set) always have the proper types for args,
5647 so we can pass the FP value just in one register. emit_library_function
5648 doesn't support PARALLEL anyway.
5650 Note that for args passed by reference, function_arg will be called
5651 with MODE and TYPE set to that of the pointer to the arg, not the arg
5655 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5656 tree type, int named)
5658 enum rs6000_abi abi = DEFAULT_ABI;
5660 /* Return a marker to indicate whether CR1 needs to set or clear the
5661 bit that V.4 uses to say fp args were passed in registers.
5662 Assume that we don't need the marker for software floating point,
5663 or compiler generated library calls. */
5664 if (mode == VOIDmode)
5667 && (cum->call_cookie & CALL_LIBCALL) == 0
5669 || (cum->nargs_prototype < 0
5670 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5672 /* For the SPE, we need to crxor CR6 always. */
5674 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5675 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5676 return GEN_INT (cum->call_cookie
5677 | ((cum->fregno == FP_ARG_MIN_REG)
5678 ? CALL_V4_SET_FP_ARGS
5679 : CALL_V4_CLEAR_FP_ARGS));
5682 return GEN_INT (cum->call_cookie);
5685 if (rs6000_darwin64_abi && mode == BLKmode
5686 && TREE_CODE (type) == RECORD_TYPE)
5688 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5689 if (rslt != NULL_RTX)
5691 /* Else fall through to usual handling. */
5694 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5695 if (TARGET_64BIT && ! cum->prototype)
5697 /* Vector parameters get passed in vector register
5698 and also in GPRs or memory, in absence of prototype. */
5701 align_words = (cum->words + 1) & ~1;
5703 if (align_words >= GP_ARG_NUM_REG)
5709 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5711 return gen_rtx_PARALLEL (mode,
5713 gen_rtx_EXPR_LIST (VOIDmode,
5715 gen_rtx_EXPR_LIST (VOIDmode,
5716 gen_rtx_REG (mode, cum->vregno),
5720 return gen_rtx_REG (mode, cum->vregno);
5721 else if (TARGET_ALTIVEC_ABI
5722 && (ALTIVEC_VECTOR_MODE (mode)
5723 || (type && TREE_CODE (type) == VECTOR_TYPE
5724 && int_size_in_bytes (type) == 16)))
5726 if (named || abi == ABI_V4)
5730 /* Vector parameters to varargs functions under AIX or Darwin
5731 get passed in memory and possibly also in GPRs. */
5732 int align, align_words, n_words;
5733 enum machine_mode part_mode;
5735 /* Vector parameters must be 16-byte aligned. This places them at
5736 2 mod 4 in terms of words in 32-bit mode, since the parameter
5737 save area starts at offset 24 from the stack. In 64-bit mode,
5738 they just have to start on an even word, since the parameter
5739 save area is 16-byte aligned. */
5741 align = (2 - cum->words) & 3;
5743 align = cum->words & 1;
5744 align_words = cum->words + align;
5746 /* Out of registers? Memory, then. */
5747 if (align_words >= GP_ARG_NUM_REG)
5750 if (TARGET_32BIT && TARGET_POWERPC64)
5751 return rs6000_mixed_function_arg (mode, type, align_words);
5753 /* The vector value goes in GPRs. Only the part of the
5754 value in GPRs is reported here. */
5756 n_words = rs6000_arg_size (mode, type);
5757 if (align_words + n_words > GP_ARG_NUM_REG)
5758 /* Fortunately, there are only two possibilities, the value
5759 is either wholly in GPRs or half in GPRs and half not. */
5762 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5765 else if (TARGET_SPE_ABI && TARGET_SPE
5766 && (SPE_VECTOR_MODE (mode)
5767 || (TARGET_E500_DOUBLE && (mode == DFmode
5772 || mode == TCmode))))
5773 return rs6000_spe_function_arg (cum, mode, type);
5775 else if (abi == ABI_V4)
5777 if (TARGET_HARD_FLOAT && TARGET_FPRS
5778 && (mode == SFmode || mode == DFmode
5779 || (mode == TFmode && !TARGET_IEEEQUAD)
5780 || mode == DDmode || mode == TDmode))
5782 /* _Decimal128 must use an even/odd register pair. This assumes
5783 that the register number is odd when fregno is odd. */
5784 if (mode == TDmode && (cum->fregno % 2) == 1)
5787 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5788 <= FP_ARG_V4_MAX_REG)
5789 return gen_rtx_REG (mode, cum->fregno);
5795 int n_words = rs6000_arg_size (mode, type);
5796 int gregno = cum->sysv_gregno;
5798 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5799 (r7,r8) or (r9,r10). As does any other 2 word item such
5800 as complex int due to a historical mistake. */
5802 gregno += (1 - gregno) & 1;
5804 /* Multi-reg args are not split between registers and stack. */
5805 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5808 if (TARGET_32BIT && TARGET_POWERPC64)
5809 return rs6000_mixed_function_arg (mode, type,
5810 gregno - GP_ARG_MIN_REG);
5811 return gen_rtx_REG (mode, gregno);
5816 int align_words = rs6000_parm_start (mode, type, cum->words);
5818 /* _Decimal128 must be passed in an even/odd float register pair.
5819 This assumes that the register number is odd when fregno is odd. */
5820 if (mode == TDmode && (cum->fregno % 2) == 1)
5823 if (USE_FP_FOR_ARG_P (cum, mode, type))
5825 rtx rvec[GP_ARG_NUM_REG + 1];
5829 enum machine_mode fmode = mode;
5830 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5832 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5834 /* Currently, we only ever need one reg here because complex
5835 doubles are split. */
5836 gcc_assert (cum->fregno == FP_ARG_MAX_REG
5837 && (fmode == TFmode || fmode == TDmode));
5839 /* Long double or _Decimal128 split over regs and memory. */
5840 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
5843 /* Do we also need to pass this arg in the parameter save
5846 && (cum->nargs_prototype <= 0
5847 || (DEFAULT_ABI == ABI_AIX
5849 && align_words >= GP_ARG_NUM_REG)));
5851 if (!needs_psave && mode == fmode)
5852 return gen_rtx_REG (fmode, cum->fregno);
5857 /* Describe the part that goes in gprs or the stack.
5858 This piece must come first, before the fprs. */
5859 if (align_words < GP_ARG_NUM_REG)
5861 unsigned long n_words = rs6000_arg_size (mode, type);
5863 if (align_words + n_words > GP_ARG_NUM_REG
5864 || (TARGET_32BIT && TARGET_POWERPC64))
5866 /* If this is partially on the stack, then we only
5867 include the portion actually in registers here. */
5868 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5871 if (align_words + n_words > GP_ARG_NUM_REG)
5872 /* Not all of the arg fits in gprs. Say that it
5873 goes in memory too, using a magic NULL_RTX
5874 component. Also see comment in
5875 rs6000_mixed_function_arg for why the normal
5876 function_arg_partial_nregs scheme doesn't work
5878 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5882 r = gen_rtx_REG (rmode,
5883 GP_ARG_MIN_REG + align_words);
5884 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5885 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5887 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5891 /* The whole arg fits in gprs. */
5892 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5893 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5897 /* It's entirely in memory. */
5898 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5901 /* Describe where this piece goes in the fprs. */
5902 r = gen_rtx_REG (fmode, cum->fregno);
5903 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5905 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5907 else if (align_words < GP_ARG_NUM_REG)
5909 if (TARGET_32BIT && TARGET_POWERPC64)
5910 return rs6000_mixed_function_arg (mode, type, align_words);
5912 if (mode == BLKmode)
5915 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5922 /* For an arg passed partly in registers and partly in memory, this is
5923 the number of bytes passed in registers. For args passed entirely in
5924 registers or entirely in memory, zero. When an arg is described by a
5925 PARALLEL, perhaps using more than one register type, this function
5926 returns the number of bytes used by the first element of the PARALLEL. */
5929 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5930 tree type, bool named)
5935 if (DEFAULT_ABI == ABI_V4)
5938 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5939 && cum->nargs_prototype >= 0)
5942 /* In this complicated case we just disable the partial_nregs code. */
5943 if (rs6000_darwin64_abi && mode == BLKmode
5944 && TREE_CODE (type) == RECORD_TYPE
5945 && int_size_in_bytes (type) > 0)
5948 align_words = rs6000_parm_start (mode, type, cum->words);
5950 if (USE_FP_FOR_ARG_P (cum, mode, type))
5952 /* If we are passing this arg in the fixed parameter save area
5953 (gprs or memory) as well as fprs, then this function should
5954 return the number of partial bytes passed in the parameter
5955 save area rather than partial bytes passed in fprs. */
5957 && (cum->nargs_prototype <= 0
5958 || (DEFAULT_ABI == ABI_AIX
5960 && align_words >= GP_ARG_NUM_REG)))
5962 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5963 > FP_ARG_MAX_REG + 1)
5964 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5965 else if (cum->nargs_prototype >= 0)
5969 if (align_words < GP_ARG_NUM_REG
5970 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5971 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5973 if (ret != 0 && TARGET_DEBUG_ARG)
5974 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5979 /* A C expression that indicates when an argument must be passed by
5980 reference. If nonzero for an argument, a copy of that argument is
5981 made in memory and a pointer to the argument is passed instead of
5982 the argument itself. The pointer is passed in whatever way is
5983 appropriate for passing a pointer to that type.
5985 Under V.4, aggregates and long double are passed by reference.
5987 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5988 reference unless the AltiVec vector extension ABI is in force.
5990 As an extension to all ABIs, variable sized types are passed by
5994 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5995 enum machine_mode mode, const_tree type,
5996 bool named ATTRIBUTE_UNUSED)
5998 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
6000 if (TARGET_DEBUG_ARG)
6001 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
6008 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
6010 if (TARGET_DEBUG_ARG)
6011 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
6015 if (int_size_in_bytes (type) < 0)
6017 if (TARGET_DEBUG_ARG)
6018 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
6022 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6023 modes only exist for GCC vector types if -maltivec. */
6024 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
6026 if (TARGET_DEBUG_ARG)
6027 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
6031 /* Pass synthetic vectors in memory. */
6032 if (TREE_CODE (type) == VECTOR_TYPE
6033 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6035 static bool warned_for_pass_big_vectors = false;
6036 if (TARGET_DEBUG_ARG)
6037 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
6038 if (!warned_for_pass_big_vectors)
6040 warning (0, "GCC vector passed by reference: "
6041 "non-standard ABI extension with no compatibility guarantee");
6042 warned_for_pass_big_vectors = true;
6051 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
6054 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
6059 for (i = 0; i < nregs; i++)
6061 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
6062 if (reload_completed)
6064 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
6067 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
6068 i * GET_MODE_SIZE (reg_mode));
6071 tem = replace_equiv_address (tem, XEXP (tem, 0));
6075 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
6079 /* Perform any needed actions needed for a function that is receiving a
6080 variable number of arguments.
6084 MODE and TYPE are the mode and type of the current parameter.
6086 PRETEND_SIZE is a variable that should be set to the amount of stack
6087 that must be pushed by the prolog to pretend that our caller pushed
6090 Normally, this macro will push all remaining incoming registers on the
6091 stack and set PRETEND_SIZE to the length of the registers pushed. */
6094 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6095 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6098 CUMULATIVE_ARGS next_cum;
6099 int reg_size = TARGET_32BIT ? 4 : 8;
6100 rtx save_area = NULL_RTX, mem;
6101 int first_reg_offset;
6104 /* Skip the last named argument. */
6106 function_arg_advance (&next_cum, mode, type, 1, 0);
6108 if (DEFAULT_ABI == ABI_V4)
6110 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
6114 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
6115 HOST_WIDE_INT offset = 0;
6117 /* Try to optimize the size of the varargs save area.
6118 The ABI requires that ap.reg_save_area is doubleword
6119 aligned, but we don't need to allocate space for all
6120 the bytes, only those to which we actually will save
6122 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
6123 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
6124 if (TARGET_HARD_FLOAT && TARGET_FPRS
6125 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6126 && cfun->va_list_fpr_size)
6129 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
6130 * UNITS_PER_FP_WORD;
6131 if (cfun->va_list_fpr_size
6132 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6133 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
6135 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6136 * UNITS_PER_FP_WORD;
6140 offset = -((first_reg_offset * reg_size) & ~7);
6141 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6143 gpr_reg_num = cfun->va_list_gpr_size;
6144 if (reg_size == 4 && (first_reg_offset & 1))
6147 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6150 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6152 - (int) (GP_ARG_NUM_REG * reg_size);
6154 if (gpr_size + fpr_size)
6157 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6158 gcc_assert (GET_CODE (reg_save_area) == MEM);
6159 reg_save_area = XEXP (reg_save_area, 0);
6160 if (GET_CODE (reg_save_area) == PLUS)
6162 gcc_assert (XEXP (reg_save_area, 0)
6163 == virtual_stack_vars_rtx);
6164 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6165 offset += INTVAL (XEXP (reg_save_area, 1));
6168 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6171 cfun->machine->varargs_save_offset = offset;
6172 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6177 first_reg_offset = next_cum.words;
6178 save_area = virtual_incoming_args_rtx;
6180 if (targetm.calls.must_pass_in_stack (mode, type))
6181 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6184 set = get_varargs_alias_set ();
6185 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6186 && cfun->va_list_gpr_size)
6188 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6190 if (va_list_gpr_counter_field)
6192 /* V4 va_list_gpr_size counts number of registers needed. */
6193 if (nregs > cfun->va_list_gpr_size)
6194 nregs = cfun->va_list_gpr_size;
6198 /* char * va_list instead counts number of bytes needed. */
6199 if (nregs > cfun->va_list_gpr_size / reg_size)
6200 nregs = cfun->va_list_gpr_size / reg_size;
6203 mem = gen_rtx_MEM (BLKmode,
6204 plus_constant (save_area,
6205 first_reg_offset * reg_size));
6206 MEM_NOTRAP_P (mem) = 1;
6207 set_mem_alias_set (mem, set);
6208 set_mem_align (mem, BITS_PER_WORD);
6210 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6214 /* Save FP registers if needed. */
6215 if (DEFAULT_ABI == ABI_V4
6216 && TARGET_HARD_FLOAT && TARGET_FPRS
6218 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6219 && cfun->va_list_fpr_size)
6221 int fregno = next_cum.fregno, nregs;
6222 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6223 rtx lab = gen_label_rtx ();
6224 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6225 * UNITS_PER_FP_WORD);
6228 (gen_rtx_SET (VOIDmode,
6230 gen_rtx_IF_THEN_ELSE (VOIDmode,
6231 gen_rtx_NE (VOIDmode, cr1,
6233 gen_rtx_LABEL_REF (VOIDmode, lab),
6237 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6238 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6240 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6241 MEM_NOTRAP_P (mem) = 1;
6242 set_mem_alias_set (mem, set);
6243 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6244 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6251 /* Create the va_list data type. */
6254 rs6000_build_builtin_va_list (void)
6256 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6258 /* For AIX, prefer 'char *' because that's what the system
6259 header files like. */
6260 if (DEFAULT_ABI != ABI_V4)
6261 return build_pointer_type (char_type_node);
6263 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6264 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6266 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6267 unsigned_char_type_node);
6268 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6269 unsigned_char_type_node);
6270 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6272 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6273 short_unsigned_type_node);
6274 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6276 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6279 va_list_gpr_counter_field = f_gpr;
6280 va_list_fpr_counter_field = f_fpr;
6282 DECL_FIELD_CONTEXT (f_gpr) = record;
6283 DECL_FIELD_CONTEXT (f_fpr) = record;
6284 DECL_FIELD_CONTEXT (f_res) = record;
6285 DECL_FIELD_CONTEXT (f_ovf) = record;
6286 DECL_FIELD_CONTEXT (f_sav) = record;
6288 TREE_CHAIN (record) = type_decl;
6289 TYPE_NAME (record) = type_decl;
6290 TYPE_FIELDS (record) = f_gpr;
6291 TREE_CHAIN (f_gpr) = f_fpr;
6292 TREE_CHAIN (f_fpr) = f_res;
6293 TREE_CHAIN (f_res) = f_ovf;
6294 TREE_CHAIN (f_ovf) = f_sav;
6296 layout_type (record);
6298 /* The correct type is an array type of one element. */
6299 return build_array_type (record, build_index_type (size_zero_node));
6302 /* Implement va_start. */
6305 rs6000_va_start (tree valist, rtx nextarg)
6307 HOST_WIDE_INT words, n_gpr, n_fpr;
6308 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6309 tree gpr, fpr, ovf, sav, t;
6311 /* Only SVR4 needs something special. */
6312 if (DEFAULT_ABI != ABI_V4)
6314 std_expand_builtin_va_start (valist, nextarg);
6318 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6319 f_fpr = TREE_CHAIN (f_gpr);
6320 f_res = TREE_CHAIN (f_fpr);
6321 f_ovf = TREE_CHAIN (f_res);
6322 f_sav = TREE_CHAIN (f_ovf);
6324 valist = build_va_arg_indirect_ref (valist);
6325 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6326 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6327 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6328 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6330 /* Count number of gp and fp argument registers used. */
6331 words = current_function_args_info.words;
6332 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6334 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6337 if (TARGET_DEBUG_ARG)
6338 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6339 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6340 words, n_gpr, n_fpr);
6342 if (cfun->va_list_gpr_size)
6344 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6345 build_int_cst (NULL_TREE, n_gpr));
6346 TREE_SIDE_EFFECTS (t) = 1;
6347 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6350 if (cfun->va_list_fpr_size)
6352 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6353 build_int_cst (NULL_TREE, n_fpr));
6354 TREE_SIDE_EFFECTS (t) = 1;
6355 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6358 /* Find the overflow area. */
6359 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6361 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6362 size_int (words * UNITS_PER_WORD));
6363 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6364 TREE_SIDE_EFFECTS (t) = 1;
6365 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6367 /* If there were no va_arg invocations, don't set up the register
6369 if (!cfun->va_list_gpr_size
6370 && !cfun->va_list_fpr_size
6371 && n_gpr < GP_ARG_NUM_REG
6372 && n_fpr < FP_ARG_V4_MAX_REG)
6375 /* Find the register save area. */
6376 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6377 if (cfun->machine->varargs_save_offset)
6378 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6379 size_int (cfun->machine->varargs_save_offset));
6380 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6381 TREE_SIDE_EFFECTS (t) = 1;
6382 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6385 /* Implement va_arg. */
6388 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6390 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6391 tree gpr, fpr, ovf, sav, reg, t, u;
6392 int size, rsize, n_reg, sav_ofs, sav_scale;
6393 tree lab_false, lab_over, addr;
6395 tree ptrtype = build_pointer_type (type);
6398 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6400 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6401 return build_va_arg_indirect_ref (t);
6404 if (DEFAULT_ABI != ABI_V4)
6406 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6408 tree elem_type = TREE_TYPE (type);
6409 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6410 int elem_size = GET_MODE_SIZE (elem_mode);
6412 if (elem_size < UNITS_PER_WORD)
6414 tree real_part, imag_part;
6415 tree post = NULL_TREE;
6417 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6419 /* Copy the value into a temporary, lest the formal temporary
6420 be reused out from under us. */
6421 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6422 append_to_statement_list (post, pre_p);
6424 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6427 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6431 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6434 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6435 f_fpr = TREE_CHAIN (f_gpr);
6436 f_res = TREE_CHAIN (f_fpr);
6437 f_ovf = TREE_CHAIN (f_res);
6438 f_sav = TREE_CHAIN (f_ovf);
6440 valist = build_va_arg_indirect_ref (valist);
6441 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6442 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6443 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6444 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6446 size = int_size_in_bytes (type);
6447 rsize = (size + 3) / 4;
6450 if (TARGET_HARD_FLOAT && TARGET_FPRS
6451 && (TYPE_MODE (type) == SFmode
6452 || TYPE_MODE (type) == DFmode
6453 || TYPE_MODE (type) == TFmode
6454 || TYPE_MODE (type) == DDmode
6455 || TYPE_MODE (type) == TDmode))
6457 /* FP args go in FP registers, if present. */
6459 n_reg = (size + 7) / 8;
6462 if (TYPE_MODE (type) != SFmode)
6467 /* Otherwise into GP registers. */
6476 /* Pull the value out of the saved registers.... */
6479 addr = create_tmp_var (ptr_type_node, "addr");
6480 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6482 /* AltiVec vectors never go in registers when -mabi=altivec. */
6483 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6487 lab_false = create_artificial_label ();
6488 lab_over = create_artificial_label ();
6490 /* Long long and SPE vectors are aligned in the registers.
6491 As are any other 2 gpr item such as complex int due to a
6492 historical mistake. */
6494 if (n_reg == 2 && reg == gpr)
6497 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6498 build_int_cst (TREE_TYPE (reg), n_reg - 1));
6499 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6501 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6502 reg number is 0 for f1, so we want to make it odd. */
6503 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6506 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg, size_int (1));
6507 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6510 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6511 t = build2 (GE_EXPR, boolean_type_node, u, t);
6512 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6513 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6514 gimplify_and_add (t, pre_p);
6518 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6520 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
6521 build_int_cst (TREE_TYPE (reg), n_reg));
6522 u = fold_convert (sizetype, u);
6523 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
6524 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
6526 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6527 gimplify_and_add (t, pre_p);
6529 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6530 gimplify_and_add (t, pre_p);
6532 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6533 append_to_statement_list (t, pre_p);
6535 if ((n_reg == 2 && !regalign) || n_reg > 2)
6537 /* Ensure that we don't find any more args in regs.
6538 Alignment has taken care of for special cases. */
6539 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6540 gimplify_and_add (t, pre_p);
6544 /* ... otherwise out of the overflow area. */
6546 /* Care for on-stack alignment if needed. */
6550 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6551 t = fold_convert (sizetype, t);
6552 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6554 t = fold_convert (TREE_TYPE (ovf), t);
6556 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6558 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6559 gimplify_and_add (u, pre_p);
6561 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6562 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6563 gimplify_and_add (t, pre_p);
6567 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6568 append_to_statement_list (t, pre_p);
6571 if (STRICT_ALIGNMENT
6572 && (TYPE_ALIGN (type)
6573 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6575 /* The value (of type complex double, for example) may not be
6576 aligned in memory in the saved registers, so copy via a
6577 temporary. (This is the same code as used for SPARC.) */
6578 tree tmp = create_tmp_var (type, "va_arg_tmp");
6579 tree dest_addr = build_fold_addr_expr (tmp);
6581 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6582 3, dest_addr, addr, size_int (rsize * 4));
6584 gimplify_and_add (copy, pre_p);
6588 addr = fold_convert (ptrtype, addr);
6589 return build_va_arg_indirect_ref (addr);
6595 def_builtin (int mask, const char *name, tree type, int code)
6597 if (mask & target_flags)
6599 if (rs6000_builtin_decls[code])
6602 rs6000_builtin_decls[code] =
6603 add_builtin_function (name, type, code, BUILT_IN_MD,
6608 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6610 static const struct builtin_description bdesc_3arg[] =
6612 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6613 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6614 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6615 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6616 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6617 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6618 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6619 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6620 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6621 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6622 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6623 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6624 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6625 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6626 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6627 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6628 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6629 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6630 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6631 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6632 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6633 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6634 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6636 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6637 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6638 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6639 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6640 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6641 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6642 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6643 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6644 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6645 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6646 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6647 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6648 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6649 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6650 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6653 /* DST operations: void foo (void *, const int, const char). */
6655 static const struct builtin_description bdesc_dst[] =
6657 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6658 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6659 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6660 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6662 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6663 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6664 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6665 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6668 /* Simple binary operations: VECc = foo (VECa, VECb). */
6670 static struct builtin_description bdesc_2arg[] =
6672 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6673 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6674 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6675 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6676 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6677 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6678 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6679 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6680 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6681 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6682 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6683 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6684 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6685 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6686 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6687 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6688 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6689 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6690 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6691 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6692 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6693 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6694 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6695 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6696 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6697 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6698 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6699 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6700 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6701 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6702 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6703 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6704 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6705 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6706 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6707 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6708 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6709 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6710 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6711 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6712 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6713 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6714 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6715 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6716 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6717 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6718 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6719 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6720 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6721 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6722 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6723 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6724 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6725 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6726 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6727 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6728 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6729 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6730 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6731 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6732 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6733 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6734 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6735 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6736 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6737 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6738 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6739 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6740 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6741 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6742 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6743 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6744 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6745 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6746 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6747 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6748 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6749 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6750 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6751 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6752 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6753 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6754 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6755 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6756 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6757 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6758 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6759 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6760 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6761 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6762 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6763 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6764 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6765 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6766 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6767 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6768 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6769 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6770 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6771 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6772 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6773 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6774 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6775 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6776 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6777 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6778 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6779 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6780 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6781 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6782 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6784 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6785 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6786 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6787 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6788 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6789 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6790 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6791 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6792 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6793 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6794 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6795 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6796 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6797 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6798 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6799 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6800 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6801 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6802 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6803 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6804 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6805 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6806 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6807 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6808 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6809 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6810 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6811 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6812 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6813 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6814 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6815 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6816 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6817 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6818 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6819 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6820 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6821 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6822 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6823 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6824 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6825 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6826 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6827 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6828 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6829 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6830 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6831 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6832 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6833 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6834 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6835 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6836 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6837 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6838 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6839 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6840 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6841 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6842 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6843 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6844 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6845 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6846 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6847 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6848 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6849 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6850 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6851 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6852 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6853 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6854 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6855 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6856 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6857 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6858 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6859 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6860 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6861 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6862 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6863 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6864 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6865 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6866 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6867 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6868 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6869 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6870 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6871 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6872 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6873 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6874 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6875 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6876 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6877 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6878 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6879 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6880 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6881 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6882 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6883 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6884 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6885 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6886 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6887 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6888 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6889 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6890 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6891 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6892 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6893 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6894 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6895 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6896 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6897 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6898 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6899 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6900 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6901 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6902 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6903 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6904 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6905 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6906 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6907 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6908 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6909 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6910 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6912 /* Place holder, leave as first spe builtin. */
6913 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6914 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6915 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6916 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6917 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6918 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6919 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6920 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6921 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6922 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6923 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6924 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6925 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6926 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6927 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6928 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6929 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6930 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6931 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6932 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6933 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6934 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6935 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6936 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6937 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6938 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6939 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6940 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6941 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6942 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6943 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6944 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6945 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6946 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6947 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6948 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6949 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6950 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6951 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6952 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6953 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6954 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6955 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6956 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6957 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6958 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6959 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6960 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6961 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6962 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6963 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6964 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6965 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6966 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6967 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6968 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6969 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6970 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6971 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6972 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6973 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6974 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6975 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6976 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6977 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6978 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6979 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6980 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6981 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6982 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6983 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6984 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6985 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6986 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6987 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6988 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6989 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6990 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6991 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6992 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6993 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6994 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6995 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6996 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6997 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6998 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6999 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
7000 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
7001 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
7002 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
7003 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
7004 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
7005 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
7006 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
7007 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
7008 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
7009 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
7010 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
7011 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
7012 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
7013 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
7014 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
7015 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
7016 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
7017 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
7018 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
7019 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
7020 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
7021 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
7023 /* SPE binary operations expecting a 5-bit unsigned literal. */
7024 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
7026 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
7027 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
7028 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
7029 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
7030 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
7031 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
7032 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
7033 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
7034 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
7035 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
7036 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
7037 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
7038 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
7039 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
7040 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
7041 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
7042 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
7043 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
7044 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
7045 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
7046 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
7047 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
7048 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
7049 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
7050 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
7051 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
7053 /* Place-holder. Leave as last binary SPE builtin. */
7054 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
7057 /* AltiVec predicates. */
7059 struct builtin_description_predicates
7061 const unsigned int mask;
7062 const enum insn_code icode;
7064 const char *const name;
7065 const enum rs6000_builtins code;
7068 static const struct builtin_description_predicates bdesc_altivec_preds[] =
7070 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
7071 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
7072 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
7073 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
7074 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
7075 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
7076 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
7077 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
7078 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
7079 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
7080 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
7081 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
7082 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
7084 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
7085 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
7086 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
7089 /* SPE predicates. */
7090 static struct builtin_description bdesc_spe_predicates[] =
7092 /* Place-holder. Leave as first. */
7093 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
7094 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
7095 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
7096 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
7097 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
7098 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
7099 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
7100 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
7101 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
7102 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
7103 /* Place-holder. Leave as last. */
7104 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
7107 /* SPE evsel predicates. */
7108 static struct builtin_description bdesc_spe_evsel[] =
7110 /* Place-holder. Leave as first. */
7111 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
7112 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
7113 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
7114 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
7115 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
7116 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
7117 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
7118 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
7119 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
7120 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
7121 /* Place-holder. Leave as last. */
7122 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
7125 /* ABS* operations. */
7127 static const struct builtin_description bdesc_abs[] =
7129 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
7130 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
7131 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
7132 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
7133 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
7134 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
7135 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
7138 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7141 static struct builtin_description bdesc_1arg[] =
7143 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7144 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7145 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7146 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7147 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7148 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7149 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7150 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7151 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7152 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7153 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7154 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7155 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7156 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7157 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7158 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7159 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7161 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7162 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7163 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7164 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7165 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7166 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7167 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7168 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7169 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7170 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7171 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7172 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7173 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7174 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7175 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7176 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7177 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7178 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7179 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7181 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7182 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7183 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7184 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7185 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7186 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7187 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7188 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7189 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7190 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7191 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7192 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7193 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7194 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7195 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7196 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7197 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7198 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7199 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7200 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7201 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7202 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7203 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7204 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7205 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7206 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7207 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7208 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7209 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7210 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7212 /* Place-holder. Leave as last unary SPE builtin. */
7213 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
7217 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7220 tree arg0 = CALL_EXPR_ARG (exp, 0);
7221 rtx op0 = expand_normal (arg0);
7222 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7223 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7225 if (icode == CODE_FOR_nothing)
7226 /* Builtin not supported on this processor. */
7229 /* If we got invalid arguments bail out before generating bad rtl. */
7230 if (arg0 == error_mark_node)
7233 if (icode == CODE_FOR_altivec_vspltisb
7234 || icode == CODE_FOR_altivec_vspltish
7235 || icode == CODE_FOR_altivec_vspltisw
7236 || icode == CODE_FOR_spe_evsplatfi
7237 || icode == CODE_FOR_spe_evsplati)
7239 /* Only allow 5-bit *signed* literals. */
7240 if (GET_CODE (op0) != CONST_INT
7241 || INTVAL (op0) > 15
7242 || INTVAL (op0) < -16)
7244 error ("argument 1 must be a 5-bit signed literal");
7250 || GET_MODE (target) != tmode
7251 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7252 target = gen_reg_rtx (tmode);
7254 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7255 op0 = copy_to_mode_reg (mode0, op0);
7257 pat = GEN_FCN (icode) (target, op0);
7266 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7268 rtx pat, scratch1, scratch2;
7269 tree arg0 = CALL_EXPR_ARG (exp, 0);
7270 rtx op0 = expand_normal (arg0);
7271 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7272 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7274 /* If we have invalid arguments, bail out before generating bad rtl. */
7275 if (arg0 == error_mark_node)
7279 || GET_MODE (target) != tmode
7280 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7281 target = gen_reg_rtx (tmode);
7283 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7284 op0 = copy_to_mode_reg (mode0, op0);
7286 scratch1 = gen_reg_rtx (mode0);
7287 scratch2 = gen_reg_rtx (mode0);
7289 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7298 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7301 tree arg0 = CALL_EXPR_ARG (exp, 0);
7302 tree arg1 = CALL_EXPR_ARG (exp, 1);
7303 rtx op0 = expand_normal (arg0);
7304 rtx op1 = expand_normal (arg1);
7305 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7306 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7307 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7309 if (icode == CODE_FOR_nothing)
7310 /* Builtin not supported on this processor. */
7313 /* If we got invalid arguments bail out before generating bad rtl. */
7314 if (arg0 == error_mark_node || arg1 == error_mark_node)
7317 if (icode == CODE_FOR_altivec_vcfux
7318 || icode == CODE_FOR_altivec_vcfsx
7319 || icode == CODE_FOR_altivec_vctsxs
7320 || icode == CODE_FOR_altivec_vctuxs
7321 || icode == CODE_FOR_altivec_vspltb
7322 || icode == CODE_FOR_altivec_vsplth
7323 || icode == CODE_FOR_altivec_vspltw
7324 || icode == CODE_FOR_spe_evaddiw
7325 || icode == CODE_FOR_spe_evldd
7326 || icode == CODE_FOR_spe_evldh
7327 || icode == CODE_FOR_spe_evldw
7328 || icode == CODE_FOR_spe_evlhhesplat
7329 || icode == CODE_FOR_spe_evlhhossplat
7330 || icode == CODE_FOR_spe_evlhhousplat
7331 || icode == CODE_FOR_spe_evlwhe
7332 || icode == CODE_FOR_spe_evlwhos
7333 || icode == CODE_FOR_spe_evlwhou
7334 || icode == CODE_FOR_spe_evlwhsplat
7335 || icode == CODE_FOR_spe_evlwwsplat
7336 || icode == CODE_FOR_spe_evrlwi
7337 || icode == CODE_FOR_spe_evslwi
7338 || icode == CODE_FOR_spe_evsrwis
7339 || icode == CODE_FOR_spe_evsubifw
7340 || icode == CODE_FOR_spe_evsrwiu)
7342 /* Only allow 5-bit unsigned literals. */
7344 if (TREE_CODE (arg1) != INTEGER_CST
7345 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7347 error ("argument 2 must be a 5-bit unsigned literal");
7353 || GET_MODE (target) != tmode
7354 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7355 target = gen_reg_rtx (tmode);
7357 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7358 op0 = copy_to_mode_reg (mode0, op0);
7359 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7360 op1 = copy_to_mode_reg (mode1, op1);
7362 pat = GEN_FCN (icode) (target, op0, op1);
7371 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7372 tree exp, rtx target)
7375 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7376 tree arg0 = CALL_EXPR_ARG (exp, 1);
7377 tree arg1 = CALL_EXPR_ARG (exp, 2);
7378 rtx op0 = expand_normal (arg0);
7379 rtx op1 = expand_normal (arg1);
7380 enum machine_mode tmode = SImode;
7381 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7382 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7385 if (TREE_CODE (cr6_form) != INTEGER_CST)
7387 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7391 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7393 gcc_assert (mode0 == mode1);
7395 /* If we have invalid arguments, bail out before generating bad rtl. */
7396 if (arg0 == error_mark_node || arg1 == error_mark_node)
7400 || GET_MODE (target) != tmode
7401 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7402 target = gen_reg_rtx (tmode);
7404 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7405 op0 = copy_to_mode_reg (mode0, op0);
7406 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7407 op1 = copy_to_mode_reg (mode1, op1);
7409 scratch = gen_reg_rtx (mode0);
7411 pat = GEN_FCN (icode) (scratch, op0, op1,
7412 gen_rtx_SYMBOL_REF (Pmode, opcode));
7417 /* The vec_any* and vec_all* predicates use the same opcodes for two
7418 different operations, but the bits in CR6 will be different
7419 depending on what information we want. So we have to play tricks
7420 with CR6 to get the right bits out.
7422 If you think this is disgusting, look at the specs for the
7423 AltiVec predicates. */
7425 switch (cr6_form_int)
7428 emit_insn (gen_cr6_test_for_zero (target));
7431 emit_insn (gen_cr6_test_for_zero_reverse (target));
7434 emit_insn (gen_cr6_test_for_lt (target));
7437 emit_insn (gen_cr6_test_for_lt_reverse (target));
7440 error ("argument 1 of __builtin_altivec_predicate is out of range");
7448 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7451 tree arg0 = CALL_EXPR_ARG (exp, 0);
7452 tree arg1 = CALL_EXPR_ARG (exp, 1);
7453 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7454 enum machine_mode mode0 = Pmode;
7455 enum machine_mode mode1 = Pmode;
7456 rtx op0 = expand_normal (arg0);
7457 rtx op1 = expand_normal (arg1);
7459 if (icode == CODE_FOR_nothing)
7460 /* Builtin not supported on this processor. */
7463 /* If we got invalid arguments bail out before generating bad rtl. */
7464 if (arg0 == error_mark_node || arg1 == error_mark_node)
7468 || GET_MODE (target) != tmode
7469 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7470 target = gen_reg_rtx (tmode);
7472 op1 = copy_to_mode_reg (mode1, op1);
7474 if (op0 == const0_rtx)
7476 addr = gen_rtx_MEM (tmode, op1);
7480 op0 = copy_to_mode_reg (mode0, op0);
7481 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7484 pat = GEN_FCN (icode) (target, addr);
7494 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7496 tree arg0 = CALL_EXPR_ARG (exp, 0);
7497 tree arg1 = CALL_EXPR_ARG (exp, 1);
7498 tree arg2 = CALL_EXPR_ARG (exp, 2);
7499 rtx op0 = expand_normal (arg0);
7500 rtx op1 = expand_normal (arg1);
7501 rtx op2 = expand_normal (arg2);
7503 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7504 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7505 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7507 /* Invalid arguments. Bail before doing anything stoopid! */
7508 if (arg0 == error_mark_node
7509 || arg1 == error_mark_node
7510 || arg2 == error_mark_node)
7513 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7514 op0 = copy_to_mode_reg (mode2, op0);
7515 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7516 op1 = copy_to_mode_reg (mode0, op1);
7517 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7518 op2 = copy_to_mode_reg (mode1, op2);
7520 pat = GEN_FCN (icode) (op1, op2, op0);
7527 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7529 tree arg0 = CALL_EXPR_ARG (exp, 0);
7530 tree arg1 = CALL_EXPR_ARG (exp, 1);
7531 tree arg2 = CALL_EXPR_ARG (exp, 2);
7532 rtx op0 = expand_normal (arg0);
7533 rtx op1 = expand_normal (arg1);
7534 rtx op2 = expand_normal (arg2);
7536 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7537 enum machine_mode mode1 = Pmode;
7538 enum machine_mode mode2 = Pmode;
7540 /* Invalid arguments. Bail before doing anything stoopid! */
7541 if (arg0 == error_mark_node
7542 || arg1 == error_mark_node
7543 || arg2 == error_mark_node)
7546 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7547 op0 = copy_to_mode_reg (tmode, op0);
7549 op2 = copy_to_mode_reg (mode2, op2);
7551 if (op1 == const0_rtx)
7553 addr = gen_rtx_MEM (tmode, op2);
7557 op1 = copy_to_mode_reg (mode1, op1);
7558 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7561 pat = GEN_FCN (icode) (addr, op0);
7568 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
7571 tree arg0 = CALL_EXPR_ARG (exp, 0);
7572 tree arg1 = CALL_EXPR_ARG (exp, 1);
7573 tree arg2 = CALL_EXPR_ARG (exp, 2);
7574 rtx op0 = expand_normal (arg0);
7575 rtx op1 = expand_normal (arg1);
7576 rtx op2 = expand_normal (arg2);
7577 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7578 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7579 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7580 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7582 if (icode == CODE_FOR_nothing)
7583 /* Builtin not supported on this processor. */
7586 /* If we got invalid arguments bail out before generating bad rtl. */
7587 if (arg0 == error_mark_node
7588 || arg1 == error_mark_node
7589 || arg2 == error_mark_node)
7592 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7593 || icode == CODE_FOR_altivec_vsldoi_v4si
7594 || icode == CODE_FOR_altivec_vsldoi_v8hi
7595 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7597 /* Only allow 4-bit unsigned literals. */
7599 if (TREE_CODE (arg2) != INTEGER_CST
7600 || TREE_INT_CST_LOW (arg2) & ~0xf)
7602 error ("argument 3 must be a 4-bit unsigned literal");
7608 || GET_MODE (target) != tmode
7609 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7610 target = gen_reg_rtx (tmode);
7612 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7613 op0 = copy_to_mode_reg (mode0, op0);
7614 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7615 op1 = copy_to_mode_reg (mode1, op1);
7616 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7617 op2 = copy_to_mode_reg (mode2, op2);
7619 pat = GEN_FCN (icode) (target, op0, op1, op2);
7627 /* Expand the lvx builtins. */
7629 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7631 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7632 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7634 enum machine_mode tmode, mode0;
7636 enum insn_code icode;
7640 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7641 icode = CODE_FOR_altivec_lvx_v16qi;
7643 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7644 icode = CODE_FOR_altivec_lvx_v8hi;
7646 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7647 icode = CODE_FOR_altivec_lvx_v4si;
7649 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7650 icode = CODE_FOR_altivec_lvx_v4sf;
7659 arg0 = CALL_EXPR_ARG (exp, 0);
7660 op0 = expand_normal (arg0);
7661 tmode = insn_data[icode].operand[0].mode;
7662 mode0 = insn_data[icode].operand[1].mode;
7665 || GET_MODE (target) != tmode
7666 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7667 target = gen_reg_rtx (tmode);
7669 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7670 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7672 pat = GEN_FCN (icode) (target, op0);
7679 /* Expand the stvx builtins. */
7681 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7684 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7685 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7687 enum machine_mode mode0, mode1;
7689 enum insn_code icode;
7693 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7694 icode = CODE_FOR_altivec_stvx_v16qi;
7696 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7697 icode = CODE_FOR_altivec_stvx_v8hi;
7699 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7700 icode = CODE_FOR_altivec_stvx_v4si;
7702 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7703 icode = CODE_FOR_altivec_stvx_v4sf;
7710 arg0 = CALL_EXPR_ARG (exp, 0);
7711 arg1 = CALL_EXPR_ARG (exp, 1);
7712 op0 = expand_normal (arg0);
7713 op1 = expand_normal (arg1);
7714 mode0 = insn_data[icode].operand[0].mode;
7715 mode1 = insn_data[icode].operand[1].mode;
7717 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7718 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7719 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7720 op1 = copy_to_mode_reg (mode1, op1);
7722 pat = GEN_FCN (icode) (op0, op1);
7730 /* Expand the dst builtins. */
7732 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7735 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7736 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7737 tree arg0, arg1, arg2;
7738 enum machine_mode mode0, mode1, mode2;
7739 rtx pat, op0, op1, op2;
7740 const struct builtin_description *d;
7745 /* Handle DST variants. */
7747 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7748 if (d->code == fcode)
7750 arg0 = CALL_EXPR_ARG (exp, 0);
7751 arg1 = CALL_EXPR_ARG (exp, 1);
7752 arg2 = CALL_EXPR_ARG (exp, 2);
7753 op0 = expand_normal (arg0);
7754 op1 = expand_normal (arg1);
7755 op2 = expand_normal (arg2);
7756 mode0 = insn_data[d->icode].operand[0].mode;
7757 mode1 = insn_data[d->icode].operand[1].mode;
7758 mode2 = insn_data[d->icode].operand[2].mode;
7760 /* Invalid arguments, bail out before generating bad rtl. */
7761 if (arg0 == error_mark_node
7762 || arg1 == error_mark_node
7763 || arg2 == error_mark_node)
7768 if (TREE_CODE (arg2) != INTEGER_CST
7769 || TREE_INT_CST_LOW (arg2) & ~0x3)
7771 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7775 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7776 op0 = copy_to_mode_reg (Pmode, op0);
7777 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7778 op1 = copy_to_mode_reg (mode1, op1);
7780 pat = GEN_FCN (d->icode) (op0, op1, op2);
7790 /* Expand vec_init builtin. */
7792 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
7794 enum machine_mode tmode = TYPE_MODE (type);
7795 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7796 int i, n_elt = GET_MODE_NUNITS (tmode);
7797 rtvec v = rtvec_alloc (n_elt);
7799 gcc_assert (VECTOR_MODE_P (tmode));
7800 gcc_assert (n_elt == call_expr_nargs (exp));
7802 for (i = 0; i < n_elt; ++i)
7804 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
7805 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7808 if (!target || !register_operand (target, tmode))
7809 target = gen_reg_rtx (tmode);
7811 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7815 /* Return the integer constant in ARG. Constrain it to be in the range
7816 of the subparts of VEC_TYPE; issue an error if not. */
7819 get_element_number (tree vec_type, tree arg)
7821 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7823 if (!host_integerp (arg, 1)
7824 || (elt = tree_low_cst (arg, 1), elt > max))
7826 error ("selector must be an integer constant in the range 0..%wi", max);
7833 /* Expand vec_set builtin. */
7835 altivec_expand_vec_set_builtin (tree exp)
7837 enum machine_mode tmode, mode1;
7838 tree arg0, arg1, arg2;
7842 arg0 = CALL_EXPR_ARG (exp, 0);
7843 arg1 = CALL_EXPR_ARG (exp, 1);
7844 arg2 = CALL_EXPR_ARG (exp, 2);
7846 tmode = TYPE_MODE (TREE_TYPE (arg0));
7847 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7848 gcc_assert (VECTOR_MODE_P (tmode));
7850 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7851 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7852 elt = get_element_number (TREE_TYPE (arg0), arg2);
7854 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7855 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7857 op0 = force_reg (tmode, op0);
7858 op1 = force_reg (mode1, op1);
7860 rs6000_expand_vector_set (op0, op1, elt);
7865 /* Expand vec_ext builtin. */
7867 altivec_expand_vec_ext_builtin (tree exp, rtx target)
7869 enum machine_mode tmode, mode0;
7874 arg0 = CALL_EXPR_ARG (exp, 0);
7875 arg1 = CALL_EXPR_ARG (exp, 1);
7877 op0 = expand_normal (arg0);
7878 elt = get_element_number (TREE_TYPE (arg0), arg1);
7880 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7881 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7882 gcc_assert (VECTOR_MODE_P (mode0));
7884 op0 = force_reg (mode0, op0);
7886 if (optimize || !target || !register_operand (target, tmode))
7887 target = gen_reg_rtx (tmode);
7889 rs6000_expand_vector_extract (target, op0, elt);
7894 /* Expand the builtin in EXP and store the result in TARGET. Store
7895 true in *EXPANDEDP if we found a builtin to expand. */
7897 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7899 const struct builtin_description *d;
7900 const struct builtin_description_predicates *dp;
7902 enum insn_code icode;
7903 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7906 enum machine_mode tmode, mode0;
7907 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7909 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7910 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7913 error ("unresolved overload for Altivec builtin %qF", fndecl);
7917 target = altivec_expand_ld_builtin (exp, target, expandedp);
7921 target = altivec_expand_st_builtin (exp, target, expandedp);
7925 target = altivec_expand_dst_builtin (exp, target, expandedp);
7933 case ALTIVEC_BUILTIN_STVX:
7934 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
7935 case ALTIVEC_BUILTIN_STVEBX:
7936 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
7937 case ALTIVEC_BUILTIN_STVEHX:
7938 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
7939 case ALTIVEC_BUILTIN_STVEWX:
7940 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
7941 case ALTIVEC_BUILTIN_STVXL:
7942 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
7944 case ALTIVEC_BUILTIN_MFVSCR:
7945 icode = CODE_FOR_altivec_mfvscr;
7946 tmode = insn_data[icode].operand[0].mode;
7949 || GET_MODE (target) != tmode
7950 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7951 target = gen_reg_rtx (tmode);
7953 pat = GEN_FCN (icode) (target);
7959 case ALTIVEC_BUILTIN_MTVSCR:
7960 icode = CODE_FOR_altivec_mtvscr;
7961 arg0 = CALL_EXPR_ARG (exp, 0);
7962 op0 = expand_normal (arg0);
7963 mode0 = insn_data[icode].operand[0].mode;
7965 /* If we got invalid arguments bail out before generating bad rtl. */
7966 if (arg0 == error_mark_node)
7969 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7970 op0 = copy_to_mode_reg (mode0, op0);
7972 pat = GEN_FCN (icode) (op0);
7977 case ALTIVEC_BUILTIN_DSSALL:
7978 emit_insn (gen_altivec_dssall ());
7981 case ALTIVEC_BUILTIN_DSS:
7982 icode = CODE_FOR_altivec_dss;
7983 arg0 = CALL_EXPR_ARG (exp, 0);
7985 op0 = expand_normal (arg0);
7986 mode0 = insn_data[icode].operand[0].mode;
7988 /* If we got invalid arguments bail out before generating bad rtl. */
7989 if (arg0 == error_mark_node)
7992 if (TREE_CODE (arg0) != INTEGER_CST
7993 || TREE_INT_CST_LOW (arg0) & ~0x3)
7995 error ("argument to dss must be a 2-bit unsigned literal");
7999 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8000 op0 = copy_to_mode_reg (mode0, op0);
8002 emit_insn (gen_altivec_dss (op0));
8005 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
8006 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
8007 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
8008 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
8009 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
8011 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
8012 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
8013 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
8014 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
8015 return altivec_expand_vec_set_builtin (exp);
8017 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
8018 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
8019 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
8020 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
8021 return altivec_expand_vec_ext_builtin (exp, target);
8028 /* Expand abs* operations. */
8030 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8031 if (d->code == fcode)
8032 return altivec_expand_abs_builtin (d->icode, exp, target);
8034 /* Expand the AltiVec predicates. */
8035 dp = bdesc_altivec_preds;
8036 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8037 if (dp->code == fcode)
8038 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
8041 /* LV* are funky. We initialized them differently. */
8044 case ALTIVEC_BUILTIN_LVSL:
8045 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
8047 case ALTIVEC_BUILTIN_LVSR:
8048 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
8050 case ALTIVEC_BUILTIN_LVEBX:
8051 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
8053 case ALTIVEC_BUILTIN_LVEHX:
8054 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
8056 case ALTIVEC_BUILTIN_LVEWX:
8057 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
8059 case ALTIVEC_BUILTIN_LVXL:
8060 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
8062 case ALTIVEC_BUILTIN_LVX:
8063 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
8074 /* Binops that need to be initialized manually, but can be expanded
8075 automagically by rs6000_expand_binop_builtin. */
8076 static struct builtin_description bdesc_2arg_spe[] =
8078 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
8079 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
8080 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
8081 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
8082 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
8083 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
8084 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
8085 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
8086 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
8087 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
8088 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
8089 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
8090 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
8091 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
8092 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
8093 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
8094 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
8095 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
8096 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
8097 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
8098 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
8099 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
8102 /* Expand the builtin in EXP and store the result in TARGET. Store
8103 true in *EXPANDEDP if we found a builtin to expand.
8105 This expands the SPE builtins that are not simple unary and binary
8108 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
8110 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8112 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8113 enum insn_code icode;
8114 enum machine_mode tmode, mode0;
8116 struct builtin_description *d;
8121 /* Syntax check for a 5-bit unsigned immediate. */
8124 case SPE_BUILTIN_EVSTDD:
8125 case SPE_BUILTIN_EVSTDH:
8126 case SPE_BUILTIN_EVSTDW:
8127 case SPE_BUILTIN_EVSTWHE:
8128 case SPE_BUILTIN_EVSTWHO:
8129 case SPE_BUILTIN_EVSTWWE:
8130 case SPE_BUILTIN_EVSTWWO:
8131 arg1 = CALL_EXPR_ARG (exp, 2);
8132 if (TREE_CODE (arg1) != INTEGER_CST
8133 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8135 error ("argument 2 must be a 5-bit unsigned literal");
8143 /* The evsplat*i instructions are not quite generic. */
8146 case SPE_BUILTIN_EVSPLATFI:
8147 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8149 case SPE_BUILTIN_EVSPLATI:
8150 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8156 d = (struct builtin_description *) bdesc_2arg_spe;
8157 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8158 if (d->code == fcode)
8159 return rs6000_expand_binop_builtin (d->icode, exp, target);
8161 d = (struct builtin_description *) bdesc_spe_predicates;
8162 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8163 if (d->code == fcode)
8164 return spe_expand_predicate_builtin (d->icode, exp, target);
8166 d = (struct builtin_description *) bdesc_spe_evsel;
8167 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8168 if (d->code == fcode)
8169 return spe_expand_evsel_builtin (d->icode, exp, target);
8173 case SPE_BUILTIN_EVSTDDX:
8174 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8175 case SPE_BUILTIN_EVSTDHX:
8176 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8177 case SPE_BUILTIN_EVSTDWX:
8178 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8179 case SPE_BUILTIN_EVSTWHEX:
8180 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8181 case SPE_BUILTIN_EVSTWHOX:
8182 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8183 case SPE_BUILTIN_EVSTWWEX:
8184 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8185 case SPE_BUILTIN_EVSTWWOX:
8186 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8187 case SPE_BUILTIN_EVSTDD:
8188 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8189 case SPE_BUILTIN_EVSTDH:
8190 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8191 case SPE_BUILTIN_EVSTDW:
8192 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8193 case SPE_BUILTIN_EVSTWHE:
8194 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8195 case SPE_BUILTIN_EVSTWHO:
8196 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8197 case SPE_BUILTIN_EVSTWWE:
8198 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8199 case SPE_BUILTIN_EVSTWWO:
8200 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8201 case SPE_BUILTIN_MFSPEFSCR:
8202 icode = CODE_FOR_spe_mfspefscr;
8203 tmode = insn_data[icode].operand[0].mode;
8206 || GET_MODE (target) != tmode
8207 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8208 target = gen_reg_rtx (tmode);
8210 pat = GEN_FCN (icode) (target);
8215 case SPE_BUILTIN_MTSPEFSCR:
8216 icode = CODE_FOR_spe_mtspefscr;
8217 arg0 = CALL_EXPR_ARG (exp, 0);
8218 op0 = expand_normal (arg0);
8219 mode0 = insn_data[icode].operand[0].mode;
8221 if (arg0 == error_mark_node)
8224 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8225 op0 = copy_to_mode_reg (mode0, op0);
8227 pat = GEN_FCN (icode) (op0);
8240 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8242 rtx pat, scratch, tmp;
8243 tree form = CALL_EXPR_ARG (exp, 0);
8244 tree arg0 = CALL_EXPR_ARG (exp, 1);
8245 tree arg1 = CALL_EXPR_ARG (exp, 2);
8246 rtx op0 = expand_normal (arg0);
8247 rtx op1 = expand_normal (arg1);
8248 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8249 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8253 if (TREE_CODE (form) != INTEGER_CST)
8255 error ("argument 1 of __builtin_spe_predicate must be a constant");
8259 form_int = TREE_INT_CST_LOW (form);
8261 gcc_assert (mode0 == mode1);
8263 if (arg0 == error_mark_node || arg1 == error_mark_node)
8267 || GET_MODE (target) != SImode
8268 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8269 target = gen_reg_rtx (SImode);
8271 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8272 op0 = copy_to_mode_reg (mode0, op0);
8273 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8274 op1 = copy_to_mode_reg (mode1, op1);
8276 scratch = gen_reg_rtx (CCmode);
8278 pat = GEN_FCN (icode) (scratch, op0, op1);
8283 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8284 _lower_. We use one compare, but look in different bits of the
8285 CR for each variant.
8287 There are 2 elements in each SPE simd type (upper/lower). The CR
8288 bits are set as follows:
8290 BIT0 | BIT 1 | BIT 2 | BIT 3
8291 U | L | (U | L) | (U & L)
8293 So, for an "all" relationship, BIT 3 would be set.
8294 For an "any" relationship, BIT 2 would be set. Etc.
8296 Following traditional nomenclature, these bits map to:
8298 BIT0 | BIT 1 | BIT 2 | BIT 3
8301 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8306 /* All variant. OV bit. */
8308 /* We need to get to the OV bit, which is the ORDERED bit. We
8309 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8310 that's ugly and will make validate_condition_mode die.
8311 So let's just use another pattern. */
8312 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8314 /* Any variant. EQ bit. */
8318 /* Upper variant. LT bit. */
8322 /* Lower variant. GT bit. */
8327 error ("argument 1 of __builtin_spe_predicate is out of range");
8331 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8332 emit_move_insn (target, tmp);
8337 /* The evsel builtins look like this:
8339 e = __builtin_spe_evsel_OP (a, b, c, d);
8343 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8344 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8348 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8351 tree arg0 = CALL_EXPR_ARG (exp, 0);
8352 tree arg1 = CALL_EXPR_ARG (exp, 1);
8353 tree arg2 = CALL_EXPR_ARG (exp, 2);
8354 tree arg3 = CALL_EXPR_ARG (exp, 3);
8355 rtx op0 = expand_normal (arg0);
8356 rtx op1 = expand_normal (arg1);
8357 rtx op2 = expand_normal (arg2);
8358 rtx op3 = expand_normal (arg3);
8359 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8360 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8362 gcc_assert (mode0 == mode1);
8364 if (arg0 == error_mark_node || arg1 == error_mark_node
8365 || arg2 == error_mark_node || arg3 == error_mark_node)
8369 || GET_MODE (target) != mode0
8370 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8371 target = gen_reg_rtx (mode0);
8373 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8374 op0 = copy_to_mode_reg (mode0, op0);
8375 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8376 op1 = copy_to_mode_reg (mode0, op1);
8377 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8378 op2 = copy_to_mode_reg (mode0, op2);
8379 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8380 op3 = copy_to_mode_reg (mode0, op3);
8382 /* Generate the compare. */
8383 scratch = gen_reg_rtx (CCmode);
8384 pat = GEN_FCN (icode) (scratch, op0, op1);
8389 if (mode0 == V2SImode)
8390 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8392 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8397 /* Expand an expression EXP that calls a built-in function,
8398 with result going to TARGET if that's convenient
8399 (and in mode MODE if that's convenient).
8400 SUBTARGET may be used as the target for computing one of EXP's operands.
8401 IGNORE is nonzero if the value is to be ignored. */
8404 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8405 enum machine_mode mode ATTRIBUTE_UNUSED,
8406 int ignore ATTRIBUTE_UNUSED)
8408 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8409 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8410 const struct builtin_description *d;
8415 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8416 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8418 int icode = (int) CODE_FOR_altivec_lvsr;
8419 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8420 enum machine_mode mode = insn_data[icode].operand[1].mode;
8424 gcc_assert (TARGET_ALTIVEC);
8426 arg = CALL_EXPR_ARG (exp, 0);
8427 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8428 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8429 addr = memory_address (mode, op);
8430 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8434 /* For the load case need to negate the address. */
8435 op = gen_reg_rtx (GET_MODE (addr));
8436 emit_insn (gen_rtx_SET (VOIDmode, op,
8437 gen_rtx_NEG (GET_MODE (addr), addr)));
8439 op = gen_rtx_MEM (mode, op);
8442 || GET_MODE (target) != tmode
8443 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8444 target = gen_reg_rtx (tmode);
8446 /*pat = gen_altivec_lvsr (target, op);*/
8447 pat = GEN_FCN (icode) (target, op);
8455 /* FIXME: There's got to be a nicer way to handle this case than
8456 constructing a new CALL_EXPR. */
8457 if (fcode == ALTIVEC_BUILTIN_VCFUX
8458 || fcode == ALTIVEC_BUILTIN_VCFSX)
8460 if (call_expr_nargs (exp) == 1)
8461 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
8462 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
8467 ret = altivec_expand_builtin (exp, target, &success);
8474 ret = spe_expand_builtin (exp, target, &success);
8480 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
8482 /* Handle simple unary operations. */
8483 d = (struct builtin_description *) bdesc_1arg;
8484 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8485 if (d->code == fcode)
8486 return rs6000_expand_unop_builtin (d->icode, exp, target);
8488 /* Handle simple binary operations. */
8489 d = (struct builtin_description *) bdesc_2arg;
8490 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8491 if (d->code == fcode)
8492 return rs6000_expand_binop_builtin (d->icode, exp, target);
8494 /* Handle simple ternary operations. */
8496 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8497 if (d->code == fcode)
8498 return rs6000_expand_ternop_builtin (d->icode, exp, target);
8504 build_opaque_vector_type (tree node, int nunits)
8506 node = copy_node (node);
8507 TYPE_MAIN_VARIANT (node) = node;
8508 return build_vector_type (node, nunits);
8512 rs6000_init_builtins (void)
8514 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8515 V2SF_type_node = build_vector_type (float_type_node, 2);
8516 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8517 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8518 V4SF_type_node = build_vector_type (float_type_node, 4);
8519 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8520 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8522 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8523 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8524 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8526 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8527 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8528 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8529 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8531 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8532 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8533 'vector unsigned short'. */
8535 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8536 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8537 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8538 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8540 long_integer_type_internal_node = long_integer_type_node;
8541 long_unsigned_type_internal_node = long_unsigned_type_node;
8542 intQI_type_internal_node = intQI_type_node;
8543 uintQI_type_internal_node = unsigned_intQI_type_node;
8544 intHI_type_internal_node = intHI_type_node;
8545 uintHI_type_internal_node = unsigned_intHI_type_node;
8546 intSI_type_internal_node = intSI_type_node;
8547 uintSI_type_internal_node = unsigned_intSI_type_node;
8548 float_type_internal_node = float_type_node;
8549 void_type_internal_node = void_type_node;
8551 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8552 get_identifier ("__bool char"),
8553 bool_char_type_node));
8554 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8555 get_identifier ("__bool short"),
8556 bool_short_type_node));
8557 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8558 get_identifier ("__bool int"),
8559 bool_int_type_node));
8560 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8561 get_identifier ("__pixel"),
8564 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8565 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8566 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8567 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8569 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8570 get_identifier ("__vector unsigned char"),
8571 unsigned_V16QI_type_node));
8572 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8573 get_identifier ("__vector signed char"),
8575 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8576 get_identifier ("__vector __bool char"),
8577 bool_V16QI_type_node));
8579 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8580 get_identifier ("__vector unsigned short"),
8581 unsigned_V8HI_type_node));
8582 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8583 get_identifier ("__vector signed short"),
8585 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8586 get_identifier ("__vector __bool short"),
8587 bool_V8HI_type_node));
8589 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8590 get_identifier ("__vector unsigned int"),
8591 unsigned_V4SI_type_node));
8592 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8593 get_identifier ("__vector signed int"),
8595 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8596 get_identifier ("__vector __bool int"),
8597 bool_V4SI_type_node));
8599 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8600 get_identifier ("__vector float"),
8602 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8603 get_identifier ("__vector __pixel"),
8604 pixel_V8HI_type_node));
8607 spe_init_builtins ();
8609 altivec_init_builtins ();
8610 if (TARGET_ALTIVEC || TARGET_SPE)
8611 rs6000_common_init_builtins ();
8614 /* AIX libm provides clog as __clog. */
8615 if (built_in_decls [BUILT_IN_CLOG])
8616 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8620 /* Search through a set of builtins and enable the mask bits.
8621 DESC is an array of builtins.
8622 SIZE is the total number of builtins.
8623 START is the builtin enum at which to start.
8624 END is the builtin enum at which to end. */
8626 enable_mask_for_builtins (struct builtin_description *desc, int size,
8627 enum rs6000_builtins start,
8628 enum rs6000_builtins end)
8632 for (i = 0; i < size; ++i)
8633 if (desc[i].code == start)
8639 for (; i < size; ++i)
8641 /* Flip all the bits on. */
8642 desc[i].mask = target_flags;
8643 if (desc[i].code == end)
8649 spe_init_builtins (void)
8651 tree endlink = void_list_node;
8652 tree puint_type_node = build_pointer_type (unsigned_type_node);
8653 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8654 struct builtin_description *d;
8657 tree v2si_ftype_4_v2si
8658 = build_function_type
8659 (opaque_V2SI_type_node,
8660 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8661 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8662 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8663 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8666 tree v2sf_ftype_4_v2sf
8667 = build_function_type
8668 (opaque_V2SF_type_node,
8669 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8670 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8671 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8672 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8675 tree int_ftype_int_v2si_v2si
8676 = build_function_type
8678 tree_cons (NULL_TREE, integer_type_node,
8679 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8680 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8683 tree int_ftype_int_v2sf_v2sf
8684 = build_function_type
8686 tree_cons (NULL_TREE, integer_type_node,
8687 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8688 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8691 tree void_ftype_v2si_puint_int
8692 = build_function_type (void_type_node,
8693 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8694 tree_cons (NULL_TREE, puint_type_node,
8695 tree_cons (NULL_TREE,
8699 tree void_ftype_v2si_puint_char
8700 = build_function_type (void_type_node,
8701 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8702 tree_cons (NULL_TREE, puint_type_node,
8703 tree_cons (NULL_TREE,
8707 tree void_ftype_v2si_pv2si_int
8708 = build_function_type (void_type_node,
8709 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8710 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8711 tree_cons (NULL_TREE,
8715 tree void_ftype_v2si_pv2si_char
8716 = build_function_type (void_type_node,
8717 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8718 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8719 tree_cons (NULL_TREE,
8724 = build_function_type (void_type_node,
8725 tree_cons (NULL_TREE, integer_type_node, endlink));
8728 = build_function_type (integer_type_node, endlink);
8730 tree v2si_ftype_pv2si_int
8731 = build_function_type (opaque_V2SI_type_node,
8732 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8733 tree_cons (NULL_TREE, integer_type_node,
8736 tree v2si_ftype_puint_int
8737 = build_function_type (opaque_V2SI_type_node,
8738 tree_cons (NULL_TREE, puint_type_node,
8739 tree_cons (NULL_TREE, integer_type_node,
8742 tree v2si_ftype_pushort_int
8743 = build_function_type (opaque_V2SI_type_node,
8744 tree_cons (NULL_TREE, pushort_type_node,
8745 tree_cons (NULL_TREE, integer_type_node,
8748 tree v2si_ftype_signed_char
8749 = build_function_type (opaque_V2SI_type_node,
8750 tree_cons (NULL_TREE, signed_char_type_node,
8753 /* The initialization of the simple binary and unary builtins is
8754 done in rs6000_common_init_builtins, but we have to enable the
8755 mask bits here manually because we have run out of `target_flags'
8756 bits. We really need to redesign this mask business. */
8758 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8759 ARRAY_SIZE (bdesc_2arg),
8762 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8763 ARRAY_SIZE (bdesc_1arg),
8765 SPE_BUILTIN_EVSUBFUSIAAW);
8766 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8767 ARRAY_SIZE (bdesc_spe_predicates),
8768 SPE_BUILTIN_EVCMPEQ,
8769 SPE_BUILTIN_EVFSTSTLT);
8770 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8771 ARRAY_SIZE (bdesc_spe_evsel),
8772 SPE_BUILTIN_EVSEL_CMPGTS,
8773 SPE_BUILTIN_EVSEL_FSTSTEQ);
8775 (*lang_hooks.decls.pushdecl)
8776 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8777 opaque_V2SI_type_node));
8779 /* Initialize irregular SPE builtins. */
8781 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8782 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8783 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8784 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8785 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8786 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8787 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8788 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8789 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8790 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8791 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8792 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8793 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8794 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8795 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8796 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8797 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8798 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8801 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8802 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8803 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8804 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8805 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8806 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8807 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8808 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8809 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8810 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8811 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8812 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8813 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8814 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8815 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8816 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8817 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8818 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8819 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8820 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8821 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8822 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8825 d = (struct builtin_description *) bdesc_spe_predicates;
8826 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8830 switch (insn_data[d->icode].operand[1].mode)
8833 type = int_ftype_int_v2si_v2si;
8836 type = int_ftype_int_v2sf_v2sf;
8842 def_builtin (d->mask, d->name, type, d->code);
8845 /* Evsel predicates. */
8846 d = (struct builtin_description *) bdesc_spe_evsel;
8847 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8851 switch (insn_data[d->icode].operand[1].mode)
8854 type = v2si_ftype_4_v2si;
8857 type = v2sf_ftype_4_v2sf;
8863 def_builtin (d->mask, d->name, type, d->code);
8868 altivec_init_builtins (void)
8870 const struct builtin_description *d;
8871 const struct builtin_description_predicates *dp;
8875 tree pfloat_type_node = build_pointer_type (float_type_node);
8876 tree pint_type_node = build_pointer_type (integer_type_node);
8877 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8878 tree pchar_type_node = build_pointer_type (char_type_node);
8880 tree pvoid_type_node = build_pointer_type (void_type_node);
8882 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8883 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8884 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8885 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8887 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8889 tree int_ftype_opaque
8890 = build_function_type_list (integer_type_node,
8891 opaque_V4SI_type_node, NULL_TREE);
8893 tree opaque_ftype_opaque_int
8894 = build_function_type_list (opaque_V4SI_type_node,
8895 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8896 tree opaque_ftype_opaque_opaque_int
8897 = build_function_type_list (opaque_V4SI_type_node,
8898 opaque_V4SI_type_node, opaque_V4SI_type_node,
8899 integer_type_node, NULL_TREE);
8900 tree int_ftype_int_opaque_opaque
8901 = build_function_type_list (integer_type_node,
8902 integer_type_node, opaque_V4SI_type_node,
8903 opaque_V4SI_type_node, NULL_TREE);
8904 tree int_ftype_int_v4si_v4si
8905 = build_function_type_list (integer_type_node,
8906 integer_type_node, V4SI_type_node,
8907 V4SI_type_node, NULL_TREE);
8908 tree v4sf_ftype_pcfloat
8909 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8910 tree void_ftype_pfloat_v4sf
8911 = build_function_type_list (void_type_node,
8912 pfloat_type_node, V4SF_type_node, NULL_TREE);
8913 tree v4si_ftype_pcint
8914 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8915 tree void_ftype_pint_v4si
8916 = build_function_type_list (void_type_node,
8917 pint_type_node, V4SI_type_node, NULL_TREE);
8918 tree v8hi_ftype_pcshort
8919 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8920 tree void_ftype_pshort_v8hi
8921 = build_function_type_list (void_type_node,
8922 pshort_type_node, V8HI_type_node, NULL_TREE);
8923 tree v16qi_ftype_pcchar
8924 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8925 tree void_ftype_pchar_v16qi
8926 = build_function_type_list (void_type_node,
8927 pchar_type_node, V16QI_type_node, NULL_TREE);
8928 tree void_ftype_v4si
8929 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8930 tree v8hi_ftype_void
8931 = build_function_type (V8HI_type_node, void_list_node);
8932 tree void_ftype_void
8933 = build_function_type (void_type_node, void_list_node);
8935 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8937 tree opaque_ftype_long_pcvoid
8938 = build_function_type_list (opaque_V4SI_type_node,
8939 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8940 tree v16qi_ftype_long_pcvoid
8941 = build_function_type_list (V16QI_type_node,
8942 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8943 tree v8hi_ftype_long_pcvoid
8944 = build_function_type_list (V8HI_type_node,
8945 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8946 tree v4si_ftype_long_pcvoid
8947 = build_function_type_list (V4SI_type_node,
8948 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8950 tree void_ftype_opaque_long_pvoid
8951 = build_function_type_list (void_type_node,
8952 opaque_V4SI_type_node, long_integer_type_node,
8953 pvoid_type_node, NULL_TREE);
8954 tree void_ftype_v4si_long_pvoid
8955 = build_function_type_list (void_type_node,
8956 V4SI_type_node, long_integer_type_node,
8957 pvoid_type_node, NULL_TREE);
8958 tree void_ftype_v16qi_long_pvoid
8959 = build_function_type_list (void_type_node,
8960 V16QI_type_node, long_integer_type_node,
8961 pvoid_type_node, NULL_TREE);
8962 tree void_ftype_v8hi_long_pvoid
8963 = build_function_type_list (void_type_node,
8964 V8HI_type_node, long_integer_type_node,
8965 pvoid_type_node, NULL_TREE);
8966 tree int_ftype_int_v8hi_v8hi
8967 = build_function_type_list (integer_type_node,
8968 integer_type_node, V8HI_type_node,
8969 V8HI_type_node, NULL_TREE);
8970 tree int_ftype_int_v16qi_v16qi
8971 = build_function_type_list (integer_type_node,
8972 integer_type_node, V16QI_type_node,
8973 V16QI_type_node, NULL_TREE);
8974 tree int_ftype_int_v4sf_v4sf
8975 = build_function_type_list (integer_type_node,
8976 integer_type_node, V4SF_type_node,
8977 V4SF_type_node, NULL_TREE);
8978 tree v4si_ftype_v4si
8979 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8980 tree v8hi_ftype_v8hi
8981 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8982 tree v16qi_ftype_v16qi
8983 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8984 tree v4sf_ftype_v4sf
8985 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8986 tree void_ftype_pcvoid_int_int
8987 = build_function_type_list (void_type_node,
8988 pcvoid_type_node, integer_type_node,
8989 integer_type_node, NULL_TREE);
8991 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8992 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8993 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8994 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8995 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8996 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8997 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8998 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8999 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
9000 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
9001 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
9002 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
9003 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
9004 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
9005 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
9006 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
9007 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
9008 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
9009 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
9010 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
9011 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
9012 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
9013 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
9014 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
9015 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
9016 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
9017 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
9018 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
9019 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
9020 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
9021 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
9022 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
9023 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
9024 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
9025 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
9026 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
9027 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
9028 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
9029 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
9030 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
9031 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
9032 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
9033 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
9034 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
9035 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
9036 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
9038 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
9040 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
9041 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
9042 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
9043 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
9044 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
9045 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
9046 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
9047 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
9048 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
9049 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
9051 /* Add the DST variants. */
9053 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
9054 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
9056 /* Initialize the predicates. */
9057 dp = bdesc_altivec_preds;
9058 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
9060 enum machine_mode mode1;
9062 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9063 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9068 mode1 = insn_data[dp->icode].operand[1].mode;
9073 type = int_ftype_int_opaque_opaque;
9076 type = int_ftype_int_v4si_v4si;
9079 type = int_ftype_int_v8hi_v8hi;
9082 type = int_ftype_int_v16qi_v16qi;
9085 type = int_ftype_int_v4sf_v4sf;
9091 def_builtin (dp->mask, dp->name, type, dp->code);
9094 /* Initialize the abs* operators. */
9096 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
9098 enum machine_mode mode0;
9101 mode0 = insn_data[d->icode].operand[0].mode;
9106 type = v4si_ftype_v4si;
9109 type = v8hi_ftype_v8hi;
9112 type = v16qi_ftype_v16qi;
9115 type = v4sf_ftype_v4sf;
9121 def_builtin (d->mask, d->name, type, d->code);
9128 /* Initialize target builtin that implements
9129 targetm.vectorize.builtin_mask_for_load. */
9131 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
9132 v16qi_ftype_long_pcvoid,
9133 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
9134 BUILT_IN_MD, NULL, NULL_TREE);
9135 TREE_READONLY (decl) = 1;
9136 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9137 altivec_builtin_mask_for_load = decl;
9140 /* Access to the vec_init patterns. */
9141 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
9142 integer_type_node, integer_type_node,
9143 integer_type_node, NULL_TREE);
9144 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
9145 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
9147 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
9148 short_integer_type_node,
9149 short_integer_type_node,
9150 short_integer_type_node,
9151 short_integer_type_node,
9152 short_integer_type_node,
9153 short_integer_type_node,
9154 short_integer_type_node, NULL_TREE);
9155 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
9156 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
9158 ftype = build_function_type_list (V16QI_type_node, char_type_node,
9159 char_type_node, char_type_node,
9160 char_type_node, char_type_node,
9161 char_type_node, char_type_node,
9162 char_type_node, char_type_node,
9163 char_type_node, char_type_node,
9164 char_type_node, char_type_node,
9165 char_type_node, char_type_node,
9166 char_type_node, NULL_TREE);
9167 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9168 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9170 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9171 float_type_node, float_type_node,
9172 float_type_node, NULL_TREE);
9173 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9174 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9176 /* Access to the vec_set patterns. */
9177 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9179 integer_type_node, NULL_TREE);
9180 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9181 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9183 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9185 integer_type_node, NULL_TREE);
9186 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9187 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9189 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9191 integer_type_node, NULL_TREE);
9192 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9193 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9195 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9197 integer_type_node, NULL_TREE);
9198 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9199 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9201 /* Access to the vec_extract patterns. */
9202 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9203 integer_type_node, NULL_TREE);
9204 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9205 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9207 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9208 integer_type_node, NULL_TREE);
9209 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9210 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9212 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9213 integer_type_node, NULL_TREE);
9214 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9215 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9217 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9218 integer_type_node, NULL_TREE);
9219 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9220 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9224 rs6000_common_init_builtins (void)
9226 const struct builtin_description *d;
9229 tree v4sf_ftype_v4sf_v4sf_v16qi
9230 = build_function_type_list (V4SF_type_node,
9231 V4SF_type_node, V4SF_type_node,
9232 V16QI_type_node, NULL_TREE);
9233 tree v4si_ftype_v4si_v4si_v16qi
9234 = build_function_type_list (V4SI_type_node,
9235 V4SI_type_node, V4SI_type_node,
9236 V16QI_type_node, NULL_TREE);
9237 tree v8hi_ftype_v8hi_v8hi_v16qi
9238 = build_function_type_list (V8HI_type_node,
9239 V8HI_type_node, V8HI_type_node,
9240 V16QI_type_node, NULL_TREE);
9241 tree v16qi_ftype_v16qi_v16qi_v16qi
9242 = build_function_type_list (V16QI_type_node,
9243 V16QI_type_node, V16QI_type_node,
9244 V16QI_type_node, NULL_TREE);
9246 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9248 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9249 tree v16qi_ftype_int
9250 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9251 tree v8hi_ftype_v16qi
9252 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9253 tree v4sf_ftype_v4sf
9254 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9256 tree v2si_ftype_v2si_v2si
9257 = build_function_type_list (opaque_V2SI_type_node,
9258 opaque_V2SI_type_node,
9259 opaque_V2SI_type_node, NULL_TREE);
9261 tree v2sf_ftype_v2sf_v2sf
9262 = build_function_type_list (opaque_V2SF_type_node,
9263 opaque_V2SF_type_node,
9264 opaque_V2SF_type_node, NULL_TREE);
9266 tree v2si_ftype_int_int
9267 = build_function_type_list (opaque_V2SI_type_node,
9268 integer_type_node, integer_type_node,
9271 tree opaque_ftype_opaque
9272 = build_function_type_list (opaque_V4SI_type_node,
9273 opaque_V4SI_type_node, NULL_TREE);
9275 tree v2si_ftype_v2si
9276 = build_function_type_list (opaque_V2SI_type_node,
9277 opaque_V2SI_type_node, NULL_TREE);
9279 tree v2sf_ftype_v2sf
9280 = build_function_type_list (opaque_V2SF_type_node,
9281 opaque_V2SF_type_node, NULL_TREE);
9283 tree v2sf_ftype_v2si
9284 = build_function_type_list (opaque_V2SF_type_node,
9285 opaque_V2SI_type_node, NULL_TREE);
9287 tree v2si_ftype_v2sf
9288 = build_function_type_list (opaque_V2SI_type_node,
9289 opaque_V2SF_type_node, NULL_TREE);
9291 tree v2si_ftype_v2si_char
9292 = build_function_type_list (opaque_V2SI_type_node,
9293 opaque_V2SI_type_node,
9294 char_type_node, NULL_TREE);
9296 tree v2si_ftype_int_char
9297 = build_function_type_list (opaque_V2SI_type_node,
9298 integer_type_node, char_type_node, NULL_TREE);
9300 tree v2si_ftype_char
9301 = build_function_type_list (opaque_V2SI_type_node,
9302 char_type_node, NULL_TREE);
9304 tree int_ftype_int_int
9305 = build_function_type_list (integer_type_node,
9306 integer_type_node, integer_type_node,
9309 tree opaque_ftype_opaque_opaque
9310 = build_function_type_list (opaque_V4SI_type_node,
9311 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9312 tree v4si_ftype_v4si_v4si
9313 = build_function_type_list (V4SI_type_node,
9314 V4SI_type_node, V4SI_type_node, NULL_TREE);
9315 tree v4sf_ftype_v4si_int
9316 = build_function_type_list (V4SF_type_node,
9317 V4SI_type_node, integer_type_node, NULL_TREE);
9318 tree v4si_ftype_v4sf_int
9319 = build_function_type_list (V4SI_type_node,
9320 V4SF_type_node, integer_type_node, NULL_TREE);
9321 tree v4si_ftype_v4si_int
9322 = build_function_type_list (V4SI_type_node,
9323 V4SI_type_node, integer_type_node, NULL_TREE);
9324 tree v8hi_ftype_v8hi_int
9325 = build_function_type_list (V8HI_type_node,
9326 V8HI_type_node, integer_type_node, NULL_TREE);
9327 tree v16qi_ftype_v16qi_int
9328 = build_function_type_list (V16QI_type_node,
9329 V16QI_type_node, integer_type_node, NULL_TREE);
9330 tree v16qi_ftype_v16qi_v16qi_int
9331 = build_function_type_list (V16QI_type_node,
9332 V16QI_type_node, V16QI_type_node,
9333 integer_type_node, NULL_TREE);
9334 tree v8hi_ftype_v8hi_v8hi_int
9335 = build_function_type_list (V8HI_type_node,
9336 V8HI_type_node, V8HI_type_node,
9337 integer_type_node, NULL_TREE);
9338 tree v4si_ftype_v4si_v4si_int
9339 = build_function_type_list (V4SI_type_node,
9340 V4SI_type_node, V4SI_type_node,
9341 integer_type_node, NULL_TREE);
9342 tree v4sf_ftype_v4sf_v4sf_int
9343 = build_function_type_list (V4SF_type_node,
9344 V4SF_type_node, V4SF_type_node,
9345 integer_type_node, NULL_TREE);
9346 tree v4sf_ftype_v4sf_v4sf
9347 = build_function_type_list (V4SF_type_node,
9348 V4SF_type_node, V4SF_type_node, NULL_TREE);
9349 tree opaque_ftype_opaque_opaque_opaque
9350 = build_function_type_list (opaque_V4SI_type_node,
9351 opaque_V4SI_type_node, opaque_V4SI_type_node,
9352 opaque_V4SI_type_node, NULL_TREE);
9353 tree v4sf_ftype_v4sf_v4sf_v4si
9354 = build_function_type_list (V4SF_type_node,
9355 V4SF_type_node, V4SF_type_node,
9356 V4SI_type_node, NULL_TREE);
9357 tree v4sf_ftype_v4sf_v4sf_v4sf
9358 = build_function_type_list (V4SF_type_node,
9359 V4SF_type_node, V4SF_type_node,
9360 V4SF_type_node, NULL_TREE);
9361 tree v4si_ftype_v4si_v4si_v4si
9362 = build_function_type_list (V4SI_type_node,
9363 V4SI_type_node, V4SI_type_node,
9364 V4SI_type_node, NULL_TREE);
9365 tree v8hi_ftype_v8hi_v8hi
9366 = build_function_type_list (V8HI_type_node,
9367 V8HI_type_node, V8HI_type_node, NULL_TREE);
9368 tree v8hi_ftype_v8hi_v8hi_v8hi
9369 = build_function_type_list (V8HI_type_node,
9370 V8HI_type_node, V8HI_type_node,
9371 V8HI_type_node, NULL_TREE);
9372 tree v4si_ftype_v8hi_v8hi_v4si
9373 = build_function_type_list (V4SI_type_node,
9374 V8HI_type_node, V8HI_type_node,
9375 V4SI_type_node, NULL_TREE);
9376 tree v4si_ftype_v16qi_v16qi_v4si
9377 = build_function_type_list (V4SI_type_node,
9378 V16QI_type_node, V16QI_type_node,
9379 V4SI_type_node, NULL_TREE);
9380 tree v16qi_ftype_v16qi_v16qi
9381 = build_function_type_list (V16QI_type_node,
9382 V16QI_type_node, V16QI_type_node, NULL_TREE);
9383 tree v4si_ftype_v4sf_v4sf
9384 = build_function_type_list (V4SI_type_node,
9385 V4SF_type_node, V4SF_type_node, NULL_TREE);
9386 tree v8hi_ftype_v16qi_v16qi
9387 = build_function_type_list (V8HI_type_node,
9388 V16QI_type_node, V16QI_type_node, NULL_TREE);
9389 tree v4si_ftype_v8hi_v8hi
9390 = build_function_type_list (V4SI_type_node,
9391 V8HI_type_node, V8HI_type_node, NULL_TREE);
9392 tree v8hi_ftype_v4si_v4si
9393 = build_function_type_list (V8HI_type_node,
9394 V4SI_type_node, V4SI_type_node, NULL_TREE);
9395 tree v16qi_ftype_v8hi_v8hi
9396 = build_function_type_list (V16QI_type_node,
9397 V8HI_type_node, V8HI_type_node, NULL_TREE);
9398 tree v4si_ftype_v16qi_v4si
9399 = build_function_type_list (V4SI_type_node,
9400 V16QI_type_node, V4SI_type_node, NULL_TREE);
9401 tree v4si_ftype_v16qi_v16qi
9402 = build_function_type_list (V4SI_type_node,
9403 V16QI_type_node, V16QI_type_node, NULL_TREE);
9404 tree v4si_ftype_v8hi_v4si
9405 = build_function_type_list (V4SI_type_node,
9406 V8HI_type_node, V4SI_type_node, NULL_TREE);
9407 tree v4si_ftype_v8hi
9408 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9409 tree int_ftype_v4si_v4si
9410 = build_function_type_list (integer_type_node,
9411 V4SI_type_node, V4SI_type_node, NULL_TREE);
9412 tree int_ftype_v4sf_v4sf
9413 = build_function_type_list (integer_type_node,
9414 V4SF_type_node, V4SF_type_node, NULL_TREE);
9415 tree int_ftype_v16qi_v16qi
9416 = build_function_type_list (integer_type_node,
9417 V16QI_type_node, V16QI_type_node, NULL_TREE);
9418 tree int_ftype_v8hi_v8hi
9419 = build_function_type_list (integer_type_node,
9420 V8HI_type_node, V8HI_type_node, NULL_TREE);
9422 /* Add the simple ternary operators. */
9424 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9426 enum machine_mode mode0, mode1, mode2, mode3;
9428 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9429 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9440 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9443 mode0 = insn_data[d->icode].operand[0].mode;
9444 mode1 = insn_data[d->icode].operand[1].mode;
9445 mode2 = insn_data[d->icode].operand[2].mode;
9446 mode3 = insn_data[d->icode].operand[3].mode;
9449 /* When all four are of the same mode. */
9450 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9455 type = opaque_ftype_opaque_opaque_opaque;
9458 type = v4si_ftype_v4si_v4si_v4si;
9461 type = v4sf_ftype_v4sf_v4sf_v4sf;
9464 type = v8hi_ftype_v8hi_v8hi_v8hi;
9467 type = v16qi_ftype_v16qi_v16qi_v16qi;
9473 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9478 type = v4si_ftype_v4si_v4si_v16qi;
9481 type = v4sf_ftype_v4sf_v4sf_v16qi;
9484 type = v8hi_ftype_v8hi_v8hi_v16qi;
9487 type = v16qi_ftype_v16qi_v16qi_v16qi;
9493 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9494 && mode3 == V4SImode)
9495 type = v4si_ftype_v16qi_v16qi_v4si;
9496 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9497 && mode3 == V4SImode)
9498 type = v4si_ftype_v8hi_v8hi_v4si;
9499 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9500 && mode3 == V4SImode)
9501 type = v4sf_ftype_v4sf_v4sf_v4si;
9503 /* vchar, vchar, vchar, 4-bit literal. */
9504 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9506 type = v16qi_ftype_v16qi_v16qi_int;
9508 /* vshort, vshort, vshort, 4-bit literal. */
9509 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9511 type = v8hi_ftype_v8hi_v8hi_int;
9513 /* vint, vint, vint, 4-bit literal. */
9514 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9516 type = v4si_ftype_v4si_v4si_int;
9518 /* vfloat, vfloat, vfloat, 4-bit literal. */
9519 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9521 type = v4sf_ftype_v4sf_v4sf_int;
9526 def_builtin (d->mask, d->name, type, d->code);
9529 /* Add the simple binary operators. */
9530 d = (struct builtin_description *) bdesc_2arg;
9531 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9533 enum machine_mode mode0, mode1, mode2;
9535 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9536 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9546 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9549 mode0 = insn_data[d->icode].operand[0].mode;
9550 mode1 = insn_data[d->icode].operand[1].mode;
9551 mode2 = insn_data[d->icode].operand[2].mode;
9554 /* When all three operands are of the same mode. */
9555 if (mode0 == mode1 && mode1 == mode2)
9560 type = opaque_ftype_opaque_opaque;
9563 type = v4sf_ftype_v4sf_v4sf;
9566 type = v4si_ftype_v4si_v4si;
9569 type = v16qi_ftype_v16qi_v16qi;
9572 type = v8hi_ftype_v8hi_v8hi;
9575 type = v2si_ftype_v2si_v2si;
9578 type = v2sf_ftype_v2sf_v2sf;
9581 type = int_ftype_int_int;
9588 /* A few other combos we really don't want to do manually. */
9590 /* vint, vfloat, vfloat. */
9591 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9592 type = v4si_ftype_v4sf_v4sf;
9594 /* vshort, vchar, vchar. */
9595 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9596 type = v8hi_ftype_v16qi_v16qi;
9598 /* vint, vshort, vshort. */
9599 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9600 type = v4si_ftype_v8hi_v8hi;
9602 /* vshort, vint, vint. */
9603 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9604 type = v8hi_ftype_v4si_v4si;
9606 /* vchar, vshort, vshort. */
9607 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9608 type = v16qi_ftype_v8hi_v8hi;
9610 /* vint, vchar, vint. */
9611 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9612 type = v4si_ftype_v16qi_v4si;
9614 /* vint, vchar, vchar. */
9615 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9616 type = v4si_ftype_v16qi_v16qi;
9618 /* vint, vshort, vint. */
9619 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9620 type = v4si_ftype_v8hi_v4si;
9622 /* vint, vint, 5-bit literal. */
9623 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9624 type = v4si_ftype_v4si_int;
9626 /* vshort, vshort, 5-bit literal. */
9627 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9628 type = v8hi_ftype_v8hi_int;
9630 /* vchar, vchar, 5-bit literal. */
9631 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9632 type = v16qi_ftype_v16qi_int;
9634 /* vfloat, vint, 5-bit literal. */
9635 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9636 type = v4sf_ftype_v4si_int;
9638 /* vint, vfloat, 5-bit literal. */
9639 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9640 type = v4si_ftype_v4sf_int;
9642 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9643 type = v2si_ftype_int_int;
9645 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9646 type = v2si_ftype_v2si_char;
9648 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9649 type = v2si_ftype_int_char;
9654 gcc_assert (mode0 == SImode);
9658 type = int_ftype_v4si_v4si;
9661 type = int_ftype_v4sf_v4sf;
9664 type = int_ftype_v16qi_v16qi;
9667 type = int_ftype_v8hi_v8hi;
9674 def_builtin (d->mask, d->name, type, d->code);
9677 /* Add the simple unary operators. */
9678 d = (struct builtin_description *) bdesc_1arg;
9679 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9681 enum machine_mode mode0, mode1;
9683 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9684 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9693 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9696 mode0 = insn_data[d->icode].operand[0].mode;
9697 mode1 = insn_data[d->icode].operand[1].mode;
9700 if (mode0 == V4SImode && mode1 == QImode)
9701 type = v4si_ftype_int;
9702 else if (mode0 == V8HImode && mode1 == QImode)
9703 type = v8hi_ftype_int;
9704 else if (mode0 == V16QImode && mode1 == QImode)
9705 type = v16qi_ftype_int;
9706 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9707 type = opaque_ftype_opaque;
9708 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9709 type = v4sf_ftype_v4sf;
9710 else if (mode0 == V8HImode && mode1 == V16QImode)
9711 type = v8hi_ftype_v16qi;
9712 else if (mode0 == V4SImode && mode1 == V8HImode)
9713 type = v4si_ftype_v8hi;
9714 else if (mode0 == V2SImode && mode1 == V2SImode)
9715 type = v2si_ftype_v2si;
9716 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9717 type = v2sf_ftype_v2sf;
9718 else if (mode0 == V2SFmode && mode1 == V2SImode)
9719 type = v2sf_ftype_v2si;
9720 else if (mode0 == V2SImode && mode1 == V2SFmode)
9721 type = v2si_ftype_v2sf;
9722 else if (mode0 == V2SImode && mode1 == QImode)
9723 type = v2si_ftype_char;
9727 def_builtin (d->mask, d->name, type, d->code);
9732 rs6000_init_libfuncs (void)
9734 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9735 && !TARGET_POWER2 && !TARGET_POWERPC)
9737 /* AIX library routines for float->int conversion. */
9738 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9739 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9740 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9741 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9744 if (!TARGET_IEEEQUAD)
9745 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9746 if (!TARGET_XL_COMPAT)
9748 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9749 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9750 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9751 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9753 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
9755 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
9756 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
9757 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
9758 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
9759 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
9760 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
9761 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
9763 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
9764 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
9765 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
9766 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
9767 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
9768 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
9769 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
9770 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
9773 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
9774 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
9778 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9779 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9780 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9781 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9785 /* 32-bit SVR4 quad floating point routines. */
9787 set_optab_libfunc (add_optab, TFmode, "_q_add");
9788 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9789 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9790 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9791 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9792 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9793 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9795 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9796 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9797 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9798 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9799 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9800 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9802 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9803 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9804 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9805 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9806 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9807 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9808 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9809 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9814 /* Expand a block clear operation, and return 1 if successful. Return 0
9815 if we should let the compiler generate normal code.
9817 operands[0] is the destination
9818 operands[1] is the length
9819 operands[3] is the alignment */
9822 expand_block_clear (rtx operands[])
9824 rtx orig_dest = operands[0];
9825 rtx bytes_rtx = operands[1];
9826 rtx align_rtx = operands[3];
9827 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9828 HOST_WIDE_INT align;
9829 HOST_WIDE_INT bytes;
9834 /* If this is not a fixed size move, just call memcpy */
9838 /* This must be a fixed size alignment */
9839 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9840 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9842 /* Anything to clear? */
9843 bytes = INTVAL (bytes_rtx);
9847 /* Use the builtin memset after a point, to avoid huge code bloat.
9848 When optimize_size, avoid any significant code bloat; calling
9849 memset is about 4 instructions, so allow for one instruction to
9850 load zero and three to do clearing. */
9851 if (TARGET_ALTIVEC && align >= 128)
9853 else if (TARGET_POWERPC64 && align >= 32)
9855 else if (TARGET_SPE && align >= 64)
9860 if (optimize_size && bytes > 3 * clear_step)
9862 if (! optimize_size && bytes > 8 * clear_step)
9865 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9867 enum machine_mode mode = BLKmode;
9870 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9875 else if (bytes >= 8 && TARGET_SPE && align >= 64)
9880 else if (bytes >= 8 && TARGET_POWERPC64
9881 /* 64-bit loads and stores require word-aligned
9883 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9888 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9889 { /* move 4 bytes */
9893 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9894 { /* move 2 bytes */
9898 else /* move 1 byte at a time */
9904 dest = adjust_address (orig_dest, mode, offset);
9906 emit_move_insn (dest, CONST0_RTX (mode));
9913 /* Expand a block move operation, and return 1 if successful. Return 0
9914 if we should let the compiler generate normal code.
9916 operands[0] is the destination
9917 operands[1] is the source
9918 operands[2] is the length
9919 operands[3] is the alignment */
9921 #define MAX_MOVE_REG 4
9924 expand_block_move (rtx operands[])
9926 rtx orig_dest = operands[0];
9927 rtx orig_src = operands[1];
9928 rtx bytes_rtx = operands[2];
9929 rtx align_rtx = operands[3];
9930 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9935 rtx stores[MAX_MOVE_REG];
9938 /* If this is not a fixed size move, just call memcpy */
9942 /* This must be a fixed size alignment */
9943 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9944 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9946 /* Anything to move? */
9947 bytes = INTVAL (bytes_rtx);
9951 /* store_one_arg depends on expand_block_move to handle at least the size of
9952 reg_parm_stack_space. */
9953 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9956 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9959 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9960 rtx (*mov) (rtx, rtx);
9962 enum machine_mode mode = BLKmode;
9965 /* Altivec first, since it will be faster than a string move
9966 when it applies, and usually not significantly larger. */
9967 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9971 gen_func.mov = gen_movv4si;
9973 else if (TARGET_SPE && bytes >= 8 && align >= 64)
9977 gen_func.mov = gen_movv2si;
9979 else if (TARGET_STRING
9980 && bytes > 24 /* move up to 32 bytes at a time */
9988 && ! fixed_regs[12])
9990 move_bytes = (bytes > 32) ? 32 : bytes;
9991 gen_func.movmemsi = gen_movmemsi_8reg;
9993 else if (TARGET_STRING
9994 && bytes > 16 /* move up to 24 bytes at a time */
10000 && ! fixed_regs[10])
10002 move_bytes = (bytes > 24) ? 24 : bytes;
10003 gen_func.movmemsi = gen_movmemsi_6reg;
10005 else if (TARGET_STRING
10006 && bytes > 8 /* move up to 16 bytes at a time */
10010 && ! fixed_regs[8])
10012 move_bytes = (bytes > 16) ? 16 : bytes;
10013 gen_func.movmemsi = gen_movmemsi_4reg;
10015 else if (bytes >= 8 && TARGET_POWERPC64
10016 /* 64-bit loads and stores require word-aligned
10018 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10022 gen_func.mov = gen_movdi;
10024 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
10025 { /* move up to 8 bytes at a time */
10026 move_bytes = (bytes > 8) ? 8 : bytes;
10027 gen_func.movmemsi = gen_movmemsi_2reg;
10029 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10030 { /* move 4 bytes */
10033 gen_func.mov = gen_movsi;
10035 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10036 { /* move 2 bytes */
10039 gen_func.mov = gen_movhi;
10041 else if (TARGET_STRING && bytes > 1)
10042 { /* move up to 4 bytes at a time */
10043 move_bytes = (bytes > 4) ? 4 : bytes;
10044 gen_func.movmemsi = gen_movmemsi_1reg;
10046 else /* move 1 byte at a time */
10050 gen_func.mov = gen_movqi;
10053 src = adjust_address (orig_src, mode, offset);
10054 dest = adjust_address (orig_dest, mode, offset);
10056 if (mode != BLKmode)
10058 rtx tmp_reg = gen_reg_rtx (mode);
10060 emit_insn ((*gen_func.mov) (tmp_reg, src));
10061 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
10064 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
10067 for (i = 0; i < num_reg; i++)
10068 emit_insn (stores[i]);
10072 if (mode == BLKmode)
10074 /* Move the address into scratch registers. The movmemsi
10075 patterns require zero offset. */
10076 if (!REG_P (XEXP (src, 0)))
10078 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
10079 src = replace_equiv_address (src, src_reg);
10081 set_mem_size (src, GEN_INT (move_bytes));
10083 if (!REG_P (XEXP (dest, 0)))
10085 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
10086 dest = replace_equiv_address (dest, dest_reg);
10088 set_mem_size (dest, GEN_INT (move_bytes));
10090 emit_insn ((*gen_func.movmemsi) (dest, src,
10091 GEN_INT (move_bytes & 31),
10100 /* Return a string to perform a load_multiple operation.
10101 operands[0] is the vector.
10102 operands[1] is the source address.
10103 operands[2] is the first destination register. */
10106 rs6000_output_load_multiple (rtx operands[3])
10108 /* We have to handle the case where the pseudo used to contain the address
10109 is assigned to one of the output registers. */
10111 int words = XVECLEN (operands[0], 0);
10114 if (XVECLEN (operands[0], 0) == 1)
10115 return "{l|lwz} %2,0(%1)";
10117 for (i = 0; i < words; i++)
10118 if (refers_to_regno_p (REGNO (operands[2]) + i,
10119 REGNO (operands[2]) + i + 1, operands[1], 0))
10123 xop[0] = GEN_INT (4 * (words-1));
10124 xop[1] = operands[1];
10125 xop[2] = operands[2];
10126 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
10131 xop[0] = GEN_INT (4 * (words-1));
10132 xop[1] = operands[1];
10133 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
10134 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
10139 for (j = 0; j < words; j++)
10142 xop[0] = GEN_INT (j * 4);
10143 xop[1] = operands[1];
10144 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
10145 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
10147 xop[0] = GEN_INT (i * 4);
10148 xop[1] = operands[1];
10149 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
10154 return "{lsi|lswi} %2,%1,%N0";
10158 /* A validation routine: say whether CODE, a condition code, and MODE
10159 match. The other alternatives either don't make sense or should
10160 never be generated. */
10163 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
10165 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
10166 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
10167 && GET_MODE_CLASS (mode) == MODE_CC);
10169 /* These don't make sense. */
10170 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
10171 || mode != CCUNSmode);
10173 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
10174 || mode == CCUNSmode);
10176 gcc_assert (mode == CCFPmode
10177 || (code != ORDERED && code != UNORDERED
10178 && code != UNEQ && code != LTGT
10179 && code != UNGT && code != UNLT
10180 && code != UNGE && code != UNLE));
10182 /* These should never be generated except for
10183 flag_finite_math_only. */
10184 gcc_assert (mode != CCFPmode
10185 || flag_finite_math_only
10186 || (code != LE && code != GE
10187 && code != UNEQ && code != LTGT
10188 && code != UNGT && code != UNLT));
10190 /* These are invalid; the information is not there. */
10191 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10195 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10196 mask required to convert the result of a rotate insn into a shift
10197 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10200 includes_lshift_p (rtx shiftop, rtx andop)
10202 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10204 shift_mask <<= INTVAL (shiftop);
10206 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10209 /* Similar, but for right shift. */
10212 includes_rshift_p (rtx shiftop, rtx andop)
10214 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10216 shift_mask >>= INTVAL (shiftop);
10218 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10221 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10222 to perform a left shift. It must have exactly SHIFTOP least
10223 significant 0's, then one or more 1's, then zero or more 0's. */
10226 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10228 if (GET_CODE (andop) == CONST_INT)
10230 HOST_WIDE_INT c, lsb, shift_mask;
10232 c = INTVAL (andop);
10233 if (c == 0 || c == ~0)
10237 shift_mask <<= INTVAL (shiftop);
10239 /* Find the least significant one bit. */
10242 /* It must coincide with the LSB of the shift mask. */
10243 if (-lsb != shift_mask)
10246 /* Invert to look for the next transition (if any). */
10249 /* Remove the low group of ones (originally low group of zeros). */
10252 /* Again find the lsb, and check we have all 1's above. */
10256 else if (GET_CODE (andop) == CONST_DOUBLE
10257 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10259 HOST_WIDE_INT low, high, lsb;
10260 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10262 low = CONST_DOUBLE_LOW (andop);
10263 if (HOST_BITS_PER_WIDE_INT < 64)
10264 high = CONST_DOUBLE_HIGH (andop);
10266 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10267 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10270 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10272 shift_mask_high = ~0;
10273 if (INTVAL (shiftop) > 32)
10274 shift_mask_high <<= INTVAL (shiftop) - 32;
10276 lsb = high & -high;
10278 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10284 lsb = high & -high;
10285 return high == -lsb;
10288 shift_mask_low = ~0;
10289 shift_mask_low <<= INTVAL (shiftop);
10293 if (-lsb != shift_mask_low)
10296 if (HOST_BITS_PER_WIDE_INT < 64)
10301 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10303 lsb = high & -high;
10304 return high == -lsb;
10308 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
10314 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10315 to perform a left shift. It must have SHIFTOP or more least
10316 significant 0's, with the remainder of the word 1's. */
10319 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
10321 if (GET_CODE (andop) == CONST_INT)
10323 HOST_WIDE_INT c, lsb, shift_mask;
10326 shift_mask <<= INTVAL (shiftop);
10327 c = INTVAL (andop);
10329 /* Find the least significant one bit. */
10332 /* It must be covered by the shift mask.
10333 This test also rejects c == 0. */
10334 if ((lsb & shift_mask) == 0)
10337 /* Check we have all 1's above the transition, and reject all 1's. */
10338 return c == -lsb && lsb != 1;
10340 else if (GET_CODE (andop) == CONST_DOUBLE
10341 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10343 HOST_WIDE_INT low, lsb, shift_mask_low;
10345 low = CONST_DOUBLE_LOW (andop);
10347 if (HOST_BITS_PER_WIDE_INT < 64)
10349 HOST_WIDE_INT high, shift_mask_high;
10351 high = CONST_DOUBLE_HIGH (andop);
10355 shift_mask_high = ~0;
10356 if (INTVAL (shiftop) > 32)
10357 shift_mask_high <<= INTVAL (shiftop) - 32;
10359 lsb = high & -high;
10361 if ((lsb & shift_mask_high) == 0)
10364 return high == -lsb;
10370 shift_mask_low = ~0;
10371 shift_mask_low <<= INTVAL (shiftop);
10375 if ((lsb & shift_mask_low) == 0)
10378 return low == -lsb && lsb != 1;
10384 /* Return 1 if operands will generate a valid arguments to rlwimi
10385 instruction for insert with right shift in 64-bit mode. The mask may
10386 not start on the first bit or stop on the last bit because wrap-around
10387 effects of instruction do not correspond to semantics of RTL insn. */
10390 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10392 if (INTVAL (startop) > 32
10393 && INTVAL (startop) < 64
10394 && INTVAL (sizeop) > 1
10395 && INTVAL (sizeop) + INTVAL (startop) < 64
10396 && INTVAL (shiftop) > 0
10397 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10398 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10404 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10405 for lfq and stfq insns iff the registers are hard registers. */
10408 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10410 /* We might have been passed a SUBREG. */
10411 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10414 /* We might have been passed non floating point registers. */
10415 if (!FP_REGNO_P (REGNO (reg1))
10416 || !FP_REGNO_P (REGNO (reg2)))
10419 return (REGNO (reg1) == REGNO (reg2) - 1);
10422 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10423 addr1 and addr2 must be in consecutive memory locations
10424 (addr2 == addr1 + 8). */
10427 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10430 unsigned int reg1, reg2;
10431 int offset1, offset2;
10433 /* The mems cannot be volatile. */
10434 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10437 addr1 = XEXP (mem1, 0);
10438 addr2 = XEXP (mem2, 0);
10440 /* Extract an offset (if used) from the first addr. */
10441 if (GET_CODE (addr1) == PLUS)
10443 /* If not a REG, return zero. */
10444 if (GET_CODE (XEXP (addr1, 0)) != REG)
10448 reg1 = REGNO (XEXP (addr1, 0));
10449 /* The offset must be constant! */
10450 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10452 offset1 = INTVAL (XEXP (addr1, 1));
10455 else if (GET_CODE (addr1) != REG)
10459 reg1 = REGNO (addr1);
10460 /* This was a simple (mem (reg)) expression. Offset is 0. */
10464 /* And now for the second addr. */
10465 if (GET_CODE (addr2) == PLUS)
10467 /* If not a REG, return zero. */
10468 if (GET_CODE (XEXP (addr2, 0)) != REG)
10472 reg2 = REGNO (XEXP (addr2, 0));
10473 /* The offset must be constant. */
10474 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10476 offset2 = INTVAL (XEXP (addr2, 1));
10479 else if (GET_CODE (addr2) != REG)
10483 reg2 = REGNO (addr2);
10484 /* This was a simple (mem (reg)) expression. Offset is 0. */
10488 /* Both of these must have the same base register. */
10492 /* The offset for the second addr must be 8 more than the first addr. */
10493 if (offset2 != offset1 + 8)
10496 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10501 /* Return the register class of a scratch register needed to copy IN into
10502 or out of a register in CLASS in MODE. If it can be done directly,
10503 NO_REGS is returned. */
10506 rs6000_secondary_reload_class (enum reg_class class,
10507 enum machine_mode mode ATTRIBUTE_UNUSED,
10512 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10514 && MACHOPIC_INDIRECT
10518 /* We cannot copy a symbolic operand directly into anything
10519 other than BASE_REGS for TARGET_ELF. So indicate that a
10520 register from BASE_REGS is needed as an intermediate
10523 On Darwin, pic addresses require a load from memory, which
10524 needs a base register. */
10525 if (class != BASE_REGS
10526 && (GET_CODE (in) == SYMBOL_REF
10527 || GET_CODE (in) == HIGH
10528 || GET_CODE (in) == LABEL_REF
10529 || GET_CODE (in) == CONST))
10533 if (GET_CODE (in) == REG)
10535 regno = REGNO (in);
10536 if (regno >= FIRST_PSEUDO_REGISTER)
10538 regno = true_regnum (in);
10539 if (regno >= FIRST_PSEUDO_REGISTER)
10543 else if (GET_CODE (in) == SUBREG)
10545 regno = true_regnum (in);
10546 if (regno >= FIRST_PSEUDO_REGISTER)
10552 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10554 if (class == GENERAL_REGS || class == BASE_REGS
10555 || (regno >= 0 && INT_REGNO_P (regno)))
10558 /* Constants, memory, and FP registers can go into FP registers. */
10559 if ((regno == -1 || FP_REGNO_P (regno))
10560 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10563 /* Memory, and AltiVec registers can go into AltiVec registers. */
10564 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10565 && class == ALTIVEC_REGS)
10568 /* We can copy among the CR registers. */
10569 if ((class == CR_REGS || class == CR0_REGS)
10570 && regno >= 0 && CR_REGNO_P (regno))
10573 /* Otherwise, we need GENERAL_REGS. */
10574 return GENERAL_REGS;
10577 /* Given a comparison operation, return the bit number in CCR to test. We
10578 know this is a valid comparison.
10580 SCC_P is 1 if this is for an scc. That means that %D will have been
10581 used instead of %C, so the bits will be in different places.
10583 Return -1 if OP isn't a valid comparison for some reason. */
10586 ccr_bit (rtx op, int scc_p)
10588 enum rtx_code code = GET_CODE (op);
10589 enum machine_mode cc_mode;
10594 if (!COMPARISON_P (op))
10597 reg = XEXP (op, 0);
10599 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10601 cc_mode = GET_MODE (reg);
10602 cc_regnum = REGNO (reg);
10603 base_bit = 4 * (cc_regnum - CR0_REGNO);
10605 validate_condition_mode (code, cc_mode);
10607 /* When generating a sCOND operation, only positive conditions are
10610 || code == EQ || code == GT || code == LT || code == UNORDERED
10611 || code == GTU || code == LTU);
10616 return scc_p ? base_bit + 3 : base_bit + 2;
10618 return base_bit + 2;
10619 case GT: case GTU: case UNLE:
10620 return base_bit + 1;
10621 case LT: case LTU: case UNGE:
10623 case ORDERED: case UNORDERED:
10624 return base_bit + 3;
10627 /* If scc, we will have done a cror to put the bit in the
10628 unordered position. So test that bit. For integer, this is ! LT
10629 unless this is an scc insn. */
10630 return scc_p ? base_bit + 3 : base_bit;
10633 return scc_p ? base_bit + 3 : base_bit + 1;
10636 gcc_unreachable ();
10640 /* Return the GOT register. */
10643 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10645 /* The second flow pass currently (June 1999) can't update
10646 regs_ever_live without disturbing other parts of the compiler, so
10647 update it here to make the prolog/epilogue code happy. */
10648 if (!can_create_pseudo_p ()
10649 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
10650 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
10652 current_function_uses_pic_offset_table = 1;
10654 return pic_offset_table_rtx;
10657 /* Function to init struct machine_function.
10658 This will be called, via a pointer variable,
10659 from push_function_context. */
10661 static struct machine_function *
10662 rs6000_init_machine_status (void)
10664 return ggc_alloc_cleared (sizeof (machine_function));
10667 /* These macros test for integers and extract the low-order bits. */
10669 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10670 && GET_MODE (X) == VOIDmode)
10672 #define INT_LOWPART(X) \
10673 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10676 extract_MB (rtx op)
10679 unsigned long val = INT_LOWPART (op);
10681 /* If the high bit is zero, the value is the first 1 bit we find
10683 if ((val & 0x80000000) == 0)
10685 gcc_assert (val & 0xffffffff);
10688 while (((val <<= 1) & 0x80000000) == 0)
10693 /* If the high bit is set and the low bit is not, or the mask is all
10694 1's, the value is zero. */
10695 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10698 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10701 while (((val >>= 1) & 1) != 0)
10708 extract_ME (rtx op)
10711 unsigned long val = INT_LOWPART (op);
10713 /* If the low bit is zero, the value is the first 1 bit we find from
10715 if ((val & 1) == 0)
10717 gcc_assert (val & 0xffffffff);
10720 while (((val >>= 1) & 1) == 0)
10726 /* If the low bit is set and the high bit is not, or the mask is all
10727 1's, the value is 31. */
10728 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10731 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10734 while (((val <<= 1) & 0x80000000) != 0)
10740 /* Locate some local-dynamic symbol still in use by this function
10741 so that we can print its name in some tls_ld pattern. */
10743 static const char *
10744 rs6000_get_some_local_dynamic_name (void)
10748 if (cfun->machine->some_ld_name)
10749 return cfun->machine->some_ld_name;
10751 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10753 && for_each_rtx (&PATTERN (insn),
10754 rs6000_get_some_local_dynamic_name_1, 0))
10755 return cfun->machine->some_ld_name;
10757 gcc_unreachable ();
10760 /* Helper function for rs6000_get_some_local_dynamic_name. */
10763 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10767 if (GET_CODE (x) == SYMBOL_REF)
10769 const char *str = XSTR (x, 0);
10770 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10772 cfun->machine->some_ld_name = str;
10780 /* Write out a function code label. */
10783 rs6000_output_function_entry (FILE *file, const char *fname)
10785 if (fname[0] != '.')
10787 switch (DEFAULT_ABI)
10790 gcc_unreachable ();
10796 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10805 RS6000_OUTPUT_BASENAME (file, fname);
10807 assemble_name (file, fname);
10810 /* Print an operand. Recognize special options, documented below. */
10813 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10814 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10816 #define SMALL_DATA_RELOC "sda21"
10817 #define SMALL_DATA_REG 0
10821 print_operand (FILE *file, rtx x, int code)
10825 unsigned HOST_WIDE_INT uval;
10830 /* Write out an instruction after the call which may be replaced
10831 with glue code by the loader. This depends on the AIX version. */
10832 asm_fprintf (file, RS6000_CALL_GLUE);
10835 /* %a is output_address. */
10838 /* If X is a constant integer whose low-order 5 bits are zero,
10839 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10840 in the AIX assembler where "sri" with a zero shift count
10841 writes a trash instruction. */
10842 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10849 /* If constant, low-order 16 bits of constant, unsigned.
10850 Otherwise, write normally. */
10852 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10854 print_operand (file, x, 0);
10858 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10859 for 64-bit mask direction. */
10860 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10863 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10867 /* X is a CR register. Print the number of the GT bit of the CR. */
10868 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10869 output_operand_lossage ("invalid %%E value");
10871 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10875 /* Like 'J' but get to the GT bit only. */
10876 gcc_assert (GET_CODE (x) == REG);
10878 /* Bit 1 is GT bit. */
10879 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10881 /* Add one for shift count in rlinm for scc. */
10882 fprintf (file, "%d", i + 1);
10886 /* X is a CR register. Print the number of the EQ bit of the CR */
10887 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10888 output_operand_lossage ("invalid %%E value");
10890 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10894 /* X is a CR register. Print the shift count needed to move it
10895 to the high-order four bits. */
10896 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10897 output_operand_lossage ("invalid %%f value");
10899 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10903 /* Similar, but print the count for the rotate in the opposite
10905 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10906 output_operand_lossage ("invalid %%F value");
10908 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10912 /* X is a constant integer. If it is negative, print "m",
10913 otherwise print "z". This is to make an aze or ame insn. */
10914 if (GET_CODE (x) != CONST_INT)
10915 output_operand_lossage ("invalid %%G value");
10916 else if (INTVAL (x) >= 0)
10923 /* If constant, output low-order five bits. Otherwise, write
10926 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10928 print_operand (file, x, 0);
10932 /* If constant, output low-order six bits. Otherwise, write
10935 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10937 print_operand (file, x, 0);
10941 /* Print `i' if this is a constant, else nothing. */
10947 /* Write the bit number in CCR for jump. */
10948 i = ccr_bit (x, 0);
10950 output_operand_lossage ("invalid %%j code");
10952 fprintf (file, "%d", i);
10956 /* Similar, but add one for shift count in rlinm for scc and pass
10957 scc flag to `ccr_bit'. */
10958 i = ccr_bit (x, 1);
10960 output_operand_lossage ("invalid %%J code");
10962 /* If we want bit 31, write a shift count of zero, not 32. */
10963 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10967 /* X must be a constant. Write the 1's complement of the
10970 output_operand_lossage ("invalid %%k value");
10972 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10976 /* X must be a symbolic constant on ELF. Write an
10977 expression suitable for an 'addi' that adds in the low 16
10978 bits of the MEM. */
10979 if (GET_CODE (x) != CONST)
10981 print_operand_address (file, x);
10982 fputs ("@l", file);
10986 if (GET_CODE (XEXP (x, 0)) != PLUS
10987 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10988 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10989 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10990 output_operand_lossage ("invalid %%K value");
10991 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10992 fputs ("@l", file);
10993 /* For GNU as, there must be a non-alphanumeric character
10994 between 'l' and the number. The '-' is added by
10995 print_operand() already. */
10996 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10998 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
11002 /* %l is output_asm_label. */
11005 /* Write second word of DImode or DFmode reference. Works on register
11006 or non-indexed memory only. */
11007 if (GET_CODE (x) == REG)
11008 fputs (reg_names[REGNO (x) + 1], file);
11009 else if (GET_CODE (x) == MEM)
11011 /* Handle possible auto-increment. Since it is pre-increment and
11012 we have already done it, we can just use an offset of word. */
11013 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11014 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11015 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11017 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11018 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11021 output_address (XEXP (adjust_address_nv (x, SImode,
11025 if (small_data_operand (x, GET_MODE (x)))
11026 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11027 reg_names[SMALL_DATA_REG]);
11032 /* MB value for a mask operand. */
11033 if (! mask_operand (x, SImode))
11034 output_operand_lossage ("invalid %%m value");
11036 fprintf (file, "%d", extract_MB (x));
11040 /* ME value for a mask operand. */
11041 if (! mask_operand (x, SImode))
11042 output_operand_lossage ("invalid %%M value");
11044 fprintf (file, "%d", extract_ME (x));
11047 /* %n outputs the negative of its operand. */
11050 /* Write the number of elements in the vector times 4. */
11051 if (GET_CODE (x) != PARALLEL)
11052 output_operand_lossage ("invalid %%N value");
11054 fprintf (file, "%d", XVECLEN (x, 0) * 4);
11058 /* Similar, but subtract 1 first. */
11059 if (GET_CODE (x) != PARALLEL)
11060 output_operand_lossage ("invalid %%O value");
11062 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
11066 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11068 || INT_LOWPART (x) < 0
11069 || (i = exact_log2 (INT_LOWPART (x))) < 0)
11070 output_operand_lossage ("invalid %%p value");
11072 fprintf (file, "%d", i);
11076 /* The operand must be an indirect memory reference. The result
11077 is the register name. */
11078 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
11079 || REGNO (XEXP (x, 0)) >= 32)
11080 output_operand_lossage ("invalid %%P value");
11082 fputs (reg_names[REGNO (XEXP (x, 0))], file);
11086 /* This outputs the logical code corresponding to a boolean
11087 expression. The expression may have one or both operands
11088 negated (if one, only the first one). For condition register
11089 logical operations, it will also treat the negated
11090 CR codes as NOTs, but not handle NOTs of them. */
11092 const char *const *t = 0;
11094 enum rtx_code code = GET_CODE (x);
11095 static const char * const tbl[3][3] = {
11096 { "and", "andc", "nor" },
11097 { "or", "orc", "nand" },
11098 { "xor", "eqv", "xor" } };
11102 else if (code == IOR)
11104 else if (code == XOR)
11107 output_operand_lossage ("invalid %%q value");
11109 if (GET_CODE (XEXP (x, 0)) != NOT)
11113 if (GET_CODE (XEXP (x, 1)) == NOT)
11131 /* X is a CR register. Print the mask for `mtcrf'. */
11132 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11133 output_operand_lossage ("invalid %%R value");
11135 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
11139 /* Low 5 bits of 32 - value */
11141 output_operand_lossage ("invalid %%s value");
11143 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
11147 /* PowerPC64 mask position. All 0's is excluded.
11148 CONST_INT 32-bit mask is considered sign-extended so any
11149 transition must occur within the CONST_INT, not on the boundary. */
11150 if (! mask64_operand (x, DImode))
11151 output_operand_lossage ("invalid %%S value");
11153 uval = INT_LOWPART (x);
11155 if (uval & 1) /* Clear Left */
11157 #if HOST_BITS_PER_WIDE_INT > 64
11158 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11162 else /* Clear Right */
11165 #if HOST_BITS_PER_WIDE_INT > 64
11166 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11172 gcc_assert (i >= 0);
11173 fprintf (file, "%d", i);
11177 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
11178 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
11180 /* Bit 3 is OV bit. */
11181 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
11183 /* If we want bit 31, write a shift count of zero, not 32. */
11184 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11188 /* Print the symbolic name of a branch target register. */
11189 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
11190 && REGNO (x) != CTR_REGNO))
11191 output_operand_lossage ("invalid %%T value");
11192 else if (REGNO (x) == LR_REGNO)
11193 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
11195 fputs ("ctr", file);
11199 /* High-order 16 bits of constant for use in unsigned operand. */
11201 output_operand_lossage ("invalid %%u value");
11203 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11204 (INT_LOWPART (x) >> 16) & 0xffff);
11208 /* High-order 16 bits of constant for use in signed operand. */
11210 output_operand_lossage ("invalid %%v value");
11212 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11213 (INT_LOWPART (x) >> 16) & 0xffff);
11217 /* Print `u' if this has an auto-increment or auto-decrement. */
11218 if (GET_CODE (x) == MEM
11219 && (GET_CODE (XEXP (x, 0)) == PRE_INC
11220 || GET_CODE (XEXP (x, 0)) == PRE_DEC
11221 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
11226 /* Print the trap code for this operand. */
11227 switch (GET_CODE (x))
11230 fputs ("eq", file); /* 4 */
11233 fputs ("ne", file); /* 24 */
11236 fputs ("lt", file); /* 16 */
11239 fputs ("le", file); /* 20 */
11242 fputs ("gt", file); /* 8 */
11245 fputs ("ge", file); /* 12 */
11248 fputs ("llt", file); /* 2 */
11251 fputs ("lle", file); /* 6 */
11254 fputs ("lgt", file); /* 1 */
11257 fputs ("lge", file); /* 5 */
11260 gcc_unreachable ();
11265 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11268 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
11269 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
11271 print_operand (file, x, 0);
11275 /* MB value for a PowerPC64 rldic operand. */
11276 val = (GET_CODE (x) == CONST_INT
11277 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
11282 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
11283 if ((val <<= 1) < 0)
11286 #if HOST_BITS_PER_WIDE_INT == 32
11287 if (GET_CODE (x) == CONST_INT && i >= 0)
11288 i += 32; /* zero-extend high-part was all 0's */
11289 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
11291 val = CONST_DOUBLE_LOW (x);
11297 for ( ; i < 64; i++)
11298 if ((val <<= 1) < 0)
11303 fprintf (file, "%d", i + 1);
11307 if (GET_CODE (x) == MEM
11308 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
11309 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
11310 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
11315 /* Like 'L', for third word of TImode */
11316 if (GET_CODE (x) == REG)
11317 fputs (reg_names[REGNO (x) + 2], file);
11318 else if (GET_CODE (x) == MEM)
11320 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11321 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11322 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11323 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11324 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11326 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
11327 if (small_data_operand (x, GET_MODE (x)))
11328 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11329 reg_names[SMALL_DATA_REG]);
11334 /* X is a SYMBOL_REF. Write out the name preceded by a
11335 period and without any trailing data in brackets. Used for function
11336 names. If we are configured for System V (or the embedded ABI) on
11337 the PowerPC, do not emit the period, since those systems do not use
11338 TOCs and the like. */
11339 gcc_assert (GET_CODE (x) == SYMBOL_REF);
11341 /* Mark the decl as referenced so that cgraph will output the
11343 if (SYMBOL_REF_DECL (x))
11344 mark_decl_referenced (SYMBOL_REF_DECL (x));
11346 /* For macho, check to see if we need a stub. */
11349 const char *name = XSTR (x, 0);
11351 if (MACHOPIC_INDIRECT
11352 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11353 name = machopic_indirection_name (x, /*stub_p=*/true);
11355 assemble_name (file, name);
11357 else if (!DOT_SYMBOLS)
11358 assemble_name (file, XSTR (x, 0));
11360 rs6000_output_function_entry (file, XSTR (x, 0));
11364 /* Like 'L', for last word of TImode. */
11365 if (GET_CODE (x) == REG)
11366 fputs (reg_names[REGNO (x) + 3], file);
11367 else if (GET_CODE (x) == MEM)
11369 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11370 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11371 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11372 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11373 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11375 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11376 if (small_data_operand (x, GET_MODE (x)))
11377 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11378 reg_names[SMALL_DATA_REG]);
11382 /* Print AltiVec or SPE memory operand. */
11387 gcc_assert (GET_CODE (x) == MEM);
11391 /* Ugly hack because %y is overloaded. */
11392 if ((TARGET_SPE || TARGET_E500_DOUBLE)
11393 && (GET_MODE_SIZE (GET_MODE (x)) == 8
11394 || GET_MODE (x) == TFmode
11395 || GET_MODE (x) == TImode))
11397 /* Handle [reg]. */
11398 if (GET_CODE (tmp) == REG)
11400 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11403 /* Handle [reg+UIMM]. */
11404 else if (GET_CODE (tmp) == PLUS &&
11405 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11409 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11411 x = INTVAL (XEXP (tmp, 1));
11412 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11416 /* Fall through. Must be [reg+reg]. */
11419 && GET_CODE (tmp) == AND
11420 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11421 && INTVAL (XEXP (tmp, 1)) == -16)
11422 tmp = XEXP (tmp, 0);
11423 if (GET_CODE (tmp) == REG)
11424 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11427 gcc_assert (GET_CODE (tmp) == PLUS
11428 && REG_P (XEXP (tmp, 0))
11429 && REG_P (XEXP (tmp, 1)));
11431 if (REGNO (XEXP (tmp, 0)) == 0)
11432 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11433 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11435 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11436 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11442 if (GET_CODE (x) == REG)
11443 fprintf (file, "%s", reg_names[REGNO (x)]);
11444 else if (GET_CODE (x) == MEM)
11446 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11447 know the width from the mode. */
11448 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11449 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11450 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11451 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11452 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11453 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11454 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11455 output_address (XEXP (XEXP (x, 0), 1));
11457 output_address (XEXP (x, 0));
11460 output_addr_const (file, x);
11464 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11468 output_operand_lossage ("invalid %%xn code");
11472 /* Print the address of an operand. */
11475 print_operand_address (FILE *file, rtx x)
11477 if (GET_CODE (x) == REG)
11478 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11479 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11480 || GET_CODE (x) == LABEL_REF)
11482 output_addr_const (file, x);
11483 if (small_data_operand (x, GET_MODE (x)))
11484 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11485 reg_names[SMALL_DATA_REG]);
11487 gcc_assert (!TARGET_TOC);
11489 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11491 gcc_assert (REG_P (XEXP (x, 0)));
11492 if (REGNO (XEXP (x, 0)) == 0)
11493 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11494 reg_names[ REGNO (XEXP (x, 0)) ]);
11496 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11497 reg_names[ REGNO (XEXP (x, 1)) ]);
11499 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11500 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11501 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11503 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11504 && CONSTANT_P (XEXP (x, 1)))
11506 output_addr_const (file, XEXP (x, 1));
11507 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11511 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11512 && CONSTANT_P (XEXP (x, 1)))
11514 fprintf (file, "lo16(");
11515 output_addr_const (file, XEXP (x, 1));
11516 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11519 else if (legitimate_constant_pool_address_p (x))
11521 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11523 rtx contains_minus = XEXP (x, 1);
11527 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11528 turn it into (sym) for output_addr_const. */
11529 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11530 contains_minus = XEXP (contains_minus, 0);
11532 minus = XEXP (contains_minus, 0);
11533 symref = XEXP (minus, 0);
11534 XEXP (contains_minus, 0) = symref;
11539 name = XSTR (symref, 0);
11540 newname = alloca (strlen (name) + sizeof ("@toc"));
11541 strcpy (newname, name);
11542 strcat (newname, "@toc");
11543 XSTR (symref, 0) = newname;
11545 output_addr_const (file, XEXP (x, 1));
11547 XSTR (symref, 0) = name;
11548 XEXP (contains_minus, 0) = minus;
11551 output_addr_const (file, XEXP (x, 1));
11553 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11556 gcc_unreachable ();
11559 /* Target hook for assembling integer objects. The PowerPC version has
11560 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11561 is defined. It also needs to handle DI-mode objects on 64-bit
11565 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11567 #ifdef RELOCATABLE_NEEDS_FIXUP
11568 /* Special handling for SI values. */
11569 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11571 static int recurse = 0;
11573 /* For -mrelocatable, we mark all addresses that need to be fixed up
11574 in the .fixup section. */
11575 if (TARGET_RELOCATABLE
11576 && in_section != toc_section
11577 && in_section != text_section
11578 && !unlikely_text_section_p (in_section)
11580 && GET_CODE (x) != CONST_INT
11581 && GET_CODE (x) != CONST_DOUBLE
11587 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11589 ASM_OUTPUT_LABEL (asm_out_file, buf);
11590 fprintf (asm_out_file, "\t.long\t(");
11591 output_addr_const (asm_out_file, x);
11592 fprintf (asm_out_file, ")@fixup\n");
11593 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11594 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11595 fprintf (asm_out_file, "\t.long\t");
11596 assemble_name (asm_out_file, buf);
11597 fprintf (asm_out_file, "\n\t.previous\n");
11601 /* Remove initial .'s to turn a -mcall-aixdesc function
11602 address into the address of the descriptor, not the function
11604 else if (GET_CODE (x) == SYMBOL_REF
11605 && XSTR (x, 0)[0] == '.'
11606 && DEFAULT_ABI == ABI_AIX)
11608 const char *name = XSTR (x, 0);
11609 while (*name == '.')
11612 fprintf (asm_out_file, "\t.long\t%s\n", name);
11616 #endif /* RELOCATABLE_NEEDS_FIXUP */
11617 return default_assemble_integer (x, size, aligned_p);
11620 #ifdef HAVE_GAS_HIDDEN
11621 /* Emit an assembler directive to set symbol visibility for DECL to
11622 VISIBILITY_TYPE. */
11625 rs6000_assemble_visibility (tree decl, int vis)
11627 /* Functions need to have their entry point symbol visibility set as
11628 well as their descriptor symbol visibility. */
11629 if (DEFAULT_ABI == ABI_AIX
11631 && TREE_CODE (decl) == FUNCTION_DECL)
11633 static const char * const visibility_types[] = {
11634 NULL, "internal", "hidden", "protected"
11637 const char *name, *type;
11639 name = ((* targetm.strip_name_encoding)
11640 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11641 type = visibility_types[vis];
11643 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11644 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11647 default_assemble_visibility (decl, vis);
11652 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11654 /* Reversal of FP compares takes care -- an ordered compare
11655 becomes an unordered compare and vice versa. */
11656 if (mode == CCFPmode
11657 && (!flag_finite_math_only
11658 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11659 || code == UNEQ || code == LTGT))
11660 return reverse_condition_maybe_unordered (code);
11662 return reverse_condition (code);
11665 /* Generate a compare for CODE. Return a brand-new rtx that
11666 represents the result of the compare. */
11669 rs6000_generate_compare (enum rtx_code code)
11671 enum machine_mode comp_mode;
11672 rtx compare_result;
11674 if (rs6000_compare_fp_p)
11675 comp_mode = CCFPmode;
11676 else if (code == GTU || code == LTU
11677 || code == GEU || code == LEU)
11678 comp_mode = CCUNSmode;
11679 else if ((code == EQ || code == NE)
11680 && GET_CODE (rs6000_compare_op0) == SUBREG
11681 && GET_CODE (rs6000_compare_op1) == SUBREG
11682 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11683 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11684 /* These are unsigned values, perhaps there will be a later
11685 ordering compare that can be shared with this one.
11686 Unfortunately we cannot detect the signedness of the operands
11687 for non-subregs. */
11688 comp_mode = CCUNSmode;
11690 comp_mode = CCmode;
11692 /* First, the compare. */
11693 compare_result = gen_reg_rtx (comp_mode);
11695 /* E500 FP compare instructions on the GPRs. Yuck! */
11696 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
11697 && rs6000_compare_fp_p)
11699 rtx cmp, or_result, compare_result2;
11700 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11702 if (op_mode == VOIDmode)
11703 op_mode = GET_MODE (rs6000_compare_op1);
11705 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11706 This explains the following mess. */
11710 case EQ: case UNEQ: case NE: case LTGT:
11714 cmp = flag_unsafe_math_optimizations
11715 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11716 rs6000_compare_op1)
11717 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11718 rs6000_compare_op1);
11722 cmp = flag_unsafe_math_optimizations
11723 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11724 rs6000_compare_op1)
11725 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11726 rs6000_compare_op1);
11730 cmp = flag_unsafe_math_optimizations
11731 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
11732 rs6000_compare_op1)
11733 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
11734 rs6000_compare_op1);
11738 gcc_unreachable ();
11742 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11746 cmp = flag_unsafe_math_optimizations
11747 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11748 rs6000_compare_op1)
11749 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11750 rs6000_compare_op1);
11754 cmp = flag_unsafe_math_optimizations
11755 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11756 rs6000_compare_op1)
11757 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11758 rs6000_compare_op1);
11762 cmp = flag_unsafe_math_optimizations
11763 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
11764 rs6000_compare_op1)
11765 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
11766 rs6000_compare_op1);
11770 gcc_unreachable ();
11774 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11778 cmp = flag_unsafe_math_optimizations
11779 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11780 rs6000_compare_op1)
11781 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11782 rs6000_compare_op1);
11786 cmp = flag_unsafe_math_optimizations
11787 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11788 rs6000_compare_op1)
11789 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11790 rs6000_compare_op1);
11794 cmp = flag_unsafe_math_optimizations
11795 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
11796 rs6000_compare_op1)
11797 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
11798 rs6000_compare_op1);
11802 gcc_unreachable ();
11806 gcc_unreachable ();
11809 /* Synthesize LE and GE from LT/GT || EQ. */
11810 if (code == LE || code == GE || code == LEU || code == GEU)
11816 case LE: code = LT; break;
11817 case GE: code = GT; break;
11818 case LEU: code = LT; break;
11819 case GEU: code = GT; break;
11820 default: gcc_unreachable ();
11823 compare_result2 = gen_reg_rtx (CCFPmode);
11829 cmp = flag_unsafe_math_optimizations
11830 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11831 rs6000_compare_op1)
11832 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11833 rs6000_compare_op1);
11837 cmp = flag_unsafe_math_optimizations
11838 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11839 rs6000_compare_op1)
11840 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11841 rs6000_compare_op1);
11845 cmp = flag_unsafe_math_optimizations
11846 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
11847 rs6000_compare_op1)
11848 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
11849 rs6000_compare_op1);
11853 gcc_unreachable ();
11857 /* OR them together. */
11858 or_result = gen_reg_rtx (CCFPmode);
11859 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11861 compare_result = or_result;
11866 if (code == NE || code == LTGT)
11876 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11877 CLOBBERs to match cmptf_internal2 pattern. */
11878 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11879 && GET_MODE (rs6000_compare_op0) == TFmode
11880 && !TARGET_IEEEQUAD
11881 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11882 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11884 gen_rtx_SET (VOIDmode,
11886 gen_rtx_COMPARE (comp_mode,
11887 rs6000_compare_op0,
11888 rs6000_compare_op1)),
11889 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11890 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11891 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11892 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11893 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11894 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11895 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11896 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11897 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11898 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11900 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11901 comp_mode = CCEQmode;
11902 compare_result = gen_reg_rtx (CCEQmode);
11904 emit_insn (gen_stack_protect_testdi (compare_result,
11905 rs6000_compare_op0, op1));
11907 emit_insn (gen_stack_protect_testsi (compare_result,
11908 rs6000_compare_op0, op1));
11911 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11912 gen_rtx_COMPARE (comp_mode,
11913 rs6000_compare_op0,
11914 rs6000_compare_op1)));
11917 /* Some kinds of FP comparisons need an OR operation;
11918 under flag_finite_math_only we don't bother. */
11919 if (rs6000_compare_fp_p
11920 && !flag_finite_math_only
11921 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
11922 && (code == LE || code == GE
11923 || code == UNEQ || code == LTGT
11924 || code == UNGT || code == UNLT))
11926 enum rtx_code or1, or2;
11927 rtx or1_rtx, or2_rtx, compare2_rtx;
11928 rtx or_result = gen_reg_rtx (CCEQmode);
11932 case LE: or1 = LT; or2 = EQ; break;
11933 case GE: or1 = GT; or2 = EQ; break;
11934 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11935 case LTGT: or1 = LT; or2 = GT; break;
11936 case UNGT: or1 = UNORDERED; or2 = GT; break;
11937 case UNLT: or1 = UNORDERED; or2 = LT; break;
11938 default: gcc_unreachable ();
11940 validate_condition_mode (or1, comp_mode);
11941 validate_condition_mode (or2, comp_mode);
11942 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11943 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11944 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11945 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11947 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11949 compare_result = or_result;
11953 validate_condition_mode (code, GET_MODE (compare_result));
11955 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11959 /* Emit the RTL for an sCOND pattern. */
11962 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11965 enum machine_mode op_mode;
11966 enum rtx_code cond_code;
11968 condition_rtx = rs6000_generate_compare (code);
11969 cond_code = GET_CODE (condition_rtx);
11971 if (rs6000_compare_fp_p
11972 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11976 PUT_MODE (condition_rtx, SImode);
11977 t = XEXP (condition_rtx, 0);
11979 gcc_assert (cond_code == NE || cond_code == EQ);
11981 if (cond_code == NE)
11982 emit_insn (gen_e500_flip_gt_bit (t, t));
11984 emit_insn (gen_move_from_CR_gt_bit (result, t));
11988 if (cond_code == NE
11989 || cond_code == GE || cond_code == LE
11990 || cond_code == GEU || cond_code == LEU
11991 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11993 rtx not_result = gen_reg_rtx (CCEQmode);
11994 rtx not_op, rev_cond_rtx;
11995 enum machine_mode cc_mode;
11997 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11999 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
12000 SImode, XEXP (condition_rtx, 0), const0_rtx);
12001 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
12002 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
12003 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
12006 op_mode = GET_MODE (rs6000_compare_op0);
12007 if (op_mode == VOIDmode)
12008 op_mode = GET_MODE (rs6000_compare_op1);
12010 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
12012 PUT_MODE (condition_rtx, DImode);
12013 convert_move (result, condition_rtx, 0);
12017 PUT_MODE (condition_rtx, SImode);
12018 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
12022 /* Emit a branch of kind CODE to location LOC. */
12025 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
12027 rtx condition_rtx, loc_ref;
12029 condition_rtx = rs6000_generate_compare (code);
12030 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
12031 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
12032 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
12033 loc_ref, pc_rtx)));
12036 /* Return the string to output a conditional branch to LABEL, which is
12037 the operand number of the label, or -1 if the branch is really a
12038 conditional return.
12040 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12041 condition code register and its mode specifies what kind of
12042 comparison we made.
12044 REVERSED is nonzero if we should reverse the sense of the comparison.
12046 INSN is the insn. */
12049 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12051 static char string[64];
12052 enum rtx_code code = GET_CODE (op);
12053 rtx cc_reg = XEXP (op, 0);
12054 enum machine_mode mode = GET_MODE (cc_reg);
12055 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
12056 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12057 int really_reversed = reversed ^ need_longbranch;
12063 validate_condition_mode (code, mode);
12065 /* Work out which way this really branches. We could use
12066 reverse_condition_maybe_unordered here always but this
12067 makes the resulting assembler clearer. */
12068 if (really_reversed)
12070 /* Reversal of FP compares takes care -- an ordered compare
12071 becomes an unordered compare and vice versa. */
12072 if (mode == CCFPmode)
12073 code = reverse_condition_maybe_unordered (code);
12075 code = reverse_condition (code);
12078 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
12080 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12085 /* Opposite of GT. */
12094 gcc_unreachable ();
12100 /* Not all of these are actually distinct opcodes, but
12101 we distinguish them for clarity of the resulting assembler. */
12102 case NE: case LTGT:
12103 ccode = "ne"; break;
12104 case EQ: case UNEQ:
12105 ccode = "eq"; break;
12107 ccode = "ge"; break;
12108 case GT: case GTU: case UNGT:
12109 ccode = "gt"; break;
12111 ccode = "le"; break;
12112 case LT: case LTU: case UNLT:
12113 ccode = "lt"; break;
12114 case UNORDERED: ccode = "un"; break;
12115 case ORDERED: ccode = "nu"; break;
12116 case UNGE: ccode = "nl"; break;
12117 case UNLE: ccode = "ng"; break;
12119 gcc_unreachable ();
12122 /* Maybe we have a guess as to how likely the branch is.
12123 The old mnemonics don't have a way to specify this information. */
12125 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
12126 if (note != NULL_RTX)
12128 /* PROB is the difference from 50%. */
12129 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
12131 /* Only hint for highly probable/improbable branches on newer
12132 cpus as static prediction overrides processor dynamic
12133 prediction. For older cpus we may as well always hint, but
12134 assume not taken for branches that are very close to 50% as a
12135 mispredicted taken branch is more expensive than a
12136 mispredicted not-taken branch. */
12137 if (rs6000_always_hint
12138 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
12139 && br_prob_note_reliable_p (note)))
12141 if (abs (prob) > REG_BR_PROB_BASE / 20
12142 && ((prob > 0) ^ need_longbranch))
12150 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12152 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12154 /* We need to escape any '%' characters in the reg_names string.
12155 Assume they'd only be the first character.... */
12156 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
12158 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12162 /* If the branch distance was too far, we may have to use an
12163 unconditional branch to go the distance. */
12164 if (need_longbranch)
12165 s += sprintf (s, ",$+8\n\tb %s", label);
12167 s += sprintf (s, ",%s", label);
12173 /* Return the string to flip the GT bit on a CR. */
12175 output_e500_flip_gt_bit (rtx dst, rtx src)
12177 static char string[64];
12180 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
12181 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
12184 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
12185 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
12187 sprintf (string, "crnot %d,%d", a, b);
12191 /* Return insn index for the vector compare instruction for given CODE,
12192 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12196 get_vec_cmp_insn (enum rtx_code code,
12197 enum machine_mode dest_mode,
12198 enum machine_mode op_mode)
12200 if (!TARGET_ALTIVEC)
12201 return INSN_NOT_AVAILABLE;
12206 if (dest_mode == V16QImode && op_mode == V16QImode)
12207 return UNSPEC_VCMPEQUB;
12208 if (dest_mode == V8HImode && op_mode == V8HImode)
12209 return UNSPEC_VCMPEQUH;
12210 if (dest_mode == V4SImode && op_mode == V4SImode)
12211 return UNSPEC_VCMPEQUW;
12212 if (dest_mode == V4SImode && op_mode == V4SFmode)
12213 return UNSPEC_VCMPEQFP;
12216 if (dest_mode == V4SImode && op_mode == V4SFmode)
12217 return UNSPEC_VCMPGEFP;
12219 if (dest_mode == V16QImode && op_mode == V16QImode)
12220 return UNSPEC_VCMPGTSB;
12221 if (dest_mode == V8HImode && op_mode == V8HImode)
12222 return UNSPEC_VCMPGTSH;
12223 if (dest_mode == V4SImode && op_mode == V4SImode)
12224 return UNSPEC_VCMPGTSW;
12225 if (dest_mode == V4SImode && op_mode == V4SFmode)
12226 return UNSPEC_VCMPGTFP;
12229 if (dest_mode == V16QImode && op_mode == V16QImode)
12230 return UNSPEC_VCMPGTUB;
12231 if (dest_mode == V8HImode && op_mode == V8HImode)
12232 return UNSPEC_VCMPGTUH;
12233 if (dest_mode == V4SImode && op_mode == V4SImode)
12234 return UNSPEC_VCMPGTUW;
12239 return INSN_NOT_AVAILABLE;
12242 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12243 DMODE is expected destination mode. This is a recursive function. */
12246 rs6000_emit_vector_compare (enum rtx_code rcode,
12248 enum machine_mode dmode)
12252 enum machine_mode dest_mode;
12253 enum machine_mode op_mode = GET_MODE (op1);
12255 gcc_assert (TARGET_ALTIVEC);
12256 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
12258 /* Floating point vector compare instructions uses destination V4SImode.
12259 Move destination to appropriate mode later. */
12260 if (dmode == V4SFmode)
12261 dest_mode = V4SImode;
12265 mask = gen_reg_rtx (dest_mode);
12266 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12268 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
12270 bool swap_operands = false;
12271 bool try_again = false;
12276 swap_operands = true;
12281 swap_operands = true;
12289 /* Invert condition and try again.
12290 e.g., A != B becomes ~(A==B). */
12292 enum rtx_code rev_code;
12293 enum insn_code nor_code;
12296 rev_code = reverse_condition_maybe_unordered (rcode);
12297 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
12300 nor_code = optab_handler (one_cmpl_optab, (int)dest_mode)->insn_code;
12301 gcc_assert (nor_code != CODE_FOR_nothing);
12302 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
12304 if (dmode != dest_mode)
12306 rtx temp = gen_reg_rtx (dest_mode);
12307 convert_move (temp, mask, 0);
12317 /* Try GT/GTU/LT/LTU OR EQ */
12320 enum insn_code ior_code;
12321 enum rtx_code new_code;
12342 gcc_unreachable ();
12345 c_rtx = rs6000_emit_vector_compare (new_code,
12346 op0, op1, dest_mode);
12347 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
12350 ior_code = optab_handler (ior_optab, (int)dest_mode)->insn_code;
12351 gcc_assert (ior_code != CODE_FOR_nothing);
12352 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
12353 if (dmode != dest_mode)
12355 rtx temp = gen_reg_rtx (dest_mode);
12356 convert_move (temp, mask, 0);
12363 gcc_unreachable ();
12368 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12369 /* You only get two chances. */
12370 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
12382 emit_insn (gen_rtx_SET (VOIDmode, mask,
12383 gen_rtx_UNSPEC (dest_mode,
12384 gen_rtvec (2, op0, op1),
12386 if (dmode != dest_mode)
12388 rtx temp = gen_reg_rtx (dest_mode);
12389 convert_move (temp, mask, 0);
12395 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12396 valid insn doesn exist for given mode. */
12399 get_vsel_insn (enum machine_mode mode)
12404 return UNSPEC_VSEL4SI;
12407 return UNSPEC_VSEL4SF;
12410 return UNSPEC_VSEL8HI;
12413 return UNSPEC_VSEL16QI;
12416 return INSN_NOT_AVAILABLE;
12419 return INSN_NOT_AVAILABLE;
12422 /* Emit vector select insn where DEST is destination using
12423 operands OP1, OP2 and MASK. */
12426 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
12429 enum machine_mode dest_mode = GET_MODE (dest);
12430 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12432 temp = gen_reg_rtx (dest_mode);
12434 /* For each vector element, select op1 when mask is 1 otherwise
12436 t = gen_rtx_SET (VOIDmode, temp,
12437 gen_rtx_UNSPEC (dest_mode,
12438 gen_rtvec (3, op2, op1, mask),
12441 emit_move_insn (dest, temp);
12445 /* Emit vector conditional expression.
12446 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12447 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12450 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12451 rtx cond, rtx cc_op0, rtx cc_op1)
12453 enum machine_mode dest_mode = GET_MODE (dest);
12454 enum rtx_code rcode = GET_CODE (cond);
12457 if (!TARGET_ALTIVEC)
12460 /* Get the vector mask for the given relational operations. */
12461 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12463 rs6000_emit_vector_select (dest, op1, op2, mask);
12468 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12469 operands of the last comparison is nonzero/true, FALSE_COND if it
12470 is zero/false. Return 0 if the hardware has no such operation. */
12473 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12475 enum rtx_code code = GET_CODE (op);
12476 rtx op0 = rs6000_compare_op0;
12477 rtx op1 = rs6000_compare_op1;
12478 REAL_VALUE_TYPE c1;
12479 enum machine_mode compare_mode = GET_MODE (op0);
12480 enum machine_mode result_mode = GET_MODE (dest);
12482 bool is_against_zero;
12484 /* These modes should always match. */
12485 if (GET_MODE (op1) != compare_mode
12486 /* In the isel case however, we can use a compare immediate, so
12487 op1 may be a small constant. */
12488 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12490 if (GET_MODE (true_cond) != result_mode)
12492 if (GET_MODE (false_cond) != result_mode)
12495 /* First, work out if the hardware can do this at all, or
12496 if it's too slow.... */
12497 if (! rs6000_compare_fp_p)
12500 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12503 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
12504 && SCALAR_FLOAT_MODE_P (compare_mode))
12507 is_against_zero = op1 == CONST0_RTX (compare_mode);
12509 /* A floating-point subtract might overflow, underflow, or produce
12510 an inexact result, thus changing the floating-point flags, so it
12511 can't be generated if we care about that. It's safe if one side
12512 of the construct is zero, since then no subtract will be
12514 if (SCALAR_FLOAT_MODE_P (compare_mode)
12515 && flag_trapping_math && ! is_against_zero)
12518 /* Eliminate half of the comparisons by switching operands, this
12519 makes the remaining code simpler. */
12520 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12521 || code == LTGT || code == LT || code == UNLE)
12523 code = reverse_condition_maybe_unordered (code);
12525 true_cond = false_cond;
12529 /* UNEQ and LTGT take four instructions for a comparison with zero,
12530 it'll probably be faster to use a branch here too. */
12531 if (code == UNEQ && HONOR_NANS (compare_mode))
12534 if (GET_CODE (op1) == CONST_DOUBLE)
12535 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12537 /* We're going to try to implement comparisons by performing
12538 a subtract, then comparing against zero. Unfortunately,
12539 Inf - Inf is NaN which is not zero, and so if we don't
12540 know that the operand is finite and the comparison
12541 would treat EQ different to UNORDERED, we can't do it. */
12542 if (HONOR_INFINITIES (compare_mode)
12543 && code != GT && code != UNGE
12544 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12545 /* Constructs of the form (a OP b ? a : b) are safe. */
12546 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12547 || (! rtx_equal_p (op0, true_cond)
12548 && ! rtx_equal_p (op1, true_cond))))
12551 /* At this point we know we can use fsel. */
12553 /* Reduce the comparison to a comparison against zero. */
12554 if (! is_against_zero)
12556 temp = gen_reg_rtx (compare_mode);
12557 emit_insn (gen_rtx_SET (VOIDmode, temp,
12558 gen_rtx_MINUS (compare_mode, op0, op1)));
12560 op1 = CONST0_RTX (compare_mode);
12563 /* If we don't care about NaNs we can reduce some of the comparisons
12564 down to faster ones. */
12565 if (! HONOR_NANS (compare_mode))
12571 true_cond = false_cond;
12584 /* Now, reduce everything down to a GE. */
12591 temp = gen_reg_rtx (compare_mode);
12592 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12597 temp = gen_reg_rtx (compare_mode);
12598 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12603 temp = gen_reg_rtx (compare_mode);
12604 emit_insn (gen_rtx_SET (VOIDmode, temp,
12605 gen_rtx_NEG (compare_mode,
12606 gen_rtx_ABS (compare_mode, op0))));
12611 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12612 temp = gen_reg_rtx (result_mode);
12613 emit_insn (gen_rtx_SET (VOIDmode, temp,
12614 gen_rtx_IF_THEN_ELSE (result_mode,
12615 gen_rtx_GE (VOIDmode,
12617 true_cond, false_cond)));
12618 false_cond = true_cond;
12621 temp = gen_reg_rtx (compare_mode);
12622 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12627 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12628 temp = gen_reg_rtx (result_mode);
12629 emit_insn (gen_rtx_SET (VOIDmode, temp,
12630 gen_rtx_IF_THEN_ELSE (result_mode,
12631 gen_rtx_GE (VOIDmode,
12633 true_cond, false_cond)));
12634 true_cond = false_cond;
12637 temp = gen_reg_rtx (compare_mode);
12638 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12643 gcc_unreachable ();
12646 emit_insn (gen_rtx_SET (VOIDmode, dest,
12647 gen_rtx_IF_THEN_ELSE (result_mode,
12648 gen_rtx_GE (VOIDmode,
12650 true_cond, false_cond)));
12654 /* Same as above, but for ints (isel). */
12657 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12659 rtx condition_rtx, cr;
12661 /* All isel implementations thus far are 32-bits. */
12662 if (GET_MODE (rs6000_compare_op0) != SImode)
12665 /* We still have to do the compare, because isel doesn't do a
12666 compare, it just looks at the CRx bits set by a previous compare
12668 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12669 cr = XEXP (condition_rtx, 0);
12671 if (GET_MODE (cr) == CCmode)
12672 emit_insn (gen_isel_signed (dest, condition_rtx,
12673 true_cond, false_cond, cr));
12675 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12676 true_cond, false_cond, cr));
12682 output_isel (rtx *operands)
12684 enum rtx_code code;
12686 code = GET_CODE (operands[1]);
12687 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12689 PUT_CODE (operands[1], reverse_condition (code));
12690 return "isel %0,%3,%2,%j1";
12693 return "isel %0,%2,%3,%j1";
12697 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12699 enum machine_mode mode = GET_MODE (op0);
12703 if (code == SMAX || code == SMIN)
12708 if (code == SMAX || code == UMAX)
12709 target = emit_conditional_move (dest, c, op0, op1, mode,
12710 op0, op1, mode, 0);
12712 target = emit_conditional_move (dest, c, op0, op1, mode,
12713 op1, op0, mode, 0);
12714 gcc_assert (target);
12715 if (target != dest)
12716 emit_move_insn (dest, target);
12719 /* Emit instructions to perform a load-reserved/store-conditional operation.
12720 The operation performed is an atomic
12721 (set M (CODE:MODE M OP))
12722 If not NULL, BEFORE is atomically set to M before the operation, and
12723 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12724 If SYNC_P then a memory barrier is emitted before the operation.
12725 Either OP or M may be wrapped in a NOT operation. */
12728 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12729 rtx m, rtx op, rtx before_param, rtx after_param,
12732 enum machine_mode used_mode;
12733 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12736 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12737 rtx shift = NULL_RTX;
12740 emit_insn (gen_memory_barrier ());
12742 if (GET_CODE (m) == NOT)
12743 used_m = XEXP (m, 0);
12747 /* If this is smaller than SImode, we'll have to use SImode with
12749 if (mode == QImode || mode == HImode)
12753 if (MEM_ALIGN (used_m) >= 32)
12756 if (BYTES_BIG_ENDIAN)
12757 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12759 shift = GEN_INT (ishift);
12763 rtx addrSI, aligned_addr;
12764 int shift_mask = mode == QImode ? 0x18 : 0x10;
12766 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12767 XEXP (used_m, 0)));
12768 shift = gen_reg_rtx (SImode);
12770 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12771 GEN_INT (shift_mask)));
12772 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12774 aligned_addr = expand_binop (Pmode, and_optab,
12776 GEN_INT (-4), NULL_RTX,
12777 1, OPTAB_LIB_WIDEN);
12778 used_m = change_address (used_m, SImode, aligned_addr);
12779 set_mem_align (used_m, 32);
12780 /* It's safe to keep the old alias set of USED_M, because
12781 the operation is atomic and only affects the original
12783 if (GET_CODE (m) == NOT)
12784 m = gen_rtx_NOT (SImode, used_m);
12789 if (GET_CODE (op) == NOT)
12791 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12792 oldop = gen_rtx_NOT (SImode, oldop);
12795 oldop = lowpart_subreg (SImode, op, mode);
12801 newop = expand_binop (SImode, and_optab,
12802 oldop, GEN_INT (imask), NULL_RTX,
12803 1, OPTAB_LIB_WIDEN);
12804 emit_insn (gen_ashlsi3 (newop, newop, shift));
12808 newop = expand_binop (SImode, ior_optab,
12809 oldop, GEN_INT (~imask), NULL_RTX,
12810 1, OPTAB_LIB_WIDEN);
12811 emit_insn (gen_rotlsi3 (newop, newop, shift));
12819 newop = expand_binop (SImode, and_optab,
12820 oldop, GEN_INT (imask), NULL_RTX,
12821 1, OPTAB_LIB_WIDEN);
12822 emit_insn (gen_ashlsi3 (newop, newop, shift));
12824 mask = gen_reg_rtx (SImode);
12825 emit_move_insn (mask, GEN_INT (imask));
12826 emit_insn (gen_ashlsi3 (mask, mask, shift));
12829 newop = gen_rtx_PLUS (SImode, m, newop);
12831 newop = gen_rtx_MINUS (SImode, m, newop);
12832 newop = gen_rtx_AND (SImode, newop, mask);
12833 newop = gen_rtx_IOR (SImode, newop,
12834 gen_rtx_AND (SImode,
12835 gen_rtx_NOT (SImode, mask),
12841 gcc_unreachable ();
12844 if (GET_CODE (m) == NOT)
12848 mask = gen_reg_rtx (SImode);
12849 emit_move_insn (mask, GEN_INT (imask));
12850 emit_insn (gen_ashlsi3 (mask, mask, shift));
12852 xorm = gen_rtx_XOR (SImode, used_m, mask);
12853 /* Depending on the value of 'op', the XOR or the operation might
12854 be able to be simplified away. */
12855 newop = simplify_gen_binary (code, SImode, xorm, newop);
12858 used_mode = SImode;
12859 before = gen_reg_rtx (used_mode);
12860 after = gen_reg_rtx (used_mode);
12865 before = before_param;
12866 after = after_param;
12868 if (before == NULL_RTX)
12869 before = gen_reg_rtx (used_mode);
12870 if (after == NULL_RTX)
12871 after = gen_reg_rtx (used_mode);
12874 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12875 && used_mode != mode)
12876 the_op = op; /* Computed above. */
12877 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12878 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12880 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12882 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12883 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12884 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12885 gen_rtx_UNSPEC (used_mode,
12886 gen_rtvec (1, the_op),
12888 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12890 if ((code == PLUS || code == MINUS) && used_mode != mode)
12891 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12892 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12894 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12895 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12897 /* Shift and mask the return values properly. */
12898 if (used_mode != mode && before_param)
12900 emit_insn (gen_lshrsi3 (before, before, shift));
12901 convert_move (before_param, before, 1);
12904 if (used_mode != mode && after_param)
12906 emit_insn (gen_lshrsi3 (after, after, shift));
12907 convert_move (after_param, after, 1);
12910 /* The previous sequence will end with a branch that's dependent on
12911 the conditional store, so placing an isync will ensure that no
12912 other instructions (especially, no load or store instructions)
12913 can start before the atomic operation completes. */
12915 emit_insn (gen_isync ());
12918 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12919 COND is true. Mark the jump as unlikely to be taken. */
12922 emit_unlikely_jump (rtx cond, rtx label)
12924 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12927 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12928 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12929 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12932 /* A subroutine of the atomic operation splitters. Emit a load-locked
12933 instruction in MODE. */
12936 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12938 rtx (*fn) (rtx, rtx) = NULL;
12939 if (mode == SImode)
12940 fn = gen_load_locked_si;
12941 else if (mode == DImode)
12942 fn = gen_load_locked_di;
12943 emit_insn (fn (reg, mem));
12946 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12947 instruction in MODE. */
12950 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12952 rtx (*fn) (rtx, rtx, rtx) = NULL;
12953 if (mode == SImode)
12954 fn = gen_store_conditional_si;
12955 else if (mode == DImode)
12956 fn = gen_store_conditional_di;
12958 /* Emit sync before stwcx. to address PPC405 Erratum. */
12959 if (PPC405_ERRATUM77)
12960 emit_insn (gen_memory_barrier ());
12962 emit_insn (fn (res, mem, val));
12965 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
12966 to perform. MEM is the memory on which to operate. VAL is the second
12967 operand of the binary operator. BEFORE and AFTER are optional locations to
12968 return the value of MEM either before of after the operation. SCRATCH is
12969 a scratch register. */
12972 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12973 rtx before, rtx after, rtx scratch)
12975 enum machine_mode mode = GET_MODE (mem);
12976 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12978 emit_insn (gen_memory_barrier ());
12980 label = gen_label_rtx ();
12981 emit_label (label);
12982 label = gen_rtx_LABEL_REF (VOIDmode, label);
12984 if (before == NULL_RTX)
12986 emit_load_locked (mode, before, mem);
12989 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12990 else if (code == AND)
12991 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12993 x = gen_rtx_fmt_ee (code, mode, before, val);
12995 if (after != NULL_RTX)
12996 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12997 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12999 emit_store_conditional (mode, cond, mem, scratch);
13001 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13002 emit_unlikely_jump (x, label);
13004 emit_insn (gen_isync ());
13007 /* Expand an atomic compare and swap operation. MEM is the memory on which
13008 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
13009 value to be stored. SCRATCH is a scratch GPR. */
13012 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
13015 enum machine_mode mode = GET_MODE (mem);
13016 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13018 emit_insn (gen_memory_barrier ());
13020 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13021 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13022 emit_label (XEXP (label1, 0));
13024 emit_load_locked (mode, retval, mem);
13026 x = gen_rtx_COMPARE (CCmode, retval, oldval);
13027 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13029 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13030 emit_unlikely_jump (x, label2);
13032 emit_move_insn (scratch, newval);
13033 emit_store_conditional (mode, cond, mem, scratch);
13035 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13036 emit_unlikely_jump (x, label1);
13038 emit_insn (gen_isync ());
13039 emit_label (XEXP (label2, 0));
13042 /* Expand an atomic test and set operation. MEM is the memory on which
13043 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13046 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
13048 enum machine_mode mode = GET_MODE (mem);
13049 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13051 emit_insn (gen_memory_barrier ());
13053 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13054 emit_label (XEXP (label, 0));
13056 emit_load_locked (mode, retval, mem);
13057 emit_move_insn (scratch, val);
13058 emit_store_conditional (mode, cond, mem, scratch);
13060 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13061 emit_unlikely_jump (x, label);
13063 emit_insn (gen_isync ());
13067 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
13069 enum machine_mode mode = GET_MODE (mem);
13070 rtx addrSI, align, wdst, shift, mask;
13071 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
13072 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13074 /* Shift amount for subword relative to aligned word. */
13075 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
13076 shift = gen_reg_rtx (SImode);
13077 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13078 GEN_INT (shift_mask)));
13079 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13081 /* Shift and mask old value into position within word. */
13082 oldval = convert_modes (SImode, mode, oldval, 1);
13083 oldval = expand_binop (SImode, and_optab,
13084 oldval, GEN_INT (imask), NULL_RTX,
13085 1, OPTAB_LIB_WIDEN);
13086 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
13088 /* Shift and mask new value into position within word. */
13089 newval = convert_modes (SImode, mode, newval, 1);
13090 newval = expand_binop (SImode, and_optab,
13091 newval, GEN_INT (imask), NULL_RTX,
13092 1, OPTAB_LIB_WIDEN);
13093 emit_insn (gen_ashlsi3 (newval, newval, shift));
13095 /* Mask for insertion. */
13096 mask = gen_reg_rtx (SImode);
13097 emit_move_insn (mask, GEN_INT (imask));
13098 emit_insn (gen_ashlsi3 (mask, mask, shift));
13100 /* Address of aligned word containing subword. */
13101 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
13102 NULL_RTX, 1, OPTAB_LIB_WIDEN);
13103 mem = change_address (mem, SImode, align);
13104 set_mem_align (mem, 32);
13105 MEM_VOLATILE_P (mem) = 1;
13107 wdst = gen_reg_rtx (SImode);
13108 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
13109 oldval, newval, mem));
13111 emit_move_insn (dst, gen_lowpart (mode, wdst));
13115 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
13116 rtx oldval, rtx newval, rtx mem,
13119 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13121 emit_insn (gen_memory_barrier ());
13122 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13123 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13124 emit_label (XEXP (label1, 0));
13126 emit_load_locked (SImode, scratch, mem);
13128 /* Mask subword within loaded value for comparison with oldval.
13129 Use UNSPEC_AND to avoid clobber.*/
13130 emit_insn (gen_rtx_SET (SImode, dest,
13131 gen_rtx_UNSPEC (SImode,
13132 gen_rtvec (2, scratch, mask),
13135 x = gen_rtx_COMPARE (CCmode, dest, oldval);
13136 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13138 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13139 emit_unlikely_jump (x, label2);
13141 /* Clear subword within loaded value for insertion of new value. */
13142 emit_insn (gen_rtx_SET (SImode, scratch,
13143 gen_rtx_AND (SImode,
13144 gen_rtx_NOT (SImode, mask), scratch)));
13145 emit_insn (gen_iorsi3 (scratch, scratch, newval));
13146 emit_store_conditional (SImode, cond, mem, scratch);
13148 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13149 emit_unlikely_jump (x, label1);
13151 emit_insn (gen_isync ());
13152 emit_label (XEXP (label2, 0));
13156 /* Emit instructions to move SRC to DST. Called by splitters for
13157 multi-register moves. It will emit at most one instruction for
13158 each register that is accessed; that is, it won't emit li/lis pairs
13159 (or equivalent for 64-bit code). One of SRC or DST must be a hard
13163 rs6000_split_multireg_move (rtx dst, rtx src)
13165 /* The register number of the first register being moved. */
13167 /* The mode that is to be moved. */
13168 enum machine_mode mode;
13169 /* The mode that the move is being done in, and its size. */
13170 enum machine_mode reg_mode;
13172 /* The number of registers that will be moved. */
13175 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
13176 mode = GET_MODE (dst);
13177 nregs = hard_regno_nregs[reg][mode];
13178 if (FP_REGNO_P (reg))
13179 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
13180 else if (ALTIVEC_REGNO_P (reg))
13181 reg_mode = V16QImode;
13182 else if (TARGET_E500_DOUBLE && mode == TFmode)
13185 reg_mode = word_mode;
13186 reg_mode_size = GET_MODE_SIZE (reg_mode);
13188 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
13190 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
13192 /* Move register range backwards, if we might have destructive
13195 for (i = nregs - 1; i >= 0; i--)
13196 emit_insn (gen_rtx_SET (VOIDmode,
13197 simplify_gen_subreg (reg_mode, dst, mode,
13198 i * reg_mode_size),
13199 simplify_gen_subreg (reg_mode, src, mode,
13200 i * reg_mode_size)));
13206 bool used_update = false;
13208 if (MEM_P (src) && INT_REGNO_P (reg))
13212 if (GET_CODE (XEXP (src, 0)) == PRE_INC
13213 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
13216 breg = XEXP (XEXP (src, 0), 0);
13217 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
13218 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
13219 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
13220 emit_insn (TARGET_32BIT
13221 ? gen_addsi3 (breg, breg, delta_rtx)
13222 : gen_adddi3 (breg, breg, delta_rtx));
13223 src = replace_equiv_address (src, breg);
13225 else if (! rs6000_offsettable_memref_p (src))
13228 basereg = gen_rtx_REG (Pmode, reg);
13229 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
13230 src = replace_equiv_address (src, basereg);
13233 breg = XEXP (src, 0);
13234 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
13235 breg = XEXP (breg, 0);
13237 /* If the base register we are using to address memory is
13238 also a destination reg, then change that register last. */
13240 && REGNO (breg) >= REGNO (dst)
13241 && REGNO (breg) < REGNO (dst) + nregs)
13242 j = REGNO (breg) - REGNO (dst);
13245 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
13249 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
13250 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
13253 breg = XEXP (XEXP (dst, 0), 0);
13254 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
13255 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
13256 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
13258 /* We have to update the breg before doing the store.
13259 Use store with update, if available. */
13263 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
13264 emit_insn (TARGET_32BIT
13265 ? (TARGET_POWERPC64
13266 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
13267 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
13268 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
13269 used_update = true;
13272 emit_insn (TARGET_32BIT
13273 ? gen_addsi3 (breg, breg, delta_rtx)
13274 : gen_adddi3 (breg, breg, delta_rtx));
13275 dst = replace_equiv_address (dst, breg);
13278 gcc_assert (rs6000_offsettable_memref_p (dst));
13281 for (i = 0; i < nregs; i++)
13283 /* Calculate index to next subword. */
13288 /* If compiler already emitted move of first word by
13289 store with update, no need to do anything. */
13290 if (j == 0 && used_update)
13293 emit_insn (gen_rtx_SET (VOIDmode,
13294 simplify_gen_subreg (reg_mode, dst, mode,
13295 j * reg_mode_size),
13296 simplify_gen_subreg (reg_mode, src, mode,
13297 j * reg_mode_size)));
13303 /* This page contains routines that are used to determine what the
13304 function prologue and epilogue code will do and write them out. */
13306 /* Return the first fixed-point register that is required to be
13307 saved. 32 if none. */
13310 first_reg_to_save (void)
13314 /* Find lowest numbered live register. */
13315 for (first_reg = 13; first_reg <= 31; first_reg++)
13316 if (df_regs_ever_live_p (first_reg)
13317 && (! call_used_regs[first_reg]
13318 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
13319 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13320 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
13321 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
13326 && current_function_uses_pic_offset_table
13327 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
13328 return RS6000_PIC_OFFSET_TABLE_REGNUM;
13334 /* Similar, for FP regs. */
13337 first_fp_reg_to_save (void)
13341 /* Find lowest numbered live register. */
13342 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
13343 if (df_regs_ever_live_p (first_reg))
13349 /* Similar, for AltiVec regs. */
13352 first_altivec_reg_to_save (void)
13356 /* Stack frame remains as is unless we are in AltiVec ABI. */
13357 if (! TARGET_ALTIVEC_ABI)
13358 return LAST_ALTIVEC_REGNO + 1;
13360 /* On Darwin, the unwind routines are compiled without
13361 TARGET_ALTIVEC, and use save_world to save/restore the
13362 altivec registers when necessary. */
13363 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13364 && ! TARGET_ALTIVEC)
13365 return FIRST_ALTIVEC_REGNO + 20;
13367 /* Find lowest numbered live register. */
13368 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
13369 if (df_regs_ever_live_p (i))
13375 /* Return a 32-bit mask of the AltiVec registers we need to set in
13376 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13377 the 32-bit word is 0. */
13379 static unsigned int
13380 compute_vrsave_mask (void)
13382 unsigned int i, mask = 0;
13384 /* On Darwin, the unwind routines are compiled without
13385 TARGET_ALTIVEC, and use save_world to save/restore the
13386 call-saved altivec registers when necessary. */
13387 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13388 && ! TARGET_ALTIVEC)
13391 /* First, find out if we use _any_ altivec registers. */
13392 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13393 if (df_regs_ever_live_p (i))
13394 mask |= ALTIVEC_REG_BIT (i);
13399 /* Next, remove the argument registers from the set. These must
13400 be in the VRSAVE mask set by the caller, so we don't need to add
13401 them in again. More importantly, the mask we compute here is
13402 used to generate CLOBBERs in the set_vrsave insn, and we do not
13403 wish the argument registers to die. */
13404 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
13405 mask &= ~ALTIVEC_REG_BIT (i);
13407 /* Similarly, remove the return value from the set. */
13410 diddle_return_value (is_altivec_return_reg, &yes);
13412 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
13418 /* For a very restricted set of circumstances, we can cut down the
13419 size of prologues/epilogues by calling our own save/restore-the-world
13423 compute_save_world_info (rs6000_stack_t *info_ptr)
13425 info_ptr->world_save_p = 1;
13426 info_ptr->world_save_p
13427 = (WORLD_SAVE_P (info_ptr)
13428 && DEFAULT_ABI == ABI_DARWIN
13429 && ! (current_function_calls_setjmp && flag_exceptions)
13430 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
13431 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
13432 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
13433 && info_ptr->cr_save_p);
13435 /* This will not work in conjunction with sibcalls. Make sure there
13436 are none. (This check is expensive, but seldom executed.) */
13437 if (WORLD_SAVE_P (info_ptr))
13440 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
13441 if ( GET_CODE (insn) == CALL_INSN
13442 && SIBLING_CALL_P (insn))
13444 info_ptr->world_save_p = 0;
13449 if (WORLD_SAVE_P (info_ptr))
13451 /* Even if we're not touching VRsave, make sure there's room on the
13452 stack for it, if it looks like we're calling SAVE_WORLD, which
13453 will attempt to save it. */
13454 info_ptr->vrsave_size = 4;
13456 /* "Save" the VRsave register too if we're saving the world. */
13457 if (info_ptr->vrsave_mask == 0)
13458 info_ptr->vrsave_mask = compute_vrsave_mask ();
13460 /* Because the Darwin register save/restore routines only handle
13461 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13463 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13464 && (info_ptr->first_altivec_reg_save
13465 >= FIRST_SAVED_ALTIVEC_REGNO));
13472 is_altivec_return_reg (rtx reg, void *xyes)
13474 bool *yes = (bool *) xyes;
13475 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13480 /* Calculate the stack information for the current function. This is
13481 complicated by having two separate calling sequences, the AIX calling
13482 sequence and the V.4 calling sequence.
13484 AIX (and Darwin/Mac OS X) stack frames look like:
13486 SP----> +---------------------------------------+
13487 | back chain to caller | 0 0
13488 +---------------------------------------+
13489 | saved CR | 4 8 (8-11)
13490 +---------------------------------------+
13492 +---------------------------------------+
13493 | reserved for compilers | 12 24
13494 +---------------------------------------+
13495 | reserved for binders | 16 32
13496 +---------------------------------------+
13497 | saved TOC pointer | 20 40
13498 +---------------------------------------+
13499 | Parameter save area (P) | 24 48
13500 +---------------------------------------+
13501 | Alloca space (A) | 24+P etc.
13502 +---------------------------------------+
13503 | Local variable space (L) | 24+P+A
13504 +---------------------------------------+
13505 | Float/int conversion temporary (X) | 24+P+A+L
13506 +---------------------------------------+
13507 | Save area for AltiVec registers (W) | 24+P+A+L+X
13508 +---------------------------------------+
13509 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13510 +---------------------------------------+
13511 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13512 +---------------------------------------+
13513 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13514 +---------------------------------------+
13515 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13516 +---------------------------------------+
13517 old SP->| back chain to caller's caller |
13518 +---------------------------------------+
13520 The required alignment for AIX configurations is two words (i.e., 8
13524 V.4 stack frames look like:
13526 SP----> +---------------------------------------+
13527 | back chain to caller | 0
13528 +---------------------------------------+
13529 | caller's saved LR | 4
13530 +---------------------------------------+
13531 | Parameter save area (P) | 8
13532 +---------------------------------------+
13533 | Alloca space (A) | 8+P
13534 +---------------------------------------+
13535 | Varargs save area (V) | 8+P+A
13536 +---------------------------------------+
13537 | Local variable space (L) | 8+P+A+V
13538 +---------------------------------------+
13539 | Float/int conversion temporary (X) | 8+P+A+V+L
13540 +---------------------------------------+
13541 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13542 +---------------------------------------+
13543 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13544 +---------------------------------------+
13545 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13546 +---------------------------------------+
13547 | SPE: area for 64-bit GP registers |
13548 +---------------------------------------+
13549 | SPE alignment padding |
13550 +---------------------------------------+
13551 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13552 +---------------------------------------+
13553 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13554 +---------------------------------------+
13555 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13556 +---------------------------------------+
13557 old SP->| back chain to caller's caller |
13558 +---------------------------------------+
13560 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13561 given. (But note below and in sysv4.h that we require only 8 and
13562 may round up the size of our stack frame anyways. The historical
13563 reason is early versions of powerpc-linux which didn't properly
13564 align the stack at program startup. A happy side-effect is that
13565 -mno-eabi libraries can be used with -meabi programs.)
13567 The EABI configuration defaults to the V.4 layout. However,
13568 the stack alignment requirements may differ. If -mno-eabi is not
13569 given, the required stack alignment is 8 bytes; if -mno-eabi is
13570 given, the required alignment is 16 bytes. (But see V.4 comment
13573 #ifndef ABI_STACK_BOUNDARY
13574 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13577 static rs6000_stack_t *
13578 rs6000_stack_info (void)
13580 static rs6000_stack_t info;
13581 rs6000_stack_t *info_ptr = &info;
13582 int reg_size = TARGET_32BIT ? 4 : 8;
13585 HOST_WIDE_INT non_fixed_size;
13587 memset (&info, 0, sizeof (info));
13591 /* Cache value so we don't rescan instruction chain over and over. */
13592 if (cfun->machine->insn_chain_scanned_p == 0)
13593 cfun->machine->insn_chain_scanned_p
13594 = spe_func_has_64bit_regs_p () + 1;
13595 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13598 /* Select which calling sequence. */
13599 info_ptr->abi = DEFAULT_ABI;
13601 /* Calculate which registers need to be saved & save area size. */
13602 info_ptr->first_gp_reg_save = first_reg_to_save ();
13603 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13604 even if it currently looks like we won't. */
13605 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13606 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13607 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13608 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13609 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
13611 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
13613 /* For the SPE, we have an additional upper 32-bits on each GPR.
13614 Ideally we should save the entire 64-bits only when the upper
13615 half is used in SIMD instructions. Since we only record
13616 registers live (not the size they are used in), this proves
13617 difficult because we'd have to traverse the instruction chain at
13618 the right time, taking reload into account. This is a real pain,
13619 so we opt to save the GPRs in 64-bits always if but one register
13620 gets used in 64-bits. Otherwise, all the registers in the frame
13621 get saved in 32-bits.
13623 So... since when we save all GPRs (except the SP) in 64-bits, the
13624 traditional GP save area will be empty. */
13625 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13626 info_ptr->gp_size = 0;
13628 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13629 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13631 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13632 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13633 - info_ptr->first_altivec_reg_save);
13635 /* Does this function call anything? */
13636 info_ptr->calls_p = (! current_function_is_leaf
13637 || cfun->machine->ra_needs_full_frame);
13639 /* Determine if we need to save the link register. */
13640 if ((DEFAULT_ABI == ABI_AIX
13641 && current_function_profile
13642 && !TARGET_PROFILE_KERNEL)
13643 #ifdef TARGET_RELOCATABLE
13644 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13646 || (info_ptr->first_fp_reg_save != 64
13647 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13648 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13649 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13650 || info_ptr->calls_p
13651 || rs6000_ra_ever_killed ())
13653 info_ptr->lr_save_p = 1;
13654 df_set_regs_ever_live (LR_REGNO, true);
13657 /* Determine if we need to save the condition code registers. */
13658 if (df_regs_ever_live_p (CR2_REGNO)
13659 || df_regs_ever_live_p (CR3_REGNO)
13660 || df_regs_ever_live_p (CR4_REGNO))
13662 info_ptr->cr_save_p = 1;
13663 if (DEFAULT_ABI == ABI_V4)
13664 info_ptr->cr_size = reg_size;
13667 /* If the current function calls __builtin_eh_return, then we need
13668 to allocate stack space for registers that will hold data for
13669 the exception handler. */
13670 if (current_function_calls_eh_return)
13673 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13676 /* SPE saves EH registers in 64-bits. */
13677 ehrd_size = i * (TARGET_SPE_ABI
13678 && info_ptr->spe_64bit_regs_used != 0
13679 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13684 /* Determine various sizes. */
13685 info_ptr->reg_size = reg_size;
13686 info_ptr->fixed_size = RS6000_SAVE_AREA;
13687 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13688 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13689 TARGET_ALTIVEC ? 16 : 8);
13690 if (FRAME_GROWS_DOWNWARD)
13691 info_ptr->vars_size
13692 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13693 + info_ptr->parm_size,
13694 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13695 - (info_ptr->fixed_size + info_ptr->vars_size
13696 + info_ptr->parm_size);
13698 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13699 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13701 info_ptr->spe_gp_size = 0;
13703 if (TARGET_ALTIVEC_ABI)
13704 info_ptr->vrsave_mask = compute_vrsave_mask ();
13706 info_ptr->vrsave_mask = 0;
13708 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13709 info_ptr->vrsave_size = 4;
13711 info_ptr->vrsave_size = 0;
13713 compute_save_world_info (info_ptr);
13715 /* Calculate the offsets. */
13716 switch (DEFAULT_ABI)
13720 gcc_unreachable ();
13724 info_ptr->fp_save_offset = - info_ptr->fp_size;
13725 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13727 if (TARGET_ALTIVEC_ABI)
13729 info_ptr->vrsave_save_offset
13730 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13732 /* Align stack so vector save area is on a quadword boundary.
13733 The padding goes above the vectors. */
13734 if (info_ptr->altivec_size != 0)
13735 info_ptr->altivec_padding_size
13736 = info_ptr->vrsave_save_offset & 0xF;
13738 info_ptr->altivec_padding_size = 0;
13740 info_ptr->altivec_save_offset
13741 = info_ptr->vrsave_save_offset
13742 - info_ptr->altivec_padding_size
13743 - info_ptr->altivec_size;
13744 gcc_assert (info_ptr->altivec_size == 0
13745 || info_ptr->altivec_save_offset % 16 == 0);
13747 /* Adjust for AltiVec case. */
13748 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13751 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13752 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13753 info_ptr->lr_save_offset = 2*reg_size;
13757 info_ptr->fp_save_offset = - info_ptr->fp_size;
13758 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13759 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13761 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13763 /* Align stack so SPE GPR save area is aligned on a
13764 double-word boundary. */
13765 if (info_ptr->spe_gp_size != 0)
13766 info_ptr->spe_padding_size
13767 = 8 - (-info_ptr->cr_save_offset % 8);
13769 info_ptr->spe_padding_size = 0;
13771 info_ptr->spe_gp_save_offset
13772 = info_ptr->cr_save_offset
13773 - info_ptr->spe_padding_size
13774 - info_ptr->spe_gp_size;
13776 /* Adjust for SPE case. */
13777 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13779 else if (TARGET_ALTIVEC_ABI)
13781 info_ptr->vrsave_save_offset
13782 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13784 /* Align stack so vector save area is on a quadword boundary. */
13785 if (info_ptr->altivec_size != 0)
13786 info_ptr->altivec_padding_size
13787 = 16 - (-info_ptr->vrsave_save_offset % 16);
13789 info_ptr->altivec_padding_size = 0;
13791 info_ptr->altivec_save_offset
13792 = info_ptr->vrsave_save_offset
13793 - info_ptr->altivec_padding_size
13794 - info_ptr->altivec_size;
13796 /* Adjust for AltiVec case. */
13797 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13800 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13801 info_ptr->ehrd_offset -= ehrd_size;
13802 info_ptr->lr_save_offset = reg_size;
13806 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13807 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13808 + info_ptr->gp_size
13809 + info_ptr->altivec_size
13810 + info_ptr->altivec_padding_size
13811 + info_ptr->spe_gp_size
13812 + info_ptr->spe_padding_size
13814 + info_ptr->cr_size
13815 + info_ptr->vrsave_size,
13818 non_fixed_size = (info_ptr->vars_size
13819 + info_ptr->parm_size
13820 + info_ptr->save_size);
13822 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13823 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13825 /* Determine if we need to allocate any stack frame:
13827 For AIX we need to push the stack if a frame pointer is needed
13828 (because the stack might be dynamically adjusted), if we are
13829 debugging, if we make calls, or if the sum of fp_save, gp_save,
13830 and local variables are more than the space needed to save all
13831 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13832 + 18*8 = 288 (GPR13 reserved).
13834 For V.4 we don't have the stack cushion that AIX uses, but assume
13835 that the debugger can handle stackless frames. */
13837 if (info_ptr->calls_p)
13838 info_ptr->push_p = 1;
13840 else if (DEFAULT_ABI == ABI_V4)
13841 info_ptr->push_p = non_fixed_size != 0;
13843 else if (frame_pointer_needed)
13844 info_ptr->push_p = 1;
13846 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13847 info_ptr->push_p = 1;
13850 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13852 /* Zero offsets if we're not saving those registers. */
13853 if (info_ptr->fp_size == 0)
13854 info_ptr->fp_save_offset = 0;
13856 if (info_ptr->gp_size == 0)
13857 info_ptr->gp_save_offset = 0;
13859 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13860 info_ptr->altivec_save_offset = 0;
13862 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13863 info_ptr->vrsave_save_offset = 0;
13865 if (! TARGET_SPE_ABI
13866 || info_ptr->spe_64bit_regs_used == 0
13867 || info_ptr->spe_gp_size == 0)
13868 info_ptr->spe_gp_save_offset = 0;
13870 if (! info_ptr->lr_save_p)
13871 info_ptr->lr_save_offset = 0;
13873 if (! info_ptr->cr_save_p)
13874 info_ptr->cr_save_offset = 0;
13879 /* Return true if the current function uses any GPRs in 64-bit SIMD
13883 spe_func_has_64bit_regs_p (void)
13887 /* Functions that save and restore all the call-saved registers will
13888 need to save/restore the registers in 64-bits. */
13889 if (current_function_calls_eh_return
13890 || current_function_calls_setjmp
13891 || current_function_has_nonlocal_goto)
13894 insns = get_insns ();
13896 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13902 /* FIXME: This should be implemented with attributes...
13904 (set_attr "spe64" "true")....then,
13905 if (get_spe64(insn)) return true;
13907 It's the only reliable way to do the stuff below. */
13909 i = PATTERN (insn);
13910 if (GET_CODE (i) == SET)
13912 enum machine_mode mode = GET_MODE (SET_SRC (i));
13914 if (SPE_VECTOR_MODE (mode))
13916 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
13926 debug_stack_info (rs6000_stack_t *info)
13928 const char *abi_string;
13931 info = rs6000_stack_info ();
13933 fprintf (stderr, "\nStack information for function %s:\n",
13934 ((current_function_decl && DECL_NAME (current_function_decl))
13935 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13940 default: abi_string = "Unknown"; break;
13941 case ABI_NONE: abi_string = "NONE"; break;
13942 case ABI_AIX: abi_string = "AIX"; break;
13943 case ABI_DARWIN: abi_string = "Darwin"; break;
13944 case ABI_V4: abi_string = "V.4"; break;
13947 fprintf (stderr, "\tABI = %5s\n", abi_string);
13949 if (TARGET_ALTIVEC_ABI)
13950 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13952 if (TARGET_SPE_ABI)
13953 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13955 if (info->first_gp_reg_save != 32)
13956 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13958 if (info->first_fp_reg_save != 64)
13959 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13961 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13962 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13963 info->first_altivec_reg_save);
13965 if (info->lr_save_p)
13966 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13968 if (info->cr_save_p)
13969 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13971 if (info->vrsave_mask)
13972 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13975 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13978 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13980 if (info->gp_save_offset)
13981 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13983 if (info->fp_save_offset)
13984 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13986 if (info->altivec_save_offset)
13987 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13988 info->altivec_save_offset);
13990 if (info->spe_gp_save_offset)
13991 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13992 info->spe_gp_save_offset);
13994 if (info->vrsave_save_offset)
13995 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13996 info->vrsave_save_offset);
13998 if (info->lr_save_offset)
13999 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
14001 if (info->cr_save_offset)
14002 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
14004 if (info->varargs_save_offset)
14005 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
14007 if (info->total_size)
14008 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14011 if (info->vars_size)
14012 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14015 if (info->parm_size)
14016 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
14018 if (info->fixed_size)
14019 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
14022 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
14024 if (info->spe_gp_size)
14025 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
14028 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
14030 if (info->altivec_size)
14031 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
14033 if (info->vrsave_size)
14034 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
14036 if (info->altivec_padding_size)
14037 fprintf (stderr, "\taltivec_padding_size= %5d\n",
14038 info->altivec_padding_size);
14040 if (info->spe_padding_size)
14041 fprintf (stderr, "\tspe_padding_size = %5d\n",
14042 info->spe_padding_size);
14045 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
14047 if (info->save_size)
14048 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
14050 if (info->reg_size != 4)
14051 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
14053 fprintf (stderr, "\n");
14057 rs6000_return_addr (int count, rtx frame)
14059 /* Currently we don't optimize very well between prolog and body
14060 code and for PIC code the code can be actually quite bad, so
14061 don't try to be too clever here. */
14062 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
14064 cfun->machine->ra_needs_full_frame = 1;
14071 plus_constant (copy_to_reg
14072 (gen_rtx_MEM (Pmode,
14073 memory_address (Pmode, frame))),
14074 RETURN_ADDRESS_OFFSET)));
14077 cfun->machine->ra_need_lr = 1;
14078 return get_hard_reg_initial_val (Pmode, LR_REGNO);
14081 /* Say whether a function is a candidate for sibcall handling or not.
14082 We do not allow indirect calls to be optimized into sibling calls.
14083 Also, we can't do it if there are any vector parameters; there's
14084 nowhere to put the VRsave code so it works; note that functions with
14085 vector parameters are required to have a prototype, so the argument
14086 type info must be available here. (The tail recursion case can work
14087 with vector parameters, but there's no way to distinguish here.) */
14089 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
14094 if (TARGET_ALTIVEC_VRSAVE)
14096 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
14097 type; type = TREE_CHAIN (type))
14099 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
14103 if (DEFAULT_ABI == ABI_DARWIN
14104 || ((*targetm.binds_local_p) (decl)
14105 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
14107 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
14109 if (!lookup_attribute ("longcall", attr_list)
14110 || lookup_attribute ("shortcall", attr_list))
14117 /* NULL if INSN insn is valid within a low-overhead loop.
14118 Otherwise return why doloop cannot be applied.
14119 PowerPC uses the COUNT register for branch on table instructions. */
14121 static const char *
14122 rs6000_invalid_within_doloop (const_rtx insn)
14125 return "Function call in the loop.";
14128 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
14129 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
14130 return "Computed branch in the loop.";
14136 rs6000_ra_ever_killed (void)
14142 if (current_function_is_thunk)
14145 /* regs_ever_live has LR marked as used if any sibcalls are present,
14146 but this should not force saving and restoring in the
14147 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
14148 clobbers LR, so that is inappropriate. */
14150 /* Also, the prologue can generate a store into LR that
14151 doesn't really count, like this:
14154 bcl to set PIC register
14158 When we're called from the epilogue, we need to avoid counting
14159 this as a store. */
14161 push_topmost_sequence ();
14162 top = get_insns ();
14163 pop_topmost_sequence ();
14164 reg = gen_rtx_REG (Pmode, LR_REGNO);
14166 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
14172 if (!SIBLING_CALL_P (insn))
14175 else if (find_regno_note (insn, REG_INC, LR_REGNO))
14177 else if (set_of (reg, insn) != NULL_RTX
14178 && !prologue_epilogue_contains (insn))
14185 /* Emit instructions needed to load the TOC register.
14186 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14187 a constant pool; or for SVR4 -fpic. */
14190 rs6000_emit_load_toc_table (int fromprolog)
14193 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
14195 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
14198 rtx lab, tmp1, tmp2, got;
14200 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14201 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14203 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14205 got = rs6000_got_sym ();
14206 tmp1 = tmp2 = dest;
14209 tmp1 = gen_reg_rtx (Pmode);
14210 tmp2 = gen_reg_rtx (Pmode);
14212 emit_insn (gen_load_toc_v4_PIC_1 (lab));
14213 emit_move_insn (tmp1,
14214 gen_rtx_REG (Pmode, LR_REGNO));
14215 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
14216 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
14218 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
14220 emit_insn (gen_load_toc_v4_pic_si ());
14221 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
14223 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
14226 rtx temp0 = (fromprolog
14227 ? gen_rtx_REG (Pmode, 0)
14228 : gen_reg_rtx (Pmode));
14234 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14235 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14237 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
14238 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14240 emit_insn (gen_load_toc_v4_PIC_1 (symF));
14241 emit_move_insn (dest,
14242 gen_rtx_REG (Pmode, LR_REGNO));
14243 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
14249 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14250 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
14251 emit_move_insn (dest,
14252 gen_rtx_REG (Pmode, LR_REGNO));
14253 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
14255 emit_insn (gen_addsi3 (dest, temp0, dest));
14257 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
14259 /* This is for AIX code running in non-PIC ELF32. */
14262 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
14263 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14265 emit_insn (gen_elf_high (dest, realsym));
14266 emit_insn (gen_elf_low (dest, dest, realsym));
14270 gcc_assert (DEFAULT_ABI == ABI_AIX);
14273 emit_insn (gen_load_toc_aix_si (dest));
14275 emit_insn (gen_load_toc_aix_di (dest));
14279 /* Emit instructions to restore the link register after determining where
14280 its value has been stored. */
14283 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
14285 rs6000_stack_t *info = rs6000_stack_info ();
14288 operands[0] = source;
14289 operands[1] = scratch;
14291 if (info->lr_save_p)
14293 rtx frame_rtx = stack_pointer_rtx;
14294 HOST_WIDE_INT sp_offset = 0;
14297 if (frame_pointer_needed
14298 || current_function_calls_alloca
14299 || info->total_size > 32767)
14301 tmp = gen_frame_mem (Pmode, frame_rtx);
14302 emit_move_insn (operands[1], tmp);
14303 frame_rtx = operands[1];
14305 else if (info->push_p)
14306 sp_offset = info->total_size;
14308 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14309 tmp = gen_frame_mem (Pmode, tmp);
14310 emit_move_insn (tmp, operands[0]);
14313 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
14316 static GTY(()) alias_set_type set = -1;
14319 get_TOC_alias_set (void)
14322 set = new_alias_set ();
14326 /* This returns nonzero if the current function uses the TOC. This is
14327 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14328 is generated by the ABI_V4 load_toc_* patterns. */
14335 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14338 rtx pat = PATTERN (insn);
14341 if (GET_CODE (pat) == PARALLEL)
14342 for (i = 0; i < XVECLEN (pat, 0); i++)
14344 rtx sub = XVECEXP (pat, 0, i);
14345 if (GET_CODE (sub) == USE)
14347 sub = XEXP (sub, 0);
14348 if (GET_CODE (sub) == UNSPEC
14349 && XINT (sub, 1) == UNSPEC_TOC)
14359 create_TOC_reference (rtx symbol)
14361 if (!can_create_pseudo_p ())
14362 df_set_regs_ever_live (TOC_REGISTER, true);
14363 return gen_rtx_PLUS (Pmode,
14364 gen_rtx_REG (Pmode, TOC_REGISTER),
14365 gen_rtx_CONST (Pmode,
14366 gen_rtx_MINUS (Pmode, symbol,
14367 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
14370 /* If _Unwind_* has been called from within the same module,
14371 toc register is not guaranteed to be saved to 40(1) on function
14372 entry. Save it there in that case. */
14375 rs6000_aix_emit_builtin_unwind_init (void)
14378 rtx stack_top = gen_reg_rtx (Pmode);
14379 rtx opcode_addr = gen_reg_rtx (Pmode);
14380 rtx opcode = gen_reg_rtx (SImode);
14381 rtx tocompare = gen_reg_rtx (SImode);
14382 rtx no_toc_save_needed = gen_label_rtx ();
14384 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
14385 emit_move_insn (stack_top, mem);
14387 mem = gen_frame_mem (Pmode,
14388 gen_rtx_PLUS (Pmode, stack_top,
14389 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
14390 emit_move_insn (opcode_addr, mem);
14391 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
14392 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
14393 : 0xE8410028, SImode));
14395 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
14396 SImode, NULL_RTX, NULL_RTX,
14397 no_toc_save_needed);
14399 mem = gen_frame_mem (Pmode,
14400 gen_rtx_PLUS (Pmode, stack_top,
14401 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
14402 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
14403 emit_label (no_toc_save_needed);
14406 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14407 and the change to the stack pointer. */
14410 rs6000_emit_stack_tie (void)
14412 rtx mem = gen_frame_mem (BLKmode,
14413 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14415 emit_insn (gen_stack_tie (mem));
14418 /* Emit the correct code for allocating stack space, as insns.
14419 If COPY_R12, make sure a copy of the old frame is left in r12.
14420 The generated code may use hard register 0 as a temporary. */
14423 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14426 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14427 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14428 rtx todec = gen_int_mode (-size, Pmode);
14430 if (INTVAL (todec) != -size)
14432 warning (0, "stack frame too large");
14433 emit_insn (gen_trap ());
14437 if (current_function_limit_stack)
14439 if (REG_P (stack_limit_rtx)
14440 && REGNO (stack_limit_rtx) > 1
14441 && REGNO (stack_limit_rtx) <= 31)
14443 emit_insn (TARGET_32BIT
14444 ? gen_addsi3 (tmp_reg,
14447 : gen_adddi3 (tmp_reg,
14451 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14454 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14456 && DEFAULT_ABI == ABI_V4)
14458 rtx toload = gen_rtx_CONST (VOIDmode,
14459 gen_rtx_PLUS (Pmode,
14463 emit_insn (gen_elf_high (tmp_reg, toload));
14464 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14465 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14469 warning (0, "stack limit expression is not supported");
14472 if (copy_r12 || ! TARGET_UPDATE)
14473 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14479 /* Need a note here so that try_split doesn't get confused. */
14480 if (get_last_insn () == NULL_RTX)
14481 emit_note (NOTE_INSN_DELETED);
14482 insn = emit_move_insn (tmp_reg, todec);
14483 try_split (PATTERN (insn), insn, 0);
14487 insn = emit_insn (TARGET_32BIT
14488 ? gen_movsi_update (stack_reg, stack_reg,
14490 : gen_movdi_di_update (stack_reg, stack_reg,
14491 todec, stack_reg));
14495 insn = emit_insn (TARGET_32BIT
14496 ? gen_addsi3 (stack_reg, stack_reg, todec)
14497 : gen_adddi3 (stack_reg, stack_reg, todec));
14498 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14499 gen_rtx_REG (Pmode, 12));
14502 RTX_FRAME_RELATED_P (insn) = 1;
14504 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14505 gen_rtx_SET (VOIDmode, stack_reg,
14506 gen_rtx_PLUS (Pmode, stack_reg,
14511 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14512 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14513 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14514 deduce these equivalences by itself so it wasn't necessary to hold
14515 its hand so much. */
14518 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14519 rtx reg2, rtx rreg)
14523 /* copy_rtx will not make unique copies of registers, so we need to
14524 ensure we don't have unwanted sharing here. */
14526 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14529 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14531 real = copy_rtx (PATTERN (insn));
14533 if (reg2 != NULL_RTX)
14534 real = replace_rtx (real, reg2, rreg);
14536 real = replace_rtx (real, reg,
14537 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14538 STACK_POINTER_REGNUM),
14541 /* We expect that 'real' is either a SET or a PARALLEL containing
14542 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14543 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14545 if (GET_CODE (real) == SET)
14549 temp = simplify_rtx (SET_SRC (set));
14551 SET_SRC (set) = temp;
14552 temp = simplify_rtx (SET_DEST (set));
14554 SET_DEST (set) = temp;
14555 if (GET_CODE (SET_DEST (set)) == MEM)
14557 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14559 XEXP (SET_DEST (set), 0) = temp;
14566 gcc_assert (GET_CODE (real) == PARALLEL);
14567 for (i = 0; i < XVECLEN (real, 0); i++)
14568 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14570 rtx set = XVECEXP (real, 0, i);
14572 temp = simplify_rtx (SET_SRC (set));
14574 SET_SRC (set) = temp;
14575 temp = simplify_rtx (SET_DEST (set));
14577 SET_DEST (set) = temp;
14578 if (GET_CODE (SET_DEST (set)) == MEM)
14580 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14582 XEXP (SET_DEST (set), 0) = temp;
14584 RTX_FRAME_RELATED_P (set) = 1;
14589 real = spe_synthesize_frame_save (real);
14591 RTX_FRAME_RELATED_P (insn) = 1;
14592 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14597 /* Given an SPE frame note, return a PARALLEL of SETs with the
14598 original note, plus a synthetic register save. */
14601 spe_synthesize_frame_save (rtx real)
14603 rtx synth, offset, reg, real2;
14605 if (GET_CODE (real) != SET
14606 || GET_MODE (SET_SRC (real)) != V2SImode)
14609 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14610 frame related note. The parallel contains a set of the register
14611 being saved, and another set to a synthetic register (n+1200).
14612 This is so we can differentiate between 64-bit and 32-bit saves.
14613 Words cannot describe this nastiness. */
14615 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14616 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14617 && GET_CODE (SET_SRC (real)) == REG);
14620 (set (mem (plus (reg x) (const y)))
14623 (set (mem (plus (reg x) (const y+4)))
14627 real2 = copy_rtx (real);
14628 PUT_MODE (SET_DEST (real2), SImode);
14629 reg = SET_SRC (real2);
14630 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14631 synth = copy_rtx (real2);
14633 if (BYTES_BIG_ENDIAN)
14635 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14636 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14639 reg = SET_SRC (synth);
14641 synth = replace_rtx (synth, reg,
14642 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14644 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14645 synth = replace_rtx (synth, offset,
14646 GEN_INT (INTVAL (offset)
14647 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14649 RTX_FRAME_RELATED_P (synth) = 1;
14650 RTX_FRAME_RELATED_P (real2) = 1;
14651 if (BYTES_BIG_ENDIAN)
14652 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14654 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14659 /* Returns an insn that has a vrsave set operation with the
14660 appropriate CLOBBERs. */
14663 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14666 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14667 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14670 = gen_rtx_SET (VOIDmode,
14672 gen_rtx_UNSPEC_VOLATILE (SImode,
14673 gen_rtvec (2, reg, vrsave),
14674 UNSPECV_SET_VRSAVE));
14678 /* We need to clobber the registers in the mask so the scheduler
14679 does not move sets to VRSAVE before sets of AltiVec registers.
14681 However, if the function receives nonlocal gotos, reload will set
14682 all call saved registers live. We will end up with:
14684 (set (reg 999) (mem))
14685 (parallel [ (set (reg vrsave) (unspec blah))
14686 (clobber (reg 999))])
14688 The clobber will cause the store into reg 999 to be dead, and
14689 flow will attempt to delete an epilogue insn. In this case, we
14690 need an unspec use/set of the register. */
14692 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14693 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14695 if (!epiloguep || call_used_regs [i])
14696 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14697 gen_rtx_REG (V4SImode, i));
14700 rtx reg = gen_rtx_REG (V4SImode, i);
14703 = gen_rtx_SET (VOIDmode,
14705 gen_rtx_UNSPEC (V4SImode,
14706 gen_rtvec (1, reg), 27));
14710 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14712 for (i = 0; i < nclobs; ++i)
14713 XVECEXP (insn, 0, i) = clobs[i];
14718 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14719 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14722 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14723 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14725 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14726 rtx replacea, replaceb;
14728 int_rtx = GEN_INT (offset);
14730 /* Some cases that need register indexed addressing. */
14731 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14732 || (TARGET_E500_DOUBLE && mode == DFmode)
14734 && SPE_VECTOR_MODE (mode)
14735 && !SPE_CONST_OFFSET_OK (offset)))
14737 /* Whomever calls us must make sure r11 is available in the
14738 flow path of instructions in the prologue. */
14739 offset_rtx = gen_rtx_REG (Pmode, 11);
14740 emit_move_insn (offset_rtx, int_rtx);
14742 replacea = offset_rtx;
14743 replaceb = int_rtx;
14747 offset_rtx = int_rtx;
14748 replacea = NULL_RTX;
14749 replaceb = NULL_RTX;
14752 reg = gen_rtx_REG (mode, regno);
14753 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14754 mem = gen_frame_mem (mode, addr);
14756 insn = emit_move_insn (mem, reg);
14758 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14761 /* Emit an offset memory reference suitable for a frame store, while
14762 converting to a valid addressing mode. */
14765 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14767 rtx int_rtx, offset_rtx;
14769 int_rtx = GEN_INT (offset);
14771 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14772 || (TARGET_E500_DOUBLE && mode == DFmode))
14774 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14775 emit_move_insn (offset_rtx, int_rtx);
14778 offset_rtx = int_rtx;
14780 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14783 /* Look for user-defined global regs. We should not save and restore these,
14784 and cannot use stmw/lmw if there are any in its range. */
14787 no_global_regs_above (int first_greg)
14790 for (i = 0; i < 32 - first_greg; i++)
14791 if (global_regs[first_greg + i])
14796 #ifndef TARGET_FIX_AND_CONTINUE
14797 #define TARGET_FIX_AND_CONTINUE 0
14800 /* Determine whether the gp REG is really used. */
14803 rs6000_reg_live_or_pic_offset_p (int reg)
14805 return ((df_regs_ever_live_p (reg)
14806 && (!call_used_regs[reg]
14807 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14808 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14809 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14810 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14811 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
14814 /* Emit function prologue as insns. */
14817 rs6000_emit_prologue (void)
14819 rs6000_stack_t *info = rs6000_stack_info ();
14820 enum machine_mode reg_mode = Pmode;
14821 int reg_size = TARGET_32BIT ? 4 : 8;
14822 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14823 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14824 rtx frame_reg_rtx = sp_reg_rtx;
14825 rtx cr_save_rtx = NULL_RTX;
14827 int saving_FPRs_inline;
14828 int using_store_multiple;
14829 HOST_WIDE_INT sp_offset = 0;
14831 if (TARGET_FIX_AND_CONTINUE)
14833 /* gdb on darwin arranges to forward a function from the old
14834 address by modifying the first 5 instructions of the function
14835 to branch to the overriding function. This is necessary to
14836 permit function pointers that point to the old function to
14837 actually forward to the new function. */
14838 emit_insn (gen_nop ());
14839 emit_insn (gen_nop ());
14840 emit_insn (gen_nop ());
14841 emit_insn (gen_nop ());
14842 emit_insn (gen_nop ());
14845 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14847 reg_mode = V2SImode;
14851 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14852 && (!TARGET_SPE_ABI
14853 || info->spe_64bit_regs_used == 0)
14854 && info->first_gp_reg_save < 31
14855 && no_global_regs_above (info->first_gp_reg_save));
14856 saving_FPRs_inline = (info->first_fp_reg_save == 64
14857 || FP_SAVE_INLINE (info->first_fp_reg_save)
14858 || current_function_calls_eh_return
14859 || cfun->machine->ra_need_lr);
14861 /* For V.4, update stack before we do any saving and set back pointer. */
14862 if (! WORLD_SAVE_P (info)
14864 && (DEFAULT_ABI == ABI_V4
14865 || current_function_calls_eh_return))
14867 if (info->total_size < 32767)
14868 sp_offset = info->total_size;
14870 frame_reg_rtx = frame_ptr_rtx;
14871 rs6000_emit_allocate_stack (info->total_size,
14872 (frame_reg_rtx != sp_reg_rtx
14873 && (info->cr_save_p
14875 || info->first_fp_reg_save < 64
14876 || info->first_gp_reg_save < 32
14878 if (frame_reg_rtx != sp_reg_rtx)
14879 rs6000_emit_stack_tie ();
14882 /* Handle world saves specially here. */
14883 if (WORLD_SAVE_P (info))
14890 /* save_world expects lr in r0. */
14891 reg0 = gen_rtx_REG (Pmode, 0);
14892 if (info->lr_save_p)
14894 insn = emit_move_insn (reg0,
14895 gen_rtx_REG (Pmode, LR_REGNO));
14896 RTX_FRAME_RELATED_P (insn) = 1;
14899 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14900 assumptions about the offsets of various bits of the stack
14902 gcc_assert (info->gp_save_offset == -220
14903 && info->fp_save_offset == -144
14904 && info->lr_save_offset == 8
14905 && info->cr_save_offset == 4
14908 && (!current_function_calls_eh_return
14909 || info->ehrd_offset == -432)
14910 && info->vrsave_save_offset == -224
14911 && info->altivec_save_offset == -416);
14913 treg = gen_rtx_REG (SImode, 11);
14914 emit_move_insn (treg, GEN_INT (-info->total_size));
14916 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14917 in R11. It also clobbers R12, so beware! */
14919 /* Preserve CR2 for save_world prologues */
14921 sz += 32 - info->first_gp_reg_save;
14922 sz += 64 - info->first_fp_reg_save;
14923 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14924 p = rtvec_alloc (sz);
14926 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14927 gen_rtx_REG (SImode,
14929 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14930 gen_rtx_SYMBOL_REF (Pmode,
14932 /* We do floats first so that the instruction pattern matches
14934 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14936 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14937 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14938 GEN_INT (info->fp_save_offset
14939 + sp_offset + 8 * i));
14940 rtx mem = gen_frame_mem (DFmode, addr);
14942 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14944 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14946 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14947 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14948 GEN_INT (info->altivec_save_offset
14949 + sp_offset + 16 * i));
14950 rtx mem = gen_frame_mem (V4SImode, addr);
14952 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14954 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14956 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14957 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14958 GEN_INT (info->gp_save_offset
14959 + sp_offset + reg_size * i));
14960 rtx mem = gen_frame_mem (reg_mode, addr);
14962 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14966 /* CR register traditionally saved as CR2. */
14967 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14968 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14969 GEN_INT (info->cr_save_offset
14971 rtx mem = gen_frame_mem (reg_mode, addr);
14973 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14975 /* Explain about use of R0. */
14976 if (info->lr_save_p)
14978 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14979 GEN_INT (info->lr_save_offset
14981 rtx mem = gen_frame_mem (reg_mode, addr);
14983 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
14985 /* Explain what happens to the stack pointer. */
14987 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
14988 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
14991 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14992 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14993 treg, GEN_INT (-info->total_size));
14994 sp_offset = info->total_size;
14997 /* If we use the link register, get it into r0. */
14998 if (!WORLD_SAVE_P (info) && info->lr_save_p)
15000 rtx addr, reg, mem;
15002 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
15003 gen_rtx_REG (Pmode, LR_REGNO));
15004 RTX_FRAME_RELATED_P (insn) = 1;
15006 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15007 GEN_INT (info->lr_save_offset + sp_offset));
15008 reg = gen_rtx_REG (Pmode, 0);
15009 mem = gen_rtx_MEM (Pmode, addr);
15010 /* This should not be of rs6000_sr_alias_set, because of
15011 __builtin_return_address. */
15013 insn = emit_move_insn (mem, reg);
15014 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15015 NULL_RTX, NULL_RTX);
15018 /* If we need to save CR, put it into r12. */
15019 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
15023 cr_save_rtx = gen_rtx_REG (SImode, 12);
15024 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15025 RTX_FRAME_RELATED_P (insn) = 1;
15026 /* Now, there's no way that dwarf2out_frame_debug_expr is going
15027 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
15028 But that's OK. All we have to do is specify that _one_ condition
15029 code register is saved in this stack slot. The thrower's epilogue
15030 will then restore all the call-saved registers.
15031 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
15032 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
15033 gen_rtx_REG (SImode, CR2_REGNO));
15034 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15039 /* Do any required saving of fpr's. If only one or two to save, do
15040 it ourselves. Otherwise, call function. */
15041 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
15044 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15045 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15046 && ! call_used_regs[info->first_fp_reg_save+i]))
15047 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
15048 info->first_fp_reg_save + i,
15049 info->fp_save_offset + sp_offset + 8 * i,
15052 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
15056 const char *alloc_rname;
15058 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
15060 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
15061 gen_rtx_REG (Pmode,
15063 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
15064 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
15065 alloc_rname = ggc_strdup (rname);
15066 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15067 gen_rtx_SYMBOL_REF (Pmode,
15069 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15071 rtx addr, reg, mem;
15072 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15073 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15074 GEN_INT (info->fp_save_offset
15075 + sp_offset + 8*i));
15076 mem = gen_frame_mem (DFmode, addr);
15078 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
15080 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15081 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15082 NULL_RTX, NULL_RTX);
15085 /* Save GPRs. This is done as a PARALLEL if we are using
15086 the store-multiple instructions. */
15087 if (!WORLD_SAVE_P (info) && using_store_multiple)
15091 p = rtvec_alloc (32 - info->first_gp_reg_save);
15092 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15094 rtx addr, reg, mem;
15095 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15096 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15097 GEN_INT (info->gp_save_offset
15100 mem = gen_frame_mem (reg_mode, addr);
15102 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
15104 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15105 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15106 NULL_RTX, NULL_RTX);
15108 else if (!WORLD_SAVE_P (info)
15110 && info->spe_64bit_regs_used != 0
15111 && info->first_gp_reg_save != 32)
15114 rtx spe_save_area_ptr;
15115 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
15116 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
15117 && !call_used_regs[STATIC_CHAIN_REGNUM]);
15119 /* Determine whether we can address all of the registers that need
15120 to be saved with an offset from the stack pointer that fits in
15121 the small const field for SPE memory instructions. */
15122 int spe_regs_addressable_via_sp
15123 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15124 + (32 - info->first_gp_reg_save - 1) * reg_size);
15127 if (spe_regs_addressable_via_sp)
15129 spe_save_area_ptr = sp_reg_rtx;
15130 spe_offset = info->spe_gp_save_offset + sp_offset;
15134 /* Make r11 point to the start of the SPE save area. We need
15135 to be careful here if r11 is holding the static chain. If
15136 it is, then temporarily save it in r0. We would use r0 as
15137 our base register here, but using r0 as a base register in
15138 loads and stores means something different from what we
15140 if (using_static_chain_p)
15142 rtx r0 = gen_rtx_REG (Pmode, 0);
15144 gcc_assert (info->first_gp_reg_save > 11);
15146 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
15149 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15150 emit_insn (gen_addsi3 (spe_save_area_ptr, sp_reg_rtx,
15151 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15156 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15157 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15159 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15160 rtx offset, addr, mem;
15162 /* We're doing all this to ensure that the offset fits into
15163 the immediate offset of 'evstdd'. */
15164 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
15166 offset = GEN_INT (reg_size * i + spe_offset);
15167 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15168 mem = gen_rtx_MEM (V2SImode, addr);
15170 insn = emit_move_insn (mem, reg);
15172 rs6000_frame_related (insn, spe_save_area_ptr,
15173 info->spe_gp_save_offset
15174 + sp_offset + reg_size * i,
15175 offset, const0_rtx);
15178 /* Move the static chain pointer back. */
15179 if (using_static_chain_p && !spe_regs_addressable_via_sp)
15180 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
15182 else if (!WORLD_SAVE_P (info))
15185 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15186 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15188 rtx addr, reg, mem;
15189 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15191 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15192 GEN_INT (info->gp_save_offset
15195 mem = gen_frame_mem (reg_mode, addr);
15197 insn = emit_move_insn (mem, reg);
15198 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15199 NULL_RTX, NULL_RTX);
15203 /* ??? There's no need to emit actual instructions here, but it's the
15204 easiest way to get the frame unwind information emitted. */
15205 if (current_function_calls_eh_return)
15207 unsigned int i, regno;
15209 /* In AIX ABI we need to pretend we save r2 here. */
15212 rtx addr, reg, mem;
15214 reg = gen_rtx_REG (reg_mode, 2);
15215 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15216 GEN_INT (sp_offset + 5 * reg_size));
15217 mem = gen_frame_mem (reg_mode, addr);
15219 insn = emit_move_insn (mem, reg);
15220 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15221 NULL_RTX, NULL_RTX);
15222 PATTERN (insn) = gen_blockage ();
15227 regno = EH_RETURN_DATA_REGNO (i);
15228 if (regno == INVALID_REGNUM)
15231 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
15232 info->ehrd_offset + sp_offset
15233 + reg_size * (int) i,
15238 /* Save CR if we use any that must be preserved. */
15239 if (!WORLD_SAVE_P (info) && info->cr_save_p)
15241 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15242 GEN_INT (info->cr_save_offset + sp_offset));
15243 rtx mem = gen_frame_mem (SImode, addr);
15244 /* See the large comment above about why CR2_REGNO is used. */
15245 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
15247 /* If r12 was used to hold the original sp, copy cr into r0 now
15249 if (REGNO (frame_reg_rtx) == 12)
15253 cr_save_rtx = gen_rtx_REG (SImode, 0);
15254 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15255 RTX_FRAME_RELATED_P (insn) = 1;
15256 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
15257 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15262 insn = emit_move_insn (mem, cr_save_rtx);
15264 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15265 NULL_RTX, NULL_RTX);
15268 /* Update stack and set back pointer unless this is V.4,
15269 for which it was done previously. */
15270 if (!WORLD_SAVE_P (info) && info->push_p
15271 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
15273 if (info->total_size < 32767)
15274 sp_offset = info->total_size;
15276 frame_reg_rtx = frame_ptr_rtx;
15277 rs6000_emit_allocate_stack (info->total_size,
15278 (frame_reg_rtx != sp_reg_rtx
15279 && ((info->altivec_size != 0)
15280 || (info->vrsave_mask != 0)
15282 if (frame_reg_rtx != sp_reg_rtx)
15283 rs6000_emit_stack_tie ();
15286 /* Set frame pointer, if needed. */
15287 if (frame_pointer_needed)
15289 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
15291 RTX_FRAME_RELATED_P (insn) = 1;
15294 /* Save AltiVec registers if needed. Save here because the red zone does
15295 not include AltiVec registers. */
15296 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15300 /* There should be a non inline version of this, for when we
15301 are saving lots of vector registers. */
15302 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15303 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15305 rtx areg, savereg, mem;
15308 offset = info->altivec_save_offset + sp_offset
15309 + 16 * (i - info->first_altivec_reg_save);
15311 savereg = gen_rtx_REG (V4SImode, i);
15313 areg = gen_rtx_REG (Pmode, 0);
15314 emit_move_insn (areg, GEN_INT (offset));
15316 /* AltiVec addressing mode is [reg+reg]. */
15317 mem = gen_frame_mem (V4SImode,
15318 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
15320 insn = emit_move_insn (mem, savereg);
15322 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15323 areg, GEN_INT (offset));
15327 /* VRSAVE is a bit vector representing which AltiVec registers
15328 are used. The OS uses this to determine which vector
15329 registers to save on a context switch. We need to save
15330 VRSAVE on the stack frame, add whatever AltiVec registers we
15331 used in this function, and do the corresponding magic in the
15334 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15335 && info->vrsave_mask != 0)
15337 rtx reg, mem, vrsave;
15340 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
15341 as frame_reg_rtx and r11 as the static chain pointer for
15342 nested functions. */
15343 reg = gen_rtx_REG (SImode, 0);
15344 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15346 emit_insn (gen_get_vrsave_internal (reg));
15348 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
15350 if (!WORLD_SAVE_P (info))
15353 offset = info->vrsave_save_offset + sp_offset;
15354 mem = gen_frame_mem (SImode,
15355 gen_rtx_PLUS (Pmode, frame_reg_rtx,
15356 GEN_INT (offset)));
15357 insn = emit_move_insn (mem, reg);
15360 /* Include the registers in the mask. */
15361 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
15363 insn = emit_insn (generate_set_vrsave (reg, info, 0));
15366 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15367 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
15368 || (DEFAULT_ABI == ABI_V4
15369 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
15370 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
15372 /* If emit_load_toc_table will use the link register, we need to save
15373 it. We use R12 for this purpose because emit_load_toc_table
15374 can use register 0. This allows us to use a plain 'blr' to return
15375 from the procedure more often. */
15376 int save_LR_around_toc_setup = (TARGET_ELF
15377 && DEFAULT_ABI != ABI_AIX
15379 && ! info->lr_save_p
15380 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
15381 if (save_LR_around_toc_setup)
15383 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15385 insn = emit_move_insn (frame_ptr_rtx, lr);
15386 RTX_FRAME_RELATED_P (insn) = 1;
15388 rs6000_emit_load_toc_table (TRUE);
15390 insn = emit_move_insn (lr, frame_ptr_rtx);
15391 RTX_FRAME_RELATED_P (insn) = 1;
15394 rs6000_emit_load_toc_table (TRUE);
15398 if (DEFAULT_ABI == ABI_DARWIN
15399 && flag_pic && current_function_uses_pic_offset_table)
15401 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15402 rtx src = machopic_function_base_sym ();
15404 /* Save and restore LR locally around this call (in R0). */
15405 if (!info->lr_save_p)
15406 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
15408 emit_insn (gen_load_macho_picbase (src));
15410 emit_move_insn (gen_rtx_REG (Pmode,
15411 RS6000_PIC_OFFSET_TABLE_REGNUM),
15414 if (!info->lr_save_p)
15415 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
15420 /* Write function prologue. */
15423 rs6000_output_function_prologue (FILE *file,
15424 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15426 rs6000_stack_t *info = rs6000_stack_info ();
15428 if (TARGET_DEBUG_STACK)
15429 debug_stack_info (info);
15431 /* Write .extern for any function we will call to save and restore
15433 if (info->first_fp_reg_save < 64
15434 && !FP_SAVE_INLINE (info->first_fp_reg_save))
15435 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15436 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
15437 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
15438 RESTORE_FP_SUFFIX);
15440 /* Write .extern for AIX common mode routines, if needed. */
15441 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
15443 fputs ("\t.extern __mulh\n", file);
15444 fputs ("\t.extern __mull\n", file);
15445 fputs ("\t.extern __divss\n", file);
15446 fputs ("\t.extern __divus\n", file);
15447 fputs ("\t.extern __quoss\n", file);
15448 fputs ("\t.extern __quous\n", file);
15449 common_mode_defined = 1;
15452 if (! HAVE_prologue)
15456 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15457 the "toplevel" insn chain. */
15458 emit_note (NOTE_INSN_DELETED);
15459 rs6000_emit_prologue ();
15460 emit_note (NOTE_INSN_DELETED);
15462 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15466 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15468 INSN_ADDRESSES_NEW (insn, addr);
15473 if (TARGET_DEBUG_STACK)
15474 debug_rtx_list (get_insns (), 100);
15475 final (get_insns (), file, FALSE);
15479 rs6000_pic_labelno++;
15482 /* Emit function epilogue as insns.
15484 At present, dwarf2out_frame_debug_expr doesn't understand
15485 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15486 anywhere in the epilogue. Most of the insns below would in any case
15487 need special notes to explain where r11 is in relation to the stack. */
15490 rs6000_emit_epilogue (int sibcall)
15492 rs6000_stack_t *info;
15493 int restoring_FPRs_inline;
15494 int using_load_multiple;
15495 int using_mtcr_multiple;
15496 int use_backchain_to_restore_sp;
15498 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15499 rtx frame_reg_rtx = sp_reg_rtx;
15500 enum machine_mode reg_mode = Pmode;
15501 int reg_size = TARGET_32BIT ? 4 : 8;
15504 info = rs6000_stack_info ();
15506 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15508 reg_mode = V2SImode;
15512 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15513 && (!TARGET_SPE_ABI
15514 || info->spe_64bit_regs_used == 0)
15515 && info->first_gp_reg_save < 31
15516 && no_global_regs_above (info->first_gp_reg_save));
15517 restoring_FPRs_inline = (sibcall
15518 || current_function_calls_eh_return
15519 || info->first_fp_reg_save == 64
15520 || FP_SAVE_INLINE (info->first_fp_reg_save));
15521 use_backchain_to_restore_sp = (frame_pointer_needed
15522 || current_function_calls_alloca
15523 || info->total_size > 32767);
15524 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15525 || rs6000_cpu == PROCESSOR_PPC603
15526 || rs6000_cpu == PROCESSOR_PPC750
15529 if (WORLD_SAVE_P (info))
15533 const char *alloc_rname;
15536 /* eh_rest_world_r10 will return to the location saved in the LR
15537 stack slot (which is not likely to be our caller.)
15538 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15539 rest_world is similar, except any R10 parameter is ignored.
15540 The exception-handling stuff that was here in 2.95 is no
15541 longer necessary. */
15545 + 32 - info->first_gp_reg_save
15546 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15547 + 63 + 1 - info->first_fp_reg_save);
15549 strcpy (rname, ((current_function_calls_eh_return) ?
15550 "*eh_rest_world_r10" : "*rest_world"));
15551 alloc_rname = ggc_strdup (rname);
15554 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15555 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15556 gen_rtx_REG (Pmode,
15559 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15560 /* The instruction pattern requires a clobber here;
15561 it is shared with the restVEC helper. */
15563 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
15566 /* CR register traditionally saved as CR2. */
15567 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15568 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15569 GEN_INT (info->cr_save_offset));
15570 rtx mem = gen_frame_mem (reg_mode, addr);
15572 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15575 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15577 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15578 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15579 GEN_INT (info->gp_save_offset
15581 rtx mem = gen_frame_mem (reg_mode, addr);
15583 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15585 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15587 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15588 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15589 GEN_INT (info->altivec_save_offset
15591 rtx mem = gen_frame_mem (V4SImode, addr);
15593 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15595 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
15597 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15598 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15599 GEN_INT (info->fp_save_offset
15601 rtx mem = gen_frame_mem (DFmode, addr);
15603 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15606 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15608 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15610 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15612 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15614 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15615 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15620 /* Set sp_offset based on the stack push from the prologue. */
15621 if (info->total_size < 32767)
15622 sp_offset = info->total_size;
15624 /* Restore AltiVec registers if needed. */
15625 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15629 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15630 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15632 rtx addr, areg, mem;
15634 areg = gen_rtx_REG (Pmode, 0);
15636 (areg, GEN_INT (info->altivec_save_offset
15638 + 16 * (i - info->first_altivec_reg_save)));
15640 /* AltiVec addressing mode is [reg+reg]. */
15641 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15642 mem = gen_frame_mem (V4SImode, addr);
15644 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15648 /* Restore VRSAVE if needed. */
15649 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15650 && info->vrsave_mask != 0)
15652 rtx addr, mem, reg;
15654 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15655 GEN_INT (info->vrsave_save_offset + sp_offset));
15656 mem = gen_frame_mem (SImode, addr);
15657 reg = gen_rtx_REG (SImode, 12);
15658 emit_move_insn (reg, mem);
15660 emit_insn (generate_set_vrsave (reg, info, 1));
15665 /* If we have a frame pointer, a call to alloca, or a large stack
15666 frame, restore the old stack pointer using the backchain. Otherwise,
15667 we know what size to update it with. */
15668 if (use_backchain_to_restore_sp)
15670 /* Under V.4, don't reset the stack pointer until after we're done
15671 loading the saved registers. */
15672 if (DEFAULT_ABI == ABI_V4)
15673 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
15675 emit_move_insn (frame_reg_rtx,
15676 gen_rtx_MEM (Pmode, sp_reg_rtx));
15678 else if (info->push_p)
15680 if (DEFAULT_ABI == ABI_V4
15681 || current_function_calls_eh_return)
15682 sp_offset = info->total_size;
15685 emit_insn (TARGET_32BIT
15686 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15687 GEN_INT (info->total_size))
15688 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15689 GEN_INT (info->total_size)));
15693 /* Get the old lr if we saved it. */
15694 if (info->lr_save_p)
15696 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15697 info->lr_save_offset + sp_offset);
15699 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15702 /* Get the old cr if we saved it. */
15703 if (info->cr_save_p)
15705 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15706 GEN_INT (info->cr_save_offset + sp_offset));
15707 rtx mem = gen_frame_mem (SImode, addr);
15709 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15712 /* Set LR here to try to overlap restores below. */
15713 if (info->lr_save_p)
15714 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
15715 gen_rtx_REG (Pmode, 0));
15717 /* Load exception handler data registers, if needed. */
15718 if (current_function_calls_eh_return)
15720 unsigned int i, regno;
15724 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15725 GEN_INT (sp_offset + 5 * reg_size));
15726 rtx mem = gen_frame_mem (reg_mode, addr);
15728 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15735 regno = EH_RETURN_DATA_REGNO (i);
15736 if (regno == INVALID_REGNUM)
15739 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15740 info->ehrd_offset + sp_offset
15741 + reg_size * (int) i);
15743 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15747 /* Restore GPRs. This is done as a PARALLEL if we are using
15748 the load-multiple instructions. */
15749 if (using_load_multiple)
15752 p = rtvec_alloc (32 - info->first_gp_reg_save);
15753 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15755 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15756 GEN_INT (info->gp_save_offset
15759 rtx mem = gen_frame_mem (reg_mode, addr);
15762 gen_rtx_SET (VOIDmode,
15763 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15766 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15768 else if (TARGET_SPE_ABI
15769 && info->spe_64bit_regs_used != 0
15770 && info->first_gp_reg_save != 32)
15772 rtx spe_save_area_ptr;
15773 /* Determine whether we can address all of the registers that need
15774 to be saved with an offset from the stack pointer that fits in
15775 the small const field for SPE memory instructions. */
15776 int spe_regs_addressable_via_sp
15777 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15778 + (32 - info->first_gp_reg_save - 1) * reg_size);
15781 if (spe_regs_addressable_via_sp)
15783 spe_save_area_ptr = frame_reg_rtx;
15784 spe_offset = info->spe_gp_save_offset + sp_offset;
15788 /* Make r11 point to the start of the SPE save area. We worried about
15789 not clobbering it when we were saving registers in the prologue.
15790 There's no need to worry here because the static chain is passed
15791 anew to every function. */
15792 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15794 emit_insn (gen_addsi3 (spe_save_area_ptr, frame_reg_rtx,
15795 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15800 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15801 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15803 rtx offset, addr, mem;
15805 /* We're doing all this to ensure that the immediate offset
15806 fits into the immediate field of 'evldd'. */
15807 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
15809 offset = GEN_INT (spe_offset + reg_size * i);
15810 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15811 mem = gen_rtx_MEM (V2SImode, addr);
15813 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15818 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15819 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15821 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15822 GEN_INT (info->gp_save_offset
15825 rtx mem = gen_frame_mem (reg_mode, addr);
15827 emit_move_insn (gen_rtx_REG (reg_mode,
15828 info->first_gp_reg_save + i), mem);
15831 /* Restore fpr's if we need to do it without calling a function. */
15832 if (restoring_FPRs_inline)
15833 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15834 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15835 && ! call_used_regs[info->first_fp_reg_save+i]))
15838 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15839 GEN_INT (info->fp_save_offset
15842 mem = gen_frame_mem (DFmode, addr);
15844 emit_move_insn (gen_rtx_REG (DFmode,
15845 info->first_fp_reg_save + i),
15849 /* If we saved cr, restore it here. Just those that were used. */
15850 if (info->cr_save_p)
15852 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15855 if (using_mtcr_multiple)
15857 for (i = 0; i < 8; i++)
15858 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15860 gcc_assert (count);
15863 if (using_mtcr_multiple && count > 1)
15868 p = rtvec_alloc (count);
15871 for (i = 0; i < 8; i++)
15872 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15874 rtvec r = rtvec_alloc (2);
15875 RTVEC_ELT (r, 0) = r12_rtx;
15876 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15877 RTVEC_ELT (p, ndx) =
15878 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15879 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15882 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15883 gcc_assert (ndx == count);
15886 for (i = 0; i < 8; i++)
15887 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15889 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15895 /* If this is V.4, unwind the stack pointer after all of the loads
15897 if (frame_reg_rtx != sp_reg_rtx)
15899 /* This blockage is needed so that sched doesn't decide to move
15900 the sp change before the register restores. */
15901 rs6000_emit_stack_tie ();
15903 && info->spe_64bit_regs_used != 0
15904 && info->first_gp_reg_save != 32)
15905 emit_insn (gen_addsi3 (sp_reg_rtx, gen_rtx_REG (Pmode, 11),
15906 GEN_INT (-(info->spe_gp_save_offset + sp_offset))));
15908 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15910 else if (sp_offset != 0)
15911 emit_insn (TARGET_32BIT
15912 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15913 GEN_INT (sp_offset))
15914 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15915 GEN_INT (sp_offset)));
15917 if (current_function_calls_eh_return)
15919 rtx sa = EH_RETURN_STACKADJ_RTX;
15920 emit_insn (TARGET_32BIT
15921 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15922 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15928 if (! restoring_FPRs_inline)
15929 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15931 p = rtvec_alloc (2);
15933 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15934 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15935 gen_rtx_REG (Pmode,
15938 /* If we have to restore more than two FP registers, branch to the
15939 restore function. It will return to our caller. */
15940 if (! restoring_FPRs_inline)
15944 const char *alloc_rname;
15946 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15947 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15948 alloc_rname = ggc_strdup (rname);
15949 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15950 gen_rtx_SYMBOL_REF (Pmode,
15953 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15956 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15957 GEN_INT (info->fp_save_offset + 8*i));
15958 mem = gen_frame_mem (DFmode, addr);
15960 RTVEC_ELT (p, i+3) =
15961 gen_rtx_SET (VOIDmode,
15962 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15967 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15971 /* Write function epilogue. */
15974 rs6000_output_function_epilogue (FILE *file,
15975 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15977 if (! HAVE_epilogue)
15979 rtx insn = get_last_insn ();
15980 /* If the last insn was a BARRIER, we don't have to write anything except
15981 the trace table. */
15982 if (GET_CODE (insn) == NOTE)
15983 insn = prev_nonnote_insn (insn);
15984 if (insn == 0 || GET_CODE (insn) != BARRIER)
15986 /* This is slightly ugly, but at least we don't have two
15987 copies of the epilogue-emitting code. */
15990 /* A NOTE_INSN_DELETED is supposed to be at the start
15991 and end of the "toplevel" insn chain. */
15992 emit_note (NOTE_INSN_DELETED);
15993 rs6000_emit_epilogue (FALSE);
15994 emit_note (NOTE_INSN_DELETED);
15996 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16000 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16002 INSN_ADDRESSES_NEW (insn, addr);
16007 if (TARGET_DEBUG_STACK)
16008 debug_rtx_list (get_insns (), 100);
16009 final (get_insns (), file, FALSE);
16015 macho_branch_islands ();
16016 /* Mach-O doesn't support labels at the end of objects, so if
16017 it looks like we might want one, insert a NOP. */
16019 rtx insn = get_last_insn ();
16022 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
16023 insn = PREV_INSN (insn);
16027 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
16028 fputs ("\tnop\n", file);
16032 /* Output a traceback table here. See /usr/include/sys/debug.h for info
16035 We don't output a traceback table if -finhibit-size-directive was
16036 used. The documentation for -finhibit-size-directive reads
16037 ``don't output a @code{.size} assembler directive, or anything
16038 else that would cause trouble if the function is split in the
16039 middle, and the two halves are placed at locations far apart in
16040 memory.'' The traceback table has this property, since it
16041 includes the offset from the start of the function to the
16042 traceback table itself.
16044 System V.4 Powerpc's (and the embedded ABI derived from it) use a
16045 different traceback table. */
16046 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
16047 && rs6000_traceback != traceback_none && !current_function_is_thunk)
16049 const char *fname = NULL;
16050 const char *language_string = lang_hooks.name;
16051 int fixed_parms = 0, float_parms = 0, parm_info = 0;
16053 int optional_tbtab;
16054 rs6000_stack_t *info = rs6000_stack_info ();
16056 if (rs6000_traceback == traceback_full)
16057 optional_tbtab = 1;
16058 else if (rs6000_traceback == traceback_part)
16059 optional_tbtab = 0;
16061 optional_tbtab = !optimize_size && !TARGET_ELF;
16063 if (optional_tbtab)
16065 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
16066 while (*fname == '.') /* V.4 encodes . in the name */
16069 /* Need label immediately before tbtab, so we can compute
16070 its offset from the function start. */
16071 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16072 ASM_OUTPUT_LABEL (file, fname);
16075 /* The .tbtab pseudo-op can only be used for the first eight
16076 expressions, since it can't handle the possibly variable
16077 length fields that follow. However, if you omit the optional
16078 fields, the assembler outputs zeros for all optional fields
16079 anyways, giving each variable length field is minimum length
16080 (as defined in sys/debug.h). Thus we can not use the .tbtab
16081 pseudo-op at all. */
16083 /* An all-zero word flags the start of the tbtab, for debuggers
16084 that have to find it by searching forward from the entry
16085 point or from the current pc. */
16086 fputs ("\t.long 0\n", file);
16088 /* Tbtab format type. Use format type 0. */
16089 fputs ("\t.byte 0,", file);
16091 /* Language type. Unfortunately, there does not seem to be any
16092 official way to discover the language being compiled, so we
16093 use language_string.
16094 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
16095 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
16096 a number, so for now use 9. */
16097 if (! strcmp (language_string, "GNU C"))
16099 else if (! strcmp (language_string, "GNU F77")
16100 || ! strcmp (language_string, "GNU F95"))
16102 else if (! strcmp (language_string, "GNU Pascal"))
16104 else if (! strcmp (language_string, "GNU Ada"))
16106 else if (! strcmp (language_string, "GNU C++")
16107 || ! strcmp (language_string, "GNU Objective-C++"))
16109 else if (! strcmp (language_string, "GNU Java"))
16111 else if (! strcmp (language_string, "GNU Objective-C"))
16114 gcc_unreachable ();
16115 fprintf (file, "%d,", i);
16117 /* 8 single bit fields: global linkage (not set for C extern linkage,
16118 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
16119 from start of procedure stored in tbtab, internal function, function
16120 has controlled storage, function has no toc, function uses fp,
16121 function logs/aborts fp operations. */
16122 /* Assume that fp operations are used if any fp reg must be saved. */
16123 fprintf (file, "%d,",
16124 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
16126 /* 6 bitfields: function is interrupt handler, name present in
16127 proc table, function calls alloca, on condition directives
16128 (controls stack walks, 3 bits), saves condition reg, saves
16130 /* The `function calls alloca' bit seems to be set whenever reg 31 is
16131 set up as a frame pointer, even when there is no alloca call. */
16132 fprintf (file, "%d,",
16133 ((optional_tbtab << 6)
16134 | ((optional_tbtab & frame_pointer_needed) << 5)
16135 | (info->cr_save_p << 1)
16136 | (info->lr_save_p)));
16138 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
16140 fprintf (file, "%d,",
16141 (info->push_p << 7) | (64 - info->first_fp_reg_save));
16143 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
16144 fprintf (file, "%d,", (32 - first_reg_to_save ()));
16146 if (optional_tbtab)
16148 /* Compute the parameter info from the function decl argument
16151 int next_parm_info_bit = 31;
16153 for (decl = DECL_ARGUMENTS (current_function_decl);
16154 decl; decl = TREE_CHAIN (decl))
16156 rtx parameter = DECL_INCOMING_RTL (decl);
16157 enum machine_mode mode = GET_MODE (parameter);
16159 if (GET_CODE (parameter) == REG)
16161 if (SCALAR_FLOAT_MODE_P (mode))
16181 gcc_unreachable ();
16184 /* If only one bit will fit, don't or in this entry. */
16185 if (next_parm_info_bit > 0)
16186 parm_info |= (bits << (next_parm_info_bit - 1));
16187 next_parm_info_bit -= 2;
16191 fixed_parms += ((GET_MODE_SIZE (mode)
16192 + (UNITS_PER_WORD - 1))
16194 next_parm_info_bit -= 1;
16200 /* Number of fixed point parameters. */
16201 /* This is actually the number of words of fixed point parameters; thus
16202 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16203 fprintf (file, "%d,", fixed_parms);
16205 /* 2 bitfields: number of floating point parameters (7 bits), parameters
16207 /* This is actually the number of fp registers that hold parameters;
16208 and thus the maximum value is 13. */
16209 /* Set parameters on stack bit if parameters are not in their original
16210 registers, regardless of whether they are on the stack? Xlc
16211 seems to set the bit when not optimizing. */
16212 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
16214 if (! optional_tbtab)
16217 /* Optional fields follow. Some are variable length. */
16219 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
16220 11 double float. */
16221 /* There is an entry for each parameter in a register, in the order that
16222 they occur in the parameter list. Any intervening arguments on the
16223 stack are ignored. If the list overflows a long (max possible length
16224 34 bits) then completely leave off all elements that don't fit. */
16225 /* Only emit this long if there was at least one parameter. */
16226 if (fixed_parms || float_parms)
16227 fprintf (file, "\t.long %d\n", parm_info);
16229 /* Offset from start of code to tb table. */
16230 fputs ("\t.long ", file);
16231 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16233 RS6000_OUTPUT_BASENAME (file, fname);
16235 assemble_name (file, fname);
16237 rs6000_output_function_entry (file, fname);
16240 /* Interrupt handler mask. */
16241 /* Omit this long, since we never set the interrupt handler bit
16244 /* Number of CTL (controlled storage) anchors. */
16245 /* Omit this long, since the has_ctl bit is never set above. */
16247 /* Displacement into stack of each CTL anchor. */
16248 /* Omit this list of longs, because there are no CTL anchors. */
16250 /* Length of function name. */
16253 fprintf (file, "\t.short %d\n", (int) strlen (fname));
16255 /* Function name. */
16256 assemble_string (fname, strlen (fname));
16258 /* Register for alloca automatic storage; this is always reg 31.
16259 Only emit this if the alloca bit was set above. */
16260 if (frame_pointer_needed)
16261 fputs ("\t.byte 31\n", file);
16263 fputs ("\t.align 2\n", file);
16267 /* A C compound statement that outputs the assembler code for a thunk
16268 function, used to implement C++ virtual function calls with
16269 multiple inheritance. The thunk acts as a wrapper around a virtual
16270 function, adjusting the implicit object parameter before handing
16271 control off to the real function.
16273 First, emit code to add the integer DELTA to the location that
16274 contains the incoming first argument. Assume that this argument
16275 contains a pointer, and is the one used to pass the `this' pointer
16276 in C++. This is the incoming argument *before* the function
16277 prologue, e.g. `%o0' on a sparc. The addition must preserve the
16278 values of all other incoming arguments.
16280 After the addition, emit code to jump to FUNCTION, which is a
16281 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
16282 not touch the return address. Hence returning from FUNCTION will
16283 return to whoever called the current `thunk'.
16285 The effect must be as if FUNCTION had been called directly with the
16286 adjusted first argument. This macro is responsible for emitting
16287 all of the code for a thunk function; output_function_prologue()
16288 and output_function_epilogue() are not invoked.
16290 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
16291 been extracted from it.) It might possibly be useful on some
16292 targets, but probably not.
16294 If you do not define this macro, the target-independent code in the
16295 C++ frontend will generate a less efficient heavyweight thunk that
16296 calls FUNCTION instead of jumping to it. The generic approach does
16297 not support varargs. */
16300 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16301 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16304 rtx this, insn, funexp;
16306 reload_completed = 1;
16307 epilogue_completed = 1;
16309 /* Mark the end of the (empty) prologue. */
16310 emit_note (NOTE_INSN_PROLOGUE_END);
16312 /* Find the "this" pointer. If the function returns a structure,
16313 the structure return pointer is in r3. */
16314 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16315 this = gen_rtx_REG (Pmode, 4);
16317 this = gen_rtx_REG (Pmode, 3);
16319 /* Apply the constant offset, if required. */
16322 rtx delta_rtx = GEN_INT (delta);
16323 emit_insn (TARGET_32BIT
16324 ? gen_addsi3 (this, this, delta_rtx)
16325 : gen_adddi3 (this, this, delta_rtx));
16328 /* Apply the offset from the vtable, if required. */
16331 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
16332 rtx tmp = gen_rtx_REG (Pmode, 12);
16334 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
16335 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
16337 emit_insn (TARGET_32BIT
16338 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
16339 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
16340 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
16344 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
16346 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
16348 emit_insn (TARGET_32BIT
16349 ? gen_addsi3 (this, this, tmp)
16350 : gen_adddi3 (this, this, tmp));
16353 /* Generate a tail call to the target function. */
16354 if (!TREE_USED (function))
16356 assemble_external (function);
16357 TREE_USED (function) = 1;
16359 funexp = XEXP (DECL_RTL (function), 0);
16360 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
16363 if (MACHOPIC_INDIRECT)
16364 funexp = machopic_indirect_call_target (funexp);
16367 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16368 generate sibcall RTL explicitly. */
16369 insn = emit_call_insn (
16370 gen_rtx_PARALLEL (VOIDmode,
16372 gen_rtx_CALL (VOIDmode,
16373 funexp, const0_rtx),
16374 gen_rtx_USE (VOIDmode, const0_rtx),
16375 gen_rtx_USE (VOIDmode,
16376 gen_rtx_REG (SImode,
16378 gen_rtx_RETURN (VOIDmode))));
16379 SIBLING_CALL_P (insn) = 1;
16382 /* Run just enough of rest_of_compilation to get the insns emitted.
16383 There's not really enough bulk here to make other passes such as
16384 instruction scheduling worth while. Note that use_thunk calls
16385 assemble_start_function and assemble_end_function. */
16386 insn = get_insns ();
16387 insn_locators_alloc ();
16388 shorten_branches (insn);
16389 final_start_function (insn, file, 1);
16390 final (insn, file, 1);
16391 final_end_function ();
16393 reload_completed = 0;
16394 epilogue_completed = 0;
16397 /* A quick summary of the various types of 'constant-pool tables'
16400 Target Flags Name One table per
16401 AIX (none) AIX TOC object file
16402 AIX -mfull-toc AIX TOC object file
16403 AIX -mminimal-toc AIX minimal TOC translation unit
16404 SVR4/EABI (none) SVR4 SDATA object file
16405 SVR4/EABI -fpic SVR4 pic object file
16406 SVR4/EABI -fPIC SVR4 PIC translation unit
16407 SVR4/EABI -mrelocatable EABI TOC function
16408 SVR4/EABI -maix AIX TOC object file
16409 SVR4/EABI -maix -mminimal-toc
16410 AIX minimal TOC translation unit
16412 Name Reg. Set by entries contains:
16413 made by addrs? fp? sum?
16415 AIX TOC 2 crt0 as Y option option
16416 AIX minimal TOC 30 prolog gcc Y Y option
16417 SVR4 SDATA 13 crt0 gcc N Y N
16418 SVR4 pic 30 prolog ld Y not yet N
16419 SVR4 PIC 30 prolog gcc Y option option
16420 EABI TOC 30 prolog gcc Y option option
16424 /* Hash functions for the hash table. */
16427 rs6000_hash_constant (rtx k)
16429 enum rtx_code code = GET_CODE (k);
16430 enum machine_mode mode = GET_MODE (k);
16431 unsigned result = (code << 3) ^ mode;
16432 const char *format;
16435 format = GET_RTX_FORMAT (code);
16436 flen = strlen (format);
16442 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
16445 if (mode != VOIDmode)
16446 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
16458 for (; fidx < flen; fidx++)
16459 switch (format[fidx])
16464 const char *str = XSTR (k, fidx);
16465 len = strlen (str);
16466 result = result * 613 + len;
16467 for (i = 0; i < len; i++)
16468 result = result * 613 + (unsigned) str[i];
16473 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
16477 result = result * 613 + (unsigned) XINT (k, fidx);
16480 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
16481 result = result * 613 + (unsigned) XWINT (k, fidx);
16485 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
16486 result = result * 613 + (unsigned) (XWINT (k, fidx)
16493 gcc_unreachable ();
16500 toc_hash_function (const void *hash_entry)
16502 const struct toc_hash_struct *thc =
16503 (const struct toc_hash_struct *) hash_entry;
16504 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
16507 /* Compare H1 and H2 for equivalence. */
16510 toc_hash_eq (const void *h1, const void *h2)
16512 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16513 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16515 if (((const struct toc_hash_struct *) h1)->key_mode
16516 != ((const struct toc_hash_struct *) h2)->key_mode)
16519 return rtx_equal_p (r1, r2);
16522 /* These are the names given by the C++ front-end to vtables, and
16523 vtable-like objects. Ideally, this logic should not be here;
16524 instead, there should be some programmatic way of inquiring as
16525 to whether or not an object is a vtable. */
16527 #define VTABLE_NAME_P(NAME) \
16528 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16529 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16530 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16531 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16532 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16535 rs6000_output_symbol_ref (FILE *file, rtx x)
16537 /* Currently C++ toc references to vtables can be emitted before it
16538 is decided whether the vtable is public or private. If this is
16539 the case, then the linker will eventually complain that there is
16540 a reference to an unknown section. Thus, for vtables only,
16541 we emit the TOC reference to reference the symbol and not the
16543 const char *name = XSTR (x, 0);
16545 if (VTABLE_NAME_P (name))
16547 RS6000_OUTPUT_BASENAME (file, name);
16550 assemble_name (file, name);
16553 /* Output a TOC entry. We derive the entry name from what is being
16557 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16560 const char *name = buf;
16561 const char *real_name;
16563 HOST_WIDE_INT offset = 0;
16565 gcc_assert (!TARGET_NO_TOC);
16567 /* When the linker won't eliminate them, don't output duplicate
16568 TOC entries (this happens on AIX if there is any kind of TOC,
16569 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16571 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
16573 struct toc_hash_struct *h;
16576 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16577 time because GGC is not initialized at that point. */
16578 if (toc_hash_table == NULL)
16579 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
16580 toc_hash_eq, NULL);
16582 h = ggc_alloc (sizeof (*h));
16584 h->key_mode = mode;
16585 h->labelno = labelno;
16587 found = htab_find_slot (toc_hash_table, h, 1);
16588 if (*found == NULL)
16590 else /* This is indeed a duplicate.
16591 Set this label equal to that label. */
16593 fputs ("\t.set ", file);
16594 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16595 fprintf (file, "%d,", labelno);
16596 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16597 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
16603 /* If we're going to put a double constant in the TOC, make sure it's
16604 aligned properly when strict alignment is on. */
16605 if (GET_CODE (x) == CONST_DOUBLE
16606 && STRICT_ALIGNMENT
16607 && GET_MODE_BITSIZE (mode) >= 64
16608 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
16609 ASM_OUTPUT_ALIGN (file, 3);
16612 (*targetm.asm_out.internal_label) (file, "LC", labelno);
16614 /* Handle FP constants specially. Note that if we have a minimal
16615 TOC, things we put here aren't actually in the TOC, so we can allow
16617 if (GET_CODE (x) == CONST_DOUBLE &&
16618 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
16620 REAL_VALUE_TYPE rv;
16623 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16624 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16625 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
16627 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
16631 if (TARGET_MINIMAL_TOC)
16632 fputs (DOUBLE_INT_ASM_OP, file);
16634 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16635 k[0] & 0xffffffff, k[1] & 0xffffffff,
16636 k[2] & 0xffffffff, k[3] & 0xffffffff);
16637 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
16638 k[0] & 0xffffffff, k[1] & 0xffffffff,
16639 k[2] & 0xffffffff, k[3] & 0xffffffff);
16644 if (TARGET_MINIMAL_TOC)
16645 fputs ("\t.long ", file);
16647 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16648 k[0] & 0xffffffff, k[1] & 0xffffffff,
16649 k[2] & 0xffffffff, k[3] & 0xffffffff);
16650 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16651 k[0] & 0xffffffff, k[1] & 0xffffffff,
16652 k[2] & 0xffffffff, k[3] & 0xffffffff);
16656 else if (GET_CODE (x) == CONST_DOUBLE &&
16657 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16659 REAL_VALUE_TYPE rv;
16662 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16664 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16665 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
16667 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
16671 if (TARGET_MINIMAL_TOC)
16672 fputs (DOUBLE_INT_ASM_OP, file);
16674 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16675 k[0] & 0xffffffff, k[1] & 0xffffffff);
16676 fprintf (file, "0x%lx%08lx\n",
16677 k[0] & 0xffffffff, k[1] & 0xffffffff);
16682 if (TARGET_MINIMAL_TOC)
16683 fputs ("\t.long ", file);
16685 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16686 k[0] & 0xffffffff, k[1] & 0xffffffff);
16687 fprintf (file, "0x%lx,0x%lx\n",
16688 k[0] & 0xffffffff, k[1] & 0xffffffff);
16692 else if (GET_CODE (x) == CONST_DOUBLE &&
16693 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
16695 REAL_VALUE_TYPE rv;
16698 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16699 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16700 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
16702 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
16706 if (TARGET_MINIMAL_TOC)
16707 fputs (DOUBLE_INT_ASM_OP, file);
16709 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16710 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
16715 if (TARGET_MINIMAL_TOC)
16716 fputs ("\t.long ", file);
16718 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16719 fprintf (file, "0x%lx\n", l & 0xffffffff);
16723 else if (GET_MODE (x) == VOIDmode
16724 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16726 unsigned HOST_WIDE_INT low;
16727 HOST_WIDE_INT high;
16729 if (GET_CODE (x) == CONST_DOUBLE)
16731 low = CONST_DOUBLE_LOW (x);
16732 high = CONST_DOUBLE_HIGH (x);
16735 #if HOST_BITS_PER_WIDE_INT == 32
16738 high = (low & 0x80000000) ? ~0 : 0;
16742 low = INTVAL (x) & 0xffffffff;
16743 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16747 /* TOC entries are always Pmode-sized, but since this
16748 is a bigendian machine then if we're putting smaller
16749 integer constants in the TOC we have to pad them.
16750 (This is still a win over putting the constants in
16751 a separate constant pool, because then we'd have
16752 to have both a TOC entry _and_ the actual constant.)
16754 For a 32-bit target, CONST_INT values are loaded and shifted
16755 entirely within `low' and can be stored in one TOC entry. */
16757 /* It would be easy to make this work, but it doesn't now. */
16758 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16760 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16762 #if HOST_BITS_PER_WIDE_INT == 32
16763 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16764 POINTER_SIZE, &low, &high, 0);
16767 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16768 high = (HOST_WIDE_INT) low >> 32;
16775 if (TARGET_MINIMAL_TOC)
16776 fputs (DOUBLE_INT_ASM_OP, file);
16778 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16779 (long) high & 0xffffffff, (long) low & 0xffffffff);
16780 fprintf (file, "0x%lx%08lx\n",
16781 (long) high & 0xffffffff, (long) low & 0xffffffff);
16786 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16788 if (TARGET_MINIMAL_TOC)
16789 fputs ("\t.long ", file);
16791 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16792 (long) high & 0xffffffff, (long) low & 0xffffffff);
16793 fprintf (file, "0x%lx,0x%lx\n",
16794 (long) high & 0xffffffff, (long) low & 0xffffffff);
16798 if (TARGET_MINIMAL_TOC)
16799 fputs ("\t.long ", file);
16801 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16802 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16808 if (GET_CODE (x) == CONST)
16810 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16812 base = XEXP (XEXP (x, 0), 0);
16813 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16816 switch (GET_CODE (base))
16819 name = XSTR (base, 0);
16823 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16824 CODE_LABEL_NUMBER (XEXP (base, 0)));
16828 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16832 gcc_unreachable ();
16835 real_name = (*targetm.strip_name_encoding) (name);
16836 if (TARGET_MINIMAL_TOC)
16837 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16840 fprintf (file, "\t.tc %s", real_name);
16843 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16845 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16847 fputs ("[TC],", file);
16850 /* Currently C++ toc references to vtables can be emitted before it
16851 is decided whether the vtable is public or private. If this is
16852 the case, then the linker will eventually complain that there is
16853 a TOC reference to an unknown section. Thus, for vtables only,
16854 we emit the TOC reference to reference the symbol and not the
16856 if (VTABLE_NAME_P (name))
16858 RS6000_OUTPUT_BASENAME (file, name);
16860 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16861 else if (offset > 0)
16862 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16865 output_addr_const (file, x);
16869 /* Output an assembler pseudo-op to write an ASCII string of N characters
16870 starting at P to FILE.
16872 On the RS/6000, we have to do this using the .byte operation and
16873 write out special characters outside the quoted string.
16874 Also, the assembler is broken; very long strings are truncated,
16875 so we must artificially break them up early. */
16878 output_ascii (FILE *file, const char *p, int n)
16881 int i, count_string;
16882 const char *for_string = "\t.byte \"";
16883 const char *for_decimal = "\t.byte ";
16884 const char *to_close = NULL;
16887 for (i = 0; i < n; i++)
16890 if (c >= ' ' && c < 0177)
16893 fputs (for_string, file);
16896 /* Write two quotes to get one. */
16904 for_decimal = "\"\n\t.byte ";
16908 if (count_string >= 512)
16910 fputs (to_close, file);
16912 for_string = "\t.byte \"";
16913 for_decimal = "\t.byte ";
16921 fputs (for_decimal, file);
16922 fprintf (file, "%d", c);
16924 for_string = "\n\t.byte \"";
16925 for_decimal = ", ";
16931 /* Now close the string if we have written one. Then end the line. */
16933 fputs (to_close, file);
16936 /* Generate a unique section name for FILENAME for a section type
16937 represented by SECTION_DESC. Output goes into BUF.
16939 SECTION_DESC can be any string, as long as it is different for each
16940 possible section type.
16942 We name the section in the same manner as xlc. The name begins with an
16943 underscore followed by the filename (after stripping any leading directory
16944 names) with the last period replaced by the string SECTION_DESC. If
16945 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16949 rs6000_gen_section_name (char **buf, const char *filename,
16950 const char *section_desc)
16952 const char *q, *after_last_slash, *last_period = 0;
16956 after_last_slash = filename;
16957 for (q = filename; *q; q++)
16960 after_last_slash = q + 1;
16961 else if (*q == '.')
16965 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16966 *buf = (char *) xmalloc (len);
16971 for (q = after_last_slash; *q; q++)
16973 if (q == last_period)
16975 strcpy (p, section_desc);
16976 p += strlen (section_desc);
16980 else if (ISALNUM (*q))
16984 if (last_period == 0)
16985 strcpy (p, section_desc);
16990 /* Emit profile function. */
16993 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16995 /* Non-standard profiling for kernels, which just saves LR then calls
16996 _mcount without worrying about arg saves. The idea is to change
16997 the function prologue as little as possible as it isn't easy to
16998 account for arg save/restore code added just for _mcount. */
16999 if (TARGET_PROFILE_KERNEL)
17002 if (DEFAULT_ABI == ABI_AIX)
17004 #ifndef NO_PROFILE_COUNTERS
17005 # define NO_PROFILE_COUNTERS 0
17007 if (NO_PROFILE_COUNTERS)
17008 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
17012 const char *label_name;
17015 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
17016 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
17017 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
17019 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
17023 else if (DEFAULT_ABI == ABI_DARWIN)
17025 const char *mcount_name = RS6000_MCOUNT;
17026 int caller_addr_regno = LR_REGNO;
17028 /* Be conservative and always set this, at least for now. */
17029 current_function_uses_pic_offset_table = 1;
17032 /* For PIC code, set up a stub and collect the caller's address
17033 from r0, which is where the prologue puts it. */
17034 if (MACHOPIC_INDIRECT
17035 && current_function_uses_pic_offset_table)
17036 caller_addr_regno = 0;
17038 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
17040 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
17044 /* Write function profiler code. */
17047 output_function_profiler (FILE *file, int labelno)
17051 switch (DEFAULT_ABI)
17054 gcc_unreachable ();
17059 warning (0, "no profiling of 64-bit code for this ABI");
17062 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
17063 fprintf (file, "\tmflr %s\n", reg_names[0]);
17064 if (NO_PROFILE_COUNTERS)
17066 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17067 reg_names[0], reg_names[1]);
17069 else if (TARGET_SECURE_PLT && flag_pic)
17071 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
17072 reg_names[0], reg_names[1]);
17073 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17074 asm_fprintf (file, "\t{cau|addis} %s,%s,",
17075 reg_names[12], reg_names[12]);
17076 assemble_name (file, buf);
17077 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
17078 assemble_name (file, buf);
17079 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
17081 else if (flag_pic == 1)
17083 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
17084 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17085 reg_names[0], reg_names[1]);
17086 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17087 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
17088 assemble_name (file, buf);
17089 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
17091 else if (flag_pic > 1)
17093 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17094 reg_names[0], reg_names[1]);
17095 /* Now, we need to get the address of the label. */
17096 fputs ("\tbcl 20,31,1f\n\t.long ", file);
17097 assemble_name (file, buf);
17098 fputs ("-.\n1:", file);
17099 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
17100 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
17101 reg_names[0], reg_names[11]);
17102 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
17103 reg_names[0], reg_names[0], reg_names[11]);
17107 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
17108 assemble_name (file, buf);
17109 fputs ("@ha\n", file);
17110 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17111 reg_names[0], reg_names[1]);
17112 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
17113 assemble_name (file, buf);
17114 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
17117 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
17118 fprintf (file, "\tbl %s%s\n",
17119 RS6000_MCOUNT, flag_pic ? "@plt" : "");
17124 if (!TARGET_PROFILE_KERNEL)
17126 /* Don't do anything, done in output_profile_hook (). */
17130 gcc_assert (!TARGET_32BIT);
17132 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
17133 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
17135 if (cfun->static_chain_decl != NULL)
17137 asm_fprintf (file, "\tstd %s,24(%s)\n",
17138 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17139 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17140 asm_fprintf (file, "\tld %s,24(%s)\n",
17141 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17144 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17152 /* The following variable value is the last issued insn. */
17154 static rtx last_scheduled_insn;
17156 /* The following variable helps to balance issuing of load and
17157 store instructions */
17159 static int load_store_pendulum;
17161 /* Power4 load update and store update instructions are cracked into a
17162 load or store and an integer insn which are executed in the same cycle.
17163 Branches have their own dispatch slot which does not count against the
17164 GCC issue rate, but it changes the program flow so there are no other
17165 instructions to issue in this cycle. */
17168 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
17169 int verbose ATTRIBUTE_UNUSED,
17170 rtx insn, int more)
17172 last_scheduled_insn = insn;
17173 if (GET_CODE (PATTERN (insn)) == USE
17174 || GET_CODE (PATTERN (insn)) == CLOBBER)
17176 cached_can_issue_more = more;
17177 return cached_can_issue_more;
17180 if (insn_terminates_group_p (insn, current_group))
17182 cached_can_issue_more = 0;
17183 return cached_can_issue_more;
17186 /* If no reservation, but reach here */
17187 if (recog_memoized (insn) < 0)
17190 if (rs6000_sched_groups)
17192 if (is_microcoded_insn (insn))
17193 cached_can_issue_more = 0;
17194 else if (is_cracked_insn (insn))
17195 cached_can_issue_more = more > 2 ? more - 2 : 0;
17197 cached_can_issue_more = more - 1;
17199 return cached_can_issue_more;
17202 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
17205 cached_can_issue_more = more - 1;
17206 return cached_can_issue_more;
17209 /* Adjust the cost of a scheduling dependency. Return the new cost of
17210 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
17213 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
17215 enum attr_type attr_type;
17217 if (! recog_memoized (insn))
17220 switch (REG_NOTE_KIND (link))
17224 /* Data dependency; DEP_INSN writes a register that INSN reads
17225 some cycles later. */
17227 /* Separate a load from a narrower, dependent store. */
17228 if (rs6000_sched_groups
17229 && GET_CODE (PATTERN (insn)) == SET
17230 && GET_CODE (PATTERN (dep_insn)) == SET
17231 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
17232 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
17233 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
17234 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
17237 attr_type = get_attr_type (insn);
17242 /* Tell the first scheduling pass about the latency between
17243 a mtctr and bctr (and mtlr and br/blr). The first
17244 scheduling pass will not know about this latency since
17245 the mtctr instruction, which has the latency associated
17246 to it, will be generated by reload. */
17247 return TARGET_POWER ? 5 : 4;
17249 /* Leave some extra cycles between a compare and its
17250 dependent branch, to inhibit expensive mispredicts. */
17251 if ((rs6000_cpu_attr == CPU_PPC603
17252 || rs6000_cpu_attr == CPU_PPC604
17253 || rs6000_cpu_attr == CPU_PPC604E
17254 || rs6000_cpu_attr == CPU_PPC620
17255 || rs6000_cpu_attr == CPU_PPC630
17256 || rs6000_cpu_attr == CPU_PPC750
17257 || rs6000_cpu_attr == CPU_PPC7400
17258 || rs6000_cpu_attr == CPU_PPC7450
17259 || rs6000_cpu_attr == CPU_POWER4
17260 || rs6000_cpu_attr == CPU_POWER5
17261 || rs6000_cpu_attr == CPU_CELL)
17262 && recog_memoized (dep_insn)
17263 && (INSN_CODE (dep_insn) >= 0))
17265 switch (get_attr_type (dep_insn))
17269 case TYPE_DELAYED_COMPARE:
17270 case TYPE_IMUL_COMPARE:
17271 case TYPE_LMUL_COMPARE:
17272 case TYPE_FPCOMPARE:
17273 case TYPE_CR_LOGICAL:
17274 case TYPE_DELAYED_CR:
17283 case TYPE_STORE_UX:
17285 case TYPE_FPSTORE_U:
17286 case TYPE_FPSTORE_UX:
17287 if ((rs6000_cpu == PROCESSOR_POWER6)
17288 && recog_memoized (dep_insn)
17289 && (INSN_CODE (dep_insn) >= 0))
17292 if (GET_CODE (PATTERN (insn)) != SET)
17293 /* If this happens, we have to extend this to schedule
17294 optimally. Return default for now. */
17297 /* Adjust the cost for the case where the value written
17298 by a fixed point operation is used as the address
17299 gen value on a store. */
17300 switch (get_attr_type (dep_insn))
17307 if (! store_data_bypass_p (dep_insn, insn))
17311 case TYPE_LOAD_EXT:
17312 case TYPE_LOAD_EXT_U:
17313 case TYPE_LOAD_EXT_UX:
17314 case TYPE_VAR_SHIFT_ROTATE:
17315 case TYPE_VAR_DELAYED_COMPARE:
17317 if (! store_data_bypass_p (dep_insn, insn))
17323 case TYPE_FAST_COMPARE:
17326 case TYPE_INSERT_WORD:
17327 case TYPE_INSERT_DWORD:
17328 case TYPE_FPLOAD_U:
17329 case TYPE_FPLOAD_UX:
17331 case TYPE_STORE_UX:
17332 case TYPE_FPSTORE_U:
17333 case TYPE_FPSTORE_UX:
17335 if (! store_data_bypass_p (dep_insn, insn))
17343 case TYPE_IMUL_COMPARE:
17344 case TYPE_LMUL_COMPARE:
17346 if (! store_data_bypass_p (dep_insn, insn))
17352 if (! store_data_bypass_p (dep_insn, insn))
17358 if (! store_data_bypass_p (dep_insn, insn))
17371 case TYPE_LOAD_EXT:
17372 case TYPE_LOAD_EXT_U:
17373 case TYPE_LOAD_EXT_UX:
17374 if ((rs6000_cpu == PROCESSOR_POWER6)
17375 && recog_memoized (dep_insn)
17376 && (INSN_CODE (dep_insn) >= 0))
17379 /* Adjust the cost for the case where the value written
17380 by a fixed point instruction is used within the address
17381 gen portion of a subsequent load(u)(x) */
17382 switch (get_attr_type (dep_insn))
17389 if (set_to_load_agen (dep_insn, insn))
17393 case TYPE_LOAD_EXT:
17394 case TYPE_LOAD_EXT_U:
17395 case TYPE_LOAD_EXT_UX:
17396 case TYPE_VAR_SHIFT_ROTATE:
17397 case TYPE_VAR_DELAYED_COMPARE:
17399 if (set_to_load_agen (dep_insn, insn))
17405 case TYPE_FAST_COMPARE:
17408 case TYPE_INSERT_WORD:
17409 case TYPE_INSERT_DWORD:
17410 case TYPE_FPLOAD_U:
17411 case TYPE_FPLOAD_UX:
17413 case TYPE_STORE_UX:
17414 case TYPE_FPSTORE_U:
17415 case TYPE_FPSTORE_UX:
17417 if (set_to_load_agen (dep_insn, insn))
17425 case TYPE_IMUL_COMPARE:
17426 case TYPE_LMUL_COMPARE:
17428 if (set_to_load_agen (dep_insn, insn))
17434 if (set_to_load_agen (dep_insn, insn))
17440 if (set_to_load_agen (dep_insn, insn))
17451 if ((rs6000_cpu == PROCESSOR_POWER6)
17452 && recog_memoized (dep_insn)
17453 && (INSN_CODE (dep_insn) >= 0)
17454 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
17461 /* Fall out to return default cost. */
17465 case REG_DEP_OUTPUT:
17466 /* Output dependency; DEP_INSN writes a register that INSN writes some
17468 if ((rs6000_cpu == PROCESSOR_POWER6)
17469 && recog_memoized (dep_insn)
17470 && (INSN_CODE (dep_insn) >= 0))
17472 attr_type = get_attr_type (insn);
17477 if (get_attr_type (dep_insn) == TYPE_FP)
17481 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
17489 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17494 gcc_unreachable ();
17500 /* The function returns a true if INSN is microcoded.
17501 Return false otherwise. */
17504 is_microcoded_insn (rtx insn)
17506 if (!insn || !INSN_P (insn)
17507 || GET_CODE (PATTERN (insn)) == USE
17508 || GET_CODE (PATTERN (insn)) == CLOBBER)
17511 if (rs6000_cpu_attr == CPU_CELL)
17512 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17514 if (rs6000_sched_groups)
17516 enum attr_type type = get_attr_type (insn);
17517 if (type == TYPE_LOAD_EXT_U
17518 || type == TYPE_LOAD_EXT_UX
17519 || type == TYPE_LOAD_UX
17520 || type == TYPE_STORE_UX
17521 || type == TYPE_MFCR)
17528 /* The function returns true if INSN is cracked into 2 instructions
17529 by the processor (and therefore occupies 2 issue slots). */
17532 is_cracked_insn (rtx insn)
17534 if (!insn || !INSN_P (insn)
17535 || GET_CODE (PATTERN (insn)) == USE
17536 || GET_CODE (PATTERN (insn)) == CLOBBER)
17539 if (rs6000_sched_groups)
17541 enum attr_type type = get_attr_type (insn);
17542 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17543 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17544 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17545 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17546 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17547 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17548 || type == TYPE_IDIV || type == TYPE_LDIV
17549 || type == TYPE_INSERT_WORD)
17556 /* The function returns true if INSN can be issued only from
17557 the branch slot. */
17560 is_branch_slot_insn (rtx insn)
17562 if (!insn || !INSN_P (insn)
17563 || GET_CODE (PATTERN (insn)) == USE
17564 || GET_CODE (PATTERN (insn)) == CLOBBER)
17567 if (rs6000_sched_groups)
17569 enum attr_type type = get_attr_type (insn);
17570 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
17578 /* The function returns true if out_inst sets a value that is
17579 used in the address generation computation of in_insn */
17581 set_to_load_agen (rtx out_insn, rtx in_insn)
17583 rtx out_set, in_set;
17585 /* For performance reasons, only handle the simple case where
17586 both loads are a single_set. */
17587 out_set = single_set (out_insn);
17590 in_set = single_set (in_insn);
17592 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
17598 /* The function returns true if the target storage location of
17599 out_insn is adjacent to the target storage location of in_insn */
17600 /* Return 1 if memory locations are adjacent. */
17603 adjacent_mem_locations (rtx insn1, rtx insn2)
17606 rtx a = get_store_dest (PATTERN (insn1));
17607 rtx b = get_store_dest (PATTERN (insn2));
17609 if ((GET_CODE (XEXP (a, 0)) == REG
17610 || (GET_CODE (XEXP (a, 0)) == PLUS
17611 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
17612 && (GET_CODE (XEXP (b, 0)) == REG
17613 || (GET_CODE (XEXP (b, 0)) == PLUS
17614 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
17616 HOST_WIDE_INT val0 = 0, val1 = 0;
17620 if (GET_CODE (XEXP (a, 0)) == PLUS)
17622 reg0 = XEXP (XEXP (a, 0), 0);
17623 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
17626 reg0 = XEXP (a, 0);
17628 if (GET_CODE (XEXP (b, 0)) == PLUS)
17630 reg1 = XEXP (XEXP (b, 0), 0);
17631 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
17634 reg1 = XEXP (b, 0);
17636 val_diff = val1 - val0;
17638 return ((REGNO (reg0) == REGNO (reg1))
17639 && (val_diff == INTVAL (MEM_SIZE (a))
17640 || val_diff == -INTVAL (MEM_SIZE (b))));
17646 /* A C statement (sans semicolon) to update the integer scheduling
17647 priority INSN_PRIORITY (INSN). Increase the priority to execute the
17648 INSN earlier, reduce the priority to execute INSN later. Do not
17649 define this macro if you do not need to adjust the scheduling
17650 priorities of insns. */
17653 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
17655 /* On machines (like the 750) which have asymmetric integer units,
17656 where one integer unit can do multiply and divides and the other
17657 can't, reduce the priority of multiply/divide so it is scheduled
17658 before other integer operations. */
17661 if (! INSN_P (insn))
17664 if (GET_CODE (PATTERN (insn)) == USE)
17667 switch (rs6000_cpu_attr) {
17669 switch (get_attr_type (insn))
17676 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
17677 priority, priority);
17678 if (priority >= 0 && priority < 0x01000000)
17685 if (insn_must_be_first_in_group (insn)
17686 && reload_completed
17687 && current_sched_info->sched_max_insns_priority
17688 && rs6000_sched_restricted_insns_priority)
17691 /* Prioritize insns that can be dispatched only in the first
17693 if (rs6000_sched_restricted_insns_priority == 1)
17694 /* Attach highest priority to insn. This means that in
17695 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
17696 precede 'priority' (critical path) considerations. */
17697 return current_sched_info->sched_max_insns_priority;
17698 else if (rs6000_sched_restricted_insns_priority == 2)
17699 /* Increase priority of insn by a minimal amount. This means that in
17700 haifa-sched.c:ready_sort(), only 'priority' (critical path)
17701 considerations precede dispatch-slot restriction considerations. */
17702 return (priority + 1);
17705 if (rs6000_cpu == PROCESSOR_POWER6
17706 && ((load_store_pendulum == -2 && is_load_insn (insn))
17707 || (load_store_pendulum == 2 && is_store_insn (insn))))
17708 /* Attach highest priority to insn if the scheduler has just issued two
17709 stores and this instruction is a load, or two loads and this instruction
17710 is a store. Power6 wants loads and stores scheduled alternately
17712 return current_sched_info->sched_max_insns_priority;
17717 /* Return true if the instruction is nonpipelined on the Cell. */
17719 is_nonpipeline_insn (rtx insn)
17721 enum attr_type type;
17722 if (!insn || !INSN_P (insn)
17723 || GET_CODE (PATTERN (insn)) == USE
17724 || GET_CODE (PATTERN (insn)) == CLOBBER)
17727 type = get_attr_type (insn);
17728 if (type == TYPE_IMUL
17729 || type == TYPE_IMUL2
17730 || type == TYPE_IMUL3
17731 || type == TYPE_LMUL
17732 || type == TYPE_IDIV
17733 || type == TYPE_LDIV
17734 || type == TYPE_SDIV
17735 || type == TYPE_DDIV
17736 || type == TYPE_SSQRT
17737 || type == TYPE_DSQRT
17738 || type == TYPE_MFCR
17739 || type == TYPE_MFCRF
17740 || type == TYPE_MFJMPR)
17748 /* Return how many instructions the machine can issue per cycle. */
17751 rs6000_issue_rate (void)
17753 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
17754 if (!reload_completed)
17757 switch (rs6000_cpu_attr) {
17758 case CPU_RIOS1: /* ? */
17760 case CPU_PPC601: /* ? */
17785 /* Return how many instructions to look ahead for better insn
17789 rs6000_use_sched_lookahead (void)
17791 if (rs6000_cpu_attr == CPU_PPC8540)
17793 if (rs6000_cpu_attr == CPU_CELL)
17794 return (reload_completed ? 8 : 0);
17798 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
17800 rs6000_use_sched_lookahead_guard (rtx insn)
17802 if (rs6000_cpu_attr != CPU_CELL)
17805 if (insn == NULL_RTX || !INSN_P (insn))
17808 if (!reload_completed
17809 || is_nonpipeline_insn (insn)
17810 || is_microcoded_insn (insn))
17816 /* Determine is PAT refers to memory. */
17819 is_mem_ref (rtx pat)
17825 if (GET_CODE (pat) == MEM)
17828 /* Recursively process the pattern. */
17829 fmt = GET_RTX_FORMAT (GET_CODE (pat));
17831 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
17834 ret |= is_mem_ref (XEXP (pat, i));
17835 else if (fmt[i] == 'E')
17836 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
17837 ret |= is_mem_ref (XVECEXP (pat, i, j));
17843 /* Determine if PAT is a PATTERN of a load insn. */
17846 is_load_insn1 (rtx pat)
17848 if (!pat || pat == NULL_RTX)
17851 if (GET_CODE (pat) == SET)
17852 return is_mem_ref (SET_SRC (pat));
17854 if (GET_CODE (pat) == PARALLEL)
17858 for (i = 0; i < XVECLEN (pat, 0); i++)
17859 if (is_load_insn1 (XVECEXP (pat, 0, i)))
17866 /* Determine if INSN loads from memory. */
17869 is_load_insn (rtx insn)
17871 if (!insn || !INSN_P (insn))
17874 if (GET_CODE (insn) == CALL_INSN)
17877 return is_load_insn1 (PATTERN (insn));
17880 /* Determine if PAT is a PATTERN of a store insn. */
17883 is_store_insn1 (rtx pat)
17885 if (!pat || pat == NULL_RTX)
17888 if (GET_CODE (pat) == SET)
17889 return is_mem_ref (SET_DEST (pat));
17891 if (GET_CODE (pat) == PARALLEL)
17895 for (i = 0; i < XVECLEN (pat, 0); i++)
17896 if (is_store_insn1 (XVECEXP (pat, 0, i)))
17903 /* Determine if INSN stores to memory. */
17906 is_store_insn (rtx insn)
17908 if (!insn || !INSN_P (insn))
17911 return is_store_insn1 (PATTERN (insn));
17914 /* Return the dest of a store insn. */
17917 get_store_dest (rtx pat)
17919 gcc_assert (is_store_insn1 (pat));
17921 if (GET_CODE (pat) == SET)
17922 return SET_DEST (pat);
17923 else if (GET_CODE (pat) == PARALLEL)
17927 for (i = 0; i < XVECLEN (pat, 0); i++)
17929 rtx inner_pat = XVECEXP (pat, 0, i);
17930 if (GET_CODE (inner_pat) == SET
17931 && is_mem_ref (SET_DEST (inner_pat)))
17935 /* We shouldn't get here, because we should have either a simple
17936 store insn or a store with update which are covered above. */
17940 /* Returns whether the dependence between INSN and NEXT is considered
17941 costly by the given target. */
17944 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
17949 /* If the flag is not enabled - no dependence is considered costly;
17950 allow all dependent insns in the same group.
17951 This is the most aggressive option. */
17952 if (rs6000_sched_costly_dep == no_dep_costly)
17955 /* If the flag is set to 1 - a dependence is always considered costly;
17956 do not allow dependent instructions in the same group.
17957 This is the most conservative option. */
17958 if (rs6000_sched_costly_dep == all_deps_costly)
17961 insn = DEP_PRO (dep);
17962 next = DEP_CON (dep);
17964 if (rs6000_sched_costly_dep == store_to_load_dep_costly
17965 && is_load_insn (next)
17966 && is_store_insn (insn))
17967 /* Prevent load after store in the same group. */
17970 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
17971 && is_load_insn (next)
17972 && is_store_insn (insn)
17973 && DEP_TYPE (dep) == REG_DEP_TRUE)
17974 /* Prevent load after store in the same group if it is a true
17978 /* The flag is set to X; dependences with latency >= X are considered costly,
17979 and will not be scheduled in the same group. */
17980 if (rs6000_sched_costly_dep <= max_dep_latency
17981 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
17987 /* Return the next insn after INSN that is found before TAIL is reached,
17988 skipping any "non-active" insns - insns that will not actually occupy
17989 an issue slot. Return NULL_RTX if such an insn is not found. */
17992 get_next_active_insn (rtx insn, rtx tail)
17994 if (insn == NULL_RTX || insn == tail)
17999 insn = NEXT_INSN (insn);
18000 if (insn == NULL_RTX || insn == tail)
18005 || (NONJUMP_INSN_P (insn)
18006 && GET_CODE (PATTERN (insn)) != USE
18007 && GET_CODE (PATTERN (insn)) != CLOBBER
18008 && INSN_CODE (insn) != CODE_FOR_stack_tie))
18014 /* We are about to begin issuing insns for this clock cycle. */
18017 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
18018 rtx *ready ATTRIBUTE_UNUSED,
18019 int *pn_ready ATTRIBUTE_UNUSED,
18020 int clock_var ATTRIBUTE_UNUSED)
18022 int n_ready = *pn_ready;
18025 fprintf (dump, "// rs6000_sched_reorder :\n");
18027 /* Reorder the ready list, if the second to last ready insn
18028 is a nonepipeline insn. */
18029 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
18031 if (is_nonpipeline_insn (ready[n_ready - 1])
18032 && (recog_memoized (ready[n_ready - 2]) > 0))
18033 /* Simply swap first two insns. */
18035 rtx tmp = ready[n_ready - 1];
18036 ready[n_ready - 1] = ready[n_ready - 2];
18037 ready[n_ready - 2] = tmp;
18041 if (rs6000_cpu == PROCESSOR_POWER6)
18042 load_store_pendulum = 0;
18044 return rs6000_issue_rate ();
18047 /* Like rs6000_sched_reorder, but called after issuing each insn. */
18050 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
18051 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
18054 fprintf (dump, "// rs6000_sched_reorder2 :\n");
18056 /* For Power6, we need to handle some special cases to try and keep the
18057 store queue from overflowing and triggering expensive flushes.
18059 This code monitors how load and store instructions are being issued
18060 and skews the ready list one way or the other to increase the likelihood
18061 that a desired instruction is issued at the proper time.
18063 A couple of things are done. First, we maintain a "load_store_pendulum"
18064 to track the current state of load/store issue.
18066 - If the pendulum is at zero, then no loads or stores have been
18067 issued in the current cycle so we do nothing.
18069 - If the pendulum is 1, then a single load has been issued in this
18070 cycle and we attempt to locate another load in the ready list to
18073 - If the pendulum is -2, then two stores have already been
18074 issued in this cycle, so we increase the priority of the first load
18075 in the ready list to increase it's likelihood of being chosen first
18078 - If the pendulum is -1, then a single store has been issued in this
18079 cycle and we attempt to locate another store in the ready list to
18080 issue with it, preferring a store to an adjacent memory location to
18081 facilitate store pairing in the store queue.
18083 - If the pendulum is 2, then two loads have already been
18084 issued in this cycle, so we increase the priority of the first store
18085 in the ready list to increase it's likelihood of being chosen first
18088 - If the pendulum < -2 or > 2, then do nothing.
18090 Note: This code covers the most common scenarios. There exist non
18091 load/store instructions which make use of the LSU and which
18092 would need to be accounted for to strictly model the behavior
18093 of the machine. Those instructions are currently unaccounted
18094 for to help minimize compile time overhead of this code.
18096 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
18102 if (is_store_insn (last_scheduled_insn))
18103 /* Issuing a store, swing the load_store_pendulum to the left */
18104 load_store_pendulum--;
18105 else if (is_load_insn (last_scheduled_insn))
18106 /* Issuing a load, swing the load_store_pendulum to the right */
18107 load_store_pendulum++;
18109 return cached_can_issue_more;
18111 /* If the pendulum is balanced, or there is only one instruction on
18112 the ready list, then all is well, so return. */
18113 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
18114 return cached_can_issue_more;
18116 if (load_store_pendulum == 1)
18118 /* A load has been issued in this cycle. Scan the ready list
18119 for another load to issue with it */
18124 if (is_load_insn (ready[pos]))
18126 /* Found a load. Move it to the head of the ready list,
18127 and adjust it's priority so that it is more likely to
18130 for (i=pos; i<*pn_ready-1; i++)
18131 ready[i] = ready[i + 1];
18132 ready[*pn_ready-1] = tmp;
18133 if INSN_PRIORITY_KNOWN (tmp)
18134 INSN_PRIORITY (tmp)++;
18140 else if (load_store_pendulum == -2)
18142 /* Two stores have been issued in this cycle. Increase the
18143 priority of the first load in the ready list to favor it for
18144 issuing in the next cycle. */
18149 if (is_load_insn (ready[pos])
18150 && INSN_PRIORITY_KNOWN (ready[pos]))
18152 INSN_PRIORITY (ready[pos])++;
18154 /* Adjust the pendulum to account for the fact that a load
18155 was found and increased in priority. This is to prevent
18156 increasing the priority of multiple loads */
18157 load_store_pendulum--;
18164 else if (load_store_pendulum == -1)
18166 /* A store has been issued in this cycle. Scan the ready list for
18167 another store to issue with it, preferring a store to an adjacent
18169 int first_store_pos = -1;
18175 if (is_store_insn (ready[pos]))
18177 /* Maintain the index of the first store found on the
18179 if (first_store_pos == -1)
18180 first_store_pos = pos;
18182 if (is_store_insn (last_scheduled_insn)
18183 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
18185 /* Found an adjacent store. Move it to the head of the
18186 ready list, and adjust it's priority so that it is
18187 more likely to stay there */
18189 for (i=pos; i<*pn_ready-1; i++)
18190 ready[i] = ready[i + 1];
18191 ready[*pn_ready-1] = tmp;
18192 if INSN_PRIORITY_KNOWN (tmp)
18193 INSN_PRIORITY (tmp)++;
18194 first_store_pos = -1;
18202 if (first_store_pos >= 0)
18204 /* An adjacent store wasn't found, but a non-adjacent store was,
18205 so move the non-adjacent store to the front of the ready
18206 list, and adjust its priority so that it is more likely to
18208 tmp = ready[first_store_pos];
18209 for (i=first_store_pos; i<*pn_ready-1; i++)
18210 ready[i] = ready[i + 1];
18211 ready[*pn_ready-1] = tmp;
18212 if INSN_PRIORITY_KNOWN (tmp)
18213 INSN_PRIORITY (tmp)++;
18216 else if (load_store_pendulum == 2)
18218 /* Two loads have been issued in this cycle. Increase the priority
18219 of the first store in the ready list to favor it for issuing in
18225 if (is_store_insn (ready[pos])
18226 && INSN_PRIORITY_KNOWN (ready[pos]))
18228 INSN_PRIORITY (ready[pos])++;
18230 /* Adjust the pendulum to account for the fact that a store
18231 was found and increased in priority. This is to prevent
18232 increasing the priority of multiple stores */
18233 load_store_pendulum++;
18242 return cached_can_issue_more;
18245 /* Return whether the presence of INSN causes a dispatch group termination
18246 of group WHICH_GROUP.
18248 If WHICH_GROUP == current_group, this function will return true if INSN
18249 causes the termination of the current group (i.e, the dispatch group to
18250 which INSN belongs). This means that INSN will be the last insn in the
18251 group it belongs to.
18253 If WHICH_GROUP == previous_group, this function will return true if INSN
18254 causes the termination of the previous group (i.e, the dispatch group that
18255 precedes the group to which INSN belongs). This means that INSN will be
18256 the first insn in the group it belongs to). */
18259 insn_terminates_group_p (rtx insn, enum group_termination which_group)
18266 first = insn_must_be_first_in_group (insn);
18267 last = insn_must_be_last_in_group (insn);
18272 if (which_group == current_group)
18274 else if (which_group == previous_group)
18282 insn_must_be_first_in_group (rtx insn)
18284 enum attr_type type;
18287 || insn == NULL_RTX
18288 || GET_CODE (insn) == NOTE
18289 || GET_CODE (PATTERN (insn)) == USE
18290 || GET_CODE (PATTERN (insn)) == CLOBBER)
18293 switch (rs6000_cpu)
18295 case PROCESSOR_POWER5:
18296 if (is_cracked_insn (insn))
18298 case PROCESSOR_POWER4:
18299 if (is_microcoded_insn (insn))
18302 if (!rs6000_sched_groups)
18305 type = get_attr_type (insn);
18312 case TYPE_DELAYED_CR:
18313 case TYPE_CR_LOGICAL:
18327 case PROCESSOR_POWER6:
18328 type = get_attr_type (insn);
18332 case TYPE_INSERT_DWORD:
18336 case TYPE_VAR_SHIFT_ROTATE:
18343 case TYPE_INSERT_WORD:
18344 case TYPE_DELAYED_COMPARE:
18345 case TYPE_IMUL_COMPARE:
18346 case TYPE_LMUL_COMPARE:
18347 case TYPE_FPCOMPARE:
18358 case TYPE_LOAD_EXT_UX:
18360 case TYPE_STORE_UX:
18361 case TYPE_FPLOAD_U:
18362 case TYPE_FPLOAD_UX:
18363 case TYPE_FPSTORE_U:
18364 case TYPE_FPSTORE_UX:
18378 insn_must_be_last_in_group (rtx insn)
18380 enum attr_type type;
18383 || insn == NULL_RTX
18384 || GET_CODE (insn) == NOTE
18385 || GET_CODE (PATTERN (insn)) == USE
18386 || GET_CODE (PATTERN (insn)) == CLOBBER)
18389 switch (rs6000_cpu) {
18390 case PROCESSOR_POWER4:
18391 case PROCESSOR_POWER5:
18392 if (is_microcoded_insn (insn))
18395 if (is_branch_slot_insn (insn))
18399 case PROCESSOR_POWER6:
18400 type = get_attr_type (insn);
18407 case TYPE_VAR_SHIFT_ROTATE:
18414 case TYPE_DELAYED_COMPARE:
18415 case TYPE_IMUL_COMPARE:
18416 case TYPE_LMUL_COMPARE:
18417 case TYPE_FPCOMPARE:
18438 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18439 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18442 is_costly_group (rtx *group_insns, rtx next_insn)
18445 int issue_rate = rs6000_issue_rate ();
18447 for (i = 0; i < issue_rate; i++)
18449 sd_iterator_def sd_it;
18451 rtx insn = group_insns[i];
18456 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
18458 rtx next = DEP_CON (dep);
18460 if (next == next_insn
18461 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
18469 /* Utility of the function redefine_groups.
18470 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18471 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18472 to keep it "far" (in a separate group) from GROUP_INSNS, following
18473 one of the following schemes, depending on the value of the flag
18474 -minsert_sched_nops = X:
18475 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18476 in order to force NEXT_INSN into a separate group.
18477 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18478 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18479 insertion (has a group just ended, how many vacant issue slots remain in the
18480 last group, and how many dispatch groups were encountered so far). */
18483 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
18484 rtx next_insn, bool *group_end, int can_issue_more,
18489 int issue_rate = rs6000_issue_rate ();
18490 bool end = *group_end;
18493 if (next_insn == NULL_RTX)
18494 return can_issue_more;
18496 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
18497 return can_issue_more;
18499 force = is_costly_group (group_insns, next_insn);
18501 return can_issue_more;
18503 if (sched_verbose > 6)
18504 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
18505 *group_count ,can_issue_more);
18507 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
18510 can_issue_more = 0;
18512 /* Since only a branch can be issued in the last issue_slot, it is
18513 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18514 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18515 in this case the last nop will start a new group and the branch
18516 will be forced to the new group. */
18517 if (can_issue_more && !is_branch_slot_insn (next_insn))
18520 while (can_issue_more > 0)
18523 emit_insn_before (nop, next_insn);
18531 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18533 int n_nops = rs6000_sched_insert_nops;
18535 /* Nops can't be issued from the branch slot, so the effective
18536 issue_rate for nops is 'issue_rate - 1'. */
18537 if (can_issue_more == 0)
18538 can_issue_more = issue_rate;
18540 if (can_issue_more == 0)
18542 can_issue_more = issue_rate - 1;
18545 for (i = 0; i < issue_rate; i++)
18547 group_insns[i] = 0;
18554 emit_insn_before (nop, next_insn);
18555 if (can_issue_more == issue_rate - 1) /* new group begins */
18558 if (can_issue_more == 0)
18560 can_issue_more = issue_rate - 1;
18563 for (i = 0; i < issue_rate; i++)
18565 group_insns[i] = 0;
18571 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18574 /* Is next_insn going to start a new group? */
18577 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18578 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18579 || (can_issue_more < issue_rate &&
18580 insn_terminates_group_p (next_insn, previous_group)));
18581 if (*group_end && end)
18584 if (sched_verbose > 6)
18585 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
18586 *group_count, can_issue_more);
18587 return can_issue_more;
18590 return can_issue_more;
18593 /* This function tries to synch the dispatch groups that the compiler "sees"
18594 with the dispatch groups that the processor dispatcher is expected to
18595 form in practice. It tries to achieve this synchronization by forcing the
18596 estimated processor grouping on the compiler (as opposed to the function
18597 'pad_goups' which tries to force the scheduler's grouping on the processor).
18599 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18600 examines the (estimated) dispatch groups that will be formed by the processor
18601 dispatcher. It marks these group boundaries to reflect the estimated
18602 processor grouping, overriding the grouping that the scheduler had marked.
18603 Depending on the value of the flag '-minsert-sched-nops' this function can
18604 force certain insns into separate groups or force a certain distance between
18605 them by inserting nops, for example, if there exists a "costly dependence"
18608 The function estimates the group boundaries that the processor will form as
18609 follows: It keeps track of how many vacant issue slots are available after
18610 each insn. A subsequent insn will start a new group if one of the following
18612 - no more vacant issue slots remain in the current dispatch group.
18613 - only the last issue slot, which is the branch slot, is vacant, but the next
18614 insn is not a branch.
18615 - only the last 2 or less issue slots, including the branch slot, are vacant,
18616 which means that a cracked insn (which occupies two issue slots) can't be
18617 issued in this group.
18618 - less than 'issue_rate' slots are vacant, and the next insn always needs to
18619 start a new group. */
18622 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18624 rtx insn, next_insn;
18626 int can_issue_more;
18629 int group_count = 0;
18633 issue_rate = rs6000_issue_rate ();
18634 group_insns = alloca (issue_rate * sizeof (rtx));
18635 for (i = 0; i < issue_rate; i++)
18637 group_insns[i] = 0;
18639 can_issue_more = issue_rate;
18641 insn = get_next_active_insn (prev_head_insn, tail);
18644 while (insn != NULL_RTX)
18646 slot = (issue_rate - can_issue_more);
18647 group_insns[slot] = insn;
18649 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18650 if (insn_terminates_group_p (insn, current_group))
18651 can_issue_more = 0;
18653 next_insn = get_next_active_insn (insn, tail);
18654 if (next_insn == NULL_RTX)
18655 return group_count + 1;
18657 /* Is next_insn going to start a new group? */
18659 = (can_issue_more == 0
18660 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18661 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18662 || (can_issue_more < issue_rate &&
18663 insn_terminates_group_p (next_insn, previous_group)));
18665 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
18666 next_insn, &group_end, can_issue_more,
18672 can_issue_more = 0;
18673 for (i = 0; i < issue_rate; i++)
18675 group_insns[i] = 0;
18679 if (GET_MODE (next_insn) == TImode && can_issue_more)
18680 PUT_MODE (next_insn, VOIDmode);
18681 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
18682 PUT_MODE (next_insn, TImode);
18685 if (can_issue_more == 0)
18686 can_issue_more = issue_rate;
18689 return group_count;
18692 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
18693 dispatch group boundaries that the scheduler had marked. Pad with nops
18694 any dispatch groups which have vacant issue slots, in order to force the
18695 scheduler's grouping on the processor dispatcher. The function
18696 returns the number of dispatch groups found. */
18699 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18701 rtx insn, next_insn;
18704 int can_issue_more;
18706 int group_count = 0;
18708 /* Initialize issue_rate. */
18709 issue_rate = rs6000_issue_rate ();
18710 can_issue_more = issue_rate;
18712 insn = get_next_active_insn (prev_head_insn, tail);
18713 next_insn = get_next_active_insn (insn, tail);
18715 while (insn != NULL_RTX)
18718 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18720 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
18722 if (next_insn == NULL_RTX)
18727 /* If the scheduler had marked group termination at this location
18728 (between insn and next_indn), and neither insn nor next_insn will
18729 force group termination, pad the group with nops to force group
18732 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
18733 && !insn_terminates_group_p (insn, current_group)
18734 && !insn_terminates_group_p (next_insn, previous_group))
18736 if (!is_branch_slot_insn (next_insn))
18739 while (can_issue_more)
18742 emit_insn_before (nop, next_insn);
18747 can_issue_more = issue_rate;
18752 next_insn = get_next_active_insn (insn, tail);
18755 return group_count;
18758 /* We're beginning a new block. Initialize data structures as necessary. */
18761 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
18762 int sched_verbose ATTRIBUTE_UNUSED,
18763 int max_ready ATTRIBUTE_UNUSED)
18765 last_scheduled_insn = NULL_RTX;
18766 load_store_pendulum = 0;
18769 /* The following function is called at the end of scheduling BB.
18770 After reload, it inserts nops at insn group bundling. */
18773 rs6000_sched_finish (FILE *dump, int sched_verbose)
18778 fprintf (dump, "=== Finishing schedule.\n");
18780 if (reload_completed && rs6000_sched_groups)
18782 if (rs6000_sched_insert_nops == sched_finish_none)
18785 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
18786 n_groups = pad_groups (dump, sched_verbose,
18787 current_sched_info->prev_head,
18788 current_sched_info->next_tail);
18790 n_groups = redefine_groups (dump, sched_verbose,
18791 current_sched_info->prev_head,
18792 current_sched_info->next_tail);
18794 if (sched_verbose >= 6)
18796 fprintf (dump, "ngroups = %d\n", n_groups);
18797 print_rtl (dump, current_sched_info->prev_head);
18798 fprintf (dump, "Done finish_sched\n");
18803 /* Length in units of the trampoline for entering a nested function. */
18806 rs6000_trampoline_size (void)
18810 switch (DEFAULT_ABI)
18813 gcc_unreachable ();
18816 ret = (TARGET_32BIT) ? 12 : 24;
18821 ret = (TARGET_32BIT) ? 40 : 48;
18828 /* Emit RTL insns to initialize the variable parts of a trampoline.
18829 FNADDR is an RTX for the address of the function's pure code.
18830 CXT is an RTX for the static chain value for the function. */
18833 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
18835 int regsize = (TARGET_32BIT) ? 4 : 8;
18836 rtx ctx_reg = force_reg (Pmode, cxt);
18838 switch (DEFAULT_ABI)
18841 gcc_unreachable ();
18843 /* Macros to shorten the code expansions below. */
18844 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
18845 #define MEM_PLUS(addr,offset) \
18846 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
18848 /* Under AIX, just build the 3 word function descriptor */
18851 rtx fn_reg = gen_reg_rtx (Pmode);
18852 rtx toc_reg = gen_reg_rtx (Pmode);
18853 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
18854 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
18855 emit_move_insn (MEM_DEREF (addr), fn_reg);
18856 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
18857 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
18861 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
18864 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
18865 FALSE, VOIDmode, 4,
18867 GEN_INT (rs6000_trampoline_size ()), SImode,
18877 /* Table of valid machine attributes. */
18879 const struct attribute_spec rs6000_attribute_table[] =
18881 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
18882 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
18883 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18884 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18885 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18886 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18887 #ifdef SUBTARGET_ATTRIBUTE_TABLE
18888 SUBTARGET_ATTRIBUTE_TABLE,
18890 { NULL, 0, 0, false, false, false, NULL }
18893 /* Handle the "altivec" attribute. The attribute may have
18894 arguments as follows:
18896 __attribute__((altivec(vector__)))
18897 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
18898 __attribute__((altivec(bool__))) (always followed by 'unsigned')
18900 and may appear more than once (e.g., 'vector bool char') in a
18901 given declaration. */
18904 rs6000_handle_altivec_attribute (tree *node,
18905 tree name ATTRIBUTE_UNUSED,
18907 int flags ATTRIBUTE_UNUSED,
18908 bool *no_add_attrs)
18910 tree type = *node, result = NULL_TREE;
18911 enum machine_mode mode;
18914 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
18915 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
18916 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
18919 while (POINTER_TYPE_P (type)
18920 || TREE_CODE (type) == FUNCTION_TYPE
18921 || TREE_CODE (type) == METHOD_TYPE
18922 || TREE_CODE (type) == ARRAY_TYPE)
18923 type = TREE_TYPE (type);
18925 mode = TYPE_MODE (type);
18927 /* Check for invalid AltiVec type qualifiers. */
18928 if (type == long_unsigned_type_node || type == long_integer_type_node)
18931 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
18932 else if (rs6000_warn_altivec_long)
18933 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
18935 else if (type == long_long_unsigned_type_node
18936 || type == long_long_integer_type_node)
18937 error ("use of %<long long%> in AltiVec types is invalid");
18938 else if (type == double_type_node)
18939 error ("use of %<double%> in AltiVec types is invalid");
18940 else if (type == long_double_type_node)
18941 error ("use of %<long double%> in AltiVec types is invalid");
18942 else if (type == boolean_type_node)
18943 error ("use of boolean types in AltiVec types is invalid");
18944 else if (TREE_CODE (type) == COMPLEX_TYPE)
18945 error ("use of %<complex%> in AltiVec types is invalid");
18946 else if (DECIMAL_FLOAT_MODE_P (mode))
18947 error ("use of decimal floating point types in AltiVec types is invalid");
18949 switch (altivec_type)
18952 unsigned_p = TYPE_UNSIGNED (type);
18956 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
18959 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
18962 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
18964 case SFmode: result = V4SF_type_node; break;
18965 /* If the user says 'vector int bool', we may be handed the 'bool'
18966 attribute _before_ the 'vector' attribute, and so select the
18967 proper type in the 'b' case below. */
18968 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
18976 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
18977 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
18978 case QImode: case V16QImode: result = bool_V16QI_type_node;
18985 case V8HImode: result = pixel_V8HI_type_node;
18991 if (result && result != type && TYPE_READONLY (type))
18992 result = build_qualified_type (result, TYPE_QUAL_CONST);
18994 *no_add_attrs = true; /* No need to hang on to the attribute. */
18997 *node = reconstruct_complex_type (*node, result);
19002 /* AltiVec defines four built-in scalar types that serve as vector
19003 elements; we must teach the compiler how to mangle them. */
19005 static const char *
19006 rs6000_mangle_type (const_tree type)
19008 type = TYPE_MAIN_VARIANT (type);
19010 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
19011 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
19014 if (type == bool_char_type_node) return "U6__boolc";
19015 if (type == bool_short_type_node) return "U6__bools";
19016 if (type == pixel_type_node) return "u7__pixel";
19017 if (type == bool_int_type_node) return "U6__booli";
19019 /* Mangle IBM extended float long double as `g' (__float128) on
19020 powerpc*-linux where long-double-64 previously was the default. */
19021 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
19023 && TARGET_LONG_DOUBLE_128
19024 && !TARGET_IEEEQUAD)
19027 /* For all other types, use normal C++ mangling. */
19031 /* Handle a "longcall" or "shortcall" attribute; arguments as in
19032 struct attribute_spec.handler. */
19035 rs6000_handle_longcall_attribute (tree *node, tree name,
19036 tree args ATTRIBUTE_UNUSED,
19037 int flags ATTRIBUTE_UNUSED,
19038 bool *no_add_attrs)
19040 if (TREE_CODE (*node) != FUNCTION_TYPE
19041 && TREE_CODE (*node) != FIELD_DECL
19042 && TREE_CODE (*node) != TYPE_DECL)
19044 warning (OPT_Wattributes, "%qs attribute only applies to functions",
19045 IDENTIFIER_POINTER (name));
19046 *no_add_attrs = true;
19052 /* Set longcall attributes on all functions declared when
19053 rs6000_default_long_calls is true. */
19055 rs6000_set_default_type_attributes (tree type)
19057 if (rs6000_default_long_calls
19058 && (TREE_CODE (type) == FUNCTION_TYPE
19059 || TREE_CODE (type) == METHOD_TYPE))
19060 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
19062 TYPE_ATTRIBUTES (type));
19065 darwin_set_default_type_attributes (type);
19069 /* Return a reference suitable for calling a function with the
19070 longcall attribute. */
19073 rs6000_longcall_ref (rtx call_ref)
19075 const char *call_name;
19078 if (GET_CODE (call_ref) != SYMBOL_REF)
19081 /* System V adds '.' to the internal name, so skip them. */
19082 call_name = XSTR (call_ref, 0);
19083 if (*call_name == '.')
19085 while (*call_name == '.')
19088 node = get_identifier (call_name);
19089 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
19092 return force_reg (Pmode, call_ref);
19095 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
19096 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
19099 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
19100 struct attribute_spec.handler. */
19102 rs6000_handle_struct_attribute (tree *node, tree name,
19103 tree args ATTRIBUTE_UNUSED,
19104 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
19107 if (DECL_P (*node))
19109 if (TREE_CODE (*node) == TYPE_DECL)
19110 type = &TREE_TYPE (*node);
19115 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
19116 || TREE_CODE (*type) == UNION_TYPE)))
19118 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
19119 *no_add_attrs = true;
19122 else if ((is_attribute_p ("ms_struct", name)
19123 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
19124 || ((is_attribute_p ("gcc_struct", name)
19125 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
19127 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
19128 IDENTIFIER_POINTER (name));
19129 *no_add_attrs = true;
19136 rs6000_ms_bitfield_layout_p (const_tree record_type)
19138 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
19139 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
19140 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
19143 #ifdef USING_ELFOS_H
19145 /* A get_unnamed_section callback, used for switching to toc_section. */
19148 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19150 if (DEFAULT_ABI == ABI_AIX
19151 && TARGET_MINIMAL_TOC
19152 && !TARGET_RELOCATABLE)
19154 if (!toc_initialized)
19156 toc_initialized = 1;
19157 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19158 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
19159 fprintf (asm_out_file, "\t.tc ");
19160 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
19161 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19162 fprintf (asm_out_file, "\n");
19164 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19165 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19166 fprintf (asm_out_file, " = .+32768\n");
19169 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19171 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
19172 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19175 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19176 if (!toc_initialized)
19178 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19179 fprintf (asm_out_file, " = .+32768\n");
19180 toc_initialized = 1;
19185 /* Implement TARGET_ASM_INIT_SECTIONS. */
19188 rs6000_elf_asm_init_sections (void)
19191 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
19194 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
19195 SDATA2_SECTION_ASM_OP);
19198 /* Implement TARGET_SELECT_RTX_SECTION. */
19201 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
19202 unsigned HOST_WIDE_INT align)
19204 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19205 return toc_section;
19207 return default_elf_select_rtx_section (mode, x, align);
19210 /* For a SYMBOL_REF, set generic flags and then perform some
19211 target-specific processing.
19213 When the AIX ABI is requested on a non-AIX system, replace the
19214 function name with the real name (with a leading .) rather than the
19215 function descriptor name. This saves a lot of overriding code to
19216 read the prefixes. */
19219 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
19221 default_encode_section_info (decl, rtl, first);
19224 && TREE_CODE (decl) == FUNCTION_DECL
19226 && DEFAULT_ABI == ABI_AIX)
19228 rtx sym_ref = XEXP (rtl, 0);
19229 size_t len = strlen (XSTR (sym_ref, 0));
19230 char *str = alloca (len + 2);
19232 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
19233 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
19238 compare_section_name (const char *section, const char *template)
19242 len = strlen (template);
19243 return (strncmp (section, template, len) == 0
19244 && (section[len] == 0 || section[len] == '.'));
19248 rs6000_elf_in_small_data_p (const_tree decl)
19250 if (rs6000_sdata == SDATA_NONE)
19253 /* We want to merge strings, so we never consider them small data. */
19254 if (TREE_CODE (decl) == STRING_CST)
19257 /* Functions are never in the small data area. */
19258 if (TREE_CODE (decl) == FUNCTION_DECL)
19261 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
19263 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
19264 if (compare_section_name (section, ".sdata") == 0
19265 || compare_section_name (section, ".sdata2") == 0
19266 || compare_section_name (section, ".gnu.linkonce.s") == 0
19267 || compare_section_name (section, ".sbss") == 0
19268 || compare_section_name (section, ".sbss2") == 0
19269 || compare_section_name (section, ".gnu.linkonce.sb") == 0
19270 || strcmp (section, ".PPC.EMB.sdata0") == 0
19271 || strcmp (section, ".PPC.EMB.sbss0") == 0)
19276 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
19279 && (unsigned HOST_WIDE_INT) size <= g_switch_value
19280 /* If it's not public, and we're not going to reference it there,
19281 there's no need to put it in the small data section. */
19282 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
19289 #endif /* USING_ELFOS_H */
19291 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
19294 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
19296 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
19299 /* Return a REG that occurs in ADDR with coefficient 1.
19300 ADDR can be effectively incremented by incrementing REG.
19302 r0 is special and we must not select it as an address
19303 register by this routine since our caller will try to
19304 increment the returned register via an "la" instruction. */
19307 find_addr_reg (rtx addr)
19309 while (GET_CODE (addr) == PLUS)
19311 if (GET_CODE (XEXP (addr, 0)) == REG
19312 && REGNO (XEXP (addr, 0)) != 0)
19313 addr = XEXP (addr, 0);
19314 else if (GET_CODE (XEXP (addr, 1)) == REG
19315 && REGNO (XEXP (addr, 1)) != 0)
19316 addr = XEXP (addr, 1);
19317 else if (CONSTANT_P (XEXP (addr, 0)))
19318 addr = XEXP (addr, 1);
19319 else if (CONSTANT_P (XEXP (addr, 1)))
19320 addr = XEXP (addr, 0);
19322 gcc_unreachable ();
19324 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
19329 rs6000_fatal_bad_address (rtx op)
19331 fatal_insn ("bad address", op);
19336 static tree branch_island_list = 0;
19338 /* Remember to generate a branch island for far calls to the given
19342 add_compiler_branch_island (tree label_name, tree function_name,
19345 tree branch_island = build_tree_list (function_name, label_name);
19346 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
19347 TREE_CHAIN (branch_island) = branch_island_list;
19348 branch_island_list = branch_island;
19351 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19352 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19353 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19354 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19356 /* Generate far-jump branch islands for everything on the
19357 branch_island_list. Invoked immediately after the last instruction
19358 of the epilogue has been emitted; the branch-islands must be
19359 appended to, and contiguous with, the function body. Mach-O stubs
19360 are generated in machopic_output_stub(). */
19363 macho_branch_islands (void)
19366 tree branch_island;
19368 for (branch_island = branch_island_list;
19370 branch_island = TREE_CHAIN (branch_island))
19372 const char *label =
19373 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
19375 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
19376 char name_buf[512];
19377 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19378 if (name[0] == '*' || name[0] == '&')
19379 strcpy (name_buf, name+1);
19383 strcpy (name_buf+1, name);
19385 strcpy (tmp_buf, "\n");
19386 strcat (tmp_buf, label);
19387 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19388 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19389 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19390 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19393 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
19394 strcat (tmp_buf, label);
19395 strcat (tmp_buf, "_pic\n");
19396 strcat (tmp_buf, label);
19397 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
19399 strcat (tmp_buf, "\taddis r11,r11,ha16(");
19400 strcat (tmp_buf, name_buf);
19401 strcat (tmp_buf, " - ");
19402 strcat (tmp_buf, label);
19403 strcat (tmp_buf, "_pic)\n");
19405 strcat (tmp_buf, "\tmtlr r0\n");
19407 strcat (tmp_buf, "\taddi r12,r11,lo16(");
19408 strcat (tmp_buf, name_buf);
19409 strcat (tmp_buf, " - ");
19410 strcat (tmp_buf, label);
19411 strcat (tmp_buf, "_pic)\n");
19413 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
19417 strcat (tmp_buf, ":\nlis r12,hi16(");
19418 strcat (tmp_buf, name_buf);
19419 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
19420 strcat (tmp_buf, name_buf);
19421 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
19423 output_asm_insn (tmp_buf, 0);
19424 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19425 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19426 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19427 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19430 branch_island_list = 0;
19433 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19434 already there or not. */
19437 no_previous_def (tree function_name)
19439 tree branch_island;
19440 for (branch_island = branch_island_list;
19442 branch_island = TREE_CHAIN (branch_island))
19443 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19448 /* GET_PREV_LABEL gets the label name from the previous definition of
19452 get_prev_label (tree function_name)
19454 tree branch_island;
19455 for (branch_island = branch_island_list;
19457 branch_island = TREE_CHAIN (branch_island))
19458 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19459 return BRANCH_ISLAND_LABEL_NAME (branch_island);
19463 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19464 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19467 /* KEXTs still need branch islands. */
19468 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19469 || flag_mkernel || flag_apple_kext)
19471 /* INSN is either a function call or a millicode call. It may have an
19472 unconditional jump in its delay slot.
19474 CALL_DEST is the routine we are calling. */
19477 output_call (rtx insn, rtx *operands, int dest_operand_number,
19478 int cookie_operand_number)
19480 static char buf[256];
19481 if (DARWIN_GENERATE_ISLANDS
19482 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
19483 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
19486 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
19488 if (no_previous_def (funname))
19490 rtx label_rtx = gen_label_rtx ();
19491 char *label_buf, temp_buf[256];
19492 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
19493 CODE_LABEL_NUMBER (label_rtx));
19494 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
19495 labelname = get_identifier (label_buf);
19496 add_compiler_branch_island (labelname, funname, insn_line (insn));
19499 labelname = get_prev_label (funname);
19501 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19502 instruction will reach 'foo', otherwise link as 'bl L42'".
19503 "L42" should be a 'branch island', that will do a far jump to
19504 'foo'. Branch islands are generated in
19505 macho_branch_islands(). */
19506 sprintf (buf, "jbsr %%z%d,%.246s",
19507 dest_operand_number, IDENTIFIER_POINTER (labelname));
19510 sprintf (buf, "bl %%z%d", dest_operand_number);
19514 /* Generate PIC and indirect symbol stubs. */
19517 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19519 unsigned int length;
19520 char *symbol_name, *lazy_ptr_name;
19521 char *local_label_0;
19522 static int label = 0;
19524 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19525 symb = (*targetm.strip_name_encoding) (symb);
19528 length = strlen (symb);
19529 symbol_name = alloca (length + 32);
19530 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19532 lazy_ptr_name = alloca (length + 32);
19533 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19536 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19538 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19542 fprintf (file, "\t.align 5\n");
19544 fprintf (file, "%s:\n", stub);
19545 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19548 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19549 sprintf (local_label_0, "\"L%011d$spb\"", label);
19551 fprintf (file, "\tmflr r0\n");
19552 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19553 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19554 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19555 lazy_ptr_name, local_label_0);
19556 fprintf (file, "\tmtlr r0\n");
19557 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19558 (TARGET_64BIT ? "ldu" : "lwzu"),
19559 lazy_ptr_name, local_label_0);
19560 fprintf (file, "\tmtctr r12\n");
19561 fprintf (file, "\tbctr\n");
19565 fprintf (file, "\t.align 4\n");
19567 fprintf (file, "%s:\n", stub);
19568 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19570 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
19571 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
19572 (TARGET_64BIT ? "ldu" : "lwzu"),
19574 fprintf (file, "\tmtctr r12\n");
19575 fprintf (file, "\tbctr\n");
19578 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
19579 fprintf (file, "%s:\n", lazy_ptr_name);
19580 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19581 fprintf (file, "%sdyld_stub_binding_helper\n",
19582 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
19585 /* Legitimize PIC addresses. If the address is already
19586 position-independent, we return ORIG. Newly generated
19587 position-independent addresses go into a reg. This is REG if non
19588 zero, otherwise we allocate register(s) as necessary. */
19590 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19593 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
19598 if (reg == NULL && ! reload_in_progress && ! reload_completed)
19599 reg = gen_reg_rtx (Pmode);
19601 if (GET_CODE (orig) == CONST)
19605 if (GET_CODE (XEXP (orig, 0)) == PLUS
19606 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
19609 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
19611 /* Use a different reg for the intermediate value, as
19612 it will be marked UNCHANGING. */
19613 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
19614 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
19617 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
19620 if (GET_CODE (offset) == CONST_INT)
19622 if (SMALL_INT (offset))
19623 return plus_constant (base, INTVAL (offset));
19624 else if (! reload_in_progress && ! reload_completed)
19625 offset = force_reg (Pmode, offset);
19628 rtx mem = force_const_mem (Pmode, orig);
19629 return machopic_legitimize_pic_address (mem, Pmode, reg);
19632 return gen_rtx_PLUS (Pmode, base, offset);
19635 /* Fall back on generic machopic code. */
19636 return machopic_legitimize_pic_address (orig, mode, reg);
19639 /* Output a .machine directive for the Darwin assembler, and call
19640 the generic start_file routine. */
19643 rs6000_darwin_file_start (void)
19645 static const struct
19651 { "ppc64", "ppc64", MASK_64BIT },
19652 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
19653 { "power4", "ppc970", 0 },
19654 { "G5", "ppc970", 0 },
19655 { "7450", "ppc7450", 0 },
19656 { "7400", "ppc7400", MASK_ALTIVEC },
19657 { "G4", "ppc7400", 0 },
19658 { "750", "ppc750", 0 },
19659 { "740", "ppc750", 0 },
19660 { "G3", "ppc750", 0 },
19661 { "604e", "ppc604e", 0 },
19662 { "604", "ppc604", 0 },
19663 { "603e", "ppc603", 0 },
19664 { "603", "ppc603", 0 },
19665 { "601", "ppc601", 0 },
19666 { NULL, "ppc", 0 } };
19667 const char *cpu_id = "";
19670 rs6000_file_start ();
19671 darwin_file_start ();
19673 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
19674 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
19675 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
19676 && rs6000_select[i].string[0] != '\0')
19677 cpu_id = rs6000_select[i].string;
19679 /* Look through the mapping array. Pick the first name that either
19680 matches the argument, has a bit set in IF_SET that is also set
19681 in the target flags, or has a NULL name. */
19684 while (mapping[i].arg != NULL
19685 && strcmp (mapping[i].arg, cpu_id) != 0
19686 && (mapping[i].if_set & target_flags) == 0)
19689 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
19692 #endif /* TARGET_MACHO */
19696 rs6000_elf_reloc_rw_mask (void)
19700 else if (DEFAULT_ABI == ABI_AIX)
19706 /* Record an element in the table of global constructors. SYMBOL is
19707 a SYMBOL_REF of the function to be called; PRIORITY is a number
19708 between 0 and MAX_INIT_PRIORITY.
19710 This differs from default_named_section_asm_out_constructor in
19711 that we have special handling for -mrelocatable. */
19714 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
19716 const char *section = ".ctors";
19719 if (priority != DEFAULT_INIT_PRIORITY)
19721 sprintf (buf, ".ctors.%.5u",
19722 /* Invert the numbering so the linker puts us in the proper
19723 order; constructors are run from right to left, and the
19724 linker sorts in increasing order. */
19725 MAX_INIT_PRIORITY - priority);
19729 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19730 assemble_align (POINTER_SIZE);
19732 if (TARGET_RELOCATABLE)
19734 fputs ("\t.long (", asm_out_file);
19735 output_addr_const (asm_out_file, symbol);
19736 fputs (")@fixup\n", asm_out_file);
19739 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19743 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
19745 const char *section = ".dtors";
19748 if (priority != DEFAULT_INIT_PRIORITY)
19750 sprintf (buf, ".dtors.%.5u",
19751 /* Invert the numbering so the linker puts us in the proper
19752 order; constructors are run from right to left, and the
19753 linker sorts in increasing order. */
19754 MAX_INIT_PRIORITY - priority);
19758 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19759 assemble_align (POINTER_SIZE);
19761 if (TARGET_RELOCATABLE)
19763 fputs ("\t.long (", asm_out_file);
19764 output_addr_const (asm_out_file, symbol);
19765 fputs (")@fixup\n", asm_out_file);
19768 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19772 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
19776 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
19777 ASM_OUTPUT_LABEL (file, name);
19778 fputs (DOUBLE_INT_ASM_OP, file);
19779 rs6000_output_function_entry (file, name);
19780 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
19783 fputs ("\t.size\t", file);
19784 assemble_name (file, name);
19785 fputs (",24\n\t.type\t.", file);
19786 assemble_name (file, name);
19787 fputs (",@function\n", file);
19788 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
19790 fputs ("\t.globl\t.", file);
19791 assemble_name (file, name);
19796 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19797 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19798 rs6000_output_function_entry (file, name);
19799 fputs (":\n", file);
19803 if (TARGET_RELOCATABLE
19804 && !TARGET_SECURE_PLT
19805 && (get_pool_size () != 0 || current_function_profile)
19810 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
19812 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
19813 fprintf (file, "\t.long ");
19814 assemble_name (file, buf);
19816 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19817 assemble_name (file, buf);
19821 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19822 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19824 if (DEFAULT_ABI == ABI_AIX)
19826 const char *desc_name, *orig_name;
19828 orig_name = (*targetm.strip_name_encoding) (name);
19829 desc_name = orig_name;
19830 while (*desc_name == '.')
19833 if (TREE_PUBLIC (decl))
19834 fprintf (file, "\t.globl %s\n", desc_name);
19836 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19837 fprintf (file, "%s:\n", desc_name);
19838 fprintf (file, "\t.long %s\n", orig_name);
19839 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
19840 if (DEFAULT_ABI == ABI_AIX)
19841 fputs ("\t.long 0\n", file);
19842 fprintf (file, "\t.previous\n");
19844 ASM_OUTPUT_LABEL (file, name);
19848 rs6000_elf_end_indicate_exec_stack (void)
19851 file_end_indicate_exec_stack ();
19857 rs6000_xcoff_asm_output_anchor (rtx symbol)
19861 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
19862 SYMBOL_REF_BLOCK_OFFSET (symbol));
19863 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
19867 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
19869 fputs (GLOBAL_ASM_OP, stream);
19870 RS6000_OUTPUT_BASENAME (stream, name);
19871 putc ('\n', stream);
19874 /* A get_unnamed_decl callback, used for read-only sections. PTR
19875 points to the section string variable. */
19878 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
19880 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
19881 *(const char *const *) directive);
19884 /* Likewise for read-write sections. */
19887 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
19889 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
19890 *(const char *const *) directive);
19893 /* A get_unnamed_section callback, used for switching to toc_section. */
19896 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19898 if (TARGET_MINIMAL_TOC)
19900 /* toc_section is always selected at least once from
19901 rs6000_xcoff_file_start, so this is guaranteed to
19902 always be defined once and only once in each file. */
19903 if (!toc_initialized)
19905 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
19906 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
19907 toc_initialized = 1;
19909 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
19910 (TARGET_32BIT ? "" : ",3"));
19913 fputs ("\t.toc\n", asm_out_file);
19916 /* Implement TARGET_ASM_INIT_SECTIONS. */
19919 rs6000_xcoff_asm_init_sections (void)
19921 read_only_data_section
19922 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19923 &xcoff_read_only_section_name);
19925 private_data_section
19926 = get_unnamed_section (SECTION_WRITE,
19927 rs6000_xcoff_output_readwrite_section_asm_op,
19928 &xcoff_private_data_section_name);
19930 read_only_private_data_section
19931 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19932 &xcoff_private_data_section_name);
19935 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
19937 readonly_data_section = read_only_data_section;
19938 exception_section = data_section;
19942 rs6000_xcoff_reloc_rw_mask (void)
19948 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
19949 tree decl ATTRIBUTE_UNUSED)
19952 static const char * const suffix[3] = { "PR", "RO", "RW" };
19954 if (flags & SECTION_CODE)
19956 else if (flags & SECTION_WRITE)
19961 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
19962 (flags & SECTION_CODE) ? "." : "",
19963 name, suffix[smclass], flags & SECTION_ENTSIZE);
19967 rs6000_xcoff_select_section (tree decl, int reloc,
19968 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19970 if (decl_readonly_section (decl, reloc))
19972 if (TREE_PUBLIC (decl))
19973 return read_only_data_section;
19975 return read_only_private_data_section;
19979 if (TREE_PUBLIC (decl))
19980 return data_section;
19982 return private_data_section;
19987 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
19991 /* Use select_section for private and uninitialized data. */
19992 if (!TREE_PUBLIC (decl)
19993 || DECL_COMMON (decl)
19994 || DECL_INITIAL (decl) == NULL_TREE
19995 || DECL_INITIAL (decl) == error_mark_node
19996 || (flag_zero_initialized_in_bss
19997 && initializer_zerop (DECL_INITIAL (decl))))
20000 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
20001 name = (*targetm.strip_name_encoding) (name);
20002 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
20005 /* Select section for constant in constant pool.
20007 On RS/6000, all constants are in the private read-only data area.
20008 However, if this is being placed in the TOC it must be output as a
20012 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
20013 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
20015 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
20016 return toc_section;
20018 return read_only_private_data_section;
20021 /* Remove any trailing [DS] or the like from the symbol name. */
20023 static const char *
20024 rs6000_xcoff_strip_name_encoding (const char *name)
20029 len = strlen (name);
20030 if (name[len - 1] == ']')
20031 return ggc_alloc_string (name, len - 4);
20036 /* Section attributes. AIX is always PIC. */
20038 static unsigned int
20039 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
20041 unsigned int align;
20042 unsigned int flags = default_section_type_flags (decl, name, reloc);
20044 /* Align to at least UNIT size. */
20045 if (flags & SECTION_CODE)
20046 align = MIN_UNITS_PER_WORD;
20048 /* Increase alignment of large objects if not already stricter. */
20049 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
20050 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
20051 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
20053 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
20056 /* Output at beginning of assembler file.
20058 Initialize the section names for the RS/6000 at this point.
20060 Specify filename, including full path, to assembler.
20062 We want to go into the TOC section so at least one .toc will be emitted.
20063 Also, in order to output proper .bs/.es pairs, we need at least one static
20064 [RW] section emitted.
20066 Finally, declare mcount when profiling to make the assembler happy. */
20069 rs6000_xcoff_file_start (void)
20071 rs6000_gen_section_name (&xcoff_bss_section_name,
20072 main_input_filename, ".bss_");
20073 rs6000_gen_section_name (&xcoff_private_data_section_name,
20074 main_input_filename, ".rw_");
20075 rs6000_gen_section_name (&xcoff_read_only_section_name,
20076 main_input_filename, ".ro_");
20078 fputs ("\t.file\t", asm_out_file);
20079 output_quoted_string (asm_out_file, main_input_filename);
20080 fputc ('\n', asm_out_file);
20081 if (write_symbols != NO_DEBUG)
20082 switch_to_section (private_data_section);
20083 switch_to_section (text_section);
20085 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
20086 rs6000_file_start ();
20089 /* Output at end of assembler file.
20090 On the RS/6000, referencing data should automatically pull in text. */
20093 rs6000_xcoff_file_end (void)
20095 switch_to_section (text_section);
20096 fputs ("_section_.text:\n", asm_out_file);
20097 switch_to_section (data_section);
20098 fputs (TARGET_32BIT
20099 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
20102 #endif /* TARGET_XCOFF */
20104 /* Compute a (partial) cost for rtx X. Return true if the complete
20105 cost has been computed, and false if subexpressions should be
20106 scanned. In either case, *TOTAL contains the cost result. */
20109 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
20111 enum machine_mode mode = GET_MODE (x);
20115 /* On the RS/6000, if it is valid in the insn, it is free. */
20117 if (((outer_code == SET
20118 || outer_code == PLUS
20119 || outer_code == MINUS)
20120 && (satisfies_constraint_I (x)
20121 || satisfies_constraint_L (x)))
20122 || (outer_code == AND
20123 && (satisfies_constraint_K (x)
20125 ? satisfies_constraint_L (x)
20126 : satisfies_constraint_J (x))
20127 || mask_operand (x, mode)
20129 && mask64_operand (x, DImode))))
20130 || ((outer_code == IOR || outer_code == XOR)
20131 && (satisfies_constraint_K (x)
20133 ? satisfies_constraint_L (x)
20134 : satisfies_constraint_J (x))))
20135 || outer_code == ASHIFT
20136 || outer_code == ASHIFTRT
20137 || outer_code == LSHIFTRT
20138 || outer_code == ROTATE
20139 || outer_code == ROTATERT
20140 || outer_code == ZERO_EXTRACT
20141 || (outer_code == MULT
20142 && satisfies_constraint_I (x))
20143 || ((outer_code == DIV || outer_code == UDIV
20144 || outer_code == MOD || outer_code == UMOD)
20145 && exact_log2 (INTVAL (x)) >= 0)
20146 || (outer_code == COMPARE
20147 && (satisfies_constraint_I (x)
20148 || satisfies_constraint_K (x)))
20149 || (outer_code == EQ
20150 && (satisfies_constraint_I (x)
20151 || satisfies_constraint_K (x)
20153 ? satisfies_constraint_L (x)
20154 : satisfies_constraint_J (x))))
20155 || (outer_code == GTU
20156 && satisfies_constraint_I (x))
20157 || (outer_code == LTU
20158 && satisfies_constraint_P (x)))
20163 else if ((outer_code == PLUS
20164 && reg_or_add_cint_operand (x, VOIDmode))
20165 || (outer_code == MINUS
20166 && reg_or_sub_cint_operand (x, VOIDmode))
20167 || ((outer_code == SET
20168 || outer_code == IOR
20169 || outer_code == XOR)
20171 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
20173 *total = COSTS_N_INSNS (1);
20179 if (mode == DImode && code == CONST_DOUBLE)
20181 if ((outer_code == IOR || outer_code == XOR)
20182 && CONST_DOUBLE_HIGH (x) == 0
20183 && (CONST_DOUBLE_LOW (x)
20184 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
20189 else if ((outer_code == AND && and64_2_operand (x, DImode))
20190 || ((outer_code == SET
20191 || outer_code == IOR
20192 || outer_code == XOR)
20193 && CONST_DOUBLE_HIGH (x) == 0))
20195 *total = COSTS_N_INSNS (1);
20205 /* When optimizing for size, MEM should be slightly more expensive
20206 than generating address, e.g., (plus (reg) (const)).
20207 L1 cache latency is about two instructions. */
20208 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
20216 if (mode == DFmode)
20218 if (GET_CODE (XEXP (x, 0)) == MULT)
20220 /* FNMA accounted in outer NEG. */
20221 if (outer_code == NEG)
20222 *total = rs6000_cost->dmul - rs6000_cost->fp;
20224 *total = rs6000_cost->dmul;
20227 *total = rs6000_cost->fp;
20229 else if (mode == SFmode)
20231 /* FNMA accounted in outer NEG. */
20232 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20235 *total = rs6000_cost->fp;
20238 *total = COSTS_N_INSNS (1);
20242 if (mode == DFmode)
20244 if (GET_CODE (XEXP (x, 0)) == MULT
20245 || GET_CODE (XEXP (x, 1)) == MULT)
20247 /* FNMA accounted in outer NEG. */
20248 if (outer_code == NEG)
20249 *total = rs6000_cost->dmul - rs6000_cost->fp;
20251 *total = rs6000_cost->dmul;
20254 *total = rs6000_cost->fp;
20256 else if (mode == SFmode)
20258 /* FNMA accounted in outer NEG. */
20259 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20262 *total = rs6000_cost->fp;
20265 *total = COSTS_N_INSNS (1);
20269 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20270 && satisfies_constraint_I (XEXP (x, 1)))
20272 if (INTVAL (XEXP (x, 1)) >= -256
20273 && INTVAL (XEXP (x, 1)) <= 255)
20274 *total = rs6000_cost->mulsi_const9;
20276 *total = rs6000_cost->mulsi_const;
20278 /* FMA accounted in outer PLUS/MINUS. */
20279 else if ((mode == DFmode || mode == SFmode)
20280 && (outer_code == PLUS || outer_code == MINUS))
20282 else if (mode == DFmode)
20283 *total = rs6000_cost->dmul;
20284 else if (mode == SFmode)
20285 *total = rs6000_cost->fp;
20286 else if (mode == DImode)
20287 *total = rs6000_cost->muldi;
20289 *total = rs6000_cost->mulsi;
20294 if (FLOAT_MODE_P (mode))
20296 *total = mode == DFmode ? rs6000_cost->ddiv
20297 : rs6000_cost->sdiv;
20304 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20305 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
20307 if (code == DIV || code == MOD)
20309 *total = COSTS_N_INSNS (2);
20312 *total = COSTS_N_INSNS (1);
20316 if (GET_MODE (XEXP (x, 1)) == DImode)
20317 *total = rs6000_cost->divdi;
20319 *total = rs6000_cost->divsi;
20321 /* Add in shift and subtract for MOD. */
20322 if (code == MOD || code == UMOD)
20323 *total += COSTS_N_INSNS (2);
20328 *total = COSTS_N_INSNS (4);
20332 *total = COSTS_N_INSNS (6);
20336 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
20348 *total = COSTS_N_INSNS (1);
20356 /* Handle mul_highpart. */
20357 if (outer_code == TRUNCATE
20358 && GET_CODE (XEXP (x, 0)) == MULT)
20360 if (mode == DImode)
20361 *total = rs6000_cost->muldi;
20363 *total = rs6000_cost->mulsi;
20366 else if (outer_code == AND)
20369 *total = COSTS_N_INSNS (1);
20374 if (GET_CODE (XEXP (x, 0)) == MEM)
20377 *total = COSTS_N_INSNS (1);
20383 if (!FLOAT_MODE_P (mode))
20385 *total = COSTS_N_INSNS (1);
20391 case UNSIGNED_FLOAT:
20394 case FLOAT_TRUNCATE:
20395 *total = rs6000_cost->fp;
20399 if (mode == DFmode)
20402 *total = rs6000_cost->fp;
20406 switch (XINT (x, 1))
20409 *total = rs6000_cost->fp;
20421 *total = COSTS_N_INSNS (1);
20424 else if (FLOAT_MODE_P (mode)
20425 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
20427 *total = rs6000_cost->fp;
20435 /* Carry bit requires mode == Pmode.
20436 NEG or PLUS already counted so only add one. */
20438 && (outer_code == NEG || outer_code == PLUS))
20440 *total = COSTS_N_INSNS (1);
20443 if (outer_code == SET)
20445 if (XEXP (x, 1) == const0_rtx)
20447 *total = COSTS_N_INSNS (2);
20450 else if (mode == Pmode)
20452 *total = COSTS_N_INSNS (3);
20461 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
20463 *total = COSTS_N_INSNS (2);
20467 if (outer_code == COMPARE)
20481 /* A C expression returning the cost of moving data from a register of class
20482 CLASS1 to one of CLASS2. */
20485 rs6000_register_move_cost (enum machine_mode mode,
20486 enum reg_class from, enum reg_class to)
20488 /* Moves from/to GENERAL_REGS. */
20489 if (reg_classes_intersect_p (to, GENERAL_REGS)
20490 || reg_classes_intersect_p (from, GENERAL_REGS))
20492 if (! reg_classes_intersect_p (to, GENERAL_REGS))
20495 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
20496 return (rs6000_memory_move_cost (mode, from, 0)
20497 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
20499 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20501 else if (from == CR_REGS)
20505 /* A move will cost one instruction per GPR moved. */
20506 return 2 * hard_regno_nregs[0][mode];
20509 /* Moving between two similar registers is just one instruction. */
20510 else if (reg_classes_intersect_p (to, from))
20511 return (mode == TFmode || mode == TDmode) ? 4 : 2;
20513 /* Everything else has to go through GENERAL_REGS. */
20515 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
20516 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
20519 /* A C expressions returning the cost of moving data of MODE from a register to
20523 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20524 int in ATTRIBUTE_UNUSED)
20526 if (reg_classes_intersect_p (class, GENERAL_REGS))
20527 return 4 * hard_regno_nregs[0][mode];
20528 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20529 return 4 * hard_regno_nregs[32][mode];
20530 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20531 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20533 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20536 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20537 Assumes no trapping math and finite arguments. */
20540 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
20542 rtx x0, e0, e1, y1, u0, v0, one;
20544 x0 = gen_reg_rtx (SFmode);
20545 e0 = gen_reg_rtx (SFmode);
20546 e1 = gen_reg_rtx (SFmode);
20547 y1 = gen_reg_rtx (SFmode);
20548 u0 = gen_reg_rtx (SFmode);
20549 v0 = gen_reg_rtx (SFmode);
20550 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
20552 /* x0 = 1./d estimate */
20553 emit_insn (gen_rtx_SET (VOIDmode, x0,
20554 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
20556 /* e0 = 1. - d * x0 */
20557 emit_insn (gen_rtx_SET (VOIDmode, e0,
20558 gen_rtx_MINUS (SFmode, one,
20559 gen_rtx_MULT (SFmode, d, x0))));
20560 /* e1 = e0 + e0 * e0 */
20561 emit_insn (gen_rtx_SET (VOIDmode, e1,
20562 gen_rtx_PLUS (SFmode,
20563 gen_rtx_MULT (SFmode, e0, e0), e0)));
20564 /* y1 = x0 + e1 * x0 */
20565 emit_insn (gen_rtx_SET (VOIDmode, y1,
20566 gen_rtx_PLUS (SFmode,
20567 gen_rtx_MULT (SFmode, e1, x0), x0)));
20569 emit_insn (gen_rtx_SET (VOIDmode, u0,
20570 gen_rtx_MULT (SFmode, n, y1)));
20571 /* v0 = n - d * u0 */
20572 emit_insn (gen_rtx_SET (VOIDmode, v0,
20573 gen_rtx_MINUS (SFmode, n,
20574 gen_rtx_MULT (SFmode, d, u0))));
20575 /* res = u0 + v0 * y1 */
20576 emit_insn (gen_rtx_SET (VOIDmode, res,
20577 gen_rtx_PLUS (SFmode,
20578 gen_rtx_MULT (SFmode, v0, y1), u0)));
20581 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20582 Assumes no trapping math and finite arguments. */
20585 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
20587 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
20589 x0 = gen_reg_rtx (DFmode);
20590 e0 = gen_reg_rtx (DFmode);
20591 e1 = gen_reg_rtx (DFmode);
20592 e2 = gen_reg_rtx (DFmode);
20593 y1 = gen_reg_rtx (DFmode);
20594 y2 = gen_reg_rtx (DFmode);
20595 y3 = gen_reg_rtx (DFmode);
20596 u0 = gen_reg_rtx (DFmode);
20597 v0 = gen_reg_rtx (DFmode);
20598 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
20600 /* x0 = 1./d estimate */
20601 emit_insn (gen_rtx_SET (VOIDmode, x0,
20602 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
20604 /* e0 = 1. - d * x0 */
20605 emit_insn (gen_rtx_SET (VOIDmode, e0,
20606 gen_rtx_MINUS (DFmode, one,
20607 gen_rtx_MULT (SFmode, d, x0))));
20608 /* y1 = x0 + e0 * x0 */
20609 emit_insn (gen_rtx_SET (VOIDmode, y1,
20610 gen_rtx_PLUS (DFmode,
20611 gen_rtx_MULT (DFmode, e0, x0), x0)));
20613 emit_insn (gen_rtx_SET (VOIDmode, e1,
20614 gen_rtx_MULT (DFmode, e0, e0)));
20615 /* y2 = y1 + e1 * y1 */
20616 emit_insn (gen_rtx_SET (VOIDmode, y2,
20617 gen_rtx_PLUS (DFmode,
20618 gen_rtx_MULT (DFmode, e1, y1), y1)));
20620 emit_insn (gen_rtx_SET (VOIDmode, e2,
20621 gen_rtx_MULT (DFmode, e1, e1)));
20622 /* y3 = y2 + e2 * y2 */
20623 emit_insn (gen_rtx_SET (VOIDmode, y3,
20624 gen_rtx_PLUS (DFmode,
20625 gen_rtx_MULT (DFmode, e2, y2), y2)));
20627 emit_insn (gen_rtx_SET (VOIDmode, u0,
20628 gen_rtx_MULT (DFmode, n, y3)));
20629 /* v0 = n - d * u0 */
20630 emit_insn (gen_rtx_SET (VOIDmode, v0,
20631 gen_rtx_MINUS (DFmode, n,
20632 gen_rtx_MULT (DFmode, d, u0))));
20633 /* res = u0 + v0 * y3 */
20634 emit_insn (gen_rtx_SET (VOIDmode, res,
20635 gen_rtx_PLUS (DFmode,
20636 gen_rtx_MULT (DFmode, v0, y3), u0)));
20640 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
20641 target, and SRC is the argument operand. */
20644 rs6000_emit_popcount (rtx dst, rtx src)
20646 enum machine_mode mode = GET_MODE (dst);
20649 tmp1 = gen_reg_rtx (mode);
20651 if (mode == SImode)
20653 emit_insn (gen_popcntbsi2 (tmp1, src));
20654 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
20656 tmp2 = force_reg (SImode, tmp2);
20657 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
20661 emit_insn (gen_popcntbdi2 (tmp1, src));
20662 tmp2 = expand_mult (DImode, tmp1,
20663 GEN_INT ((HOST_WIDE_INT)
20664 0x01010101 << 32 | 0x01010101),
20666 tmp2 = force_reg (DImode, tmp2);
20667 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
20672 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
20673 target, and SRC is the argument operand. */
20676 rs6000_emit_parity (rtx dst, rtx src)
20678 enum machine_mode mode = GET_MODE (dst);
20681 tmp = gen_reg_rtx (mode);
20682 if (mode == SImode)
20684 /* Is mult+shift >= shift+xor+shift+xor? */
20685 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
20687 rtx tmp1, tmp2, tmp3, tmp4;
20689 tmp1 = gen_reg_rtx (SImode);
20690 emit_insn (gen_popcntbsi2 (tmp1, src));
20692 tmp2 = gen_reg_rtx (SImode);
20693 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
20694 tmp3 = gen_reg_rtx (SImode);
20695 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
20697 tmp4 = gen_reg_rtx (SImode);
20698 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
20699 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
20702 rs6000_emit_popcount (tmp, src);
20703 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
20707 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
20708 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
20710 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
20712 tmp1 = gen_reg_rtx (DImode);
20713 emit_insn (gen_popcntbdi2 (tmp1, src));
20715 tmp2 = gen_reg_rtx (DImode);
20716 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
20717 tmp3 = gen_reg_rtx (DImode);
20718 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
20720 tmp4 = gen_reg_rtx (DImode);
20721 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
20722 tmp5 = gen_reg_rtx (DImode);
20723 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
20725 tmp6 = gen_reg_rtx (DImode);
20726 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
20727 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
20730 rs6000_emit_popcount (tmp, src);
20731 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
20735 /* Return an RTX representing where to find the function value of a
20736 function returning MODE. */
20738 rs6000_complex_function_value (enum machine_mode mode)
20740 unsigned int regno;
20742 enum machine_mode inner = GET_MODE_INNER (mode);
20743 unsigned int inner_bytes = GET_MODE_SIZE (inner);
20745 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
20746 regno = FP_ARG_RETURN;
20749 regno = GP_ARG_RETURN;
20751 /* 32-bit is OK since it'll go in r3/r4. */
20752 if (TARGET_32BIT && inner_bytes >= 4)
20753 return gen_rtx_REG (mode, regno);
20756 if (inner_bytes >= 8)
20757 return gen_rtx_REG (mode, regno);
20759 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
20761 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
20762 GEN_INT (inner_bytes));
20763 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
20766 /* Define how to find the value returned by a function.
20767 VALTYPE is the data type of the value (as a tree).
20768 If the precise function being called is known, FUNC is its FUNCTION_DECL;
20769 otherwise, FUNC is 0.
20771 On the SPE, both FPs and vectors are returned in r3.
20773 On RS/6000 an integer value is in r3 and a floating-point value is in
20774 fp1, unless -msoft-float. */
20777 rs6000_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
20779 enum machine_mode mode;
20780 unsigned int regno;
20782 /* Special handling for structs in darwin64. */
20783 if (rs6000_darwin64_abi
20784 && TYPE_MODE (valtype) == BLKmode
20785 && TREE_CODE (valtype) == RECORD_TYPE
20786 && int_size_in_bytes (valtype) > 0)
20788 CUMULATIVE_ARGS valcum;
20792 valcum.fregno = FP_ARG_MIN_REG;
20793 valcum.vregno = ALTIVEC_ARG_MIN_REG;
20794 /* Do a trial code generation as if this were going to be passed as
20795 an argument; if any part goes in memory, we return NULL. */
20796 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
20799 /* Otherwise fall through to standard ABI rules. */
20802 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
20804 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20805 return gen_rtx_PARALLEL (DImode,
20807 gen_rtx_EXPR_LIST (VOIDmode,
20808 gen_rtx_REG (SImode, GP_ARG_RETURN),
20810 gen_rtx_EXPR_LIST (VOIDmode,
20811 gen_rtx_REG (SImode,
20812 GP_ARG_RETURN + 1),
20815 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
20817 return gen_rtx_PARALLEL (DCmode,
20819 gen_rtx_EXPR_LIST (VOIDmode,
20820 gen_rtx_REG (SImode, GP_ARG_RETURN),
20822 gen_rtx_EXPR_LIST (VOIDmode,
20823 gen_rtx_REG (SImode,
20824 GP_ARG_RETURN + 1),
20826 gen_rtx_EXPR_LIST (VOIDmode,
20827 gen_rtx_REG (SImode,
20828 GP_ARG_RETURN + 2),
20830 gen_rtx_EXPR_LIST (VOIDmode,
20831 gen_rtx_REG (SImode,
20832 GP_ARG_RETURN + 3),
20836 mode = TYPE_MODE (valtype);
20837 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
20838 || POINTER_TYPE_P (valtype))
20839 mode = TARGET_32BIT ? SImode : DImode;
20841 if (DECIMAL_FLOAT_MODE_P (mode))
20843 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20848 gcc_unreachable ();
20850 regno = GP_ARG_RETURN;
20853 regno = FP_ARG_RETURN;
20856 /* Use f2:f3 specified by the ABI. */
20857 regno = FP_ARG_RETURN + 1;
20862 regno = GP_ARG_RETURN;
20864 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
20865 regno = FP_ARG_RETURN;
20866 else if (TREE_CODE (valtype) == COMPLEX_TYPE
20867 && targetm.calls.split_complex_arg)
20868 return rs6000_complex_function_value (mode);
20869 else if (TREE_CODE (valtype) == VECTOR_TYPE
20870 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
20871 && ALTIVEC_VECTOR_MODE (mode))
20872 regno = ALTIVEC_ARG_RETURN;
20873 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20874 && (mode == DFmode || mode == DCmode
20875 || mode == TFmode || mode == TCmode))
20876 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20878 regno = GP_ARG_RETURN;
20880 return gen_rtx_REG (mode, regno);
20883 /* Define how to find the value returned by a library function
20884 assuming the value has mode MODE. */
20886 rs6000_libcall_value (enum machine_mode mode)
20888 unsigned int regno;
20890 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
20892 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20893 return gen_rtx_PARALLEL (DImode,
20895 gen_rtx_EXPR_LIST (VOIDmode,
20896 gen_rtx_REG (SImode, GP_ARG_RETURN),
20898 gen_rtx_EXPR_LIST (VOIDmode,
20899 gen_rtx_REG (SImode,
20900 GP_ARG_RETURN + 1),
20904 if (DECIMAL_FLOAT_MODE_P (mode))
20906 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20911 gcc_unreachable ();
20913 regno = GP_ARG_RETURN;
20916 regno = FP_ARG_RETURN;
20919 /* Use f2:f3 specified by the ABI. */
20920 regno = FP_ARG_RETURN + 1;
20925 regno = GP_ARG_RETURN;
20927 else if (SCALAR_FLOAT_MODE_P (mode)
20928 && TARGET_HARD_FLOAT && TARGET_FPRS)
20929 regno = FP_ARG_RETURN;
20930 else if (ALTIVEC_VECTOR_MODE (mode)
20931 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
20932 regno = ALTIVEC_ARG_RETURN;
20933 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
20934 return rs6000_complex_function_value (mode);
20935 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20936 && (mode == DFmode || mode == DCmode
20937 || mode == TFmode || mode == TCmode))
20938 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20940 regno = GP_ARG_RETURN;
20942 return gen_rtx_REG (mode, regno);
20945 /* Define the offset between two registers, FROM to be eliminated and its
20946 replacement TO, at the start of a routine. */
20948 rs6000_initial_elimination_offset (int from, int to)
20950 rs6000_stack_t *info = rs6000_stack_info ();
20951 HOST_WIDE_INT offset;
20953 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20954 offset = info->push_p ? 0 : -info->total_size;
20955 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20957 offset = info->push_p ? 0 : -info->total_size;
20958 if (FRAME_GROWS_DOWNWARD)
20959 offset += info->fixed_size + info->vars_size + info->parm_size;
20961 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20962 offset = FRAME_GROWS_DOWNWARD
20963 ? info->fixed_size + info->vars_size + info->parm_size
20965 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20966 offset = info->total_size;
20967 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20968 offset = info->push_p ? info->total_size : 0;
20969 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
20972 gcc_unreachable ();
20977 /* Return true if TYPE is a SPE or AltiVec opaque type. */
20980 rs6000_is_opaque_type (const_tree type)
20982 return (type == opaque_V2SI_type_node
20983 || type == opaque_V2SF_type_node
20984 || type == opaque_p_V2SI_type_node
20985 || type == opaque_V4SI_type_node);
20989 rs6000_dwarf_register_span (rtx reg)
20994 && (SPE_VECTOR_MODE (GET_MODE (reg))
20995 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
21000 regno = REGNO (reg);
21002 /* The duality of the SPE register size wreaks all kinds of havoc.
21003 This is a way of distinguishing r0 in 32-bits from r0 in
21006 gen_rtx_PARALLEL (VOIDmode,
21009 gen_rtx_REG (SImode, regno + 1200),
21010 gen_rtx_REG (SImode, regno))
21012 gen_rtx_REG (SImode, regno),
21013 gen_rtx_REG (SImode, regno + 1200)));
21016 /* Fill in sizes for SPE register high parts in table used by unwinder. */
21019 rs6000_init_dwarf_reg_sizes_extra (tree address)
21024 enum machine_mode mode = TYPE_MODE (char_type_node);
21025 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
21026 rtx mem = gen_rtx_MEM (BLKmode, addr);
21027 rtx value = gen_int_mode (4, mode);
21029 for (i = 1201; i < 1232; i++)
21031 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
21032 HOST_WIDE_INT offset
21033 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
21035 emit_move_insn (adjust_address (mem, mode, offset), value);
21040 /* Map internal gcc register numbers to DWARF2 register numbers. */
21043 rs6000_dbx_register_number (unsigned int regno)
21045 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
21047 if (regno == MQ_REGNO)
21049 if (regno == LR_REGNO)
21051 if (regno == CTR_REGNO)
21053 if (CR_REGNO_P (regno))
21054 return regno - CR0_REGNO + 86;
21055 if (regno == XER_REGNO)
21057 if (ALTIVEC_REGNO_P (regno))
21058 return regno - FIRST_ALTIVEC_REGNO + 1124;
21059 if (regno == VRSAVE_REGNO)
21061 if (regno == VSCR_REGNO)
21063 if (regno == SPE_ACC_REGNO)
21065 if (regno == SPEFSCR_REGNO)
21067 /* SPE high reg number. We get these values of regno from
21068 rs6000_dwarf_register_span. */
21069 gcc_assert (regno >= 1200 && regno < 1232);
21073 /* target hook eh_return_filter_mode */
21074 static enum machine_mode
21075 rs6000_eh_return_filter_mode (void)
21077 return TARGET_32BIT ? SImode : word_mode;
21080 /* Target hook for scalar_mode_supported_p. */
21082 rs6000_scalar_mode_supported_p (enum machine_mode mode)
21084 if (DECIMAL_FLOAT_MODE_P (mode))
21087 return default_scalar_mode_supported_p (mode);
21090 /* Target hook for vector_mode_supported_p. */
21092 rs6000_vector_mode_supported_p (enum machine_mode mode)
21095 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
21098 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
21105 /* Target hook for invalid_arg_for_unprototyped_fn. */
21106 static const char *
21107 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
21109 return (!rs6000_darwin64_abi
21111 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
21112 && (funcdecl == NULL_TREE
21113 || (TREE_CODE (funcdecl) == FUNCTION_DECL
21114 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
21115 ? N_("AltiVec argument passed to unprototyped function")
21119 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
21120 setup by using __stack_chk_fail_local hidden function instead of
21121 calling __stack_chk_fail directly. Otherwise it is better to call
21122 __stack_chk_fail directly. */
21125 rs6000_stack_protect_fail (void)
21127 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
21128 ? default_hidden_stack_protect_fail ()
21129 : default_external_stack_protect_fail ();
21132 #include "gt-rs6000.h"