1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (and (match_operand 0 "register_operand")
37 (match_test "GET_CODE (op) != REG
38 || ALTIVEC_REGNO_P (REGNO (op))
39 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
41 ;; Return 1 if op is a VSX register.
42 (define_predicate "vsx_register_operand"
43 (and (match_operand 0 "register_operand")
44 (match_test "GET_CODE (op) != REG
45 || VSX_REGNO_P (REGNO (op))
46 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
48 ;; Return 1 if op is a vector register that operates on floating point vectors
49 ;; (either altivec or VSX).
50 (define_predicate "vfloat_operand"
51 (and (match_operand 0 "register_operand")
52 (match_test "GET_CODE (op) != REG
53 || VFLOAT_REGNO_P (REGNO (op))
54 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
56 ;; Return 1 if op is a vector register that operates on integer vectors
57 ;; (only altivec, VSX doesn't support integer vectors)
58 (define_predicate "vint_operand"
59 (and (match_operand 0 "register_operand")
60 (match_test "GET_CODE (op) != REG
61 || VINT_REGNO_P (REGNO (op))
62 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
64 ;; Return 1 if op is a vector register to do logical operations on (and, or,
66 (define_predicate "vlogical_operand"
67 (and (match_operand 0 "register_operand")
68 (match_test "GET_CODE (op) != REG
69 || VLOGICAL_REGNO_P (REGNO (op))
70 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
72 ;; Return 1 if op is XER register.
73 (define_predicate "xer_operand"
74 (and (match_code "reg")
75 (match_test "XER_REGNO_P (REGNO (op))")))
77 ;; Return 1 if op is a signed 5-bit constant integer.
78 (define_predicate "s5bit_cint_operand"
79 (and (match_code "const_int")
80 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
82 ;; Return 1 if op is a unsigned 5-bit constant integer.
83 (define_predicate "u5bit_cint_operand"
84 (and (match_code "const_int")
85 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
87 ;; Return 1 if op is a signed 8-bit constant integer.
88 ;; Integer multiplication complete more quickly
89 (define_predicate "s8bit_cint_operand"
90 (and (match_code "const_int")
91 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
93 ;; Return 1 if op is a constant integer that can fit in a D field.
94 (define_predicate "short_cint_operand"
95 (and (match_code "const_int")
96 (match_test "satisfies_constraint_I (op)")))
98 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
99 (define_predicate "u_short_cint_operand"
100 (and (match_code "const_int")
101 (match_test "satisfies_constraint_K (op)")))
103 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
104 (define_predicate "non_short_cint_operand"
105 (and (match_code "const_int")
106 (match_test "(unsigned HOST_WIDE_INT)
107 (INTVAL (op) + 0x8000) >= 0x10000")))
109 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
110 (define_predicate "exact_log2_cint_operand"
111 (and (match_code "const_int")
112 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
114 ;; Return 1 if op is a register that is not special.
115 (define_predicate "gpc_reg_operand"
116 (and (match_operand 0 "register_operand")
117 (match_test "(GET_CODE (op) != REG
118 || (REGNO (op) >= ARG_POINTER_REGNUM
119 && !XER_REGNO_P (REGNO (op)))
120 || REGNO (op) < MQ_REGNO)
121 && !((TARGET_E500_DOUBLE || TARGET_SPE)
122 && invalid_e500_subreg (op, mode))")))
124 ;; Return 1 if op is a register that is a condition register field.
125 (define_predicate "cc_reg_operand"
126 (and (match_operand 0 "register_operand")
127 (match_test "GET_CODE (op) != REG
128 || REGNO (op) > LAST_VIRTUAL_REGISTER
129 || CR_REGNO_P (REGNO (op))")))
131 ;; Return 1 if op is a register that is a condition register field not cr0.
132 (define_predicate "cc_reg_not_cr0_operand"
133 (and (match_operand 0 "register_operand")
134 (match_test "GET_CODE (op) != REG
135 || REGNO (op) > LAST_VIRTUAL_REGISTER
136 || CR_REGNO_NOT_CR0_P (REGNO (op))")))
138 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
139 (define_predicate "cc_reg_not_micro_cr0_operand"
140 (and (match_operand 0 "register_operand")
141 (match_test "GET_CODE (op) != REG
142 || REGNO (op) > LAST_VIRTUAL_REGISTER
143 || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op)))
144 || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))")))
146 ;; Return 1 if op is a constant integer valid for D field
147 ;; or non-special register register.
148 (define_predicate "reg_or_short_operand"
149 (if_then_else (match_code "const_int")
150 (match_operand 0 "short_cint_operand")
151 (match_operand 0 "gpc_reg_operand")))
153 ;; Return 1 if op is a constant integer valid whose negation is valid for
154 ;; D field or non-special register register.
155 ;; Do not allow a constant zero because all patterns that call this
156 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
157 ;; or equal to const, which does not work for zero.
158 (define_predicate "reg_or_neg_short_operand"
159 (if_then_else (match_code "const_int")
160 (match_test "satisfies_constraint_P (op)
161 && INTVAL (op) != 0")
162 (match_operand 0 "gpc_reg_operand")))
164 ;; Return 1 if op is a constant integer valid for DS field
165 ;; or non-special register.
166 (define_predicate "reg_or_aligned_short_operand"
167 (if_then_else (match_code "const_int")
168 (and (match_operand 0 "short_cint_operand")
169 (match_test "!(INTVAL (op) & 3)"))
170 (match_operand 0 "gpc_reg_operand")))
172 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
173 ;; or non-special register.
174 (define_predicate "reg_or_u_short_operand"
175 (if_then_else (match_code "const_int")
176 (match_operand 0 "u_short_cint_operand")
177 (match_operand 0 "gpc_reg_operand")))
179 ;; Return 1 if op is any constant integer
180 ;; or non-special register.
181 (define_predicate "reg_or_cint_operand"
182 (ior (match_code "const_int")
183 (match_operand 0 "gpc_reg_operand")))
185 ;; Return 1 if op is a constant integer valid for addition
186 ;; or non-special register.
187 (define_predicate "reg_or_add_cint_operand"
188 (if_then_else (match_code "const_int")
189 (match_test "(HOST_BITS_PER_WIDE_INT == 32
190 && (mode == SImode || INTVAL (op) < 0x7fff8000))
191 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
192 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
193 (match_operand 0 "gpc_reg_operand")))
195 ;; Return 1 if op is a constant integer valid for subtraction
196 ;; or non-special register.
197 (define_predicate "reg_or_sub_cint_operand"
198 (if_then_else (match_code "const_int")
199 (match_test "(HOST_BITS_PER_WIDE_INT == 32
200 && (mode == SImode || - INTVAL (op) < 0x7fff8000))
201 || ((unsigned HOST_WIDE_INT) (- INTVAL (op)
203 ? 0x80000000 : 0x80008000))
204 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
205 (match_operand 0 "gpc_reg_operand")))
207 ;; Return 1 if op is any 32-bit unsigned constant integer
208 ;; or non-special register.
209 (define_predicate "reg_or_logical_cint_operand"
210 (if_then_else (match_code "const_int")
211 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
213 || ((INTVAL (op) & GET_MODE_MASK (mode)
214 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
215 (if_then_else (match_code "const_double")
216 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
218 && CONST_DOUBLE_HIGH (op) == 0")
219 (match_operand 0 "gpc_reg_operand"))))
221 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
222 ;; with no more than one instruction per word.
223 (define_predicate "easy_fp_constant"
224 (match_code "const_double")
229 if (GET_MODE (op) != mode
230 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
233 /* Consider all constants with -msoft-float to be easy. */
234 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
235 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
239 if (DECIMAL_FLOAT_MODE_P (mode))
242 /* If we are using V.4 style PIC, consider all constants to be hard. */
243 if (flag_pic && DEFAULT_ABI == ABI_V4)
246 #ifdef TARGET_RELOCATABLE
247 /* Similarly if we are using -mrelocatable, consider all constants
249 if (TARGET_RELOCATABLE)
256 if (TARGET_E500_DOUBLE)
259 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
260 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
262 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
263 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
264 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
265 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
268 /* The constant 0.f is easy under VSX. */
269 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode))
272 /* Force constants to memory before reload to utilize
273 compress_float_constant.
274 Avoid this when flag_unsafe_math_optimizations is enabled
275 because RDIV division to reciprocal optimization is not able
276 to regenerate the division. */
277 if (TARGET_E500_DOUBLE
278 || (!reload_in_progress && !reload_completed
279 && !flag_unsafe_math_optimizations))
282 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
283 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
285 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
286 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
289 /* The constant 0.f is easy. */
290 if (op == CONST0_RTX (SFmode))
293 /* Force constants to memory before reload to utilize
294 compress_float_constant.
295 Avoid this when flag_unsafe_math_optimizations is enabled
296 because RDIV division to reciprocal optimization is not able
297 to regenerate the division. */
298 if (!reload_in_progress && !reload_completed
299 && !flag_unsafe_math_optimizations)
302 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
303 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
305 return num_insns_constant_wide (k[0]) == 1;
308 return ((TARGET_POWERPC64
309 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
310 || (num_insns_constant (op, DImode) <= 2));
320 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
321 ;; vector register without using memory.
322 (define_predicate "easy_vector_constant"
323 (match_code "const_vector")
325 /* As the paired vectors are actually FPRs it seems that there is
326 no easy way to load a CONST_VECTOR without using memory. */
327 if (TARGET_PAIRED_FLOAT)
330 if ((VSX_VECTOR_MODE (mode) || mode == TImode) && zero_constant (op, mode))
333 if (ALTIVEC_VECTOR_MODE (mode))
335 if (zero_constant (op, mode))
337 return easy_altivec_constant (op, mode);
340 if (SPE_VECTOR_MODE (mode))
343 if (zero_constant (op, mode))
345 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
348 /* Limit SPE vectors to 15 bits signed. These we can generate with:
353 I don't know how efficient it would be to allow bigger constants,
354 considering we'll have an extra 'ori' for every 'li'. I doubt 5
355 instructions is better than a 64-bit memory load, but I don't
356 have the e500 timing specs. */
357 if (mode == V2SImode)
359 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
360 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
361 return cst >= -0x7fff && cst <= 0x7fff
362 && cst2 >= -0x7fff && cst2 <= 0x7fff;
369 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
370 (define_predicate "easy_vector_constant_add_self"
371 (and (match_code "const_vector")
372 (and (match_test "TARGET_ALTIVEC")
373 (match_test "easy_altivec_constant (op, mode)")))
375 HOST_WIDE_INT val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
376 val = ((val & 0xff) ^ 0x80) - 0x80;
377 return EASY_VECTOR_15_ADD_SELF (val);
380 ;; Return 1 if operand is constant zero (scalars and vectors).
381 (define_predicate "zero_constant"
382 (and (match_code "const_int,const_double,const_vector")
383 (match_test "op == CONST0_RTX (mode)")))
385 ;; Return 1 if operand is 0.0.
386 ;; or non-special register register field no cr0
387 (define_predicate "zero_fp_constant"
388 (and (match_code "const_double")
389 (match_test "SCALAR_FLOAT_MODE_P (mode)
390 && op == CONST0_RTX (mode)")))
392 ;; Return 1 if the operand is in volatile memory. Note that during the
393 ;; RTL generation phase, memory_operand does not return TRUE for volatile
394 ;; memory references. So this function allows us to recognize volatile
395 ;; references where it's safe.
396 (define_predicate "volatile_mem_operand"
397 (and (and (match_code "mem")
398 (match_test "MEM_VOLATILE_P (op)"))
399 (if_then_else (match_test "reload_completed")
400 (match_operand 0 "memory_operand")
401 (if_then_else (match_test "reload_in_progress")
402 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
403 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
405 ;; Return 1 if the operand is an offsettable memory operand.
406 (define_predicate "offsettable_mem_operand"
407 (and (match_operand 0 "memory_operand")
408 (match_test "offsettable_nonstrict_memref_p (op)")))
410 ;; Return 1 if the operand is a memory operand with an address divisible by 4
411 (define_predicate "word_offset_memref_operand"
412 (match_operand 0 "memory_operand")
414 /* Address inside MEM. */
417 /* Extract address from auto-inc/dec. */
418 if (GET_CODE (op) == PRE_INC
419 || GET_CODE (op) == PRE_DEC)
421 else if (GET_CODE (op) == PRE_MODIFY)
424 return (GET_CODE (op) != PLUS
425 || ! REG_P (XEXP (op, 0))
426 || GET_CODE (XEXP (op, 1)) != CONST_INT
427 || INTVAL (XEXP (op, 1)) % 4 == 0);
430 ;; Return 1 if the operand is an indexed or indirect memory operand.
431 (define_predicate "indexed_or_indirect_operand"
435 if (VECTOR_MEM_ALTIVEC_P (mode)
436 && GET_CODE (op) == AND
437 && GET_CODE (XEXP (op, 1)) == CONST_INT
438 && INTVAL (XEXP (op, 1)) == -16)
441 else if (VECTOR_MEM_VSX_P (mode)
442 && GET_CODE (op) == PRE_MODIFY)
445 return indexed_or_indirect_address (op, mode);
448 ;; Return 1 if the operand is an indexed or indirect memory operand with an
449 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
450 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
451 ;; while VSX uses the full address and traps)
452 (define_predicate "altivec_indexed_or_indirect_operand"
456 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
457 && GET_CODE (op) == AND
458 && GET_CODE (XEXP (op, 1)) == CONST_INT
459 && INTVAL (XEXP (op, 1)) == -16)
460 return indexed_or_indirect_address (XEXP (op, 0), mode);
465 ;; Return 1 if the operand is an indexed or indirect address.
466 (define_special_predicate "indexed_or_indirect_address"
467 (and (match_test "REG_P (op)
468 || (GET_CODE (op) == PLUS
469 /* Omit testing REG_P (XEXP (op, 0)). */
470 && REG_P (XEXP (op, 1)))")
471 (match_operand 0 "address_operand")))
473 ;; Used for the destination of the fix_truncdfsi2 expander.
474 ;; If stfiwx will be used, the result goes to memory; otherwise,
475 ;; we're going to emit a store and a load of a subreg, so the dest is a
477 (define_predicate "fix_trunc_dest_operand"
478 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
479 (match_operand 0 "memory_operand")
480 (match_operand 0 "gpc_reg_operand")))
482 ;; Return 1 if the operand is either a non-special register or can be used
483 ;; as the operand of a `mode' add insn.
484 (define_predicate "add_operand"
485 (if_then_else (match_code "const_int")
486 (match_test "satisfies_constraint_I (op)
487 || satisfies_constraint_L (op)")
488 (match_operand 0 "gpc_reg_operand")))
490 ;; Return 1 if OP is a constant but not a valid add_operand.
491 (define_predicate "non_add_cint_operand"
492 (and (match_code "const_int")
493 (match_test "!satisfies_constraint_I (op)
494 && !satisfies_constraint_L (op)")))
496 ;; Return 1 if the operand is a constant that can be used as the operand
498 (define_predicate "logical_const_operand"
499 (match_code "const_int,const_double")
501 HOST_WIDE_INT opl, oph;
503 if (GET_CODE (op) == CONST_INT)
505 opl = INTVAL (op) & GET_MODE_MASK (mode);
507 if (HOST_BITS_PER_WIDE_INT <= 32
508 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
511 else if (GET_CODE (op) == CONST_DOUBLE)
513 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT);
515 opl = CONST_DOUBLE_LOW (op);
516 oph = CONST_DOUBLE_HIGH (op);
523 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
524 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
527 ;; Return 1 if the operand is a non-special register or a constant that
528 ;; can be used as the operand of an OR or XOR.
529 (define_predicate "logical_operand"
530 (ior (match_operand 0 "gpc_reg_operand")
531 (match_operand 0 "logical_const_operand")))
533 ;; Return 1 if op is a constant that is not a logical operand, but could
534 ;; be split into one.
535 (define_predicate "non_logical_cint_operand"
536 (and (match_code "const_int,const_double")
537 (and (not (match_operand 0 "logical_operand"))
538 (match_operand 0 "reg_or_logical_cint_operand"))))
540 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
541 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
542 ;; transitions). Reject all ones and all zeros, since these should have
543 ;; been optimized away and confuse the making of MB and ME.
544 (define_predicate "mask_operand"
545 (match_code "const_int")
547 HOST_WIDE_INT c, lsb;
551 if (TARGET_POWERPC64)
553 /* Fail if the mask is not 32-bit. */
554 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
557 /* Fail if the mask wraps around because the upper 32-bits of the
558 mask will all be 1s, contrary to GCC's internal view. */
559 if ((c & 0x80000001) == 0x80000001)
563 /* We don't change the number of transitions by inverting,
564 so make sure we start with the LS bit zero. */
568 /* Reject all zeros or all ones. */
572 /* Find the first transition. */
575 /* Invert to look for a second transition. */
578 /* Erase first transition. */
581 /* Find the second transition (if any). */
584 /* Match if all the bits above are 1's (or c is zero). */
588 ;; Return 1 for the PowerPC64 rlwinm corner case.
589 (define_predicate "mask_operand_wrap"
590 (match_code "const_int")
592 HOST_WIDE_INT c, lsb;
596 if ((c & 0x80000001) != 0x80000001)
610 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
611 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
612 ;; transition). Reject all zeros, since zero should have been
613 ;; optimized away and confuses the making of MB and ME.
614 (define_predicate "mask64_operand"
615 (match_code "const_int")
617 HOST_WIDE_INT c, lsb;
621 /* Reject all zeros. */
625 /* We don't change the number of transitions by inverting,
626 so make sure we start with the LS bit zero. */
630 /* Find the first transition. */
633 /* Match if all the bits above are 1's (or c is zero). */
637 ;; Like mask64_operand, but allow up to three transitions. This
638 ;; predicate is used by insn patterns that generate two rldicl or
639 ;; rldicr machine insns.
640 (define_predicate "mask64_2_operand"
641 (match_code "const_int")
643 HOST_WIDE_INT c, lsb;
647 /* Disallow all zeros. */
651 /* We don't change the number of transitions by inverting,
652 so make sure we start with the LS bit zero. */
656 /* Find the first transition. */
659 /* Invert to look for a second transition. */
662 /* Erase first transition. */
665 /* Find the second transition. */
668 /* Invert to look for a third transition. */
671 /* Erase second transition. */
674 /* Find the third transition (if any). */
677 /* Match if all the bits above are 1's (or c is zero). */
681 ;; Like and_operand, but also match constants that can be implemented
682 ;; with two rldicl or rldicr insns.
683 (define_predicate "and64_2_operand"
684 (ior (match_operand 0 "mask64_2_operand")
685 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
686 (match_operand 0 "gpc_reg_operand")
687 (match_operand 0 "logical_operand"))))
689 ;; Return 1 if the operand is either a non-special register or a
690 ;; constant that can be used as the operand of a logical AND.
691 (define_predicate "and_operand"
692 (ior (match_operand 0 "mask_operand")
693 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
694 (match_operand 0 "mask64_operand"))
695 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
696 (match_operand 0 "gpc_reg_operand")
697 (match_operand 0 "logical_operand")))))
699 ;; Return 1 if the operand is either a logical operand or a short cint operand.
700 (define_predicate "scc_eq_operand"
701 (ior (match_operand 0 "logical_operand")
702 (match_operand 0 "short_cint_operand")))
704 ;; Return 1 if the operand is a general non-special register or memory operand.
705 (define_predicate "reg_or_mem_operand"
706 (ior (match_operand 0 "memory_operand")
707 (ior (and (match_code "mem")
708 (match_test "macho_lo_sum_memory_operand (op, mode)"))
709 (ior (match_operand 0 "volatile_mem_operand")
710 (match_operand 0 "gpc_reg_operand")))))
712 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
713 (define_predicate "reg_or_none500mem_operand"
714 (if_then_else (match_code "mem")
715 (and (match_test "!TARGET_E500_DOUBLE")
716 (ior (match_operand 0 "memory_operand")
717 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
718 (match_operand 0 "volatile_mem_operand"))))
719 (match_operand 0 "gpc_reg_operand")))
721 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
722 (define_predicate "zero_reg_mem_operand"
723 (ior (match_operand 0 "zero_fp_constant")
724 (match_operand 0 "reg_or_mem_operand")))
726 ;; Return 1 if the operand is a general register or memory operand without
727 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
729 (define_predicate "lwa_operand"
730 (match_code "reg,subreg,mem")
734 if (reload_completed && GET_CODE (inner) == SUBREG)
735 inner = SUBREG_REG (inner);
737 return gpc_reg_operand (inner, mode)
738 || (memory_operand (inner, mode)
739 && GET_CODE (XEXP (inner, 0)) != PRE_INC
740 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
741 && (GET_CODE (XEXP (inner, 0)) != PRE_MODIFY
742 || legitimate_indexed_address_p (XEXP (XEXP (inner, 0), 1), 0))
743 && (GET_CODE (XEXP (inner, 0)) != PLUS
744 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
745 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
748 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
749 (define_predicate "symbol_ref_operand"
750 (and (match_code "symbol_ref")
751 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
752 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
754 ;; Return 1 if op is an operand that can be loaded via the GOT.
755 ;; or non-special register register field no cr0
756 (define_predicate "got_operand"
757 (match_code "symbol_ref,const,label_ref"))
759 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
760 ;; excluding labels involving addition.
761 (define_predicate "got_no_const_operand"
762 (match_code "symbol_ref,label_ref"))
764 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
765 (define_predicate "rs6000_tls_symbol_ref"
766 (and (match_code "symbol_ref")
767 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
769 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
770 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
771 (define_predicate "call_operand"
772 (if_then_else (match_code "reg")
773 (match_test "REGNO (op) == LR_REGNO
774 || REGNO (op) == CTR_REGNO
775 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
776 (match_code "symbol_ref")))
778 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
780 (define_predicate "current_file_function_operand"
781 (and (match_code "symbol_ref")
782 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
783 && ((SYMBOL_REF_LOCAL_P (op)
784 && (DEFAULT_ABI != ABI_AIX
785 || !SYMBOL_REF_EXTERNAL_P (op)))
786 || (op == XEXP (DECL_RTL (current_function_decl),
789 ;; Return 1 if this operand is a valid input for a move insn.
790 (define_predicate "input_operand"
791 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
792 const_double,const_vector,const_int,plus")
794 /* Memory is always valid. */
795 if (memory_operand (op, mode))
798 /* For floating-point, easy constants are valid. */
799 if (SCALAR_FLOAT_MODE_P (mode)
801 && easy_fp_constant (op, mode))
804 /* Allow any integer constant. */
805 if (GET_MODE_CLASS (mode) == MODE_INT
806 && (GET_CODE (op) == CONST_INT
807 || GET_CODE (op) == CONST_DOUBLE))
810 /* Allow easy vector constants. */
811 if (GET_CODE (op) == CONST_VECTOR
812 && easy_vector_constant (op, mode))
815 /* Do not allow invalid E500 subregs. */
816 if ((TARGET_E500_DOUBLE || TARGET_SPE)
817 && GET_CODE (op) == SUBREG
818 && invalid_e500_subreg (op, mode))
821 /* For floating-point or multi-word mode, the only remaining valid type
823 if (SCALAR_FLOAT_MODE_P (mode)
824 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
825 return register_operand (op, mode);
827 /* The only cases left are integral modes one word or smaller (we
828 do not get called for MODE_CC values). These can be in any
830 if (register_operand (op, mode))
833 /* A SYMBOL_REF referring to the TOC is valid. */
834 if (legitimate_constant_pool_address_p (op))
837 /* A constant pool expression (relative to the TOC) is valid */
838 if (toc_relative_expr_p (op))
841 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
843 if (DEFAULT_ABI == ABI_V4
844 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
845 && small_data_operand (op, Pmode))
851 ;; Return true if OP is an invalid SUBREG operation on the e500.
852 (define_predicate "rs6000_nonimmediate_operand"
853 (match_code "reg,subreg,mem")
855 if ((TARGET_E500_DOUBLE || TARGET_SPE)
856 && GET_CODE (op) == SUBREG
857 && invalid_e500_subreg (op, mode))
860 return nonimmediate_operand (op, mode);
863 ;; Return true if operand is boolean operator.
864 (define_predicate "boolean_operator"
865 (match_code "and,ior,xor"))
867 ;; Return true if operand is OR-form of boolean operator.
868 (define_predicate "boolean_or_operator"
869 (match_code "ior,xor"))
871 ;; Return true if operand is an equality operator.
872 (define_special_predicate "equality_operator"
873 (match_code "eq,ne"))
875 ;; Return true if operand is MIN or MAX operator.
876 (define_predicate "min_max_operator"
877 (match_code "smin,smax,umin,umax"))
879 ;; Return 1 if OP is a comparison operation that is valid for a branch
880 ;; instruction. We check the opcode against the mode of the CC value.
881 ;; validate_condition_mode is an assertion.
882 (define_predicate "branch_comparison_operator"
883 (and (match_operand 0 "comparison_operator")
884 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
885 (match_test "validate_condition_mode (GET_CODE (op),
886 GET_MODE (XEXP (op, 0))),
889 (define_predicate "rs6000_cbranch_operator"
890 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
891 (match_operand 0 "ordered_comparison_operator")
892 (match_operand 0 "comparison_operator")))
894 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
895 ;; it must be a positive comparison.
896 (define_predicate "scc_comparison_operator"
897 (and (match_operand 0 "branch_comparison_operator")
898 (match_code "eq,lt,gt,ltu,gtu,unordered")))
900 ;; Return 1 if OP is a comparison operation that is valid for a branch
901 ;; insn, which is true if the corresponding bit in the CC register is set.
902 (define_predicate "branch_positive_comparison_operator"
903 (and (match_operand 0 "branch_comparison_operator")
904 (match_code "eq,lt,gt,ltu,gtu,unordered")))
906 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
907 (define_predicate "load_multiple_operation"
908 (match_code "parallel")
910 int count = XVECLEN (op, 0);
911 unsigned int dest_regno;
915 /* Perform a quick check so we don't blow up below. */
917 || GET_CODE (XVECEXP (op, 0, 0)) != SET
918 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
919 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
922 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
923 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
925 for (i = 1; i < count; i++)
927 rtx elt = XVECEXP (op, 0, i);
929 if (GET_CODE (elt) != SET
930 || GET_CODE (SET_DEST (elt)) != REG
931 || GET_MODE (SET_DEST (elt)) != SImode
932 || REGNO (SET_DEST (elt)) != dest_regno + i
933 || GET_CODE (SET_SRC (elt)) != MEM
934 || GET_MODE (SET_SRC (elt)) != SImode
935 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
936 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
937 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
938 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
945 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
946 ;; The second vector element is a CLOBBER.
947 (define_predicate "store_multiple_operation"
948 (match_code "parallel")
950 int count = XVECLEN (op, 0) - 1;
951 unsigned int src_regno;
955 /* Perform a quick check so we don't blow up below. */
957 || GET_CODE (XVECEXP (op, 0, 0)) != SET
958 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
959 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
962 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
963 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
965 for (i = 1; i < count; i++)
967 rtx elt = XVECEXP (op, 0, i + 1);
969 if (GET_CODE (elt) != SET
970 || GET_CODE (SET_SRC (elt)) != REG
971 || GET_MODE (SET_SRC (elt)) != SImode
972 || REGNO (SET_SRC (elt)) != src_regno + i
973 || GET_CODE (SET_DEST (elt)) != MEM
974 || GET_MODE (SET_DEST (elt)) != SImode
975 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
976 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
977 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
978 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
985 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
987 (define_predicate "save_world_operation"
988 (match_code "parallel")
993 int count = XVECLEN (op, 0);
999 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1000 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1003 for (i=1; i <= 18; i++)
1005 elt = XVECEXP (op, 0, index++);
1006 if (GET_CODE (elt) != SET
1007 || GET_CODE (SET_DEST (elt)) != MEM
1008 || ! memory_operand (SET_DEST (elt), DFmode)
1009 || GET_CODE (SET_SRC (elt)) != REG
1010 || GET_MODE (SET_SRC (elt)) != DFmode)
1014 for (i=1; i <= 12; i++)
1016 elt = XVECEXP (op, 0, index++);
1017 if (GET_CODE (elt) != SET
1018 || GET_CODE (SET_DEST (elt)) != MEM
1019 || GET_CODE (SET_SRC (elt)) != REG
1020 || GET_MODE (SET_SRC (elt)) != V4SImode)
1024 for (i=1; i <= 19; i++)
1026 elt = XVECEXP (op, 0, index++);
1027 if (GET_CODE (elt) != SET
1028 || GET_CODE (SET_DEST (elt)) != MEM
1029 || ! memory_operand (SET_DEST (elt), Pmode)
1030 || GET_CODE (SET_SRC (elt)) != REG
1031 || GET_MODE (SET_SRC (elt)) != Pmode)
1035 elt = XVECEXP (op, 0, index++);
1036 if (GET_CODE (elt) != SET
1037 || GET_CODE (SET_DEST (elt)) != MEM
1038 || ! memory_operand (SET_DEST (elt), Pmode)
1039 || GET_CODE (SET_SRC (elt)) != REG
1040 || REGNO (SET_SRC (elt)) != CR2_REGNO
1041 || GET_MODE (SET_SRC (elt)) != Pmode)
1044 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1045 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1050 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1052 (define_predicate "restore_world_operation"
1053 (match_code "parallel")
1058 int count = XVECLEN (op, 0);
1064 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1065 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1066 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1067 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1070 elt = XVECEXP (op, 0, index++);
1071 if (GET_CODE (elt) != SET
1072 || GET_CODE (SET_SRC (elt)) != MEM
1073 || ! memory_operand (SET_SRC (elt), Pmode)
1074 || GET_CODE (SET_DEST (elt)) != REG
1075 || REGNO (SET_DEST (elt)) != CR2_REGNO
1076 || GET_MODE (SET_DEST (elt)) != Pmode)
1079 for (i=1; i <= 19; i++)
1081 elt = XVECEXP (op, 0, index++);
1082 if (GET_CODE (elt) != SET
1083 || GET_CODE (SET_SRC (elt)) != MEM
1084 || ! memory_operand (SET_SRC (elt), Pmode)
1085 || GET_CODE (SET_DEST (elt)) != REG
1086 || GET_MODE (SET_DEST (elt)) != Pmode)
1090 for (i=1; i <= 12; i++)
1092 elt = XVECEXP (op, 0, index++);
1093 if (GET_CODE (elt) != SET
1094 || GET_CODE (SET_SRC (elt)) != MEM
1095 || GET_CODE (SET_DEST (elt)) != REG
1096 || GET_MODE (SET_DEST (elt)) != V4SImode)
1100 for (i=1; i <= 18; i++)
1102 elt = XVECEXP (op, 0, index++);
1103 if (GET_CODE (elt) != SET
1104 || GET_CODE (SET_SRC (elt)) != MEM
1105 || ! memory_operand (SET_SRC (elt), DFmode)
1106 || GET_CODE (SET_DEST (elt)) != REG
1107 || GET_MODE (SET_DEST (elt)) != DFmode)
1111 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1112 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1113 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1114 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1115 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1120 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1121 (define_predicate "vrsave_operation"
1122 (match_code "parallel")
1124 int count = XVECLEN (op, 0);
1125 unsigned int dest_regno, src_regno;
1129 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1130 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1131 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1132 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1135 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1136 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1138 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1141 for (i = 1; i < count; i++)
1143 rtx elt = XVECEXP (op, 0, i);
1145 if (GET_CODE (elt) != CLOBBER
1146 && GET_CODE (elt) != SET)
1153 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1154 (define_predicate "mfcr_operation"
1155 (match_code "parallel")
1157 int count = XVECLEN (op, 0);
1160 /* Perform a quick check so we don't blow up below. */
1162 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1163 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1164 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1167 for (i = 0; i < count; i++)
1169 rtx exp = XVECEXP (op, 0, i);
1174 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1176 if (GET_CODE (src_reg) != REG
1177 || GET_MODE (src_reg) != CCmode
1178 || ! CR_REGNO_P (REGNO (src_reg)))
1181 if (GET_CODE (exp) != SET
1182 || GET_CODE (SET_DEST (exp)) != REG
1183 || GET_MODE (SET_DEST (exp)) != SImode
1184 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1186 unspec = SET_SRC (exp);
1187 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1189 if (GET_CODE (unspec) != UNSPEC
1190 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1191 || XVECLEN (unspec, 0) != 2
1192 || XVECEXP (unspec, 0, 0) != src_reg
1193 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1194 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1200 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1201 (define_predicate "mtcrf_operation"
1202 (match_code "parallel")
1204 int count = XVECLEN (op, 0);
1208 /* Perform a quick check so we don't blow up below. */
1210 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1211 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1212 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1214 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1216 if (GET_CODE (src_reg) != REG
1217 || GET_MODE (src_reg) != SImode
1218 || ! INT_REGNO_P (REGNO (src_reg)))
1221 for (i = 0; i < count; i++)
1223 rtx exp = XVECEXP (op, 0, i);
1227 if (GET_CODE (exp) != SET
1228 || GET_CODE (SET_DEST (exp)) != REG
1229 || GET_MODE (SET_DEST (exp)) != CCmode
1230 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1232 unspec = SET_SRC (exp);
1233 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1235 if (GET_CODE (unspec) != UNSPEC
1236 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1237 || XVECLEN (unspec, 0) != 2
1238 || XVECEXP (unspec, 0, 0) != src_reg
1239 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1240 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1246 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1247 (define_predicate "lmw_operation"
1248 (match_code "parallel")
1250 int count = XVECLEN (op, 0);
1251 unsigned int dest_regno;
1253 unsigned int base_regno;
1254 HOST_WIDE_INT offset;
1257 /* Perform a quick check so we don't blow up below. */
1259 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1260 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1261 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1264 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1265 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1268 || count != 32 - (int) dest_regno)
1271 if (legitimate_indirect_address_p (src_addr, 0))
1274 base_regno = REGNO (src_addr);
1275 if (base_regno == 0)
1278 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
1280 offset = INTVAL (XEXP (src_addr, 1));
1281 base_regno = REGNO (XEXP (src_addr, 0));
1286 for (i = 0; i < count; i++)
1288 rtx elt = XVECEXP (op, 0, i);
1291 HOST_WIDE_INT newoffset;
1293 if (GET_CODE (elt) != SET
1294 || GET_CODE (SET_DEST (elt)) != REG
1295 || GET_MODE (SET_DEST (elt)) != SImode
1296 || REGNO (SET_DEST (elt)) != dest_regno + i
1297 || GET_CODE (SET_SRC (elt)) != MEM
1298 || GET_MODE (SET_SRC (elt)) != SImode)
1300 newaddr = XEXP (SET_SRC (elt), 0);
1301 if (legitimate_indirect_address_p (newaddr, 0))
1306 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1308 addr_reg = XEXP (newaddr, 0);
1309 newoffset = INTVAL (XEXP (newaddr, 1));
1313 if (REGNO (addr_reg) != base_regno
1314 || newoffset != offset + 4 * i)
1321 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1322 (define_predicate "stmw_operation"
1323 (match_code "parallel")
1325 int count = XVECLEN (op, 0);
1326 unsigned int src_regno;
1328 unsigned int base_regno;
1329 HOST_WIDE_INT offset;
1332 /* Perform a quick check so we don't blow up below. */
1334 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1335 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1336 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1339 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1340 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1343 || count != 32 - (int) src_regno)
1346 if (legitimate_indirect_address_p (dest_addr, 0))
1349 base_regno = REGNO (dest_addr);
1350 if (base_regno == 0)
1353 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
1355 offset = INTVAL (XEXP (dest_addr, 1));
1356 base_regno = REGNO (XEXP (dest_addr, 0));
1361 for (i = 0; i < count; i++)
1363 rtx elt = XVECEXP (op, 0, i);
1366 HOST_WIDE_INT newoffset;
1368 if (GET_CODE (elt) != SET
1369 || GET_CODE (SET_SRC (elt)) != REG
1370 || GET_MODE (SET_SRC (elt)) != SImode
1371 || REGNO (SET_SRC (elt)) != src_regno + i
1372 || GET_CODE (SET_DEST (elt)) != MEM
1373 || GET_MODE (SET_DEST (elt)) != SImode)
1375 newaddr = XEXP (SET_DEST (elt), 0);
1376 if (legitimate_indirect_address_p (newaddr, 0))
1381 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1383 addr_reg = XEXP (newaddr, 0);
1384 newoffset = INTVAL (XEXP (newaddr, 1));
1388 if (REGNO (addr_reg) != base_regno
1389 || newoffset != offset + 4 * i)