1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19 ;; Boston, MA 02110-1301, USA.
21 ;; Return 1 for anything except PARALLEL.
22 (define_predicate "any_operand"
23 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
25 ;; Return 1 for any PARALLEL.
26 (define_predicate "any_parallel_operand"
27 (match_code "parallel"))
29 ;; Return 1 if op is COUNT register.
30 (define_predicate "count_register_operand"
31 (and (match_code "reg")
32 (match_test "REGNO (op) == COUNT_REGISTER_REGNUM
33 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
35 ;; Return 1 if op is an Altivec register.
36 (define_predicate "altivec_register_operand"
37 (and (match_operand 0 "register_operand")
38 (match_test "GET_CODE (op) != REG
39 || ALTIVEC_REGNO_P (REGNO (op))
40 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
42 ;; Return 1 if op is XER register.
43 (define_predicate "xer_operand"
44 (and (match_code "reg")
45 (match_test "XER_REGNO_P (REGNO (op))")))
47 ;; Return 1 if op is a signed 5-bit constant integer.
48 (define_predicate "s5bit_cint_operand"
49 (and (match_code "const_int")
50 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
52 ;; Return 1 if op is a unsigned 5-bit constant integer.
53 (define_predicate "u5bit_cint_operand"
54 (and (match_code "const_int")
55 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
57 ;; Return 1 if op is a signed 8-bit constant integer.
58 ;; Integer multiplcation complete more quickly
59 (define_predicate "s8bit_cint_operand"
60 (and (match_code "const_int")
61 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
63 ;; Return 1 if op is a constant integer that can fit in a D field.
64 (define_predicate "short_cint_operand"
65 (and (match_code "const_int")
66 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')")))
68 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
69 (define_predicate "u_short_cint_operand"
70 (and (match_code "const_int")
71 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')")))
73 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
74 (define_predicate "non_short_cint_operand"
75 (and (match_code "const_int")
76 (match_test "(unsigned HOST_WIDE_INT)
77 (INTVAL (op) + 0x8000) >= 0x10000")))
79 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
80 (define_predicate "exact_log2_cint_operand"
81 (and (match_code "const_int")
82 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
84 ;; Return 1 if op is a register that is not special.
85 (define_predicate "gpc_reg_operand"
86 (and (match_operand 0 "register_operand")
87 (match_test "GET_CODE (op) != REG
88 || (REGNO (op) >= ARG_POINTER_REGNUM
89 && !XER_REGNO_P (REGNO (op)))
90 || REGNO (op) < MQ_REGNO")))
92 ;; Return 1 if op is a register that is a condition register field.
93 (define_predicate "cc_reg_operand"
94 (and (match_operand 0 "register_operand")
95 (match_test "GET_CODE (op) != REG
96 || REGNO (op) > LAST_VIRTUAL_REGISTER
97 || CR_REGNO_P (REGNO (op))")))
99 ;; Return 1 if op is a register that is a condition register field not cr0.
100 (define_predicate "cc_reg_not_cr0_operand"
101 (and (match_operand 0 "register_operand")
102 (match_test "GET_CODE (op) != REG
103 || REGNO (op) > LAST_VIRTUAL_REGISTER
104 || CR_REGNO_NOT_CR0_P (REGNO (op))")))
106 ;; Return 1 if op is a constant integer valid for D field
107 ;; or non-special register register.
108 (define_predicate "reg_or_short_operand"
109 (if_then_else (match_code "const_int")
110 (match_operand 0 "short_cint_operand")
111 (match_operand 0 "gpc_reg_operand")))
113 ;; Return 1 if op is a constant integer valid whose negation is valid for
114 ;; D field or non-special register register.
115 ;; Do not allow a constant zero because all patterns that call this
116 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
117 ;; or equal to const, which does not work for zero.
118 (define_predicate "reg_or_neg_short_operand"
119 (if_then_else (match_code "const_int")
120 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'P')
121 && INTVAL (op) != 0")
122 (match_operand 0 "gpc_reg_operand")))
124 ;; Return 1 if op is a constant integer valid for DS field
125 ;; or non-special register.
126 (define_predicate "reg_or_aligned_short_operand"
127 (if_then_else (match_code "const_int")
128 (and (match_operand 0 "short_cint_operand")
129 (match_test "!(INTVAL (op) & 3)"))
130 (match_operand 0 "gpc_reg_operand")))
132 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
133 ;; or non-special register.
134 (define_predicate "reg_or_u_short_operand"
135 (if_then_else (match_code "const_int")
136 (match_operand 0 "u_short_cint_operand")
137 (match_operand 0 "gpc_reg_operand")))
139 ;; Return 1 if op is any constant integer
140 ;; or non-special register.
141 (define_predicate "reg_or_cint_operand"
142 (ior (match_code "const_int")
143 (match_operand 0 "gpc_reg_operand")))
145 ;; Return 1 if op is a constant integer valid for addition
146 ;; or non-special register.
147 (define_predicate "reg_or_add_cint_operand"
148 (if_then_else (match_code "const_int")
149 (match_test "(HOST_BITS_PER_WIDE_INT == 32
150 && (mode == SImode || INTVAL (op) < 0x7fff8000))
151 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
152 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
153 (match_operand 0 "gpc_reg_operand")))
155 ;; Return 1 if op is a constant integer valid for subtraction
156 ;; or non-special register.
157 (define_predicate "reg_or_sub_cint_operand"
158 (if_then_else (match_code "const_int")
159 (match_test "(HOST_BITS_PER_WIDE_INT == 32
160 && (mode == SImode || - INTVAL (op) < 0x7fff8000))
161 || ((unsigned HOST_WIDE_INT) (- INTVAL (op)
163 ? 0x80000000 : 0x80008000))
164 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
165 (match_operand 0 "gpc_reg_operand")))
167 ;; Return 1 if op is any 32-bit unsigned constant integer
168 ;; or non-special register.
169 (define_predicate "reg_or_logical_cint_operand"
170 (if_then_else (match_code "const_int")
171 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
173 || ((INTVAL (op) & GET_MODE_MASK (mode)
174 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
175 (if_then_else (match_code "const_double")
176 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
178 && CONST_DOUBLE_HIGH (op) == 0")
179 (match_operand 0 "gpc_reg_operand"))))
181 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
182 ;; with no more than one instruction per word.
183 (define_predicate "easy_fp_constant"
184 (match_code "const_double")
189 if (GET_MODE (op) != mode
190 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
193 /* Consider all constants with -msoft-float to be easy. */
194 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
198 /* If we are using V.4 style PIC, consider all constants to be hard. */
199 if (flag_pic && DEFAULT_ABI == ABI_V4)
202 #ifdef TARGET_RELOCATABLE
203 /* Similarly if we are using -mrelocatable, consider all constants
205 if (TARGET_RELOCATABLE)
212 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
213 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
215 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
216 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
217 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
218 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
221 /* Force constants to memory before reload to utilize
222 compress_float_constant.
223 Avoid this when flag_unsafe_math_optimizations is enabled
224 because RDIV division to reciprocal optimization is not able
225 to regenerate the division. */
226 if (TARGET_E500_DOUBLE
227 || (!reload_in_progress && !reload_completed
228 && !flag_unsafe_math_optimizations))
231 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
232 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
234 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
235 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
238 /* The constant 0.f is easy. */
239 if (op == CONST0_RTX (SFmode))
242 /* Force constants to memory before reload to utilize
243 compress_float_constant.
244 Avoid this when flag_unsafe_math_optimizations is enabled
245 because RDIV division to reciprocal optimization is not able
246 to regenerate the division. */
247 if (!reload_in_progress && !reload_completed
248 && !flag_unsafe_math_optimizations)
251 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
252 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
254 return num_insns_constant_wide (k[0]) == 1;
257 return ((TARGET_POWERPC64
258 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
259 || (num_insns_constant (op, DImode) <= 2));
269 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
270 ;; vector register without using memory.
271 (define_predicate "easy_vector_constant"
272 (match_code "const_vector")
276 if (!TARGET_ALTIVEC && !TARGET_SPE)
279 if (zero_constant (op, mode)
280 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
281 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
284 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
287 if (TARGET_SPE && mode == V1DImode)
290 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
291 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
293 /* Limit SPE vectors to 15 bits signed. These we can generate with:
298 I don't know how efficient it would be to allow bigger constants,
299 considering we'll have an extra 'ori' for every 'li'. I doubt 5
300 instructions is better than a 64-bit memory load, but I don't
301 have the e500 timing specs. */
302 if (TARGET_SPE && mode == V2SImode
303 && cst >= -0x7fff && cst <= 0x7fff
304 && cst2 >= -0x7fff && cst2 <= 0x7fff)
308 && easy_vector_same (op, mode))
310 cst = easy_vector_splat_const (cst, mode);
311 if (EASY_VECTOR_15_ADD_SELF (cst)
312 || EASY_VECTOR_15 (cst))
318 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
319 (define_predicate "easy_vector_constant_add_self"
320 (and (match_code "const_vector")
321 (and (match_test "TARGET_ALTIVEC")
322 (and (match_test "easy_vector_same (op, mode)")
323 (match_test "EASY_VECTOR_15_ADD_SELF
324 (easy_vector_splat_const
325 (INTVAL (CONST_VECTOR_ELT (op, 0)),
328 ;; Return 1 if operand is constant zero (scalars and vectors).
329 (define_predicate "zero_constant"
330 (and (match_code "const_int,const_double,const_vector")
331 (match_test "op == CONST0_RTX (mode)")))
333 ;; Return 1 if operand is 0.0.
334 ;; or non-special register register field no cr0
335 (define_predicate "zero_fp_constant"
336 (and (match_code "const_double")
337 (match_test "GET_MODE_CLASS (mode) == MODE_FLOAT
338 && op == CONST0_RTX (mode)")))
340 ;; Return 1 if the operand is in volatile memory. Note that during the
341 ;; RTL generation phase, memory_operand does not return TRUE for volatile
342 ;; memory references. So this function allows us to recognize volatile
343 ;; references where it's safe.
344 (define_predicate "volatile_mem_operand"
345 (and (and (match_code "mem")
346 (match_test "MEM_VOLATILE_P (op)"))
347 (if_then_else (match_test "reload_completed")
348 (match_operand 0 "memory_operand")
349 (if_then_else (match_test "reload_in_progress")
350 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
351 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
353 ;; Return 1 if the operand is an offsettable memory operand.
354 (define_predicate "offsettable_mem_operand"
355 (and (match_code "mem")
356 (match_test "offsettable_address_p (reload_completed
357 || reload_in_progress,
358 mode, XEXP (op, 0))")))
360 ;; Return 1 if the operand is an indexed or indirect memory operand.
361 (define_predicate "indexed_or_indirect_operand"
362 (match_operand 0 "memory_operand")
364 rtx tmp = XEXP (op, 0);
367 && ALTIVEC_VECTOR_MODE (mode)
368 && GET_CODE (tmp) == AND
369 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
370 && INTVAL (XEXP (tmp, 1)) == -16)
374 || (GET_CODE (tmp) == PLUS
375 && REG_P (XEXP (tmp, 0))
376 && REG_P (XEXP (tmp, 1)));
379 ;; Return 1 if the operand is a memory operand with an address divisible by 4
380 (define_predicate "word_offset_memref_operand"
381 (and (match_operand 0 "memory_operand")
382 (match_test "GET_CODE (XEXP (op, 0)) != PLUS
383 || ! REG_P (XEXP (XEXP (op, 0), 0))
384 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT
385 || INTVAL (XEXP (XEXP (op, 0), 1)) % 4 == 0")))
387 ;; Return 1 if the operand is an indexed or indirect address.
388 (define_predicate "indexed_or_indirect_address"
389 (and (match_operand 0 "address_operand")
390 (match_test "REG_P (op)
391 || (GET_CODE (op) == PLUS
392 && REG_P (XEXP (op, 0))
393 && REG_P (XEXP (op, 1)))")))
395 ;; Used for the destination of the fix_truncdfsi2 expander.
396 ;; If stfiwx will be used, the result goes to memory; otherwise,
397 ;; we're going to emit a store and a load of a subreg, so the dest is a
399 (define_predicate "fix_trunc_dest_operand"
400 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
401 (match_operand 0 "memory_operand")
402 (match_operand 0 "gpc_reg_operand")))
404 ;; Return 1 if the operand is either a non-special register or can be used
405 ;; as the operand of a `mode' add insn.
406 (define_predicate "add_operand"
407 (if_then_else (match_code "const_int")
408 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
409 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')")
410 (match_operand 0 "gpc_reg_operand")))
412 ;; Return 1 if OP is a constant but not a valid add_operand.
413 (define_predicate "non_add_cint_operand"
414 (and (match_code "const_int")
415 (match_test "!CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
416 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')")))
418 ;; Return 1 if the operand is a non-special register or a constant that
419 ;; can be used as the operand of an OR or XOR.
420 (define_predicate "logical_operand"
421 (match_code "reg,subreg,const_int,const_double")
423 HOST_WIDE_INT opl, oph;
425 if (gpc_reg_operand (op, mode))
428 if (GET_CODE (op) == CONST_INT)
430 opl = INTVAL (op) & GET_MODE_MASK (mode);
432 if (HOST_BITS_PER_WIDE_INT <= 32
433 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
436 else if (GET_CODE (op) == CONST_DOUBLE)
438 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT);
440 opl = CONST_DOUBLE_LOW (op);
441 oph = CONST_DOUBLE_HIGH (op);
448 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
449 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
452 ;; Return 1 if op is a constant that is not a logical operand, but could
453 ;; be split into one.
454 (define_predicate "non_logical_cint_operand"
455 (and (match_code "const_int,const_double")
456 (and (not (match_operand 0 "logical_operand"))
457 (match_operand 0 "reg_or_logical_cint_operand"))))
459 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
460 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
461 ;; transitions). Reject all ones and all zeros, since these should have
462 ;; been optimized away and confuse the making of MB and ME.
463 (define_predicate "mask_operand"
464 (match_code "const_int")
466 HOST_WIDE_INT c, lsb;
470 if (TARGET_POWERPC64)
472 /* Fail if the mask is not 32-bit. */
473 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
476 /* Fail if the mask wraps around because the upper 32-bits of the
477 mask will all be 1s, contrary to GCC's internal view. */
478 if ((c & 0x80000001) == 0x80000001)
482 /* We don't change the number of transitions by inverting,
483 so make sure we start with the LS bit zero. */
487 /* Reject all zeros or all ones. */
491 /* Find the first transition. */
494 /* Invert to look for a second transition. */
497 /* Erase first transition. */
500 /* Find the second transition (if any). */
503 /* Match if all the bits above are 1's (or c is zero). */
507 ;; Return 1 for the PowerPC64 rlwinm corner case.
508 (define_predicate "mask_operand_wrap"
509 (match_code "const_int")
511 HOST_WIDE_INT c, lsb;
515 if ((c & 0x80000001) != 0x80000001)
529 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
530 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
531 ;; transition). Reject all zeros, since zero should have been
532 ;; optimized away and confuses the making of MB and ME.
533 (define_predicate "mask64_operand"
534 (match_code "const_int")
536 HOST_WIDE_INT c, lsb;
540 /* Reject all zeros. */
544 /* We don't change the number of transitions by inverting,
545 so make sure we start with the LS bit zero. */
549 /* Find the first transition. */
552 /* Match if all the bits above are 1's (or c is zero). */
556 ;; Like mask64_operand, but allow up to three transitions. This
557 ;; predicate is used by insn patterns that generate two rldicl or
558 ;; rldicr machine insns.
559 (define_predicate "mask64_2_operand"
560 (match_code "const_int")
562 HOST_WIDE_INT c, lsb;
566 /* Disallow all zeros. */
570 /* We don't change the number of transitions by inverting,
571 so make sure we start with the LS bit zero. */
575 /* Find the first transition. */
578 /* Invert to look for a second transition. */
581 /* Erase first transition. */
584 /* Find the second transition. */
587 /* Invert to look for a third transition. */
590 /* Erase second transition. */
593 /* Find the third transition (if any). */
596 /* Match if all the bits above are 1's (or c is zero). */
600 ;; Like and_operand, but also match constants that can be implemented
601 ;; with two rldicl or rldicr insns.
602 (define_predicate "and64_2_operand"
603 (ior (match_operand 0 "mask64_2_operand")
604 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
605 (match_operand 0 "gpc_reg_operand")
606 (match_operand 0 "logical_operand"))))
608 ;; Return 1 if the operand is either a non-special register or a
609 ;; constant that can be used as the operand of a logical AND.
610 (define_predicate "and_operand"
611 (ior (match_operand 0 "mask_operand")
612 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
613 (match_operand 0 "mask64_operand"))
614 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
615 (match_operand 0 "gpc_reg_operand")
616 (match_operand 0 "logical_operand")))))
618 ;; Return 1 if the operand is either a logical operand or a short cint operand.
619 (define_predicate "scc_eq_operand"
620 (ior (match_operand 0 "logical_operand")
621 (match_operand 0 "short_cint_operand")))
623 ;; Return 1 if the operand is a general non-special register or memory operand.
624 (define_predicate "reg_or_mem_operand"
625 (if_then_else (match_code "mem")
626 (ior (match_operand 0 "memory_operand")
627 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
628 (match_operand 0 "volatile_mem_operand")))
629 (match_operand 0 "gpc_reg_operand")))
631 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
632 (define_predicate "reg_or_none500mem_operand"
633 (if_then_else (match_code "mem")
634 (and (match_test "!TARGET_E500_DOUBLE")
635 (ior (match_operand 0 "memory_operand")
636 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
637 (match_operand 0 "volatile_mem_operand"))))
638 (match_operand 0 "gpc_reg_operand")))
640 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
641 (define_predicate "zero_reg_mem_operand"
642 (ior (match_operand 0 "zero_fp_constant")
643 (match_operand 0 "reg_or_mem_operand")))
645 ;; Return 1 if the operand is a general register or memory operand without
646 ;; pre_inc or pre_dec, which produces invalid form of PowerPC lwa
648 (define_predicate "lwa_operand"
649 (match_code "reg,subreg,mem")
653 if (reload_completed && GET_CODE (inner) == SUBREG)
654 inner = SUBREG_REG (inner);
656 return gpc_reg_operand (inner, mode)
657 || (memory_operand (inner, mode)
658 && GET_CODE (XEXP (inner, 0)) != PRE_INC
659 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
660 && (GET_CODE (XEXP (inner, 0)) != PLUS
661 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
662 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
665 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
666 (define_predicate "symbol_ref_operand"
667 (and (match_code "symbol_ref")
668 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
669 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
671 ;; Return 1 if op is an operand that can be loaded via the GOT.
672 ;; or non-special register register field no cr0
673 (define_predicate "got_operand"
674 (match_code "symbol_ref,const,label_ref"))
676 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
677 ;; excluding labels involving addition.
678 (define_predicate "got_no_const_operand"
679 (match_code "symbol_ref,label_ref"))
681 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
682 (define_predicate "rs6000_tls_symbol_ref"
683 (and (match_code "symbol_ref")
684 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
686 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
687 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
688 (define_predicate "call_operand"
689 (if_then_else (match_code "reg")
690 (match_test "REGNO (op) == LINK_REGISTER_REGNUM
691 || REGNO (op) == COUNT_REGISTER_REGNUM
692 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
693 (match_code "symbol_ref")))
695 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
697 (define_predicate "current_file_function_operand"
698 (and (match_code "symbol_ref")
699 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
700 && (SYMBOL_REF_LOCAL_P (op)
701 || (op == XEXP (DECL_RTL (current_function_decl),
704 ;; Return 1 if this operand is a valid input for a move insn.
705 (define_predicate "input_operand"
706 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
707 const_double,const_vector,const_int,plus")
709 /* Memory is always valid. */
710 if (memory_operand (op, mode))
713 /* For floating-point, easy constants are valid. */
714 if (GET_MODE_CLASS (mode) == MODE_FLOAT
716 && easy_fp_constant (op, mode))
719 /* Allow any integer constant. */
720 if (GET_MODE_CLASS (mode) == MODE_INT
721 && (GET_CODE (op) == CONST_INT
722 || GET_CODE (op) == CONST_DOUBLE))
725 /* Allow easy vector constants. */
726 if (GET_CODE (op) == CONST_VECTOR
727 && easy_vector_constant (op, mode))
730 /* For floating-point or multi-word mode, the only remaining valid type
732 if (GET_MODE_CLASS (mode) == MODE_FLOAT
733 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
734 return register_operand (op, mode);
736 /* The only cases left are integral modes one word or smaller (we
737 do not get called for MODE_CC values). These can be in any
739 if (register_operand (op, mode))
742 /* A SYMBOL_REF referring to the TOC is valid. */
743 if (legitimate_constant_pool_address_p (op))
746 /* A constant pool expression (relative to the TOC) is valid */
747 if (toc_relative_expr_p (op))
750 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
752 if (DEFAULT_ABI == ABI_V4
753 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
754 && small_data_operand (op, Pmode))
760 ;; Return true if OP is an invalid SUBREG operation on the e500.
761 (define_predicate "rs6000_nonimmediate_operand"
762 (match_code "reg,subreg,mem")
764 if (TARGET_E500_DOUBLE
765 && GET_CODE (op) == SUBREG
766 && invalid_e500_subreg (op, mode))
769 return nonimmediate_operand (op, mode);
772 ;; Return true if operand is boolean operator.
773 (define_predicate "boolean_operator"
774 (match_code "and,ior,xor"))
776 ;; Return true if operand is OR-form of boolean operator.
777 (define_predicate "boolean_or_operator"
778 (match_code "ior,xor"))
780 ;; Return true if operand is an equality operator.
781 (define_special_predicate "equality_operator"
782 (match_code "eq,ne"))
784 ;; Return true if operand is MIN or MAX operator.
785 (define_predicate "min_max_operator"
786 (match_code "smin,smax,umin,umax"))
788 ;; Return 1 if OP is a comparison operation that is valid for a branch
789 ;; instruction. We check the opcode against the mode of the CC value.
790 ;; validate_condition_mode is an assertion.
791 (define_predicate "branch_comparison_operator"
792 (and (match_operand 0 "comparison_operator")
793 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
794 (match_test "validate_condition_mode (GET_CODE (op),
795 GET_MODE (XEXP (op, 0))),
798 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
799 ;; it must be a positive comparison.
800 (define_predicate "scc_comparison_operator"
801 (and (match_operand 0 "branch_comparison_operator")
802 (match_code "eq,lt,gt,ltu,gtu,unordered")))
804 ;; Return 1 if OP is a comparison operation that is valid for a branch
805 ;; insn, which is true if the corresponding bit in the CC register is set.
806 (define_predicate "branch_positive_comparison_operator"
807 (and (match_operand 0 "branch_comparison_operator")
808 (match_code "eq,lt,gt,ltu,gtu,unordered")))
810 ;; Return 1 is OP is a comparison operation that is valid for a trap insn.
811 (define_predicate "trap_comparison_operator"
812 (and (match_operand 0 "comparison_operator")
813 (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu")))
815 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
816 (define_predicate "load_multiple_operation"
817 (match_code "parallel")
819 int count = XVECLEN (op, 0);
820 unsigned int dest_regno;
824 /* Perform a quick check so we don't blow up below. */
826 || GET_CODE (XVECEXP (op, 0, 0)) != SET
827 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
828 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
831 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
832 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
834 for (i = 1; i < count; i++)
836 rtx elt = XVECEXP (op, 0, i);
838 if (GET_CODE (elt) != SET
839 || GET_CODE (SET_DEST (elt)) != REG
840 || GET_MODE (SET_DEST (elt)) != SImode
841 || REGNO (SET_DEST (elt)) != dest_regno + i
842 || GET_CODE (SET_SRC (elt)) != MEM
843 || GET_MODE (SET_SRC (elt)) != SImode
844 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
845 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
846 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
847 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
854 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
855 ;; The second vector element is a CLOBBER.
856 (define_predicate "store_multiple_operation"
857 (match_code "parallel")
859 int count = XVECLEN (op, 0) - 1;
860 unsigned int src_regno;
864 /* Perform a quick check so we don't blow up below. */
866 || GET_CODE (XVECEXP (op, 0, 0)) != SET
867 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
868 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
871 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
872 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
874 for (i = 1; i < count; i++)
876 rtx elt = XVECEXP (op, 0, i + 1);
878 if (GET_CODE (elt) != SET
879 || GET_CODE (SET_SRC (elt)) != REG
880 || GET_MODE (SET_SRC (elt)) != SImode
881 || REGNO (SET_SRC (elt)) != src_regno + i
882 || GET_CODE (SET_DEST (elt)) != MEM
883 || GET_MODE (SET_DEST (elt)) != SImode
884 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
885 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
886 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
887 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
894 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
896 (define_predicate "save_world_operation"
897 (match_code "parallel")
902 int count = XVECLEN (op, 0);
908 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
909 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
912 for (i=1; i <= 18; i++)
914 elt = XVECEXP (op, 0, index++);
915 if (GET_CODE (elt) != SET
916 || GET_CODE (SET_DEST (elt)) != MEM
917 || ! memory_operand (SET_DEST (elt), DFmode)
918 || GET_CODE (SET_SRC (elt)) != REG
919 || GET_MODE (SET_SRC (elt)) != DFmode)
923 for (i=1; i <= 12; i++)
925 elt = XVECEXP (op, 0, index++);
926 if (GET_CODE (elt) != SET
927 || GET_CODE (SET_DEST (elt)) != MEM
928 || GET_CODE (SET_SRC (elt)) != REG
929 || GET_MODE (SET_SRC (elt)) != V4SImode)
933 for (i=1; i <= 19; i++)
935 elt = XVECEXP (op, 0, index++);
936 if (GET_CODE (elt) != SET
937 || GET_CODE (SET_DEST (elt)) != MEM
938 || ! memory_operand (SET_DEST (elt), Pmode)
939 || GET_CODE (SET_SRC (elt)) != REG
940 || GET_MODE (SET_SRC (elt)) != Pmode)
944 elt = XVECEXP (op, 0, index++);
945 if (GET_CODE (elt) != SET
946 || GET_CODE (SET_DEST (elt)) != MEM
947 || ! memory_operand (SET_DEST (elt), Pmode)
948 || GET_CODE (SET_SRC (elt)) != REG
949 || REGNO (SET_SRC (elt)) != CR2_REGNO
950 || GET_MODE (SET_SRC (elt)) != Pmode)
953 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
954 || GET_CODE (XVECEXP (op, 0, index++)) != USE
955 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
960 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
962 (define_predicate "restore_world_operation"
963 (match_code "parallel")
968 int count = XVECLEN (op, 0);
974 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
975 || GET_CODE (XVECEXP (op, 0, index++)) != USE
976 || GET_CODE (XVECEXP (op, 0, index++)) != USE
977 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
980 elt = XVECEXP (op, 0, index++);
981 if (GET_CODE (elt) != SET
982 || GET_CODE (SET_SRC (elt)) != MEM
983 || ! memory_operand (SET_SRC (elt), Pmode)
984 || GET_CODE (SET_DEST (elt)) != REG
985 || REGNO (SET_DEST (elt)) != CR2_REGNO
986 || GET_MODE (SET_DEST (elt)) != Pmode)
989 for (i=1; i <= 19; i++)
991 elt = XVECEXP (op, 0, index++);
992 if (GET_CODE (elt) != SET
993 || GET_CODE (SET_SRC (elt)) != MEM
994 || ! memory_operand (SET_SRC (elt), Pmode)
995 || GET_CODE (SET_DEST (elt)) != REG
996 || GET_MODE (SET_DEST (elt)) != Pmode)
1000 for (i=1; i <= 12; i++)
1002 elt = XVECEXP (op, 0, index++);
1003 if (GET_CODE (elt) != SET
1004 || GET_CODE (SET_SRC (elt)) != MEM
1005 || GET_CODE (SET_DEST (elt)) != REG
1006 || GET_MODE (SET_DEST (elt)) != V4SImode)
1010 for (i=1; i <= 18; i++)
1012 elt = XVECEXP (op, 0, index++);
1013 if (GET_CODE (elt) != SET
1014 || GET_CODE (SET_SRC (elt)) != MEM
1015 || ! memory_operand (SET_SRC (elt), DFmode)
1016 || GET_CODE (SET_DEST (elt)) != REG
1017 || GET_MODE (SET_DEST (elt)) != DFmode)
1021 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1022 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1023 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1024 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1025 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1030 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1031 (define_predicate "vrsave_operation"
1032 (match_code "parallel")
1034 int count = XVECLEN (op, 0);
1035 unsigned int dest_regno, src_regno;
1039 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1040 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1041 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
1044 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1045 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1047 if (dest_regno != VRSAVE_REGNO
1048 && src_regno != VRSAVE_REGNO)
1051 for (i = 1; i < count; i++)
1053 rtx elt = XVECEXP (op, 0, i);
1055 if (GET_CODE (elt) != CLOBBER
1056 && GET_CODE (elt) != SET)
1063 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1064 (define_predicate "mfcr_operation"
1065 (match_code "parallel")
1067 int count = XVECLEN (op, 0);
1070 /* Perform a quick check so we don't blow up below. */
1072 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1073 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1074 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1077 for (i = 0; i < count; i++)
1079 rtx exp = XVECEXP (op, 0, i);
1084 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1086 if (GET_CODE (src_reg) != REG
1087 || GET_MODE (src_reg) != CCmode
1088 || ! CR_REGNO_P (REGNO (src_reg)))
1091 if (GET_CODE (exp) != SET
1092 || GET_CODE (SET_DEST (exp)) != REG
1093 || GET_MODE (SET_DEST (exp)) != SImode
1094 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1096 unspec = SET_SRC (exp);
1097 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1099 if (GET_CODE (unspec) != UNSPEC
1100 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1101 || XVECLEN (unspec, 0) != 2
1102 || XVECEXP (unspec, 0, 0) != src_reg
1103 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1104 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1110 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1111 (define_predicate "mtcrf_operation"
1112 (match_code "parallel")
1114 int count = XVECLEN (op, 0);
1118 /* Perform a quick check so we don't blow up below. */
1120 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1121 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1122 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1124 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1126 if (GET_CODE (src_reg) != REG
1127 || GET_MODE (src_reg) != SImode
1128 || ! INT_REGNO_P (REGNO (src_reg)))
1131 for (i = 0; i < count; i++)
1133 rtx exp = XVECEXP (op, 0, i);
1137 if (GET_CODE (exp) != SET
1138 || GET_CODE (SET_DEST (exp)) != REG
1139 || GET_MODE (SET_DEST (exp)) != CCmode
1140 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1142 unspec = SET_SRC (exp);
1143 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1145 if (GET_CODE (unspec) != UNSPEC
1146 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1147 || XVECLEN (unspec, 0) != 2
1148 || XVECEXP (unspec, 0, 0) != src_reg
1149 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1150 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1156 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1157 (define_predicate "lmw_operation"
1158 (match_code "parallel")
1160 int count = XVECLEN (op, 0);
1161 unsigned int dest_regno;
1163 unsigned int base_regno;
1164 HOST_WIDE_INT offset;
1167 /* Perform a quick check so we don't blow up below. */
1169 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1170 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1171 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1174 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1175 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1178 || count != 32 - (int) dest_regno)
1181 if (legitimate_indirect_address_p (src_addr, 0))
1184 base_regno = REGNO (src_addr);
1185 if (base_regno == 0)
1188 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
1190 offset = INTVAL (XEXP (src_addr, 1));
1191 base_regno = REGNO (XEXP (src_addr, 0));
1196 for (i = 0; i < count; i++)
1198 rtx elt = XVECEXP (op, 0, i);
1201 HOST_WIDE_INT newoffset;
1203 if (GET_CODE (elt) != SET
1204 || GET_CODE (SET_DEST (elt)) != REG
1205 || GET_MODE (SET_DEST (elt)) != SImode
1206 || REGNO (SET_DEST (elt)) != dest_regno + i
1207 || GET_CODE (SET_SRC (elt)) != MEM
1208 || GET_MODE (SET_SRC (elt)) != SImode)
1210 newaddr = XEXP (SET_SRC (elt), 0);
1211 if (legitimate_indirect_address_p (newaddr, 0))
1216 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1218 addr_reg = XEXP (newaddr, 0);
1219 newoffset = INTVAL (XEXP (newaddr, 1));
1223 if (REGNO (addr_reg) != base_regno
1224 || newoffset != offset + 4 * i)
1231 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1232 (define_predicate "stmw_operation"
1233 (match_code "parallel")
1235 int count = XVECLEN (op, 0);
1236 unsigned int src_regno;
1238 unsigned int base_regno;
1239 HOST_WIDE_INT offset;
1242 /* Perform a quick check so we don't blow up below. */
1244 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1245 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1246 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1249 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1250 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1253 || count != 32 - (int) src_regno)
1256 if (legitimate_indirect_address_p (dest_addr, 0))
1259 base_regno = REGNO (dest_addr);
1260 if (base_regno == 0)
1263 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
1265 offset = INTVAL (XEXP (dest_addr, 1));
1266 base_regno = REGNO (XEXP (dest_addr, 0));
1271 for (i = 0; i < count; i++)
1273 rtx elt = XVECEXP (op, 0, i);
1276 HOST_WIDE_INT newoffset;
1278 if (GET_CODE (elt) != SET
1279 || GET_CODE (SET_SRC (elt)) != REG
1280 || GET_MODE (SET_SRC (elt)) != SImode
1281 || REGNO (SET_SRC (elt)) != src_regno + i
1282 || GET_CODE (SET_DEST (elt)) != MEM
1283 || GET_MODE (SET_DEST (elt)) != SImode)
1285 newaddr = XEXP (SET_DEST (elt), 0);
1286 if (legitimate_indirect_address_p (newaddr, 0))
1291 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1293 addr_reg = XEXP (newaddr, 0);
1294 newoffset = INTVAL (XEXP (newaddr, 1));
1298 if (REGNO (addr_reg) != base_regno
1299 || newoffset != offset + 4 * i)