1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;; Return 1 for anything except PARALLEL.
22 (define_predicate "any_operand"
23 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
25 ;; Return 1 for any PARALLEL.
26 (define_predicate "any_parallel_operand"
27 (match_code "parallel"))
29 ;; Return 1 if op is COUNT register.
30 (define_predicate "count_register_operand"
31 (and (match_code "reg")
32 (match_test "REGNO (op) == COUNT_REGISTER_REGNUM
33 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
35 ;; Return 1 if op is an Altivec register.
36 (define_predicate "altivec_register_operand"
37 (and (match_operand 0 "register_operand")
38 (match_test "GET_CODE (op) != REG
39 || ALTIVEC_REGNO_P (REGNO (op))
40 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
42 ;; Return 1 if op is XER register.
43 (define_predicate "xer_operand"
44 (and (match_code "reg")
45 (match_test "XER_REGNO_P (REGNO (op))")))
47 ;; Return 1 if op is a signed 8-bit constant integer.
48 ;; Integer multiplcation complete more quickly
49 (define_predicate "s8bit_cint_operand"
50 (and (match_code "const_int")
51 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
53 ;; Return 1 if op is a constant integer that can fit in a D field.
54 (define_predicate "short_cint_operand"
55 (and (match_code "const_int")
56 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')")))
58 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
59 (define_predicate "u_short_cint_operand"
60 (and (match_code "const_int")
61 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')")))
63 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
64 (define_predicate "non_short_cint_operand"
65 (and (match_code "const_int")
66 (match_test "(unsigned HOST_WIDE_INT)
67 (INTVAL (op) + 0x8000) >= 0x10000")))
69 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
70 (define_predicate "exact_log2_cint_operand"
71 (and (match_code "const_int")
72 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
74 ;; Return 1 if op is a register that is not special.
75 (define_predicate "gpc_reg_operand"
76 (and (match_operand 0 "register_operand")
77 (match_test "GET_CODE (op) != REG
78 || (REGNO (op) >= ARG_POINTER_REGNUM
79 && !XER_REGNO_P (REGNO (op)))
80 || REGNO (op) < MQ_REGNO")))
82 ;; Return 1 if op is a register that is a condition register field.
83 (define_predicate "cc_reg_operand"
84 (and (match_operand 0 "register_operand")
85 (match_test "GET_CODE (op) != REG
86 || REGNO (op) > LAST_VIRTUAL_REGISTER
87 || CR_REGNO_P (REGNO (op))")))
89 ;; Return 1 if op is a register that is a condition register field not cr0.
90 (define_predicate "cc_reg_not_cr0_operand"
91 (and (match_operand 0 "register_operand")
92 (match_test "GET_CODE (op) != REG
93 || REGNO (op) > LAST_VIRTUAL_REGISTER
94 || CR_REGNO_NOT_CR0_P (REGNO (op))")))
96 ;; Return 1 if op is a constant integer valid for D field
97 ;; or non-special register register.
98 (define_predicate "reg_or_short_operand"
99 (if_then_else (match_code "const_int")
100 (match_operand 0 "short_cint_operand")
101 (match_operand 0 "gpc_reg_operand")))
103 ;; Return 1 if op is a constant integer valid whose negation is valid for
104 ;; D field or non-special register register.
105 ;; Do not allow a constant zero because all patterns that call this
106 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
107 ;; or equal to const, which does not work for zero.
108 (define_predicate "reg_or_neg_short_operand"
109 (if_then_else (match_code "const_int")
110 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'P')
111 && INTVAL (op) != 0")
112 (match_operand 0 "gpc_reg_operand")))
114 ;; Return 1 if op is a constant integer valid for DS field
115 ;; or non-special register.
116 (define_predicate "reg_or_aligned_short_operand"
117 (if_then_else (match_code "const_int")
118 (and (match_operand 0 "short_cint_operand")
119 (match_test "!(INTVAL (op) & 3)"))
120 (match_operand 0 "gpc_reg_operand")))
122 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
123 ;; or non-special register.
124 (define_predicate "reg_or_u_short_operand"
125 (if_then_else (match_code "const_int")
126 (match_operand 0 "u_short_cint_operand")
127 (match_operand 0 "gpc_reg_operand")))
129 ;; Return 1 if op is any constant integer
130 ;; or non-special register.
131 (define_predicate "reg_or_cint_operand"
132 (ior (match_code "const_int")
133 (match_operand 0 "gpc_reg_operand")))
135 ;; Return 1 if op is a 32-bit signed constant integer valid for arithmetic
136 ;; or non-special register.
137 (define_predicate "reg_or_arith_cint_operand"
138 (if_then_else (match_code "const_int")
139 (match_test "HOST_BITS_PER_WIDE_INT == 32
140 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
141 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
142 (match_operand 0 "gpc_reg_operand")))
144 ;; Return 1 if op is a 32-bit signed constant integer valid for 64-bit addition
145 ;; or non-special register.
146 (define_predicate "reg_or_add_cint64_operand"
147 (if_then_else (match_code "const_int")
148 (match_test "(HOST_BITS_PER_WIDE_INT == 32 && INTVAL (op) < 0x7fff8000)
149 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
150 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
151 (match_operand 0 "gpc_reg_operand")))
153 ;; Return 1 if op is a 32-bit constant integer valid for 64-bit subtraction
154 ;; or non-special register.
155 (define_predicate "reg_or_sub_cint64_operand"
156 (if_then_else (match_code "const_int")
157 (match_test "(HOST_BITS_PER_WIDE_INT == 32 && INTVAL (op) < 0x7fff8000)
158 || ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
159 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
160 (match_operand 0 "gpc_reg_operand")))
162 ;; Return 1 if op is any 32-bit unsigned constant integer
163 ;; or non-special register.
164 (define_predicate "reg_or_logical_cint_operand"
165 (if_then_else (match_code "const_int")
166 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
168 || ((INTVAL (op) & GET_MODE_MASK (mode)
169 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
170 (if_then_else (match_code "const_double")
171 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
173 && CONST_DOUBLE_HIGH (op) == 0")
174 (match_operand 0 "gpc_reg_operand"))))
176 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
177 ;; with no more than one instruction per word.
178 (define_predicate "easy_fp_constant"
179 (match_code "const_double")
181 if (GET_MODE (op) != mode
182 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
185 /* Consider all constants with -msoft-float to be easy. */
186 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
190 /* If we are using V.4 style PIC, consider all constants to be hard. */
191 if (flag_pic && DEFAULT_ABI == ABI_V4)
194 #ifdef TARGET_RELOCATABLE
195 /* Similarly if we are using -mrelocatable, consider all constants
197 if (TARGET_RELOCATABLE)
206 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
207 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
209 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
210 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
211 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
212 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
215 else if (mode == DFmode)
220 /* Force constants to memory before reload to utilize
221 compress_float_constant.
222 Avoid this when flag_unsafe_math_optimizations is enabled
223 because RDIV division to reciprocal optimization is not able
224 to regenerate the division. */
225 if (TARGET_E500_DOUBLE
226 || (!reload_in_progress && !reload_completed
227 && !flag_unsafe_math_optimizations))
230 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
231 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
233 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
234 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
237 else if (mode == SFmode)
242 /* Force constants to memory before reload to utilize
243 compress_float_constant.
244 Avoid this when flag_unsafe_math_optimizations is enabled
245 because RDIV division to reciprocal optimization is not able
246 to regenerate the division. */
247 if (!reload_in_progress && !reload_completed
248 && !flag_unsafe_math_optimizations)
251 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
252 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
254 return num_insns_constant_wide (l) == 1;
257 else if (mode == DImode)
258 return ((TARGET_POWERPC64
259 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
260 || (num_insns_constant (op, DImode) <= 2));
262 else if (mode == SImode)
268 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
269 ;; vector register without using memory.
270 (define_predicate "easy_vector_constant"
271 (match_code "const_vector")
275 if (!TARGET_ALTIVEC && !TARGET_SPE)
278 if (zero_constant (op, mode)
279 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
280 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
283 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
286 if (TARGET_SPE && mode == V1DImode)
289 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
290 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
292 /* Limit SPE vectors to 15 bits signed. These we can generate with:
297 I don't know how efficient it would be to allow bigger constants,
298 considering we'll have an extra 'ori' for every 'li'. I doubt 5
299 instructions is better than a 64-bit memory load, but I don't
300 have the e500 timing specs. */
301 if (TARGET_SPE && mode == V2SImode
302 && cst >= -0x7fff && cst <= 0x7fff
303 && cst2 >= -0x7fff && cst2 <= 0x7fff)
307 && easy_vector_same (op, mode))
309 cst = easy_vector_splat_const (cst, mode);
310 if (EASY_VECTOR_15_ADD_SELF (cst)
311 || EASY_VECTOR_15 (cst))
317 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
318 (define_predicate "easy_vector_constant_add_self"
319 (and (match_code "const_vector")
320 (and (match_test "TARGET_ALTIVEC")
321 (and (match_test "easy_vector_same (op, mode)")
322 (match_test "EASY_VECTOR_15_ADD_SELF
323 (easy_vector_splat_const
324 (INTVAL (CONST_VECTOR_ELT (op, 0)),
327 ;; Return 1 if operand is constant zero (scalars and vectors).
328 (define_predicate "zero_constant"
329 (and (match_code "const_int,const_double,const_vector")
330 (match_test "op == CONST0_RTX (mode)")))
332 ;; Return 1 if operand is 0.0.
333 ;; or non-special register register field no cr0
334 (define_predicate "zero_fp_constant"
335 (and (match_code "const_double")
336 (match_test "GET_MODE_CLASS (mode) == MODE_FLOAT
337 && op == CONST0_RTX (mode)")))
339 ;; Return 1 if the operand is in volatile memory. Note that during the
340 ;; RTL generation phase, memory_operand does not return TRUE for volatile
341 ;; memory references. So this function allows us to recognize volatile
342 ;; references where it's safe.
343 (define_predicate "volatile_mem_operand"
344 (and (and (match_code "mem")
345 (match_test "MEM_VOLATILE_P (op)"))
346 (if_then_else (match_test "reload_completed")
347 (match_operand 0 "memory_operand")
348 (if_then_else (match_test "reload_in_progress")
349 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
350 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
352 ;; Return 1 if the operand is an offsettable memory operand.
353 (define_predicate "offsettable_mem_operand"
354 (and (match_code "mem")
355 (match_test "offsettable_address_p (reload_completed
356 || reload_in_progress,
357 mode, XEXP (op, 0))")))
359 ;; Return 1 if the operand is an indexed or indirect memory operand.
360 (define_predicate "indexed_or_indirect_operand"
361 (and (match_operand 0 "memory_operand")
362 (match_test "REG_P (XEXP (op, 0))
363 || (GET_CODE (XEXP (op, 0)) == PLUS
364 && REG_P (XEXP (XEXP (op, 0), 0))
365 && REG_P (XEXP (XEXP (op, 0), 1)))")))
367 ;; Return 1 if the operand is a memory operand with an address divisible by 4
368 (define_predicate "word_offset_memref_operand"
369 (and (match_operand 0 "memory_operand")
370 (match_test "GET_CODE (XEXP (op, 0)) != PLUS
371 || ! REG_P (XEXP (XEXP (op, 0), 0))
372 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT
373 || INTVAL (XEXP (XEXP (op, 0), 1)) % 4 == 0")))
375 ;; Return 1 if the operand is either a non-special register or can be used
376 ;; as the operand of a `mode' add insn.
377 (define_predicate "add_operand"
378 (if_then_else (match_code "const_int")
379 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
380 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')")
381 (match_operand 0 "gpc_reg_operand")))
383 ;; Return 1 if OP is a constant but not a valid add_operand.
384 (define_predicate "non_add_cint_operand"
385 (and (match_code "const_int")
386 (match_test "!CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
387 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')")))
389 ;; Return 1 if the operand is a non-special register or a constant that
390 ;; can be used as the operand of an OR or XOR.
391 (define_predicate "logical_operand"
392 (match_code "reg,subreg,const_int,const_double")
394 HOST_WIDE_INT opl, oph;
396 if (gpc_reg_operand (op, mode))
399 if (GET_CODE (op) == CONST_INT)
401 opl = INTVAL (op) & GET_MODE_MASK (mode);
403 if (HOST_BITS_PER_WIDE_INT <= 32
404 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
407 else if (GET_CODE (op) == CONST_DOUBLE)
409 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
412 opl = CONST_DOUBLE_LOW (op);
413 oph = CONST_DOUBLE_HIGH (op);
420 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
421 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
424 ;; Return 1 if op is a constant that is not a logical operand, but could
425 ;; be split into one.
426 (define_predicate "non_logical_cint_operand"
427 (and (match_code "const_int,const_double")
428 (and (not (match_operand 0 "logical_operand"))
429 (match_operand 0 "reg_or_logical_cint_operand"))))
431 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask (no
432 ;; more than two 1->0 or 0->1 transitions). Reject all ones and all
433 ;; zeros, since these should have been optimized away and confuse the
434 ;; making of MB and ME.
435 (define_predicate "mask_operand"
436 (match_code "const_int")
438 HOST_WIDE_INT c, lsb;
442 /* Fail in 64-bit mode if the mask wraps around because the upper
443 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
444 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
447 /* We don't change the number of transitions by inverting,
448 so make sure we start with the LS bit zero. */
452 /* Reject all zeros or all ones. */
456 /* Find the first transition. */
459 /* Invert to look for a second transition. */
462 /* Erase first transition. */
465 /* Find the second transition (if any). */
468 /* Match if all the bits above are 1's (or c is zero). */
472 ;; Return 1 for the PowerPC64 rlwinm corner case.
473 (define_predicate "mask_operand_wrap"
474 (match_code "const_int")
476 HOST_WIDE_INT c, lsb;
480 if ((c & 0x80000001) != 0x80000001)
494 ;; Return 1 if the operand is a constant that is a PowerPC64 mask (no more
495 ;; than one 1->0 or 0->1 transitions). Reject all zeros, since zero
496 ;; should have been optimized away and confuses the making of MB and ME.
497 (define_predicate "mask64_operand"
498 (match_code "const_int")
500 HOST_WIDE_INT c, lsb;
504 /* Reject all zeros. */
508 /* We don't change the number of transitions by inverting,
509 so make sure we start with the LS bit zero. */
513 /* Find the transition, and check that all bits above are 1's. */
516 /* Match if all the bits above are 1's (or c is zero). */
520 ;; Like mask64_operand, but allow up to three transitions. This
521 ;; predicate is used by insn patterns that generate two rldicl or
522 ;; rldicr machine insns.
523 (define_predicate "mask64_2_operand"
524 (match_code "const_int")
526 return mask64_1or2_operand (op, mode, false);
529 ;; Return 1 if the operand is either a non-special register or a constant
530 ;; that can be used as the operand of a PowerPC64 logical AND insn.
531 (define_predicate "and64_operand"
532 (ior (match_operand 0 "mask64_operand")
533 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
534 (match_operand 0 "gpc_reg_operand")
535 (match_operand 0 "logical_operand"))))
537 ;; Like and64_operand, but also match constants that can be implemented
538 ;; with two rldicl or rldicr insns.
539 (define_predicate "and64_2_operand"
540 (ior (and (match_code "const_int")
541 (match_test "mask64_1or2_operand (op, mode, true)"))
542 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
543 (match_operand 0 "gpc_reg_operand")
544 (match_operand 0 "logical_operand"))))
546 ;; Return 1 if the operand is either a non-special register or a
547 ;; constant that can be used as the operand of a logical AND.
548 (define_predicate "and_operand"
549 (ior (match_operand 0 "mask_operand")
550 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
551 (match_operand 0 "gpc_reg_operand")
552 (match_operand 0 "logical_operand"))))
554 ;; Return 1 if the operand is a general non-special register or memory operand.
555 (define_predicate "reg_or_mem_operand"
556 (if_then_else (match_code "mem")
557 (ior (match_operand 0 "memory_operand")
558 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
559 (match_operand 0 "volatile_mem_operand")))
560 (match_operand 0 "gpc_reg_operand")))
562 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
563 (define_predicate "reg_or_none500mem_operand"
564 (if_then_else (match_code "mem")
565 (and (match_test "!TARGET_E500_DOUBLE")
566 (ior (match_operand 0 "memory_operand")
567 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
568 (match_operand 0 "volatile_mem_operand"))))
569 (match_operand 0 "gpc_reg_operand")))
571 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
572 (define_predicate "zero_reg_mem_operand"
573 (ior (match_operand 0 "zero_fp_constant")
574 (match_operand 0 "reg_or_mem_operand")))
576 ;; Return 1 if the operand is a general register or memory operand without
577 ;; pre_inc or pre_dec, which produces invalid form of PowerPC lwa
579 (define_predicate "lwa_operand"
580 (match_code "reg,subreg,mem")
584 if (reload_completed && GET_CODE (inner) == SUBREG)
585 inner = SUBREG_REG (inner);
587 return gpc_reg_operand (inner, mode)
588 || (memory_operand (inner, mode)
589 && GET_CODE (XEXP (inner, 0)) != PRE_INC
590 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
591 && (GET_CODE (XEXP (inner, 0)) != PLUS
592 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
593 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
596 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
597 (define_predicate "symbol_ref_operand"
598 (and (match_code "symbol_ref")
599 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
600 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
602 ;; Return 1 if op is an operand that can be loaded via the GOT.
603 ;; or non-special register register field no cr0
604 (define_predicate "got_operand"
605 (match_code "symbol_ref,const,label_ref"))
607 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
608 ;; excluding labels involving addition.
609 (define_predicate "got_no_const_operand"
610 (match_code "symbol_ref,label_ref"))
612 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
613 (define_predicate "rs6000_tls_symbol_ref"
614 (and (match_code "symbol_ref")
615 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
617 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
618 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
619 (define_predicate "call_operand"
620 (if_then_else (match_code "reg")
621 (match_test "REGNO (op) == LINK_REGISTER_REGNUM
622 || REGNO (op) == COUNT_REGISTER_REGNUM
623 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
624 (match_code "symbol_ref")))
626 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
628 (define_predicate "current_file_function_operand"
629 (and (match_code "symbol_ref")
630 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
631 && (SYMBOL_REF_LOCAL_P (op)
632 || (op == XEXP (DECL_RTL (current_function_decl),
635 ;; Return 1 if this operand is a valid input for a move insn.
636 (define_predicate "input_operand"
637 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
638 const_double,const_vector,const_int,plus")
640 /* Memory is always valid. */
641 if (memory_operand (op, mode))
644 /* For floating-point, easy constants are valid. */
645 if (GET_MODE_CLASS (mode) == MODE_FLOAT
647 && easy_fp_constant (op, mode))
650 /* Allow any integer constant. */
651 if (GET_MODE_CLASS (mode) == MODE_INT
652 && (GET_CODE (op) == CONST_INT
653 || GET_CODE (op) == CONST_DOUBLE))
656 /* Allow easy vector constants. */
657 if (GET_CODE (op) == CONST_VECTOR
658 && easy_vector_constant (op, mode))
661 /* For floating-point or multi-word mode, the only remaining valid type
663 if (GET_MODE_CLASS (mode) == MODE_FLOAT
664 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
665 return register_operand (op, mode);
667 /* The only cases left are integral modes one word or smaller (we
668 do not get called for MODE_CC values). These can be in any
670 if (register_operand (op, mode))
673 /* A SYMBOL_REF referring to the TOC is valid. */
674 if (legitimate_constant_pool_address_p (op))
677 /* A constant pool expression (relative to the TOC) is valid */
678 if (toc_relative_expr_p (op))
681 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
683 if (DEFAULT_ABI == ABI_V4
684 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
685 && small_data_operand (op, Pmode))
691 ;; Return true if OP is an invalid SUBREG operation on the e500.
692 (define_predicate "rs6000_nonimmediate_operand"
693 (match_code "reg,subreg,mem")
695 if (TARGET_E500_DOUBLE
696 && GET_CODE (op) == SUBREG
697 && invalid_e500_subreg (op, mode))
700 return nonimmediate_operand (op, mode);
703 ;; Return true if operand is boolean operator.
704 (define_predicate "boolean_operator"
705 (match_code "and,ior,xor"))
707 ;; Return true if operand is OR-form of boolean operator.
708 (define_predicate "boolean_or_operator"
709 (match_code "ior,xor"))
711 ;; Return true if operand is MIN or MAX operator.
712 (define_predicate "min_max_operator"
713 (match_code "smin,smax,umin,umax"))
715 ;; Return 1 if OP is a comparison operation that is valid for a branch
716 ;; instruction. We check the opcode against the mode of the CC value.
717 ;; validate_condition_mode is an assertion.
718 (define_predicate "branch_comparison_operator"
719 (and (match_operand 0 "comparison_operator")
720 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
721 (match_test "validate_condition_mode (GET_CODE (op),
722 GET_MODE (XEXP (op, 0))),
725 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
726 ;; it must be a positive comparison.
727 (define_predicate "scc_comparison_operator"
728 (and (match_operand 0 "branch_comparison_operator")
729 (match_code "eq,lt,gt,ltu,gtu,unordered")))
731 ;; Return 1 if OP is a comparison operation that is valid for a branch
732 ;; insn, which is true if the corresponding bit in the CC register is set.
733 (define_predicate "branch_positive_comparison_operator"
734 (and (match_operand 0 "branch_comparison_operator")
735 (match_code "eq,lt,gt,ltu,gtu,unordered")))
737 ;; Return 1 is OP is a comparison operation that is valid for a trap insn.
738 (define_predicate "trap_comparison_operator"
739 (and (match_operand 0 "comparison_operator")
740 (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu")))
742 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
743 (define_predicate "load_multiple_operation"
744 (match_code "parallel")
746 int count = XVECLEN (op, 0);
747 unsigned int dest_regno;
751 /* Perform a quick check so we don't blow up below. */
753 || GET_CODE (XVECEXP (op, 0, 0)) != SET
754 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
755 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
758 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
759 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
761 for (i = 1; i < count; i++)
763 rtx elt = XVECEXP (op, 0, i);
765 if (GET_CODE (elt) != SET
766 || GET_CODE (SET_DEST (elt)) != REG
767 || GET_MODE (SET_DEST (elt)) != SImode
768 || REGNO (SET_DEST (elt)) != dest_regno + i
769 || GET_CODE (SET_SRC (elt)) != MEM
770 || GET_MODE (SET_SRC (elt)) != SImode
771 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
772 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
773 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
774 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
781 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
782 ;; The second vector element is a CLOBBER.
783 (define_predicate "store_multiple_operation"
784 (match_code "parallel")
786 int count = XVECLEN (op, 0) - 1;
787 unsigned int src_regno;
791 /* Perform a quick check so we don't blow up below. */
793 || GET_CODE (XVECEXP (op, 0, 0)) != SET
794 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
795 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
798 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
799 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
801 for (i = 1; i < count; i++)
803 rtx elt = XVECEXP (op, 0, i + 1);
805 if (GET_CODE (elt) != SET
806 || GET_CODE (SET_SRC (elt)) != REG
807 || GET_MODE (SET_SRC (elt)) != SImode
808 || REGNO (SET_SRC (elt)) != src_regno + i
809 || GET_CODE (SET_DEST (elt)) != MEM
810 || GET_MODE (SET_DEST (elt)) != SImode
811 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
812 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
813 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
814 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
821 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
823 (define_predicate "save_world_operation"
824 (match_code "parallel")
829 int count = XVECLEN (op, 0);
835 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
836 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
839 for (i=1; i <= 18; i++)
841 elt = XVECEXP (op, 0, index++);
842 if (GET_CODE (elt) != SET
843 || GET_CODE (SET_DEST (elt)) != MEM
844 || ! memory_operand (SET_DEST (elt), DFmode)
845 || GET_CODE (SET_SRC (elt)) != REG
846 || GET_MODE (SET_SRC (elt)) != DFmode)
850 for (i=1; i <= 12; i++)
852 elt = XVECEXP (op, 0, index++);
853 if (GET_CODE (elt) != SET
854 || GET_CODE (SET_DEST (elt)) != MEM
855 || GET_CODE (SET_SRC (elt)) != REG
856 || GET_MODE (SET_SRC (elt)) != V4SImode)
860 for (i=1; i <= 19; i++)
862 elt = XVECEXP (op, 0, index++);
863 if (GET_CODE (elt) != SET
864 || GET_CODE (SET_DEST (elt)) != MEM
865 || ! memory_operand (SET_DEST (elt), Pmode)
866 || GET_CODE (SET_SRC (elt)) != REG
867 || GET_MODE (SET_SRC (elt)) != Pmode)
871 elt = XVECEXP (op, 0, index++);
872 if (GET_CODE (elt) != SET
873 || GET_CODE (SET_DEST (elt)) != MEM
874 || ! memory_operand (SET_DEST (elt), Pmode)
875 || GET_CODE (SET_SRC (elt)) != REG
876 || REGNO (SET_SRC (elt)) != CR2_REGNO
877 || GET_MODE (SET_SRC (elt)) != Pmode)
880 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
881 || GET_CODE (XVECEXP (op, 0, index++)) != USE
882 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
887 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
889 (define_predicate "restore_world_operation"
890 (match_code "parallel")
895 int count = XVECLEN (op, 0);
901 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
902 || GET_CODE (XVECEXP (op, 0, index++)) != USE
903 || GET_CODE (XVECEXP (op, 0, index++)) != USE
904 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
907 elt = XVECEXP (op, 0, index++);
908 if (GET_CODE (elt) != SET
909 || GET_CODE (SET_SRC (elt)) != MEM
910 || ! memory_operand (SET_SRC (elt), Pmode)
911 || GET_CODE (SET_DEST (elt)) != REG
912 || REGNO (SET_DEST (elt)) != CR2_REGNO
913 || GET_MODE (SET_DEST (elt)) != Pmode)
916 for (i=1; i <= 19; i++)
918 elt = XVECEXP (op, 0, index++);
919 if (GET_CODE (elt) != SET
920 || GET_CODE (SET_SRC (elt)) != MEM
921 || ! memory_operand (SET_SRC (elt), Pmode)
922 || GET_CODE (SET_DEST (elt)) != REG
923 || GET_MODE (SET_DEST (elt)) != Pmode)
927 for (i=1; i <= 12; i++)
929 elt = XVECEXP (op, 0, index++);
930 if (GET_CODE (elt) != SET
931 || GET_CODE (SET_SRC (elt)) != MEM
932 || GET_CODE (SET_DEST (elt)) != REG
933 || GET_MODE (SET_DEST (elt)) != V4SImode)
937 for (i=1; i <= 18; i++)
939 elt = XVECEXP (op, 0, index++);
940 if (GET_CODE (elt) != SET
941 || GET_CODE (SET_SRC (elt)) != MEM
942 || ! memory_operand (SET_SRC (elt), DFmode)
943 || GET_CODE (SET_DEST (elt)) != REG
944 || GET_MODE (SET_DEST (elt)) != DFmode)
948 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
949 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
950 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
951 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
952 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
957 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
958 (define_predicate "vrsave_operation"
959 (match_code "parallel")
961 int count = XVECLEN (op, 0);
962 unsigned int dest_regno, src_regno;
966 || GET_CODE (XVECEXP (op, 0, 0)) != SET
967 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
968 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
971 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
972 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
974 if (dest_regno != VRSAVE_REGNO
975 && src_regno != VRSAVE_REGNO)
978 for (i = 1; i < count; i++)
980 rtx elt = XVECEXP (op, 0, i);
982 if (GET_CODE (elt) != CLOBBER
983 && GET_CODE (elt) != SET)
990 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
991 (define_predicate "mfcr_operation"
992 (match_code "parallel")
994 int count = XVECLEN (op, 0);
997 /* Perform a quick check so we don't blow up below. */
999 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1000 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1001 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1004 for (i = 0; i < count; i++)
1006 rtx exp = XVECEXP (op, 0, i);
1011 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1013 if (GET_CODE (src_reg) != REG
1014 || GET_MODE (src_reg) != CCmode
1015 || ! CR_REGNO_P (REGNO (src_reg)))
1018 if (GET_CODE (exp) != SET
1019 || GET_CODE (SET_DEST (exp)) != REG
1020 || GET_MODE (SET_DEST (exp)) != SImode
1021 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1023 unspec = SET_SRC (exp);
1024 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1026 if (GET_CODE (unspec) != UNSPEC
1027 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1028 || XVECLEN (unspec, 0) != 2
1029 || XVECEXP (unspec, 0, 0) != src_reg
1030 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1031 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1037 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1038 (define_predicate "mtcrf_operation"
1039 (match_code "parallel")
1041 int count = XVECLEN (op, 0);
1045 /* Perform a quick check so we don't blow up below. */
1047 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1048 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1049 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1051 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1053 if (GET_CODE (src_reg) != REG
1054 || GET_MODE (src_reg) != SImode
1055 || ! INT_REGNO_P (REGNO (src_reg)))
1058 for (i = 0; i < count; i++)
1060 rtx exp = XVECEXP (op, 0, i);
1064 if (GET_CODE (exp) != SET
1065 || GET_CODE (SET_DEST (exp)) != REG
1066 || GET_MODE (SET_DEST (exp)) != CCmode
1067 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1069 unspec = SET_SRC (exp);
1070 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1072 if (GET_CODE (unspec) != UNSPEC
1073 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1074 || XVECLEN (unspec, 0) != 2
1075 || XVECEXP (unspec, 0, 0) != src_reg
1076 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1077 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1083 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1084 (define_predicate "lmw_operation"
1085 (match_code "parallel")
1087 int count = XVECLEN (op, 0);
1088 unsigned int dest_regno;
1090 unsigned int base_regno;
1091 HOST_WIDE_INT offset;
1094 /* Perform a quick check so we don't blow up below. */
1096 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1097 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1098 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1101 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1102 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1105 || count != 32 - (int) dest_regno)
1108 if (legitimate_indirect_address_p (src_addr, 0))
1111 base_regno = REGNO (src_addr);
1112 if (base_regno == 0)
1115 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
1117 offset = INTVAL (XEXP (src_addr, 1));
1118 base_regno = REGNO (XEXP (src_addr, 0));
1123 for (i = 0; i < count; i++)
1125 rtx elt = XVECEXP (op, 0, i);
1128 HOST_WIDE_INT newoffset;
1130 if (GET_CODE (elt) != SET
1131 || GET_CODE (SET_DEST (elt)) != REG
1132 || GET_MODE (SET_DEST (elt)) != SImode
1133 || REGNO (SET_DEST (elt)) != dest_regno + i
1134 || GET_CODE (SET_SRC (elt)) != MEM
1135 || GET_MODE (SET_SRC (elt)) != SImode)
1137 newaddr = XEXP (SET_SRC (elt), 0);
1138 if (legitimate_indirect_address_p (newaddr, 0))
1143 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1145 addr_reg = XEXP (newaddr, 0);
1146 newoffset = INTVAL (XEXP (newaddr, 1));
1150 if (REGNO (addr_reg) != base_regno
1151 || newoffset != offset + 4 * i)
1158 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1159 (define_predicate "stmw_operation"
1160 (match_code "parallel")
1162 int count = XVECLEN (op, 0);
1163 unsigned int src_regno;
1165 unsigned int base_regno;
1166 HOST_WIDE_INT offset;
1169 /* Perform a quick check so we don't blow up below. */
1171 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1172 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1173 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1176 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1177 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1180 || count != 32 - (int) src_regno)
1183 if (legitimate_indirect_address_p (dest_addr, 0))
1186 base_regno = REGNO (dest_addr);
1187 if (base_regno == 0)
1190 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
1192 offset = INTVAL (XEXP (dest_addr, 1));
1193 base_regno = REGNO (XEXP (dest_addr, 0));
1198 for (i = 0; i < count; i++)
1200 rtx elt = XVECEXP (op, 0, i);
1203 HOST_WIDE_INT newoffset;
1205 if (GET_CODE (elt) != SET
1206 || GET_CODE (SET_SRC (elt)) != REG
1207 || GET_MODE (SET_SRC (elt)) != SImode
1208 || REGNO (SET_SRC (elt)) != src_regno + i
1209 || GET_CODE (SET_DEST (elt)) != MEM
1210 || GET_MODE (SET_DEST (elt)) != SImode)
1212 newaddr = XEXP (SET_DEST (elt), 0);
1213 if (legitimate_indirect_address_p (newaddr, 0))
1218 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1220 addr_reg = XEXP (newaddr, 0);
1221 newoffset = INTVAL (XEXP (newaddr, 1));
1225 if (REGNO (addr_reg) != base_regno
1226 || newoffset != offset + 4 * i)