1 ;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors.
2 ;; Copyright (C) 2003, 2004 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 2, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to the
18 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
19 ;; MA 02110-1301, USA.
21 (define_automaton "ppc40x,ppc40xiu")
22 (define_cpu_unit "bpu_40x,fpu_405" "ppc40x")
23 (define_cpu_unit "iu_40x" "ppc40xiu")
25 ;; PPC401 / PPC403 / PPC405 32-bit integer only IU BPU
26 ;; Embedded PowerPC controller
28 ;; Max issue two insns/cycle (includes one branch)
29 (define_insn_reservation "ppc403-load" 2
30 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
32 (eq_attr "cpu" "ppc403,ppc405"))
35 (define_insn_reservation "ppc403-store" 2
36 (and (eq_attr "type" "store,store_ux,store_u")
37 (eq_attr "cpu" "ppc403,ppc405"))
40 (define_insn_reservation "ppc403-integer" 1
41 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
42 var_shift_rotate,cntlz,exts")
43 (eq_attr "cpu" "ppc403,ppc405"))
46 (define_insn_reservation "ppc403-two" 1
47 (and (eq_attr "type" "two")
48 (eq_attr "cpu" "ppc403,ppc405"))
51 (define_insn_reservation "ppc403-three" 1
52 (and (eq_attr "type" "three")
53 (eq_attr "cpu" "ppc403,ppc405"))
54 "iu_40x,iu_40x,iu_40x")
56 (define_insn_reservation "ppc403-compare" 3
57 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
59 (eq_attr "cpu" "ppc403,ppc405"))
60 "iu_40x,nothing,bpu_40x")
62 (define_insn_reservation "ppc403-imul" 4
63 (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
64 (eq_attr "cpu" "ppc403"))
67 (define_insn_reservation "ppc405-imul" 5
68 (and (eq_attr "type" "imul,imul_compare")
69 (eq_attr "cpu" "ppc405"))
72 (define_insn_reservation "ppc405-imul2" 3
73 (and (eq_attr "type" "imul2")
74 (eq_attr "cpu" "ppc405"))
77 (define_insn_reservation "ppc405-imul3" 2
78 (and (eq_attr "type" "imul3")
79 (eq_attr "cpu" "ppc405"))
82 (define_insn_reservation "ppc403-idiv" 33
83 (and (eq_attr "type" "idiv")
84 (eq_attr "cpu" "ppc403,ppc405"))
87 (define_insn_reservation "ppc403-mfcr" 2
88 (and (eq_attr "type" "mfcr")
89 (eq_attr "cpu" "ppc403,ppc405"))
92 (define_insn_reservation "ppc403-mtcr" 3
93 (and (eq_attr "type" "mtcr")
94 (eq_attr "cpu" "ppc403,ppc405"))
97 (define_insn_reservation "ppc403-mtjmpr" 4
98 (and (eq_attr "type" "mtjmpr")
99 (eq_attr "cpu" "ppc403,ppc405"))
102 (define_insn_reservation "ppc403-mfjmpr" 2
103 (and (eq_attr "type" "mfjmpr")
104 (eq_attr "cpu" "ppc403,ppc405"))
107 (define_insn_reservation "ppc403-jmpreg" 1
108 (and (eq_attr "type" "jmpreg,branch,isync")
109 (eq_attr "cpu" "ppc403,ppc405"))
112 (define_insn_reservation "ppc403-cr" 2
113 (and (eq_attr "type" "cr_logical,delayed_cr")
114 (eq_attr "cpu" "ppc403,ppc405"))
117 (define_insn_reservation "ppc405-float" 11
118 (and (eq_attr "type" "fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,\
119 fpcompare,fp,dmul,sdiv,ddiv")
120 (eq_attr "cpu" "ppc405"))