1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001,2008, 2009 Free Software Foundation, Inc.
3 Contributed by picoChip Designs Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
55 #include "picochip-protos.h"
57 #include "insn-attr.h" /* For DFA state_t. */
58 #include "insn-config.h" /* Required by recog.h */
59 #include "insn-codes.h" /* For CODE_FOR_? */
60 #include "optabs.h" /* For GEN_FCN */
61 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
62 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
63 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
64 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
67 /* Target AE ISA information. */
68 enum picochip_dfa_type picochip_schedule_type;
70 bool picochip_has_mul_unit = false;
71 bool picochip_has_mac_unit = false;
73 /* targetm hook function prototypes. */
75 void picochip_asm_file_start (void);
76 void picochip_asm_file_end (void);
78 void picochip_init_libfuncs (void);
79 void picochip_reorg (void);
81 int picochip_arg_partial_bytes (CUMULATIVE_ARGS * p_cum,
82 enum machine_mode mode,
83 tree type, bool named);
85 int picochip_sched_lookahead (void);
86 int picochip_sched_issue_rate (void);
87 int picochip_sched_adjust_cost (rtx insn, rtx link,
88 rtx dep_insn, int cost);
89 int picochip_sched_reorder (FILE * file, int verbose, rtx * ready,
90 int *n_readyp, int clock);
92 void picochip_init_builtins (void);
93 rtx picochip_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
95 bool picochip_rtx_costs (rtx x, int code, int outer_code, int* total);
96 bool picochip_return_in_memory(const_tree type,
97 const_tree fntype ATTRIBUTE_UNUSED);
98 bool picochip_legitimate_address_p (enum machine_mode, rtx, bool);
100 rtx picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED, int incoming ATTRIBUTE_UNUSED);
101 rtx picochip_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
102 bool outgoing ATTRIBUTE_UNUSED);
104 picochip_secondary_reload (bool in_p,
105 rtx x ATTRIBUTE_UNUSED,
106 enum reg_class cla ATTRIBUTE_UNUSED,
107 enum machine_mode mode,
108 secondary_reload_info *sri);
110 picochip_asm_named_section (const char *name,
111 unsigned int flags ATTRIBUTE_UNUSED,
112 tree decl ATTRIBUTE_UNUSED);
114 static rtx picochip_static_chain (const_tree, bool);
116 /* Lookup table mapping a register number to the earliest containing
117 class. Used by REGNO_REG_CLASS. */
118 const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER] =
120 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
121 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
122 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
123 GR_REGS, FRAME_REGS, PTR_REGS, CONST_REGS,
124 ACC_REGS, CC_REGS, GR_REGS, GR_REGS
127 /* picoChip register names. */
128 const char *picochip_regnames[] = REGISTER_NAMES;
130 /* Define the maximum number of registers which may be used to pass
131 * parameters to functions. */
132 #define MAX_CALL_PARAMETER_REGS 6
135 /* Target scheduling information. */
137 /* Determine whether we run our final scheduling pass or not. We always
138 avoid the normal second scheduling pass. */
139 int picochip_flag_schedule_insns2;
141 /* Check if variable tracking needs to be run. */
142 int picochip_flag_var_tracking;
144 /* This flag indicates whether the next instruction to be output is a
145 VLIW continuation instruction. It is used to communicate between
146 final_prescan_insn and asm_output_opcode. */
147 static int picochip_vliw_continuation = 0;
149 /* This variable is used to communicate the current instruction
150 between final_prescan_insn and functions such as asm_output_opcode,
151 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
152 current instruction. */
153 static rtx picochip_current_prescan_insn;
155 static bool picochip_is_delay_slot_pending = 0;
157 /* When final_prescan_insn is called, it computes information about
158 the current VLIW packet, and stores it in this structure. When
159 instructions are output, this state is used to make sure that the
160 instructions are output in the correct way (e.g., which ALU to use,
161 whether a macro branch was ever previously a real branch, etc.). */
164 int contains_pico_alu_insn;
165 int contains_non_cc_alu_insn;
166 int num_alu_insns_so_far;
168 /* Record how many instructions are contained in the packet. */
169 int num_insns_in_packet;
171 /* There was a case for this to be more than 1 */
172 int num_cfi_labels_deferred;
173 char cfi_label_name[2][256]; /* Used to record the name of a CFI label
174 emitted inside a VLIW packet. */
175 char lm_label_name[256]; /* Used to record the name of an LM label. */
178 struct vliw_state picochip_current_vliw_state;
180 /* Save/restore recog_data. */
181 static int picochip_saved_which_alternative;
182 static struct recog_data picochip_saved_recog_data;
184 /* Determine which ALU to use for the instruction in
185 picochip_current_prescan_insn. */
186 static char picochip_get_vliw_alu_id (void);
188 /* Initialize the GCC target structure. */
190 #undef TARGET_ASM_FUNCTION_PROLOGUE
191 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
193 #undef TARGET_ASM_FUNCTION_EPILOGUE
194 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
196 #undef TARGET_ASM_INTERNAL_LABEL
197 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
199 #undef TARGET_ASM_GLOBALIZE_LABEL
200 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
202 #undef TARGET_ASM_BYTE_OP
203 #define TARGET_ASM_BYTE_OP ".initByte "
204 #undef TARGET_ASM_ALIGNED_HI_OP
205 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
206 #undef TARGET_ASM_UNALIGNED_HI_OP
207 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
208 #undef TARGET_ASM_ALIGNED_SI_OP
209 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
210 #undef TARGET_ASM_UNALIGNED_SI_OP
211 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
213 #undef TARGET_INIT_BUILTINS
214 #define TARGET_INIT_BUILTINS picochip_init_builtins
216 #undef TARGET_EXPAND_BUILTIN
217 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
219 #undef TARGET_RTX_COSTS
220 #define TARGET_RTX_COSTS picochip_rtx_costs
222 #undef TARGET_SCHED_ISSUE_RATE
223 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
225 #undef TARGET_SCHED_REORDER
226 #define TARGET_SCHED_REORDER picochip_sched_reorder
228 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
229 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
230 picochip_sched_lookahead
232 #undef TARGET_SCHED_ADJUST_COST
233 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
235 #undef TARGET_ASM_NAMED_SECTION
236 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
238 #undef TARGET_HAVE_NAMED_SECTIONS
239 #define TARGET_HAVE_NAMED_SECTIONS 1
241 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
242 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
244 #undef TARGET_INIT_LIBFUNCS
245 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
247 #undef TARGET_ASM_FILE_START
248 #define TARGET_ASM_FILE_START picochip_asm_file_start
250 #undef TARGET_ASM_FILE_END
251 #define TARGET_ASM_FILE_END picochip_asm_file_end
253 #undef TARGET_MACHINE_DEPENDENT_REORG
254 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
256 #undef TARGET_ARG_PARTIAL_BYTES
257 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
259 #undef TARGET_PROMOTE_FUNCTION_MODE
260 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
261 #undef TARGET_PROMOTE_PROTOTYPES
262 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
264 /* Target support for Anchored Addresses optimization */
265 #undef TARGET_MIN_ANCHOR_OFFSET
266 #define TARGET_MIN_ANCHOR_OFFSET 0
267 #undef TARGET_MAX_ANCHOR_OFFSET
268 #define TARGET_MAX_ANCHOR_OFFSET 7
269 #undef TARGET_ASM_OUTPUT_ANCHOR
270 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
272 #undef TARGET_FUNCTION_VALUE
273 #define TARGET_FUNCTION_VALUE picochip_function_value
275 #undef TARGET_LIBGCC_CMP_RETURN_MODE
276 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
279 #undef TARGET_LEGITIMATE_ADDRESS_P
280 #define TARGET_LEGITIMATE_ADDRESS_P picochip_legitimate_address_p
282 /* Loading and storing QImode values to and from memory
283 usually requires a scratch register. */
284 #undef TARGET_SECONDARY_RELOAD
285 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
286 #undef DONT_USE_BUILTIN_SETJMP
287 #define DONT_USE_BUILTIN_SETJMP 1
289 /* How Large Values are Returned */
291 #undef TARGET_RETURN_IN_MEMORY
292 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
294 #undef TARGET_STATIC_CHAIN
295 #define TARGET_STATIC_CHAIN picochip_static_chain
297 struct gcc_target targetm = TARGET_INITIALIZER;
300 /* Only return a value in memory if it is greater than 4 bytes.
301 int_size_in_bytes returns -1 for variable size objects, which go in
302 memory always. The cast to unsigned makes -1 > 8. */
305 picochip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
307 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 4);
310 /* Allow certain command options to be overriden. */
312 picochip_override_options (void)
314 /* If we are optimizing for stack, dont let inliner to inline functions
315 that could potentially increase stack size.*/
316 if (flag_conserve_stack)
318 PARAM_VALUE (PARAM_LARGE_STACK_FRAME) = 0;
319 PARAM_VALUE (PARAM_STACK_FRAME_GROWTH) = 0;
322 /* Turn off the elimination of unused types. The elaborator
323 generates various interesting types to represent constants,
324 generics, and so on, and it is useful to retain this information
325 in the debug output. The increased size of the debug information
326 is not really an issue for us. */
327 flag_eliminate_unused_debug_types = 0;
329 /* Even if the user specifies a -fno-omit-frame-pointer on the
330 command line, we still want to go ahead and omit frame pointer
331 usages, since we dont really have a frame pointer register.
332 So, all accesses to FP need to be converted to accesses off
334 flag_omit_frame_pointer = 1;
336 /* Turning on anchored addresses by default. This is an optimization
337 that could decrease the code size by placing anchors in data and
338 accessing offsets from the anchor for file local data variables.
339 This isnt the default at O2 as yet. */
340 flag_section_anchors = 1;
342 /* Turn off the second scheduling pass, and move it to
343 picochip_reorg, to avoid having the second jump optimisation
344 trash the instruction modes (e.g., instructions are changed to
345 TImode to mark the beginning of cycles). Two types of DFA
346 scheduling are possible: space and speed. In both cases,
347 instructions are reordered to avoid stalls (e.g., memory loads
348 stall for one cycle). Speed scheduling will also enable VLIW
349 instruction packing. VLIW instructions use more code space, so
350 VLIW scheduling is disabled when scheduling for size. */
351 picochip_flag_schedule_insns2 = flag_schedule_insns_after_reload;
352 flag_schedule_insns_after_reload = 0;
353 if (picochip_flag_schedule_insns2)
357 picochip_schedule_type = DFA_TYPE_SPACE;
360 picochip_schedule_type = DFA_TYPE_SPEED;
361 flag_delayed_branch = 0;
366 picochip_schedule_type = DFA_TYPE_NONE;
368 /* Ensure that the debug level is always at least -g2. The flow
369 analyser works at its best if it always has debug
370 information. DWARF is non-intrusive, so it makes no difference to
371 code quality if debug is always enabled. */
372 if (debug_info_level < DINFO_LEVEL_NORMAL)
374 debug_info_level = DINFO_LEVEL_NORMAL;
375 write_symbols = DWARF2_DEBUG;
378 /* Options of the form -mae=mac, and so on will be substituted by
379 the compiler driver for the appropriate byte access and multiply
380 unit ISA options. Any unrecognised AE types will end up being
381 passed to the compiler, which should reject them as invalid. */
382 if (picochip_ae_type_string != NULL)
383 error ("invalid AE type specified (%s)\n", picochip_ae_type_string);
385 /* Override any specific capabilities of the instruction set. These
386 take precedence over any capabilities inferred from the AE type,
387 regardless of where the options appear on the command line. */
388 if (picochip_mul_type_string == NULL)
390 /* Default to MEM-type multiply, for historical compatibility. */
391 picochip_has_mac_unit = false;
392 picochip_has_mul_unit = true;
396 picochip_has_mac_unit = false;
397 picochip_has_mul_unit = false;
399 if (strcmp (picochip_mul_type_string, "mul") == 0)
400 picochip_has_mul_unit = true;
401 else if (strcmp (picochip_mul_type_string, "mac") == 0)
402 picochip_has_mac_unit = true;
403 else if (strcmp (picochip_mul_type_string, "none") == 0)
404 { /* Do nothing. Unit types already set to false. */ }
406 error ("Invalid mul type specified (%s) - expected mac, mul or none",
407 picochip_mul_type_string);
413 /* Initialise the library functions to handle arithmetic on some of
416 picochip_init_libfuncs (void)
419 set_optab_libfunc (ashr_optab, DImode, "__ashrdi3");
420 set_optab_libfunc (ashl_optab, DImode, "__ashldi3");
421 set_optab_libfunc (lshr_optab, DImode, "__lshrdi3");
423 /* 64-bit signed multiplication. */
424 set_optab_libfunc (smul_optab, DImode, "__muldi3");
426 /* Signed division */
427 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
428 set_optab_libfunc (sdiv_optab, DImode, "__divdi3");
431 set_optab_libfunc (smod_optab, HImode, "__modhi3");
432 set_optab_libfunc (smod_optab, DImode, "__moddi3");
434 /* 32-bit count leading Zeros*/
435 set_optab_libfunc (clz_optab, SImode, "_clzsi2");
437 /* 64-bit comparison */
438 set_optab_libfunc (ucmp_optab, DImode, "__ucmpdi2");
439 set_optab_libfunc (cmp_optab, DImode, "__cmpdi2");
441 /* 64-bit addition and subtraction*/
442 set_optab_libfunc (add_optab, DImode, "_adddi3");
443 set_optab_libfunc (sub_optab, DImode, "_subdi3");
446 /* Return the register class for letter C. */
448 picochip_reg_class_from_letter (unsigned c)
466 pico_leaf_reg_alloc_order[] = LEAF_REG_ALLOC_ORDER;
468 pico_nonleaf_reg_alloc_order[] = REG_ALLOC_ORDER;
471 picochip_order_regs_for_local_alloc (void)
473 /* We change the order for leaf functions alone. We put r12 at
474 the end since using it will prevent us to combine stw/ldws to
475 stl/ldl and it gives no benefit. In non-leaf functions, we
476 would anyway saveup/restore r12, so it makes sense to use it.*/
478 if (leaf_function_p())
480 memcpy ((char *)reg_alloc_order, (const char *) pico_leaf_reg_alloc_order,
481 FIRST_PSEUDO_REGISTER * sizeof (int));
485 memcpy ((char *)reg_alloc_order, (const char *) pico_nonleaf_reg_alloc_order,
486 FIRST_PSEUDO_REGISTER * sizeof (int));
490 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
492 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value, unsigned c)
497 case 'I': /* 4 bits signed. */
498 return value + 8 < 16;
499 case 'J': /* 4 bits unsigned. */
501 case 'K': /* 8 bits signed. */
502 return value + 128 < 256;
503 case 'M': /* 4-bit magnitude. */
504 return abs (value) < 16;
505 case 'N': /* 10 bits signed. */
506 return value + 512 > 1024;
507 case 'O': /* 16 bits signed. */
508 return value + 32768 < 65536;
509 default: /* Unknown letter. */
514 /* Stack utility functions. */
516 picochip_return_addr_rtx(int count, rtx frameaddr ATTRIBUTE_UNUSED)
519 return gen_rtx_REG (Pmode, LINK_REGNUM);
525 /* Emit a set of parallel register expressions used to store
526 blockmode values to pass to functions. */
528 picochip_emit_register_parallel (int size_in_units, int offset)
532 rtx vector[MAX_CALL_PARAMETER_REGS];
536 /* Compute the base register, and number of required registers. */
537 base_reg = offset / 2;
538 num_regs = size_in_units / 2;
539 if (size_in_units % 2 == 1)
542 /* Emit a register for each part of the block mode value to be
543 passed in a register. */
544 for (i = 0; i < num_regs; i++)
545 vector[i] = gen_rtx_EXPR_LIST (VOIDmode,
546 gen_rtx_REG (HImode, base_reg + i),
548 result = gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (num_regs, vector));
554 /* Emit an instruction to allocate a suitable amount of space on the
555 stack, by decrementing the stack pointer. */
557 picochip_emit_stack_allocate (int adjustment)
560 rtx stack_pointer_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
562 /* Use an addition of a negative value. */
563 insn = emit_insn (gen_addhi3 (stack_pointer_reg, stack_pointer_reg,
564 GEN_INT (-adjustment)));
566 /* Make the instruction frame related. Also add an expression note,
567 so that the correct Dwarf information is generated (see documention
568 for RTX_FRAME_RELATED_P for more details). */
569 RTX_FRAME_RELATED_P (insn) = 1;
571 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
572 gen_rtx_SET (VOIDmode, stack_pointer_reg,
573 gen_rtx_PLUS (Pmode, stack_pointer_reg,
574 GEN_INT (-adjustment))),
579 /* Emit an instruction to save a register of the given mode. The
580 offset at which to save the register is given relative to the stack
583 picochip_emit_save_register (rtx reg, int offset)
585 rtx stack_pointer, address, mem, insn;
587 stack_pointer = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
589 address = gen_rtx_PLUS (Pmode, stack_pointer, GEN_INT (offset));
591 mem = gen_rtx_MEM (GET_MODE (reg), address);
593 insn = emit_move_insn (mem, reg);
594 RTX_FRAME_RELATED_P (insn) = 1;
596 /* For modes other than HImode, create a note explaining that
597 multiple registers have been saved. This allows the correct DWARF
598 call frame information to be generated. */
599 switch (GET_MODE (reg))
602 /* The RTL is sufficient to explain HImode register saves. */
606 /* SImode must be broken down into parallel HImode register saves. */
614 gen_rtx_PLUS (Pmode, stack_pointer,
616 gen_rtx_REG (HImode, REGNO (reg)));
617 RTX_FRAME_RELATED_P (RTVEC_ELT (p, 0)) = 1;
620 gen_rtx_SET (HImode, gen_rtx_MEM (HImode,
625 gen_rtx_REG (HImode, REGNO (reg) + 1));
626 RTX_FRAME_RELATED_P (RTVEC_ELT (p, 1)) = 1;
629 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
630 gen_rtx_PARALLEL (VOIDmode, p),
638 ("unexpected mode %s encountered in picochip_emit_save_register\n",
639 GET_MODE_NAME (GET_MODE (reg)));
644 /* Emit an instruction to restore a register of the given mode. The
645 offset from which to restore the register is given relative to the
648 picochip_emit_restore_register (rtx reg, int offset)
650 rtx stack_pointer, address, mem, insn;
652 stack_pointer = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
654 address = gen_rtx_PLUS (Pmode, stack_pointer, GEN_INT (offset));
656 mem = gen_rtx_MEM (GET_MODE (reg), address);
658 insn = emit_move_insn (reg, mem);
662 /* Check that the given byte offset is aligned to the given number of
665 picochip_is_aligned (int byte_offset, int bit_alignment)
667 int byte_alignment = bit_alignment / BITS_PER_UNIT;
668 return (byte_offset % byte_alignment) == 0;
671 /*****************************************************************************
674 * The following section contains code which controls how the stack is
677 * The stack is laid out as follows (high addresses first):
680 * Pretend arguments (ARG PTR)
684 * Outgoing arguments (SP)
686 * The (constant) offsets of the different areas must be calculated
687 * relative to the stack area immediately below, and aligned
688 * appropriately. For example, the frame offset is computed by
689 * determining the offset of the special register area, adding the
690 * size of the special register area, and then aligning the resulting
691 * offset correctly. In turn, the special register offset is computed
692 * from the general register offset, and so on. This enables the
693 * different offsets to change size and alignment, without requiring
694 * the code for other offset calculations to be rewritten.
696 * The argument pointer, and the frame pointer are eliminated wherever
697 * possible, by replacing them with a constant offset from the stack
698 * pointer. In the rare cases where constant offsets from the stack
699 * pointer cannot be computed, another register will be allocated to
700 * serve as the argument pointer, or the frame pointer.
702 * The save registers are stored at small offsets from the caller, to
703 * enable the more efficient SP-based ISA instructions to be used.
705 ****************************************************************************/
707 /* Compute the size of an argument in units. */
709 picochip_compute_arg_size (tree type, enum machine_mode mode)
711 int type_size_in_units = 0;
714 type_size_in_units = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
716 type_size_in_units = GET_MODE_SIZE (mode);
718 return type_size_in_units;
722 /* Determine where the next outgoing arg should be placed. */
724 picochip_function_arg (CUMULATIVE_ARGS cum, int mode, tree type,
725 int named ATTRIBUTE_UNUSED)
728 int type_align_in_units = 0;
729 int type_size_in_units;
731 int offset_overflow = 0;
733 /* VOIDmode is passed when computing the second argument to a `call'
734 pattern. This can be ignored. */
735 if (mode == VOIDmode)
738 /* Compute the alignment and size of the parameter. */
739 type_align_in_units =
740 picochip_get_function_arg_boundary (mode) / BITS_PER_UNIT;
741 type_size_in_units = picochip_compute_arg_size (type, mode);
743 /* Compute the correct offset (i.e., ensure that the offset meets
744 the alignment requirements). */
745 offset_overflow = cum % type_align_in_units;
746 if (offset_overflow == 0)
749 new_offset = (cum - offset_overflow) + type_align_in_units;
753 printf ("Function arg:\n");
754 printf (" Type valid: %s\n", (type ? "yes" : "no"));
755 printf (" Cumulative Value: %d\n", cum);
756 printf (" Mode: %s\n", GET_MODE_NAME (mode));
757 printf (" Type size: %i units\n", type_size_in_units);
758 printf (" Alignment: %i units\n", type_align_in_units);
759 printf (" New offset: %i\n", new_offset);
763 /* If the new offset is outside the register space, return. */
764 if (new_offset >= MAX_CALL_PARAMETER_REGS * 2)
767 /* If the end of the argument is outside the register space, then
768 the argument must overlap the register space. Return the first
769 available register. */
770 if ((new_offset + type_size_in_units) > (MAX_CALL_PARAMETER_REGS * 2))
771 return gen_rtx_REG (HImode, new_offset / 2);
773 /* Create a register of the required mode to hold the parameter. */
774 reg = new_offset / 2;
789 return gen_rtx_REG ((enum machine_mode) mode, reg);
793 /* Empty blockmode values can be passed as arguments (e.g.,
794 * empty structs). These require no registers
795 * whatsoever. Non-empty blockmode values are passed in a set
796 * of parallel registers. */
797 if (type_size_in_units == 0)
800 return picochip_emit_register_parallel (type_size_in_units, new_offset);
805 (0, "Defaulting to stack for %s register creation\n",
806 GET_MODE_NAME (mode));
814 /* Determine where the next incoming function argument will
815 appear. Normally, this works in exactly the same way as
816 picochip_function_arg, except when the function in question is a
817 varadic function. In this case, the incoming arguments all appear
818 to be passed on the stack (actually, some of the arguments are
819 passed in registers, which are then pushed onto the stack by the
820 function prologue). */
822 picochip_incoming_function_arg (CUMULATIVE_ARGS cum, int mode,
823 tree type, int named)
829 return picochip_function_arg (cum, mode, type, named);
833 /* Gives the alignment boundary, in bits, of an argument with the
836 picochip_get_function_arg_boundary (enum machine_mode mode)
841 align = STACK_BOUNDARY;
843 align = GET_MODE_ALIGNMENT (mode);
845 if (align < PARM_BOUNDARY)
846 align = PARM_BOUNDARY;
852 /* Compute partial registers. */
854 picochip_arg_partial_bytes (CUMULATIVE_ARGS * p_cum, enum machine_mode mode,
855 tree type, bool named ATTRIBUTE_UNUSED)
857 int type_align_in_units = 0;
858 int type_size_in_units;
860 int offset_overflow = 0;
862 unsigned cum = *((unsigned *) p_cum);
864 /* VOIDmode is passed when computing the second argument to a `call'
865 pattern. This can be ignored. */
866 if (mode == VOIDmode)
869 /* Compute the alignment and size of the parameter. */
870 type_align_in_units =
871 picochip_get_function_arg_boundary (mode) / BITS_PER_UNIT;
872 type_size_in_units = picochip_compute_arg_size (type, mode);
874 /* Compute the correct offset (i.e., ensure that the offset meets
875 the alignment requirements). */
876 offset_overflow = cum % type_align_in_units;
877 if (offset_overflow == 0)
880 new_offset = (cum - offset_overflow) + type_align_in_units;
884 printf ("Partial function arg nregs:\n");
885 printf (" Type valid: %s\n", (type ? "yes" : "no"));
886 printf (" Cumulative Value: %d\n", cum);
887 printf (" Mode: %s\n", GET_MODE_NAME (mode));
888 printf (" Type size: %i units\n", type_size_in_units);
889 printf (" Alignment: %i units\n", type_align_in_units);
890 printf (" New offset: %i\n", new_offset);
894 /* If the new offset is outside the register space, return. */
895 if (new_offset >= (MAX_CALL_PARAMETER_REGS * 2))
898 /* If the end of the argument is outside the register space, then
899 the argument must overlap the register space. Return the number
900 of bytes which are passed in registers. */
901 if ((new_offset + type_size_in_units) > (MAX_CALL_PARAMETER_REGS * 2))
902 return ((MAX_CALL_PARAMETER_REGS * 2) - new_offset);
908 /* Advance the cumulative args counter, returning the new counter. */
910 picochip_arg_advance (const CUMULATIVE_ARGS cum, int mode,
911 tree type, int named ATTRIBUTE_UNUSED)
913 int type_align_in_units = 0;
914 int type_size_in_units;
916 int offset_overflow = 0;
918 /* VOIDmode is passed when computing the second argument to a `call'
919 pattern. This can be ignored. */
920 if (mode == VOIDmode)
923 /* Compute the alignment and size of the parameter. */
924 type_align_in_units =
925 picochip_get_function_arg_boundary (mode) / BITS_PER_UNIT;
926 type_size_in_units = picochip_compute_arg_size (type, mode);
928 /* Compute the correct offset (i.e., ensure that the offset meets
929 the alignment requirements). */
930 offset_overflow = cum % type_align_in_units;
931 if (offset_overflow == 0)
934 new_offset = (cum - offset_overflow) + type_align_in_units;
936 /* Advance past the last argument. */
937 new_offset += type_size_in_units;
943 /* Determine whether a register needs saving/restoring. It does if it
944 is live in a function, and isn't a call-used register. */
946 picochip_reg_needs_saving (int reg_num)
948 return df_regs_ever_live_p(reg_num) && !call_used_regs[reg_num];
951 /* Compute and return offset of the main frame. */
953 picochip_frame_byte_offset (void)
955 gcc_assert(picochip_is_aligned
956 (crtl->outgoing_args_size, BITS_PER_WORD));
958 return crtl->outgoing_args_size;
961 /* Return the size of the main frame. */
963 picochip_frame_size_in_bytes (void)
965 int frame_size = get_frame_size();
966 int stack_align = STACK_BOUNDARY/BITS_PER_UNIT;
967 if (!picochip_is_aligned (frame_size, STACK_BOUNDARY))
968 frame_size = frame_size + (stack_align - frame_size%stack_align);
969 gcc_assert(picochip_is_aligned (frame_size, STACK_BOUNDARY));
973 /* Compute and return the size (in bytes) of the register save/restore
974 area for the current function. This only includes the general
975 purpose registers - the special purpose stack pointer and link
976 registers are not included in this area. */
978 picochip_save_area_size_in_bytes (void)
980 int num_regs_to_save = 0;
983 /* Read through all the registers, determining which need to be saved. */
984 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
986 if (picochip_reg_needs_saving (i))
987 num_regs_to_save += 1;
990 return num_regs_to_save * UNITS_PER_WORD;
994 /* Compute and return offset of the save area base. */
996 picochip_save_area_byte_offset (void)
998 int base_offset = (picochip_frame_byte_offset () +
999 picochip_frame_size_in_bytes ());
1001 gcc_assert(picochip_is_aligned (base_offset, BITS_PER_WORD));
1007 /* Compute and return offset of the special register save area. This
1008 area can be found immediately above the normal save area. It must
1009 be aligned, to allow the registers to be saved and restored as a
1012 picochip_special_save_area_byte_offset (void)
1014 int byte_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
1015 int offset = (picochip_save_area_byte_offset () +
1016 picochip_save_area_size_in_bytes ());
1018 if ((offset % byte_alignment) != 0)
1019 offset = ((offset / byte_alignment) + 1) * byte_alignment;
1025 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1027 picochip_can_eliminate_link_sp_save (void)
1029 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1030 changing during optimizations phases. So, this function returns different
1031 values when called from initial_elimination_offset and then again when it
1032 is called from prologue/epilogue generation. This means that argument
1033 accesses become wrong. This wouldnt happen only if we were not using the
1034 stack at all. The following conditions ensures that.*/
1036 return (current_function_is_leaf &&
1037 !df_regs_ever_live_p(LINK_REGNUM) &&
1038 !df_regs_ever_live_p(STACK_POINTER_REGNUM) &&
1039 (picochip_special_save_area_byte_offset() == 0) &&
1040 (crtl->args.size == 0) &&
1041 (crtl->args.pretend_args_size == 0));
1044 /* Compute the size of the special reg save area (SP and LNK). If the
1045 SP/LNK registers don't need to be saved, this area can shrink to
1048 picochip_special_save_area_size_in_bytes (void)
1052 if (picochip_can_eliminate_link_sp_save ())
1055 return 2 * UNITS_PER_WORD;
1058 /* Return the number of pretend arguments. If this function is
1059 varadic, all the incoming arguments are effectively passed on the
1060 stack. If this function has real pretend arguments (caused by a
1061 value being passed partially on the stack and partially in
1062 registers), then return the number of registers used. */
1064 picochip_pretend_arg_area_size (void)
1067 if (crtl->args.pretend_args_size != 0)
1069 gcc_assert(crtl->args.pretend_args_size % 4 == 0);
1071 return crtl->args.pretend_args_size;
1073 else if (cfun->stdarg)
1080 /* Compute and return the offset of the pretend arguments. The pretend
1081 arguments are contiguous with the incoming arguments, and must be
1082 correctly aligned. */
1084 picochip_pretend_arg_area_byte_offset (void)
1086 int base_offset = 0;
1088 base_offset = (picochip_special_save_area_byte_offset () +
1089 picochip_special_save_area_size_in_bytes ());
1091 gcc_assert(picochip_is_aligned (base_offset, STACK_BOUNDARY));
1092 gcc_assert(picochip_is_aligned
1093 (base_offset + picochip_pretend_arg_area_size (), STACK_BOUNDARY));
1099 /* Compute and return the offset of the incoming arguments. If a
1100 static chain is in use, this will be passed just before the other
1101 arguments. This means that the pretend argument mechanism, used in
1102 variadic functions, doesn't work properly. Thus, static chains work
1103 on their own, as do variadic functions, but not the combination of
1104 the two. This isn't really a problem. */
1106 picochip_arg_area_byte_offset (void)
1108 int base_offset = (picochip_pretend_arg_area_byte_offset () +
1109 picochip_pretend_arg_area_size ());
1111 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1112 the alignment on a 32-bit boundary must be maintained. */
1113 if (cfun->static_chain_decl != NULL)
1115 gcc_assert (!cfun->stdarg);
1119 gcc_assert(picochip_is_aligned (base_offset, STACK_BOUNDARY));
1126 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED, int mode)
1129 /* Special case - only one register needed. */
1130 if (GET_MODE_CLASS (mode) == MODE_CC)
1133 /* We actually do not allocate acc0 ever. But, it seems like we need to
1134 make it look like a allocatable register for the dataflow checks to work
1135 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1140 /* General case - compute how much space in terms of units. */
1141 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1146 picochip_class_max_nregs (int class, int mode)
1148 int size = ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1150 if (class == ACC_REGS)
1153 if (GET_MODE_CLASS (mode) == MODE_CC)
1160 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1161 argument pointer) by replacing it with a constant offset from the
1162 main stack register. */
1164 initial_elimination_offset (int from, int to)
1166 int offset_from_sp = 0;
1168 if (FRAME_POINTER_REGNUM == from && STACK_POINTER_REGNUM == to)
1169 offset_from_sp = picochip_frame_byte_offset ();
1170 else if (ARG_POINTER_REGNUM == from && STACK_POINTER_REGNUM == to)
1171 offset_from_sp = picochip_pretend_arg_area_byte_offset ();
1175 return offset_from_sp;
1179 /* Compute and return the size of the incoming argument area. */
1181 picochip_arg_area_size_in_bytes (void)
1183 return crtl->args.size;
1186 /* Determine whether the given register is valid. When the strict mode
1187 is used, only hard registers are valid, otherwise any register is
1190 picochip_legitimate_address_register (rtx x, unsigned strict)
1193 /* Sanity check - non-registers shouldn't make it here, but... */
1194 if (REG != GET_CODE (x))
1198 return REGNO (x) < FIRST_NONHARD_REGISTER;
1204 /* Determine whether the given constant is in the range required for
1205 the given base register. */
1207 picochip_const_ok_for_base (enum machine_mode mode, int regno, int offset)
1209 HOST_WIDE_INT corrected_offset;
1211 if (GET_MODE_SIZE (mode) != 0)
1213 if (GET_MODE_SIZE(mode) <= 4)
1215 /* We used to allow incorrect offsets if strict is 0. But, this would
1216 then rely on reload doing the right thing. We have had problems
1217 there before, and on > 4.3 compiler, there are no benefits. */
1218 if (offset % GET_MODE_SIZE (mode) != 0)
1220 corrected_offset = offset / GET_MODE_SIZE (mode);
1224 if (offset % 4 != 0)
1226 corrected_offset = offset / 4;
1231 /* Default to the byte offset as supplied. */
1232 corrected_offset = offset;
1235 /* The offset from the base register can be different depending upon
1236 the base register. The stack/frame/argument pointer offsets can
1237 all be greater than a simple register-based offset. Note that the
1238 frame/argument pointer registers are actually eliminations of the
1239 stack pointer, so a value which is valid for an offset to, for
1240 example, the frame pointer, might be invalid for the stack
1241 pointer once the elimination has occurred. However, there is no
1242 need to handle this special case here, as the stack offset is
1243 always checked after elimination anyway, and the generated code
1244 seems to have identical performance. */
1245 if (regno == STACK_POINTER_REGNUM ||
1246 regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
1247 return picochip_const_ok_for_letter_p (corrected_offset, 'K');
1249 return picochip_const_ok_for_letter_p (corrected_offset, 'J');
1253 /* Determine whether a given rtx is a legitimate address for machine_mode
1254 MODE. STRICT is non-zero if we're being strict - any pseudo that
1255 is not a hard register must be a memory reference. */
1257 picochip_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
1261 switch (GET_CODE (x))
1264 valid = picochip_legitimate_address_register (x, strict);
1269 rtx base = XEXP (x, 0);
1270 rtx offset = XEXP (x, 1);
1272 valid = (REG == GET_CODE (base) &&
1273 REGNO_OK_FOR_BASE_P (REGNO(base)) &&
1274 picochip_legitimate_address_register (base, strict) &&
1275 CONST_INT == GET_CODE (offset) &&
1276 picochip_const_ok_for_base (mode, REGNO (base),
1282 /* The user can select whether a symbol can be used as a memory
1283 address. Typically, this will decrease execution time (no
1284 register load is required first), but will increase code size
1285 (because the symbol will be used several times, rather than
1286 loaded once into a register.*/
1287 valid = TARGET_SYMBOL_AS_ADDRESS;
1292 /* A constant memory address must be a (plus (symbol_ref)
1293 (const_int)), and is only allowed when the symbols are
1294 permitted addresses. */
1295 rtx inner = XEXP (x, 0);
1297 valid = (TARGET_SYMBOL_AS_ADDRESS &&
1298 PLUS == GET_CODE (inner) &&
1299 SYMBOL_REF == GET_CODE (XEXP (inner, 0)) &&
1300 CONST_INT == GET_CODE (XEXP (inner, 1)));
1314 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1316 picochip_symbol_offset (rtx operand)
1319 return (PLUS == GET_CODE (operand) &&
1320 SYMBOL_REF == GET_CODE (XEXP (operand, 0)) &&
1321 CONST_INT == GET_CODE (XEXP (operand, 1)));
1325 /* Assembly output. */
1327 /* The format here should match the format used in the output of
1328 symbol_ref's elsewhere in this file. */
1330 picochip_output_label (FILE * stream, const char name[])
1332 int is_cfi_label = (strncmp (name, "picoMark_LCFI", 13) == 0);
1334 /* If VLIW scheduling is in use, any Call Frame Information labels
1335 generated inside a packet must have their output deferred until
1336 the end of the packet. */
1337 if (picochip_schedule_type == DFA_TYPE_SPEED &&
1338 is_cfi_label && picochip_vliw_continuation)
1340 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
1342 internal_error ("LCFI labels have already been deferred.");
1344 strcpy (picochip_current_vliw_state.cfi_label_name[
1345 picochip_current_vliw_state.num_cfi_labels_deferred], name);
1346 picochip_current_vliw_state.num_cfi_labels_deferred++;
1350 assemble_name (stream, name);
1352 if (strncmp (name, "picoMark_", 9) == 0)
1353 fprintf (stream, "=\n");
1355 fprintf (stream, ":\n");
1361 /* The format here should match the format used in the output of
1362 symbol_ref's elsewhere in this file. */
1364 picochip_output_labelref (FILE * stream, const char name[])
1366 fprintf (stream, "_%s", name);
1370 picochip_weaken_label (FILE * stream, const char name[])
1372 fprintf (stream, ".weak ");
1373 assemble_name (stream, name);
1374 fprintf (stream, "\n");
1377 /* Return true if the given label (or label prefix) denotes a marker
1378 label which should be emitted in the form LABEL= */
1380 picochip_is_marker_prefix (const char *prefix)
1382 return (strcmp (prefix, "L") != 0 && strcmp (prefix, "LC") != 0
1383 && strcmp (prefix, "LP") != 0);
1387 picochip_output_internal_label (FILE * stream, const char *prefix,
1391 /* Emit different types of label, based upon their prefix. They
1392 are handled differently to allow the assembler to ensure that
1393 branch target labels are properly aligned, while other labels
1394 will only serve as code markers, not branch targets. Aligning
1395 labels unnecessarily can result in much code wastage. */
1396 if (picochip_is_marker_prefix (prefix))
1398 /* Special label marker. If it appears in the middle of a VLIW
1399 packet, defer it until the end of the packet. There has
1400 never been a need to handle more than one lm label at a time. */
1401 if (picochip_schedule_type == DFA_TYPE_SPEED &&
1402 (strcmp (prefix, "LM")) == 0 && picochip_vliw_continuation)
1404 if (strlen (picochip_current_vliw_state.lm_label_name) != 0)
1405 internal_error ("LM label has already been deferred.");
1407 sprintf (picochip_current_vliw_state.lm_label_name,
1408 "picoMark_%s%ld", prefix, num);
1413 fprintf (stream, "_picoMark_%s%ld=\n", prefix, num);
1420 fprintf (stream, "_%s%ld:\n", prefix, num);
1426 picochip_generate_internal_label (char *str, const char *prefix, long num)
1428 /* Two types of internal label can be generated: branch target
1429 labels and code marker labels. Branch target labels must always
1430 be aligned (since code will execute at these
1431 points). Differentiate between the two by prepending markers with
1432 a unique prefix, which can later be used in output_label to
1433 figure out which label syntax to use. */
1434 if (picochip_is_marker_prefix (prefix))
1435 sprintf (str, "picoMark_%s%ld", prefix, num);
1437 sprintf (str, "%s%ld", prefix, num);
1442 picochip_asm_output_anchor (rtx symbol)
1444 fprintf (asm_out_file, ".offsetData _%s, ",XSTR (symbol, 0));
1445 fprintf (asm_out_file, "+ " HOST_WIDE_INT_PRINT_DEC"\n",SYMBOL_REF_BLOCK_OFFSET(symbol));
1449 picochip_output_aligned_common (FILE * stream, const char *name,
1450 unsigned size, unsigned alignment)
1453 fprintf (stream, ".commonData ");
1454 assemble_name (stream, name);
1455 fprintf (stream, ", %u, %u\n", size, alignment / 8);
1456 picochip_output_global (stream, name);
1461 picochip_output_aligned_local (FILE * stream, const char *name,
1462 unsigned size, unsigned alignment)
1465 fprintf (stream, ".commonData ");
1466 assemble_name (stream, name);
1467 fprintf (stream, ", %u, %u\n", size, alignment / 8);
1472 picochip_output_global (FILE * stream, const char *name)
1474 fprintf (stream, ".global ");
1475 assemble_name (stream, name);
1476 fprintf (stream, "\n");
1479 /* Output an assembly language string. Output as a sequence of decimal
1480 numbers, followed by the literal string to make it obvious what the
1481 numbers represent. */
1483 picochip_output_ascii (FILE * file, const char *str, int length)
1487 fprintf (file, ".ascii ");
1489 for (i = 0; i < length; ++i)
1491 fprintf (file, "16#%hhx# ", (char) (str[i]));
1494 fprintf (file, " ; ");
1496 for (i = 0; i < length; ++i)
1503 fprintf (file, "\\n");
1506 fprintf (file, "\\t");
1509 fprintf (file, "\\0");
1512 fprintf (file, "%c", c);
1517 fprintf (file, "\n");
1521 /* Output the beginning of an ASM file. */
1523 picochip_asm_file_start (void)
1525 default_file_start ();
1527 fprintf (asm_out_file, "// picoChip ASM file\n");
1528 fprintf (asm_out_file, "//.file \"%s\"\n", main_input_filename);
1530 fprintf (asm_out_file, "// Has byte access: %s\n",
1531 (TARGET_HAS_BYTE_ACCESS ? "Yes" : "No"));
1533 if (TARGET_HAS_MUL_UNIT)
1534 fprintf (asm_out_file, "// Has multiply: Yes (Multiply unit)\n");
1535 else if (TARGET_HAS_MAC_UNIT)
1536 fprintf (asm_out_file, "// Has multiply: Yes (Mac unit)\n");
1538 fprintf (asm_out_file, "// Has multiply: No\n");
1540 /* Variable tracking should be run after all optimizations which change order
1541 of insns. It also needs a valid CFG. This can't be done in
1542 picochip_override_options, because flag_var_tracking is finalized after
1544 picochip_flag_var_tracking = flag_var_tracking;
1545 flag_var_tracking = 0;
1548 /* Output the end of an ASM file. */
1550 picochip_asm_file_end (void)
1552 /* Include a segment end to make it easy for PERL scripts to grab
1553 segments. This is now done by assembler*/
1555 fprintf (asm_out_file, "// End of picoChip ASM file\n");
1559 /* Output frame debug information to the given stream. */
1561 picochip_output_frame_debug (FILE * file)
1565 if (current_function_is_leaf)
1566 fprintf (file, "\t\t// Leaf function\n");
1568 fprintf (file, "\t\t// Non-leaf function\n");
1570 if (picochip_can_eliminate_link_sp_save ())
1571 fprintf (file, "\t\t// Link/fp save/restore can be eliminated\n");
1573 if (cfun->static_chain_decl != NULL)
1574 fprintf (file, "\t\t// Static chain in use\n");
1576 fprintf (file, "\t\t// Incoming argument size: %d bytes\n",
1577 picochip_arg_area_size_in_bytes ());
1578 fprintf (file, "\t\t// Incoming arg offset: %d\n",
1579 picochip_arg_area_byte_offset ());
1580 fprintf (file, "\t\t// Pretend arg size: %d\n",
1581 picochip_pretend_arg_area_size ());
1582 fprintf (file, "\t\t// Pretend arg offset (ARGP): %d\n",
1583 picochip_pretend_arg_area_byte_offset ());
1584 fprintf (file, "\t\t// Special reg area size: %d bytes\n",
1585 picochip_special_save_area_size_in_bytes ());
1586 fprintf (file, "\t\t// Special reg area offset: %d\n",
1587 picochip_special_save_area_byte_offset ());
1589 /* Output which registers are saved. */
1590 fprintf (file, "\t\t// Saved regs: ");
1591 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1593 if (picochip_reg_needs_saving (i))
1594 fprintf (file, "%s ", picochip_regnames[i]);
1596 fprintf (file, "\t\t\n");
1598 fprintf (file, "\t\t// Save area size: %d bytes\n",
1599 picochip_save_area_size_in_bytes ());
1600 fprintf (file, "\t\t// Save area offset: %d\n",
1601 picochip_save_area_byte_offset ());
1603 fprintf (file, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1604 fprintf (file, "\t\t// Frame offset (FP): %d\n",
1605 picochip_frame_byte_offset ());
1607 fprintf (file, "\t\t// Outgoing argument area size: %d bytes\n",
1608 crtl->outgoing_args_size);
1612 /* Output picoChip function prologue. This contains human-readable
1613 information about the function. */
1615 picochip_function_prologue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1617 /* Get the function's name, as described by its RTL. This may be
1618 different from the DECL_NAME name used in the source file. The
1619 real declaration name must be used, to ensure that the prologue
1620 emits the right information for the linker. */
1623 x = DECL_RTL (current_function_decl);
1624 gcc_assert (MEM_P (x));
1626 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1627 fnname = XSTR (x, 0);
1629 /* Note that the name of the function is given in the &_%s
1630 form. This matches the name of the function as used in labels,
1631 and function calls, and enables processCallGraph to match
1632 function calls to the name of the function, as defined here. */
1633 fprintf (file, "// picoChip Function Prologue : &_%s = %d bytes\n",
1634 fnname, picochip_arg_area_byte_offset ());
1636 picochip_output_frame_debug (file);
1637 fprintf (file, "\n");
1641 /* Output picoChip function epilogue. */
1643 picochip_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1648 x = DECL_RTL (current_function_decl);
1649 gcc_assert (MEM_P (x));
1651 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1652 fnname = XSTR (x, 0);
1653 fprintf (file, "\n// picoChip Function Epilogue : %s\n\n",
1657 /* Manipulate the asm output. Some machines only execute the code when
1658 there is actually a chance of needing it (e.g., FRV doesn't execute
1659 it if the scheduling pass wasn't used). We always execute it,
1660 simple to ensure that it is exercised more often, and bugs are more
1663 This function's prime reason for existence is to insert the VLIW
1664 separators where appropriate. The separators must be inserted
1665 before any comments which appear at the end of the file.
1669 picochip_asm_output_opcode (FILE * f, const char *ptr)
1673 /* Flag to specify when a VLIW continuation has been inserted onto
1674 the line. Continuations are either inserted before any comments,
1675 or before the end of the line is reached. The flag ensures that
1676 we don't insert continuations twice (i.e., at the comment and the
1678 int continuation_inserted = 0;
1680 /* If the instruction uses multiple lines (i.e., a new line
1681 character appears in the opcode), then ensure that no attempt is
1682 made to pack it into a VLIW. */
1683 if (strchr (ptr, '\n') != NULL && picochip_vliw_continuation)
1685 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s\n",
1689 /* If a delay slot is pending, output the directive to the assembler
1690 before the instruction. */
1691 if (picochip_is_delay_slot_pending)
1693 picochip_is_delay_slot_pending = 0;
1697 /* Keep going for entire opcode. All substitution performed ourselves. */
1702 /* Determine whether a VLIW continuation must be inserted before
1703 any comments, or the end of the opcode. A flag is set to show
1704 that we have inserted a continuation on this line, so that we
1705 don't try to insert another continuation when the end of the
1706 opcode is reached. The only other case for a continuation
1707 might have been a newline, but these aren't allowed in
1708 conjunction with VLIW continuations (see above code). */
1709 if (picochip_vliw_continuation &&
1710 !continuation_inserted &&
1711 ((c == '/' && (*ptr == '/')) || *ptr == '\0'))
1714 continuation_inserted = 1;
1717 /* Detect an explicit VLIW separator. */
1718 if (c == '%' && (*ptr == '|'))
1723 /* Detect the need for an ALU id operand. */
1724 else if (c == '%' && (*ptr == '#'))
1726 fputc (picochip_get_vliw_alu_id (), f);
1729 printf ("Generated ALU char at %s for insn %d\n", ptr,
1730 INSN_UID (picochip_current_prescan_insn));
1732 /* Skip past unwanted # */
1735 /* Detect the need for branch delay slot. */
1736 else if (c == '%' && (*ptr == '>'))
1738 /* Only emit delay slots (NOP's, or otherwise) when delay
1739 * slot scheduling has actually been enabled, otherwise VLIW
1740 * scheduling and delay slot scheduling output combine to
1741 * produce nasty effects. */
1742 if (flag_delayed_branch)
1744 if (dbr_sequence_length () == 0)
1745 fputs ("\n=->\tNOP", f);
1747 picochip_is_delay_slot_pending = 1;
1750 /* Skip past unwanted > */
1753 /* Detect any %digit specifiers. */
1754 else if (c == '%' && (*ptr >= '0' && *ptr <= '9'))
1757 picochip_print_operand (f, recog_data.operand[c], 0);
1758 while ((c = *ptr) >= '0' && c <= '9')
1761 /* Detect any %letterdigit specifiers. */
1762 else if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
1763 || (*ptr >= 'A' && *ptr <= 'Z')))
1765 int letter = *ptr++;
1772 output_asm_label (recog_data.operand[c]);
1776 output_address (recog_data.operand[c]);
1780 picochip_print_operand (f, recog_data.operand[c], letter);
1783 while ((c = *ptr) >= '0' && c <= '9')
1788 ("picochip_asm_output_opcode - can't output unknown operator %c\n",
1794 /* Reached the end of the packet. If any labels were deferred
1795 during output, emit them now. */
1796 if (!picochip_vliw_continuation)
1798 if (picochip_current_vliw_state.num_cfi_labels_deferred != 0)
1801 assemble_name (f, picochip_current_vliw_state.cfi_label_name[0]);
1803 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
1806 assemble_name (f, picochip_current_vliw_state.cfi_label_name[1]);
1811 if (strlen (picochip_current_vliw_state.lm_label_name) != 0)
1814 assemble_name (f, picochip_current_vliw_state.lm_label_name);
1819 /* Output an end-of-packet marker if requested. */
1820 if (!picochip_vliw_continuation &&
1821 TARGET_DEBUG && picochip_schedule_type == DFA_TYPE_SPEED)
1822 fprintf (f, "\n\t//-------------- End of VLIW packet -----------------");
1827 /* Function RTL expansion. */
1829 /* Expand the prologue into RTL. */
1831 picochip_expand_prologue (void)
1833 int stack_adjustment = 0;
1834 int special_save_offset = 0;
1835 int general_save_offset = 0;
1836 int reg_save_offset = 0;
1839 stack_adjustment = picochip_arg_area_byte_offset ();
1840 general_save_offset =
1841 -(stack_adjustment - picochip_save_area_byte_offset ());
1842 special_save_offset =
1843 -(stack_adjustment - picochip_special_save_area_byte_offset ());
1845 /* Save the link registers. We could try to save just one register
1846 here. This would reduce the amount of stack space required.
1847 There hasnt been a good reason to do that so far. */
1848 if (!picochip_can_eliminate_link_sp_save ())
1849 picochip_emit_save_register (gen_rtx_REG (SImode, LINK_REGNUM),
1850 special_save_offset);
1852 /* Save callee-save registers. */
1853 reg_save_offset = 0;
1854 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1856 if (picochip_reg_needs_saving (i))
1859 /* If this register is an even numbered register, and the
1860 next register also needs to be saved, use a SImode save,
1861 which does both in one instruction. Note that a special
1862 check is performed to ensure that the double word aligned
1863 store is valid (e.g., it is possible that r6, r8, r9 need
1864 to be saved, in which case once r6 has been saved, the
1865 stored offset is no longer aligned, and an STL/LDL
1866 instruction becomes invalid). Alternately, we could store all
1867 aligned registers first and then save the single one(s). */
1869 picochip_reg_needs_saving (i + 1) &&
1870 picochip_is_aligned (reg_save_offset, LONG_TYPE_SIZE))
1872 picochip_emit_save_register (gen_rtx_REG (SImode, i),
1873 general_save_offset +
1875 reg_save_offset += 2 * UNITS_PER_WORD;
1880 picochip_emit_save_register (gen_rtx_REG (HImode, i),
1881 general_save_offset +
1883 reg_save_offset += UNITS_PER_WORD;
1889 /* Emit a stack adjustment where required. */
1890 if (stack_adjustment != 0)
1891 picochip_emit_stack_allocate (stack_adjustment);
1893 /* If this function uses varadic arguments, write any unnamed
1894 registers to the stack. */
1897 int stdarg_offset = picochip_pretend_arg_area_byte_offset ();
1899 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
1900 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
1902 picochip_emit_save_register (gen_rtx_REG (SImode, 0), stdarg_offset);
1903 picochip_emit_save_register (gen_rtx_REG (SImode, 2),
1905 picochip_emit_save_register (gen_rtx_REG (SImode, 4),
1912 /* Expand the epilogue into RTL. */
1914 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED)
1916 int stack_adjustment = 0;
1917 int special_save_offset = 0;
1918 int general_save_offset = 0;
1919 int reg_save_offset = 0;
1921 int use_link_fp_restore_stack_adjust = 0; /* Default to using an explicit
1924 stack_adjustment = picochip_arg_area_byte_offset ();
1925 general_save_offset =
1926 -(stack_adjustment - picochip_save_area_byte_offset ());
1927 special_save_offset =
1928 -(stack_adjustment - picochip_special_save_area_byte_offset ());
1930 /* Emit a stack adjustment where required. */
1931 if (stack_adjustment != 0)
1933 /* If the link/fp is already being restored, and the offset to
1934 their save location is small enough, don't bother adjusting
1935 the stack explicitly. */
1936 if (picochip_special_save_area_byte_offset () < 512 &&
1937 !picochip_can_eliminate_link_sp_save ())
1938 use_link_fp_restore_stack_adjust = 1;
1940 /* Explicitly restore the stack. */
1941 picochip_emit_stack_allocate (-stack_adjustment);
1944 /* Restore the Link/FP registers. Only save the link register? */
1945 if (!picochip_can_eliminate_link_sp_save ())
1947 if (use_link_fp_restore_stack_adjust)
1948 picochip_emit_restore_register (gen_rtx_REG (SImode, LINK_REGNUM),
1949 picochip_special_save_area_byte_offset
1952 picochip_emit_restore_register (gen_rtx_REG (SImode, LINK_REGNUM),
1953 special_save_offset);
1956 /* Restore callee-save registers. */
1957 reg_save_offset = 0;
1958 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1960 if (picochip_reg_needs_saving (i))
1963 /* If this register is an even numbered register, and the
1964 next register also needs to be saved, use a SImode save,
1965 which does both in one instruction. Note that a special
1966 check is performed to ensure that the double word aligned
1967 store is valid (e.g., it is possible that r6, r8, r9 need
1968 to be saved, in which case once r6 has been saved, the
1969 stored offset is no longer aligned, and an STL/LDL
1970 instruction becomes invalid). We could store all aligned
1971 registers first, and then save the single one(s). */
1973 picochip_reg_needs_saving (i + 1) &&
1974 picochip_is_aligned (reg_save_offset, LONG_TYPE_SIZE))
1976 picochip_emit_restore_register (gen_rtx_REG (SImode, i),
1977 general_save_offset +
1979 reg_save_offset += 2 * UNITS_PER_WORD;
1984 picochip_emit_restore_register (gen_rtx_REG (HImode, i),
1985 general_save_offset +
1987 reg_save_offset += UNITS_PER_WORD;
1993 /* Emit a return instruction, which matches a (parallel
1994 [(return) (use r12)]) */
1997 p = rtvec_alloc (2);
1999 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
2000 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
2001 gen_rtx_REG (Pmode, LINK_REGNUM));
2002 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
2007 /* Assembly instruction output. */
2009 /* Test whether the given branch instruction is short, or long. Short
2010 * branches are equivalent to real branches, and may be DFA
2011 * scheduled. Long branches expand to a macro which is handled by the
2012 * elaborator, and cannot be scheduled. Occasionally, the branch
2013 * shortening pass, which is run after DFA scheduling, will change the
2014 * code layout and cause the short branch to be reverted into a long
2015 * branch. Instead of having to fix this up by emitting new assembly,
2016 * the short branch is emitted anyway. There is plenty of slack in the
2017 * calculation of long and short branches (10-bit offset, but only
2018 * 9-bits used in computation), so there is enough slack for this to
2021 picochip_is_short_branch (rtx insn)
2023 int isRealShortBranch = (get_attr_length(insn) == SHORT_BRANCH_LENGTH);
2025 return (isRealShortBranch ||
2026 (!isRealShortBranch &&
2027 picochip_current_vliw_state.num_insns_in_packet > 1));
2030 /* Output a compare-and-branch instruction (matching the cbranch
2033 picochip_output_cbranch (rtx operands[])
2036 if (HImode != GET_MODE (operands[1]) ||
2037 (HImode != GET_MODE (operands[2]) &&
2038 GET_CODE (operands[2]) != CONST_INT))
2040 internal_error ("%s: At least one operand can't be handled",
2044 /* Use the type of comparison to output the appropriate condition
2046 switch (GET_CODE (operands[0]))
2049 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2052 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2055 /* Reverse the operand order to be GE */
2056 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2059 /* Reverse operand order of GEU. */
2060 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2063 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2066 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2069 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2072 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2075 /* Reversed operand version of LT. */
2076 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2079 /* Reverse an LTU. */
2080 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2087 /* Output a compare-and-branch instruction (matching the cbranch
2088 pattern). This function is current unused since the cbranch
2089 split is disabled. The function is kept around so we can use
2090 it when we understand how to do cbranch split safely. */
2092 picochip_output_compare (rtx operands[])
2095 if (HImode != GET_MODE (operands[1]) ||
2096 (HImode != GET_MODE (operands[2]) &&
2097 GET_CODE (operands[2]) != CONST_INT))
2099 internal_error ("%s: At least one operand can't be handled",
2103 /* Use the type of comparison to output the appropriate condition
2105 int code = GET_CODE (operands[0]);
2109 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2112 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2115 /* Reverse the operand order to be GE */
2116 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2119 /* Reverse operand order of GEU. */
2120 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2123 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2126 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2129 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2132 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2135 /* Reversed operand version of LT. */
2136 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2139 /* Reverse an LTU. */
2140 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2147 /* Output the branch insn part of a compare-and-branch split. */
2149 picochip_output_branch (rtx operands[], rtx insn)
2152 int code = GET_CODE(operands[2]);
2153 if (picochip_is_short_branch (insn))
2155 /* Short branches can be output directly using the
2156 appropriate instruction. */
2160 return ("BNE %l0 %>");
2162 return ("BEQ %l0 %>");
2164 return ("BGE %l0 %>");
2166 return ("BHS %l0 %>");
2168 return ("BGE %l0 %>");
2170 return ("BHS %l0 %>");
2172 return ("BLT %l0 %>");
2174 return ("BLO %l0 %>");
2176 return ("BLT %l0 %>");
2178 return ("BLO %l0 %>");
2180 internal_error ("Unknown short branch in %s (type %d)\n",
2181 __FUNCTION__, (int) INTVAL (operands[1]));
2182 return "UNKNOWN_BRANCH";
2187 /* Long branches result in the emission of a special
2188 instruction, which the assembler expands into a suitable long
2191 /* Use the type of comparison to output the appropriate condition
2196 return ("JMPNE %l0 %>");
2198 return ("JMPEQ %l0 %>");
2200 return ("JMPGE %l0 %>");
2202 return ("JMPHS %l0 %>");
2204 return ("JMPGE %l0 %>");
2206 return ("JMPHS %l0 %>");
2208 return ("JMPLT %l0 %>");
2210 return ("JMPLO %l0 %>");
2212 return ("JMPLT %l0 %>");
2214 return ("JMPLO %l0 %>");
2217 internal_error ("Unknown long branch in %s (type %d)\n",
2218 __FUNCTION__, (int) INTVAL (operands[1]));
2219 return "UNKNOWN_BRANCH";
2225 /* Output a jump instruction. */
2227 picochip_output_jump (rtx insn)
2229 if (picochip_is_short_branch (insn))
2232 return "JMPRA %l0%>";
2236 picochip_output_put_array (int alternative, rtx operands[])
2238 /* Local output buffer. */
2241 int portArraySize = INTVAL(operands[1]);
2242 int portBaseIndex = INTVAL(operands[2]);
2244 if (alternative == 0)
2246 sprintf (buf, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2247 portArraySize, portBaseIndex);
2248 output_asm_insn (buf, operands);
2250 else if (alternative == 1)
2252 /* Constant port id. Emit a real instruction. */
2253 int portIndex = INTVAL(operands[0]) + portBaseIndex;
2254 if (portIndex < portBaseIndex ||
2255 portIndex >= (portBaseIndex + portArraySize))
2257 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2258 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2260 sprintf(buf, "PUT R[0:1],%d", portIndex);
2261 output_asm_insn (buf, operands);
2266 /* Both alternatives output the insn directly. */
2270 const char *picochip_output_get_array (int alternative, rtx operands[])
2272 /* Local output buffer. */
2275 int portArraySize = INTVAL(operands[1]);
2276 int portBaseIndex = INTVAL(operands[2]);
2278 if (alternative == 0)
2280 sprintf (buf, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2281 portArraySize, portBaseIndex);
2282 output_asm_insn (buf, operands);
2284 else if (alternative == 1)
2286 /* Constant port id. Emit a real instruction. */
2287 int portIndex = INTVAL(operands[0]) + portBaseIndex;
2288 if (portIndex < portBaseIndex ||
2289 portIndex >= (portBaseIndex + portArraySize))
2291 error ("GET uses port array index %d, which is out of range [%d..%d)",
2292 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2294 sprintf(buf, "GET %d,R[0:1]", portIndex);
2295 output_asm_insn (buf, operands);
2300 /* Both alternatives output the insn directly. */
2304 const char *picochip_output_testport_array (int alternative, rtx operands[])
2306 /* Local output buffer. */
2309 int portArraySize = INTVAL(operands[2]);
2310 int portBaseIndex = INTVAL(operands[3]);
2312 if (alternative == 0)
2314 sprintf (buf, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2315 portArraySize, portBaseIndex);
2316 output_asm_insn (buf, operands);
2318 else if (alternative == 1)
2320 /* Constant port id. Emit a real instruction. */
2321 int portIndex = INTVAL(operands[1]) + portBaseIndex;
2322 if (portIndex < portBaseIndex ||
2323 portIndex >= (portBaseIndex + portArraySize))
2325 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2326 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2328 sprintf(buf, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex);
2329 output_asm_insn (buf, operands);
2334 /* Both alternatives output the insn directly. */
2338 /* Output a comparison operand as a symbol (e.g., >). */
2340 picochip_print_comparison (FILE * file, rtx operand, int letter)
2345 /* Output just the comparison symbol. */
2346 switch (GET_CODE (operand))
2349 fprintf (file, "!=");
2352 fprintf (file, "==");
2355 fprintf (file, ">=");
2358 fprintf (file, ">={U}");
2361 fprintf (file, "<");
2364 fprintf (file, "<{U}");
2367 fprintf (file, "<=");
2370 fprintf (file, "<={U}");
2373 fprintf (file, ">");
2376 fprintf (file, ">{U}");
2384 /* Output the comparison formatted as operand,symbol,operand */
2385 rtx op0 = XEXP (operand, 0);
2386 rtx op1 = XEXP (operand, 1);
2388 picochip_print_operand (file, op0, 0);
2389 picochip_print_comparison (file, operand, 'i');
2390 picochip_print_operand (file, op1, 0);
2394 /* This function generates a memory address operand in the given
2395 mode. That is, if the address contains a constant offset, then the
2396 offset is divided by the required mode size to compute the
2397 mode specific offset. By default, picochip_print_operand_address calls
2398 this function using the natural mode of the operand, but special
2399 operand codes can be used to invoke the computation using an
2400 unnatural mode (e.g., compute the HI aligned address of an SI mode
2403 picochip_print_memory_address (FILE * file, rtx operand,
2404 enum machine_mode mode)
2406 rtx address = XEXP (operand, 0);
2409 if (MEM != GET_CODE (operand))
2410 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2415 printf ("picochip_print_memory_address: ");
2416 print_rtl (stdout, operand);
2420 switch (GET_CODE (address))
2424 /* Grab the address components. */
2425 rtx base = XEXP (address, 0);
2426 rtx offset = XEXP (address, 1);
2428 /* Only handle reg+const addresses */
2429 if (REG == GET_CODE (base) && CONST_INT == GET_CODE (offset))
2431 /* Sanity check. If an FP+offset address is given, ensure
2432 that the offset lies within the given frame, or a lower
2434 if (REGNO (base) == STACK_POINTER_REGNUM )
2435 gcc_assert (INTVAL (offset) <= (picochip_arg_area_byte_offset () +
2438 /* Print the base register - identical for all modes. */
2439 fprintf (file, "(");
2440 picochip_print_operand (file, base, 'r');
2441 fprintf (file, ")");
2443 /* Print the constant offset with compensation for the mode. */
2447 picochip_print_operand (file, offset, 'Q');
2451 picochip_print_operand (file, offset, 'H');
2456 picochip_print_operand (file, offset, 'S');
2460 picochip_print_operand (file, offset, 'D');
2474 picochip_print_operand (file, address, 's');
2483 inner = XEXP (address, 0);
2485 /* Sanity check - the CONST memory address must be a base+offset. */
2486 gcc_assert (PLUS == GET_CODE (inner));
2488 base = XEXP (inner, 0);
2489 offset = XEXP (inner, 1);
2491 fprintf (file, "&_%s%+d", XSTR (base, 0), XINT (offset, 0));
2497 /* Register operand. Provide a zero offset. */
2498 fprintf (file, "(");
2499 picochip_print_operand (file, address, 'r');
2500 fprintf (file, ")0");
2509 /* Output an operand. Formatting letters allow particular parts of
2510 the operand to be output. */
2512 picochip_print_operand (FILE * file, rtx operand, int letter)
2515 /* Handle special cases. */
2518 /* VLIW continuation, for explicit VLIW sequences. */
2520 fprintf (file, "\\");
2525 fputc (picochip_get_vliw_alu_id (), file);
2528 /* Delay slot specifier. */
2530 /* This should be handled in asm_output_opcode. */
2533 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2535 switch (GET_CODE (operand))
2538 fprintf (file, "AND");
2541 fprintf (file, "OR");
2544 fprintf (file, "XOR");
2547 fprintf (file, "ADD");
2550 fprintf (file, "SUB");
2557 /* Symbolic instructions (e.g., lshift becomes <<). */
2559 switch (GET_CODE (operand))
2562 fprintf (file, "&");
2565 fprintf (file, "|");
2568 fprintf (file, "^");
2571 fprintf (file, "+");
2574 fprintf (file, "-");
2577 fprintf (file, "UNKNOWN_INSN");
2582 default: /* Not a punctuation character - process as normal. */
2586 switch (GET_CODE (operand))
2592 /* Write a range of registers. */
2593 fprintf (file, "R[%d:%d]", REGNO (operand) + 1, REGNO (operand));
2597 /* The upper register of a pair is requested. */
2598 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 1]);
2602 /* The lower register of a pair is requested. Equivalent to the
2603 default, but included for completeness. */
2604 fprintf (file, "%s", picochip_regnames[REGNO (operand)]);
2608 /* The 3rd register of a DI mode register. */
2609 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 2]);
2613 /* The 4th register of a DI mode register. */
2614 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 3]);
2618 fprintf (file, "%s", picochip_regnames[REGNO (operand)]);
2623 /* A range of letters can be used to format integers. The
2624 letters Q/H/S are used to divide the constant by the width of
2625 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2626 to obtain the upper and lower 16-bits of a 32-bit
2627 constant. Where possible, signed numbers are used, since
2628 signed representations of numbers may be more compact (e.g.,
2629 65535 can be represented as -1, which fits into a small
2630 constant, whereas 65535 requires a large constant). */
2634 fprintf (file, "%ld", INTVAL (operand));
2638 fprintf (file, "%ld", INTVAL (operand) / 2);
2642 fprintf (file, "%ld", INTVAL (operand) / 4);
2646 fprintf (file, "%d", exact_log2 (INTVAL(operand)));
2650 fprintf (file, "%hi", (short) ((INTVAL (operand) >> 16) & 0xFFFF));
2654 fprintf (file, "%hi", (short) (INTVAL (operand) & 0xFFFF));
2658 fprintf (file, "%ld", INTVAL (operand));
2668 if (GET_MODE (operand) != SFmode)
2669 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2671 REAL_VALUE_FROM_CONST_DOUBLE (rv, operand);
2672 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
2677 fprintf (file, "%hi", (short) ((val >> 16) & 0xFFFF));
2681 fprintf (file, "%hi", (short) (val & 0xFFFF));
2689 /* Output a symbol. The output format must match that of
2690 picochip_output_label. */
2692 /* Ensure that the symbol is marked as referenced. Gcc can
2693 occasionally omit the function bodies when it believes them
2694 to be unreferenced. */
2695 if (SYMBOL_REF_DECL (operand))
2696 mark_decl_referenced (SYMBOL_REF_DECL (operand));
2697 fprintf (file, "&");
2698 assemble_name (file, XSTR (operand, 0));
2702 /* This format must match that of picochip_output_label. */
2703 fprintf (file, "&");
2704 output_asm_label (operand);
2709 rtx addr = XEXP (operand, 0);
2714 if (PLUS != GET_CODE (addr))
2715 fatal_insn ("Bad address, not (reg+disp):", addr);
2717 picochip_print_operand (file, XEXP (addr, 1), 0);
2721 /* Output a memory address in byte mode notation (i.e., the
2722 constant address (if any) is the actual byte address. */
2723 picochip_print_memory_address (file, operand, QImode);
2726 /* Output a constant offset of the given mode (i.e., divide
2727 the constant by the number of units in the mode to get the
2730 picochip_print_memory_address (file, operand, QImode);
2734 picochip_print_memory_address (file, operand, HImode);
2738 picochip_print_memory_address (file, operand, SImode);
2742 picochip_print_memory_address (file, operand, SFmode);
2746 if (PLUS != GET_CODE (addr))
2747 fatal_insn ("Bad address, not (reg+disp):", addr);
2749 picochip_print_operand (file, XEXP (addr, 0), 0);
2752 /* When the mem operand is (reg + big offset) which cannot
2753 be represented in an instruction as operand, the compiler
2754 automatically generates the instruction to put in (reg +
2755 big offset) into another register. In such cases, it
2756 returns '0' as the character. This needs to be handled
2760 if (REG != GET_CODE (addr))
2761 fatal_insn ("Bad address, not register:", addr);
2763 picochip_print_operand (file, addr, 0);
2767 fprintf (file, "Unknown mem operand - letter %c ",
2769 print_rtl (file, operand);
2777 rtx const_exp = XEXP (operand, 0);
2779 /* Handle constant offsets to symbol references. */
2780 if (PLUS == GET_CODE (const_exp) &&
2781 SYMBOL_REF == GET_CODE (XEXP (const_exp, 0)) &&
2782 CONST_INT == GET_CODE (XEXP (const_exp, 1)))
2785 picochip_print_operand (file, XEXP (const_exp, 0), 0);
2786 if (INTVAL (XEXP (const_exp, 1)) >= 0)
2787 fprintf (file, "+");
2788 /* else use the - from the operand (i.e., AP-2)) */
2790 picochip_print_operand (file, XEXP (const_exp, 1), letter);
2799 /* PLUS expressions are of the form (base + offset). Different
2800 options (analagous to those of memory PLUS expressions) are used
2801 to extract the base and offset components. */
2806 picochip_print_operand (file, XEXP (operand, 0), 0);
2810 picochip_print_operand (file, XEXP (operand, 1), 0);
2815 /* If the expression is composed entirely of constants,
2816 evaluate the result. This should only occur with the
2817 picoChip specific comms instructions, which are emitted as
2818 base+offset expressions. */
2819 if (CONST_INT == GET_CODE (XEXP (operand, 0)) &&
2820 CONST_INT == GET_CODE (XEXP (operand, 1)))
2822 HOST_WIDE_INT result = (XINT (XEXP (operand, 0), 0) +
2823 XINT (XEXP (operand, 1), 0));
2824 fprintf (file, "%ld", result);
2828 fprintf (file, "(");
2829 picochip_print_operand (file, XEXP (operand, 0), 0);
2830 fprintf (file, "+");
2831 picochip_print_operand (file, XEXP (operand, 1), 0);
2832 fprintf (file, ")");
2839 /* Comparison operations. */
2850 picochip_print_comparison (file, operand, letter);
2854 fprintf (stderr, "Unknown operand encountered in %s\n", __FUNCTION__);
2855 print_rtl (file, operand);
2862 /* Output an operand address */
2864 picochip_print_operand_address (FILE * file, rtx operand)
2867 switch (GET_CODE (operand))
2871 /* This format must match that of picochip_output_label. */
2872 assemble_name (file, XSTR (operand, 0));
2876 /* Note this format must match that of picochip_output_label. */
2877 fprintf (file, "_L%d", XINT (operand, 5));
2881 /* Pass on to a specialised memory address generator. */
2882 picochip_print_memory_address (file, operand, GET_MODE (operand));
2893 /* Scheduling functions. */
2895 /* Save some of the contents of recog_data. */
2897 picochip_save_recog_data (void)
2899 picochip_saved_which_alternative = which_alternative;
2900 memcpy (&picochip_saved_recog_data, &recog_data,
2901 sizeof (struct recog_data));
2904 /* Restore some of the contents of global variable recog_data. */
2906 picochip_restore_recog_data (void)
2908 which_alternative = picochip_saved_which_alternative;
2909 memcpy (&recog_data, &picochip_saved_recog_data,
2910 sizeof (struct recog_data));
2913 /* Ensure that no var tracking notes are emitted in the middle of a
2914 three-instruction bundle. */
2916 reorder_var_tracking_notes (void)
2922 rtx queue = NULL_RTX;
2924 for (insn = BB_HEAD (bb); insn != BB_END (bb); insn = next)
2926 next = NEXT_INSN (insn);
2928 if (NONDEBUG_INSN_P (insn))
2930 /* Emit queued up notes before the first instruction of a bundle. */
2931 if (GET_MODE (insn) == TImode)
2935 rtx next_queue = PREV_INSN (queue);
2936 NEXT_INSN (PREV_INSN(insn)) = queue;
2937 PREV_INSN (queue) = PREV_INSN(insn);
2938 PREV_INSN (insn) = queue;
2939 NEXT_INSN (queue) = insn;
2944 else if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_VAR_LOCATION)
2946 rtx prev = PREV_INSN (insn);
2947 PREV_INSN (next) = prev;
2948 NEXT_INSN (prev) = next;
2949 PREV_INSN (insn) = queue;
2956 /* Perform machine dependent operations on the rtl chain INSNS. */
2958 picochip_reorg (void)
2960 rtx insn, insn1, vliw_start;
2961 int vliw_insn_location = 0;
2963 /* We are freeing block_for_insn in the toplev to keep compatibility
2964 with old MDEP_REORGS that are not CFG based. Recompute it now. */
2965 compute_bb_for_insn ();
2970 if (picochip_schedule_type != DFA_TYPE_NONE)
2972 timevar_push (TV_SCHED2);
2974 /* Process the instruction list, computing the sizes of each
2975 instruction, and consequently branch distances. This can
2976 result in some branches becoming short enough to be treated
2977 as a real branch instruction, rather than an assembly branch
2978 macro which may expand into multiple instructions. The
2979 benefit of shortening branches is that real branch
2980 instructions can be properly DFA scheduled, whereas macro
2982 shorten_branches (get_insns ());
2984 /* Do control and data sched analysis again,
2985 and write some more of the results to dump file. */
2991 timevar_pop (TV_SCHED2);
2995 if (picochip_schedule_type == DFA_TYPE_SPEED)
2997 /* Whenever a VLIW packet is generated, all instructions in
2998 that packet must appear to come from the same source
2999 location. The following code finds all the VLIW packets,
3000 and tags their instructions with the location of the first
3001 instruction from the packet. Clearly this will result in
3002 strange behaviour when debugging the code, but since
3003 debugging and optimisation are being used in conjunction,
3004 strange behaviour is certain to occur anyway. */
3005 /* Slight bit of change. If the vliw set contains a branch
3006 or call instruction, we pick its location.*/
3007 for (insn = get_insns (); insn; insn = next_insn (insn))
3010 /* If this is the first instruction in the VLIW packet,
3011 extract its location. */
3012 if (GET_MODE (insn) == TImode)
3015 vliw_insn_location = INSN_LOCATOR (insn);
3017 if (JUMP_P (insn) || CALL_P(insn))
3019 vliw_insn_location = INSN_LOCATOR (insn);
3020 for (insn1 = vliw_start; insn1 != insn ; insn1 = next_insn (insn1))
3021 INSN_LOCATOR (insn1) = vliw_insn_location;
3023 /* Tag subsequent instructions with the same location. */
3024 if (NONDEBUG_INSN_P (insn))
3025 INSN_LOCATOR (insn) = vliw_insn_location;
3031 /* Locate the note marking the end of the function's prologue. If
3032 the note appears in the middle of a VLIW packet, move the note to
3033 the end. This avoids unpleasant consequences such as trying to
3034 emit prologue markers (e.g., .loc/.file directives) in the middle
3036 if (picochip_schedule_type == DFA_TYPE_SPEED)
3038 rtx prologue_end_note = NULL;
3039 rtx last_insn_in_packet = NULL;
3041 for (insn = get_insns (); insn; insn = next_insn (insn))
3043 /* The prologue end must be moved to the end of the VLIW packet. */
3044 if (NOTE_KIND (insn) == NOTE_INSN_PROLOGUE_END)
3046 prologue_end_note = insn;
3051 /* Find the last instruction in this packet. */
3052 for (insn = prologue_end_note; insn; insn = next_real_insn (insn))
3054 if (GET_MODE (insn) == TImode)
3057 last_insn_in_packet = insn;
3060 if (last_insn_in_packet != NULL)
3062 rtx tmp_note = emit_note_after (NOTE_KIND(prologue_end_note), last_insn_in_packet);
3063 memcpy(&NOTE_DATA (tmp_note), &NOTE_DATA(prologue_end_note), sizeof(NOTE_DATA(prologue_end_note)));
3064 delete_insn (prologue_end_note);
3067 if (picochip_flag_var_tracking)
3069 timevar_push (TV_VAR_TRACKING);
3070 variable_tracking_main ();
3071 /* We also have to deal with variable tracking notes in the middle
3073 reorder_var_tracking_notes();
3074 timevar_pop (TV_VAR_TRACKING);
3078 /* Return the ALU character identifier for the current
3079 instruction. This will be 0 or 1. */
3081 picochip_get_vliw_alu_id (void)
3085 /* Always use ALU 0 if VLIW scheduling is disabled. */
3086 if (picochip_schedule_type != DFA_TYPE_SPEED)
3089 /* Get the attribute type of the instruction. Note that this can
3090 ruin the contents of recog_data, so save/restore around the
3092 picochip_save_recog_data ();
3093 attr_type = get_attr_type (picochip_current_prescan_insn);
3094 picochip_restore_recog_data ();
3096 if (picochip_current_vliw_state.contains_pico_alu_insn)
3099 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3100 else it must be the other ALU (either basic or nonCc)
3101 instruction which goes into 1. */
3102 if (attr_type == TYPE_PICOALU)
3108 else if (picochip_current_vliw_state.contains_non_cc_alu_insn)
3110 /* Is this the non CC instruction? If it is, then stuff it into
3111 ALU 1, else it must be a picoAlu or basicAlu, in which case
3112 it goes into ALU 0. */
3113 if (attr_type == TYPE_NONCCALU)
3120 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3121 whether an ALU instruction has already been scheduled in this
3123 switch (picochip_current_vliw_state.num_alu_insns_so_far)
3126 picochip_current_vliw_state.num_alu_insns_so_far++;
3130 picochip_current_vliw_state.num_alu_insns_so_far++;
3134 internal_error ("Too many ALU instructions emitted (%d)\n",
3135 picochip_current_vliw_state.num_alu_insns_so_far);
3142 /* Reset any information about the current VLIW packing status. */
3144 picochip_reset_vliw (rtx insn)
3146 rtx local_insn = insn;
3148 /* Nothing to do if VLIW scheduling isn't being used. */
3149 if (picochip_schedule_type != DFA_TYPE_SPEED)
3153 printf ("%s on insn %d\n", __FUNCTION__, INSN_UID (insn));
3156 picochip_current_vliw_state.contains_pico_alu_insn = 0;
3157 picochip_current_vliw_state.contains_non_cc_alu_insn = 0;
3158 picochip_current_vliw_state.num_alu_insns_so_far = 0;
3159 picochip_current_vliw_state.num_cfi_labels_deferred = 0;
3160 picochip_current_vliw_state.lm_label_name[0] = 0;
3161 picochip_current_vliw_state.num_insns_in_packet = 0;
3163 /* Read through the VLIW packet, classifying the instructions where
3168 if (NOTE_P (local_insn) || DEBUG_INSN_P(local_insn))
3170 local_insn = NEXT_INSN (local_insn);
3173 else if (!INSN_P (local_insn))
3177 /* It is an instruction, but is it ours? */
3178 if (INSN_CODE (local_insn) != -1)
3182 picochip_current_vliw_state.num_insns_in_packet += 1;
3184 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3185 get_attr_type function can overwrite the values in
3186 the recog_data global, hence this is saved and
3187 restored around the call. Not doing so results in
3188 asm_output_opcode being called with a different
3189 instruction to final_prescan_insn, which is fatal. */
3190 picochip_save_recog_data ();
3191 attr_type = get_attr_type (local_insn);
3192 picochip_restore_recog_data ();
3194 if (attr_type == TYPE_PICOALU)
3195 picochip_current_vliw_state.contains_pico_alu_insn = 1;
3196 if (attr_type == TYPE_NONCCALU)
3197 picochip_current_vliw_state.contains_non_cc_alu_insn = 1;
3202 /* Get the next instruction. */
3203 local_insn = NEXT_INSN (local_insn);
3205 /* Keep going while the next instruction is part of the same
3206 VLIW packet (i.e., its a valid instruction and doesn't mark
3207 the start of a new VLIW packet. */
3209 while (local_insn &&
3210 (GET_MODE (local_insn) != TImode) && (INSN_CODE (local_insn) != -1));
3215 picochip_sched_reorder (FILE * file, int verbose,
3216 rtx * ready ATTRIBUTE_UNUSED,
3217 int *n_readyp ATTRIBUTE_UNUSED, int clock)
3221 fprintf (file, ";;\tClock %d\n", clock);
3223 return picochip_sched_issue_rate ();
3228 picochip_sched_lookahead (void)
3230 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3236 picochip_sched_issue_rate (void)
3241 /* Adjust the scheduling cost between the two given instructions,
3242 which have the given dependency. */
3244 picochip_sched_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
3249 printf ("Sched Adjust Cost: %d->%d is %d\n",
3250 INSN_UID (insn), INSN_UID (dep_insn), cost);
3252 printf (" Dependency type:");
3253 switch (REG_NOTE_KIND (link))
3261 case REG_DEP_OUTPUT:
3262 printf ("OUTPUT\n");
3265 printf ("Unknown (%d)\n", REG_NOTE_KIND (link));
3269 /* Anti-dependencies are used to enforce the ordering between a
3270 * branch, and any subsequent instructions. For example:
3275 * The ADD instruction must execute after the branch, and this is
3276 * enforced using an anti-dependency. Unfortunately, VLIW machines
3277 * are happy to execute anti-dependent instructions in the same
3278 * cycle, which then results in a schedule like the following being
3281 * BNE someLabel \ ADD.0 r0,r1,r2
3283 * The instruction which would normally be conditionally executed
3284 * depending upon the outcome of the branch, is now unconditionally
3285 * executed every time. To prevent this happening, any
3286 * anti-dependencies between a branch and another instruction are
3287 * promoted to become real dependencies.
3289 if ((JUMP_P (dep_insn) || CALL_P(dep_insn)) && REG_NOTE_KIND (link) == REG_DEP_ANTI)
3293 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3294 INSN_UID (insn), INSN_UID (dep_insn));
3303 /* Return the minimum of the two values */
3305 minimum (int a, int b)
3311 /* I dont expect to get to this function with a==b.*/
3316 /* This function checks if the memory of the two stores are just off by 2 bytes.
3317 It returns the lower memory operand's index.*/
3320 memory_just_off (rtx opnd1, rtx opnd2)
3322 int offset1 = 0, offset2 = 0;
3325 if (GET_CODE(XEXP(opnd1, 0)) == PLUS && GET_CODE(XEXP(XEXP(opnd1, 0),1)) == CONST_INT)
3327 offset1 = INTVAL(XEXP(XEXP(opnd1, 0), 1));
3328 reg1 = REGNO(XEXP(XEXP(opnd1, 0), 0));
3332 reg1 = REGNO(XEXP(opnd1, 0));
3334 if (GET_CODE(XEXP(opnd2, 0)) == PLUS && GET_CODE(XEXP(XEXP(opnd2, 0), 1)) == CONST_INT)
3336 offset2 = INTVAL(XEXP(XEXP(opnd2, 0), 1));
3337 reg2 = REGNO(XEXP(XEXP(opnd2, 0), 0));
3341 reg2 = REGNO(XEXP(opnd2, 0));
3344 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3345 should be 4 byte aligned. We can currently guarentee that only if the base
3346 address is FP(R13) and the offset is aligned. */
3348 if (reg1 == reg2 && reg1 == 13 && abs(offset1-offset2) == 2 && minimum(offset1, offset2) % 4 == 0)
3349 return (minimum(offset1, offset2) == offset1) ? 1:2;
3355 registers_just_off (rtx opnd1, rtx opnd2)
3358 reg1 = REGNO(opnd1);
3359 reg2 = REGNO(opnd2);
3360 if (abs(reg1-reg2) == 1 && minimum(reg1, reg2) % 2 == 0)
3361 return (minimum(reg1, reg2) == reg1)?1:2;
3365 /* Check to see if the two LDWs can be peepholed together into a LDL
3366 They can be if the registers getting loaded into are contiguous
3367 and the memory addresses are contiguous as well.
3371 can be merged together into
3375 1. The LDWs themselves only guarentee that r11 will be a 2-byte
3376 aligned address. Only FP can be assumed to be 4 byte aligned.
3377 2. The progression of addresses and the register numbers should
3378 be similar. For eg., if you swap r2 and r3 in the above instructions,
3379 the resultant pair cannot be merged.
3383 ok_to_peephole_ldw(rtx opnd0, rtx opnd1, rtx opnd2, rtx opnd3)
3385 int memtest=0,regtest=0;
3386 regtest = registers_just_off(opnd1,opnd3);
3390 memtest = memory_just_off(opnd0,opnd2);
3394 if (regtest == memtest)
3401 /* Similar to LDW peephole */
3403 ok_to_peephole_stw(rtx opnd0, rtx opnd1, rtx opnd2, rtx opnd3)
3405 int memtest=0,regtest=0;
3406 regtest = registers_just_off(opnd1,opnd3);
3410 memtest = memory_just_off(opnd0,opnd2);
3414 if (regtest == memtest)
3422 /* Generate a SImode register with the register number that is the smaller of the two */
3424 gen_min_reg(rtx opnd1,rtx opnd2)
3426 return gen_rtx_REG (SImode, minimum(REGNO(opnd1),REGNO(opnd2)));
3429 /* Generate a SImode memory with the address that is the smaller of the two */
3431 gen_SImode_mem(rtx opnd1,rtx opnd2)
3433 int offset1=0,offset2=0;
3435 if (GET_CODE(XEXP(opnd1,0)) == PLUS && GET_CODE(XEXP(XEXP(opnd1,0),1)) == CONST_INT)
3437 offset1 = INTVAL(XEXP(XEXP(opnd1,0),1));
3438 reg = XEXP(XEXP(opnd1,0),0);
3442 reg = XEXP(opnd1,0);
3444 if (GET_CODE(XEXP(opnd2,0)) == PLUS && GET_CODE(XEXP(XEXP(opnd2,0),1)) == CONST_INT)
3446 offset2 = INTVAL(XEXP(XEXP(opnd2,0),1));
3448 rtx address = gen_rtx_PLUS (HImode, reg, GEN_INT(minimum(offset1,offset2)));
3449 return gen_rtx_MEM(SImode,address);
3453 picochip_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int* total)
3460 /* Need to penalize immediates that need to be encoded as long constants.*/
3461 if (code == CONST_INT && !(INTVAL (x) >= 0 && INTVAL (x) < 16))
3463 *total = COSTS_N_INSNS(1);
3471 *total = COSTS_N_INSNS (outer_code != MEM);
3476 /* if_then_else come out of cbranch instructions. It will get split into
3477 a condition code generating subtraction and a branch */
3478 *total = COSTS_N_INSNS (2);
3485 if (GET_MODE(x) == SImode)
3486 *total = COSTS_N_INSNS (2);
3487 if (GET_MODE(x) == DImode)
3488 *total = COSTS_N_INSNS (4);
3492 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3493 if (GET_MODE(x) == QImode && !TARGET_HAS_BYTE_ACCESS)
3494 *total = COSTS_N_INSNS (10);
3496 /* 64-bit accesses have to be done through 2 32-bit access */
3497 if (GET_MODE(x) == DImode)
3498 *total = COSTS_N_INSNS (2);
3504 /* SImode shifts are expensive */
3505 if (GET_MODE(x) == SImode)
3506 *total = COSTS_N_INSNS (10);
3508 /* Register shift by constant is cheap. */
3509 if ((GET_MODE(x) == QImode || GET_MODE(x) == HImode)
3510 && GET_CODE(XEXP(x, 0)) == REG
3511 && GET_CODE(XEXP(x, 1)) == CONST_INT)
3512 *total = COSTS_N_INSNS (1);
3514 *total = COSTS_N_INSNS (4);
3521 /* Divisions are more expensive than the default 7*/
3522 if (GET_MODE(x) == SImode)
3523 *total = COSTS_N_INSNS (20);
3525 *total = COSTS_N_INSNS (12);
3530 /* Look for the simple cases of multiplying register*register or
3531 register*constant. */
3532 if ((GET_MODE(x) == QImode || GET_MODE(x) == HImode)
3533 && ((GET_CODE(XEXP(x, 0)) == REG
3534 && (GET_CODE(XEXP(x, 1)) == REG || GET_CODE(XEXP(x,1)) == CONST_INT))
3535 || (GET_CODE(XEXP(x, 0)) == ZERO_EXTEND
3536 && GET_CODE(XEXP(XEXP(x, 0),0)) == REG
3537 && GET_CODE(XEXP(x, 1)) == ZERO_EXTEND
3538 && GET_CODE(XEXP(XEXP(x, 1),0)) == REG)))
3541 /* When optimising for size, multiplication by constant
3542 should be discouraged slightly over multiplication by a
3544 if (picochip_has_mac_unit)
3546 /* Single cycle multiplication, but the result must be
3547 loaded back into a general register afterwards. */
3548 *total = COSTS_N_INSNS(2);
3551 else if (picochip_has_mul_unit)
3553 /* Single cycle multiplication. */
3554 *total = COSTS_N_INSNS(1);
3557 /* Else no multiply available. Use default cost. */
3567 if (localTotal != 0)
3569 *total = localTotal;
3580 picochip_final_prescan_insn (rtx insn, rtx * opvec ATTRIBUTE_UNUSED,
3581 int num_operands ATTRIBUTE_UNUSED)
3585 picochip_current_prescan_insn = insn;
3588 printf ("Final prescan on INSN %d with mode %s\n",
3589 INSN_UID (insn), GET_MODE_NAME (GET_MODE (insn)));
3591 /* If this is the start of a new instruction cycle, or no scheduling
3592 is used, then reset the VLIW status. */
3593 if (GET_MODE (insn) == TImode || !picochip_schedule_type == DFA_TYPE_SPEED)
3594 picochip_reset_vliw (insn);
3596 /* No VLIW scheduling occured, so don't go any further. */
3597 if (picochip_schedule_type != DFA_TYPE_SPEED)
3600 /* Look for the next printable instruction. This loop terminates on
3601 any recognisable instruction, and on any unrecognisable
3602 instruction with TImode. */
3604 for (local_insn = NEXT_INSN (local_insn); local_insn;
3605 local_insn = NEXT_INSN (local_insn))
3607 if (NOTE_P (local_insn) || DEBUG_INSN_P(local_insn))
3609 else if (!INSN_P (local_insn))
3611 else if (GET_MODE (local_insn) == TImode
3612 || INSN_CODE (local_insn) != -1)
3616 /* Set the continuation flag if the next instruction can be packed
3617 with the current instruction (i.e., the next instruction is
3618 valid, and isn't the start of a new cycle). */
3619 picochip_vliw_continuation = (local_insn && NONDEBUG_INSN_P (local_insn) &&
3620 (GET_MODE (local_insn) != TImode));
3624 /* Builtin functions. */
3625 /* Given a builtin function taking 2 operands (i.e., target + source),
3626 emit the RTL for the underlying instruction. */
3628 picochip_expand_builtin_2op (enum insn_code icode, tree arglist, rtx target)
3632 enum machine_mode tmode, mode0;
3634 /* Grab the incoming argument and emit its RTL. */
3635 arg0 = TREE_VALUE (arglist);
3636 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3638 /* Determine the modes of the instruction operands. */
3639 tmode = insn_data[icode].operand[0].mode;
3640 mode0 = insn_data[icode].operand[1].mode;
3642 /* Ensure that the incoming argument RTL is in a register of the
3644 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
3645 op0 = copy_to_mode_reg (mode0, op0);
3647 /* If there isn't a suitable target, emit a target register. */
3649 || GET_MODE (target) != tmode
3650 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
3651 target = gen_reg_rtx (tmode);
3653 /* Emit and return the new instruction. */
3654 pat = GEN_FCN (icode) (target, op0);
3663 /* Given a builtin function taking 3 operands (i.e., target + two
3664 source), emit the RTL for the underlying instruction. */
3666 picochip_expand_builtin_3op (enum insn_code icode, tree arglist, rtx target)
3670 enum machine_mode tmode, mode0, mode1;
3672 /* Grab the function's arguments. */
3673 arg0 = TREE_VALUE (arglist);
3674 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3676 /* Emit rtl sequences for the function arguments. */
3677 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3678 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3680 /* Get the mode's of each of the instruction operands. */
3681 tmode = insn_data[icode].operand[0].mode;
3682 mode0 = insn_data[icode].operand[1].mode;
3683 mode1 = insn_data[icode].operand[2].mode;
3685 /* Ensure that each of the function argument rtl sequences are in a
3686 register of the correct mode. */
3687 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
3688 op0 = copy_to_mode_reg (mode0, op0);
3689 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
3690 op1 = copy_to_mode_reg (mode1, op1);
3692 /* If no target has been given, create a register to use as the target. */
3694 || GET_MODE (target) != tmode
3695 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
3696 target = gen_reg_rtx (tmode);
3698 /* Emit and return the new instruction. */
3699 pat = GEN_FCN (icode) (target, op0, op1);
3708 /* Expand a builtin function which takes two arguments, and returns a void. */
3710 picochip_expand_builtin_2opvoid (enum insn_code icode, tree arglist)
3714 enum machine_mode mode0, mode1;
3716 /* Grab the function's arguments. */
3717 arg0 = TREE_VALUE (arglist);
3718 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3720 /* Emit rtl sequences for the function arguments. */
3721 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3722 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3724 /* Get the mode's of each of the instruction operands. */
3725 mode0 = insn_data[icode].operand[0].mode;
3726 mode1 = insn_data[icode].operand[1].mode;
3728 /* Ensure that each of the function argument rtl sequences are in a
3729 register of the correct mode. */
3730 if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
3731 op0 = copy_to_mode_reg (mode0, op0);
3732 if (!(*insn_data[icode].operand[1].predicate) (op1, mode1))
3733 op1 = copy_to_mode_reg (mode1, op1);
3735 /* Emit and return the new instruction. */
3736 pat = GEN_FCN (icode) (op0, op1);
3745 /* Expand an array get into the corresponding RTL. */
3747 picochip_expand_array_get (tree arglist, rtx target)
3749 tree arg0, arg1, arg2;
3750 rtx op0, op1, op2, pat;
3752 /* Grab the function's arguments. */
3753 arg0 = TREE_VALUE (arglist);
3754 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3755 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3757 /* Emit rtl sequences for the function arguments. */
3758 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3759 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3760 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
3762 /* The second and third operands must be constant. Nothing else will
3764 if (CONST_INT != GET_CODE (op1))
3765 internal_error ("%s: Second source operand is not a constant",
3767 if (CONST_INT != GET_CODE (op2))
3768 internal_error ("%s: Third source operand is not a constant",
3771 /* If no target has been given, create a register to use as the target. */
3772 if (target == 0 || GET_MODE (target) != SImode)
3773 target = gen_reg_rtx (SImode);
3775 /* The first operand must be a HImode register or a constant. If it
3776 isn't, force it into a HImode register. */
3777 if (GET_MODE (op0) != HImode || REG != GET_CODE (op0))
3778 op0 = copy_to_mode_reg (HImode, op0);
3781 /* Emit and return the new instruction. */
3782 pat = gen_commsArrayGet (target, op0, op1, op2);
3789 /* Expand an array put into the corresponding RTL. */
3791 picochip_expand_array_put (tree arglist, rtx target)
3793 tree arg0, arg1, arg2, arg3;
3794 rtx op0, op1, op2, op3, pat;
3796 /* Grab the function's arguments. */
3797 arg0 = TREE_VALUE (arglist);
3798 arg1 = TREE_VALUE (arglist->common.chain);
3799 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3800 arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
3802 /* Emit rtl sequences for the function arguments. */
3803 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3804 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3805 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
3806 op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
3808 /* The first operand must be an SImode register. */
3809 if (GET_MODE (op0) != SImode || REG != GET_CODE (op0))
3810 op0 = copy_to_mode_reg (SImode, op0);
3812 /* The second (index) operand must be a HImode register, or a
3813 constant. If it isn't, force it into a HImode register. */
3814 if (GET_MODE (op1) != HImode || REG != GET_CODE (op1))
3815 op1 = copy_to_mode_reg (HImode, op1);
3817 /* The remaining operands must be constant. Nothing else will do. */
3818 if (CONST_INT != GET_CODE (op2))
3819 internal_error ("%s: Third source operand is not a constant",
3821 if (CONST_INT != GET_CODE (op3))
3822 internal_error ("%s: Fourth source operand is not a constant",
3825 /* Emit and return the new instruction. */
3826 pat = gen_commsArrayPut (op0, op1, op2, op3);
3833 /* Expand an array testport into the corresponding RTL. */
3835 picochip_expand_array_testport (tree arglist, rtx target)
3837 tree arg0, arg1, arg2;
3838 rtx op0, op1, op2, pat;
3840 /* Grab the function's arguments. */
3841 arg0 = TREE_VALUE (arglist);
3842 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3843 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3845 /* Emit rtl sequences for the function arguments. */
3846 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3847 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3848 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
3850 /* The first operand must be a HImode register, or a constant. If it
3851 isn't, force it into a HImode register. */
3852 if (GET_MODE (op0) != HImode || REG != GET_CODE (op0))
3853 op0 = copy_to_mode_reg (HImode, op0);
3855 /* The second and third operands must be constant. Nothing else will
3857 if (CONST_INT != GET_CODE (op1))
3858 internal_error ("%s: Second source operand is not a constant",
3860 if (CONST_INT != GET_CODE (op2))
3861 internal_error ("%s: Third source operand is not a constant",
3864 /* If no target has been given, create a HImode register to use as
3866 if (target == 0 || GET_MODE (target) != HImode)
3867 target = gen_reg_rtx (HImode);
3869 /* Emit and return the new instruction. */
3870 pat = gen_commsArrayTestPort (target, op0, op1, op2);
3877 /* Generate a unique HALT instruction by giving the instruction a
3878 unique integer. This integer makes no difference to the assembly
3879 output (other than a comment indicating the supplied id), but the
3880 presence of the unique integer prevents the compiler from combining
3881 several different halt instructions into one instruction. This
3882 means that each use of the halt instruction is unique, which in
3883 turn means that assertions work as expected. */
3885 picochip_generate_halt (void)
3887 static int currentId = 0;
3888 rtx id = GEN_INT (currentId);
3892 emit_insn (gen_halt (id));
3894 /* A barrier is inserted to prevent the compiler from thinking that
3895 it has to continue execution after the HALT.*/
3898 rtx insns = get_insns();
3905 /* Initialise the builtin functions. Start by initialising
3906 descriptions of different types of functions (e.g., void fn(int),
3907 int fn(void)), and then use these to define the builtins. */
3909 picochip_init_builtins (void)
3911 tree endlink = void_list_node;
3912 tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
3913 tree unsigned_endlink = tree_cons (NULL_TREE, unsigned_type_node, endlink);
3914 tree long_endlink = tree_cons (NULL_TREE, long_integer_type_node, endlink);
3915 tree int_int_endlink =
3916 tree_cons (NULL_TREE, integer_type_node, int_endlink);
3917 tree int_int_int_endlink =
3918 tree_cons (NULL_TREE, integer_type_node, int_int_endlink);
3919 tree int_long_endlink =
3920 tree_cons (NULL_TREE, integer_type_node, long_endlink);
3921 tree pchar_type_node = build_pointer_type (char_type_node);
3922 tree long_int_int_int_endlink =
3923 tree_cons (NULL_TREE, long_integer_type_node, int_int_int_endlink);
3925 tree int_ftype_void, int_ftype_int, int_ftype_int_int, void_ftype_pchar;
3926 tree long_ftype_int, long_ftype_int_int, long_ftype_int_int_int;
3927 tree void_ftype_int_long, int_ftype_int_int_int,
3928 void_ftype_long_int_int_int;
3929 tree void_ftype_void, void_ftype_int, unsigned_ftype_unsigned;
3931 /* void func (void) */
3932 void_ftype_void = build_function_type (void_type_node, endlink);
3934 /* void func (void *) */
3936 = build_function_type (void_type_node,
3937 tree_cons (NULL_TREE, pchar_type_node, endlink));
3939 /* int func (void) */
3940 int_ftype_void = build_function_type (integer_type_node, endlink);
3942 /* void func (int) */
3943 void_ftype_int = build_function_type (void_type_node, int_endlink);
3945 /* int func (int) */
3946 int_ftype_int = build_function_type (integer_type_node, int_endlink);
3948 /* unsigned int func (unsigned int) */
3949 unsigned_ftype_unsigned = build_function_type (unsigned_type_node, unsigned_endlink);
3951 /* int func(int, int) */
3953 = build_function_type (integer_type_node, int_int_endlink);
3955 /* long func(int) */
3956 long_ftype_int = build_function_type (long_integer_type_node, int_endlink);
3958 /* long func(int, int) */
3960 = build_function_type (long_integer_type_node, int_int_endlink);
3962 /* long func(int, int, int) */
3963 long_ftype_int_int_int
3964 = build_function_type (long_integer_type_node, int_int_int_endlink);
3966 /* int func(int, int, int) */
3967 int_ftype_int_int_int
3968 = build_function_type (integer_type_node, int_int_int_endlink);
3970 /* void func(int, long) */
3972 = build_function_type (void_type_node, int_long_endlink);
3974 /* void func(long, int, int, int) */
3975 void_ftype_long_int_int_int
3976 = build_function_type (void_type_node, long_int_int_int_endlink);
3978 /* Initialise the sign-bit-count function. */
3979 add_builtin_function ("__builtin_sbc", int_ftype_int,
3980 PICOCHIP_BUILTIN_SBC, BUILT_IN_MD, NULL,
3982 add_builtin_function ("picoSbc", int_ftype_int, PICOCHIP_BUILTIN_SBC,
3983 BUILT_IN_MD, NULL, NULL_TREE);
3985 /* Initialise the bit reverse function. */
3986 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned,
3987 PICOCHIP_BUILTIN_BREV, BUILT_IN_MD, NULL,
3989 add_builtin_function ("picoBrev", unsigned_ftype_unsigned,
3990 PICOCHIP_BUILTIN_BREV, BUILT_IN_MD, NULL,
3993 /* Initialise the byte swap function. */
3994 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned,
3995 PICOCHIP_BUILTIN_BYTESWAP, BUILT_IN_MD, NULL,
3997 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned,
3998 PICOCHIP_BUILTIN_BYTESWAP, BUILT_IN_MD, NULL,
4001 /* Initialise the ASRI function (note that while this can be coded
4002 using a signed shift in C, extra scratch registers are required,
4003 which we avoid by having a direct builtin to map to the
4005 add_builtin_function ("__builtin_asri", int_ftype_int_int,
4006 PICOCHIP_BUILTIN_ASRI, BUILT_IN_MD, NULL,
4009 /* Initialise saturating addition. */
4010 add_builtin_function ("__builtin_adds", int_ftype_int_int,
4011 PICOCHIP_BUILTIN_ADDS, BUILT_IN_MD, NULL,
4013 add_builtin_function ("picoAdds", int_ftype_int_int,
4014 PICOCHIP_BUILTIN_ADDS, BUILT_IN_MD, NULL,
4017 /* Initialise saturating subtraction. */
4018 add_builtin_function ("__builtin_subs", int_ftype_int_int,
4019 PICOCHIP_BUILTIN_SUBS, BUILT_IN_MD, NULL,
4021 add_builtin_function ("picoSubs", int_ftype_int_int,
4022 PICOCHIP_BUILTIN_SUBS, BUILT_IN_MD, NULL,
4025 /* Scalar comms builtins. */
4026 add_builtin_function ("__builtin_get", long_ftype_int,
4027 PICOCHIP_BUILTIN_GET, BUILT_IN_MD, NULL,
4029 add_builtin_function ("__builtin_put", void_ftype_int_long,
4030 PICOCHIP_BUILTIN_PUT, BUILT_IN_MD, NULL,
4032 add_builtin_function ("__builtin_testport", int_ftype_int,
4033 PICOCHIP_BUILTIN_TESTPORT, BUILT_IN_MD, NULL,
4036 /* Array comms builtins. */
4037 add_builtin_function ("__builtin_put_array",
4038 void_ftype_long_int_int_int,
4039 PICOCHIP_BUILTIN_PUT_ARRAY, BUILT_IN_MD, NULL,
4041 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int,
4042 PICOCHIP_BUILTIN_GET_ARRAY, BUILT_IN_MD, NULL,
4044 add_builtin_function ("__builtin_testport_array",
4045 int_ftype_int_int_int,
4046 PICOCHIP_BUILTIN_TESTPORT_ARRAY, BUILT_IN_MD,
4049 /* Halt instruction. Note that the builtin function is marked as
4050 having the attribute `noreturn' so that the compiler realises
4051 that the halt stops the program dead. */
4052 tree noreturn = tree_cons (get_identifier ("noreturn"), NULL, NULL);
4053 add_builtin_function ("__builtin_halt", void_ftype_void,
4054 PICOCHIP_BUILTIN_HALT, BUILT_IN_MD, NULL,
4056 add_builtin_function ("picoHalt", void_ftype_void,
4057 PICOCHIP_BUILTIN_HALT, BUILT_IN_MD, NULL,
4062 /* Expand a call to a builtin function. */
4064 picochip_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
4065 enum machine_mode mode ATTRIBUTE_UNUSED,
4066 int ignore ATTRIBUTE_UNUSED)
4068 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
4069 tree arglist = CALL_EXPR_ARGS(exp);
4070 int fcode = DECL_FUNCTION_CODE (fndecl);
4074 case PICOCHIP_BUILTIN_ASRI:
4075 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri, arglist,
4078 case PICOCHIP_BUILTIN_ADDS:
4079 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3, arglist,
4082 case PICOCHIP_BUILTIN_SUBS:
4083 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3, arglist,
4086 case PICOCHIP_BUILTIN_SBC:
4087 return picochip_expand_builtin_2op (CODE_FOR_sbc, arglist, target);
4089 case PICOCHIP_BUILTIN_BREV:
4090 return picochip_expand_builtin_2op (CODE_FOR_brev, arglist, target);
4092 case PICOCHIP_BUILTIN_BYTESWAP:
4093 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2, arglist, target);
4095 case PICOCHIP_BUILTIN_GET:
4096 return picochip_expand_builtin_2op (CODE_FOR_commsGet, arglist, target);
4098 case PICOCHIP_BUILTIN_PUT:
4099 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut, arglist);
4101 case PICOCHIP_BUILTIN_TESTPORT:
4102 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort, arglist,
4105 case PICOCHIP_BUILTIN_PUT_ARRAY:
4106 return picochip_expand_array_put (arglist, target);
4108 case PICOCHIP_BUILTIN_GET_ARRAY:
4109 return picochip_expand_array_get (arglist, target);
4111 case PICOCHIP_BUILTIN_TESTPORT_ARRAY:
4112 return picochip_expand_array_testport (arglist, target);
4114 case PICOCHIP_BUILTIN_HALT:
4115 return picochip_generate_halt ();
4122 /* Should really do something sensible here. */
4126 /* Emit warnings. */
4128 picochip_warn_inefficient (const char *msg)
4130 if (TARGET_INEFFICIENT_WARNINGS)
4131 warning (OPT_minefficient_warnings,
4132 "%s (disable warning using -mno-inefficient-warnings)", msg);
4136 warn_of_byte_access (void)
4138 static int warned = 0;
4142 picochip_warn_inefficient
4143 ("byte access is synthesised - consider using MUL AE");
4150 picochip_function_value (const_tree valtype, const_tree func,
4151 bool outgoing ATTRIBUTE_UNUSED)
4153 enum machine_mode mode = TYPE_MODE (valtype);
4154 int unsignedp = TYPE_UNSIGNED (valtype);
4156 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4157 just as PROMOTE_MODE does. */
4158 mode = promote_function_mode (valtype, mode, &unsignedp, func, 1);
4160 return gen_rtx_REG (mode, 0);
4164 /* Check that the value of the given mode will fit in the register of
4167 picochip_hard_regno_mode_ok (int regno, enum machine_mode mode)
4170 if (GET_MODE_CLASS (mode) == MODE_CC)
4171 return regno == CC_REGNUM;
4173 /* If the CC register is being used, then only CC mode values are
4174 allowed (which have already been tested). */
4175 if (regno == CC_REGNUM || regno == ACC_REGNUM)
4178 /* Must be a valid register. */
4182 /* Modes QI and HI may be placed in any register except the CC. */
4183 if (mode == QImode || mode == HImode)
4186 /* DI must be in a quad register. */
4188 return (regno % 4 == 0);
4190 /* All other modes must be placed in a even numbered register. */
4191 return !(regno & 1);
4195 /* Extract the lower and upper components of a constant value. */
4198 picochip_get_low_const (rtx value)
4200 return gen_int_mode (INTVAL (value) & 0xFFFF, HImode);
4204 picochip_get_high_const (rtx value)
4206 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4207 return gen_int_mode ((INTVAL (value) >> 16) & 0xFFFF, HImode);
4211 /* Loading and storing QImode values to and from memory in a machine
4212 without byte access requires might require a scratch
4213 register. However, the scratch register might correspond to the
4214 register in which the value is being loaded. To ensure that a
4215 scratch register is supplied which is definitely different to the
4216 output register, request a register pair. This effectively gives a
4217 choice of two registers to choose from, so that we a guaranteed to
4218 get at least one register which is different to the output
4219 register. This trick is taken from the alpha implementation. */
4221 picochip_secondary_reload (bool in_p,
4222 rtx x ATTRIBUTE_UNUSED,
4223 enum reg_class cla ATTRIBUTE_UNUSED,
4224 enum machine_mode mode,
4225 secondary_reload_info *sri)
4227 if (mode == QImode && !TARGET_HAS_BYTE_ACCESS)
4230 sri->icode = CODE_FOR_reload_outqi;
4232 sri->icode = CODE_FOR_reload_inqi;
4235 /* We dont need to return a register class type when we need only a
4236 scratch register. It realizes the scratch register type by looking
4237 at the instruction definition for sri->icode. We only need to
4238 return the register type when we need intermediaries for copies.*/
4242 /* Return true if the given memory operand can be aligned to a
4243 word+offset memory reference (e.g., FP+3 can be converted into the
4244 memory operand FP+2, with the offset 1). */
4246 picochip_alignable_memory_operand (rtx mem_operand,
4247 enum machine_mode mode ATTRIBUTE_UNUSED)
4251 /* Not a mem operand. Refuse immediately. */
4252 if (MEM != GET_CODE (mem_operand))
4255 address = XEXP (mem_operand, 0);
4257 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4258 return ((PLUS == GET_CODE (address) &&
4259 REGNO (XEXP (address, 0)) == STACK_POINTER_REGNUM &&
4260 CONST_INT == GET_CODE (XEXP (address, 1)) &&
4261 picochip_const_ok_for_letter_p (INTVAL (XEXP (address, 1)), 'K'))
4262 || (REG == GET_CODE (address)
4263 && REGNO (address) == STACK_POINTER_REGNUM));
4267 /* Return true if the given memory reference is to a word aligned
4268 address. Currently this means it must be either SP, or
4269 SP+offset. We could replace this function with alignable
4270 memory references in the above function?. */
4272 picochip_word_aligned_memory_reference (rtx operand)
4276 /* The address must be the SP register, or a constant, aligned
4277 offset from SP which doesn't exceed the FP+offset
4279 return ((PLUS == GET_CODE (operand)
4280 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
4281 && picochip_is_aligned (INTVAL (XEXP (operand, 1)), 16)
4282 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand, 1)),
4284 || (REG == GET_CODE (operand)
4285 && REGNO (operand) == STACK_POINTER_REGNUM));
4289 /* Given an alignable memory location, convert the memory location
4290 into a HI mode access, storing the new memory reference in
4291 paligned_mem, and the number of bits by which to shift in pbitnum
4292 (i.e., given a reference to FP+3, this creates an aligned reference
4293 of FP+2, with an 8-bit shift). This code is a modification of that
4294 found in the Alpha port. */
4296 picochip_get_hi_aligned_mem (rtx ref, rtx * paligned_mem, rtx * pbitnum)
4299 HOST_WIDE_INT offset = 0;
4301 gcc_assert (GET_CODE (ref) == MEM);
4303 if (reload_in_progress && !memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
4305 base = find_replacement (&XEXP (ref, 0));
4307 gcc_assert(memory_address_p (GET_MODE (ref), base));
4311 base = XEXP (ref, 0);
4314 if (GET_CODE (base) == PLUS)
4316 offset += INTVAL (XEXP (base, 1));
4317 base = XEXP (base, 0);
4320 *paligned_mem = widen_memory_access (ref, HImode, (offset & ~1) - offset);
4327 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4331 *pbitnum = GEN_INT ((offset & 1) * 8);
4335 /* Return true if the given operand is an absolute address in memory
4336 (i.e., a symbolic offset). */
4338 picochip_absolute_memory_operand (rtx op,
4339 enum machine_mode mode ATTRIBUTE_UNUSED)
4342 if (MEM == GET_CODE (op))
4344 rtx address = XEXP (op, 0);
4346 /* Symbols are valid absolute addresses. */
4347 if (SYMBOL_REF == GET_CODE (address))
4350 /* Constant offsets to symbols are valid absolute addresses. */
4351 if (CONST == GET_CODE (address) &&
4352 PLUS == GET_CODE (XEXP (address, 0)) &&
4353 SYMBOL_REF == GET_CODE (XEXP (XEXP (address, 0), 0)) &&
4354 CONST_INT == GET_CODE (XEXP (XEXP (address, 0), 1)))
4361 /* Symbols are valid absolute addresses. */
4362 if (SYMBOL_REF == GET_CODE (XEXP (op, 0)))
4371 picochip_asm_named_section (const char *name,
4372 unsigned int flags ATTRIBUTE_UNUSED,
4373 tree decl ATTRIBUTE_UNUSED)
4375 fprintf (asm_out_file, ".section %s\n", name);
4379 /* Check if we can make a conditional copy instruction. This is emitted as an
4380 instruction to set the condition register, followed by an instruction which
4381 uses the condition registers to perform the conditional move. */
4383 picochip_check_conditional_copy (rtx * operands)
4386 rtx branch_op_0 = XEXP (operands[1], 0);
4387 rtx branch_op_1 = XEXP (operands[1], 1);
4389 /* Only HI mode conditional moves are currently allowed. Can we add
4391 if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
4394 /* Is the comparison valid? Only allow operands which are registers
4395 if they are HImode. SI mode comparisons against 0 could be
4396 handled using logical operations (e.g., SIreg != 0 when low ||
4397 high). Need to find test cases to provoke this though (fixunssfdi
4398 in libgcc does, but is complicated). */
4399 if (GET_MODE (branch_op_0) != HImode ||
4400 !(register_operand (branch_op_0, GET_MODE (branch_op_0))))
4402 if (GET_MODE (branch_op_1) != HImode ||
4403 !(picochip_comparison_operand (branch_op_1, GET_MODE (branch_op_1))))
4412 picochip_static_chain (const_tree ARG_UNUSED (fndecl), bool incoming_p)
4416 addr = arg_pointer_rtx;
4418 addr = plus_constant (stack_pointer_rtx, -2 * UNITS_PER_WORD);
4419 return gen_frame_mem (Pmode, addr);