1 /* Subroutines for gcc2 for pdp11.
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2004, 2005,
3 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "diagnostic-core.h"
42 #include "target-def.h"
45 /* this is the current value returned by the macro FIRST_PARM_OFFSET
47 int current_first_parm_offset;
49 /* Routines to encode/decode pdp11 floats */
50 static void encode_pdp11_f (const struct real_format *fmt,
51 long *, const REAL_VALUE_TYPE *);
52 static void decode_pdp11_f (const struct real_format *,
53 REAL_VALUE_TYPE *, const long *);
54 static void encode_pdp11_d (const struct real_format *fmt,
55 long *, const REAL_VALUE_TYPE *);
56 static void decode_pdp11_d (const struct real_format *,
57 REAL_VALUE_TYPE *, const long *);
59 /* These two are taken from the corresponding vax descriptors
60 in real.c, changing only the encode/decode routine pointers. */
61 const struct real_format pdp11_f_format =
82 const struct real_format pdp11_d_format =
104 encode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf,
105 const REAL_VALUE_TYPE *r)
107 (*vax_f_format.encode) (fmt, buf, r);
108 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
112 decode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED,
113 REAL_VALUE_TYPE *r, const long *buf)
116 tbuf = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
117 (*vax_f_format.decode) (fmt, r, &tbuf);
121 encode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf,
122 const REAL_VALUE_TYPE *r)
124 (*vax_d_format.encode) (fmt, buf, r);
125 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
126 buf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16);
130 decode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED,
131 REAL_VALUE_TYPE *r, const long *buf)
134 tbuf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
135 tbuf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16);
136 (*vax_d_format.decode) (fmt, r, tbuf);
139 /* This is where the condition code register lives. */
140 /* rtx cc0_reg_rtx; - no longer needed? */
142 static bool pdp11_handle_option (size_t, const char *, int);
143 static void pdp11_option_init_struct (struct gcc_options *);
144 static rtx find_addr_reg (rtx);
145 static const char *singlemove_string (rtx *);
146 static bool pdp11_assemble_integer (rtx, unsigned int, int);
147 static void pdp11_output_function_prologue (FILE *, HOST_WIDE_INT);
148 static void pdp11_output_function_epilogue (FILE *, HOST_WIDE_INT);
149 static bool pdp11_rtx_costs (rtx, int, int, int *, bool);
150 static bool pdp11_return_in_memory (const_tree, const_tree);
151 static rtx pdp11_function_value (const_tree, const_tree, bool);
152 static rtx pdp11_libcall_value (enum machine_mode, const_rtx);
153 static bool pdp11_function_value_regno_p (const unsigned int);
154 static void pdp11_trampoline_init (rtx, tree, rtx);
155 static rtx pdp11_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
157 static void pdp11_function_arg_advance (CUMULATIVE_ARGS *,
158 enum machine_mode, const_tree, bool);
159 static void pdp11_conditional_register_usage (void);
161 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
163 static const struct default_options pdp11_option_optimization_table[] =
165 { OPT_LEVELS_3_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
166 { OPT_LEVELS_NONE, 0, NULL, 0 }
169 /* Initialize the GCC target structure. */
170 #undef TARGET_ASM_BYTE_OP
171 #define TARGET_ASM_BYTE_OP NULL
172 #undef TARGET_ASM_ALIGNED_HI_OP
173 #define TARGET_ASM_ALIGNED_HI_OP NULL
174 #undef TARGET_ASM_ALIGNED_SI_OP
175 #define TARGET_ASM_ALIGNED_SI_OP NULL
176 #undef TARGET_ASM_INTEGER
177 #define TARGET_ASM_INTEGER pdp11_assemble_integer
179 #undef TARGET_ASM_FUNCTION_PROLOGUE
180 #define TARGET_ASM_FUNCTION_PROLOGUE pdp11_output_function_prologue
181 #undef TARGET_ASM_FUNCTION_EPILOGUE
182 #define TARGET_ASM_FUNCTION_EPILOGUE pdp11_output_function_epilogue
184 #undef TARGET_ASM_OPEN_PAREN
185 #define TARGET_ASM_OPEN_PAREN "["
186 #undef TARGET_ASM_CLOSE_PAREN
187 #define TARGET_ASM_CLOSE_PAREN "]"
189 #undef TARGET_DEFAULT_TARGET_FLAGS
190 #define TARGET_DEFAULT_TARGET_FLAGS \
191 (MASK_FPU | MASK_45 | TARGET_UNIX_ASM_DEFAULT)
192 #undef TARGET_HANDLE_OPTION
193 #define TARGET_HANDLE_OPTION pdp11_handle_option
194 #undef TARGET_OPTION_OPTIMIZATION_TABLE
195 #define TARGET_OPTION_OPTIMIZATION_TABLE pdp11_option_optimization_table
196 #undef TARGET_OPTION_INIT_STRUCT
197 #define TARGET_OPTION_INIT_STRUCT pdp11_option_init_struct
199 #undef TARGET_RTX_COSTS
200 #define TARGET_RTX_COSTS pdp11_rtx_costs
202 #undef TARGET_FUNCTION_ARG
203 #define TARGET_FUNCTION_ARG pdp11_function_arg
204 #undef TARGET_FUNCTION_ARG_ADVANCE
205 #define TARGET_FUNCTION_ARG_ADVANCE pdp11_function_arg_advance
207 #undef TARGET_RETURN_IN_MEMORY
208 #define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory
210 #undef TARGET_FUNCTION_VALUE
211 #define TARGET_FUNCTION_VALUE pdp11_function_value
212 #undef TARGET_LIBCALL_VALUE
213 #define TARGET_LIBCALL_VALUE pdp11_libcall_value
214 #undef TARGET_FUNCTION_VALUE_REGNO_P
215 #define TARGET_FUNCTION_VALUE_REGNO_P pdp11_function_value_regno_p
217 #undef TARGET_TRAMPOLINE_INIT
218 #define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init
220 #undef TARGET_SECONDARY_RELOAD
221 #define TARGET_SECONDARY_RELOAD pdp11_secondary_reload
223 #undef TARGET_REGISTER_MOVE_COST
224 #define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost
226 #undef TARGET_PREFERRED_RELOAD_CLASS
227 #define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class
229 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
230 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class
232 #undef TARGET_LEGITIMATE_ADDRESS_P
233 #define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p
235 #undef TARGET_CONDITIONAL_REGISTER_USAGE
236 #define TARGET_CONDITIONAL_REGISTER_USAGE pdp11_conditional_register_usage
238 /* Implement TARGET_HANDLE_OPTION. */
241 pdp11_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
242 int value ATTRIBUTE_UNUSED)
247 target_flags &= ~(MASK_40 | MASK_45);
255 /* Implement TARGET_OPTION_INIT_STRUCT. */
258 pdp11_option_init_struct (struct gcc_options *opts)
260 opts->x_flag_finite_math_only = 0;
261 opts->x_flag_trapping_math = 0;
262 opts->x_flag_signaling_nans = 0;
266 stream is a stdio stream to output the code to.
267 size is an int: how many units of temporary storage to allocate.
268 Refer to the array `regs_ever_live' to determine which registers
269 to save; `regs_ever_live[I]' is nonzero if register number I
270 is ever used in the function. This macro is responsible for
271 knowing which registers should not be saved even if used.
275 pdp11_output_function_prologue (FILE *stream, HOST_WIDE_INT size)
277 HOST_WIDE_INT fsize = ((size) + 1) & ~1;
282 "\n\t; /* function prologue %s*/\n",
283 current_function_name ());
285 /* if we are outputting code for main,
286 the switch FPU to right mode if TARGET_FPU */
287 if (MAIN_NAME_P (DECL_NAME (current_function_decl)) && TARGET_FPU)
290 "\t;/* switch cpu to double float, single integer */\n");
291 fprintf(stream, "\tsetd\n");
292 fprintf(stream, "\tseti\n\n");
295 if (frame_pointer_needed)
297 fprintf(stream, "\tmov r5, -(sp)\n");
298 fprintf(stream, "\tmov sp, r5\n");
307 asm_fprintf (stream, "\tsub $%#wo, sp\n", fsize);
309 /* save CPU registers */
310 for (regno = R0_REGNUM; regno <= PC_REGNUM; regno++)
311 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
312 if (! ((regno == FRAME_POINTER_REGNUM)
313 && frame_pointer_needed))
314 fprintf (stream, "\tmov %s, -(sp)\n", reg_names[regno]);
315 /* fpu regs saving */
317 /* via_ac specifies the ac to use for saving ac4, ac5 */
320 for (regno = AC0_REGNUM; regno <= AC5_REGNUM ; regno++)
323 if (LOAD_FPU_REG_P(regno)
324 && df_regs_ever_live_p (regno)
325 && ! call_used_regs[regno])
327 fprintf (stream, "\tstd %s, -(sp)\n", reg_names[regno]);
331 /* maybe make ac4, ac5 call used regs?? */
333 if (NO_LOAD_FPU_REG_P(regno)
334 && df_regs_ever_live_p (regno)
335 && ! call_used_regs[regno])
337 gcc_assert (via_ac != -1);
338 fprintf (stream, "\tldd %s, %s\n",
339 reg_names[regno], reg_names[via_ac]);
340 fprintf (stream, "\tstd %s, -(sp)\n", reg_names[via_ac]);
344 fprintf (stream, "\t;/* end of prologue */\n\n");
348 The function epilogue should not depend on the current stack pointer!
349 It should use the frame pointer only. This is mandatory because
350 of alloca; we also take advantage of it to omit stack adjustments
353 /* maybe we can make leaf functions faster by switching to the
354 second register file - this way we don't have to save regs!
355 leaf functions are ~ 50% of all functions (dynamically!)
357 set/clear bit 11 (dec. 2048) of status word for switching register files -
358 but how can we do this? the pdp11/45 manual says bit may only
359 be set (p.24), but not cleared!
361 switching to kernel is probably more expensive, so we'll leave it
362 like this and not use the second set of registers...
364 maybe as option if you want to generate code for kernel mode? */
367 pdp11_output_function_epilogue (FILE *stream, HOST_WIDE_INT size)
369 HOST_WIDE_INT fsize = ((size) + 1) & ~1;
374 fprintf (stream, "\n\t; /*function epilogue */\n");
376 if (frame_pointer_needed)
378 /* hope this is safe - m68k does it also .... */
379 df_set_regs_ever_live (FRAME_POINTER_REGNUM, false);
381 for (i = PC_REGNUM, j = 0 ; i >= 0 ; i--)
382 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
385 /* remember # of pushed bytes for CPU regs */
388 /* change fp -> r5 due to the compile error on libgcc2.c */
389 for (i = PC_REGNUM ; i >= R0_REGNUM ; i--)
390 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
391 fprintf(stream, "\tmov %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
392 (-fsize-2*j--)&0xffff, reg_names[i]);
397 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
398 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
404 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
406 if (LOAD_FPU_REG_P(i)
407 && df_regs_ever_live_p (i)
408 && ! call_used_regs[i])
410 fprintf(stream, "\tldd %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
411 (-fsize-k)&0xffff, reg_names[i]);
415 if (NO_LOAD_FPU_REG_P(i)
416 && df_regs_ever_live_p (i)
417 && ! call_used_regs[i])
419 gcc_assert (LOAD_FPU_REG_P(via_ac));
421 fprintf(stream, "\tldd %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
422 (-fsize-k)&0xffff, reg_names[via_ac]);
423 fprintf(stream, "\tstd %s, %s\n", reg_names[via_ac], reg_names[i]);
428 fprintf(stream, "\tmov r5, sp\n");
429 fprintf (stream, "\tmov (sp)+, r5\n");
436 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
437 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
440 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
442 if (LOAD_FPU_REG_P(i)
443 && df_regs_ever_live_p (i)
444 && ! call_used_regs[i])
445 fprintf(stream, "\tldd (sp)+, %s\n", reg_names[i]);
447 if (NO_LOAD_FPU_REG_P(i)
448 && df_regs_ever_live_p (i)
449 && ! call_used_regs[i])
451 gcc_assert (LOAD_FPU_REG_P(via_ac));
453 fprintf(stream, "\tldd (sp)+, %s\n", reg_names[via_ac]);
454 fprintf(stream, "\tstd %s, %s\n", reg_names[via_ac], reg_names[i]);
458 for (i = PC_REGNUM; i >= 0; i--)
459 if (df_regs_ever_live_p (i) && !call_used_regs[i])
460 fprintf(stream, "\tmov (sp)+, %s\n", reg_names[i]);
463 fprintf((stream), "\tadd $%#" HOST_WIDE_INT_PRINT "o, sp\n",
467 fprintf (stream, "\trts pc\n");
468 fprintf (stream, "\t;/* end of epilogue*/\n\n\n");
471 /* Return the best assembler insn template
472 for moving operands[1] into operands[0] as a fullword. */
474 singlemove_string (rtx *operands)
476 if (operands[1] != const0_rtx)
483 /* Output assembler code to perform a doubleword move insn
484 with operands OPERANDS. */
487 output_move_double (rtx *operands)
489 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
491 rtx addreg0 = 0, addreg1 = 0;
493 /* First classify both operands. */
495 if (REG_P (operands[0]))
497 else if (offsettable_memref_p (operands[0]))
499 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
501 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
503 else if (GET_CODE (operands[0]) == MEM)
508 if (REG_P (operands[1]))
510 else if (CONSTANT_P (operands[1])
512 || GET_CODE (operands[1]) == CONST_DOUBLE
516 else if (offsettable_memref_p (operands[1]))
518 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
520 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
522 else if (GET_CODE (operands[1]) == MEM)
527 /* Check for the cases that the operand constraints are not
528 supposed to allow to happen. Abort if we get one,
529 because generating code for these cases is painful. */
531 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
533 /* If one operand is decrementing and one is incrementing
534 decrement the former register explicitly
535 and change that operand into ordinary indexing. */
537 if (optype0 == PUSHOP && optype1 == POPOP)
539 operands[0] = XEXP (XEXP (operands[0], 0), 0);
540 output_asm_insn ("sub $4,%0", operands);
541 operands[0] = gen_rtx_MEM (SImode, operands[0]);
544 if (optype0 == POPOP && optype1 == PUSHOP)
546 operands[1] = XEXP (XEXP (operands[1], 0), 0);
547 output_asm_insn ("sub $4,%1", operands);
548 operands[1] = gen_rtx_MEM (SImode, operands[1]);
552 /* If an operand is an unoffsettable memory ref, find a register
553 we can increment temporarily to make it refer to the second word. */
555 if (optype0 == MEMOP)
556 addreg0 = find_addr_reg (XEXP (operands[0], 0));
558 if (optype1 == MEMOP)
559 addreg1 = find_addr_reg (XEXP (operands[1], 0));
561 /* Ok, we can do one word at a time.
562 Normally we do the low-numbered word first,
563 but if either operand is autodecrementing then we
564 do the high-numbered word first.
566 In either case, set up in LATEHALF the operands to use
567 for the high-numbered word and in some cases alter the
568 operands in OPERANDS to be suitable for the low-numbered word. */
570 if (optype0 == REGOP)
571 latehalf[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
572 else if (optype0 == OFFSOP)
573 latehalf[0] = adjust_address (operands[0], HImode, 2);
575 latehalf[0] = operands[0];
577 if (optype1 == REGOP)
578 latehalf[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1);
579 else if (optype1 == OFFSOP)
580 latehalf[1] = adjust_address (operands[1], HImode, 2);
581 else if (optype1 == CNSTOP)
583 if (CONSTANT_P (operands[1]))
585 /* now the mess begins, high word is in lower word???
587 that's what ashc makes me think, but I don't remember :-( */
588 latehalf[1] = GEN_INT (INTVAL(operands[1]) >> 16);
589 operands[1] = GEN_INT (INTVAL(operands[1]) & 0xff);
592 /* immediate 32-bit values not allowed */
593 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE);
596 latehalf[1] = operands[1];
598 /* If insn is effectively movd N(sp),-(sp) then we will do the
599 high word first. We should use the adjusted operand 1 (which is N+4(sp))
600 for the low word as well, to compensate for the first decrement of sp. */
601 if (optype0 == PUSHOP
602 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
603 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
604 operands[1] = latehalf[1];
606 /* If one or both operands autodecrementing,
607 do the two words, high-numbered first. */
609 /* Likewise, the first move would clobber the source of the second one,
610 do them in the other order. This happens only for registers;
611 such overlap can't happen in memory unless the user explicitly
612 sets it up, and that is an undefined circumstance. */
614 if (optype0 == PUSHOP || optype1 == PUSHOP
615 || (optype0 == REGOP && optype1 == REGOP
616 && REGNO (operands[0]) == REGNO (latehalf[1])))
618 /* Make any unoffsettable addresses point at high-numbered word. */
620 output_asm_insn ("add $2,%0", &addreg0);
622 output_asm_insn ("add $2,%0", &addreg1);
625 output_asm_insn (singlemove_string (latehalf), latehalf);
627 /* Undo the adds we just did. */
629 output_asm_insn ("sub $2,%0", &addreg0);
631 output_asm_insn ("sub $2,%0", &addreg1);
633 /* Do low-numbered word. */
634 return singlemove_string (operands);
637 /* Normal case: do the two words, low-numbered first. */
639 output_asm_insn (singlemove_string (operands), operands);
641 /* Make any unoffsettable addresses point at high-numbered word. */
643 output_asm_insn ("add $2,%0", &addreg0);
645 output_asm_insn ("add $2,%0", &addreg1);
648 output_asm_insn (singlemove_string (latehalf), latehalf);
650 /* Undo the adds we just did. */
652 output_asm_insn ("sub $2,%0", &addreg0);
654 output_asm_insn ("sub $2,%0", &addreg1);
658 /* Output assembler code to perform a quadword move insn
659 with operands OPERANDS. */
662 output_move_quad (rtx *operands)
664 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
666 rtx addreg0 = 0, addreg1 = 0;
668 output_asm_insn(";/* movdi/df: %1 -> %0 */", operands);
670 if (REG_P (operands[0]))
672 else if (offsettable_memref_p (operands[0]))
674 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
676 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
678 else if (GET_CODE (operands[0]) == MEM)
683 if (REG_P (operands[1]))
685 else if (CONSTANT_P (operands[1])
686 || GET_CODE (operands[1]) == CONST_DOUBLE)
688 else if (offsettable_memref_p (operands[1]))
690 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
692 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
694 else if (GET_CODE (operands[1]) == MEM)
699 /* Check for the cases that the operand constraints are not
700 supposed to allow to happen. Abort if we get one,
701 because generating code for these cases is painful. */
703 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
705 if (optype0 == REGOP || optype1 == REGOP)
707 /* check for use of clrd????
708 if you ever allow ac4 and ac5 (now we require secondary load)
709 you must check whether
710 you want to load into them or store from them -
711 then dump ac0 into $help$ movce ac4/5 to ac0, do the
712 store from ac0, and restore ac0 - if you can find
713 an unused ac[0-3], use that and you save a store and a load!*/
715 if (FPU_REG_P(REGNO(operands[0])))
717 if (GET_CODE(operands[1]) == CONST_DOUBLE)
720 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
722 if (REAL_VALUES_EQUAL (r, dconst0))
723 return "{clrd|clrf} %0";
726 return "{ldd|movf} %1, %0";
729 if (FPU_REG_P(REGNO(operands[1])))
730 return "{std|movf} %1, %0";
733 /* If one operand is decrementing and one is incrementing
734 decrement the former register explicitly
735 and change that operand into ordinary indexing. */
737 if (optype0 == PUSHOP && optype1 == POPOP)
739 operands[0] = XEXP (XEXP (operands[0], 0), 0);
740 output_asm_insn ("sub $8,%0", operands);
741 operands[0] = gen_rtx_MEM (DImode, operands[0]);
744 if (optype0 == POPOP && optype1 == PUSHOP)
746 operands[1] = XEXP (XEXP (operands[1], 0), 0);
747 output_asm_insn ("sub $8,%1", operands);
748 operands[1] = gen_rtx_MEM (SImode, operands[1]);
752 /* If an operand is an unoffsettable memory ref, find a register
753 we can increment temporarily to make it refer to the second word. */
755 if (optype0 == MEMOP)
756 addreg0 = find_addr_reg (XEXP (operands[0], 0));
758 if (optype1 == MEMOP)
759 addreg1 = find_addr_reg (XEXP (operands[1], 0));
761 /* Ok, we can do one word at a time.
762 Normally we do the low-numbered word first,
763 but if either operand is autodecrementing then we
764 do the high-numbered word first.
766 In either case, set up in LATEHALF the operands to use
767 for the high-numbered word and in some cases alter the
768 operands in OPERANDS to be suitable for the low-numbered word. */
770 if (optype0 == REGOP)
771 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
772 else if (optype0 == OFFSOP)
773 latehalf[0] = adjust_address (operands[0], SImode, 4);
775 latehalf[0] = operands[0];
777 if (optype1 == REGOP)
778 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
779 else if (optype1 == OFFSOP)
780 latehalf[1] = adjust_address (operands[1], SImode, 4);
781 else if (optype1 == CNSTOP)
783 if (GET_CODE (operands[1]) == CONST_DOUBLE)
787 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
788 REAL_VALUE_TO_TARGET_DOUBLE (r, dval);
789 latehalf[1] = GEN_INT (dval[1]);
790 operands[1] = GEN_INT (dval[0]);
792 else if (GET_CODE(operands[1]) == CONST_INT)
794 latehalf[1] = const0_rtx;
800 latehalf[1] = operands[1];
802 /* If insn is effectively movd N(sp),-(sp) then we will do the
803 high word first. We should use the adjusted operand 1 (which is N+4(sp))
804 for the low word as well, to compensate for the first decrement of sp. */
805 if (optype0 == PUSHOP
806 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
807 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
808 operands[1] = latehalf[1];
810 /* If one or both operands autodecrementing,
811 do the two words, high-numbered first. */
813 /* Likewise, the first move would clobber the source of the second one,
814 do them in the other order. This happens only for registers;
815 such overlap can't happen in memory unless the user explicitly
816 sets it up, and that is an undefined circumstance. */
818 if (optype0 == PUSHOP || optype1 == PUSHOP
819 || (optype0 == REGOP && optype1 == REGOP
820 && REGNO (operands[0]) == REGNO (latehalf[1])))
822 /* Make any unoffsettable addresses point at high-numbered word. */
824 output_asm_insn ("add $4,%0", &addreg0);
826 output_asm_insn ("add $4,%0", &addreg1);
829 output_asm_insn(output_move_double(latehalf), latehalf);
831 /* Undo the adds we just did. */
833 output_asm_insn ("sub $4,%0", &addreg0);
835 output_asm_insn ("sub $4,%0", &addreg1);
837 /* Do low-numbered word. */
838 return output_move_double (operands);
841 /* Normal case: do the two words, low-numbered first. */
843 output_asm_insn (output_move_double (operands), operands);
845 /* Make any unoffsettable addresses point at high-numbered word. */
847 output_asm_insn ("add $4,%0", &addreg0);
849 output_asm_insn ("add $4,%0", &addreg1);
852 output_asm_insn (output_move_double (latehalf), latehalf);
854 /* Undo the adds we just did. */
856 output_asm_insn ("sub $4,%0", &addreg0);
858 output_asm_insn ("sub $4,%0", &addreg1);
864 /* Return a REG that occurs in ADDR with coefficient 1.
865 ADDR can be effectively incremented by incrementing REG. */
868 find_addr_reg (rtx addr)
870 while (GET_CODE (addr) == PLUS)
872 if (GET_CODE (XEXP (addr, 0)) == REG)
873 addr = XEXP (addr, 0);
874 if (GET_CODE (XEXP (addr, 1)) == REG)
875 addr = XEXP (addr, 1);
876 if (CONSTANT_P (XEXP (addr, 0)))
877 addr = XEXP (addr, 1);
878 if (CONSTANT_P (XEXP (addr, 1)))
879 addr = XEXP (addr, 0);
881 if (GET_CODE (addr) == REG)
886 /* Output an ascii string. */
888 output_ascii (FILE *file, const char *p, int size)
892 /* This used to output .byte "string", which doesn't work with the UNIX
893 assembler and I think not with DEC ones either. */
894 fprintf (file, "\t.byte ");
896 for (i = 0; i < size; i++)
898 register int c = p[i];
901 fprintf (file, "%#o", c);
910 print_operand_address (FILE *file, register rtx addr)
918 switch (GET_CODE (addr))
925 addr = XEXP (addr, 0);
930 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
935 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
940 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
946 if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
947 || GET_CODE (XEXP (addr, 0)) == MEM)
949 offset = XEXP (addr, 0);
950 addr = XEXP (addr, 1);
952 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
953 || GET_CODE (XEXP (addr, 1)) == MEM)
955 offset = XEXP (addr, 1);
956 addr = XEXP (addr, 0);
958 if (GET_CODE (addr) != PLUS)
960 else if (GET_CODE (XEXP (addr, 0)) == REG)
962 breg = XEXP (addr, 0);
963 addr = XEXP (addr, 1);
965 else if (GET_CODE (XEXP (addr, 1)) == REG)
967 breg = XEXP (addr, 1);
968 addr = XEXP (addr, 0);
970 if (GET_CODE (addr) == REG)
972 gcc_assert (breg == 0);
978 gcc_assert (addr == 0);
982 output_addr_const_pdp11 (file, addr);
985 gcc_assert (GET_CODE (breg) == REG);
986 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
991 if (!again && GET_CODE (addr) == CONST_INT)
993 /* Absolute (integer number) address. */
994 if (!TARGET_UNIX_ASM)
995 fprintf (file, "@$");
997 output_addr_const_pdp11 (file, addr);
1001 /* Target hook to assemble integer objects. We need to use the
1002 pdp-specific version of output_addr_const. */
1005 pdp11_assemble_integer (rtx x, unsigned int size, int aligned_p)
1011 fprintf (asm_out_file, "\t.byte\t");
1012 output_addr_const_pdp11 (asm_out_file, GEN_INT (INTVAL (x) & 0xff));
1014 fprintf (asm_out_file, " /* char */\n");
1018 fprintf (asm_out_file, TARGET_UNIX_ASM ? "\t" : "\t.word\t");
1019 output_addr_const_pdp11 (asm_out_file, x);
1020 fprintf (asm_out_file, " /* short */\n");
1023 return default_assemble_integer (x, size, aligned_p);
1027 /* register move costs, indexed by regs */
1029 static const int move_costs[N_REG_CLASSES][N_REG_CLASSES] =
1031 /* NO MUL GEN LFPU NLFPU FPU ALL */
1033 /* NO */ { 0, 0, 0, 0, 0, 0, 0},
1034 /* MUL */ { 0, 2, 2, 22, 22, 22, 22},
1035 /* GEN */ { 0, 2, 2, 22, 22, 22, 22},
1036 /* LFPU */ { 0, 22, 22, 2, 2, 2, 22},
1037 /* NLFPU */ { 0, 22, 22, 2, 10, 10, 22},
1038 /* FPU */ { 0, 22, 22, 2, 10, 10, 22},
1039 /* ALL */ { 0, 22, 22, 22, 22, 22, 22}
1043 /* -- note that some moves are tremendously expensive,
1044 because they require lots of tricks! do we have to
1045 charge the costs incurred by secondary reload class
1046 -- as we do here with 10 -- or not ? */
1049 pdp11_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1050 reg_class_t c1, reg_class_t c2)
1052 return move_costs[(int)c1][(int)c2];
1056 pdp11_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total,
1057 bool speed ATTRIBUTE_UNUSED)
1062 if (INTVAL (x) == 0 || INTVAL (x) == -1 || INTVAL (x) == 1)
1072 /* Twice as expensive as REG. */
1077 /* Twice (or 4 times) as expensive as 16 bit. */
1082 /* ??? There is something wrong in MULT because MULT is not
1083 as cheap as total = 2 even if we can shift! */
1084 /* If optimizing for size make mult etc cheap, but not 1, so when
1085 in doubt the faster insn is chosen. */
1087 *total = COSTS_N_INSNS (2);
1089 *total = COSTS_N_INSNS (11);
1094 *total = COSTS_N_INSNS (2);
1096 *total = COSTS_N_INSNS (25);
1101 *total = COSTS_N_INSNS (2);
1103 *total = COSTS_N_INSNS (26);
1107 /* Equivalent to length, so same for optimize_size. */
1108 *total = COSTS_N_INSNS (3);
1112 /* Only used for qi->hi. */
1113 *total = COSTS_N_INSNS (1);
1117 if (GET_MODE (x) == HImode)
1118 *total = COSTS_N_INSNS (1);
1119 else if (GET_MODE (x) == SImode)
1120 *total = COSTS_N_INSNS (6);
1122 *total = COSTS_N_INSNS (2);
1129 *total = COSTS_N_INSNS (1);
1130 else if (GET_MODE (x) == QImode)
1132 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1133 *total = COSTS_N_INSNS (8); /* worst case */
1135 *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1)));
1137 else if (GET_MODE (x) == HImode)
1139 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1141 if (abs (INTVAL (XEXP (x, 1))) == 1)
1142 *total = COSTS_N_INSNS (1);
1144 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1)));
1147 *total = COSTS_N_INSNS (10); /* worst case */
1149 else if (GET_MODE (x) == SImode)
1151 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1152 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1)));
1153 else /* worst case */
1154 *total = COSTS_N_INSNS (18);
1164 output_jump (enum rtx_code code, int inv, int length)
1168 static char buf[1000];
1169 const char *pos, *neg;
1173 case EQ: pos = "beq", neg = "bne"; break;
1174 case NE: pos = "bne", neg = "beq"; break;
1175 case GT: pos = "bgt", neg = "ble"; break;
1176 case GTU: pos = "bhi", neg = "blos"; break;
1177 case LT: pos = "blt", neg = "bge"; break;
1178 case LTU: pos = "blo", neg = "bhis"; break;
1179 case GE: pos = "bge", neg = "blt"; break;
1180 case GEU: pos = "bhis", neg = "blo"; break;
1181 case LE: pos = "ble", neg = "bgt"; break;
1182 case LEU: pos = "blos", neg = "bhi"; break;
1183 default: gcc_unreachable ();
1187 /* currently we don't need this, because the tstdf and cmpdf
1188 copy the condition code immediately, and other float operations are not
1189 yet recognized as changing the FCC - if so, then the length-cost of all
1190 jump insns increases by one, because we have to potentially copy the
1192 if (cc_status.flags & CC_IN_FPU)
1193 output_asm_insn("cfcc", NULL);
1200 sprintf(buf, "%s %%l1", inv ? neg : pos);
1206 sprintf(buf, "%s JMP_%d\n\tjmp %%l1\nJMP_%d:", inv ? pos : neg, x, x);
1220 notice_update_cc_on_set(rtx exp, rtx insn ATTRIBUTE_UNUSED)
1222 if (GET_CODE (SET_DEST (exp)) == CC0)
1224 cc_status.flags = 0;
1225 cc_status.value1 = SET_DEST (exp);
1226 cc_status.value2 = SET_SRC (exp);
1229 if (GET_MODE(SET_SRC(exp)) == DFmode)
1230 cc_status.flags |= CC_IN_FPU;
1233 else if ((GET_CODE (SET_DEST (exp)) == REG
1234 || GET_CODE (SET_DEST (exp)) == MEM)
1235 && GET_CODE (SET_SRC (exp)) != PC
1236 && (GET_MODE (SET_DEST(exp)) == HImode
1237 || GET_MODE (SET_DEST(exp)) == QImode)
1238 && (GET_CODE (SET_SRC(exp)) == PLUS
1239 || GET_CODE (SET_SRC(exp)) == MINUS
1240 || GET_CODE (SET_SRC(exp)) == AND
1241 || GET_CODE (SET_SRC(exp)) == IOR
1242 || GET_CODE (SET_SRC(exp)) == XOR
1243 || GET_CODE (SET_SRC(exp)) == NOT
1244 || GET_CODE (SET_SRC(exp)) == NEG
1245 || GET_CODE (SET_SRC(exp)) == REG
1246 || GET_CODE (SET_SRC(exp)) == MEM))
1248 cc_status.flags = 0;
1249 cc_status.value1 = SET_SRC (exp);
1250 cc_status.value2 = SET_DEST (exp);
1252 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
1254 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
1255 cc_status.value2 = 0;
1256 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
1258 && GET_CODE (cc_status.value2) == MEM)
1259 cc_status.value2 = 0;
1261 else if (GET_CODE (SET_SRC (exp)) == CALL)
1265 else if (GET_CODE (SET_DEST (exp)) == REG)
1268 if ((cc_status.value1
1269 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)))
1270 cc_status.value1 = 0;
1271 if ((cc_status.value2
1272 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)))
1273 cc_status.value2 = 0;
1275 else if (SET_DEST(exp) == pc_rtx)
1279 else /* if (GET_CODE (SET_DEST (exp)) == MEM) */
1281 /* the last else is a bit paranoiac, but since nearly all instructions
1282 play with condition codes, it's reasonable! */
1284 CC_STATUS_INIT; /* paranoia*/
1290 simple_memory_operand(rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1294 /* Eliminate non-memory operations */
1295 if (GET_CODE (op) != MEM)
1299 /* dword operations really put out 2 instructions, so eliminate them. */
1300 if (GET_MODE_SIZE (GET_MODE (op)) > (HAVE_64BIT_P () ? 8 : 4))
1304 /* Decode the address now. */
1308 addr = XEXP (op, 0);
1310 switch (GET_CODE (addr))
1313 /* (R0) - no extra cost */
1318 /* -(R0), (R0)+ - cheap! */
1322 /* cheap - is encoded in addressing mode info!
1324 -- except for @(R0), which has to be @0(R0) !!! */
1326 if (GET_CODE (XEXP (addr, 0)) == REG)
1336 /* @#address - extra cost */
1340 /* X(R0) - extra cost */
1352 * output a block move:
1354 * operands[0] ... to
1355 * operands[1] ... from
1356 * operands[2] ... length
1357 * operands[3] ... alignment
1358 * operands[4] ... scratch register
1363 output_block_move(rtx *operands)
1365 static int count = 0;
1368 if (GET_CODE(operands[2]) == CONST_INT
1371 if (INTVAL(operands[2]) < 16
1372 && INTVAL(operands[3]) == 1)
1376 for (i = 1; i <= INTVAL(operands[2]); i++)
1377 output_asm_insn("movb (%1)+, (%0)+", operands);
1381 else if (INTVAL(operands[2]) < 32)
1385 for (i = 1; i <= INTVAL(operands[2])/2; i++)
1386 output_asm_insn("mov (%1)+, (%0)+", operands);
1388 /* may I assume that moved quantity is
1389 multiple of alignment ???
1398 /* can do other clever things, maybe... */
1401 if (CONSTANT_P(operands[2]) )
1403 /* just move count to scratch */
1404 output_asm_insn("mov %2, %4", operands);
1408 /* just clobber the register */
1409 operands[4] = operands[2];
1413 /* switch over alignment */
1414 switch (INTVAL(operands[3]))
1430 sprintf(buf, "\nmovestrhi%d:", count);
1431 output_asm_insn(buf, NULL);
1433 output_asm_insn("movb (%1)+, (%0)+", operands);
1437 sprintf(buf, "sob %%4, movestrhi%d", count);
1438 output_asm_insn(buf, operands);
1442 output_asm_insn("dec %4", operands);
1444 sprintf(buf, "bgt movestrhi%d", count);
1445 output_asm_insn(buf, NULL);
1467 generate_compact_code:
1469 output_asm_insn("asr %4", operands);
1471 sprintf(buf, "\nmovestrhi%d:", count);
1472 output_asm_insn(buf, NULL);
1474 output_asm_insn("mov (%1)+, (%0)+", operands);
1478 sprintf(buf, "sob %%4, movestrhi%d", count);
1479 output_asm_insn(buf, operands);
1483 output_asm_insn("dec %4", operands);
1485 sprintf(buf, "bgt movestrhi%d", count);
1486 output_asm_insn(buf, NULL);
1512 goto generate_compact_code;
1514 output_asm_insn("asr %4", operands);
1515 output_asm_insn("asr %4", operands);
1517 sprintf(buf, "\nmovestrhi%d:", count);
1518 output_asm_insn(buf, NULL);
1520 output_asm_insn("mov (%1)+, (%0)+", operands);
1521 output_asm_insn("mov (%1)+, (%0)+", operands);
1525 sprintf(buf, "sob %%4, movestrhi%d", count);
1526 output_asm_insn(buf, operands);
1530 output_asm_insn("dec %4", operands);
1532 sprintf(buf, "bgt movestrhi%d", count);
1533 output_asm_insn(buf, NULL);
1563 goto generate_compact_code;
1565 output_asm_insn("asr %4", operands);
1566 output_asm_insn("asr %4", operands);
1567 output_asm_insn("asr %4", operands);
1569 sprintf(buf, "\nmovestrhi%d:", count);
1570 output_asm_insn(buf, NULL);
1572 output_asm_insn("mov (%1)+, (%0)+", operands);
1573 output_asm_insn("mov (%1)+, (%0)+", operands);
1574 output_asm_insn("mov (%1)+, (%0)+", operands);
1575 output_asm_insn("mov (%1)+, (%0)+", operands);
1579 sprintf(buf, "sob %%4, movestrhi%d", count);
1580 output_asm_insn(buf, operands);
1584 output_asm_insn("dec %4", operands);
1586 sprintf(buf, "bgt movestrhi%d", count);
1587 output_asm_insn(buf, NULL);
1600 /* This function checks whether a real value can be encoded as
1601 a literal, i.e., addressing mode 27. In that mode, real values
1602 are one word values, so the remaining 48 bits have to be zero. */
1604 legitimate_const_double_p (rtx address)
1608 REAL_VALUE_FROM_CONST_DOUBLE (r, address);
1609 REAL_VALUE_TO_TARGET_DOUBLE (r, sval);
1610 if ((sval[0] & 0xffff) == 0 && sval[1] == 0)
1615 /* Implement CANNOT_CHANGE_MODE_CLASS. */
1617 pdp11_cannot_change_mode_class (enum machine_mode from,
1618 enum machine_mode to,
1619 enum reg_class rclass)
1621 /* Also, FPU registers contain a whole float value and the parts of
1622 it are not separately accessible.
1624 So we disallow all mode changes involving FPRs. */
1625 if (FLOAT_MODE_P (from) != FLOAT_MODE_P (to))
1628 return reg_classes_intersect_p (FPU_REGS, rclass);
1631 /* TARGET_PREFERRED_RELOAD_CLASS
1633 Given an rtx X being reloaded into a reg required to be
1634 in class CLASS, return the class of reg to actually use.
1635 In general this is just CLASS; but on some machines
1636 in some cases it is preferable to use a more restrictive class.
1638 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1641 pdp11_preferred_reload_class (rtx x, reg_class_t rclass)
1643 if (rclass == FPU_REGS)
1644 return LOAD_FPU_REGS;
1645 if (rclass == ALL_REGS)
1647 if (FLOAT_MODE_P (GET_MODE (x)))
1648 return LOAD_FPU_REGS;
1650 return GENERAL_REGS;
1655 /* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
1657 Given an rtx X being reloaded into a reg required to be
1658 in class CLASS, return the class of reg to actually use.
1659 In general this is just CLASS; but on some machines
1660 in some cases it is preferable to use a more restrictive class.
1662 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1665 pdp11_preferred_output_reload_class (rtx x, reg_class_t rclass)
1667 if (rclass == FPU_REGS)
1668 return LOAD_FPU_REGS;
1669 if (rclass == ALL_REGS)
1671 if (FLOAT_MODE_P (GET_MODE (x)))
1672 return LOAD_FPU_REGS;
1674 return GENERAL_REGS;
1680 /* TARGET_SECONDARY_RELOAD.
1682 FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an
1683 intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else
1684 can be loade/stored directly. */
1686 pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED,
1688 reg_class_t reload_class,
1689 enum machine_mode reload_mode ATTRIBUTE_UNUSED,
1690 secondary_reload_info *sri ATTRIBUTE_UNUSED)
1692 if (reload_class != NO_LOAD_FPU_REGS || GET_CODE (x) != REG ||
1693 REGNO_REG_CLASS (REGNO (x)) == LOAD_FPU_REGS)
1696 return LOAD_FPU_REGS;
1699 /* Target routine to check if register to register move requires memory.
1701 The answer is yes if we're going between general register and FPU
1702 registers. The mode doesn't matter in making this check.
1705 pdp11_secondary_memory_needed (reg_class_t c1, reg_class_t c2,
1706 enum machine_mode mode ATTRIBUTE_UNUSED)
1708 int fromfloat = (c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS ||
1710 int tofloat = (c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS ||
1713 return (fromfloat != tofloat);
1716 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1717 that is a valid memory address for an instruction.
1718 The MODE argument is the machine mode for the MEM expression
1719 that wants to use this address.
1724 pdp11_legitimate_address_p (enum machine_mode mode,
1725 rtx operand, bool strict)
1729 /* accept @#address */
1730 if (CONSTANT_ADDRESS_P (operand))
1733 switch (GET_CODE (operand))
1737 return !strict || REGNO_OK_FOR_BASE_P (REGNO (operand));
1741 return GET_CODE (XEXP (operand, 0)) == REG
1742 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))))
1743 && CONSTANT_ADDRESS_P (XEXP (operand, 1));
1747 return GET_CODE (XEXP (operand, 0)) == REG
1748 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))));
1752 return GET_CODE (XEXP (operand, 0)) == REG
1753 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))));
1756 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */
1757 return GET_CODE (XEXP (operand, 0)) == REG
1758 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
1759 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS
1760 && GET_CODE (XEXP (xfoob, 0)) == REG
1761 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM
1762 && CONSTANT_P (XEXP (xfoob, 1))
1763 && INTVAL (XEXP (xfoob,1)) == -2;
1766 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */
1767 return GET_CODE (XEXP (operand, 0)) == REG
1768 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
1769 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS
1770 && GET_CODE (XEXP (xfoob, 0)) == REG
1771 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM
1772 && CONSTANT_P (XEXP (xfoob, 1))
1773 && INTVAL (XEXP (xfoob,1)) == 2;
1776 /* handle another level of indirection ! */
1777 xfoob = XEXP (operand, 0);
1779 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently
1780 also forbidden for float, because we have to handle this
1781 in output_move_double and/or output_move_quad() - we could
1782 do it, but currently it's not worth it!!!
1783 now that DFmode cannot go into CPU register file,
1784 maybe I should allow float ...
1785 but then I have to handle memory-to-memory moves in movdf ?? */
1786 if (GET_MODE_BITSIZE(mode) > 16)
1789 /* accept @address */
1790 if (CONSTANT_ADDRESS_P (xfoob))
1793 switch (GET_CODE (xfoob))
1796 /* accept @(R0) - which is @0(R0) */
1797 return !strict || REGNO_OK_FOR_BASE_P(REGNO (xfoob));
1801 return GET_CODE (XEXP (xfoob, 0)) == REG
1802 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))))
1803 && CONSTANT_ADDRESS_P (XEXP (xfoob, 1));
1807 return GET_CODE (XEXP (xfoob, 0)) == REG
1808 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))));
1812 return GET_CODE (XEXP (xfoob, 0)) == REG
1813 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))));
1816 /* anything else is invalid */
1821 /* anything else is invalid */
1825 /* Return the class number of the smallest class containing
1826 reg number REGNO. */
1828 pdp11_regno_reg_class (int regno)
1830 if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
1831 return GENERAL_REGS;
1832 else if (regno > AC3_REGNUM)
1833 return NO_LOAD_FPU_REGS;
1834 else if (regno >= AC0_REGNUM)
1835 return LOAD_FPU_REGS;
1839 return GENERAL_REGS;
1844 pdp11_sp_frame_offset (void)
1846 int offset = 0, regno;
1847 offset = get_frame_size();
1848 for (regno = 0; regno <= PC_REGNUM; regno++)
1849 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
1851 for (regno = AC0_REGNUM; regno <= AC5_REGNUM; regno++)
1852 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
1858 /* Return the offset between two registers, one to be eliminated, and the other
1859 its replacement, at the start of a routine. */
1862 pdp11_initial_elimination_offset (int from, int to)
1866 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
1868 else if (from == FRAME_POINTER_REGNUM
1869 && to == HARD_FRAME_POINTER_REGNUM)
1873 gcc_assert (to == STACK_POINTER_REGNUM);
1875 /* Get the size of the register save area. */
1876 spoff = pdp11_sp_frame_offset ();
1877 if (from == FRAME_POINTER_REGNUM)
1880 gcc_assert (from == ARG_POINTER_REGNUM);
1882 /* If there is a frame pointer, that is saved too. */
1883 if (frame_pointer_needed)
1886 /* Account for the saved PC in the function call. */
1891 /* A copy of output_addr_const modified for pdp11 expression syntax.
1892 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't
1893 use, and for debugging output, which we don't support with this port either.
1894 So this copy should get called whenever needed.
1897 output_addr_const_pdp11 (FILE *file, rtx x)
1902 switch (GET_CODE (x))
1905 gcc_assert (flag_pic);
1910 assemble_name (file, XSTR (x, 0));
1914 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0)));
1915 assemble_name (file, buf);
1919 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
1920 assemble_name (file, buf);
1924 fprintf (file, "%#o", (int) INTVAL (x) & 0xffff);
1928 /* This used to output parentheses around the expression,
1929 but that does not work on the 386 (either ATT or BSD assembler). */
1930 output_addr_const_pdp11 (file, XEXP (x, 0));
1934 if (GET_MODE (x) == VOIDmode)
1936 /* We can use %o if the number is one word and positive. */
1937 gcc_assert (!CONST_DOUBLE_HIGH (x));
1938 fprintf (file, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x));
1941 /* We can't handle floating point constants;
1942 PRINT_OPERAND must handle them. */
1943 output_operand_lossage ("floating constant misused");
1947 /* Some assemblers need integer constants to appear last (e.g. masm). */
1948 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
1950 output_addr_const_pdp11 (file, XEXP (x, 1));
1951 if (INTVAL (XEXP (x, 0)) >= 0)
1952 fprintf (file, "+");
1953 output_addr_const_pdp11 (file, XEXP (x, 0));
1957 output_addr_const_pdp11 (file, XEXP (x, 0));
1958 if (INTVAL (XEXP (x, 1)) >= 0)
1959 fprintf (file, "+");
1960 output_addr_const_pdp11 (file, XEXP (x, 1));
1965 /* Avoid outputting things like x-x or x+5-x,
1966 since some assemblers can't handle that. */
1967 x = simplify_subtraction (x);
1968 if (GET_CODE (x) != MINUS)
1971 output_addr_const_pdp11 (file, XEXP (x, 0));
1972 fprintf (file, "-");
1973 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1974 && INTVAL (XEXP (x, 1)) < 0)
1976 fprintf (file, targetm.asm_out.open_paren);
1977 output_addr_const_pdp11 (file, XEXP (x, 1));
1978 fprintf (file, targetm.asm_out.close_paren);
1981 output_addr_const_pdp11 (file, XEXP (x, 1));
1986 output_addr_const_pdp11 (file, XEXP (x, 0));
1990 output_operand_lossage ("invalid expression as operand");
1994 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1997 pdp11_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1999 /* Integers 32 bits and under, and scalar floats (if FPU), are returned
2000 in registers. The rest go into memory. */
2001 return (TYPE_MODE (type) == DImode
2002 || (FLOAT_MODE_P (TYPE_MODE (type)) && ! TARGET_AC0)
2003 || TREE_CODE (type) == VECTOR_TYPE
2004 || COMPLEX_MODE_P (TYPE_MODE (type)));
2007 /* Worker function for TARGET_FUNCTION_VALUE.
2009 On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */
2012 pdp11_function_value (const_tree valtype,
2013 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
2014 bool outgoing ATTRIBUTE_UNUSED)
2016 return gen_rtx_REG (TYPE_MODE (valtype),
2017 BASE_RETURN_VALUE_REG(TYPE_MODE(valtype)));
2020 /* Worker function for TARGET_LIBCALL_VALUE. */
2023 pdp11_libcall_value (enum machine_mode mode,
2024 const_rtx fun ATTRIBUTE_UNUSED)
2026 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG(mode));
2029 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
2031 On the pdp, the first "output" reg is the only register thus used.
2033 maybe ac0 ? - as option someday! */
2036 pdp11_function_value_regno_p (const unsigned int regno)
2038 return (regno == RETVAL_REGNUM) || (TARGET_AC0 && (regno == AC0_REGNUM));
2041 /* Worker function for TARGET_TRAMPOLINE_INIT.
2043 trampoline - how should i do it in separate i+d ?
2044 have some allocate_trampoline magic???
2046 the following should work for shared I/D:
2048 MOV #STATIC, $4 01270Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM
2049 JMP @#FUNCTION 000137 0x0000 <- FUNCTION
2053 pdp11_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2055 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
2058 gcc_assert (!TARGET_SPLIT);
2060 mem = adjust_address (m_tramp, HImode, 0);
2061 emit_move_insn (mem, GEN_INT (012700+STATIC_CHAIN_REGNUM));
2062 mem = adjust_address (m_tramp, HImode, 2);
2063 emit_move_insn (mem, chain_value);
2064 mem = adjust_address (m_tramp, HImode, 4);
2065 emit_move_insn (mem, GEN_INT (000137));
2066 emit_move_insn (mem, fnaddr);
2069 /* Worker function for TARGET_FUNCTION_ARG.
2071 Determine where to put an argument to a function.
2072 Value is zero to push the argument on the stack,
2073 or a hard register in which to store the argument.
2075 MODE is the argument's machine mode.
2076 TYPE is the data type of the argument (as a tree).
2077 This is null for libcalls where that information may
2079 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2080 the preceding args and about the function being called.
2081 NAMED is nonzero if this argument is a named parameter
2082 (otherwise it is an extra parameter matching an ellipsis). */
2085 pdp11_function_arg (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2086 enum machine_mode mode ATTRIBUTE_UNUSED,
2087 const_tree type ATTRIBUTE_UNUSED,
2088 bool named ATTRIBUTE_UNUSED)
2093 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE.
2095 Update the data in CUM to advance over an argument of mode MODE and
2096 data type TYPE. (TYPE is null for libcalls where that information
2097 may not be available.) */
2100 pdp11_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2101 const_tree type, bool named ATTRIBUTE_UNUSED)
2103 *cum += (mode != BLKmode
2104 ? GET_MODE_SIZE (mode)
2105 : int_size_in_bytes (type));
2108 /* Make sure everything's fine if we *don't* have an FPU.
2109 This assumes that putting a register in fixed_regs will keep the
2110 compiler's mitts completely off it. We don't bother to zero it out
2111 of register classes. Also fix incompatible register naming with
2112 the UNIX assembler. */
2115 pdp11_conditional_register_usage (void)
2121 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]);
2122 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ )
2123 if (TEST_HARD_REG_BIT (x, i))
2124 fixed_regs[i] = call_used_regs[i] = 1;
2128 call_used_regs[AC0_REGNUM] = 1;
2129 if (TARGET_UNIX_ASM)
2131 /* Change names of FPU registers for the UNIX assembler. */
2132 reg_names[8] = "fr0";
2133 reg_names[9] = "fr1";
2134 reg_names[10] = "fr2";
2135 reg_names[11] = "fr3";
2136 reg_names[12] = "fr4";
2137 reg_names[13] = "fr5";
2141 struct gcc_target targetm = TARGET_INITIALIZER;