1 /* Subroutines for gcc2 for pdp11.
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2004, 2005,
3 2006, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
34 #include "insn-attr.h"
42 #include "target-def.h"
46 #define FPU_REG_P(X) ((X)>=8 && (X)<14)
47 #define CPU_REG_P(X) ((X)>=0 && (X)<8)
50 /* this is the current value returned by the macro FIRST_PARM_OFFSET
52 int current_first_parm_offset;
54 /* Routines to encode/decode pdp11 floats */
55 static void encode_pdp11_f (const struct real_format *fmt,
56 long *, const REAL_VALUE_TYPE *);
57 static void decode_pdp11_f (const struct real_format *,
58 REAL_VALUE_TYPE *, const long *);
59 static void encode_pdp11_d (const struct real_format *fmt,
60 long *, const REAL_VALUE_TYPE *);
61 static void decode_pdp11_d (const struct real_format *,
62 REAL_VALUE_TYPE *, const long *);
64 /* These two are taken from the corresponding vax descriptors
65 in real.c, changing only the encode/decode routine pointers. */
66 const struct real_format pdp11_f_format =
87 const struct real_format pdp11_d_format =
109 encode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf,
110 const REAL_VALUE_TYPE *r)
112 (*vax_f_format.encode) (fmt, buf, r);
113 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
117 decode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED,
118 REAL_VALUE_TYPE *r, const long *buf)
121 tbuf = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
122 (*vax_f_format.decode) (fmt, r, &tbuf);
126 encode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf,
127 const REAL_VALUE_TYPE *r)
129 (*vax_d_format.encode) (fmt, buf, r);
130 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
131 buf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16);
135 decode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED,
136 REAL_VALUE_TYPE *r, const long *buf)
139 tbuf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
140 tbuf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16);
141 (*vax_d_format.decode) (fmt, r, tbuf);
144 /* This is where the condition code register lives. */
145 /* rtx cc0_reg_rtx; - no longer needed? */
147 static bool pdp11_handle_option (size_t, const char *, int);
148 static rtx find_addr_reg (rtx);
149 static const char *singlemove_string (rtx *);
150 static bool pdp11_assemble_integer (rtx, unsigned int, int);
151 static void pdp11_output_function_prologue (FILE *, HOST_WIDE_INT);
152 static void pdp11_output_function_epilogue (FILE *, HOST_WIDE_INT);
153 static bool pdp11_rtx_costs (rtx, int, int, int *, bool);
154 static bool pdp11_return_in_memory (const_tree, const_tree);
156 /* Initialize the GCC target structure. */
157 #undef TARGET_ASM_BYTE_OP
158 #define TARGET_ASM_BYTE_OP NULL
159 #undef TARGET_ASM_ALIGNED_HI_OP
160 #define TARGET_ASM_ALIGNED_HI_OP NULL
161 #undef TARGET_ASM_ALIGNED_SI_OP
162 #define TARGET_ASM_ALIGNED_SI_OP NULL
163 #undef TARGET_ASM_INTEGER
164 #define TARGET_ASM_INTEGER pdp11_assemble_integer
166 #undef TARGET_ASM_FUNCTION_PROLOGUE
167 #define TARGET_ASM_FUNCTION_PROLOGUE pdp11_output_function_prologue
168 #undef TARGET_ASM_FUNCTION_EPILOGUE
169 #define TARGET_ASM_FUNCTION_EPILOGUE pdp11_output_function_epilogue
171 #undef TARGET_ASM_OPEN_PAREN
172 #define TARGET_ASM_OPEN_PAREN "["
173 #undef TARGET_ASM_CLOSE_PAREN
174 #define TARGET_ASM_CLOSE_PAREN "]"
176 #undef TARGET_DEFAULT_TARGET_FLAGS
177 #define TARGET_DEFAULT_TARGET_FLAGS \
178 (MASK_FPU | MASK_45 | MASK_ABSHI_BUILTIN | TARGET_UNIX_ASM_DEFAULT)
179 #undef TARGET_HANDLE_OPTION
180 #define TARGET_HANDLE_OPTION pdp11_handle_option
182 #undef TARGET_RTX_COSTS
183 #define TARGET_RTX_COSTS pdp11_rtx_costs
185 #undef TARGET_RETURN_IN_MEMORY
186 #define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory
188 struct gcc_target targetm = TARGET_INITIALIZER;
190 /* Implement TARGET_HANDLE_OPTION. */
193 pdp11_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
194 int value ATTRIBUTE_UNUSED)
199 target_flags &= ~(MASK_40 | MASK_45);
207 /* Nonzero if OP is a valid second operand for an arithmetic insn. */
210 arith_operand (rtx op, enum machine_mode mode)
212 return (register_operand (op, mode) || GET_CODE (op) == CONST_INT);
216 const_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
218 return (GET_CODE (op) == CONST_INT);
222 immediate15_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
224 return (GET_CODE (op) == CONST_INT && ((INTVAL (op) & 0x8000) == 0x0000));
228 expand_shift_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
230 return (GET_CODE (op) == CONST_INT
231 && abs (INTVAL(op)) > 1
232 && abs (INTVAL(op)) <= 4);
236 stream is a stdio stream to output the code to.
237 size is an int: how many units of temporary storage to allocate.
238 Refer to the array `regs_ever_live' to determine which registers
239 to save; `regs_ever_live[I]' is nonzero if register number I
240 is ever used in the function. This macro is responsible for
241 knowing which registers should not be saved even if used.
247 pdp11_output_function_prologue (FILE *stream, HOST_WIDE_INT size)
249 fprintf (stream, "\tjsr r5, csv\n");
252 fprintf (stream, "\t/*abuse empty parameter slot for locals!*/\n");
254 asm_fprintf (stream, "\tsub $%#wo, sp\n", size - 2);
262 pdp11_output_function_prologue (FILE *stream, HOST_WIDE_INT size)
264 HOST_WIDE_INT fsize = ((size) + 1) & ~1;
269 "\n\t; /* function prologue %s*/\n",
270 current_function_name ());
272 /* if we are outputting code for main,
273 the switch FPU to right mode if TARGET_FPU */
274 if (MAIN_NAME_P (DECL_NAME (current_function_decl)) && TARGET_FPU)
277 "\t;/* switch cpu to double float, single integer */\n");
278 fprintf(stream, "\tsetd\n");
279 fprintf(stream, "\tseti\n\n");
282 if (frame_pointer_needed)
284 fprintf(stream, "\tmov r5, -(sp)\n");
285 fprintf(stream, "\tmov sp, r5\n");
294 asm_fprintf (stream, "\tsub $%#wo, sp\n", fsize);
296 /* save CPU registers */
297 for (regno = 0; regno < 8; regno++)
298 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
299 if (! ((regno == FRAME_POINTER_REGNUM)
300 && frame_pointer_needed))
301 fprintf (stream, "\tmov %s, -(sp)\n", reg_names[regno]);
302 /* fpu regs saving */
304 /* via_ac specifies the ac to use for saving ac4, ac5 */
307 for (regno = 8; regno < FIRST_PSEUDO_REGISTER ; regno++)
310 if (LOAD_FPU_REG_P(regno)
311 && df_regs_ever_live_p (regno)
312 && ! call_used_regs[regno])
314 fprintf (stream, "\tstd %s, -(sp)\n", reg_names[regno]);
318 /* maybe make ac4, ac5 call used regs?? */
320 if (NO_LOAD_FPU_REG_P(regno)
321 && df_regs_ever_live_p (regno)
322 && ! call_used_regs[regno])
324 gcc_assert (via_ac != -1);
325 fprintf (stream, "\tldd %s, %s\n",
326 reg_names[regno], reg_names[via_ac]);
327 fprintf (stream, "\tstd %s, -(sp)\n", reg_names[via_ac]);
331 fprintf (stream, "\t;/* end of prologue */\n\n");
334 #endif /* !TWO_BSD */
337 The function epilogue should not depend on the current stack pointer!
338 It should use the frame pointer only. This is mandatory because
339 of alloca; we also take advantage of it to omit stack adjustments
342 /* maybe we can make leaf functions faster by switching to the
343 second register file - this way we don't have to save regs!
344 leaf functions are ~ 50% of all functions (dynamically!)
346 set/clear bit 11 (dec. 2048) of status word for switching register files -
347 but how can we do this? the pdp11/45 manual says bit may only
348 be set (p.24), but not cleared!
350 switching to kernel is probably more expensive, so we'll leave it
351 like this and not use the second set of registers...
353 maybe as option if you want to generate code for kernel mode? */
358 pdp11_output_function_epilogue (FILE *stream,
359 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
361 fprintf (stream, "\t/* SP ignored by cret? */\n");
362 fprintf (stream, "\tjmp cret\n");
368 pdp11_output_function_epilogue (FILE *stream, HOST_WIDE_INT size)
370 HOST_WIDE_INT fsize = ((size) + 1) & ~1;
375 fprintf (stream, "\n\t; /*function epilogue */\n");
377 if (frame_pointer_needed)
379 /* hope this is safe - m68k does it also .... */
380 df_set_regs_ever_live (FRAME_POINTER_REGNUM, false);
382 for (i =7, j = 0 ; i >= 0 ; i--)
383 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
386 /* remember # of pushed bytes for CPU regs */
389 /* change fp -> r5 due to the compile error on libgcc2.c */
390 for (i =7 ; i >= 0 ; i--)
391 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
392 fprintf(stream, "\tmov %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
393 (-fsize-2*j--)&0xffff, reg_names[i]);
396 via_ac = FIRST_PSEUDO_REGISTER -1;
398 for (i = FIRST_PSEUDO_REGISTER; i > 7; i--)
399 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
405 for (i = FIRST_PSEUDO_REGISTER; i > 7; i--)
407 if (LOAD_FPU_REG_P(i)
408 && df_regs_ever_live_p (i)
409 && ! call_used_regs[i])
411 fprintf(stream, "\tldd %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
412 (-fsize-k)&0xffff, reg_names[i]);
416 if (NO_LOAD_FPU_REG_P(i)
417 && df_regs_ever_live_p (i)
418 && ! call_used_regs[i])
420 gcc_assert (LOAD_FPU_REG_P(via_ac));
422 fprintf(stream, "\tldd %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
423 (-fsize-k)&0xffff, reg_names[via_ac]);
424 fprintf(stream, "\tstd %s, %s\n", reg_names[via_ac], reg_names[i]);
429 fprintf(stream, "\tmov r5, sp\n");
430 fprintf (stream, "\tmov (sp)+, r5\n");
434 via_ac = FIRST_PSEUDO_REGISTER -1;
437 for (i = FIRST_PSEUDO_REGISTER; i > 7; i--)
438 if (df_regs_ever_live_p (i) && call_used_regs[i])
441 for (i = FIRST_PSEUDO_REGISTER; i > 7; i--)
443 if (LOAD_FPU_REG_P(i)
444 && df_regs_ever_live_p (i)
445 && ! call_used_regs[i])
446 fprintf(stream, "\tldd (sp)+, %s\n", reg_names[i]);
448 if (NO_LOAD_FPU_REG_P(i)
449 && df_regs_ever_live_p (i)
450 && ! call_used_regs[i])
452 gcc_assert (LOAD_FPU_REG_P(via_ac));
454 fprintf(stream, "\tldd (sp)+, %s\n", reg_names[via_ac]);
455 fprintf(stream, "\tstd %s, %s\n", reg_names[via_ac], reg_names[i]);
459 for (i=7; i >= 0; i--)
460 if (df_regs_ever_live_p (i) && !call_used_regs[i])
461 fprintf(stream, "\tmov (sp)+, %s\n", reg_names[i]);
464 fprintf((stream), "\tadd $%#" HOST_WIDE_INT_PRINT "o, sp\n",
468 fprintf (stream, "\trts pc\n");
469 fprintf (stream, "\t;/* end of epilogue*/\n\n\n");
472 #endif /* !TWO_BSD */
474 /* Return the best assembler insn template
475 for moving operands[1] into operands[0] as a fullword. */
477 singlemove_string (rtx *operands)
479 if (operands[1] != const0_rtx)
486 /* Output assembler code to perform a doubleword move insn
487 with operands OPERANDS. */
490 output_move_double (rtx *operands)
492 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
494 rtx addreg0 = 0, addreg1 = 0;
496 /* First classify both operands. */
498 if (REG_P (operands[0]))
500 else if (offsettable_memref_p (operands[0]))
502 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
504 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
506 else if (GET_CODE (operands[0]) == MEM)
511 if (REG_P (operands[1]))
513 else if (CONSTANT_P (operands[1])
515 || GET_CODE (operands[1]) == CONST_DOUBLE
519 else if (offsettable_memref_p (operands[1]))
521 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
523 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
525 else if (GET_CODE (operands[1]) == MEM)
530 /* Check for the cases that the operand constraints are not
531 supposed to allow to happen. Abort if we get one,
532 because generating code for these cases is painful. */
534 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
536 /* If one operand is decrementing and one is incrementing
537 decrement the former register explicitly
538 and change that operand into ordinary indexing. */
540 if (optype0 == PUSHOP && optype1 == POPOP)
542 operands[0] = XEXP (XEXP (operands[0], 0), 0);
543 output_asm_insn ("sub $4,%0", operands);
544 operands[0] = gen_rtx_MEM (SImode, operands[0]);
547 if (optype0 == POPOP && optype1 == PUSHOP)
549 operands[1] = XEXP (XEXP (operands[1], 0), 0);
550 output_asm_insn ("sub $4,%1", operands);
551 operands[1] = gen_rtx_MEM (SImode, operands[1]);
555 /* If an operand is an unoffsettable memory ref, find a register
556 we can increment temporarily to make it refer to the second word. */
558 if (optype0 == MEMOP)
559 addreg0 = find_addr_reg (XEXP (operands[0], 0));
561 if (optype1 == MEMOP)
562 addreg1 = find_addr_reg (XEXP (operands[1], 0));
564 /* Ok, we can do one word at a time.
565 Normally we do the low-numbered word first,
566 but if either operand is autodecrementing then we
567 do the high-numbered word first.
569 In either case, set up in LATEHALF the operands to use
570 for the high-numbered word and in some cases alter the
571 operands in OPERANDS to be suitable for the low-numbered word. */
573 if (optype0 == REGOP)
574 latehalf[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
575 else if (optype0 == OFFSOP)
576 latehalf[0] = adjust_address (operands[0], HImode, 2);
578 latehalf[0] = operands[0];
580 if (optype1 == REGOP)
581 latehalf[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1);
582 else if (optype1 == OFFSOP)
583 latehalf[1] = adjust_address (operands[1], HImode, 2);
584 else if (optype1 == CNSTOP)
586 if (CONSTANT_P (operands[1]))
588 /* now the mess begins, high word is in lower word???
590 that's what ashc makes me think, but I don't remember :-( */
591 latehalf[1] = GEN_INT (INTVAL(operands[1]) >> 16);
592 operands[1] = GEN_INT (INTVAL(operands[1]) & 0xff);
595 /* immediate 32-bit values not allowed */
596 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE);
599 latehalf[1] = operands[1];
601 /* If insn is effectively movd N(sp),-(sp) then we will do the
602 high word first. We should use the adjusted operand 1 (which is N+4(sp))
603 for the low word as well, to compensate for the first decrement of sp. */
604 if (optype0 == PUSHOP
605 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
606 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
607 operands[1] = latehalf[1];
609 /* If one or both operands autodecrementing,
610 do the two words, high-numbered first. */
612 /* Likewise, the first move would clobber the source of the second one,
613 do them in the other order. This happens only for registers;
614 such overlap can't happen in memory unless the user explicitly
615 sets it up, and that is an undefined circumstance. */
617 if (optype0 == PUSHOP || optype1 == PUSHOP
618 || (optype0 == REGOP && optype1 == REGOP
619 && REGNO (operands[0]) == REGNO (latehalf[1])))
621 /* Make any unoffsettable addresses point at high-numbered word. */
623 output_asm_insn ("add $2,%0", &addreg0);
625 output_asm_insn ("add $2,%0", &addreg1);
628 output_asm_insn (singlemove_string (latehalf), latehalf);
630 /* Undo the adds we just did. */
632 output_asm_insn ("sub $2,%0", &addreg0);
634 output_asm_insn ("sub $2,%0", &addreg1);
636 /* Do low-numbered word. */
637 return singlemove_string (operands);
640 /* Normal case: do the two words, low-numbered first. */
642 output_asm_insn (singlemove_string (operands), operands);
644 /* Make any unoffsettable addresses point at high-numbered word. */
646 output_asm_insn ("add $2,%0", &addreg0);
648 output_asm_insn ("add $2,%0", &addreg1);
651 output_asm_insn (singlemove_string (latehalf), latehalf);
653 /* Undo the adds we just did. */
655 output_asm_insn ("sub $2,%0", &addreg0);
657 output_asm_insn ("sub $2,%0", &addreg1);
661 /* Output assembler code to perform a quadword move insn
662 with operands OPERANDS. */
665 output_move_quad (rtx *operands)
667 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
669 rtx addreg0 = 0, addreg1 = 0;
671 output_asm_insn(";/* movdi/df: %1 -> %0 */", operands);
673 if (REG_P (operands[0]))
675 else if (offsettable_memref_p (operands[0]))
677 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
679 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
681 else if (GET_CODE (operands[0]) == MEM)
686 if (REG_P (operands[1]))
688 else if (CONSTANT_P (operands[1])
689 || GET_CODE (operands[1]) == CONST_DOUBLE)
691 else if (offsettable_memref_p (operands[1]))
693 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
695 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
697 else if (GET_CODE (operands[1]) == MEM)
702 /* Check for the cases that the operand constraints are not
703 supposed to allow to happen. Abort if we get one,
704 because generating code for these cases is painful. */
706 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
708 /* check if we move a CPU reg to an FPU reg, or vice versa! */
709 if (optype0 == REGOP && optype1 == REGOP)
710 /* bogus - 64 bit cannot reside in CPU! */
711 gcc_assert (!CPU_REG_P(REGNO(operands[0]))
712 && !CPU_REG_P (REGNO(operands[1])));
714 if (optype0 == REGOP || optype1 == REGOP)
716 /* check for use of clrd????
717 if you ever allow ac4 and ac5 (now we require secondary load)
718 you must check whether
719 you want to load into them or store from them -
720 then dump ac0 into $help$ movce ac4/5 to ac0, do the
721 store from ac0, and restore ac0 - if you can find
722 an unused ac[0-3], use that and you save a store and a load!*/
724 if (FPU_REG_P(REGNO(operands[0])))
726 if (GET_CODE(operands[1]) == CONST_DOUBLE)
729 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
731 if (REAL_VALUES_EQUAL (r, dconst0))
732 return "{clrd|clrf} %0";
735 return "{ldd|movf} %1, %0";
738 if (FPU_REG_P(REGNO(operands[1])))
739 return "{std|movf} %1, %0";
742 /* If one operand is decrementing and one is incrementing
743 decrement the former register explicitly
744 and change that operand into ordinary indexing. */
746 if (optype0 == PUSHOP && optype1 == POPOP)
748 operands[0] = XEXP (XEXP (operands[0], 0), 0);
749 output_asm_insn ("sub $8,%0", operands);
750 operands[0] = gen_rtx_MEM (DImode, operands[0]);
753 if (optype0 == POPOP && optype1 == PUSHOP)
755 operands[1] = XEXP (XEXP (operands[1], 0), 0);
756 output_asm_insn ("sub $8,%1", operands);
757 operands[1] = gen_rtx_MEM (SImode, operands[1]);
761 /* If an operand is an unoffsettable memory ref, find a register
762 we can increment temporarily to make it refer to the second word. */
764 if (optype0 == MEMOP)
765 addreg0 = find_addr_reg (XEXP (operands[0], 0));
767 if (optype1 == MEMOP)
768 addreg1 = find_addr_reg (XEXP (operands[1], 0));
770 /* Ok, we can do one word at a time.
771 Normally we do the low-numbered word first,
772 but if either operand is autodecrementing then we
773 do the high-numbered word first.
775 In either case, set up in LATEHALF the operands to use
776 for the high-numbered word and in some cases alter the
777 operands in OPERANDS to be suitable for the low-numbered word. */
779 if (optype0 == REGOP)
780 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
781 else if (optype0 == OFFSOP)
782 latehalf[0] = adjust_address (operands[0], SImode, 4);
784 latehalf[0] = operands[0];
786 if (optype1 == REGOP)
787 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
788 else if (optype1 == OFFSOP)
789 latehalf[1] = adjust_address (operands[1], SImode, 4);
790 else if (optype1 == CNSTOP)
792 if (GET_CODE (operands[1]) == CONST_DOUBLE)
796 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
797 REAL_VALUE_TO_TARGET_DOUBLE (r, dval);
798 latehalf[1] = GEN_INT (dval[1]);
799 operands[1] = GEN_INT (dval[0]);
801 else if (GET_CODE(operands[1]) == CONST_INT)
803 latehalf[1] = const0_rtx;
809 latehalf[1] = operands[1];
811 /* If insn is effectively movd N(sp),-(sp) then we will do the
812 high word first. We should use the adjusted operand 1 (which is N+4(sp))
813 for the low word as well, to compensate for the first decrement of sp. */
814 if (optype0 == PUSHOP
815 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
816 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
817 operands[1] = latehalf[1];
819 /* If one or both operands autodecrementing,
820 do the two words, high-numbered first. */
822 /* Likewise, the first move would clobber the source of the second one,
823 do them in the other order. This happens only for registers;
824 such overlap can't happen in memory unless the user explicitly
825 sets it up, and that is an undefined circumstance. */
827 if (optype0 == PUSHOP || optype1 == PUSHOP
828 || (optype0 == REGOP && optype1 == REGOP
829 && REGNO (operands[0]) == REGNO (latehalf[1])))
831 /* Make any unoffsettable addresses point at high-numbered word. */
833 output_asm_insn ("add $4,%0", &addreg0);
835 output_asm_insn ("add $4,%0", &addreg1);
838 output_asm_insn(output_move_double(latehalf), latehalf);
840 /* Undo the adds we just did. */
842 output_asm_insn ("sub $4,%0", &addreg0);
844 output_asm_insn ("sub $4,%0", &addreg1);
846 /* Do low-numbered word. */
847 return output_move_double (operands);
850 /* Normal case: do the two words, low-numbered first. */
852 output_asm_insn (output_move_double (operands), operands);
854 /* Make any unoffsettable addresses point at high-numbered word. */
856 output_asm_insn ("add $4,%0", &addreg0);
858 output_asm_insn ("add $4,%0", &addreg1);
861 output_asm_insn (output_move_double (latehalf), latehalf);
863 /* Undo the adds we just did. */
865 output_asm_insn ("sub $4,%0", &addreg0);
867 output_asm_insn ("sub $4,%0", &addreg1);
873 /* Return a REG that occurs in ADDR with coefficient 1.
874 ADDR can be effectively incremented by incrementing REG. */
877 find_addr_reg (rtx addr)
879 while (GET_CODE (addr) == PLUS)
881 if (GET_CODE (XEXP (addr, 0)) == REG)
882 addr = XEXP (addr, 0);
883 if (GET_CODE (XEXP (addr, 1)) == REG)
884 addr = XEXP (addr, 1);
885 if (CONSTANT_P (XEXP (addr, 0)))
886 addr = XEXP (addr, 1);
887 if (CONSTANT_P (XEXP (addr, 1)))
888 addr = XEXP (addr, 0);
890 if (GET_CODE (addr) == REG)
895 /* Output an ascii string. */
897 output_ascii (FILE *file, const char *p, int size)
901 /* This used to output .byte "string", which doesn't work with the UNIX
902 assembler and I think not with DEC ones either. */
903 fprintf (file, "\t.byte ");
905 for (i = 0; i < size; i++)
907 register int c = p[i];
910 fprintf (file, "%#o", c);
918 /* --- stole from out-vax, needs changes */
921 print_operand_address (FILE *file, register rtx addr)
923 register rtx reg1, reg2, breg, ireg;
928 switch (GET_CODE (addr))
935 addr = XEXP (addr, 0);
939 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
944 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
949 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
956 if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
957 || GET_CODE (XEXP (addr, 0)) == MEM)
959 offset = XEXP (addr, 0);
960 addr = XEXP (addr, 1);
962 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
963 || GET_CODE (XEXP (addr, 1)) == MEM)
965 offset = XEXP (addr, 1);
966 addr = XEXP (addr, 0);
968 if (GET_CODE (addr) != PLUS)
970 else if (GET_CODE (XEXP (addr, 0)) == MULT)
972 reg1 = XEXP (addr, 0);
973 addr = XEXP (addr, 1);
975 else if (GET_CODE (XEXP (addr, 1)) == MULT)
977 reg1 = XEXP (addr, 1);
978 addr = XEXP (addr, 0);
980 else if (GET_CODE (XEXP (addr, 0)) == REG)
982 reg1 = XEXP (addr, 0);
983 addr = XEXP (addr, 1);
985 else if (GET_CODE (XEXP (addr, 1)) == REG)
987 reg1 = XEXP (addr, 1);
988 addr = XEXP (addr, 0);
990 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
1000 gcc_assert (addr == 0);
1003 if (reg1 != 0 && GET_CODE (reg1) == MULT)
1008 else if (reg2 != 0 && GET_CODE (reg2) == MULT)
1013 else if (reg2 != 0 || GET_CODE (addr) == MEM)
1024 output_address (addr);
1027 gcc_assert (GET_CODE (breg) == REG);
1028 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
1032 if (GET_CODE (ireg) == MULT)
1033 ireg = XEXP (ireg, 0);
1034 gcc_assert (GET_CODE (ireg) == REG);
1035 gcc_unreachable(); /* ??? */
1036 fprintf (file, "[%s]", reg_names[REGNO (ireg)]);
1041 output_addr_const_pdp11 (file, addr);
1045 /* Target hook to assemble integer objects. We need to use the
1046 pdp-specific version of output_addr_const. */
1049 pdp11_assemble_integer (rtx x, unsigned int size, int aligned_p)
1055 fprintf (asm_out_file, "\t.byte\t");
1056 output_addr_const_pdp11 (asm_out_file, x);
1057 fprintf (asm_out_file, " /* char */\n");
1061 fprintf (asm_out_file, TARGET_UNIX_ASM ? "\t" : "\t.word\t");
1062 output_addr_const_pdp11 (asm_out_file, x);
1063 fprintf (asm_out_file, " /* short */\n");
1066 return default_assemble_integer (x, size, aligned_p);
1070 /* register move costs, indexed by regs */
1072 static const int move_costs[N_REG_CLASSES][N_REG_CLASSES] =
1074 /* NO MUL GEN LFPU NLFPU FPU ALL */
1076 /* NO */ { 0, 0, 0, 0, 0, 0, 0},
1077 /* MUL */ { 0, 2, 2, 10, 22, 22, 22},
1078 /* GEN */ { 0, 2, 2, 10, 22, 22, 22},
1079 /* LFPU */ { 0, 10, 10, 2, 2, 2, 10},
1080 /* NLFPU */ { 0, 22, 22, 2, 2, 2, 22},
1081 /* FPU */ { 0, 22, 22, 2, 2, 2, 22},
1082 /* ALL */ { 0, 22, 22, 10, 22, 22, 22}
1086 /* -- note that some moves are tremendously expensive,
1087 because they require lots of tricks! do we have to
1088 charge the costs incurred by secondary reload class
1089 -- as we do here with 22 -- or not ? */
1092 register_move_cost(enum reg_class c1, enum reg_class c2)
1094 return move_costs[(int)c1][(int)c2];
1098 pdp11_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total,
1099 bool speed ATTRIBUTE_UNUSED)
1104 if (INTVAL (x) == 0 || INTVAL (x) == -1 || INTVAL (x) == 1)
1114 /* Twice as expensive as REG. */
1119 /* Twice (or 4 times) as expensive as 16 bit. */
1124 /* ??? There is something wrong in MULT because MULT is not
1125 as cheap as total = 2 even if we can shift! */
1126 /* If optimizing for size make mult etc cheap, but not 1, so when
1127 in doubt the faster insn is chosen. */
1129 *total = COSTS_N_INSNS (2);
1131 *total = COSTS_N_INSNS (11);
1136 *total = COSTS_N_INSNS (2);
1138 *total = COSTS_N_INSNS (25);
1143 *total = COSTS_N_INSNS (2);
1145 *total = COSTS_N_INSNS (26);
1149 /* Equivalent to length, so same for optimize_size. */
1150 *total = COSTS_N_INSNS (3);
1154 /* Only used for qi->hi. */
1155 *total = COSTS_N_INSNS (1);
1159 if (GET_MODE (x) == HImode)
1160 *total = COSTS_N_INSNS (1);
1161 else if (GET_MODE (x) == SImode)
1162 *total = COSTS_N_INSNS (6);
1164 *total = COSTS_N_INSNS (2);
1171 *total = COSTS_N_INSNS (1);
1172 else if (GET_MODE (x) == QImode)
1174 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1175 *total = COSTS_N_INSNS (8); /* worst case */
1177 *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1)));
1179 else if (GET_MODE (x) == HImode)
1181 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1183 if (abs (INTVAL (XEXP (x, 1))) == 1)
1184 *total = COSTS_N_INSNS (1);
1186 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1)));
1189 *total = COSTS_N_INSNS (10); /* worst case */
1191 else if (GET_MODE (x) == SImode)
1193 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1194 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1)));
1195 else /* worst case */
1196 *total = COSTS_N_INSNS (18);
1206 output_jump (const char *pos, const char *neg, int length)
1210 static char buf[1000];
1213 /* currently we don't need this, because the tstdf and cmpdf
1214 copy the condition code immediately, and other float operations are not
1215 yet recognized as changing the FCC - if so, then the length-cost of all
1216 jump insns increases by one, because we have to potentially copy the
1218 if (cc_status.flags & CC_IN_FPU)
1219 output_asm_insn("cfcc", NULL);
1227 strcat(buf, " %l0");
1233 sprintf(buf, "%s JMP_%d\n\tjmp %%l0\nJMP_%d:", neg, x, x);
1247 notice_update_cc_on_set(rtx exp, rtx insn ATTRIBUTE_UNUSED)
1249 if (GET_CODE (SET_DEST (exp)) == CC0)
1251 cc_status.flags = 0;
1252 cc_status.value1 = SET_DEST (exp);
1253 cc_status.value2 = SET_SRC (exp);
1256 if (GET_MODE(SET_SRC(exp)) == DFmode)
1257 cc_status.flags |= CC_IN_FPU;
1260 else if ((GET_CODE (SET_DEST (exp)) == REG
1261 || GET_CODE (SET_DEST (exp)) == MEM)
1262 && GET_CODE (SET_SRC (exp)) != PC
1263 && (GET_MODE (SET_DEST(exp)) == HImode
1264 || GET_MODE (SET_DEST(exp)) == QImode)
1265 && (GET_CODE (SET_SRC(exp)) == PLUS
1266 || GET_CODE (SET_SRC(exp)) == MINUS
1267 || GET_CODE (SET_SRC(exp)) == AND
1268 || GET_CODE (SET_SRC(exp)) == IOR
1269 || GET_CODE (SET_SRC(exp)) == XOR
1270 || GET_CODE (SET_SRC(exp)) == NOT
1271 || GET_CODE (SET_SRC(exp)) == NEG
1272 || GET_CODE (SET_SRC(exp)) == REG
1273 || GET_CODE (SET_SRC(exp)) == MEM))
1275 cc_status.flags = 0;
1276 cc_status.value1 = SET_SRC (exp);
1277 cc_status.value2 = SET_DEST (exp);
1279 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
1281 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
1282 cc_status.value2 = 0;
1283 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
1285 && GET_CODE (cc_status.value2) == MEM)
1286 cc_status.value2 = 0;
1288 else if (GET_CODE (SET_SRC (exp)) == CALL)
1292 else if (GET_CODE (SET_DEST (exp)) == REG)
1295 if ((cc_status.value1
1296 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)))
1297 cc_status.value1 = 0;
1298 if ((cc_status.value2
1299 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)))
1300 cc_status.value2 = 0;
1302 else if (SET_DEST(exp) == pc_rtx)
1306 else /* if (GET_CODE (SET_DEST (exp)) == MEM) */
1308 /* the last else is a bit paranoiac, but since nearly all instructions
1309 play with condition codes, it's reasonable! */
1311 CC_STATUS_INIT; /* paranoia*/
1317 simple_memory_operand(rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1321 /* Eliminate non-memory operations */
1322 if (GET_CODE (op) != MEM)
1326 /* dword operations really put out 2 instructions, so eliminate them. */
1327 if (GET_MODE_SIZE (GET_MODE (op)) > (HAVE_64BIT_P () ? 8 : 4))
1331 /* Decode the address now. */
1335 addr = XEXP (op, 0);
1337 switch (GET_CODE (addr))
1340 /* (R0) - no extra cost */
1345 /* -(R0), (R0)+ - cheap! */
1349 /* cheap - is encoded in addressing mode info!
1351 -- except for @(R0), which has to be @0(R0) !!! */
1353 if (GET_CODE (XEXP (addr, 0)) == REG)
1363 /* @#address - extra cost */
1367 /* X(R0) - extra cost */
1379 * output a block move:
1381 * operands[0] ... to
1382 * operands[1] ... from
1383 * operands[2] ... length
1384 * operands[3] ... alignment
1385 * operands[4] ... scratch register
1390 output_block_move(rtx *operands)
1392 static int count = 0;
1395 if (GET_CODE(operands[2]) == CONST_INT
1398 if (INTVAL(operands[2]) < 16
1399 && INTVAL(operands[3]) == 1)
1403 for (i = 1; i <= INTVAL(operands[2]); i++)
1404 output_asm_insn("movb (%1)+, (%0)+", operands);
1408 else if (INTVAL(operands[2]) < 32)
1412 for (i = 1; i <= INTVAL(operands[2])/2; i++)
1413 output_asm_insn("mov (%1)+, (%0)+", operands);
1415 /* may I assume that moved quantity is
1416 multiple of alignment ???
1425 /* can do other clever things, maybe... */
1428 if (CONSTANT_P(operands[2]) )
1430 /* just move count to scratch */
1431 output_asm_insn("mov %2, %4", operands);
1435 /* just clobber the register */
1436 operands[4] = operands[2];
1440 /* switch over alignment */
1441 switch (INTVAL(operands[3]))
1457 sprintf(buf, "\nmovestrhi%d:", count);
1458 output_asm_insn(buf, NULL);
1460 output_asm_insn("movb (%1)+, (%0)+", operands);
1464 sprintf(buf, "sob %%4, movestrhi%d", count);
1465 output_asm_insn(buf, operands);
1469 output_asm_insn("dec %4", operands);
1471 sprintf(buf, "bgt movestrhi%d", count);
1472 output_asm_insn(buf, NULL);
1494 generate_compact_code:
1496 output_asm_insn("asr %4", operands);
1498 sprintf(buf, "\nmovestrhi%d:", count);
1499 output_asm_insn(buf, NULL);
1501 output_asm_insn("mov (%1)+, (%0)+", operands);
1505 sprintf(buf, "sob %%4, movestrhi%d", count);
1506 output_asm_insn(buf, operands);
1510 output_asm_insn("dec %4", operands);
1512 sprintf(buf, "bgt movestrhi%d", count);
1513 output_asm_insn(buf, NULL);
1539 goto generate_compact_code;
1541 output_asm_insn("asr %4", operands);
1542 output_asm_insn("asr %4", operands);
1544 sprintf(buf, "\nmovestrhi%d:", count);
1545 output_asm_insn(buf, NULL);
1547 output_asm_insn("mov (%1)+, (%0)+", operands);
1548 output_asm_insn("mov (%1)+, (%0)+", operands);
1552 sprintf(buf, "sob %%4, movestrhi%d", count);
1553 output_asm_insn(buf, operands);
1557 output_asm_insn("dec %4", operands);
1559 sprintf(buf, "bgt movestrhi%d", count);
1560 output_asm_insn(buf, NULL);
1590 goto generate_compact_code;
1592 output_asm_insn("asr %4", operands);
1593 output_asm_insn("asr %4", operands);
1594 output_asm_insn("asr %4", operands);
1596 sprintf(buf, "\nmovestrhi%d:", count);
1597 output_asm_insn(buf, NULL);
1599 output_asm_insn("mov (%1)+, (%0)+", operands);
1600 output_asm_insn("mov (%1)+, (%0)+", operands);
1601 output_asm_insn("mov (%1)+, (%0)+", operands);
1602 output_asm_insn("mov (%1)+, (%0)+", operands);
1606 sprintf(buf, "sob %%4, movestrhi%d", count);
1607 output_asm_insn(buf, operands);
1611 output_asm_insn("dec %4", operands);
1613 sprintf(buf, "bgt movestrhi%d", count);
1614 output_asm_insn(buf, NULL);
1628 legitimate_address_p (enum machine_mode mode, rtx address)
1630 /* #define REG_OK_STRICT */
1631 GO_IF_LEGITIMATE_ADDRESS(mode, address, win);
1638 /* #undef REG_OK_STRICT */
1641 /* This function checks whether a real value can be encoded as
1642 a literal, i.e., addressing mode 27. In that mode, real values
1643 are one word values, so the remaining 48 bits have to be zero. */
1645 legitimate_const_double_p (rtx address)
1649 REAL_VALUE_FROM_CONST_DOUBLE (r, address);
1650 REAL_VALUE_TO_TARGET_DOUBLE (r, sval);
1651 if ((sval[0] & 0xffff) == 0 && sval[1] == 0)
1656 /* A copy of output_addr_const modified for pdp11 expression syntax.
1657 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't
1658 use, and for debugging output, which we don't support with this port either.
1659 So this copy should get called whenever needed.
1662 output_addr_const_pdp11 (FILE *file, rtx x)
1667 switch (GET_CODE (x))
1670 gcc_assert (flag_pic);
1675 assemble_name (file, XSTR (x, 0));
1679 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0)));
1680 assemble_name (file, buf);
1684 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
1685 assemble_name (file, buf);
1689 /* Should we check for constants which are too big? Maybe cutting
1690 them off to 16 bits is OK? */
1691 fprintf (file, "%#ho", (unsigned short) INTVAL (x));
1695 /* This used to output parentheses around the expression,
1696 but that does not work on the 386 (either ATT or BSD assembler). */
1697 output_addr_const_pdp11 (file, XEXP (x, 0));
1701 if (GET_MODE (x) == VOIDmode)
1703 /* We can use %o if the number is one word and positive. */
1704 gcc_assert (!CONST_DOUBLE_HIGH (x));
1705 fprintf (file, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x));
1708 /* We can't handle floating point constants;
1709 PRINT_OPERAND must handle them. */
1710 output_operand_lossage ("floating constant misused");
1714 /* Some assemblers need integer constants to appear last (e.g. masm). */
1715 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
1717 output_addr_const_pdp11 (file, XEXP (x, 1));
1718 if (INTVAL (XEXP (x, 0)) >= 0)
1719 fprintf (file, "+");
1720 output_addr_const_pdp11 (file, XEXP (x, 0));
1724 output_addr_const_pdp11 (file, XEXP (x, 0));
1725 if (INTVAL (XEXP (x, 1)) >= 0)
1726 fprintf (file, "+");
1727 output_addr_const_pdp11 (file, XEXP (x, 1));
1732 /* Avoid outputting things like x-x or x+5-x,
1733 since some assemblers can't handle that. */
1734 x = simplify_subtraction (x);
1735 if (GET_CODE (x) != MINUS)
1738 output_addr_const_pdp11 (file, XEXP (x, 0));
1739 fprintf (file, "-");
1740 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1741 && INTVAL (XEXP (x, 1)) < 0)
1743 fprintf (file, targetm.asm_out.open_paren);
1744 output_addr_const_pdp11 (file, XEXP (x, 1));
1745 fprintf (file, targetm.asm_out.close_paren);
1748 output_addr_const_pdp11 (file, XEXP (x, 1));
1753 output_addr_const_pdp11 (file, XEXP (x, 0));
1757 output_operand_lossage ("invalid expression as operand");
1761 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1764 pdp11_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1766 /* Should probably return DImode and DFmode in memory, lest
1767 we fill up all regs!
1769 have to, else we crash - exception: maybe return result in
1770 ac0 if DFmode and FPU present - compatibility problem with
1771 libraries for non-floating point.... */
1772 return (TYPE_MODE (type) == DImode
1773 || (TYPE_MODE (type) == DFmode && ! TARGET_AC0));