1 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
5 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
6 Software Science at the University of Utah.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
24 enum cmp_type /* comparison type */
26 CMP_SI, /* compare integers */
27 CMP_SF, /* compare single precision floats */
28 CMP_DF, /* compare double precision floats */
29 CMP_MAX /* max comparison type */
32 /* For long call handling. */
33 extern unsigned long total_code_bytes;
35 /* Which processor to schedule for. */
47 /* For -mschedule= option. */
48 extern enum processor_type pa_cpu;
50 /* For -munix= option. */
51 extern int flag_pa_unix;
53 #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
55 /* Print subsidiary information on the compiler version in use. */
57 #define TARGET_VERSION fputs (" (hppa)", stderr);
59 #define TARGET_PA_10 (!TARGET_PA_11 && !TARGET_PA_20)
61 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
63 #define TARGET_64BIT 0
66 /* Generate code for ELF32 ABI. */
68 #define TARGET_ELF32 0
71 /* Generate code for SOM 32bit ABI. */
76 /* HP-UX UNIX features. */
81 /* HP-UX 10.10 UNIX 95 features. */
82 #ifndef TARGET_HPUX_10_10
83 #define TARGET_HPUX_10_10 0
86 /* HP-UX 11.* features (11.00, 11.11, 11.23, etc.) */
87 #ifndef TARGET_HPUX_11
88 #define TARGET_HPUX_11 0
91 /* HP-UX 11i multibyte and UNIX 98 extensions. */
92 #ifndef TARGET_HPUX_11_11
93 #define TARGET_HPUX_11_11 0
96 /* The following three defines are potential target switches. The current
97 defines are optimal given the current capabilities of GAS and GNU ld. */
99 /* Define to a C expression evaluating to true to use long absolute calls.
100 Currently, only the HP assembler and SOM linker support long absolute
101 calls. They are used only in non-pic code. */
102 #define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS)
104 /* Define to a C expression evaluating to true to use long pic symbol
105 difference calls. This is a call variant similar to the long pic
106 pc-relative call. Long pic symbol difference calls are only used with
107 the HP SOM linker. Currently, only the HP assembler supports these
108 calls. GAS doesn't allow an arbitrary difference of two symbols. */
109 #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS)
111 /* Define to a C expression evaluating to true to use long pic
112 pc-relative calls. Long pic pc-relative calls are only used with
113 GAS. Currently, they are usable for calls within a module but
114 not for external calls. */
115 #define TARGET_LONG_PIC_PCREL_CALL 0
117 /* Define to a C expression evaluating to true to use SOM secondary
118 definition symbols for weak support. Linker support for secondary
119 definition symbols is buggy prior to HP-UX 11.X. */
120 #define TARGET_SOM_SDEF 0
122 /* Define to a C expression evaluating to true to save the entry value
123 of SP in the current frame marker. This is normally unnecessary.
124 However, the HP-UX unwind library looks at the SAVE_SP callinfo flag.
125 HP compilers don't use this flag but it is supported by the assembler.
126 We set this flag to indicate that register %r3 has been saved at the
127 start of the frame. Thus, when the HP unwind library is used, we
128 need to generate additional code to save SP into the frame marker. */
129 #define TARGET_HPUX_UNWIND_LIBRARY 0
131 #ifndef TARGET_DEFAULT
132 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
135 #ifndef TARGET_CPU_DEFAULT
136 #define TARGET_CPU_DEFAULT 0
139 #ifndef TARGET_SCHED_DEFAULT
140 #define TARGET_SCHED_DEFAULT PROCESSOR_8000
143 /* Support for a compile-time default CPU, et cetera. The rules are:
144 --with-schedule is ignored if -mschedule is specified.
145 --with-arch is ignored if -march is specified. */
146 #define OPTION_DEFAULT_SPECS \
147 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
148 {"schedule", "%{!mschedule=*:-mschedule=%(VALUE)}" }
150 /* Specify the dialect of assembler to use. New mnemonics is dialect one
151 and the old mnemonics are dialect zero. */
152 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
154 #define OVERRIDE_OPTIONS override_options ()
156 /* Override some settings from dbxelf.h. */
158 /* We do not have to be compatible with dbx, so we enable gdb extensions
160 #define DEFAULT_GDB_EXTENSIONS 1
162 /* This used to be zero (no max length), but big enums and such can
163 cause huge strings which killed gas.
165 We also have to avoid lossage in dbxout.c -- it does not compute the
166 string size accurately, so we are real conservative here. */
167 #undef DBX_CONTIN_LENGTH
168 #define DBX_CONTIN_LENGTH 3000
170 /* GDB always assumes the current function's frame begins at the value
171 of the stack pointer upon entry to the current function. Accessing
172 local variables and parameters passed on the stack is done using the
173 base of the frame + an offset provided by GCC.
175 For functions which have frame pointers this method works fine;
176 the (frame pointer) == (stack pointer at function entry) and GCC provides
177 an offset relative to the frame pointer.
179 This loses for functions without a frame pointer; GCC provides an offset
180 which is relative to the stack pointer after adjusting for the function's
181 frame size. GDB would prefer the offset to be relative to the value of
182 the stack pointer at the function's entry. Yuk! */
183 #define DEBUGGER_AUTO_OFFSET(X) \
184 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
185 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
187 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
188 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
189 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
191 #define TARGET_CPU_CPP_BUILTINS() \
193 builtin_assert("cpu=hppa"); \
194 builtin_assert("machine=hppa"); \
195 builtin_define("__hppa"); \
196 builtin_define("__hppa__"); \
198 builtin_define("_PA_RISC2_0"); \
199 else if (TARGET_PA_11) \
200 builtin_define("_PA_RISC1_1"); \
202 builtin_define("_PA_RISC1_0"); \
205 /* An old set of OS defines for various BSD-like systems. */
206 #define TARGET_OS_CPP_BUILTINS() \
209 builtin_define_std ("REVARGV"); \
210 builtin_define_std ("hp800"); \
211 builtin_define_std ("hp9000"); \
212 builtin_define_std ("hp9k8"); \
213 if (!c_dialect_cxx () && !flag_iso) \
214 builtin_define ("hppa"); \
215 builtin_define_std ("spectrum"); \
216 builtin_define_std ("unix"); \
217 builtin_assert ("system=bsd"); \
218 builtin_assert ("system=unix"); \
222 #define CC1_SPEC "%{pg:} %{p:}"
224 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
226 /* We don't want -lg. */
228 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
231 /* This macro defines command-line switches that modify the default
234 The definition is be an initializer for an array of structures. Each
235 array element has have three elements: the switch name, one of the
236 enumeration codes ADD or DELETE to indicate whether the string should be
237 inserted or deleted, and the string to be inserted or deleted. */
238 #define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}}
240 /* Make gcc agree with <machine/ansi.h> */
242 #define SIZE_TYPE "unsigned int"
243 #define PTRDIFF_TYPE "int"
244 #define WCHAR_TYPE "unsigned int"
245 #define WCHAR_TYPE_SIZE 32
247 /* Show we can debug even without a frame pointer. */
248 #define CAN_DEBUG_WITHOUT_FP
250 /* target machine storage layout */
251 typedef struct machine_function GTY(())
253 /* Flag indicating that a .NSUBSPA directive has been output for
258 /* Define this macro if it is advisable to hold scalars in registers
259 in a wider mode than that declared by the program. In such cases,
260 the value is constrained to be within the bounds of the declared
261 type, but kept valid in the wider mode. The signedness of the
262 extension may differ from that of the type. */
264 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
265 if (GET_MODE_CLASS (MODE) == MODE_INT \
266 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
269 /* Define this if most significant bit is lowest numbered
270 in instructions that operate on numbered bit-fields. */
271 #define BITS_BIG_ENDIAN 1
273 /* Define this if most significant byte of a word is the lowest numbered. */
274 /* That is true on the HP-PA. */
275 #define BYTES_BIG_ENDIAN 1
277 /* Define this if most significant word of a multiword number is lowest
279 #define WORDS_BIG_ENDIAN 1
281 #define MAX_BITS_PER_WORD 64
283 /* Width of a word, in units (bytes). */
284 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
286 /* Minimum number of units in a word. If this is undefined, the default
287 is UNITS_PER_WORD. Otherwise, it is the constant value that is the
288 smallest value that UNITS_PER_WORD can have at run-time.
290 FIXME: This needs to be 4 when TARGET_64BIT is true to suppress the
291 building of various TImode routines in libgcc. The HP runtime
292 specification doesn't provide the alignment requirements and calling
293 conventions for TImode variables. */
294 #define MIN_UNITS_PER_WORD 4
296 /* The widest floating point format supported by the hardware. Note that
297 setting this influences some Ada floating point type sizes, currently
298 required for GNAT to operate properly. */
299 #define WIDEST_HARDWARE_FP_SIZE 64
301 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
302 #define PARM_BOUNDARY BITS_PER_WORD
304 /* Largest alignment required for any stack parameter, in bits.
305 Don't define this if it is equal to PARM_BOUNDARY */
306 #define MAX_PARM_BOUNDARY BIGGEST_ALIGNMENT
308 /* Boundary (in *bits*) on which stack pointer is always aligned;
309 certain optimizations in combine depend on this.
311 The HP-UX runtime documents mandate 64-byte and 16-byte alignment for
312 the stack on the 32 and 64-bit ports, respectively. However, we
313 are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT
314 in main. Thus, we treat the former as the preferred alignment. */
315 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
316 #define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512)
318 /* Allocation boundary (in *bits*) for the code of a function. */
319 #define FUNCTION_BOUNDARY BITS_PER_WORD
321 /* Alignment of field after `int : 0' in a structure. */
322 #define EMPTY_FIELD_BOUNDARY 32
324 /* Every structure's size must be a multiple of this. */
325 #define STRUCTURE_SIZE_BOUNDARY 8
327 /* A bit-field declared as `int' forces `int' alignment for the struct. */
328 #define PCC_BITFIELD_TYPE_MATTERS 1
330 /* No data type wants to be aligned rounder than this. */
331 #define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD)
333 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
334 #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
335 ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
337 /* Make arrays of chars word-aligned for the same reasons. */
338 #define DATA_ALIGNMENT(TYPE, ALIGN) \
339 (TREE_CODE (TYPE) == ARRAY_TYPE \
340 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
341 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
343 /* Set this nonzero if move instructions will actually fail to work
344 when given unaligned data. */
345 #define STRICT_ALIGNMENT 1
347 /* Value is 1 if it is a good idea to tie two pseudo registers
348 when one has mode MODE1 and one has mode MODE2.
349 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
350 for any hard reg, then this must be 0 for correct output. */
351 #define MODES_TIEABLE_P(MODE1, MODE2) \
352 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
354 /* Specify the registers used for certain standard purposes.
355 The values of these macros are register numbers. */
357 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
358 /* #define PC_REGNUM */
360 /* Register to use for pushing function arguments. */
361 #define STACK_POINTER_REGNUM 30
363 /* Base register for access to local variables of the function. */
364 #define FRAME_POINTER_REGNUM 3
366 /* Value should be nonzero if functions must have frame pointers. */
367 #define FRAME_POINTER_REQUIRED \
368 (current_function_calls_alloca)
370 /* Don't allow hard registers to be renamed into r2 unless r2
371 is already live or already being saved (due to eh). */
373 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
374 ((NEW_REG) != 2 || df_regs_ever_live_p (2) || current_function_calls_eh_return)
376 /* C statement to store the difference between the frame pointer
377 and the stack pointer values immediately after the function prologue.
379 Note, we always pretend that this is a leaf function because if
380 it's not, there's no point in trying to eliminate the
381 frame pointer. If it is a leaf function, we guessed right! */
382 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
383 do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
385 /* Base register for access to arguments of the function. */
386 #define ARG_POINTER_REGNUM (TARGET_64BIT ? 29 : 3)
388 /* Register in which static-chain is passed to a function. */
389 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? 31 : 29)
391 /* Register used to address the offset table for position-independent
393 #define PIC_OFFSET_TABLE_REGNUM \
394 (flag_pic ? (TARGET_64BIT ? 27 : 19) : INVALID_REGNUM)
396 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
398 /* Function to return the rtx used to save the pic offset table register
399 across function calls. */
400 extern struct rtx_def *hppa_pic_save_rtx (void);
402 #define DEFAULT_PCC_STRUCT_RETURN 0
404 /* Register in which address to store a structure value
405 is passed to a function. */
406 #define PA_STRUCT_VALUE_REGNUM 28
408 /* Describe how we implement __builtin_eh_return. */
409 #define EH_RETURN_DATA_REGNO(N) \
410 ((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM)
411 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
412 #define EH_RETURN_HANDLER_RTX pa_eh_return_handler_rtx ()
414 /* Offset from the frame pointer register value to the top of stack. */
415 #define FRAME_POINTER_CFA_OFFSET(FNDECL) 0
417 /* A C expression whose value is RTL representing the location of the
418 incoming return address at the beginning of any function, before the
419 prologue. You only need to define this macro if you want to support
420 call frame debugging information like that provided by DWARF 2. */
421 #define INCOMING_RETURN_ADDR_RTX (gen_rtx_REG (word_mode, 2))
422 #define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (2))
424 /* A C expression whose value is an integer giving a DWARF 2 column
425 number that may be used as an alternate return column. This should
426 be defined only if DWARF_FRAME_RETURN_COLUMN is set to a general
427 register, but an alternate column needs to be used for signal frames.
429 Column 0 is not used but unfortunately its register size is set to
430 4 bytes (sizeof CCmode) so it can't be used on 64-bit targets. */
431 #define DWARF_ALT_FRAME_RETURN_COLUMN FIRST_PSEUDO_REGISTER
433 /* This macro chooses the encoding of pointers embedded in the exception
434 handling sections. If at all possible, this should be defined such
435 that the exception handling section will not require dynamic relocations,
436 and so may be read-only.
438 Because the HP assembler auto aligns, it is necessary to use
439 DW_EH_PE_aligned. It's not possible to make the data read-only
440 on the HP-UX SOM port since the linker requires fixups for label
441 differences in different sections to be word aligned. However,
442 the SOM linker can do unaligned fixups for absolute pointers.
443 We also need aligned pointers for global and function pointers.
445 Although the HP-UX 64-bit ELF linker can handle unaligned pc-relative
446 fixups, the runtime doesn't have a consistent relationship between
447 text and data for dynamically loaded objects. Thus, it's not possible
448 to use pc-relative encoding for pointers on this target. It may be
449 possible to use segment relative encodings but GAS doesn't currently
450 have a mechanism to generate these encodings. For other targets, we
451 use pc-relative encoding for pointers. If the pointer might require
452 dynamic relocation, we make it indirect. */
453 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
454 (TARGET_GAS && !TARGET_HPUX \
456 | ((GLOBAL) || (CODE) == 2 ? DW_EH_PE_indirect : 0) \
457 | (TARGET_64BIT ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)) \
458 : (!TARGET_GAS || (GLOBAL) || (CODE) == 2 \
459 ? DW_EH_PE_aligned : DW_EH_PE_absptr))
461 /* Handle special EH pointer encodings. Absolute, pc-relative, and
462 indirect are handled automatically. We output pc-relative, and
463 indirect pc-relative ourself since we need some special magic to
464 generate pc-relative relocations, and to handle indirect function
466 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
468 if (((ENCODING) & 0x70) == DW_EH_PE_pcrel) \
470 fputs (integer_asm_op (SIZE, FALSE), FILE); \
471 if ((ENCODING) & DW_EH_PE_indirect) \
472 output_addr_const (FILE, get_deferred_plabel (ADDR)); \
474 assemble_name (FILE, XSTR ((ADDR), 0)); \
475 fputs ("+8-$PIC_pcrel$0", FILE); \
481 /* The class value for index registers, and the one for base regs. */
482 #define INDEX_REG_CLASS GENERAL_REGS
483 #define BASE_REG_CLASS GENERAL_REGS
485 #define FP_REG_CLASS_P(CLASS) \
486 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
488 /* True if register is floating-point. */
489 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
491 /* Given an rtx X being reloaded into a reg required to be
492 in class CLASS, return the class of reg to actually use.
493 In general this is just CLASS; but on some machines
494 in some cases it is preferable to use a more restrictive class. */
495 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
497 #define MAYBE_FP_REG_CLASS_P(CLASS) \
498 reg_classes_intersect_p ((CLASS), FP_REGS)
500 /* On the PA it is not possible to directly move data between
501 GENERAL_REGS and FP_REGS. On the 32-bit port, we use the
502 location at SP-16. We don't expose this location in the RTL to
503 avoid scheduling related problems. For example, the store and
504 load could be separated by a call to a pure or const function
505 which has no frame and uses SP-16. */
506 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
508 && (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \
509 || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1)))
512 /* Stack layout; function entry, exit and calling. */
514 /* Define this if pushing a word on the stack
515 makes the stack pointer a smaller address. */
516 /* #define STACK_GROWS_DOWNWARD */
518 /* Believe it or not. */
519 #define ARGS_GROW_DOWNWARD
521 /* Define this to nonzero if the nominal address of the stack frame
522 is at the high-address end of the local variables;
523 that is, each additional local variable allocated
524 goes at a more negative offset in the frame. */
525 #define FRAME_GROWS_DOWNWARD 0
527 /* Offset within stack frame to start allocating local variables at.
528 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
529 first local allocated. Otherwise, it is the offset to the BEGINNING
530 of the first local allocated.
532 On the 32-bit ports, we reserve one slot for the previous frame
533 pointer and one fill slot. The fill slot is for compatibility
534 with HP compiled programs. On the 64-bit ports, we reserve one
535 slot for the previous frame pointer. */
536 #define STARTING_FRAME_OFFSET 8
538 /* Define STACK_ALIGNMENT_NEEDED to zero to disable final alignment
539 of the stack. The default is to align it to STACK_BOUNDARY. */
540 #define STACK_ALIGNMENT_NEEDED 0
542 /* If we generate an insn to push BYTES bytes,
543 this says how many the stack pointer really advances by.
544 On the HP-PA, don't define this because there are no push insns. */
545 /* #define PUSH_ROUNDING(BYTES) */
547 /* Offset of first parameter from the argument pointer register value.
548 This value will be negated because the arguments grow down.
549 Also note that on STACK_GROWS_UPWARD machines (such as this one)
550 this is the distance from the frame pointer to the end of the first
551 argument, not it's beginning. To get the real offset of the first
552 argument, the size of the argument must be added. */
554 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
556 /* When a parameter is passed in a register, stack space is still
558 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
560 /* Define this if the above stack space is to be considered part of the
561 space allocated by the caller. */
562 #define OUTGOING_REG_PARM_STACK_SPACE 1
564 /* Keep the stack pointer constant throughout the function.
565 This is both an optimization and a necessity: longjmp
566 doesn't behave itself when the stack pointer moves within
568 #define ACCUMULATE_OUTGOING_ARGS 1
570 /* The weird HPPA calling conventions require a minimum of 48 bytes on
571 the stack: 16 bytes for register saves, and 32 bytes for magic.
572 This is the difference between the logical top of stack and the
575 On the 64-bit port, the HP C compiler allocates a 48-byte frame
576 marker, although the runtime documentation only describes a 16
577 byte marker. For compatibility, we allocate 48 bytes. */
578 #define STACK_POINTER_OFFSET \
579 (TARGET_64BIT ? -(current_function_outgoing_args_size + 48): -32)
581 #define STACK_DYNAMIC_OFFSET(FNDECL) \
583 ? (STACK_POINTER_OFFSET) \
584 : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size))
586 /* Value is 1 if returning from a function call automatically
587 pops the arguments described by the number-of-args field in the call.
588 FUNDECL is the declaration node of the function (as a tree),
589 FUNTYPE is the data type of the function (as a tree),
590 or for a library call it is an identifier node for the subroutine name. */
592 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
594 /* Define how to find the value returned by a function.
595 VALTYPE is the data type of the value (as a tree).
596 If the precise function being called is known, FUNC is its FUNCTION_DECL;
597 otherwise, FUNC is 0. */
599 #define FUNCTION_VALUE(VALTYPE, FUNC) function_value (VALTYPE, FUNC)
601 /* Define how to find the value returned by a library function
602 assuming the value has mode MODE. */
604 #define LIBCALL_VALUE(MODE) \
606 (! TARGET_SOFT_FLOAT \
607 && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
609 /* 1 if N is a possible register number for a function value
610 as seen by the caller. */
612 #define FUNCTION_VALUE_REGNO_P(N) \
613 ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
616 /* Define a data type for recording info about an argument list
617 during the scan of that argument list. This data type should
618 hold all necessary information about the function itself
619 and about the args processed so far, enough to enable macros
620 such as FUNCTION_ARG to determine where the next arg should go.
622 On the HP-PA, the WORDS field holds the number of words
623 of arguments scanned so far (including the invisible argument,
624 if any, which holds the structure-value-address). Thus, 4 or
625 more means all following args should go on the stack.
627 The INCOMING field tracks whether this is an "incoming" or
630 The INDIRECT field indicates whether this is is an indirect
633 The NARGS_PROTOTYPE field indicates that an argument does not
634 have a prototype when it less than or equal to 0. */
636 struct hppa_args {int words, nargs_prototype, incoming, indirect; };
638 #define CUMULATIVE_ARGS struct hppa_args
640 /* Initialize a variable CUM of type CUMULATIVE_ARGS
641 for a call to a function whose data type is FNTYPE.
642 For a library call, FNTYPE is 0. */
644 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
646 (CUM).incoming = 0, \
647 (CUM).indirect = (FNTYPE) && !(FNDECL), \
648 (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \
649 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
650 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
651 || pa_return_in_memory (TREE_TYPE (FNTYPE), 0))) \
656 /* Similar, but when scanning the definition of a procedure. We always
657 set NARGS_PROTOTYPE large so we never return a PARALLEL. */
659 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
661 (CUM).incoming = 1, \
662 (CUM).indirect = 0, \
663 (CUM).nargs_prototype = 1000
665 /* Figure out the size in words of the function argument. The size
666 returned by this macro should always be greater than zero because
667 we pass variable and zero sized objects by reference. */
669 #define FUNCTION_ARG_SIZE(MODE, TYPE) \
670 ((((MODE) != BLKmode \
671 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
672 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
674 /* Update the data in CUM to advance over an argument
675 of mode MODE and data type TYPE.
676 (TYPE is null for libcalls where that information may not be available.) */
678 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
679 { (CUM).nargs_prototype--; \
680 (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \
681 + (((CUM).words & 01) && (TYPE) != 0 \
682 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \
685 /* Determine where to put an argument to a function.
686 Value is zero to push the argument on the stack,
687 or a hard register in which to store the argument.
689 MODE is the argument's machine mode.
690 TYPE is the data type of the argument (as a tree).
691 This is null for libcalls where that information may
693 CUM is a variable of type CUMULATIVE_ARGS which gives info about
694 the preceding args and about the function being called.
695 NAMED is nonzero if this argument is a named parameter
696 (otherwise it is an extra parameter matching an ellipsis).
698 On the HP-PA the first four words of args are normally in registers
699 and the rest are pushed. But any arg that won't entirely fit in regs
702 Arguments passed in registers are either 1 or 2 words long.
704 The caller must make a distinction between calls to explicitly named
705 functions and calls through pointers to functions -- the conventions
706 are different! Calls through pointers to functions only use general
707 registers for the first four argument words.
709 Of course all this is different for the portable runtime model
710 HP wants everyone to use for ELF. Ugh. Here's a quick description
711 of how it's supposed to work.
713 1) callee side remains unchanged. It expects integer args to be
714 in the integer registers, float args in the float registers and
715 unnamed args in integer registers.
717 2) caller side now depends on if the function being called has
718 a prototype in scope (rather than if it's being called indirectly).
720 2a) If there is a prototype in scope, then arguments are passed
721 according to their type (ints in integer registers, floats in float
722 registers, unnamed args in integer registers.
724 2b) If there is no prototype in scope, then floating point arguments
725 are passed in both integer and float registers. egad.
727 FYI: The portable parameter passing conventions are almost exactly like
728 the standard parameter passing conventions on the RS6000. That's why
729 you'll see lots of similar code in rs6000.h. */
731 /* If defined, a C expression which determines whether, and in which
732 direction, to pad out an argument with extra space. */
733 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
735 /* Specify padding for the last element of a block move between registers
738 The 64-bit runtime specifies that objects need to be left justified
739 (i.e., the normal justification for a big endian target). The 32-bit
740 runtime specifies right justification for objects smaller than 64 bits.
741 We use a DImode register in the parallel for 5 to 7 byte structures
742 so that there is only one element. This allows the object to be
744 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
745 function_arg_padding ((MODE), (TYPE))
747 /* Do not expect to understand this without reading it several times. I'm
748 tempted to try and simply it, but I worry about breaking something. */
750 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
751 function_arg (&CUM, MODE, TYPE, NAMED)
753 /* If defined, a C expression that gives the alignment boundary, in
754 bits, of an argument with the specified mode and type. If it is
755 not defined, `PARM_BOUNDARY' is used for all arguments. */
757 /* Arguments larger than one word are double word aligned. */
759 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
761 ? (integer_zerop (TYPE_SIZE (TYPE)) \
762 || !TREE_CONSTANT (TYPE_SIZE (TYPE)) \
763 || int_size_in_bytes (TYPE) <= UNITS_PER_WORD) \
764 : GET_MODE_SIZE(MODE) <= UNITS_PER_WORD) \
765 ? PARM_BOUNDARY : MAX_PARM_BOUNDARY)
768 extern GTY(()) rtx hppa_compare_op0;
769 extern GTY(()) rtx hppa_compare_op1;
770 extern enum cmp_type hppa_branch_type;
772 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
773 as assembly via FUNCTION_PROFILER. Just output a local label.
774 We can't use the function label because the GAS SOM target can't
775 handle the difference of a global symbol and a local symbol. */
777 #ifndef FUNC_BEGIN_PROLOG_LABEL
778 #define FUNC_BEGIN_PROLOG_LABEL "LFBP"
781 #define FUNCTION_PROFILER(FILE, LABEL) \
782 (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
784 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
785 void hppa_profile_hook (int label_no);
787 /* The profile counter if emitted must come before the prologue. */
788 #define PROFILE_BEFORE_PROLOGUE 1
790 /* We never want final.c to emit profile counters. When profile
791 counters are required, we have to defer emitting them to the end
792 of the current file. */
793 #define NO_PROFILE_COUNTERS 1
795 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
796 the stack pointer does not matter. The value is tested only in
797 functions that have frame pointers.
798 No definition is equivalent to always zero. */
800 extern int may_call_alloca;
802 #define EXIT_IGNORE_STACK \
803 (get_frame_size () != 0 \
804 || current_function_calls_alloca || current_function_outgoing_args_size)
806 /* Output assembler code for a block containing the constant parts
807 of a trampoline, leaving space for the variable parts.\
809 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
810 and then branches to the specified routine.
812 This code template is copied from text segment to stack location
813 and then patched with INITIALIZE_TRAMPOLINE to contain
814 valid values, and then entered as a subroutine.
816 It is best to keep this as small as possible to avoid having to
817 flush multiple lines in the cache. */
819 #define TRAMPOLINE_TEMPLATE(FILE) \
823 fputs ("\tldw 36(%r22),%r21\n", FILE); \
824 fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
825 if (ASSEMBLER_DIALECT == 0) \
826 fputs ("\tdepi 0,31,2,%r21\n", FILE); \
828 fputs ("\tdepwi 0,31,2,%r21\n", FILE); \
829 fputs ("\tldw 4(%r21),%r19\n", FILE); \
830 fputs ("\tldw 0(%r21),%r21\n", FILE); \
833 fputs ("\tbve (%r21)\n", FILE); \
834 fputs ("\tldw 40(%r22),%r29\n", FILE); \
835 fputs ("\t.word 0\n", FILE); \
836 fputs ("\t.word 0\n", FILE); \
840 fputs ("\tldsid (%r21),%r1\n", FILE); \
841 fputs ("\tmtsp %r1,%sr0\n", FILE); \
842 fputs ("\tbe 0(%sr0,%r21)\n", FILE); \
843 fputs ("\tldw 40(%r22),%r29\n", FILE); \
845 fputs ("\t.word 0\n", FILE); \
846 fputs ("\t.word 0\n", FILE); \
847 fputs ("\t.word 0\n", FILE); \
848 fputs ("\t.word 0\n", FILE); \
852 fputs ("\t.dword 0\n", FILE); \
853 fputs ("\t.dword 0\n", FILE); \
854 fputs ("\t.dword 0\n", FILE); \
855 fputs ("\t.dword 0\n", FILE); \
856 fputs ("\tmfia %r31\n", FILE); \
857 fputs ("\tldd 24(%r31),%r1\n", FILE); \
858 fputs ("\tldd 24(%r1),%r27\n", FILE); \
859 fputs ("\tldd 16(%r1),%r1\n", FILE); \
860 fputs ("\tbve (%r1)\n", FILE); \
861 fputs ("\tldd 32(%r31),%r31\n", FILE); \
862 fputs ("\t.dword 0 ; fptr\n", FILE); \
863 fputs ("\t.dword 0 ; static link\n", FILE); \
867 /* Length in units of the trampoline for entering a nested function. */
869 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
871 /* Length in units of the trampoline instruction code. */
873 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
875 /* Minimum length of a cache line. A length of 16 will work on all
876 PA-RISC processors. All PA 1.1 processors have a cache line of
877 32 bytes. Most but not all PA 2.0 processors have a cache line
878 of 64 bytes. As cache flushes are expensive and we don't support
879 PA 1.0, we use a minimum length of 32. */
881 #define MIN_CACHELINE_SIZE 32
883 /* Emit RTL insns to initialize the variable parts of a trampoline.
884 FNADDR is an RTX for the address of the function's pure code.
885 CXT is an RTX for the static chain value for the function.
887 Move the function address to the trampoline template at offset 36.
888 Move the static chain value to trampoline template at offset 40.
889 Move the trampoline address to trampoline template at offset 44.
890 Move r19 to trampoline template at offset 48. The latter two
891 words create a plabel for the indirect call to the trampoline.
893 A similar sequence is used for the 64-bit port but the plabel is
894 at the beginning of the trampoline.
896 Finally, the cache entries for the trampoline code are flushed.
897 This is necessary to ensure that the trampoline instruction sequence
898 is written to memory prior to any attempts at prefetching the code
901 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
903 rtx start_addr = gen_reg_rtx (Pmode); \
904 rtx end_addr = gen_reg_rtx (Pmode); \
905 rtx line_length = gen_reg_rtx (Pmode); \
910 tmp = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
911 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
912 tmp = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
913 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
915 /* Create a fat pointer for the trampoline. */ \
916 tmp = memory_address (Pmode, plus_constant ((TRAMP), 44)); \
917 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP)); \
918 tmp = memory_address (Pmode, plus_constant ((TRAMP), 48)); \
919 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
920 gen_rtx_REG (Pmode, 19)); \
922 /* fdc and fic only use registers for the address to flush, \
923 they do not accept integer displacements. We align the \
924 start and end addresses to the beginning of their respective \
925 cache lines to minimize the number of lines flushed. */ \
926 tmp = force_reg (Pmode, (TRAMP)); \
927 emit_insn (gen_andsi3 (start_addr, tmp, \
928 GEN_INT (-MIN_CACHELINE_SIZE))); \
929 tmp = force_reg (Pmode, \
930 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
931 emit_insn (gen_andsi3 (end_addr, tmp, \
932 GEN_INT (-MIN_CACHELINE_SIZE))); \
933 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
934 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
935 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
936 gen_reg_rtx (Pmode), \
937 gen_reg_rtx (Pmode))); \
941 tmp = memory_address (Pmode, plus_constant ((TRAMP), 56)); \
942 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
943 tmp = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
944 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
946 /* Create a fat pointer for the trampoline. */ \
947 tmp = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
948 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
949 force_reg (Pmode, plus_constant ((TRAMP), 32))); \
950 tmp = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
951 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
952 gen_rtx_REG (Pmode, 27)); \
954 /* fdc and fic only use registers for the address to flush, \
955 they do not accept integer displacements. We align the \
956 start and end addresses to the beginning of their respective \
957 cache lines to minimize the number of lines flushed. */ \
958 tmp = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
959 emit_insn (gen_anddi3 (start_addr, tmp, \
960 GEN_INT (-MIN_CACHELINE_SIZE))); \
961 tmp = force_reg (Pmode, \
962 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
963 emit_insn (gen_anddi3 (end_addr, tmp, \
964 GEN_INT (-MIN_CACHELINE_SIZE))); \
965 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
966 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
967 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
968 gen_reg_rtx (Pmode), \
969 gen_reg_rtx (Pmode))); \
973 /* Perform any machine-specific adjustment in the address of the trampoline.
974 ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
975 Adjust the trampoline address to point to the plabel at offset 44. */
977 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
978 if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))
980 /* Addressing modes, and classification of registers for them.
982 Using autoincrement addressing modes on PA8000 class machines is
985 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
986 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
988 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
989 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
991 /* Macros to check register numbers against specific register classes. */
993 /* The following macros assume that X is a hard or pseudo reg number.
994 They give nonzero only if X is a hard reg of the suitable class
995 or a pseudo reg currently allocated to a suitable hard reg.
996 Since they use reg_renumber, they are safe only once reg_renumber
997 has been allocated, which happens in local-alloc.c. */
999 #define REGNO_OK_FOR_INDEX_P(X) \
1001 || (X >= FIRST_PSEUDO_REGISTER \
1003 && (unsigned) reg_renumber[X] < 32)))
1004 #define REGNO_OK_FOR_BASE_P(X) \
1006 || (X >= FIRST_PSEUDO_REGISTER \
1008 && (unsigned) reg_renumber[X] < 32)))
1009 #define REGNO_OK_FOR_FP_P(X) \
1011 || (X >= FIRST_PSEUDO_REGISTER \
1013 && FP_REGNO_P (reg_renumber[X])))
1015 /* Now macros that check whether X is a register and also,
1016 strictly, whether it is in a specified class.
1018 These macros are specific to the HP-PA, and may be used only
1019 in code for printing assembler insns and in conditions for
1020 define_optimization. */
1022 /* 1 if X is an fp register. */
1024 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1026 /* Maximum number of registers that can appear in a valid memory address. */
1028 #define MAX_REGS_PER_ADDRESS 2
1030 /* Non-TLS symbolic references. */
1031 #define PA_SYMBOL_REF_TLS_P(RTX) \
1032 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
1034 /* Recognize any constant value that is a valid address except
1035 for symbolic addresses. We get better CSE by rejecting them
1036 here and allowing hppa_legitimize_address to break them up. We
1037 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
1039 #define CONSTANT_ADDRESS_P(X) \
1040 ((GET_CODE (X) == LABEL_REF \
1041 || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
1042 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1043 || GET_CODE (X) == HIGH) \
1044 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
1046 /* A C expression that is nonzero if we are using the new HP assembler. */
1048 #ifndef NEW_HP_ASSEMBLER
1049 #define NEW_HP_ASSEMBLER 0
1052 /* The macros below define the immediate range for CONST_INTS on
1053 the 64-bit port. Constants in this range can be loaded in three
1054 instructions using a ldil/ldo/depdi sequence. Constants outside
1055 this range are forced to the constant pool prior to reload. */
1057 #define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
1058 #define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31)
1059 #define LEGITIMATE_64BIT_CONST_INT_P(X) \
1060 ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)
1062 /* A C expression that is nonzero if X is a legitimate constant for an
1065 We include all constant integers and constant doubles, but not
1066 floating-point, except for floating-point zero. We reject LABEL_REFs
1067 if we're not using gas or the new HP assembler.
1069 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
1070 that need more than three instructions to load prior to reload. This
1071 limit is somewhat arbitrary. It takes three instructions to load a
1072 CONST_INT from memory but two are memory accesses. It may be better
1073 to increase the allowed range for CONST_INTS. We may also be able
1074 to handle CONST_DOUBLES. */
1076 #define LEGITIMATE_CONSTANT_P(X) \
1077 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1078 || (X) == CONST0_RTX (GET_MODE (X))) \
1079 && (NEW_HP_ASSEMBLER \
1081 || GET_CODE (X) != LABEL_REF) \
1083 || GET_CODE (X) != CONST_DOUBLE) \
1085 || HOST_BITS_PER_WIDE_INT <= 32 \
1086 || GET_CODE (X) != CONST_INT \
1087 || reload_in_progress \
1088 || reload_completed \
1089 || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X)) \
1090 || cint_ok_for_move (INTVAL (X))) \
1091 && !function_label_operand (X, VOIDmode))
1093 /* Target flags set on a symbol_ref. */
1095 /* Set by ASM_OUTPUT_SYMBOL_REF when a symbol_ref is output. */
1096 #define SYMBOL_FLAG_REFERENCED (1 << SYMBOL_FLAG_MACH_DEP_SHIFT)
1097 #define SYMBOL_REF_REFERENCED_P(RTX) \
1098 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_REFERENCED) != 0)
1100 /* Defines for constraints.md. */
1102 /* Return 1 iff OP is a scaled or unscaled index address. */
1103 #define IS_INDEX_ADDR_P(OP) \
1104 (GET_CODE (OP) == PLUS \
1105 && GET_MODE (OP) == Pmode \
1106 && (GET_CODE (XEXP (OP, 0)) == MULT \
1107 || GET_CODE (XEXP (OP, 1)) == MULT \
1108 || (REG_P (XEXP (OP, 0)) \
1109 && REG_P (XEXP (OP, 1)))))
1111 /* Return 1 iff OP is a LO_SUM DLT address. */
1112 #define IS_LO_SUM_DLT_ADDR_P(OP) \
1113 (GET_CODE (OP) == LO_SUM \
1114 && GET_MODE (OP) == Pmode \
1115 && REG_P (XEXP (OP, 0)) \
1116 && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
1117 && GET_CODE (XEXP (OP, 1)) == UNSPEC)
1119 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1120 and check its validity for a certain class.
1121 We have two alternate definitions for each of them.
1122 The usual definition accepts all pseudo regs; the other rejects
1123 them unless they have been allocated suitable hard regs.
1124 The symbol REG_OK_STRICT causes the latter definition to be used.
1126 Most source files want to accept pseudo regs in the hope that
1127 they will get allocated to the class that the insn wants them to be in.
1128 Source files for reload pass need to be strict.
1129 After reload, it makes no difference, since pseudo regs have
1130 been eliminated by then. */
1132 #ifndef REG_OK_STRICT
1134 /* Nonzero if X is a hard reg that can be used as an index
1135 or if it is a pseudo reg. */
1136 #define REG_OK_FOR_INDEX_P(X) \
1137 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1138 /* Nonzero if X is a hard reg that can be used as a base reg
1139 or if it is a pseudo reg. */
1140 #define REG_OK_FOR_BASE_P(X) \
1141 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1145 /* Nonzero if X is a hard reg that can be used as an index. */
1146 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1147 /* Nonzero if X is a hard reg that can be used as a base reg. */
1148 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1152 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1153 valid memory address for an instruction. The MODE argument is the
1154 machine mode for the MEM expression that wants to use this address.
1156 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
1157 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
1158 available with floating point loads and stores, and integer loads.
1159 We get better code by allowing indexed addresses in the initial
1162 The acceptance of indexed addresses as legitimate implies that we
1163 must provide patterns for doing indexed integer stores, or the move
1164 expanders must force the address of an indexed store to a register.
1165 We have adopted the latter approach.
1167 Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that
1168 the base register is a valid pointer for indexed instructions.
1169 On targets that have non-equivalent space registers, we have to
1170 know at the time of assembler output which register in a REG+REG
1171 pair is the base register. The REG_POINTER flag is sometimes lost
1172 in reload and the following passes, so it can't be relied on during
1173 code generation. Thus, we either have to canonicalize the order
1174 of the registers in REG+REG indexed addresses, or treat REG+REG
1175 addresses separately and provide patterns for both permutations.
1177 The latter approach requires several hundred additional lines of
1178 code in pa.md. The downside to canonicalizing is that a PLUS
1179 in the wrong order can't combine to form to make a scaled indexed
1180 memory operand. As we won't need to canonicalize the operands if
1181 the REG_POINTER lossage can be fixed, it seems better canonicalize.
1183 We initially break out scaled indexed addresses in canonical order
1184 in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
1185 scaled indexed addresses during RTL generation. However, fold_rtx
1186 has its own opinion on how the operands of a PLUS should be ordered.
1187 If one of the operands is equivalent to a constant, it will make
1188 that operand the second operand. As the base register is likely to
1189 be equivalent to a SYMBOL_REF, we have made it the second operand.
1191 GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the
1192 operands are in the order INDEX+BASE on targets with non-equivalent
1193 space registers, and in any order on targets with equivalent space
1194 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
1196 We treat a SYMBOL_REF as legitimate if it is part of the current
1197 function's constant-pool, because such addresses can actually be
1198 output as REG+SMALLINT.
1200 Note we only allow 5-bit immediates for access to a constant address;
1201 doing so avoids losing for loading/storing a FP register at an address
1202 which will not fit in 5 bits. */
1204 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
1205 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
1207 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
1208 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
1210 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
1211 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
1213 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
1214 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
1216 #if HOST_BITS_PER_WIDE_INT > 32
1217 #define VAL_32_BITS_P(X) \
1218 ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \
1219 < (unsigned HOST_WIDE_INT) 2 << 31)
1221 #define VAL_32_BITS_P(X) 1
1223 #define INT_32_BITS(X) VAL_32_BITS_P (INTVAL (X))
1225 /* These are the modes that we allow for scaled indexing. */
1226 #define MODE_OK_FOR_SCALED_INDEXING_P(MODE) \
1227 ((TARGET_64BIT && (MODE) == DImode) \
1228 || (MODE) == SImode \
1229 || (MODE) == HImode \
1230 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1232 /* These are the modes that we allow for unscaled indexing. */
1233 #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \
1234 ((TARGET_64BIT && (MODE) == DImode) \
1235 || (MODE) == SImode \
1236 || (MODE) == HImode \
1237 || (MODE) == QImode \
1238 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1240 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1242 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1243 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
1244 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
1245 && REG_P (XEXP (X, 0)) \
1246 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
1248 else if (GET_CODE (X) == PLUS) \
1250 rtx base = 0, index = 0; \
1251 if (REG_P (XEXP (X, 1)) \
1252 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1253 base = XEXP (X, 1), index = XEXP (X, 0); \
1254 else if (REG_P (XEXP (X, 0)) \
1255 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1256 base = XEXP (X, 0), index = XEXP (X, 1); \
1258 && GET_CODE (index) == CONST_INT \
1259 && ((INT_14_BITS (index) \
1260 && (((MODE) != DImode \
1261 && (MODE) != SFmode \
1262 && (MODE) != DFmode) \
1263 /* The base register for DImode loads and stores \
1264 with long displacements must be aligned because \
1265 the lower three bits in the displacement are \
1266 assumed to be zero. */ \
1267 || ((MODE) == DImode \
1269 || (INTVAL (index) % 8) == 0)) \
1270 /* Similarly, the base register for SFmode/DFmode \
1271 loads and stores with long displacements must \
1274 FIXME: the ELF32 linker clobbers the LSB of \
1275 the FP register number in PA 2.0 floating-point \
1276 insns with long displacements. This is because \
1277 R_PARISC_DPREL14WR and other relocations like \
1278 it are not supported. For now, we reject long \
1279 displacements on this target. */ \
1280 || (((MODE) == SFmode || (MODE) == DFmode) \
1281 && (TARGET_SOFT_FLOAT \
1284 && (INTVAL (index) \
1285 % GET_MODE_SIZE (MODE)) == 0))))) \
1286 || INT_5_BITS (index))) \
1288 if (!TARGET_DISABLE_INDEXING \
1289 /* Only accept the "canonical" INDEX+BASE operand order \
1290 on targets with non-equivalent space registers. */ \
1291 && (TARGET_NO_SPACE_REGS \
1292 ? (base && REG_P (index)) \
1293 : (base == XEXP (X, 1) && REG_P (index) \
1294 && (reload_completed \
1295 || (reload_in_progress && HARD_REGISTER_P (base)) \
1296 || REG_POINTER (base)) \
1297 && (reload_completed \
1298 || (reload_in_progress && HARD_REGISTER_P (index)) \
1299 || !REG_POINTER (index)))) \
1300 && MODE_OK_FOR_UNSCALED_INDEXING_P (MODE) \
1301 && REG_OK_FOR_INDEX_P (index) \
1302 && borx_reg_operand (base, Pmode) \
1303 && borx_reg_operand (index, Pmode)) \
1305 if (!TARGET_DISABLE_INDEXING \
1307 && GET_CODE (index) == MULT \
1308 && MODE_OK_FOR_SCALED_INDEXING_P (MODE) \
1309 && REG_P (XEXP (index, 0)) \
1310 && GET_MODE (XEXP (index, 0)) == Pmode \
1311 && REG_OK_FOR_INDEX_P (XEXP (index, 0)) \
1312 && GET_CODE (XEXP (index, 1)) == CONST_INT \
1313 && INTVAL (XEXP (index, 1)) \
1314 == (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
1315 && borx_reg_operand (base, Pmode)) \
1318 else if (GET_CODE (X) == LO_SUM \
1319 && GET_CODE (XEXP (X, 0)) == REG \
1320 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1321 && CONSTANT_P (XEXP (X, 1)) \
1322 && (TARGET_SOFT_FLOAT \
1323 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1326 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1327 || ((MODE) != SFmode \
1328 && (MODE) != DFmode))) \
1330 else if (GET_CODE (X) == LO_SUM \
1331 && GET_CODE (XEXP (X, 0)) == SUBREG \
1332 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG \
1333 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0))) \
1334 && CONSTANT_P (XEXP (X, 1)) \
1335 && (TARGET_SOFT_FLOAT \
1336 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1339 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1340 || ((MODE) != SFmode \
1341 && (MODE) != DFmode))) \
1343 else if (GET_CODE (X) == LABEL_REF \
1344 || (GET_CODE (X) == CONST_INT \
1345 && INT_5_BITS (X))) \
1347 /* Needed for -fPIC */ \
1348 else if (GET_CODE (X) == LO_SUM \
1349 && GET_CODE (XEXP (X, 0)) == REG \
1350 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1351 && GET_CODE (XEXP (X, 1)) == UNSPEC \
1352 && (TARGET_SOFT_FLOAT \
1353 || (TARGET_PA_20 && !TARGET_ELF32) \
1354 || ((MODE) != SFmode \
1355 && (MODE) != DFmode))) \
1359 /* Look for machine dependent ways to make the invalid address AD a
1362 For the PA, transform:
1364 memory(X + <large int>)
1368 if (<large int> & mask) >= 16
1369 Y = (<large int> & ~mask) + mask + 1 Round up.
1371 Y = (<large int> & ~mask) Round down.
1373 memory (Z + (<large int> - Y));
1375 This makes reload inheritance and reload_cse work better since Z
1378 There may be more opportunities to improve code with this hook. */
1379 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
1381 long offset, newoffset, mask; \
1382 rtx new, temp = NULL_RTX; \
1384 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1385 ? (TARGET_PA_20 && !TARGET_ELF32 ? 0x3fff : 0x1f) : 0x3fff); \
1387 if (optimize && GET_CODE (AD) == PLUS) \
1388 temp = simplify_binary_operation (PLUS, Pmode, \
1389 XEXP (AD, 0), XEXP (AD, 1)); \
1391 new = temp ? temp : AD; \
1394 && GET_CODE (new) == PLUS \
1395 && GET_CODE (XEXP (new, 0)) == REG \
1396 && GET_CODE (XEXP (new, 1)) == CONST_INT) \
1398 offset = INTVAL (XEXP ((new), 1)); \
1400 /* Choose rounding direction. Round up if we are >= halfway. */ \
1401 if ((offset & mask) >= ((mask + 1) / 2)) \
1402 newoffset = (offset & ~mask) + mask + 1; \
1404 newoffset = offset & ~mask; \
1406 /* Ensure that long displacements are aligned. */ \
1407 if (!VAL_5_BITS_P (newoffset) \
1408 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1409 newoffset &= ~(GET_MODE_SIZE (MODE) -1); \
1411 if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \
1413 temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \
1414 GEN_INT (newoffset)); \
1415 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
1416 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
1417 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
1427 /* Try machine-dependent ways of modifying an illegitimate address
1428 to be legitimate. If we find one, return the new, valid address.
1429 This macro is used in only one place: `memory_address' in explow.c.
1431 OLDX is the address as it was before break_out_memory_refs was called.
1432 In some cases it is useful to look at this to decide what needs to be done.
1434 MODE and WIN are passed so that this macro can use
1435 GO_IF_LEGITIMATE_ADDRESS.
1437 It is always safe for this macro to do nothing. It exists to recognize
1438 opportunities to optimize the output. */
1440 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1441 { rtx orig_x = (X); \
1442 (X) = hppa_legitimize_address (X, OLDX, MODE); \
1443 if ((X) != orig_x && memory_address_p (MODE, X)) \
1446 /* Go to LABEL if ADDR (a legitimate address expression)
1447 has an effect that depends on the machine mode it is used for. */
1449 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1451 #define TARGET_ASM_SELECT_SECTION pa_select_section
1453 /* Return a nonzero value if DECL has a section attribute. */
1454 #define IN_NAMED_SECTION_P(DECL) \
1455 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
1456 && DECL_SECTION_NAME (DECL) != NULL_TREE)
1458 /* Define this macro if references to a symbol must be treated
1459 differently depending on something about the variable or
1460 function named by the symbol (such as what section it is in).
1462 The macro definition, if any, is executed immediately after the
1463 rtl for DECL or other node is created.
1464 The value of the rtl will be a `mem' whose address is a
1467 The usual thing for this macro to do is to a flag in the
1468 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1469 name string in the `symbol_ref' (if one bit is not enough
1472 On the HP-PA we use this to indicate if a symbol is in text or
1473 data space. Also, function labels need special treatment. */
1475 #define TEXT_SPACE_P(DECL)\
1476 (TREE_CODE (DECL) == FUNCTION_DECL \
1477 || (TREE_CODE (DECL) == VAR_DECL \
1478 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1479 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
1481 || CONSTANT_CLASS_P (DECL))
1483 #define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
1485 /* Specify the machine mode that this machine uses for the index in the
1486 tablejump instruction. For small tables, an element consists of a
1487 ia-relative branch and its delay slot. When -mbig-switch is specified,
1488 we use a 32-bit absolute address for non-pic code, and a 32-bit offset
1489 for both 32 and 64-bit pic code. */
1490 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
1492 /* Jump tables must be 32-bit aligned, no matter the size of the element. */
1493 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1495 /* Define this as 1 if `char' should by default be signed; else as 0. */
1496 #define DEFAULT_SIGNED_CHAR 1
1498 /* Max number of bytes we can move from memory to memory
1499 in one reasonably fast instruction. */
1502 /* Higher than the default as we prefer to use simple move insns
1503 (better scheduling and delay slot filling) and because our
1504 built-in block move is really a 2X unrolled loop.
1506 Believe it or not, this has to be big enough to allow for copying all
1507 arguments passed in registers to avoid infinite recursion during argument
1508 setup for a function call. Why? Consider how we copy the stack slots
1509 reserved for parameters when they may be trashed by a call. */
1510 #define MOVE_RATIO (TARGET_64BIT ? 8 : 4)
1512 /* Define if operations between registers always perform the operation
1513 on the full register even if a narrower mode is specified. */
1514 #define WORD_REGISTER_OPERATIONS
1516 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1517 will either zero-extend or sign-extend. The value of this macro should
1518 be the code that says which one of the two operations is implicitly
1519 done, UNKNOWN if none. */
1520 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1522 /* Nonzero if access to memory by bytes is slow and undesirable. */
1523 #define SLOW_BYTE_ACCESS 1
1525 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1526 is done just by pretending it is already truncated. */
1527 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1529 /* Specify the machine mode that pointers have.
1530 After generation of rtl, the compiler makes no further distinction
1531 between pointers and any other objects of this machine mode. */
1532 #define Pmode word_mode
1534 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1535 return the mode to be used for the comparison. For floating-point, CCFPmode
1536 should be used. CC_NOOVmode should be used when the first operand is a
1537 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1539 #define SELECT_CC_MODE(OP,X,Y) \
1540 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1542 /* A function address in a call instruction
1543 is a byte address (for indexing purposes)
1544 so give the MEM rtx a byte's mode. */
1545 #define FUNCTION_MODE SImode
1547 /* Define this if addresses of constant functions
1548 shouldn't be put through pseudo regs where they can be cse'd.
1549 Desirable on machines where ordinary constants are expensive
1550 but a CALL with constant address is cheap. */
1551 #define NO_FUNCTION_CSE
1553 /* Define this to be nonzero if shift instructions ignore all but the low-order
1555 #define SHIFT_COUNT_TRUNCATED 1
1557 /* Compute extra cost of moving data between one register class
1560 Make moves from SAR so expensive they should never happen. We used to
1561 have 0xffff here, but that generates overflow in rare cases.
1563 Copies involving a FP register and a non-FP register are relatively
1564 expensive because they must go through memory.
1566 Other copies are reasonably cheap. */
1567 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1568 (CLASS1 == SHIFT_REGS ? 0x100 \
1569 : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \
1570 : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \
1573 /* Adjust the cost of branches. */
1574 #define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1576 /* Handling the special cases is going to get too complicated for a macro,
1577 just call `pa_adjust_insn_length' to do the real work. */
1578 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1579 LENGTH += pa_adjust_insn_length (INSN, LENGTH);
1581 /* Millicode insns are actually function calls with some special
1582 constraints on arguments and register usage.
1584 Millicode calls always expect their arguments in the integer argument
1585 registers, and always return their result in %r29 (ret1). They
1586 are expected to clobber their arguments, %r1, %r29, and the return
1587 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1589 This macro tells reorg that the references to arguments and
1590 millicode calls do not appear to happen until after the millicode call.
1591 This allows reorg to put insns which set the argument registers into the
1592 delay slot of the millicode call -- thus they act more like traditional
1595 Note we cannot consider side effects of the insn to be delayed because
1596 the branch and link insn will clobber the return pointer. If we happened
1597 to use the return pointer in the delay slot of the call, then we lose.
1599 get_attr_type will try to recognize the given insn, so make sure to
1600 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1602 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
1605 /* Control the assembler format that we output. */
1607 /* A C string constant describing how to begin a comment in the target
1608 assembler language. The compiler assumes that the comment will end at
1609 the end of the line. */
1611 #define ASM_COMMENT_START ";"
1613 /* Output to assembler file text saying following lines
1614 may contain character constants, extra white space, comments, etc. */
1616 #define ASM_APP_ON ""
1618 /* Output to assembler file text saying following lines
1619 no longer contain unusual constructs. */
1621 #define ASM_APP_OFF ""
1623 /* This is how to output the definition of a user-level label named NAME,
1624 such as the label on a static function or variable NAME. */
1626 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1628 assemble_name ((FILE), (NAME)); \
1630 fputs (":\n", (FILE)); \
1632 fputc ('\n', (FILE)); \
1635 /* This is how to output a reference to a user-level label named NAME.
1636 `assemble_name' uses this. */
1638 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1640 const char *xname = (NAME); \
1641 if (FUNCTION_NAME_P (NAME)) \
1643 if (xname[0] == '*') \
1646 fputs (user_label_prefix, FILE); \
1647 fputs (xname, FILE); \
1650 /* This how we output the symbol_ref X. */
1652 #define ASM_OUTPUT_SYMBOL_REF(FILE,X) \
1654 SYMBOL_REF_FLAGS (X) |= SYMBOL_FLAG_REFERENCED; \
1655 assemble_name (FILE, XSTR (X, 0)); \
1658 /* This is how to store into the string LABEL
1659 the symbol_ref name of an internal numbered label where
1660 PREFIX is the class of label and NUM is the number within the class.
1661 This is suitable for output with `assemble_name'. */
1663 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1664 sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
1666 /* Output the definition of a compiler-generated label named NAME. */
1668 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,NAME) \
1670 assemble_name_raw ((FILE), (NAME)); \
1672 fputs (":\n", (FILE)); \
1674 fputc ('\n', (FILE)); \
1677 #define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
1679 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1680 output_ascii ((FILE), (P), (SIZE))
1682 /* Jump tables are always placed in the text section. Technically, it
1683 is possible to put them in the readonly data section when -mbig-switch
1684 is specified. This has the benefit of getting the table out of .text
1685 and reducing branch lengths as a result. The downside is that an
1686 additional insn (addil) is needed to access the table when generating
1687 PIC code. The address difference table also has to use 32-bit
1688 pc-relative relocations. Currently, GAS does not support these
1689 relocations, although it is easily modified to do this operation.
1690 The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
1691 when using ELF GAS. A simple difference can be used when using
1692 SOM GAS or the HP assembler. The final downside is GDB complains
1693 about the nesting of the label for the table when debugging. */
1695 #define JUMP_TABLES_IN_TEXT_SECTION 1
1697 /* This is how to output an element of a case-vector that is absolute. */
1699 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1700 if (TARGET_BIG_SWITCH) \
1701 fprintf (FILE, "\t.word L$%04d\n", VALUE); \
1703 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1705 /* This is how to output an element of a case-vector that is relative.
1706 Since we always place jump tables in the text section, the difference
1707 is absolute and requires no relocation. */
1709 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1710 if (TARGET_BIG_SWITCH) \
1711 fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL); \
1713 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1715 /* This is how to output an assembler line that says to advance the
1716 location counter to a multiple of 2**LOG bytes. */
1718 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1719 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1721 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1722 fprintf (FILE, "\t.blockz "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1723 (unsigned HOST_WIDE_INT)(SIZE))
1725 /* This says how to output an assembler line to define an uninitialized
1726 global variable with size SIZE (in bytes) and alignment ALIGN (in bits).
1727 This macro exists to properly support languages like C++ which do not
1728 have common data. */
1730 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1731 pa_asm_output_aligned_bss (FILE, NAME, SIZE, ALIGN)
1733 /* This says how to output an assembler line to define a global common symbol
1734 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1736 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1737 pa_asm_output_aligned_common (FILE, NAME, SIZE, ALIGN)
1739 /* This says how to output an assembler line to define a local common symbol
1740 with size SIZE (in bytes) and alignment ALIGN (in bits). This macro
1741 controls how the assembler definitions of uninitialized static variables
1744 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1745 pa_asm_output_aligned_local (FILE, NAME, SIZE, ALIGN)
1747 /* All HP assemblers use "!" to separate logical lines. */
1748 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '!')
1750 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1751 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1753 /* Print operand X (an rtx) in assembler syntax to file FILE.
1754 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1755 For `%' followed by punctuation, CODE is the punctuation and X is null.
1757 On the HP-PA, the CODE can be `r', meaning this is a register-only operand
1758 and an immediate zero should be represented as `r0'.
1760 Several % codes are defined:
1762 C compare conditions
1763 N extract conditions
1764 M modifier to handle preincrement addressing for memory refs.
1765 F modifier to handle preincrement addressing for fp memory refs */
1767 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1770 /* Print a memory address as an operand to reference that memory location. */
1772 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1773 { rtx addr = ADDR; \
1774 switch (GET_CODE (addr)) \
1777 fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
1780 gcc_assert (GET_CODE (XEXP (addr, 1)) == CONST_INT); \
1781 fprintf (FILE, "%d(%s)", (int)INTVAL (XEXP (addr, 1)), \
1782 reg_names [REGNO (XEXP (addr, 0))]); \
1785 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
1786 fputs ("R'", FILE); \
1787 else if (flag_pic == 0) \
1788 fputs ("RR'", FILE); \
1790 fputs ("RT'", FILE); \
1791 output_global_address (FILE, XEXP (addr, 1), 0); \
1792 fputs ("(", FILE); \
1793 output_operand (XEXP (addr, 0), 0); \
1794 fputs (")", FILE); \
1797 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC "(%%r0)", INTVAL (addr)); \
1800 output_addr_const (FILE, addr); \
1804 /* Find the return address associated with the frame given by
1806 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
1807 (return_addr_rtx (COUNT, FRAMEADDR))
1809 /* Used to mask out junk bits from the return address, such as
1810 processor state, interrupt status, condition codes and the like. */
1811 #define MASK_RETURN_ADDR \
1812 /* The privilege level is in the two low order bits, mask em out \
1813 of the return address. */ \
1816 /* The number of Pmode words for the setjmp buffer. */
1817 #define JMP_BUF_SIZE 50
1819 /* We need a libcall to canonicalize function pointers on TARGET_ELF32. */
1820 #define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \
1821 "__canonicalize_funcptr_for_compare"
1824 #undef TARGET_HAVE_TLS
1825 #define TARGET_HAVE_TLS true
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