1 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
6 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
7 Software Science at the University of Utah.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING3. If not see
23 <http://www.gnu.org/licenses/>. */
25 /* For long call handling. */
26 extern unsigned long total_code_bytes;
28 #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
30 /* Print subsidiary information on the compiler version in use. */
32 #define TARGET_VERSION fputs (" (hppa)", stderr);
34 #define TARGET_PA_10 (!TARGET_PA_11 && !TARGET_PA_20)
36 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
38 #define TARGET_64BIT 0
41 /* Generate code for ELF32 ABI. */
43 #define TARGET_ELF32 0
46 /* Generate code for SOM 32bit ABI. */
51 /* HP-UX UNIX features. */
56 /* HP-UX 10.10 UNIX 95 features. */
57 #ifndef TARGET_HPUX_10_10
58 #define TARGET_HPUX_10_10 0
61 /* HP-UX 11.* features (11.00, 11.11, 11.23, etc.) */
62 #ifndef TARGET_HPUX_11
63 #define TARGET_HPUX_11 0
66 /* HP-UX 11i multibyte and UNIX 98 extensions. */
67 #ifndef TARGET_HPUX_11_11
68 #define TARGET_HPUX_11_11 0
71 /* HP-UX long double library. */
72 #ifndef HPUX_LONG_DOUBLE_LIBRARY
73 #define HPUX_LONG_DOUBLE_LIBRARY 0
76 /* The following three defines are potential target switches. The current
77 defines are optimal given the current capabilities of GAS and GNU ld. */
79 /* Define to a C expression evaluating to true to use long absolute calls.
80 Currently, only the HP assembler and SOM linker support long absolute
81 calls. They are used only in non-pic code. */
82 #define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS)
84 /* Define to a C expression evaluating to true to use long PIC symbol
85 difference calls. Long PIC symbol difference calls are only used with
86 the HP assembler and linker. The HP assembler detects this instruction
87 sequence and treats it as long pc-relative call. Currently, GAS only
88 allows a difference of two symbols in the same subspace, and it doesn't
89 detect the sequence as a pc-relative call. */
90 #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS && TARGET_HPUX)
92 /* Define to a C expression evaluating to true to use long PIC
93 pc-relative calls. Long PIC pc-relative calls are only used with
94 GAS. Currently, they are usable for calls which bind local to a
95 module but not for external calls. */
96 #define TARGET_LONG_PIC_PCREL_CALL 0
98 /* Define to a C expression evaluating to true to use SOM secondary
99 definition symbols for weak support. Linker support for secondary
100 definition symbols is buggy prior to HP-UX 11.X. */
101 #define TARGET_SOM_SDEF 0
103 /* Define to a C expression evaluating to true to save the entry value
104 of SP in the current frame marker. This is normally unnecessary.
105 However, the HP-UX unwind library looks at the SAVE_SP callinfo flag.
106 HP compilers don't use this flag but it is supported by the assembler.
107 We set this flag to indicate that register %r3 has been saved at the
108 start of the frame. Thus, when the HP unwind library is used, we
109 need to generate additional code to save SP into the frame marker. */
110 #define TARGET_HPUX_UNWIND_LIBRARY 0
112 #ifndef TARGET_DEFAULT
113 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
116 #ifndef TARGET_CPU_DEFAULT
117 #define TARGET_CPU_DEFAULT 0
120 #ifndef TARGET_SCHED_DEFAULT
121 #define TARGET_SCHED_DEFAULT PROCESSOR_8000
124 /* Support for a compile-time default CPU, et cetera. The rules are:
125 --with-schedule is ignored if -mschedule is specified.
126 --with-arch is ignored if -march is specified. */
127 #define OPTION_DEFAULT_SPECS \
128 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
129 {"schedule", "%{!mschedule=*:-mschedule=%(VALUE)}" }
131 /* Specify the dialect of assembler to use. New mnemonics is dialect one
132 and the old mnemonics are dialect zero. */
133 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
135 /* Override some settings from dbxelf.h. */
137 /* We do not have to be compatible with dbx, so we enable gdb extensions
139 #define DEFAULT_GDB_EXTENSIONS 1
141 /* This used to be zero (no max length), but big enums and such can
142 cause huge strings which killed gas.
144 We also have to avoid lossage in dbxout.c -- it does not compute the
145 string size accurately, so we are real conservative here. */
146 #undef DBX_CONTIN_LENGTH
147 #define DBX_CONTIN_LENGTH 3000
149 /* GDB always assumes the current function's frame begins at the value
150 of the stack pointer upon entry to the current function. Accessing
151 local variables and parameters passed on the stack is done using the
152 base of the frame + an offset provided by GCC.
154 For functions which have frame pointers this method works fine;
155 the (frame pointer) == (stack pointer at function entry) and GCC provides
156 an offset relative to the frame pointer.
158 This loses for functions without a frame pointer; GCC provides an offset
159 which is relative to the stack pointer after adjusting for the function's
160 frame size. GDB would prefer the offset to be relative to the value of
161 the stack pointer at the function's entry. Yuk! */
162 #define DEBUGGER_AUTO_OFFSET(X) \
163 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
164 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
166 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
167 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
168 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
170 #define TARGET_CPU_CPP_BUILTINS() \
172 builtin_assert("cpu=hppa"); \
173 builtin_assert("machine=hppa"); \
174 builtin_define("__hppa"); \
175 builtin_define("__hppa__"); \
177 builtin_define("_PA_RISC2_0"); \
178 else if (TARGET_PA_11) \
179 builtin_define("_PA_RISC1_1"); \
181 builtin_define("_PA_RISC1_0"); \
184 /* An old set of OS defines for various BSD-like systems. */
185 #define TARGET_OS_CPP_BUILTINS() \
188 builtin_define_std ("REVARGV"); \
189 builtin_define_std ("hp800"); \
190 builtin_define_std ("hp9000"); \
191 builtin_define_std ("hp9k8"); \
192 if (!c_dialect_cxx () && !flag_iso) \
193 builtin_define ("hppa"); \
194 builtin_define_std ("spectrum"); \
195 builtin_define_std ("unix"); \
196 builtin_assert ("system=bsd"); \
197 builtin_assert ("system=unix"); \
201 #define CC1_SPEC "%{pg:} %{p:}"
203 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
205 /* We don't want -lg. */
207 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
210 /* Make gcc agree with <machine/ansi.h> */
212 #define SIZE_TYPE "unsigned int"
213 #define PTRDIFF_TYPE "int"
214 #define WCHAR_TYPE "unsigned int"
215 #define WCHAR_TYPE_SIZE 32
217 /* target machine storage layout */
218 typedef struct GTY(()) machine_function
220 /* Flag indicating that a .NSUBSPA directive has been output for
225 /* Define this macro if it is advisable to hold scalars in registers
226 in a wider mode than that declared by the program. In such cases,
227 the value is constrained to be within the bounds of the declared
228 type, but kept valid in the wider mode. The signedness of the
229 extension may differ from that of the type. */
231 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
232 if (GET_MODE_CLASS (MODE) == MODE_INT \
233 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
236 /* Define this if most significant bit is lowest numbered
237 in instructions that operate on numbered bit-fields. */
238 #define BITS_BIG_ENDIAN 1
240 /* Define this if most significant byte of a word is the lowest numbered. */
241 /* That is true on the HP-PA. */
242 #define BYTES_BIG_ENDIAN 1
244 /* Define this if most significant word of a multiword number is lowest
246 #define WORDS_BIG_ENDIAN 1
248 #define MAX_BITS_PER_WORD 64
250 /* Width of a word, in units (bytes). */
251 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
253 /* Minimum number of units in a word. If this is undefined, the default
254 is UNITS_PER_WORD. Otherwise, it is the constant value that is the
255 smallest value that UNITS_PER_WORD can have at run-time.
257 FIXME: This needs to be 4 when TARGET_64BIT is true to suppress the
258 building of various TImode routines in libgcc. The HP runtime
259 specification doesn't provide the alignment requirements and calling
260 conventions for TImode variables. */
261 #define MIN_UNITS_PER_WORD 4
263 /* The widest floating point format supported by the hardware. Note that
264 setting this influences some Ada floating point type sizes, currently
265 required for GNAT to operate properly. */
266 #define WIDEST_HARDWARE_FP_SIZE 64
268 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
269 #define PARM_BOUNDARY BITS_PER_WORD
271 /* Largest alignment required for any stack parameter, in bits.
272 Don't define this if it is equal to PARM_BOUNDARY */
273 #define MAX_PARM_BOUNDARY BIGGEST_ALIGNMENT
275 /* Boundary (in *bits*) on which stack pointer is always aligned;
276 certain optimizations in combine depend on this.
278 The HP-UX runtime documents mandate 64-byte and 16-byte alignment for
279 the stack on the 32 and 64-bit ports, respectively. However, we
280 are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT
281 in main. Thus, we treat the former as the preferred alignment. */
282 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
283 #define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512)
285 /* Allocation boundary (in *bits*) for the code of a function. */
286 #define FUNCTION_BOUNDARY BITS_PER_WORD
288 /* Alignment of field after `int : 0' in a structure. */
289 #define EMPTY_FIELD_BOUNDARY 32
291 /* Every structure's size must be a multiple of this. */
292 #define STRUCTURE_SIZE_BOUNDARY 8
294 /* A bit-field declared as `int' forces `int' alignment for the struct. */
295 #define PCC_BITFIELD_TYPE_MATTERS 1
297 /* No data type wants to be aligned rounder than this. */
298 #define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD)
300 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
301 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
302 (TREE_CODE (EXP) == STRING_CST \
303 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
305 /* Make arrays of chars word-aligned for the same reasons. */
306 #define DATA_ALIGNMENT(TYPE, ALIGN) \
307 (TREE_CODE (TYPE) == ARRAY_TYPE \
308 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
309 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
311 /* Set this nonzero if move instructions will actually fail to work
312 when given unaligned data. */
313 #define STRICT_ALIGNMENT 1
315 /* Value is 1 if it is a good idea to tie two pseudo registers
316 when one has mode MODE1 and one has mode MODE2.
317 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
318 for any hard reg, then this must be 0 for correct output. */
319 #define MODES_TIEABLE_P(MODE1, MODE2) \
320 pa_modes_tieable_p (MODE1, MODE2)
322 /* Specify the registers used for certain standard purposes.
323 The values of these macros are register numbers. */
325 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
326 /* #define PC_REGNUM */
328 /* Register to use for pushing function arguments. */
329 #define STACK_POINTER_REGNUM 30
331 /* Fixed register for local variable access. Always eliminated. */
332 #define FRAME_POINTER_REGNUM (TARGET_64BIT ? 61 : 89)
334 /* Base register for access to local variables of the function. */
335 #define HARD_FRAME_POINTER_REGNUM 3
337 /* Don't allow hard registers to be renamed into r2 unless r2
338 is already live or already being saved (due to eh). */
340 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
341 ((NEW_REG) != 2 || df_regs_ever_live_p (2) || crtl->calls_eh_return)
343 /* Base register for access to arguments of the function. */
344 #define ARG_POINTER_REGNUM (TARGET_64BIT ? 29 : 3)
346 /* Register in which static-chain is passed to a function. */
347 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? 31 : 29)
349 /* Register used to address the offset table for position-independent
351 #define PIC_OFFSET_TABLE_REGNUM \
352 (flag_pic ? (TARGET_64BIT ? 27 : 19) : INVALID_REGNUM)
354 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
356 /* Function to return the rtx used to save the pic offset table register
357 across function calls. */
358 extern struct rtx_def *hppa_pic_save_rtx (void);
360 #define DEFAULT_PCC_STRUCT_RETURN 0
362 /* Register in which address to store a structure value
363 is passed to a function. */
364 #define PA_STRUCT_VALUE_REGNUM 28
366 /* Definitions for register eliminations.
368 We have two registers that can be eliminated. First, the frame pointer
369 register can often be eliminated in favor of the stack pointer register.
370 Secondly, the argument pointer register can always be eliminated in the
373 /* This is an array of structures. Each structure initializes one pair
374 of eliminable registers. The "from" register number is given first,
375 followed by "to". Eliminations of the same "from" register are listed
376 in order of preference.
378 The argument pointer cannot be eliminated in the 64-bit runtime. It
379 is the same register as the hard frame pointer in the 32-bit runtime.
380 So, it does not need to be listed. */
381 #define ELIMINABLE_REGS \
382 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
383 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
384 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
386 /* Define the offset between two registers, one to be eliminated,
387 and the other its replacement, at the start of a routine. */
388 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
389 ((OFFSET) = pa_initial_elimination_offset(FROM, TO))
391 /* Describe how we implement __builtin_eh_return. */
392 #define EH_RETURN_DATA_REGNO(N) \
393 ((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM)
394 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
395 #define EH_RETURN_HANDLER_RTX pa_eh_return_handler_rtx ()
397 /* Offset from the frame pointer register value to the top of stack. */
398 #define FRAME_POINTER_CFA_OFFSET(FNDECL) 0
400 /* The maximum number of hard registers that can be saved in the call
401 frame. The soft frame pointer is not included. */
402 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
404 /* A C expression whose value is RTL representing the location of the
405 incoming return address at the beginning of any function, before the
406 prologue. You only need to define this macro if you want to support
407 call frame debugging information like that provided by DWARF 2. */
408 #define INCOMING_RETURN_ADDR_RTX (gen_rtx_REG (word_mode, 2))
409 #define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (2))
411 /* A C expression whose value is an integer giving a DWARF 2 column
412 number that may be used as an alternate return column. This should
413 be defined only if DWARF_FRAME_RETURN_COLUMN is set to a general
414 register, but an alternate column needs to be used for signal frames.
416 Column 0 is not used but unfortunately its register size is set to
417 4 bytes (sizeof CCmode) so it can't be used on 64-bit targets. */
418 #define DWARF_ALT_FRAME_RETURN_COLUMN (FIRST_PSEUDO_REGISTER - 1)
420 /* This macro chooses the encoding of pointers embedded in the exception
421 handling sections. If at all possible, this should be defined such
422 that the exception handling section will not require dynamic relocations,
423 and so may be read-only.
425 Because the HP assembler auto aligns, it is necessary to use
426 DW_EH_PE_aligned. It's not possible to make the data read-only
427 on the HP-UX SOM port since the linker requires fixups for label
428 differences in different sections to be word aligned. However,
429 the SOM linker can do unaligned fixups for absolute pointers.
430 We also need aligned pointers for global and function pointers.
432 Although the HP-UX 64-bit ELF linker can handle unaligned pc-relative
433 fixups, the runtime doesn't have a consistent relationship between
434 text and data for dynamically loaded objects. Thus, it's not possible
435 to use pc-relative encoding for pointers on this target. It may be
436 possible to use segment relative encodings but GAS doesn't currently
437 have a mechanism to generate these encodings. For other targets, we
438 use pc-relative encoding for pointers. If the pointer might require
439 dynamic relocation, we make it indirect. */
440 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
441 (TARGET_GAS && !TARGET_HPUX \
443 | ((GLOBAL) || (CODE) == 2 ? DW_EH_PE_indirect : 0) \
444 | (TARGET_64BIT ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)) \
445 : (!TARGET_GAS || (GLOBAL) || (CODE) == 2 \
446 ? DW_EH_PE_aligned : DW_EH_PE_absptr))
448 /* Handle special EH pointer encodings. Absolute, pc-relative, and
449 indirect are handled automatically. We output pc-relative, and
450 indirect pc-relative ourself since we need some special magic to
451 generate pc-relative relocations, and to handle indirect function
453 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
455 if (((ENCODING) & 0x70) == DW_EH_PE_pcrel) \
457 fputs (integer_asm_op (SIZE, FALSE), FILE); \
458 if ((ENCODING) & DW_EH_PE_indirect) \
459 output_addr_const (FILE, get_deferred_plabel (ADDR)); \
461 assemble_name (FILE, XSTR ((ADDR), 0)); \
462 fputs ("+8-$PIC_pcrel$0", FILE); \
468 /* The class value for index registers, and the one for base regs. */
469 #define INDEX_REG_CLASS GENERAL_REGS
470 #define BASE_REG_CLASS GENERAL_REGS
472 #define FP_REG_CLASS_P(CLASS) \
473 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
475 /* True if register is floating-point. */
476 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
478 #define MAYBE_FP_REG_CLASS_P(CLASS) \
479 reg_classes_intersect_p ((CLASS), FP_REGS)
482 /* Stack layout; function entry, exit and calling. */
484 /* Define this if pushing a word on the stack
485 makes the stack pointer a smaller address. */
486 /* #define STACK_GROWS_DOWNWARD */
488 /* Believe it or not. */
489 #define ARGS_GROW_DOWNWARD
491 /* Define this to nonzero if the nominal address of the stack frame
492 is at the high-address end of the local variables;
493 that is, each additional local variable allocated
494 goes at a more negative offset in the frame. */
495 #define FRAME_GROWS_DOWNWARD 0
497 /* Offset within stack frame to start allocating local variables at.
498 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
499 first local allocated. Otherwise, it is the offset to the BEGINNING
500 of the first local allocated.
502 On the 32-bit ports, we reserve one slot for the previous frame
503 pointer and one fill slot. The fill slot is for compatibility
504 with HP compiled programs. On the 64-bit ports, we reserve one
505 slot for the previous frame pointer. */
506 #define STARTING_FRAME_OFFSET 8
508 /* Define STACK_ALIGNMENT_NEEDED to zero to disable final alignment
509 of the stack. The default is to align it to STACK_BOUNDARY. */
510 #define STACK_ALIGNMENT_NEEDED 0
512 /* If we generate an insn to push BYTES bytes,
513 this says how many the stack pointer really advances by.
514 On the HP-PA, don't define this because there are no push insns. */
515 /* #define PUSH_ROUNDING(BYTES) */
517 /* Offset of first parameter from the argument pointer register value.
518 This value will be negated because the arguments grow down.
519 Also note that on STACK_GROWS_UPWARD machines (such as this one)
520 this is the distance from the frame pointer to the end of the first
521 argument, not it's beginning. To get the real offset of the first
522 argument, the size of the argument must be added. */
524 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
526 /* When a parameter is passed in a register, stack space is still
528 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
530 /* Define this if the above stack space is to be considered part of the
531 space allocated by the caller. */
532 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
534 /* Keep the stack pointer constant throughout the function.
535 This is both an optimization and a necessity: longjmp
536 doesn't behave itself when the stack pointer moves within
538 #define ACCUMULATE_OUTGOING_ARGS 1
540 /* The weird HPPA calling conventions require a minimum of 48 bytes on
541 the stack: 16 bytes for register saves, and 32 bytes for magic.
542 This is the difference between the logical top of stack and the
545 On the 64-bit port, the HP C compiler allocates a 48-byte frame
546 marker, although the runtime documentation only describes a 16
547 byte marker. For compatibility, we allocate 48 bytes. */
548 #define STACK_POINTER_OFFSET \
549 (TARGET_64BIT ? -(crtl->outgoing_args_size + 48): -32)
551 #define STACK_DYNAMIC_OFFSET(FNDECL) \
553 ? (STACK_POINTER_OFFSET) \
554 : ((STACK_POINTER_OFFSET) - crtl->outgoing_args_size))
557 /* Define a data type for recording info about an argument list
558 during the scan of that argument list. This data type should
559 hold all necessary information about the function itself
560 and about the args processed so far, enough to enable macros
561 such as FUNCTION_ARG to determine where the next arg should go.
563 On the HP-PA, the WORDS field holds the number of words
564 of arguments scanned so far (including the invisible argument,
565 if any, which holds the structure-value-address). Thus, 4 or
566 more means all following args should go on the stack.
568 The INCOMING field tracks whether this is an "incoming" or
571 The INDIRECT field indicates whether this is is an indirect
574 The NARGS_PROTOTYPE field indicates that an argument does not
575 have a prototype when it less than or equal to 0. */
577 struct hppa_args {int words, nargs_prototype, incoming, indirect; };
579 #define CUMULATIVE_ARGS struct hppa_args
581 /* Initialize a variable CUM of type CUMULATIVE_ARGS
582 for a call to a function whose data type is FNTYPE.
583 For a library call, FNTYPE is 0. */
585 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
587 (CUM).incoming = 0, \
588 (CUM).indirect = (FNTYPE) && !(FNDECL), \
589 (CUM).nargs_prototype = (FNTYPE && prototype_p (FNTYPE) \
590 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
591 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
592 || pa_return_in_memory (TREE_TYPE (FNTYPE), 0))) \
597 /* Similar, but when scanning the definition of a procedure. We always
598 set NARGS_PROTOTYPE large so we never return a PARALLEL. */
600 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
602 (CUM).incoming = 1, \
603 (CUM).indirect = 0, \
604 (CUM).nargs_prototype = 1000
606 /* Figure out the size in words of the function argument. The size
607 returned by this macro should always be greater than zero because
608 we pass variable and zero sized objects by reference. */
610 #define FUNCTION_ARG_SIZE(MODE, TYPE) \
611 ((((MODE) != BLKmode \
612 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
613 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
615 /* Determine where to put an argument to a function.
616 Value is zero to push the argument on the stack,
617 or a hard register in which to store the argument.
619 MODE is the argument's machine mode.
620 TYPE is the data type of the argument (as a tree).
621 This is null for libcalls where that information may
623 CUM is a variable of type CUMULATIVE_ARGS which gives info about
624 the preceding args and about the function being called.
625 NAMED is nonzero if this argument is a named parameter
626 (otherwise it is an extra parameter matching an ellipsis).
628 On the HP-PA the first four words of args are normally in registers
629 and the rest are pushed. But any arg that won't entirely fit in regs
632 Arguments passed in registers are either 1 or 2 words long.
634 The caller must make a distinction between calls to explicitly named
635 functions and calls through pointers to functions -- the conventions
636 are different! Calls through pointers to functions only use general
637 registers for the first four argument words.
639 Of course all this is different for the portable runtime model
640 HP wants everyone to use for ELF. Ugh. Here's a quick description
641 of how it's supposed to work.
643 1) callee side remains unchanged. It expects integer args to be
644 in the integer registers, float args in the float registers and
645 unnamed args in integer registers.
647 2) caller side now depends on if the function being called has
648 a prototype in scope (rather than if it's being called indirectly).
650 2a) If there is a prototype in scope, then arguments are passed
651 according to their type (ints in integer registers, floats in float
652 registers, unnamed args in integer registers.
654 2b) If there is no prototype in scope, then floating point arguments
655 are passed in both integer and float registers. egad.
657 FYI: The portable parameter passing conventions are almost exactly like
658 the standard parameter passing conventions on the RS6000. That's why
659 you'll see lots of similar code in rs6000.h. */
661 /* If defined, a C expression which determines whether, and in which
662 direction, to pad out an argument with extra space. */
663 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
665 /* Specify padding for the last element of a block move between registers
668 The 64-bit runtime specifies that objects need to be left justified
669 (i.e., the normal justification for a big endian target). The 32-bit
670 runtime specifies right justification for objects smaller than 64 bits.
671 We use a DImode register in the parallel for 5 to 7 byte structures
672 so that there is only one element. This allows the object to be
674 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
675 function_arg_padding ((MODE), (TYPE))
678 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
679 as assembly via FUNCTION_PROFILER. Just output a local label.
680 We can't use the function label because the GAS SOM target can't
681 handle the difference of a global symbol and a local symbol. */
683 #ifndef FUNC_BEGIN_PROLOG_LABEL
684 #define FUNC_BEGIN_PROLOG_LABEL "LFBP"
687 #define FUNCTION_PROFILER(FILE, LABEL) \
688 (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
690 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
691 void hppa_profile_hook (int label_no);
693 /* The profile counter if emitted must come before the prologue. */
694 #define PROFILE_BEFORE_PROLOGUE 1
696 /* We never want final.c to emit profile counters. When profile
697 counters are required, we have to defer emitting them to the end
698 of the current file. */
699 #define NO_PROFILE_COUNTERS 1
701 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
702 the stack pointer does not matter. The value is tested only in
703 functions that have frame pointers.
704 No definition is equivalent to always zero. */
706 extern int may_call_alloca;
708 #define EXIT_IGNORE_STACK \
709 (get_frame_size () != 0 \
710 || cfun->calls_alloca || crtl->outgoing_args_size)
712 /* Length in units of the trampoline for entering a nested function. */
714 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
716 /* Alignment required by the trampoline. */
718 #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD
720 /* Minimum length of a cache line. A length of 16 will work on all
721 PA-RISC processors. All PA 1.1 processors have a cache line of
722 32 bytes. Most but not all PA 2.0 processors have a cache line
723 of 64 bytes. As cache flushes are expensive and we don't support
724 PA 1.0, we use a minimum length of 32. */
726 #define MIN_CACHELINE_SIZE 32
729 /* Addressing modes, and classification of registers for them.
731 Using autoincrement addressing modes on PA8000 class machines is
734 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
735 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
737 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
738 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
740 /* Macros to check register numbers against specific register classes. */
742 /* The following macros assume that X is a hard or pseudo reg number.
743 They give nonzero only if X is a hard reg of the suitable class
744 or a pseudo reg currently allocated to a suitable hard reg.
745 Since they use reg_renumber, they are safe only once reg_renumber
746 has been allocated, which happens in local-alloc.c. */
748 #define REGNO_OK_FOR_INDEX_P(X) \
750 || ((X) == FRAME_POINTER_REGNUM) \
751 || ((X) >= FIRST_PSEUDO_REGISTER \
753 && (unsigned) reg_renumber[X] < 32)))
754 #define REGNO_OK_FOR_BASE_P(X) \
756 || ((X) == FRAME_POINTER_REGNUM) \
757 || ((X) >= FIRST_PSEUDO_REGISTER \
759 && (unsigned) reg_renumber[X] < 32)))
760 #define REGNO_OK_FOR_FP_P(X) \
762 || (X >= FIRST_PSEUDO_REGISTER \
764 && FP_REGNO_P (reg_renumber[X])))
766 /* Now macros that check whether X is a register and also,
767 strictly, whether it is in a specified class.
769 These macros are specific to the HP-PA, and may be used only
770 in code for printing assembler insns and in conditions for
771 define_optimization. */
773 /* 1 if X is an fp register. */
775 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
777 /* Maximum number of registers that can appear in a valid memory address. */
779 #define MAX_REGS_PER_ADDRESS 2
781 /* Non-TLS symbolic references. */
782 #define PA_SYMBOL_REF_TLS_P(RTX) \
783 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
785 /* Recognize any constant value that is a valid address except
786 for symbolic addresses. We get better CSE by rejecting them
787 here and allowing hppa_legitimize_address to break them up. We
788 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
790 #define CONSTANT_ADDRESS_P(X) \
791 ((GET_CODE (X) == LABEL_REF \
792 || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
793 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
794 || GET_CODE (X) == HIGH) \
795 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
797 /* A C expression that is nonzero if we are using the new HP assembler. */
799 #ifndef NEW_HP_ASSEMBLER
800 #define NEW_HP_ASSEMBLER 0
803 /* The macros below define the immediate range for CONST_INTS on
804 the 64-bit port. Constants in this range can be loaded in three
805 instructions using a ldil/ldo/depdi sequence. Constants outside
806 this range are forced to the constant pool prior to reload. */
808 #define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
809 #define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31)
810 #define LEGITIMATE_64BIT_CONST_INT_P(X) \
811 ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)
813 /* A C expression that is nonzero if X is a legitimate constant for an
816 We include all constant integers and constant doubles, but not
817 floating-point, except for floating-point zero. We reject LABEL_REFs
818 if we're not using gas or the new HP assembler.
820 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
821 that need more than three instructions to load prior to reload. This
822 limit is somewhat arbitrary. It takes three instructions to load a
823 CONST_INT from memory but two are memory accesses. It may be better
824 to increase the allowed range for CONST_INTS. We may also be able
825 to handle CONST_DOUBLES. */
827 #define LEGITIMATE_CONSTANT_P(X) \
828 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
829 || (X) == CONST0_RTX (GET_MODE (X))) \
830 && (NEW_HP_ASSEMBLER \
832 || GET_CODE (X) != LABEL_REF) \
834 || GET_CODE (X) != CONST_DOUBLE) \
836 || HOST_BITS_PER_WIDE_INT <= 32 \
837 || GET_CODE (X) != CONST_INT \
838 || reload_in_progress \
839 || reload_completed \
840 || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X)) \
841 || cint_ok_for_move (INTVAL (X))) \
842 && !function_label_operand (X, VOIDmode))
844 /* Target flags set on a symbol_ref. */
846 /* Set by ASM_OUTPUT_SYMBOL_REF when a symbol_ref is output. */
847 #define SYMBOL_FLAG_REFERENCED (1 << SYMBOL_FLAG_MACH_DEP_SHIFT)
848 #define SYMBOL_REF_REFERENCED_P(RTX) \
849 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_REFERENCED) != 0)
851 /* Defines for constraints.md. */
853 /* Return 1 iff OP is a scaled or unscaled index address. */
854 #define IS_INDEX_ADDR_P(OP) \
855 (GET_CODE (OP) == PLUS \
856 && GET_MODE (OP) == Pmode \
857 && (GET_CODE (XEXP (OP, 0)) == MULT \
858 || GET_CODE (XEXP (OP, 1)) == MULT \
859 || (REG_P (XEXP (OP, 0)) \
860 && REG_P (XEXP (OP, 1)))))
862 /* Return 1 iff OP is a LO_SUM DLT address. */
863 #define IS_LO_SUM_DLT_ADDR_P(OP) \
864 (GET_CODE (OP) == LO_SUM \
865 && GET_MODE (OP) == Pmode \
866 && REG_P (XEXP (OP, 0)) \
867 && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
868 && GET_CODE (XEXP (OP, 1)) == UNSPEC)
870 /* Nonzero if 14-bit offsets can be used for all loads and stores.
871 This is not possible when generating PA 1.x code as floating point
872 loads and stores only support 5-bit offsets. Note that we do not
873 forbid the use of 14-bit offsets in GO_IF_LEGITIMATE_ADDRESS.
874 Instead, we use pa_secondary_reload() to reload integer mode
875 REG+D memory addresses used in floating point loads and stores.
877 FIXME: the ELF32 linker clobbers the LSB of the FP register number
878 in PA 2.0 floating-point insns with long displacements. This is
879 because R_PARISC_DPREL14WR and other relocations like it are not
880 yet supported by GNU ld. For now, we reject long displacements
883 #define INT14_OK_STRICT \
885 || TARGET_DISABLE_FPREGS \
886 || (TARGET_PA_20 && !TARGET_ELF32))
888 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
889 and check its validity for a certain class.
890 We have two alternate definitions for each of them.
891 The usual definition accepts all pseudo regs; the other rejects
892 them unless they have been allocated suitable hard regs.
893 The symbol REG_OK_STRICT causes the latter definition to be used.
895 Most source files want to accept pseudo regs in the hope that
896 they will get allocated to the class that the insn wants them to be in.
897 Source files for reload pass need to be strict.
898 After reload, it makes no difference, since pseudo regs have
899 been eliminated by then. */
901 #ifndef REG_OK_STRICT
903 /* Nonzero if X is a hard reg that can be used as an index
904 or if it is a pseudo reg. */
905 #define REG_OK_FOR_INDEX_P(X) \
906 (REGNO (X) && (REGNO (X) < 32 \
907 || REGNO (X) == FRAME_POINTER_REGNUM \
908 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
910 /* Nonzero if X is a hard reg that can be used as a base reg
911 or if it is a pseudo reg. */
912 #define REG_OK_FOR_BASE_P(X) \
913 (REGNO (X) && (REGNO (X) < 32 \
914 || REGNO (X) == FRAME_POINTER_REGNUM \
915 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
919 /* Nonzero if X is a hard reg that can be used as an index. */
920 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
922 /* Nonzero if X is a hard reg that can be used as a base reg. */
923 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
927 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
928 valid memory address for an instruction. The MODE argument is the
929 machine mode for the MEM expression that wants to use this address.
931 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
932 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
933 available with floating point loads and stores, and integer loads.
934 We get better code by allowing indexed addresses in the initial
937 The acceptance of indexed addresses as legitimate implies that we
938 must provide patterns for doing indexed integer stores, or the move
939 expanders must force the address of an indexed store to a register.
940 We have adopted the latter approach.
942 Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that
943 the base register is a valid pointer for indexed instructions.
944 On targets that have non-equivalent space registers, we have to
945 know at the time of assembler output which register in a REG+REG
946 pair is the base register. The REG_POINTER flag is sometimes lost
947 in reload and the following passes, so it can't be relied on during
948 code generation. Thus, we either have to canonicalize the order
949 of the registers in REG+REG indexed addresses, or treat REG+REG
950 addresses separately and provide patterns for both permutations.
952 The latter approach requires several hundred additional lines of
953 code in pa.md. The downside to canonicalizing is that a PLUS
954 in the wrong order can't combine to form to make a scaled indexed
955 memory operand. As we won't need to canonicalize the operands if
956 the REG_POINTER lossage can be fixed, it seems better canonicalize.
958 We initially break out scaled indexed addresses in canonical order
959 in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
960 scaled indexed addresses during RTL generation. However, fold_rtx
961 has its own opinion on how the operands of a PLUS should be ordered.
962 If one of the operands is equivalent to a constant, it will make
963 that operand the second operand. As the base register is likely to
964 be equivalent to a SYMBOL_REF, we have made it the second operand.
966 GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the
967 operands are in the order INDEX+BASE on targets with non-equivalent
968 space registers, and in any order on targets with equivalent space
969 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
971 We treat a SYMBOL_REF as legitimate if it is part of the current
972 function's constant-pool, because such addresses can actually be
973 output as REG+SMALLINT. */
975 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
976 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
978 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
979 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
981 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
982 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
984 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
985 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
987 #if HOST_BITS_PER_WIDE_INT > 32
988 #define VAL_32_BITS_P(X) \
989 ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \
990 < (unsigned HOST_WIDE_INT) 2 << 31)
992 #define VAL_32_BITS_P(X) 1
994 #define INT_32_BITS(X) VAL_32_BITS_P (INTVAL (X))
996 /* These are the modes that we allow for scaled indexing. */
997 #define MODE_OK_FOR_SCALED_INDEXING_P(MODE) \
998 ((TARGET_64BIT && (MODE) == DImode) \
999 || (MODE) == SImode \
1000 || (MODE) == HImode \
1001 || (MODE) == SFmode \
1002 || (MODE) == DFmode)
1004 /* These are the modes that we allow for unscaled indexing. */
1005 #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \
1006 ((TARGET_64BIT && (MODE) == DImode) \
1007 || (MODE) == SImode \
1008 || (MODE) == HImode \
1009 || (MODE) == QImode \
1010 || (MODE) == SFmode \
1011 || (MODE) == DFmode)
1013 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1015 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1016 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
1017 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
1018 && REG_P (XEXP (X, 0)) \
1019 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
1021 else if (GET_CODE (X) == PLUS) \
1023 rtx base = 0, index = 0; \
1024 if (REG_P (XEXP (X, 1)) \
1025 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1026 base = XEXP (X, 1), index = XEXP (X, 0); \
1027 else if (REG_P (XEXP (X, 0)) \
1028 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1029 base = XEXP (X, 0), index = XEXP (X, 1); \
1031 && GET_CODE (index) == CONST_INT \
1032 && ((INT_14_BITS (index) \
1033 && (((MODE) != DImode \
1034 && (MODE) != SFmode \
1035 && (MODE) != DFmode) \
1036 /* The base register for DImode loads and stores \
1037 with long displacements must be aligned because \
1038 the lower three bits in the displacement are \
1039 assumed to be zero. */ \
1040 || ((MODE) == DImode \
1042 || (INTVAL (index) % 8) == 0)) \
1043 /* Similarly, the base register for SFmode/DFmode \
1044 loads and stores with long displacements must \
1046 || (((MODE) == SFmode || (MODE) == DFmode) \
1047 && INT14_OK_STRICT \
1048 && (INTVAL (index) % GET_MODE_SIZE (MODE)) == 0))) \
1049 || INT_5_BITS (index))) \
1051 if (!TARGET_DISABLE_INDEXING \
1052 /* Only accept the "canonical" INDEX+BASE operand order \
1053 on targets with non-equivalent space registers. */ \
1054 && (TARGET_NO_SPACE_REGS \
1055 ? (base && REG_P (index)) \
1056 : (base == XEXP (X, 1) && REG_P (index) \
1057 && (reload_completed \
1058 || (reload_in_progress && HARD_REGISTER_P (base)) \
1059 || REG_POINTER (base)) \
1060 && (reload_completed \
1061 || (reload_in_progress && HARD_REGISTER_P (index)) \
1062 || !REG_POINTER (index)))) \
1063 && MODE_OK_FOR_UNSCALED_INDEXING_P (MODE) \
1064 && REG_OK_FOR_INDEX_P (index) \
1065 && borx_reg_operand (base, Pmode) \
1066 && borx_reg_operand (index, Pmode)) \
1068 if (!TARGET_DISABLE_INDEXING \
1070 && GET_CODE (index) == MULT \
1071 && MODE_OK_FOR_SCALED_INDEXING_P (MODE) \
1072 && REG_P (XEXP (index, 0)) \
1073 && GET_MODE (XEXP (index, 0)) == Pmode \
1074 && REG_OK_FOR_INDEX_P (XEXP (index, 0)) \
1075 && GET_CODE (XEXP (index, 1)) == CONST_INT \
1076 && INTVAL (XEXP (index, 1)) \
1077 == (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
1078 && borx_reg_operand (base, Pmode)) \
1081 else if (GET_CODE (X) == LO_SUM \
1082 && GET_CODE (XEXP (X, 0)) == REG \
1083 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1084 && CONSTANT_P (XEXP (X, 1)) \
1085 && (TARGET_SOFT_FLOAT \
1086 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1089 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1090 || ((MODE) != SFmode \
1091 && (MODE) != DFmode))) \
1093 else if (GET_CODE (X) == LO_SUM \
1094 && GET_CODE (XEXP (X, 0)) == SUBREG \
1095 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG \
1096 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0))) \
1097 && CONSTANT_P (XEXP (X, 1)) \
1098 && (TARGET_SOFT_FLOAT \
1099 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1102 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1103 || ((MODE) != SFmode \
1104 && (MODE) != DFmode))) \
1106 else if (GET_CODE (X) == CONST_INT && INT_5_BITS (X)) \
1108 /* Needed for -fPIC */ \
1109 else if (GET_CODE (X) == LO_SUM \
1110 && GET_CODE (XEXP (X, 0)) == REG \
1111 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1112 && GET_CODE (XEXP (X, 1)) == UNSPEC \
1113 && (TARGET_SOFT_FLOAT \
1114 || (TARGET_PA_20 && !TARGET_ELF32) \
1115 || ((MODE) != SFmode \
1116 && (MODE) != DFmode))) \
1120 /* Look for machine dependent ways to make the invalid address AD a
1123 For the PA, transform:
1125 memory(X + <large int>)
1129 if (<large int> & mask) >= 16
1130 Y = (<large int> & ~mask) + mask + 1 Round up.
1132 Y = (<large int> & ~mask) Round down.
1134 memory (Z + (<large int> - Y));
1136 This makes reload inheritance and reload_cse work better since Z
1139 There may be more opportunities to improve code with this hook. */
1140 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
1142 long offset, newoffset, mask; \
1143 rtx new_rtx, temp = NULL_RTX; \
1145 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1146 ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff); \
1148 if (optimize && GET_CODE (AD) == PLUS) \
1149 temp = simplify_binary_operation (PLUS, Pmode, \
1150 XEXP (AD, 0), XEXP (AD, 1)); \
1152 new_rtx = temp ? temp : AD; \
1155 && GET_CODE (new_rtx) == PLUS \
1156 && GET_CODE (XEXP (new_rtx, 0)) == REG \
1157 && GET_CODE (XEXP (new_rtx, 1)) == CONST_INT) \
1159 offset = INTVAL (XEXP ((new_rtx), 1)); \
1161 /* Choose rounding direction. Round up if we are >= halfway. */ \
1162 if ((offset & mask) >= ((mask + 1) / 2)) \
1163 newoffset = (offset & ~mask) + mask + 1; \
1165 newoffset = offset & ~mask; \
1167 /* Ensure that long displacements are aligned. */ \
1168 if (mask == 0x3fff \
1169 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1170 || (TARGET_64BIT && (MODE) == DImode))) \
1171 newoffset &= ~(GET_MODE_SIZE (MODE) - 1); \
1173 if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \
1175 temp = gen_rtx_PLUS (Pmode, XEXP (new_rtx, 0), \
1176 GEN_INT (newoffset)); \
1177 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
1178 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
1179 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
1188 #define TARGET_ASM_SELECT_SECTION pa_select_section
1190 /* Return a nonzero value if DECL has a section attribute. */
1191 #define IN_NAMED_SECTION_P(DECL) \
1192 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
1193 && DECL_SECTION_NAME (DECL) != NULL_TREE)
1195 /* Define this macro if references to a symbol must be treated
1196 differently depending on something about the variable or
1197 function named by the symbol (such as what section it is in).
1199 The macro definition, if any, is executed immediately after the
1200 rtl for DECL or other node is created.
1201 The value of the rtl will be a `mem' whose address is a
1204 The usual thing for this macro to do is to a flag in the
1205 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1206 name string in the `symbol_ref' (if one bit is not enough
1209 On the HP-PA we use this to indicate if a symbol is in text or
1210 data space. Also, function labels need special treatment. */
1212 #define TEXT_SPACE_P(DECL)\
1213 (TREE_CODE (DECL) == FUNCTION_DECL \
1214 || (TREE_CODE (DECL) == VAR_DECL \
1215 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1216 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
1218 || CONSTANT_CLASS_P (DECL))
1220 #define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
1222 /* Specify the machine mode that this machine uses for the index in the
1223 tablejump instruction. For small tables, an element consists of a
1224 ia-relative branch and its delay slot. When -mbig-switch is specified,
1225 we use a 32-bit absolute address for non-pic code, and a 32-bit offset
1226 for both 32 and 64-bit pic code. */
1227 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
1229 /* Jump tables must be 32-bit aligned, no matter the size of the element. */
1230 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1232 /* Define this as 1 if `char' should by default be signed; else as 0. */
1233 #define DEFAULT_SIGNED_CHAR 1
1235 /* Max number of bytes we can move from memory to memory
1236 in one reasonably fast instruction. */
1239 /* Higher than the default as we prefer to use simple move insns
1240 (better scheduling and delay slot filling) and because our
1241 built-in block move is really a 2X unrolled loop.
1243 Believe it or not, this has to be big enough to allow for copying all
1244 arguments passed in registers to avoid infinite recursion during argument
1245 setup for a function call. Why? Consider how we copy the stack slots
1246 reserved for parameters when they may be trashed by a call. */
1247 #define MOVE_RATIO(speed) (TARGET_64BIT ? 8 : 4)
1249 /* Define if operations between registers always perform the operation
1250 on the full register even if a narrower mode is specified. */
1251 #define WORD_REGISTER_OPERATIONS
1253 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1254 will either zero-extend or sign-extend. The value of this macro should
1255 be the code that says which one of the two operations is implicitly
1256 done, UNKNOWN if none. */
1257 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1259 /* Nonzero if access to memory by bytes is slow and undesirable. */
1260 #define SLOW_BYTE_ACCESS 1
1262 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1263 is done just by pretending it is already truncated. */
1264 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1266 /* Specify the machine mode that pointers have.
1267 After generation of rtl, the compiler makes no further distinction
1268 between pointers and any other objects of this machine mode. */
1269 #define Pmode word_mode
1271 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1272 return the mode to be used for the comparison. For floating-point, CCFPmode
1273 should be used. CC_NOOVmode should be used when the first operand is a
1274 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1276 #define SELECT_CC_MODE(OP,X,Y) \
1277 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1279 /* A function address in a call instruction
1280 is a byte address (for indexing purposes)
1281 so give the MEM rtx a byte's mode. */
1282 #define FUNCTION_MODE SImode
1284 /* Define this if addresses of constant functions
1285 shouldn't be put through pseudo regs where they can be cse'd.
1286 Desirable on machines where ordinary constants are expensive
1287 but a CALL with constant address is cheap. */
1288 #define NO_FUNCTION_CSE
1290 /* Define this to be nonzero if shift instructions ignore all but the low-order
1292 #define SHIFT_COUNT_TRUNCATED 1
1294 /* Adjust the cost of branches. */
1295 #define BRANCH_COST(speed_p, predictable_p) (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1297 /* Handling the special cases is going to get too complicated for a macro,
1298 just call `pa_adjust_insn_length' to do the real work. */
1299 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1300 LENGTH += pa_adjust_insn_length (INSN, LENGTH);
1302 /* Millicode insns are actually function calls with some special
1303 constraints on arguments and register usage.
1305 Millicode calls always expect their arguments in the integer argument
1306 registers, and always return their result in %r29 (ret1). They
1307 are expected to clobber their arguments, %r1, %r29, and the return
1308 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1310 This macro tells reorg that the references to arguments and
1311 millicode calls do not appear to happen until after the millicode call.
1312 This allows reorg to put insns which set the argument registers into the
1313 delay slot of the millicode call -- thus they act more like traditional
1316 Note we cannot consider side effects of the insn to be delayed because
1317 the branch and link insn will clobber the return pointer. If we happened
1318 to use the return pointer in the delay slot of the call, then we lose.
1320 get_attr_type will try to recognize the given insn, so make sure to
1321 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1323 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
1326 /* Control the assembler format that we output. */
1328 /* A C string constant describing how to begin a comment in the target
1329 assembler language. The compiler assumes that the comment will end at
1330 the end of the line. */
1332 #define ASM_COMMENT_START ";"
1334 /* Output to assembler file text saying following lines
1335 may contain character constants, extra white space, comments, etc. */
1337 #define ASM_APP_ON ""
1339 /* Output to assembler file text saying following lines
1340 no longer contain unusual constructs. */
1342 #define ASM_APP_OFF ""
1344 /* This is how to output the definition of a user-level label named NAME,
1345 such as the label on a static function or variable NAME. */
1347 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1349 assemble_name ((FILE), (NAME)); \
1351 fputs (":\n", (FILE)); \
1353 fputc ('\n', (FILE)); \
1356 /* This is how to output a reference to a user-level label named NAME.
1357 `assemble_name' uses this. */
1359 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1361 const char *xname = (NAME); \
1362 if (FUNCTION_NAME_P (NAME)) \
1364 if (xname[0] == '*') \
1367 fputs (user_label_prefix, FILE); \
1368 fputs (xname, FILE); \
1371 /* This how we output the symbol_ref X. */
1373 #define ASM_OUTPUT_SYMBOL_REF(FILE,X) \
1375 SYMBOL_REF_FLAGS (X) |= SYMBOL_FLAG_REFERENCED; \
1376 assemble_name (FILE, XSTR (X, 0)); \
1379 /* This is how to store into the string LABEL
1380 the symbol_ref name of an internal numbered label where
1381 PREFIX is the class of label and NUM is the number within the class.
1382 This is suitable for output with `assemble_name'. */
1384 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1385 sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
1387 /* Output the definition of a compiler-generated label named NAME. */
1389 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,NAME) \
1391 assemble_name_raw ((FILE), (NAME)); \
1393 fputs (":\n", (FILE)); \
1395 fputc ('\n', (FILE)); \
1398 #define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
1400 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1401 output_ascii ((FILE), (P), (SIZE))
1403 /* Jump tables are always placed in the text section. Technically, it
1404 is possible to put them in the readonly data section when -mbig-switch
1405 is specified. This has the benefit of getting the table out of .text
1406 and reducing branch lengths as a result. The downside is that an
1407 additional insn (addil) is needed to access the table when generating
1408 PIC code. The address difference table also has to use 32-bit
1409 pc-relative relocations. Currently, GAS does not support these
1410 relocations, although it is easily modified to do this operation.
1411 The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
1412 when using ELF GAS. A simple difference can be used when using
1413 SOM GAS or the HP assembler. The final downside is GDB complains
1414 about the nesting of the label for the table when debugging. */
1416 #define JUMP_TABLES_IN_TEXT_SECTION 1
1418 /* This is how to output an element of a case-vector that is absolute. */
1420 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1421 if (TARGET_BIG_SWITCH) \
1422 fprintf (FILE, "\t.word L$%04d\n", VALUE); \
1424 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1426 /* This is how to output an element of a case-vector that is relative.
1427 Since we always place jump tables in the text section, the difference
1428 is absolute and requires no relocation. */
1430 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1431 if (TARGET_BIG_SWITCH) \
1432 fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL); \
1434 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1436 /* This is how to output an assembler line that says to advance the
1437 location counter to a multiple of 2**LOG bytes. */
1439 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1440 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1442 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1443 fprintf (FILE, "\t.blockz "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1444 (unsigned HOST_WIDE_INT)(SIZE))
1446 /* This says how to output an assembler line to define an uninitialized
1447 global variable with size SIZE (in bytes) and alignment ALIGN (in bits).
1448 This macro exists to properly support languages like C++ which do not
1449 have common data. */
1451 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1452 pa_asm_output_aligned_bss (FILE, NAME, SIZE, ALIGN)
1454 /* This says how to output an assembler line to define a global common symbol
1455 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1457 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1458 pa_asm_output_aligned_common (FILE, NAME, SIZE, ALIGN)
1460 /* This says how to output an assembler line to define a local common symbol
1461 with size SIZE (in bytes) and alignment ALIGN (in bits). This macro
1462 controls how the assembler definitions of uninitialized static variables
1465 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1466 pa_asm_output_aligned_local (FILE, NAME, SIZE, ALIGN)
1468 /* All HP assemblers use "!" to separate logical lines. */
1469 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '!')
1471 /* Print operand X (an rtx) in assembler syntax to file FILE.
1472 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1473 For `%' followed by punctuation, CODE is the punctuation and X is null.
1475 On the HP-PA, the CODE can be `r', meaning this is a register-only operand
1476 and an immediate zero should be represented as `r0'.
1478 Several % codes are defined:
1480 C compare conditions
1481 N extract conditions
1482 M modifier to handle preincrement addressing for memory refs.
1483 F modifier to handle preincrement addressing for fp memory refs */
1485 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1488 /* Print a memory address as an operand to reference that memory location. */
1490 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1491 { rtx addr = ADDR; \
1492 switch (GET_CODE (addr)) \
1495 fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
1498 gcc_assert (GET_CODE (XEXP (addr, 1)) == CONST_INT); \
1499 fprintf (FILE, "%d(%s)", (int)INTVAL (XEXP (addr, 1)), \
1500 reg_names [REGNO (XEXP (addr, 0))]); \
1503 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
1504 fputs ("R'", FILE); \
1505 else if (flag_pic == 0) \
1506 fputs ("RR'", FILE); \
1508 fputs ("RT'", FILE); \
1509 output_global_address (FILE, XEXP (addr, 1), 0); \
1510 fputs ("(", FILE); \
1511 output_operand (XEXP (addr, 0), 0); \
1512 fputs (")", FILE); \
1515 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC "(%%r0)", INTVAL (addr)); \
1518 output_addr_const (FILE, addr); \
1522 /* Find the return address associated with the frame given by
1524 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
1525 (return_addr_rtx (COUNT, FRAMEADDR))
1527 /* Used to mask out junk bits from the return address, such as
1528 processor state, interrupt status, condition codes and the like. */
1529 #define MASK_RETURN_ADDR \
1530 /* The privilege level is in the two low order bits, mask em out \
1531 of the return address. */ \
1534 /* The number of Pmode words for the setjmp buffer. */
1535 #define JMP_BUF_SIZE 50
1537 /* We need a libcall to canonicalize function pointers on TARGET_ELF32. */
1538 #define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \
1539 "__canonicalize_funcptr_for_compare"
1542 #undef TARGET_HAVE_TLS
1543 #define TARGET_HAVE_TLS true