1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
45 #ifndef DO_FRAME_NOTES
46 #ifdef INCOMING_RETURN_ADDR_RTX
47 #define DO_FRAME_NOTES 1
49 #define DO_FRAME_NOTES 0
53 static void pa_init_machine_status PARAMS ((struct function *));
54 static void pa_mark_machine_status PARAMS ((struct function *));
55 static void pa_free_machine_status PARAMS ((struct function *));
56 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
57 static void pa_combine_instructions PARAMS ((rtx));
58 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
59 static int forward_branch_p PARAMS ((rtx));
60 static int shadd_constant_p PARAMS ((int));
61 static void pa_add_gc_roots PARAMS ((void));
62 static void mark_deferred_plabels PARAMS ((void *));
63 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
64 static int compute_movstrsi_length PARAMS ((rtx));
65 static void remove_useless_addtr_insns PARAMS ((rtx, int));
66 static rtx store_reg PARAMS ((int, int, int));
67 static rtx load_reg PARAMS ((int, int, int));
68 static rtx set_reg_plus_d PARAMS ((int, int, int));
70 /* Save the operands last given to a compare for use when we
71 generate a scc or bcc insn. */
73 rtx hppa_compare_op0, hppa_compare_op1;
74 enum cmp_type hppa_branch_type;
76 /* Which cpu we are scheduling for. */
77 enum processor_type pa_cpu;
79 /* String to hold which cpu we are scheduling for. */
80 const char *pa_cpu_string;
82 /* Which architecture we are generating code for. */
83 enum architecture_type pa_arch;
85 /* String to hold which architecture we are generating code for. */
86 const char *pa_arch_string;
88 /* Counts for the number of callee-saved general and floating point
89 registers which were saved by the current function's prologue. */
90 static int gr_saved, fr_saved;
92 static rtx find_addr_reg PARAMS ((rtx));
94 /* Keep track of the number of bytes we have output in the CODE subspaces
95 during this compilation so we'll know when to emit inline long-calls. */
97 unsigned int total_code_bytes;
99 /* Variables to handle plabels that we discover are necessary at assembly
100 output time. They are output after the current function. */
102 struct deferred_plabel
106 } *deferred_plabels = 0;
107 int n_deferred_plabels = 0;
112 /* Default to 7100LC scheduling. */
113 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
115 pa_cpu_string = "7100";
116 pa_cpu = PROCESSOR_7100;
118 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
120 pa_cpu_string = "700";
121 pa_cpu = PROCESSOR_700;
123 else if (pa_cpu_string == NULL
124 || ! strcmp (pa_cpu_string, "7100LC"))
126 pa_cpu_string = "7100LC";
127 pa_cpu = PROCESSOR_7100LC;
129 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
131 pa_cpu_string = "7200";
132 pa_cpu = PROCESSOR_7200;
134 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "8000"))
136 pa_cpu_string = "8000";
137 pa_cpu = PROCESSOR_8000;
141 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string);
144 /* Set the instruction set architecture. */
145 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
147 pa_arch_string = "1.0";
148 pa_arch = ARCHITECTURE_10;
149 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
151 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
153 pa_arch_string = "1.1";
154 pa_arch = ARCHITECTURE_11;
155 target_flags &= ~MASK_PA_20;
156 target_flags |= MASK_PA_11;
158 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
160 pa_arch_string = "2.0";
161 pa_arch = ARCHITECTURE_20;
162 target_flags |= MASK_PA_11 | MASK_PA_20;
164 else if (pa_arch_string)
166 warning ("Unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
169 if (flag_pic && TARGET_PORTABLE_RUNTIME)
171 warning ("PIC code generation is not supported in the portable runtime model\n");
174 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
176 warning ("PIC code generation is not compatible with fast indirect calls\n");
179 if (! TARGET_GAS && write_symbols != NO_DEBUG)
181 warning ("-g is only supported when using GAS on this processor,");
182 warning ("-g option disabled.");
183 write_symbols = NO_DEBUG;
186 /* We only support the "big PIC" model now. And we always generate PIC
187 code when in 64bit mode. */
188 if (flag_pic == 1 || TARGET_64BIT)
191 /* Register global variables with the garbage collector. */
194 /* Arrange to save and restore machine status around nested functions. */
195 init_machine_status = pa_init_machine_status;
196 mark_machine_status = pa_mark_machine_status;
197 free_machine_status = pa_free_machine_status;
200 /* Functions to initialize pic_offset_table_save_rtx.
201 These will be called, via pointer variables,
202 from push_function_context and pop_function_context. */
205 pa_init_machine_status (p)
208 p->machine = (machine_function *) xmalloc (sizeof (machine_function));
210 p->machine->pic_offset_table_save_rtx = NULL_RTX;
214 pa_mark_machine_status (p)
218 ggc_mark_rtx (p->machine->pic_offset_table_save_rtx);
222 pa_free_machine_status (p)
225 if (p->machine == NULL)
233 /* Return non-zero only if OP is a register of mode MODE,
236 reg_or_0_operand (op, mode)
238 enum machine_mode mode;
240 return (op == CONST0_RTX (mode) || register_operand (op, mode));
243 /* Return non-zero if OP is suitable for use in a call to a named
246 For 2.5 try to eliminate either call_operand_address or
247 function_label_operand, they perform very similar functions. */
249 call_operand_address (op, mode)
251 enum machine_mode mode ATTRIBUTE_UNUSED;
253 return (GET_MODE (op) == word_mode
254 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
257 /* Return 1 if X contains a symbolic expression. We know these
258 expressions will have one of a few well defined forms, so
259 we need only check those forms. */
261 symbolic_expression_p (x)
265 /* Strip off any HIGH. */
266 if (GET_CODE (x) == HIGH)
269 return (symbolic_operand (x, VOIDmode));
273 symbolic_operand (op, mode)
275 enum machine_mode mode ATTRIBUTE_UNUSED;
277 switch (GET_CODE (op))
284 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
285 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
286 && GET_CODE (XEXP (op, 1)) == CONST_INT);
292 /* Return truth value of statement that OP is a symbolic memory
293 operand of mode MODE. */
296 symbolic_memory_operand (op, mode)
298 enum machine_mode mode ATTRIBUTE_UNUSED;
300 if (GET_CODE (op) == SUBREG)
301 op = SUBREG_REG (op);
302 if (GET_CODE (op) != MEM)
305 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
306 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
309 /* Return 1 if the operand is either a register or a memory operand that is
313 reg_or_nonsymb_mem_operand (op, mode)
315 enum machine_mode mode;
317 if (register_operand (op, mode))
320 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
326 /* Return 1 if the operand is either a register, zero, or a memory operand
327 that is not symbolic. */
330 reg_or_0_or_nonsymb_mem_operand (op, mode)
332 enum machine_mode mode;
334 if (register_operand (op, mode))
337 if (op == CONST0_RTX (mode))
340 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
346 /* Accept any constant that can be moved in one instructions into a
349 cint_ok_for_move (intval)
350 HOST_WIDE_INT intval;
352 /* OK if ldo, ldil, or zdepi, can be used. */
353 return (CONST_OK_FOR_LETTER_P (intval, 'J')
354 || CONST_OK_FOR_LETTER_P (intval, 'N')
355 || CONST_OK_FOR_LETTER_P (intval, 'K'));
358 /* Accept anything that can be moved in one instruction into a general
361 move_operand (op, mode)
363 enum machine_mode mode;
365 if (register_operand (op, mode))
368 if (GET_CODE (op) == CONSTANT_P_RTX)
371 if (GET_CODE (op) == CONST_INT)
372 return cint_ok_for_move (INTVAL (op));
374 if (GET_CODE (op) == SUBREG)
375 op = SUBREG_REG (op);
376 if (GET_CODE (op) != MEM)
381 /* We consider a LO_SUM DLT reference a move_operand now since it has
382 been merged into the normal movsi/movdi patterns. */
383 if (GET_CODE (op) == LO_SUM
384 && GET_CODE (XEXP (op, 0)) == REG
385 && REG_OK_FOR_BASE_P (XEXP (op, 0))
386 && GET_CODE (XEXP (op, 1)) == UNSPEC
387 && GET_MODE (op) == Pmode)
390 /* Since move_operand is only used for source operands, we can always
391 allow scaled indexing! */
392 if (! TARGET_DISABLE_INDEXING
393 && GET_CODE (op) == PLUS
394 && ((GET_CODE (XEXP (op, 0)) == MULT
395 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
396 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
397 && INTVAL (XEXP (XEXP (op, 0), 1)) == GET_MODE_SIZE (mode)
398 && GET_CODE (XEXP (op, 1)) == REG)
399 || (GET_CODE (XEXP (op, 1)) == MULT
400 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
401 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
402 && INTVAL (XEXP (XEXP (op, 1), 1)) == GET_MODE_SIZE (mode)
403 && GET_CODE (XEXP (op, 0)) == REG)))
406 return memory_address_p (mode, op);
409 /* Accept REG and any CONST_INT that can be moved in one instruction into a
412 reg_or_cint_move_operand (op, mode)
414 enum machine_mode mode;
416 if (register_operand (op, mode))
419 if (GET_CODE (op) == CONST_INT)
420 return cint_ok_for_move (INTVAL (op));
426 pic_label_operand (op, mode)
428 enum machine_mode mode ATTRIBUTE_UNUSED;
433 switch (GET_CODE (op))
439 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
440 && GET_CODE (XEXP (op, 1)) == CONST_INT);
447 fp_reg_operand (op, mode)
449 enum machine_mode mode ATTRIBUTE_UNUSED;
451 return reg_renumber && FP_REG_P (op);
456 /* Return truth value of whether OP can be used as an operand in a
457 three operand arithmetic insn that accepts registers of mode MODE
458 or 14-bit signed integers. */
460 arith_operand (op, mode)
462 enum machine_mode mode;
464 return (register_operand (op, mode)
465 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
468 /* Return truth value of whether OP can be used as an operand in a
469 three operand arithmetic insn that accepts registers of mode MODE
470 or 11-bit signed integers. */
472 arith11_operand (op, mode)
474 enum machine_mode mode;
476 return (register_operand (op, mode)
477 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
480 /* A constant integer suitable for use in a PRE_MODIFY memory
483 pre_cint_operand (op, mode)
485 enum machine_mode mode ATTRIBUTE_UNUSED;
487 return (GET_CODE (op) == CONST_INT
488 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
491 /* A constant integer suitable for use in a POST_MODIFY memory
494 post_cint_operand (op, mode)
496 enum machine_mode mode ATTRIBUTE_UNUSED;
498 return (GET_CODE (op) == CONST_INT
499 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
503 arith_double_operand (op, mode)
505 enum machine_mode mode;
507 return (register_operand (op, mode)
508 || (GET_CODE (op) == CONST_DOUBLE
509 && GET_MODE (op) == mode
510 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
511 && ((CONST_DOUBLE_HIGH (op) >= 0)
512 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
515 /* Return truth value of whether OP is a integer which fits the
516 range constraining immediate operands in three-address insns, or
517 is an integer register. */
520 ireg_or_int5_operand (op, mode)
522 enum machine_mode mode ATTRIBUTE_UNUSED;
524 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
525 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
528 /* Return nonzero if OP is an integer register, else return zero. */
530 ireg_operand (op, mode)
532 enum machine_mode mode ATTRIBUTE_UNUSED;
534 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
537 /* Return truth value of whether OP is a integer which fits the
538 range constraining immediate operands in three-address insns. */
541 int5_operand (op, mode)
543 enum machine_mode mode ATTRIBUTE_UNUSED;
545 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
549 uint5_operand (op, mode)
551 enum machine_mode mode ATTRIBUTE_UNUSED;
553 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
557 int11_operand (op, mode)
559 enum machine_mode mode ATTRIBUTE_UNUSED;
561 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
565 uint32_operand (op, mode)
567 enum machine_mode mode ATTRIBUTE_UNUSED;
569 #if HOST_BITS_PER_WIDE_INT > 32
570 /* All allowed constants will fit a CONST_INT. */
571 return (GET_CODE (op) == CONST_INT
572 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
574 return (GET_CODE (op) == CONST_INT
575 || (GET_CODE (op) == CONST_DOUBLE
576 && CONST_DOUBLE_HIGH (op) == 0));
581 arith5_operand (op, mode)
583 enum machine_mode mode;
585 return register_operand (op, mode) || int5_operand (op, mode);
588 /* True iff zdepi can be used to generate this CONST_INT.
589 zdepi first sign extends a 5 bit signed number to a given field
590 length, then places this field anywhere in a zero. */
593 unsigned HOST_WIDE_INT x;
595 unsigned HOST_WIDE_INT lsb_mask, t;
597 /* This might not be obvious, but it's at least fast.
598 This function is critical; we don't have the time loops would take. */
600 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
601 /* Return true iff t is a power of two. */
602 return ((t & (t - 1)) == 0);
605 /* True iff depi or extru can be used to compute (reg & mask).
606 Accept bit pattern like these:
612 unsigned HOST_WIDE_INT mask;
615 mask += mask & -mask;
616 return (mask & (mask - 1)) == 0;
619 /* True iff depi or extru can be used to compute (reg & OP). */
621 and_operand (op, mode)
623 enum machine_mode mode;
625 return (register_operand (op, mode)
626 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
629 /* True iff depi can be used to compute (reg | MASK). */
632 unsigned HOST_WIDE_INT mask;
634 mask += mask & -mask;
635 return (mask & (mask - 1)) == 0;
638 /* True iff depi can be used to compute (reg | OP). */
640 ior_operand (op, mode)
642 enum machine_mode mode ATTRIBUTE_UNUSED;
644 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
648 lhs_lshift_operand (op, mode)
650 enum machine_mode mode;
652 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
655 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
656 Such values can be the left hand side x in (x << r), using the zvdepi
659 lhs_lshift_cint_operand (op, mode)
661 enum machine_mode mode ATTRIBUTE_UNUSED;
663 unsigned HOST_WIDE_INT x;
664 if (GET_CODE (op) != CONST_INT)
666 x = INTVAL (op) >> 4;
667 return (x & (x + 1)) == 0;
671 arith32_operand (op, mode)
673 enum machine_mode mode;
675 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
679 pc_or_label_operand (op, mode)
681 enum machine_mode mode ATTRIBUTE_UNUSED;
683 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
686 /* Legitimize PIC addresses. If the address is already
687 position-independent, we return ORIG. Newly generated
688 position-independent addresses go to REG. If we need more
689 than one register, we lose. */
692 legitimize_pic_address (orig, mode, reg)
694 enum machine_mode mode;
698 /* Labels need special handling. */
699 if (pic_label_operand (orig, mode))
701 /* We do not want to go through the movXX expanders here since that
702 would create recursion.
704 Nor do we really want to call a generator for a named pattern
705 since that requires multiple patterns if we want to support
708 So instead we just emit the raw set, which avoids the movXX
709 expanders completely. */
710 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
711 current_function_uses_pic_offset_table = 1;
714 if (GET_CODE (orig) == SYMBOL_REF)
720 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
721 gen_rtx_HIGH (word_mode, orig)));
723 = gen_rtx_MEM (Pmode,
724 gen_rtx_LO_SUM (Pmode, reg,
725 gen_rtx_UNSPEC (Pmode,
729 current_function_uses_pic_offset_table = 1;
730 RTX_UNCHANGING_P (pic_ref) = 1;
731 emit_move_insn (reg, pic_ref);
734 else if (GET_CODE (orig) == CONST)
738 if (GET_CODE (XEXP (orig, 0)) == PLUS
739 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
745 if (GET_CODE (XEXP (orig, 0)) == PLUS)
747 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
748 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
749 base == reg ? 0 : reg);
752 if (GET_CODE (orig) == CONST_INT)
754 if (INT_14_BITS (orig))
755 return plus_constant_for_output (base, INTVAL (orig));
756 orig = force_reg (Pmode, orig);
758 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
759 /* Likewise, should we set special REG_NOTEs here? */
764 /* Try machine-dependent ways of modifying an illegitimate address
765 to be legitimate. If we find one, return the new, valid address.
766 This macro is used in only one place: `memory_address' in explow.c.
768 OLDX is the address as it was before break_out_memory_refs was called.
769 In some cases it is useful to look at this to decide what needs to be done.
771 MODE and WIN are passed so that this macro can use
772 GO_IF_LEGITIMATE_ADDRESS.
774 It is always safe for this macro to do nothing. It exists to recognize
775 opportunities to optimize the output.
777 For the PA, transform:
779 memory(X + <large int>)
783 if (<large int> & mask) >= 16
784 Y = (<large int> & ~mask) + mask + 1 Round up.
786 Y = (<large int> & ~mask) Round down.
788 memory (Z + (<large int> - Y));
790 This is for CSE to find several similar references, and only use one Z.
792 X can either be a SYMBOL_REF or REG, but because combine can not
793 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
794 D will not fit in 14 bits.
796 MODE_FLOAT references allow displacements which fit in 5 bits, so use
799 MODE_INT references allow displacements which fit in 14 bits, so use
802 This relies on the fact that most mode MODE_FLOAT references will use FP
803 registers and most mode MODE_INT references will use integer registers.
804 (In the rare case of an FP register used in an integer MODE, we depend
805 on secondary reloads to clean things up.)
808 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
809 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
810 addressing modes to be used).
812 Put X and Z into registers. Then put the entire expression into
816 hppa_legitimize_address (x, oldx, mode)
817 rtx x, oldx ATTRIBUTE_UNUSED;
818 enum machine_mode mode;
823 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
825 /* Strip off CONST. */
826 if (GET_CODE (x) == CONST)
829 /* Special case. Get the SYMBOL_REF into a register and use indexing.
830 That should always be safe. */
831 if (GET_CODE (x) == PLUS
832 && GET_CODE (XEXP (x, 0)) == REG
833 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
835 rtx reg = force_reg (Pmode, XEXP (x, 1));
836 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
839 /* Note we must reject symbols which represent function addresses
840 since the assembler/linker can't handle arithmetic on plabels. */
841 if (GET_CODE (x) == PLUS
842 && GET_CODE (XEXP (x, 1)) == CONST_INT
843 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
844 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
845 || GET_CODE (XEXP (x, 0)) == REG))
847 rtx int_part, ptr_reg;
849 int offset = INTVAL (XEXP (x, 1));
852 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
853 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
855 /* Choose which way to round the offset. Round up if we
856 are >= halfway to the next boundary. */
857 if ((offset & mask) >= ((mask + 1) / 2))
858 newoffset = (offset & ~ mask) + mask + 1;
860 newoffset = (offset & ~ mask);
862 /* If the newoffset will not fit in 14 bits (ldo), then
863 handling this would take 4 or 5 instructions (2 to load
864 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
865 add the new offset and the SYMBOL_REF.) Combine can
866 not handle 4->2 or 5->2 combinations, so do not create
868 if (! VAL_14_BITS_P (newoffset)
869 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
871 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
874 gen_rtx_HIGH (Pmode, const_part));
877 gen_rtx_LO_SUM (Pmode,
878 tmp_reg, const_part));
882 if (! VAL_14_BITS_P (newoffset))
883 int_part = force_reg (Pmode, GEN_INT (newoffset));
885 int_part = GEN_INT (newoffset);
887 ptr_reg = force_reg (Pmode,
889 force_reg (Pmode, XEXP (x, 0)),
892 return plus_constant (ptr_reg, offset - newoffset);
895 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
897 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
898 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
899 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
900 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
901 || GET_CODE (XEXP (x, 1)) == SUBREG)
902 && GET_CODE (XEXP (x, 1)) != CONST)
904 int val = INTVAL (XEXP (XEXP (x, 0), 1));
908 if (GET_CODE (reg1) != REG)
909 reg1 = force_reg (Pmode, force_operand (reg1, 0));
911 reg2 = XEXP (XEXP (x, 0), 0);
912 if (GET_CODE (reg2) != REG)
913 reg2 = force_reg (Pmode, force_operand (reg2, 0));
915 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
922 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
924 Only do so for floating point modes since this is more speculative
925 and we lose if it's an integer store. */
926 if (GET_CODE (x) == PLUS
927 && GET_CODE (XEXP (x, 0)) == PLUS
928 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
929 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
930 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
931 && (mode == SFmode || mode == DFmode))
934 /* First, try and figure out what to use as a base register. */
935 rtx reg1, reg2, base, idx, orig_base;
937 reg1 = XEXP (XEXP (x, 0), 1);
942 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
943 then emit_move_sequence will turn on REG_POINTER so we'll know
944 it's a base register below. */
945 if (GET_CODE (reg1) != REG)
946 reg1 = force_reg (Pmode, force_operand (reg1, 0));
948 if (GET_CODE (reg2) != REG)
949 reg2 = force_reg (Pmode, force_operand (reg2, 0));
951 /* Figure out what the base and index are. */
953 if (GET_CODE (reg1) == REG
954 && REG_POINTER (reg1))
957 orig_base = XEXP (XEXP (x, 0), 1);
958 idx = gen_rtx_PLUS (Pmode,
960 XEXP (XEXP (XEXP (x, 0), 0), 0),
961 XEXP (XEXP (XEXP (x, 0), 0), 1)),
964 else if (GET_CODE (reg2) == REG
965 && REG_POINTER (reg2))
968 orig_base = XEXP (x, 1);
975 /* If the index adds a large constant, try to scale the
976 constant so that it can be loaded with only one insn. */
977 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
978 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
979 / INTVAL (XEXP (XEXP (idx, 0), 1)))
980 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
982 /* Divide the CONST_INT by the scale factor, then add it to A. */
983 int val = INTVAL (XEXP (idx, 1));
985 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
986 reg1 = XEXP (XEXP (idx, 0), 0);
987 if (GET_CODE (reg1) != REG)
988 reg1 = force_reg (Pmode, force_operand (reg1, 0));
990 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
992 /* We can now generate a simple scaled indexed address. */
995 (Pmode, gen_rtx_PLUS (Pmode,
996 gen_rtx_MULT (Pmode, reg1,
997 XEXP (XEXP (idx, 0), 1)),
1001 /* If B + C is still a valid base register, then add them. */
1002 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1003 && INTVAL (XEXP (idx, 1)) <= 4096
1004 && INTVAL (XEXP (idx, 1)) >= -4096)
1006 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1009 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1011 reg2 = XEXP (XEXP (idx, 0), 0);
1012 if (GET_CODE (reg2) != CONST_INT)
1013 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1015 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1016 gen_rtx_MULT (Pmode,
1022 /* Get the index into a register, then add the base + index and
1023 return a register holding the result. */
1025 /* First get A into a register. */
1026 reg1 = XEXP (XEXP (idx, 0), 0);
1027 if (GET_CODE (reg1) != REG)
1028 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1030 /* And get B into a register. */
1031 reg2 = XEXP (idx, 1);
1032 if (GET_CODE (reg2) != REG)
1033 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1035 reg1 = force_reg (Pmode,
1036 gen_rtx_PLUS (Pmode,
1037 gen_rtx_MULT (Pmode, reg1,
1038 XEXP (XEXP (idx, 0), 1)),
1041 /* Add the result to our base register and return. */
1042 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1046 /* Uh-oh. We might have an address for x[n-100000]. This needs
1047 special handling to avoid creating an indexed memory address
1048 with x-100000 as the base.
1050 If the constant part is small enough, then it's still safe because
1051 there is a guard page at the beginning and end of the data segment.
1053 Scaled references are common enough that we want to try and rearrange the
1054 terms so that we can use indexing for these addresses too. Only
1055 do the optimization for floatint point modes. */
1057 if (GET_CODE (x) == PLUS
1058 && symbolic_expression_p (XEXP (x, 1)))
1060 /* Ugly. We modify things here so that the address offset specified
1061 by the index expression is computed first, then added to x to form
1062 the entire address. */
1064 rtx regx1, regx2, regy1, regy2, y;
1066 /* Strip off any CONST. */
1068 if (GET_CODE (y) == CONST)
1071 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1073 /* See if this looks like
1074 (plus (mult (reg) (shadd_const))
1075 (const (plus (symbol_ref) (const_int))))
1077 Where const_int is small. In that case the const
1078 expression is a valid pointer for indexing.
1080 If const_int is big, but can be divided evenly by shadd_const
1081 and added to (reg). This allows more scaled indexed addresses. */
1082 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1083 && GET_CODE (XEXP (x, 0)) == MULT
1084 && GET_CODE (XEXP (y, 1)) == CONST_INT
1085 && INTVAL (XEXP (y, 1)) >= -4096
1086 && INTVAL (XEXP (y, 1)) <= 4095
1087 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1088 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1090 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1094 if (GET_CODE (reg1) != REG)
1095 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1097 reg2 = XEXP (XEXP (x, 0), 0);
1098 if (GET_CODE (reg2) != REG)
1099 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1101 return force_reg (Pmode,
1102 gen_rtx_PLUS (Pmode,
1103 gen_rtx_MULT (Pmode,
1108 else if ((mode == DFmode || mode == SFmode)
1109 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1110 && GET_CODE (XEXP (x, 0)) == MULT
1111 && GET_CODE (XEXP (y, 1)) == CONST_INT
1112 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1113 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1114 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1117 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1118 / INTVAL (XEXP (XEXP (x, 0), 1))));
1119 regx2 = XEXP (XEXP (x, 0), 0);
1120 if (GET_CODE (regx2) != REG)
1121 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1122 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1126 gen_rtx_PLUS (Pmode,
1127 gen_rtx_MULT (Pmode, regx2,
1128 XEXP (XEXP (x, 0), 1)),
1129 force_reg (Pmode, XEXP (y, 0))));
1131 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1132 && INTVAL (XEXP (y, 1)) >= -4096
1133 && INTVAL (XEXP (y, 1)) <= 4095)
1135 /* This is safe because of the guard page at the
1136 beginning and end of the data space. Just
1137 return the original address. */
1142 /* Doesn't look like one we can optimize. */
1143 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1144 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1145 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1146 regx1 = force_reg (Pmode,
1147 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1149 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1157 /* For the HPPA, REG and REG+CONST is cost 0
1158 and addresses involving symbolic constants are cost 2.
1160 PIC addresses are very expensive.
1162 It is no coincidence that this has the same structure
1163 as GO_IF_LEGITIMATE_ADDRESS. */
1165 hppa_address_cost (X)
1168 if (GET_CODE (X) == PLUS)
1170 else if (GET_CODE (X) == LO_SUM)
1172 else if (GET_CODE (X) == HIGH)
1177 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1178 new rtx with the correct mode. */
1180 force_mode (mode, orig)
1181 enum machine_mode mode;
1184 if (mode == GET_MODE (orig))
1187 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1190 return gen_rtx_REG (mode, REGNO (orig));
1193 /* Emit insns to move operands[1] into operands[0].
1195 Return 1 if we have written out everything that needs to be done to
1196 do the move. Otherwise, return 0 and the caller will emit the move
1199 Note SCRATCH_REG may not be in the proper mode depending on how it
1200 will be used. This routine is resposible for creating a new copy
1201 of SCRATCH_REG in the proper mode. */
1204 emit_move_sequence (operands, mode, scratch_reg)
1206 enum machine_mode mode;
1209 register rtx operand0 = operands[0];
1210 register rtx operand1 = operands[1];
1214 && reload_in_progress && GET_CODE (operand0) == REG
1215 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1216 operand0 = reg_equiv_mem[REGNO (operand0)];
1217 else if (scratch_reg
1218 && reload_in_progress && GET_CODE (operand0) == SUBREG
1219 && GET_CODE (SUBREG_REG (operand0)) == REG
1220 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1222 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1223 the code which tracks sets/uses for delete_output_reload. */
1224 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1225 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1226 SUBREG_BYTE (operand0));
1227 operand0 = alter_subreg (temp);
1231 && reload_in_progress && GET_CODE (operand1) == REG
1232 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1233 operand1 = reg_equiv_mem[REGNO (operand1)];
1234 else if (scratch_reg
1235 && reload_in_progress && GET_CODE (operand1) == SUBREG
1236 && GET_CODE (SUBREG_REG (operand1)) == REG
1237 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1239 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1240 the code which tracks sets/uses for delete_output_reload. */
1241 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1242 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1243 SUBREG_BYTE (operand1));
1244 operand1 = alter_subreg (temp);
1247 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1248 && ((tem = find_replacement (&XEXP (operand0, 0)))
1249 != XEXP (operand0, 0)))
1250 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1251 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1252 && ((tem = find_replacement (&XEXP (operand1, 0)))
1253 != XEXP (operand1, 0)))
1254 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1256 /* Handle secondary reloads for loads/stores of FP registers from
1257 REG+D addresses where D does not fit in 5 bits, including
1258 (subreg (mem (addr))) cases. */
1259 if (fp_reg_operand (operand0, mode)
1260 && ((GET_CODE (operand1) == MEM
1261 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1262 || ((GET_CODE (operand1) == SUBREG
1263 && GET_CODE (XEXP (operand1, 0)) == MEM
1264 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1267 if (GET_CODE (operand1) == SUBREG)
1268 operand1 = XEXP (operand1, 0);
1270 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1271 it in WORD_MODE regardless of what mode it was originally given
1273 scratch_reg = force_mode (word_mode, scratch_reg);
1275 /* D might not fit in 14 bits either; for such cases load D into
1277 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1279 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1280 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1282 XEXP (XEXP (operand1, 0), 0),
1286 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1287 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1288 gen_rtx_MEM (mode, scratch_reg)));
1291 else if (fp_reg_operand (operand1, mode)
1292 && ((GET_CODE (operand0) == MEM
1293 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1294 || ((GET_CODE (operand0) == SUBREG)
1295 && GET_CODE (XEXP (operand0, 0)) == MEM
1296 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1299 if (GET_CODE (operand0) == SUBREG)
1300 operand0 = XEXP (operand0, 0);
1302 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1303 it in WORD_MODE regardless of what mode it was originally given
1305 scratch_reg = force_mode (word_mode, scratch_reg);
1307 /* D might not fit in 14 bits either; for such cases load D into
1309 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1311 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1312 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1315 XEXP (XEXP (operand0, 0),
1320 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1321 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1325 /* Handle secondary reloads for loads of FP registers from constant
1326 expressions by forcing the constant into memory.
1328 use scratch_reg to hold the address of the memory location.
1330 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1331 NO_REGS when presented with a const_int and an register class
1332 containing only FP registers. Doing so unfortunately creates
1333 more problems than it solves. Fix this for 2.5. */
1334 else if (fp_reg_operand (operand0, mode)
1335 && CONSTANT_P (operand1)
1340 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1341 it in WORD_MODE regardless of what mode it was originally given
1343 scratch_reg = force_mode (word_mode, scratch_reg);
1345 /* Force the constant into memory and put the address of the
1346 memory location into scratch_reg. */
1347 xoperands[0] = scratch_reg;
1348 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1349 emit_move_sequence (xoperands, Pmode, 0);
1351 /* Now load the destination register. */
1352 emit_insn (gen_rtx_SET (mode, operand0,
1353 gen_rtx_MEM (mode, scratch_reg)));
1356 /* Handle secondary reloads for SAR. These occur when trying to load
1357 the SAR from memory, FP register, or with a constant. */
1358 else if (GET_CODE (operand0) == REG
1359 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1360 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1361 && (GET_CODE (operand1) == MEM
1362 || GET_CODE (operand1) == CONST_INT
1363 || (GET_CODE (operand1) == REG
1364 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1367 /* D might not fit in 14 bits either; for such cases load D into
1369 if (GET_CODE (operand1) == MEM
1370 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1372 /* We are reloading the address into the scratch register, so we
1373 want to make sure the scratch register is a full register. */
1374 scratch_reg = force_mode (word_mode, scratch_reg);
1376 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1377 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1380 XEXP (XEXP (operand1, 0),
1384 /* Now we are going to load the scratch register from memory,
1385 we want to load it in the same width as the original MEM,
1386 which must be the same as the width of the ultimate destination,
1388 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1390 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1395 /* We want to load the scratch register using the same mode as
1396 the ultimate destination. */
1397 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1399 emit_move_insn (scratch_reg, operand1);
1402 /* And emit the insn to set the ultimate destination. We know that
1403 the scratch register has the same mode as the destination at this
1405 emit_move_insn (operand0, scratch_reg);
1408 /* Handle most common case: storing into a register. */
1409 else if (register_operand (operand0, mode))
1411 if (register_operand (operand1, mode)
1412 || (GET_CODE (operand1) == CONST_INT && INT_14_BITS (operand1))
1413 || (operand1 == CONST0_RTX (mode))
1414 || (GET_CODE (operand1) == HIGH
1415 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1416 /* Only `general_operands' can come here, so MEM is ok. */
1417 || GET_CODE (operand1) == MEM)
1419 /* Run this case quickly. */
1420 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1424 else if (GET_CODE (operand0) == MEM)
1426 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1427 && !(reload_in_progress || reload_completed))
1429 rtx temp = gen_reg_rtx (DFmode);
1431 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1432 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1435 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1437 /* Run this case quickly. */
1438 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1441 if (! (reload_in_progress || reload_completed))
1443 operands[0] = validize_mem (operand0);
1444 operands[1] = operand1 = force_reg (mode, operand1);
1448 /* Simplify the source if we need to.
1449 Note we do have to handle function labels here, even though we do
1450 not consider them legitimate constants. Loop optimizations can
1451 call the emit_move_xxx with one as a source. */
1452 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1453 || function_label_operand (operand1, mode)
1454 || (GET_CODE (operand1) == HIGH
1455 && symbolic_operand (XEXP (operand1, 0), mode)))
1459 if (GET_CODE (operand1) == HIGH)
1462 operand1 = XEXP (operand1, 0);
1464 if (symbolic_operand (operand1, mode))
1466 /* Argh. The assembler and linker can't handle arithmetic
1469 So we force the plabel into memory, load operand0 from
1470 the memory location, then add in the constant part. */
1471 if ((GET_CODE (operand1) == CONST
1472 && GET_CODE (XEXP (operand1, 0)) == PLUS
1473 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1474 || function_label_operand (operand1, mode))
1476 rtx temp, const_part;
1478 /* Figure out what (if any) scratch register to use. */
1479 if (reload_in_progress || reload_completed)
1481 scratch_reg = scratch_reg ? scratch_reg : operand0;
1482 /* SCRATCH_REG will hold an address and maybe the actual
1483 data. We want it in WORD_MODE regardless of what mode it
1484 was originally given to us. */
1485 scratch_reg = force_mode (word_mode, scratch_reg);
1488 scratch_reg = gen_reg_rtx (Pmode);
1490 if (GET_CODE (operand1) == CONST)
1492 /* Save away the constant part of the expression. */
1493 const_part = XEXP (XEXP (operand1, 0), 1);
1494 if (GET_CODE (const_part) != CONST_INT)
1497 /* Force the function label into memory. */
1498 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1502 /* No constant part. */
1503 const_part = NULL_RTX;
1505 /* Force the function label into memory. */
1506 temp = force_const_mem (mode, operand1);
1510 /* Get the address of the memory location. PIC-ify it if
1512 temp = XEXP (temp, 0);
1514 temp = legitimize_pic_address (temp, mode, scratch_reg);
1516 /* Put the address of the memory location into our destination
1519 emit_move_sequence (operands, mode, scratch_reg);
1521 /* Now load from the memory location into our destination
1523 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1524 emit_move_sequence (operands, mode, scratch_reg);
1526 /* And add back in the constant part. */
1527 if (const_part != NULL_RTX)
1528 expand_inc (operand0, const_part);
1537 if (reload_in_progress || reload_completed)
1539 temp = scratch_reg ? scratch_reg : operand0;
1540 /* TEMP will hold an address and maybe the actual
1541 data. We want it in WORD_MODE regardless of what mode it
1542 was originally given to us. */
1543 temp = force_mode (word_mode, temp);
1546 temp = gen_reg_rtx (Pmode);
1548 /* (const (plus (symbol) (const_int))) must be forced to
1549 memory during/after reload if the const_int will not fit
1551 if (GET_CODE (operand1) == CONST
1552 && GET_CODE (XEXP (operand1, 0)) == PLUS
1553 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1554 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1555 && (reload_completed || reload_in_progress)
1558 operands[1] = force_const_mem (mode, operand1);
1559 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1561 emit_move_sequence (operands, mode, temp);
1565 operands[1] = legitimize_pic_address (operand1, mode, temp);
1566 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1569 /* On the HPPA, references to data space are supposed to use dp,
1570 register 27, but showing it in the RTL inhibits various cse
1571 and loop optimizations. */
1576 if (reload_in_progress || reload_completed)
1578 temp = scratch_reg ? scratch_reg : operand0;
1579 /* TEMP will hold an address and maybe the actual
1580 data. We want it in WORD_MODE regardless of what mode it
1581 was originally given to us. */
1582 temp = force_mode (word_mode, temp);
1585 temp = gen_reg_rtx (mode);
1587 /* Loading a SYMBOL_REF into a register makes that register
1588 safe to be used as the base in an indexed address.
1590 Don't mark hard registers though. That loses. */
1591 if (GET_CODE (operand0) == REG
1592 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1593 REG_POINTER (operand0) = 1;
1594 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1595 REG_POINTER (temp) = 1;
1597 set = gen_rtx_SET (mode, operand0, temp);
1599 set = gen_rtx_SET (VOIDmode,
1601 gen_rtx_LO_SUM (mode, temp, operand1));
1603 emit_insn (gen_rtx_SET (VOIDmode,
1605 gen_rtx_HIGH (mode, operand1)));
1611 else if (GET_CODE (operand1) != CONST_INT
1612 || ! cint_ok_for_move (INTVAL (operand1)))
1615 int need_zero_extend = 0;
1617 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1618 && HOST_BITS_PER_WIDE_INT > 32
1619 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1621 HOST_WIDE_INT val = INTVAL (operand1);
1624 /* If the value is the same after a 32->64bit sign
1625 extension, then we can use it as-is. Else we will
1626 need to sign extend the constant from 32->64bits
1627 then zero extend the result from 32->64bits. */
1628 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1629 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1632 need_zero_extend = 1;
1633 operand1 = GEN_INT (nval);
1637 if (reload_in_progress || reload_completed)
1640 temp = gen_reg_rtx (mode);
1642 emit_insn (gen_rtx_SET (VOIDmode, temp,
1643 gen_rtx_HIGH (mode, operand1)));
1644 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1645 emit_move_insn (operands[0], operands[1]);
1647 if (need_zero_extend)
1649 emit_insn (gen_zero_extendsidi2 (operands[0],
1650 gen_rtx_SUBREG (SImode,
1658 /* Now have insn-emit do whatever it normally does. */
1662 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1663 it will need a link/runtime reloc). */
1671 switch (TREE_CODE (exp))
1678 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1679 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1684 case NON_LVALUE_EXPR:
1685 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1691 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1692 if (TREE_VALUE (link) != 0)
1693 reloc |= reloc_needed (TREE_VALUE (link));
1706 /* Does operand (which is a symbolic_operand) live in text space? If
1707 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1710 read_only_operand (operand, mode)
1712 enum machine_mode mode ATTRIBUTE_UNUSED;
1714 if (GET_CODE (operand) == CONST)
1715 operand = XEXP (XEXP (operand, 0), 0);
1718 if (GET_CODE (operand) == SYMBOL_REF)
1719 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1723 if (GET_CODE (operand) == SYMBOL_REF)
1724 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1730 /* Return the best assembler insn template
1731 for moving operands[1] into operands[0] as a fullword. */
1733 singlemove_string (operands)
1736 HOST_WIDE_INT intval;
1738 if (GET_CODE (operands[0]) == MEM)
1739 return "stw %r1,%0";
1740 if (GET_CODE (operands[1]) == MEM)
1742 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1747 if (GET_MODE (operands[1]) != SFmode)
1750 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1752 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1753 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1755 operands[1] = GEN_INT (i);
1756 /* Fall through to CONST_INT case. */
1758 if (GET_CODE (operands[1]) == CONST_INT)
1760 intval = INTVAL (operands[1]);
1762 if (VAL_14_BITS_P (intval))
1764 else if ((intval & 0x7ff) == 0)
1765 return "ldil L'%1,%0";
1766 else if (zdepi_cint_p (intval))
1767 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1769 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1771 return "copy %1,%0";
1775 /* Compute position (in OP[1]) and width (in OP[2])
1776 useful for copying IMM to a register using the zdepi
1777 instructions. Store the immediate value to insert in OP[0]. */
1779 compute_zdepwi_operands (imm, op)
1780 unsigned HOST_WIDE_INT imm;
1785 /* Find the least significant set bit in IMM. */
1786 for (lsb = 0; lsb < 32; lsb++)
1793 /* Choose variants based on *sign* of the 5-bit field. */
1794 if ((imm & 0x10) == 0)
1795 len = (lsb <= 28) ? 4 : 32 - lsb;
1798 /* Find the width of the bitstring in IMM. */
1799 for (len = 5; len < 32; len++)
1801 if ((imm & (1 << len)) == 0)
1805 /* Sign extend IMM as a 5-bit value. */
1806 imm = (imm & 0xf) - 0x10;
1814 /* Compute position (in OP[1]) and width (in OP[2])
1815 useful for copying IMM to a register using the depdi,z
1816 instructions. Store the immediate value to insert in OP[0]. */
1818 compute_zdepdi_operands (imm, op)
1819 unsigned HOST_WIDE_INT imm;
1822 HOST_WIDE_INT lsb, len;
1824 /* Find the least significant set bit in IMM. */
1825 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1832 /* Choose variants based on *sign* of the 5-bit field. */
1833 if ((imm & 0x10) == 0)
1834 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1835 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1838 /* Find the width of the bitstring in IMM. */
1839 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1841 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
1845 /* Sign extend IMM as a 5-bit value. */
1846 imm = (imm & 0xf) - 0x10;
1854 /* Output assembler code to perform a doubleword move insn
1855 with operands OPERANDS. */
1858 output_move_double (operands)
1861 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1863 rtx addreg0 = 0, addreg1 = 0;
1865 /* First classify both operands. */
1867 if (REG_P (operands[0]))
1869 else if (offsettable_memref_p (operands[0]))
1871 else if (GET_CODE (operands[0]) == MEM)
1876 if (REG_P (operands[1]))
1878 else if (CONSTANT_P (operands[1]))
1880 else if (offsettable_memref_p (operands[1]))
1882 else if (GET_CODE (operands[1]) == MEM)
1887 /* Check for the cases that the operand constraints are not
1888 supposed to allow to happen. Abort if we get one,
1889 because generating code for these cases is painful. */
1891 if (optype0 != REGOP && optype1 != REGOP)
1894 /* Handle auto decrementing and incrementing loads and stores
1895 specifically, since the structure of the function doesn't work
1896 for them without major modification. Do it better when we learn
1897 this port about the general inc/dec addressing of PA.
1898 (This was written by tege. Chide him if it doesn't work.) */
1900 if (optype0 == MEMOP)
1902 /* We have to output the address syntax ourselves, since print_operand
1903 doesn't deal with the addresses we want to use. Fix this later. */
1905 rtx addr = XEXP (operands[0], 0);
1906 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1908 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1910 operands[0] = XEXP (addr, 0);
1911 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1914 if (!reg_overlap_mentioned_p (high_reg, addr))
1916 /* No overlap between high target register and address
1917 register. (We do this in a non-obvious way to
1918 save a register file writeback) */
1919 if (GET_CODE (addr) == POST_INC)
1920 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
1921 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
1926 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1928 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1930 operands[0] = XEXP (addr, 0);
1931 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1934 if (!reg_overlap_mentioned_p (high_reg, addr))
1936 /* No overlap between high target register and address
1937 register. (We do this in a non-obvious way to
1938 save a register file writeback) */
1939 if (GET_CODE (addr) == PRE_INC)
1940 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
1941 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
1947 if (optype1 == MEMOP)
1949 /* We have to output the address syntax ourselves, since print_operand
1950 doesn't deal with the addresses we want to use. Fix this later. */
1952 rtx addr = XEXP (operands[1], 0);
1953 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1955 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1957 operands[1] = XEXP (addr, 0);
1958 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1961 if (!reg_overlap_mentioned_p (high_reg, addr))
1963 /* No overlap between high target register and address
1964 register. (We do this in a non-obvious way to
1965 save a register file writeback) */
1966 if (GET_CODE (addr) == POST_INC)
1967 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
1968 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0}";
1972 /* This is an undefined situation. We should load into the
1973 address register *and* update that register. Probably
1974 we don't need to handle this at all. */
1975 if (GET_CODE (addr) == POST_INC)
1976 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
1977 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
1980 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1982 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1984 operands[1] = XEXP (addr, 0);
1985 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1988 if (!reg_overlap_mentioned_p (high_reg, addr))
1990 /* No overlap between high target register and address
1991 register. (We do this in a non-obvious way to
1992 save a register file writeback) */
1993 if (GET_CODE (addr) == PRE_INC)
1994 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
1995 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
1999 /* This is an undefined situation. We should load into the
2000 address register *and* update that register. Probably
2001 we don't need to handle this at all. */
2002 if (GET_CODE (addr) == PRE_INC)
2003 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2004 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2007 else if (GET_CODE (addr) == PLUS
2008 && GET_CODE (XEXP (addr, 0)) == MULT)
2010 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2012 if (!reg_overlap_mentioned_p (high_reg, addr))
2016 xoperands[0] = high_reg;
2017 xoperands[1] = XEXP (addr, 1);
2018 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2019 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2020 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2022 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2028 xoperands[0] = high_reg;
2029 xoperands[1] = XEXP (addr, 1);
2030 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2031 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2032 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2034 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2039 /* If an operand is an unoffsettable memory ref, find a register
2040 we can increment temporarily to make it refer to the second word. */
2042 if (optype0 == MEMOP)
2043 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2045 if (optype1 == MEMOP)
2046 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2048 /* Ok, we can do one word at a time.
2049 Normally we do the low-numbered word first.
2051 In either case, set up in LATEHALF the operands to use
2052 for the high-numbered word and in some cases alter the
2053 operands in OPERANDS to be suitable for the low-numbered word. */
2055 if (optype0 == REGOP)
2056 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2057 else if (optype0 == OFFSOP)
2058 latehalf[0] = adj_offsettable_operand (operands[0], 4);
2060 latehalf[0] = operands[0];
2062 if (optype1 == REGOP)
2063 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2064 else if (optype1 == OFFSOP)
2065 latehalf[1] = adj_offsettable_operand (operands[1], 4);
2066 else if (optype1 == CNSTOP)
2067 split_double (operands[1], &operands[1], &latehalf[1]);
2069 latehalf[1] = operands[1];
2071 /* If the first move would clobber the source of the second one,
2072 do them in the other order.
2074 This can happen in two cases:
2076 mem -> register where the first half of the destination register
2077 is the same register used in the memory's address. Reload
2078 can create such insns.
2080 mem in this case will be either register indirect or register
2081 indirect plus a valid offset.
2083 register -> register move where REGNO(dst) == REGNO(src + 1)
2084 someone (Tim/Tege?) claimed this can happen for parameter loads.
2086 Handle mem -> register case first. */
2087 if (optype0 == REGOP
2088 && (optype1 == MEMOP || optype1 == OFFSOP)
2089 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2092 /* Do the late half first. */
2094 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2095 output_asm_insn (singlemove_string (latehalf), latehalf);
2099 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2100 return singlemove_string (operands);
2103 /* Now handle register -> register case. */
2104 if (optype0 == REGOP && optype1 == REGOP
2105 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2107 output_asm_insn (singlemove_string (latehalf), latehalf);
2108 return singlemove_string (operands);
2111 /* Normal case: do the two words, low-numbered first. */
2113 output_asm_insn (singlemove_string (operands), operands);
2115 /* Make any unoffsettable addresses point at high-numbered word. */
2117 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2119 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2122 output_asm_insn (singlemove_string (latehalf), latehalf);
2124 /* Undo the adds we just did. */
2126 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2128 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2134 output_fp_move_double (operands)
2137 if (FP_REG_P (operands[0]))
2139 if (FP_REG_P (operands[1])
2140 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2141 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2143 output_asm_insn ("fldd%F1 %1,%0", operands);
2145 else if (FP_REG_P (operands[1]))
2147 output_asm_insn ("fstd%F0 %1,%0", operands);
2149 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2151 if (GET_CODE (operands[0]) == REG)
2154 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2155 xoperands[0] = operands[0];
2156 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2158 /* This is a pain. You have to be prepared to deal with an
2159 arbitrary address here including pre/post increment/decrement.
2161 so avoid this in the MD. */
2169 /* Return a REG that occurs in ADDR with coefficient 1.
2170 ADDR can be effectively incremented by incrementing REG. */
2173 find_addr_reg (addr)
2176 while (GET_CODE (addr) == PLUS)
2178 if (GET_CODE (XEXP (addr, 0)) == REG)
2179 addr = XEXP (addr, 0);
2180 else if (GET_CODE (XEXP (addr, 1)) == REG)
2181 addr = XEXP (addr, 1);
2182 else if (CONSTANT_P (XEXP (addr, 0)))
2183 addr = XEXP (addr, 1);
2184 else if (CONSTANT_P (XEXP (addr, 1)))
2185 addr = XEXP (addr, 0);
2189 if (GET_CODE (addr) == REG)
2194 /* Emit code to perform a block move.
2196 OPERANDS[0] is the destination pointer as a REG, clobbered.
2197 OPERANDS[1] is the source pointer as a REG, clobbered.
2198 OPERANDS[2] is a register for temporary storage.
2199 OPERANDS[4] is the size as a CONST_INT
2200 OPERANDS[3] is a register for temporary storage.
2201 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2202 OPERANDS[6] is another temporary register. */
2205 output_block_move (operands, size_is_constant)
2207 int size_is_constant ATTRIBUTE_UNUSED;
2209 int align = INTVAL (operands[5]);
2210 unsigned long n_bytes = INTVAL (operands[4]);
2212 /* We can't move more than four bytes at a time because the PA
2213 has no longer integer move insns. (Could use fp mem ops?) */
2217 /* Note that we know each loop below will execute at least twice
2218 (else we would have open-coded the copy). */
2222 /* Pre-adjust the loop counter. */
2223 operands[4] = GEN_INT (n_bytes - 8);
2224 output_asm_insn ("ldi %4,%2", operands);
2227 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2228 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2229 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2230 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2231 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2233 /* Handle the residual. There could be up to 7 bytes of
2234 residual to copy! */
2235 if (n_bytes % 8 != 0)
2237 operands[4] = GEN_INT (n_bytes % 4);
2238 if (n_bytes % 8 >= 4)
2239 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2240 if (n_bytes % 4 != 0)
2241 output_asm_insn ("ldw 0(%1),%6", operands);
2242 if (n_bytes % 8 >= 4)
2243 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2244 if (n_bytes % 4 != 0)
2245 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2250 /* Pre-adjust the loop counter. */
2251 operands[4] = GEN_INT (n_bytes - 4);
2252 output_asm_insn ("ldi %4,%2", operands);
2255 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2256 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2257 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2258 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2259 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2261 /* Handle the residual. */
2262 if (n_bytes % 4 != 0)
2264 if (n_bytes % 4 >= 2)
2265 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2266 if (n_bytes % 2 != 0)
2267 output_asm_insn ("ldb 0(%1),%6", operands);
2268 if (n_bytes % 4 >= 2)
2269 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2270 if (n_bytes % 2 != 0)
2271 output_asm_insn ("stb %6,0(%0)", operands);
2276 /* Pre-adjust the loop counter. */
2277 operands[4] = GEN_INT (n_bytes - 2);
2278 output_asm_insn ("ldi %4,%2", operands);
2281 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2282 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2283 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2284 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2285 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2287 /* Handle the residual. */
2288 if (n_bytes % 2 != 0)
2290 output_asm_insn ("ldb 0(%1),%3", operands);
2291 output_asm_insn ("stb %3,0(%0)", operands);
2300 /* Count the number of insns necessary to handle this block move.
2302 Basic structure is the same as emit_block_move, except that we
2303 count insns rather than emit them. */
2306 compute_movstrsi_length (insn)
2309 rtx pat = PATTERN (insn);
2310 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2311 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
2312 unsigned int n_insns = 0;
2314 /* We can't move more than four bytes at a time because the PA
2315 has no longer integer move insns. (Could use fp mem ops?) */
2319 /* The basic copying loop. */
2323 if (n_bytes % (2 * align) != 0)
2325 if ((n_bytes % (2 * align)) >= align)
2328 if ((n_bytes % align) != 0)
2332 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2338 output_and (operands)
2341 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2343 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2344 int ls0, ls1, ms0, p, len;
2346 for (ls0 = 0; ls0 < 32; ls0++)
2347 if ((mask & (1 << ls0)) == 0)
2350 for (ls1 = ls0; ls1 < 32; ls1++)
2351 if ((mask & (1 << ls1)) != 0)
2354 for (ms0 = ls1; ms0 < 32; ms0++)
2355 if ((mask & (1 << ms0)) == 0)
2368 operands[2] = GEN_INT (len);
2369 return "{extru|extrw,u} %1,31,%2,%0";
2373 /* We could use this `depi' for the case above as well, but `depi'
2374 requires one more register file access than an `extru'. */
2379 operands[2] = GEN_INT (p);
2380 operands[3] = GEN_INT (len);
2381 return "{depi|depwi} 0,%2,%3,%0";
2385 return "and %1,%2,%0";
2388 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2389 storing the result in operands[0]. */
2391 output_64bit_and (operands)
2394 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2396 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2397 int ls0, ls1, ms0, p, len;
2399 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2400 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2403 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2404 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2407 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2408 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2411 if (ms0 != HOST_BITS_PER_WIDE_INT)
2414 if (ls1 == HOST_BITS_PER_WIDE_INT)
2421 operands[2] = GEN_INT (len);
2422 return "extrd,u %1,63,%2,%0";
2426 /* We could use this `depi' for the case above as well, but `depi'
2427 requires one more register file access than an `extru'. */
2432 operands[2] = GEN_INT (p);
2433 operands[3] = GEN_INT (len);
2434 return "depdi 0,%2,%3,%0";
2438 return "and %1,%2,%0";
2442 output_ior (operands)
2445 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2446 int bs0, bs1, p, len;
2448 if (INTVAL (operands[2]) == 0)
2449 return "copy %1,%0";
2451 for (bs0 = 0; bs0 < 32; bs0++)
2452 if ((mask & (1 << bs0)) != 0)
2455 for (bs1 = bs0; bs1 < 32; bs1++)
2456 if ((mask & (1 << bs1)) == 0)
2459 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2465 operands[2] = GEN_INT (p);
2466 operands[3] = GEN_INT (len);
2467 return "{depi|depwi} -1,%2,%3,%0";
2470 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2471 storing the result in operands[0]. */
2473 output_64bit_ior (operands)
2476 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2477 int bs0, bs1, p, len;
2479 if (INTVAL (operands[2]) == 0)
2480 return "copy %1,%0";
2482 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2483 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2486 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2487 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2490 if (bs1 != HOST_BITS_PER_WIDE_INT
2491 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2497 operands[2] = GEN_INT (p);
2498 operands[3] = GEN_INT (len);
2499 return "depdi -1,%2,%3,%0";
2502 /* Output an ascii string. */
2504 output_ascii (file, p, size)
2506 const unsigned char *p;
2511 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2513 /* The HP assembler can only take strings of 256 characters at one
2514 time. This is a limitation on input line length, *not* the
2515 length of the string. Sigh. Even worse, it seems that the
2516 restriction is in number of input characters (see \xnn &
2517 \whatever). So we have to do this very carefully. */
2519 fputs ("\t.STRING \"", file);
2522 for (i = 0; i < size; i += 4)
2526 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2528 register unsigned int c = p[i + io];
2530 if (c == '\"' || c == '\\')
2531 partial_output[co++] = '\\';
2532 if (c >= ' ' && c < 0177)
2533 partial_output[co++] = c;
2537 partial_output[co++] = '\\';
2538 partial_output[co++] = 'x';
2539 hexd = c / 16 - 0 + '0';
2541 hexd -= '9' - 'a' + 1;
2542 partial_output[co++] = hexd;
2543 hexd = c % 16 - 0 + '0';
2545 hexd -= '9' - 'a' + 1;
2546 partial_output[co++] = hexd;
2549 if (chars_output + co > 243)
2551 fputs ("\"\n\t.STRING \"", file);
2554 fwrite (partial_output, 1, co, file);
2558 fputs ("\"\n", file);
2561 /* Try to rewrite floating point comparisons & branches to avoid
2562 useless add,tr insns.
2564 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2565 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2566 first attempt to remove useless add,tr insns. It is zero
2567 for the second pass as reorg sometimes leaves bogus REG_DEAD
2570 When CHECK_NOTES is zero we can only eliminate add,tr insns
2571 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2574 remove_useless_addtr_insns (insns, check_notes)
2579 static int pass = 0;
2581 /* This is fairly cheap, so always run it when optimizing. */
2585 int fbranch_count = 0;
2587 /* Walk all the insns in this function looking for fcmp & fbranch
2588 instructions. Keep track of how many of each we find. */
2589 insns = get_insns ();
2590 for (insn = insns; insn; insn = next_insn (insn))
2594 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2595 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2598 tmp = PATTERN (insn);
2600 /* It must be a set. */
2601 if (GET_CODE (tmp) != SET)
2604 /* If the destination is CCFP, then we've found an fcmp insn. */
2605 tmp = SET_DEST (tmp);
2606 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2612 tmp = PATTERN (insn);
2613 /* If this is an fbranch instruction, bump the fbranch counter. */
2614 if (GET_CODE (tmp) == SET
2615 && SET_DEST (tmp) == pc_rtx
2616 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2617 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2618 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2619 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2627 /* Find all floating point compare + branch insns. If possible,
2628 reverse the comparison & the branch to avoid add,tr insns. */
2629 for (insn = insns; insn; insn = next_insn (insn))
2633 /* Ignore anything that isn't an INSN. */
2634 if (GET_CODE (insn) != INSN)
2637 tmp = PATTERN (insn);
2639 /* It must be a set. */
2640 if (GET_CODE (tmp) != SET)
2643 /* The destination must be CCFP, which is register zero. */
2644 tmp = SET_DEST (tmp);
2645 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2648 /* INSN should be a set of CCFP.
2650 See if the result of this insn is used in a reversed FP
2651 conditional branch. If so, reverse our condition and
2652 the branch. Doing so avoids useless add,tr insns. */
2653 next = next_insn (insn);
2656 /* Jumps, calls and labels stop our search. */
2657 if (GET_CODE (next) == JUMP_INSN
2658 || GET_CODE (next) == CALL_INSN
2659 || GET_CODE (next) == CODE_LABEL)
2662 /* As does another fcmp insn. */
2663 if (GET_CODE (next) == INSN
2664 && GET_CODE (PATTERN (next)) == SET
2665 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2666 && REGNO (SET_DEST (PATTERN (next))) == 0)
2669 next = next_insn (next);
2672 /* Is NEXT_INSN a branch? */
2674 && GET_CODE (next) == JUMP_INSN)
2676 rtx pattern = PATTERN (next);
2678 /* If it a reversed fp conditional branch (eg uses add,tr)
2679 and CCFP dies, then reverse our conditional and the branch
2680 to avoid the add,tr. */
2681 if (GET_CODE (pattern) == SET
2682 && SET_DEST (pattern) == pc_rtx
2683 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2684 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2685 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2686 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2687 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2688 && (fcmp_count == fbranch_count
2690 && find_regno_note (next, REG_DEAD, 0))))
2692 /* Reverse the branch. */
2693 tmp = XEXP (SET_SRC (pattern), 1);
2694 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2695 XEXP (SET_SRC (pattern), 2) = tmp;
2696 INSN_CODE (next) = -1;
2698 /* Reverse our condition. */
2699 tmp = PATTERN (insn);
2700 PUT_CODE (XEXP (tmp, 1),
2701 (reverse_condition_maybe_unordered
2702 (GET_CODE (XEXP (tmp, 1)))));
2712 /* You may have trouble believing this, but this is the 32 bit HP-PA
2717 Variable arguments (optional; any number may be allocated)
2719 SP-(4*(N+9)) arg word N
2724 Fixed arguments (must be allocated; may remain unused)
2733 SP-32 External Data Pointer (DP)
2735 SP-24 External/stub RP (RP')
2739 SP-8 Calling Stub RP (RP'')
2744 SP-0 Stack Pointer (points to next available address)
2748 /* This function saves registers as follows. Registers marked with ' are
2749 this function's registers (as opposed to the previous function's).
2750 If a frame_pointer isn't needed, r4 is saved as a general register;
2751 the space for the frame pointer is still allocated, though, to keep
2757 SP (FP') Previous FP
2758 SP + 4 Alignment filler (sigh)
2759 SP + 8 Space for locals reserved here.
2763 SP + n All call saved register used.
2767 SP + o All call saved fp registers used.
2771 SP + p (SP') points to next available address.
2775 /* Global variables set by FUNCTION_PROLOGUE. */
2776 /* Size of frame. Need to know this to emit return insns from
2778 static int actual_fsize;
2779 static int local_fsize, save_fregs;
2781 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2782 Handle case where DISP > 8k by using the add_high_const patterns.
2784 Note in DISP > 8k case, we will leave the high part of the address
2785 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2788 store_reg (reg, disp, base)
2789 int reg, disp, base;
2791 rtx i, dest, src, basereg;
2793 src = gen_rtx_REG (word_mode, reg);
2794 basereg = gen_rtx_REG (Pmode, base);
2795 if (VAL_14_BITS_P (disp))
2797 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2798 i = emit_move_insn (dest, src);
2802 rtx delta = GEN_INT (disp);
2803 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
2804 rtx tmpreg = gen_rtx_REG (Pmode, 1);
2805 emit_move_insn (tmpreg, high);
2806 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
2807 i = emit_move_insn (dest, src);
2812 /* Emit RTL to set REG to the value specified by BASE+DISP.
2813 Handle case where DISP > 8k by using the add_high_const patterns.
2815 Note in DISP > 8k case, we will leave the high part of the address
2816 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2819 set_reg_plus_d (reg, base, disp)
2820 int reg, base, disp;
2824 if (VAL_14_BITS_P (disp))
2826 i = emit_move_insn (gen_rtx_REG (Pmode, reg),
2827 plus_constant (gen_rtx_REG (Pmode, base), disp));
2831 rtx delta = GEN_INT (disp);
2832 emit_move_insn (gen_rtx_REG (Pmode, 1),
2833 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, base),
2834 gen_rtx_HIGH (Pmode, delta)));
2835 i = emit_move_insn (gen_rtx_REG (Pmode, reg),
2836 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
2843 compute_frame_size (size, fregs_live)
2849 /* Space for frame pointer + filler. If any frame is allocated
2850 we need to add this in because of STARTING_FRAME_OFFSET.
2852 Similar code also appears in hppa_expand_prologue. Change both
2853 of them at the same time. */
2854 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
2856 /* Account for space used by the callee general register saves. */
2857 for (i = 18; i >= 3; i--)
2858 if (regs_ever_live[i])
2859 fsize += UNITS_PER_WORD;
2861 /* Round the stack. */
2862 fsize = (fsize + 7) & ~7;
2864 /* Account for space used by the callee floating point register saves. */
2865 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
2866 if (regs_ever_live[i]
2867 || (! TARGET_64BIT && regs_ever_live[i + 1]))
2872 /* We always save both halves of the FP register, so always
2873 increment the frame size by 8 bytes. */
2877 /* The various ABIs include space for the outgoing parameters in the
2878 size of the current function's stack frame. */
2879 fsize += current_function_outgoing_args_size;
2881 /* Allocate space for the fixed frame marker. This space must be
2882 allocated for any function that makes calls or otherwise allocates
2884 if (!current_function_is_leaf || fsize)
2887 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
2891 output_function_prologue (file, size)
2893 int size ATTRIBUTE_UNUSED;
2895 /* The function's label and associated .PROC must never be
2896 separated and must be output *after* any profiling declarations
2897 to avoid changing spaces/subspaces within a procedure. */
2898 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
2899 fputs ("\t.PROC\n", file);
2901 /* hppa_expand_prologue does the dirty work now. We just need
2902 to output the assembler directives which denote the start
2904 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
2905 if (regs_ever_live[2])
2906 fputs (",CALLS,SAVE_RP", file);
2908 fputs (",NO_CALLS", file);
2910 if (frame_pointer_needed)
2911 fputs (",SAVE_SP", file);
2913 /* Pass on information about the number of callee register saves
2914 performed in the prologue.
2916 The compiler is supposed to pass the highest register number
2917 saved, the assembler then has to adjust that number before
2918 entering it into the unwind descriptor (to account for any
2919 caller saved registers with lower register numbers than the
2920 first callee saved register). */
2922 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
2925 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
2927 fputs ("\n\t.ENTRY\n", file);
2929 /* If we're using GAS and not using the portable runtime model, then
2930 we don't need to accumulate the total number of code bytes. */
2931 if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
2932 total_code_bytes = 0;
2933 else if (INSN_ADDRESSES_SET_P ())
2935 unsigned int old_total = total_code_bytes;
2937 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_insn ()));
2938 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
2940 /* Be prepared to handle overflows. */
2941 total_code_bytes = old_total > total_code_bytes ? -1 : total_code_bytes;
2944 total_code_bytes = -1;
2946 remove_useless_addtr_insns (get_insns (), 0);
2954 RTX_FRAME_RELATED_P (insn) = 1; \
2958 #define FRP(INSN) INSN
2962 hppa_expand_prologue ()
2964 extern char call_used_regs[];
2965 int size = get_frame_size ();
2966 int merge_sp_adjust_with_store = 0;
2968 rtx tmpreg, size_rtx;
2974 /* Allocate space for frame pointer + filler. If any frame is allocated
2975 we need to add this in because of STARTING_FRAME_OFFSET.
2977 Similar code also appears in compute_frame_size. Change both
2978 of them at the same time. */
2979 local_fsize = size + (size || frame_pointer_needed
2980 ? STARTING_FRAME_OFFSET : 0);
2982 actual_fsize = compute_frame_size (size, &save_fregs);
2984 /* Compute a few things we will use often. */
2985 tmpreg = gen_rtx_REG (word_mode, 1);
2986 size_rtx = GEN_INT (actual_fsize);
2988 /* Save RP first. The calling conventions manual states RP will
2989 always be stored into the caller's frame at sp - 20 or sp - 16
2990 depending on which ABI is in use. */
2991 if (regs_ever_live[2])
2992 FRP (store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM));
2994 /* Allocate the local frame and set up the frame pointer if needed. */
2995 if (actual_fsize != 0)
2997 if (frame_pointer_needed)
2999 /* Copy the old frame pointer temporarily into %r1. Set up the
3000 new stack pointer, then store away the saved old frame pointer
3001 into the stack at sp+actual_fsize and at the same time update
3002 the stack pointer by actual_fsize bytes. Two versions, first
3003 handles small (<8k) frames. The second handles large (>=8k)
3005 emit_move_insn (tmpreg, frame_pointer_rtx);
3006 FRP (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx));
3007 if (VAL_14_BITS_P (actual_fsize))
3009 rtx insn = emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
3014 RTX_FRAME_RELATED_P (insn) = 1;
3016 gen_rtx_SET (VOIDmode,
3017 gen_rtx_MEM (word_mode,
3020 gen_rtx_SET (VOIDmode,
3022 gen_rtx_PLUS (word_mode,
3026 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3027 gen_rtx_SEQUENCE (VOIDmode, vec),
3033 /* It is incorrect to store the saved frame pointer at *sp,
3034 then increment sp (writes beyond the current stack boundary).
3036 So instead use stwm to store at *sp and post-increment the
3037 stack pointer as an atomic operation. Then increment sp to
3038 finish allocating the new frame. */
3039 int adjust1 = 8192 - 64;
3040 int adjust2 = actual_fsize - adjust1;
3041 rtx delta = GEN_INT (adjust1);
3042 rtx insn = emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
3047 RTX_FRAME_RELATED_P (insn) = 1;
3049 gen_rtx_SET (VOIDmode,
3050 gen_rtx_MEM (word_mode,
3053 gen_rtx_SET (VOIDmode,
3055 gen_rtx_PLUS (word_mode,
3059 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3060 gen_rtx_SEQUENCE (VOIDmode, vec),
3064 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3065 STACK_POINTER_REGNUM,
3068 /* Prevent register spills from being scheduled before the
3069 stack pointer is raised. Necessary as we will be storing
3070 registers using the frame pointer as a base register, and
3071 we happen to set fp before raising sp. */
3072 emit_insn (gen_blockage ());
3074 /* no frame pointer needed. */
3077 /* In some cases we can perform the first callee register save
3078 and allocating the stack frame at the same time. If so, just
3079 make a note of it and defer allocating the frame until saving
3080 the callee registers. */
3081 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3082 merge_sp_adjust_with_store = 1;
3083 /* Can not optimize. Adjust the stack frame by actual_fsize
3086 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3087 STACK_POINTER_REGNUM,
3092 /* Normal register save.
3094 Do not save the frame pointer in the frame_pointer_needed case. It
3095 was done earlier. */
3096 if (frame_pointer_needed)
3098 for (i = 18, offset = local_fsize; i >= 4; i--)
3099 if (regs_ever_live[i] && ! call_used_regs[i])
3101 FRP (store_reg (i, offset, FRAME_POINTER_REGNUM));
3102 offset += UNITS_PER_WORD;
3105 /* Account for %r3 which is saved in a special place. */
3108 /* No frame pointer needed. */
3111 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3112 if (regs_ever_live[i] && ! call_used_regs[i])
3114 /* If merge_sp_adjust_with_store is nonzero, then we can
3115 optimize the first GR save. */
3116 if (merge_sp_adjust_with_store)
3118 rtx delta = GEN_INT (-offset);
3119 merge_sp_adjust_with_store = 0;
3120 FRP (emit_insn (gen_post_store (stack_pointer_rtx,
3121 gen_rtx_REG (word_mode, i),
3125 FRP (store_reg (i, offset, STACK_POINTER_REGNUM));
3126 offset += UNITS_PER_WORD;
3130 /* If we wanted to merge the SP adjustment with a GR save, but we never
3131 did any GR saves, then just emit the adjustment here. */
3132 if (merge_sp_adjust_with_store)
3133 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3134 STACK_POINTER_REGNUM,
3138 /* The hppa calling conventions say that %r19, the pic offset
3139 register, is saved at sp - 32 (in this function's frame)
3140 when generating PIC code. FIXME: What is the correct thing
3141 to do for functions which make no calls and allocate no
3142 frame? Do we need to allocate a frame, or can we just omit
3143 the save? For now we'll just omit the save. */
3144 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3145 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3147 /* Align pointer properly (doubleword boundary). */
3148 offset = (offset + 7) & ~7;
3150 /* Floating point register store. */
3153 /* First get the frame or stack pointer to the start of the FP register
3155 if (frame_pointer_needed)
3156 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset));
3158 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM, offset));
3160 /* Now actually save the FP registers. */
3161 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3163 if (regs_ever_live[i]
3164 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3167 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3168 reg = gen_rtx_REG (DFmode, i);
3169 FRP (emit_move_insn (addr, reg));
3176 /* ?!? Do we want frame notes in the epilogue yet? */
3177 #undef DO_FRAME_NOTES
3178 #define DO_FRAME_NOTES 0
3180 #define FRP(INSN) INSN
3182 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3183 Handle case where DISP > 8k by using the add_high_const patterns. */
3186 load_reg (reg, disp, base)
3187 int reg, disp, base;
3189 rtx i, src, dest, basereg;
3191 dest = gen_rtx_REG (word_mode, reg);
3192 basereg = gen_rtx_REG (Pmode, base);
3193 if (VAL_14_BITS_P (disp))
3195 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3196 i = emit_move_insn (dest, src);
3200 rtx delta = GEN_INT (disp);
3201 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3202 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3203 emit_move_insn (tmpreg, high);
3204 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3205 i = emit_move_insn (dest, src);
3211 output_function_epilogue (file, size)
3213 int size ATTRIBUTE_UNUSED;
3215 rtx insn = get_last_insn ();
3217 /* hppa_expand_epilogue does the dirty work now. We just need
3218 to output the assembler directives which denote the end
3221 To make debuggers happy, emit a nop if the epilogue was completely
3222 eliminated due to a volatile call as the last insn in the
3223 current function. That way the return address (in %r2) will
3224 always point to a valid instruction in the current function. */
3226 /* Get the last real insn. */
3227 if (GET_CODE (insn) == NOTE)
3228 insn = prev_real_insn (insn);
3230 /* If it is a sequence, then look inside. */
3231 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3232 insn = XVECEXP (PATTERN (insn), 0, 0);
3234 /* If insn is a CALL_INSN, then it must be a call to a volatile
3235 function (otherwise there would be epilogue insns). */
3236 if (insn && GET_CODE (insn) == CALL_INSN)
3237 fputs ("\tnop\n", file);
3239 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3243 hppa_expand_epilogue ()
3247 int merge_sp_adjust_with_load = 0;
3250 /* We will use this often. */
3251 tmpreg = gen_rtx_REG (word_mode, 1);
3253 /* Try to restore RP early to avoid load/use interlocks when
3254 RP gets used in the return (bv) instruction. This appears to still
3255 be necessary even when we schedule the prologue and epilogue. */
3256 if (regs_ever_live [2])
3258 ret_off = TARGET_64BIT ? -16 : -20;
3259 if (frame_pointer_needed)
3261 FRP (load_reg (2, ret_off, FRAME_POINTER_REGNUM));
3266 /* No frame pointer, and stack is smaller than 8k. */
3267 if (VAL_14_BITS_P (ret_off - actual_fsize))
3269 FRP (load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM));
3275 /* General register restores. */
3276 if (frame_pointer_needed)
3278 for (i = 18, offset = local_fsize; i >= 4; i--)
3279 if (regs_ever_live[i] && ! call_used_regs[i])
3281 FRP (load_reg (i, offset, FRAME_POINTER_REGNUM));
3282 offset += UNITS_PER_WORD;
3287 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3289 if (regs_ever_live[i] && ! call_used_regs[i])
3291 /* Only for the first load.
3292 merge_sp_adjust_with_load holds the register load
3293 with which we will merge the sp adjustment. */
3294 if (merge_sp_adjust_with_load == 0
3296 && VAL_14_BITS_P (-actual_fsize))
3297 merge_sp_adjust_with_load = i;
3299 FRP (load_reg (i, offset, STACK_POINTER_REGNUM));
3300 offset += UNITS_PER_WORD;
3305 /* Align pointer properly (doubleword boundary). */
3306 offset = (offset + 7) & ~7;
3308 /* FP register restores. */
3311 /* Adjust the register to index off of. */
3312 if (frame_pointer_needed)
3313 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset));
3315 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM, offset));
3317 /* Actually do the restores now. */
3318 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3319 if (regs_ever_live[i]
3320 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3322 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3323 rtx dest = gen_rtx_REG (DFmode, i);
3324 FRP (emit_move_insn (dest, src));
3328 /* Emit a blockage insn here to keep these insns from being moved to
3329 an earlier spot in the epilogue, or into the main instruction stream.
3331 This is necessary as we must not cut the stack back before all the
3332 restores are finished. */
3333 emit_insn (gen_blockage ());
3335 /* Reset stack pointer (and possibly frame pointer). The stack
3336 pointer is initially set to fp + 64 to avoid a race condition. */
3337 if (frame_pointer_needed)
3339 rtx delta = GEN_INT (-64);
3340 FRP (set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64));
3341 FRP (emit_insn (gen_pre_load (frame_pointer_rtx,
3345 /* If we were deferring a callee register restore, do it now. */
3346 else if (merge_sp_adjust_with_load)
3348 rtx delta = GEN_INT (-actual_fsize);
3349 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3350 FRP (emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)));
3352 else if (actual_fsize != 0)
3353 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3354 STACK_POINTER_REGNUM,
3357 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3358 frame greater than 8k), do so now. */
3360 FRP (load_reg (2, ret_off, STACK_POINTER_REGNUM));
3363 /* Set up a callee saved register for the pic offset table register. */
3365 hppa_init_pic_save ()
3369 picreg = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM);
3370 PIC_OFFSET_TABLE_SAVE_RTX = gen_reg_rtx (Pmode);
3371 RTX_UNCHANGING_P (PIC_OFFSET_TABLE_SAVE_RTX) = 1;
3372 insn = gen_rtx_SET (VOIDmode, PIC_OFFSET_TABLE_SAVE_RTX, picreg);
3374 /* Emit the insn at the beginning of the function after the prologue. */
3375 if (tail_recursion_reentry)
3376 emit_insn_before (insn, tail_recursion_reentry);
3378 /* We must have been called via PROFILE_HOOK. */
3383 hppa_profile_hook (label_no)
3384 int label_no ATTRIBUTE_UNUSED;
3388 /* No profiling for inline functions. We don't want extra calls to
3389 _mcount when the inline function is expanded. Even if that made
3390 sense, it wouldn't work here as there is no function label for
3391 the inline expansion. */
3392 if (DECL_INLINE (cfun->decl))
3396 emit_move_insn (arg_pointer_rtx,
3397 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3400 if (flag_pic && PIC_OFFSET_TABLE_SAVE_RTX == NULL_RTX)
3401 hppa_init_pic_save ();
3403 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3405 #ifndef NO_PROFILE_COUNTERS
3407 rtx count_label_rtx, addr, r24;
3408 char label_name[16];
3410 ASM_GENERATE_INTERNAL_LABEL (label_name, "LP", label_no);
3411 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (label_name));
3417 current_function_uses_pic_offset_table = 1;
3418 tmpreg = gen_rtx_REG (Pmode, 1);
3419 emit_move_insn (tmpreg,
3420 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3421 gen_rtx_HIGH (Pmode, count_label_rtx)));
3422 addr = gen_rtx_MEM (Pmode,
3423 gen_rtx_LO_SUM (Pmode, tmpreg, count_label_rtx));
3427 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3428 emit_move_insn (tmpreg, gen_rtx_HIGH (Pmode, count_label_rtx));
3429 addr = gen_rtx_LO_SUM (Pmode, tmpreg, count_label_rtx);
3431 r24 = gen_rtx_REG (Pmode, 24);
3432 emit_move_insn (r24, addr);
3434 /* %r25 is set from within the output pattern. */
3436 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3437 GEN_INT (TARGET_64BIT ? 24 : 12),
3438 XEXP (DECL_RTL (cfun->decl), 0)));
3440 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3443 /* %r25 is set from within the output pattern. */
3445 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3446 GEN_INT (TARGET_64BIT ? 16 : 8),
3447 XEXP (DECL_RTL (cfun->decl), 0)));
3450 /* Indicate the _mcount call cannot throw, nor will it execute a
3452 REG_NOTES (call_insn)
3453 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3457 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3459 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3461 emit_move_insn (pic_offset_table_rtx, PIC_OFFSET_TABLE_SAVE_RTX);
3465 /* Fetch the return address for the frame COUNT steps up from
3466 the current frame, after the prologue. FRAMEADDR is the
3467 frame pointer of the COUNT frame.
3469 We want to ignore any export stub remnants here.
3471 The value returned is used in two different ways:
3473 1. To find a function's caller.
3475 2. To change the return address for a function.
3477 This function handles most instances of case 1; however, it will
3478 fail if there are two levels of stubs to execute on the return
3479 path. The only way I believe that can happen is if the return value
3480 needs a parameter relocation, which never happens for C code.
3482 This function handles most instances of case 2; however, it will
3483 fail if we did not originally have stub code on the return path
3484 but will need code on the new return path. This can happen if
3485 the caller & callee are both in the main program, but the new
3486 return location is in a shared library.
3488 To handle this correctly we need to set the return pointer at
3489 frame-20 to point to a return stub frame-24 to point to the
3490 location we wish to return to. */
3493 return_addr_rtx (count, frameaddr)
3494 int count ATTRIBUTE_UNUSED;
3502 return gen_rtx_MEM (Pmode, plus_constant (frameaddr, -16));
3504 if (TARGET_NO_SPACE_REGS)
3505 return gen_rtx_MEM (Pmode, plus_constant (frameaddr, -20));
3507 /* First, we start off with the normal return address pointer from
3510 saved_rp = gen_reg_rtx (Pmode);
3511 emit_move_insn (saved_rp, plus_constant (frameaddr, -20));
3513 /* Get pointer to the instruction stream. We have to mask out the
3514 privilege level from the two low order bits of the return address
3515 pointer here so that ins will point to the start of the first
3516 instruction that would have been executed if we returned. */
3517 ins = copy_to_reg (gen_rtx_AND (Pmode,
3518 copy_to_reg (gen_rtx_MEM (Pmode, saved_rp)),
3520 label = gen_label_rtx ();
3522 /* Check the instruction stream at the normal return address for the
3525 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3526 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3527 0x00011820 | stub+16: mtsp r1,sr0
3528 0xe0400002 | stub+20: be,n 0(sr0,rp)
3530 If it is an export stub, than our return address is really in
3533 emit_cmp_insn (gen_rtx_MEM (SImode, ins),
3534 GEN_INT (0x4bc23fd1),
3535 NE, NULL_RTX, SImode, 1, 0);
3536 emit_jump_insn (gen_bne (label));
3538 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3539 GEN_INT (0x004010a1),
3540 NE, NULL_RTX, SImode, 1, 0);
3541 emit_jump_insn (gen_bne (label));
3543 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3544 GEN_INT (0x00011820),
3545 NE, NULL_RTX, SImode, 1, 0);
3546 emit_jump_insn (gen_bne (label));
3548 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3549 GEN_INT (0xe0400002),
3550 NE, NULL_RTX, SImode, 1, 0);
3552 /* If there is no export stub then just use our initial guess of
3555 emit_jump_insn (gen_bne (label));
3557 /* Here we know that our return address pointer points to an export
3558 stub. We don't want to return the address of the export stub,
3559 but rather the return address that leads back into user code.
3560 That return address is stored at -24[frameaddr]. */
3562 emit_move_insn (saved_rp, plus_constant (frameaddr, -24));
3565 return gen_rtx_MEM (Pmode, memory_address (Pmode, saved_rp));
3568 /* This is only valid once reload has completed because it depends on
3569 knowing exactly how much (if any) frame there is and...
3571 It's only valid if there is no frame marker to de-allocate and...
3573 It's only valid if %r2 hasn't been saved into the caller's frame
3574 (we're not profiling and %r2 isn't live anywhere). */
3576 hppa_can_use_return_insn_p ()
3578 return (reload_completed
3579 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3580 && ! regs_ever_live[2]
3581 && ! frame_pointer_needed);
3585 emit_bcond_fp (code, operand0)
3589 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3590 gen_rtx_IF_THEN_ELSE (VOIDmode,
3591 gen_rtx_fmt_ee (code,
3593 gen_rtx_REG (CCFPmode, 0),
3595 gen_rtx_LABEL_REF (VOIDmode, operand0),
3601 gen_cmp_fp (code, operand0, operand1)
3603 rtx operand0, operand1;
3605 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3606 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3609 /* Adjust the cost of a scheduling dependency. Return the new cost of
3610 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3613 pa_adjust_cost (insn, link, dep_insn, cost)
3619 enum attr_type attr_type;
3621 /* Don't adjust costs for a pa8000 chip. */
3622 if (pa_cpu >= PROCESSOR_8000)
3625 if (! recog_memoized (insn))
3628 attr_type = get_attr_type (insn);
3630 if (REG_NOTE_KIND (link) == 0)
3632 /* Data dependency; DEP_INSN writes a register that INSN reads some
3635 if (attr_type == TYPE_FPSTORE)
3637 rtx pat = PATTERN (insn);
3638 rtx dep_pat = PATTERN (dep_insn);
3639 if (GET_CODE (pat) == PARALLEL)
3641 /* This happens for the fstXs,mb patterns. */
3642 pat = XVECEXP (pat, 0, 0);
3644 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3645 /* If this happens, we have to extend this to schedule
3646 optimally. Return 0 for now. */
3649 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
3651 if (! recog_memoized (dep_insn))
3653 /* DEP_INSN is writing its result to the register
3654 being stored in the fpstore INSN. */
3655 switch (get_attr_type (dep_insn))
3658 /* This cost 3 cycles, not 2 as the md says for the
3667 case TYPE_FPSQRTSGL:
3668 case TYPE_FPSQRTDBL:
3669 /* In these important cases, we save one cycle compared to
3670 when flop instruction feed each other. */
3679 /* For other data dependencies, the default cost specified in the
3683 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3685 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3688 if (attr_type == TYPE_FPLOAD)
3690 rtx pat = PATTERN (insn);
3691 rtx dep_pat = PATTERN (dep_insn);
3692 if (GET_CODE (pat) == PARALLEL)
3694 /* This happens for the fldXs,mb patterns. */
3695 pat = XVECEXP (pat, 0, 0);
3697 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3698 /* If this happens, we have to extend this to schedule
3699 optimally. Return 0 for now. */
3702 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3704 if (! recog_memoized (dep_insn))
3706 switch (get_attr_type (dep_insn))
3713 case TYPE_FPSQRTSGL:
3714 case TYPE_FPSQRTDBL:
3715 /* A fpload can't be issued until one cycle before a
3716 preceding arithmetic operation has finished if
3717 the target of the fpload is any of the sources
3718 (or destination) of the arithmetic operation. */
3726 else if (attr_type == TYPE_FPALU)
3728 rtx pat = PATTERN (insn);
3729 rtx dep_pat = PATTERN (dep_insn);
3730 if (GET_CODE (pat) == PARALLEL)
3732 /* This happens for the fldXs,mb patterns. */
3733 pat = XVECEXP (pat, 0, 0);
3735 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3736 /* If this happens, we have to extend this to schedule
3737 optimally. Return 0 for now. */
3740 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3742 if (! recog_memoized (dep_insn))
3744 switch (get_attr_type (dep_insn))
3748 case TYPE_FPSQRTSGL:
3749 case TYPE_FPSQRTDBL:
3750 /* An ALU flop can't be issued until two cycles before a
3751 preceding divide or sqrt operation has finished if
3752 the target of the ALU flop is any of the sources
3753 (or destination) of the divide or sqrt operation. */
3762 /* For other anti dependencies, the cost is 0. */
3765 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3767 /* Output dependency; DEP_INSN writes a register that INSN writes some
3769 if (attr_type == TYPE_FPLOAD)
3771 rtx pat = PATTERN (insn);
3772 rtx dep_pat = PATTERN (dep_insn);
3773 if (GET_CODE (pat) == PARALLEL)
3775 /* This happens for the fldXs,mb patterns. */
3776 pat = XVECEXP (pat, 0, 0);
3778 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3779 /* If this happens, we have to extend this to schedule
3780 optimally. Return 0 for now. */
3783 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3785 if (! recog_memoized (dep_insn))
3787 switch (get_attr_type (dep_insn))
3794 case TYPE_FPSQRTSGL:
3795 case TYPE_FPSQRTDBL:
3796 /* A fpload can't be issued until one cycle before a
3797 preceding arithmetic operation has finished if
3798 the target of the fpload is the destination of the
3799 arithmetic operation. */
3807 else if (attr_type == TYPE_FPALU)
3809 rtx pat = PATTERN (insn);
3810 rtx dep_pat = PATTERN (dep_insn);
3811 if (GET_CODE (pat) == PARALLEL)
3813 /* This happens for the fldXs,mb patterns. */
3814 pat = XVECEXP (pat, 0, 0);
3816 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3817 /* If this happens, we have to extend this to schedule
3818 optimally. Return 0 for now. */
3821 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3823 if (! recog_memoized (dep_insn))
3825 switch (get_attr_type (dep_insn))
3829 case TYPE_FPSQRTSGL:
3830 case TYPE_FPSQRTDBL:
3831 /* An ALU flop can't be issued until two cycles before a
3832 preceding divide or sqrt operation has finished if
3833 the target of the ALU flop is also the target of
3834 the divide or sqrt operation. */
3843 /* For other output dependencies, the cost is 0. */
3850 /* Return any length adjustment needed by INSN which already has its length
3851 computed as LENGTH. Return zero if no adjustment is necessary.
3853 For the PA: function calls, millicode calls, and backwards short
3854 conditional branches with unfilled delay slots need an adjustment by +1
3855 (to account for the NOP which will be inserted into the instruction stream).
3857 Also compute the length of an inline block move here as it is too
3858 complicated to express as a length attribute in pa.md. */
3860 pa_adjust_insn_length (insn, length)
3864 rtx pat = PATTERN (insn);
3866 /* Call insns which are *not* indirect and have unfilled delay slots. */
3867 if (GET_CODE (insn) == CALL_INSN)
3870 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
3871 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
3873 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
3874 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
3880 /* Jumps inside switch tables which have unfilled delay slots
3881 also need adjustment. */
3882 else if (GET_CODE (insn) == JUMP_INSN
3883 && simplejump_p (insn)
3884 && GET_MODE (insn) == SImode)
3886 /* Millicode insn with an unfilled delay slot. */
3887 else if (GET_CODE (insn) == INSN
3888 && GET_CODE (pat) != SEQUENCE
3889 && GET_CODE (pat) != USE
3890 && GET_CODE (pat) != CLOBBER
3891 && get_attr_type (insn) == TYPE_MILLI)
3893 /* Block move pattern. */
3894 else if (GET_CODE (insn) == INSN
3895 && GET_CODE (pat) == PARALLEL
3896 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3897 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
3898 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
3899 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
3900 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
3901 return compute_movstrsi_length (insn) - 4;
3902 /* Conditional branch with an unfilled delay slot. */
3903 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
3905 /* Adjust a short backwards conditional with an unfilled delay slot. */
3906 if (GET_CODE (pat) == SET
3908 && ! forward_branch_p (insn))
3910 else if (GET_CODE (pat) == PARALLEL
3911 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
3914 /* Adjust dbra insn with short backwards conditional branch with
3915 unfilled delay slot -- only for case where counter is in a
3916 general register register. */
3917 else if (GET_CODE (pat) == PARALLEL
3918 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
3919 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
3920 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
3922 && ! forward_branch_p (insn))
3930 /* Print operand X (an rtx) in assembler syntax to file FILE.
3931 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3932 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3935 print_operand (file, x, code)
3943 /* Output a 'nop' if there's nothing for the delay slot. */
3944 if (dbr_sequence_length () == 0)
3945 fputs ("\n\tnop", file);
3948 /* Output an nullification completer if there's nothing for the */
3949 /* delay slot or nullification is requested. */
3950 if (dbr_sequence_length () == 0 ||
3952 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
3956 /* Print out the second register name of a register pair.
3957 I.e., R (6) => 7. */
3958 fputs (reg_names[REGNO (x) + 1], file);
3961 /* A register or zero. */
3963 || (x == CONST0_RTX (DFmode))
3964 || (x == CONST0_RTX (SFmode)))
3966 fputs ("%r0", file);
3972 /* A register or zero (floating point). */
3974 || (x == CONST0_RTX (DFmode))
3975 || (x == CONST0_RTX (SFmode)))
3977 fputs ("%fr0", file);
3986 xoperands[0] = XEXP (XEXP (x, 0), 0);
3987 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
3988 output_global_address (file, xoperands[1], 0);
3989 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
3993 case 'C': /* Plain (C)ondition */
3995 switch (GET_CODE (x))
3998 fputs ("=", file); break;
4000 fputs ("<>", file); break;
4002 fputs (">", file); break;
4004 fputs (">=", file); break;
4006 fputs (">>=", file); break;
4008 fputs (">>", file); break;
4010 fputs ("<", file); break;
4012 fputs ("<=", file); break;
4014 fputs ("<<=", file); break;
4016 fputs ("<<", file); break;
4021 case 'N': /* Condition, (N)egated */
4022 switch (GET_CODE (x))
4025 fputs ("<>", file); break;
4027 fputs ("=", file); break;
4029 fputs ("<=", file); break;
4031 fputs ("<", file); break;
4033 fputs ("<<", file); break;
4035 fputs ("<<=", file); break;
4037 fputs (">=", file); break;
4039 fputs (">", file); break;
4041 fputs (">>", file); break;
4043 fputs (">>=", file); break;
4048 /* For floating point comparisons. Note that the output
4049 predicates are the complement of the desired mode. */
4051 switch (GET_CODE (x))
4054 fputs ("!=", file); break;
4056 fputs ("=", file); break;
4058 fputs ("!>", file); break;
4060 fputs ("!>=", file); break;
4062 fputs ("!<", file); break;
4064 fputs ("!<=", file); break;
4066 fputs ("!<>", file); break;
4068 fputs (">", file); break;
4070 fputs (">=", file); break;
4072 fputs ("<", file); break;
4074 fputs ("<=", file); break;
4076 fputs ("<>", file); break;
4078 fputs ("<=>", file); break;
4080 fputs ("!<=>", file); break;
4085 case 'S': /* Condition, operands are (S)wapped. */
4086 switch (GET_CODE (x))
4089 fputs ("=", file); break;
4091 fputs ("<>", file); break;
4093 fputs ("<", file); break;
4095 fputs ("<=", file); break;
4097 fputs ("<<=", file); break;
4099 fputs ("<<", file); break;
4101 fputs (">", file); break;
4103 fputs (">=", file); break;
4105 fputs (">>=", file); break;
4107 fputs (">>", file); break;
4112 case 'B': /* Condition, (B)oth swapped and negate. */
4113 switch (GET_CODE (x))
4116 fputs ("<>", file); break;
4118 fputs ("=", file); break;
4120 fputs (">=", file); break;
4122 fputs (">", file); break;
4124 fputs (">>", file); break;
4126 fputs (">>=", file); break;
4128 fputs ("<=", file); break;
4130 fputs ("<", file); break;
4132 fputs ("<<", file); break;
4134 fputs ("<<=", file); break;
4140 if (GET_CODE (x) == CONST_INT)
4142 fprintf (file, "%d", ~INTVAL (x));
4147 if (GET_CODE (x) == CONST_INT)
4149 fprintf (file, "%d", 64 - (INTVAL (x) & 63));
4154 if (GET_CODE (x) == CONST_INT)
4156 fprintf (file, "%d", 32 - (INTVAL (x) & 31));
4161 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4163 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4168 if (GET_CODE (x) == CONST_INT)
4170 fprintf (file, "%d", 63 - (INTVAL (x) & 63));
4175 if (GET_CODE (x) == CONST_INT)
4177 fprintf (file, "%d", 31 - (INTVAL (x) & 31));
4182 if (GET_CODE (x) == CONST_INT)
4187 switch (GET_CODE (XEXP (x, 0)))
4191 if (ASSEMBLER_DIALECT == 0)
4192 fputs ("s,mb", file);
4194 fputs (",mb", file);
4198 if (ASSEMBLER_DIALECT == 0)
4199 fputs ("s,ma", file);
4201 fputs (",ma", file);
4204 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4205 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4207 if (ASSEMBLER_DIALECT == 0)
4208 fputs ("x,s", file);
4212 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4216 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4222 output_global_address (file, x, 0);
4225 output_global_address (file, x, 1);
4227 case 0: /* Don't do anything special */
4232 compute_zdepwi_operands (INTVAL (x), op);
4233 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4239 compute_zdepdi_operands (INTVAL (x), op);
4240 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4244 /* We can get here from a .vtable_inherit due to our
4245 CONSTANT_ADDRESS_P rejecting perfectly good constant
4251 if (GET_CODE (x) == REG)
4253 fputs (reg_names [REGNO (x)], file);
4254 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4260 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4261 && (REGNO (x) & 1) == 0)
4264 else if (GET_CODE (x) == MEM)
4266 int size = GET_MODE_SIZE (GET_MODE (x));
4267 rtx base = NULL_RTX;
4268 switch (GET_CODE (XEXP (x, 0)))
4272 base = XEXP (XEXP (x, 0), 0);
4273 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4277 base = XEXP (XEXP (x, 0), 0);
4278 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4281 if (GET_CODE (XEXP (x, 0)) == PLUS
4282 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4283 fprintf (file, "%s(%s)",
4284 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4285 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4286 else if (GET_CODE (XEXP (x, 0)) == PLUS
4287 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4288 fprintf (file, "%s(%s)",
4289 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4290 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4292 output_address (XEXP (x, 0));
4297 output_addr_const (file, x);
4300 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4303 output_global_address (file, x, round_constant)
4309 /* Imagine (high (const (plus ...))). */
4310 if (GET_CODE (x) == HIGH)
4313 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4314 assemble_name (file, XSTR (x, 0));
4315 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4317 assemble_name (file, XSTR (x, 0));
4318 fputs ("-$global$", file);
4320 else if (GET_CODE (x) == CONST)
4322 const char *sep = "";
4323 int offset = 0; /* assembler wants -$global$ at end */
4324 rtx base = NULL_RTX;
4326 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4328 base = XEXP (XEXP (x, 0), 0);
4329 output_addr_const (file, base);
4331 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4332 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4335 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4337 base = XEXP (XEXP (x, 0), 1);
4338 output_addr_const (file, base);
4340 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4341 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4344 /* How bogus. The compiler is apparently responsible for
4345 rounding the constant if it uses an LR field selector.
4347 The linker and/or assembler seem a better place since
4348 they have to do this kind of thing already.
4350 If we fail to do this, HP's optimizing linker may eliminate
4351 an addil, but not update the ldw/stw/ldo instruction that
4352 uses the result of the addil. */
4354 offset = ((offset + 0x1000) & ~0x1fff);
4356 if (GET_CODE (XEXP (x, 0)) == PLUS)
4366 else if (GET_CODE (XEXP (x, 0)) == MINUS
4367 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4371 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4372 fputs ("-$global$", file);
4374 fprintf (file, "%s%d", sep, offset);
4377 output_addr_const (file, x);
4381 output_deferred_plabels (file)
4385 /* If we have deferred plabels, then we need to switch into the data
4386 section and align it to a 4 byte boundary before we output the
4387 deferred plabels. */
4388 if (n_deferred_plabels)
4391 ASM_OUTPUT_ALIGN (file, 2);
4394 /* Now output the deferred plabels. */
4395 for (i = 0; i < n_deferred_plabels; i++)
4397 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4398 assemble_integer (gen_rtx_SYMBOL_REF (VOIDmode,
4399 deferred_plabels[i].name), 4, 1);
4403 /* HP's millicode routines mean something special to the assembler.
4404 Keep track of which ones we have used. */
4406 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
4407 static void import_milli PARAMS ((enum millicodes));
4408 static char imported[(int) end1000];
4409 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4410 static char import_string[] = ".IMPORT $$....,MILLICODE";
4411 #define MILLI_START 10
4415 enum millicodes code;
4417 char str[sizeof (import_string)];
4419 if (!imported[(int) code])
4421 imported[(int) code] = 1;
4422 strcpy (str, import_string);
4423 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4424 output_asm_insn (str, 0);
4428 /* The register constraints have put the operands and return value in
4429 the proper registers. */
4432 output_mul_insn (unsignedp, insn)
4433 int unsignedp ATTRIBUTE_UNUSED;
4436 import_milli (mulI);
4437 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4440 /* Emit the rtl for doing a division by a constant. */
4442 /* Do magic division millicodes exist for this value? */
4443 static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4446 /* We'll use an array to keep track of the magic millicodes and
4447 whether or not we've used them already. [n][0] is signed, [n][1] is
4450 static int div_milli[16][2];
4453 div_operand (op, mode)
4455 enum machine_mode mode;
4457 return (mode == SImode
4458 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4459 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4460 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4464 emit_hpdiv_const (operands, unsignedp)
4468 if (GET_CODE (operands[2]) == CONST_INT
4469 && INTVAL (operands[2]) > 0
4470 && INTVAL (operands[2]) < 16
4471 && magic_milli[INTVAL (operands[2])])
4473 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4476 (PARALLEL, VOIDmode,
4477 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4478 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4480 gen_rtx_REG (SImode, 26),
4482 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4483 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4484 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4485 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4486 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 31)))));
4487 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4494 output_div_insn (operands, unsignedp, insn)
4501 /* If the divisor is a constant, try to use one of the special
4503 if (GET_CODE (operands[0]) == CONST_INT)
4505 static char buf[100];
4506 divisor = INTVAL (operands[0]);
4507 if (!div_milli[divisor][unsignedp])
4509 div_milli[divisor][unsignedp] = 1;
4511 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4513 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4517 sprintf (buf, "$$divU_%d", INTVAL (operands[0]));
4518 return output_millicode_call (insn,
4519 gen_rtx_SYMBOL_REF (SImode, buf));
4523 sprintf (buf, "$$divI_%d", INTVAL (operands[0]));
4524 return output_millicode_call (insn,
4525 gen_rtx_SYMBOL_REF (SImode, buf));
4528 /* Divisor isn't a special constant. */
4533 import_milli (divU);
4534 return output_millicode_call (insn,
4535 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4539 import_milli (divI);
4540 return output_millicode_call (insn,
4541 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4546 /* Output a $$rem millicode to do mod. */
4549 output_mod_insn (unsignedp, insn)
4555 import_milli (remU);
4556 return output_millicode_call (insn,
4557 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4561 import_milli (remI);
4562 return output_millicode_call (insn,
4563 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4568 output_arg_descriptor (call_insn)
4571 const char *arg_regs[4];
4572 enum machine_mode arg_mode;
4574 int i, output_flag = 0;
4577 /* We neither need nor want argument location descriptors for the
4578 64bit runtime environment or the ELF32 environment. */
4579 if (TARGET_64BIT || TARGET_ELF32)
4582 for (i = 0; i < 4; i++)
4585 /* Specify explicitly that no argument relocations should take place
4586 if using the portable runtime calling conventions. */
4587 if (TARGET_PORTABLE_RUNTIME)
4589 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4594 if (GET_CODE (call_insn) != CALL_INSN)
4596 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4598 rtx use = XEXP (link, 0);
4600 if (! (GET_CODE (use) == USE
4601 && GET_CODE (XEXP (use, 0)) == REG
4602 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4605 arg_mode = GET_MODE (XEXP (use, 0));
4606 regno = REGNO (XEXP (use, 0));
4607 if (regno >= 23 && regno <= 26)
4609 arg_regs[26 - regno] = "GR";
4610 if (arg_mode == DImode)
4611 arg_regs[25 - regno] = "GR";
4613 else if (regno >= 32 && regno <= 39)
4615 if (arg_mode == SFmode)
4616 arg_regs[(regno - 32) / 2] = "FR";
4619 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4620 arg_regs[(regno - 34) / 2] = "FR";
4621 arg_regs[(regno - 34) / 2 + 1] = "FU";
4623 arg_regs[(regno - 34) / 2] = "FU";
4624 arg_regs[(regno - 34) / 2 + 1] = "FR";
4629 fputs ("\t.CALL ", asm_out_file);
4630 for (i = 0; i < 4; i++)
4635 fputc (',', asm_out_file);
4636 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4639 fputc ('\n', asm_out_file);
4642 /* Return the class of any secondary reload register that is needed to
4643 move IN into a register in class CLASS using mode MODE.
4645 Profiling has showed this routine and its descendants account for
4646 a significant amount of compile time (~7%). So it has been
4647 optimized to reduce redundant computations and eliminate useless
4650 It might be worthwhile to try and make this a leaf function too. */
4653 secondary_reload_class (class, mode, in)
4654 enum reg_class class;
4655 enum machine_mode mode;
4658 int regno, is_symbolic;
4660 /* Trying to load a constant into a FP register during PIC code
4661 generation will require %r1 as a scratch register. */
4663 && GET_MODE_CLASS (mode) == MODE_INT
4664 && FP_REG_CLASS_P (class)
4665 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4668 /* Profiling showed the PA port spends about 1.3% of its compilation
4669 time in true_regnum from calls inside secondary_reload_class. */
4671 if (GET_CODE (in) == REG)
4674 if (regno >= FIRST_PSEUDO_REGISTER)
4675 regno = true_regnum (in);
4677 else if (GET_CODE (in) == SUBREG)
4678 regno = true_regnum (in);
4682 /* If we have something like (mem (mem (...)), we can safely assume the
4683 inner MEM will end up in a general register after reloading, so there's
4684 no need for a secondary reload. */
4685 if (GET_CODE (in) == MEM
4686 && GET_CODE (XEXP (in, 0)) == MEM)
4689 /* Handle out of range displacement for integer mode loads/stores of
4691 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
4692 && GET_MODE_CLASS (mode) == MODE_INT
4693 && FP_REG_CLASS_P (class))
4694 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
4695 return GENERAL_REGS;
4697 /* A SAR<->FP register copy requires a secondary register (GPR) as
4698 well as secondary memory. */
4699 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4700 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
4701 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
4702 return GENERAL_REGS;
4704 if (GET_CODE (in) == HIGH)
4707 /* Profiling has showed GCC spends about 2.6% of its compilation
4708 time in symbolic_operand from calls inside secondary_reload_class.
4710 We use an inline copy and only compute its return value once to avoid
4712 switch (GET_CODE (in))
4722 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
4723 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
4724 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
4734 && read_only_operand (in, VOIDmode))
4737 if (class != R1_REGS && is_symbolic)
4744 function_arg_padding (mode, type)
4745 enum machine_mode mode;
4750 if (mode == BLKmode)
4752 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4753 size = int_size_in_bytes (type) * BITS_PER_UNIT;
4755 return upward; /* Don't know if this is right, but */
4756 /* same as old definition. */
4759 size = GET_MODE_BITSIZE (mode);
4760 if (size < PARM_BOUNDARY)
4762 else if (size % PARM_BOUNDARY)
4769 /* Do what is necessary for `va_start'. We look at the current function
4770 to determine if stdargs or varargs is used and fill in an initial
4771 va_list. A pointer to this constructor is returned. */
4774 hppa_builtin_saveregs ()
4777 tree fntype = TREE_TYPE (current_function_decl);
4778 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
4779 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4780 != void_type_node)))
4781 ? UNITS_PER_WORD : 0);
4784 offset = plus_constant (current_function_arg_offset_rtx, argadj);
4786 offset = current_function_arg_offset_rtx;
4792 /* Adjust for varargs/stdarg differences. */
4794 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
4796 offset = current_function_arg_offset_rtx;
4798 /* We need to save %r26 .. %r19 inclusive starting at offset -64
4799 from the incoming arg pointer and growing to larger addresses. */
4800 for (i = 26, off = -64; i >= 19; i--, off += 8)
4801 emit_move_insn (gen_rtx_MEM (word_mode,
4802 plus_constant (arg_pointer_rtx, off)),
4803 gen_rtx_REG (word_mode, i));
4805 /* The incoming args pointer points just beyond the flushback area;
4806 normally this is not a serious concern. Howver, when we are doing
4807 varargs/stdargs we want to make the arg pointer point to the start
4808 of the incoming argument area. */
4809 emit_move_insn (virtual_incoming_args_rtx,
4810 plus_constant (arg_pointer_rtx, -64));
4812 /* Now return a pointer to the first anonymous argument. */
4813 return copy_to_reg (expand_binop (Pmode, add_optab,
4814 virtual_incoming_args_rtx,
4815 offset, 0, 0, OPTAB_LIB_WIDEN));
4818 /* Store general registers on the stack. */
4819 dest = gen_rtx_MEM (BLKmode,
4820 plus_constant (current_function_internal_arg_pointer,
4822 MEM_ALIAS_SET (dest) = get_varargs_alias_set ();
4823 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
4825 /* move_block_from_reg will emit code to store the argument registers
4826 individually as scalar stores.
4828 However, other insns may later load from the same addresses for
4829 a structure load (passing a struct to a varargs routine).
4831 The alias code assumes that such aliasing can never happen, so we
4832 have to keep memory referencing insns from moving up beyond the
4833 last argument register store. So we emit a blockage insn here. */
4834 emit_insn (gen_blockage ());
4836 if (current_function_check_memory_usage)
4837 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4839 GEN_INT (4 * UNITS_PER_WORD), TYPE_MODE (sizetype),
4840 GEN_INT (MEMORY_USE_RW),
4841 TYPE_MODE (integer_type_node));
4843 return copy_to_reg (expand_binop (Pmode, add_optab,
4844 current_function_internal_arg_pointer,
4845 offset, 0, 0, OPTAB_LIB_WIDEN));
4849 hppa_va_start (stdarg_p, valist, nextarg)
4850 int stdarg_p ATTRIBUTE_UNUSED;
4854 nextarg = expand_builtin_saveregs ();
4855 std_expand_builtin_va_start (1, valist, nextarg);
4859 hppa_va_arg (valist, type)
4862 HOST_WIDE_INT align, size, ofs;
4867 /* Every argument in PA64 is passed by value (including large structs).
4868 Arguments with size greater than 8 must be aligned 0 MOD 16. */
4870 size = int_size_in_bytes (type);
4871 if (size > UNITS_PER_WORD)
4873 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4874 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4875 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4876 build_int_2 (-2 * UNITS_PER_WORD, -1));
4877 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4878 TREE_SIDE_EFFECTS (t) = 1;
4879 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4881 return std_expand_builtin_va_arg (valist, type);
4884 /* Compute the rounded size of the type. */
4885 align = PARM_BOUNDARY / BITS_PER_UNIT;
4886 size = int_size_in_bytes (type);
4888 ptr = build_pointer_type (type);
4890 /* "Large" types are passed by reference. */
4893 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
4894 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4895 TREE_SIDE_EFFECTS (t) = 1;
4897 pptr = build_pointer_type (ptr);
4898 t = build1 (NOP_EXPR, pptr, t);
4899 TREE_SIDE_EFFECTS (t) = 1;
4901 t = build1 (INDIRECT_REF, ptr, t);
4902 TREE_SIDE_EFFECTS (t) = 1;
4906 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4907 build_int_2 (-size, -1));
4909 /* Copied from va-pa.h, but we probably don't need to align
4910 to word size, since we generate and preserve that invariant. */
4911 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
4912 build_int_2 ((size > 4 ? -8 : -4), -1));
4914 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4915 TREE_SIDE_EFFECTS (t) = 1;
4917 ofs = (8 - size) % 4;
4920 t = build (PLUS_EXPR, TREE_TYPE (valist), t, build_int_2 (ofs, 0));
4921 TREE_SIDE_EFFECTS (t) = 1;
4924 t = build1 (NOP_EXPR, ptr, t);
4925 TREE_SIDE_EFFECTS (t) = 1;
4929 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
4934 /* This routine handles all the normal conditional branch sequences we
4935 might need to generate. It handles compare immediate vs compare
4936 register, nullification of delay slots, varying length branches,
4937 negated branches, and all combinations of the above. It returns the
4938 output appropriate to emit the branch corresponding to all given
4942 output_cbranch (operands, nullify, length, negated, insn)
4944 int nullify, length, negated;
4947 static char buf[100];
4950 /* A conditional branch to the following instruction (eg the delay slot) is
4951 asking for a disaster. This can happen when not optimizing.
4953 In such cases it is safe to emit nothing. */
4955 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4958 /* If this is a long branch with its delay slot unfilled, set `nullify'
4959 as it can nullify the delay slot and save a nop. */
4960 if (length == 8 && dbr_sequence_length () == 0)
4963 /* If this is a short forward conditional branch which did not get
4964 its delay slot filled, the delay slot can still be nullified. */
4965 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4966 nullify = forward_branch_p (insn);
4968 /* A forward branch over a single nullified insn can be done with a
4969 comclr instruction. This avoids a single cycle penalty due to
4970 mis-predicted branch if we fall through (branch not taken). */
4972 && next_real_insn (insn) != 0
4973 && get_attr_length (next_real_insn (insn)) == 4
4974 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4980 /* All short conditional branches except backwards with an unfilled
4984 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
4986 strcpy (buf, "{com%I2b,|cmp%I2b,}");
4987 if (GET_MODE (operands[1]) == DImode)
4990 strcat (buf, "%B3");
4992 strcat (buf, "%S3");
4994 strcat (buf, " %2,%r1,%%r0");
4996 strcat (buf, ",n %2,%r1,%0");
4998 strcat (buf, " %2,%r1,%0");
5001 /* All long conditionals. Note an short backward branch with an
5002 unfilled delay slot is treated just like a long backward branch
5003 with an unfilled delay slot. */
5005 /* Handle weird backwards branch with a filled delay slot
5006 with is nullified. */
5007 if (dbr_sequence_length () != 0
5008 && ! forward_branch_p (insn)
5011 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5012 if (GET_MODE (operands[1]) == DImode)
5015 strcat (buf, "%S3");
5017 strcat (buf, "%B3");
5018 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5020 /* Handle short backwards branch with an unfilled delay slot.
5021 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5022 taken and untaken branches. */
5023 else if (dbr_sequence_length () == 0
5024 && ! forward_branch_p (insn)
5025 && INSN_ADDRESSES_SET_P ()
5026 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5027 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5029 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5030 if (GET_MODE (operands[1]) == DImode)
5033 strcat (buf, "%B3 %2,%r1,%0%#");
5035 strcat (buf, "%S3 %2,%r1,%0%#");
5039 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5040 if (GET_MODE (operands[1]) == DImode)
5043 strcat (buf, "%S3");
5045 strcat (buf, "%B3");
5047 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5049 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5054 /* Very long branch. Right now we only handle these when not
5055 optimizing. See "jump" pattern in pa.md for details. */
5059 /* Create a reversed conditional branch which branches around
5060 the following insns. */
5062 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5064 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5065 if (GET_MODE (operands[1]) == DImode)
5069 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5072 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5074 output_asm_insn (buf, operands);
5076 /* Output an insn to save %r1. */
5077 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5079 /* Now output a very long branch to the original target. */
5080 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5082 /* Now restore the value of %r1 in the delay slot. We're not
5083 optimizing so we know nothing else can be in the delay slot. */
5084 return "ldw -16(%%r30),%%r1";
5087 /* Very long branch when generating PIC code. Right now we only
5088 handle these when not optimizing. See "jump" pattern in pa.md
5093 /* Create a reversed conditional branch which branches around
5094 the following insns. */
5096 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5098 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5099 if (GET_MODE (operands[1]) == DImode)
5102 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5104 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5106 output_asm_insn (buf, operands);
5108 /* Output an insn to save %r1. */
5109 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5111 /* Now output a very long PIC branch to the original target. */
5115 xoperands[0] = operands[0];
5116 xoperands[1] = operands[1];
5117 xoperands[2] = operands[2];
5118 xoperands[3] = operands[3];
5119 xoperands[4] = gen_label_rtx ();
5121 output_asm_insn ("{bl|b,l} .+8,%%r1\n\taddil L'%l0-%l4,%%r1",
5123 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5124 CODE_LABEL_NUMBER (xoperands[4]));
5125 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
5129 /* Now restore the value of %r1 in the delay slot. We're not
5130 optimizing so we know nothing else can be in the delay slot. */
5131 return "ldw -16(%%r30),%%r1";
5139 /* This routine handles all the branch-on-bit conditional branch sequences we
5140 might need to generate. It handles nullification of delay slots,
5141 varying length branches, negated branches and all combinations of the
5142 above. it returns the appropriate output template to emit the branch. */
5145 output_bb (operands, nullify, length, negated, insn, which)
5146 rtx *operands ATTRIBUTE_UNUSED;
5147 int nullify, length, negated;
5151 static char buf[100];
5154 /* A conditional branch to the following instruction (eg the delay slot) is
5155 asking for a disaster. I do not think this can happen as this pattern
5156 is only used when optimizing; jump optimization should eliminate the
5157 jump. But be prepared just in case. */
5159 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5162 /* If this is a long branch with its delay slot unfilled, set `nullify'
5163 as it can nullify the delay slot and save a nop. */
5164 if (length == 8 && dbr_sequence_length () == 0)
5167 /* If this is a short forward conditional branch which did not get
5168 its delay slot filled, the delay slot can still be nullified. */
5169 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5170 nullify = forward_branch_p (insn);
5172 /* A forward branch over a single nullified insn can be done with a
5173 extrs instruction. This avoids a single cycle penalty due to
5174 mis-predicted branch if we fall through (branch not taken). */
5177 && next_real_insn (insn) != 0
5178 && get_attr_length (next_real_insn (insn)) == 4
5179 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5186 /* All short conditional branches except backwards with an unfilled
5190 strcpy (buf, "{extrs,|extrw,s,}");
5192 strcpy (buf, "bb,");
5193 if (useskip && GET_MODE (operands[0]) == DImode)
5194 strcpy (buf, "extrd,s,*");
5195 else if (GET_MODE (operands[0]) == DImode)
5196 strcpy (buf, "bb,*");
5197 if ((which == 0 && negated)
5198 || (which == 1 && ! negated))
5203 strcat (buf, " %0,%1,1,%%r0");
5204 else if (nullify && negated)
5205 strcat (buf, ",n %0,%1,%3");
5206 else if (nullify && ! negated)
5207 strcat (buf, ",n %0,%1,%2");
5208 else if (! nullify && negated)
5209 strcat (buf, "%0,%1,%3");
5210 else if (! nullify && ! negated)
5211 strcat (buf, " %0,%1,%2");
5214 /* All long conditionals. Note an short backward branch with an
5215 unfilled delay slot is treated just like a long backward branch
5216 with an unfilled delay slot. */
5218 /* Handle weird backwards branch with a filled delay slot
5219 with is nullified. */
5220 if (dbr_sequence_length () != 0
5221 && ! forward_branch_p (insn)
5224 strcpy (buf, "bb,");
5225 if (GET_MODE (operands[0]) == DImode)
5227 if ((which == 0 && negated)
5228 || (which == 1 && ! negated))
5233 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5235 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5237 /* Handle short backwards branch with an unfilled delay slot.
5238 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5239 taken and untaken branches. */
5240 else if (dbr_sequence_length () == 0
5241 && ! forward_branch_p (insn)
5242 && INSN_ADDRESSES_SET_P ()
5243 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5244 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5246 strcpy (buf, "bb,");
5247 if (GET_MODE (operands[0]) == DImode)
5249 if ((which == 0 && negated)
5250 || (which == 1 && ! negated))
5255 strcat (buf, " %0,%1,%3%#");
5257 strcat (buf, " %0,%1,%2%#");
5261 strcpy (buf, "{extrs,|extrw,s,}");
5262 if (GET_MODE (operands[0]) == DImode)
5263 strcpy (buf, "extrd,s,*");
5264 if ((which == 0 && negated)
5265 || (which == 1 && ! negated))
5269 if (nullify && negated)
5270 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5271 else if (nullify && ! negated)
5272 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5274 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5276 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5286 /* This routine handles all the branch-on-variable-bit conditional branch
5287 sequences we might need to generate. It handles nullification of delay
5288 slots, varying length branches, negated branches and all combinations
5289 of the above. it returns the appropriate output template to emit the
5293 output_bvb (operands, nullify, length, negated, insn, which)
5294 rtx *operands ATTRIBUTE_UNUSED;
5295 int nullify, length, negated;
5299 static char buf[100];
5302 /* A conditional branch to the following instruction (eg the delay slot) is
5303 asking for a disaster. I do not think this can happen as this pattern
5304 is only used when optimizing; jump optimization should eliminate the
5305 jump. But be prepared just in case. */
5307 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5310 /* If this is a long branch with its delay slot unfilled, set `nullify'
5311 as it can nullify the delay slot and save a nop. */
5312 if (length == 8 && dbr_sequence_length () == 0)
5315 /* If this is a short forward conditional branch which did not get
5316 its delay slot filled, the delay slot can still be nullified. */
5317 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5318 nullify = forward_branch_p (insn);
5320 /* A forward branch over a single nullified insn can be done with a
5321 extrs instruction. This avoids a single cycle penalty due to
5322 mis-predicted branch if we fall through (branch not taken). */
5325 && next_real_insn (insn) != 0
5326 && get_attr_length (next_real_insn (insn)) == 4
5327 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5334 /* All short conditional branches except backwards with an unfilled
5338 strcpy (buf, "{vextrs,|extrw,s,}");
5340 strcpy (buf, "{bvb,|bb,}");
5341 if (useskip && GET_MODE (operands[0]) == DImode)
5342 strcpy (buf, "extrd,s,*}");
5343 else if (GET_MODE (operands[0]) == DImode)
5344 strcpy (buf, "bb,*");
5345 if ((which == 0 && negated)
5346 || (which == 1 && ! negated))
5351 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5352 else if (nullify && negated)
5353 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5354 else if (nullify && ! negated)
5355 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5356 else if (! nullify && negated)
5357 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5358 else if (! nullify && ! negated)
5359 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5362 /* All long conditionals. Note an short backward branch with an
5363 unfilled delay slot is treated just like a long backward branch
5364 with an unfilled delay slot. */
5366 /* Handle weird backwards branch with a filled delay slot
5367 with is nullified. */
5368 if (dbr_sequence_length () != 0
5369 && ! forward_branch_p (insn)
5372 strcpy (buf, "{bvb,|bb,}");
5373 if (GET_MODE (operands[0]) == DImode)
5375 if ((which == 0 && negated)
5376 || (which == 1 && ! negated))
5381 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5383 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5385 /* Handle short backwards branch with an unfilled delay slot.
5386 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5387 taken and untaken branches. */
5388 else if (dbr_sequence_length () == 0
5389 && ! forward_branch_p (insn)
5390 && INSN_ADDRESSES_SET_P ()
5391 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5392 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5394 strcpy (buf, "{bvb,|bb,}");
5395 if (GET_MODE (operands[0]) == DImode)
5397 if ((which == 0 && negated)
5398 || (which == 1 && ! negated))
5403 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5405 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5409 strcpy (buf, "{vextrs,|extrw,s,}");
5410 if (GET_MODE (operands[0]) == DImode)
5411 strcpy (buf, "extrd,s,*");
5412 if ((which == 0 && negated)
5413 || (which == 1 && ! negated))
5417 if (nullify && negated)
5418 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5419 else if (nullify && ! negated)
5420 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5422 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5424 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5434 /* Return the output template for emitting a dbra type insn.
5436 Note it may perform some output operations on its own before
5437 returning the final output string. */
5439 output_dbra (operands, insn, which_alternative)
5442 int which_alternative;
5445 /* A conditional branch to the following instruction (eg the delay slot) is
5446 asking for a disaster. Be prepared! */
5448 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5450 if (which_alternative == 0)
5451 return "ldo %1(%0),%0";
5452 else if (which_alternative == 1)
5454 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5455 output_asm_insn ("ldw -16(%%r30),%4", operands);
5456 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5457 return "{fldws|fldw} -16(%%r30),%0";
5461 output_asm_insn ("ldw %0,%4", operands);
5462 return "ldo %1(%4),%4\n\tstw %4,%0";
5466 if (which_alternative == 0)
5468 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5469 int length = get_attr_length (insn);
5471 /* If this is a long branch with its delay slot unfilled, set `nullify'
5472 as it can nullify the delay slot and save a nop. */
5473 if (length == 8 && dbr_sequence_length () == 0)
5476 /* If this is a short forward conditional branch which did not get
5477 its delay slot filled, the delay slot can still be nullified. */
5478 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5479 nullify = forward_branch_p (insn);
5481 /* Handle short versions first. */
5482 if (length == 4 && nullify)
5483 return "addib,%C2,n %1,%0,%3";
5484 else if (length == 4 && ! nullify)
5485 return "addib,%C2 %1,%0,%3";
5486 else if (length == 8)
5488 /* Handle weird backwards branch with a fulled delay slot
5489 which is nullified. */
5490 if (dbr_sequence_length () != 0
5491 && ! forward_branch_p (insn)
5493 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5494 /* Handle short backwards branch with an unfilled delay slot.
5495 Using a addb;nop rather than addi;bl saves 1 cycle for both
5496 taken and untaken branches. */
5497 else if (dbr_sequence_length () == 0
5498 && ! forward_branch_p (insn)
5499 && INSN_ADDRESSES_SET_P ()
5500 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5501 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5502 return "addib,%C2 %1,%0,%3%#";
5504 /* Handle normal cases. */
5506 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5508 return "addi,%N2 %1,%0,%0\n\tb %3";
5513 /* Deal with gross reload from FP register case. */
5514 else if (which_alternative == 1)
5516 /* Move loop counter from FP register to MEM then into a GR,
5517 increment the GR, store the GR into MEM, and finally reload
5518 the FP register from MEM from within the branch's delay slot. */
5519 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5521 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5522 if (get_attr_length (insn) == 24)
5523 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5525 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5527 /* Deal with gross reload from memory case. */
5530 /* Reload loop counter from memory, the store back to memory
5531 happens in the branch's delay slot. */
5532 output_asm_insn ("ldw %0,%4", operands);
5533 if (get_attr_length (insn) == 12)
5534 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5536 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5540 /* Return the output template for emitting a dbra type insn.
5542 Note it may perform some output operations on its own before
5543 returning the final output string. */
5545 output_movb (operands, insn, which_alternative, reverse_comparison)
5548 int which_alternative;
5549 int reverse_comparison;
5552 /* A conditional branch to the following instruction (eg the delay slot) is
5553 asking for a disaster. Be prepared! */
5555 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5557 if (which_alternative == 0)
5558 return "copy %1,%0";
5559 else if (which_alternative == 1)
5561 output_asm_insn ("stw %1,-16(%%r30)", operands);
5562 return "{fldws|fldw} -16(%%r30),%0";
5564 else if (which_alternative == 2)
5570 /* Support the second variant. */
5571 if (reverse_comparison)
5572 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5574 if (which_alternative == 0)
5576 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5577 int length = get_attr_length (insn);
5579 /* If this is a long branch with its delay slot unfilled, set `nullify'
5580 as it can nullify the delay slot and save a nop. */
5581 if (length == 8 && dbr_sequence_length () == 0)
5584 /* If this is a short forward conditional branch which did not get
5585 its delay slot filled, the delay slot can still be nullified. */
5586 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5587 nullify = forward_branch_p (insn);
5589 /* Handle short versions first. */
5590 if (length == 4 && nullify)
5591 return "movb,%C2,n %1,%0,%3";
5592 else if (length == 4 && ! nullify)
5593 return "movb,%C2 %1,%0,%3";
5594 else if (length == 8)
5596 /* Handle weird backwards branch with a filled delay slot
5597 which is nullified. */
5598 if (dbr_sequence_length () != 0
5599 && ! forward_branch_p (insn)
5601 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5603 /* Handle short backwards branch with an unfilled delay slot.
5604 Using a movb;nop rather than or;bl saves 1 cycle for both
5605 taken and untaken branches. */
5606 else if (dbr_sequence_length () == 0
5607 && ! forward_branch_p (insn)
5608 && INSN_ADDRESSES_SET_P ()
5609 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5610 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5611 return "movb,%C2 %1,%0,%3%#";
5612 /* Handle normal cases. */
5614 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5616 return "or,%N2 %1,%%r0,%0\n\tb %3";
5621 /* Deal with gross reload from FP register case. */
5622 else if (which_alternative == 1)
5624 /* Move loop counter from FP register to MEM then into a GR,
5625 increment the GR, store the GR into MEM, and finally reload
5626 the FP register from MEM from within the branch's delay slot. */
5627 output_asm_insn ("stw %1,-16(%%r30)", operands);
5628 if (get_attr_length (insn) == 12)
5629 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
5631 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5633 /* Deal with gross reload from memory case. */
5634 else if (which_alternative == 2)
5636 /* Reload loop counter from memory, the store back to memory
5637 happens in the branch's delay slot. */
5638 if (get_attr_length (insn) == 8)
5639 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
5641 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5643 /* Handle SAR as a destination. */
5646 if (get_attr_length (insn) == 8)
5647 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
5649 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5654 /* INSN is a millicode call. It may have an unconditional jump in its delay
5657 CALL_DEST is the routine we are calling. */
5660 output_millicode_call (insn, call_dest)
5668 xoperands[3] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
5670 /* Handle common case -- empty delay slot or no jump in the delay slot,
5671 and we're sure that the branch will reach the beginning of the $CODE$
5673 if ((dbr_sequence_length () == 0
5674 && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
5675 || (dbr_sequence_length () != 0
5676 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5677 && get_attr_length (insn) == 4))
5679 xoperands[0] = call_dest;
5680 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
5684 /* This call may not reach the beginning of the $CODE$ subspace. */
5685 if (get_attr_length (insn) > 4)
5687 int delay_insn_deleted = 0;
5689 /* We need to emit an inline long-call branch. */
5690 if (dbr_sequence_length () != 0
5691 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5693 /* A non-jump insn in the delay slot. By definition we can
5694 emit this insn before the call. */
5695 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5697 /* Now delete the delay insn. */
5698 PUT_CODE (NEXT_INSN (insn), NOTE);
5699 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5700 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5701 delay_insn_deleted = 1;
5704 /* PIC long millicode call sequence. */
5707 xoperands[0] = call_dest;
5708 xoperands[1] = gen_label_rtx ();
5709 /* Get our address + 8 into %r1. */
5710 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5712 /* Add %r1 to the offset of our target from the next insn. */
5713 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
5714 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5715 CODE_LABEL_NUMBER (xoperands[1]));
5716 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
5718 /* Get the return address into %r31. */
5719 output_asm_insn ("blr 0,%3", xoperands);
5721 /* Branch to our target which is in %r1. */
5722 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
5724 /* Empty delay slot. Note this insn gets fetched twice and
5725 executed once. To be safe we use a nop. */
5726 output_asm_insn ("nop", xoperands);
5728 /* Pure portable runtime doesn't allow be/ble; we also don't have
5729 PIC support in the assembler/linker, so this sequence is needed. */
5730 else if (TARGET_PORTABLE_RUNTIME)
5732 xoperands[0] = call_dest;
5733 /* Get the address of our target into %r29. */
5734 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
5735 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
5737 /* Get our return address into %r31. */
5738 output_asm_insn ("blr %%r0,%3", xoperands);
5740 /* Jump to our target address in %r29. */
5741 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
5743 /* Empty delay slot. Note this insn gets fetched twice and
5744 executed once. To be safe we use a nop. */
5745 output_asm_insn ("nop", xoperands);
5747 /* If we're allowed to use be/ble instructions, then this is the
5748 best sequence to use for a long millicode call. */
5751 xoperands[0] = call_dest;
5752 output_asm_insn ("ldil L%%%0,%3", xoperands);
5753 output_asm_insn ("{ble|be,l} R%%%0(%%sr4,%3)", xoperands);
5754 output_asm_insn ("nop", xoperands);
5757 /* If we had a jump in the call's delay slot, output it now. */
5758 if (dbr_sequence_length () != 0
5759 && !delay_insn_deleted)
5761 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5762 output_asm_insn ("b,n %0", xoperands);
5764 /* Now delete the delay insn. */
5765 PUT_CODE (NEXT_INSN (insn), NOTE);
5766 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5767 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5772 /* This call has an unconditional jump in its delay slot and the
5773 call is known to reach its target or the beginning of the current
5776 /* Use the containing sequence insn's address. */
5777 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5779 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
5780 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
5782 /* If the branch was too far away, emit a normal call followed
5783 by a nop, followed by the unconditional branch.
5785 If the branch is close, then adjust %r2 from within the
5786 call's delay slot. */
5788 xoperands[0] = call_dest;
5789 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5790 if (! VAL_14_BITS_P (distance))
5791 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
5794 xoperands[2] = gen_label_rtx ();
5795 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
5797 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5798 CODE_LABEL_NUMBER (xoperands[2]));
5801 /* Delete the jump. */
5802 PUT_CODE (NEXT_INSN (insn), NOTE);
5803 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5804 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5808 extern struct obstack permanent_obstack;
5810 /* INSN is either a function call. It may have an unconditional jump
5813 CALL_DEST is the routine we are calling. */
5816 output_call (insn, call_dest, sibcall)
5825 /* Handle common case -- empty delay slot or no jump in the delay slot,
5826 and we're sure that the branch will reach the beginning of the $CODE$
5828 if ((dbr_sequence_length () == 0
5829 && get_attr_length (insn) == 8)
5830 || (dbr_sequence_length () != 0
5831 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5832 && get_attr_length (insn) == 4))
5834 xoperands[0] = call_dest;
5835 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
5836 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
5840 /* This call may not reach the beginning of the $CODE$ subspace. */
5841 if (get_attr_length (insn) > 8)
5843 int delay_insn_deleted = 0;
5847 /* We need to emit an inline long-call branch. Furthermore,
5848 because we're changing a named function call into an indirect
5849 function call well after the parameters have been set up, we
5850 need to make sure any FP args appear in both the integer
5851 and FP registers. Also, we need move any delay slot insn
5852 out of the delay slot. And finally, we can't rely on the linker
5853 being able to fix the call to $$dyncall! -- Yuk!. */
5854 if (dbr_sequence_length () != 0
5855 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5857 /* A non-jump insn in the delay slot. By definition we can
5858 emit this insn before the call (and in fact before argument
5860 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5862 /* Now delete the delay insn. */
5863 PUT_CODE (NEXT_INSN (insn), NOTE);
5864 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5865 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5866 delay_insn_deleted = 1;
5869 /* Now copy any FP arguments into integer registers. */
5870 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
5872 int arg_mode, regno;
5873 rtx use = XEXP (link, 0);
5874 if (! (GET_CODE (use) == USE
5875 && GET_CODE (XEXP (use, 0)) == REG
5876 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5879 arg_mode = GET_MODE (XEXP (use, 0));
5880 regno = REGNO (XEXP (use, 0));
5881 /* Is it a floating point register? */
5882 if (regno >= 32 && regno <= 39)
5884 /* Copy from the FP register into an integer register
5886 if (arg_mode == SFmode)
5888 xoperands[0] = XEXP (use, 0);
5889 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
5890 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
5892 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5896 xoperands[0] = XEXP (use, 0);
5897 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
5898 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
5900 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
5901 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5906 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5907 we don't have any direct calls in that case. */
5910 const char *name = XSTR (call_dest, 0);
5912 /* See if we have already put this function on the list
5913 of deferred plabels. This list is generally small,
5914 so a liner search is not too ugly. If it proves too
5915 slow replace it with something faster. */
5916 for (i = 0; i < n_deferred_plabels; i++)
5917 if (strcmp (name, deferred_plabels[i].name) == 0)
5920 /* If the deferred plabel list is empty, or this entry was
5921 not found on the list, create a new entry on the list. */
5922 if (deferred_plabels == NULL || i == n_deferred_plabels)
5924 const char *real_name;
5926 if (deferred_plabels == 0)
5927 deferred_plabels = (struct deferred_plabel *)
5928 xmalloc (1 * sizeof (struct deferred_plabel));
5930 deferred_plabels = (struct deferred_plabel *)
5931 xrealloc (deferred_plabels,
5932 ((n_deferred_plabels + 1)
5933 * sizeof (struct deferred_plabel)));
5935 i = n_deferred_plabels++;
5936 deferred_plabels[i].internal_label = gen_label_rtx ();
5937 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
5939 strcpy (deferred_plabels[i].name, name);
5941 /* Gross. We have just implicitly taken the address of this
5942 function, mark it as such. */
5943 STRIP_NAME_ENCODING (real_name, name);
5944 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5947 /* We have to load the address of the function using a procedure
5948 label (plabel). Inline plabels can lose for PIC and other
5949 cases, so avoid them by creating a 32bit plabel in the data
5953 xoperands[0] = deferred_plabels[i].internal_label;
5954 xoperands[1] = gen_label_rtx ();
5956 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
5957 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
5958 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
5960 /* Get our address + 8 into %r1. */
5961 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5963 /* Add %r1 to the offset of dyncall from the next insn. */
5964 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
5965 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5966 CODE_LABEL_NUMBER (xoperands[1]));
5967 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
5969 /* Get the return address into %r31. */
5970 output_asm_insn ("blr %%r0,%%r31", xoperands);
5972 /* Branch to our target which is in %r1. */
5973 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5977 /* This call never returns, so we do not need to fix the
5979 output_asm_insn ("nop", xoperands);
5983 /* Copy the return address into %r2 also. */
5984 output_asm_insn ("copy %%r31,%%r2", xoperands);
5989 xoperands[0] = deferred_plabels[i].internal_label;
5991 /* Get the address of our target into %r22. */
5992 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
5993 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
5995 /* Get the high part of the address of $dyncall into %r2, then
5996 add in the low part in the branch instruction. */
5997 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
5998 output_asm_insn ("{ble|be,l} R%%$$dyncall(%%sr4,%%r2)",
6003 /* This call never returns, so we do not need to fix the
6005 output_asm_insn ("nop", xoperands);
6009 /* Copy the return address into %r2 also. */
6010 output_asm_insn ("copy %%r31,%%r2", xoperands);
6015 /* If we had a jump in the call's delay slot, output it now. */
6016 if (dbr_sequence_length () != 0
6017 && !delay_insn_deleted)
6019 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6020 output_asm_insn ("b,n %0", xoperands);
6022 /* Now delete the delay insn. */
6023 PUT_CODE (NEXT_INSN (insn), NOTE);
6024 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6025 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6030 /* This call has an unconditional jump in its delay slot and the
6031 call is known to reach its target or the beginning of the current
6034 /* Use the containing sequence insn's address. */
6035 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6037 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6038 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6040 /* If the branch was too far away, emit a normal call followed
6041 by a nop, followed by the unconditional branch.
6043 If the branch is close, then adjust %r2 from within the
6044 call's delay slot. */
6046 xoperands[0] = call_dest;
6047 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6048 if (! VAL_14_BITS_P (distance))
6049 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
6052 xoperands[3] = gen_label_rtx ();
6053 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6055 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6056 CODE_LABEL_NUMBER (xoperands[3]));
6059 /* Delete the jump. */
6060 PUT_CODE (NEXT_INSN (insn), NOTE);
6061 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6062 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6066 /* In HPUX 8.0's shared library scheme, special relocations are needed
6067 for function labels if they might be passed to a function
6068 in a shared library (because shared libraries don't live in code
6069 space), and special magic is needed to construct their address. */
6072 hppa_encode_label (sym)
6075 const char *str = XSTR (sym, 0);
6076 int len = strlen (str) + 1;
6079 p = newstr = alloca (len + 1);
6088 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6092 function_label_operand (op, mode)
6094 enum machine_mode mode ATTRIBUTE_UNUSED;
6096 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6099 /* Returns 1 if OP is a function label involved in a simple addition
6100 with a constant. Used to keep certain patterns from matching
6101 during instruction combination. */
6103 is_function_label_plus_const (op)
6106 /* Strip off any CONST. */
6107 if (GET_CODE (op) == CONST)
6110 return (GET_CODE (op) == PLUS
6111 && function_label_operand (XEXP (op, 0), Pmode)
6112 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6115 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6116 use in fmpyadd instructions. */
6118 fmpyaddoperands (operands)
6121 enum machine_mode mode = GET_MODE (operands[0]);
6123 /* Must be a floating point mode. */
6124 if (mode != SFmode && mode != DFmode)
6127 /* All modes must be the same. */
6128 if (! (mode == GET_MODE (operands[1])
6129 && mode == GET_MODE (operands[2])
6130 && mode == GET_MODE (operands[3])
6131 && mode == GET_MODE (operands[4])
6132 && mode == GET_MODE (operands[5])))
6135 /* All operands must be registers. */
6136 if (! (GET_CODE (operands[1]) == REG
6137 && GET_CODE (operands[2]) == REG
6138 && GET_CODE (operands[3]) == REG
6139 && GET_CODE (operands[4]) == REG
6140 && GET_CODE (operands[5]) == REG))
6143 /* Only 2 real operands to the addition. One of the input operands must
6144 be the same as the output operand. */
6145 if (! rtx_equal_p (operands[3], operands[4])
6146 && ! rtx_equal_p (operands[3], operands[5]))
6149 /* Inout operand of add can not conflict with any operands from multiply. */
6150 if (rtx_equal_p (operands[3], operands[0])
6151 || rtx_equal_p (operands[3], operands[1])
6152 || rtx_equal_p (operands[3], operands[2]))
6155 /* multiply can not feed into addition operands. */
6156 if (rtx_equal_p (operands[4], operands[0])
6157 || rtx_equal_p (operands[5], operands[0]))
6160 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6162 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6163 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6164 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6165 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6166 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6167 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6170 /* Passed. Operands are suitable for fmpyadd. */
6174 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6175 use in fmpysub instructions. */
6177 fmpysuboperands (operands)
6180 enum machine_mode mode = GET_MODE (operands[0]);
6182 /* Must be a floating point mode. */
6183 if (mode != SFmode && mode != DFmode)
6186 /* All modes must be the same. */
6187 if (! (mode == GET_MODE (operands[1])
6188 && mode == GET_MODE (operands[2])
6189 && mode == GET_MODE (operands[3])
6190 && mode == GET_MODE (operands[4])
6191 && mode == GET_MODE (operands[5])))
6194 /* All operands must be registers. */
6195 if (! (GET_CODE (operands[1]) == REG
6196 && GET_CODE (operands[2]) == REG
6197 && GET_CODE (operands[3]) == REG
6198 && GET_CODE (operands[4]) == REG
6199 && GET_CODE (operands[5]) == REG))
6202 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6203 operation, so operands[4] must be the same as operand[3]. */
6204 if (! rtx_equal_p (operands[3], operands[4]))
6207 /* multiply can not feed into subtraction. */
6208 if (rtx_equal_p (operands[5], operands[0]))
6211 /* Inout operand of sub can not conflict with any operands from multiply. */
6212 if (rtx_equal_p (operands[3], operands[0])
6213 || rtx_equal_p (operands[3], operands[1])
6214 || rtx_equal_p (operands[3], operands[2]))
6217 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6219 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6220 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6221 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6222 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6223 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6224 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6227 /* Passed. Operands are suitable for fmpysub. */
6232 plus_xor_ior_operator (op, mode)
6234 enum machine_mode mode ATTRIBUTE_UNUSED;
6236 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6237 || GET_CODE (op) == IOR);
6240 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6241 constants for shadd instructions. */
6243 shadd_constant_p (val)
6246 if (val == 2 || val == 4 || val == 8)
6252 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6253 the valid constant for shadd instructions. */
6255 shadd_operand (op, mode)
6257 enum machine_mode mode ATTRIBUTE_UNUSED;
6259 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6262 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6265 basereg_operand (op, mode)
6267 enum machine_mode mode;
6269 /* cse will create some unscaled indexed addresses, however; it
6270 generally isn't a win on the PA, so avoid creating unscaled
6271 indexed addresses until after cse is finished. */
6272 if (!cse_not_expected)
6275 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6276 we don't have to worry about the braindamaged implicit space
6277 register selection from the basereg. */
6278 if (TARGET_NO_SPACE_REGS)
6279 return (GET_CODE (op) == REG);
6281 /* While it's always safe to index off the frame pointer, it's not
6282 always profitable, particularly when the frame pointer is being
6284 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6287 return (GET_CODE (op) == REG
6289 && register_operand (op, mode));
6292 /* Return 1 if this operand is anything other than a hard register. */
6295 non_hard_reg_operand (op, mode)
6297 enum machine_mode mode ATTRIBUTE_UNUSED;
6299 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6302 /* Return 1 if INSN branches forward. Should be using insn_addresses
6303 to avoid walking through all the insns... */
6305 forward_branch_p (insn)
6308 rtx label = JUMP_LABEL (insn);
6315 insn = NEXT_INSN (insn);
6318 return (insn == label);
6321 /* Return 1 if OP is an equality comparison, else return 0. */
6323 eq_neq_comparison_operator (op, mode)
6325 enum machine_mode mode ATTRIBUTE_UNUSED;
6327 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6330 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6332 movb_comparison_operator (op, mode)
6334 enum machine_mode mode ATTRIBUTE_UNUSED;
6336 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6337 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6340 /* Return 1 if INSN is in the delay slot of a call instruction. */
6342 jump_in_call_delay (insn)
6346 if (GET_CODE (insn) != JUMP_INSN)
6349 if (PREV_INSN (insn)
6350 && PREV_INSN (PREV_INSN (insn))
6351 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6353 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6355 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6356 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6363 /* Output an unconditional move and branch insn. */
6366 output_parallel_movb (operands, length)
6370 /* These are the cases in which we win. */
6372 return "mov%I1b,tr %1,%0,%2";
6374 /* None of these cases wins, but they don't lose either. */
6375 if (dbr_sequence_length () == 0)
6377 /* Nothing in the delay slot, fake it by putting the combined
6378 insn (the copy or add) in the delay slot of a bl. */
6379 if (GET_CODE (operands[1]) == CONST_INT)
6380 return "b %2\n\tldi %1,%0";
6382 return "b %2\n\tcopy %1,%0";
6386 /* Something in the delay slot, but we've got a long branch. */
6387 if (GET_CODE (operands[1]) == CONST_INT)
6388 return "ldi %1,%0\n\tb %2";
6390 return "copy %1,%0\n\tb %2";
6394 /* Output an unconditional add and branch insn. */
6397 output_parallel_addb (operands, length)
6401 /* To make life easy we want operand0 to be the shared input/output
6402 operand and operand1 to be the readonly operand. */
6403 if (operands[0] == operands[1])
6404 operands[1] = operands[2];
6406 /* These are the cases in which we win. */
6408 return "add%I1b,tr %1,%0,%3";
6410 /* None of these cases win, but they don't lose either. */
6411 if (dbr_sequence_length () == 0)
6413 /* Nothing in the delay slot, fake it by putting the combined
6414 insn (the copy or add) in the delay slot of a bl. */
6415 return "b %3\n\tadd%I1 %1,%0,%0";
6419 /* Something in the delay slot, but we've got a long branch. */
6420 return "add%I1 %1,%0,%0\n\tb %3";
6424 /* Return nonzero if INSN (a jump insn) immediately follows a call to
6425 a named function. This is used to discourage creating parallel movb/addb
6426 insns since a jump which immediately follows a call can execute in the
6427 delay slot of the call.
6429 It is also used to avoid filling the delay slot of a jump which
6430 immediately follows a call since the jump can usually be eliminated
6431 completely by modifying RP in the delay slot of the call. */
6434 following_call (insn)
6437 /* We do not parallel movb,addb or place jumps into call delay slots when
6438 optimizing for the PA8000. */
6439 if (pa_cpu != PROCESSOR_8000)
6442 /* Find the previous real insn, skipping NOTEs. */
6443 insn = PREV_INSN (insn);
6444 while (insn && GET_CODE (insn) == NOTE)
6445 insn = PREV_INSN (insn);
6447 /* Check for CALL_INSNs and millicode calls. */
6449 && ((GET_CODE (insn) == CALL_INSN
6450 && get_attr_type (insn) != TYPE_DYNCALL)
6451 || (GET_CODE (insn) == INSN
6452 && GET_CODE (PATTERN (insn)) != SEQUENCE
6453 && GET_CODE (PATTERN (insn)) != USE
6454 && GET_CODE (PATTERN (insn)) != CLOBBER
6455 && get_attr_type (insn) == TYPE_MILLI)))
6461 /* We use this hook to perform a PA specific optimization which is difficult
6462 to do in earlier passes.
6464 We want the delay slots of branches within jump tables to be filled.
6465 None of the compiler passes at the moment even has the notion that a
6466 PA jump table doesn't contain addresses, but instead contains actual
6469 Because we actually jump into the table, the addresses of each entry
6470 must stay constant in relation to the beginning of the table (which
6471 itself must stay constant relative to the instruction to jump into
6472 it). I don't believe we can guarantee earlier passes of the compiler
6473 will adhere to those rules.
6475 So, late in the compilation process we find all the jump tables, and
6476 expand them into real code -- eg each entry in the jump table vector
6477 will get an appropriate label followed by a jump to the final target.
6479 Reorg and the final jump pass can then optimize these branches and
6480 fill their delay slots. We end up with smaller, more efficient code.
6482 The jump instructions within the table are special; we must be able
6483 to identify them during assembly output (if the jumps don't get filled
6484 we need to emit a nop rather than nullifying the delay slot)). We
6485 identify jumps in switch tables by marking the SET with DImode.
6487 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6488 insns. This serves two purposes, first it prevents jump.c from
6489 noticing that the last N entries in the table jump to the instruction
6490 immediately after the table and deleting the jumps. Second, those
6491 insns mark where we should emit .begin_brtab and .end_brtab directives
6492 when using GAS (allows for better link time optimizations). */
6500 remove_useless_addtr_insns (insns, 1);
6502 if (pa_cpu < PROCESSOR_8000)
6503 pa_combine_instructions (get_insns ());
6506 /* This is fairly cheap, so always run it if optimizing. */
6507 if (optimize > 0 && !TARGET_BIG_SWITCH)
6509 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6510 insns = get_insns ();
6511 for (insn = insns; insn; insn = NEXT_INSN (insn))
6513 rtx pattern, tmp, location;
6514 unsigned int length, i;
6516 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6517 if (GET_CODE (insn) != JUMP_INSN
6518 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6519 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6522 /* Emit marker for the beginning of the branch table. */
6523 emit_insn_before (gen_begin_brtab (), insn);
6525 pattern = PATTERN (insn);
6526 location = PREV_INSN (insn);
6527 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6529 for (i = 0; i < length; i++)
6531 /* Emit a label before each jump to keep jump.c from
6532 removing this code. */
6533 tmp = gen_label_rtx ();
6534 LABEL_NUSES (tmp) = 1;
6535 emit_label_after (tmp, location);
6536 location = NEXT_INSN (location);
6538 if (GET_CODE (pattern) == ADDR_VEC)
6540 /* Emit the jump itself. */
6541 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
6542 tmp = emit_jump_insn_after (tmp, location);
6543 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
6544 /* It is easy to rely on the branch table markers
6545 during assembly output to trigger the correct code
6546 for a switch table jump with an unfilled delay slot,
6548 However, that requires state and assumes that we look
6551 We can't make such assumptions when computing the length
6552 of instructions. Ugh. We could walk the insn chain to
6553 determine if this instruction is in a branch table, but
6554 that can get rather expensive, particularly during the
6555 branch shortening phase of the compiler.
6557 So instead we mark this jump as being special. This is
6558 far from ideal and knows that no code after this will
6559 muck around with the mode of the JUMP_INSN itself. */
6560 PUT_MODE (tmp, SImode);
6561 LABEL_NUSES (JUMP_LABEL (tmp))++;
6562 location = NEXT_INSN (location);
6566 /* Emit the jump itself. */
6567 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
6568 tmp = emit_jump_insn_after (tmp, location);
6569 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
6570 /* It is easy to rely on the branch table markers
6571 during assembly output to trigger the correct code
6572 for a switch table jump with an unfilled delay slot,
6574 However, that requires state and assumes that we look
6577 We can't make such assumptions when computing the length
6578 of instructions. Ugh. We could walk the insn chain to
6579 determine if this instruction is in a branch table, but
6580 that can get rather expensive, particularly during the
6581 branch shortening phase of the compiler.
6583 So instead we mark this jump as being special. This is
6584 far from ideal and knows that no code after this will
6585 muck around with the mode of the JUMP_INSN itself. */
6586 PUT_MODE (tmp, SImode);
6587 LABEL_NUSES (JUMP_LABEL (tmp))++;
6588 location = NEXT_INSN (location);
6591 /* Emit a BARRIER after the jump. */
6592 emit_barrier_after (location);
6593 location = NEXT_INSN (location);
6596 /* Emit marker for the end of the branch table. */
6597 emit_insn_before (gen_end_brtab (), location);
6598 location = NEXT_INSN (location);
6599 emit_barrier_after (location);
6601 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6607 /* Sill need an end_brtab insn. */
6608 insns = get_insns ();
6609 for (insn = insns; insn; insn = NEXT_INSN (insn))
6611 /* Find an ADDR_VEC insn. */
6612 if (GET_CODE (insn) != JUMP_INSN
6613 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6614 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6617 /* Now generate markers for the beginning and end of the
6619 emit_insn_before (gen_begin_brtab (), insn);
6620 emit_insn_after (gen_end_brtab (), insn);
6625 /* The PA has a number of odd instructions which can perform multiple
6626 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6627 it may be profitable to combine two instructions into one instruction
6628 with two outputs. It's not profitable PA2.0 machines because the
6629 two outputs would take two slots in the reorder buffers.
6631 This routine finds instructions which can be combined and combines
6632 them. We only support some of the potential combinations, and we
6633 only try common ways to find suitable instructions.
6635 * addb can add two registers or a register and a small integer
6636 and jump to a nearby (+-8k) location. Normally the jump to the
6637 nearby location is conditional on the result of the add, but by
6638 using the "true" condition we can make the jump unconditional.
6639 Thus addb can perform two independent operations in one insn.
6641 * movb is similar to addb in that it can perform a reg->reg
6642 or small immediate->reg copy and jump to a nearby (+-8k location).
6644 * fmpyadd and fmpysub can perform a FP multiply and either an
6645 FP add or FP sub if the operands of the multiply and add/sub are
6646 independent (there are other minor restrictions). Note both
6647 the fmpy and fadd/fsub can in theory move to better spots according
6648 to data dependencies, but for now we require the fmpy stay at a
6651 * Many of the memory operations can perform pre & post updates
6652 of index registers. GCC's pre/post increment/decrement addressing
6653 is far too simple to take advantage of all the possibilities. This
6654 pass may not be suitable since those insns may not be independent.
6656 * comclr can compare two ints or an int and a register, nullify
6657 the following instruction and zero some other register. This
6658 is more difficult to use as it's harder to find an insn which
6659 will generate a comclr than finding something like an unconditional
6660 branch. (conditional moves & long branches create comclr insns).
6662 * Most arithmetic operations can conditionally skip the next
6663 instruction. They can be viewed as "perform this operation
6664 and conditionally jump to this nearby location" (where nearby
6665 is an insns away). These are difficult to use due to the
6666 branch length restrictions. */
6669 pa_combine_instructions (insns)
6670 rtx insns ATTRIBUTE_UNUSED;
6674 /* This can get expensive since the basic algorithm is on the
6675 order of O(n^2) (or worse). Only do it for -O2 or higher
6676 levels of optimization. */
6680 /* Walk down the list of insns looking for "anchor" insns which
6681 may be combined with "floating" insns. As the name implies,
6682 "anchor" instructions don't move, while "floating" insns may
6684 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
6685 new = make_insn_raw (new);
6687 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
6689 enum attr_pa_combine_type anchor_attr;
6690 enum attr_pa_combine_type floater_attr;
6692 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6693 Also ignore any special USE insns. */
6694 if ((GET_CODE (anchor) != INSN
6695 && GET_CODE (anchor) != JUMP_INSN
6696 && GET_CODE (anchor) != CALL_INSN)
6697 || GET_CODE (PATTERN (anchor)) == USE
6698 || GET_CODE (PATTERN (anchor)) == CLOBBER
6699 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
6700 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
6703 anchor_attr = get_attr_pa_combine_type (anchor);
6704 /* See if anchor is an insn suitable for combination. */
6705 if (anchor_attr == PA_COMBINE_TYPE_FMPY
6706 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
6707 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6708 && ! forward_branch_p (anchor)))
6712 for (floater = PREV_INSN (anchor);
6714 floater = PREV_INSN (floater))
6716 if (GET_CODE (floater) == NOTE
6717 || (GET_CODE (floater) == INSN
6718 && (GET_CODE (PATTERN (floater)) == USE
6719 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6722 /* Anything except a regular INSN will stop our search. */
6723 if (GET_CODE (floater) != INSN
6724 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6725 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6731 /* See if FLOATER is suitable for combination with the
6733 floater_attr = get_attr_pa_combine_type (floater);
6734 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6735 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6736 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6737 && floater_attr == PA_COMBINE_TYPE_FMPY))
6739 /* If ANCHOR and FLOATER can be combined, then we're
6740 done with this pass. */
6741 if (pa_can_combine_p (new, anchor, floater, 0,
6742 SET_DEST (PATTERN (floater)),
6743 XEXP (SET_SRC (PATTERN (floater)), 0),
6744 XEXP (SET_SRC (PATTERN (floater)), 1)))
6748 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6749 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
6751 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
6753 if (pa_can_combine_p (new, anchor, floater, 0,
6754 SET_DEST (PATTERN (floater)),
6755 XEXP (SET_SRC (PATTERN (floater)), 0),
6756 XEXP (SET_SRC (PATTERN (floater)), 1)))
6761 if (pa_can_combine_p (new, anchor, floater, 0,
6762 SET_DEST (PATTERN (floater)),
6763 SET_SRC (PATTERN (floater)),
6764 SET_SRC (PATTERN (floater))))
6770 /* If we didn't find anything on the backwards scan try forwards. */
6772 && (anchor_attr == PA_COMBINE_TYPE_FMPY
6773 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
6775 for (floater = anchor; floater; floater = NEXT_INSN (floater))
6777 if (GET_CODE (floater) == NOTE
6778 || (GET_CODE (floater) == INSN
6779 && (GET_CODE (PATTERN (floater)) == USE
6780 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6784 /* Anything except a regular INSN will stop our search. */
6785 if (GET_CODE (floater) != INSN
6786 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6787 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6793 /* See if FLOATER is suitable for combination with the
6795 floater_attr = get_attr_pa_combine_type (floater);
6796 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6797 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6798 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6799 && floater_attr == PA_COMBINE_TYPE_FMPY))
6801 /* If ANCHOR and FLOATER can be combined, then we're
6802 done with this pass. */
6803 if (pa_can_combine_p (new, anchor, floater, 1,
6804 SET_DEST (PATTERN (floater)),
6805 XEXP (SET_SRC (PATTERN (floater)),
6807 XEXP (SET_SRC (PATTERN (floater)),
6814 /* FLOATER will be nonzero if we found a suitable floating
6815 insn for combination with ANCHOR. */
6817 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6818 || anchor_attr == PA_COMBINE_TYPE_FMPY))
6820 /* Emit the new instruction and delete the old anchor. */
6821 emit_insn_before (gen_rtx_PARALLEL
6823 gen_rtvec (2, PATTERN (anchor),
6824 PATTERN (floater))),
6827 PUT_CODE (anchor, NOTE);
6828 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6829 NOTE_SOURCE_FILE (anchor) = 0;
6831 /* Emit a special USE insn for FLOATER, then delete
6832 the floating insn. */
6833 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6834 delete_insn (floater);
6839 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
6842 /* Emit the new_jump instruction and delete the old anchor. */
6844 = emit_jump_insn_before (gen_rtx_PARALLEL
6846 gen_rtvec (2, PATTERN (anchor),
6847 PATTERN (floater))),
6850 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
6851 PUT_CODE (anchor, NOTE);
6852 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6853 NOTE_SOURCE_FILE (anchor) = 0;
6855 /* Emit a special USE insn for FLOATER, then delete
6856 the floating insn. */
6857 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6858 delete_insn (floater);
6866 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
6867 rtx new, anchor, floater;
6869 rtx dest, src1, src2;
6871 int insn_code_number;
6874 /* Create a PARALLEL with the patterns of ANCHOR and
6875 FLOATER, try to recognize it, then test constraints
6876 for the resulting pattern.
6878 If the pattern doesn't match or the constraints
6879 aren't met keep searching for a suitable floater
6881 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
6882 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
6883 INSN_CODE (new) = -1;
6884 insn_code_number = recog_memoized (new);
6885 if (insn_code_number < 0
6886 || !constrain_operands (1))
6900 /* There's up to three operands to consider. One
6901 output and two inputs.
6903 The output must not be used between FLOATER & ANCHOR
6904 exclusive. The inputs must not be set between
6905 FLOATER and ANCHOR exclusive. */
6907 if (reg_used_between_p (dest, start, end))
6910 if (reg_set_between_p (src1, start, end))
6913 if (reg_set_between_p (src2, start, end))
6916 /* If we get here, then everything is good. */
6920 /* Return nonzero if references for INSN are delayed.
6922 Millicode insns are actually function calls with some special
6923 constraints on arguments and register usage.
6925 Millicode calls always expect their arguments in the integer argument
6926 registers, and always return their result in %r29 (ret1). They
6927 are expected to clobber their arguments, %r1, %r29, and %r31 and
6930 By considering this effects delayed reorg reorg can put insns
6931 which set the argument registers into the delay slot of the millicode
6932 call -- thus they act more like traditional CALL_INSNs.
6934 get_attr_type will try to recognize the given insn, so make sure to
6935 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
6938 insn_refs_are_delayed (insn)
6941 return ((GET_CODE (insn) == INSN
6942 && GET_CODE (PATTERN (insn)) != SEQUENCE
6943 && GET_CODE (PATTERN (insn)) != USE
6944 && GET_CODE (PATTERN (insn)) != CLOBBER
6945 && get_attr_type (insn) == TYPE_MILLI));
6948 /* Return the location of a parameter that is passed in a register or NULL
6949 if the parameter has any component that is passed in memory.
6951 This is new code and will be pushed to into the net sources after
6954 ??? We might want to restructure this so that it looks more like other
6957 function_arg (cum, mode, type, named, incoming)
6958 CUMULATIVE_ARGS *cum;
6959 enum machine_mode mode;
6961 int named ATTRIBUTE_UNUSED;
6964 int max_arg_words = (TARGET_64BIT ? 8 : 4);
6971 /* If this arg would be passed partially or totally on the stack, then
6972 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
6973 handle arguments which are split between regs and stack slots if
6974 the ABI mandates split arguments. */
6975 if (cum->words + FUNCTION_ARG_SIZE (mode, type) > max_arg_words
6976 || mode == VOIDmode)
6982 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
6984 if (cum->words + offset >= max_arg_words
6985 || mode == VOIDmode)
6989 /* The 32bit ABIs and the 64bit ABIs are rather different,
6990 particularly in their handling of FP registers. We might
6991 be able to cleverly share code between them, but I'm not
6992 going to bother in the hope that splitting them up results
6993 in code that is more easily understood.
6995 The 64bit code probably is very wrong for structure passing. */
6998 /* Advance the base registers to their current locations.
7000 Remember, gprs grow towards smaller register numbers while
7001 fprs grow to higher register numbers. Also remember FP regs
7002 are always 4 bytes wide, while the size of an integer register
7003 varies based on the size of the target word. */
7004 gpr_reg_base = 26 - cum->words;
7005 fpr_reg_base = 32 + cum->words;
7007 /* If the argument is more than a word long, then we need to align
7008 the base registers. Same caveats as above. */
7009 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7011 if (mode != BLKmode)
7013 /* First deal with alignment of the doubleword. */
7014 gpr_reg_base -= (cum->words & 1);
7016 /* This seems backwards, but it is what HP specifies. We need
7017 gpr_reg_base to point to the smaller numbered register of
7018 the integer register pair. So if we have an even register
7019 number, then decrement the gpr base. */
7020 gpr_reg_base -= ((gpr_reg_base % 2) == 0);
7022 /* FP values behave sanely, except that each FP reg is only
7024 fpr_reg_base += ((fpr_reg_base % 2) == 0);
7029 int i, offset = 0, ub;
7030 ub = FUNCTION_ARG_SIZE (mode, type);
7032 MAX (0, max_arg_words - cum->words - (cum->words & 1)));
7033 gpr_reg_base -= (cum->words & 1);
7034 for (i = 0; i < ub; i++)
7036 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7037 gen_rtx_REG (DImode,
7046 return XEXP (loc[0], 0);
7048 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7054 /* If the argument is larger than a word, then we know precisely
7055 which registers we must use. */
7056 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7071 /* We have a single word (32 bits). A simple computation
7072 will get us the register #s we need. */
7073 gpr_reg_base = 26 - cum->words;
7074 fpr_reg_base = 32 + 2 * cum->words;
7078 if (TARGET_64BIT && mode == TFmode)
7084 gen_rtx_EXPR_LIST (VOIDmode,
7085 gen_rtx_REG (DImode, gpr_reg_base + 1),
7087 gen_rtx_EXPR_LIST (VOIDmode,
7088 gen_rtx_REG (DImode, gpr_reg_base),
7091 /* Determine if the register needs to be passed in both general and
7092 floating point registers. */
7093 if ((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7094 /* If we are doing soft-float with portable runtime, then there
7095 is no need to worry about FP regs. */
7096 && ! TARGET_SOFT_FLOAT
7097 /* The parameter must be some kind of float, else we can just
7098 pass it in integer registers. */
7099 && FLOAT_MODE_P (mode)
7100 /* The target function must not have a prototype. */
7101 && cum->nargs_prototype <= 0
7102 /* libcalls do not need to pass items in both FP and general
7104 && type != NULL_TREE
7105 /* All this hair applies to outgoing args only. */
7112 gen_rtx_EXPR_LIST (VOIDmode,
7113 gen_rtx_REG (mode, fpr_reg_base),
7115 gen_rtx_EXPR_LIST (VOIDmode,
7116 gen_rtx_REG (mode, gpr_reg_base),
7121 /* See if we should pass this parameter in a general register. */
7122 if (TARGET_SOFT_FLOAT
7123 /* Indirect calls in the normal 32bit ABI require all arguments
7124 to be passed in general registers. */
7125 || (!TARGET_PORTABLE_RUNTIME
7128 /* If the parameter is not a floating point parameter, then
7129 it belongs in GPRs. */
7130 || !FLOAT_MODE_P (mode))
7131 retval = gen_rtx_REG (mode, gpr_reg_base);
7133 retval = gen_rtx_REG (mode, fpr_reg_base);
7139 /* If this arg would be passed totally in registers or totally on the stack,
7140 then this routine should return zero. It is currently called only for
7141 the 64-bit target. */
7143 function_arg_partial_nregs (cum, mode, type, named)
7144 CUMULATIVE_ARGS *cum;
7145 enum machine_mode mode;
7147 int named ATTRIBUTE_UNUSED;
7149 unsigned int max_arg_words = 8;
7150 unsigned int offset = 0;
7152 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7155 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
7156 /* Arg fits fully into registers. */
7158 else if (cum->words + offset >= max_arg_words)
7159 /* Arg fully on the stack. */
7163 return max_arg_words - cum->words - offset;
7167 /* Return 1 if this is a comparison operator. This allows the use of
7168 MATCH_OPERATOR to recognize all the branch insns. */
7171 cmpib_comparison_operator (op, mode)
7173 enum machine_mode mode;
7175 return ((mode == VOIDmode || GET_MODE (op) == mode)
7176 && (GET_CODE (op) == EQ
7177 || GET_CODE (op) == NE
7178 || GET_CODE (op) == GT
7179 || GET_CODE (op) == GTU
7180 || GET_CODE (op) == GE
7181 || GET_CODE (op) == LT
7182 || GET_CODE (op) == LE
7183 || GET_CODE (op) == LEU));
7186 /* Mark ARG (which is really a struct deferred_plabel **) for GC. */
7189 mark_deferred_plabels (arg)
7192 struct deferred_plabel *dp = *(struct deferred_plabel **) arg;
7195 for (i = 0; i < n_deferred_plabels; ++i)
7196 ggc_mark_rtx (dp[i].internal_label);
7199 /* Called to register all of our global variables with the garbage
7205 ggc_add_rtx_root (&hppa_compare_op0, 1);
7206 ggc_add_rtx_root (&hppa_compare_op1, 1);
7207 ggc_add_root (&deferred_plabels, 1, sizeof (&deferred_plabels),
7208 &mark_deferred_plabels);