1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
41 #include "integrate.h"
50 #include "target-def.h"
52 static int hppa_use_dfa_pipeline_interface PARAMS ((void));
54 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
55 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
58 hppa_use_dfa_pipeline_interface ()
63 /* Return nonzero if there is a bypass for the output of
64 OUT_INSN and the fp store IN_INSN. */
66 hppa_fpstore_bypass_p (out_insn, in_insn)
67 rtx out_insn, in_insn;
69 enum machine_mode store_mode;
70 enum machine_mode other_mode;
73 if (recog_memoized (in_insn) < 0
74 || get_attr_type (in_insn) != TYPE_FPSTORE
75 || recog_memoized (out_insn) < 0)
78 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
80 set = single_set (out_insn);
84 other_mode = GET_MODE (SET_SRC (set));
86 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
90 #ifndef DO_FRAME_NOTES
91 #ifdef INCOMING_RETURN_ADDR_RTX
92 #define DO_FRAME_NOTES 1
94 #define DO_FRAME_NOTES 0
98 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
99 static void pa_combine_instructions PARAMS ((rtx));
100 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
101 static int forward_branch_p PARAMS ((rtx));
102 static int shadd_constant_p PARAMS ((int));
103 static void pa_add_gc_roots PARAMS ((void));
104 static void mark_deferred_plabels PARAMS ((void *));
105 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
106 static int compute_movstrsi_length PARAMS ((rtx));
107 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
108 static void remove_useless_addtr_insns PARAMS ((rtx, int));
109 static void store_reg PARAMS ((int, int, int));
110 static void store_reg_modify PARAMS ((int, int, int));
111 static void load_reg PARAMS ((int, int, int));
112 static void set_reg_plus_d PARAMS ((int, int, int, int));
113 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
114 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
115 static int pa_adjust_priority PARAMS ((rtx, int));
116 static int pa_issue_rate PARAMS ((void));
117 static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
119 static void pa_encode_section_info PARAMS ((tree, int));
120 static const char *pa_strip_name_encoding PARAMS ((const char *));
122 /* Save the operands last given to a compare for use when we
123 generate a scc or bcc insn. */
125 rtx hppa_compare_op0, hppa_compare_op1;
126 enum cmp_type hppa_branch_type;
128 /* Which cpu we are scheduling for. */
129 enum processor_type pa_cpu;
131 /* String to hold which cpu we are scheduling for. */
132 const char *pa_cpu_string;
134 /* Which architecture we are generating code for. */
135 enum architecture_type pa_arch;
137 /* String to hold which architecture we are generating code for. */
138 const char *pa_arch_string;
140 /* Counts for the number of callee-saved general and floating point
141 registers which were saved by the current function's prologue. */
142 static int gr_saved, fr_saved;
144 static rtx find_addr_reg PARAMS ((rtx));
146 /* Keep track of the number of bytes we have output in the CODE subspaces
147 during this compilation so we'll know when to emit inline long-calls. */
149 unsigned int total_code_bytes;
151 /* Variables to handle plabels that we discover are necessary at assembly
152 output time. They are output after the current function. */
154 struct deferred_plabel
158 } *deferred_plabels = 0;
159 int n_deferred_plabels = 0;
161 /* Initialize the GCC target structure. */
163 #undef TARGET_ASM_ALIGNED_HI_OP
164 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
165 #undef TARGET_ASM_ALIGNED_SI_OP
166 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
167 #undef TARGET_ASM_ALIGNED_DI_OP
168 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
169 #undef TARGET_ASM_UNALIGNED_HI_OP
170 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
171 #undef TARGET_ASM_UNALIGNED_SI_OP
172 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
173 #undef TARGET_ASM_UNALIGNED_DI_OP
174 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
175 #undef TARGET_ASM_INTEGER
176 #define TARGET_ASM_INTEGER pa_assemble_integer
178 #undef TARGET_ASM_FUNCTION_PROLOGUE
179 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
180 #undef TARGET_ASM_FUNCTION_EPILOGUE
181 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
183 #undef TARGET_SCHED_ADJUST_COST
184 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
185 #undef TARGET_SCHED_ADJUST_PRIORITY
186 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
187 #undef TARGET_SCHED_ISSUE_RATE
188 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
190 #undef TARGET_ENCODE_SECTION_INFO
191 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
192 #undef TARGET_STRIP_NAME_ENCODING
193 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
195 struct gcc_target targetm = TARGET_INITIALIZER;
200 /* Default to 8000 scheduling. */
201 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
203 pa_cpu_string = "7100";
204 pa_cpu = PROCESSOR_7100;
206 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
208 pa_cpu_string = "700";
209 pa_cpu = PROCESSOR_700;
211 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100LC"))
213 pa_cpu_string = "7100LC";
214 pa_cpu = PROCESSOR_7100LC;
216 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
218 pa_cpu_string = "7200";
219 pa_cpu = PROCESSOR_7200;
221 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7300"))
223 pa_cpu_string = "7300";
224 pa_cpu = PROCESSOR_7300;
226 else if (pa_cpu_string == NULL
227 || ! strcmp (pa_cpu_string, "8000"))
229 pa_cpu_string = "8000";
230 pa_cpu = PROCESSOR_8000;
234 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
237 /* Set the instruction set architecture. */
238 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
240 pa_arch_string = "1.0";
241 pa_arch = ARCHITECTURE_10;
242 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
244 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
246 pa_arch_string = "1.1";
247 pa_arch = ARCHITECTURE_11;
248 target_flags &= ~MASK_PA_20;
249 target_flags |= MASK_PA_11;
251 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
253 pa_arch_string = "2.0";
254 pa_arch = ARCHITECTURE_20;
255 target_flags |= MASK_PA_11 | MASK_PA_20;
257 else if (pa_arch_string)
259 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
262 /* Unconditional branches in the delay slot are not compatible with dwarf2
263 call frame information. There is no benefit in using this optimization
264 on PA8000 and later processors. */
265 if (pa_cpu >= PROCESSOR_8000
266 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
267 || flag_unwind_tables)
268 target_flags &= ~MASK_JUMP_IN_DELAY;
270 if (flag_pic && TARGET_PORTABLE_RUNTIME)
272 warning ("PIC code generation is not supported in the portable runtime model\n");
275 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
277 warning ("PIC code generation is not compatible with fast indirect calls\n");
280 if (! TARGET_GAS && write_symbols != NO_DEBUG)
282 warning ("-g is only supported when using GAS on this processor,");
283 warning ("-g option disabled");
284 write_symbols = NO_DEBUG;
287 /* We only support the "big PIC" model now. And we always generate PIC
288 code when in 64bit mode. */
289 if (flag_pic == 1 || TARGET_64BIT)
292 /* We can't guarantee that .dword is available for 32-bit targets. */
293 if (UNITS_PER_WORD == 4)
294 targetm.asm_out.aligned_op.di = NULL;
296 /* The unaligned ops are only available when using GAS. */
299 targetm.asm_out.unaligned_op.hi = NULL;
300 targetm.asm_out.unaligned_op.si = NULL;
301 targetm.asm_out.unaligned_op.di = NULL;
304 /* Register global variables with the garbage collector. */
308 /* Return non-zero only if OP is a register of mode MODE,
311 reg_or_0_operand (op, mode)
313 enum machine_mode mode;
315 return (op == CONST0_RTX (mode) || register_operand (op, mode));
318 /* Return non-zero if OP is suitable for use in a call to a named
321 For 2.5 try to eliminate either call_operand_address or
322 function_label_operand, they perform very similar functions. */
324 call_operand_address (op, mode)
326 enum machine_mode mode ATTRIBUTE_UNUSED;
328 return (GET_MODE (op) == word_mode
329 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
332 /* Return 1 if X contains a symbolic expression. We know these
333 expressions will have one of a few well defined forms, so
334 we need only check those forms. */
336 symbolic_expression_p (x)
340 /* Strip off any HIGH. */
341 if (GET_CODE (x) == HIGH)
344 return (symbolic_operand (x, VOIDmode));
348 symbolic_operand (op, mode)
350 enum machine_mode mode ATTRIBUTE_UNUSED;
352 switch (GET_CODE (op))
359 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
360 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
361 && GET_CODE (XEXP (op, 1)) == CONST_INT);
367 /* Return truth value of statement that OP is a symbolic memory
368 operand of mode MODE. */
371 symbolic_memory_operand (op, mode)
373 enum machine_mode mode ATTRIBUTE_UNUSED;
375 if (GET_CODE (op) == SUBREG)
376 op = SUBREG_REG (op);
377 if (GET_CODE (op) != MEM)
380 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
381 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
384 /* Return 1 if the operand is either a register or a memory operand that is
388 reg_or_nonsymb_mem_operand (op, mode)
390 enum machine_mode mode;
392 if (register_operand (op, mode))
395 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
401 /* Return 1 if the operand is either a register, zero, or a memory operand
402 that is not symbolic. */
405 reg_or_0_or_nonsymb_mem_operand (op, mode)
407 enum machine_mode mode;
409 if (register_operand (op, mode))
412 if (op == CONST0_RTX (mode))
415 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
421 /* Return 1 if the operand is a register operand or a non-symbolic memory
422 operand after reload. This predicate is used for branch patterns that
423 internally handle register reloading. We need to accept non-symbolic
424 memory operands after reload to ensure that the pattern is still valid
425 if reload didn't find a hard register for the operand. */
428 reg_before_reload_operand (op, mode)
430 enum machine_mode mode;
432 /* Don't accept a SUBREG since it will need a reload. */
433 if (GET_CODE (op) == SUBREG)
436 if (register_operand (op, mode))
440 && memory_operand (op, mode)
441 && ! symbolic_memory_operand (op, mode))
447 /* Accept any constant that can be moved in one instructions into a
450 cint_ok_for_move (intval)
451 HOST_WIDE_INT intval;
453 /* OK if ldo, ldil, or zdepi, can be used. */
454 return (CONST_OK_FOR_LETTER_P (intval, 'J')
455 || CONST_OK_FOR_LETTER_P (intval, 'N')
456 || CONST_OK_FOR_LETTER_P (intval, 'K'));
459 /* Accept anything that can be moved in one instruction into a general
462 move_operand (op, mode)
464 enum machine_mode mode;
466 if (register_operand (op, mode))
469 if (GET_CODE (op) == CONSTANT_P_RTX)
472 if (GET_CODE (op) == CONST_INT)
473 return cint_ok_for_move (INTVAL (op));
475 if (GET_CODE (op) == SUBREG)
476 op = SUBREG_REG (op);
477 if (GET_CODE (op) != MEM)
482 /* We consider a LO_SUM DLT reference a move_operand now since it has
483 been merged into the normal movsi/movdi patterns. */
484 if (GET_CODE (op) == LO_SUM
485 && GET_CODE (XEXP (op, 0)) == REG
486 && REG_OK_FOR_BASE_P (XEXP (op, 0))
487 && GET_CODE (XEXP (op, 1)) == UNSPEC
488 && GET_MODE (op) == Pmode)
491 /* Since move_operand is only used for source operands, we can always
492 allow scaled indexing! */
493 if (! TARGET_DISABLE_INDEXING
494 && GET_CODE (op) == PLUS
495 && ((GET_CODE (XEXP (op, 0)) == MULT
496 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
497 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
498 && INTVAL (XEXP (XEXP (op, 0), 1))
499 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
500 && GET_CODE (XEXP (op, 1)) == REG)
501 || (GET_CODE (XEXP (op, 1)) == MULT
502 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
503 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
504 && INTVAL (XEXP (XEXP (op, 1), 1))
505 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
506 && GET_CODE (XEXP (op, 0)) == REG)))
509 return memory_address_p (mode, op);
512 /* Accept REG and any CONST_INT that can be moved in one instruction into a
515 reg_or_cint_move_operand (op, mode)
517 enum machine_mode mode;
519 if (register_operand (op, mode))
522 if (GET_CODE (op) == CONST_INT)
523 return cint_ok_for_move (INTVAL (op));
529 pic_label_operand (op, mode)
531 enum machine_mode mode ATTRIBUTE_UNUSED;
536 switch (GET_CODE (op))
542 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
543 && GET_CODE (XEXP (op, 1)) == CONST_INT);
550 fp_reg_operand (op, mode)
552 enum machine_mode mode ATTRIBUTE_UNUSED;
554 return reg_renumber && FP_REG_P (op);
559 /* Return truth value of whether OP can be used as an operand in a
560 three operand arithmetic insn that accepts registers of mode MODE
561 or 14-bit signed integers. */
563 arith_operand (op, mode)
565 enum machine_mode mode;
567 return (register_operand (op, mode)
568 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
571 /* Return truth value of whether OP can be used as an operand in a
572 three operand arithmetic insn that accepts registers of mode MODE
573 or 11-bit signed integers. */
575 arith11_operand (op, mode)
577 enum machine_mode mode;
579 return (register_operand (op, mode)
580 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
583 /* A constant integer suitable for use in a PRE_MODIFY memory
586 pre_cint_operand (op, mode)
588 enum machine_mode mode ATTRIBUTE_UNUSED;
590 return (GET_CODE (op) == CONST_INT
591 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
594 /* A constant integer suitable for use in a POST_MODIFY memory
597 post_cint_operand (op, mode)
599 enum machine_mode mode ATTRIBUTE_UNUSED;
601 return (GET_CODE (op) == CONST_INT
602 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
606 arith_double_operand (op, mode)
608 enum machine_mode mode;
610 return (register_operand (op, mode)
611 || (GET_CODE (op) == CONST_DOUBLE
612 && GET_MODE (op) == mode
613 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
614 && ((CONST_DOUBLE_HIGH (op) >= 0)
615 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
618 /* Return truth value of whether OP is an integer which fits the
619 range constraining immediate operands in three-address insns, or
620 is an integer register. */
623 ireg_or_int5_operand (op, mode)
625 enum machine_mode mode ATTRIBUTE_UNUSED;
627 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
628 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
631 /* Return nonzero if OP is an integer register, else return zero. */
633 ireg_operand (op, mode)
635 enum machine_mode mode ATTRIBUTE_UNUSED;
637 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
640 /* Return truth value of whether OP is an integer which fits the
641 range constraining immediate operands in three-address insns. */
644 int5_operand (op, mode)
646 enum machine_mode mode ATTRIBUTE_UNUSED;
648 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
652 uint5_operand (op, mode)
654 enum machine_mode mode ATTRIBUTE_UNUSED;
656 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
660 int11_operand (op, mode)
662 enum machine_mode mode ATTRIBUTE_UNUSED;
664 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
668 uint32_operand (op, mode)
670 enum machine_mode mode ATTRIBUTE_UNUSED;
672 #if HOST_BITS_PER_WIDE_INT > 32
673 /* All allowed constants will fit a CONST_INT. */
674 return (GET_CODE (op) == CONST_INT
675 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
677 return (GET_CODE (op) == CONST_INT
678 || (GET_CODE (op) == CONST_DOUBLE
679 && CONST_DOUBLE_HIGH (op) == 0));
684 arith5_operand (op, mode)
686 enum machine_mode mode;
688 return register_operand (op, mode) || int5_operand (op, mode);
691 /* True iff zdepi can be used to generate this CONST_INT.
692 zdepi first sign extends a 5 bit signed number to a given field
693 length, then places this field anywhere in a zero. */
696 unsigned HOST_WIDE_INT x;
698 unsigned HOST_WIDE_INT lsb_mask, t;
700 /* This might not be obvious, but it's at least fast.
701 This function is critical; we don't have the time loops would take. */
703 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
704 /* Return true iff t is a power of two. */
705 return ((t & (t - 1)) == 0);
708 /* True iff depi or extru can be used to compute (reg & mask).
709 Accept bit pattern like these:
715 unsigned HOST_WIDE_INT mask;
718 mask += mask & -mask;
719 return (mask & (mask - 1)) == 0;
722 /* True iff depi or extru can be used to compute (reg & OP). */
724 and_operand (op, mode)
726 enum machine_mode mode;
728 return (register_operand (op, mode)
729 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
732 /* True iff depi can be used to compute (reg | MASK). */
735 unsigned HOST_WIDE_INT mask;
737 mask += mask & -mask;
738 return (mask & (mask - 1)) == 0;
741 /* True iff depi can be used to compute (reg | OP). */
743 ior_operand (op, mode)
745 enum machine_mode mode ATTRIBUTE_UNUSED;
747 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
751 lhs_lshift_operand (op, mode)
753 enum machine_mode mode;
755 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
758 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
759 Such values can be the left hand side x in (x << r), using the zvdepi
762 lhs_lshift_cint_operand (op, mode)
764 enum machine_mode mode ATTRIBUTE_UNUSED;
766 unsigned HOST_WIDE_INT x;
767 if (GET_CODE (op) != CONST_INT)
769 x = INTVAL (op) >> 4;
770 return (x & (x + 1)) == 0;
774 arith32_operand (op, mode)
776 enum machine_mode mode;
778 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
782 pc_or_label_operand (op, mode)
784 enum machine_mode mode ATTRIBUTE_UNUSED;
786 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
789 /* Legitimize PIC addresses. If the address is already
790 position-independent, we return ORIG. Newly generated
791 position-independent addresses go to REG. If we need more
792 than one register, we lose. */
795 legitimize_pic_address (orig, mode, reg)
797 enum machine_mode mode;
801 /* Labels need special handling. */
802 if (pic_label_operand (orig, mode))
804 /* We do not want to go through the movXX expanders here since that
805 would create recursion.
807 Nor do we really want to call a generator for a named pattern
808 since that requires multiple patterns if we want to support
811 So instead we just emit the raw set, which avoids the movXX
812 expanders completely. */
813 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
814 current_function_uses_pic_offset_table = 1;
817 if (GET_CODE (orig) == SYMBOL_REF)
823 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
824 gen_rtx_HIGH (word_mode, orig)));
826 = gen_rtx_MEM (Pmode,
827 gen_rtx_LO_SUM (Pmode, reg,
828 gen_rtx_UNSPEC (Pmode,
832 current_function_uses_pic_offset_table = 1;
833 RTX_UNCHANGING_P (pic_ref) = 1;
834 emit_move_insn (reg, pic_ref);
837 else if (GET_CODE (orig) == CONST)
841 if (GET_CODE (XEXP (orig, 0)) == PLUS
842 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
848 if (GET_CODE (XEXP (orig, 0)) == PLUS)
850 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
851 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
852 base == reg ? 0 : reg);
855 if (GET_CODE (orig) == CONST_INT)
857 if (INT_14_BITS (orig))
858 return plus_constant (base, INTVAL (orig));
859 orig = force_reg (Pmode, orig);
861 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
862 /* Likewise, should we set special REG_NOTEs here? */
867 /* Try machine-dependent ways of modifying an illegitimate address
868 to be legitimate. If we find one, return the new, valid address.
869 This macro is used in only one place: `memory_address' in explow.c.
871 OLDX is the address as it was before break_out_memory_refs was called.
872 In some cases it is useful to look at this to decide what needs to be done.
874 MODE and WIN are passed so that this macro can use
875 GO_IF_LEGITIMATE_ADDRESS.
877 It is always safe for this macro to do nothing. It exists to recognize
878 opportunities to optimize the output.
880 For the PA, transform:
882 memory(X + <large int>)
886 if (<large int> & mask) >= 16
887 Y = (<large int> & ~mask) + mask + 1 Round up.
889 Y = (<large int> & ~mask) Round down.
891 memory (Z + (<large int> - Y));
893 This is for CSE to find several similar references, and only use one Z.
895 X can either be a SYMBOL_REF or REG, but because combine can not
896 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
897 D will not fit in 14 bits.
899 MODE_FLOAT references allow displacements which fit in 5 bits, so use
902 MODE_INT references allow displacements which fit in 14 bits, so use
905 This relies on the fact that most mode MODE_FLOAT references will use FP
906 registers and most mode MODE_INT references will use integer registers.
907 (In the rare case of an FP register used in an integer MODE, we depend
908 on secondary reloads to clean things up.)
911 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
912 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
913 addressing modes to be used).
915 Put X and Z into registers. Then put the entire expression into
919 hppa_legitimize_address (x, oldx, mode)
920 rtx x, oldx ATTRIBUTE_UNUSED;
921 enum machine_mode mode;
926 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
928 /* Strip off CONST. */
929 if (GET_CODE (x) == CONST)
932 /* Special case. Get the SYMBOL_REF into a register and use indexing.
933 That should always be safe. */
934 if (GET_CODE (x) == PLUS
935 && GET_CODE (XEXP (x, 0)) == REG
936 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
938 rtx reg = force_reg (Pmode, XEXP (x, 1));
939 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
942 /* Note we must reject symbols which represent function addresses
943 since the assembler/linker can't handle arithmetic on plabels. */
944 if (GET_CODE (x) == PLUS
945 && GET_CODE (XEXP (x, 1)) == CONST_INT
946 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
947 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
948 || GET_CODE (XEXP (x, 0)) == REG))
950 rtx int_part, ptr_reg;
952 int offset = INTVAL (XEXP (x, 1));
955 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
956 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
958 /* Choose which way to round the offset. Round up if we
959 are >= halfway to the next boundary. */
960 if ((offset & mask) >= ((mask + 1) / 2))
961 newoffset = (offset & ~ mask) + mask + 1;
963 newoffset = (offset & ~ mask);
965 /* If the newoffset will not fit in 14 bits (ldo), then
966 handling this would take 4 or 5 instructions (2 to load
967 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
968 add the new offset and the SYMBOL_REF.) Combine can
969 not handle 4->2 or 5->2 combinations, so do not create
971 if (! VAL_14_BITS_P (newoffset)
972 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
974 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
977 gen_rtx_HIGH (Pmode, const_part));
980 gen_rtx_LO_SUM (Pmode,
981 tmp_reg, const_part));
985 if (! VAL_14_BITS_P (newoffset))
986 int_part = force_reg (Pmode, GEN_INT (newoffset));
988 int_part = GEN_INT (newoffset);
990 ptr_reg = force_reg (Pmode,
992 force_reg (Pmode, XEXP (x, 0)),
995 return plus_constant (ptr_reg, offset - newoffset);
998 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1000 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1001 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1002 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1003 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
1004 || GET_CODE (XEXP (x, 1)) == SUBREG)
1005 && GET_CODE (XEXP (x, 1)) != CONST)
1007 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1011 if (GET_CODE (reg1) != REG)
1012 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1014 reg2 = XEXP (XEXP (x, 0), 0);
1015 if (GET_CODE (reg2) != REG)
1016 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1018 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1019 gen_rtx_MULT (Pmode,
1025 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1027 Only do so for floating point modes since this is more speculative
1028 and we lose if it's an integer store. */
1029 if (GET_CODE (x) == PLUS
1030 && GET_CODE (XEXP (x, 0)) == PLUS
1031 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1032 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1033 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1034 && (mode == SFmode || mode == DFmode))
1037 /* First, try and figure out what to use as a base register. */
1038 rtx reg1, reg2, base, idx, orig_base;
1040 reg1 = XEXP (XEXP (x, 0), 1);
1045 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1046 then emit_move_sequence will turn on REG_POINTER so we'll know
1047 it's a base register below. */
1048 if (GET_CODE (reg1) != REG)
1049 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1051 if (GET_CODE (reg2) != REG)
1052 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1054 /* Figure out what the base and index are. */
1056 if (GET_CODE (reg1) == REG
1057 && REG_POINTER (reg1))
1060 orig_base = XEXP (XEXP (x, 0), 1);
1061 idx = gen_rtx_PLUS (Pmode,
1062 gen_rtx_MULT (Pmode,
1063 XEXP (XEXP (XEXP (x, 0), 0), 0),
1064 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1067 else if (GET_CODE (reg2) == REG
1068 && REG_POINTER (reg2))
1071 orig_base = XEXP (x, 1);
1078 /* If the index adds a large constant, try to scale the
1079 constant so that it can be loaded with only one insn. */
1080 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1081 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1082 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1083 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1085 /* Divide the CONST_INT by the scale factor, then add it to A. */
1086 int val = INTVAL (XEXP (idx, 1));
1088 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1089 reg1 = XEXP (XEXP (idx, 0), 0);
1090 if (GET_CODE (reg1) != REG)
1091 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1093 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1095 /* We can now generate a simple scaled indexed address. */
1098 (Pmode, gen_rtx_PLUS (Pmode,
1099 gen_rtx_MULT (Pmode, reg1,
1100 XEXP (XEXP (idx, 0), 1)),
1104 /* If B + C is still a valid base register, then add them. */
1105 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1106 && INTVAL (XEXP (idx, 1)) <= 4096
1107 && INTVAL (XEXP (idx, 1)) >= -4096)
1109 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1112 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1114 reg2 = XEXP (XEXP (idx, 0), 0);
1115 if (GET_CODE (reg2) != CONST_INT)
1116 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1118 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1119 gen_rtx_MULT (Pmode,
1125 /* Get the index into a register, then add the base + index and
1126 return a register holding the result. */
1128 /* First get A into a register. */
1129 reg1 = XEXP (XEXP (idx, 0), 0);
1130 if (GET_CODE (reg1) != REG)
1131 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1133 /* And get B into a register. */
1134 reg2 = XEXP (idx, 1);
1135 if (GET_CODE (reg2) != REG)
1136 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1138 reg1 = force_reg (Pmode,
1139 gen_rtx_PLUS (Pmode,
1140 gen_rtx_MULT (Pmode, reg1,
1141 XEXP (XEXP (idx, 0), 1)),
1144 /* Add the result to our base register and return. */
1145 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1149 /* Uh-oh. We might have an address for x[n-100000]. This needs
1150 special handling to avoid creating an indexed memory address
1151 with x-100000 as the base.
1153 If the constant part is small enough, then it's still safe because
1154 there is a guard page at the beginning and end of the data segment.
1156 Scaled references are common enough that we want to try and rearrange the
1157 terms so that we can use indexing for these addresses too. Only
1158 do the optimization for floatint point modes. */
1160 if (GET_CODE (x) == PLUS
1161 && symbolic_expression_p (XEXP (x, 1)))
1163 /* Ugly. We modify things here so that the address offset specified
1164 by the index expression is computed first, then added to x to form
1165 the entire address. */
1167 rtx regx1, regx2, regy1, regy2, y;
1169 /* Strip off any CONST. */
1171 if (GET_CODE (y) == CONST)
1174 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1176 /* See if this looks like
1177 (plus (mult (reg) (shadd_const))
1178 (const (plus (symbol_ref) (const_int))))
1180 Where const_int is small. In that case the const
1181 expression is a valid pointer for indexing.
1183 If const_int is big, but can be divided evenly by shadd_const
1184 and added to (reg). This allows more scaled indexed addresses. */
1185 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1186 && GET_CODE (XEXP (x, 0)) == MULT
1187 && GET_CODE (XEXP (y, 1)) == CONST_INT
1188 && INTVAL (XEXP (y, 1)) >= -4096
1189 && INTVAL (XEXP (y, 1)) <= 4095
1190 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1191 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1193 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1197 if (GET_CODE (reg1) != REG)
1198 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1200 reg2 = XEXP (XEXP (x, 0), 0);
1201 if (GET_CODE (reg2) != REG)
1202 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1204 return force_reg (Pmode,
1205 gen_rtx_PLUS (Pmode,
1206 gen_rtx_MULT (Pmode,
1211 else if ((mode == DFmode || mode == SFmode)
1212 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1213 && GET_CODE (XEXP (x, 0)) == MULT
1214 && GET_CODE (XEXP (y, 1)) == CONST_INT
1215 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1216 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1217 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1220 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1221 / INTVAL (XEXP (XEXP (x, 0), 1))));
1222 regx2 = XEXP (XEXP (x, 0), 0);
1223 if (GET_CODE (regx2) != REG)
1224 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1225 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1229 gen_rtx_PLUS (Pmode,
1230 gen_rtx_MULT (Pmode, regx2,
1231 XEXP (XEXP (x, 0), 1)),
1232 force_reg (Pmode, XEXP (y, 0))));
1234 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1235 && INTVAL (XEXP (y, 1)) >= -4096
1236 && INTVAL (XEXP (y, 1)) <= 4095)
1238 /* This is safe because of the guard page at the
1239 beginning and end of the data space. Just
1240 return the original address. */
1245 /* Doesn't look like one we can optimize. */
1246 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1247 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1248 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1249 regx1 = force_reg (Pmode,
1250 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1252 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1260 /* For the HPPA, REG and REG+CONST is cost 0
1261 and addresses involving symbolic constants are cost 2.
1263 PIC addresses are very expensive.
1265 It is no coincidence that this has the same structure
1266 as GO_IF_LEGITIMATE_ADDRESS. */
1268 hppa_address_cost (X)
1271 if (GET_CODE (X) == PLUS)
1273 else if (GET_CODE (X) == LO_SUM)
1275 else if (GET_CODE (X) == HIGH)
1280 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1281 new rtx with the correct mode. */
1283 force_mode (mode, orig)
1284 enum machine_mode mode;
1287 if (mode == GET_MODE (orig))
1290 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1293 return gen_rtx_REG (mode, REGNO (orig));
1296 /* Emit insns to move operands[1] into operands[0].
1298 Return 1 if we have written out everything that needs to be done to
1299 do the move. Otherwise, return 0 and the caller will emit the move
1302 Note SCRATCH_REG may not be in the proper mode depending on how it
1303 will be used. This routine is resposible for creating a new copy
1304 of SCRATCH_REG in the proper mode. */
1307 emit_move_sequence (operands, mode, scratch_reg)
1309 enum machine_mode mode;
1312 register rtx operand0 = operands[0];
1313 register rtx operand1 = operands[1];
1317 && reload_in_progress && GET_CODE (operand0) == REG
1318 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1319 operand0 = reg_equiv_mem[REGNO (operand0)];
1320 else if (scratch_reg
1321 && reload_in_progress && GET_CODE (operand0) == SUBREG
1322 && GET_CODE (SUBREG_REG (operand0)) == REG
1323 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1325 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1326 the code which tracks sets/uses for delete_output_reload. */
1327 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1328 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1329 SUBREG_BYTE (operand0));
1330 operand0 = alter_subreg (&temp);
1334 && reload_in_progress && GET_CODE (operand1) == REG
1335 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1336 operand1 = reg_equiv_mem[REGNO (operand1)];
1337 else if (scratch_reg
1338 && reload_in_progress && GET_CODE (operand1) == SUBREG
1339 && GET_CODE (SUBREG_REG (operand1)) == REG
1340 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1342 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1343 the code which tracks sets/uses for delete_output_reload. */
1344 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1345 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1346 SUBREG_BYTE (operand1));
1347 operand1 = alter_subreg (&temp);
1350 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1351 && ((tem = find_replacement (&XEXP (operand0, 0)))
1352 != XEXP (operand0, 0)))
1353 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1354 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1355 && ((tem = find_replacement (&XEXP (operand1, 0)))
1356 != XEXP (operand1, 0)))
1357 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1359 /* Handle secondary reloads for loads/stores of FP registers from
1360 REG+D addresses where D does not fit in 5 bits, including
1361 (subreg (mem (addr))) cases. */
1362 if (fp_reg_operand (operand0, mode)
1363 && ((GET_CODE (operand1) == MEM
1364 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1365 || ((GET_CODE (operand1) == SUBREG
1366 && GET_CODE (XEXP (operand1, 0)) == MEM
1367 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1370 if (GET_CODE (operand1) == SUBREG)
1371 operand1 = XEXP (operand1, 0);
1373 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1374 it in WORD_MODE regardless of what mode it was originally given
1376 scratch_reg = force_mode (word_mode, scratch_reg);
1378 /* D might not fit in 14 bits either; for such cases load D into
1380 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1382 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1383 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1385 XEXP (XEXP (operand1, 0), 0),
1389 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1390 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1391 gen_rtx_MEM (mode, scratch_reg)));
1394 else if (fp_reg_operand (operand1, mode)
1395 && ((GET_CODE (operand0) == MEM
1396 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1397 || ((GET_CODE (operand0) == SUBREG)
1398 && GET_CODE (XEXP (operand0, 0)) == MEM
1399 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1402 if (GET_CODE (operand0) == SUBREG)
1403 operand0 = XEXP (operand0, 0);
1405 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1406 it in WORD_MODE regardless of what mode it was originally given
1408 scratch_reg = force_mode (word_mode, scratch_reg);
1410 /* D might not fit in 14 bits either; for such cases load D into
1412 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1414 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1415 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1418 XEXP (XEXP (operand0, 0),
1423 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1424 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1428 /* Handle secondary reloads for loads of FP registers from constant
1429 expressions by forcing the constant into memory.
1431 use scratch_reg to hold the address of the memory location.
1433 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1434 NO_REGS when presented with a const_int and an register class
1435 containing only FP registers. Doing so unfortunately creates
1436 more problems than it solves. Fix this for 2.5. */
1437 else if (fp_reg_operand (operand0, mode)
1438 && CONSTANT_P (operand1)
1443 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1444 it in WORD_MODE regardless of what mode it was originally given
1446 scratch_reg = force_mode (word_mode, scratch_reg);
1448 /* Force the constant into memory and put the address of the
1449 memory location into scratch_reg. */
1450 xoperands[0] = scratch_reg;
1451 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1452 emit_move_sequence (xoperands, Pmode, 0);
1454 /* Now load the destination register. */
1455 emit_insn (gen_rtx_SET (mode, operand0,
1456 gen_rtx_MEM (mode, scratch_reg)));
1459 /* Handle secondary reloads for SAR. These occur when trying to load
1460 the SAR from memory, FP register, or with a constant. */
1461 else if (GET_CODE (operand0) == REG
1462 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1463 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1464 && (GET_CODE (operand1) == MEM
1465 || GET_CODE (operand1) == CONST_INT
1466 || (GET_CODE (operand1) == REG
1467 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1470 /* D might not fit in 14 bits either; for such cases load D into
1472 if (GET_CODE (operand1) == MEM
1473 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1475 /* We are reloading the address into the scratch register, so we
1476 want to make sure the scratch register is a full register. */
1477 scratch_reg = force_mode (word_mode, scratch_reg);
1479 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1480 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1483 XEXP (XEXP (operand1, 0),
1487 /* Now we are going to load the scratch register from memory,
1488 we want to load it in the same width as the original MEM,
1489 which must be the same as the width of the ultimate destination,
1491 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1493 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1498 /* We want to load the scratch register using the same mode as
1499 the ultimate destination. */
1500 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1502 emit_move_insn (scratch_reg, operand1);
1505 /* And emit the insn to set the ultimate destination. We know that
1506 the scratch register has the same mode as the destination at this
1508 emit_move_insn (operand0, scratch_reg);
1511 /* Handle most common case: storing into a register. */
1512 else if (register_operand (operand0, mode))
1514 if (register_operand (operand1, mode)
1515 || (GET_CODE (operand1) == CONST_INT
1516 && cint_ok_for_move (INTVAL (operand1)))
1517 || (operand1 == CONST0_RTX (mode))
1518 || (GET_CODE (operand1) == HIGH
1519 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1520 /* Only `general_operands' can come here, so MEM is ok. */
1521 || GET_CODE (operand1) == MEM)
1523 /* Run this case quickly. */
1524 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1528 else if (GET_CODE (operand0) == MEM)
1530 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1531 && !(reload_in_progress || reload_completed))
1533 rtx temp = gen_reg_rtx (DFmode);
1535 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1536 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1539 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1541 /* Run this case quickly. */
1542 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1545 if (! (reload_in_progress || reload_completed))
1547 operands[0] = validize_mem (operand0);
1548 operands[1] = operand1 = force_reg (mode, operand1);
1552 /* Simplify the source if we need to.
1553 Note we do have to handle function labels here, even though we do
1554 not consider them legitimate constants. Loop optimizations can
1555 call the emit_move_xxx with one as a source. */
1556 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1557 || function_label_operand (operand1, mode)
1558 || (GET_CODE (operand1) == HIGH
1559 && symbolic_operand (XEXP (operand1, 0), mode)))
1563 if (GET_CODE (operand1) == HIGH)
1566 operand1 = XEXP (operand1, 0);
1568 if (symbolic_operand (operand1, mode))
1570 /* Argh. The assembler and linker can't handle arithmetic
1573 So we force the plabel into memory, load operand0 from
1574 the memory location, then add in the constant part. */
1575 if ((GET_CODE (operand1) == CONST
1576 && GET_CODE (XEXP (operand1, 0)) == PLUS
1577 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1578 || function_label_operand (operand1, mode))
1580 rtx temp, const_part;
1582 /* Figure out what (if any) scratch register to use. */
1583 if (reload_in_progress || reload_completed)
1585 scratch_reg = scratch_reg ? scratch_reg : operand0;
1586 /* SCRATCH_REG will hold an address and maybe the actual
1587 data. We want it in WORD_MODE regardless of what mode it
1588 was originally given to us. */
1589 scratch_reg = force_mode (word_mode, scratch_reg);
1592 scratch_reg = gen_reg_rtx (Pmode);
1594 if (GET_CODE (operand1) == CONST)
1596 /* Save away the constant part of the expression. */
1597 const_part = XEXP (XEXP (operand1, 0), 1);
1598 if (GET_CODE (const_part) != CONST_INT)
1601 /* Force the function label into memory. */
1602 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1606 /* No constant part. */
1607 const_part = NULL_RTX;
1609 /* Force the function label into memory. */
1610 temp = force_const_mem (mode, operand1);
1614 /* Get the address of the memory location. PIC-ify it if
1616 temp = XEXP (temp, 0);
1618 temp = legitimize_pic_address (temp, mode, scratch_reg);
1620 /* Put the address of the memory location into our destination
1623 emit_move_sequence (operands, mode, scratch_reg);
1625 /* Now load from the memory location into our destination
1627 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1628 emit_move_sequence (operands, mode, scratch_reg);
1630 /* And add back in the constant part. */
1631 if (const_part != NULL_RTX)
1632 expand_inc (operand0, const_part);
1641 if (reload_in_progress || reload_completed)
1643 temp = scratch_reg ? scratch_reg : operand0;
1644 /* TEMP will hold an address and maybe the actual
1645 data. We want it in WORD_MODE regardless of what mode it
1646 was originally given to us. */
1647 temp = force_mode (word_mode, temp);
1650 temp = gen_reg_rtx (Pmode);
1652 /* (const (plus (symbol) (const_int))) must be forced to
1653 memory during/after reload if the const_int will not fit
1655 if (GET_CODE (operand1) == CONST
1656 && GET_CODE (XEXP (operand1, 0)) == PLUS
1657 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1658 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1659 && (reload_completed || reload_in_progress)
1662 operands[1] = force_const_mem (mode, operand1);
1663 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1665 emit_move_sequence (operands, mode, temp);
1669 operands[1] = legitimize_pic_address (operand1, mode, temp);
1670 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1673 /* On the HPPA, references to data space are supposed to use dp,
1674 register 27, but showing it in the RTL inhibits various cse
1675 and loop optimizations. */
1680 if (reload_in_progress || reload_completed)
1682 temp = scratch_reg ? scratch_reg : operand0;
1683 /* TEMP will hold an address and maybe the actual
1684 data. We want it in WORD_MODE regardless of what mode it
1685 was originally given to us. */
1686 temp = force_mode (word_mode, temp);
1689 temp = gen_reg_rtx (mode);
1691 /* Loading a SYMBOL_REF into a register makes that register
1692 safe to be used as the base in an indexed address.
1694 Don't mark hard registers though. That loses. */
1695 if (GET_CODE (operand0) == REG
1696 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1697 REG_POINTER (operand0) = 1;
1698 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1699 REG_POINTER (temp) = 1;
1701 set = gen_rtx_SET (mode, operand0, temp);
1703 set = gen_rtx_SET (VOIDmode,
1705 gen_rtx_LO_SUM (mode, temp, operand1));
1707 emit_insn (gen_rtx_SET (VOIDmode,
1709 gen_rtx_HIGH (mode, operand1)));
1715 else if (GET_CODE (operand1) != CONST_INT
1716 || ! cint_ok_for_move (INTVAL (operand1)))
1718 rtx extend = NULL_RTX;
1721 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1722 && HOST_BITS_PER_WIDE_INT > 32
1723 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1725 HOST_WIDE_INT val = INTVAL (operand1);
1728 /* Extract the low order 32 bits of the value and sign extend.
1729 If the new value is the same as the original value, we can
1730 can use the original value as-is. If the new value is
1731 different, we use it and insert the most-significant 32-bits
1732 of the original value into the final result. */
1733 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1734 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1737 #if HOST_BITS_PER_WIDE_INT > 32
1738 extend = GEN_INT (val >> 32);
1740 operand1 = GEN_INT (nval);
1744 if (reload_in_progress || reload_completed)
1747 temp = gen_reg_rtx (mode);
1749 if (GET_CODE (operand1) == CONST_INT)
1751 /* Directly break constant into low and high parts. This
1752 provides better optimization opportunities because various
1753 passes recognize constants split with PLUS but not LO_SUM.
1754 We use a 14-bit signed low part except when the addition
1755 of 0x4000 to the high part might change the sign of the
1757 HOST_WIDE_INT value = INTVAL (operand1);
1758 HOST_WIDE_INT low = value & 0x3fff;
1759 HOST_WIDE_INT high = value & ~ 0x3fff;
1763 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1771 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1772 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1776 emit_insn (gen_rtx_SET (VOIDmode, temp,
1777 gen_rtx_HIGH (mode, operand1)));
1778 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1781 emit_move_insn (operands[0], operands[1]);
1783 if (extend != NULL_RTX)
1784 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1790 /* Now have insn-emit do whatever it normally does. */
1794 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1795 it will need a link/runtime reloc). */
1803 switch (TREE_CODE (exp))
1810 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1811 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1816 case NON_LVALUE_EXPR:
1817 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1823 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1824 if (TREE_VALUE (link) != 0)
1825 reloc |= reloc_needed (TREE_VALUE (link));
1838 /* Does operand (which is a symbolic_operand) live in text space?
1839 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
1843 read_only_operand (operand, mode)
1845 enum machine_mode mode ATTRIBUTE_UNUSED;
1847 if (GET_CODE (operand) == CONST)
1848 operand = XEXP (XEXP (operand, 0), 0);
1851 if (GET_CODE (operand) == SYMBOL_REF)
1852 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1856 if (GET_CODE (operand) == SYMBOL_REF)
1857 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1863 /* Return the best assembler insn template
1864 for moving operands[1] into operands[0] as a fullword. */
1866 singlemove_string (operands)
1869 HOST_WIDE_INT intval;
1871 if (GET_CODE (operands[0]) == MEM)
1872 return "stw %r1,%0";
1873 if (GET_CODE (operands[1]) == MEM)
1875 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1880 if (GET_MODE (operands[1]) != SFmode)
1883 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1885 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1886 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1888 operands[1] = GEN_INT (i);
1889 /* Fall through to CONST_INT case. */
1891 if (GET_CODE (operands[1]) == CONST_INT)
1893 intval = INTVAL (operands[1]);
1895 if (VAL_14_BITS_P (intval))
1897 else if ((intval & 0x7ff) == 0)
1898 return "ldil L'%1,%0";
1899 else if (zdepi_cint_p (intval))
1900 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1902 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1904 return "copy %1,%0";
1908 /* Compute position (in OP[1]) and width (in OP[2])
1909 useful for copying IMM to a register using the zdepi
1910 instructions. Store the immediate value to insert in OP[0]. */
1912 compute_zdepwi_operands (imm, op)
1913 unsigned HOST_WIDE_INT imm;
1918 /* Find the least significant set bit in IMM. */
1919 for (lsb = 0; lsb < 32; lsb++)
1926 /* Choose variants based on *sign* of the 5-bit field. */
1927 if ((imm & 0x10) == 0)
1928 len = (lsb <= 28) ? 4 : 32 - lsb;
1931 /* Find the width of the bitstring in IMM. */
1932 for (len = 5; len < 32; len++)
1934 if ((imm & (1 << len)) == 0)
1938 /* Sign extend IMM as a 5-bit value. */
1939 imm = (imm & 0xf) - 0x10;
1947 /* Compute position (in OP[1]) and width (in OP[2])
1948 useful for copying IMM to a register using the depdi,z
1949 instructions. Store the immediate value to insert in OP[0]. */
1951 compute_zdepdi_operands (imm, op)
1952 unsigned HOST_WIDE_INT imm;
1955 HOST_WIDE_INT lsb, len;
1957 /* Find the least significant set bit in IMM. */
1958 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1965 /* Choose variants based on *sign* of the 5-bit field. */
1966 if ((imm & 0x10) == 0)
1967 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1968 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1971 /* Find the width of the bitstring in IMM. */
1972 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1974 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
1978 /* Sign extend IMM as a 5-bit value. */
1979 imm = (imm & 0xf) - 0x10;
1987 /* Output assembler code to perform a doubleword move insn
1988 with operands OPERANDS. */
1991 output_move_double (operands)
1994 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1996 rtx addreg0 = 0, addreg1 = 0;
1998 /* First classify both operands. */
2000 if (REG_P (operands[0]))
2002 else if (offsettable_memref_p (operands[0]))
2004 else if (GET_CODE (operands[0]) == MEM)
2009 if (REG_P (operands[1]))
2011 else if (CONSTANT_P (operands[1]))
2013 else if (offsettable_memref_p (operands[1]))
2015 else if (GET_CODE (operands[1]) == MEM)
2020 /* Check for the cases that the operand constraints are not
2021 supposed to allow to happen. Abort if we get one,
2022 because generating code for these cases is painful. */
2024 if (optype0 != REGOP && optype1 != REGOP)
2027 /* Handle auto decrementing and incrementing loads and stores
2028 specifically, since the structure of the function doesn't work
2029 for them without major modification. Do it better when we learn
2030 this port about the general inc/dec addressing of PA.
2031 (This was written by tege. Chide him if it doesn't work.) */
2033 if (optype0 == MEMOP)
2035 /* We have to output the address syntax ourselves, since print_operand
2036 doesn't deal with the addresses we want to use. Fix this later. */
2038 rtx addr = XEXP (operands[0], 0);
2039 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2041 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2043 operands[0] = XEXP (addr, 0);
2044 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2047 if (!reg_overlap_mentioned_p (high_reg, addr))
2049 /* No overlap between high target register and address
2050 register. (We do this in a non-obvious way to
2051 save a register file writeback) */
2052 if (GET_CODE (addr) == POST_INC)
2053 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2054 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2059 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2061 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2063 operands[0] = XEXP (addr, 0);
2064 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2067 if (!reg_overlap_mentioned_p (high_reg, addr))
2069 /* No overlap between high target register and address
2070 register. (We do this in a non-obvious way to
2071 save a register file writeback) */
2072 if (GET_CODE (addr) == PRE_INC)
2073 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2074 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2080 if (optype1 == MEMOP)
2082 /* We have to output the address syntax ourselves, since print_operand
2083 doesn't deal with the addresses we want to use. Fix this later. */
2085 rtx addr = XEXP (operands[1], 0);
2086 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2088 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2090 operands[1] = XEXP (addr, 0);
2091 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2094 if (!reg_overlap_mentioned_p (high_reg, addr))
2096 /* No overlap between high target register and address
2097 register. (We do this in a non-obvious way to
2098 save a register file writeback) */
2099 if (GET_CODE (addr) == POST_INC)
2100 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2101 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2105 /* This is an undefined situation. We should load into the
2106 address register *and* update that register. Probably
2107 we don't need to handle this at all. */
2108 if (GET_CODE (addr) == POST_INC)
2109 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2110 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2113 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2115 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2117 operands[1] = XEXP (addr, 0);
2118 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2121 if (!reg_overlap_mentioned_p (high_reg, addr))
2123 /* No overlap between high target register and address
2124 register. (We do this in a non-obvious way to
2125 save a register file writeback) */
2126 if (GET_CODE (addr) == PRE_INC)
2127 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2128 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2132 /* This is an undefined situation. We should load into the
2133 address register *and* update that register. Probably
2134 we don't need to handle this at all. */
2135 if (GET_CODE (addr) == PRE_INC)
2136 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2137 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2140 else if (GET_CODE (addr) == PLUS
2141 && GET_CODE (XEXP (addr, 0)) == MULT)
2143 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2145 if (!reg_overlap_mentioned_p (high_reg, addr))
2149 xoperands[0] = high_reg;
2150 xoperands[1] = XEXP (addr, 1);
2151 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2152 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2153 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2155 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2161 xoperands[0] = high_reg;
2162 xoperands[1] = XEXP (addr, 1);
2163 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2164 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2165 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2167 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2172 /* If an operand is an unoffsettable memory ref, find a register
2173 we can increment temporarily to make it refer to the second word. */
2175 if (optype0 == MEMOP)
2176 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2178 if (optype1 == MEMOP)
2179 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2181 /* Ok, we can do one word at a time.
2182 Normally we do the low-numbered word first.
2184 In either case, set up in LATEHALF the operands to use
2185 for the high-numbered word and in some cases alter the
2186 operands in OPERANDS to be suitable for the low-numbered word. */
2188 if (optype0 == REGOP)
2189 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2190 else if (optype0 == OFFSOP)
2191 latehalf[0] = adjust_address (operands[0], SImode, 4);
2193 latehalf[0] = operands[0];
2195 if (optype1 == REGOP)
2196 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2197 else if (optype1 == OFFSOP)
2198 latehalf[1] = adjust_address (operands[1], SImode, 4);
2199 else if (optype1 == CNSTOP)
2200 split_double (operands[1], &operands[1], &latehalf[1]);
2202 latehalf[1] = operands[1];
2204 /* If the first move would clobber the source of the second one,
2205 do them in the other order.
2207 This can happen in two cases:
2209 mem -> register where the first half of the destination register
2210 is the same register used in the memory's address. Reload
2211 can create such insns.
2213 mem in this case will be either register indirect or register
2214 indirect plus a valid offset.
2216 register -> register move where REGNO(dst) == REGNO(src + 1)
2217 someone (Tim/Tege?) claimed this can happen for parameter loads.
2219 Handle mem -> register case first. */
2220 if (optype0 == REGOP
2221 && (optype1 == MEMOP || optype1 == OFFSOP)
2222 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2225 /* Do the late half first. */
2227 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2228 output_asm_insn (singlemove_string (latehalf), latehalf);
2232 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2233 return singlemove_string (operands);
2236 /* Now handle register -> register case. */
2237 if (optype0 == REGOP && optype1 == REGOP
2238 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2240 output_asm_insn (singlemove_string (latehalf), latehalf);
2241 return singlemove_string (operands);
2244 /* Normal case: do the two words, low-numbered first. */
2246 output_asm_insn (singlemove_string (operands), operands);
2248 /* Make any unoffsettable addresses point at high-numbered word. */
2250 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2252 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2255 output_asm_insn (singlemove_string (latehalf), latehalf);
2257 /* Undo the adds we just did. */
2259 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2261 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2267 output_fp_move_double (operands)
2270 if (FP_REG_P (operands[0]))
2272 if (FP_REG_P (operands[1])
2273 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2274 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2276 output_asm_insn ("fldd%F1 %1,%0", operands);
2278 else if (FP_REG_P (operands[1]))
2280 output_asm_insn ("fstd%F0 %1,%0", operands);
2282 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2284 if (GET_CODE (operands[0]) == REG)
2287 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2288 xoperands[0] = operands[0];
2289 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2291 /* This is a pain. You have to be prepared to deal with an
2292 arbitrary address here including pre/post increment/decrement.
2294 so avoid this in the MD. */
2302 /* Return a REG that occurs in ADDR with coefficient 1.
2303 ADDR can be effectively incremented by incrementing REG. */
2306 find_addr_reg (addr)
2309 while (GET_CODE (addr) == PLUS)
2311 if (GET_CODE (XEXP (addr, 0)) == REG)
2312 addr = XEXP (addr, 0);
2313 else if (GET_CODE (XEXP (addr, 1)) == REG)
2314 addr = XEXP (addr, 1);
2315 else if (CONSTANT_P (XEXP (addr, 0)))
2316 addr = XEXP (addr, 1);
2317 else if (CONSTANT_P (XEXP (addr, 1)))
2318 addr = XEXP (addr, 0);
2322 if (GET_CODE (addr) == REG)
2327 /* Emit code to perform a block move.
2329 OPERANDS[0] is the destination pointer as a REG, clobbered.
2330 OPERANDS[1] is the source pointer as a REG, clobbered.
2331 OPERANDS[2] is a register for temporary storage.
2332 OPERANDS[4] is the size as a CONST_INT
2333 OPERANDS[3] is a register for temporary storage.
2334 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2335 OPERANDS[6] is another temporary register. */
2338 output_block_move (operands, size_is_constant)
2340 int size_is_constant ATTRIBUTE_UNUSED;
2342 int align = INTVAL (operands[5]);
2343 unsigned long n_bytes = INTVAL (operands[4]);
2345 /* We can't move more than four bytes at a time because the PA
2346 has no longer integer move insns. (Could use fp mem ops?) */
2350 /* Note that we know each loop below will execute at least twice
2351 (else we would have open-coded the copy). */
2355 /* Pre-adjust the loop counter. */
2356 operands[4] = GEN_INT (n_bytes - 8);
2357 output_asm_insn ("ldi %4,%2", operands);
2360 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2361 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2362 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2363 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2364 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2366 /* Handle the residual. There could be up to 7 bytes of
2367 residual to copy! */
2368 if (n_bytes % 8 != 0)
2370 operands[4] = GEN_INT (n_bytes % 4);
2371 if (n_bytes % 8 >= 4)
2372 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2373 if (n_bytes % 4 != 0)
2374 output_asm_insn ("ldw 0(%1),%6", operands);
2375 if (n_bytes % 8 >= 4)
2376 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2377 if (n_bytes % 4 != 0)
2378 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2383 /* Pre-adjust the loop counter. */
2384 operands[4] = GEN_INT (n_bytes - 4);
2385 output_asm_insn ("ldi %4,%2", operands);
2388 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2389 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2390 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2391 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2392 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2394 /* Handle the residual. */
2395 if (n_bytes % 4 != 0)
2397 if (n_bytes % 4 >= 2)
2398 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2399 if (n_bytes % 2 != 0)
2400 output_asm_insn ("ldb 0(%1),%6", operands);
2401 if (n_bytes % 4 >= 2)
2402 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2403 if (n_bytes % 2 != 0)
2404 output_asm_insn ("stb %6,0(%0)", operands);
2409 /* Pre-adjust the loop counter. */
2410 operands[4] = GEN_INT (n_bytes - 2);
2411 output_asm_insn ("ldi %4,%2", operands);
2414 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2415 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2416 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2417 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2418 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2420 /* Handle the residual. */
2421 if (n_bytes % 2 != 0)
2423 output_asm_insn ("ldb 0(%1),%3", operands);
2424 output_asm_insn ("stb %3,0(%0)", operands);
2433 /* Count the number of insns necessary to handle this block move.
2435 Basic structure is the same as emit_block_move, except that we
2436 count insns rather than emit them. */
2439 compute_movstrsi_length (insn)
2442 rtx pat = PATTERN (insn);
2443 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2444 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2445 unsigned int n_insns = 0;
2447 /* We can't move more than four bytes at a time because the PA
2448 has no longer integer move insns. (Could use fp mem ops?) */
2452 /* The basic copying loop. */
2456 if (n_bytes % (2 * align) != 0)
2458 if ((n_bytes % (2 * align)) >= align)
2461 if ((n_bytes % align) != 0)
2465 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2471 output_and (operands)
2474 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2476 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2477 int ls0, ls1, ms0, p, len;
2479 for (ls0 = 0; ls0 < 32; ls0++)
2480 if ((mask & (1 << ls0)) == 0)
2483 for (ls1 = ls0; ls1 < 32; ls1++)
2484 if ((mask & (1 << ls1)) != 0)
2487 for (ms0 = ls1; ms0 < 32; ms0++)
2488 if ((mask & (1 << ms0)) == 0)
2501 operands[2] = GEN_INT (len);
2502 return "{extru|extrw,u} %1,31,%2,%0";
2506 /* We could use this `depi' for the case above as well, but `depi'
2507 requires one more register file access than an `extru'. */
2512 operands[2] = GEN_INT (p);
2513 operands[3] = GEN_INT (len);
2514 return "{depi|depwi} 0,%2,%3,%0";
2518 return "and %1,%2,%0";
2521 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2522 storing the result in operands[0]. */
2524 output_64bit_and (operands)
2527 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2529 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2530 int ls0, ls1, ms0, p, len;
2532 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2533 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2536 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2537 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2540 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2541 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2544 if (ms0 != HOST_BITS_PER_WIDE_INT)
2547 if (ls1 == HOST_BITS_PER_WIDE_INT)
2554 operands[2] = GEN_INT (len);
2555 return "extrd,u %1,63,%2,%0";
2559 /* We could use this `depi' for the case above as well, but `depi'
2560 requires one more register file access than an `extru'. */
2565 operands[2] = GEN_INT (p);
2566 operands[3] = GEN_INT (len);
2567 return "depdi 0,%2,%3,%0";
2571 return "and %1,%2,%0";
2575 output_ior (operands)
2578 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2579 int bs0, bs1, p, len;
2581 if (INTVAL (operands[2]) == 0)
2582 return "copy %1,%0";
2584 for (bs0 = 0; bs0 < 32; bs0++)
2585 if ((mask & (1 << bs0)) != 0)
2588 for (bs1 = bs0; bs1 < 32; bs1++)
2589 if ((mask & (1 << bs1)) == 0)
2592 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2598 operands[2] = GEN_INT (p);
2599 operands[3] = GEN_INT (len);
2600 return "{depi|depwi} -1,%2,%3,%0";
2603 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2604 storing the result in operands[0]. */
2606 output_64bit_ior (operands)
2609 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2610 int bs0, bs1, p, len;
2612 if (INTVAL (operands[2]) == 0)
2613 return "copy %1,%0";
2615 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2616 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2619 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2620 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2623 if (bs1 != HOST_BITS_PER_WIDE_INT
2624 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2630 operands[2] = GEN_INT (p);
2631 operands[3] = GEN_INT (len);
2632 return "depdi -1,%2,%3,%0";
2635 /* Target hook for assembling integer objects. This code handles
2636 aligned SI and DI integers specially, since function references must
2637 be preceded by P%. */
2640 pa_assemble_integer (x, size, aligned_p)
2645 if (size == UNITS_PER_WORD && aligned_p
2646 && function_label_operand (x, VOIDmode))
2648 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2649 output_addr_const (asm_out_file, x);
2650 fputc ('\n', asm_out_file);
2653 return default_assemble_integer (x, size, aligned_p);
2656 /* Output an ascii string. */
2658 output_ascii (file, p, size)
2665 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2667 /* The HP assembler can only take strings of 256 characters at one
2668 time. This is a limitation on input line length, *not* the
2669 length of the string. Sigh. Even worse, it seems that the
2670 restriction is in number of input characters (see \xnn &
2671 \whatever). So we have to do this very carefully. */
2673 fputs ("\t.STRING \"", file);
2676 for (i = 0; i < size; i += 4)
2680 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2682 register unsigned int c = (unsigned char) p[i + io];
2684 if (c == '\"' || c == '\\')
2685 partial_output[co++] = '\\';
2686 if (c >= ' ' && c < 0177)
2687 partial_output[co++] = c;
2691 partial_output[co++] = '\\';
2692 partial_output[co++] = 'x';
2693 hexd = c / 16 - 0 + '0';
2695 hexd -= '9' - 'a' + 1;
2696 partial_output[co++] = hexd;
2697 hexd = c % 16 - 0 + '0';
2699 hexd -= '9' - 'a' + 1;
2700 partial_output[co++] = hexd;
2703 if (chars_output + co > 243)
2705 fputs ("\"\n\t.STRING \"", file);
2708 fwrite (partial_output, 1, (size_t) co, file);
2712 fputs ("\"\n", file);
2715 /* Try to rewrite floating point comparisons & branches to avoid
2716 useless add,tr insns.
2718 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2719 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2720 first attempt to remove useless add,tr insns. It is zero
2721 for the second pass as reorg sometimes leaves bogus REG_DEAD
2724 When CHECK_NOTES is zero we can only eliminate add,tr insns
2725 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2728 remove_useless_addtr_insns (insns, check_notes)
2733 static int pass = 0;
2735 /* This is fairly cheap, so always run it when optimizing. */
2739 int fbranch_count = 0;
2741 /* Walk all the insns in this function looking for fcmp & fbranch
2742 instructions. Keep track of how many of each we find. */
2743 insns = get_insns ();
2744 for (insn = insns; insn; insn = next_insn (insn))
2748 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2749 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2752 tmp = PATTERN (insn);
2754 /* It must be a set. */
2755 if (GET_CODE (tmp) != SET)
2758 /* If the destination is CCFP, then we've found an fcmp insn. */
2759 tmp = SET_DEST (tmp);
2760 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2766 tmp = PATTERN (insn);
2767 /* If this is an fbranch instruction, bump the fbranch counter. */
2768 if (GET_CODE (tmp) == SET
2769 && SET_DEST (tmp) == pc_rtx
2770 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2771 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2772 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2773 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2781 /* Find all floating point compare + branch insns. If possible,
2782 reverse the comparison & the branch to avoid add,tr insns. */
2783 for (insn = insns; insn; insn = next_insn (insn))
2787 /* Ignore anything that isn't an INSN. */
2788 if (GET_CODE (insn) != INSN)
2791 tmp = PATTERN (insn);
2793 /* It must be a set. */
2794 if (GET_CODE (tmp) != SET)
2797 /* The destination must be CCFP, which is register zero. */
2798 tmp = SET_DEST (tmp);
2799 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2802 /* INSN should be a set of CCFP.
2804 See if the result of this insn is used in a reversed FP
2805 conditional branch. If so, reverse our condition and
2806 the branch. Doing so avoids useless add,tr insns. */
2807 next = next_insn (insn);
2810 /* Jumps, calls and labels stop our search. */
2811 if (GET_CODE (next) == JUMP_INSN
2812 || GET_CODE (next) == CALL_INSN
2813 || GET_CODE (next) == CODE_LABEL)
2816 /* As does another fcmp insn. */
2817 if (GET_CODE (next) == INSN
2818 && GET_CODE (PATTERN (next)) == SET
2819 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2820 && REGNO (SET_DEST (PATTERN (next))) == 0)
2823 next = next_insn (next);
2826 /* Is NEXT_INSN a branch? */
2828 && GET_CODE (next) == JUMP_INSN)
2830 rtx pattern = PATTERN (next);
2832 /* If it a reversed fp conditional branch (eg uses add,tr)
2833 and CCFP dies, then reverse our conditional and the branch
2834 to avoid the add,tr. */
2835 if (GET_CODE (pattern) == SET
2836 && SET_DEST (pattern) == pc_rtx
2837 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2838 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2839 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2840 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2841 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2842 && (fcmp_count == fbranch_count
2844 && find_regno_note (next, REG_DEAD, 0))))
2846 /* Reverse the branch. */
2847 tmp = XEXP (SET_SRC (pattern), 1);
2848 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2849 XEXP (SET_SRC (pattern), 2) = tmp;
2850 INSN_CODE (next) = -1;
2852 /* Reverse our condition. */
2853 tmp = PATTERN (insn);
2854 PUT_CODE (XEXP (tmp, 1),
2855 (reverse_condition_maybe_unordered
2856 (GET_CODE (XEXP (tmp, 1)))));
2866 /* You may have trouble believing this, but this is the 32 bit HP-PA
2871 Variable arguments (optional; any number may be allocated)
2873 SP-(4*(N+9)) arg word N
2878 Fixed arguments (must be allocated; may remain unused)
2887 SP-32 External Data Pointer (DP)
2889 SP-24 External/stub RP (RP')
2893 SP-8 Calling Stub RP (RP'')
2898 SP-0 Stack Pointer (points to next available address)
2902 /* This function saves registers as follows. Registers marked with ' are
2903 this function's registers (as opposed to the previous function's).
2904 If a frame_pointer isn't needed, r4 is saved as a general register;
2905 the space for the frame pointer is still allocated, though, to keep
2911 SP (FP') Previous FP
2912 SP + 4 Alignment filler (sigh)
2913 SP + 8 Space for locals reserved here.
2917 SP + n All call saved register used.
2921 SP + o All call saved fp registers used.
2925 SP + p (SP') points to next available address.
2929 /* Global variables set by output_function_prologue(). */
2930 /* Size of frame. Need to know this to emit return insns from
2932 static int actual_fsize;
2933 static int local_fsize, save_fregs;
2935 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2936 Handle case where DISP > 8k by using the add_high_const patterns.
2938 Note in DISP > 8k case, we will leave the high part of the address
2939 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2942 store_reg (reg, disp, base)
2943 int reg, disp, base;
2945 rtx insn, dest, src, basereg;
2947 src = gen_rtx_REG (word_mode, reg);
2948 basereg = gen_rtx_REG (Pmode, base);
2949 if (VAL_14_BITS_P (disp))
2951 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2952 insn = emit_move_insn (dest, src);
2956 rtx delta = GEN_INT (disp);
2957 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
2958 rtx tmpreg = gen_rtx_REG (Pmode, 1);
2959 emit_move_insn (tmpreg, high);
2960 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
2961 insn = emit_move_insn (dest, src);
2965 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2966 gen_rtx_SET (VOIDmode,
2967 gen_rtx_MEM (word_mode,
2968 gen_rtx_PLUS (word_mode, basereg,
2976 RTX_FRAME_RELATED_P (insn) = 1;
2979 /* Emit RTL to store REG at the memory location specified by BASE and then
2980 add MOD to BASE. MOD must be <= 8k. */
2983 store_reg_modify (base, reg, mod)
2986 rtx insn, basereg, srcreg, delta;
2988 if (! VAL_14_BITS_P (mod))
2991 basereg = gen_rtx_REG (Pmode, base);
2992 srcreg = gen_rtx_REG (word_mode, reg);
2993 delta = GEN_INT (mod);
2995 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
2998 RTX_FRAME_RELATED_P (insn) = 1;
3000 /* RTX_FRAME_RELATED_P must be set on each frame related set
3001 in a parallel with more than one element. Don't set
3002 RTX_FRAME_RELATED_P in the first set if reg is temporary
3003 register 1. The effect of this operation is recorded in
3004 the initial copy. */
3007 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3008 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3012 /* The first element of a PARALLEL is always processed if it is
3013 a SET. Thus, we need an expression list for this case. */
3015 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3016 gen_rtx_SET (VOIDmode, basereg,
3017 gen_rtx_PLUS (word_mode, basereg, delta)),
3023 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3024 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3025 whether to add a frame note or not.
3027 In the DISP > 8k case, we leave the high part of the address in %r1.
3028 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3031 set_reg_plus_d (reg, base, disp, note)
3032 int reg, base, disp, note;
3036 if (VAL_14_BITS_P (disp))
3038 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3039 plus_constant (gen_rtx_REG (Pmode, base), disp));
3043 rtx basereg = gen_rtx_REG (Pmode, base);
3044 rtx delta = GEN_INT (disp);
3046 emit_move_insn (gen_rtx_REG (Pmode, 1),
3047 gen_rtx_PLUS (Pmode, basereg,
3048 gen_rtx_HIGH (Pmode, delta)));
3049 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3050 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
3054 if (DO_FRAME_NOTES && note)
3055 RTX_FRAME_RELATED_P (insn) = 1;
3059 compute_frame_size (size, fregs_live)
3065 /* Space for frame pointer + filler. If any frame is allocated
3066 we need to add this in because of STARTING_FRAME_OFFSET.
3068 Similar code also appears in hppa_expand_prologue. Change both
3069 of them at the same time. */
3070 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
3072 /* If the current function calls __builtin_eh_return, then we need
3073 to allocate stack space for registers that will hold data for
3074 the exception handler. */
3075 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3079 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3081 fsize += i * UNITS_PER_WORD;
3084 /* Account for space used by the callee general register saves. */
3085 for (i = 18; i >= 3; i--)
3086 if (regs_ever_live[i])
3087 fsize += UNITS_PER_WORD;
3089 /* Round the stack. */
3090 fsize = (fsize + 7) & ~7;
3092 /* Account for space used by the callee floating point register saves. */
3093 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3094 if (regs_ever_live[i]
3095 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3100 /* We always save both halves of the FP register, so always
3101 increment the frame size by 8 bytes. */
3105 /* The various ABIs include space for the outgoing parameters in the
3106 size of the current function's stack frame. */
3107 fsize += current_function_outgoing_args_size;
3109 /* Allocate space for the fixed frame marker. This space must be
3110 allocated for any function that makes calls or otherwise allocates
3112 if (!current_function_is_leaf || fsize)
3113 fsize += TARGET_64BIT ? 16 : 32;
3115 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
3118 /* Generate the assembly code for function entry. FILE is a stdio
3119 stream to output the code to. SIZE is an int: how many units of
3120 temporary storage to allocate.
3122 Refer to the array `regs_ever_live' to determine which registers to
3123 save; `regs_ever_live[I]' is nonzero if register number I is ever
3124 used in the function. This function is responsible for knowing
3125 which registers should not be saved even if used. */
3127 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3128 of memory. If any fpu reg is used in the function, we allocate
3129 such a block here, at the bottom of the frame, just in case it's needed.
3131 If this function is a leaf procedure, then we may choose not
3132 to do a "save" insn. The decision about whether or not
3133 to do this is made in regclass.c. */
3136 pa_output_function_prologue (file, size)
3138 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3140 /* The function's label and associated .PROC must never be
3141 separated and must be output *after* any profiling declarations
3142 to avoid changing spaces/subspaces within a procedure. */
3143 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3144 fputs ("\t.PROC\n", file);
3146 /* hppa_expand_prologue does the dirty work now. We just need
3147 to output the assembler directives which denote the start
3149 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
3150 if (regs_ever_live[2])
3151 fputs (",CALLS,SAVE_RP", file);
3153 fputs (",NO_CALLS", file);
3155 if (frame_pointer_needed)
3156 fputs (",SAVE_SP", file);
3158 /* Pass on information about the number of callee register saves
3159 performed in the prologue.
3161 The compiler is supposed to pass the highest register number
3162 saved, the assembler then has to adjust that number before
3163 entering it into the unwind descriptor (to account for any
3164 caller saved registers with lower register numbers than the
3165 first callee saved register). */
3167 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3170 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3172 fputs ("\n\t.ENTRY\n", file);
3174 /* If we're using GAS and SOM, and not using the portable runtime model,
3175 then we don't need to accumulate the total number of code bytes. */
3176 if ((TARGET_GAS && TARGET_SOM && ! TARGET_PORTABLE_RUNTIME)
3177 /* FIXME: we can't handle long calls for TARGET_64BIT. */
3179 total_code_bytes = 0;
3180 else if (INSN_ADDRESSES_SET_P ())
3182 unsigned int old_total = total_code_bytes;
3184 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_insn ()));
3185 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3187 /* Be prepared to handle overflows. */
3188 if (old_total > total_code_bytes)
3189 total_code_bytes = -1;
3192 total_code_bytes = -1;
3194 remove_useless_addtr_insns (get_insns (), 0);
3198 hppa_expand_prologue ()
3200 int size = get_frame_size ();
3201 int merge_sp_adjust_with_store = 0;
3209 /* Allocate space for frame pointer + filler. If any frame is allocated
3210 we need to add this in because of STARTING_FRAME_OFFSET.
3212 Similar code also appears in compute_frame_size. Change both
3213 of them at the same time. */
3214 local_fsize = size + (size || frame_pointer_needed
3215 ? STARTING_FRAME_OFFSET : 0);
3217 actual_fsize = compute_frame_size (size, &save_fregs);
3219 /* Compute a few things we will use often. */
3220 tmpreg = gen_rtx_REG (word_mode, 1);
3222 /* Save RP first. The calling conventions manual states RP will
3223 always be stored into the caller's frame at sp - 20 or sp - 16
3224 depending on which ABI is in use. */
3225 if (regs_ever_live[2] || current_function_calls_eh_return)
3226 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3228 /* Allocate the local frame and set up the frame pointer if needed. */
3229 if (actual_fsize != 0)
3231 if (frame_pointer_needed)
3233 /* Copy the old frame pointer temporarily into %r1. Set up the
3234 new stack pointer, then store away the saved old frame pointer
3235 into the stack at sp and at the same time update the stack
3236 pointer by actual_fsize bytes. Two versions, first
3237 handles small (<8k) frames. The second handles large (>=8k)
3239 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3242 /* We need to record the frame pointer save here since the
3243 new frame pointer is set in the following insn. */
3244 RTX_FRAME_RELATED_P (insn) = 1;
3246 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3247 gen_rtx_SET (VOIDmode,
3248 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3253 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3255 RTX_FRAME_RELATED_P (insn) = 1;
3257 if (VAL_14_BITS_P (actual_fsize))
3258 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3261 /* It is incorrect to store the saved frame pointer at *sp,
3262 then increment sp (writes beyond the current stack boundary).
3264 So instead use stwm to store at *sp and post-increment the
3265 stack pointer as an atomic operation. Then increment sp to
3266 finish allocating the new frame. */
3267 int adjust1 = 8192 - 64;
3268 int adjust2 = actual_fsize - adjust1;
3270 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3271 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3275 /* Prevent register spills from being scheduled before the
3276 stack pointer is raised. Necessary as we will be storing
3277 registers using the frame pointer as a base register, and
3278 we happen to set fp before raising sp. */
3279 emit_insn (gen_blockage ());
3281 /* no frame pointer needed. */
3284 /* In some cases we can perform the first callee register save
3285 and allocating the stack frame at the same time. If so, just
3286 make a note of it and defer allocating the frame until saving
3287 the callee registers. */
3288 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3289 merge_sp_adjust_with_store = 1;
3290 /* Can not optimize. Adjust the stack frame by actual_fsize
3293 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3298 /* Normal register save.
3300 Do not save the frame pointer in the frame_pointer_needed case. It
3301 was done earlier. */
3302 if (frame_pointer_needed)
3304 offset = local_fsize;
3306 /* Saving the EH return data registers in the frame is the simplest
3307 way to get the frame unwind information emitted. We put them
3308 just before the general registers. */
3309 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3311 unsigned int i, regno;
3315 regno = EH_RETURN_DATA_REGNO (i);
3316 if (regno == INVALID_REGNUM)
3319 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3320 offset += UNITS_PER_WORD;
3324 for (i = 18; i >= 4; i--)
3325 if (regs_ever_live[i] && ! call_used_regs[i])
3327 store_reg (i, offset, FRAME_POINTER_REGNUM);
3328 offset += UNITS_PER_WORD;
3331 /* Account for %r3 which is saved in a special place. */
3334 /* No frame pointer needed. */
3337 offset = local_fsize - actual_fsize;
3339 /* Saving the EH return data registers in the frame is the simplest
3340 way to get the frame unwind information emitted. */
3341 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3343 unsigned int i, regno;
3347 regno = EH_RETURN_DATA_REGNO (i);
3348 if (regno == INVALID_REGNUM)
3351 /* If merge_sp_adjust_with_store is nonzero, then we can
3352 optimize the first save. */
3353 if (merge_sp_adjust_with_store)
3355 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3356 merge_sp_adjust_with_store = 0;
3359 store_reg (regno, offset, STACK_POINTER_REGNUM);
3360 offset += UNITS_PER_WORD;
3364 for (i = 18; i >= 3; i--)
3365 if (regs_ever_live[i] && ! call_used_regs[i])
3367 /* If merge_sp_adjust_with_store is nonzero, then we can
3368 optimize the first GR save. */
3369 if (merge_sp_adjust_with_store)
3371 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3372 merge_sp_adjust_with_store = 0;
3375 store_reg (i, offset, STACK_POINTER_REGNUM);
3376 offset += UNITS_PER_WORD;
3380 /* If we wanted to merge the SP adjustment with a GR save, but we never
3381 did any GR saves, then just emit the adjustment here. */
3382 if (merge_sp_adjust_with_store)
3383 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3387 /* The hppa calling conventions say that %r19, the pic offset
3388 register, is saved at sp - 32 (in this function's frame)
3389 when generating PIC code. FIXME: What is the correct thing
3390 to do for functions which make no calls and allocate no
3391 frame? Do we need to allocate a frame, or can we just omit
3392 the save? For now we'll just omit the save. */
3393 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3394 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3396 /* Align pointer properly (doubleword boundary). */
3397 offset = (offset + 7) & ~7;
3399 /* Floating point register store. */
3404 /* First get the frame or stack pointer to the start of the FP register
3406 if (frame_pointer_needed)
3408 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3409 base = frame_pointer_rtx;
3413 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3414 base = stack_pointer_rtx;
3417 /* Now actually save the FP registers. */
3418 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3420 if (regs_ever_live[i]
3421 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3423 rtx addr, insn, reg;
3424 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3425 reg = gen_rtx_REG (DFmode, i);
3426 insn = emit_move_insn (addr, reg);
3429 RTX_FRAME_RELATED_P (insn) = 1;
3432 rtx mem = gen_rtx_MEM (DFmode,
3433 plus_constant (base, offset));
3435 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3436 gen_rtx_SET (VOIDmode, mem, reg),
3441 rtx meml = gen_rtx_MEM (SFmode,
3442 plus_constant (base, offset));
3443 rtx memr = gen_rtx_MEM (SFmode,
3444 plus_constant (base, offset + 4));
3445 rtx regl = gen_rtx_REG (SFmode, i);
3446 rtx regr = gen_rtx_REG (SFmode, i + 1);
3447 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3448 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3451 RTX_FRAME_RELATED_P (setl) = 1;
3452 RTX_FRAME_RELATED_P (setr) = 1;
3453 vec = gen_rtvec (2, setl, setr);
3455 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3456 gen_rtx_SEQUENCE (VOIDmode, vec),
3460 offset += GET_MODE_SIZE (DFmode);
3466 /* FIXME: expand_call and expand_millicode_call need to be fixed to
3467 prevent insns with frame notes being scheduled in the delay slot
3468 of calls. This causes problems because the dwarf2 output code
3469 processes the insn list serially. For now, limit the migration
3470 of prologue insns with a blockage. */
3472 emit_insn (gen_blockage ());
3475 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3476 Handle case where DISP > 8k by using the add_high_const patterns. */
3479 load_reg (reg, disp, base)
3480 int reg, disp, base;
3482 rtx src, dest, basereg;
3484 dest = gen_rtx_REG (word_mode, reg);
3485 basereg = gen_rtx_REG (Pmode, base);
3486 if (VAL_14_BITS_P (disp))
3488 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3489 emit_move_insn (dest, src);
3493 rtx delta = GEN_INT (disp);
3494 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3495 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3496 emit_move_insn (tmpreg, high);
3497 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3498 emit_move_insn (dest, src);
3502 /* This function generates the assembly code for function exit.
3503 Args are as for output_function_prologue ().
3505 The function epilogue should not depend on the current stack
3506 pointer! It should use the frame pointer only. This is mandatory
3507 because of alloca; we also take advantage of it to omit stack
3508 adjustments before returning. */
3511 pa_output_function_epilogue (file, size)
3513 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3515 rtx insn = get_last_insn ();
3517 /* hppa_expand_epilogue does the dirty work now. We just need
3518 to output the assembler directives which denote the end
3521 To make debuggers happy, emit a nop if the epilogue was completely
3522 eliminated due to a volatile call as the last insn in the
3523 current function. That way the return address (in %r2) will
3524 always point to a valid instruction in the current function. */
3526 /* Get the last real insn. */
3527 if (GET_CODE (insn) == NOTE)
3528 insn = prev_real_insn (insn);
3530 /* If it is a sequence, then look inside. */
3531 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3532 insn = XVECEXP (PATTERN (insn), 0, 0);
3534 /* If insn is a CALL_INSN, then it must be a call to a volatile
3535 function (otherwise there would be epilogue insns). */
3536 if (insn && GET_CODE (insn) == CALL_INSN)
3537 fputs ("\tnop\n", file);
3539 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3543 hppa_expand_epilogue ()
3547 int merge_sp_adjust_with_load = 0;
3550 /* We will use this often. */
3551 tmpreg = gen_rtx_REG (word_mode, 1);
3553 /* Try to restore RP early to avoid load/use interlocks when
3554 RP gets used in the return (bv) instruction. This appears to still
3555 be necessary even when we schedule the prologue and epilogue. */
3556 if (regs_ever_live [2] || current_function_calls_eh_return)
3558 ret_off = TARGET_64BIT ? -16 : -20;
3559 if (frame_pointer_needed)
3561 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3566 /* No frame pointer, and stack is smaller than 8k. */
3567 if (VAL_14_BITS_P (ret_off - actual_fsize))
3569 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3575 /* General register restores. */
3576 if (frame_pointer_needed)
3578 offset = local_fsize;
3580 /* If the current function calls __builtin_eh_return, then we need
3581 to restore the saved EH data registers. */
3582 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3584 unsigned int i, regno;
3588 regno = EH_RETURN_DATA_REGNO (i);
3589 if (regno == INVALID_REGNUM)
3592 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3593 offset += UNITS_PER_WORD;
3597 for (i = 18; i >= 4; i--)
3598 if (regs_ever_live[i] && ! call_used_regs[i])
3600 load_reg (i, offset, FRAME_POINTER_REGNUM);
3601 offset += UNITS_PER_WORD;
3606 offset = local_fsize - actual_fsize;
3608 /* If the current function calls __builtin_eh_return, then we need
3609 to restore the saved EH data registers. */
3610 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3612 unsigned int i, regno;
3616 regno = EH_RETURN_DATA_REGNO (i);
3617 if (regno == INVALID_REGNUM)
3620 /* Only for the first load.
3621 merge_sp_adjust_with_load holds the register load
3622 with which we will merge the sp adjustment. */
3623 if (merge_sp_adjust_with_load == 0
3625 && VAL_14_BITS_P (-actual_fsize))
3626 merge_sp_adjust_with_load = regno;
3628 load_reg (regno, offset, STACK_POINTER_REGNUM);
3629 offset += UNITS_PER_WORD;
3633 for (i = 18; i >= 3; i--)
3635 if (regs_ever_live[i] && ! call_used_regs[i])
3637 /* Only for the first load.
3638 merge_sp_adjust_with_load holds the register load
3639 with which we will merge the sp adjustment. */
3640 if (merge_sp_adjust_with_load == 0
3642 && VAL_14_BITS_P (-actual_fsize))
3643 merge_sp_adjust_with_load = i;
3645 load_reg (i, offset, STACK_POINTER_REGNUM);
3646 offset += UNITS_PER_WORD;
3651 /* Align pointer properly (doubleword boundary). */
3652 offset = (offset + 7) & ~7;
3654 /* FP register restores. */
3657 /* Adjust the register to index off of. */
3658 if (frame_pointer_needed)
3659 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3661 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3663 /* Actually do the restores now. */
3664 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3665 if (regs_ever_live[i]
3666 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3668 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3669 rtx dest = gen_rtx_REG (DFmode, i);
3670 emit_move_insn (dest, src);
3674 /* Emit a blockage insn here to keep these insns from being moved to
3675 an earlier spot in the epilogue, or into the main instruction stream.
3677 This is necessary as we must not cut the stack back before all the
3678 restores are finished. */
3679 emit_insn (gen_blockage ());
3681 /* Reset stack pointer (and possibly frame pointer). The stack
3682 pointer is initially set to fp + 64 to avoid a race condition. */
3683 if (frame_pointer_needed)
3685 rtx delta = GEN_INT (-64);
3687 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
3688 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
3690 /* If we were deferring a callee register restore, do it now. */
3691 else if (merge_sp_adjust_with_load)
3693 rtx delta = GEN_INT (-actual_fsize);
3694 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3696 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
3698 else if (actual_fsize != 0)
3699 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3702 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3703 frame greater than 8k), do so now. */
3705 load_reg (2, ret_off, STACK_POINTER_REGNUM);
3707 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3709 rtx sa = EH_RETURN_STACKADJ_RTX;
3711 emit_insn (gen_blockage ());
3712 emit_insn (TARGET_64BIT
3713 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
3714 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
3719 hppa_pic_save_rtx ()
3721 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3725 hppa_profile_hook (label_no)
3728 rtx begin_label_rtx, call_insn;
3729 char begin_label_name[16];
3731 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3733 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3736 emit_move_insn (arg_pointer_rtx,
3737 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3740 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3742 #ifndef NO_PROFILE_COUNTERS
3744 rtx count_label_rtx, addr, r24;
3745 char count_label_name[16];
3747 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3748 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3750 addr = force_reg (Pmode, count_label_rtx);
3751 r24 = gen_rtx_REG (Pmode, 24);
3752 emit_move_insn (r24, addr);
3754 /* %r25 is set from within the output pattern. */
3756 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3757 GEN_INT (TARGET_64BIT ? 24 : 12),
3760 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3763 /* %r25 is set from within the output pattern. */
3765 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3766 GEN_INT (TARGET_64BIT ? 16 : 8),
3770 /* Indicate the _mcount call cannot throw, nor will it execute a
3772 REG_NOTES (call_insn)
3773 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3777 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3779 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3781 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3785 /* Fetch the return address for the frame COUNT steps up from
3786 the current frame, after the prologue. FRAMEADDR is the
3787 frame pointer of the COUNT frame.
3789 We want to ignore any export stub remnants here. To handle this,
3790 we examine the code at the return address, and if it is an export
3791 stub, we return a memory rtx for the stub return address stored
3794 The value returned is used in two different ways:
3796 1. To find a function's caller.
3798 2. To change the return address for a function.
3800 This function handles most instances of case 1; however, it will
3801 fail if there are two levels of stubs to execute on the return
3802 path. The only way I believe that can happen is if the return value
3803 needs a parameter relocation, which never happens for C code.
3805 This function handles most instances of case 2; however, it will
3806 fail if we did not originally have stub code on the return path
3807 but will need stub code on the new return path. This can happen if
3808 the caller & callee are both in the main program, but the new
3809 return location is in a shared library. */
3812 return_addr_rtx (count, frameaddr)
3824 rp = get_hard_reg_initial_val (Pmode, 2);
3826 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
3829 saved_rp = gen_reg_rtx (Pmode);
3830 emit_move_insn (saved_rp, rp);
3832 /* Get pointer to the instruction stream. We have to mask out the
3833 privilege level from the two low order bits of the return address
3834 pointer here so that ins will point to the start of the first
3835 instruction that would have been executed if we returned. */
3836 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
3837 label = gen_label_rtx ();
3839 /* Check the instruction stream at the normal return address for the
3842 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3843 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3844 0x00011820 | stub+16: mtsp r1,sr0
3845 0xe0400002 | stub+20: be,n 0(sr0,rp)
3847 If it is an export stub, than our return address is really in
3850 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
3851 NULL_RTX, SImode, 1);
3852 emit_jump_insn (gen_bne (label));
3854 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3855 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
3856 emit_jump_insn (gen_bne (label));
3858 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3859 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
3860 emit_jump_insn (gen_bne (label));
3862 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3863 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
3865 /* If there is no export stub then just use the value saved from
3866 the return pointer register. */
3868 emit_jump_insn (gen_bne (label));
3870 /* Here we know that our return address points to an export
3871 stub. We don't want to return the address of the export stub,
3872 but rather the return address of the export stub. That return
3873 address is stored at -24[frameaddr]. */
3875 emit_move_insn (saved_rp,
3877 memory_address (Pmode,
3878 plus_constant (frameaddr,
3885 /* This is only valid once reload has completed because it depends on
3886 knowing exactly how much (if any) frame there is and...
3888 It's only valid if there is no frame marker to de-allocate and...
3890 It's only valid if %r2 hasn't been saved into the caller's frame
3891 (we're not profiling and %r2 isn't live anywhere). */
3893 hppa_can_use_return_insn_p ()
3895 return (reload_completed
3896 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3897 && ! regs_ever_live[2]
3898 && ! frame_pointer_needed);
3902 emit_bcond_fp (code, operand0)
3906 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3907 gen_rtx_IF_THEN_ELSE (VOIDmode,
3908 gen_rtx_fmt_ee (code,
3910 gen_rtx_REG (CCFPmode, 0),
3912 gen_rtx_LABEL_REF (VOIDmode, operand0),
3918 gen_cmp_fp (code, operand0, operand1)
3920 rtx operand0, operand1;
3922 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3923 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3926 /* Adjust the cost of a scheduling dependency. Return the new cost of
3927 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3930 pa_adjust_cost (insn, link, dep_insn, cost)
3936 enum attr_type attr_type;
3938 /* Don't adjust costs for a pa8000 chip, also do not adjust any
3939 true dependencies as they are described with bypasses now. */
3940 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
3943 if (! recog_memoized (insn))
3946 attr_type = get_attr_type (insn);
3948 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3950 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3953 if (attr_type == TYPE_FPLOAD)
3955 rtx pat = PATTERN (insn);
3956 rtx dep_pat = PATTERN (dep_insn);
3957 if (GET_CODE (pat) == PARALLEL)
3959 /* This happens for the fldXs,mb patterns. */
3960 pat = XVECEXP (pat, 0, 0);
3962 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3963 /* If this happens, we have to extend this to schedule
3964 optimally. Return 0 for now. */
3967 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3969 if (! recog_memoized (dep_insn))
3971 switch (get_attr_type (dep_insn))
3978 case TYPE_FPSQRTSGL:
3979 case TYPE_FPSQRTDBL:
3980 /* A fpload can't be issued until one cycle before a
3981 preceding arithmetic operation has finished if
3982 the target of the fpload is any of the sources
3983 (or destination) of the arithmetic operation. */
3984 return insn_default_latency (dep_insn) - 1;
3991 else if (attr_type == TYPE_FPALU)
3993 rtx pat = PATTERN (insn);
3994 rtx dep_pat = PATTERN (dep_insn);
3995 if (GET_CODE (pat) == PARALLEL)
3997 /* This happens for the fldXs,mb patterns. */
3998 pat = XVECEXP (pat, 0, 0);
4000 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4001 /* If this happens, we have to extend this to schedule
4002 optimally. Return 0 for now. */
4005 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4007 if (! recog_memoized (dep_insn))
4009 switch (get_attr_type (dep_insn))
4013 case TYPE_FPSQRTSGL:
4014 case TYPE_FPSQRTDBL:
4015 /* An ALU flop can't be issued until two cycles before a
4016 preceding divide or sqrt operation has finished if
4017 the target of the ALU flop is any of the sources
4018 (or destination) of the divide or sqrt operation. */
4019 return insn_default_latency (dep_insn) - 2;
4027 /* For other anti dependencies, the cost is 0. */
4030 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4032 /* Output dependency; DEP_INSN writes a register that INSN writes some
4034 if (attr_type == TYPE_FPLOAD)
4036 rtx pat = PATTERN (insn);
4037 rtx dep_pat = PATTERN (dep_insn);
4038 if (GET_CODE (pat) == PARALLEL)
4040 /* This happens for the fldXs,mb patterns. */
4041 pat = XVECEXP (pat, 0, 0);
4043 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4044 /* If this happens, we have to extend this to schedule
4045 optimally. Return 0 for now. */
4048 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4050 if (! recog_memoized (dep_insn))
4052 switch (get_attr_type (dep_insn))
4059 case TYPE_FPSQRTSGL:
4060 case TYPE_FPSQRTDBL:
4061 /* A fpload can't be issued until one cycle before a
4062 preceding arithmetic operation has finished if
4063 the target of the fpload is the destination of the
4064 arithmetic operation.
4066 Exception: For PA7100LC, PA7200 and PA7300, the cost
4067 is 3 cycles, unless they bundle together. We also
4068 pay the penalty if the second insn is a fpload. */
4069 return insn_default_latency (dep_insn) - 1;
4076 else if (attr_type == TYPE_FPALU)
4078 rtx pat = PATTERN (insn);
4079 rtx dep_pat = PATTERN (dep_insn);
4080 if (GET_CODE (pat) == PARALLEL)
4082 /* This happens for the fldXs,mb patterns. */
4083 pat = XVECEXP (pat, 0, 0);
4085 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4086 /* If this happens, we have to extend this to schedule
4087 optimally. Return 0 for now. */
4090 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4092 if (! recog_memoized (dep_insn))
4094 switch (get_attr_type (dep_insn))
4098 case TYPE_FPSQRTSGL:
4099 case TYPE_FPSQRTDBL:
4100 /* An ALU flop can't be issued until two cycles before a
4101 preceding divide or sqrt operation has finished if
4102 the target of the ALU flop is also the target of
4103 the divide or sqrt operation. */
4104 return insn_default_latency (dep_insn) - 2;
4112 /* For other output dependencies, the cost is 0. */
4119 /* Adjust scheduling priorities. We use this to try and keep addil
4120 and the next use of %r1 close together. */
4122 pa_adjust_priority (insn, priority)
4126 rtx set = single_set (insn);
4130 src = SET_SRC (set);
4131 dest = SET_DEST (set);
4132 if (GET_CODE (src) == LO_SUM
4133 && symbolic_operand (XEXP (src, 1), VOIDmode)
4134 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4137 else if (GET_CODE (src) == MEM
4138 && GET_CODE (XEXP (src, 0)) == LO_SUM
4139 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4140 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4143 else if (GET_CODE (dest) == MEM
4144 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4145 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4146 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4152 /* The 700 can only issue a single insn at a time.
4153 The 7XXX processors can issue two insns at a time.
4154 The 8000 can issue 4 insns at a time. */
4160 case PROCESSOR_700: return 1;
4161 case PROCESSOR_7100: return 2;
4162 case PROCESSOR_7100LC: return 2;
4163 case PROCESSOR_7200: return 2;
4164 case PROCESSOR_7300: return 2;
4165 case PROCESSOR_8000: return 4;
4174 /* Return any length adjustment needed by INSN which already has its length
4175 computed as LENGTH. Return zero if no adjustment is necessary.
4177 For the PA: function calls, millicode calls, and backwards short
4178 conditional branches with unfilled delay slots need an adjustment by +1
4179 (to account for the NOP which will be inserted into the instruction stream).
4181 Also compute the length of an inline block move here as it is too
4182 complicated to express as a length attribute in pa.md. */
4184 pa_adjust_insn_length (insn, length)
4188 rtx pat = PATTERN (insn);
4190 /* Call insns which are *not* indirect and have unfilled delay slots. */
4191 if (GET_CODE (insn) == CALL_INSN)
4194 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4195 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4197 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4198 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4204 /* Jumps inside switch tables which have unfilled delay slots
4205 also need adjustment. */
4206 else if (GET_CODE (insn) == JUMP_INSN
4207 && simplejump_p (insn)
4208 && GET_MODE (insn) == SImode)
4210 /* Millicode insn with an unfilled delay slot. */
4211 else if (GET_CODE (insn) == INSN
4212 && GET_CODE (pat) != SEQUENCE
4213 && GET_CODE (pat) != USE
4214 && GET_CODE (pat) != CLOBBER
4215 && get_attr_type (insn) == TYPE_MILLI)
4217 /* Block move pattern. */
4218 else if (GET_CODE (insn) == INSN
4219 && GET_CODE (pat) == PARALLEL
4220 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4221 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4222 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4223 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4224 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4225 return compute_movstrsi_length (insn) - 4;
4226 /* Conditional branch with an unfilled delay slot. */
4227 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4229 /* Adjust a short backwards conditional with an unfilled delay slot. */
4230 if (GET_CODE (pat) == SET
4232 && ! forward_branch_p (insn))
4234 else if (GET_CODE (pat) == PARALLEL
4235 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4238 /* Adjust dbra insn with short backwards conditional branch with
4239 unfilled delay slot -- only for case where counter is in a
4240 general register register. */
4241 else if (GET_CODE (pat) == PARALLEL
4242 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4243 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4244 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4246 && ! forward_branch_p (insn))
4254 /* Print operand X (an rtx) in assembler syntax to file FILE.
4255 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4256 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4259 print_operand (file, x, code)
4267 /* Output a 'nop' if there's nothing for the delay slot. */
4268 if (dbr_sequence_length () == 0)
4269 fputs ("\n\tnop", file);
4272 /* Output an nullification completer if there's nothing for the */
4273 /* delay slot or nullification is requested. */
4274 if (dbr_sequence_length () == 0 ||
4276 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4280 /* Print out the second register name of a register pair.
4281 I.e., R (6) => 7. */
4282 fputs (reg_names[REGNO (x) + 1], file);
4285 /* A register or zero. */
4287 || (x == CONST0_RTX (DFmode))
4288 || (x == CONST0_RTX (SFmode)))
4290 fputs ("%r0", file);
4296 /* A register or zero (floating point). */
4298 || (x == CONST0_RTX (DFmode))
4299 || (x == CONST0_RTX (SFmode)))
4301 fputs ("%fr0", file);
4310 xoperands[0] = XEXP (XEXP (x, 0), 0);
4311 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4312 output_global_address (file, xoperands[1], 0);
4313 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4317 case 'C': /* Plain (C)ondition */
4319 switch (GET_CODE (x))
4322 fputs ("=", file); break;
4324 fputs ("<>", file); break;
4326 fputs (">", file); break;
4328 fputs (">=", file); break;
4330 fputs (">>=", file); break;
4332 fputs (">>", file); break;
4334 fputs ("<", file); break;
4336 fputs ("<=", file); break;
4338 fputs ("<<=", file); break;
4340 fputs ("<<", file); break;
4345 case 'N': /* Condition, (N)egated */
4346 switch (GET_CODE (x))
4349 fputs ("<>", file); break;
4351 fputs ("=", file); break;
4353 fputs ("<=", file); break;
4355 fputs ("<", file); break;
4357 fputs ("<<", file); break;
4359 fputs ("<<=", file); break;
4361 fputs (">=", file); break;
4363 fputs (">", file); break;
4365 fputs (">>", file); break;
4367 fputs (">>=", file); break;
4372 /* For floating point comparisons. Note that the output
4373 predicates are the complement of the desired mode. */
4375 switch (GET_CODE (x))
4378 fputs ("!=", file); break;
4380 fputs ("=", file); break;
4382 fputs ("!>", file); break;
4384 fputs ("!>=", file); break;
4386 fputs ("!<", file); break;
4388 fputs ("!<=", file); break;
4390 fputs ("!<>", file); break;
4392 fputs (">", file); break;
4394 fputs (">=", file); break;
4396 fputs ("<", file); break;
4398 fputs ("<=", file); break;
4400 fputs ("<>", file); break;
4402 fputs ("<=>", file); break;
4404 fputs ("!<=>", file); break;
4409 case 'S': /* Condition, operands are (S)wapped. */
4410 switch (GET_CODE (x))
4413 fputs ("=", file); break;
4415 fputs ("<>", file); break;
4417 fputs ("<", file); break;
4419 fputs ("<=", file); break;
4421 fputs ("<<=", file); break;
4423 fputs ("<<", file); break;
4425 fputs (">", file); break;
4427 fputs (">=", file); break;
4429 fputs (">>=", file); break;
4431 fputs (">>", file); break;
4436 case 'B': /* Condition, (B)oth swapped and negate. */
4437 switch (GET_CODE (x))
4440 fputs ("<>", file); break;
4442 fputs ("=", file); break;
4444 fputs (">=", file); break;
4446 fputs (">", file); break;
4448 fputs (">>", file); break;
4450 fputs (">>=", file); break;
4452 fputs ("<=", file); break;
4454 fputs ("<", file); break;
4456 fputs ("<<", file); break;
4458 fputs ("<<=", file); break;
4464 if (GET_CODE (x) == CONST_INT)
4466 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4471 if (GET_CODE (x) == CONST_INT)
4473 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4478 if (GET_CODE (x) == CONST_INT)
4480 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4485 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4487 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4492 if (GET_CODE (x) == CONST_INT)
4494 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4499 if (GET_CODE (x) == CONST_INT)
4501 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4506 if (GET_CODE (x) == CONST_INT)
4511 switch (GET_CODE (XEXP (x, 0)))
4515 if (ASSEMBLER_DIALECT == 0)
4516 fputs ("s,mb", file);
4518 fputs (",mb", file);
4522 if (ASSEMBLER_DIALECT == 0)
4523 fputs ("s,ma", file);
4525 fputs (",ma", file);
4528 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4529 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4531 if (ASSEMBLER_DIALECT == 0)
4532 fputs ("x,s", file);
4536 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4540 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4546 output_global_address (file, x, 0);
4549 output_global_address (file, x, 1);
4551 case 0: /* Don't do anything special */
4556 compute_zdepwi_operands (INTVAL (x), op);
4557 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4563 compute_zdepdi_operands (INTVAL (x), op);
4564 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4568 /* We can get here from a .vtable_inherit due to our
4569 CONSTANT_ADDRESS_P rejecting perfectly good constant
4575 if (GET_CODE (x) == REG)
4577 fputs (reg_names [REGNO (x)], file);
4578 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4584 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4585 && (REGNO (x) & 1) == 0)
4588 else if (GET_CODE (x) == MEM)
4590 int size = GET_MODE_SIZE (GET_MODE (x));
4591 rtx base = NULL_RTX;
4592 switch (GET_CODE (XEXP (x, 0)))
4596 base = XEXP (XEXP (x, 0), 0);
4597 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4601 base = XEXP (XEXP (x, 0), 0);
4602 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4605 if (GET_CODE (XEXP (x, 0)) == PLUS
4606 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4607 fprintf (file, "%s(%s)",
4608 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4609 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4610 else if (GET_CODE (XEXP (x, 0)) == PLUS
4611 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4612 fprintf (file, "%s(%s)",
4613 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4614 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4616 output_address (XEXP (x, 0));
4621 output_addr_const (file, x);
4624 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4627 output_global_address (file, x, round_constant)
4633 /* Imagine (high (const (plus ...))). */
4634 if (GET_CODE (x) == HIGH)
4637 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4638 assemble_name (file, XSTR (x, 0));
4639 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4641 assemble_name (file, XSTR (x, 0));
4642 fputs ("-$global$", file);
4644 else if (GET_CODE (x) == CONST)
4646 const char *sep = "";
4647 int offset = 0; /* assembler wants -$global$ at end */
4648 rtx base = NULL_RTX;
4650 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4652 base = XEXP (XEXP (x, 0), 0);
4653 output_addr_const (file, base);
4655 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4656 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4659 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4661 base = XEXP (XEXP (x, 0), 1);
4662 output_addr_const (file, base);
4664 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4665 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4668 /* How bogus. The compiler is apparently responsible for
4669 rounding the constant if it uses an LR field selector.
4671 The linker and/or assembler seem a better place since
4672 they have to do this kind of thing already.
4674 If we fail to do this, HP's optimizing linker may eliminate
4675 an addil, but not update the ldw/stw/ldo instruction that
4676 uses the result of the addil. */
4678 offset = ((offset + 0x1000) & ~0x1fff);
4680 if (GET_CODE (XEXP (x, 0)) == PLUS)
4690 else if (GET_CODE (XEXP (x, 0)) == MINUS
4691 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4695 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4696 fputs ("-$global$", file);
4698 fprintf (file, "%s%d", sep, offset);
4701 output_addr_const (file, x);
4705 output_deferred_plabels (file)
4709 /* If we have deferred plabels, then we need to switch into the data
4710 section and align it to a 4 byte boundary before we output the
4711 deferred plabels. */
4712 if (n_deferred_plabels)
4715 ASM_OUTPUT_ALIGN (file, 2);
4718 /* Now output the deferred plabels. */
4719 for (i = 0; i < n_deferred_plabels; i++)
4721 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4722 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4723 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
4727 /* HP's millicode routines mean something special to the assembler.
4728 Keep track of which ones we have used. */
4730 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
4731 static void import_milli PARAMS ((enum millicodes));
4732 static char imported[(int) end1000];
4733 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4734 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4735 #define MILLI_START 10
4739 enum millicodes code;
4741 char str[sizeof (import_string)];
4743 if (!imported[(int) code])
4745 imported[(int) code] = 1;
4746 strcpy (str, import_string);
4747 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4748 output_asm_insn (str, 0);
4752 /* The register constraints have put the operands and return value in
4753 the proper registers. */
4756 output_mul_insn (unsignedp, insn)
4757 int unsignedp ATTRIBUTE_UNUSED;
4760 import_milli (mulI);
4761 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4764 /* Emit the rtl for doing a division by a constant. */
4766 /* Do magic division millicodes exist for this value? */
4767 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4770 /* We'll use an array to keep track of the magic millicodes and
4771 whether or not we've used them already. [n][0] is signed, [n][1] is
4774 static int div_milli[16][2];
4777 div_operand (op, mode)
4779 enum machine_mode mode;
4781 return (mode == SImode
4782 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4783 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4784 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4788 emit_hpdiv_const (operands, unsignedp)
4792 if (GET_CODE (operands[2]) == CONST_INT
4793 && INTVAL (operands[2]) > 0
4794 && INTVAL (operands[2]) < 16
4795 && magic_milli[INTVAL (operands[2])])
4797 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4799 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4802 (PARALLEL, VOIDmode,
4803 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4804 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4806 gen_rtx_REG (SImode, 26),
4808 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4809 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4810 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4811 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4812 gen_rtx_CLOBBER (VOIDmode, ret))));
4813 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4820 output_div_insn (operands, unsignedp, insn)
4827 /* If the divisor is a constant, try to use one of the special
4829 if (GET_CODE (operands[0]) == CONST_INT)
4831 static char buf[100];
4832 divisor = INTVAL (operands[0]);
4833 if (!div_milli[divisor][unsignedp])
4835 div_milli[divisor][unsignedp] = 1;
4837 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4839 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4843 sprintf (buf, "$$divU_");
4844 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4845 return output_millicode_call (insn,
4846 gen_rtx_SYMBOL_REF (SImode, buf));
4850 sprintf (buf, "$$divI_");
4851 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4852 return output_millicode_call (insn,
4853 gen_rtx_SYMBOL_REF (SImode, buf));
4856 /* Divisor isn't a special constant. */
4861 import_milli (divU);
4862 return output_millicode_call (insn,
4863 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4867 import_milli (divI);
4868 return output_millicode_call (insn,
4869 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4874 /* Output a $$rem millicode to do mod. */
4877 output_mod_insn (unsignedp, insn)
4883 import_milli (remU);
4884 return output_millicode_call (insn,
4885 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4889 import_milli (remI);
4890 return output_millicode_call (insn,
4891 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4896 output_arg_descriptor (call_insn)
4899 const char *arg_regs[4];
4900 enum machine_mode arg_mode;
4902 int i, output_flag = 0;
4905 /* We neither need nor want argument location descriptors for the
4906 64bit runtime environment or the ELF32 environment. */
4907 if (TARGET_64BIT || TARGET_ELF32)
4910 for (i = 0; i < 4; i++)
4913 /* Specify explicitly that no argument relocations should take place
4914 if using the portable runtime calling conventions. */
4915 if (TARGET_PORTABLE_RUNTIME)
4917 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4922 if (GET_CODE (call_insn) != CALL_INSN)
4924 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4926 rtx use = XEXP (link, 0);
4928 if (! (GET_CODE (use) == USE
4929 && GET_CODE (XEXP (use, 0)) == REG
4930 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4933 arg_mode = GET_MODE (XEXP (use, 0));
4934 regno = REGNO (XEXP (use, 0));
4935 if (regno >= 23 && regno <= 26)
4937 arg_regs[26 - regno] = "GR";
4938 if (arg_mode == DImode)
4939 arg_regs[25 - regno] = "GR";
4941 else if (regno >= 32 && regno <= 39)
4943 if (arg_mode == SFmode)
4944 arg_regs[(regno - 32) / 2] = "FR";
4947 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4948 arg_regs[(regno - 34) / 2] = "FR";
4949 arg_regs[(regno - 34) / 2 + 1] = "FU";
4951 arg_regs[(regno - 34) / 2] = "FU";
4952 arg_regs[(regno - 34) / 2 + 1] = "FR";
4957 fputs ("\t.CALL ", asm_out_file);
4958 for (i = 0; i < 4; i++)
4963 fputc (',', asm_out_file);
4964 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4967 fputc ('\n', asm_out_file);
4970 /* Return the class of any secondary reload register that is needed to
4971 move IN into a register in class CLASS using mode MODE.
4973 Profiling has showed this routine and its descendants account for
4974 a significant amount of compile time (~7%). So it has been
4975 optimized to reduce redundant computations and eliminate useless
4978 It might be worthwhile to try and make this a leaf function too. */
4981 secondary_reload_class (class, mode, in)
4982 enum reg_class class;
4983 enum machine_mode mode;
4986 int regno, is_symbolic;
4988 /* Trying to load a constant into a FP register during PIC code
4989 generation will require %r1 as a scratch register. */
4991 && GET_MODE_CLASS (mode) == MODE_INT
4992 && FP_REG_CLASS_P (class)
4993 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4996 /* Profiling showed the PA port spends about 1.3% of its compilation
4997 time in true_regnum from calls inside secondary_reload_class. */
4999 if (GET_CODE (in) == REG)
5002 if (regno >= FIRST_PSEUDO_REGISTER)
5003 regno = true_regnum (in);
5005 else if (GET_CODE (in) == SUBREG)
5006 regno = true_regnum (in);
5010 /* If we have something like (mem (mem (...)), we can safely assume the
5011 inner MEM will end up in a general register after reloading, so there's
5012 no need for a secondary reload. */
5013 if (GET_CODE (in) == MEM
5014 && GET_CODE (XEXP (in, 0)) == MEM)
5017 /* Handle out of range displacement for integer mode loads/stores of
5019 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5020 && GET_MODE_CLASS (mode) == MODE_INT
5021 && FP_REG_CLASS_P (class))
5022 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5023 return GENERAL_REGS;
5025 /* A SAR<->FP register copy requires a secondary register (GPR) as
5026 well as secondary memory. */
5027 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5028 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5029 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5030 return GENERAL_REGS;
5032 if (GET_CODE (in) == HIGH)
5035 /* Profiling has showed GCC spends about 2.6% of its compilation
5036 time in symbolic_operand from calls inside secondary_reload_class.
5038 We use an inline copy and only compute its return value once to avoid
5040 switch (GET_CODE (in))
5050 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5051 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5052 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5062 && read_only_operand (in, VOIDmode))
5065 if (class != R1_REGS && is_symbolic)
5072 function_arg_padding (mode, type)
5073 enum machine_mode mode;
5078 if (mode == BLKmode)
5080 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
5081 size = int_size_in_bytes (type) * BITS_PER_UNIT;
5083 return upward; /* Don't know if this is right, but */
5084 /* same as old definition. */
5087 size = GET_MODE_BITSIZE (mode);
5088 if (size < PARM_BOUNDARY)
5090 else if (size % PARM_BOUNDARY)
5097 /* Do what is necessary for `va_start'. We look at the current function
5098 to determine if stdargs or varargs is used and fill in an initial
5099 va_list. A pointer to this constructor is returned. */
5102 hppa_builtin_saveregs ()
5105 tree fntype = TREE_TYPE (current_function_decl);
5106 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5107 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5108 != void_type_node)))
5109 ? UNITS_PER_WORD : 0);
5112 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5114 offset = current_function_arg_offset_rtx;
5120 /* Adjust for varargs/stdarg differences. */
5122 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5124 offset = current_function_arg_offset_rtx;
5126 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5127 from the incoming arg pointer and growing to larger addresses. */
5128 for (i = 26, off = -64; i >= 19; i--, off += 8)
5129 emit_move_insn (gen_rtx_MEM (word_mode,
5130 plus_constant (arg_pointer_rtx, off)),
5131 gen_rtx_REG (word_mode, i));
5133 /* The incoming args pointer points just beyond the flushback area;
5134 normally this is not a serious concern. However, when we are doing
5135 varargs/stdargs we want to make the arg pointer point to the start
5136 of the incoming argument area. */
5137 emit_move_insn (virtual_incoming_args_rtx,
5138 plus_constant (arg_pointer_rtx, -64));
5140 /* Now return a pointer to the first anonymous argument. */
5141 return copy_to_reg (expand_binop (Pmode, add_optab,
5142 virtual_incoming_args_rtx,
5143 offset, 0, 0, OPTAB_LIB_WIDEN));
5146 /* Store general registers on the stack. */
5147 dest = gen_rtx_MEM (BLKmode,
5148 plus_constant (current_function_internal_arg_pointer,
5150 set_mem_alias_set (dest, get_varargs_alias_set ());
5151 set_mem_align (dest, BITS_PER_WORD);
5152 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
5154 /* move_block_from_reg will emit code to store the argument registers
5155 individually as scalar stores.
5157 However, other insns may later load from the same addresses for
5158 a structure load (passing a struct to a varargs routine).
5160 The alias code assumes that such aliasing can never happen, so we
5161 have to keep memory referencing insns from moving up beyond the
5162 last argument register store. So we emit a blockage insn here. */
5163 emit_insn (gen_blockage ());
5165 return copy_to_reg (expand_binop (Pmode, add_optab,
5166 current_function_internal_arg_pointer,
5167 offset, 0, 0, OPTAB_LIB_WIDEN));
5171 hppa_va_start (stdarg_p, valist, nextarg)
5172 int stdarg_p ATTRIBUTE_UNUSED;
5176 nextarg = expand_builtin_saveregs ();
5177 std_expand_builtin_va_start (1, valist, nextarg);
5181 hppa_va_arg (valist, type)
5184 HOST_WIDE_INT align, size, ofs;
5189 /* Every argument in PA64 is passed by value (including large structs).
5190 Arguments with size greater than 8 must be aligned 0 MOD 16. */
5192 size = int_size_in_bytes (type);
5193 if (size > UNITS_PER_WORD)
5195 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5196 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5197 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5198 build_int_2 (-2 * UNITS_PER_WORD, -1));
5199 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5200 TREE_SIDE_EFFECTS (t) = 1;
5201 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5203 return std_expand_builtin_va_arg (valist, type);
5206 /* Compute the rounded size of the type. */
5207 align = PARM_BOUNDARY / BITS_PER_UNIT;
5208 size = int_size_in_bytes (type);
5210 ptr = build_pointer_type (type);
5212 /* "Large" types are passed by reference. */
5215 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5216 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5217 TREE_SIDE_EFFECTS (t) = 1;
5219 pptr = build_pointer_type (ptr);
5220 t = build1 (NOP_EXPR, pptr, t);
5221 TREE_SIDE_EFFECTS (t) = 1;
5223 t = build1 (INDIRECT_REF, ptr, t);
5224 TREE_SIDE_EFFECTS (t) = 1;
5228 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5229 build_int_2 (-size, -1));
5231 /* Copied from va-pa.h, but we probably don't need to align
5232 to word size, since we generate and preserve that invariant. */
5233 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5234 build_int_2 ((size > 4 ? -8 : -4), -1));
5236 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5237 TREE_SIDE_EFFECTS (t) = 1;
5239 ofs = (8 - size) % 4;
5242 t = build (PLUS_EXPR, TREE_TYPE (valist), t, build_int_2 (ofs, 0));
5243 TREE_SIDE_EFFECTS (t) = 1;
5246 t = build1 (NOP_EXPR, ptr, t);
5247 TREE_SIDE_EFFECTS (t) = 1;
5251 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
5256 /* This routine handles all the normal conditional branch sequences we
5257 might need to generate. It handles compare immediate vs compare
5258 register, nullification of delay slots, varying length branches,
5259 negated branches, and all combinations of the above. It returns the
5260 output appropriate to emit the branch corresponding to all given
5264 output_cbranch (operands, nullify, length, negated, insn)
5266 int nullify, length, negated;
5269 static char buf[100];
5272 /* A conditional branch to the following instruction (eg the delay slot) is
5273 asking for a disaster. This can happen when not optimizing.
5275 In such cases it is safe to emit nothing. */
5277 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5280 /* If this is a long branch with its delay slot unfilled, set `nullify'
5281 as it can nullify the delay slot and save a nop. */
5282 if (length == 8 && dbr_sequence_length () == 0)
5285 /* If this is a short forward conditional branch which did not get
5286 its delay slot filled, the delay slot can still be nullified. */
5287 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5288 nullify = forward_branch_p (insn);
5290 /* A forward branch over a single nullified insn can be done with a
5291 comclr instruction. This avoids a single cycle penalty due to
5292 mis-predicted branch if we fall through (branch not taken). */
5294 && next_real_insn (insn) != 0
5295 && get_attr_length (next_real_insn (insn)) == 4
5296 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5302 /* All short conditional branches except backwards with an unfilled
5306 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5308 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5309 if (GET_MODE (operands[1]) == DImode)
5312 strcat (buf, "%B3");
5314 strcat (buf, "%S3");
5316 strcat (buf, " %2,%r1,%%r0");
5318 strcat (buf, ",n %2,%r1,%0");
5320 strcat (buf, " %2,%r1,%0");
5323 /* All long conditionals. Note an short backward branch with an
5324 unfilled delay slot is treated just like a long backward branch
5325 with an unfilled delay slot. */
5327 /* Handle weird backwards branch with a filled delay slot
5328 with is nullified. */
5329 if (dbr_sequence_length () != 0
5330 && ! forward_branch_p (insn)
5333 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5334 if (GET_MODE (operands[1]) == DImode)
5337 strcat (buf, "%S3");
5339 strcat (buf, "%B3");
5340 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5342 /* Handle short backwards branch with an unfilled delay slot.
5343 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5344 taken and untaken branches. */
5345 else if (dbr_sequence_length () == 0
5346 && ! forward_branch_p (insn)
5347 && INSN_ADDRESSES_SET_P ()
5348 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5349 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5351 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5352 if (GET_MODE (operands[1]) == DImode)
5355 strcat (buf, "%B3 %2,%r1,%0%#");
5357 strcat (buf, "%S3 %2,%r1,%0%#");
5361 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5362 if (GET_MODE (operands[1]) == DImode)
5365 strcat (buf, "%S3");
5367 strcat (buf, "%B3");
5369 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5371 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5376 /* Very long branch. Right now we only handle these when not
5377 optimizing. See "jump" pattern in pa.md for details. */
5381 /* Create a reversed conditional branch which branches around
5382 the following insns. */
5384 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5386 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5387 if (GET_MODE (operands[1]) == DImode)
5391 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5394 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5396 output_asm_insn (buf, operands);
5398 /* Output an insn to save %r1. */
5399 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5401 /* Now output a very long branch to the original target. */
5402 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5404 /* Now restore the value of %r1 in the delay slot. We're not
5405 optimizing so we know nothing else can be in the delay slot. */
5406 return "ldw -16(%%r30),%%r1";
5409 /* Very long branch when generating PIC code. Right now we only
5410 handle these when not optimizing. See "jump" pattern in pa.md
5415 /* Create a reversed conditional branch which branches around
5416 the following insns. */
5418 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5420 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5421 if (GET_MODE (operands[1]) == DImode)
5424 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5426 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5428 output_asm_insn (buf, operands);
5430 /* Output an insn to save %r1. */
5431 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5433 /* Now output a very long PIC branch to the original target. */
5437 xoperands[0] = operands[0];
5438 xoperands[1] = operands[1];
5439 xoperands[2] = operands[2];
5440 xoperands[3] = operands[3];
5441 if (TARGET_SOM || ! TARGET_GAS)
5442 xoperands[4] = gen_label_rtx ();
5444 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5445 if (TARGET_SOM || ! TARGET_GAS)
5447 output_asm_insn ("addil L'%l0-%l4,%%r1", xoperands);
5448 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5449 CODE_LABEL_NUMBER (xoperands[4]));
5450 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1", xoperands);
5454 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
5455 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1",
5458 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5461 /* Now restore the value of %r1 in the delay slot. We're not
5462 optimizing so we know nothing else can be in the delay slot. */
5463 return "ldw -16(%%r30),%%r1";
5471 /* This routine handles all the branch-on-bit conditional branch sequences we
5472 might need to generate. It handles nullification of delay slots,
5473 varying length branches, negated branches and all combinations of the
5474 above. it returns the appropriate output template to emit the branch. */
5477 output_bb (operands, nullify, length, negated, insn, which)
5478 rtx *operands ATTRIBUTE_UNUSED;
5479 int nullify, length, negated;
5483 static char buf[100];
5486 /* A conditional branch to the following instruction (eg the delay slot) is
5487 asking for a disaster. I do not think this can happen as this pattern
5488 is only used when optimizing; jump optimization should eliminate the
5489 jump. But be prepared just in case. */
5491 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5494 /* If this is a long branch with its delay slot unfilled, set `nullify'
5495 as it can nullify the delay slot and save a nop. */
5496 if (length == 8 && dbr_sequence_length () == 0)
5499 /* If this is a short forward conditional branch which did not get
5500 its delay slot filled, the delay slot can still be nullified. */
5501 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5502 nullify = forward_branch_p (insn);
5504 /* A forward branch over a single nullified insn can be done with a
5505 extrs instruction. This avoids a single cycle penalty due to
5506 mis-predicted branch if we fall through (branch not taken). */
5509 && next_real_insn (insn) != 0
5510 && get_attr_length (next_real_insn (insn)) == 4
5511 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5518 /* All short conditional branches except backwards with an unfilled
5522 strcpy (buf, "{extrs,|extrw,s,}");
5524 strcpy (buf, "bb,");
5525 if (useskip && GET_MODE (operands[0]) == DImode)
5526 strcpy (buf, "extrd,s,*");
5527 else if (GET_MODE (operands[0]) == DImode)
5528 strcpy (buf, "bb,*");
5529 if ((which == 0 && negated)
5530 || (which == 1 && ! negated))
5535 strcat (buf, " %0,%1,1,%%r0");
5536 else if (nullify && negated)
5537 strcat (buf, ",n %0,%1,%3");
5538 else if (nullify && ! negated)
5539 strcat (buf, ",n %0,%1,%2");
5540 else if (! nullify && negated)
5541 strcat (buf, "%0,%1,%3");
5542 else if (! nullify && ! negated)
5543 strcat (buf, " %0,%1,%2");
5546 /* All long conditionals. Note an short backward branch with an
5547 unfilled delay slot is treated just like a long backward branch
5548 with an unfilled delay slot. */
5550 /* Handle weird backwards branch with a filled delay slot
5551 with is nullified. */
5552 if (dbr_sequence_length () != 0
5553 && ! forward_branch_p (insn)
5556 strcpy (buf, "bb,");
5557 if (GET_MODE (operands[0]) == DImode)
5559 if ((which == 0 && negated)
5560 || (which == 1 && ! negated))
5565 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5567 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5569 /* Handle short backwards branch with an unfilled delay slot.
5570 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5571 taken and untaken branches. */
5572 else if (dbr_sequence_length () == 0
5573 && ! forward_branch_p (insn)
5574 && INSN_ADDRESSES_SET_P ()
5575 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5576 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5578 strcpy (buf, "bb,");
5579 if (GET_MODE (operands[0]) == DImode)
5581 if ((which == 0 && negated)
5582 || (which == 1 && ! negated))
5587 strcat (buf, " %0,%1,%3%#");
5589 strcat (buf, " %0,%1,%2%#");
5593 strcpy (buf, "{extrs,|extrw,s,}");
5594 if (GET_MODE (operands[0]) == DImode)
5595 strcpy (buf, "extrd,s,*");
5596 if ((which == 0 && negated)
5597 || (which == 1 && ! negated))
5601 if (nullify && negated)
5602 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5603 else if (nullify && ! negated)
5604 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5606 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5608 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5618 /* This routine handles all the branch-on-variable-bit conditional branch
5619 sequences we might need to generate. It handles nullification of delay
5620 slots, varying length branches, negated branches and all combinations
5621 of the above. it returns the appropriate output template to emit the
5625 output_bvb (operands, nullify, length, negated, insn, which)
5626 rtx *operands ATTRIBUTE_UNUSED;
5627 int nullify, length, negated;
5631 static char buf[100];
5634 /* A conditional branch to the following instruction (eg the delay slot) is
5635 asking for a disaster. I do not think this can happen as this pattern
5636 is only used when optimizing; jump optimization should eliminate the
5637 jump. But be prepared just in case. */
5639 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5642 /* If this is a long branch with its delay slot unfilled, set `nullify'
5643 as it can nullify the delay slot and save a nop. */
5644 if (length == 8 && dbr_sequence_length () == 0)
5647 /* If this is a short forward conditional branch which did not get
5648 its delay slot filled, the delay slot can still be nullified. */
5649 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5650 nullify = forward_branch_p (insn);
5652 /* A forward branch over a single nullified insn can be done with a
5653 extrs instruction. This avoids a single cycle penalty due to
5654 mis-predicted branch if we fall through (branch not taken). */
5657 && next_real_insn (insn) != 0
5658 && get_attr_length (next_real_insn (insn)) == 4
5659 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5666 /* All short conditional branches except backwards with an unfilled
5670 strcpy (buf, "{vextrs,|extrw,s,}");
5672 strcpy (buf, "{bvb,|bb,}");
5673 if (useskip && GET_MODE (operands[0]) == DImode)
5674 strcpy (buf, "extrd,s,*}");
5675 else if (GET_MODE (operands[0]) == DImode)
5676 strcpy (buf, "bb,*");
5677 if ((which == 0 && negated)
5678 || (which == 1 && ! negated))
5683 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5684 else if (nullify && negated)
5685 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5686 else if (nullify && ! negated)
5687 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5688 else if (! nullify && negated)
5689 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5690 else if (! nullify && ! negated)
5691 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5694 /* All long conditionals. Note an short backward branch with an
5695 unfilled delay slot is treated just like a long backward branch
5696 with an unfilled delay slot. */
5698 /* Handle weird backwards branch with a filled delay slot
5699 with is nullified. */
5700 if (dbr_sequence_length () != 0
5701 && ! forward_branch_p (insn)
5704 strcpy (buf, "{bvb,|bb,}");
5705 if (GET_MODE (operands[0]) == DImode)
5707 if ((which == 0 && negated)
5708 || (which == 1 && ! negated))
5713 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5715 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5717 /* Handle short backwards branch with an unfilled delay slot.
5718 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5719 taken and untaken branches. */
5720 else if (dbr_sequence_length () == 0
5721 && ! forward_branch_p (insn)
5722 && INSN_ADDRESSES_SET_P ()
5723 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5724 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5726 strcpy (buf, "{bvb,|bb,}");
5727 if (GET_MODE (operands[0]) == DImode)
5729 if ((which == 0 && negated)
5730 || (which == 1 && ! negated))
5735 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5737 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5741 strcpy (buf, "{vextrs,|extrw,s,}");
5742 if (GET_MODE (operands[0]) == DImode)
5743 strcpy (buf, "extrd,s,*");
5744 if ((which == 0 && negated)
5745 || (which == 1 && ! negated))
5749 if (nullify && negated)
5750 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5751 else if (nullify && ! negated)
5752 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5754 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5756 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5766 /* Return the output template for emitting a dbra type insn.
5768 Note it may perform some output operations on its own before
5769 returning the final output string. */
5771 output_dbra (operands, insn, which_alternative)
5774 int which_alternative;
5777 /* A conditional branch to the following instruction (eg the delay slot) is
5778 asking for a disaster. Be prepared! */
5780 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5782 if (which_alternative == 0)
5783 return "ldo %1(%0),%0";
5784 else if (which_alternative == 1)
5786 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5787 output_asm_insn ("ldw -16(%%r30),%4", operands);
5788 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5789 return "{fldws|fldw} -16(%%r30),%0";
5793 output_asm_insn ("ldw %0,%4", operands);
5794 return "ldo %1(%4),%4\n\tstw %4,%0";
5798 if (which_alternative == 0)
5800 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5801 int length = get_attr_length (insn);
5803 /* If this is a long branch with its delay slot unfilled, set `nullify'
5804 as it can nullify the delay slot and save a nop. */
5805 if (length == 8 && dbr_sequence_length () == 0)
5808 /* If this is a short forward conditional branch which did not get
5809 its delay slot filled, the delay slot can still be nullified. */
5810 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5811 nullify = forward_branch_p (insn);
5813 /* Handle short versions first. */
5814 if (length == 4 && nullify)
5815 return "addib,%C2,n %1,%0,%3";
5816 else if (length == 4 && ! nullify)
5817 return "addib,%C2 %1,%0,%3";
5818 else if (length == 8)
5820 /* Handle weird backwards branch with a fulled delay slot
5821 which is nullified. */
5822 if (dbr_sequence_length () != 0
5823 && ! forward_branch_p (insn)
5825 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5826 /* Handle short backwards branch with an unfilled delay slot.
5827 Using a addb;nop rather than addi;bl saves 1 cycle for both
5828 taken and untaken branches. */
5829 else if (dbr_sequence_length () == 0
5830 && ! forward_branch_p (insn)
5831 && INSN_ADDRESSES_SET_P ()
5832 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5833 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5834 return "addib,%C2 %1,%0,%3%#";
5836 /* Handle normal cases. */
5838 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5840 return "addi,%N2 %1,%0,%0\n\tb %3";
5845 /* Deal with gross reload from FP register case. */
5846 else if (which_alternative == 1)
5848 /* Move loop counter from FP register to MEM then into a GR,
5849 increment the GR, store the GR into MEM, and finally reload
5850 the FP register from MEM from within the branch's delay slot. */
5851 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5853 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5854 if (get_attr_length (insn) == 24)
5855 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5857 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5859 /* Deal with gross reload from memory case. */
5862 /* Reload loop counter from memory, the store back to memory
5863 happens in the branch's delay slot. */
5864 output_asm_insn ("ldw %0,%4", operands);
5865 if (get_attr_length (insn) == 12)
5866 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5868 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5872 /* Return the output template for emitting a dbra type insn.
5874 Note it may perform some output operations on its own before
5875 returning the final output string. */
5877 output_movb (operands, insn, which_alternative, reverse_comparison)
5880 int which_alternative;
5881 int reverse_comparison;
5884 /* A conditional branch to the following instruction (eg the delay slot) is
5885 asking for a disaster. Be prepared! */
5887 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5889 if (which_alternative == 0)
5890 return "copy %1,%0";
5891 else if (which_alternative == 1)
5893 output_asm_insn ("stw %1,-16(%%r30)", operands);
5894 return "{fldws|fldw} -16(%%r30),%0";
5896 else if (which_alternative == 2)
5902 /* Support the second variant. */
5903 if (reverse_comparison)
5904 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5906 if (which_alternative == 0)
5908 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5909 int length = get_attr_length (insn);
5911 /* If this is a long branch with its delay slot unfilled, set `nullify'
5912 as it can nullify the delay slot and save a nop. */
5913 if (length == 8 && dbr_sequence_length () == 0)
5916 /* If this is a short forward conditional branch which did not get
5917 its delay slot filled, the delay slot can still be nullified. */
5918 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5919 nullify = forward_branch_p (insn);
5921 /* Handle short versions first. */
5922 if (length == 4 && nullify)
5923 return "movb,%C2,n %1,%0,%3";
5924 else if (length == 4 && ! nullify)
5925 return "movb,%C2 %1,%0,%3";
5926 else if (length == 8)
5928 /* Handle weird backwards branch with a filled delay slot
5929 which is nullified. */
5930 if (dbr_sequence_length () != 0
5931 && ! forward_branch_p (insn)
5933 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5935 /* Handle short backwards branch with an unfilled delay slot.
5936 Using a movb;nop rather than or;bl saves 1 cycle for both
5937 taken and untaken branches. */
5938 else if (dbr_sequence_length () == 0
5939 && ! forward_branch_p (insn)
5940 && INSN_ADDRESSES_SET_P ()
5941 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5942 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5943 return "movb,%C2 %1,%0,%3%#";
5944 /* Handle normal cases. */
5946 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5948 return "or,%N2 %1,%%r0,%0\n\tb %3";
5953 /* Deal with gross reload from FP register case. */
5954 else if (which_alternative == 1)
5956 /* Move loop counter from FP register to MEM then into a GR,
5957 increment the GR, store the GR into MEM, and finally reload
5958 the FP register from MEM from within the branch's delay slot. */
5959 output_asm_insn ("stw %1,-16(%%r30)", operands);
5960 if (get_attr_length (insn) == 12)
5961 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
5963 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5965 /* Deal with gross reload from memory case. */
5966 else if (which_alternative == 2)
5968 /* Reload loop counter from memory, the store back to memory
5969 happens in the branch's delay slot. */
5970 if (get_attr_length (insn) == 8)
5971 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
5973 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5975 /* Handle SAR as a destination. */
5978 if (get_attr_length (insn) == 8)
5979 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
5981 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5986 /* INSN is a millicode call. It may have an unconditional jump in its delay
5989 CALL_DEST is the routine we are calling. */
5992 output_millicode_call (insn, call_dest)
5996 int attr_length = get_attr_length (insn);
5997 int seq_length = dbr_sequence_length ();
6002 xoperands[3] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6004 /* Handle common case -- empty delay slot or no jump in the delay slot,
6005 and we're sure that the branch will reach the beginning of the $CODE$
6006 subspace. The within reach form of the $$sh_func_adrs call has
6007 a length of 28 and attribute type of multi. This length is the
6008 same as the maximum length of an out of reach PIC call to $$div. */
6009 if ((seq_length == 0
6010 && (attr_length == 8
6011 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6013 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6014 && attr_length == 4))
6016 xoperands[0] = call_dest;
6017 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
6021 /* This call may not reach the beginning of the $CODE$ subspace. */
6022 if (attr_length > 8)
6024 int delay_insn_deleted = 0;
6026 /* We need to emit an inline long-call branch. */
6028 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6030 /* A non-jump insn in the delay slot. By definition we can
6031 emit this insn before the call. */
6032 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6034 /* Now delete the delay insn. */
6035 PUT_CODE (NEXT_INSN (insn), NOTE);
6036 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6037 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6038 delay_insn_deleted = 1;
6041 /* PIC long millicode call sequence. */
6044 xoperands[0] = call_dest;
6045 if (TARGET_SOM || ! TARGET_GAS)
6046 xoperands[1] = gen_label_rtx ();
6048 /* Get our address + 8 into %r1. */
6049 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6051 if (TARGET_SOM || ! TARGET_GAS)
6053 /* Add %r1 to the offset of our target from the next insn. */
6054 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
6055 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6056 CODE_LABEL_NUMBER (xoperands[1]));
6057 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
6061 output_asm_insn ("addil L%%%0-$PIC_pcrel$0+4,%%r1", xoperands);
6062 output_asm_insn ("ldo R%%%0-$PIC_pcrel$0+8(%%r1),%%r1",
6066 /* Get the return address into %r31. */
6067 output_asm_insn ("blr 0,%3", xoperands);
6069 /* Branch to our target which is in %r1. */
6070 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
6072 /* Empty delay slot. Note this insn gets fetched twice and
6073 executed once. To be safe we use a nop. */
6074 output_asm_insn ("nop", xoperands);
6076 /* Pure portable runtime doesn't allow be/ble; we also don't have
6077 PIC support in the assembler/linker, so this sequence is needed. */
6078 else if (TARGET_PORTABLE_RUNTIME)
6080 xoperands[0] = call_dest;
6081 /* Get the address of our target into %r29. */
6082 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
6083 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
6085 /* Get our return address into %r31. */
6086 output_asm_insn ("blr %%r0,%3", xoperands);
6088 /* Jump to our target address in %r29. */
6089 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
6091 /* Empty delay slot. Note this insn gets fetched twice and
6092 executed once. To be safe we use a nop. */
6093 output_asm_insn ("nop", xoperands);
6095 /* If we're allowed to use be/ble instructions, then this is the
6096 best sequence to use for a long millicode call. */
6099 xoperands[0] = call_dest;
6100 output_asm_insn ("ldil L%%%0,%3", xoperands);
6101 output_asm_insn ("{ble|be,l} R%%%0(%%sr4,%3)", xoperands);
6102 output_asm_insn ("nop", xoperands);
6105 /* If we had a jump in the call's delay slot, output it now. */
6106 if (seq_length != 0 && !delay_insn_deleted)
6108 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6109 output_asm_insn ("b,n %0", xoperands);
6111 /* Now delete the delay insn. */
6112 PUT_CODE (NEXT_INSN (insn), NOTE);
6113 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6114 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6119 /* This call has an unconditional jump in its delay slot and the
6120 call is known to reach its target or the beginning of the current
6123 /* Use the containing sequence insn's address. */
6124 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6126 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6127 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6129 /* If the branch was too far away, emit a normal call followed
6130 by a nop, followed by the unconditional branch.
6132 If the branch is close, then adjust %r2 from within the
6133 call's delay slot. */
6135 xoperands[0] = call_dest;
6136 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6137 if (! VAL_14_BITS_P (distance))
6138 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
6141 xoperands[2] = gen_label_rtx ();
6142 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
6144 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6145 CODE_LABEL_NUMBER (xoperands[2]));
6148 /* Delete the jump. */
6149 PUT_CODE (NEXT_INSN (insn), NOTE);
6150 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6151 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6155 extern struct obstack permanent_obstack;
6157 /* INSN is either a function call. It may have an unconditional jump
6160 CALL_DEST is the routine we are calling. */
6163 output_call (insn, call_dest, sibcall)
6168 int attr_length = get_attr_length (insn);
6169 int seq_length = dbr_sequence_length ();
6174 /* Handle common case -- empty delay slot or no jump in the delay slot,
6175 and we're sure that the branch will reach the beginning of the $CODE$
6177 if ((seq_length == 0 && attr_length == 12)
6179 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6180 && attr_length == 8))
6182 xoperands[0] = call_dest;
6183 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
6184 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
6188 /* This call may not reach the beginning of the $CODE$ subspace. */
6189 if (attr_length > 12)
6191 int delay_insn_deleted = 0;
6195 /* We need to emit an inline long-call branch. Furthermore,
6196 because we're changing a named function call into an indirect
6197 function call well after the parameters have been set up, we
6198 need to make sure any FP args appear in both the integer
6199 and FP registers. Also, we need move any delay slot insn
6200 out of the delay slot. And finally, we can't rely on the linker
6201 being able to fix the call to $$dyncall! -- Yuk!. */
6203 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6205 /* A non-jump insn in the delay slot. By definition we can
6206 emit this insn before the call (and in fact before argument
6208 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6210 /* Now delete the delay insn. */
6211 PUT_CODE (NEXT_INSN (insn), NOTE);
6212 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6213 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6214 delay_insn_deleted = 1;
6217 /* Now copy any FP arguments into integer registers. */
6218 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6220 int arg_mode, regno;
6221 rtx use = XEXP (link, 0);
6222 if (! (GET_CODE (use) == USE
6223 && GET_CODE (XEXP (use, 0)) == REG
6224 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6227 arg_mode = GET_MODE (XEXP (use, 0));
6228 regno = REGNO (XEXP (use, 0));
6229 /* Is it a floating point register? */
6230 if (regno >= 32 && regno <= 39)
6232 /* Copy from the FP register into an integer register
6234 if (arg_mode == SFmode)
6236 xoperands[0] = XEXP (use, 0);
6237 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6238 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
6240 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6244 xoperands[0] = XEXP (use, 0);
6245 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6246 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
6248 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6249 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6254 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
6255 we don't have any direct calls in that case. */
6258 const char *name = XSTR (call_dest, 0);
6260 /* See if we have already put this function on the list
6261 of deferred plabels. This list is generally small,
6262 so a liner search is not too ugly. If it proves too
6263 slow replace it with something faster. */
6264 for (i = 0; i < n_deferred_plabels; i++)
6265 if (strcmp (name, deferred_plabels[i].name) == 0)
6268 /* If the deferred plabel list is empty, or this entry was
6269 not found on the list, create a new entry on the list. */
6270 if (deferred_plabels == NULL || i == n_deferred_plabels)
6272 const char *real_name;
6274 if (deferred_plabels == 0)
6275 deferred_plabels = (struct deferred_plabel *)
6276 xmalloc (1 * sizeof (struct deferred_plabel));
6278 deferred_plabels = (struct deferred_plabel *)
6279 xrealloc (deferred_plabels,
6280 ((n_deferred_plabels + 1)
6281 * sizeof (struct deferred_plabel)));
6283 i = n_deferred_plabels++;
6284 deferred_plabels[i].internal_label = gen_label_rtx ();
6285 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
6287 strcpy (deferred_plabels[i].name, name);
6289 /* Gross. We have just implicitly taken the address of this
6290 function, mark it as such. */
6291 real_name = (*targetm.strip_name_encoding) (name);
6292 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
6295 /* We have to load the address of the function using a procedure
6296 label (plabel). Inline plabels can lose for PIC and other
6297 cases, so avoid them by creating a 32bit plabel in the data
6301 xoperands[0] = deferred_plabels[i].internal_label;
6302 if (TARGET_SOM || ! TARGET_GAS)
6303 xoperands[1] = gen_label_rtx ();
6305 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
6306 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
6307 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
6309 /* Get our address + 8 into %r1. */
6310 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6312 if (TARGET_SOM || ! TARGET_GAS)
6314 /* Add %r1 to the offset of dyncall from the next insn. */
6315 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
6316 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6317 CODE_LABEL_NUMBER (xoperands[1]));
6318 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
6322 output_asm_insn ("addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1",
6324 output_asm_insn ("ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
6328 /* Get the return address into %r31. */
6329 output_asm_insn ("blr %%r0,%%r31", xoperands);
6331 /* Branch to our target which is in %r1. */
6332 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6336 /* This call never returns, so we do not need to fix the
6338 output_asm_insn ("nop", xoperands);
6342 /* Copy the return address into %r2 also. */
6343 output_asm_insn ("copy %%r31,%%r2", xoperands);
6348 xoperands[0] = deferred_plabels[i].internal_label;
6350 /* Get the address of our target into %r22. */
6351 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
6352 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
6354 /* Get the high part of the address of $dyncall into %r2, then
6355 add in the low part in the branch instruction. */
6356 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
6357 output_asm_insn ("{ble|be,l} R%%$$dyncall(%%sr4,%%r2)",
6362 /* This call never returns, so we do not need to fix the
6364 output_asm_insn ("nop", xoperands);
6368 /* Copy the return address into %r2 also. */
6369 output_asm_insn ("copy %%r31,%%r2", xoperands);
6374 /* If we had a jump in the call's delay slot, output it now. */
6375 if (seq_length != 0 && !delay_insn_deleted)
6377 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6378 output_asm_insn ("b,n %0", xoperands);
6380 /* Now delete the delay insn. */
6381 PUT_CODE (NEXT_INSN (insn), NOTE);
6382 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6383 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6388 /* This call has an unconditional jump in its delay slot and the
6389 call is known to reach its target or the beginning of the current
6392 /* Use the containing sequence insn's address. */
6393 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6395 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6396 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6398 /* If the branch is too far away, emit a normal call followed
6399 by a nop, followed by the unconditional branch. If the branch
6400 is close, then adjust %r2 in the call's delay slot. */
6402 xoperands[0] = call_dest;
6403 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6404 if (! VAL_14_BITS_P (distance))
6405 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
6408 xoperands[3] = gen_label_rtx ();
6409 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6411 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6412 CODE_LABEL_NUMBER (xoperands[3]));
6415 /* Delete the jump. */
6416 PUT_CODE (NEXT_INSN (insn), NOTE);
6417 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6418 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6422 /* In HPUX 8.0's shared library scheme, special relocations are needed
6423 for function labels if they might be passed to a function
6424 in a shared library (because shared libraries don't live in code
6425 space), and special magic is needed to construct their address. */
6428 hppa_encode_label (sym)
6431 const char *str = XSTR (sym, 0);
6432 int len = strlen (str) + 1;
6435 p = newstr = alloca (len + 1);
6444 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6448 pa_encode_section_info (decl, first)
6452 if (first && TEXT_SPACE_P (decl))
6455 if (TREE_CODE (decl) == FUNCTION_DECL
6456 || TREE_CODE (decl) == VAR_DECL)
6457 rtl = DECL_RTL (decl);
6459 rtl = TREE_CST_RTL (decl);
6460 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
6461 if (TREE_CODE (decl) == FUNCTION_DECL)
6462 hppa_encode_label (XEXP (DECL_RTL (decl), 0));
6466 /* This is sort of inverse to pa_encode_section_info. */
6469 pa_strip_name_encoding (str)
6472 return str + (*str == '*' || *str == '@');
6476 function_label_operand (op, mode)
6478 enum machine_mode mode ATTRIBUTE_UNUSED;
6480 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6483 /* Returns 1 if OP is a function label involved in a simple addition
6484 with a constant. Used to keep certain patterns from matching
6485 during instruction combination. */
6487 is_function_label_plus_const (op)
6490 /* Strip off any CONST. */
6491 if (GET_CODE (op) == CONST)
6494 return (GET_CODE (op) == PLUS
6495 && function_label_operand (XEXP (op, 0), Pmode)
6496 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6499 /* Output assembly code for a thunk to FUNCTION. */
6502 pa_asm_output_mi_thunk (file, thunk_fndecl, delta, function)
6508 const char *target_name = XSTR (XEXP (DECL_RTL (function), 0), 0);
6509 static unsigned int current_thunk_number;
6512 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
6513 lab = (*targetm.strip_name_encoding) (label);
6514 target_name = (*targetm.strip_name_encoding) (target_name);
6515 /* FIXME: total_code_bytes is not handled correctly in files with
6517 pa_output_function_prologue (file, 0);
6518 if (VAL_14_BITS_P (delta))
6520 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6522 fprintf (file, "\taddil LT%%%s,%%r19\n", lab);
6523 fprintf (file, "\tldw RT%%%s(%%r1),%%r22\n", lab);
6524 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6525 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6526 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6527 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6528 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6529 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6530 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
6531 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6532 fprintf (file, "(%%r26),%%r26\n");
6536 fprintf (file, "\tb %s\n\tldo ", target_name);
6537 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6538 fprintf (file, "(%%r26),%%r26\n");
6543 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6545 fprintf (file, "\taddil L%%");
6546 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6547 fprintf (file, ",%%r26\n\tldo R%%");
6548 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6549 fprintf (file, "(%%r1),%%r26\n");
6550 fprintf (file, "\taddil LT%%%s,%%r19\n", lab);
6551 fprintf (file, "\tldw RT%%%s(%%r1),%%r22\n", lab);
6552 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6553 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6554 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6555 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6556 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6557 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6558 fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n");
6562 fprintf (file, "\taddil L%%");
6563 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6564 fprintf (file, ",%%r26\n\tb %s\n\tldo R%%", target_name);
6565 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6566 fprintf (file, "(%%r1),%%r26\n");
6570 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
6571 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6574 fprintf (file, "\t.align 4\n");
6575 ASM_OUTPUT_INTERNAL_LABEL (file, "LTHN", current_thunk_number);
6576 fprintf (file, "\t.word P%%%s\n", target_name);
6577 function_section (thunk_fndecl);
6579 current_thunk_number++;
6582 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6583 use in fmpyadd instructions. */
6585 fmpyaddoperands (operands)
6588 enum machine_mode mode = GET_MODE (operands[0]);
6590 /* Must be a floating point mode. */
6591 if (mode != SFmode && mode != DFmode)
6594 /* All modes must be the same. */
6595 if (! (mode == GET_MODE (operands[1])
6596 && mode == GET_MODE (operands[2])
6597 && mode == GET_MODE (operands[3])
6598 && mode == GET_MODE (operands[4])
6599 && mode == GET_MODE (operands[5])))
6602 /* All operands must be registers. */
6603 if (! (GET_CODE (operands[1]) == REG
6604 && GET_CODE (operands[2]) == REG
6605 && GET_CODE (operands[3]) == REG
6606 && GET_CODE (operands[4]) == REG
6607 && GET_CODE (operands[5]) == REG))
6610 /* Only 2 real operands to the addition. One of the input operands must
6611 be the same as the output operand. */
6612 if (! rtx_equal_p (operands[3], operands[4])
6613 && ! rtx_equal_p (operands[3], operands[5]))
6616 /* Inout operand of add can not conflict with any operands from multiply. */
6617 if (rtx_equal_p (operands[3], operands[0])
6618 || rtx_equal_p (operands[3], operands[1])
6619 || rtx_equal_p (operands[3], operands[2]))
6622 /* multiply can not feed into addition operands. */
6623 if (rtx_equal_p (operands[4], operands[0])
6624 || rtx_equal_p (operands[5], operands[0]))
6627 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6629 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6630 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6631 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6632 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6633 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6634 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6637 /* Passed. Operands are suitable for fmpyadd. */
6641 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6642 use in fmpysub instructions. */
6644 fmpysuboperands (operands)
6647 enum machine_mode mode = GET_MODE (operands[0]);
6649 /* Must be a floating point mode. */
6650 if (mode != SFmode && mode != DFmode)
6653 /* All modes must be the same. */
6654 if (! (mode == GET_MODE (operands[1])
6655 && mode == GET_MODE (operands[2])
6656 && mode == GET_MODE (operands[3])
6657 && mode == GET_MODE (operands[4])
6658 && mode == GET_MODE (operands[5])))
6661 /* All operands must be registers. */
6662 if (! (GET_CODE (operands[1]) == REG
6663 && GET_CODE (operands[2]) == REG
6664 && GET_CODE (operands[3]) == REG
6665 && GET_CODE (operands[4]) == REG
6666 && GET_CODE (operands[5]) == REG))
6669 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6670 operation, so operands[4] must be the same as operand[3]. */
6671 if (! rtx_equal_p (operands[3], operands[4]))
6674 /* multiply can not feed into subtraction. */
6675 if (rtx_equal_p (operands[5], operands[0]))
6678 /* Inout operand of sub can not conflict with any operands from multiply. */
6679 if (rtx_equal_p (operands[3], operands[0])
6680 || rtx_equal_p (operands[3], operands[1])
6681 || rtx_equal_p (operands[3], operands[2]))
6684 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6686 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6687 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6688 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6689 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6690 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6691 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6694 /* Passed. Operands are suitable for fmpysub. */
6699 plus_xor_ior_operator (op, mode)
6701 enum machine_mode mode ATTRIBUTE_UNUSED;
6703 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6704 || GET_CODE (op) == IOR);
6707 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6708 constants for shadd instructions. */
6710 shadd_constant_p (val)
6713 if (val == 2 || val == 4 || val == 8)
6719 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6720 the valid constant for shadd instructions. */
6722 shadd_operand (op, mode)
6724 enum machine_mode mode ATTRIBUTE_UNUSED;
6726 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6729 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6732 basereg_operand (op, mode)
6734 enum machine_mode mode;
6736 /* cse will create some unscaled indexed addresses, however; it
6737 generally isn't a win on the PA, so avoid creating unscaled
6738 indexed addresses until after cse is finished. */
6739 if (!cse_not_expected)
6742 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6743 we don't have to worry about the braindamaged implicit space
6744 register selection from the basereg. */
6745 if (TARGET_NO_SPACE_REGS)
6746 return (GET_CODE (op) == REG);
6748 /* While it's always safe to index off the frame pointer, it's not
6749 always profitable, particularly when the frame pointer is being
6751 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6754 return (GET_CODE (op) == REG
6756 && register_operand (op, mode));
6759 /* Return 1 if this operand is anything other than a hard register. */
6762 non_hard_reg_operand (op, mode)
6764 enum machine_mode mode ATTRIBUTE_UNUSED;
6766 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6769 /* Return 1 if INSN branches forward. Should be using insn_addresses
6770 to avoid walking through all the insns... */
6772 forward_branch_p (insn)
6775 rtx label = JUMP_LABEL (insn);
6782 insn = NEXT_INSN (insn);
6785 return (insn == label);
6788 /* Return 1 if OP is an equality comparison, else return 0. */
6790 eq_neq_comparison_operator (op, mode)
6792 enum machine_mode mode ATTRIBUTE_UNUSED;
6794 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6797 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6799 movb_comparison_operator (op, mode)
6801 enum machine_mode mode ATTRIBUTE_UNUSED;
6803 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6804 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6807 /* Return 1 if INSN is in the delay slot of a call instruction. */
6809 jump_in_call_delay (insn)
6813 if (GET_CODE (insn) != JUMP_INSN)
6816 if (PREV_INSN (insn)
6817 && PREV_INSN (PREV_INSN (insn))
6818 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6820 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6822 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6823 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6830 /* Output an unconditional move and branch insn. */
6833 output_parallel_movb (operands, length)
6837 /* These are the cases in which we win. */
6839 return "mov%I1b,tr %1,%0,%2";
6841 /* None of these cases wins, but they don't lose either. */
6842 if (dbr_sequence_length () == 0)
6844 /* Nothing in the delay slot, fake it by putting the combined
6845 insn (the copy or add) in the delay slot of a bl. */
6846 if (GET_CODE (operands[1]) == CONST_INT)
6847 return "b %2\n\tldi %1,%0";
6849 return "b %2\n\tcopy %1,%0";
6853 /* Something in the delay slot, but we've got a long branch. */
6854 if (GET_CODE (operands[1]) == CONST_INT)
6855 return "ldi %1,%0\n\tb %2";
6857 return "copy %1,%0\n\tb %2";
6861 /* Output an unconditional add and branch insn. */
6864 output_parallel_addb (operands, length)
6868 /* To make life easy we want operand0 to be the shared input/output
6869 operand and operand1 to be the readonly operand. */
6870 if (operands[0] == operands[1])
6871 operands[1] = operands[2];
6873 /* These are the cases in which we win. */
6875 return "add%I1b,tr %1,%0,%3";
6877 /* None of these cases win, but they don't lose either. */
6878 if (dbr_sequence_length () == 0)
6880 /* Nothing in the delay slot, fake it by putting the combined
6881 insn (the copy or add) in the delay slot of a bl. */
6882 return "b %3\n\tadd%I1 %1,%0,%0";
6886 /* Something in the delay slot, but we've got a long branch. */
6887 return "add%I1 %1,%0,%0\n\tb %3";
6891 /* Return nonzero if INSN (a jump insn) immediately follows a call
6892 to a named function. This is used to avoid filling the delay slot
6893 of the jump since it can usually be eliminated by modifying RP in
6894 the delay slot of the call. */
6897 following_call (insn)
6900 if (! TARGET_JUMP_IN_DELAY)
6903 /* Find the previous real insn, skipping NOTEs. */
6904 insn = PREV_INSN (insn);
6905 while (insn && GET_CODE (insn) == NOTE)
6906 insn = PREV_INSN (insn);
6908 /* Check for CALL_INSNs and millicode calls. */
6910 && ((GET_CODE (insn) == CALL_INSN
6911 && get_attr_type (insn) != TYPE_DYNCALL)
6912 || (GET_CODE (insn) == INSN
6913 && GET_CODE (PATTERN (insn)) != SEQUENCE
6914 && GET_CODE (PATTERN (insn)) != USE
6915 && GET_CODE (PATTERN (insn)) != CLOBBER
6916 && get_attr_type (insn) == TYPE_MILLI)))
6922 /* We use this hook to perform a PA specific optimization which is difficult
6923 to do in earlier passes.
6925 We want the delay slots of branches within jump tables to be filled.
6926 None of the compiler passes at the moment even has the notion that a
6927 PA jump table doesn't contain addresses, but instead contains actual
6930 Because we actually jump into the table, the addresses of each entry
6931 must stay constant in relation to the beginning of the table (which
6932 itself must stay constant relative to the instruction to jump into
6933 it). I don't believe we can guarantee earlier passes of the compiler
6934 will adhere to those rules.
6936 So, late in the compilation process we find all the jump tables, and
6937 expand them into real code -- eg each entry in the jump table vector
6938 will get an appropriate label followed by a jump to the final target.
6940 Reorg and the final jump pass can then optimize these branches and
6941 fill their delay slots. We end up with smaller, more efficient code.
6943 The jump instructions within the table are special; we must be able
6944 to identify them during assembly output (if the jumps don't get filled
6945 we need to emit a nop rather than nullifying the delay slot)). We
6946 identify jumps in switch tables by marking the SET with DImode.
6948 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6949 insns. This serves two purposes, first it prevents jump.c from
6950 noticing that the last N entries in the table jump to the instruction
6951 immediately after the table and deleting the jumps. Second, those
6952 insns mark where we should emit .begin_brtab and .end_brtab directives
6953 when using GAS (allows for better link time optimizations). */
6961 remove_useless_addtr_insns (insns, 1);
6963 if (pa_cpu < PROCESSOR_8000)
6964 pa_combine_instructions (get_insns ());
6967 /* This is fairly cheap, so always run it if optimizing. */
6968 if (optimize > 0 && !TARGET_BIG_SWITCH)
6970 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6971 insns = get_insns ();
6972 for (insn = insns; insn; insn = NEXT_INSN (insn))
6974 rtx pattern, tmp, location;
6975 unsigned int length, i;
6977 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6978 if (GET_CODE (insn) != JUMP_INSN
6979 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6980 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6983 /* Emit marker for the beginning of the branch table. */
6984 emit_insn_before (gen_begin_brtab (), insn);
6986 pattern = PATTERN (insn);
6987 location = PREV_INSN (insn);
6988 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6990 for (i = 0; i < length; i++)
6992 /* Emit a label before each jump to keep jump.c from
6993 removing this code. */
6994 tmp = gen_label_rtx ();
6995 LABEL_NUSES (tmp) = 1;
6996 emit_label_after (tmp, location);
6997 location = NEXT_INSN (location);
6999 if (GET_CODE (pattern) == ADDR_VEC)
7001 /* Emit the jump itself. */
7002 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
7003 tmp = emit_jump_insn_after (tmp, location);
7004 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
7005 /* It is easy to rely on the branch table markers
7006 during assembly output to trigger the correct code
7007 for a switch table jump with an unfilled delay slot,
7009 However, that requires state and assumes that we look
7012 We can't make such assumptions when computing the length
7013 of instructions. Ugh. We could walk the insn chain to
7014 determine if this instruction is in a branch table, but
7015 that can get rather expensive, particularly during the
7016 branch shortening phase of the compiler.
7018 So instead we mark this jump as being special. This is
7019 far from ideal and knows that no code after this will
7020 muck around with the mode of the JUMP_INSN itself. */
7021 PUT_MODE (tmp, SImode);
7022 LABEL_NUSES (JUMP_LABEL (tmp))++;
7023 location = NEXT_INSN (location);
7027 /* Emit the jump itself. */
7028 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
7029 tmp = emit_jump_insn_after (tmp, location);
7030 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
7031 /* It is easy to rely on the branch table markers
7032 during assembly output to trigger the correct code
7033 for a switch table jump with an unfilled delay slot,
7035 However, that requires state and assumes that we look
7038 We can't make such assumptions when computing the length
7039 of instructions. Ugh. We could walk the insn chain to
7040 determine if this instruction is in a branch table, but
7041 that can get rather expensive, particularly during the
7042 branch shortening phase of the compiler.
7044 So instead we mark this jump as being special. This is
7045 far from ideal and knows that no code after this will
7046 muck around with the mode of the JUMP_INSN itself. */
7047 PUT_MODE (tmp, SImode);
7048 LABEL_NUSES (JUMP_LABEL (tmp))++;
7049 location = NEXT_INSN (location);
7052 /* Emit a BARRIER after the jump. */
7053 emit_barrier_after (location);
7054 location = NEXT_INSN (location);
7057 /* Emit marker for the end of the branch table. */
7058 emit_insn_before (gen_end_brtab (), location);
7059 location = NEXT_INSN (location);
7060 emit_barrier_after (location);
7062 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
7068 /* Sill need an end_brtab insn. */
7069 insns = get_insns ();
7070 for (insn = insns; insn; insn = NEXT_INSN (insn))
7072 /* Find an ADDR_VEC insn. */
7073 if (GET_CODE (insn) != JUMP_INSN
7074 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7075 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7078 /* Now generate markers for the beginning and end of the
7080 emit_insn_before (gen_begin_brtab (), insn);
7081 emit_insn_after (gen_end_brtab (), insn);
7086 /* The PA has a number of odd instructions which can perform multiple
7087 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
7088 it may be profitable to combine two instructions into one instruction
7089 with two outputs. It's not profitable PA2.0 machines because the
7090 two outputs would take two slots in the reorder buffers.
7092 This routine finds instructions which can be combined and combines
7093 them. We only support some of the potential combinations, and we
7094 only try common ways to find suitable instructions.
7096 * addb can add two registers or a register and a small integer
7097 and jump to a nearby (+-8k) location. Normally the jump to the
7098 nearby location is conditional on the result of the add, but by
7099 using the "true" condition we can make the jump unconditional.
7100 Thus addb can perform two independent operations in one insn.
7102 * movb is similar to addb in that it can perform a reg->reg
7103 or small immediate->reg copy and jump to a nearby (+-8k location).
7105 * fmpyadd and fmpysub can perform a FP multiply and either an
7106 FP add or FP sub if the operands of the multiply and add/sub are
7107 independent (there are other minor restrictions). Note both
7108 the fmpy and fadd/fsub can in theory move to better spots according
7109 to data dependencies, but for now we require the fmpy stay at a
7112 * Many of the memory operations can perform pre & post updates
7113 of index registers. GCC's pre/post increment/decrement addressing
7114 is far too simple to take advantage of all the possibilities. This
7115 pass may not be suitable since those insns may not be independent.
7117 * comclr can compare two ints or an int and a register, nullify
7118 the following instruction and zero some other register. This
7119 is more difficult to use as it's harder to find an insn which
7120 will generate a comclr than finding something like an unconditional
7121 branch. (conditional moves & long branches create comclr insns).
7123 * Most arithmetic operations can conditionally skip the next
7124 instruction. They can be viewed as "perform this operation
7125 and conditionally jump to this nearby location" (where nearby
7126 is an insns away). These are difficult to use due to the
7127 branch length restrictions. */
7130 pa_combine_instructions (insns)
7131 rtx insns ATTRIBUTE_UNUSED;
7135 /* This can get expensive since the basic algorithm is on the
7136 order of O(n^2) (or worse). Only do it for -O2 or higher
7137 levels of optimization. */
7141 /* Walk down the list of insns looking for "anchor" insns which
7142 may be combined with "floating" insns. As the name implies,
7143 "anchor" instructions don't move, while "floating" insns may
7145 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
7146 new = make_insn_raw (new);
7148 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
7150 enum attr_pa_combine_type anchor_attr;
7151 enum attr_pa_combine_type floater_attr;
7153 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
7154 Also ignore any special USE insns. */
7155 if ((GET_CODE (anchor) != INSN
7156 && GET_CODE (anchor) != JUMP_INSN
7157 && GET_CODE (anchor) != CALL_INSN)
7158 || GET_CODE (PATTERN (anchor)) == USE
7159 || GET_CODE (PATTERN (anchor)) == CLOBBER
7160 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
7161 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
7164 anchor_attr = get_attr_pa_combine_type (anchor);
7165 /* See if anchor is an insn suitable for combination. */
7166 if (anchor_attr == PA_COMBINE_TYPE_FMPY
7167 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
7168 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7169 && ! forward_branch_p (anchor)))
7173 for (floater = PREV_INSN (anchor);
7175 floater = PREV_INSN (floater))
7177 if (GET_CODE (floater) == NOTE
7178 || (GET_CODE (floater) == INSN
7179 && (GET_CODE (PATTERN (floater)) == USE
7180 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7183 /* Anything except a regular INSN will stop our search. */
7184 if (GET_CODE (floater) != INSN
7185 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7186 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7192 /* See if FLOATER is suitable for combination with the
7194 floater_attr = get_attr_pa_combine_type (floater);
7195 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7196 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7197 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7198 && floater_attr == PA_COMBINE_TYPE_FMPY))
7200 /* If ANCHOR and FLOATER can be combined, then we're
7201 done with this pass. */
7202 if (pa_can_combine_p (new, anchor, floater, 0,
7203 SET_DEST (PATTERN (floater)),
7204 XEXP (SET_SRC (PATTERN (floater)), 0),
7205 XEXP (SET_SRC (PATTERN (floater)), 1)))
7209 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7210 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
7212 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
7214 if (pa_can_combine_p (new, anchor, floater, 0,
7215 SET_DEST (PATTERN (floater)),
7216 XEXP (SET_SRC (PATTERN (floater)), 0),
7217 XEXP (SET_SRC (PATTERN (floater)), 1)))
7222 if (pa_can_combine_p (new, anchor, floater, 0,
7223 SET_DEST (PATTERN (floater)),
7224 SET_SRC (PATTERN (floater)),
7225 SET_SRC (PATTERN (floater))))
7231 /* If we didn't find anything on the backwards scan try forwards. */
7233 && (anchor_attr == PA_COMBINE_TYPE_FMPY
7234 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
7236 for (floater = anchor; floater; floater = NEXT_INSN (floater))
7238 if (GET_CODE (floater) == NOTE
7239 || (GET_CODE (floater) == INSN
7240 && (GET_CODE (PATTERN (floater)) == USE
7241 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7245 /* Anything except a regular INSN will stop our search. */
7246 if (GET_CODE (floater) != INSN
7247 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7248 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7254 /* See if FLOATER is suitable for combination with the
7256 floater_attr = get_attr_pa_combine_type (floater);
7257 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7258 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7259 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7260 && floater_attr == PA_COMBINE_TYPE_FMPY))
7262 /* If ANCHOR and FLOATER can be combined, then we're
7263 done with this pass. */
7264 if (pa_can_combine_p (new, anchor, floater, 1,
7265 SET_DEST (PATTERN (floater)),
7266 XEXP (SET_SRC (PATTERN (floater)),
7268 XEXP (SET_SRC (PATTERN (floater)),
7275 /* FLOATER will be nonzero if we found a suitable floating
7276 insn for combination with ANCHOR. */
7278 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7279 || anchor_attr == PA_COMBINE_TYPE_FMPY))
7281 /* Emit the new instruction and delete the old anchor. */
7282 emit_insn_before (gen_rtx_PARALLEL
7284 gen_rtvec (2, PATTERN (anchor),
7285 PATTERN (floater))),
7288 PUT_CODE (anchor, NOTE);
7289 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7290 NOTE_SOURCE_FILE (anchor) = 0;
7292 /* Emit a special USE insn for FLOATER, then delete
7293 the floating insn. */
7294 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7295 delete_insn (floater);
7300 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
7303 /* Emit the new_jump instruction and delete the old anchor. */
7305 = emit_jump_insn_before (gen_rtx_PARALLEL
7307 gen_rtvec (2, PATTERN (anchor),
7308 PATTERN (floater))),
7311 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
7312 PUT_CODE (anchor, NOTE);
7313 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7314 NOTE_SOURCE_FILE (anchor) = 0;
7316 /* Emit a special USE insn for FLOATER, then delete
7317 the floating insn. */
7318 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7319 delete_insn (floater);
7327 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
7328 rtx new, anchor, floater;
7330 rtx dest, src1, src2;
7332 int insn_code_number;
7335 /* Create a PARALLEL with the patterns of ANCHOR and
7336 FLOATER, try to recognize it, then test constraints
7337 for the resulting pattern.
7339 If the pattern doesn't match or the constraints
7340 aren't met keep searching for a suitable floater
7342 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
7343 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
7344 INSN_CODE (new) = -1;
7345 insn_code_number = recog_memoized (new);
7346 if (insn_code_number < 0
7347 || (extract_insn (new), ! constrain_operands (1)))
7361 /* There's up to three operands to consider. One
7362 output and two inputs.
7364 The output must not be used between FLOATER & ANCHOR
7365 exclusive. The inputs must not be set between
7366 FLOATER and ANCHOR exclusive. */
7368 if (reg_used_between_p (dest, start, end))
7371 if (reg_set_between_p (src1, start, end))
7374 if (reg_set_between_p (src2, start, end))
7377 /* If we get here, then everything is good. */
7381 /* Return nonzero if references for INSN are delayed.
7383 Millicode insns are actually function calls with some special
7384 constraints on arguments and register usage.
7386 Millicode calls always expect their arguments in the integer argument
7387 registers, and always return their result in %r29 (ret1). They
7388 are expected to clobber their arguments, %r1, %r29, and the return
7389 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
7391 This function tells reorg that the references to arguments and
7392 millicode calls do not appear to happen until after the millicode call.
7393 This allows reorg to put insns which set the argument registers into the
7394 delay slot of the millicode call -- thus they act more like traditional
7397 Note we can not consider side effects of the insn to be delayed because
7398 the branch and link insn will clobber the return pointer. If we happened
7399 to use the return pointer in the delay slot of the call, then we lose.
7401 get_attr_type will try to recognize the given insn, so make sure to
7402 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
7405 insn_refs_are_delayed (insn)
7408 return ((GET_CODE (insn) == INSN
7409 && GET_CODE (PATTERN (insn)) != SEQUENCE
7410 && GET_CODE (PATTERN (insn)) != USE
7411 && GET_CODE (PATTERN (insn)) != CLOBBER
7412 && get_attr_type (insn) == TYPE_MILLI));
7415 /* Return the location of a parameter that is passed in a register or NULL
7416 if the parameter has any component that is passed in memory.
7418 This is new code and will be pushed to into the net sources after
7421 ??? We might want to restructure this so that it looks more like other
7424 function_arg (cum, mode, type, named, incoming)
7425 CUMULATIVE_ARGS *cum;
7426 enum machine_mode mode;
7428 int named ATTRIBUTE_UNUSED;
7431 int max_arg_words = (TARGET_64BIT ? 8 : 4);
7438 /* If this arg would be passed partially or totally on the stack, then
7439 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
7440 handle arguments which are split between regs and stack slots if
7441 the ABI mandates split arguments. */
7442 if (cum->words + FUNCTION_ARG_SIZE (mode, type) > max_arg_words
7443 || mode == VOIDmode)
7449 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7451 if (cum->words + offset >= max_arg_words
7452 || mode == VOIDmode)
7456 /* The 32bit ABIs and the 64bit ABIs are rather different,
7457 particularly in their handling of FP registers. We might
7458 be able to cleverly share code between them, but I'm not
7459 going to bother in the hope that splitting them up results
7460 in code that is more easily understood.
7462 The 64bit code probably is very wrong for structure passing. */
7465 /* Advance the base registers to their current locations.
7467 Remember, gprs grow towards smaller register numbers while
7468 fprs grow to higher register numbers. Also remember FP regs
7469 are always 4 bytes wide, while the size of an integer register
7470 varies based on the size of the target word. */
7471 gpr_reg_base = 26 - cum->words;
7472 fpr_reg_base = 32 + cum->words;
7474 /* If the argument is more than a word long, then we need to align
7475 the base registers. Same caveats as above. */
7476 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7478 if (mode != BLKmode)
7480 /* First deal with alignment of the doubleword. */
7481 gpr_reg_base -= (cum->words & 1);
7483 /* This seems backwards, but it is what HP specifies. We need
7484 gpr_reg_base to point to the smaller numbered register of
7485 the integer register pair. So if we have an even register
7486 number, then decrement the gpr base. */
7487 gpr_reg_base -= ((gpr_reg_base % 2) == 0);
7489 /* FP values behave sanely, except that each FP reg is only
7491 fpr_reg_base += ((fpr_reg_base % 2) == 0);
7496 int i, offset = 0, ub;
7497 ub = FUNCTION_ARG_SIZE (mode, type);
7499 MAX (0, max_arg_words - cum->words - (cum->words & 1)));
7500 gpr_reg_base -= (cum->words & 1);
7501 for (i = 0; i < ub; i++)
7503 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7504 gen_rtx_REG (DImode,
7513 return XEXP (loc[0], 0);
7515 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7521 /* If the argument is larger than a word, then we know precisely
7522 which registers we must use. */
7523 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7538 /* We have a single word (32 bits). A simple computation
7539 will get us the register #s we need. */
7540 gpr_reg_base = 26 - cum->words;
7541 fpr_reg_base = 32 + 2 * cum->words;
7545 if (TARGET_64BIT && mode == TFmode)
7551 gen_rtx_EXPR_LIST (VOIDmode,
7552 gen_rtx_REG (DImode, gpr_reg_base + 1),
7554 gen_rtx_EXPR_LIST (VOIDmode,
7555 gen_rtx_REG (DImode, gpr_reg_base),
7558 /* Determine if the argument needs to be passed in both general and
7559 floating point registers. */
7560 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7561 /* If we are doing soft-float with portable runtime, then there
7562 is no need to worry about FP regs. */
7563 && ! TARGET_SOFT_FLOAT
7564 /* The parameter must be some kind of float, else we can just
7565 pass it in integer registers. */
7566 && FLOAT_MODE_P (mode)
7567 /* The target function must not have a prototype. */
7568 && cum->nargs_prototype <= 0
7569 /* libcalls do not need to pass items in both FP and general
7571 && type != NULL_TREE
7572 /* All this hair applies to outgoing args only. */
7574 /* Also pass outgoing floating arguments in both registers in indirect
7575 calls with the 32 bit ABI and the HP assembler since there is no
7576 way to the specify argument locations in static functions. */
7581 && FLOAT_MODE_P (mode)))
7587 gen_rtx_EXPR_LIST (VOIDmode,
7588 gen_rtx_REG (mode, fpr_reg_base),
7590 gen_rtx_EXPR_LIST (VOIDmode,
7591 gen_rtx_REG (mode, gpr_reg_base),
7596 /* See if we should pass this parameter in a general register. */
7597 if (TARGET_SOFT_FLOAT
7598 /* Indirect calls in the normal 32bit ABI require all arguments
7599 to be passed in general registers. */
7600 || (!TARGET_PORTABLE_RUNTIME
7604 /* If the parameter is not a floating point parameter, then
7605 it belongs in GPRs. */
7606 || !FLOAT_MODE_P (mode))
7607 retval = gen_rtx_REG (mode, gpr_reg_base);
7609 retval = gen_rtx_REG (mode, fpr_reg_base);
7615 /* If this arg would be passed totally in registers or totally on the stack,
7616 then this routine should return zero. It is currently called only for
7617 the 64-bit target. */
7619 function_arg_partial_nregs (cum, mode, type, named)
7620 CUMULATIVE_ARGS *cum;
7621 enum machine_mode mode;
7623 int named ATTRIBUTE_UNUSED;
7625 unsigned int max_arg_words = 8;
7626 unsigned int offset = 0;
7628 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7631 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
7632 /* Arg fits fully into registers. */
7634 else if (cum->words + offset >= max_arg_words)
7635 /* Arg fully on the stack. */
7639 return max_arg_words - cum->words - offset;
7643 /* Return 1 if this is a comparison operator. This allows the use of
7644 MATCH_OPERATOR to recognize all the branch insns. */
7647 cmpib_comparison_operator (op, mode)
7649 enum machine_mode mode;
7651 return ((mode == VOIDmode || GET_MODE (op) == mode)
7652 && (GET_CODE (op) == EQ
7653 || GET_CODE (op) == NE
7654 || GET_CODE (op) == GT
7655 || GET_CODE (op) == GTU
7656 || GET_CODE (op) == GE
7657 || GET_CODE (op) == LT
7658 || GET_CODE (op) == LE
7659 || GET_CODE (op) == LEU));
7662 /* Mark ARG (which is really a struct deferred_plabel **) for GC. */
7665 mark_deferred_plabels (arg)
7668 struct deferred_plabel *dp = *(struct deferred_plabel **) arg;
7671 for (i = 0; i < n_deferred_plabels; ++i)
7672 ggc_mark_rtx (dp[i].internal_label);
7675 /* Called to register all of our global variables with the garbage
7681 ggc_add_rtx_root (&hppa_compare_op0, 1);
7682 ggc_add_rtx_root (&hppa_compare_op1, 1);
7683 ggc_add_root (&deferred_plabels, 1, sizeof (&deferred_plabels),
7684 &mark_deferred_plabels);
7687 /* On hpux10, the linker will give an error if we have a reference
7688 in the read-only data section to a symbol defined in a shared
7689 library. Therefore, expressions that might require a reloc can
7690 not be placed in the read-only data section. */
7693 pa_select_section (exp, reloc, align)
7696 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
7698 if (TREE_CODE (exp) == VAR_DECL
7699 && TREE_READONLY (exp)
7700 && !TREE_THIS_VOLATILE (exp)
7701 && DECL_INITIAL (exp)
7702 && (DECL_INITIAL (exp) == error_mark_node
7703 || TREE_CONSTANT (DECL_INITIAL (exp)))
7705 readonly_data_section ();
7706 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
7707 && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings)
7709 readonly_data_section ();