1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
45 #ifndef DO_FRAME_NOTES
46 #ifdef INCOMING_RETURN_ADDR_RTX
47 #define DO_FRAME_NOTES 1
49 #define DO_FRAME_NOTES 0
53 static void pa_init_machine_status PARAMS ((struct function *));
54 static void pa_mark_machine_status PARAMS ((struct function *));
55 static void pa_free_machine_status PARAMS ((struct function *));
56 static void pa_combine_instructions PARAMS ((rtx));
57 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
58 static int forward_branch_p PARAMS ((rtx));
59 static int shadd_constant_p PARAMS ((int));
60 static void pa_add_gc_roots PARAMS ((void));
61 static void mark_deferred_plabels PARAMS ((void *));
62 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
63 static int compute_movstrsi_length PARAMS ((rtx));
64 static void remove_useless_addtr_insns PARAMS ((rtx, int));
65 static rtx store_reg PARAMS ((int, int, int));
66 static rtx load_reg PARAMS ((int, int, int));
67 static rtx set_reg_plus_d PARAMS ((int, int, int));
69 /* Save the operands last given to a compare for use when we
70 generate a scc or bcc insn. */
72 rtx hppa_compare_op0, hppa_compare_op1;
73 enum cmp_type hppa_branch_type;
75 /* Which cpu we are scheduling for. */
76 enum processor_type pa_cpu;
78 /* String to hold which cpu we are scheduling for. */
79 const char *pa_cpu_string;
81 /* Which architecture we are generating code for. */
82 enum architecture_type pa_arch;
84 /* String to hold which architecture we are generating code for. */
85 const char *pa_arch_string;
87 /* Counts for the number of callee-saved general and floating point
88 registers which were saved by the current function's prologue. */
89 static int gr_saved, fr_saved;
91 static rtx find_addr_reg PARAMS ((rtx));
93 /* Keep track of the number of bytes we have output in the CODE subspaces
94 during this compilation so we'll know when to emit inline long-calls. */
96 unsigned int total_code_bytes;
98 /* Variables to handle plabels that we discover are necessary at assembly
99 output time. They are output after the current function. */
101 struct deferred_plabel
105 } *deferred_plabels = 0;
106 int n_deferred_plabels = 0;
111 /* Default to 7100LC scheduling. */
112 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
114 pa_cpu_string = "7100";
115 pa_cpu = PROCESSOR_7100;
117 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
119 pa_cpu_string = "700";
120 pa_cpu = PROCESSOR_700;
122 else if (pa_cpu_string == NULL
123 || ! strcmp (pa_cpu_string, "7100LC"))
125 pa_cpu_string = "7100LC";
126 pa_cpu = PROCESSOR_7100LC;
128 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
130 pa_cpu_string = "7200";
131 pa_cpu = PROCESSOR_7200;
133 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "8000"))
135 pa_cpu_string = "8000";
136 pa_cpu = PROCESSOR_8000;
140 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string);
143 /* Set the instruction set architecture. */
144 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
146 pa_arch_string = "1.0";
147 pa_arch = ARCHITECTURE_10;
148 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
150 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
152 pa_arch_string = "1.1";
153 pa_arch = ARCHITECTURE_11;
154 target_flags &= ~MASK_PA_20;
155 target_flags |= MASK_PA_11;
157 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
159 pa_arch_string = "2.0";
160 pa_arch = ARCHITECTURE_20;
161 target_flags |= MASK_PA_11 | MASK_PA_20;
163 else if (pa_arch_string)
165 warning ("Unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
168 if (flag_pic && TARGET_PORTABLE_RUNTIME)
170 warning ("PIC code generation is not supported in the portable runtime model\n");
173 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
175 warning ("PIC code generation is not compatible with fast indirect calls\n");
178 if (! TARGET_GAS && write_symbols != NO_DEBUG)
180 warning ("-g is only supported when using GAS on this processor,");
181 warning ("-g option disabled.");
182 write_symbols = NO_DEBUG;
185 /* We only support the "big PIC" model now. And we always generate PIC
186 code when in 64bit mode. */
187 if (flag_pic == 1 || TARGET_64BIT)
190 /* Register global variables with the garbage collector. */
193 /* Arrange to save and restore machine status around nested functions. */
194 init_machine_status = pa_init_machine_status;
195 mark_machine_status = pa_mark_machine_status;
196 free_machine_status = pa_free_machine_status;
199 /* Functions to initialize pic_offset_table_save_rtx.
200 These will be called, via pointer variables,
201 from push_function_context and pop_function_context. */
204 pa_init_machine_status (p)
207 p->machine = (machine_function *) xmalloc (sizeof (machine_function));
209 p->machine->pic_offset_table_save_rtx = NULL_RTX;
213 pa_mark_machine_status (p)
217 ggc_mark_rtx (p->machine->pic_offset_table_save_rtx);
221 pa_free_machine_status (p)
224 if (p->machine == NULL)
232 /* Return non-zero only if OP is a register of mode MODE,
235 reg_or_0_operand (op, mode)
237 enum machine_mode mode;
239 return (op == CONST0_RTX (mode) || register_operand (op, mode));
242 /* Return non-zero if OP is suitable for use in a call to a named
245 For 2.5 try to eliminate either call_operand_address or
246 function_label_operand, they perform very similar functions. */
248 call_operand_address (op, mode)
250 enum machine_mode mode ATTRIBUTE_UNUSED;
252 return (GET_MODE (op) == word_mode
253 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
256 /* Return 1 if X contains a symbolic expression. We know these
257 expressions will have one of a few well defined forms, so
258 we need only check those forms. */
260 symbolic_expression_p (x)
264 /* Strip off any HIGH. */
265 if (GET_CODE (x) == HIGH)
268 return (symbolic_operand (x, VOIDmode));
272 symbolic_operand (op, mode)
274 enum machine_mode mode ATTRIBUTE_UNUSED;
276 switch (GET_CODE (op))
283 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
284 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
285 && GET_CODE (XEXP (op, 1)) == CONST_INT);
291 /* Return truth value of statement that OP is a symbolic memory
292 operand of mode MODE. */
295 symbolic_memory_operand (op, mode)
297 enum machine_mode mode ATTRIBUTE_UNUSED;
299 if (GET_CODE (op) == SUBREG)
300 op = SUBREG_REG (op);
301 if (GET_CODE (op) != MEM)
304 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
305 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
308 /* Return 1 if the operand is either a register or a memory operand that is
312 reg_or_nonsymb_mem_operand (op, mode)
314 enum machine_mode mode;
316 if (register_operand (op, mode))
319 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
325 /* Return 1 if the operand is either a register, zero, or a memory operand
326 that is not symbolic. */
329 reg_or_0_or_nonsymb_mem_operand (op, mode)
331 enum machine_mode mode;
333 if (register_operand (op, mode))
336 if (op == CONST0_RTX (mode))
339 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
345 /* Accept any constant that can be moved in one instructions into a
348 cint_ok_for_move (intval)
349 HOST_WIDE_INT intval;
351 /* OK if ldo, ldil, or zdepi, can be used. */
352 return (CONST_OK_FOR_LETTER_P (intval, 'J')
353 || CONST_OK_FOR_LETTER_P (intval, 'N')
354 || CONST_OK_FOR_LETTER_P (intval, 'K'));
357 /* Accept anything that can be moved in one instruction into a general
360 move_operand (op, mode)
362 enum machine_mode mode;
364 if (register_operand (op, mode))
367 if (GET_CODE (op) == CONSTANT_P_RTX)
370 if (GET_CODE (op) == CONST_INT)
371 return cint_ok_for_move (INTVAL (op));
373 if (GET_CODE (op) == SUBREG)
374 op = SUBREG_REG (op);
375 if (GET_CODE (op) != MEM)
380 /* We consider a LO_SUM DLT reference a move_operand now since it has
381 been merged into the normal movsi/movdi patterns. */
382 if (GET_CODE (op) == LO_SUM
383 && GET_CODE (XEXP (op, 0)) == REG
384 && REG_OK_FOR_BASE_P (XEXP (op, 0))
385 && GET_CODE (XEXP (op, 1)) == UNSPEC
386 && GET_MODE (op) == Pmode)
389 /* Since move_operand is only used for source operands, we can always
390 allow scaled indexing! */
391 if (! TARGET_DISABLE_INDEXING
392 && GET_CODE (op) == PLUS
393 && ((GET_CODE (XEXP (op, 0)) == MULT
394 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
395 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
396 && INTVAL (XEXP (XEXP (op, 0), 1)) == GET_MODE_SIZE (mode)
397 && GET_CODE (XEXP (op, 1)) == REG)
398 || (GET_CODE (XEXP (op, 1)) == MULT
399 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
400 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
401 && INTVAL (XEXP (XEXP (op, 1), 1)) == GET_MODE_SIZE (mode)
402 && GET_CODE (XEXP (op, 0)) == REG)))
405 return memory_address_p (mode, op);
408 /* Accept REG and any CONST_INT that can be moved in one instruction into a
411 reg_or_cint_move_operand (op, mode)
413 enum machine_mode mode;
415 if (register_operand (op, mode))
418 if (GET_CODE (op) == CONST_INT)
419 return cint_ok_for_move (INTVAL (op));
425 pic_label_operand (op, mode)
427 enum machine_mode mode ATTRIBUTE_UNUSED;
432 switch (GET_CODE (op))
438 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
439 && GET_CODE (XEXP (op, 1)) == CONST_INT);
446 fp_reg_operand (op, mode)
448 enum machine_mode mode ATTRIBUTE_UNUSED;
450 return reg_renumber && FP_REG_P (op);
455 /* Return truth value of whether OP can be used as an operand in a
456 three operand arithmetic insn that accepts registers of mode MODE
457 or 14-bit signed integers. */
459 arith_operand (op, mode)
461 enum machine_mode mode;
463 return (register_operand (op, mode)
464 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
467 /* Return truth value of whether OP can be used as an operand in a
468 three operand arithmetic insn that accepts registers of mode MODE
469 or 11-bit signed integers. */
471 arith11_operand (op, mode)
473 enum machine_mode mode;
475 return (register_operand (op, mode)
476 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
479 /* A constant integer suitable for use in a PRE_MODIFY memory
482 pre_cint_operand (op, mode)
484 enum machine_mode mode ATTRIBUTE_UNUSED;
486 return (GET_CODE (op) == CONST_INT
487 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
490 /* A constant integer suitable for use in a POST_MODIFY memory
493 post_cint_operand (op, mode)
495 enum machine_mode mode ATTRIBUTE_UNUSED;
497 return (GET_CODE (op) == CONST_INT
498 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
502 arith_double_operand (op, mode)
504 enum machine_mode mode;
506 return (register_operand (op, mode)
507 || (GET_CODE (op) == CONST_DOUBLE
508 && GET_MODE (op) == mode
509 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
510 && ((CONST_DOUBLE_HIGH (op) >= 0)
511 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
514 /* Return truth value of whether OP is a integer which fits the
515 range constraining immediate operands in three-address insns, or
516 is an integer register. */
519 ireg_or_int5_operand (op, mode)
521 enum machine_mode mode ATTRIBUTE_UNUSED;
523 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
524 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
527 /* Return nonzero if OP is an integer register, else return zero. */
529 ireg_operand (op, mode)
531 enum machine_mode mode ATTRIBUTE_UNUSED;
533 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
536 /* Return truth value of whether OP is a integer which fits the
537 range constraining immediate operands in three-address insns. */
540 int5_operand (op, mode)
542 enum machine_mode mode ATTRIBUTE_UNUSED;
544 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
548 uint5_operand (op, mode)
550 enum machine_mode mode ATTRIBUTE_UNUSED;
552 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
556 int11_operand (op, mode)
558 enum machine_mode mode ATTRIBUTE_UNUSED;
560 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
564 uint32_operand (op, mode)
566 enum machine_mode mode ATTRIBUTE_UNUSED;
568 #if HOST_BITS_PER_WIDE_INT > 32
569 /* All allowed constants will fit a CONST_INT. */
570 return (GET_CODE (op) == CONST_INT
571 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
573 return (GET_CODE (op) == CONST_INT
574 || (GET_CODE (op) == CONST_DOUBLE
575 && CONST_DOUBLE_HIGH (op) == 0));
580 arith5_operand (op, mode)
582 enum machine_mode mode;
584 return register_operand (op, mode) || int5_operand (op, mode);
587 /* True iff zdepi can be used to generate this CONST_INT.
588 zdepi first sign extends a 5 bit signed number to a given field
589 length, then places this field anywhere in a zero. */
592 unsigned HOST_WIDE_INT x;
594 unsigned HOST_WIDE_INT lsb_mask, t;
596 /* This might not be obvious, but it's at least fast.
597 This function is critical; we don't have the time loops would take. */
599 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
600 /* Return true iff t is a power of two. */
601 return ((t & (t - 1)) == 0);
604 /* True iff depi or extru can be used to compute (reg & mask).
605 Accept bit pattern like these:
611 unsigned HOST_WIDE_INT mask;
614 mask += mask & -mask;
615 return (mask & (mask - 1)) == 0;
618 /* True iff depi or extru can be used to compute (reg & OP). */
620 and_operand (op, mode)
622 enum machine_mode mode;
624 return (register_operand (op, mode)
625 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
628 /* True iff depi can be used to compute (reg | MASK). */
631 unsigned HOST_WIDE_INT mask;
633 mask += mask & -mask;
634 return (mask & (mask - 1)) == 0;
637 /* True iff depi can be used to compute (reg | OP). */
639 ior_operand (op, mode)
641 enum machine_mode mode ATTRIBUTE_UNUSED;
643 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
647 lhs_lshift_operand (op, mode)
649 enum machine_mode mode;
651 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
654 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
655 Such values can be the left hand side x in (x << r), using the zvdepi
658 lhs_lshift_cint_operand (op, mode)
660 enum machine_mode mode ATTRIBUTE_UNUSED;
662 unsigned HOST_WIDE_INT x;
663 if (GET_CODE (op) != CONST_INT)
665 x = INTVAL (op) >> 4;
666 return (x & (x + 1)) == 0;
670 arith32_operand (op, mode)
672 enum machine_mode mode;
674 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
678 pc_or_label_operand (op, mode)
680 enum machine_mode mode ATTRIBUTE_UNUSED;
682 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
685 /* Legitimize PIC addresses. If the address is already
686 position-independent, we return ORIG. Newly generated
687 position-independent addresses go to REG. If we need more
688 than one register, we lose. */
691 legitimize_pic_address (orig, mode, reg)
693 enum machine_mode mode;
697 /* Labels need special handling. */
698 if (pic_label_operand (orig, mode))
700 /* We do not want to go through the movXX expanders here since that
701 would create recursion.
703 Nor do we really want to call a generator for a named pattern
704 since that requires multiple patterns if we want to support
707 So instead we just emit the raw set, which avoids the movXX
708 expanders completely. */
709 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
710 current_function_uses_pic_offset_table = 1;
713 if (GET_CODE (orig) == SYMBOL_REF)
719 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
720 gen_rtx_HIGH (word_mode, orig)));
722 = gen_rtx_MEM (Pmode,
723 gen_rtx_LO_SUM (Pmode, reg,
724 gen_rtx_UNSPEC (Pmode,
728 current_function_uses_pic_offset_table = 1;
729 RTX_UNCHANGING_P (pic_ref) = 1;
730 emit_move_insn (reg, pic_ref);
733 else if (GET_CODE (orig) == CONST)
737 if (GET_CODE (XEXP (orig, 0)) == PLUS
738 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
744 if (GET_CODE (XEXP (orig, 0)) == PLUS)
746 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
747 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
748 base == reg ? 0 : reg);
751 if (GET_CODE (orig) == CONST_INT)
753 if (INT_14_BITS (orig))
754 return plus_constant_for_output (base, INTVAL (orig));
755 orig = force_reg (Pmode, orig);
757 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
758 /* Likewise, should we set special REG_NOTEs here? */
763 /* Try machine-dependent ways of modifying an illegitimate address
764 to be legitimate. If we find one, return the new, valid address.
765 This macro is used in only one place: `memory_address' in explow.c.
767 OLDX is the address as it was before break_out_memory_refs was called.
768 In some cases it is useful to look at this to decide what needs to be done.
770 MODE and WIN are passed so that this macro can use
771 GO_IF_LEGITIMATE_ADDRESS.
773 It is always safe for this macro to do nothing. It exists to recognize
774 opportunities to optimize the output.
776 For the PA, transform:
778 memory(X + <large int>)
782 if (<large int> & mask) >= 16
783 Y = (<large int> & ~mask) + mask + 1 Round up.
785 Y = (<large int> & ~mask) Round down.
787 memory (Z + (<large int> - Y));
789 This is for CSE to find several similar references, and only use one Z.
791 X can either be a SYMBOL_REF or REG, but because combine can not
792 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
793 D will not fit in 14 bits.
795 MODE_FLOAT references allow displacements which fit in 5 bits, so use
798 MODE_INT references allow displacements which fit in 14 bits, so use
801 This relies on the fact that most mode MODE_FLOAT references will use FP
802 registers and most mode MODE_INT references will use integer registers.
803 (In the rare case of an FP register used in an integer MODE, we depend
804 on secondary reloads to clean things up.)
807 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
808 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
809 addressing modes to be used).
811 Put X and Z into registers. Then put the entire expression into
815 hppa_legitimize_address (x, oldx, mode)
816 rtx x, oldx ATTRIBUTE_UNUSED;
817 enum machine_mode mode;
822 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
824 /* Strip off CONST. */
825 if (GET_CODE (x) == CONST)
828 /* Special case. Get the SYMBOL_REF into a register and use indexing.
829 That should always be safe. */
830 if (GET_CODE (x) == PLUS
831 && GET_CODE (XEXP (x, 0)) == REG
832 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
834 rtx reg = force_reg (Pmode, XEXP (x, 1));
835 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
838 /* Note we must reject symbols which represent function addresses
839 since the assembler/linker can't handle arithmetic on plabels. */
840 if (GET_CODE (x) == PLUS
841 && GET_CODE (XEXP (x, 1)) == CONST_INT
842 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
843 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
844 || GET_CODE (XEXP (x, 0)) == REG))
846 rtx int_part, ptr_reg;
848 int offset = INTVAL (XEXP (x, 1));
851 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
852 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
854 /* Choose which way to round the offset. Round up if we
855 are >= halfway to the next boundary. */
856 if ((offset & mask) >= ((mask + 1) / 2))
857 newoffset = (offset & ~ mask) + mask + 1;
859 newoffset = (offset & ~ mask);
861 /* If the newoffset will not fit in 14 bits (ldo), then
862 handling this would take 4 or 5 instructions (2 to load
863 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
864 add the new offset and the SYMBOL_REF.) Combine can
865 not handle 4->2 or 5->2 combinations, so do not create
867 if (! VAL_14_BITS_P (newoffset)
868 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
870 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
873 gen_rtx_HIGH (Pmode, const_part));
876 gen_rtx_LO_SUM (Pmode,
877 tmp_reg, const_part));
881 if (! VAL_14_BITS_P (newoffset))
882 int_part = force_reg (Pmode, GEN_INT (newoffset));
884 int_part = GEN_INT (newoffset);
886 ptr_reg = force_reg (Pmode,
888 force_reg (Pmode, XEXP (x, 0)),
891 return plus_constant (ptr_reg, offset - newoffset);
894 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
896 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
897 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
898 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
899 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
900 || GET_CODE (XEXP (x, 1)) == SUBREG)
901 && GET_CODE (XEXP (x, 1)) != CONST)
903 int val = INTVAL (XEXP (XEXP (x, 0), 1));
907 if (GET_CODE (reg1) != REG)
908 reg1 = force_reg (Pmode, force_operand (reg1, 0));
910 reg2 = XEXP (XEXP (x, 0), 0);
911 if (GET_CODE (reg2) != REG)
912 reg2 = force_reg (Pmode, force_operand (reg2, 0));
914 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
921 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
923 Only do so for floating point modes since this is more speculative
924 and we lose if it's an integer store. */
925 if (GET_CODE (x) == PLUS
926 && GET_CODE (XEXP (x, 0)) == PLUS
927 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
928 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
929 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
930 && (mode == SFmode || mode == DFmode))
933 /* First, try and figure out what to use as a base register. */
934 rtx reg1, reg2, base, idx, orig_base;
936 reg1 = XEXP (XEXP (x, 0), 1);
941 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
942 then emit_move_sequence will turn on REG_POINTER so we'll know
943 it's a base register below. */
944 if (GET_CODE (reg1) != REG)
945 reg1 = force_reg (Pmode, force_operand (reg1, 0));
947 if (GET_CODE (reg2) != REG)
948 reg2 = force_reg (Pmode, force_operand (reg2, 0));
950 /* Figure out what the base and index are. */
952 if (GET_CODE (reg1) == REG
953 && REG_POINTER (reg1))
956 orig_base = XEXP (XEXP (x, 0), 1);
957 idx = gen_rtx_PLUS (Pmode,
959 XEXP (XEXP (XEXP (x, 0), 0), 0),
960 XEXP (XEXP (XEXP (x, 0), 0), 1)),
963 else if (GET_CODE (reg2) == REG
964 && REG_POINTER (reg2))
967 orig_base = XEXP (x, 1);
974 /* If the index adds a large constant, try to scale the
975 constant so that it can be loaded with only one insn. */
976 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
977 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
978 / INTVAL (XEXP (XEXP (idx, 0), 1)))
979 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
981 /* Divide the CONST_INT by the scale factor, then add it to A. */
982 int val = INTVAL (XEXP (idx, 1));
984 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
985 reg1 = XEXP (XEXP (idx, 0), 0);
986 if (GET_CODE (reg1) != REG)
987 reg1 = force_reg (Pmode, force_operand (reg1, 0));
989 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
991 /* We can now generate a simple scaled indexed address. */
994 (Pmode, gen_rtx_PLUS (Pmode,
995 gen_rtx_MULT (Pmode, reg1,
996 XEXP (XEXP (idx, 0), 1)),
1000 /* If B + C is still a valid base register, then add them. */
1001 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1002 && INTVAL (XEXP (idx, 1)) <= 4096
1003 && INTVAL (XEXP (idx, 1)) >= -4096)
1005 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1008 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1010 reg2 = XEXP (XEXP (idx, 0), 0);
1011 if (GET_CODE (reg2) != CONST_INT)
1012 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1014 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1015 gen_rtx_MULT (Pmode,
1021 /* Get the index into a register, then add the base + index and
1022 return a register holding the result. */
1024 /* First get A into a register. */
1025 reg1 = XEXP (XEXP (idx, 0), 0);
1026 if (GET_CODE (reg1) != REG)
1027 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1029 /* And get B into a register. */
1030 reg2 = XEXP (idx, 1);
1031 if (GET_CODE (reg2) != REG)
1032 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1034 reg1 = force_reg (Pmode,
1035 gen_rtx_PLUS (Pmode,
1036 gen_rtx_MULT (Pmode, reg1,
1037 XEXP (XEXP (idx, 0), 1)),
1040 /* Add the result to our base register and return. */
1041 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1045 /* Uh-oh. We might have an address for x[n-100000]. This needs
1046 special handling to avoid creating an indexed memory address
1047 with x-100000 as the base.
1049 If the constant part is small enough, then it's still safe because
1050 there is a guard page at the beginning and end of the data segment.
1052 Scaled references are common enough that we want to try and rearrange the
1053 terms so that we can use indexing for these addresses too. Only
1054 do the optimization for floatint point modes. */
1056 if (GET_CODE (x) == PLUS
1057 && symbolic_expression_p (XEXP (x, 1)))
1059 /* Ugly. We modify things here so that the address offset specified
1060 by the index expression is computed first, then added to x to form
1061 the entire address. */
1063 rtx regx1, regx2, regy1, regy2, y;
1065 /* Strip off any CONST. */
1067 if (GET_CODE (y) == CONST)
1070 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1072 /* See if this looks like
1073 (plus (mult (reg) (shadd_const))
1074 (const (plus (symbol_ref) (const_int))))
1076 Where const_int is small. In that case the const
1077 expression is a valid pointer for indexing.
1079 If const_int is big, but can be divided evenly by shadd_const
1080 and added to (reg). This allows more scaled indexed addresses. */
1081 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1082 && GET_CODE (XEXP (x, 0)) == MULT
1083 && GET_CODE (XEXP (y, 1)) == CONST_INT
1084 && INTVAL (XEXP (y, 1)) >= -4096
1085 && INTVAL (XEXP (y, 1)) <= 4095
1086 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1087 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1089 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1093 if (GET_CODE (reg1) != REG)
1094 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1096 reg2 = XEXP (XEXP (x, 0), 0);
1097 if (GET_CODE (reg2) != REG)
1098 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1100 return force_reg (Pmode,
1101 gen_rtx_PLUS (Pmode,
1102 gen_rtx_MULT (Pmode,
1107 else if ((mode == DFmode || mode == SFmode)
1108 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1109 && GET_CODE (XEXP (x, 0)) == MULT
1110 && GET_CODE (XEXP (y, 1)) == CONST_INT
1111 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1112 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1113 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1116 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1117 / INTVAL (XEXP (XEXP (x, 0), 1))));
1118 regx2 = XEXP (XEXP (x, 0), 0);
1119 if (GET_CODE (regx2) != REG)
1120 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1121 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1125 gen_rtx_PLUS (Pmode,
1126 gen_rtx_MULT (Pmode, regx2,
1127 XEXP (XEXP (x, 0), 1)),
1128 force_reg (Pmode, XEXP (y, 0))));
1130 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1131 && INTVAL (XEXP (y, 1)) >= -4096
1132 && INTVAL (XEXP (y, 1)) <= 4095)
1134 /* This is safe because of the guard page at the
1135 beginning and end of the data space. Just
1136 return the original address. */
1141 /* Doesn't look like one we can optimize. */
1142 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1143 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1144 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1145 regx1 = force_reg (Pmode,
1146 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1148 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1156 /* For the HPPA, REG and REG+CONST is cost 0
1157 and addresses involving symbolic constants are cost 2.
1159 PIC addresses are very expensive.
1161 It is no coincidence that this has the same structure
1162 as GO_IF_LEGITIMATE_ADDRESS. */
1164 hppa_address_cost (X)
1167 if (GET_CODE (X) == PLUS)
1169 else if (GET_CODE (X) == LO_SUM)
1171 else if (GET_CODE (X) == HIGH)
1176 /* Emit insns to move operands[1] into operands[0].
1178 Return 1 if we have written out everything that needs to be done to
1179 do the move. Otherwise, return 0 and the caller will emit the move
1182 Note SCRATCH_REG may not be in the proper mode depending on how it
1183 will be used. This routine is resposible for creating a new copy
1184 of SCRATCH_REG in the proper mode. */
1187 emit_move_sequence (operands, mode, scratch_reg)
1189 enum machine_mode mode;
1192 register rtx operand0 = operands[0];
1193 register rtx operand1 = operands[1];
1197 && reload_in_progress && GET_CODE (operand0) == REG
1198 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1199 operand0 = reg_equiv_mem[REGNO (operand0)];
1200 else if (scratch_reg
1201 && reload_in_progress && GET_CODE (operand0) == SUBREG
1202 && GET_CODE (SUBREG_REG (operand0)) == REG
1203 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1205 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1206 the code which tracks sets/uses for delete_output_reload. */
1207 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1208 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1209 SUBREG_BYTE (operand0));
1210 operand0 = alter_subreg (temp);
1214 && reload_in_progress && GET_CODE (operand1) == REG
1215 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1216 operand1 = reg_equiv_mem[REGNO (operand1)];
1217 else if (scratch_reg
1218 && reload_in_progress && GET_CODE (operand1) == SUBREG
1219 && GET_CODE (SUBREG_REG (operand1)) == REG
1220 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1222 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1223 the code which tracks sets/uses for delete_output_reload. */
1224 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1225 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1226 SUBREG_BYTE (operand1));
1227 operand1 = alter_subreg (temp);
1230 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1231 && ((tem = find_replacement (&XEXP (operand0, 0)))
1232 != XEXP (operand0, 0)))
1233 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1234 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1235 && ((tem = find_replacement (&XEXP (operand1, 0)))
1236 != XEXP (operand1, 0)))
1237 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1239 /* Handle secondary reloads for loads/stores of FP registers from
1240 REG+D addresses where D does not fit in 5 bits, including
1241 (subreg (mem (addr))) cases. */
1242 if (fp_reg_operand (operand0, mode)
1243 && ((GET_CODE (operand1) == MEM
1244 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1245 || ((GET_CODE (operand1) == SUBREG
1246 && GET_CODE (XEXP (operand1, 0)) == MEM
1247 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1250 if (GET_CODE (operand1) == SUBREG)
1251 operand1 = XEXP (operand1, 0);
1253 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1254 it in WORD_MODE regardless of what mode it was originally given
1256 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1258 /* D might not fit in 14 bits either; for such cases load D into
1260 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1262 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1263 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1265 XEXP (XEXP (operand1, 0), 0),
1269 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1270 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1271 gen_rtx_MEM (mode, scratch_reg)));
1274 else if (fp_reg_operand (operand1, mode)
1275 && ((GET_CODE (operand0) == MEM
1276 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1277 || ((GET_CODE (operand0) == SUBREG)
1278 && GET_CODE (XEXP (operand0, 0)) == MEM
1279 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1282 if (GET_CODE (operand0) == SUBREG)
1283 operand0 = XEXP (operand0, 0);
1285 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1286 it in WORD_MODE regardless of what mode it was originally given
1288 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1290 /* D might not fit in 14 bits either; for such cases load D into
1292 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1294 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1295 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1298 XEXP (XEXP (operand0, 0),
1303 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1304 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1308 /* Handle secondary reloads for loads of FP registers from constant
1309 expressions by forcing the constant into memory.
1311 use scratch_reg to hold the address of the memory location.
1313 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1314 NO_REGS when presented with a const_int and an register class
1315 containing only FP registers. Doing so unfortunately creates
1316 more problems than it solves. Fix this for 2.5. */
1317 else if (fp_reg_operand (operand0, mode)
1318 && CONSTANT_P (operand1)
1323 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1324 it in WORD_MODE regardless of what mode it was originally given
1326 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1328 /* Force the constant into memory and put the address of the
1329 memory location into scratch_reg. */
1330 xoperands[0] = scratch_reg;
1331 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1332 emit_move_sequence (xoperands, Pmode, 0);
1334 /* Now load the destination register. */
1335 emit_insn (gen_rtx_SET (mode, operand0,
1336 gen_rtx_MEM (mode, scratch_reg)));
1339 /* Handle secondary reloads for SAR. These occur when trying to load
1340 the SAR from memory, FP register, or with a constant. */
1341 else if (GET_CODE (operand0) == REG
1342 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1343 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1344 && (GET_CODE (operand1) == MEM
1345 || GET_CODE (operand1) == CONST_INT
1346 || (GET_CODE (operand1) == REG
1347 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1350 /* D might not fit in 14 bits either; for such cases load D into
1352 if (GET_CODE (operand1) == MEM
1353 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1355 /* We are reloading the address into the scratch register, so we
1356 want to make sure the scratch register is a full register. */
1357 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1359 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1360 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1363 XEXP (XEXP (operand1, 0),
1367 /* Now we are going to load the scratch register from memory,
1368 we want to load it in the same width as the original MEM,
1369 which must be the same as the width of the ultimate destination,
1371 scratch_reg = gen_rtx_REG (GET_MODE (operand0), REGNO (scratch_reg));
1373 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1378 /* We want to load the scratch register using the same mode as
1379 the ultimate destination. */
1380 scratch_reg = gen_rtx_REG (GET_MODE (operand0), REGNO (scratch_reg));
1381 emit_move_insn (scratch_reg, operand1);
1384 /* And emit the insn to set the ultimate destination. We know that
1385 the scratch register has the same mode as the destination at this
1387 emit_move_insn (operand0, scratch_reg);
1390 /* Handle most common case: storing into a register. */
1391 else if (register_operand (operand0, mode))
1393 if (register_operand (operand1, mode)
1394 || (GET_CODE (operand1) == CONST_INT && INT_14_BITS (operand1))
1395 || (operand1 == CONST0_RTX (mode))
1396 || (GET_CODE (operand1) == HIGH
1397 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1398 /* Only `general_operands' can come here, so MEM is ok. */
1399 || GET_CODE (operand1) == MEM)
1401 /* Run this case quickly. */
1402 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1406 else if (GET_CODE (operand0) == MEM)
1408 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1409 && !(reload_in_progress || reload_completed))
1411 rtx temp = gen_reg_rtx (DFmode);
1413 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1414 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1417 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1419 /* Run this case quickly. */
1420 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1423 if (! (reload_in_progress || reload_completed))
1425 operands[0] = validize_mem (operand0);
1426 operands[1] = operand1 = force_reg (mode, operand1);
1430 /* Simplify the source if we need to.
1431 Note we do have to handle function labels here, even though we do
1432 not consider them legitimate constants. Loop optimizations can
1433 call the emit_move_xxx with one as a source. */
1434 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1435 || function_label_operand (operand1, mode)
1436 || (GET_CODE (operand1) == HIGH
1437 && symbolic_operand (XEXP (operand1, 0), mode)))
1441 if (GET_CODE (operand1) == HIGH)
1444 operand1 = XEXP (operand1, 0);
1446 if (symbolic_operand (operand1, mode))
1448 /* Argh. The assembler and linker can't handle arithmetic
1451 So we force the plabel into memory, load operand0 from
1452 the memory location, then add in the constant part. */
1453 if ((GET_CODE (operand1) == CONST
1454 && GET_CODE (XEXP (operand1, 0)) == PLUS
1455 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1456 || function_label_operand (operand1, mode))
1458 rtx temp, const_part;
1460 /* Figure out what (if any) scratch register to use. */
1461 if (reload_in_progress || reload_completed)
1463 scratch_reg = scratch_reg ? scratch_reg : operand0;
1464 /* SCRATCH_REG will hold an address and maybe the actual
1465 data. We want it in WORD_MODE regardless of what mode it
1466 was originally given to us. */
1467 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1470 scratch_reg = gen_reg_rtx (Pmode);
1472 if (GET_CODE (operand1) == CONST)
1474 /* Save away the constant part of the expression. */
1475 const_part = XEXP (XEXP (operand1, 0), 1);
1476 if (GET_CODE (const_part) != CONST_INT)
1479 /* Force the function label into memory. */
1480 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1484 /* No constant part. */
1485 const_part = NULL_RTX;
1487 /* Force the function label into memory. */
1488 temp = force_const_mem (mode, operand1);
1492 /* Get the address of the memory location. PIC-ify it if
1494 temp = XEXP (temp, 0);
1496 temp = legitimize_pic_address (temp, mode, scratch_reg);
1498 /* Put the address of the memory location into our destination
1501 emit_move_sequence (operands, mode, scratch_reg);
1503 /* Now load from the memory location into our destination
1505 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1506 emit_move_sequence (operands, mode, scratch_reg);
1508 /* And add back in the constant part. */
1509 if (const_part != NULL_RTX)
1510 expand_inc (operand0, const_part);
1519 if (reload_in_progress || reload_completed)
1521 temp = scratch_reg ? scratch_reg : operand0;
1522 /* TEMP will hold an address and maybe the actual
1523 data. We want it in WORD_MODE regardless of what mode it
1524 was originally given to us. */
1525 temp = gen_rtx_REG (word_mode, REGNO (temp));
1528 temp = gen_reg_rtx (Pmode);
1530 /* (const (plus (symbol) (const_int))) must be forced to
1531 memory during/after reload if the const_int will not fit
1533 if (GET_CODE (operand1) == CONST
1534 && GET_CODE (XEXP (operand1, 0)) == PLUS
1535 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1536 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1537 && (reload_completed || reload_in_progress)
1540 operands[1] = force_const_mem (mode, operand1);
1541 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1543 emit_move_sequence (operands, mode, temp);
1547 operands[1] = legitimize_pic_address (operand1, mode, temp);
1548 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1551 /* On the HPPA, references to data space are supposed to use dp,
1552 register 27, but showing it in the RTL inhibits various cse
1553 and loop optimizations. */
1558 if (reload_in_progress || reload_completed)
1560 temp = scratch_reg ? scratch_reg : operand0;
1561 /* TEMP will hold an address and maybe the actual
1562 data. We want it in WORD_MODE regardless of what mode it
1563 was originally given to us. */
1564 temp = gen_rtx_REG (word_mode, REGNO (temp));
1567 temp = gen_reg_rtx (mode);
1569 /* Loading a SYMBOL_REF into a register makes that register
1570 safe to be used as the base in an indexed address.
1572 Don't mark hard registers though. That loses. */
1573 if (GET_CODE (operand0) == REG
1574 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1575 REG_POINTER (operand0) = 1;
1576 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1577 REG_POINTER (temp) = 1;
1579 set = gen_rtx_SET (mode, operand0, temp);
1581 set = gen_rtx_SET (VOIDmode,
1583 gen_rtx_LO_SUM (mode, temp, operand1));
1585 emit_insn (gen_rtx_SET (VOIDmode,
1587 gen_rtx_HIGH (mode, operand1)));
1593 else if (GET_CODE (operand1) != CONST_INT
1594 || ! cint_ok_for_move (INTVAL (operand1)))
1597 int need_zero_extend = 0;
1599 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1600 && HOST_BITS_PER_WIDE_INT > 32
1601 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1603 HOST_WIDE_INT val = INTVAL (operand1);
1606 /* If the value is the same after a 32->64bit sign
1607 extension, then we can use it as-is. Else we will
1608 need to sign extend the constant from 32->64bits
1609 then zero extend the result from 32->64bits. */
1610 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1611 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1614 need_zero_extend = 1;
1615 operand1 = GEN_INT (nval);
1619 if (reload_in_progress || reload_completed)
1622 temp = gen_reg_rtx (mode);
1624 emit_insn (gen_rtx_SET (VOIDmode, temp,
1625 gen_rtx_HIGH (mode, operand1)));
1626 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1627 emit_move_insn (operands[0], operands[1]);
1629 if (need_zero_extend)
1631 emit_insn (gen_zero_extendsidi2 (operands[0],
1632 gen_rtx_SUBREG (SImode,
1640 /* Now have insn-emit do whatever it normally does. */
1644 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1645 it will need a link/runtime reloc). */
1653 switch (TREE_CODE (exp))
1660 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1661 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1666 case NON_LVALUE_EXPR:
1667 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1673 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1674 if (TREE_VALUE (link) != 0)
1675 reloc |= reloc_needed (TREE_VALUE (link));
1688 /* Does operand (which is a symbolic_operand) live in text space? If
1689 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1692 read_only_operand (operand, mode)
1694 enum machine_mode mode ATTRIBUTE_UNUSED;
1696 if (GET_CODE (operand) == CONST)
1697 operand = XEXP (XEXP (operand, 0), 0);
1700 if (GET_CODE (operand) == SYMBOL_REF)
1701 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1705 if (GET_CODE (operand) == SYMBOL_REF)
1706 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1712 /* Return the best assembler insn template
1713 for moving operands[1] into operands[0] as a fullword. */
1715 singlemove_string (operands)
1718 HOST_WIDE_INT intval;
1720 if (GET_CODE (operands[0]) == MEM)
1721 return "stw %r1,%0";
1722 if (GET_CODE (operands[1]) == MEM)
1724 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1729 if (GET_MODE (operands[1]) != SFmode)
1732 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1734 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1735 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1737 operands[1] = GEN_INT (i);
1738 /* Fall through to CONST_INT case. */
1740 if (GET_CODE (operands[1]) == CONST_INT)
1742 intval = INTVAL (operands[1]);
1744 if (VAL_14_BITS_P (intval))
1746 else if ((intval & 0x7ff) == 0)
1747 return "ldil L'%1,%0";
1748 else if (zdepi_cint_p (intval))
1749 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1751 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1753 return "copy %1,%0";
1757 /* Compute position (in OP[1]) and width (in OP[2])
1758 useful for copying IMM to a register using the zdepi
1759 instructions. Store the immediate value to insert in OP[0]. */
1761 compute_zdepwi_operands (imm, op)
1762 unsigned HOST_WIDE_INT imm;
1767 /* Find the least significant set bit in IMM. */
1768 for (lsb = 0; lsb < 32; lsb++)
1775 /* Choose variants based on *sign* of the 5-bit field. */
1776 if ((imm & 0x10) == 0)
1777 len = (lsb <= 28) ? 4 : 32 - lsb;
1780 /* Find the width of the bitstring in IMM. */
1781 for (len = 5; len < 32; len++)
1783 if ((imm & (1 << len)) == 0)
1787 /* Sign extend IMM as a 5-bit value. */
1788 imm = (imm & 0xf) - 0x10;
1796 /* Compute position (in OP[1]) and width (in OP[2])
1797 useful for copying IMM to a register using the depdi,z
1798 instructions. Store the immediate value to insert in OP[0]. */
1800 compute_zdepdi_operands (imm, op)
1801 unsigned HOST_WIDE_INT imm;
1804 HOST_WIDE_INT lsb, len;
1806 /* Find the least significant set bit in IMM. */
1807 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1814 /* Choose variants based on *sign* of the 5-bit field. */
1815 if ((imm & 0x10) == 0)
1816 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1817 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1820 /* Find the width of the bitstring in IMM. */
1821 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1823 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
1827 /* Sign extend IMM as a 5-bit value. */
1828 imm = (imm & 0xf) - 0x10;
1836 /* Output assembler code to perform a doubleword move insn
1837 with operands OPERANDS. */
1840 output_move_double (operands)
1843 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1845 rtx addreg0 = 0, addreg1 = 0;
1847 /* First classify both operands. */
1849 if (REG_P (operands[0]))
1851 else if (offsettable_memref_p (operands[0]))
1853 else if (GET_CODE (operands[0]) == MEM)
1858 if (REG_P (operands[1]))
1860 else if (CONSTANT_P (operands[1]))
1862 else if (offsettable_memref_p (operands[1]))
1864 else if (GET_CODE (operands[1]) == MEM)
1869 /* Check for the cases that the operand constraints are not
1870 supposed to allow to happen. Abort if we get one,
1871 because generating code for these cases is painful. */
1873 if (optype0 != REGOP && optype1 != REGOP)
1876 /* Handle auto decrementing and incrementing loads and stores
1877 specifically, since the structure of the function doesn't work
1878 for them without major modification. Do it better when we learn
1879 this port about the general inc/dec addressing of PA.
1880 (This was written by tege. Chide him if it doesn't work.) */
1882 if (optype0 == MEMOP)
1884 /* We have to output the address syntax ourselves, since print_operand
1885 doesn't deal with the addresses we want to use. Fix this later. */
1887 rtx addr = XEXP (operands[0], 0);
1888 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1890 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1892 operands[0] = XEXP (addr, 0);
1893 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1896 if (!reg_overlap_mentioned_p (high_reg, addr))
1898 /* No overlap between high target register and address
1899 register. (We do this in a non-obvious way to
1900 save a register file writeback) */
1901 if (GET_CODE (addr) == POST_INC)
1902 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
1903 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
1908 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1910 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1912 operands[0] = XEXP (addr, 0);
1913 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1916 if (!reg_overlap_mentioned_p (high_reg, addr))
1918 /* No overlap between high target register and address
1919 register. (We do this in a non-obvious way to
1920 save a register file writeback) */
1921 if (GET_CODE (addr) == PRE_INC)
1922 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
1923 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
1929 if (optype1 == MEMOP)
1931 /* We have to output the address syntax ourselves, since print_operand
1932 doesn't deal with the addresses we want to use. Fix this later. */
1934 rtx addr = XEXP (operands[1], 0);
1935 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1937 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1939 operands[1] = XEXP (addr, 0);
1940 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1943 if (!reg_overlap_mentioned_p (high_reg, addr))
1945 /* No overlap between high target register and address
1946 register. (We do this in a non-obvious way to
1947 save a register file writeback) */
1948 if (GET_CODE (addr) == POST_INC)
1949 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
1950 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0}";
1954 /* This is an undefined situation. We should load into the
1955 address register *and* update that register. Probably
1956 we don't need to handle this at all. */
1957 if (GET_CODE (addr) == POST_INC)
1958 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
1959 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
1962 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1964 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1966 operands[1] = XEXP (addr, 0);
1967 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1970 if (!reg_overlap_mentioned_p (high_reg, addr))
1972 /* No overlap between high target register and address
1973 register. (We do this in a non-obvious way to
1974 save a register file writeback) */
1975 if (GET_CODE (addr) == PRE_INC)
1976 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
1977 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
1981 /* This is an undefined situation. We should load into the
1982 address register *and* update that register. Probably
1983 we don't need to handle this at all. */
1984 if (GET_CODE (addr) == PRE_INC)
1985 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
1986 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
1989 else if (GET_CODE (addr) == PLUS
1990 && GET_CODE (XEXP (addr, 0)) == MULT)
1992 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1994 if (!reg_overlap_mentioned_p (high_reg, addr))
1998 xoperands[0] = high_reg;
1999 xoperands[1] = XEXP (addr, 1);
2000 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2001 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2002 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2004 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2010 xoperands[0] = high_reg;
2011 xoperands[1] = XEXP (addr, 1);
2012 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2013 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2014 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2016 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2021 /* If an operand is an unoffsettable memory ref, find a register
2022 we can increment temporarily to make it refer to the second word. */
2024 if (optype0 == MEMOP)
2025 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2027 if (optype1 == MEMOP)
2028 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2030 /* Ok, we can do one word at a time.
2031 Normally we do the low-numbered word first.
2033 In either case, set up in LATEHALF the operands to use
2034 for the high-numbered word and in some cases alter the
2035 operands in OPERANDS to be suitable for the low-numbered word. */
2037 if (optype0 == REGOP)
2038 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2039 else if (optype0 == OFFSOP)
2040 latehalf[0] = adj_offsettable_operand (operands[0], 4);
2042 latehalf[0] = operands[0];
2044 if (optype1 == REGOP)
2045 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2046 else if (optype1 == OFFSOP)
2047 latehalf[1] = adj_offsettable_operand (operands[1], 4);
2048 else if (optype1 == CNSTOP)
2049 split_double (operands[1], &operands[1], &latehalf[1]);
2051 latehalf[1] = operands[1];
2053 /* If the first move would clobber the source of the second one,
2054 do them in the other order.
2056 This can happen in two cases:
2058 mem -> register where the first half of the destination register
2059 is the same register used in the memory's address. Reload
2060 can create such insns.
2062 mem in this case will be either register indirect or register
2063 indirect plus a valid offset.
2065 register -> register move where REGNO(dst) == REGNO(src + 1)
2066 someone (Tim/Tege?) claimed this can happen for parameter loads.
2068 Handle mem -> register case first. */
2069 if (optype0 == REGOP
2070 && (optype1 == MEMOP || optype1 == OFFSOP)
2071 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2074 /* Do the late half first. */
2076 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2077 output_asm_insn (singlemove_string (latehalf), latehalf);
2081 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2082 return singlemove_string (operands);
2085 /* Now handle register -> register case. */
2086 if (optype0 == REGOP && optype1 == REGOP
2087 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2089 output_asm_insn (singlemove_string (latehalf), latehalf);
2090 return singlemove_string (operands);
2093 /* Normal case: do the two words, low-numbered first. */
2095 output_asm_insn (singlemove_string (operands), operands);
2097 /* Make any unoffsettable addresses point at high-numbered word. */
2099 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2101 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2104 output_asm_insn (singlemove_string (latehalf), latehalf);
2106 /* Undo the adds we just did. */
2108 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2110 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2116 output_fp_move_double (operands)
2119 if (FP_REG_P (operands[0]))
2121 if (FP_REG_P (operands[1])
2122 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2123 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2125 output_asm_insn ("fldd%F1 %1,%0", operands);
2127 else if (FP_REG_P (operands[1]))
2129 output_asm_insn ("fstd%F0 %1,%0", operands);
2131 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2133 if (GET_CODE (operands[0]) == REG)
2136 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2137 xoperands[0] = operands[0];
2138 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2140 /* This is a pain. You have to be prepared to deal with an
2141 arbitrary address here including pre/post increment/decrement.
2143 so avoid this in the MD. */
2151 /* Return a REG that occurs in ADDR with coefficient 1.
2152 ADDR can be effectively incremented by incrementing REG. */
2155 find_addr_reg (addr)
2158 while (GET_CODE (addr) == PLUS)
2160 if (GET_CODE (XEXP (addr, 0)) == REG)
2161 addr = XEXP (addr, 0);
2162 else if (GET_CODE (XEXP (addr, 1)) == REG)
2163 addr = XEXP (addr, 1);
2164 else if (CONSTANT_P (XEXP (addr, 0)))
2165 addr = XEXP (addr, 1);
2166 else if (CONSTANT_P (XEXP (addr, 1)))
2167 addr = XEXP (addr, 0);
2171 if (GET_CODE (addr) == REG)
2176 /* Emit code to perform a block move.
2178 OPERANDS[0] is the destination pointer as a REG, clobbered.
2179 OPERANDS[1] is the source pointer as a REG, clobbered.
2180 OPERANDS[2] is a register for temporary storage.
2181 OPERANDS[4] is the size as a CONST_INT
2182 OPERANDS[3] is a register for temporary storage.
2183 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2184 OPERANDS[6] is another temporary register. */
2187 output_block_move (operands, size_is_constant)
2189 int size_is_constant ATTRIBUTE_UNUSED;
2191 int align = INTVAL (operands[5]);
2192 unsigned long n_bytes = INTVAL (operands[4]);
2194 /* We can't move more than four bytes at a time because the PA
2195 has no longer integer move insns. (Could use fp mem ops?) */
2199 /* Note that we know each loop below will execute at least twice
2200 (else we would have open-coded the copy). */
2204 /* Pre-adjust the loop counter. */
2205 operands[4] = GEN_INT (n_bytes - 8);
2206 output_asm_insn ("ldi %4,%2", operands);
2209 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2210 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2211 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2212 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2213 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2215 /* Handle the residual. There could be up to 7 bytes of
2216 residual to copy! */
2217 if (n_bytes % 8 != 0)
2219 operands[4] = GEN_INT (n_bytes % 4);
2220 if (n_bytes % 8 >= 4)
2221 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2222 if (n_bytes % 4 != 0)
2223 output_asm_insn ("ldw 0(%1),%6", operands);
2224 if (n_bytes % 8 >= 4)
2225 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2226 if (n_bytes % 4 != 0)
2227 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2232 /* Pre-adjust the loop counter. */
2233 operands[4] = GEN_INT (n_bytes - 4);
2234 output_asm_insn ("ldi %4,%2", operands);
2237 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2238 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2239 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2240 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2241 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2243 /* Handle the residual. */
2244 if (n_bytes % 4 != 0)
2246 if (n_bytes % 4 >= 2)
2247 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2248 if (n_bytes % 2 != 0)
2249 output_asm_insn ("ldb 0(%1),%6", operands);
2250 if (n_bytes % 4 >= 2)
2251 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2252 if (n_bytes % 2 != 0)
2253 output_asm_insn ("stb %6,0(%0)", operands);
2258 /* Pre-adjust the loop counter. */
2259 operands[4] = GEN_INT (n_bytes - 2);
2260 output_asm_insn ("ldi %4,%2", operands);
2263 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2264 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2265 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2266 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2267 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2269 /* Handle the residual. */
2270 if (n_bytes % 2 != 0)
2272 output_asm_insn ("ldb 0(%1),%3", operands);
2273 output_asm_insn ("stb %3,0(%0)", operands);
2282 /* Count the number of insns necessary to handle this block move.
2284 Basic structure is the same as emit_block_move, except that we
2285 count insns rather than emit them. */
2288 compute_movstrsi_length (insn)
2291 rtx pat = PATTERN (insn);
2292 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2293 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
2294 unsigned int n_insns = 0;
2296 /* We can't move more than four bytes at a time because the PA
2297 has no longer integer move insns. (Could use fp mem ops?) */
2301 /* The basic copying loop. */
2305 if (n_bytes % (2 * align) != 0)
2307 if ((n_bytes % (2 * align)) >= align)
2310 if ((n_bytes % align) != 0)
2314 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2320 output_and (operands)
2323 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2325 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2326 int ls0, ls1, ms0, p, len;
2328 for (ls0 = 0; ls0 < 32; ls0++)
2329 if ((mask & (1 << ls0)) == 0)
2332 for (ls1 = ls0; ls1 < 32; ls1++)
2333 if ((mask & (1 << ls1)) != 0)
2336 for (ms0 = ls1; ms0 < 32; ms0++)
2337 if ((mask & (1 << ms0)) == 0)
2350 operands[2] = GEN_INT (len);
2351 return "{extru|extrw,u} %1,31,%2,%0";
2355 /* We could use this `depi' for the case above as well, but `depi'
2356 requires one more register file access than an `extru'. */
2361 operands[2] = GEN_INT (p);
2362 operands[3] = GEN_INT (len);
2363 return "{depi|depwi} 0,%2,%3,%0";
2367 return "and %1,%2,%0";
2370 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2371 storing the result in operands[0]. */
2373 output_64bit_and (operands)
2376 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2378 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2379 int ls0, ls1, ms0, p, len;
2381 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2382 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2385 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2386 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2389 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2390 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2393 if (ms0 != HOST_BITS_PER_WIDE_INT)
2396 if (ls1 == HOST_BITS_PER_WIDE_INT)
2403 operands[2] = GEN_INT (len);
2404 return "extrd,u %1,63,%2,%0";
2408 /* We could use this `depi' for the case above as well, but `depi'
2409 requires one more register file access than an `extru'. */
2414 operands[2] = GEN_INT (p);
2415 operands[3] = GEN_INT (len);
2416 return "depdi 0,%2,%3,%0";
2420 return "and %1,%2,%0";
2424 output_ior (operands)
2427 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2428 int bs0, bs1, p, len;
2430 if (INTVAL (operands[2]) == 0)
2431 return "copy %1,%0";
2433 for (bs0 = 0; bs0 < 32; bs0++)
2434 if ((mask & (1 << bs0)) != 0)
2437 for (bs1 = bs0; bs1 < 32; bs1++)
2438 if ((mask & (1 << bs1)) == 0)
2441 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2447 operands[2] = GEN_INT (p);
2448 operands[3] = GEN_INT (len);
2449 return "{depi|depwi} -1,%2,%3,%0";
2452 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2453 storing the result in operands[0]. */
2455 output_64bit_ior (operands)
2458 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2459 int bs0, bs1, p, len;
2461 if (INTVAL (operands[2]) == 0)
2462 return "copy %1,%0";
2464 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2465 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2468 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2469 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2472 if (bs1 != HOST_BITS_PER_WIDE_INT
2473 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2479 operands[2] = GEN_INT (p);
2480 operands[3] = GEN_INT (len);
2481 return "depdi -1,%2,%3,%0";
2484 /* Output an ascii string. */
2486 output_ascii (file, p, size)
2488 const unsigned char *p;
2493 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2495 /* The HP assembler can only take strings of 256 characters at one
2496 time. This is a limitation on input line length, *not* the
2497 length of the string. Sigh. Even worse, it seems that the
2498 restriction is in number of input characters (see \xnn &
2499 \whatever). So we have to do this very carefully. */
2501 fputs ("\t.STRING \"", file);
2504 for (i = 0; i < size; i += 4)
2508 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2510 register unsigned int c = p[i + io];
2512 if (c == '\"' || c == '\\')
2513 partial_output[co++] = '\\';
2514 if (c >= ' ' && c < 0177)
2515 partial_output[co++] = c;
2519 partial_output[co++] = '\\';
2520 partial_output[co++] = 'x';
2521 hexd = c / 16 - 0 + '0';
2523 hexd -= '9' - 'a' + 1;
2524 partial_output[co++] = hexd;
2525 hexd = c % 16 - 0 + '0';
2527 hexd -= '9' - 'a' + 1;
2528 partial_output[co++] = hexd;
2531 if (chars_output + co > 243)
2533 fputs ("\"\n\t.STRING \"", file);
2536 fwrite (partial_output, 1, co, file);
2540 fputs ("\"\n", file);
2543 /* Try to rewrite floating point comparisons & branches to avoid
2544 useless add,tr insns.
2546 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2547 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2548 first attempt to remove useless add,tr insns. It is zero
2549 for the second pass as reorg sometimes leaves bogus REG_DEAD
2552 When CHECK_NOTES is zero we can only eliminate add,tr insns
2553 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2556 remove_useless_addtr_insns (insns, check_notes)
2561 static int pass = 0;
2563 /* This is fairly cheap, so always run it when optimizing. */
2567 int fbranch_count = 0;
2569 /* Walk all the insns in this function looking for fcmp & fbranch
2570 instructions. Keep track of how many of each we find. */
2571 insns = get_insns ();
2572 for (insn = insns; insn; insn = next_insn (insn))
2576 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2577 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2580 tmp = PATTERN (insn);
2582 /* It must be a set. */
2583 if (GET_CODE (tmp) != SET)
2586 /* If the destination is CCFP, then we've found an fcmp insn. */
2587 tmp = SET_DEST (tmp);
2588 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2594 tmp = PATTERN (insn);
2595 /* If this is an fbranch instruction, bump the fbranch counter. */
2596 if (GET_CODE (tmp) == SET
2597 && SET_DEST (tmp) == pc_rtx
2598 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2599 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2600 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2601 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2609 /* Find all floating point compare + branch insns. If possible,
2610 reverse the comparison & the branch to avoid add,tr insns. */
2611 for (insn = insns; insn; insn = next_insn (insn))
2615 /* Ignore anything that isn't an INSN. */
2616 if (GET_CODE (insn) != INSN)
2619 tmp = PATTERN (insn);
2621 /* It must be a set. */
2622 if (GET_CODE (tmp) != SET)
2625 /* The destination must be CCFP, which is register zero. */
2626 tmp = SET_DEST (tmp);
2627 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2630 /* INSN should be a set of CCFP.
2632 See if the result of this insn is used in a reversed FP
2633 conditional branch. If so, reverse our condition and
2634 the branch. Doing so avoids useless add,tr insns. */
2635 next = next_insn (insn);
2638 /* Jumps, calls and labels stop our search. */
2639 if (GET_CODE (next) == JUMP_INSN
2640 || GET_CODE (next) == CALL_INSN
2641 || GET_CODE (next) == CODE_LABEL)
2644 /* As does another fcmp insn. */
2645 if (GET_CODE (next) == INSN
2646 && GET_CODE (PATTERN (next)) == SET
2647 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2648 && REGNO (SET_DEST (PATTERN (next))) == 0)
2651 next = next_insn (next);
2654 /* Is NEXT_INSN a branch? */
2656 && GET_CODE (next) == JUMP_INSN)
2658 rtx pattern = PATTERN (next);
2660 /* If it a reversed fp conditional branch (eg uses add,tr)
2661 and CCFP dies, then reverse our conditional and the branch
2662 to avoid the add,tr. */
2663 if (GET_CODE (pattern) == SET
2664 && SET_DEST (pattern) == pc_rtx
2665 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2666 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2667 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2668 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2669 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2670 && (fcmp_count == fbranch_count
2672 && find_regno_note (next, REG_DEAD, 0))))
2674 /* Reverse the branch. */
2675 tmp = XEXP (SET_SRC (pattern), 1);
2676 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2677 XEXP (SET_SRC (pattern), 2) = tmp;
2678 INSN_CODE (next) = -1;
2680 /* Reverse our condition. */
2681 tmp = PATTERN (insn);
2682 PUT_CODE (XEXP (tmp, 1),
2683 (reverse_condition_maybe_unordered
2684 (GET_CODE (XEXP (tmp, 1)))));
2694 /* You may have trouble believing this, but this is the 32 bit HP-PA
2699 Variable arguments (optional; any number may be allocated)
2701 SP-(4*(N+9)) arg word N
2706 Fixed arguments (must be allocated; may remain unused)
2715 SP-32 External Data Pointer (DP)
2717 SP-24 External/stub RP (RP')
2721 SP-8 Calling Stub RP (RP'')
2726 SP-0 Stack Pointer (points to next available address)
2730 /* This function saves registers as follows. Registers marked with ' are
2731 this function's registers (as opposed to the previous function's).
2732 If a frame_pointer isn't needed, r4 is saved as a general register;
2733 the space for the frame pointer is still allocated, though, to keep
2739 SP (FP') Previous FP
2740 SP + 4 Alignment filler (sigh)
2741 SP + 8 Space for locals reserved here.
2745 SP + n All call saved register used.
2749 SP + o All call saved fp registers used.
2753 SP + p (SP') points to next available address.
2757 /* Global variables set by FUNCTION_PROLOGUE. */
2758 /* Size of frame. Need to know this to emit return insns from
2760 static int actual_fsize;
2761 static int local_fsize, save_fregs;
2763 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2764 Handle case where DISP > 8k by using the add_high_const patterns.
2766 Note in DISP > 8k case, we will leave the high part of the address
2767 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2770 store_reg (reg, disp, base)
2771 int reg, disp, base;
2773 rtx i, dest, src, basereg;
2775 src = gen_rtx_REG (word_mode, reg);
2776 basereg = gen_rtx_REG (Pmode, base);
2777 if (VAL_14_BITS_P (disp))
2779 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2780 i = emit_move_insn (dest, src);
2784 rtx delta = GEN_INT (disp);
2785 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
2786 rtx tmpreg = gen_rtx_REG (Pmode, 1);
2787 emit_move_insn (tmpreg, high);
2788 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
2789 i = emit_move_insn (dest, src);
2794 /* Emit RTL to set REG to the value specified by BASE+DISP.
2795 Handle case where DISP > 8k by using the add_high_const patterns.
2797 Note in DISP > 8k case, we will leave the high part of the address
2798 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2801 set_reg_plus_d (reg, base, disp)
2802 int reg, base, disp;
2806 if (VAL_14_BITS_P (disp))
2808 i = emit_move_insn (gen_rtx_REG (Pmode, reg),
2809 plus_constant (gen_rtx_REG (Pmode, base), disp));
2813 rtx delta = GEN_INT (disp);
2814 emit_move_insn (gen_rtx_REG (Pmode, 1),
2815 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, base),
2816 gen_rtx_HIGH (Pmode, delta)));
2817 i = emit_move_insn (gen_rtx_REG (Pmode, reg),
2818 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
2825 compute_frame_size (size, fregs_live)
2831 /* Space for frame pointer + filler. If any frame is allocated
2832 we need to add this in because of STARTING_FRAME_OFFSET.
2834 Similar code also appears in hppa_expand_prologue. Change both
2835 of them at the same time. */
2836 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
2838 /* Account for space used by the callee general register saves. */
2839 for (i = 18; i >= 3; i--)
2840 if (regs_ever_live[i])
2841 fsize += UNITS_PER_WORD;
2843 /* Round the stack. */
2844 fsize = (fsize + 7) & ~7;
2846 /* Account for space used by the callee floating point register saves. */
2847 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
2848 if (regs_ever_live[i]
2849 || (! TARGET_64BIT && regs_ever_live[i + 1]))
2854 /* We always save both halves of the FP register, so always
2855 increment the frame size by 8 bytes. */
2859 /* The various ABIs include space for the outgoing parameters in the
2860 size of the current function's stack frame. */
2861 fsize += current_function_outgoing_args_size;
2863 /* Allocate space for the fixed frame marker. This space must be
2864 allocated for any function that makes calls or otherwise allocates
2866 if (!current_function_is_leaf || fsize)
2869 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
2873 output_function_prologue (file, size)
2875 int size ATTRIBUTE_UNUSED;
2877 /* The function's label and associated .PROC must never be
2878 separated and must be output *after* any profiling declarations
2879 to avoid changing spaces/subspaces within a procedure. */
2880 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
2881 fputs ("\t.PROC\n", file);
2883 /* hppa_expand_prologue does the dirty work now. We just need
2884 to output the assembler directives which denote the start
2886 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
2887 if (regs_ever_live[2])
2888 fputs (",CALLS,SAVE_RP", file);
2890 fputs (",NO_CALLS", file);
2892 if (frame_pointer_needed)
2893 fputs (",SAVE_SP", file);
2895 /* Pass on information about the number of callee register saves
2896 performed in the prologue.
2898 The compiler is supposed to pass the highest register number
2899 saved, the assembler then has to adjust that number before
2900 entering it into the unwind descriptor (to account for any
2901 caller saved registers with lower register numbers than the
2902 first callee saved register). */
2904 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
2907 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
2909 fputs ("\n\t.ENTRY\n", file);
2911 /* If we're using GAS and not using the portable runtime model, then
2912 we don't need to accumulate the total number of code bytes. */
2913 if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
2914 total_code_bytes = 0;
2915 else if (INSN_ADDRESSES_SET_P ())
2917 unsigned int old_total = total_code_bytes;
2919 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_insn ()));
2920 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
2922 /* Be prepared to handle overflows. */
2923 total_code_bytes = old_total > total_code_bytes ? -1 : total_code_bytes;
2926 total_code_bytes = -1;
2928 remove_useless_addtr_insns (get_insns (), 0);
2936 RTX_FRAME_RELATED_P (insn) = 1; \
2940 #define FRP (INSN) INSN
2944 hppa_expand_prologue ()
2946 extern char call_used_regs[];
2947 int size = get_frame_size ();
2948 int merge_sp_adjust_with_store = 0;
2950 rtx tmpreg, size_rtx;
2956 /* Allocate space for frame pointer + filler. If any frame is allocated
2957 we need to add this in because of STARTING_FRAME_OFFSET.
2959 Similar code also appears in compute_frame_size. Change both
2960 of them at the same time. */
2961 local_fsize = size + (size || frame_pointer_needed
2962 ? STARTING_FRAME_OFFSET : 0);
2964 actual_fsize = compute_frame_size (size, &save_fregs);
2966 /* Compute a few things we will use often. */
2967 tmpreg = gen_rtx_REG (word_mode, 1);
2968 size_rtx = GEN_INT (actual_fsize);
2970 /* Save RP first. The calling conventions manual states RP will
2971 always be stored into the caller's frame at sp - 20 or sp - 16
2972 depending on which ABI is in use. */
2973 if (regs_ever_live[2])
2974 FRP (store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM));
2976 /* Allocate the local frame and set up the frame pointer if needed. */
2977 if (actual_fsize != 0)
2979 if (frame_pointer_needed)
2981 /* Copy the old frame pointer temporarily into %r1. Set up the
2982 new stack pointer, then store away the saved old frame pointer
2983 into the stack at sp+actual_fsize and at the same time update
2984 the stack pointer by actual_fsize bytes. Two versions, first
2985 handles small (<8k) frames. The second handles large (>=8k)
2987 emit_move_insn (tmpreg, frame_pointer_rtx);
2988 FRP (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx));
2989 if (VAL_14_BITS_P (actual_fsize))
2991 rtx insn = emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
2996 RTX_FRAME_RELATED_P (insn) = 1;
2998 gen_rtx_SET (VOIDmode,
2999 gen_rtx_MEM (word_mode,
3002 gen_rtx_SET (VOIDmode,
3004 gen_rtx_PLUS (word_mode,
3008 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3009 gen_rtx_SEQUENCE (VOIDmode, vec),
3015 /* It is incorrect to store the saved frame pointer at *sp,
3016 then increment sp (writes beyond the current stack boundary).
3018 So instead use stwm to store at *sp and post-increment the
3019 stack pointer as an atomic operation. Then increment sp to
3020 finish allocating the new frame. */
3021 int adjust1 = 8192 - 64;
3022 int adjust2 = actual_fsize - adjust1;
3023 rtx delta = GEN_INT (adjust1);
3024 rtx insn = emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
3029 RTX_FRAME_RELATED_P (insn) = 1;
3031 gen_rtx_SET (VOIDmode,
3032 gen_rtx_MEM (word_mode,
3035 gen_rtx_SET (VOIDmode,
3037 gen_rtx_PLUS (word_mode,
3041 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3042 gen_rtx_SEQUENCE (VOIDmode, vec),
3046 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3047 STACK_POINTER_REGNUM,
3050 /* Prevent register spills from being scheduled before the
3051 stack pointer is raised. Necessary as we will be storing
3052 registers using the frame pointer as a base register, and
3053 we happen to set fp before raising sp. */
3054 emit_insn (gen_blockage ());
3056 /* no frame pointer needed. */
3059 /* In some cases we can perform the first callee register save
3060 and allocating the stack frame at the same time. If so, just
3061 make a note of it and defer allocating the frame until saving
3062 the callee registers. */
3063 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3064 merge_sp_adjust_with_store = 1;
3065 /* Can not optimize. Adjust the stack frame by actual_fsize
3068 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3069 STACK_POINTER_REGNUM,
3074 /* Normal register save.
3076 Do not save the frame pointer in the frame_pointer_needed case. It
3077 was done earlier. */
3078 if (frame_pointer_needed)
3080 for (i = 18, offset = local_fsize; i >= 4; i--)
3081 if (regs_ever_live[i] && ! call_used_regs[i])
3083 FRP (store_reg (i, offset, FRAME_POINTER_REGNUM));
3084 offset += UNITS_PER_WORD;
3087 /* Account for %r3 which is saved in a special place. */
3090 /* No frame pointer needed. */
3093 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3094 if (regs_ever_live[i] && ! call_used_regs[i])
3096 /* If merge_sp_adjust_with_store is nonzero, then we can
3097 optimize the first GR save. */
3098 if (merge_sp_adjust_with_store)
3100 rtx delta = GEN_INT (-offset);
3101 merge_sp_adjust_with_store = 0;
3102 FRP (emit_insn (gen_post_store (stack_pointer_rtx,
3103 gen_rtx_REG (word_mode, i),
3107 FRP (store_reg (i, offset, STACK_POINTER_REGNUM));
3108 offset += UNITS_PER_WORD;
3112 /* If we wanted to merge the SP adjustment with a GR save, but we never
3113 did any GR saves, then just emit the adjustment here. */
3114 if (merge_sp_adjust_with_store)
3115 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3116 STACK_POINTER_REGNUM,
3120 /* The hppa calling conventions say that %r19, the pic offset
3121 register, is saved at sp - 32 (in this function's frame)
3122 when generating PIC code. FIXME: What is the correct thing
3123 to do for functions which make no calls and allocate no
3124 frame? Do we need to allocate a frame, or can we just omit
3125 the save? For now we'll just omit the save. */
3126 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3127 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3129 /* Align pointer properly (doubleword boundary). */
3130 offset = (offset + 7) & ~7;
3132 /* Floating point register store. */
3135 /* First get the frame or stack pointer to the start of the FP register
3137 if (frame_pointer_needed)
3138 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset));
3140 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM, offset));
3142 /* Now actually save the FP registers. */
3143 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3145 if (regs_ever_live[i]
3146 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3149 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3150 reg = gen_rtx_REG (DFmode, i);
3151 FRP (emit_move_insn (addr, reg));
3158 /* ?!? Do we want frame notes in the epilogue yet? */
3159 #undef DO_FRAME_NOTES
3160 #define DO_FRAME_NOTES 0
3162 #define FRP(INSN) INSN
3164 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3165 Handle case where DISP > 8k by using the add_high_const patterns. */
3168 load_reg (reg, disp, base)
3169 int reg, disp, base;
3171 rtx i, src, dest, basereg;
3173 dest = gen_rtx_REG (word_mode, reg);
3174 basereg = gen_rtx_REG (Pmode, base);
3175 if (VAL_14_BITS_P (disp))
3177 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3178 i = emit_move_insn (dest, src);
3182 rtx delta = GEN_INT (disp);
3183 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3184 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3185 emit_move_insn (tmpreg, high);
3186 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3187 i = emit_move_insn (dest, src);
3193 output_function_epilogue (file, size)
3195 int size ATTRIBUTE_UNUSED;
3197 rtx insn = get_last_insn ();
3199 /* hppa_expand_epilogue does the dirty work now. We just need
3200 to output the assembler directives which denote the end
3203 To make debuggers happy, emit a nop if the epilogue was completely
3204 eliminated due to a volatile call as the last insn in the
3205 current function. That way the return address (in %r2) will
3206 always point to a valid instruction in the current function. */
3208 /* Get the last real insn. */
3209 if (GET_CODE (insn) == NOTE)
3210 insn = prev_real_insn (insn);
3212 /* If it is a sequence, then look inside. */
3213 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3214 insn = XVECEXP (PATTERN (insn), 0, 0);
3216 /* If insn is a CALL_INSN, then it must be a call to a volatile
3217 function (otherwise there would be epilogue insns). */
3218 if (insn && GET_CODE (insn) == CALL_INSN)
3219 fputs ("\tnop\n", file);
3221 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3225 hppa_expand_epilogue ()
3229 int merge_sp_adjust_with_load = 0;
3232 /* We will use this often. */
3233 tmpreg = gen_rtx_REG (word_mode, 1);
3235 /* Try to restore RP early to avoid load/use interlocks when
3236 RP gets used in the return (bv) instruction. This appears to still
3237 be necessary even when we schedule the prologue and epilogue. */
3238 if (regs_ever_live [2])
3240 ret_off = TARGET_64BIT ? -16 : -20;
3241 if (frame_pointer_needed)
3243 FRP (load_reg (2, ret_off, FRAME_POINTER_REGNUM));
3248 /* No frame pointer, and stack is smaller than 8k. */
3249 if (VAL_14_BITS_P (ret_off - actual_fsize))
3251 FRP (load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM));
3257 /* General register restores. */
3258 if (frame_pointer_needed)
3260 for (i = 18, offset = local_fsize; i >= 4; i--)
3261 if (regs_ever_live[i] && ! call_used_regs[i])
3263 FRP (load_reg (i, offset, FRAME_POINTER_REGNUM));
3264 offset += UNITS_PER_WORD;
3269 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3271 if (regs_ever_live[i] && ! call_used_regs[i])
3273 /* Only for the first load.
3274 merge_sp_adjust_with_load holds the register load
3275 with which we will merge the sp adjustment. */
3276 if (merge_sp_adjust_with_load == 0
3278 && VAL_14_BITS_P (-actual_fsize))
3279 merge_sp_adjust_with_load = i;
3281 FRP (load_reg (i, offset, STACK_POINTER_REGNUM));
3282 offset += UNITS_PER_WORD;
3287 /* Align pointer properly (doubleword boundary). */
3288 offset = (offset + 7) & ~7;
3290 /* FP register restores. */
3293 /* Adjust the register to index off of. */
3294 if (frame_pointer_needed)
3295 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset));
3297 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM, offset));
3299 /* Actually do the restores now. */
3300 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3301 if (regs_ever_live[i]
3302 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3304 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3305 rtx dest = gen_rtx_REG (DFmode, i);
3306 FRP (emit_move_insn (dest, src));
3310 /* Emit a blockage insn here to keep these insns from being moved to
3311 an earlier spot in the epilogue, or into the main instruction stream.
3313 This is necessary as we must not cut the stack back before all the
3314 restores are finished. */
3315 emit_insn (gen_blockage ());
3317 /* Reset stack pointer (and possibly frame pointer). The stack
3318 pointer is initially set to fp + 64 to avoid a race condition. */
3319 if (frame_pointer_needed)
3321 rtx delta = GEN_INT (-64);
3322 FRP (set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64));
3323 FRP (emit_insn (gen_pre_load (frame_pointer_rtx,
3327 /* If we were deferring a callee register restore, do it now. */
3328 else if (merge_sp_adjust_with_load)
3330 rtx delta = GEN_INT (-actual_fsize);
3331 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3332 FRP (emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)));
3334 else if (actual_fsize != 0)
3335 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3336 STACK_POINTER_REGNUM,
3339 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3340 frame greater than 8k), do so now. */
3342 FRP (load_reg (2, ret_off, STACK_POINTER_REGNUM));
3345 /* Set up a callee saved register for the pic offset table register. */
3347 hppa_init_pic_save ()
3351 picreg = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM);
3352 PIC_OFFSET_TABLE_SAVE_RTX = gen_reg_rtx (Pmode);
3353 RTX_UNCHANGING_P (PIC_OFFSET_TABLE_SAVE_RTX) = 1;
3354 insn = gen_rtx_SET (VOIDmode, PIC_OFFSET_TABLE_SAVE_RTX, picreg);
3356 /* Emit the insn at the beginning of the function after the prologue. */
3357 if (tail_recursion_reentry)
3358 emit_insn_before (insn, tail_recursion_reentry);
3360 /* We must have been called via PROFILE_HOOK. */
3365 hppa_profile_hook (label_no)
3366 int label_no ATTRIBUTE_UNUSED;
3370 /* No profiling for inline functions. We don't want extra calls to
3371 _mcount when the inline function is expanded. Even if that made
3372 sense, it wouldn't work here as there is no function label for
3373 the inline expansion. */
3374 if (DECL_INLINE (cfun->decl))
3378 emit_move_insn (arg_pointer_rtx,
3379 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3382 if (flag_pic && PIC_OFFSET_TABLE_SAVE_RTX == NULL_RTX)
3383 hppa_init_pic_save ();
3385 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3387 #ifndef NO_PROFILE_COUNTERS
3389 rtx count_label_rtx, addr, r24;
3390 char label_name[16];
3392 ASM_GENERATE_INTERNAL_LABEL (label_name, "LP", label_no);
3393 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (label_name));
3399 current_function_uses_pic_offset_table = 1;
3400 tmpreg = gen_rtx_REG (Pmode, 1);
3401 emit_move_insn (tmpreg,
3402 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3403 gen_rtx_HIGH (Pmode, count_label_rtx)));
3404 addr = gen_rtx_MEM (Pmode,
3405 gen_rtx_LO_SUM (Pmode, tmpreg, count_label_rtx));
3409 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3410 emit_move_insn (tmpreg, gen_rtx_HIGH (Pmode, count_label_rtx));
3411 addr = gen_rtx_LO_SUM (Pmode, tmpreg, count_label_rtx);
3413 r24 = gen_rtx_REG (Pmode, 24);
3414 emit_move_insn (r24, addr);
3416 /* %r25 is set from within the output pattern. */
3418 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3419 GEN_INT (TARGET_64BIT ? 24 : 12),
3420 XEXP (DECL_RTL (cfun->decl), 0)));
3422 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3425 /* %r25 is set from within the output pattern. */
3427 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3428 GEN_INT (TARGET_64BIT ? 16 : 8),
3429 XEXP (DECL_RTL (cfun->decl), 0)));
3432 /* Indicate the _mcount call cannot throw, nor will it execute a
3434 REG_NOTES (call_insn)
3435 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3439 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3441 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3443 emit_move_insn (pic_offset_table_rtx, PIC_OFFSET_TABLE_SAVE_RTX);
3447 /* Fetch the return address for the frame COUNT steps up from
3448 the current frame, after the prologue. FRAMEADDR is the
3449 frame pointer of the COUNT frame.
3451 We want to ignore any export stub remnants here.
3453 The value returned is used in two different ways:
3455 1. To find a function's caller.
3457 2. To change the return address for a function.
3459 This function handles most instances of case 1; however, it will
3460 fail if there are two levels of stubs to execute on the return
3461 path. The only way I believe that can happen is if the return value
3462 needs a parameter relocation, which never happens for C code.
3464 This function handles most instances of case 2; however, it will
3465 fail if we did not originally have stub code on the return path
3466 but will need code on the new return path. This can happen if
3467 the caller & callee are both in the main program, but the new
3468 return location is in a shared library.
3470 To handle this correctly we need to set the return pointer at
3471 frame-20 to point to a return stub frame-24 to point to the
3472 location we wish to return to. */
3475 return_addr_rtx (count, frameaddr)
3476 int count ATTRIBUTE_UNUSED;
3484 return gen_rtx_MEM (Pmode, plus_constant (frameaddr, -16));
3486 if (TARGET_NO_SPACE_REGS)
3487 return gen_rtx_MEM (Pmode, plus_constant (frameaddr, -20));
3489 /* First, we start off with the normal return address pointer from
3492 saved_rp = gen_reg_rtx (Pmode);
3493 emit_move_insn (saved_rp, plus_constant (frameaddr, -20));
3495 /* Get pointer to the instruction stream. We have to mask out the
3496 privilege level from the two low order bits of the return address
3497 pointer here so that ins will point to the start of the first
3498 instruction that would have been executed if we returned. */
3499 ins = copy_to_reg (gen_rtx_AND (Pmode,
3500 copy_to_reg (gen_rtx_MEM (Pmode, saved_rp)),
3502 label = gen_label_rtx ();
3504 /* Check the instruction stream at the normal return address for the
3507 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3508 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3509 0x00011820 | stub+16: mtsp r1,sr0
3510 0xe0400002 | stub+20: be,n 0(sr0,rp)
3512 If it is an export stub, than our return address is really in
3515 emit_cmp_insn (gen_rtx_MEM (SImode, ins),
3516 GEN_INT (0x4bc23fd1),
3517 NE, NULL_RTX, SImode, 1, 0);
3518 emit_jump_insn (gen_bne (label));
3520 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3521 GEN_INT (0x004010a1),
3522 NE, NULL_RTX, SImode, 1, 0);
3523 emit_jump_insn (gen_bne (label));
3525 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3526 GEN_INT (0x00011820),
3527 NE, NULL_RTX, SImode, 1, 0);
3528 emit_jump_insn (gen_bne (label));
3530 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3531 GEN_INT (0xe0400002),
3532 NE, NULL_RTX, SImode, 1, 0);
3534 /* If there is no export stub then just use our initial guess of
3537 emit_jump_insn (gen_bne (label));
3539 /* Here we know that our return address pointer points to an export
3540 stub. We don't want to return the address of the export stub,
3541 but rather the return address that leads back into user code.
3542 That return address is stored at -24[frameaddr]. */
3544 emit_move_insn (saved_rp, plus_constant (frameaddr, -24));
3547 return gen_rtx_MEM (Pmode, memory_address (Pmode, saved_rp));
3550 /* This is only valid once reload has completed because it depends on
3551 knowing exactly how much (if any) frame there is and...
3553 It's only valid if there is no frame marker to de-allocate and...
3555 It's only valid if %r2 hasn't been saved into the caller's frame
3556 (we're not profiling and %r2 isn't live anywhere). */
3558 hppa_can_use_return_insn_p ()
3560 return (reload_completed
3561 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3562 && ! regs_ever_live[2]
3563 && ! frame_pointer_needed);
3567 emit_bcond_fp (code, operand0)
3571 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3572 gen_rtx_IF_THEN_ELSE (VOIDmode,
3573 gen_rtx_fmt_ee (code,
3575 gen_rtx_REG (CCFPmode, 0),
3577 gen_rtx_LABEL_REF (VOIDmode, operand0),
3583 gen_cmp_fp (code, operand0, operand1)
3585 rtx operand0, operand1;
3587 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3588 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3591 /* Adjust the cost of a scheduling dependency. Return the new cost of
3592 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3595 pa_adjust_cost (insn, link, dep_insn, cost)
3601 enum attr_type attr_type;
3603 /* Don't adjust costs for a pa8000 chip. */
3604 if (pa_cpu >= PROCESSOR_8000)
3607 if (! recog_memoized (insn))
3610 attr_type = get_attr_type (insn);
3612 if (REG_NOTE_KIND (link) == 0)
3614 /* Data dependency; DEP_INSN writes a register that INSN reads some
3617 if (attr_type == TYPE_FPSTORE)
3619 rtx pat = PATTERN (insn);
3620 rtx dep_pat = PATTERN (dep_insn);
3621 if (GET_CODE (pat) == PARALLEL)
3623 /* This happens for the fstXs,mb patterns. */
3624 pat = XVECEXP (pat, 0, 0);
3626 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3627 /* If this happens, we have to extend this to schedule
3628 optimally. Return 0 for now. */
3631 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
3633 if (! recog_memoized (dep_insn))
3635 /* DEP_INSN is writing its result to the register
3636 being stored in the fpstore INSN. */
3637 switch (get_attr_type (dep_insn))
3640 /* This cost 3 cycles, not 2 as the md says for the
3649 case TYPE_FPSQRTSGL:
3650 case TYPE_FPSQRTDBL:
3651 /* In these important cases, we save one cycle compared to
3652 when flop instruction feed each other. */
3661 /* For other data dependencies, the default cost specified in the
3665 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3667 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3670 if (attr_type == TYPE_FPLOAD)
3672 rtx pat = PATTERN (insn);
3673 rtx dep_pat = PATTERN (dep_insn);
3674 if (GET_CODE (pat) == PARALLEL)
3676 /* This happens for the fldXs,mb patterns. */
3677 pat = XVECEXP (pat, 0, 0);
3679 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3680 /* If this happens, we have to extend this to schedule
3681 optimally. Return 0 for now. */
3684 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3686 if (! recog_memoized (dep_insn))
3688 switch (get_attr_type (dep_insn))
3695 case TYPE_FPSQRTSGL:
3696 case TYPE_FPSQRTDBL:
3697 /* A fpload can't be issued until one cycle before a
3698 preceding arithmetic operation has finished if
3699 the target of the fpload is any of the sources
3700 (or destination) of the arithmetic operation. */
3708 else if (attr_type == TYPE_FPALU)
3710 rtx pat = PATTERN (insn);
3711 rtx dep_pat = PATTERN (dep_insn);
3712 if (GET_CODE (pat) == PARALLEL)
3714 /* This happens for the fldXs,mb patterns. */
3715 pat = XVECEXP (pat, 0, 0);
3717 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3718 /* If this happens, we have to extend this to schedule
3719 optimally. Return 0 for now. */
3722 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3724 if (! recog_memoized (dep_insn))
3726 switch (get_attr_type (dep_insn))
3730 case TYPE_FPSQRTSGL:
3731 case TYPE_FPSQRTDBL:
3732 /* An ALU flop can't be issued until two cycles before a
3733 preceding divide or sqrt operation has finished if
3734 the target of the ALU flop is any of the sources
3735 (or destination) of the divide or sqrt operation. */
3744 /* For other anti dependencies, the cost is 0. */
3747 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3749 /* Output dependency; DEP_INSN writes a register that INSN writes some
3751 if (attr_type == TYPE_FPLOAD)
3753 rtx pat = PATTERN (insn);
3754 rtx dep_pat = PATTERN (dep_insn);
3755 if (GET_CODE (pat) == PARALLEL)
3757 /* This happens for the fldXs,mb patterns. */
3758 pat = XVECEXP (pat, 0, 0);
3760 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3761 /* If this happens, we have to extend this to schedule
3762 optimally. Return 0 for now. */
3765 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3767 if (! recog_memoized (dep_insn))
3769 switch (get_attr_type (dep_insn))
3776 case TYPE_FPSQRTSGL:
3777 case TYPE_FPSQRTDBL:
3778 /* A fpload can't be issued until one cycle before a
3779 preceding arithmetic operation has finished if
3780 the target of the fpload is the destination of the
3781 arithmetic operation. */
3789 else if (attr_type == TYPE_FPALU)
3791 rtx pat = PATTERN (insn);
3792 rtx dep_pat = PATTERN (dep_insn);
3793 if (GET_CODE (pat) == PARALLEL)
3795 /* This happens for the fldXs,mb patterns. */
3796 pat = XVECEXP (pat, 0, 0);
3798 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3799 /* If this happens, we have to extend this to schedule
3800 optimally. Return 0 for now. */
3803 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3805 if (! recog_memoized (dep_insn))
3807 switch (get_attr_type (dep_insn))
3811 case TYPE_FPSQRTSGL:
3812 case TYPE_FPSQRTDBL:
3813 /* An ALU flop can't be issued until two cycles before a
3814 preceding divide or sqrt operation has finished if
3815 the target of the ALU flop is also the target of
3816 the divide or sqrt operation. */
3825 /* For other output dependencies, the cost is 0. */
3832 /* Return any length adjustment needed by INSN which already has its length
3833 computed as LENGTH. Return zero if no adjustment is necessary.
3835 For the PA: function calls, millicode calls, and backwards short
3836 conditional branches with unfilled delay slots need an adjustment by +1
3837 (to account for the NOP which will be inserted into the instruction stream).
3839 Also compute the length of an inline block move here as it is too
3840 complicated to express as a length attribute in pa.md. */
3842 pa_adjust_insn_length (insn, length)
3846 rtx pat = PATTERN (insn);
3848 /* Call insns which are *not* indirect and have unfilled delay slots. */
3849 if (GET_CODE (insn) == CALL_INSN)
3852 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
3853 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
3855 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
3856 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
3862 /* Jumps inside switch tables which have unfilled delay slots
3863 also need adjustment. */
3864 else if (GET_CODE (insn) == JUMP_INSN
3865 && simplejump_p (insn)
3866 && GET_MODE (insn) == SImode)
3868 /* Millicode insn with an unfilled delay slot. */
3869 else if (GET_CODE (insn) == INSN
3870 && GET_CODE (pat) != SEQUENCE
3871 && GET_CODE (pat) != USE
3872 && GET_CODE (pat) != CLOBBER
3873 && get_attr_type (insn) == TYPE_MILLI)
3875 /* Block move pattern. */
3876 else if (GET_CODE (insn) == INSN
3877 && GET_CODE (pat) == PARALLEL
3878 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3879 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
3880 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
3881 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
3882 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
3883 return compute_movstrsi_length (insn) - 4;
3884 /* Conditional branch with an unfilled delay slot. */
3885 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
3887 /* Adjust a short backwards conditional with an unfilled delay slot. */
3888 if (GET_CODE (pat) == SET
3890 && ! forward_branch_p (insn))
3892 else if (GET_CODE (pat) == PARALLEL
3893 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
3896 /* Adjust dbra insn with short backwards conditional branch with
3897 unfilled delay slot -- only for case where counter is in a
3898 general register register. */
3899 else if (GET_CODE (pat) == PARALLEL
3900 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
3901 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
3902 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
3904 && ! forward_branch_p (insn))
3912 /* Print operand X (an rtx) in assembler syntax to file FILE.
3913 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3914 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3917 print_operand (file, x, code)
3925 /* Output a 'nop' if there's nothing for the delay slot. */
3926 if (dbr_sequence_length () == 0)
3927 fputs ("\n\tnop", file);
3930 /* Output an nullification completer if there's nothing for the */
3931 /* delay slot or nullification is requested. */
3932 if (dbr_sequence_length () == 0 ||
3934 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
3938 /* Print out the second register name of a register pair.
3939 I.e., R (6) => 7. */
3940 fputs (reg_names[REGNO (x) + 1], file);
3943 /* A register or zero. */
3945 || (x == CONST0_RTX (DFmode))
3946 || (x == CONST0_RTX (SFmode)))
3948 fputs ("%r0", file);
3954 /* A register or zero (floating point). */
3956 || (x == CONST0_RTX (DFmode))
3957 || (x == CONST0_RTX (SFmode)))
3959 fputs ("%fr0", file);
3968 xoperands[0] = XEXP (XEXP (x, 0), 0);
3969 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
3970 output_global_address (file, xoperands[1], 0);
3971 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
3975 case 'C': /* Plain (C)ondition */
3977 switch (GET_CODE (x))
3980 fputs ("=", file); break;
3982 fputs ("<>", file); break;
3984 fputs (">", file); break;
3986 fputs (">=", file); break;
3988 fputs (">>=", file); break;
3990 fputs (">>", file); break;
3992 fputs ("<", file); break;
3994 fputs ("<=", file); break;
3996 fputs ("<<=", file); break;
3998 fputs ("<<", file); break;
4003 case 'N': /* Condition, (N)egated */
4004 switch (GET_CODE (x))
4007 fputs ("<>", file); break;
4009 fputs ("=", file); break;
4011 fputs ("<=", file); break;
4013 fputs ("<", file); break;
4015 fputs ("<<", file); break;
4017 fputs ("<<=", file); break;
4019 fputs (">=", file); break;
4021 fputs (">", file); break;
4023 fputs (">>", file); break;
4025 fputs (">>=", file); break;
4030 /* For floating point comparisons. Note that the output
4031 predicates are the complement of the desired mode. */
4033 switch (GET_CODE (x))
4036 fputs ("!=", file); break;
4038 fputs ("=", file); break;
4040 fputs ("!>", file); break;
4042 fputs ("!>=", file); break;
4044 fputs ("!<", file); break;
4046 fputs ("!<=", file); break;
4048 fputs ("!<>", file); break;
4050 fputs (">", file); break;
4052 fputs (">=", file); break;
4054 fputs ("<", file); break;
4056 fputs ("<=", file); break;
4058 fputs ("<>", file); break;
4060 fputs ("<=>", file); break;
4062 fputs ("!<=>", file); break;
4067 case 'S': /* Condition, operands are (S)wapped. */
4068 switch (GET_CODE (x))
4071 fputs ("=", file); break;
4073 fputs ("<>", file); break;
4075 fputs ("<", file); break;
4077 fputs ("<=", file); break;
4079 fputs ("<<=", file); break;
4081 fputs ("<<", file); break;
4083 fputs (">", file); break;
4085 fputs (">=", file); break;
4087 fputs (">>=", file); break;
4089 fputs (">>", file); break;
4094 case 'B': /* Condition, (B)oth swapped and negate. */
4095 switch (GET_CODE (x))
4098 fputs ("<>", file); break;
4100 fputs ("=", file); break;
4102 fputs (">=", file); break;
4104 fputs (">", file); break;
4106 fputs (">>", file); break;
4108 fputs (">>=", file); break;
4110 fputs ("<=", file); break;
4112 fputs ("<", file); break;
4114 fputs ("<<", file); break;
4116 fputs ("<<=", file); break;
4122 if (GET_CODE (x) == CONST_INT)
4124 fprintf (file, "%d", ~INTVAL (x));
4129 if (GET_CODE (x) == CONST_INT)
4131 fprintf (file, "%d", 64 - (INTVAL (x) & 63));
4136 if (GET_CODE (x) == CONST_INT)
4138 fprintf (file, "%d", 32 - (INTVAL (x) & 31));
4143 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4145 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4150 if (GET_CODE (x) == CONST_INT)
4152 fprintf (file, "%d", 63 - (INTVAL (x) & 63));
4157 if (GET_CODE (x) == CONST_INT)
4159 fprintf (file, "%d", 31 - (INTVAL (x) & 31));
4164 if (GET_CODE (x) == CONST_INT)
4169 switch (GET_CODE (XEXP (x, 0)))
4173 if (ASSEMBLER_DIALECT == 0)
4174 fputs ("s,mb", file);
4176 fputs (",mb", file);
4180 if (ASSEMBLER_DIALECT == 0)
4181 fputs ("s,ma", file);
4183 fputs (",ma", file);
4186 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4187 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4189 if (ASSEMBLER_DIALECT == 0)
4190 fputs ("x,s", file);
4194 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4198 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4204 output_global_address (file, x, 0);
4207 output_global_address (file, x, 1);
4209 case 0: /* Don't do anything special */
4214 compute_zdepwi_operands (INTVAL (x), op);
4215 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4221 compute_zdepdi_operands (INTVAL (x), op);
4222 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4226 /* We can get here from a .vtable_inherit due to our
4227 CONSTANT_ADDRESS_P rejecting perfectly good constant
4233 if (GET_CODE (x) == REG)
4235 fputs (reg_names [REGNO (x)], file);
4236 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4242 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4243 && (REGNO (x) & 1) == 0)
4246 else if (GET_CODE (x) == MEM)
4248 int size = GET_MODE_SIZE (GET_MODE (x));
4249 rtx base = NULL_RTX;
4250 switch (GET_CODE (XEXP (x, 0)))
4254 base = XEXP (XEXP (x, 0), 0);
4255 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4259 base = XEXP (XEXP (x, 0), 0);
4260 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4263 if (GET_CODE (XEXP (x, 0)) == PLUS
4264 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4265 fprintf (file, "%s(%s)",
4266 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4267 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4268 else if (GET_CODE (XEXP (x, 0)) == PLUS
4269 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4270 fprintf (file, "%s(%s)",
4271 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4272 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4274 output_address (XEXP (x, 0));
4279 output_addr_const (file, x);
4282 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4285 output_global_address (file, x, round_constant)
4291 /* Imagine (high (const (plus ...))). */
4292 if (GET_CODE (x) == HIGH)
4295 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4296 assemble_name (file, XSTR (x, 0));
4297 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4299 assemble_name (file, XSTR (x, 0));
4300 fputs ("-$global$", file);
4302 else if (GET_CODE (x) == CONST)
4304 const char *sep = "";
4305 int offset = 0; /* assembler wants -$global$ at end */
4306 rtx base = NULL_RTX;
4308 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4310 base = XEXP (XEXP (x, 0), 0);
4311 output_addr_const (file, base);
4313 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4314 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4317 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4319 base = XEXP (XEXP (x, 0), 1);
4320 output_addr_const (file, base);
4322 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4323 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4326 /* How bogus. The compiler is apparently responsible for
4327 rounding the constant if it uses an LR field selector.
4329 The linker and/or assembler seem a better place since
4330 they have to do this kind of thing already.
4332 If we fail to do this, HP's optimizing linker may eliminate
4333 an addil, but not update the ldw/stw/ldo instruction that
4334 uses the result of the addil. */
4336 offset = ((offset + 0x1000) & ~0x1fff);
4338 if (GET_CODE (XEXP (x, 0)) == PLUS)
4348 else if (GET_CODE (XEXP (x, 0)) == MINUS
4349 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4353 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4354 fputs ("-$global$", file);
4356 fprintf (file, "%s%d", sep, offset);
4359 output_addr_const (file, x);
4363 output_deferred_plabels (file)
4367 /* If we have deferred plabels, then we need to switch into the data
4368 section and align it to a 4 byte boundary before we output the
4369 deferred plabels. */
4370 if (n_deferred_plabels)
4373 ASM_OUTPUT_ALIGN (file, 2);
4376 /* Now output the deferred plabels. */
4377 for (i = 0; i < n_deferred_plabels; i++)
4379 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4380 assemble_integer (gen_rtx_SYMBOL_REF (VOIDmode,
4381 deferred_plabels[i].name), 4, 1);
4385 /* HP's millicode routines mean something special to the assembler.
4386 Keep track of which ones we have used. */
4388 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
4389 static void import_milli PARAMS ((enum millicodes));
4390 static char imported[(int) end1000];
4391 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4392 static char import_string[] = ".IMPORT $$....,MILLICODE";
4393 #define MILLI_START 10
4397 enum millicodes code;
4399 char str[sizeof (import_string)];
4401 if (!imported[(int) code])
4403 imported[(int) code] = 1;
4404 strcpy (str, import_string);
4405 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4406 output_asm_insn (str, 0);
4410 /* The register constraints have put the operands and return value in
4411 the proper registers. */
4414 output_mul_insn (unsignedp, insn)
4415 int unsignedp ATTRIBUTE_UNUSED;
4418 import_milli (mulI);
4419 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4422 /* Emit the rtl for doing a division by a constant. */
4424 /* Do magic division millicodes exist for this value? */
4425 static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4428 /* We'll use an array to keep track of the magic millicodes and
4429 whether or not we've used them already. [n][0] is signed, [n][1] is
4432 static int div_milli[16][2];
4435 div_operand (op, mode)
4437 enum machine_mode mode;
4439 return (mode == SImode
4440 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4441 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4442 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4446 emit_hpdiv_const (operands, unsignedp)
4450 if (GET_CODE (operands[2]) == CONST_INT
4451 && INTVAL (operands[2]) > 0
4452 && INTVAL (operands[2]) < 16
4453 && magic_milli[INTVAL (operands[2])])
4455 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4458 (PARALLEL, VOIDmode,
4459 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4460 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4462 gen_rtx_REG (SImode, 26),
4464 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4465 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4466 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4467 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4468 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 31)))));
4469 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4476 output_div_insn (operands, unsignedp, insn)
4483 /* If the divisor is a constant, try to use one of the special
4485 if (GET_CODE (operands[0]) == CONST_INT)
4487 static char buf[100];
4488 divisor = INTVAL (operands[0]);
4489 if (!div_milli[divisor][unsignedp])
4491 div_milli[divisor][unsignedp] = 1;
4493 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4495 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4499 sprintf (buf, "$$divU_%d", INTVAL (operands[0]));
4500 return output_millicode_call (insn,
4501 gen_rtx_SYMBOL_REF (SImode, buf));
4505 sprintf (buf, "$$divI_%d", INTVAL (operands[0]));
4506 return output_millicode_call (insn,
4507 gen_rtx_SYMBOL_REF (SImode, buf));
4510 /* Divisor isn't a special constant. */
4515 import_milli (divU);
4516 return output_millicode_call (insn,
4517 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4521 import_milli (divI);
4522 return output_millicode_call (insn,
4523 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4528 /* Output a $$rem millicode to do mod. */
4531 output_mod_insn (unsignedp, insn)
4537 import_milli (remU);
4538 return output_millicode_call (insn,
4539 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4543 import_milli (remI);
4544 return output_millicode_call (insn,
4545 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4550 output_arg_descriptor (call_insn)
4553 const char *arg_regs[4];
4554 enum machine_mode arg_mode;
4556 int i, output_flag = 0;
4559 /* We neither need nor want argument location descriptors for the
4560 64bit runtime environment or the ELF32 environment. */
4561 if (TARGET_64BIT || TARGET_ELF32)
4564 for (i = 0; i < 4; i++)
4567 /* Specify explicitly that no argument relocations should take place
4568 if using the portable runtime calling conventions. */
4569 if (TARGET_PORTABLE_RUNTIME)
4571 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4576 if (GET_CODE (call_insn) != CALL_INSN)
4578 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4580 rtx use = XEXP (link, 0);
4582 if (! (GET_CODE (use) == USE
4583 && GET_CODE (XEXP (use, 0)) == REG
4584 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4587 arg_mode = GET_MODE (XEXP (use, 0));
4588 regno = REGNO (XEXP (use, 0));
4589 if (regno >= 23 && regno <= 26)
4591 arg_regs[26 - regno] = "GR";
4592 if (arg_mode == DImode)
4593 arg_regs[25 - regno] = "GR";
4595 else if (regno >= 32 && regno <= 39)
4597 if (arg_mode == SFmode)
4598 arg_regs[(regno - 32) / 2] = "FR";
4601 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4602 arg_regs[(regno - 34) / 2] = "FR";
4603 arg_regs[(regno - 34) / 2 + 1] = "FU";
4605 arg_regs[(regno - 34) / 2] = "FU";
4606 arg_regs[(regno - 34) / 2 + 1] = "FR";
4611 fputs ("\t.CALL ", asm_out_file);
4612 for (i = 0; i < 4; i++)
4617 fputc (',', asm_out_file);
4618 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4621 fputc ('\n', asm_out_file);
4624 /* Return the class of any secondary reload register that is needed to
4625 move IN into a register in class CLASS using mode MODE.
4627 Profiling has showed this routine and its descendants account for
4628 a significant amount of compile time (~7%). So it has been
4629 optimized to reduce redundant computations and eliminate useless
4632 It might be worthwhile to try and make this a leaf function too. */
4635 secondary_reload_class (class, mode, in)
4636 enum reg_class class;
4637 enum machine_mode mode;
4640 int regno, is_symbolic;
4642 /* Trying to load a constant into a FP register during PIC code
4643 generation will require %r1 as a scratch register. */
4645 && GET_MODE_CLASS (mode) == MODE_INT
4646 && FP_REG_CLASS_P (class)
4647 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4650 /* Profiling showed the PA port spends about 1.3% of its compilation
4651 time in true_regnum from calls inside secondary_reload_class. */
4653 if (GET_CODE (in) == REG)
4656 if (regno >= FIRST_PSEUDO_REGISTER)
4657 regno = true_regnum (in);
4659 else if (GET_CODE (in) == SUBREG)
4660 regno = true_regnum (in);
4664 /* If we have something like (mem (mem (...)), we can safely assume the
4665 inner MEM will end up in a general register after reloading, so there's
4666 no need for a secondary reload. */
4667 if (GET_CODE (in) == MEM
4668 && GET_CODE (XEXP (in, 0)) == MEM)
4671 /* Handle out of range displacement for integer mode loads/stores of
4673 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
4674 && GET_MODE_CLASS (mode) == MODE_INT
4675 && FP_REG_CLASS_P (class))
4676 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
4677 return GENERAL_REGS;
4679 if (GET_CODE (in) == HIGH)
4682 /* Profiling has showed GCC spends about 2.6% of its compilation
4683 time in symbolic_operand from calls inside secondary_reload_class.
4685 We use an inline copy and only compute its return value once to avoid
4687 switch (GET_CODE (in))
4697 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
4698 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
4699 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
4709 && read_only_operand (in, VOIDmode))
4712 if (class != R1_REGS && is_symbolic)
4719 function_arg_padding (mode, type)
4720 enum machine_mode mode;
4725 if (mode == BLKmode)
4727 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4728 size = int_size_in_bytes (type) * BITS_PER_UNIT;
4730 return upward; /* Don't know if this is right, but */
4731 /* same as old definition. */
4734 size = GET_MODE_BITSIZE (mode);
4735 if (size < PARM_BOUNDARY)
4737 else if (size % PARM_BOUNDARY)
4744 /* Do what is necessary for `va_start'. We look at the current function
4745 to determine if stdargs or varargs is used and fill in an initial
4746 va_list. A pointer to this constructor is returned. */
4749 hppa_builtin_saveregs ()
4752 tree fntype = TREE_TYPE (current_function_decl);
4753 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
4754 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4755 != void_type_node)))
4756 ? UNITS_PER_WORD : 0);
4759 offset = plus_constant (current_function_arg_offset_rtx, argadj);
4761 offset = current_function_arg_offset_rtx;
4767 /* Adjust for varargs/stdarg differences. */
4769 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
4771 offset = current_function_arg_offset_rtx;
4773 /* We need to save %r26 .. %r19 inclusive starting at offset -64
4774 from the incoming arg pointer and growing to larger addresses. */
4775 for (i = 26, off = -64; i >= 19; i--, off += 8)
4776 emit_move_insn (gen_rtx_MEM (word_mode,
4777 plus_constant (arg_pointer_rtx, off)),
4778 gen_rtx_REG (word_mode, i));
4780 /* The incoming args pointer points just beyond the flushback area;
4781 normally this is not a serious concern. Howver, when we are doing
4782 varargs/stdargs we want to make the arg pointer point to the start
4783 of the incoming argument area. */
4784 emit_move_insn (virtual_incoming_args_rtx,
4785 plus_constant (arg_pointer_rtx, -64));
4787 /* Now return a pointer to the first anonymous argument. */
4788 return copy_to_reg (expand_binop (Pmode, add_optab,
4789 virtual_incoming_args_rtx,
4790 offset, 0, 0, OPTAB_LIB_WIDEN));
4793 /* Store general registers on the stack. */
4794 dest = gen_rtx_MEM (BLKmode,
4795 plus_constant (current_function_internal_arg_pointer,
4797 MEM_ALIAS_SET (dest) = get_varargs_alias_set ();
4798 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
4800 /* move_block_from_reg will emit code to store the argument registers
4801 individually as scalar stores.
4803 However, other insns may later load from the same addresses for
4804 a structure load (passing a struct to a varargs routine).
4806 The alias code assumes that such aliasing can never happen, so we
4807 have to keep memory referencing insns from moving up beyond the
4808 last argument register store. So we emit a blockage insn here. */
4809 emit_insn (gen_blockage ());
4811 if (current_function_check_memory_usage)
4812 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4814 GEN_INT (4 * UNITS_PER_WORD), TYPE_MODE (sizetype),
4815 GEN_INT (MEMORY_USE_RW),
4816 TYPE_MODE (integer_type_node));
4818 return copy_to_reg (expand_binop (Pmode, add_optab,
4819 current_function_internal_arg_pointer,
4820 offset, 0, 0, OPTAB_LIB_WIDEN));
4824 hppa_va_start (stdarg_p, valist, nextarg)
4825 int stdarg_p ATTRIBUTE_UNUSED;
4829 nextarg = expand_builtin_saveregs ();
4830 std_expand_builtin_va_start (1, valist, nextarg);
4834 hppa_va_arg (valist, type)
4837 HOST_WIDE_INT align, size, ofs;
4842 /* Every argument in PA64 is passed by value (including large structs).
4843 Arguments with size greater than 8 must be aligned 0 MOD 16. */
4845 size = int_size_in_bytes (type);
4846 if (size > UNITS_PER_WORD)
4848 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4849 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4850 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4851 build_int_2 (-2 * UNITS_PER_WORD, -1));
4852 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4853 TREE_SIDE_EFFECTS (t) = 1;
4854 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4856 return std_expand_builtin_va_arg (valist, type);
4859 /* Compute the rounded size of the type. */
4860 align = PARM_BOUNDARY / BITS_PER_UNIT;
4861 size = int_size_in_bytes (type);
4863 ptr = build_pointer_type (type);
4865 /* "Large" types are passed by reference. */
4868 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
4869 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4870 TREE_SIDE_EFFECTS (t) = 1;
4872 pptr = build_pointer_type (ptr);
4873 t = build1 (NOP_EXPR, pptr, t);
4874 TREE_SIDE_EFFECTS (t) = 1;
4876 t = build1 (INDIRECT_REF, ptr, t);
4877 TREE_SIDE_EFFECTS (t) = 1;
4881 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4882 build_int_2 (-size, -1));
4884 /* Copied from va-pa.h, but we probably don't need to align
4885 to word size, since we generate and preserve that invariant. */
4886 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
4887 build_int_2 ((size > 4 ? -8 : -4), -1));
4889 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4890 TREE_SIDE_EFFECTS (t) = 1;
4892 ofs = (8 - size) % 4;
4895 t = build (PLUS_EXPR, TREE_TYPE (valist), t, build_int_2 (ofs, 0));
4896 TREE_SIDE_EFFECTS (t) = 1;
4899 t = build1 (NOP_EXPR, ptr, t);
4900 TREE_SIDE_EFFECTS (t) = 1;
4904 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
4909 /* This routine handles all the normal conditional branch sequences we
4910 might need to generate. It handles compare immediate vs compare
4911 register, nullification of delay slots, varying length branches,
4912 negated branches, and all combinations of the above. It returns the
4913 output appropriate to emit the branch corresponding to all given
4917 output_cbranch (operands, nullify, length, negated, insn)
4919 int nullify, length, negated;
4922 static char buf[100];
4925 /* A conditional branch to the following instruction (eg the delay slot) is
4926 asking for a disaster. This can happen when not optimizing.
4928 In such cases it is safe to emit nothing. */
4930 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4933 /* If this is a long branch with its delay slot unfilled, set `nullify'
4934 as it can nullify the delay slot and save a nop. */
4935 if (length == 8 && dbr_sequence_length () == 0)
4938 /* If this is a short forward conditional branch which did not get
4939 its delay slot filled, the delay slot can still be nullified. */
4940 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4941 nullify = forward_branch_p (insn);
4943 /* A forward branch over a single nullified insn can be done with a
4944 comclr instruction. This avoids a single cycle penalty due to
4945 mis-predicted branch if we fall through (branch not taken). */
4947 && next_real_insn (insn) != 0
4948 && get_attr_length (next_real_insn (insn)) == 4
4949 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4955 /* All short conditional branches except backwards with an unfilled
4959 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
4961 strcpy (buf, "{com%I2b,|cmp%I2b,}");
4962 if (GET_MODE (operands[1]) == DImode)
4965 strcat (buf, "%B3");
4967 strcat (buf, "%S3");
4969 strcat (buf, " %2,%r1,%%r0");
4971 strcat (buf, ",n %2,%r1,%0");
4973 strcat (buf, " %2,%r1,%0");
4976 /* All long conditionals. Note an short backward branch with an
4977 unfilled delay slot is treated just like a long backward branch
4978 with an unfilled delay slot. */
4980 /* Handle weird backwards branch with a filled delay slot
4981 with is nullified. */
4982 if (dbr_sequence_length () != 0
4983 && ! forward_branch_p (insn)
4986 strcpy (buf, "{com%I2b,|cmp%I2b,}");
4987 if (GET_MODE (operands[1]) == DImode)
4990 strcat (buf, "%S3");
4992 strcat (buf, "%B3");
4993 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
4995 /* Handle short backwards branch with an unfilled delay slot.
4996 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
4997 taken and untaken branches. */
4998 else if (dbr_sequence_length () == 0
4999 && ! forward_branch_p (insn)
5000 && INSN_ADDRESSES_SET_P ()
5001 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5002 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5004 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5005 if (GET_MODE (operands[1]) == DImode)
5008 strcat (buf, "%B3 %2,%r1,%0%#");
5010 strcat (buf, "%S3 %2,%r1,%0%#");
5014 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5015 if (GET_MODE (operands[1]) == DImode)
5018 strcat (buf, "%S3");
5020 strcat (buf, "%B3");
5022 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5024 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5029 /* Very long branch. Right now we only handle these when not
5030 optimizing. See "jump" pattern in pa.md for details. */
5034 /* Create a reversed conditional branch which branches around
5035 the following insns. */
5037 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5039 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5040 if (GET_MODE (operands[1]) == DImode)
5044 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5047 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5049 output_asm_insn (buf, operands);
5051 /* Output an insn to save %r1. */
5052 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5054 /* Now output a very long branch to the original target. */
5055 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5057 /* Now restore the value of %r1 in the delay slot. We're not
5058 optimizing so we know nothing else can be in the delay slot. */
5059 return "ldw -16(%%r30),%%r1";
5062 /* Very long branch when generating PIC code. Right now we only
5063 handle these when not optimizing. See "jump" pattern in pa.md
5068 /* Create a reversed conditional branch which branches around
5069 the following insns. */
5071 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5073 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5074 if (GET_MODE (operands[1]) == DImode)
5077 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5079 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5081 output_asm_insn (buf, operands);
5083 /* Output an insn to save %r1. */
5084 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5086 /* Now output a very long PIC branch to the original target. */
5090 xoperands[0] = operands[0];
5091 xoperands[1] = operands[1];
5092 xoperands[2] = operands[2];
5093 xoperands[3] = operands[3];
5094 xoperands[4] = gen_label_rtx ();
5096 output_asm_insn ("{bl|b,l} .+8,%%r1\n\taddil L'%l0-%l4,%%r1",
5098 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5099 CODE_LABEL_NUMBER (xoperands[4]));
5100 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
5104 /* Now restore the value of %r1 in the delay slot. We're not
5105 optimizing so we know nothing else can be in the delay slot. */
5106 return "ldw -16(%%r30),%%r1";
5114 /* This routine handles all the branch-on-bit conditional branch sequences we
5115 might need to generate. It handles nullification of delay slots,
5116 varying length branches, negated branches and all combinations of the
5117 above. it returns the appropriate output template to emit the branch. */
5120 output_bb (operands, nullify, length, negated, insn, which)
5121 rtx *operands ATTRIBUTE_UNUSED;
5122 int nullify, length, negated;
5126 static char buf[100];
5129 /* A conditional branch to the following instruction (eg the delay slot) is
5130 asking for a disaster. I do not think this can happen as this pattern
5131 is only used when optimizing; jump optimization should eliminate the
5132 jump. But be prepared just in case. */
5134 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5137 /* If this is a long branch with its delay slot unfilled, set `nullify'
5138 as it can nullify the delay slot and save a nop. */
5139 if (length == 8 && dbr_sequence_length () == 0)
5142 /* If this is a short forward conditional branch which did not get
5143 its delay slot filled, the delay slot can still be nullified. */
5144 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5145 nullify = forward_branch_p (insn);
5147 /* A forward branch over a single nullified insn can be done with a
5148 extrs instruction. This avoids a single cycle penalty due to
5149 mis-predicted branch if we fall through (branch not taken). */
5152 && next_real_insn (insn) != 0
5153 && get_attr_length (next_real_insn (insn)) == 4
5154 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5161 /* All short conditional branches except backwards with an unfilled
5165 strcpy (buf, "{extrs,|extrw,s,}");
5167 strcpy (buf, "bb,");
5168 if (useskip && GET_MODE (operands[0]) == DImode)
5169 strcpy (buf, "extrd,s,*");
5170 else if (GET_MODE (operands[0]) == DImode)
5171 strcpy (buf, "bb,*");
5172 if ((which == 0 && negated)
5173 || (which == 1 && ! negated))
5178 strcat (buf, " %0,%1,1,%%r0");
5179 else if (nullify && negated)
5180 strcat (buf, ",n %0,%1,%3");
5181 else if (nullify && ! negated)
5182 strcat (buf, ",n %0,%1,%2");
5183 else if (! nullify && negated)
5184 strcat (buf, "%0,%1,%3");
5185 else if (! nullify && ! negated)
5186 strcat (buf, " %0,%1,%2");
5189 /* All long conditionals. Note an short backward branch with an
5190 unfilled delay slot is treated just like a long backward branch
5191 with an unfilled delay slot. */
5193 /* Handle weird backwards branch with a filled delay slot
5194 with is nullified. */
5195 if (dbr_sequence_length () != 0
5196 && ! forward_branch_p (insn)
5199 strcpy (buf, "bb,");
5200 if (GET_MODE (operands[0]) == DImode)
5202 if ((which == 0 && negated)
5203 || (which == 1 && ! negated))
5208 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5210 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5212 /* Handle short backwards branch with an unfilled delay slot.
5213 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5214 taken and untaken branches. */
5215 else if (dbr_sequence_length () == 0
5216 && ! forward_branch_p (insn)
5217 && INSN_ADDRESSES_SET_P ()
5218 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5219 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5221 strcpy (buf, "bb,");
5222 if (GET_MODE (operands[0]) == DImode)
5224 if ((which == 0 && negated)
5225 || (which == 1 && ! negated))
5230 strcat (buf, " %0,%1,%3%#");
5232 strcat (buf, " %0,%1,%2%#");
5236 strcpy (buf, "{extrs,|extrw,s,}");
5237 if (GET_MODE (operands[0]) == DImode)
5238 strcpy (buf, "extrd,s,*");
5239 if ((which == 0 && negated)
5240 || (which == 1 && ! negated))
5244 if (nullify && negated)
5245 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5246 else if (nullify && ! negated)
5247 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5249 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5251 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5261 /* This routine handles all the branch-on-variable-bit conditional branch
5262 sequences we might need to generate. It handles nullification of delay
5263 slots, varying length branches, negated branches and all combinations
5264 of the above. it returns the appropriate output template to emit the
5268 output_bvb (operands, nullify, length, negated, insn, which)
5269 rtx *operands ATTRIBUTE_UNUSED;
5270 int nullify, length, negated;
5274 static char buf[100];
5277 /* A conditional branch to the following instruction (eg the delay slot) is
5278 asking for a disaster. I do not think this can happen as this pattern
5279 is only used when optimizing; jump optimization should eliminate the
5280 jump. But be prepared just in case. */
5282 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5285 /* If this is a long branch with its delay slot unfilled, set `nullify'
5286 as it can nullify the delay slot and save a nop. */
5287 if (length == 8 && dbr_sequence_length () == 0)
5290 /* If this is a short forward conditional branch which did not get
5291 its delay slot filled, the delay slot can still be nullified. */
5292 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5293 nullify = forward_branch_p (insn);
5295 /* A forward branch over a single nullified insn can be done with a
5296 extrs instruction. This avoids a single cycle penalty due to
5297 mis-predicted branch if we fall through (branch not taken). */
5300 && next_real_insn (insn) != 0
5301 && get_attr_length (next_real_insn (insn)) == 4
5302 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5309 /* All short conditional branches except backwards with an unfilled
5313 strcpy (buf, "{vextrs,|extrw,s,}");
5315 strcpy (buf, "{bvb,|bb,}");
5316 if (useskip && GET_MODE (operands[0]) == DImode)
5317 strcpy (buf, "extrd,s,*}");
5318 else if (GET_MODE (operands[0]) == DImode)
5319 strcpy (buf, "bb,*");
5320 if ((which == 0 && negated)
5321 || (which == 1 && ! negated))
5326 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5327 else if (nullify && negated)
5328 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5329 else if (nullify && ! negated)
5330 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5331 else if (! nullify && negated)
5332 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5333 else if (! nullify && ! negated)
5334 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5337 /* All long conditionals. Note an short backward branch with an
5338 unfilled delay slot is treated just like a long backward branch
5339 with an unfilled delay slot. */
5341 /* Handle weird backwards branch with a filled delay slot
5342 with is nullified. */
5343 if (dbr_sequence_length () != 0
5344 && ! forward_branch_p (insn)
5347 strcpy (buf, "{bvb,|bb,}");
5348 if (GET_MODE (operands[0]) == DImode)
5350 if ((which == 0 && negated)
5351 || (which == 1 && ! negated))
5356 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5358 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5360 /* Handle short backwards branch with an unfilled delay slot.
5361 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5362 taken and untaken branches. */
5363 else if (dbr_sequence_length () == 0
5364 && ! forward_branch_p (insn)
5365 && INSN_ADDRESSES_SET_P ()
5366 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5367 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5369 strcpy (buf, "{bvb,|bb,}");
5370 if (GET_MODE (operands[0]) == DImode)
5372 if ((which == 0 && negated)
5373 || (which == 1 && ! negated))
5378 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5380 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5384 strcpy (buf, "{vextrs,|extrw,s,}");
5385 if (GET_MODE (operands[0]) == DImode)
5386 strcpy (buf, "extrd,s,*");
5387 if ((which == 0 && negated)
5388 || (which == 1 && ! negated))
5392 if (nullify && negated)
5393 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5394 else if (nullify && ! negated)
5395 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5397 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5399 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5409 /* Return the output template for emitting a dbra type insn.
5411 Note it may perform some output operations on its own before
5412 returning the final output string. */
5414 output_dbra (operands, insn, which_alternative)
5417 int which_alternative;
5420 /* A conditional branch to the following instruction (eg the delay slot) is
5421 asking for a disaster. Be prepared! */
5423 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5425 if (which_alternative == 0)
5426 return "ldo %1(%0),%0";
5427 else if (which_alternative == 1)
5429 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5430 output_asm_insn ("ldw -16(%%r30),%4", operands);
5431 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5432 return "{fldws|fldw} -16(%%r30),%0";
5436 output_asm_insn ("ldw %0,%4", operands);
5437 return "ldo %1(%4),%4\n\tstw %4,%0";
5441 if (which_alternative == 0)
5443 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5444 int length = get_attr_length (insn);
5446 /* If this is a long branch with its delay slot unfilled, set `nullify'
5447 as it can nullify the delay slot and save a nop. */
5448 if (length == 8 && dbr_sequence_length () == 0)
5451 /* If this is a short forward conditional branch which did not get
5452 its delay slot filled, the delay slot can still be nullified. */
5453 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5454 nullify = forward_branch_p (insn);
5456 /* Handle short versions first. */
5457 if (length == 4 && nullify)
5458 return "addib,%C2,n %1,%0,%3";
5459 else if (length == 4 && ! nullify)
5460 return "addib,%C2 %1,%0,%3";
5461 else if (length == 8)
5463 /* Handle weird backwards branch with a fulled delay slot
5464 which is nullified. */
5465 if (dbr_sequence_length () != 0
5466 && ! forward_branch_p (insn)
5468 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5469 /* Handle short backwards branch with an unfilled delay slot.
5470 Using a addb;nop rather than addi;bl saves 1 cycle for both
5471 taken and untaken branches. */
5472 else if (dbr_sequence_length () == 0
5473 && ! forward_branch_p (insn)
5474 && INSN_ADDRESSES_SET_P ()
5475 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5476 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5477 return "addib,%C2 %1,%0,%3%#";
5479 /* Handle normal cases. */
5481 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5483 return "addi,%N2 %1,%0,%0\n\tb %3";
5488 /* Deal with gross reload from FP register case. */
5489 else if (which_alternative == 1)
5491 /* Move loop counter from FP register to MEM then into a GR,
5492 increment the GR, store the GR into MEM, and finally reload
5493 the FP register from MEM from within the branch's delay slot. */
5494 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5496 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5497 if (get_attr_length (insn) == 24)
5498 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5500 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5502 /* Deal with gross reload from memory case. */
5505 /* Reload loop counter from memory, the store back to memory
5506 happens in the branch's delay slot. */
5507 output_asm_insn ("ldw %0,%4", operands);
5508 if (get_attr_length (insn) == 12)
5509 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5511 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5515 /* Return the output template for emitting a dbra type insn.
5517 Note it may perform some output operations on its own before
5518 returning the final output string. */
5520 output_movb (operands, insn, which_alternative, reverse_comparison)
5523 int which_alternative;
5524 int reverse_comparison;
5527 /* A conditional branch to the following instruction (eg the delay slot) is
5528 asking for a disaster. Be prepared! */
5530 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5532 if (which_alternative == 0)
5533 return "copy %1,%0";
5534 else if (which_alternative == 1)
5536 output_asm_insn ("stw %1,-16(%%r30)", operands);
5537 return "{fldws|fldw} -16(%%r30),%0";
5539 else if (which_alternative == 2)
5545 /* Support the second variant. */
5546 if (reverse_comparison)
5547 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5549 if (which_alternative == 0)
5551 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5552 int length = get_attr_length (insn);
5554 /* If this is a long branch with its delay slot unfilled, set `nullify'
5555 as it can nullify the delay slot and save a nop. */
5556 if (length == 8 && dbr_sequence_length () == 0)
5559 /* If this is a short forward conditional branch which did not get
5560 its delay slot filled, the delay slot can still be nullified. */
5561 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5562 nullify = forward_branch_p (insn);
5564 /* Handle short versions first. */
5565 if (length == 4 && nullify)
5566 return "movb,%C2,n %1,%0,%3";
5567 else if (length == 4 && ! nullify)
5568 return "movb,%C2 %1,%0,%3";
5569 else if (length == 8)
5571 /* Handle weird backwards branch with a filled delay slot
5572 which is nullified. */
5573 if (dbr_sequence_length () != 0
5574 && ! forward_branch_p (insn)
5576 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5578 /* Handle short backwards branch with an unfilled delay slot.
5579 Using a movb;nop rather than or;bl saves 1 cycle for both
5580 taken and untaken branches. */
5581 else if (dbr_sequence_length () == 0
5582 && ! forward_branch_p (insn)
5583 && INSN_ADDRESSES_SET_P ()
5584 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5585 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5586 return "movb,%C2 %1,%0,%3%#";
5587 /* Handle normal cases. */
5589 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5591 return "or,%N2 %1,%%r0,%0\n\tb %3";
5596 /* Deal with gross reload from FP register case. */
5597 else if (which_alternative == 1)
5599 /* Move loop counter from FP register to MEM then into a GR,
5600 increment the GR, store the GR into MEM, and finally reload
5601 the FP register from MEM from within the branch's delay slot. */
5602 output_asm_insn ("stw %1,-16(%%r30)", operands);
5603 if (get_attr_length (insn) == 12)
5604 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
5606 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5608 /* Deal with gross reload from memory case. */
5609 else if (which_alternative == 2)
5611 /* Reload loop counter from memory, the store back to memory
5612 happens in the branch's delay slot. */
5613 if (get_attr_length (insn) == 8)
5614 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
5616 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5618 /* Handle SAR as a destination. */
5621 if (get_attr_length (insn) == 8)
5622 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
5624 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5629 /* INSN is a millicode call. It may have an unconditional jump in its delay
5632 CALL_DEST is the routine we are calling. */
5635 output_millicode_call (insn, call_dest)
5643 xoperands[3] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
5645 /* Handle common case -- empty delay slot or no jump in the delay slot,
5646 and we're sure that the branch will reach the beginning of the $CODE$
5648 if ((dbr_sequence_length () == 0
5649 && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
5650 || (dbr_sequence_length () != 0
5651 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5652 && get_attr_length (insn) == 4))
5654 xoperands[0] = call_dest;
5655 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
5659 /* This call may not reach the beginning of the $CODE$ subspace. */
5660 if (get_attr_length (insn) > 4)
5662 int delay_insn_deleted = 0;
5664 /* We need to emit an inline long-call branch. */
5665 if (dbr_sequence_length () != 0
5666 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5668 /* A non-jump insn in the delay slot. By definition we can
5669 emit this insn before the call. */
5670 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5672 /* Now delete the delay insn. */
5673 PUT_CODE (NEXT_INSN (insn), NOTE);
5674 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5675 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5676 delay_insn_deleted = 1;
5679 /* PIC long millicode call sequence. */
5682 xoperands[0] = call_dest;
5683 xoperands[1] = gen_label_rtx ();
5684 /* Get our address + 8 into %r1. */
5685 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5687 /* Add %r1 to the offset of our target from the next insn. */
5688 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
5689 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5690 CODE_LABEL_NUMBER (xoperands[1]));
5691 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
5693 /* Get the return address into %r31. */
5694 output_asm_insn ("blr 0,%3", xoperands);
5696 /* Branch to our target which is in %r1. */
5697 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
5699 /* Empty delay slot. Note this insn gets fetched twice and
5700 executed once. To be safe we use a nop. */
5701 output_asm_insn ("nop", xoperands);
5703 /* Pure portable runtime doesn't allow be/ble; we also don't have
5704 PIC support in the assembler/linker, so this sequence is needed. */
5705 else if (TARGET_PORTABLE_RUNTIME)
5707 xoperands[0] = call_dest;
5708 /* Get the address of our target into %r29. */
5709 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
5710 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
5712 /* Get our return address into %r31. */
5713 output_asm_insn ("blr %%r0,%3", xoperands);
5715 /* Jump to our target address in %r29. */
5716 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
5718 /* Empty delay slot. Note this insn gets fetched twice and
5719 executed once. To be safe we use a nop. */
5720 output_asm_insn ("nop", xoperands);
5722 /* If we're allowed to use be/ble instructions, then this is the
5723 best sequence to use for a long millicode call. */
5726 xoperands[0] = call_dest;
5727 output_asm_insn ("ldil L%%%0,%3", xoperands);
5728 output_asm_insn ("{ble|be,l} R%%%0(%%sr4,%3)", xoperands);
5729 output_asm_insn ("nop", xoperands);
5732 /* If we had a jump in the call's delay slot, output it now. */
5733 if (dbr_sequence_length () != 0
5734 && !delay_insn_deleted)
5736 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5737 output_asm_insn ("b,n %0", xoperands);
5739 /* Now delete the delay insn. */
5740 PUT_CODE (NEXT_INSN (insn), NOTE);
5741 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5742 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5747 /* This call has an unconditional jump in its delay slot and the
5748 call is known to reach its target or the beginning of the current
5751 /* Use the containing sequence insn's address. */
5752 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5754 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
5755 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
5757 /* If the branch was too far away, emit a normal call followed
5758 by a nop, followed by the unconditional branch.
5760 If the branch is close, then adjust %r2 from within the
5761 call's delay slot. */
5763 xoperands[0] = call_dest;
5764 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5765 if (! VAL_14_BITS_P (distance))
5766 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
5769 xoperands[2] = gen_label_rtx ();
5770 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
5772 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5773 CODE_LABEL_NUMBER (xoperands[2]));
5776 /* Delete the jump. */
5777 PUT_CODE (NEXT_INSN (insn), NOTE);
5778 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5779 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5783 extern struct obstack permanent_obstack;
5785 /* INSN is either a function call. It may have an unconditional jump
5788 CALL_DEST is the routine we are calling. */
5791 output_call (insn, call_dest, sibcall)
5800 /* Handle common case -- empty delay slot or no jump in the delay slot,
5801 and we're sure that the branch will reach the beginning of the $CODE$
5803 if ((dbr_sequence_length () == 0
5804 && get_attr_length (insn) == 8)
5805 || (dbr_sequence_length () != 0
5806 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5807 && get_attr_length (insn) == 4))
5809 xoperands[0] = call_dest;
5810 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
5811 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
5815 /* This call may not reach the beginning of the $CODE$ subspace. */
5816 if (get_attr_length (insn) > 8)
5818 int delay_insn_deleted = 0;
5822 /* We need to emit an inline long-call branch. Furthermore,
5823 because we're changing a named function call into an indirect
5824 function call well after the parameters have been set up, we
5825 need to make sure any FP args appear in both the integer
5826 and FP registers. Also, we need move any delay slot insn
5827 out of the delay slot. And finally, we can't rely on the linker
5828 being able to fix the call to $$dyncall! -- Yuk!. */
5829 if (dbr_sequence_length () != 0
5830 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5832 /* A non-jump insn in the delay slot. By definition we can
5833 emit this insn before the call (and in fact before argument
5835 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5837 /* Now delete the delay insn. */
5838 PUT_CODE (NEXT_INSN (insn), NOTE);
5839 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5840 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5841 delay_insn_deleted = 1;
5844 /* Now copy any FP arguments into integer registers. */
5845 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
5847 int arg_mode, regno;
5848 rtx use = XEXP (link, 0);
5849 if (! (GET_CODE (use) == USE
5850 && GET_CODE (XEXP (use, 0)) == REG
5851 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5854 arg_mode = GET_MODE (XEXP (use, 0));
5855 regno = REGNO (XEXP (use, 0));
5856 /* Is it a floating point register? */
5857 if (regno >= 32 && regno <= 39)
5859 /* Copy from the FP register into an integer register
5861 if (arg_mode == SFmode)
5863 xoperands[0] = XEXP (use, 0);
5864 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
5865 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
5867 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5871 xoperands[0] = XEXP (use, 0);
5872 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
5873 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
5875 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
5876 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5881 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5882 we don't have any direct calls in that case. */
5885 const char *name = XSTR (call_dest, 0);
5887 /* See if we have already put this function on the list
5888 of deferred plabels. This list is generally small,
5889 so a liner search is not too ugly. If it proves too
5890 slow replace it with something faster. */
5891 for (i = 0; i < n_deferred_plabels; i++)
5892 if (strcmp (name, deferred_plabels[i].name) == 0)
5895 /* If the deferred plabel list is empty, or this entry was
5896 not found on the list, create a new entry on the list. */
5897 if (deferred_plabels == NULL || i == n_deferred_plabels)
5899 const char *real_name;
5901 if (deferred_plabels == 0)
5902 deferred_plabels = (struct deferred_plabel *)
5903 xmalloc (1 * sizeof (struct deferred_plabel));
5905 deferred_plabels = (struct deferred_plabel *)
5906 xrealloc (deferred_plabels,
5907 ((n_deferred_plabels + 1)
5908 * sizeof (struct deferred_plabel)));
5910 i = n_deferred_plabels++;
5911 deferred_plabels[i].internal_label = gen_label_rtx ();
5912 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
5914 strcpy (deferred_plabels[i].name, name);
5916 /* Gross. We have just implicitly taken the address of this
5917 function, mark it as such. */
5918 STRIP_NAME_ENCODING (real_name, name);
5919 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5922 /* We have to load the address of the function using a procedure
5923 label (plabel). Inline plabels can lose for PIC and other
5924 cases, so avoid them by creating a 32bit plabel in the data
5928 xoperands[0] = deferred_plabels[i].internal_label;
5929 xoperands[1] = gen_label_rtx ();
5931 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
5932 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
5933 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
5935 /* Get our address + 8 into %r1. */
5936 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5938 /* Add %r1 to the offset of dyncall from the next insn. */
5939 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
5940 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5941 CODE_LABEL_NUMBER (xoperands[1]));
5942 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
5944 /* Get the return address into %r31. */
5945 output_asm_insn ("blr %%r0,%%r31", xoperands);
5947 /* Branch to our target which is in %r1. */
5948 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5952 /* This call never returns, so we do not need to fix the
5954 output_asm_insn ("nop", xoperands);
5958 /* Copy the return address into %r2 also. */
5959 output_asm_insn ("copy %%r31,%%r2", xoperands);
5964 xoperands[0] = deferred_plabels[i].internal_label;
5966 /* Get the address of our target into %r22. */
5967 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
5968 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
5970 /* Get the high part of the address of $dyncall into %r2, then
5971 add in the low part in the branch instruction. */
5972 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
5973 output_asm_insn ("{ble|be,l} R%%$$dyncall(%%sr4,%%r2)",
5978 /* This call never returns, so we do not need to fix the
5980 output_asm_insn ("nop", xoperands);
5984 /* Copy the return address into %r2 also. */
5985 output_asm_insn ("copy %%r31,%%r2", xoperands);
5990 /* If we had a jump in the call's delay slot, output it now. */
5991 if (dbr_sequence_length () != 0
5992 && !delay_insn_deleted)
5994 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5995 output_asm_insn ("b,n %0", xoperands);
5997 /* Now delete the delay insn. */
5998 PUT_CODE (NEXT_INSN (insn), NOTE);
5999 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6000 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6005 /* This call has an unconditional jump in its delay slot and the
6006 call is known to reach its target or the beginning of the current
6009 /* Use the containing sequence insn's address. */
6010 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6012 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6013 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6015 /* If the branch was too far away, emit a normal call followed
6016 by a nop, followed by the unconditional branch.
6018 If the branch is close, then adjust %r2 from within the
6019 call's delay slot. */
6021 xoperands[0] = call_dest;
6022 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6023 if (! VAL_14_BITS_P (distance))
6024 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
6027 xoperands[3] = gen_label_rtx ();
6028 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6030 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6031 CODE_LABEL_NUMBER (xoperands[3]));
6034 /* Delete the jump. */
6035 PUT_CODE (NEXT_INSN (insn), NOTE);
6036 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6037 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6041 /* In HPUX 8.0's shared library scheme, special relocations are needed
6042 for function labels if they might be passed to a function
6043 in a shared library (because shared libraries don't live in code
6044 space), and special magic is needed to construct their address. */
6047 hppa_encode_label (sym)
6050 const char *str = XSTR (sym, 0);
6051 int len = strlen (str) + 1;
6054 p = newstr = alloca (len + 1);
6063 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6067 function_label_operand (op, mode)
6069 enum machine_mode mode ATTRIBUTE_UNUSED;
6071 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6074 /* Returns 1 if OP is a function label involved in a simple addition
6075 with a constant. Used to keep certain patterns from matching
6076 during instruction combination. */
6078 is_function_label_plus_const (op)
6081 /* Strip off any CONST. */
6082 if (GET_CODE (op) == CONST)
6085 return (GET_CODE (op) == PLUS
6086 && function_label_operand (XEXP (op, 0), Pmode)
6087 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6090 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6091 use in fmpyadd instructions. */
6093 fmpyaddoperands (operands)
6096 enum machine_mode mode = GET_MODE (operands[0]);
6098 /* Must be a floating point mode. */
6099 if (mode != SFmode && mode != DFmode)
6102 /* All modes must be the same. */
6103 if (! (mode == GET_MODE (operands[1])
6104 && mode == GET_MODE (operands[2])
6105 && mode == GET_MODE (operands[3])
6106 && mode == GET_MODE (operands[4])
6107 && mode == GET_MODE (operands[5])))
6110 /* All operands must be registers. */
6111 if (! (GET_CODE (operands[1]) == REG
6112 && GET_CODE (operands[2]) == REG
6113 && GET_CODE (operands[3]) == REG
6114 && GET_CODE (operands[4]) == REG
6115 && GET_CODE (operands[5]) == REG))
6118 /* Only 2 real operands to the addition. One of the input operands must
6119 be the same as the output operand. */
6120 if (! rtx_equal_p (operands[3], operands[4])
6121 && ! rtx_equal_p (operands[3], operands[5]))
6124 /* Inout operand of add can not conflict with any operands from multiply. */
6125 if (rtx_equal_p (operands[3], operands[0])
6126 || rtx_equal_p (operands[3], operands[1])
6127 || rtx_equal_p (operands[3], operands[2]))
6130 /* multiply can not feed into addition operands. */
6131 if (rtx_equal_p (operands[4], operands[0])
6132 || rtx_equal_p (operands[5], operands[0]))
6135 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6137 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6138 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6139 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6140 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6141 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6142 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6145 /* Passed. Operands are suitable for fmpyadd. */
6149 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6150 use in fmpysub instructions. */
6152 fmpysuboperands (operands)
6155 enum machine_mode mode = GET_MODE (operands[0]);
6157 /* Must be a floating point mode. */
6158 if (mode != SFmode && mode != DFmode)
6161 /* All modes must be the same. */
6162 if (! (mode == GET_MODE (operands[1])
6163 && mode == GET_MODE (operands[2])
6164 && mode == GET_MODE (operands[3])
6165 && mode == GET_MODE (operands[4])
6166 && mode == GET_MODE (operands[5])))
6169 /* All operands must be registers. */
6170 if (! (GET_CODE (operands[1]) == REG
6171 && GET_CODE (operands[2]) == REG
6172 && GET_CODE (operands[3]) == REG
6173 && GET_CODE (operands[4]) == REG
6174 && GET_CODE (operands[5]) == REG))
6177 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6178 operation, so operands[4] must be the same as operand[3]. */
6179 if (! rtx_equal_p (operands[3], operands[4]))
6182 /* multiply can not feed into subtraction. */
6183 if (rtx_equal_p (operands[5], operands[0]))
6186 /* Inout operand of sub can not conflict with any operands from multiply. */
6187 if (rtx_equal_p (operands[3], operands[0])
6188 || rtx_equal_p (operands[3], operands[1])
6189 || rtx_equal_p (operands[3], operands[2]))
6192 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6194 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6195 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6196 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6197 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6198 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6199 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6202 /* Passed. Operands are suitable for fmpysub. */
6207 plus_xor_ior_operator (op, mode)
6209 enum machine_mode mode ATTRIBUTE_UNUSED;
6211 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6212 || GET_CODE (op) == IOR);
6215 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6216 constants for shadd instructions. */
6218 shadd_constant_p (val)
6221 if (val == 2 || val == 4 || val == 8)
6227 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6228 the valid constant for shadd instructions. */
6230 shadd_operand (op, mode)
6232 enum machine_mode mode ATTRIBUTE_UNUSED;
6234 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6237 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6240 basereg_operand (op, mode)
6242 enum machine_mode mode;
6244 /* cse will create some unscaled indexed addresses, however; it
6245 generally isn't a win on the PA, so avoid creating unscaled
6246 indexed addresses until after cse is finished. */
6247 if (!cse_not_expected)
6250 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6251 we don't have to worry about the braindamaged implicit space
6252 register selection from the basereg. */
6253 if (TARGET_NO_SPACE_REGS)
6254 return (GET_CODE (op) == REG);
6256 /* While it's always safe to index off the frame pointer, it's not
6257 always profitable, particularly when the frame pointer is being
6259 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6262 return (GET_CODE (op) == REG
6264 && register_operand (op, mode));
6267 /* Return 1 if this operand is anything other than a hard register. */
6270 non_hard_reg_operand (op, mode)
6272 enum machine_mode mode ATTRIBUTE_UNUSED;
6274 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6277 /* Return 1 if INSN branches forward. Should be using insn_addresses
6278 to avoid walking through all the insns... */
6280 forward_branch_p (insn)
6283 rtx label = JUMP_LABEL (insn);
6290 insn = NEXT_INSN (insn);
6293 return (insn == label);
6296 /* Return 1 if OP is an equality comparison, else return 0. */
6298 eq_neq_comparison_operator (op, mode)
6300 enum machine_mode mode ATTRIBUTE_UNUSED;
6302 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6305 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6307 movb_comparison_operator (op, mode)
6309 enum machine_mode mode ATTRIBUTE_UNUSED;
6311 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6312 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6315 /* Return 1 if INSN is in the delay slot of a call instruction. */
6317 jump_in_call_delay (insn)
6321 if (GET_CODE (insn) != JUMP_INSN)
6324 if (PREV_INSN (insn)
6325 && PREV_INSN (PREV_INSN (insn))
6326 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6328 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6330 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6331 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6338 /* Output an unconditional move and branch insn. */
6341 output_parallel_movb (operands, length)
6345 /* These are the cases in which we win. */
6347 return "mov%I1b,tr %1,%0,%2";
6349 /* None of these cases wins, but they don't lose either. */
6350 if (dbr_sequence_length () == 0)
6352 /* Nothing in the delay slot, fake it by putting the combined
6353 insn (the copy or add) in the delay slot of a bl. */
6354 if (GET_CODE (operands[1]) == CONST_INT)
6355 return "b %2\n\tldi %1,%0";
6357 return "b %2\n\tcopy %1,%0";
6361 /* Something in the delay slot, but we've got a long branch. */
6362 if (GET_CODE (operands[1]) == CONST_INT)
6363 return "ldi %1,%0\n\tb %2";
6365 return "copy %1,%0\n\tb %2";
6369 /* Output an unconditional add and branch insn. */
6372 output_parallel_addb (operands, length)
6376 /* To make life easy we want operand0 to be the shared input/output
6377 operand and operand1 to be the readonly operand. */
6378 if (operands[0] == operands[1])
6379 operands[1] = operands[2];
6381 /* These are the cases in which we win. */
6383 return "add%I1b,tr %1,%0,%3";
6385 /* None of these cases win, but they don't lose either. */
6386 if (dbr_sequence_length () == 0)
6388 /* Nothing in the delay slot, fake it by putting the combined
6389 insn (the copy or add) in the delay slot of a bl. */
6390 return "b %3\n\tadd%I1 %1,%0,%0";
6394 /* Something in the delay slot, but we've got a long branch. */
6395 return "add%I1 %1,%0,%0\n\tb %3";
6399 /* Return nonzero if INSN (a jump insn) immediately follows a call to
6400 a named function. This is used to discourage creating parallel movb/addb
6401 insns since a jump which immediately follows a call can execute in the
6402 delay slot of the call.
6404 It is also used to avoid filling the delay slot of a jump which
6405 immediately follows a call since the jump can usually be eliminated
6406 completely by modifying RP in the delay slot of the call. */
6409 following_call (insn)
6412 /* We do not parallel movb,addb or place jumps into call delay slots when
6413 optimizing for the PA8000. */
6414 if (pa_cpu != PROCESSOR_8000)
6417 /* Find the previous real insn, skipping NOTEs. */
6418 insn = PREV_INSN (insn);
6419 while (insn && GET_CODE (insn) == NOTE)
6420 insn = PREV_INSN (insn);
6422 /* Check for CALL_INSNs and millicode calls. */
6424 && ((GET_CODE (insn) == CALL_INSN
6425 && get_attr_type (insn) != TYPE_DYNCALL)
6426 || (GET_CODE (insn) == INSN
6427 && GET_CODE (PATTERN (insn)) != SEQUENCE
6428 && GET_CODE (PATTERN (insn)) != USE
6429 && GET_CODE (PATTERN (insn)) != CLOBBER
6430 && get_attr_type (insn) == TYPE_MILLI)))
6436 /* We use this hook to perform a PA specific optimization which is difficult
6437 to do in earlier passes.
6439 We want the delay slots of branches within jump tables to be filled.
6440 None of the compiler passes at the moment even has the notion that a
6441 PA jump table doesn't contain addresses, but instead contains actual
6444 Because we actually jump into the table, the addresses of each entry
6445 must stay constant in relation to the beginning of the table (which
6446 itself must stay constant relative to the instruction to jump into
6447 it). I don't believe we can guarantee earlier passes of the compiler
6448 will adhere to those rules.
6450 So, late in the compilation process we find all the jump tables, and
6451 expand them into real code -- eg each entry in the jump table vector
6452 will get an appropriate label followed by a jump to the final target.
6454 Reorg and the final jump pass can then optimize these branches and
6455 fill their delay slots. We end up with smaller, more efficient code.
6457 The jump instructions within the table are special; we must be able
6458 to identify them during assembly output (if the jumps don't get filled
6459 we need to emit a nop rather than nullifying the delay slot)). We
6460 identify jumps in switch tables by marking the SET with DImode.
6462 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6463 insns. This serves two purposes, first it prevents jump.c from
6464 noticing that the last N entries in the table jump to the instruction
6465 immediately after the table and deleting the jumps. Second, those
6466 insns mark where we should emit .begin_brtab and .end_brtab directives
6467 when using GAS (allows for better link time optimizations). */
6475 remove_useless_addtr_insns (insns, 1);
6477 if (pa_cpu < PROCESSOR_8000)
6478 pa_combine_instructions (get_insns ());
6481 /* This is fairly cheap, so always run it if optimizing. */
6482 if (optimize > 0 && !TARGET_BIG_SWITCH)
6484 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6485 insns = get_insns ();
6486 for (insn = insns; insn; insn = NEXT_INSN (insn))
6488 rtx pattern, tmp, location;
6489 unsigned int length, i;
6491 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6492 if (GET_CODE (insn) != JUMP_INSN
6493 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6494 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6497 /* Emit marker for the beginning of the branch table. */
6498 emit_insn_before (gen_begin_brtab (), insn);
6500 pattern = PATTERN (insn);
6501 location = PREV_INSN (insn);
6502 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6504 for (i = 0; i < length; i++)
6506 /* Emit a label before each jump to keep jump.c from
6507 removing this code. */
6508 tmp = gen_label_rtx ();
6509 LABEL_NUSES (tmp) = 1;
6510 emit_label_after (tmp, location);
6511 location = NEXT_INSN (location);
6513 if (GET_CODE (pattern) == ADDR_VEC)
6515 /* Emit the jump itself. */
6516 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
6517 tmp = emit_jump_insn_after (tmp, location);
6518 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
6519 /* It is easy to rely on the branch table markers
6520 during assembly output to trigger the correct code
6521 for a switch table jump with an unfilled delay slot,
6523 However, that requires state and assumes that we look
6526 We can't make such assumptions when computing the length
6527 of instructions. Ugh. We could walk the insn chain to
6528 determine if this instruction is in a branch table, but
6529 that can get rather expensive, particularly during the
6530 branch shortening phase of the compiler.
6532 So instead we mark this jump as being special. This is
6533 far from ideal and knows that no code after this will
6534 muck around with the mode of the JUMP_INSN itself. */
6535 PUT_MODE (tmp, SImode);
6536 LABEL_NUSES (JUMP_LABEL (tmp))++;
6537 location = NEXT_INSN (location);
6541 /* Emit the jump itself. */
6542 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
6543 tmp = emit_jump_insn_after (tmp, location);
6544 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
6545 /* It is easy to rely on the branch table markers
6546 during assembly output to trigger the correct code
6547 for a switch table jump with an unfilled delay slot,
6549 However, that requires state and assumes that we look
6552 We can't make such assumptions when computing the length
6553 of instructions. Ugh. We could walk the insn chain to
6554 determine if this instruction is in a branch table, but
6555 that can get rather expensive, particularly during the
6556 branch shortening phase of the compiler.
6558 So instead we mark this jump as being special. This is
6559 far from ideal and knows that no code after this will
6560 muck around with the mode of the JUMP_INSN itself. */
6561 PUT_MODE (tmp, SImode);
6562 LABEL_NUSES (JUMP_LABEL (tmp))++;
6563 location = NEXT_INSN (location);
6566 /* Emit a BARRIER after the jump. */
6567 emit_barrier_after (location);
6568 location = NEXT_INSN (location);
6571 /* Emit marker for the end of the branch table. */
6572 emit_insn_before (gen_end_brtab (), location);
6573 location = NEXT_INSN (location);
6574 emit_barrier_after (location);
6576 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6582 /* Sill need an end_brtab insn. */
6583 insns = get_insns ();
6584 for (insn = insns; insn; insn = NEXT_INSN (insn))
6586 /* Find an ADDR_VEC insn. */
6587 if (GET_CODE (insn) != JUMP_INSN
6588 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6589 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6592 /* Now generate markers for the beginning and end of the
6594 emit_insn_before (gen_begin_brtab (), insn);
6595 emit_insn_after (gen_end_brtab (), insn);
6600 /* The PA has a number of odd instructions which can perform multiple
6601 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6602 it may be profitable to combine two instructions into one instruction
6603 with two outputs. It's not profitable PA2.0 machines because the
6604 two outputs would take two slots in the reorder buffers.
6606 This routine finds instructions which can be combined and combines
6607 them. We only support some of the potential combinations, and we
6608 only try common ways to find suitable instructions.
6610 * addb can add two registers or a register and a small integer
6611 and jump to a nearby (+-8k) location. Normally the jump to the
6612 nearby location is conditional on the result of the add, but by
6613 using the "true" condition we can make the jump unconditional.
6614 Thus addb can perform two independent operations in one insn.
6616 * movb is similar to addb in that it can perform a reg->reg
6617 or small immediate->reg copy and jump to a nearby (+-8k location).
6619 * fmpyadd and fmpysub can perform a FP multiply and either an
6620 FP add or FP sub if the operands of the multiply and add/sub are
6621 independent (there are other minor restrictions). Note both
6622 the fmpy and fadd/fsub can in theory move to better spots according
6623 to data dependencies, but for now we require the fmpy stay at a
6626 * Many of the memory operations can perform pre & post updates
6627 of index registers. GCC's pre/post increment/decrement addressing
6628 is far too simple to take advantage of all the possibilities. This
6629 pass may not be suitable since those insns may not be independent.
6631 * comclr can compare two ints or an int and a register, nullify
6632 the following instruction and zero some other register. This
6633 is more difficult to use as it's harder to find an insn which
6634 will generate a comclr than finding something like an unconditional
6635 branch. (conditional moves & long branches create comclr insns).
6637 * Most arithmetic operations can conditionally skip the next
6638 instruction. They can be viewed as "perform this operation
6639 and conditionally jump to this nearby location" (where nearby
6640 is an insns away). These are difficult to use due to the
6641 branch length restrictions. */
6644 pa_combine_instructions (insns)
6645 rtx insns ATTRIBUTE_UNUSED;
6649 /* This can get expensive since the basic algorithm is on the
6650 order of O(n^2) (or worse). Only do it for -O2 or higher
6651 levels of optimization. */
6655 /* Walk down the list of insns looking for "anchor" insns which
6656 may be combined with "floating" insns. As the name implies,
6657 "anchor" instructions don't move, while "floating" insns may
6659 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
6660 new = make_insn_raw (new);
6662 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
6664 enum attr_pa_combine_type anchor_attr;
6665 enum attr_pa_combine_type floater_attr;
6667 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6668 Also ignore any special USE insns. */
6669 if ((GET_CODE (anchor) != INSN
6670 && GET_CODE (anchor) != JUMP_INSN
6671 && GET_CODE (anchor) != CALL_INSN)
6672 || GET_CODE (PATTERN (anchor)) == USE
6673 || GET_CODE (PATTERN (anchor)) == CLOBBER
6674 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
6675 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
6678 anchor_attr = get_attr_pa_combine_type (anchor);
6679 /* See if anchor is an insn suitable for combination. */
6680 if (anchor_attr == PA_COMBINE_TYPE_FMPY
6681 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
6682 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6683 && ! forward_branch_p (anchor)))
6687 for (floater = PREV_INSN (anchor);
6689 floater = PREV_INSN (floater))
6691 if (GET_CODE (floater) == NOTE
6692 || (GET_CODE (floater) == INSN
6693 && (GET_CODE (PATTERN (floater)) == USE
6694 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6697 /* Anything except a regular INSN will stop our search. */
6698 if (GET_CODE (floater) != INSN
6699 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6700 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6706 /* See if FLOATER is suitable for combination with the
6708 floater_attr = get_attr_pa_combine_type (floater);
6709 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6710 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6711 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6712 && floater_attr == PA_COMBINE_TYPE_FMPY))
6714 /* If ANCHOR and FLOATER can be combined, then we're
6715 done with this pass. */
6716 if (pa_can_combine_p (new, anchor, floater, 0,
6717 SET_DEST (PATTERN (floater)),
6718 XEXP (SET_SRC (PATTERN (floater)), 0),
6719 XEXP (SET_SRC (PATTERN (floater)), 1)))
6723 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6724 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
6726 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
6728 if (pa_can_combine_p (new, anchor, floater, 0,
6729 SET_DEST (PATTERN (floater)),
6730 XEXP (SET_SRC (PATTERN (floater)), 0),
6731 XEXP (SET_SRC (PATTERN (floater)), 1)))
6736 if (pa_can_combine_p (new, anchor, floater, 0,
6737 SET_DEST (PATTERN (floater)),
6738 SET_SRC (PATTERN (floater)),
6739 SET_SRC (PATTERN (floater))))
6745 /* If we didn't find anything on the backwards scan try forwards. */
6747 && (anchor_attr == PA_COMBINE_TYPE_FMPY
6748 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
6750 for (floater = anchor; floater; floater = NEXT_INSN (floater))
6752 if (GET_CODE (floater) == NOTE
6753 || (GET_CODE (floater) == INSN
6754 && (GET_CODE (PATTERN (floater)) == USE
6755 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6759 /* Anything except a regular INSN will stop our search. */
6760 if (GET_CODE (floater) != INSN
6761 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6762 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6768 /* See if FLOATER is suitable for combination with the
6770 floater_attr = get_attr_pa_combine_type (floater);
6771 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6772 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6773 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6774 && floater_attr == PA_COMBINE_TYPE_FMPY))
6776 /* If ANCHOR and FLOATER can be combined, then we're
6777 done with this pass. */
6778 if (pa_can_combine_p (new, anchor, floater, 1,
6779 SET_DEST (PATTERN (floater)),
6780 XEXP (SET_SRC (PATTERN (floater)),
6782 XEXP (SET_SRC (PATTERN (floater)),
6789 /* FLOATER will be nonzero if we found a suitable floating
6790 insn for combination with ANCHOR. */
6792 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6793 || anchor_attr == PA_COMBINE_TYPE_FMPY))
6795 /* Emit the new instruction and delete the old anchor. */
6796 emit_insn_before (gen_rtx_PARALLEL
6798 gen_rtvec (2, PATTERN (anchor),
6799 PATTERN (floater))),
6802 PUT_CODE (anchor, NOTE);
6803 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6804 NOTE_SOURCE_FILE (anchor) = 0;
6806 /* Emit a special USE insn for FLOATER, then delete
6807 the floating insn. */
6808 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6809 delete_insn (floater);
6814 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
6817 /* Emit the new_jump instruction and delete the old anchor. */
6819 = emit_jump_insn_before (gen_rtx_PARALLEL
6821 gen_rtvec (2, PATTERN (anchor),
6822 PATTERN (floater))),
6825 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
6826 PUT_CODE (anchor, NOTE);
6827 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6828 NOTE_SOURCE_FILE (anchor) = 0;
6830 /* Emit a special USE insn for FLOATER, then delete
6831 the floating insn. */
6832 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6833 delete_insn (floater);
6841 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
6842 rtx new, anchor, floater;
6844 rtx dest, src1, src2;
6846 int insn_code_number;
6849 /* Create a PARALLEL with the patterns of ANCHOR and
6850 FLOATER, try to recognize it, then test constraints
6851 for the resulting pattern.
6853 If the pattern doesn't match or the constraints
6854 aren't met keep searching for a suitable floater
6856 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
6857 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
6858 INSN_CODE (new) = -1;
6859 insn_code_number = recog_memoized (new);
6860 if (insn_code_number < 0
6861 || !constrain_operands (1))
6875 /* There's up to three operands to consider. One
6876 output and two inputs.
6878 The output must not be used between FLOATER & ANCHOR
6879 exclusive. The inputs must not be set between
6880 FLOATER and ANCHOR exclusive. */
6882 if (reg_used_between_p (dest, start, end))
6885 if (reg_set_between_p (src1, start, end))
6888 if (reg_set_between_p (src2, start, end))
6891 /* If we get here, then everything is good. */
6895 /* Return nonzero if references for INSN are delayed.
6897 Millicode insns are actually function calls with some special
6898 constraints on arguments and register usage.
6900 Millicode calls always expect their arguments in the integer argument
6901 registers, and always return their result in %r29 (ret1). They
6902 are expected to clobber their arguments, %r1, %r29, and %r31 and
6905 By considering this effects delayed reorg reorg can put insns
6906 which set the argument registers into the delay slot of the millicode
6907 call -- thus they act more like traditional CALL_INSNs.
6909 get_attr_type will try to recognize the given insn, so make sure to
6910 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
6913 insn_refs_are_delayed (insn)
6916 return ((GET_CODE (insn) == INSN
6917 && GET_CODE (PATTERN (insn)) != SEQUENCE
6918 && GET_CODE (PATTERN (insn)) != USE
6919 && GET_CODE (PATTERN (insn)) != CLOBBER
6920 && get_attr_type (insn) == TYPE_MILLI));
6923 /* Return the location of a parameter that is passed in a register or NULL
6924 if the parameter has any component that is passed in memory.
6926 This is new code and will be pushed to into the net sources after
6929 ??? We might want to restructure this so that it looks more like other
6932 function_arg (cum, mode, type, named, incoming)
6933 CUMULATIVE_ARGS *cum;
6934 enum machine_mode mode;
6936 int named ATTRIBUTE_UNUSED;
6939 int max_arg_words = (TARGET_64BIT ? 8 : 4);
6946 /* If this arg would be passed partially or totally on the stack, then
6947 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
6948 handle arguments which are split between regs and stack slots if
6949 the ABI mandates split arguments. */
6950 if (cum->words + FUNCTION_ARG_SIZE (mode, type) > max_arg_words
6951 || mode == VOIDmode)
6957 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
6959 if (cum->words + offset >= max_arg_words
6960 || mode == VOIDmode)
6964 /* The 32bit ABIs and the 64bit ABIs are rather different,
6965 particularly in their handling of FP registers. We might
6966 be able to cleverly share code between them, but I'm not
6967 going to bother in the hope that splitting them up results
6968 in code that is more easily understood.
6970 The 64bit code probably is very wrong for structure passing. */
6973 /* Advance the base registers to their current locations.
6975 Remember, gprs grow towards smaller register numbers while
6976 fprs grow to higher register numbers. Also remember FP regs
6977 are always 4 bytes wide, while the size of an integer register
6978 varies based on the size of the target word. */
6979 gpr_reg_base = 26 - cum->words;
6980 fpr_reg_base = 32 + cum->words;
6982 /* If the argument is more than a word long, then we need to align
6983 the base registers. Same caveats as above. */
6984 if (FUNCTION_ARG_SIZE (mode, type) > 1)
6986 if (mode != BLKmode)
6988 /* First deal with alignment of the doubleword. */
6989 gpr_reg_base -= (cum->words & 1);
6991 /* This seems backwards, but it is what HP specifies. We need
6992 gpr_reg_base to point to the smaller numbered register of
6993 the integer register pair. So if we have an even register
6994 number, then decrement the gpr base. */
6995 gpr_reg_base -= ((gpr_reg_base % 2) == 0);
6997 /* FP values behave sanely, except that each FP reg is only
6999 fpr_reg_base += ((fpr_reg_base % 2) == 0);
7004 int i, offset = 0, ub;
7005 ub = FUNCTION_ARG_SIZE (mode, type);
7007 MAX (0, max_arg_words - cum->words - (cum->words & 1)));
7008 gpr_reg_base -= (cum->words & 1);
7009 for (i = 0; i < ub; i++)
7011 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7012 gen_rtx_REG (DImode,
7021 return XEXP (loc[0], 0);
7023 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7029 /* If the argument is larger than a word, then we know precisely
7030 which registers we must use. */
7031 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7046 /* We have a single word (32 bits). A simple computation
7047 will get us the register #s we need. */
7048 gpr_reg_base = 26 - cum->words;
7049 fpr_reg_base = 32 + 2 * cum->words;
7053 if (TARGET_64BIT && mode == TFmode)
7059 gen_rtx_EXPR_LIST (VOIDmode,
7060 gen_rtx_REG (DImode, gpr_reg_base + 1),
7062 gen_rtx_EXPR_LIST (VOIDmode,
7063 gen_rtx_REG (DImode, gpr_reg_base),
7066 /* Determine if the register needs to be passed in both general and
7067 floating point registers. */
7068 if ((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7069 /* If we are doing soft-float with portable runtime, then there
7070 is no need to worry about FP regs. */
7071 && ! TARGET_SOFT_FLOAT
7072 /* The parameter must be some kind of float, else we can just
7073 pass it in integer registers. */
7074 && FLOAT_MODE_P (mode)
7075 /* The target function must not have a prototype. */
7076 && cum->nargs_prototype <= 0
7077 /* libcalls do not need to pass items in both FP and general
7079 && type != NULL_TREE
7080 /* All this hair applies to outgoing args only. */
7087 gen_rtx_EXPR_LIST (VOIDmode,
7088 gen_rtx_REG (mode, fpr_reg_base),
7090 gen_rtx_EXPR_LIST (VOIDmode,
7091 gen_rtx_REG (mode, gpr_reg_base),
7096 /* See if we should pass this parameter in a general register. */
7097 if (TARGET_SOFT_FLOAT
7098 /* Indirect calls in the normal 32bit ABI require all arguments
7099 to be passed in general registers. */
7100 || (!TARGET_PORTABLE_RUNTIME
7103 /* If the parameter is not a floating point parameter, then
7104 it belongs in GPRs. */
7105 || !FLOAT_MODE_P (mode))
7106 retval = gen_rtx_REG (mode, gpr_reg_base);
7108 retval = gen_rtx_REG (mode, fpr_reg_base);
7114 /* If this arg would be passed totally in registers or totally on the stack,
7115 then this routine should return zero. It is currently called only for
7116 the 64-bit target. */
7118 function_arg_partial_nregs (cum, mode, type, named)
7119 CUMULATIVE_ARGS *cum;
7120 enum machine_mode mode;
7122 int named ATTRIBUTE_UNUSED;
7124 unsigned int max_arg_words = 8;
7125 unsigned int offset = 0;
7127 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7130 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
7131 /* Arg fits fully into registers. */
7133 else if (cum->words + offset >= max_arg_words)
7134 /* Arg fully on the stack. */
7138 return max_arg_words - cum->words - offset;
7142 /* Return 1 if this is a comparison operator. This allows the use of
7143 MATCH_OPERATOR to recognize all the branch insns. */
7146 cmpib_comparison_operator (op, mode)
7148 enum machine_mode mode;
7150 return ((mode == VOIDmode || GET_MODE (op) == mode)
7151 && (GET_CODE (op) == EQ
7152 || GET_CODE (op) == NE
7153 || GET_CODE (op) == GT
7154 || GET_CODE (op) == GTU
7155 || GET_CODE (op) == GE
7156 || GET_CODE (op) == LT
7157 || GET_CODE (op) == LE
7158 || GET_CODE (op) == LEU));
7161 /* Mark ARG (which is really a struct deferred_plabel **) for GC. */
7164 mark_deferred_plabels (arg)
7167 struct deferred_plabel *dp = *(struct deferred_plabel **) arg;
7170 for (i = 0; i < n_deferred_plabels; ++i)
7171 ggc_mark_rtx (dp[i].internal_label);
7174 /* Called to register all of our global variables with the garbage
7180 ggc_add_rtx_root (&hppa_compare_op0, 1);
7181 ggc_add_rtx_root (&hppa_compare_op1, 1);
7182 ggc_add_root (&deferred_plabels, 1, sizeof (&deferred_plabels),
7183 &mark_deferred_plabels);