1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
41 #include "integrate.h"
50 #include "target-def.h"
52 static int hppa_use_dfa_pipeline_interface PARAMS ((void));
54 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
55 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
58 hppa_use_dfa_pipeline_interface ()
63 /* Return nonzero if there is a bypass for the output of
64 OUT_INSN and the fp store IN_INSN. */
66 hppa_fpstore_bypass_p (out_insn, in_insn)
67 rtx out_insn, in_insn;
69 enum machine_mode store_mode;
70 enum machine_mode other_mode;
73 if (recog_memoized (in_insn) < 0
74 || get_attr_type (in_insn) != TYPE_FPSTORE
75 || recog_memoized (out_insn) < 0)
78 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
80 set = single_set (out_insn);
84 other_mode = GET_MODE (SET_SRC (set));
86 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
90 #ifndef DO_FRAME_NOTES
91 #ifdef INCOMING_RETURN_ADDR_RTX
92 #define DO_FRAME_NOTES 1
94 #define DO_FRAME_NOTES 0
98 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
99 static void pa_combine_instructions PARAMS ((rtx));
100 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
101 static int forward_branch_p PARAMS ((rtx));
102 static int shadd_constant_p PARAMS ((int));
103 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
104 static int compute_movstrsi_length PARAMS ((rtx));
105 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
106 static void remove_useless_addtr_insns PARAMS ((rtx, int));
107 static void store_reg PARAMS ((int, int, int));
108 static void store_reg_modify PARAMS ((int, int, int));
109 static void load_reg PARAMS ((int, int, int));
110 static void set_reg_plus_d PARAMS ((int, int, int, int));
111 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
112 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
113 static int pa_adjust_priority PARAMS ((rtx, int));
114 static int pa_issue_rate PARAMS ((void));
115 static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
117 static void pa_encode_section_info PARAMS ((tree, int));
118 static const char *pa_strip_name_encoding PARAMS ((const char *));
119 static void pa_globalize_label PARAMS ((FILE *, const char *))
122 /* Save the operands last given to a compare for use when we
123 generate a scc or bcc insn. */
125 rtx hppa_compare_op0, hppa_compare_op1;
126 enum cmp_type hppa_branch_type;
128 /* Which cpu we are scheduling for. */
129 enum processor_type pa_cpu;
131 /* String to hold which cpu we are scheduling for. */
132 const char *pa_cpu_string;
134 /* Which architecture we are generating code for. */
135 enum architecture_type pa_arch;
137 /* String to hold which architecture we are generating code for. */
138 const char *pa_arch_string;
140 /* Counts for the number of callee-saved general and floating point
141 registers which were saved by the current function's prologue. */
142 static int gr_saved, fr_saved;
144 static rtx find_addr_reg PARAMS ((rtx));
146 /* Keep track of the number of bytes we have output in the CODE subspaces
147 during this compilation so we'll know when to emit inline long-calls. */
149 unsigned int total_code_bytes;
151 /* Variables to handle plabels that we discover are necessary at assembly
152 output time. They are output after the current function. */
154 struct deferred_plabel GTY(())
159 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
161 static size_t n_deferred_plabels = 0;
163 /* Initialize the GCC target structure. */
165 #undef TARGET_ASM_ALIGNED_HI_OP
166 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
167 #undef TARGET_ASM_ALIGNED_SI_OP
168 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
169 #undef TARGET_ASM_ALIGNED_DI_OP
170 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
171 #undef TARGET_ASM_UNALIGNED_HI_OP
172 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
173 #undef TARGET_ASM_UNALIGNED_SI_OP
174 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
175 #undef TARGET_ASM_UNALIGNED_DI_OP
176 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
177 #undef TARGET_ASM_INTEGER
178 #define TARGET_ASM_INTEGER pa_assemble_integer
180 #undef TARGET_ASM_FUNCTION_PROLOGUE
181 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
182 #undef TARGET_ASM_FUNCTION_EPILOGUE
183 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
185 #undef TARGET_SCHED_ADJUST_COST
186 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
187 #undef TARGET_SCHED_ADJUST_PRIORITY
188 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
189 #undef TARGET_SCHED_ISSUE_RATE
190 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
192 #undef TARGET_ENCODE_SECTION_INFO
193 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
194 #undef TARGET_STRIP_NAME_ENCODING
195 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
197 struct gcc_target targetm = TARGET_INITIALIZER;
202 if (pa_cpu_string == NULL)
203 pa_cpu_string = TARGET_SCHED_DEFAULT;
205 if (! strcmp (pa_cpu_string, "8000"))
207 pa_cpu_string = "8000";
208 pa_cpu = PROCESSOR_8000;
210 else if (! strcmp (pa_cpu_string, "7100"))
212 pa_cpu_string = "7100";
213 pa_cpu = PROCESSOR_7100;
215 else if (! strcmp (pa_cpu_string, "700"))
217 pa_cpu_string = "700";
218 pa_cpu = PROCESSOR_700;
220 else if (! strcmp (pa_cpu_string, "7100LC"))
222 pa_cpu_string = "7100LC";
223 pa_cpu = PROCESSOR_7100LC;
225 else if (! strcmp (pa_cpu_string, "7200"))
227 pa_cpu_string = "7200";
228 pa_cpu = PROCESSOR_7200;
230 else if (! strcmp (pa_cpu_string, "7300"))
232 pa_cpu_string = "7300";
233 pa_cpu = PROCESSOR_7300;
237 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
240 /* Set the instruction set architecture. */
241 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
243 pa_arch_string = "1.0";
244 pa_arch = ARCHITECTURE_10;
245 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
247 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
249 pa_arch_string = "1.1";
250 pa_arch = ARCHITECTURE_11;
251 target_flags &= ~MASK_PA_20;
252 target_flags |= MASK_PA_11;
254 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
256 pa_arch_string = "2.0";
257 pa_arch = ARCHITECTURE_20;
258 target_flags |= MASK_PA_11 | MASK_PA_20;
260 else if (pa_arch_string)
262 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
265 /* Unconditional branches in the delay slot are not compatible with dwarf2
266 call frame information. There is no benefit in using this optimization
267 on PA8000 and later processors. */
268 if (pa_cpu >= PROCESSOR_8000
269 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
270 || flag_unwind_tables)
271 target_flags &= ~MASK_JUMP_IN_DELAY;
273 if (flag_pic && TARGET_PORTABLE_RUNTIME)
275 warning ("PIC code generation is not supported in the portable runtime model\n");
278 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
280 warning ("PIC code generation is not compatible with fast indirect calls\n");
283 if (! TARGET_GAS && write_symbols != NO_DEBUG)
285 warning ("-g is only supported when using GAS on this processor,");
286 warning ("-g option disabled");
287 write_symbols = NO_DEBUG;
290 /* We only support the "big PIC" model now. And we always generate PIC
291 code when in 64bit mode. */
292 if (flag_pic == 1 || TARGET_64BIT)
295 /* We can't guarantee that .dword is available for 32-bit targets. */
296 if (UNITS_PER_WORD == 4)
297 targetm.asm_out.aligned_op.di = NULL;
299 /* The unaligned ops are only available when using GAS. */
302 targetm.asm_out.unaligned_op.hi = NULL;
303 targetm.asm_out.unaligned_op.si = NULL;
304 targetm.asm_out.unaligned_op.di = NULL;
308 /* Return nonzero only if OP is a register of mode MODE,
311 reg_or_0_operand (op, mode)
313 enum machine_mode mode;
315 return (op == CONST0_RTX (mode) || register_operand (op, mode));
318 /* Return nonzero if OP is suitable for use in a call to a named
321 For 2.5 try to eliminate either call_operand_address or
322 function_label_operand, they perform very similar functions. */
324 call_operand_address (op, mode)
326 enum machine_mode mode ATTRIBUTE_UNUSED;
328 return (GET_MODE (op) == word_mode
329 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
332 /* Return 1 if X contains a symbolic expression. We know these
333 expressions will have one of a few well defined forms, so
334 we need only check those forms. */
336 symbolic_expression_p (x)
340 /* Strip off any HIGH. */
341 if (GET_CODE (x) == HIGH)
344 return (symbolic_operand (x, VOIDmode));
348 symbolic_operand (op, mode)
350 enum machine_mode mode ATTRIBUTE_UNUSED;
352 switch (GET_CODE (op))
359 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
360 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
361 && GET_CODE (XEXP (op, 1)) == CONST_INT);
367 /* Return truth value of statement that OP is a symbolic memory
368 operand of mode MODE. */
371 symbolic_memory_operand (op, mode)
373 enum machine_mode mode ATTRIBUTE_UNUSED;
375 if (GET_CODE (op) == SUBREG)
376 op = SUBREG_REG (op);
377 if (GET_CODE (op) != MEM)
380 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
381 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
384 /* Return 1 if the operand is either a register or a memory operand that is
388 reg_or_nonsymb_mem_operand (op, mode)
390 enum machine_mode mode;
392 if (register_operand (op, mode))
395 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
401 /* Return 1 if the operand is either a register, zero, or a memory operand
402 that is not symbolic. */
405 reg_or_0_or_nonsymb_mem_operand (op, mode)
407 enum machine_mode mode;
409 if (register_operand (op, mode))
412 if (op == CONST0_RTX (mode))
415 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
421 /* Return 1 if the operand is a register operand or a non-symbolic memory
422 operand after reload. This predicate is used for branch patterns that
423 internally handle register reloading. We need to accept non-symbolic
424 memory operands after reload to ensure that the pattern is still valid
425 if reload didn't find a hard register for the operand. */
428 reg_before_reload_operand (op, mode)
430 enum machine_mode mode;
432 /* Don't accept a SUBREG since it will need a reload. */
433 if (GET_CODE (op) == SUBREG)
436 if (register_operand (op, mode))
440 && memory_operand (op, mode)
441 && ! symbolic_memory_operand (op, mode))
447 /* Accept any constant that can be moved in one instruction into a
450 cint_ok_for_move (intval)
451 HOST_WIDE_INT intval;
453 /* OK if ldo, ldil, or zdepi, can be used. */
454 return (CONST_OK_FOR_LETTER_P (intval, 'J')
455 || CONST_OK_FOR_LETTER_P (intval, 'N')
456 || CONST_OK_FOR_LETTER_P (intval, 'K'));
459 /* Accept anything that can be moved in one instruction into a general
462 move_operand (op, mode)
464 enum machine_mode mode;
466 if (register_operand (op, mode))
469 if (GET_CODE (op) == CONSTANT_P_RTX)
472 if (GET_CODE (op) == CONST_INT)
473 return cint_ok_for_move (INTVAL (op));
475 if (GET_CODE (op) == SUBREG)
476 op = SUBREG_REG (op);
477 if (GET_CODE (op) != MEM)
482 /* We consider a LO_SUM DLT reference a move_operand now since it has
483 been merged into the normal movsi/movdi patterns. */
484 if (GET_CODE (op) == LO_SUM
485 && GET_CODE (XEXP (op, 0)) == REG
486 && REG_OK_FOR_BASE_P (XEXP (op, 0))
487 && GET_CODE (XEXP (op, 1)) == UNSPEC
488 && GET_MODE (op) == Pmode)
491 /* Since move_operand is only used for source operands, we can always
492 allow scaled indexing! */
493 if (! TARGET_DISABLE_INDEXING
494 && GET_CODE (op) == PLUS
495 && ((GET_CODE (XEXP (op, 0)) == MULT
496 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
497 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
498 && INTVAL (XEXP (XEXP (op, 0), 1))
499 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
500 && GET_CODE (XEXP (op, 1)) == REG)
501 || (GET_CODE (XEXP (op, 1)) == MULT
502 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
503 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
504 && INTVAL (XEXP (XEXP (op, 1), 1))
505 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
506 && GET_CODE (XEXP (op, 0)) == REG)))
509 return memory_address_p (mode, op);
512 /* Accept REG and any CONST_INT that can be moved in one instruction into a
515 reg_or_cint_move_operand (op, mode)
517 enum machine_mode mode;
519 if (register_operand (op, mode))
522 if (GET_CODE (op) == CONST_INT)
523 return cint_ok_for_move (INTVAL (op));
529 pic_label_operand (op, mode)
531 enum machine_mode mode ATTRIBUTE_UNUSED;
536 switch (GET_CODE (op))
542 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
543 && GET_CODE (XEXP (op, 1)) == CONST_INT);
550 fp_reg_operand (op, mode)
552 enum machine_mode mode ATTRIBUTE_UNUSED;
554 return reg_renumber && FP_REG_P (op);
559 /* Return truth value of whether OP can be used as an operand in a
560 three operand arithmetic insn that accepts registers of mode MODE
561 or 14-bit signed integers. */
563 arith_operand (op, mode)
565 enum machine_mode mode;
567 return (register_operand (op, mode)
568 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
571 /* Return truth value of whether OP can be used as an operand in a
572 three operand arithmetic insn that accepts registers of mode MODE
573 or 11-bit signed integers. */
575 arith11_operand (op, mode)
577 enum machine_mode mode;
579 return (register_operand (op, mode)
580 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
583 /* Return truth value of whether OP can be used as an operand in a
586 adddi3_operand (op, mode)
588 enum machine_mode mode;
590 return (register_operand (op, mode)
591 || (GET_CODE (op) == CONST_INT
592 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
595 /* A constant integer suitable for use in a PRE_MODIFY memory
598 pre_cint_operand (op, mode)
600 enum machine_mode mode ATTRIBUTE_UNUSED;
602 return (GET_CODE (op) == CONST_INT
603 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
606 /* A constant integer suitable for use in a POST_MODIFY memory
609 post_cint_operand (op, mode)
611 enum machine_mode mode ATTRIBUTE_UNUSED;
613 return (GET_CODE (op) == CONST_INT
614 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
618 arith_double_operand (op, mode)
620 enum machine_mode mode;
622 return (register_operand (op, mode)
623 || (GET_CODE (op) == CONST_DOUBLE
624 && GET_MODE (op) == mode
625 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
626 && ((CONST_DOUBLE_HIGH (op) >= 0)
627 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
630 /* Return truth value of whether OP is an integer which fits the
631 range constraining immediate operands in three-address insns, or
632 is an integer register. */
635 ireg_or_int5_operand (op, mode)
637 enum machine_mode mode ATTRIBUTE_UNUSED;
639 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
640 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
643 /* Return nonzero if OP is an integer register, else return zero. */
645 ireg_operand (op, mode)
647 enum machine_mode mode ATTRIBUTE_UNUSED;
649 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
652 /* Return truth value of whether OP is an integer which fits the
653 range constraining immediate operands in three-address insns. */
656 int5_operand (op, mode)
658 enum machine_mode mode ATTRIBUTE_UNUSED;
660 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
664 uint5_operand (op, mode)
666 enum machine_mode mode ATTRIBUTE_UNUSED;
668 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
672 int11_operand (op, mode)
674 enum machine_mode mode ATTRIBUTE_UNUSED;
676 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
680 uint32_operand (op, mode)
682 enum machine_mode mode ATTRIBUTE_UNUSED;
684 #if HOST_BITS_PER_WIDE_INT > 32
685 /* All allowed constants will fit a CONST_INT. */
686 return (GET_CODE (op) == CONST_INT
687 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
689 return (GET_CODE (op) == CONST_INT
690 || (GET_CODE (op) == CONST_DOUBLE
691 && CONST_DOUBLE_HIGH (op) == 0));
696 arith5_operand (op, mode)
698 enum machine_mode mode;
700 return register_operand (op, mode) || int5_operand (op, mode);
703 /* True iff zdepi can be used to generate this CONST_INT.
704 zdepi first sign extends a 5 bit signed number to a given field
705 length, then places this field anywhere in a zero. */
708 unsigned HOST_WIDE_INT x;
710 unsigned HOST_WIDE_INT lsb_mask, t;
712 /* This might not be obvious, but it's at least fast.
713 This function is critical; we don't have the time loops would take. */
715 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
716 /* Return true iff t is a power of two. */
717 return ((t & (t - 1)) == 0);
720 /* True iff depi or extru can be used to compute (reg & mask).
721 Accept bit pattern like these:
727 unsigned HOST_WIDE_INT mask;
730 mask += mask & -mask;
731 return (mask & (mask - 1)) == 0;
734 /* True iff depi or extru can be used to compute (reg & OP). */
736 and_operand (op, mode)
738 enum machine_mode mode;
740 return (register_operand (op, mode)
741 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
744 /* True iff depi can be used to compute (reg | MASK). */
747 unsigned HOST_WIDE_INT mask;
749 mask += mask & -mask;
750 return (mask & (mask - 1)) == 0;
753 /* True iff depi can be used to compute (reg | OP). */
755 ior_operand (op, mode)
757 enum machine_mode mode ATTRIBUTE_UNUSED;
759 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
763 lhs_lshift_operand (op, mode)
765 enum machine_mode mode;
767 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
770 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
771 Such values can be the left hand side x in (x << r), using the zvdepi
774 lhs_lshift_cint_operand (op, mode)
776 enum machine_mode mode ATTRIBUTE_UNUSED;
778 unsigned HOST_WIDE_INT x;
779 if (GET_CODE (op) != CONST_INT)
781 x = INTVAL (op) >> 4;
782 return (x & (x + 1)) == 0;
786 arith32_operand (op, mode)
788 enum machine_mode mode;
790 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
794 pc_or_label_operand (op, mode)
796 enum machine_mode mode ATTRIBUTE_UNUSED;
798 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
801 /* Legitimize PIC addresses. If the address is already
802 position-independent, we return ORIG. Newly generated
803 position-independent addresses go to REG. If we need more
804 than one register, we lose. */
807 legitimize_pic_address (orig, mode, reg)
809 enum machine_mode mode;
813 /* Labels need special handling. */
814 if (pic_label_operand (orig, mode))
816 /* We do not want to go through the movXX expanders here since that
817 would create recursion.
819 Nor do we really want to call a generator for a named pattern
820 since that requires multiple patterns if we want to support
823 So instead we just emit the raw set, which avoids the movXX
824 expanders completely. */
825 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
826 current_function_uses_pic_offset_table = 1;
829 if (GET_CODE (orig) == SYMBOL_REF)
835 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
836 gen_rtx_HIGH (word_mode, orig)));
838 = gen_rtx_MEM (Pmode,
839 gen_rtx_LO_SUM (Pmode, reg,
840 gen_rtx_UNSPEC (Pmode,
844 current_function_uses_pic_offset_table = 1;
845 RTX_UNCHANGING_P (pic_ref) = 1;
846 emit_move_insn (reg, pic_ref);
849 else if (GET_CODE (orig) == CONST)
853 if (GET_CODE (XEXP (orig, 0)) == PLUS
854 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
860 if (GET_CODE (XEXP (orig, 0)) == PLUS)
862 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
863 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
864 base == reg ? 0 : reg);
867 if (GET_CODE (orig) == CONST_INT)
869 if (INT_14_BITS (orig))
870 return plus_constant (base, INTVAL (orig));
871 orig = force_reg (Pmode, orig);
873 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
874 /* Likewise, should we set special REG_NOTEs here? */
879 /* Try machine-dependent ways of modifying an illegitimate address
880 to be legitimate. If we find one, return the new, valid address.
881 This macro is used in only one place: `memory_address' in explow.c.
883 OLDX is the address as it was before break_out_memory_refs was called.
884 In some cases it is useful to look at this to decide what needs to be done.
886 MODE and WIN are passed so that this macro can use
887 GO_IF_LEGITIMATE_ADDRESS.
889 It is always safe for this macro to do nothing. It exists to recognize
890 opportunities to optimize the output.
892 For the PA, transform:
894 memory(X + <large int>)
898 if (<large int> & mask) >= 16
899 Y = (<large int> & ~mask) + mask + 1 Round up.
901 Y = (<large int> & ~mask) Round down.
903 memory (Z + (<large int> - Y));
905 This is for CSE to find several similar references, and only use one Z.
907 X can either be a SYMBOL_REF or REG, but because combine can not
908 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
909 D will not fit in 14 bits.
911 MODE_FLOAT references allow displacements which fit in 5 bits, so use
914 MODE_INT references allow displacements which fit in 14 bits, so use
917 This relies on the fact that most mode MODE_FLOAT references will use FP
918 registers and most mode MODE_INT references will use integer registers.
919 (In the rare case of an FP register used in an integer MODE, we depend
920 on secondary reloads to clean things up.)
923 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
924 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
925 addressing modes to be used).
927 Put X and Z into registers. Then put the entire expression into
931 hppa_legitimize_address (x, oldx, mode)
932 rtx x, oldx ATTRIBUTE_UNUSED;
933 enum machine_mode mode;
938 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
940 /* Strip off CONST. */
941 if (GET_CODE (x) == CONST)
944 /* Special case. Get the SYMBOL_REF into a register and use indexing.
945 That should always be safe. */
946 if (GET_CODE (x) == PLUS
947 && GET_CODE (XEXP (x, 0)) == REG
948 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
950 rtx reg = force_reg (Pmode, XEXP (x, 1));
951 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
954 /* Note we must reject symbols which represent function addresses
955 since the assembler/linker can't handle arithmetic on plabels. */
956 if (GET_CODE (x) == PLUS
957 && GET_CODE (XEXP (x, 1)) == CONST_INT
958 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
959 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
960 || GET_CODE (XEXP (x, 0)) == REG))
962 rtx int_part, ptr_reg;
964 int offset = INTVAL (XEXP (x, 1));
967 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
968 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
970 /* Choose which way to round the offset. Round up if we
971 are >= halfway to the next boundary. */
972 if ((offset & mask) >= ((mask + 1) / 2))
973 newoffset = (offset & ~ mask) + mask + 1;
975 newoffset = (offset & ~ mask);
977 /* If the newoffset will not fit in 14 bits (ldo), then
978 handling this would take 4 or 5 instructions (2 to load
979 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
980 add the new offset and the SYMBOL_REF.) Combine can
981 not handle 4->2 or 5->2 combinations, so do not create
983 if (! VAL_14_BITS_P (newoffset)
984 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
986 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
989 gen_rtx_HIGH (Pmode, const_part));
992 gen_rtx_LO_SUM (Pmode,
993 tmp_reg, const_part));
997 if (! VAL_14_BITS_P (newoffset))
998 int_part = force_reg (Pmode, GEN_INT (newoffset));
1000 int_part = GEN_INT (newoffset);
1002 ptr_reg = force_reg (Pmode,
1003 gen_rtx_PLUS (Pmode,
1004 force_reg (Pmode, XEXP (x, 0)),
1007 return plus_constant (ptr_reg, offset - newoffset);
1010 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1012 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1013 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1014 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1015 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
1016 || GET_CODE (XEXP (x, 1)) == SUBREG)
1017 && GET_CODE (XEXP (x, 1)) != CONST)
1019 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1023 if (GET_CODE (reg1) != REG)
1024 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1026 reg2 = XEXP (XEXP (x, 0), 0);
1027 if (GET_CODE (reg2) != REG)
1028 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1030 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1031 gen_rtx_MULT (Pmode,
1037 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1039 Only do so for floating point modes since this is more speculative
1040 and we lose if it's an integer store. */
1041 if (GET_CODE (x) == PLUS
1042 && GET_CODE (XEXP (x, 0)) == PLUS
1043 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1044 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1045 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1046 && (mode == SFmode || mode == DFmode))
1049 /* First, try and figure out what to use as a base register. */
1050 rtx reg1, reg2, base, idx, orig_base;
1052 reg1 = XEXP (XEXP (x, 0), 1);
1057 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1058 then emit_move_sequence will turn on REG_POINTER so we'll know
1059 it's a base register below. */
1060 if (GET_CODE (reg1) != REG)
1061 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1063 if (GET_CODE (reg2) != REG)
1064 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1066 /* Figure out what the base and index are. */
1068 if (GET_CODE (reg1) == REG
1069 && REG_POINTER (reg1))
1072 orig_base = XEXP (XEXP (x, 0), 1);
1073 idx = gen_rtx_PLUS (Pmode,
1074 gen_rtx_MULT (Pmode,
1075 XEXP (XEXP (XEXP (x, 0), 0), 0),
1076 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1079 else if (GET_CODE (reg2) == REG
1080 && REG_POINTER (reg2))
1083 orig_base = XEXP (x, 1);
1090 /* If the index adds a large constant, try to scale the
1091 constant so that it can be loaded with only one insn. */
1092 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1093 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1094 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1095 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1097 /* Divide the CONST_INT by the scale factor, then add it to A. */
1098 int val = INTVAL (XEXP (idx, 1));
1100 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1101 reg1 = XEXP (XEXP (idx, 0), 0);
1102 if (GET_CODE (reg1) != REG)
1103 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1105 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1107 /* We can now generate a simple scaled indexed address. */
1110 (Pmode, gen_rtx_PLUS (Pmode,
1111 gen_rtx_MULT (Pmode, reg1,
1112 XEXP (XEXP (idx, 0), 1)),
1116 /* If B + C is still a valid base register, then add them. */
1117 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1118 && INTVAL (XEXP (idx, 1)) <= 4096
1119 && INTVAL (XEXP (idx, 1)) >= -4096)
1121 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1124 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1126 reg2 = XEXP (XEXP (idx, 0), 0);
1127 if (GET_CODE (reg2) != CONST_INT)
1128 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1130 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1131 gen_rtx_MULT (Pmode,
1137 /* Get the index into a register, then add the base + index and
1138 return a register holding the result. */
1140 /* First get A into a register. */
1141 reg1 = XEXP (XEXP (idx, 0), 0);
1142 if (GET_CODE (reg1) != REG)
1143 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1145 /* And get B into a register. */
1146 reg2 = XEXP (idx, 1);
1147 if (GET_CODE (reg2) != REG)
1148 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1150 reg1 = force_reg (Pmode,
1151 gen_rtx_PLUS (Pmode,
1152 gen_rtx_MULT (Pmode, reg1,
1153 XEXP (XEXP (idx, 0), 1)),
1156 /* Add the result to our base register and return. */
1157 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1161 /* Uh-oh. We might have an address for x[n-100000]. This needs
1162 special handling to avoid creating an indexed memory address
1163 with x-100000 as the base.
1165 If the constant part is small enough, then it's still safe because
1166 there is a guard page at the beginning and end of the data segment.
1168 Scaled references are common enough that we want to try and rearrange the
1169 terms so that we can use indexing for these addresses too. Only
1170 do the optimization for floatint point modes. */
1172 if (GET_CODE (x) == PLUS
1173 && symbolic_expression_p (XEXP (x, 1)))
1175 /* Ugly. We modify things here so that the address offset specified
1176 by the index expression is computed first, then added to x to form
1177 the entire address. */
1179 rtx regx1, regx2, regy1, regy2, y;
1181 /* Strip off any CONST. */
1183 if (GET_CODE (y) == CONST)
1186 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1188 /* See if this looks like
1189 (plus (mult (reg) (shadd_const))
1190 (const (plus (symbol_ref) (const_int))))
1192 Where const_int is small. In that case the const
1193 expression is a valid pointer for indexing.
1195 If const_int is big, but can be divided evenly by shadd_const
1196 and added to (reg). This allows more scaled indexed addresses. */
1197 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1198 && GET_CODE (XEXP (x, 0)) == MULT
1199 && GET_CODE (XEXP (y, 1)) == CONST_INT
1200 && INTVAL (XEXP (y, 1)) >= -4096
1201 && INTVAL (XEXP (y, 1)) <= 4095
1202 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1203 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1205 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1209 if (GET_CODE (reg1) != REG)
1210 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1212 reg2 = XEXP (XEXP (x, 0), 0);
1213 if (GET_CODE (reg2) != REG)
1214 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1216 return force_reg (Pmode,
1217 gen_rtx_PLUS (Pmode,
1218 gen_rtx_MULT (Pmode,
1223 else if ((mode == DFmode || mode == SFmode)
1224 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1225 && GET_CODE (XEXP (x, 0)) == MULT
1226 && GET_CODE (XEXP (y, 1)) == CONST_INT
1227 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1228 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1229 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1232 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1233 / INTVAL (XEXP (XEXP (x, 0), 1))));
1234 regx2 = XEXP (XEXP (x, 0), 0);
1235 if (GET_CODE (regx2) != REG)
1236 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1237 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1241 gen_rtx_PLUS (Pmode,
1242 gen_rtx_MULT (Pmode, regx2,
1243 XEXP (XEXP (x, 0), 1)),
1244 force_reg (Pmode, XEXP (y, 0))));
1246 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1247 && INTVAL (XEXP (y, 1)) >= -4096
1248 && INTVAL (XEXP (y, 1)) <= 4095)
1250 /* This is safe because of the guard page at the
1251 beginning and end of the data space. Just
1252 return the original address. */
1257 /* Doesn't look like one we can optimize. */
1258 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1259 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1260 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1261 regx1 = force_reg (Pmode,
1262 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1264 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1272 /* For the HPPA, REG and REG+CONST is cost 0
1273 and addresses involving symbolic constants are cost 2.
1275 PIC addresses are very expensive.
1277 It is no coincidence that this has the same structure
1278 as GO_IF_LEGITIMATE_ADDRESS. */
1280 hppa_address_cost (X)
1283 if (GET_CODE (X) == PLUS)
1285 else if (GET_CODE (X) == LO_SUM)
1287 else if (GET_CODE (X) == HIGH)
1292 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1293 new rtx with the correct mode. */
1295 force_mode (mode, orig)
1296 enum machine_mode mode;
1299 if (mode == GET_MODE (orig))
1302 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1305 return gen_rtx_REG (mode, REGNO (orig));
1308 /* Emit insns to move operands[1] into operands[0].
1310 Return 1 if we have written out everything that needs to be done to
1311 do the move. Otherwise, return 0 and the caller will emit the move
1314 Note SCRATCH_REG may not be in the proper mode depending on how it
1315 will be used. This routine is resposible for creating a new copy
1316 of SCRATCH_REG in the proper mode. */
1319 emit_move_sequence (operands, mode, scratch_reg)
1321 enum machine_mode mode;
1324 register rtx operand0 = operands[0];
1325 register rtx operand1 = operands[1];
1329 && reload_in_progress && GET_CODE (operand0) == REG
1330 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1331 operand0 = reg_equiv_mem[REGNO (operand0)];
1332 else if (scratch_reg
1333 && reload_in_progress && GET_CODE (operand0) == SUBREG
1334 && GET_CODE (SUBREG_REG (operand0)) == REG
1335 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1337 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1338 the code which tracks sets/uses for delete_output_reload. */
1339 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1340 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1341 SUBREG_BYTE (operand0));
1342 operand0 = alter_subreg (&temp);
1346 && reload_in_progress && GET_CODE (operand1) == REG
1347 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1348 operand1 = reg_equiv_mem[REGNO (operand1)];
1349 else if (scratch_reg
1350 && reload_in_progress && GET_CODE (operand1) == SUBREG
1351 && GET_CODE (SUBREG_REG (operand1)) == REG
1352 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1354 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1355 the code which tracks sets/uses for delete_output_reload. */
1356 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1357 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1358 SUBREG_BYTE (operand1));
1359 operand1 = alter_subreg (&temp);
1362 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1363 && ((tem = find_replacement (&XEXP (operand0, 0)))
1364 != XEXP (operand0, 0)))
1365 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1366 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1367 && ((tem = find_replacement (&XEXP (operand1, 0)))
1368 != XEXP (operand1, 0)))
1369 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1371 /* Handle secondary reloads for loads/stores of FP registers from
1372 REG+D addresses where D does not fit in 5 bits, including
1373 (subreg (mem (addr))) cases. */
1374 if (fp_reg_operand (operand0, mode)
1375 && ((GET_CODE (operand1) == MEM
1376 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1377 || ((GET_CODE (operand1) == SUBREG
1378 && GET_CODE (XEXP (operand1, 0)) == MEM
1379 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1382 if (GET_CODE (operand1) == SUBREG)
1383 operand1 = XEXP (operand1, 0);
1385 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1386 it in WORD_MODE regardless of what mode it was originally given
1388 scratch_reg = force_mode (word_mode, scratch_reg);
1390 /* D might not fit in 14 bits either; for such cases load D into
1392 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1394 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1395 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1397 XEXP (XEXP (operand1, 0), 0),
1401 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1402 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1403 gen_rtx_MEM (mode, scratch_reg)));
1406 else if (fp_reg_operand (operand1, mode)
1407 && ((GET_CODE (operand0) == MEM
1408 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1409 || ((GET_CODE (operand0) == SUBREG)
1410 && GET_CODE (XEXP (operand0, 0)) == MEM
1411 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1414 if (GET_CODE (operand0) == SUBREG)
1415 operand0 = XEXP (operand0, 0);
1417 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1418 it in WORD_MODE regardless of what mode it was originally given
1420 scratch_reg = force_mode (word_mode, scratch_reg);
1422 /* D might not fit in 14 bits either; for such cases load D into
1424 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1426 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1427 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1430 XEXP (XEXP (operand0, 0),
1435 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1436 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1440 /* Handle secondary reloads for loads of FP registers from constant
1441 expressions by forcing the constant into memory.
1443 use scratch_reg to hold the address of the memory location.
1445 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1446 NO_REGS when presented with a const_int and an register class
1447 containing only FP registers. Doing so unfortunately creates
1448 more problems than it solves. Fix this for 2.5. */
1449 else if (fp_reg_operand (operand0, mode)
1450 && CONSTANT_P (operand1)
1455 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1456 it in WORD_MODE regardless of what mode it was originally given
1458 scratch_reg = force_mode (word_mode, scratch_reg);
1460 /* Force the constant into memory and put the address of the
1461 memory location into scratch_reg. */
1462 xoperands[0] = scratch_reg;
1463 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1464 emit_move_sequence (xoperands, Pmode, 0);
1466 /* Now load the destination register. */
1467 emit_insn (gen_rtx_SET (mode, operand0,
1468 gen_rtx_MEM (mode, scratch_reg)));
1471 /* Handle secondary reloads for SAR. These occur when trying to load
1472 the SAR from memory, FP register, or with a constant. */
1473 else if (GET_CODE (operand0) == REG
1474 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1475 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1476 && (GET_CODE (operand1) == MEM
1477 || GET_CODE (operand1) == CONST_INT
1478 || (GET_CODE (operand1) == REG
1479 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1482 /* D might not fit in 14 bits either; for such cases load D into
1484 if (GET_CODE (operand1) == MEM
1485 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1487 /* We are reloading the address into the scratch register, so we
1488 want to make sure the scratch register is a full register. */
1489 scratch_reg = force_mode (word_mode, scratch_reg);
1491 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1492 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1495 XEXP (XEXP (operand1, 0),
1499 /* Now we are going to load the scratch register from memory,
1500 we want to load it in the same width as the original MEM,
1501 which must be the same as the width of the ultimate destination,
1503 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1505 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1510 /* We want to load the scratch register using the same mode as
1511 the ultimate destination. */
1512 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1514 emit_move_insn (scratch_reg, operand1);
1517 /* And emit the insn to set the ultimate destination. We know that
1518 the scratch register has the same mode as the destination at this
1520 emit_move_insn (operand0, scratch_reg);
1523 /* Handle most common case: storing into a register. */
1524 else if (register_operand (operand0, mode))
1526 if (register_operand (operand1, mode)
1527 || (GET_CODE (operand1) == CONST_INT
1528 && cint_ok_for_move (INTVAL (operand1)))
1529 || (operand1 == CONST0_RTX (mode))
1530 || (GET_CODE (operand1) == HIGH
1531 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1532 /* Only `general_operands' can come here, so MEM is ok. */
1533 || GET_CODE (operand1) == MEM)
1535 /* Run this case quickly. */
1536 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1540 else if (GET_CODE (operand0) == MEM)
1542 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1543 && !(reload_in_progress || reload_completed))
1545 rtx temp = gen_reg_rtx (DFmode);
1547 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1548 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1551 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1553 /* Run this case quickly. */
1554 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1557 if (! (reload_in_progress || reload_completed))
1559 operands[0] = validize_mem (operand0);
1560 operands[1] = operand1 = force_reg (mode, operand1);
1564 /* Simplify the source if we need to.
1565 Note we do have to handle function labels here, even though we do
1566 not consider them legitimate constants. Loop optimizations can
1567 call the emit_move_xxx with one as a source. */
1568 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1569 || function_label_operand (operand1, mode)
1570 || (GET_CODE (operand1) == HIGH
1571 && symbolic_operand (XEXP (operand1, 0), mode)))
1575 if (GET_CODE (operand1) == HIGH)
1578 operand1 = XEXP (operand1, 0);
1580 if (symbolic_operand (operand1, mode))
1582 /* Argh. The assembler and linker can't handle arithmetic
1585 So we force the plabel into memory, load operand0 from
1586 the memory location, then add in the constant part. */
1587 if ((GET_CODE (operand1) == CONST
1588 && GET_CODE (XEXP (operand1, 0)) == PLUS
1589 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1590 || function_label_operand (operand1, mode))
1592 rtx temp, const_part;
1594 /* Figure out what (if any) scratch register to use. */
1595 if (reload_in_progress || reload_completed)
1597 scratch_reg = scratch_reg ? scratch_reg : operand0;
1598 /* SCRATCH_REG will hold an address and maybe the actual
1599 data. We want it in WORD_MODE regardless of what mode it
1600 was originally given to us. */
1601 scratch_reg = force_mode (word_mode, scratch_reg);
1604 scratch_reg = gen_reg_rtx (Pmode);
1606 if (GET_CODE (operand1) == CONST)
1608 /* Save away the constant part of the expression. */
1609 const_part = XEXP (XEXP (operand1, 0), 1);
1610 if (GET_CODE (const_part) != CONST_INT)
1613 /* Force the function label into memory. */
1614 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1618 /* No constant part. */
1619 const_part = NULL_RTX;
1621 /* Force the function label into memory. */
1622 temp = force_const_mem (mode, operand1);
1626 /* Get the address of the memory location. PIC-ify it if
1628 temp = XEXP (temp, 0);
1630 temp = legitimize_pic_address (temp, mode, scratch_reg);
1632 /* Put the address of the memory location into our destination
1635 emit_move_sequence (operands, mode, scratch_reg);
1637 /* Now load from the memory location into our destination
1639 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1640 emit_move_sequence (operands, mode, scratch_reg);
1642 /* And add back in the constant part. */
1643 if (const_part != NULL_RTX)
1644 expand_inc (operand0, const_part);
1653 if (reload_in_progress || reload_completed)
1655 temp = scratch_reg ? scratch_reg : operand0;
1656 /* TEMP will hold an address and maybe the actual
1657 data. We want it in WORD_MODE regardless of what mode it
1658 was originally given to us. */
1659 temp = force_mode (word_mode, temp);
1662 temp = gen_reg_rtx (Pmode);
1664 /* (const (plus (symbol) (const_int))) must be forced to
1665 memory during/after reload if the const_int will not fit
1667 if (GET_CODE (operand1) == CONST
1668 && GET_CODE (XEXP (operand1, 0)) == PLUS
1669 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1670 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1671 && (reload_completed || reload_in_progress)
1674 operands[1] = force_const_mem (mode, operand1);
1675 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1677 emit_move_sequence (operands, mode, temp);
1681 operands[1] = legitimize_pic_address (operand1, mode, temp);
1682 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1685 /* On the HPPA, references to data space are supposed to use dp,
1686 register 27, but showing it in the RTL inhibits various cse
1687 and loop optimizations. */
1692 if (reload_in_progress || reload_completed)
1694 temp = scratch_reg ? scratch_reg : operand0;
1695 /* TEMP will hold an address and maybe the actual
1696 data. We want it in WORD_MODE regardless of what mode it
1697 was originally given to us. */
1698 temp = force_mode (word_mode, temp);
1701 temp = gen_reg_rtx (mode);
1703 /* Loading a SYMBOL_REF into a register makes that register
1704 safe to be used as the base in an indexed address.
1706 Don't mark hard registers though. That loses. */
1707 if (GET_CODE (operand0) == REG
1708 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1709 REG_POINTER (operand0) = 1;
1710 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1711 REG_POINTER (temp) = 1;
1713 set = gen_rtx_SET (mode, operand0, temp);
1715 set = gen_rtx_SET (VOIDmode,
1717 gen_rtx_LO_SUM (mode, temp, operand1));
1719 emit_insn (gen_rtx_SET (VOIDmode,
1721 gen_rtx_HIGH (mode, operand1)));
1727 else if (GET_CODE (operand1) != CONST_INT
1728 || ! cint_ok_for_move (INTVAL (operand1)))
1730 rtx extend = NULL_RTX;
1733 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1734 && HOST_BITS_PER_WIDE_INT > 32
1735 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1737 HOST_WIDE_INT val = INTVAL (operand1);
1740 /* Extract the low order 32 bits of the value and sign extend.
1741 If the new value is the same as the original value, we can
1742 can use the original value as-is. If the new value is
1743 different, we use it and insert the most-significant 32-bits
1744 of the original value into the final result. */
1745 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1746 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1749 #if HOST_BITS_PER_WIDE_INT > 32
1750 extend = GEN_INT (val >> 32);
1752 operand1 = GEN_INT (nval);
1756 if (reload_in_progress || reload_completed)
1759 temp = gen_reg_rtx (mode);
1761 /* We don't directly split DImode constants on 32-bit targets
1762 because PLUS uses an 11-bit immediate and the insn sequence
1763 generated is not as efficient as the one using HIGH/LO_SUM. */
1764 if (GET_CODE (operand1) == CONST_INT
1765 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1767 /* Directly break constant into high and low parts. This
1768 provides better optimization opportunities because various
1769 passes recognize constants split with PLUS but not LO_SUM.
1770 We use a 14-bit signed low part except when the addition
1771 of 0x4000 to the high part might change the sign of the
1773 HOST_WIDE_INT value = INTVAL (operand1);
1774 HOST_WIDE_INT low = value & 0x3fff;
1775 HOST_WIDE_INT high = value & ~ 0x3fff;
1779 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1787 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1788 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1792 emit_insn (gen_rtx_SET (VOIDmode, temp,
1793 gen_rtx_HIGH (mode, operand1)));
1794 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1797 emit_move_insn (operands[0], operands[1]);
1799 if (extend != NULL_RTX)
1800 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1806 /* Now have insn-emit do whatever it normally does. */
1810 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1811 it will need a link/runtime reloc). */
1819 switch (TREE_CODE (exp))
1826 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1827 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1832 case NON_LVALUE_EXPR:
1833 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1839 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1840 if (TREE_VALUE (link) != 0)
1841 reloc |= reloc_needed (TREE_VALUE (link));
1854 /* Does operand (which is a symbolic_operand) live in text space?
1855 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
1859 read_only_operand (operand, mode)
1861 enum machine_mode mode ATTRIBUTE_UNUSED;
1863 if (GET_CODE (operand) == CONST)
1864 operand = XEXP (XEXP (operand, 0), 0);
1867 if (GET_CODE (operand) == SYMBOL_REF)
1868 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1872 if (GET_CODE (operand) == SYMBOL_REF)
1873 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1879 /* Return the best assembler insn template
1880 for moving operands[1] into operands[0] as a fullword. */
1882 singlemove_string (operands)
1885 HOST_WIDE_INT intval;
1887 if (GET_CODE (operands[0]) == MEM)
1888 return "stw %r1,%0";
1889 if (GET_CODE (operands[1]) == MEM)
1891 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1896 if (GET_MODE (operands[1]) != SFmode)
1899 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1901 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1902 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1904 operands[1] = GEN_INT (i);
1905 /* Fall through to CONST_INT case. */
1907 if (GET_CODE (operands[1]) == CONST_INT)
1909 intval = INTVAL (operands[1]);
1911 if (VAL_14_BITS_P (intval))
1913 else if ((intval & 0x7ff) == 0)
1914 return "ldil L'%1,%0";
1915 else if (zdepi_cint_p (intval))
1916 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1918 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1920 return "copy %1,%0";
1924 /* Compute position (in OP[1]) and width (in OP[2])
1925 useful for copying IMM to a register using the zdepi
1926 instructions. Store the immediate value to insert in OP[0]. */
1928 compute_zdepwi_operands (imm, op)
1929 unsigned HOST_WIDE_INT imm;
1934 /* Find the least significant set bit in IMM. */
1935 for (lsb = 0; lsb < 32; lsb++)
1942 /* Choose variants based on *sign* of the 5-bit field. */
1943 if ((imm & 0x10) == 0)
1944 len = (lsb <= 28) ? 4 : 32 - lsb;
1947 /* Find the width of the bitstring in IMM. */
1948 for (len = 5; len < 32; len++)
1950 if ((imm & (1 << len)) == 0)
1954 /* Sign extend IMM as a 5-bit value. */
1955 imm = (imm & 0xf) - 0x10;
1963 /* Compute position (in OP[1]) and width (in OP[2])
1964 useful for copying IMM to a register using the depdi,z
1965 instructions. Store the immediate value to insert in OP[0]. */
1967 compute_zdepdi_operands (imm, op)
1968 unsigned HOST_WIDE_INT imm;
1971 HOST_WIDE_INT lsb, len;
1973 /* Find the least significant set bit in IMM. */
1974 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1981 /* Choose variants based on *sign* of the 5-bit field. */
1982 if ((imm & 0x10) == 0)
1983 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1984 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1987 /* Find the width of the bitstring in IMM. */
1988 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1990 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
1994 /* Sign extend IMM as a 5-bit value. */
1995 imm = (imm & 0xf) - 0x10;
2003 /* Output assembler code to perform a doubleword move insn
2004 with operands OPERANDS. */
2007 output_move_double (operands)
2010 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2012 rtx addreg0 = 0, addreg1 = 0;
2014 /* First classify both operands. */
2016 if (REG_P (operands[0]))
2018 else if (offsettable_memref_p (operands[0]))
2020 else if (GET_CODE (operands[0]) == MEM)
2025 if (REG_P (operands[1]))
2027 else if (CONSTANT_P (operands[1]))
2029 else if (offsettable_memref_p (operands[1]))
2031 else if (GET_CODE (operands[1]) == MEM)
2036 /* Check for the cases that the operand constraints are not
2037 supposed to allow to happen. Abort if we get one,
2038 because generating code for these cases is painful. */
2040 if (optype0 != REGOP && optype1 != REGOP)
2043 /* Handle auto decrementing and incrementing loads and stores
2044 specifically, since the structure of the function doesn't work
2045 for them without major modification. Do it better when we learn
2046 this port about the general inc/dec addressing of PA.
2047 (This was written by tege. Chide him if it doesn't work.) */
2049 if (optype0 == MEMOP)
2051 /* We have to output the address syntax ourselves, since print_operand
2052 doesn't deal with the addresses we want to use. Fix this later. */
2054 rtx addr = XEXP (operands[0], 0);
2055 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2057 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2059 operands[0] = XEXP (addr, 0);
2060 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2063 if (!reg_overlap_mentioned_p (high_reg, addr))
2065 /* No overlap between high target register and address
2066 register. (We do this in a non-obvious way to
2067 save a register file writeback) */
2068 if (GET_CODE (addr) == POST_INC)
2069 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2070 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2075 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2077 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2079 operands[0] = XEXP (addr, 0);
2080 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2083 if (!reg_overlap_mentioned_p (high_reg, addr))
2085 /* No overlap between high target register and address
2086 register. (We do this in a non-obvious way to
2087 save a register file writeback) */
2088 if (GET_CODE (addr) == PRE_INC)
2089 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2090 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2096 if (optype1 == MEMOP)
2098 /* We have to output the address syntax ourselves, since print_operand
2099 doesn't deal with the addresses we want to use. Fix this later. */
2101 rtx addr = XEXP (operands[1], 0);
2102 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2104 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2106 operands[1] = XEXP (addr, 0);
2107 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2110 if (!reg_overlap_mentioned_p (high_reg, addr))
2112 /* No overlap between high target register and address
2113 register. (We do this in a non-obvious way to
2114 save a register file writeback) */
2115 if (GET_CODE (addr) == POST_INC)
2116 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2117 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2121 /* This is an undefined situation. We should load into the
2122 address register *and* update that register. Probably
2123 we don't need to handle this at all. */
2124 if (GET_CODE (addr) == POST_INC)
2125 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2126 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2129 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2131 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2133 operands[1] = XEXP (addr, 0);
2134 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2137 if (!reg_overlap_mentioned_p (high_reg, addr))
2139 /* No overlap between high target register and address
2140 register. (We do this in a non-obvious way to
2141 save a register file writeback) */
2142 if (GET_CODE (addr) == PRE_INC)
2143 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2144 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2148 /* This is an undefined situation. We should load into the
2149 address register *and* update that register. Probably
2150 we don't need to handle this at all. */
2151 if (GET_CODE (addr) == PRE_INC)
2152 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2153 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2156 else if (GET_CODE (addr) == PLUS
2157 && GET_CODE (XEXP (addr, 0)) == MULT)
2159 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2161 if (!reg_overlap_mentioned_p (high_reg, addr))
2165 xoperands[0] = high_reg;
2166 xoperands[1] = XEXP (addr, 1);
2167 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2168 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2169 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2171 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2177 xoperands[0] = high_reg;
2178 xoperands[1] = XEXP (addr, 1);
2179 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2180 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2181 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2183 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2188 /* If an operand is an unoffsettable memory ref, find a register
2189 we can increment temporarily to make it refer to the second word. */
2191 if (optype0 == MEMOP)
2192 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2194 if (optype1 == MEMOP)
2195 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2197 /* Ok, we can do one word at a time.
2198 Normally we do the low-numbered word first.
2200 In either case, set up in LATEHALF the operands to use
2201 for the high-numbered word and in some cases alter the
2202 operands in OPERANDS to be suitable for the low-numbered word. */
2204 if (optype0 == REGOP)
2205 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2206 else if (optype0 == OFFSOP)
2207 latehalf[0] = adjust_address (operands[0], SImode, 4);
2209 latehalf[0] = operands[0];
2211 if (optype1 == REGOP)
2212 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2213 else if (optype1 == OFFSOP)
2214 latehalf[1] = adjust_address (operands[1], SImode, 4);
2215 else if (optype1 == CNSTOP)
2216 split_double (operands[1], &operands[1], &latehalf[1]);
2218 latehalf[1] = operands[1];
2220 /* If the first move would clobber the source of the second one,
2221 do them in the other order.
2223 This can happen in two cases:
2225 mem -> register where the first half of the destination register
2226 is the same register used in the memory's address. Reload
2227 can create such insns.
2229 mem in this case will be either register indirect or register
2230 indirect plus a valid offset.
2232 register -> register move where REGNO(dst) == REGNO(src + 1)
2233 someone (Tim/Tege?) claimed this can happen for parameter loads.
2235 Handle mem -> register case first. */
2236 if (optype0 == REGOP
2237 && (optype1 == MEMOP || optype1 == OFFSOP)
2238 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2241 /* Do the late half first. */
2243 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2244 output_asm_insn (singlemove_string (latehalf), latehalf);
2248 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2249 return singlemove_string (operands);
2252 /* Now handle register -> register case. */
2253 if (optype0 == REGOP && optype1 == REGOP
2254 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2256 output_asm_insn (singlemove_string (latehalf), latehalf);
2257 return singlemove_string (operands);
2260 /* Normal case: do the two words, low-numbered first. */
2262 output_asm_insn (singlemove_string (operands), operands);
2264 /* Make any unoffsettable addresses point at high-numbered word. */
2266 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2268 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2271 output_asm_insn (singlemove_string (latehalf), latehalf);
2273 /* Undo the adds we just did. */
2275 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2277 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2283 output_fp_move_double (operands)
2286 if (FP_REG_P (operands[0]))
2288 if (FP_REG_P (operands[1])
2289 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2290 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2292 output_asm_insn ("fldd%F1 %1,%0", operands);
2294 else if (FP_REG_P (operands[1]))
2296 output_asm_insn ("fstd%F0 %1,%0", operands);
2298 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2300 if (GET_CODE (operands[0]) == REG)
2303 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2304 xoperands[0] = operands[0];
2305 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2307 /* This is a pain. You have to be prepared to deal with an
2308 arbitrary address here including pre/post increment/decrement.
2310 so avoid this in the MD. */
2318 /* Return a REG that occurs in ADDR with coefficient 1.
2319 ADDR can be effectively incremented by incrementing REG. */
2322 find_addr_reg (addr)
2325 while (GET_CODE (addr) == PLUS)
2327 if (GET_CODE (XEXP (addr, 0)) == REG)
2328 addr = XEXP (addr, 0);
2329 else if (GET_CODE (XEXP (addr, 1)) == REG)
2330 addr = XEXP (addr, 1);
2331 else if (CONSTANT_P (XEXP (addr, 0)))
2332 addr = XEXP (addr, 1);
2333 else if (CONSTANT_P (XEXP (addr, 1)))
2334 addr = XEXP (addr, 0);
2338 if (GET_CODE (addr) == REG)
2343 /* Emit code to perform a block move.
2345 OPERANDS[0] is the destination pointer as a REG, clobbered.
2346 OPERANDS[1] is the source pointer as a REG, clobbered.
2347 OPERANDS[2] is a register for temporary storage.
2348 OPERANDS[4] is the size as a CONST_INT
2349 OPERANDS[3] is a register for temporary storage.
2350 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2351 OPERANDS[6] is another temporary register. */
2354 output_block_move (operands, size_is_constant)
2356 int size_is_constant ATTRIBUTE_UNUSED;
2358 int align = INTVAL (operands[5]);
2359 unsigned long n_bytes = INTVAL (operands[4]);
2361 /* We can't move more than four bytes at a time because the PA
2362 has no longer integer move insns. (Could use fp mem ops?) */
2366 /* Note that we know each loop below will execute at least twice
2367 (else we would have open-coded the copy). */
2371 /* Pre-adjust the loop counter. */
2372 operands[4] = GEN_INT (n_bytes - 8);
2373 output_asm_insn ("ldi %4,%2", operands);
2376 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2377 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2378 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2379 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2380 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2382 /* Handle the residual. There could be up to 7 bytes of
2383 residual to copy! */
2384 if (n_bytes % 8 != 0)
2386 operands[4] = GEN_INT (n_bytes % 4);
2387 if (n_bytes % 8 >= 4)
2388 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2389 if (n_bytes % 4 != 0)
2390 output_asm_insn ("ldw 0(%1),%6", operands);
2391 if (n_bytes % 8 >= 4)
2392 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2393 if (n_bytes % 4 != 0)
2394 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2399 /* Pre-adjust the loop counter. */
2400 operands[4] = GEN_INT (n_bytes - 4);
2401 output_asm_insn ("ldi %4,%2", operands);
2404 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2405 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2406 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2407 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2408 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2410 /* Handle the residual. */
2411 if (n_bytes % 4 != 0)
2413 if (n_bytes % 4 >= 2)
2414 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2415 if (n_bytes % 2 != 0)
2416 output_asm_insn ("ldb 0(%1),%6", operands);
2417 if (n_bytes % 4 >= 2)
2418 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2419 if (n_bytes % 2 != 0)
2420 output_asm_insn ("stb %6,0(%0)", operands);
2425 /* Pre-adjust the loop counter. */
2426 operands[4] = GEN_INT (n_bytes - 2);
2427 output_asm_insn ("ldi %4,%2", operands);
2430 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2431 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2432 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2433 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2434 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2436 /* Handle the residual. */
2437 if (n_bytes % 2 != 0)
2439 output_asm_insn ("ldb 0(%1),%3", operands);
2440 output_asm_insn ("stb %3,0(%0)", operands);
2449 /* Count the number of insns necessary to handle this block move.
2451 Basic structure is the same as emit_block_move, except that we
2452 count insns rather than emit them. */
2455 compute_movstrsi_length (insn)
2458 rtx pat = PATTERN (insn);
2459 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2460 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2461 unsigned int n_insns = 0;
2463 /* We can't move more than four bytes at a time because the PA
2464 has no longer integer move insns. (Could use fp mem ops?) */
2468 /* The basic copying loop. */
2472 if (n_bytes % (2 * align) != 0)
2474 if ((n_bytes % (2 * align)) >= align)
2477 if ((n_bytes % align) != 0)
2481 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2487 output_and (operands)
2490 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2492 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2493 int ls0, ls1, ms0, p, len;
2495 for (ls0 = 0; ls0 < 32; ls0++)
2496 if ((mask & (1 << ls0)) == 0)
2499 for (ls1 = ls0; ls1 < 32; ls1++)
2500 if ((mask & (1 << ls1)) != 0)
2503 for (ms0 = ls1; ms0 < 32; ms0++)
2504 if ((mask & (1 << ms0)) == 0)
2517 operands[2] = GEN_INT (len);
2518 return "{extru|extrw,u} %1,31,%2,%0";
2522 /* We could use this `depi' for the case above as well, but `depi'
2523 requires one more register file access than an `extru'. */
2528 operands[2] = GEN_INT (p);
2529 operands[3] = GEN_INT (len);
2530 return "{depi|depwi} 0,%2,%3,%0";
2534 return "and %1,%2,%0";
2537 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2538 storing the result in operands[0]. */
2540 output_64bit_and (operands)
2543 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2545 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2546 int ls0, ls1, ms0, p, len;
2548 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2549 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2552 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2553 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2556 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2557 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2560 if (ms0 != HOST_BITS_PER_WIDE_INT)
2563 if (ls1 == HOST_BITS_PER_WIDE_INT)
2570 operands[2] = GEN_INT (len);
2571 return "extrd,u %1,63,%2,%0";
2575 /* We could use this `depi' for the case above as well, but `depi'
2576 requires one more register file access than an `extru'. */
2581 operands[2] = GEN_INT (p);
2582 operands[3] = GEN_INT (len);
2583 return "depdi 0,%2,%3,%0";
2587 return "and %1,%2,%0";
2591 output_ior (operands)
2594 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2595 int bs0, bs1, p, len;
2597 if (INTVAL (operands[2]) == 0)
2598 return "copy %1,%0";
2600 for (bs0 = 0; bs0 < 32; bs0++)
2601 if ((mask & (1 << bs0)) != 0)
2604 for (bs1 = bs0; bs1 < 32; bs1++)
2605 if ((mask & (1 << bs1)) == 0)
2608 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2614 operands[2] = GEN_INT (p);
2615 operands[3] = GEN_INT (len);
2616 return "{depi|depwi} -1,%2,%3,%0";
2619 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2620 storing the result in operands[0]. */
2622 output_64bit_ior (operands)
2625 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2626 int bs0, bs1, p, len;
2628 if (INTVAL (operands[2]) == 0)
2629 return "copy %1,%0";
2631 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2632 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2635 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2636 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2639 if (bs1 != HOST_BITS_PER_WIDE_INT
2640 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2646 operands[2] = GEN_INT (p);
2647 operands[3] = GEN_INT (len);
2648 return "depdi -1,%2,%3,%0";
2651 /* Target hook for assembling integer objects. This code handles
2652 aligned SI and DI integers specially, since function references must
2653 be preceded by P%. */
2656 pa_assemble_integer (x, size, aligned_p)
2661 if (size == UNITS_PER_WORD && aligned_p
2662 && function_label_operand (x, VOIDmode))
2664 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2665 output_addr_const (asm_out_file, x);
2666 fputc ('\n', asm_out_file);
2669 return default_assemble_integer (x, size, aligned_p);
2672 /* Output an ascii string. */
2674 output_ascii (file, p, size)
2681 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2683 /* The HP assembler can only take strings of 256 characters at one
2684 time. This is a limitation on input line length, *not* the
2685 length of the string. Sigh. Even worse, it seems that the
2686 restriction is in number of input characters (see \xnn &
2687 \whatever). So we have to do this very carefully. */
2689 fputs ("\t.STRING \"", file);
2692 for (i = 0; i < size; i += 4)
2696 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2698 register unsigned int c = (unsigned char) p[i + io];
2700 if (c == '\"' || c == '\\')
2701 partial_output[co++] = '\\';
2702 if (c >= ' ' && c < 0177)
2703 partial_output[co++] = c;
2707 partial_output[co++] = '\\';
2708 partial_output[co++] = 'x';
2709 hexd = c / 16 - 0 + '0';
2711 hexd -= '9' - 'a' + 1;
2712 partial_output[co++] = hexd;
2713 hexd = c % 16 - 0 + '0';
2715 hexd -= '9' - 'a' + 1;
2716 partial_output[co++] = hexd;
2719 if (chars_output + co > 243)
2721 fputs ("\"\n\t.STRING \"", file);
2724 fwrite (partial_output, 1, (size_t) co, file);
2728 fputs ("\"\n", file);
2731 /* Try to rewrite floating point comparisons & branches to avoid
2732 useless add,tr insns.
2734 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2735 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2736 first attempt to remove useless add,tr insns. It is zero
2737 for the second pass as reorg sometimes leaves bogus REG_DEAD
2740 When CHECK_NOTES is zero we can only eliminate add,tr insns
2741 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2744 remove_useless_addtr_insns (insns, check_notes)
2749 static int pass = 0;
2751 /* This is fairly cheap, so always run it when optimizing. */
2755 int fbranch_count = 0;
2757 /* Walk all the insns in this function looking for fcmp & fbranch
2758 instructions. Keep track of how many of each we find. */
2759 insns = get_insns ();
2760 for (insn = insns; insn; insn = next_insn (insn))
2764 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2765 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2768 tmp = PATTERN (insn);
2770 /* It must be a set. */
2771 if (GET_CODE (tmp) != SET)
2774 /* If the destination is CCFP, then we've found an fcmp insn. */
2775 tmp = SET_DEST (tmp);
2776 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2782 tmp = PATTERN (insn);
2783 /* If this is an fbranch instruction, bump the fbranch counter. */
2784 if (GET_CODE (tmp) == SET
2785 && SET_DEST (tmp) == pc_rtx
2786 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2787 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2788 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2789 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2797 /* Find all floating point compare + branch insns. If possible,
2798 reverse the comparison & the branch to avoid add,tr insns. */
2799 for (insn = insns; insn; insn = next_insn (insn))
2803 /* Ignore anything that isn't an INSN. */
2804 if (GET_CODE (insn) != INSN)
2807 tmp = PATTERN (insn);
2809 /* It must be a set. */
2810 if (GET_CODE (tmp) != SET)
2813 /* The destination must be CCFP, which is register zero. */
2814 tmp = SET_DEST (tmp);
2815 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2818 /* INSN should be a set of CCFP.
2820 See if the result of this insn is used in a reversed FP
2821 conditional branch. If so, reverse our condition and
2822 the branch. Doing so avoids useless add,tr insns. */
2823 next = next_insn (insn);
2826 /* Jumps, calls and labels stop our search. */
2827 if (GET_CODE (next) == JUMP_INSN
2828 || GET_CODE (next) == CALL_INSN
2829 || GET_CODE (next) == CODE_LABEL)
2832 /* As does another fcmp insn. */
2833 if (GET_CODE (next) == INSN
2834 && GET_CODE (PATTERN (next)) == SET
2835 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2836 && REGNO (SET_DEST (PATTERN (next))) == 0)
2839 next = next_insn (next);
2842 /* Is NEXT_INSN a branch? */
2844 && GET_CODE (next) == JUMP_INSN)
2846 rtx pattern = PATTERN (next);
2848 /* If it a reversed fp conditional branch (eg uses add,tr)
2849 and CCFP dies, then reverse our conditional and the branch
2850 to avoid the add,tr. */
2851 if (GET_CODE (pattern) == SET
2852 && SET_DEST (pattern) == pc_rtx
2853 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2854 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2855 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2856 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2857 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2858 && (fcmp_count == fbranch_count
2860 && find_regno_note (next, REG_DEAD, 0))))
2862 /* Reverse the branch. */
2863 tmp = XEXP (SET_SRC (pattern), 1);
2864 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2865 XEXP (SET_SRC (pattern), 2) = tmp;
2866 INSN_CODE (next) = -1;
2868 /* Reverse our condition. */
2869 tmp = PATTERN (insn);
2870 PUT_CODE (XEXP (tmp, 1),
2871 (reverse_condition_maybe_unordered
2872 (GET_CODE (XEXP (tmp, 1)))));
2882 /* You may have trouble believing this, but this is the 32 bit HP-PA
2887 Variable arguments (optional; any number may be allocated)
2889 SP-(4*(N+9)) arg word N
2894 Fixed arguments (must be allocated; may remain unused)
2903 SP-32 External Data Pointer (DP)
2905 SP-24 External/stub RP (RP')
2909 SP-8 Calling Stub RP (RP'')
2914 SP-0 Stack Pointer (points to next available address)
2918 /* This function saves registers as follows. Registers marked with ' are
2919 this function's registers (as opposed to the previous function's).
2920 If a frame_pointer isn't needed, r4 is saved as a general register;
2921 the space for the frame pointer is still allocated, though, to keep
2927 SP (FP') Previous FP
2928 SP + 4 Alignment filler (sigh)
2929 SP + 8 Space for locals reserved here.
2933 SP + n All call saved register used.
2937 SP + o All call saved fp registers used.
2941 SP + p (SP') points to next available address.
2945 /* Global variables set by output_function_prologue(). */
2946 /* Size of frame. Need to know this to emit return insns from
2948 static int actual_fsize;
2949 static int local_fsize, save_fregs;
2951 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2952 Handle case where DISP > 8k by using the add_high_const patterns.
2954 Note in DISP > 8k case, we will leave the high part of the address
2955 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2958 store_reg (reg, disp, base)
2959 int reg, disp, base;
2961 rtx insn, dest, src, basereg;
2963 src = gen_rtx_REG (word_mode, reg);
2964 basereg = gen_rtx_REG (Pmode, base);
2965 if (VAL_14_BITS_P (disp))
2967 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2968 insn = emit_move_insn (dest, src);
2972 rtx delta = GEN_INT (disp);
2973 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
2974 rtx tmpreg = gen_rtx_REG (Pmode, 1);
2975 emit_move_insn (tmpreg, high);
2976 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
2977 insn = emit_move_insn (dest, src);
2981 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2982 gen_rtx_SET (VOIDmode,
2983 gen_rtx_MEM (word_mode,
2984 gen_rtx_PLUS (word_mode, basereg,
2992 RTX_FRAME_RELATED_P (insn) = 1;
2995 /* Emit RTL to store REG at the memory location specified by BASE and then
2996 add MOD to BASE. MOD must be <= 8k. */
2999 store_reg_modify (base, reg, mod)
3002 rtx insn, basereg, srcreg, delta;
3004 if (! VAL_14_BITS_P (mod))
3007 basereg = gen_rtx_REG (Pmode, base);
3008 srcreg = gen_rtx_REG (word_mode, reg);
3009 delta = GEN_INT (mod);
3011 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3014 RTX_FRAME_RELATED_P (insn) = 1;
3016 /* RTX_FRAME_RELATED_P must be set on each frame related set
3017 in a parallel with more than one element. Don't set
3018 RTX_FRAME_RELATED_P in the first set if reg is temporary
3019 register 1. The effect of this operation is recorded in
3020 the initial copy. */
3023 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3024 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3028 /* The first element of a PARALLEL is always processed if it is
3029 a SET. Thus, we need an expression list for this case. */
3031 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3032 gen_rtx_SET (VOIDmode, basereg,
3033 gen_rtx_PLUS (word_mode, basereg, delta)),
3039 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3040 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3041 whether to add a frame note or not.
3043 In the DISP > 8k case, we leave the high part of the address in %r1.
3044 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3047 set_reg_plus_d (reg, base, disp, note)
3048 int reg, base, disp, note;
3052 if (VAL_14_BITS_P (disp))
3054 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3055 plus_constant (gen_rtx_REG (Pmode, base), disp));
3059 rtx basereg = gen_rtx_REG (Pmode, base);
3060 rtx delta = GEN_INT (disp);
3062 emit_move_insn (gen_rtx_REG (Pmode, 1),
3063 gen_rtx_PLUS (Pmode, basereg,
3064 gen_rtx_HIGH (Pmode, delta)));
3065 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3066 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
3070 if (DO_FRAME_NOTES && note)
3071 RTX_FRAME_RELATED_P (insn) = 1;
3075 compute_frame_size (size, fregs_live)
3081 /* Space for frame pointer + filler. If any frame is allocated
3082 we need to add this in because of STARTING_FRAME_OFFSET.
3084 Similar code also appears in hppa_expand_prologue. Change both
3085 of them at the same time. */
3086 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
3088 /* If the current function calls __builtin_eh_return, then we need
3089 to allocate stack space for registers that will hold data for
3090 the exception handler. */
3091 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3095 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3097 fsize += i * UNITS_PER_WORD;
3100 /* Account for space used by the callee general register saves. */
3101 for (i = 18; i >= 3; i--)
3102 if (regs_ever_live[i])
3103 fsize += UNITS_PER_WORD;
3105 /* Round the stack. */
3106 fsize = (fsize + 7) & ~7;
3108 /* Account for space used by the callee floating point register saves. */
3109 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3110 if (regs_ever_live[i]
3111 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3116 /* We always save both halves of the FP register, so always
3117 increment the frame size by 8 bytes. */
3121 /* The various ABIs include space for the outgoing parameters in the
3122 size of the current function's stack frame. */
3123 fsize += current_function_outgoing_args_size;
3125 /* Allocate space for the fixed frame marker. This space must be
3126 allocated for any function that makes calls or otherwise allocates
3128 if (!current_function_is_leaf || fsize)
3129 fsize += TARGET_64BIT ? 16 : 32;
3131 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
3134 /* Generate the assembly code for function entry. FILE is a stdio
3135 stream to output the code to. SIZE is an int: how many units of
3136 temporary storage to allocate.
3138 Refer to the array `regs_ever_live' to determine which registers to
3139 save; `regs_ever_live[I]' is nonzero if register number I is ever
3140 used in the function. This function is responsible for knowing
3141 which registers should not be saved even if used. */
3143 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3144 of memory. If any fpu reg is used in the function, we allocate
3145 such a block here, at the bottom of the frame, just in case it's needed.
3147 If this function is a leaf procedure, then we may choose not
3148 to do a "save" insn. The decision about whether or not
3149 to do this is made in regclass.c. */
3152 pa_output_function_prologue (file, size)
3154 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3156 /* The function's label and associated .PROC must never be
3157 separated and must be output *after* any profiling declarations
3158 to avoid changing spaces/subspaces within a procedure. */
3159 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3160 fputs ("\t.PROC\n", file);
3162 /* hppa_expand_prologue does the dirty work now. We just need
3163 to output the assembler directives which denote the start
3165 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
3166 if (regs_ever_live[2])
3167 fputs (",CALLS,SAVE_RP", file);
3169 fputs (",NO_CALLS", file);
3171 if (frame_pointer_needed)
3172 fputs (",SAVE_SP", file);
3174 /* Pass on information about the number of callee register saves
3175 performed in the prologue.
3177 The compiler is supposed to pass the highest register number
3178 saved, the assembler then has to adjust that number before
3179 entering it into the unwind descriptor (to account for any
3180 caller saved registers with lower register numbers than the
3181 first callee saved register). */
3183 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3186 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3188 fputs ("\n\t.ENTRY\n", file);
3190 /* If we're using GAS and SOM, and not using the portable runtime model,
3191 then we don't need to accumulate the total number of code bytes. */
3192 if ((TARGET_GAS && TARGET_SOM && ! TARGET_PORTABLE_RUNTIME)
3193 /* FIXME: we can't handle long calls for TARGET_64BIT. */
3195 total_code_bytes = 0;
3196 else if (INSN_ADDRESSES_SET_P ())
3198 unsigned int old_total = total_code_bytes;
3200 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_nonnote_insn ()));
3201 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3203 /* Be prepared to handle overflows. */
3204 if (old_total > total_code_bytes)
3205 total_code_bytes = -1;
3208 total_code_bytes = -1;
3210 remove_useless_addtr_insns (get_insns (), 0);
3214 hppa_expand_prologue ()
3216 int size = get_frame_size ();
3217 int merge_sp_adjust_with_store = 0;
3225 /* Allocate space for frame pointer + filler. If any frame is allocated
3226 we need to add this in because of STARTING_FRAME_OFFSET.
3228 Similar code also appears in compute_frame_size. Change both
3229 of them at the same time. */
3230 local_fsize = size + (size || frame_pointer_needed
3231 ? STARTING_FRAME_OFFSET : 0);
3233 actual_fsize = compute_frame_size (size, &save_fregs);
3235 /* Compute a few things we will use often. */
3236 tmpreg = gen_rtx_REG (word_mode, 1);
3238 /* Save RP first. The calling conventions manual states RP will
3239 always be stored into the caller's frame at sp - 20 or sp - 16
3240 depending on which ABI is in use. */
3241 if (regs_ever_live[2] || current_function_calls_eh_return)
3242 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3244 /* Allocate the local frame and set up the frame pointer if needed. */
3245 if (actual_fsize != 0)
3247 if (frame_pointer_needed)
3249 /* Copy the old frame pointer temporarily into %r1. Set up the
3250 new stack pointer, then store away the saved old frame pointer
3251 into the stack at sp and at the same time update the stack
3252 pointer by actual_fsize bytes. Two versions, first
3253 handles small (<8k) frames. The second handles large (>=8k)
3255 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3258 /* We need to record the frame pointer save here since the
3259 new frame pointer is set in the following insn. */
3260 RTX_FRAME_RELATED_P (insn) = 1;
3262 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3263 gen_rtx_SET (VOIDmode,
3264 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3269 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3271 RTX_FRAME_RELATED_P (insn) = 1;
3273 if (VAL_14_BITS_P (actual_fsize))
3274 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3277 /* It is incorrect to store the saved frame pointer at *sp,
3278 then increment sp (writes beyond the current stack boundary).
3280 So instead use stwm to store at *sp and post-increment the
3281 stack pointer as an atomic operation. Then increment sp to
3282 finish allocating the new frame. */
3283 int adjust1 = 8192 - 64;
3284 int adjust2 = actual_fsize - adjust1;
3286 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3287 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3291 /* Prevent register spills from being scheduled before the
3292 stack pointer is raised. Necessary as we will be storing
3293 registers using the frame pointer as a base register, and
3294 we happen to set fp before raising sp. */
3295 emit_insn (gen_blockage ());
3297 /* no frame pointer needed. */
3300 /* In some cases we can perform the first callee register save
3301 and allocating the stack frame at the same time. If so, just
3302 make a note of it and defer allocating the frame until saving
3303 the callee registers. */
3304 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3305 merge_sp_adjust_with_store = 1;
3306 /* Can not optimize. Adjust the stack frame by actual_fsize
3309 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3314 /* Normal register save.
3316 Do not save the frame pointer in the frame_pointer_needed case. It
3317 was done earlier. */
3318 if (frame_pointer_needed)
3320 offset = local_fsize;
3322 /* Saving the EH return data registers in the frame is the simplest
3323 way to get the frame unwind information emitted. We put them
3324 just before the general registers. */
3325 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3327 unsigned int i, regno;
3331 regno = EH_RETURN_DATA_REGNO (i);
3332 if (regno == INVALID_REGNUM)
3335 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3336 offset += UNITS_PER_WORD;
3340 for (i = 18; i >= 4; i--)
3341 if (regs_ever_live[i] && ! call_used_regs[i])
3343 store_reg (i, offset, FRAME_POINTER_REGNUM);
3344 offset += UNITS_PER_WORD;
3347 /* Account for %r3 which is saved in a special place. */
3350 /* No frame pointer needed. */
3353 offset = local_fsize - actual_fsize;
3355 /* Saving the EH return data registers in the frame is the simplest
3356 way to get the frame unwind information emitted. */
3357 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3359 unsigned int i, regno;
3363 regno = EH_RETURN_DATA_REGNO (i);
3364 if (regno == INVALID_REGNUM)
3367 /* If merge_sp_adjust_with_store is nonzero, then we can
3368 optimize the first save. */
3369 if (merge_sp_adjust_with_store)
3371 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3372 merge_sp_adjust_with_store = 0;
3375 store_reg (regno, offset, STACK_POINTER_REGNUM);
3376 offset += UNITS_PER_WORD;
3380 for (i = 18; i >= 3; i--)
3381 if (regs_ever_live[i] && ! call_used_regs[i])
3383 /* If merge_sp_adjust_with_store is nonzero, then we can
3384 optimize the first GR save. */
3385 if (merge_sp_adjust_with_store)
3387 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3388 merge_sp_adjust_with_store = 0;
3391 store_reg (i, offset, STACK_POINTER_REGNUM);
3392 offset += UNITS_PER_WORD;
3396 /* If we wanted to merge the SP adjustment with a GR save, but we never
3397 did any GR saves, then just emit the adjustment here. */
3398 if (merge_sp_adjust_with_store)
3399 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3403 /* The hppa calling conventions say that %r19, the pic offset
3404 register, is saved at sp - 32 (in this function's frame)
3405 when generating PIC code. FIXME: What is the correct thing
3406 to do for functions which make no calls and allocate no
3407 frame? Do we need to allocate a frame, or can we just omit
3408 the save? For now we'll just omit the save. */
3409 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3410 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3412 /* Align pointer properly (doubleword boundary). */
3413 offset = (offset + 7) & ~7;
3415 /* Floating point register store. */
3420 /* First get the frame or stack pointer to the start of the FP register
3422 if (frame_pointer_needed)
3424 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3425 base = frame_pointer_rtx;
3429 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3430 base = stack_pointer_rtx;
3433 /* Now actually save the FP registers. */
3434 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3436 if (regs_ever_live[i]
3437 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3439 rtx addr, insn, reg;
3440 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3441 reg = gen_rtx_REG (DFmode, i);
3442 insn = emit_move_insn (addr, reg);
3445 RTX_FRAME_RELATED_P (insn) = 1;
3448 rtx mem = gen_rtx_MEM (DFmode,
3449 plus_constant (base, offset));
3451 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3452 gen_rtx_SET (VOIDmode, mem, reg),
3457 rtx meml = gen_rtx_MEM (SFmode,
3458 plus_constant (base, offset));
3459 rtx memr = gen_rtx_MEM (SFmode,
3460 plus_constant (base, offset + 4));
3461 rtx regl = gen_rtx_REG (SFmode, i);
3462 rtx regr = gen_rtx_REG (SFmode, i + 1);
3463 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3464 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3467 RTX_FRAME_RELATED_P (setl) = 1;
3468 RTX_FRAME_RELATED_P (setr) = 1;
3469 vec = gen_rtvec (2, setl, setr);
3471 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3472 gen_rtx_SEQUENCE (VOIDmode, vec),
3476 offset += GET_MODE_SIZE (DFmode);
3482 /* FIXME: expand_call and expand_millicode_call need to be fixed to
3483 prevent insns with frame notes being scheduled in the delay slot
3484 of calls. This causes problems because the dwarf2 output code
3485 processes the insn list serially. For now, limit the migration
3486 of prologue insns with a blockage. */
3488 emit_insn (gen_blockage ());
3491 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3492 Handle case where DISP > 8k by using the add_high_const patterns. */
3495 load_reg (reg, disp, base)
3496 int reg, disp, base;
3498 rtx src, dest, basereg;
3500 dest = gen_rtx_REG (word_mode, reg);
3501 basereg = gen_rtx_REG (Pmode, base);
3502 if (VAL_14_BITS_P (disp))
3504 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3505 emit_move_insn (dest, src);
3509 rtx delta = GEN_INT (disp);
3510 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3511 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3512 emit_move_insn (tmpreg, high);
3513 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3514 emit_move_insn (dest, src);
3518 /* This function generates the assembly code for function exit.
3519 Args are as for output_function_prologue ().
3521 The function epilogue should not depend on the current stack
3522 pointer! It should use the frame pointer only. This is mandatory
3523 because of alloca; we also take advantage of it to omit stack
3524 adjustments before returning. */
3527 pa_output_function_epilogue (file, size)
3529 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3531 rtx insn = get_last_insn ();
3533 /* hppa_expand_epilogue does the dirty work now. We just need
3534 to output the assembler directives which denote the end
3537 To make debuggers happy, emit a nop if the epilogue was completely
3538 eliminated due to a volatile call as the last insn in the
3539 current function. That way the return address (in %r2) will
3540 always point to a valid instruction in the current function. */
3542 /* Get the last real insn. */
3543 if (GET_CODE (insn) == NOTE)
3544 insn = prev_real_insn (insn);
3546 /* If it is a sequence, then look inside. */
3547 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3548 insn = XVECEXP (PATTERN (insn), 0, 0);
3550 /* If insn is a CALL_INSN, then it must be a call to a volatile
3551 function (otherwise there would be epilogue insns). */
3552 if (insn && GET_CODE (insn) == CALL_INSN)
3553 fputs ("\tnop\n", file);
3555 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3559 hppa_expand_epilogue ()
3563 int merge_sp_adjust_with_load = 0;
3566 /* We will use this often. */
3567 tmpreg = gen_rtx_REG (word_mode, 1);
3569 /* Try to restore RP early to avoid load/use interlocks when
3570 RP gets used in the return (bv) instruction. This appears to still
3571 be necessary even when we schedule the prologue and epilogue. */
3572 if (regs_ever_live [2] || current_function_calls_eh_return)
3574 ret_off = TARGET_64BIT ? -16 : -20;
3575 if (frame_pointer_needed)
3577 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3582 /* No frame pointer, and stack is smaller than 8k. */
3583 if (VAL_14_BITS_P (ret_off - actual_fsize))
3585 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3591 /* General register restores. */
3592 if (frame_pointer_needed)
3594 offset = local_fsize;
3596 /* If the current function calls __builtin_eh_return, then we need
3597 to restore the saved EH data registers. */
3598 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3600 unsigned int i, regno;
3604 regno = EH_RETURN_DATA_REGNO (i);
3605 if (regno == INVALID_REGNUM)
3608 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3609 offset += UNITS_PER_WORD;
3613 for (i = 18; i >= 4; i--)
3614 if (regs_ever_live[i] && ! call_used_regs[i])
3616 load_reg (i, offset, FRAME_POINTER_REGNUM);
3617 offset += UNITS_PER_WORD;
3622 offset = local_fsize - actual_fsize;
3624 /* If the current function calls __builtin_eh_return, then we need
3625 to restore the saved EH data registers. */
3626 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3628 unsigned int i, regno;
3632 regno = EH_RETURN_DATA_REGNO (i);
3633 if (regno == INVALID_REGNUM)
3636 /* Only for the first load.
3637 merge_sp_adjust_with_load holds the register load
3638 with which we will merge the sp adjustment. */
3639 if (merge_sp_adjust_with_load == 0
3641 && VAL_14_BITS_P (-actual_fsize))
3642 merge_sp_adjust_with_load = regno;
3644 load_reg (regno, offset, STACK_POINTER_REGNUM);
3645 offset += UNITS_PER_WORD;
3649 for (i = 18; i >= 3; i--)
3651 if (regs_ever_live[i] && ! call_used_regs[i])
3653 /* Only for the first load.
3654 merge_sp_adjust_with_load holds the register load
3655 with which we will merge the sp adjustment. */
3656 if (merge_sp_adjust_with_load == 0
3658 && VAL_14_BITS_P (-actual_fsize))
3659 merge_sp_adjust_with_load = i;
3661 load_reg (i, offset, STACK_POINTER_REGNUM);
3662 offset += UNITS_PER_WORD;
3667 /* Align pointer properly (doubleword boundary). */
3668 offset = (offset + 7) & ~7;
3670 /* FP register restores. */
3673 /* Adjust the register to index off of. */
3674 if (frame_pointer_needed)
3675 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3677 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3679 /* Actually do the restores now. */
3680 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3681 if (regs_ever_live[i]
3682 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3684 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3685 rtx dest = gen_rtx_REG (DFmode, i);
3686 emit_move_insn (dest, src);
3690 /* Emit a blockage insn here to keep these insns from being moved to
3691 an earlier spot in the epilogue, or into the main instruction stream.
3693 This is necessary as we must not cut the stack back before all the
3694 restores are finished. */
3695 emit_insn (gen_blockage ());
3697 /* Reset stack pointer (and possibly frame pointer). The stack
3698 pointer is initially set to fp + 64 to avoid a race condition. */
3699 if (frame_pointer_needed)
3701 rtx delta = GEN_INT (-64);
3703 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
3704 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
3706 /* If we were deferring a callee register restore, do it now. */
3707 else if (merge_sp_adjust_with_load)
3709 rtx delta = GEN_INT (-actual_fsize);
3710 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3712 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
3714 else if (actual_fsize != 0)
3715 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3718 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3719 frame greater than 8k), do so now. */
3721 load_reg (2, ret_off, STACK_POINTER_REGNUM);
3723 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3725 rtx sa = EH_RETURN_STACKADJ_RTX;
3727 emit_insn (gen_blockage ());
3728 emit_insn (TARGET_64BIT
3729 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
3730 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
3735 hppa_pic_save_rtx ()
3737 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3741 hppa_profile_hook (label_no)
3744 rtx begin_label_rtx, call_insn;
3745 char begin_label_name[16];
3747 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3749 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3752 emit_move_insn (arg_pointer_rtx,
3753 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3756 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3758 #ifndef NO_PROFILE_COUNTERS
3760 rtx count_label_rtx, addr, r24;
3761 char count_label_name[16];
3763 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3764 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3766 addr = force_reg (Pmode, count_label_rtx);
3767 r24 = gen_rtx_REG (Pmode, 24);
3768 emit_move_insn (r24, addr);
3770 /* %r25 is set from within the output pattern. */
3772 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3773 GEN_INT (TARGET_64BIT ? 24 : 12),
3776 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3779 /* %r25 is set from within the output pattern. */
3781 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3782 GEN_INT (TARGET_64BIT ? 16 : 8),
3786 /* Indicate the _mcount call cannot throw, nor will it execute a
3788 REG_NOTES (call_insn)
3789 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3793 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3795 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3797 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3801 /* Fetch the return address for the frame COUNT steps up from
3802 the current frame, after the prologue. FRAMEADDR is the
3803 frame pointer of the COUNT frame.
3805 We want to ignore any export stub remnants here. To handle this,
3806 we examine the code at the return address, and if it is an export
3807 stub, we return a memory rtx for the stub return address stored
3810 The value returned is used in two different ways:
3812 1. To find a function's caller.
3814 2. To change the return address for a function.
3816 This function handles most instances of case 1; however, it will
3817 fail if there are two levels of stubs to execute on the return
3818 path. The only way I believe that can happen is if the return value
3819 needs a parameter relocation, which never happens for C code.
3821 This function handles most instances of case 2; however, it will
3822 fail if we did not originally have stub code on the return path
3823 but will need stub code on the new return path. This can happen if
3824 the caller & callee are both in the main program, but the new
3825 return location is in a shared library. */
3828 return_addr_rtx (count, frameaddr)
3840 rp = get_hard_reg_initial_val (Pmode, 2);
3842 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
3845 saved_rp = gen_reg_rtx (Pmode);
3846 emit_move_insn (saved_rp, rp);
3848 /* Get pointer to the instruction stream. We have to mask out the
3849 privilege level from the two low order bits of the return address
3850 pointer here so that ins will point to the start of the first
3851 instruction that would have been executed if we returned. */
3852 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
3853 label = gen_label_rtx ();
3855 /* Check the instruction stream at the normal return address for the
3858 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3859 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3860 0x00011820 | stub+16: mtsp r1,sr0
3861 0xe0400002 | stub+20: be,n 0(sr0,rp)
3863 If it is an export stub, than our return address is really in
3866 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
3867 NULL_RTX, SImode, 1);
3868 emit_jump_insn (gen_bne (label));
3870 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3871 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
3872 emit_jump_insn (gen_bne (label));
3874 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3875 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
3876 emit_jump_insn (gen_bne (label));
3878 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3879 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
3881 /* If there is no export stub then just use the value saved from
3882 the return pointer register. */
3884 emit_jump_insn (gen_bne (label));
3886 /* Here we know that our return address points to an export
3887 stub. We don't want to return the address of the export stub,
3888 but rather the return address of the export stub. That return
3889 address is stored at -24[frameaddr]. */
3891 emit_move_insn (saved_rp,
3893 memory_address (Pmode,
3894 plus_constant (frameaddr,
3901 /* This is only valid once reload has completed because it depends on
3902 knowing exactly how much (if any) frame there is and...
3904 It's only valid if there is no frame marker to de-allocate and...
3906 It's only valid if %r2 hasn't been saved into the caller's frame
3907 (we're not profiling and %r2 isn't live anywhere). */
3909 hppa_can_use_return_insn_p ()
3911 return (reload_completed
3912 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3913 && ! regs_ever_live[2]
3914 && ! frame_pointer_needed);
3918 emit_bcond_fp (code, operand0)
3922 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3923 gen_rtx_IF_THEN_ELSE (VOIDmode,
3924 gen_rtx_fmt_ee (code,
3926 gen_rtx_REG (CCFPmode, 0),
3928 gen_rtx_LABEL_REF (VOIDmode, operand0),
3934 gen_cmp_fp (code, operand0, operand1)
3936 rtx operand0, operand1;
3938 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3939 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3942 /* Adjust the cost of a scheduling dependency. Return the new cost of
3943 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3946 pa_adjust_cost (insn, link, dep_insn, cost)
3952 enum attr_type attr_type;
3954 /* Don't adjust costs for a pa8000 chip, also do not adjust any
3955 true dependencies as they are described with bypasses now. */
3956 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
3959 if (! recog_memoized (insn))
3962 attr_type = get_attr_type (insn);
3964 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3966 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3969 if (attr_type == TYPE_FPLOAD)
3971 rtx pat = PATTERN (insn);
3972 rtx dep_pat = PATTERN (dep_insn);
3973 if (GET_CODE (pat) == PARALLEL)
3975 /* This happens for the fldXs,mb patterns. */
3976 pat = XVECEXP (pat, 0, 0);
3978 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3979 /* If this happens, we have to extend this to schedule
3980 optimally. Return 0 for now. */
3983 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3985 if (! recog_memoized (dep_insn))
3987 switch (get_attr_type (dep_insn))
3994 case TYPE_FPSQRTSGL:
3995 case TYPE_FPSQRTDBL:
3996 /* A fpload can't be issued until one cycle before a
3997 preceding arithmetic operation has finished if
3998 the target of the fpload is any of the sources
3999 (or destination) of the arithmetic operation. */
4000 return insn_default_latency (dep_insn) - 1;
4007 else if (attr_type == TYPE_FPALU)
4009 rtx pat = PATTERN (insn);
4010 rtx dep_pat = PATTERN (dep_insn);
4011 if (GET_CODE (pat) == PARALLEL)
4013 /* This happens for the fldXs,mb patterns. */
4014 pat = XVECEXP (pat, 0, 0);
4016 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4017 /* If this happens, we have to extend this to schedule
4018 optimally. Return 0 for now. */
4021 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4023 if (! recog_memoized (dep_insn))
4025 switch (get_attr_type (dep_insn))
4029 case TYPE_FPSQRTSGL:
4030 case TYPE_FPSQRTDBL:
4031 /* An ALU flop can't be issued until two cycles before a
4032 preceding divide or sqrt operation has finished if
4033 the target of the ALU flop is any of the sources
4034 (or destination) of the divide or sqrt operation. */
4035 return insn_default_latency (dep_insn) - 2;
4043 /* For other anti dependencies, the cost is 0. */
4046 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4048 /* Output dependency; DEP_INSN writes a register that INSN writes some
4050 if (attr_type == TYPE_FPLOAD)
4052 rtx pat = PATTERN (insn);
4053 rtx dep_pat = PATTERN (dep_insn);
4054 if (GET_CODE (pat) == PARALLEL)
4056 /* This happens for the fldXs,mb patterns. */
4057 pat = XVECEXP (pat, 0, 0);
4059 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4060 /* If this happens, we have to extend this to schedule
4061 optimally. Return 0 for now. */
4064 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4066 if (! recog_memoized (dep_insn))
4068 switch (get_attr_type (dep_insn))
4075 case TYPE_FPSQRTSGL:
4076 case TYPE_FPSQRTDBL:
4077 /* A fpload can't be issued until one cycle before a
4078 preceding arithmetic operation has finished if
4079 the target of the fpload is the destination of the
4080 arithmetic operation.
4082 Exception: For PA7100LC, PA7200 and PA7300, the cost
4083 is 3 cycles, unless they bundle together. We also
4084 pay the penalty if the second insn is a fpload. */
4085 return insn_default_latency (dep_insn) - 1;
4092 else if (attr_type == TYPE_FPALU)
4094 rtx pat = PATTERN (insn);
4095 rtx dep_pat = PATTERN (dep_insn);
4096 if (GET_CODE (pat) == PARALLEL)
4098 /* This happens for the fldXs,mb patterns. */
4099 pat = XVECEXP (pat, 0, 0);
4101 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4102 /* If this happens, we have to extend this to schedule
4103 optimally. Return 0 for now. */
4106 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4108 if (! recog_memoized (dep_insn))
4110 switch (get_attr_type (dep_insn))
4114 case TYPE_FPSQRTSGL:
4115 case TYPE_FPSQRTDBL:
4116 /* An ALU flop can't be issued until two cycles before a
4117 preceding divide or sqrt operation has finished if
4118 the target of the ALU flop is also the target of
4119 the divide or sqrt operation. */
4120 return insn_default_latency (dep_insn) - 2;
4128 /* For other output dependencies, the cost is 0. */
4135 /* Adjust scheduling priorities. We use this to try and keep addil
4136 and the next use of %r1 close together. */
4138 pa_adjust_priority (insn, priority)
4142 rtx set = single_set (insn);
4146 src = SET_SRC (set);
4147 dest = SET_DEST (set);
4148 if (GET_CODE (src) == LO_SUM
4149 && symbolic_operand (XEXP (src, 1), VOIDmode)
4150 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4153 else if (GET_CODE (src) == MEM
4154 && GET_CODE (XEXP (src, 0)) == LO_SUM
4155 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4156 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4159 else if (GET_CODE (dest) == MEM
4160 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4161 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4162 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4168 /* The 700 can only issue a single insn at a time.
4169 The 7XXX processors can issue two insns at a time.
4170 The 8000 can issue 4 insns at a time. */
4176 case PROCESSOR_700: return 1;
4177 case PROCESSOR_7100: return 2;
4178 case PROCESSOR_7100LC: return 2;
4179 case PROCESSOR_7200: return 2;
4180 case PROCESSOR_7300: return 2;
4181 case PROCESSOR_8000: return 4;
4190 /* Return any length adjustment needed by INSN which already has its length
4191 computed as LENGTH. Return zero if no adjustment is necessary.
4193 For the PA: function calls, millicode calls, and backwards short
4194 conditional branches with unfilled delay slots need an adjustment by +1
4195 (to account for the NOP which will be inserted into the instruction stream).
4197 Also compute the length of an inline block move here as it is too
4198 complicated to express as a length attribute in pa.md. */
4200 pa_adjust_insn_length (insn, length)
4204 rtx pat = PATTERN (insn);
4206 /* Call insns which are *not* indirect and have unfilled delay slots. */
4207 if (GET_CODE (insn) == CALL_INSN)
4210 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4211 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4213 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4214 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4220 /* Jumps inside switch tables which have unfilled delay slots
4221 also need adjustment. */
4222 else if (GET_CODE (insn) == JUMP_INSN
4223 && simplejump_p (insn)
4224 && GET_MODE (insn) == SImode)
4226 /* Millicode insn with an unfilled delay slot. */
4227 else if (GET_CODE (insn) == INSN
4228 && GET_CODE (pat) != SEQUENCE
4229 && GET_CODE (pat) != USE
4230 && GET_CODE (pat) != CLOBBER
4231 && get_attr_type (insn) == TYPE_MILLI)
4233 /* Block move pattern. */
4234 else if (GET_CODE (insn) == INSN
4235 && GET_CODE (pat) == PARALLEL
4236 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4237 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4238 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4239 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4240 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4241 return compute_movstrsi_length (insn) - 4;
4242 /* Conditional branch with an unfilled delay slot. */
4243 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4245 /* Adjust a short backwards conditional with an unfilled delay slot. */
4246 if (GET_CODE (pat) == SET
4248 && ! forward_branch_p (insn))
4250 else if (GET_CODE (pat) == PARALLEL
4251 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4254 /* Adjust dbra insn with short backwards conditional branch with
4255 unfilled delay slot -- only for case where counter is in a
4256 general register register. */
4257 else if (GET_CODE (pat) == PARALLEL
4258 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4259 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4260 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4262 && ! forward_branch_p (insn))
4270 /* Print operand X (an rtx) in assembler syntax to file FILE.
4271 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4272 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4275 print_operand (file, x, code)
4283 /* Output a 'nop' if there's nothing for the delay slot. */
4284 if (dbr_sequence_length () == 0)
4285 fputs ("\n\tnop", file);
4288 /* Output an nullification completer if there's nothing for the */
4289 /* delay slot or nullification is requested. */
4290 if (dbr_sequence_length () == 0 ||
4292 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4296 /* Print out the second register name of a register pair.
4297 I.e., R (6) => 7. */
4298 fputs (reg_names[REGNO (x) + 1], file);
4301 /* A register or zero. */
4303 || (x == CONST0_RTX (DFmode))
4304 || (x == CONST0_RTX (SFmode)))
4306 fputs ("%r0", file);
4312 /* A register or zero (floating point). */
4314 || (x == CONST0_RTX (DFmode))
4315 || (x == CONST0_RTX (SFmode)))
4317 fputs ("%fr0", file);
4326 xoperands[0] = XEXP (XEXP (x, 0), 0);
4327 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4328 output_global_address (file, xoperands[1], 0);
4329 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4333 case 'C': /* Plain (C)ondition */
4335 switch (GET_CODE (x))
4338 fputs ("=", file); break;
4340 fputs ("<>", file); break;
4342 fputs (">", file); break;
4344 fputs (">=", file); break;
4346 fputs (">>=", file); break;
4348 fputs (">>", file); break;
4350 fputs ("<", file); break;
4352 fputs ("<=", file); break;
4354 fputs ("<<=", file); break;
4356 fputs ("<<", file); break;
4361 case 'N': /* Condition, (N)egated */
4362 switch (GET_CODE (x))
4365 fputs ("<>", file); break;
4367 fputs ("=", file); break;
4369 fputs ("<=", file); break;
4371 fputs ("<", file); break;
4373 fputs ("<<", file); break;
4375 fputs ("<<=", file); break;
4377 fputs (">=", file); break;
4379 fputs (">", file); break;
4381 fputs (">>", file); break;
4383 fputs (">>=", file); break;
4388 /* For floating point comparisons. Note that the output
4389 predicates are the complement of the desired mode. */
4391 switch (GET_CODE (x))
4394 fputs ("!=", file); break;
4396 fputs ("=", file); break;
4398 fputs ("!>", file); break;
4400 fputs ("!>=", file); break;
4402 fputs ("!<", file); break;
4404 fputs ("!<=", file); break;
4406 fputs ("!<>", file); break;
4408 fputs (">", file); break;
4410 fputs (">=", file); break;
4412 fputs ("<", file); break;
4414 fputs ("<=", file); break;
4416 fputs ("<>", file); break;
4418 fputs ("<=>", file); break;
4420 fputs ("!<=>", file); break;
4425 case 'S': /* Condition, operands are (S)wapped. */
4426 switch (GET_CODE (x))
4429 fputs ("=", file); break;
4431 fputs ("<>", file); break;
4433 fputs ("<", file); break;
4435 fputs ("<=", file); break;
4437 fputs ("<<=", file); break;
4439 fputs ("<<", file); break;
4441 fputs (">", file); break;
4443 fputs (">=", file); break;
4445 fputs (">>=", file); break;
4447 fputs (">>", file); break;
4452 case 'B': /* Condition, (B)oth swapped and negate. */
4453 switch (GET_CODE (x))
4456 fputs ("<>", file); break;
4458 fputs ("=", file); break;
4460 fputs (">=", file); break;
4462 fputs (">", file); break;
4464 fputs (">>", file); break;
4466 fputs (">>=", file); break;
4468 fputs ("<=", file); break;
4470 fputs ("<", file); break;
4472 fputs ("<<", file); break;
4474 fputs ("<<=", file); break;
4480 if (GET_CODE (x) == CONST_INT)
4482 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4487 if (GET_CODE (x) == CONST_INT)
4489 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4494 if (GET_CODE (x) == CONST_INT)
4496 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4501 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4503 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4508 if (GET_CODE (x) == CONST_INT)
4510 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4515 if (GET_CODE (x) == CONST_INT)
4517 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4522 if (GET_CODE (x) == CONST_INT)
4527 switch (GET_CODE (XEXP (x, 0)))
4531 if (ASSEMBLER_DIALECT == 0)
4532 fputs ("s,mb", file);
4534 fputs (",mb", file);
4538 if (ASSEMBLER_DIALECT == 0)
4539 fputs ("s,ma", file);
4541 fputs (",ma", file);
4544 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4545 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4547 if (ASSEMBLER_DIALECT == 0)
4548 fputs ("x,s", file);
4552 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4556 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4562 output_global_address (file, x, 0);
4565 output_global_address (file, x, 1);
4567 case 0: /* Don't do anything special */
4572 compute_zdepwi_operands (INTVAL (x), op);
4573 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4579 compute_zdepdi_operands (INTVAL (x), op);
4580 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4584 /* We can get here from a .vtable_inherit due to our
4585 CONSTANT_ADDRESS_P rejecting perfectly good constant
4591 if (GET_CODE (x) == REG)
4593 fputs (reg_names [REGNO (x)], file);
4594 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4600 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4601 && (REGNO (x) & 1) == 0)
4604 else if (GET_CODE (x) == MEM)
4606 int size = GET_MODE_SIZE (GET_MODE (x));
4607 rtx base = NULL_RTX;
4608 switch (GET_CODE (XEXP (x, 0)))
4612 base = XEXP (XEXP (x, 0), 0);
4613 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4617 base = XEXP (XEXP (x, 0), 0);
4618 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4621 if (GET_CODE (XEXP (x, 0)) == PLUS
4622 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4623 fprintf (file, "%s(%s)",
4624 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4625 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4626 else if (GET_CODE (XEXP (x, 0)) == PLUS
4627 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4628 fprintf (file, "%s(%s)",
4629 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4630 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4632 output_address (XEXP (x, 0));
4637 output_addr_const (file, x);
4640 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4643 output_global_address (file, x, round_constant)
4649 /* Imagine (high (const (plus ...))). */
4650 if (GET_CODE (x) == HIGH)
4653 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4654 assemble_name (file, XSTR (x, 0));
4655 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4657 assemble_name (file, XSTR (x, 0));
4658 fputs ("-$global$", file);
4660 else if (GET_CODE (x) == CONST)
4662 const char *sep = "";
4663 int offset = 0; /* assembler wants -$global$ at end */
4664 rtx base = NULL_RTX;
4666 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4668 base = XEXP (XEXP (x, 0), 0);
4669 output_addr_const (file, base);
4671 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4672 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4675 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4677 base = XEXP (XEXP (x, 0), 1);
4678 output_addr_const (file, base);
4680 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4681 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4684 /* How bogus. The compiler is apparently responsible for
4685 rounding the constant if it uses an LR field selector.
4687 The linker and/or assembler seem a better place since
4688 they have to do this kind of thing already.
4690 If we fail to do this, HP's optimizing linker may eliminate
4691 an addil, but not update the ldw/stw/ldo instruction that
4692 uses the result of the addil. */
4694 offset = ((offset + 0x1000) & ~0x1fff);
4696 if (GET_CODE (XEXP (x, 0)) == PLUS)
4706 else if (GET_CODE (XEXP (x, 0)) == MINUS
4707 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4711 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4712 fputs ("-$global$", file);
4714 fprintf (file, "%s%d", sep, offset);
4717 output_addr_const (file, x);
4721 output_deferred_plabels (file)
4725 /* If we have deferred plabels, then we need to switch into the data
4726 section and align it to a 4 byte boundary before we output the
4727 deferred plabels. */
4728 if (n_deferred_plabels)
4731 ASM_OUTPUT_ALIGN (file, 2);
4734 /* Now output the deferred plabels. */
4735 for (i = 0; i < n_deferred_plabels; i++)
4737 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4738 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4739 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
4743 /* HP's millicode routines mean something special to the assembler.
4744 Keep track of which ones we have used. */
4746 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
4747 static void import_milli PARAMS ((enum millicodes));
4748 static char imported[(int) end1000];
4749 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
4750 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4751 #define MILLI_START 10
4755 enum millicodes code;
4757 char str[sizeof (import_string)];
4759 if (!imported[(int) code])
4761 imported[(int) code] = 1;
4762 strcpy (str, import_string);
4763 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4764 output_asm_insn (str, 0);
4768 /* The register constraints have put the operands and return value in
4769 the proper registers. */
4772 output_mul_insn (unsignedp, insn)
4773 int unsignedp ATTRIBUTE_UNUSED;
4776 import_milli (mulI);
4777 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4780 /* Emit the rtl for doing a division by a constant. */
4782 /* Do magic division millicodes exist for this value? */
4783 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4786 /* We'll use an array to keep track of the magic millicodes and
4787 whether or not we've used them already. [n][0] is signed, [n][1] is
4790 static int div_milli[16][2];
4793 div_operand (op, mode)
4795 enum machine_mode mode;
4797 return (mode == SImode
4798 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4799 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4800 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4804 emit_hpdiv_const (operands, unsignedp)
4808 if (GET_CODE (operands[2]) == CONST_INT
4809 && INTVAL (operands[2]) > 0
4810 && INTVAL (operands[2]) < 16
4811 && magic_milli[INTVAL (operands[2])])
4813 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4815 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4818 (PARALLEL, VOIDmode,
4819 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4820 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4822 gen_rtx_REG (SImode, 26),
4824 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4825 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4826 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4827 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4828 gen_rtx_CLOBBER (VOIDmode, ret))));
4829 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4836 output_div_insn (operands, unsignedp, insn)
4843 /* If the divisor is a constant, try to use one of the special
4845 if (GET_CODE (operands[0]) == CONST_INT)
4847 static char buf[100];
4848 divisor = INTVAL (operands[0]);
4849 if (!div_milli[divisor][unsignedp])
4851 div_milli[divisor][unsignedp] = 1;
4853 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4855 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4859 sprintf (buf, "$$divU_");
4860 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4861 return output_millicode_call (insn,
4862 gen_rtx_SYMBOL_REF (SImode, buf));
4866 sprintf (buf, "$$divI_");
4867 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4868 return output_millicode_call (insn,
4869 gen_rtx_SYMBOL_REF (SImode, buf));
4872 /* Divisor isn't a special constant. */
4877 import_milli (divU);
4878 return output_millicode_call (insn,
4879 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4883 import_milli (divI);
4884 return output_millicode_call (insn,
4885 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4890 /* Output a $$rem millicode to do mod. */
4893 output_mod_insn (unsignedp, insn)
4899 import_milli (remU);
4900 return output_millicode_call (insn,
4901 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4905 import_milli (remI);
4906 return output_millicode_call (insn,
4907 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4912 output_arg_descriptor (call_insn)
4915 const char *arg_regs[4];
4916 enum machine_mode arg_mode;
4918 int i, output_flag = 0;
4921 /* We neither need nor want argument location descriptors for the
4922 64bit runtime environment or the ELF32 environment. */
4923 if (TARGET_64BIT || TARGET_ELF32)
4926 for (i = 0; i < 4; i++)
4929 /* Specify explicitly that no argument relocations should take place
4930 if using the portable runtime calling conventions. */
4931 if (TARGET_PORTABLE_RUNTIME)
4933 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4938 if (GET_CODE (call_insn) != CALL_INSN)
4940 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4942 rtx use = XEXP (link, 0);
4944 if (! (GET_CODE (use) == USE
4945 && GET_CODE (XEXP (use, 0)) == REG
4946 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4949 arg_mode = GET_MODE (XEXP (use, 0));
4950 regno = REGNO (XEXP (use, 0));
4951 if (regno >= 23 && regno <= 26)
4953 arg_regs[26 - regno] = "GR";
4954 if (arg_mode == DImode)
4955 arg_regs[25 - regno] = "GR";
4957 else if (regno >= 32 && regno <= 39)
4959 if (arg_mode == SFmode)
4960 arg_regs[(regno - 32) / 2] = "FR";
4963 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4964 arg_regs[(regno - 34) / 2] = "FR";
4965 arg_regs[(regno - 34) / 2 + 1] = "FU";
4967 arg_regs[(regno - 34) / 2] = "FU";
4968 arg_regs[(regno - 34) / 2 + 1] = "FR";
4973 fputs ("\t.CALL ", asm_out_file);
4974 for (i = 0; i < 4; i++)
4979 fputc (',', asm_out_file);
4980 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4983 fputc ('\n', asm_out_file);
4986 /* Return the class of any secondary reload register that is needed to
4987 move IN into a register in class CLASS using mode MODE.
4989 Profiling has showed this routine and its descendants account for
4990 a significant amount of compile time (~7%). So it has been
4991 optimized to reduce redundant computations and eliminate useless
4994 It might be worthwhile to try and make this a leaf function too. */
4997 secondary_reload_class (class, mode, in)
4998 enum reg_class class;
4999 enum machine_mode mode;
5002 int regno, is_symbolic;
5004 /* Trying to load a constant into a FP register during PIC code
5005 generation will require %r1 as a scratch register. */
5007 && GET_MODE_CLASS (mode) == MODE_INT
5008 && FP_REG_CLASS_P (class)
5009 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5012 /* Profiling showed the PA port spends about 1.3% of its compilation
5013 time in true_regnum from calls inside secondary_reload_class. */
5015 if (GET_CODE (in) == REG)
5018 if (regno >= FIRST_PSEUDO_REGISTER)
5019 regno = true_regnum (in);
5021 else if (GET_CODE (in) == SUBREG)
5022 regno = true_regnum (in);
5026 /* If we have something like (mem (mem (...)), we can safely assume the
5027 inner MEM will end up in a general register after reloading, so there's
5028 no need for a secondary reload. */
5029 if (GET_CODE (in) == MEM
5030 && GET_CODE (XEXP (in, 0)) == MEM)
5033 /* Handle out of range displacement for integer mode loads/stores of
5035 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5036 && GET_MODE_CLASS (mode) == MODE_INT
5037 && FP_REG_CLASS_P (class))
5038 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5039 return GENERAL_REGS;
5041 /* A SAR<->FP register copy requires a secondary register (GPR) as
5042 well as secondary memory. */
5043 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5044 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5045 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5046 return GENERAL_REGS;
5048 if (GET_CODE (in) == HIGH)
5051 /* Profiling has showed GCC spends about 2.6% of its compilation
5052 time in symbolic_operand from calls inside secondary_reload_class.
5054 We use an inline copy and only compute its return value once to avoid
5056 switch (GET_CODE (in))
5066 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5067 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5068 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5078 && read_only_operand (in, VOIDmode))
5081 if (class != R1_REGS && is_symbolic)
5088 function_arg_padding (mode, type)
5089 enum machine_mode mode;
5093 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5095 /* Return none if justification is not required. */
5097 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5098 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5101 /* The directions set here are ignored when a BLKmode argument larger
5102 than a word is placed in a register. Different code is used for
5103 the stack and registers. This makes it difficult to have a
5104 consistent data representation for both the stack and registers.
5105 For both runtimes, the justification and padding for arguments on
5106 the stack and in registers should be identical. */
5108 /* The 64-bit runtime specifies left justification for aggregates. */
5111 /* The 32-bit runtime architecture specifies right justification.
5112 When the argument is passed on the stack, the argument is padded
5113 with garbage on the left. The HP compiler pads with zeros. */
5117 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5124 /* Do what is necessary for `va_start'. We look at the current function
5125 to determine if stdargs or varargs is used and fill in an initial
5126 va_list. A pointer to this constructor is returned. */
5129 hppa_builtin_saveregs ()
5132 tree fntype = TREE_TYPE (current_function_decl);
5133 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5134 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5135 != void_type_node)))
5136 ? UNITS_PER_WORD : 0);
5139 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5141 offset = current_function_arg_offset_rtx;
5147 /* Adjust for varargs/stdarg differences. */
5149 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5151 offset = current_function_arg_offset_rtx;
5153 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5154 from the incoming arg pointer and growing to larger addresses. */
5155 for (i = 26, off = -64; i >= 19; i--, off += 8)
5156 emit_move_insn (gen_rtx_MEM (word_mode,
5157 plus_constant (arg_pointer_rtx, off)),
5158 gen_rtx_REG (word_mode, i));
5160 /* The incoming args pointer points just beyond the flushback area;
5161 normally this is not a serious concern. However, when we are doing
5162 varargs/stdargs we want to make the arg pointer point to the start
5163 of the incoming argument area. */
5164 emit_move_insn (virtual_incoming_args_rtx,
5165 plus_constant (arg_pointer_rtx, -64));
5167 /* Now return a pointer to the first anonymous argument. */
5168 return copy_to_reg (expand_binop (Pmode, add_optab,
5169 virtual_incoming_args_rtx,
5170 offset, 0, 0, OPTAB_LIB_WIDEN));
5173 /* Store general registers on the stack. */
5174 dest = gen_rtx_MEM (BLKmode,
5175 plus_constant (current_function_internal_arg_pointer,
5177 set_mem_alias_set (dest, get_varargs_alias_set ());
5178 set_mem_align (dest, BITS_PER_WORD);
5179 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
5181 /* move_block_from_reg will emit code to store the argument registers
5182 individually as scalar stores.
5184 However, other insns may later load from the same addresses for
5185 a structure load (passing a struct to a varargs routine).
5187 The alias code assumes that such aliasing can never happen, so we
5188 have to keep memory referencing insns from moving up beyond the
5189 last argument register store. So we emit a blockage insn here. */
5190 emit_insn (gen_blockage ());
5192 return copy_to_reg (expand_binop (Pmode, add_optab,
5193 current_function_internal_arg_pointer,
5194 offset, 0, 0, OPTAB_LIB_WIDEN));
5198 hppa_va_start (valist, nextarg)
5202 nextarg = expand_builtin_saveregs ();
5203 std_expand_builtin_va_start (valist, nextarg);
5207 hppa_va_arg (valist, type)
5210 HOST_WIDE_INT size = int_size_in_bytes (type);
5216 /* Every argument in PA64 is supposed to be passed by value
5217 (including large structs). However, as a GCC extension, we
5218 pass zero and variable sized arguments by reference. Empty
5219 structures are a GCC extension not supported by the HP
5220 compilers. Thus, passing them by reference isn't likely
5221 to conflict with the ABI. For variable sized arguments,
5222 GCC doesn't have the infrastructure to allocate these to
5225 /* Arguments with a size greater than 8 must be aligned 0 MOD 16. */
5227 if (size > UNITS_PER_WORD)
5229 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5230 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5231 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5232 build_int_2 (-2 * UNITS_PER_WORD, -1));
5233 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5234 TREE_SIDE_EFFECTS (t) = 1;
5235 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5239 return std_expand_builtin_va_arg (valist, type);
5242 ptr = build_pointer_type (type);
5244 /* Args grow upward. */
5245 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
5246 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5247 TREE_SIDE_EFFECTS (t) = 1;
5249 pptr = build_pointer_type (ptr);
5250 t = build1 (NOP_EXPR, pptr, t);
5251 TREE_SIDE_EFFECTS (t) = 1;
5253 t = build1 (INDIRECT_REF, ptr, t);
5254 TREE_SIDE_EFFECTS (t) = 1;
5257 else /* !TARGET_64BIT */
5259 ptr = build_pointer_type (type);
5261 /* "Large" and variable sized types are passed by reference. */
5262 if (size > 8 || size <= 0)
5264 /* Args grow downward. */
5265 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5266 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5267 TREE_SIDE_EFFECTS (t) = 1;
5269 pptr = build_pointer_type (ptr);
5270 t = build1 (NOP_EXPR, pptr, t);
5271 TREE_SIDE_EFFECTS (t) = 1;
5273 t = build1 (INDIRECT_REF, ptr, t);
5274 TREE_SIDE_EFFECTS (t) = 1;
5278 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5279 build_int_2 (-size, -1));
5281 /* Copied from va-pa.h, but we probably don't need to align to
5282 word size, since we generate and preserve that invariant. */
5283 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5284 build_int_2 ((size > 4 ? -8 : -4), -1));
5286 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5287 TREE_SIDE_EFFECTS (t) = 1;
5289 ofs = (8 - size) % 4;
5292 t = build (PLUS_EXPR, TREE_TYPE (valist), t,
5293 build_int_2 (ofs, 0));
5294 TREE_SIDE_EFFECTS (t) = 1;
5297 t = build1 (NOP_EXPR, ptr, t);
5298 TREE_SIDE_EFFECTS (t) = 1;
5303 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
5308 /* This routine handles all the normal conditional branch sequences we
5309 might need to generate. It handles compare immediate vs compare
5310 register, nullification of delay slots, varying length branches,
5311 negated branches, and all combinations of the above. It returns the
5312 output appropriate to emit the branch corresponding to all given
5316 output_cbranch (operands, nullify, length, negated, insn)
5318 int nullify, length, negated;
5321 static char buf[100];
5324 /* A conditional branch to the following instruction (eg the delay slot) is
5325 asking for a disaster. This can happen when not optimizing.
5327 In such cases it is safe to emit nothing. */
5329 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5332 /* If this is a long branch with its delay slot unfilled, set `nullify'
5333 as it can nullify the delay slot and save a nop. */
5334 if (length == 8 && dbr_sequence_length () == 0)
5337 /* If this is a short forward conditional branch which did not get
5338 its delay slot filled, the delay slot can still be nullified. */
5339 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5340 nullify = forward_branch_p (insn);
5342 /* A forward branch over a single nullified insn can be done with a
5343 comclr instruction. This avoids a single cycle penalty due to
5344 mis-predicted branch if we fall through (branch not taken). */
5346 && next_real_insn (insn) != 0
5347 && get_attr_length (next_real_insn (insn)) == 4
5348 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5354 /* All short conditional branches except backwards with an unfilled
5358 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5360 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5361 if (GET_MODE (operands[1]) == DImode)
5364 strcat (buf, "%B3");
5366 strcat (buf, "%S3");
5368 strcat (buf, " %2,%r1,%%r0");
5370 strcat (buf, ",n %2,%r1,%0");
5372 strcat (buf, " %2,%r1,%0");
5375 /* All long conditionals. Note an short backward branch with an
5376 unfilled delay slot is treated just like a long backward branch
5377 with an unfilled delay slot. */
5379 /* Handle weird backwards branch with a filled delay slot
5380 with is nullified. */
5381 if (dbr_sequence_length () != 0
5382 && ! forward_branch_p (insn)
5385 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5386 if (GET_MODE (operands[1]) == DImode)
5389 strcat (buf, "%S3");
5391 strcat (buf, "%B3");
5392 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5394 /* Handle short backwards branch with an unfilled delay slot.
5395 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5396 taken and untaken branches. */
5397 else if (dbr_sequence_length () == 0
5398 && ! forward_branch_p (insn)
5399 && INSN_ADDRESSES_SET_P ()
5400 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5401 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5403 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5404 if (GET_MODE (operands[1]) == DImode)
5407 strcat (buf, "%B3 %2,%r1,%0%#");
5409 strcat (buf, "%S3 %2,%r1,%0%#");
5413 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5414 if (GET_MODE (operands[1]) == DImode)
5417 strcat (buf, "%S3");
5419 strcat (buf, "%B3");
5421 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5423 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5428 /* Very long branch. Right now we only handle these when not
5429 optimizing. See "jump" pattern in pa.md for details. */
5433 /* Create a reversed conditional branch which branches around
5434 the following insns. */
5436 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5438 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5439 if (GET_MODE (operands[1]) == DImode)
5443 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5446 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5448 output_asm_insn (buf, operands);
5450 /* Output an insn to save %r1. */
5451 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5453 /* Now output a very long branch to the original target. */
5454 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5456 /* Now restore the value of %r1 in the delay slot. We're not
5457 optimizing so we know nothing else can be in the delay slot. */
5458 return "ldw -16(%%r30),%%r1";
5461 /* Very long branch when generating PIC code. Right now we only
5462 handle these when not optimizing. See "jump" pattern in pa.md
5467 /* Create a reversed conditional branch which branches around
5468 the following insns. */
5470 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5472 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5473 if (GET_MODE (operands[1]) == DImode)
5476 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5478 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5480 output_asm_insn (buf, operands);
5482 /* Output an insn to save %r1. */
5483 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5485 /* Now output a very long PIC branch to the original target. */
5489 xoperands[0] = operands[0];
5490 xoperands[1] = operands[1];
5491 xoperands[2] = operands[2];
5492 xoperands[3] = operands[3];
5493 if (TARGET_SOM || ! TARGET_GAS)
5494 xoperands[4] = gen_label_rtx ();
5496 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5497 if (TARGET_SOM || ! TARGET_GAS)
5499 output_asm_insn ("addil L'%l0-%l4,%%r1", xoperands);
5500 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5501 CODE_LABEL_NUMBER (xoperands[4]));
5502 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1", xoperands);
5506 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
5507 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1",
5510 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5513 /* Now restore the value of %r1 in the delay slot. We're not
5514 optimizing so we know nothing else can be in the delay slot. */
5515 return "ldw -16(%%r30),%%r1";
5523 /* This routine handles all the branch-on-bit conditional branch sequences we
5524 might need to generate. It handles nullification of delay slots,
5525 varying length branches, negated branches and all combinations of the
5526 above. it returns the appropriate output template to emit the branch. */
5529 output_bb (operands, nullify, length, negated, insn, which)
5530 rtx *operands ATTRIBUTE_UNUSED;
5531 int nullify, length, negated;
5535 static char buf[100];
5538 /* A conditional branch to the following instruction (eg the delay slot) is
5539 asking for a disaster. I do not think this can happen as this pattern
5540 is only used when optimizing; jump optimization should eliminate the
5541 jump. But be prepared just in case. */
5543 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5546 /* If this is a long branch with its delay slot unfilled, set `nullify'
5547 as it can nullify the delay slot and save a nop. */
5548 if (length == 8 && dbr_sequence_length () == 0)
5551 /* If this is a short forward conditional branch which did not get
5552 its delay slot filled, the delay slot can still be nullified. */
5553 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5554 nullify = forward_branch_p (insn);
5556 /* A forward branch over a single nullified insn can be done with a
5557 extrs instruction. This avoids a single cycle penalty due to
5558 mis-predicted branch if we fall through (branch not taken). */
5561 && next_real_insn (insn) != 0
5562 && get_attr_length (next_real_insn (insn)) == 4
5563 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5570 /* All short conditional branches except backwards with an unfilled
5574 strcpy (buf, "{extrs,|extrw,s,}");
5576 strcpy (buf, "bb,");
5577 if (useskip && GET_MODE (operands[0]) == DImode)
5578 strcpy (buf, "extrd,s,*");
5579 else if (GET_MODE (operands[0]) == DImode)
5580 strcpy (buf, "bb,*");
5581 if ((which == 0 && negated)
5582 || (which == 1 && ! negated))
5587 strcat (buf, " %0,%1,1,%%r0");
5588 else if (nullify && negated)
5589 strcat (buf, ",n %0,%1,%3");
5590 else if (nullify && ! negated)
5591 strcat (buf, ",n %0,%1,%2");
5592 else if (! nullify && negated)
5593 strcat (buf, "%0,%1,%3");
5594 else if (! nullify && ! negated)
5595 strcat (buf, " %0,%1,%2");
5598 /* All long conditionals. Note an short backward branch with an
5599 unfilled delay slot is treated just like a long backward branch
5600 with an unfilled delay slot. */
5602 /* Handle weird backwards branch with a filled delay slot
5603 with is nullified. */
5604 if (dbr_sequence_length () != 0
5605 && ! forward_branch_p (insn)
5608 strcpy (buf, "bb,");
5609 if (GET_MODE (operands[0]) == DImode)
5611 if ((which == 0 && negated)
5612 || (which == 1 && ! negated))
5617 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5619 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5621 /* Handle short backwards branch with an unfilled delay slot.
5622 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5623 taken and untaken branches. */
5624 else if (dbr_sequence_length () == 0
5625 && ! forward_branch_p (insn)
5626 && INSN_ADDRESSES_SET_P ()
5627 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5628 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5630 strcpy (buf, "bb,");
5631 if (GET_MODE (operands[0]) == DImode)
5633 if ((which == 0 && negated)
5634 || (which == 1 && ! negated))
5639 strcat (buf, " %0,%1,%3%#");
5641 strcat (buf, " %0,%1,%2%#");
5645 strcpy (buf, "{extrs,|extrw,s,}");
5646 if (GET_MODE (operands[0]) == DImode)
5647 strcpy (buf, "extrd,s,*");
5648 if ((which == 0 && negated)
5649 || (which == 1 && ! negated))
5653 if (nullify && negated)
5654 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5655 else if (nullify && ! negated)
5656 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5658 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5660 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5670 /* This routine handles all the branch-on-variable-bit conditional branch
5671 sequences we might need to generate. It handles nullification of delay
5672 slots, varying length branches, negated branches and all combinations
5673 of the above. it returns the appropriate output template to emit the
5677 output_bvb (operands, nullify, length, negated, insn, which)
5678 rtx *operands ATTRIBUTE_UNUSED;
5679 int nullify, length, negated;
5683 static char buf[100];
5686 /* A conditional branch to the following instruction (eg the delay slot) is
5687 asking for a disaster. I do not think this can happen as this pattern
5688 is only used when optimizing; jump optimization should eliminate the
5689 jump. But be prepared just in case. */
5691 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5694 /* If this is a long branch with its delay slot unfilled, set `nullify'
5695 as it can nullify the delay slot and save a nop. */
5696 if (length == 8 && dbr_sequence_length () == 0)
5699 /* If this is a short forward conditional branch which did not get
5700 its delay slot filled, the delay slot can still be nullified. */
5701 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5702 nullify = forward_branch_p (insn);
5704 /* A forward branch over a single nullified insn can be done with a
5705 extrs instruction. This avoids a single cycle penalty due to
5706 mis-predicted branch if we fall through (branch not taken). */
5709 && next_real_insn (insn) != 0
5710 && get_attr_length (next_real_insn (insn)) == 4
5711 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5718 /* All short conditional branches except backwards with an unfilled
5722 strcpy (buf, "{vextrs,|extrw,s,}");
5724 strcpy (buf, "{bvb,|bb,}");
5725 if (useskip && GET_MODE (operands[0]) == DImode)
5726 strcpy (buf, "extrd,s,*}");
5727 else if (GET_MODE (operands[0]) == DImode)
5728 strcpy (buf, "bb,*");
5729 if ((which == 0 && negated)
5730 || (which == 1 && ! negated))
5735 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5736 else if (nullify && negated)
5737 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5738 else if (nullify && ! negated)
5739 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5740 else if (! nullify && negated)
5741 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5742 else if (! nullify && ! negated)
5743 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5746 /* All long conditionals. Note an short backward branch with an
5747 unfilled delay slot is treated just like a long backward branch
5748 with an unfilled delay slot. */
5750 /* Handle weird backwards branch with a filled delay slot
5751 with is nullified. */
5752 if (dbr_sequence_length () != 0
5753 && ! forward_branch_p (insn)
5756 strcpy (buf, "{bvb,|bb,}");
5757 if (GET_MODE (operands[0]) == DImode)
5759 if ((which == 0 && negated)
5760 || (which == 1 && ! negated))
5765 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5767 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5769 /* Handle short backwards branch with an unfilled delay slot.
5770 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5771 taken and untaken branches. */
5772 else if (dbr_sequence_length () == 0
5773 && ! forward_branch_p (insn)
5774 && INSN_ADDRESSES_SET_P ()
5775 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5776 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5778 strcpy (buf, "{bvb,|bb,}");
5779 if (GET_MODE (operands[0]) == DImode)
5781 if ((which == 0 && negated)
5782 || (which == 1 && ! negated))
5787 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5789 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5793 strcpy (buf, "{vextrs,|extrw,s,}");
5794 if (GET_MODE (operands[0]) == DImode)
5795 strcpy (buf, "extrd,s,*");
5796 if ((which == 0 && negated)
5797 || (which == 1 && ! negated))
5801 if (nullify && negated)
5802 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5803 else if (nullify && ! negated)
5804 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5806 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5808 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5818 /* Return the output template for emitting a dbra type insn.
5820 Note it may perform some output operations on its own before
5821 returning the final output string. */
5823 output_dbra (operands, insn, which_alternative)
5826 int which_alternative;
5829 /* A conditional branch to the following instruction (eg the delay slot) is
5830 asking for a disaster. Be prepared! */
5832 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5834 if (which_alternative == 0)
5835 return "ldo %1(%0),%0";
5836 else if (which_alternative == 1)
5838 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5839 output_asm_insn ("ldw -16(%%r30),%4", operands);
5840 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5841 return "{fldws|fldw} -16(%%r30),%0";
5845 output_asm_insn ("ldw %0,%4", operands);
5846 return "ldo %1(%4),%4\n\tstw %4,%0";
5850 if (which_alternative == 0)
5852 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5853 int length = get_attr_length (insn);
5855 /* If this is a long branch with its delay slot unfilled, set `nullify'
5856 as it can nullify the delay slot and save a nop. */
5857 if (length == 8 && dbr_sequence_length () == 0)
5860 /* If this is a short forward conditional branch which did not get
5861 its delay slot filled, the delay slot can still be nullified. */
5862 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5863 nullify = forward_branch_p (insn);
5865 /* Handle short versions first. */
5866 if (length == 4 && nullify)
5867 return "addib,%C2,n %1,%0,%3";
5868 else if (length == 4 && ! nullify)
5869 return "addib,%C2 %1,%0,%3";
5870 else if (length == 8)
5872 /* Handle weird backwards branch with a fulled delay slot
5873 which is nullified. */
5874 if (dbr_sequence_length () != 0
5875 && ! forward_branch_p (insn)
5877 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5878 /* Handle short backwards branch with an unfilled delay slot.
5879 Using a addb;nop rather than addi;bl saves 1 cycle for both
5880 taken and untaken branches. */
5881 else if (dbr_sequence_length () == 0
5882 && ! forward_branch_p (insn)
5883 && INSN_ADDRESSES_SET_P ()
5884 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5885 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5886 return "addib,%C2 %1,%0,%3%#";
5888 /* Handle normal cases. */
5890 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5892 return "addi,%N2 %1,%0,%0\n\tb %3";
5897 /* Deal with gross reload from FP register case. */
5898 else if (which_alternative == 1)
5900 /* Move loop counter from FP register to MEM then into a GR,
5901 increment the GR, store the GR into MEM, and finally reload
5902 the FP register from MEM from within the branch's delay slot. */
5903 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5905 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5906 if (get_attr_length (insn) == 24)
5907 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5909 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5911 /* Deal with gross reload from memory case. */
5914 /* Reload loop counter from memory, the store back to memory
5915 happens in the branch's delay slot. */
5916 output_asm_insn ("ldw %0,%4", operands);
5917 if (get_attr_length (insn) == 12)
5918 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5920 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5924 /* Return the output template for emitting a dbra type insn.
5926 Note it may perform some output operations on its own before
5927 returning the final output string. */
5929 output_movb (operands, insn, which_alternative, reverse_comparison)
5932 int which_alternative;
5933 int reverse_comparison;
5936 /* A conditional branch to the following instruction (eg the delay slot) is
5937 asking for a disaster. Be prepared! */
5939 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5941 if (which_alternative == 0)
5942 return "copy %1,%0";
5943 else if (which_alternative == 1)
5945 output_asm_insn ("stw %1,-16(%%r30)", operands);
5946 return "{fldws|fldw} -16(%%r30),%0";
5948 else if (which_alternative == 2)
5954 /* Support the second variant. */
5955 if (reverse_comparison)
5956 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5958 if (which_alternative == 0)
5960 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5961 int length = get_attr_length (insn);
5963 /* If this is a long branch with its delay slot unfilled, set `nullify'
5964 as it can nullify the delay slot and save a nop. */
5965 if (length == 8 && dbr_sequence_length () == 0)
5968 /* If this is a short forward conditional branch which did not get
5969 its delay slot filled, the delay slot can still be nullified. */
5970 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5971 nullify = forward_branch_p (insn);
5973 /* Handle short versions first. */
5974 if (length == 4 && nullify)
5975 return "movb,%C2,n %1,%0,%3";
5976 else if (length == 4 && ! nullify)
5977 return "movb,%C2 %1,%0,%3";
5978 else if (length == 8)
5980 /* Handle weird backwards branch with a filled delay slot
5981 which is nullified. */
5982 if (dbr_sequence_length () != 0
5983 && ! forward_branch_p (insn)
5985 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5987 /* Handle short backwards branch with an unfilled delay slot.
5988 Using a movb;nop rather than or;bl saves 1 cycle for both
5989 taken and untaken branches. */
5990 else if (dbr_sequence_length () == 0
5991 && ! forward_branch_p (insn)
5992 && INSN_ADDRESSES_SET_P ()
5993 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5994 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5995 return "movb,%C2 %1,%0,%3%#";
5996 /* Handle normal cases. */
5998 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6000 return "or,%N2 %1,%%r0,%0\n\tb %3";
6005 /* Deal with gross reload from FP register case. */
6006 else if (which_alternative == 1)
6008 /* Move loop counter from FP register to MEM then into a GR,
6009 increment the GR, store the GR into MEM, and finally reload
6010 the FP register from MEM from within the branch's delay slot. */
6011 output_asm_insn ("stw %1,-16(%%r30)", operands);
6012 if (get_attr_length (insn) == 12)
6013 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6015 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6017 /* Deal with gross reload from memory case. */
6018 else if (which_alternative == 2)
6020 /* Reload loop counter from memory, the store back to memory
6021 happens in the branch's delay slot. */
6022 if (get_attr_length (insn) == 8)
6023 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6025 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6027 /* Handle SAR as a destination. */
6030 if (get_attr_length (insn) == 8)
6031 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6033 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6038 /* INSN is a millicode call. It may have an unconditional jump in its delay
6041 CALL_DEST is the routine we are calling. */
6044 output_millicode_call (insn, call_dest)
6048 int attr_length = get_attr_length (insn);
6049 int seq_length = dbr_sequence_length ();
6054 xoperands[3] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6056 /* Handle common case -- empty delay slot or no jump in the delay slot,
6057 and we're sure that the branch will reach the beginning of the $CODE$
6058 subspace. The within reach form of the $$sh_func_adrs call has
6059 a length of 28 and attribute type of multi. This length is the
6060 same as the maximum length of an out of reach PIC call to $$div. */
6061 if ((seq_length == 0
6062 && (attr_length == 8
6063 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6065 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6066 && attr_length == 4))
6068 xoperands[0] = call_dest;
6069 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
6073 /* This call may not reach the beginning of the $CODE$ subspace. */
6074 if (attr_length > 8)
6076 int delay_insn_deleted = 0;
6078 /* We need to emit an inline long-call branch. */
6080 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6082 /* A non-jump insn in the delay slot. By definition we can
6083 emit this insn before the call. */
6084 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6086 /* Now delete the delay insn. */
6087 PUT_CODE (NEXT_INSN (insn), NOTE);
6088 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6089 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6090 delay_insn_deleted = 1;
6093 /* PIC long millicode call sequence. */
6096 xoperands[0] = call_dest;
6097 if (TARGET_SOM || ! TARGET_GAS)
6098 xoperands[1] = gen_label_rtx ();
6100 /* Get our address + 8 into %r1. */
6101 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6103 if (TARGET_SOM || ! TARGET_GAS)
6105 /* Add %r1 to the offset of our target from the next insn. */
6106 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
6107 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6108 CODE_LABEL_NUMBER (xoperands[1]));
6109 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
6113 output_asm_insn ("addil L%%%0-$PIC_pcrel$0+4,%%r1", xoperands);
6114 output_asm_insn ("ldo R%%%0-$PIC_pcrel$0+8(%%r1),%%r1",
6118 /* Get the return address into %r31. */
6119 output_asm_insn ("blr 0,%3", xoperands);
6121 /* Branch to our target which is in %r1. */
6122 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
6124 /* Empty delay slot. Note this insn gets fetched twice and
6125 executed once. To be safe we use a nop. */
6126 output_asm_insn ("nop", xoperands);
6128 /* Pure portable runtime doesn't allow be/ble; we also don't have
6129 PIC support in the assembler/linker, so this sequence is needed. */
6130 else if (TARGET_PORTABLE_RUNTIME)
6132 xoperands[0] = call_dest;
6133 /* Get the address of our target into %r29. */
6134 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
6135 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
6137 /* Get our return address into %r31. */
6138 output_asm_insn ("blr %%r0,%3", xoperands);
6140 /* Jump to our target address in %r29. */
6141 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
6143 /* Empty delay slot. Note this insn gets fetched twice and
6144 executed once. To be safe we use a nop. */
6145 output_asm_insn ("nop", xoperands);
6147 /* If we're allowed to use be/ble instructions, then this is the
6148 best sequence to use for a long millicode call. */
6151 xoperands[0] = call_dest;
6152 output_asm_insn ("ldil L%%%0,%3", xoperands);
6154 output_asm_insn ("be,l R%%%0(%%sr4,%3),%%sr0,%%r31", xoperands);
6156 output_asm_insn ("ble R%%%0(%%sr4,%3)", xoperands);
6157 output_asm_insn ("nop", xoperands);
6160 /* If we had a jump in the call's delay slot, output it now. */
6161 if (seq_length != 0 && !delay_insn_deleted)
6163 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6164 output_asm_insn ("b,n %0", xoperands);
6166 /* Now delete the delay insn. */
6167 PUT_CODE (NEXT_INSN (insn), NOTE);
6168 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6169 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6174 /* This call has an unconditional jump in its delay slot and the
6175 call is known to reach its target or the beginning of the current
6178 /* Use the containing sequence insn's address. */
6179 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6181 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6182 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6184 /* If the branch was too far away, emit a normal call followed
6185 by a nop, followed by the unconditional branch.
6187 If the branch is close, then adjust %r2 from within the
6188 call's delay slot. */
6190 xoperands[0] = call_dest;
6191 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6192 if (! VAL_14_BITS_P (distance))
6193 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
6196 xoperands[2] = gen_label_rtx ();
6197 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
6199 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6200 CODE_LABEL_NUMBER (xoperands[2]));
6203 /* Delete the jump. */
6204 PUT_CODE (NEXT_INSN (insn), NOTE);
6205 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6206 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6210 /* INSN is either a function call. It may have an unconditional jump
6213 CALL_DEST is the routine we are calling. */
6216 output_call (insn, call_dest, sibcall)
6221 int attr_length = get_attr_length (insn);
6222 int seq_length = dbr_sequence_length ();
6227 /* Handle common case -- empty delay slot or no jump in the delay slot,
6228 and we're sure that the branch will reach the beginning of the $CODE$
6230 if ((seq_length == 0 && attr_length == 12)
6232 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6233 && attr_length == 8))
6235 xoperands[0] = call_dest;
6236 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
6237 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
6241 /* This call may not reach the beginning of the $CODE$ subspace. */
6242 if (attr_length > 12)
6244 int delay_insn_deleted = 0;
6248 /* We need to emit an inline long-call branch. Furthermore,
6249 because we're changing a named function call into an indirect
6250 function call well after the parameters have been set up, we
6251 need to make sure any FP args appear in both the integer
6252 and FP registers. Also, we need move any delay slot insn
6253 out of the delay slot. And finally, we can't rely on the linker
6254 being able to fix the call to $$dyncall! -- Yuk!. */
6256 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6258 /* A non-jump insn in the delay slot. By definition we can
6259 emit this insn before the call (and in fact before argument
6261 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6263 /* Now delete the delay insn. */
6264 PUT_CODE (NEXT_INSN (insn), NOTE);
6265 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6266 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6267 delay_insn_deleted = 1;
6270 /* Now copy any FP arguments into integer registers. */
6271 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6273 int arg_mode, regno;
6274 rtx use = XEXP (link, 0);
6275 if (! (GET_CODE (use) == USE
6276 && GET_CODE (XEXP (use, 0)) == REG
6277 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6280 arg_mode = GET_MODE (XEXP (use, 0));
6281 regno = REGNO (XEXP (use, 0));
6282 /* Is it a floating point register? */
6283 if (regno >= 32 && regno <= 39)
6285 /* Copy from the FP register into an integer register
6287 if (arg_mode == SFmode)
6289 xoperands[0] = XEXP (use, 0);
6290 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6291 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
6293 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6297 xoperands[0] = XEXP (use, 0);
6298 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6299 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
6301 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6302 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6307 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
6308 we don't have any direct calls in that case. */
6311 const char *name = XSTR (call_dest, 0);
6313 /* See if we have already put this function on the list
6314 of deferred plabels. This list is generally small,
6315 so a liner search is not too ugly. If it proves too
6316 slow replace it with something faster. */
6317 for (i = 0; i < n_deferred_plabels; i++)
6318 if (strcmp (name, deferred_plabels[i].name) == 0)
6321 /* If the deferred plabel list is empty, or this entry was
6322 not found on the list, create a new entry on the list. */
6323 if (deferred_plabels == NULL || i == n_deferred_plabels)
6325 const char *real_name;
6327 if (deferred_plabels == 0)
6328 deferred_plabels = (struct deferred_plabel *)
6329 ggc_alloc (sizeof (struct deferred_plabel));
6331 deferred_plabels = (struct deferred_plabel *)
6332 ggc_realloc (deferred_plabels,
6333 ((n_deferred_plabels + 1)
6334 * sizeof (struct deferred_plabel)));
6336 i = n_deferred_plabels++;
6337 deferred_plabels[i].internal_label = gen_label_rtx ();
6338 deferred_plabels[i].name = ggc_strdup (name);
6340 /* Gross. We have just implicitly taken the address of this
6341 function, mark it as such. */
6342 real_name = (*targetm.strip_name_encoding) (name);
6343 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
6346 /* We have to load the address of the function using a procedure
6347 label (plabel). Inline plabels can lose for PIC and other
6348 cases, so avoid them by creating a 32bit plabel in the data
6352 xoperands[0] = deferred_plabels[i].internal_label;
6353 if (TARGET_SOM || ! TARGET_GAS)
6354 xoperands[1] = gen_label_rtx ();
6356 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
6357 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
6358 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
6360 /* Get our address + 8 into %r1. */
6361 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6363 if (TARGET_SOM || ! TARGET_GAS)
6365 /* Add %r1 to the offset of dyncall from the next insn. */
6366 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
6367 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6368 CODE_LABEL_NUMBER (xoperands[1]));
6369 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
6373 output_asm_insn ("addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1",
6375 output_asm_insn ("ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
6379 /* Get the return address into %r31. */
6380 output_asm_insn ("blr %%r0,%%r31", xoperands);
6382 /* Branch to our target which is in %r1. */
6383 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6387 /* This call never returns, so we do not need to fix the
6389 output_asm_insn ("nop", xoperands);
6393 /* Copy the return address into %r2 also. */
6394 output_asm_insn ("copy %%r31,%%r2", xoperands);
6399 xoperands[0] = deferred_plabels[i].internal_label;
6401 /* Get the address of our target into %r22. */
6402 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
6403 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
6405 /* Get the high part of the address of $dyncall into %r2, then
6406 add in the low part in the branch instruction. */
6407 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
6409 output_asm_insn ("be,l R%%$$dyncall(%%sr4,%%r2),%%sr0,%%r31",
6412 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands);
6416 /* This call never returns, so we do not need to fix the
6418 output_asm_insn ("nop", xoperands);
6422 /* Copy the return address into %r2 also. */
6423 output_asm_insn ("copy %%r31,%%r2", xoperands);
6428 /* If we had a jump in the call's delay slot, output it now. */
6429 if (seq_length != 0 && !delay_insn_deleted)
6431 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6432 output_asm_insn ("b,n %0", xoperands);
6434 /* Now delete the delay insn. */
6435 PUT_CODE (NEXT_INSN (insn), NOTE);
6436 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6437 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6442 /* This call has an unconditional jump in its delay slot and the
6443 call is known to reach its target or the beginning of the current
6446 /* Use the containing sequence insn's address. */
6447 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6449 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6450 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6452 /* If the branch is too far away, emit a normal call followed
6453 by a nop, followed by the unconditional branch. If the branch
6454 is close, then adjust %r2 in the call's delay slot. */
6456 xoperands[0] = call_dest;
6457 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6458 if (! VAL_14_BITS_P (distance))
6459 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
6462 xoperands[3] = gen_label_rtx ();
6463 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6465 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6466 CODE_LABEL_NUMBER (xoperands[3]));
6469 /* Delete the jump. */
6470 PUT_CODE (NEXT_INSN (insn), NOTE);
6471 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6472 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6476 /* In HPUX 8.0's shared library scheme, special relocations are needed
6477 for function labels if they might be passed to a function
6478 in a shared library (because shared libraries don't live in code
6479 space), and special magic is needed to construct their address. */
6482 hppa_encode_label (sym)
6485 const char *str = XSTR (sym, 0);
6486 int len = strlen (str) + 1;
6489 p = newstr = alloca (len + 1);
6498 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6502 pa_encode_section_info (decl, first)
6506 if (first && TEXT_SPACE_P (decl))
6509 if (TREE_CODE (decl) == FUNCTION_DECL
6510 || TREE_CODE (decl) == VAR_DECL)
6511 rtl = DECL_RTL (decl);
6513 rtl = TREE_CST_RTL (decl);
6514 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
6515 if (TREE_CODE (decl) == FUNCTION_DECL)
6516 hppa_encode_label (XEXP (DECL_RTL (decl), 0));
6520 /* This is sort of inverse to pa_encode_section_info. */
6523 pa_strip_name_encoding (str)
6526 return str + (*str == '*' || *str == '@');
6530 function_label_operand (op, mode)
6532 enum machine_mode mode ATTRIBUTE_UNUSED;
6534 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6537 /* Returns 1 if OP is a function label involved in a simple addition
6538 with a constant. Used to keep certain patterns from matching
6539 during instruction combination. */
6541 is_function_label_plus_const (op)
6544 /* Strip off any CONST. */
6545 if (GET_CODE (op) == CONST)
6548 return (GET_CODE (op) == PLUS
6549 && function_label_operand (XEXP (op, 0), Pmode)
6550 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6553 /* Output assembly code for a thunk to FUNCTION. */
6556 pa_asm_output_mi_thunk (file, thunk_fndecl, delta, function)
6559 HOST_WIDE_INT delta;
6562 const char *target_name = XSTR (XEXP (DECL_RTL (function), 0), 0);
6563 static unsigned int current_thunk_number;
6566 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
6567 lab = (*targetm.strip_name_encoding) (label);
6568 target_name = (*targetm.strip_name_encoding) (target_name);
6569 /* FIXME: total_code_bytes is not handled correctly in files with
6571 pa_output_function_prologue (file, 0);
6572 if (VAL_14_BITS_P (delta))
6574 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6576 fprintf (file, "\taddil LT%%%s,%%r19\n", lab);
6577 fprintf (file, "\tldw RT%%%s(%%r1),%%r22\n", lab);
6578 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6579 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6580 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6581 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6582 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6583 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6584 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
6585 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6586 fprintf (file, "(%%r26),%%r26\n");
6590 fprintf (file, "\tb %s\n\tldo ", target_name);
6591 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6592 fprintf (file, "(%%r26),%%r26\n");
6597 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6599 fprintf (file, "\taddil L%%");
6600 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6601 fprintf (file, ",%%r26\n\tldo R%%");
6602 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6603 fprintf (file, "(%%r1),%%r26\n");
6604 fprintf (file, "\taddil LT%%%s,%%r19\n", lab);
6605 fprintf (file, "\tldw RT%%%s(%%r1),%%r22\n", lab);
6606 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6607 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6608 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6609 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6610 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6611 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6612 fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n");
6616 fprintf (file, "\taddil L%%");
6617 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6618 fprintf (file, ",%%r26\n\tb %s\n\tldo R%%", target_name);
6619 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6620 fprintf (file, "(%%r1),%%r26\n");
6624 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
6625 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6628 fprintf (file, "\t.align 4\n");
6629 ASM_OUTPUT_INTERNAL_LABEL (file, "LTHN", current_thunk_number);
6630 fprintf (file, "\t.word P%%%s\n", target_name);
6631 function_section (thunk_fndecl);
6633 current_thunk_number++;
6636 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6637 use in fmpyadd instructions. */
6639 fmpyaddoperands (operands)
6642 enum machine_mode mode = GET_MODE (operands[0]);
6644 /* Must be a floating point mode. */
6645 if (mode != SFmode && mode != DFmode)
6648 /* All modes must be the same. */
6649 if (! (mode == GET_MODE (operands[1])
6650 && mode == GET_MODE (operands[2])
6651 && mode == GET_MODE (operands[3])
6652 && mode == GET_MODE (operands[4])
6653 && mode == GET_MODE (operands[5])))
6656 /* All operands must be registers. */
6657 if (! (GET_CODE (operands[1]) == REG
6658 && GET_CODE (operands[2]) == REG
6659 && GET_CODE (operands[3]) == REG
6660 && GET_CODE (operands[4]) == REG
6661 && GET_CODE (operands[5]) == REG))
6664 /* Only 2 real operands to the addition. One of the input operands must
6665 be the same as the output operand. */
6666 if (! rtx_equal_p (operands[3], operands[4])
6667 && ! rtx_equal_p (operands[3], operands[5]))
6670 /* Inout operand of add can not conflict with any operands from multiply. */
6671 if (rtx_equal_p (operands[3], operands[0])
6672 || rtx_equal_p (operands[3], operands[1])
6673 || rtx_equal_p (operands[3], operands[2]))
6676 /* multiply can not feed into addition operands. */
6677 if (rtx_equal_p (operands[4], operands[0])
6678 || rtx_equal_p (operands[5], operands[0]))
6681 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6683 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6684 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6685 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6686 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6687 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6688 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6691 /* Passed. Operands are suitable for fmpyadd. */
6695 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6696 use in fmpysub instructions. */
6698 fmpysuboperands (operands)
6701 enum machine_mode mode = GET_MODE (operands[0]);
6703 /* Must be a floating point mode. */
6704 if (mode != SFmode && mode != DFmode)
6707 /* All modes must be the same. */
6708 if (! (mode == GET_MODE (operands[1])
6709 && mode == GET_MODE (operands[2])
6710 && mode == GET_MODE (operands[3])
6711 && mode == GET_MODE (operands[4])
6712 && mode == GET_MODE (operands[5])))
6715 /* All operands must be registers. */
6716 if (! (GET_CODE (operands[1]) == REG
6717 && GET_CODE (operands[2]) == REG
6718 && GET_CODE (operands[3]) == REG
6719 && GET_CODE (operands[4]) == REG
6720 && GET_CODE (operands[5]) == REG))
6723 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6724 operation, so operands[4] must be the same as operand[3]. */
6725 if (! rtx_equal_p (operands[3], operands[4]))
6728 /* multiply can not feed into subtraction. */
6729 if (rtx_equal_p (operands[5], operands[0]))
6732 /* Inout operand of sub can not conflict with any operands from multiply. */
6733 if (rtx_equal_p (operands[3], operands[0])
6734 || rtx_equal_p (operands[3], operands[1])
6735 || rtx_equal_p (operands[3], operands[2]))
6738 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6740 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6741 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6742 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6743 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6744 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6745 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6748 /* Passed. Operands are suitable for fmpysub. */
6753 plus_xor_ior_operator (op, mode)
6755 enum machine_mode mode ATTRIBUTE_UNUSED;
6757 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6758 || GET_CODE (op) == IOR);
6761 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6762 constants for shadd instructions. */
6764 shadd_constant_p (val)
6767 if (val == 2 || val == 4 || val == 8)
6773 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6774 the valid constant for shadd instructions. */
6776 shadd_operand (op, mode)
6778 enum machine_mode mode ATTRIBUTE_UNUSED;
6780 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6783 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6786 basereg_operand (op, mode)
6788 enum machine_mode mode;
6790 /* cse will create some unscaled indexed addresses, however; it
6791 generally isn't a win on the PA, so avoid creating unscaled
6792 indexed addresses until after cse is finished. */
6793 if (!cse_not_expected)
6796 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6797 we don't have to worry about the braindamaged implicit space
6798 register selection from the basereg. */
6799 if (TARGET_NO_SPACE_REGS)
6800 return (GET_CODE (op) == REG);
6802 /* While it's always safe to index off the frame pointer, it's not
6803 always profitable, particularly when the frame pointer is being
6805 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6808 return (GET_CODE (op) == REG
6810 && register_operand (op, mode));
6813 /* Return 1 if this operand is anything other than a hard register. */
6816 non_hard_reg_operand (op, mode)
6818 enum machine_mode mode ATTRIBUTE_UNUSED;
6820 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6823 /* Return 1 if INSN branches forward. Should be using insn_addresses
6824 to avoid walking through all the insns... */
6826 forward_branch_p (insn)
6829 rtx label = JUMP_LABEL (insn);
6836 insn = NEXT_INSN (insn);
6839 return (insn == label);
6842 /* Return 1 if OP is an equality comparison, else return 0. */
6844 eq_neq_comparison_operator (op, mode)
6846 enum machine_mode mode ATTRIBUTE_UNUSED;
6848 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6851 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6853 movb_comparison_operator (op, mode)
6855 enum machine_mode mode ATTRIBUTE_UNUSED;
6857 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6858 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6861 /* Return 1 if INSN is in the delay slot of a call instruction. */
6863 jump_in_call_delay (insn)
6867 if (GET_CODE (insn) != JUMP_INSN)
6870 if (PREV_INSN (insn)
6871 && PREV_INSN (PREV_INSN (insn))
6872 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6874 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6876 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6877 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6884 /* Output an unconditional move and branch insn. */
6887 output_parallel_movb (operands, length)
6891 /* These are the cases in which we win. */
6893 return "mov%I1b,tr %1,%0,%2";
6895 /* None of these cases wins, but they don't lose either. */
6896 if (dbr_sequence_length () == 0)
6898 /* Nothing in the delay slot, fake it by putting the combined
6899 insn (the copy or add) in the delay slot of a bl. */
6900 if (GET_CODE (operands[1]) == CONST_INT)
6901 return "b %2\n\tldi %1,%0";
6903 return "b %2\n\tcopy %1,%0";
6907 /* Something in the delay slot, but we've got a long branch. */
6908 if (GET_CODE (operands[1]) == CONST_INT)
6909 return "ldi %1,%0\n\tb %2";
6911 return "copy %1,%0\n\tb %2";
6915 /* Output an unconditional add and branch insn. */
6918 output_parallel_addb (operands, length)
6922 /* To make life easy we want operand0 to be the shared input/output
6923 operand and operand1 to be the readonly operand. */
6924 if (operands[0] == operands[1])
6925 operands[1] = operands[2];
6927 /* These are the cases in which we win. */
6929 return "add%I1b,tr %1,%0,%3";
6931 /* None of these cases win, but they don't lose either. */
6932 if (dbr_sequence_length () == 0)
6934 /* Nothing in the delay slot, fake it by putting the combined
6935 insn (the copy or add) in the delay slot of a bl. */
6936 return "b %3\n\tadd%I1 %1,%0,%0";
6940 /* Something in the delay slot, but we've got a long branch. */
6941 return "add%I1 %1,%0,%0\n\tb %3";
6945 /* Return nonzero if INSN (a jump insn) immediately follows a call
6946 to a named function. This is used to avoid filling the delay slot
6947 of the jump since it can usually be eliminated by modifying RP in
6948 the delay slot of the call. */
6951 following_call (insn)
6954 if (! TARGET_JUMP_IN_DELAY)
6957 /* Find the previous real insn, skipping NOTEs. */
6958 insn = PREV_INSN (insn);
6959 while (insn && GET_CODE (insn) == NOTE)
6960 insn = PREV_INSN (insn);
6962 /* Check for CALL_INSNs and millicode calls. */
6964 && ((GET_CODE (insn) == CALL_INSN
6965 && get_attr_type (insn) != TYPE_DYNCALL)
6966 || (GET_CODE (insn) == INSN
6967 && GET_CODE (PATTERN (insn)) != SEQUENCE
6968 && GET_CODE (PATTERN (insn)) != USE
6969 && GET_CODE (PATTERN (insn)) != CLOBBER
6970 && get_attr_type (insn) == TYPE_MILLI)))
6976 /* We use this hook to perform a PA specific optimization which is difficult
6977 to do in earlier passes.
6979 We want the delay slots of branches within jump tables to be filled.
6980 None of the compiler passes at the moment even has the notion that a
6981 PA jump table doesn't contain addresses, but instead contains actual
6984 Because we actually jump into the table, the addresses of each entry
6985 must stay constant in relation to the beginning of the table (which
6986 itself must stay constant relative to the instruction to jump into
6987 it). I don't believe we can guarantee earlier passes of the compiler
6988 will adhere to those rules.
6990 So, late in the compilation process we find all the jump tables, and
6991 expand them into real code -- eg each entry in the jump table vector
6992 will get an appropriate label followed by a jump to the final target.
6994 Reorg and the final jump pass can then optimize these branches and
6995 fill their delay slots. We end up with smaller, more efficient code.
6997 The jump instructions within the table are special; we must be able
6998 to identify them during assembly output (if the jumps don't get filled
6999 we need to emit a nop rather than nullifying the delay slot)). We
7000 identify jumps in switch tables by marking the SET with DImode.
7002 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
7003 insns. This serves two purposes, first it prevents jump.c from
7004 noticing that the last N entries in the table jump to the instruction
7005 immediately after the table and deleting the jumps. Second, those
7006 insns mark where we should emit .begin_brtab and .end_brtab directives
7007 when using GAS (allows for better link time optimizations). */
7015 remove_useless_addtr_insns (insns, 1);
7017 if (pa_cpu < PROCESSOR_8000)
7018 pa_combine_instructions (get_insns ());
7021 /* This is fairly cheap, so always run it if optimizing. */
7022 if (optimize > 0 && !TARGET_BIG_SWITCH)
7024 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
7025 insns = get_insns ();
7026 for (insn = insns; insn; insn = NEXT_INSN (insn))
7028 rtx pattern, tmp, location;
7029 unsigned int length, i;
7031 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
7032 if (GET_CODE (insn) != JUMP_INSN
7033 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7034 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7037 /* Emit marker for the beginning of the branch table. */
7038 emit_insn_before (gen_begin_brtab (), insn);
7040 pattern = PATTERN (insn);
7041 location = PREV_INSN (insn);
7042 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
7044 for (i = 0; i < length; i++)
7046 /* Emit a label before each jump to keep jump.c from
7047 removing this code. */
7048 tmp = gen_label_rtx ();
7049 LABEL_NUSES (tmp) = 1;
7050 emit_label_after (tmp, location);
7051 location = NEXT_INSN (location);
7053 if (GET_CODE (pattern) == ADDR_VEC)
7055 /* Emit the jump itself. */
7056 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
7057 tmp = emit_jump_insn_after (tmp, location);
7058 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
7059 /* It is easy to rely on the branch table markers
7060 during assembly output to trigger the correct code
7061 for a switch table jump with an unfilled delay slot,
7063 However, that requires state and assumes that we look
7066 We can't make such assumptions when computing the length
7067 of instructions. Ugh. We could walk the insn chain to
7068 determine if this instruction is in a branch table, but
7069 that can get rather expensive, particularly during the
7070 branch shortening phase of the compiler.
7072 So instead we mark this jump as being special. This is
7073 far from ideal and knows that no code after this will
7074 muck around with the mode of the JUMP_INSN itself. */
7075 PUT_MODE (tmp, SImode);
7076 LABEL_NUSES (JUMP_LABEL (tmp))++;
7077 location = NEXT_INSN (location);
7081 /* Emit the jump itself. */
7082 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
7083 tmp = emit_jump_insn_after (tmp, location);
7084 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
7085 /* It is easy to rely on the branch table markers
7086 during assembly output to trigger the correct code
7087 for a switch table jump with an unfilled delay slot,
7089 However, that requires state and assumes that we look
7092 We can't make such assumptions when computing the length
7093 of instructions. Ugh. We could walk the insn chain to
7094 determine if this instruction is in a branch table, but
7095 that can get rather expensive, particularly during the
7096 branch shortening phase of the compiler.
7098 So instead we mark this jump as being special. This is
7099 far from ideal and knows that no code after this will
7100 muck around with the mode of the JUMP_INSN itself. */
7101 PUT_MODE (tmp, SImode);
7102 LABEL_NUSES (JUMP_LABEL (tmp))++;
7103 location = NEXT_INSN (location);
7106 /* Emit a BARRIER after the jump. */
7107 emit_barrier_after (location);
7108 location = NEXT_INSN (location);
7111 /* Emit marker for the end of the branch table. */
7112 emit_insn_before (gen_end_brtab (), location);
7113 location = NEXT_INSN (location);
7114 emit_barrier_after (location);
7116 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
7122 /* Sill need an end_brtab insn. */
7123 insns = get_insns ();
7124 for (insn = insns; insn; insn = NEXT_INSN (insn))
7126 /* Find an ADDR_VEC insn. */
7127 if (GET_CODE (insn) != JUMP_INSN
7128 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7129 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7132 /* Now generate markers for the beginning and end of the
7134 emit_insn_before (gen_begin_brtab (), insn);
7135 emit_insn_after (gen_end_brtab (), insn);
7140 /* The PA has a number of odd instructions which can perform multiple
7141 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
7142 it may be profitable to combine two instructions into one instruction
7143 with two outputs. It's not profitable PA2.0 machines because the
7144 two outputs would take two slots in the reorder buffers.
7146 This routine finds instructions which can be combined and combines
7147 them. We only support some of the potential combinations, and we
7148 only try common ways to find suitable instructions.
7150 * addb can add two registers or a register and a small integer
7151 and jump to a nearby (+-8k) location. Normally the jump to the
7152 nearby location is conditional on the result of the add, but by
7153 using the "true" condition we can make the jump unconditional.
7154 Thus addb can perform two independent operations in one insn.
7156 * movb is similar to addb in that it can perform a reg->reg
7157 or small immediate->reg copy and jump to a nearby (+-8k location).
7159 * fmpyadd and fmpysub can perform a FP multiply and either an
7160 FP add or FP sub if the operands of the multiply and add/sub are
7161 independent (there are other minor restrictions). Note both
7162 the fmpy and fadd/fsub can in theory move to better spots according
7163 to data dependencies, but for now we require the fmpy stay at a
7166 * Many of the memory operations can perform pre & post updates
7167 of index registers. GCC's pre/post increment/decrement addressing
7168 is far too simple to take advantage of all the possibilities. This
7169 pass may not be suitable since those insns may not be independent.
7171 * comclr can compare two ints or an int and a register, nullify
7172 the following instruction and zero some other register. This
7173 is more difficult to use as it's harder to find an insn which
7174 will generate a comclr than finding something like an unconditional
7175 branch. (conditional moves & long branches create comclr insns).
7177 * Most arithmetic operations can conditionally skip the next
7178 instruction. They can be viewed as "perform this operation
7179 and conditionally jump to this nearby location" (where nearby
7180 is an insns away). These are difficult to use due to the
7181 branch length restrictions. */
7184 pa_combine_instructions (insns)
7185 rtx insns ATTRIBUTE_UNUSED;
7189 /* This can get expensive since the basic algorithm is on the
7190 order of O(n^2) (or worse). Only do it for -O2 or higher
7191 levels of optimization. */
7195 /* Walk down the list of insns looking for "anchor" insns which
7196 may be combined with "floating" insns. As the name implies,
7197 "anchor" instructions don't move, while "floating" insns may
7199 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
7200 new = make_insn_raw (new);
7202 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
7204 enum attr_pa_combine_type anchor_attr;
7205 enum attr_pa_combine_type floater_attr;
7207 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
7208 Also ignore any special USE insns. */
7209 if ((GET_CODE (anchor) != INSN
7210 && GET_CODE (anchor) != JUMP_INSN
7211 && GET_CODE (anchor) != CALL_INSN)
7212 || GET_CODE (PATTERN (anchor)) == USE
7213 || GET_CODE (PATTERN (anchor)) == CLOBBER
7214 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
7215 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
7218 anchor_attr = get_attr_pa_combine_type (anchor);
7219 /* See if anchor is an insn suitable for combination. */
7220 if (anchor_attr == PA_COMBINE_TYPE_FMPY
7221 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
7222 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7223 && ! forward_branch_p (anchor)))
7227 for (floater = PREV_INSN (anchor);
7229 floater = PREV_INSN (floater))
7231 if (GET_CODE (floater) == NOTE
7232 || (GET_CODE (floater) == INSN
7233 && (GET_CODE (PATTERN (floater)) == USE
7234 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7237 /* Anything except a regular INSN will stop our search. */
7238 if (GET_CODE (floater) != INSN
7239 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7240 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7246 /* See if FLOATER is suitable for combination with the
7248 floater_attr = get_attr_pa_combine_type (floater);
7249 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7250 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7251 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7252 && floater_attr == PA_COMBINE_TYPE_FMPY))
7254 /* If ANCHOR and FLOATER can be combined, then we're
7255 done with this pass. */
7256 if (pa_can_combine_p (new, anchor, floater, 0,
7257 SET_DEST (PATTERN (floater)),
7258 XEXP (SET_SRC (PATTERN (floater)), 0),
7259 XEXP (SET_SRC (PATTERN (floater)), 1)))
7263 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7264 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
7266 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
7268 if (pa_can_combine_p (new, anchor, floater, 0,
7269 SET_DEST (PATTERN (floater)),
7270 XEXP (SET_SRC (PATTERN (floater)), 0),
7271 XEXP (SET_SRC (PATTERN (floater)), 1)))
7276 if (pa_can_combine_p (new, anchor, floater, 0,
7277 SET_DEST (PATTERN (floater)),
7278 SET_SRC (PATTERN (floater)),
7279 SET_SRC (PATTERN (floater))))
7285 /* If we didn't find anything on the backwards scan try forwards. */
7287 && (anchor_attr == PA_COMBINE_TYPE_FMPY
7288 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
7290 for (floater = anchor; floater; floater = NEXT_INSN (floater))
7292 if (GET_CODE (floater) == NOTE
7293 || (GET_CODE (floater) == INSN
7294 && (GET_CODE (PATTERN (floater)) == USE
7295 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7299 /* Anything except a regular INSN will stop our search. */
7300 if (GET_CODE (floater) != INSN
7301 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7302 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7308 /* See if FLOATER is suitable for combination with the
7310 floater_attr = get_attr_pa_combine_type (floater);
7311 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7312 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7313 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7314 && floater_attr == PA_COMBINE_TYPE_FMPY))
7316 /* If ANCHOR and FLOATER can be combined, then we're
7317 done with this pass. */
7318 if (pa_can_combine_p (new, anchor, floater, 1,
7319 SET_DEST (PATTERN (floater)),
7320 XEXP (SET_SRC (PATTERN (floater)),
7322 XEXP (SET_SRC (PATTERN (floater)),
7329 /* FLOATER will be nonzero if we found a suitable floating
7330 insn for combination with ANCHOR. */
7332 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7333 || anchor_attr == PA_COMBINE_TYPE_FMPY))
7335 /* Emit the new instruction and delete the old anchor. */
7336 emit_insn_before (gen_rtx_PARALLEL
7338 gen_rtvec (2, PATTERN (anchor),
7339 PATTERN (floater))),
7342 PUT_CODE (anchor, NOTE);
7343 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7344 NOTE_SOURCE_FILE (anchor) = 0;
7346 /* Emit a special USE insn for FLOATER, then delete
7347 the floating insn. */
7348 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7349 delete_insn (floater);
7354 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
7357 /* Emit the new_jump instruction and delete the old anchor. */
7359 = emit_jump_insn_before (gen_rtx_PARALLEL
7361 gen_rtvec (2, PATTERN (anchor),
7362 PATTERN (floater))),
7365 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
7366 PUT_CODE (anchor, NOTE);
7367 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7368 NOTE_SOURCE_FILE (anchor) = 0;
7370 /* Emit a special USE insn for FLOATER, then delete
7371 the floating insn. */
7372 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7373 delete_insn (floater);
7381 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
7382 rtx new, anchor, floater;
7384 rtx dest, src1, src2;
7386 int insn_code_number;
7389 /* Create a PARALLEL with the patterns of ANCHOR and
7390 FLOATER, try to recognize it, then test constraints
7391 for the resulting pattern.
7393 If the pattern doesn't match or the constraints
7394 aren't met keep searching for a suitable floater
7396 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
7397 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
7398 INSN_CODE (new) = -1;
7399 insn_code_number = recog_memoized (new);
7400 if (insn_code_number < 0
7401 || (extract_insn (new), ! constrain_operands (1)))
7415 /* There's up to three operands to consider. One
7416 output and two inputs.
7418 The output must not be used between FLOATER & ANCHOR
7419 exclusive. The inputs must not be set between
7420 FLOATER and ANCHOR exclusive. */
7422 if (reg_used_between_p (dest, start, end))
7425 if (reg_set_between_p (src1, start, end))
7428 if (reg_set_between_p (src2, start, end))
7431 /* If we get here, then everything is good. */
7435 /* Return nonzero if references for INSN are delayed.
7437 Millicode insns are actually function calls with some special
7438 constraints on arguments and register usage.
7440 Millicode calls always expect their arguments in the integer argument
7441 registers, and always return their result in %r29 (ret1). They
7442 are expected to clobber their arguments, %r1, %r29, and the return
7443 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
7445 This function tells reorg that the references to arguments and
7446 millicode calls do not appear to happen until after the millicode call.
7447 This allows reorg to put insns which set the argument registers into the
7448 delay slot of the millicode call -- thus they act more like traditional
7451 Note we can not consider side effects of the insn to be delayed because
7452 the branch and link insn will clobber the return pointer. If we happened
7453 to use the return pointer in the delay slot of the call, then we lose.
7455 get_attr_type will try to recognize the given insn, so make sure to
7456 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
7459 insn_refs_are_delayed (insn)
7462 return ((GET_CODE (insn) == INSN
7463 && GET_CODE (PATTERN (insn)) != SEQUENCE
7464 && GET_CODE (PATTERN (insn)) != USE
7465 && GET_CODE (PATTERN (insn)) != CLOBBER
7466 && get_attr_type (insn) == TYPE_MILLI));
7469 /* Return the location of a parameter that is passed in a register or NULL
7470 if the parameter has any component that is passed in memory.
7472 This is new code and will be pushed to into the net sources after
7475 ??? We might want to restructure this so that it looks more like other
7478 function_arg (cum, mode, type, named, incoming)
7479 CUMULATIVE_ARGS *cum;
7480 enum machine_mode mode;
7482 int named ATTRIBUTE_UNUSED;
7485 int max_arg_words = (TARGET_64BIT ? 8 : 4);
7492 if (mode == VOIDmode)
7495 arg_size = FUNCTION_ARG_SIZE (mode, type);
7497 /* If this arg would be passed partially or totally on the stack, then
7498 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
7499 handle arguments which are split between regs and stack slots if
7500 the ABI mandates split arguments. */
7503 /* The 32-bit ABI does not split arguments. */
7504 if (cum->words + arg_size > max_arg_words)
7510 alignment = cum->words & 1;
7511 if (cum->words + alignment >= max_arg_words)
7515 /* The 32bit ABIs and the 64bit ABIs are rather different,
7516 particularly in their handling of FP registers. We might
7517 be able to cleverly share code between them, but I'm not
7518 going to bother in the hope that splitting them up results
7519 in code that is more easily understood. */
7523 /* Advance the base registers to their current locations.
7525 Remember, gprs grow towards smaller register numbers while
7526 fprs grow to higher register numbers. Also remember that
7527 although FP regs are 32-bit addressable, we pretend that
7528 the registers are 64-bits wide. */
7529 gpr_reg_base = 26 - cum->words;
7530 fpr_reg_base = 32 + cum->words;
7532 /* Arguments wider than one word and small aggregates need special
7536 || (type && AGGREGATE_TYPE_P (type)))
7538 /* Double-extended precision (80-bit), quad-precision (128-bit)
7539 and aggregates including complex numbers are aligned on
7540 128-bit boundaries. The first eight 64-bit argument slots
7541 are associated one-to-one, with general registers r26
7542 through r19, and also with floating-point registers fr4
7543 through fr11. Arguments larger than one word are always
7544 passed in general registers.
7546 Using a PARALLEL with a word mode register results in left
7547 justified data on a big-endian target. */
7550 int i, offset = 0, ub = arg_size;
7552 /* Align the base register. */
7553 gpr_reg_base -= alignment;
7555 ub = MIN (ub, max_arg_words - cum->words - alignment);
7556 for (i = 0; i < ub; i++)
7558 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7559 gen_rtx_REG (DImode, gpr_reg_base),
7565 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7570 /* If the argument is larger than a word, then we know precisely
7571 which registers we must use. */
7585 /* Structures 5 to 8 bytes in size are passed in the general
7586 registers in the same manner as other non floating-point
7587 objects. The data is right-justified and zero-extended
7590 This is magic. Normally, using a PARALLEL results in left
7591 justified data on a big-endian target. However, using a
7592 single double-word register provides the required right
7593 justication for 5 to 8 byte structures. This has nothing
7594 to do with the direction of padding specified for the argument.
7595 It has to do with how the data is widened and shifted into
7596 and from the register.
7598 Aside from adding load_multiple and store_multiple patterns,
7599 this is the only way that I have found to obtain right
7600 justification of BLKmode data when it has a size greater
7601 than one word. Splitting the operation into two SImode loads
7602 or returning a DImode REG results in left justified data. */
7603 if (mode == BLKmode)
7607 loc[0] = gen_rtx_EXPR_LIST (VOIDmode,
7608 gen_rtx_REG (DImode, gpr_reg_base),
7610 return gen_rtx_PARALLEL (mode, gen_rtvec_v (1, loc));
7615 /* We have a single word (32 bits). A simple computation
7616 will get us the register #s we need. */
7617 gpr_reg_base = 26 - cum->words;
7618 fpr_reg_base = 32 + 2 * cum->words;
7622 /* Determine if the argument needs to be passed in both general and
7623 floating point registers. */
7624 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7625 /* If we are doing soft-float with portable runtime, then there
7626 is no need to worry about FP regs. */
7627 && ! TARGET_SOFT_FLOAT
7628 /* The parameter must be some kind of float, else we can just
7629 pass it in integer registers. */
7630 && FLOAT_MODE_P (mode)
7631 /* The target function must not have a prototype. */
7632 && cum->nargs_prototype <= 0
7633 /* libcalls do not need to pass items in both FP and general
7635 && type != NULL_TREE
7636 /* All this hair applies to outgoing args only. */
7638 /* Also pass outgoing floating arguments in both registers in indirect
7639 calls with the 32 bit ABI and the HP assembler since there is no
7640 way to the specify argument locations in static functions. */
7645 && FLOAT_MODE_P (mode)))
7651 gen_rtx_EXPR_LIST (VOIDmode,
7652 gen_rtx_REG (mode, fpr_reg_base),
7654 gen_rtx_EXPR_LIST (VOIDmode,
7655 gen_rtx_REG (mode, gpr_reg_base),
7660 /* See if we should pass this parameter in a general register. */
7661 if (TARGET_SOFT_FLOAT
7662 /* Indirect calls in the normal 32bit ABI require all arguments
7663 to be passed in general registers. */
7664 || (!TARGET_PORTABLE_RUNTIME
7668 /* If the parameter is not a floating point parameter, then
7669 it belongs in GPRs. */
7670 || !FLOAT_MODE_P (mode))
7671 retval = gen_rtx_REG (mode, gpr_reg_base);
7673 retval = gen_rtx_REG (mode, fpr_reg_base);
7679 /* If this arg would be passed totally in registers or totally on the stack,
7680 then this routine should return zero. It is currently called only for
7681 the 64-bit target. */
7683 function_arg_partial_nregs (cum, mode, type, named)
7684 CUMULATIVE_ARGS *cum;
7685 enum machine_mode mode;
7687 int named ATTRIBUTE_UNUSED;
7689 unsigned int max_arg_words = 8;
7690 unsigned int offset = 0;
7692 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7695 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
7696 /* Arg fits fully into registers. */
7698 else if (cum->words + offset >= max_arg_words)
7699 /* Arg fully on the stack. */
7703 return max_arg_words - cum->words - offset;
7707 /* Return 1 if this is a comparison operator. This allows the use of
7708 MATCH_OPERATOR to recognize all the branch insns. */
7711 cmpib_comparison_operator (op, mode)
7713 enum machine_mode mode;
7715 return ((mode == VOIDmode || GET_MODE (op) == mode)
7716 && (GET_CODE (op) == EQ
7717 || GET_CODE (op) == NE
7718 || GET_CODE (op) == GT
7719 || GET_CODE (op) == GTU
7720 || GET_CODE (op) == GE
7721 || GET_CODE (op) == LT
7722 || GET_CODE (op) == LE
7723 || GET_CODE (op) == LEU));
7726 /* On hpux10, the linker will give an error if we have a reference
7727 in the read-only data section to a symbol defined in a shared
7728 library. Therefore, expressions that might require a reloc can
7729 not be placed in the read-only data section. */
7732 pa_select_section (exp, reloc, align)
7735 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
7737 if (TREE_CODE (exp) == VAR_DECL
7738 && TREE_READONLY (exp)
7739 && !TREE_THIS_VOLATILE (exp)
7740 && DECL_INITIAL (exp)
7741 && (DECL_INITIAL (exp) == error_mark_node
7742 || TREE_CONSTANT (DECL_INITIAL (exp)))
7744 readonly_data_section ();
7745 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
7746 && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings)
7748 readonly_data_section ();
7754 pa_globalize_label (stream, name)
7758 /* We only handle DATA objects here, functions are globalized in
7759 ASM_DECLARE_FUNCTION_NAME. */
7760 if (! FUNCTION_NAME_P (name))
7762 fputs ("\t.EXPORT ", stream);
7763 assemble_name (stream, name);
7764 fputs (",DATA\n", stream);