1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
46 static void pa_init_machine_status PARAMS ((struct function *));
47 static void pa_mark_machine_status PARAMS ((struct function *));
48 static void pa_free_machine_status PARAMS ((struct function *));
49 static void pa_combine_instructions PARAMS ((rtx));
50 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
51 static int forward_branch_p PARAMS ((rtx));
52 static int shadd_constant_p PARAMS ((int));
53 static void pa_add_gc_roots PARAMS ((void));
54 static void mark_deferred_plabels PARAMS ((void *));
55 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
56 static int compute_movstrsi_length PARAMS ((rtx));
57 static void remove_useless_addtr_insns PARAMS ((rtx, int));
58 static void store_reg PARAMS ((int, int, int));
59 static void load_reg PARAMS ((int, int, int));
60 static void set_reg_plus_d PARAMS ((int, int, int));
62 /* Save the operands last given to a compare for use when we
63 generate a scc or bcc insn. */
65 rtx hppa_compare_op0, hppa_compare_op1;
66 enum cmp_type hppa_branch_type;
68 /* Which cpu we are scheduling for. */
69 enum processor_type pa_cpu;
71 /* String to hold which cpu we are scheduling for. */
72 const char *pa_cpu_string;
74 /* Which architecture we are generating code for. */
75 enum architecture_type pa_arch;
77 /* String to hold which architecture we are generating code for. */
78 const char *pa_arch_string;
80 /* Set by the FUNCTION_PROFILER macro. */
81 int hp_profile_labelno;
83 /* Counts for the number of callee-saved general and floating point
84 registers which were saved by the current function's prologue. */
85 static int gr_saved, fr_saved;
87 static rtx find_addr_reg PARAMS ((rtx));
89 /* Keep track of the number of bytes we have output in the CODE subspaces
90 during this compilation so we'll know when to emit inline long-calls. */
92 unsigned int total_code_bytes;
94 /* Variables to handle plabels that we discover are necessary at assembly
95 output time. They are output after the current function. */
97 struct deferred_plabel
101 } *deferred_plabels = 0;
102 int n_deferred_plabels = 0;
107 /* Default to 7100LC scheduling. */
108 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
110 pa_cpu_string = "7100";
111 pa_cpu = PROCESSOR_7100;
113 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
115 pa_cpu_string = "700";
116 pa_cpu = PROCESSOR_700;
118 else if (pa_cpu_string == NULL
119 || ! strcmp (pa_cpu_string, "7100LC"))
121 pa_cpu_string = "7100LC";
122 pa_cpu = PROCESSOR_7100LC;
124 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
126 pa_cpu_string = "7200";
127 pa_cpu = PROCESSOR_7200;
129 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "8000"))
131 pa_cpu_string = "8000";
132 pa_cpu = PROCESSOR_8000;
136 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string);
139 /* Set the instruction set architecture. */
140 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
142 pa_arch_string = "1.0";
143 pa_arch = ARCHITECTURE_10;
144 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
146 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
148 pa_arch_string = "1.1";
149 pa_arch = ARCHITECTURE_11;
150 target_flags &= ~MASK_PA_20;
151 target_flags |= MASK_PA_11;
153 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
155 pa_arch_string = "2.0";
156 pa_arch = ARCHITECTURE_20;
157 target_flags |= MASK_PA_11 | MASK_PA_20;
159 else if (pa_arch_string)
161 warning ("Unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
164 if (flag_pic && TARGET_PORTABLE_RUNTIME)
166 warning ("PIC code generation is not supported in the portable runtime model\n");
169 if (flag_pic && (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS))
171 warning ("PIC code generation is not compatible with fast indirect calls\n");
174 if (flag_pic && profile_flag)
176 warning ("PIC code generation is not compatible with profiling\n");
179 if (! TARGET_GAS && write_symbols != NO_DEBUG)
181 warning ("-g is only supported when using GAS on this processor,");
182 warning ("-g option disabled.");
183 write_symbols = NO_DEBUG;
186 /* We always generate PIC code when in 64bit mode. */
190 /* Register global variables with the garbage collector. */
193 /* Arrange to save and restore machine status around nested functions. */
194 init_machine_status = pa_init_machine_status;
195 mark_machine_status = pa_mark_machine_status;
196 free_machine_status = pa_free_machine_status;
199 /* Functions to initialize pic_offset_table_save_rtx.
200 These will be called, via pointer variables,
201 from push_function_context and pop_function_context. */
204 pa_init_machine_status (p)
207 p->machine = (machine_function *) xmalloc (sizeof (machine_function));
209 p->machine->pic_offset_table_save_rtx = NULL_RTX;
213 pa_mark_machine_status (p)
217 ggc_mark_rtx (p->machine->pic_offset_table_save_rtx);
221 pa_free_machine_status (p)
224 if (p->machine == NULL)
232 /* Return non-zero only if OP is a register of mode MODE,
235 reg_or_0_operand (op, mode)
237 enum machine_mode mode;
239 return (op == CONST0_RTX (mode) || register_operand (op, mode));
242 /* Return non-zero if OP is suitable for use in a call to a named
245 For 2.5 try to eliminate either call_operand_address or
246 function_label_operand, they perform very similar functions. */
248 call_operand_address (op, mode)
250 enum machine_mode mode ATTRIBUTE_UNUSED;
252 return (GET_MODE (op) == word_mode
253 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
256 /* Return 1 if X contains a symbolic expression. We know these
257 expressions will have one of a few well defined forms, so
258 we need only check those forms. */
260 symbolic_expression_p (x)
264 /* Strip off any HIGH. */
265 if (GET_CODE (x) == HIGH)
268 return (symbolic_operand (x, VOIDmode));
272 symbolic_operand (op, mode)
274 enum machine_mode mode ATTRIBUTE_UNUSED;
276 switch (GET_CODE (op))
283 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
284 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
285 && GET_CODE (XEXP (op, 1)) == CONST_INT);
291 /* Return truth value of statement that OP is a symbolic memory
292 operand of mode MODE. */
295 symbolic_memory_operand (op, mode)
297 enum machine_mode mode ATTRIBUTE_UNUSED;
299 if (GET_CODE (op) == SUBREG)
300 op = SUBREG_REG (op);
301 if (GET_CODE (op) != MEM)
304 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
305 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
308 /* Return 1 if the operand is either a register or a memory operand that is
312 reg_or_nonsymb_mem_operand (op, mode)
314 enum machine_mode mode;
316 if (register_operand (op, mode))
319 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
325 /* Return 1 if the operand is either a register, zero, or a memory operand
326 that is not symbolic. */
329 reg_or_0_or_nonsymb_mem_operand (op, mode)
331 enum machine_mode mode;
333 if (register_operand (op, mode))
336 if (op == CONST0_RTX (mode))
339 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
345 /* Accept any constant that can be moved in one instructions into a
348 cint_ok_for_move (intval)
349 HOST_WIDE_INT intval;
351 /* OK if ldo, ldil, or zdepi, can be used. */
352 return (CONST_OK_FOR_LETTER_P (intval, 'J')
353 || CONST_OK_FOR_LETTER_P (intval, 'N')
354 || CONST_OK_FOR_LETTER_P (intval, 'K'));
357 /* Accept anything that can be moved in one instruction into a general
360 move_operand (op, mode)
362 enum machine_mode mode;
364 if (register_operand (op, mode))
367 if (GET_CODE (op) == CONSTANT_P_RTX)
370 if (GET_CODE (op) == CONST_INT)
371 return cint_ok_for_move (INTVAL (op));
373 if (GET_CODE (op) == SUBREG)
374 op = SUBREG_REG (op);
375 if (GET_CODE (op) != MEM)
380 /* The LO_SUM part of a DLT reference is not considered a move_operand;
381 we must reject it here since it must be accepted by memory_address_p. */
382 if (GET_CODE (op) == LO_SUM
383 && GET_CODE (XEXP (op, 0)) == REG
384 && REG_OK_FOR_BASE_P (XEXP (op, 0))
385 && GET_CODE (XEXP (op, 1)) == UNSPEC)
388 /* Since move_operand is only used for source operands, we can always
389 allow scaled indexing! */
390 if (! TARGET_DISABLE_INDEXING
391 && GET_CODE (op) == PLUS
392 && ((GET_CODE (XEXP (op, 0)) == MULT
393 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
394 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
395 && INTVAL (XEXP (XEXP (op, 0), 1)) == GET_MODE_SIZE (mode)
396 && GET_CODE (XEXP (op, 1)) == REG)
397 || (GET_CODE (XEXP (op, 1)) == MULT
398 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
399 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
400 && INTVAL (XEXP (XEXP (op, 1), 1)) == GET_MODE_SIZE (mode)
401 && GET_CODE (XEXP (op, 0)) == REG)))
404 return memory_address_p (mode, op);
407 /* Accept REG and any CONST_INT that can be moved in one instruction into a
410 reg_or_cint_move_operand (op, mode)
412 enum machine_mode mode;
414 if (register_operand (op, mode))
417 if (GET_CODE (op) == CONST_INT)
418 return cint_ok_for_move (INTVAL (op));
424 pic_label_operand (op, mode)
426 enum machine_mode mode ATTRIBUTE_UNUSED;
431 switch (GET_CODE (op))
437 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
438 && GET_CODE (XEXP (op, 1)) == CONST_INT);
445 fp_reg_operand (op, mode)
447 enum machine_mode mode ATTRIBUTE_UNUSED;
449 return reg_renumber && FP_REG_P (op);
454 /* Return truth value of whether OP can be used as an operand in a
455 three operand arithmetic insn that accepts registers of mode MODE
456 or 14-bit signed integers. */
458 arith_operand (op, mode)
460 enum machine_mode mode;
462 return (register_operand (op, mode)
463 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
466 /* Return truth value of whether OP can be used as an operand in a
467 three operand arithmetic insn that accepts registers of mode MODE
468 or 11-bit signed integers. */
470 arith11_operand (op, mode)
472 enum machine_mode mode;
474 return (register_operand (op, mode)
475 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
478 /* A constant integer suitable for use in a PRE_MODIFY memory
481 pre_cint_operand (op, mode)
483 enum machine_mode mode ATTRIBUTE_UNUSED;
485 return (GET_CODE (op) == CONST_INT
486 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
489 /* A constant integer suitable for use in a POST_MODIFY memory
492 post_cint_operand (op, mode)
494 enum machine_mode mode ATTRIBUTE_UNUSED;
496 return (GET_CODE (op) == CONST_INT
497 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
501 arith_double_operand (op, mode)
503 enum machine_mode mode;
505 return (register_operand (op, mode)
506 || (GET_CODE (op) == CONST_DOUBLE
507 && GET_MODE (op) == mode
508 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
509 && ((CONST_DOUBLE_HIGH (op) >= 0)
510 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
513 /* Return truth value of whether OP is a integer which fits the
514 range constraining immediate operands in three-address insns, or
515 is an integer register. */
518 ireg_or_int5_operand (op, mode)
520 enum machine_mode mode ATTRIBUTE_UNUSED;
522 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
523 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
526 /* Return nonzero if OP is an integer register, else return zero. */
528 ireg_operand (op, mode)
530 enum machine_mode mode ATTRIBUTE_UNUSED;
532 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
535 /* Return truth value of whether OP is a integer which fits the
536 range constraining immediate operands in three-address insns. */
539 int5_operand (op, mode)
541 enum machine_mode mode ATTRIBUTE_UNUSED;
543 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
547 uint5_operand (op, mode)
549 enum machine_mode mode ATTRIBUTE_UNUSED;
551 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
555 int11_operand (op, mode)
557 enum machine_mode mode ATTRIBUTE_UNUSED;
559 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
563 uint32_operand (op, mode)
565 enum machine_mode mode ATTRIBUTE_UNUSED;
567 #if HOST_BITS_PER_WIDE_INT > 32
568 /* All allowed constants will fit a CONST_INT. */
569 return (GET_CODE (op) == CONST_INT
570 && (INTVAL (op) >= 0 && INTVAL (op) < 0x100000000L));
572 return (GET_CODE (op) == CONST_INT
573 || (GET_CODE (op) == CONST_DOUBLE
574 && CONST_DOUBLE_HIGH (op) == 0));
579 arith5_operand (op, mode)
581 enum machine_mode mode;
583 return register_operand (op, mode) || int5_operand (op, mode);
586 /* True iff zdepi can be used to generate this CONST_INT. */
589 unsigned HOST_WIDE_INT x;
591 unsigned HOST_WIDE_INT lsb_mask, t;
593 /* This might not be obvious, but it's at least fast.
594 This function is critical; we don't have the time loops would take. */
596 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
597 /* Return true iff t is a power of two. */
598 return ((t & (t - 1)) == 0);
601 /* True iff depi or extru can be used to compute (reg & mask).
602 Accept bit pattern like these:
608 unsigned HOST_WIDE_INT mask;
611 mask += mask & -mask;
612 return (mask & (mask - 1)) == 0;
615 /* True iff depi or extru can be used to compute (reg & OP). */
617 and_operand (op, mode)
619 enum machine_mode mode;
621 return (register_operand (op, mode)
622 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
625 /* True iff depi can be used to compute (reg | MASK). */
628 unsigned HOST_WIDE_INT mask;
630 mask += mask & -mask;
631 return (mask & (mask - 1)) == 0;
634 /* True iff depi can be used to compute (reg | OP). */
636 ior_operand (op, mode)
638 enum machine_mode mode ATTRIBUTE_UNUSED;
640 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
644 lhs_lshift_operand (op, mode)
646 enum machine_mode mode;
648 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
651 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
652 Such values can be the left hand side x in (x << r), using the zvdepi
655 lhs_lshift_cint_operand (op, mode)
657 enum machine_mode mode ATTRIBUTE_UNUSED;
659 unsigned HOST_WIDE_INT x;
660 if (GET_CODE (op) != CONST_INT)
662 x = INTVAL (op) >> 4;
663 return (x & (x + 1)) == 0;
667 arith32_operand (op, mode)
669 enum machine_mode mode;
671 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
675 pc_or_label_operand (op, mode)
677 enum machine_mode mode ATTRIBUTE_UNUSED;
679 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
682 /* Legitimize PIC addresses. If the address is already
683 position-independent, we return ORIG. Newly generated
684 position-independent addresses go to REG. If we need more
685 than one register, we lose. */
688 legitimize_pic_address (orig, mode, reg)
690 enum machine_mode mode;
694 /* Labels need special handling. */
695 if (pic_label_operand (orig, mode))
697 /* We do not want to go through the movXX expanders here since that
698 would create recursion.
700 Nor do we really want to call a generator for a named pattern
701 since that requires multiple patterns if we want to support
704 So instead we just emit the raw set, which avoids the movXX
705 expanders completely. */
706 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
707 current_function_uses_pic_offset_table = 1;
710 if (GET_CODE (orig) == SYMBOL_REF)
718 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
719 gen_rtx_HIGH (word_mode, orig)));
721 = gen_rtx_MEM (Pmode,
722 gen_rtx_LO_SUM (Pmode, reg,
723 gen_rtx_UNSPEC (Pmode,
728 pic_ref = gen_rtx_MEM (Pmode,
729 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
732 current_function_uses_pic_offset_table = 1;
733 RTX_UNCHANGING_P (pic_ref) = 1;
734 emit_move_insn (reg, pic_ref);
737 else if (GET_CODE (orig) == CONST)
741 if (GET_CODE (XEXP (orig, 0)) == PLUS
742 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
748 if (GET_CODE (XEXP (orig, 0)) == PLUS)
750 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
751 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
752 base == reg ? 0 : reg);
755 if (GET_CODE (orig) == CONST_INT)
757 if (INT_14_BITS (orig))
758 return plus_constant_for_output (base, INTVAL (orig));
759 orig = force_reg (Pmode, orig);
761 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
762 /* Likewise, should we set special REG_NOTEs here? */
767 /* Try machine-dependent ways of modifying an illegitimate address
768 to be legitimate. If we find one, return the new, valid address.
769 This macro is used in only one place: `memory_address' in explow.c.
771 OLDX is the address as it was before break_out_memory_refs was called.
772 In some cases it is useful to look at this to decide what needs to be done.
774 MODE and WIN are passed so that this macro can use
775 GO_IF_LEGITIMATE_ADDRESS.
777 It is always safe for this macro to do nothing. It exists to recognize
778 opportunities to optimize the output.
780 For the PA, transform:
782 memory(X + <large int>)
786 if (<large int> & mask) >= 16
787 Y = (<large int> & ~mask) + mask + 1 Round up.
789 Y = (<large int> & ~mask) Round down.
791 memory (Z + (<large int> - Y));
793 This is for CSE to find several similar references, and only use one Z.
795 X can either be a SYMBOL_REF or REG, but because combine can not
796 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
797 D will not fit in 14 bits.
799 MODE_FLOAT references allow displacements which fit in 5 bits, so use
802 MODE_INT references allow displacements which fit in 14 bits, so use
805 This relies on the fact that most mode MODE_FLOAT references will use FP
806 registers and most mode MODE_INT references will use integer registers.
807 (In the rare case of an FP register used in an integer MODE, we depend
808 on secondary reloads to clean things up.)
811 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
812 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
813 addressing modes to be used).
815 Put X and Z into registers. Then put the entire expression into
819 hppa_legitimize_address (x, oldx, mode)
820 rtx x, oldx ATTRIBUTE_UNUSED;
821 enum machine_mode mode;
826 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
828 /* Strip off CONST. */
829 if (GET_CODE (x) == CONST)
832 /* Special case. Get the SYMBOL_REF into a register and use indexing.
833 That should always be safe. */
834 if (GET_CODE (x) == PLUS
835 && GET_CODE (XEXP (x, 0)) == REG
836 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
838 rtx reg = force_reg (Pmode, XEXP (x, 1));
839 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
842 /* Note we must reject symbols which represent function addresses
843 since the assembler/linker can't handle arithmetic on plabels. */
844 if (GET_CODE (x) == PLUS
845 && GET_CODE (XEXP (x, 1)) == CONST_INT
846 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
847 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
848 || GET_CODE (XEXP (x, 0)) == REG))
850 rtx int_part, ptr_reg;
852 int offset = INTVAL (XEXP (x, 1));
855 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
856 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
858 /* Choose which way to round the offset. Round up if we
859 are >= halfway to the next boundary. */
860 if ((offset & mask) >= ((mask + 1) / 2))
861 newoffset = (offset & ~ mask) + mask + 1;
863 newoffset = (offset & ~ mask);
865 /* If the newoffset will not fit in 14 bits (ldo), then
866 handling this would take 4 or 5 instructions (2 to load
867 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
868 add the new offset and the SYMBOL_REF.) Combine can
869 not handle 4->2 or 5->2 combinations, so do not create
871 if (! VAL_14_BITS_P (newoffset)
872 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
874 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
877 gen_rtx_HIGH (Pmode, const_part));
880 gen_rtx_LO_SUM (Pmode,
881 tmp_reg, const_part));
885 if (! VAL_14_BITS_P (newoffset))
886 int_part = force_reg (Pmode, GEN_INT (newoffset));
888 int_part = GEN_INT (newoffset);
890 ptr_reg = force_reg (Pmode,
892 force_reg (Pmode, XEXP (x, 0)),
895 return plus_constant (ptr_reg, offset - newoffset);
898 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
900 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
901 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
902 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
903 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
904 || GET_CODE (XEXP (x, 1)) == SUBREG)
905 && GET_CODE (XEXP (x, 1)) != CONST)
907 int val = INTVAL (XEXP (XEXP (x, 0), 1));
911 if (GET_CODE (reg1) != REG)
912 reg1 = force_reg (Pmode, force_operand (reg1, 0));
914 reg2 = XEXP (XEXP (x, 0), 0);
915 if (GET_CODE (reg2) != REG)
916 reg2 = force_reg (Pmode, force_operand (reg2, 0));
918 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
925 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
927 Only do so for floating point modes since this is more speculative
928 and we lose if it's an integer store. */
929 if (GET_CODE (x) == PLUS
930 && GET_CODE (XEXP (x, 0)) == PLUS
931 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
932 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
933 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
934 && (mode == SFmode || mode == DFmode))
937 /* First, try and figure out what to use as a base register. */
938 rtx reg1, reg2, base, idx, orig_base;
940 reg1 = XEXP (XEXP (x, 0), 1);
945 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
946 then emit_move_sequence will turn on REG_POINTER so we'll know
947 it's a base register below. */
948 if (GET_CODE (reg1) != REG)
949 reg1 = force_reg (Pmode, force_operand (reg1, 0));
951 if (GET_CODE (reg2) != REG)
952 reg2 = force_reg (Pmode, force_operand (reg2, 0));
954 /* Figure out what the base and index are. */
956 if (GET_CODE (reg1) == REG
957 && REG_POINTER (reg1))
960 orig_base = XEXP (XEXP (x, 0), 1);
961 idx = gen_rtx_PLUS (Pmode,
963 XEXP (XEXP (XEXP (x, 0), 0), 0),
964 XEXP (XEXP (XEXP (x, 0), 0), 1)),
967 else if (GET_CODE (reg2) == REG
968 && REG_POINTER (reg2))
971 orig_base = XEXP (x, 1);
978 /* If the index adds a large constant, try to scale the
979 constant so that it can be loaded with only one insn. */
980 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
981 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
982 / INTVAL (XEXP (XEXP (idx, 0), 1)))
983 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
985 /* Divide the CONST_INT by the scale factor, then add it to A. */
986 int val = INTVAL (XEXP (idx, 1));
988 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
989 reg1 = XEXP (XEXP (idx, 0), 0);
990 if (GET_CODE (reg1) != REG)
991 reg1 = force_reg (Pmode, force_operand (reg1, 0));
993 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
995 /* We can now generate a simple scaled indexed address. */
998 (Pmode, gen_rtx_PLUS (Pmode,
999 gen_rtx_MULT (Pmode, reg1,
1000 XEXP (XEXP (idx, 0), 1)),
1004 /* If B + C is still a valid base register, then add them. */
1005 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1006 && INTVAL (XEXP (idx, 1)) <= 4096
1007 && INTVAL (XEXP (idx, 1)) >= -4096)
1009 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1012 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1014 reg2 = XEXP (XEXP (idx, 0), 0);
1015 if (GET_CODE (reg2) != CONST_INT)
1016 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1018 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1019 gen_rtx_MULT (Pmode,
1025 /* Get the index into a register, then add the base + index and
1026 return a register holding the result. */
1028 /* First get A into a register. */
1029 reg1 = XEXP (XEXP (idx, 0), 0);
1030 if (GET_CODE (reg1) != REG)
1031 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1033 /* And get B into a register. */
1034 reg2 = XEXP (idx, 1);
1035 if (GET_CODE (reg2) != REG)
1036 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1038 reg1 = force_reg (Pmode,
1039 gen_rtx_PLUS (Pmode,
1040 gen_rtx_MULT (Pmode, reg1,
1041 XEXP (XEXP (idx, 0), 1)),
1044 /* Add the result to our base register and return. */
1045 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1049 /* Uh-oh. We might have an address for x[n-100000]. This needs
1050 special handling to avoid creating an indexed memory address
1051 with x-100000 as the base.
1053 If the constant part is small enough, then it's still safe because
1054 there is a guard page at the beginning and end of the data segment.
1056 Scaled references are common enough that we want to try and rearrange the
1057 terms so that we can use indexing for these addresses too. Only
1058 do the optimization for floatint point modes. */
1060 if (GET_CODE (x) == PLUS
1061 && symbolic_expression_p (XEXP (x, 1)))
1063 /* Ugly. We modify things here so that the address offset specified
1064 by the index expression is computed first, then added to x to form
1065 the entire address. */
1067 rtx regx1, regx2, regy1, regy2, y;
1069 /* Strip off any CONST. */
1071 if (GET_CODE (y) == CONST)
1074 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1076 /* See if this looks like
1077 (plus (mult (reg) (shadd_const))
1078 (const (plus (symbol_ref) (const_int))))
1080 Where const_int is small. In that case the const
1081 expression is a valid pointer for indexing.
1083 If const_int is big, but can be divided evenly by shadd_const
1084 and added to (reg). This allows more scaled indexed addresses. */
1085 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1086 && GET_CODE (XEXP (x, 0)) == MULT
1087 && GET_CODE (XEXP (y, 1)) == CONST_INT
1088 && INTVAL (XEXP (y, 1)) >= -4096
1089 && INTVAL (XEXP (y, 1)) <= 4095
1090 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1091 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1093 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1097 if (GET_CODE (reg1) != REG)
1098 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1100 reg2 = XEXP (XEXP (x, 0), 0);
1101 if (GET_CODE (reg2) != REG)
1102 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1104 return force_reg (Pmode,
1105 gen_rtx_PLUS (Pmode,
1106 gen_rtx_MULT (Pmode,
1111 else if ((mode == DFmode || mode == SFmode)
1112 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1113 && GET_CODE (XEXP (x, 0)) == MULT
1114 && GET_CODE (XEXP (y, 1)) == CONST_INT
1115 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1116 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1117 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1120 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1121 / INTVAL (XEXP (XEXP (x, 0), 1))));
1122 regx2 = XEXP (XEXP (x, 0), 0);
1123 if (GET_CODE (regx2) != REG)
1124 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1125 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1129 gen_rtx_PLUS (Pmode,
1130 gen_rtx_MULT (Pmode, regx2,
1131 XEXP (XEXP (x, 0), 1)),
1132 force_reg (Pmode, XEXP (y, 0))));
1134 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1135 && INTVAL (XEXP (y, 1)) >= -4096
1136 && INTVAL (XEXP (y, 1)) <= 4095)
1138 /* This is safe because of the guard page at the
1139 beginning and end of the data space. Just
1140 return the original address. */
1145 /* Doesn't look like one we can optimize. */
1146 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1147 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1148 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1149 regx1 = force_reg (Pmode,
1150 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1152 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1160 /* For the HPPA, REG and REG+CONST is cost 0
1161 and addresses involving symbolic constants are cost 2.
1163 PIC addresses are very expensive.
1165 It is no coincidence that this has the same structure
1166 as GO_IF_LEGITIMATE_ADDRESS. */
1168 hppa_address_cost (X)
1171 if (GET_CODE (X) == PLUS)
1173 else if (GET_CODE (X) == LO_SUM)
1175 else if (GET_CODE (X) == HIGH)
1180 /* Emit insns to move operands[1] into operands[0].
1182 Return 1 if we have written out everything that needs to be done to
1183 do the move. Otherwise, return 0 and the caller will emit the move
1186 Note SCRATCH_REG may not be in the proper mode depending on how it
1187 will be used. This routine is resposible for creating a new copy
1188 of SCRATCH_REG in the proper mode. */
1191 emit_move_sequence (operands, mode, scratch_reg)
1193 enum machine_mode mode;
1196 register rtx operand0 = operands[0];
1197 register rtx operand1 = operands[1];
1201 && reload_in_progress && GET_CODE (operand0) == REG
1202 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1203 operand0 = reg_equiv_mem[REGNO (operand0)];
1204 else if (scratch_reg
1205 && reload_in_progress && GET_CODE (operand0) == SUBREG
1206 && GET_CODE (SUBREG_REG (operand0)) == REG
1207 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1209 /* We must not alter SUBREG_WORD (operand0) since that would confuse
1210 the code which tracks sets/uses for delete_output_reload. */
1211 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1212 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1213 SUBREG_WORD (operand0));
1214 operand0 = alter_subreg (temp);
1218 && reload_in_progress && GET_CODE (operand1) == REG
1219 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1220 operand1 = reg_equiv_mem[REGNO (operand1)];
1221 else if (scratch_reg
1222 && reload_in_progress && GET_CODE (operand1) == SUBREG
1223 && GET_CODE (SUBREG_REG (operand1)) == REG
1224 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1226 /* We must not alter SUBREG_WORD (operand0) since that would confuse
1227 the code which tracks sets/uses for delete_output_reload. */
1228 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1229 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1230 SUBREG_WORD (operand1));
1231 operand1 = alter_subreg (temp);
1234 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1235 && ((tem = find_replacement (&XEXP (operand0, 0)))
1236 != XEXP (operand0, 0)))
1237 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1238 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1239 && ((tem = find_replacement (&XEXP (operand1, 0)))
1240 != XEXP (operand1, 0)))
1241 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1243 /* Handle secondary reloads for loads/stores of FP registers from
1244 REG+D addresses where D does not fit in 5 bits, including
1245 (subreg (mem (addr))) cases. */
1246 if (fp_reg_operand (operand0, mode)
1247 && ((GET_CODE (operand1) == MEM
1248 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1249 || ((GET_CODE (operand1) == SUBREG
1250 && GET_CODE (XEXP (operand1, 0)) == MEM
1251 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1254 if (GET_CODE (operand1) == SUBREG)
1255 operand1 = XEXP (operand1, 0);
1257 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1258 it in WORD_MODE regardless of what mode it was originally given
1260 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1262 /* D might not fit in 14 bits either; for such cases load D into
1264 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1266 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1267 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1269 XEXP (XEXP (operand1, 0), 0),
1273 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1274 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1275 gen_rtx_MEM (mode, scratch_reg)));
1278 else if (fp_reg_operand (operand1, mode)
1279 && ((GET_CODE (operand0) == MEM
1280 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1281 || ((GET_CODE (operand0) == SUBREG)
1282 && GET_CODE (XEXP (operand0, 0)) == MEM
1283 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1286 if (GET_CODE (operand0) == SUBREG)
1287 operand0 = XEXP (operand0, 0);
1289 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1290 it in WORD_MODE regardless of what mode it was originally given
1292 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1294 /* D might not fit in 14 bits either; for such cases load D into
1296 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1298 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1299 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1302 XEXP (XEXP (operand0, 0),
1307 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1308 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1312 /* Handle secondary reloads for loads of FP registers from constant
1313 expressions by forcing the constant into memory.
1315 use scratch_reg to hold the address of the memory location.
1317 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1318 NO_REGS when presented with a const_int and an register class
1319 containing only FP registers. Doing so unfortunately creates
1320 more problems than it solves. Fix this for 2.5. */
1321 else if (fp_reg_operand (operand0, mode)
1322 && CONSTANT_P (operand1)
1327 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1328 it in WORD_MODE regardless of what mode it was originally given
1330 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1332 /* Force the constant into memory and put the address of the
1333 memory location into scratch_reg. */
1334 xoperands[0] = scratch_reg;
1335 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1336 emit_move_sequence (xoperands, Pmode, 0);
1338 /* Now load the destination register. */
1339 emit_insn (gen_rtx_SET (mode, operand0,
1340 gen_rtx_MEM (mode, scratch_reg)));
1343 /* Handle secondary reloads for SAR. These occur when trying to load
1344 the SAR from memory a FP register, or with a constant. */
1345 else if (GET_CODE (operand0) == REG
1346 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1347 && (GET_CODE (operand1) == MEM
1348 || GET_CODE (operand1) == CONST_INT
1349 || (GET_CODE (operand1) == REG
1350 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1353 /* D might not fit in 14 bits either; for such cases load D into
1355 if (GET_CODE (operand1) == MEM
1356 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1358 /* We are reloading the address into the scratch register, so we
1359 want to make sure the scratch register is a full register. */
1360 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1362 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1363 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1366 XEXP (XEXP (operand1, 0),
1370 /* Now we are going to load the scratch register from memory,
1371 we want to load it in the same width as the original MEM,
1372 which must be the same as the width of the ultimate destination,
1374 scratch_reg = gen_rtx_REG (GET_MODE (operand0), REGNO (scratch_reg));
1376 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1381 /* We want to load the scratch register using the same mode as
1382 the ultimate destination. */
1383 scratch_reg = gen_rtx_REG (GET_MODE (operand0), REGNO (scratch_reg));
1384 emit_move_insn (scratch_reg, operand1);
1387 /* And emit the insn to set the ultimate destination. We know that
1388 the scratch register has the same mode as the destination at this
1390 emit_move_insn (operand0, scratch_reg);
1393 /* Handle most common case: storing into a register. */
1394 else if (register_operand (operand0, mode))
1396 if (register_operand (operand1, mode)
1397 || (GET_CODE (operand1) == CONST_INT && INT_14_BITS (operand1))
1398 || (operand1 == CONST0_RTX (mode))
1399 || (GET_CODE (operand1) == HIGH
1400 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1401 /* Only `general_operands' can come here, so MEM is ok. */
1402 || GET_CODE (operand1) == MEM)
1404 /* Run this case quickly. */
1405 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1409 else if (GET_CODE (operand0) == MEM)
1411 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1412 && !(reload_in_progress || reload_completed))
1414 rtx temp = gen_reg_rtx (DFmode);
1416 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1417 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1420 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1422 /* Run this case quickly. */
1423 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1426 if (! (reload_in_progress || reload_completed))
1428 operands[0] = validize_mem (operand0);
1429 operands[1] = operand1 = force_reg (mode, operand1);
1433 /* Simplify the source if we need to.
1434 Note we do have to handle function labels here, even though we do
1435 not consider them legitimate constants. Loop optimizations can
1436 call the emit_move_xxx with one as a source. */
1437 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1438 || function_label_operand (operand1, mode)
1439 || (GET_CODE (operand1) == HIGH
1440 && symbolic_operand (XEXP (operand1, 0), mode)))
1444 if (GET_CODE (operand1) == HIGH)
1447 operand1 = XEXP (operand1, 0);
1449 if (symbolic_operand (operand1, mode))
1451 /* Argh. The assembler and linker can't handle arithmetic
1454 So we force the plabel into memory, load operand0 from
1455 the memory location, then add in the constant part. */
1456 if ((GET_CODE (operand1) == CONST
1457 && GET_CODE (XEXP (operand1, 0)) == PLUS
1458 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1459 || function_label_operand (operand1, mode))
1461 rtx temp, const_part;
1463 /* Figure out what (if any) scratch register to use. */
1464 if (reload_in_progress || reload_completed)
1466 scratch_reg = scratch_reg ? scratch_reg : operand0;
1467 /* SCRATCH_REG will hold an address and maybe the actual
1468 data. We want it in WORD_MODE regardless of what mode it
1469 was originally given to us. */
1470 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1473 scratch_reg = gen_reg_rtx (Pmode);
1475 if (GET_CODE (operand1) == CONST)
1477 /* Save away the constant part of the expression. */
1478 const_part = XEXP (XEXP (operand1, 0), 1);
1479 if (GET_CODE (const_part) != CONST_INT)
1482 /* Force the function label into memory. */
1483 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1487 /* No constant part. */
1488 const_part = NULL_RTX;
1490 /* Force the function label into memory. */
1491 temp = force_const_mem (mode, operand1);
1495 /* Get the address of the memory location. PIC-ify it if
1497 temp = XEXP (temp, 0);
1499 temp = legitimize_pic_address (temp, mode, scratch_reg);
1501 /* Put the address of the memory location into our destination
1504 emit_move_sequence (operands, mode, scratch_reg);
1506 /* Now load from the memory location into our destination
1508 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1509 emit_move_sequence (operands, mode, scratch_reg);
1511 /* And add back in the constant part. */
1512 if (const_part != NULL_RTX)
1513 expand_inc (operand0, const_part);
1522 if (reload_in_progress || reload_completed)
1524 temp = scratch_reg ? scratch_reg : operand0;
1525 /* TEMP will hold an address and maybe the actual
1526 data. We want it in WORD_MODE regardless of what mode it
1527 was originally given to us. */
1528 temp = gen_rtx_REG (word_mode, REGNO (temp));
1531 temp = gen_reg_rtx (Pmode);
1533 /* (const (plus (symbol) (const_int))) must be forced to
1534 memory during/after reload if the const_int will not fit
1536 if (GET_CODE (operand1) == CONST
1537 && GET_CODE (XEXP (operand1, 0)) == PLUS
1538 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1539 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1540 && (reload_completed || reload_in_progress)
1543 operands[1] = force_const_mem (mode, operand1);
1544 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1546 emit_move_sequence (operands, mode, temp);
1550 operands[1] = legitimize_pic_address (operand1, mode, temp);
1551 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1554 /* On the HPPA, references to data space are supposed to use dp,
1555 register 27, but showing it in the RTL inhibits various cse
1556 and loop optimizations. */
1561 if (reload_in_progress || reload_completed)
1563 temp = scratch_reg ? scratch_reg : operand0;
1564 /* TEMP will hold an address and maybe the actual
1565 data. We want it in WORD_MODE regardless of what mode it
1566 was originally given to us. */
1567 temp = gen_rtx_REG (word_mode, REGNO (temp));
1570 temp = gen_reg_rtx (mode);
1572 /* Loading a SYMBOL_REF into a register makes that register
1573 safe to be used as the base in an indexed address.
1575 Don't mark hard registers though. That loses. */
1576 if (GET_CODE (operand0) == REG
1577 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1578 REG_POINTER (operand0) = 1;
1579 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1580 REG_POINTER (temp) = 1;
1582 set = gen_rtx_SET (mode, operand0, temp);
1584 set = gen_rtx_SET (VOIDmode,
1586 gen_rtx_LO_SUM (mode, temp, operand1));
1588 emit_insn (gen_rtx_SET (VOIDmode,
1590 gen_rtx_HIGH (mode, operand1)));
1596 else if (GET_CODE (operand1) != CONST_INT
1597 || ! cint_ok_for_move (INTVAL (operand1)))
1600 int need_zero_extend = 0;
1602 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1603 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1605 HOST_WIDE_INT val = INTVAL (operand1);
1606 HOST_WIDE_INT nval = INTVAL (operand1);
1608 /* If the value is the same after a 32->64bit sign
1609 extension, then we can use it as-is. Else we will
1610 need to sign extend the constant from 32->64bits
1611 then zero extend the result from 32->64bits. */
1612 nval = ((val & 0xffffffff) ^ (~0x7fffffff)) + 0x80000000;
1615 need_zero_extend = 1;
1616 operand1 = GEN_INT (nval);
1620 if (reload_in_progress || reload_completed)
1623 temp = gen_reg_rtx (mode);
1625 emit_insn (gen_rtx_SET (VOIDmode, temp,
1626 gen_rtx_HIGH (mode, operand1)));
1627 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1628 emit_move_insn (operands[0], operands[1]);
1630 if (need_zero_extend)
1632 emit_insn (gen_zero_extendsidi2 (operands[0],
1633 gen_rtx_SUBREG (SImode,
1641 /* Now have insn-emit do whatever it normally does. */
1645 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1646 it will need a link/runtime reloc). */
1654 switch (TREE_CODE (exp))
1661 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1662 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1667 case NON_LVALUE_EXPR:
1668 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1674 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1675 if (TREE_VALUE (link) != 0)
1676 reloc |= reloc_needed (TREE_VALUE (link));
1689 /* Does operand (which is a symbolic_operand) live in text space? If
1690 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1693 read_only_operand (operand, mode)
1695 enum machine_mode mode ATTRIBUTE_UNUSED;
1697 if (GET_CODE (operand) == CONST)
1698 operand = XEXP (XEXP (operand, 0), 0);
1701 if (GET_CODE (operand) == SYMBOL_REF)
1702 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1706 if (GET_CODE (operand) == SYMBOL_REF)
1707 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1713 /* Return the best assembler insn template
1714 for moving operands[1] into operands[0] as a fullword. */
1716 singlemove_string (operands)
1719 HOST_WIDE_INT intval;
1721 if (GET_CODE (operands[0]) == MEM)
1722 return "stw %r1,%0";
1723 if (GET_CODE (operands[1]) == MEM)
1725 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1730 if (GET_MODE (operands[1]) != SFmode)
1733 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1735 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1736 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1738 operands[1] = GEN_INT (i);
1739 /* Fall through to CONST_INT case. */
1741 if (GET_CODE (operands[1]) == CONST_INT)
1743 intval = INTVAL (operands[1]);
1745 if (VAL_14_BITS_P (intval))
1747 else if ((intval & 0x7ff) == 0)
1748 return "ldil L'%1,%0";
1749 else if (zdepi_cint_p (intval))
1750 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1752 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1754 return "copy %1,%0";
1758 /* Compute position (in OP[1]) and width (in OP[2])
1759 useful for copying IMM to a register using the zdepi
1760 instructions. Store the immediate value to insert in OP[0]. */
1762 compute_zdepwi_operands (imm, op)
1763 unsigned HOST_WIDE_INT imm;
1768 /* Find the least significant set bit in IMM. */
1769 for (lsb = 0; lsb < 32; lsb++)
1776 /* Choose variants based on *sign* of the 5-bit field. */
1777 if ((imm & 0x10) == 0)
1778 len = (lsb <= 28) ? 4 : 32 - lsb;
1781 /* Find the width of the bitstring in IMM. */
1782 for (len = 5; len < 32; len++)
1784 if ((imm & (1 << len)) == 0)
1788 /* Sign extend IMM as a 5-bit value. */
1789 imm = (imm & 0xf) - 0x10;
1797 /* Compute position (in OP[1]) and width (in OP[2])
1798 useful for copying IMM to a register using the depdi,z
1799 instructions. Store the immediate value to insert in OP[0]. */
1801 compute_zdepdi_operands (imm, op)
1802 unsigned HOST_WIDE_INT imm;
1805 HOST_WIDE_INT lsb, len;
1807 /* Find the least significant set bit in IMM. */
1808 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1815 /* Choose variants based on *sign* of the 5-bit field. */
1816 if ((imm & 0x10) == 0)
1817 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1818 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1821 /* Find the width of the bitstring in IMM. */
1822 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1824 if ((imm & ((unsigned HOST_WIDE_INT)1 << len)) == 0)
1828 /* Sign extend IMM as a 5-bit value. */
1829 imm = (imm & 0xf) - 0x10;
1837 /* Output assembler code to perform a doubleword move insn
1838 with operands OPERANDS. */
1841 output_move_double (operands)
1844 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1846 rtx addreg0 = 0, addreg1 = 0;
1848 /* First classify both operands. */
1850 if (REG_P (operands[0]))
1852 else if (offsettable_memref_p (operands[0]))
1854 else if (GET_CODE (operands[0]) == MEM)
1859 if (REG_P (operands[1]))
1861 else if (CONSTANT_P (operands[1]))
1863 else if (offsettable_memref_p (operands[1]))
1865 else if (GET_CODE (operands[1]) == MEM)
1870 /* Check for the cases that the operand constraints are not
1871 supposed to allow to happen. Abort if we get one,
1872 because generating code for these cases is painful. */
1874 if (optype0 != REGOP && optype1 != REGOP)
1877 /* Handle auto decrementing and incrementing loads and stores
1878 specifically, since the structure of the function doesn't work
1879 for them without major modification. Do it better when we learn
1880 this port about the general inc/dec addressing of PA.
1881 (This was written by tege. Chide him if it doesn't work.) */
1883 if (optype0 == MEMOP)
1885 /* We have to output the address syntax ourselves, since print_operand
1886 doesn't deal with the addresses we want to use. Fix this later. */
1888 rtx addr = XEXP (operands[0], 0);
1889 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1891 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1893 operands[0] = XEXP (addr, 0);
1894 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1897 if (!reg_overlap_mentioned_p (high_reg, addr))
1899 /* No overlap between high target register and address
1900 register. (We do this in a non-obvious way to
1901 save a register file writeback) */
1902 if (GET_CODE (addr) == POST_INC)
1903 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
1904 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
1909 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1911 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1913 operands[0] = XEXP (addr, 0);
1914 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1917 if (!reg_overlap_mentioned_p (high_reg, addr))
1919 /* No overlap between high target register and address
1920 register. (We do this in a non-obvious way to
1921 save a register file writeback) */
1922 if (GET_CODE (addr) == PRE_INC)
1923 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
1924 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
1930 if (optype1 == MEMOP)
1932 /* We have to output the address syntax ourselves, since print_operand
1933 doesn't deal with the addresses we want to use. Fix this later. */
1935 rtx addr = XEXP (operands[1], 0);
1936 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1938 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1940 operands[1] = XEXP (addr, 0);
1941 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1944 if (!reg_overlap_mentioned_p (high_reg, addr))
1946 /* No overlap between high target register and address
1947 register. (We do this in a non-obvious way to
1948 save a register file writeback) */
1949 if (GET_CODE (addr) == POST_INC)
1950 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
1951 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0}";
1955 /* This is an undefined situation. We should load into the
1956 address register *and* update that register. Probably
1957 we don't need to handle this at all. */
1958 if (GET_CODE (addr) == POST_INC)
1959 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
1960 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
1963 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1965 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1967 operands[1] = XEXP (addr, 0);
1968 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1971 if (!reg_overlap_mentioned_p (high_reg, addr))
1973 /* No overlap between high target register and address
1974 register. (We do this in a non-obvious way to
1975 save a register file writeback) */
1976 if (GET_CODE (addr) == PRE_INC)
1977 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
1978 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
1982 /* This is an undefined situation. We should load into the
1983 address register *and* update that register. Probably
1984 we don't need to handle this at all. */
1985 if (GET_CODE (addr) == PRE_INC)
1986 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
1987 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
1990 else if (GET_CODE (addr) == PLUS
1991 && GET_CODE (XEXP (addr, 0)) == MULT)
1993 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1995 if (!reg_overlap_mentioned_p (high_reg, addr))
1999 xoperands[0] = high_reg;
2000 xoperands[1] = XEXP (addr, 1);
2001 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2002 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2003 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2005 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2011 xoperands[0] = high_reg;
2012 xoperands[1] = XEXP (addr, 1);
2013 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2014 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2015 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2017 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2023 /* If an operand is an unoffsettable memory ref, find a register
2024 we can increment temporarily to make it refer to the second word. */
2026 if (optype0 == MEMOP)
2027 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2029 if (optype1 == MEMOP)
2030 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2032 /* Ok, we can do one word at a time.
2033 Normally we do the low-numbered word first.
2035 In either case, set up in LATEHALF the operands to use
2036 for the high-numbered word and in some cases alter the
2037 operands in OPERANDS to be suitable for the low-numbered word. */
2039 if (optype0 == REGOP)
2040 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2041 else if (optype0 == OFFSOP)
2042 latehalf[0] = adj_offsettable_operand (operands[0], 4);
2044 latehalf[0] = operands[0];
2046 if (optype1 == REGOP)
2047 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2048 else if (optype1 == OFFSOP)
2049 latehalf[1] = adj_offsettable_operand (operands[1], 4);
2050 else if (optype1 == CNSTOP)
2051 split_double (operands[1], &operands[1], &latehalf[1]);
2053 latehalf[1] = operands[1];
2055 /* If the first move would clobber the source of the second one,
2056 do them in the other order.
2058 This can happen in two cases:
2060 mem -> register where the first half of the destination register
2061 is the same register used in the memory's address. Reload
2062 can create such insns.
2064 mem in this case will be either register indirect or register
2065 indirect plus a valid offset.
2067 register -> register move where REGNO(dst) == REGNO(src + 1)
2068 someone (Tim/Tege?) claimed this can happen for parameter loads.
2070 Handle mem -> register case first. */
2071 if (optype0 == REGOP
2072 && (optype1 == MEMOP || optype1 == OFFSOP)
2073 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2076 /* Do the late half first. */
2078 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2079 output_asm_insn (singlemove_string (latehalf), latehalf);
2083 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2084 return singlemove_string (operands);
2087 /* Now handle register -> register case. */
2088 if (optype0 == REGOP && optype1 == REGOP
2089 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2091 output_asm_insn (singlemove_string (latehalf), latehalf);
2092 return singlemove_string (operands);
2095 /* Normal case: do the two words, low-numbered first. */
2097 output_asm_insn (singlemove_string (operands), operands);
2099 /* Make any unoffsettable addresses point at high-numbered word. */
2101 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2103 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2106 output_asm_insn (singlemove_string (latehalf), latehalf);
2108 /* Undo the adds we just did. */
2110 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2112 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2118 output_fp_move_double (operands)
2121 if (FP_REG_P (operands[0]))
2123 if (FP_REG_P (operands[1])
2124 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2125 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2127 output_asm_insn ("fldd%F1 %1,%0", operands);
2129 else if (FP_REG_P (operands[1]))
2131 output_asm_insn ("fstd%F0 %1,%0", operands);
2133 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2135 if (GET_CODE (operands[0]) == REG)
2138 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2139 xoperands[0] = operands[0];
2140 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2142 /* This is a pain. You have to be prepared to deal with an
2143 arbitrary address here including pre/post increment/decrement.
2145 so avoid this in the MD. */
2153 /* Return a REG that occurs in ADDR with coefficient 1.
2154 ADDR can be effectively incremented by incrementing REG. */
2157 find_addr_reg (addr)
2160 while (GET_CODE (addr) == PLUS)
2162 if (GET_CODE (XEXP (addr, 0)) == REG)
2163 addr = XEXP (addr, 0);
2164 else if (GET_CODE (XEXP (addr, 1)) == REG)
2165 addr = XEXP (addr, 1);
2166 else if (CONSTANT_P (XEXP (addr, 0)))
2167 addr = XEXP (addr, 1);
2168 else if (CONSTANT_P (XEXP (addr, 1)))
2169 addr = XEXP (addr, 0);
2173 if (GET_CODE (addr) == REG)
2178 /* Emit code to perform a block move.
2180 OPERANDS[0] is the destination pointer as a REG, clobbered.
2181 OPERANDS[1] is the source pointer as a REG, clobbered.
2182 OPERANDS[2] is a register for temporary storage.
2183 OPERANDS[4] is the size as a CONST_INT
2184 OPERANDS[3] is a register for temporary storage.
2185 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2186 OPERANDS[6] is another temporary register. */
2189 output_block_move (operands, size_is_constant)
2191 int size_is_constant ATTRIBUTE_UNUSED;
2193 int align = INTVAL (operands[5]);
2194 unsigned long n_bytes = INTVAL (operands[4]);
2196 /* We can't move more than four bytes at a time because the PA
2197 has no longer integer move insns. (Could use fp mem ops?) */
2201 /* Note that we know each loop below will execute at least twice
2202 (else we would have open-coded the copy). */
2206 /* Pre-adjust the loop counter. */
2207 operands[4] = GEN_INT (n_bytes - 8);
2208 output_asm_insn ("ldi %4,%2", operands);
2211 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2212 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2213 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2214 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2215 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2217 /* Handle the residual. There could be up to 7 bytes of
2218 residual to copy! */
2219 if (n_bytes % 8 != 0)
2221 operands[4] = GEN_INT (n_bytes % 4);
2222 if (n_bytes % 8 >= 4)
2223 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2224 if (n_bytes % 4 != 0)
2225 output_asm_insn ("ldw 0(%1),%6", operands);
2226 if (n_bytes % 8 >= 4)
2227 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2228 if (n_bytes % 4 != 0)
2229 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2234 /* Pre-adjust the loop counter. */
2235 operands[4] = GEN_INT (n_bytes - 4);
2236 output_asm_insn ("ldi %4,%2", operands);
2239 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2240 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2241 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2242 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2243 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2245 /* Handle the residual. */
2246 if (n_bytes % 4 != 0)
2248 if (n_bytes % 4 >= 2)
2249 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2250 if (n_bytes % 2 != 0)
2251 output_asm_insn ("ldb 0(%1),%6", operands);
2252 if (n_bytes % 4 >= 2)
2253 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2254 if (n_bytes % 2 != 0)
2255 output_asm_insn ("stb %6,0(%0)", operands);
2260 /* Pre-adjust the loop counter. */
2261 operands[4] = GEN_INT (n_bytes - 2);
2262 output_asm_insn ("ldi %4,%2", operands);
2265 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2266 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2267 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2268 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2269 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2271 /* Handle the residual. */
2272 if (n_bytes % 2 != 0)
2274 output_asm_insn ("ldb 0(%1),%3", operands);
2275 output_asm_insn ("stb %3,0(%0)", operands);
2284 /* Count the number of insns necessary to handle this block move.
2286 Basic structure is the same as emit_block_move, except that we
2287 count insns rather than emit them. */
2290 compute_movstrsi_length (insn)
2293 rtx pat = PATTERN (insn);
2294 int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2295 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
2296 unsigned int n_insns = 0;
2298 /* We can't move more than four bytes at a time because the PA
2299 has no longer integer move insns. (Could use fp mem ops?) */
2303 /* The basic copying loop. */
2307 if (n_bytes % (2 * align) != 0)
2309 if ((n_bytes % (2 * align)) >= align)
2312 if ((n_bytes % align) != 0)
2316 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2322 output_and (operands)
2325 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2327 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2328 int ls0, ls1, ms0, p, len;
2330 for (ls0 = 0; ls0 < 32; ls0++)
2331 if ((mask & (1 << ls0)) == 0)
2334 for (ls1 = ls0; ls1 < 32; ls1++)
2335 if ((mask & (1 << ls1)) != 0)
2338 for (ms0 = ls1; ms0 < 32; ms0++)
2339 if ((mask & (1 << ms0)) == 0)
2352 operands[2] = GEN_INT (len);
2353 return "{extru|extrw,u} %1,31,%2,%0";
2357 /* We could use this `depi' for the case above as well, but `depi'
2358 requires one more register file access than an `extru'. */
2363 operands[2] = GEN_INT (p);
2364 operands[3] = GEN_INT (len);
2365 return "{depi|depwi} 0,%2,%3,%0";
2369 return "and %1,%2,%0";
2372 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2373 storing the result in operands[0]. */
2375 output_64bit_and (operands)
2378 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2380 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2381 unsigned HOST_WIDE_INT ls0, ls1, ms0, p, len;
2383 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2384 if ((mask & ((unsigned HOST_WIDE_INT)1 << ls0)) == 0)
2387 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2388 if ((mask & ((unsigned HOST_WIDE_INT)1 << ls1)) != 0)
2391 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2392 if ((mask & ((unsigned HOST_WIDE_INT)1 << ms0)) == 0)
2395 if (ms0 != HOST_BITS_PER_WIDE_INT)
2398 if (ls1 == HOST_BITS_PER_WIDE_INT)
2405 operands[2] = GEN_INT (len);
2406 return "extrd,u %1,63,%2,%0";
2410 /* We could use this `depi' for the case above as well, but `depi'
2411 requires one more register file access than an `extru'. */
2416 operands[2] = GEN_INT (p);
2417 operands[3] = GEN_INT (len);
2418 return "depdi 0,%2,%3,%0";
2422 return "and %1,%2,%0";
2426 output_ior (operands)
2429 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2430 int bs0, bs1, p, len;
2432 if (INTVAL (operands[2]) == 0)
2433 return "copy %1,%0";
2435 for (bs0 = 0; bs0 < 32; bs0++)
2436 if ((mask & (1 << bs0)) != 0)
2439 for (bs1 = bs0; bs1 < 32; bs1++)
2440 if ((mask & (1 << bs1)) == 0)
2443 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2449 operands[2] = GEN_INT (p);
2450 operands[3] = GEN_INT (len);
2451 return "{depi|depwi} -1,%2,%3,%0";
2454 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2455 storing the result in operands[0]. */
2457 output_64bit_ior (operands)
2460 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2461 unsigned HOST_WIDE_INT bs0, bs1, p, len;
2463 if (INTVAL (operands[2]) == 0)
2464 return "copy %1,%0";
2466 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2467 if ((mask & ((unsigned HOST_WIDE_INT)1 << bs0)) != 0)
2470 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2471 if ((mask & ((unsigned HOST_WIDE_INT)1 << bs1)) == 0)
2474 if (bs1 != HOST_BITS_PER_WIDE_INT
2475 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2481 operands[2] = GEN_INT (p);
2482 operands[3] = GEN_INT (len);
2483 return "depdi -1,%2,%3,%0";
2486 /* Output an ascii string. */
2488 output_ascii (file, p, size)
2490 const unsigned char *p;
2495 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2497 /* The HP assembler can only take strings of 256 characters at one
2498 time. This is a limitation on input line length, *not* the
2499 length of the string. Sigh. Even worse, it seems that the
2500 restriction is in number of input characters (see \xnn &
2501 \whatever). So we have to do this very carefully. */
2503 fputs ("\t.STRING \"", file);
2506 for (i = 0; i < size; i += 4)
2510 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2512 register unsigned int c = p[i + io];
2514 if (c == '\"' || c == '\\')
2515 partial_output[co++] = '\\';
2516 if (c >= ' ' && c < 0177)
2517 partial_output[co++] = c;
2521 partial_output[co++] = '\\';
2522 partial_output[co++] = 'x';
2523 hexd = c / 16 - 0 + '0';
2525 hexd -= '9' - 'a' + 1;
2526 partial_output[co++] = hexd;
2527 hexd = c % 16 - 0 + '0';
2529 hexd -= '9' - 'a' + 1;
2530 partial_output[co++] = hexd;
2533 if (chars_output + co > 243)
2535 fputs ("\"\n\t.STRING \"", file);
2538 fwrite (partial_output, 1, co, file);
2542 fputs ("\"\n", file);
2545 /* Try to rewrite floating point comparisons & branches to avoid
2546 useless add,tr insns.
2548 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2549 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2550 first attempt to remove useless add,tr insns. It is zero
2551 for the second pass as reorg sometimes leaves bogus REG_DEAD
2554 When CHECK_NOTES is zero we can only eliminate add,tr insns
2555 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2558 remove_useless_addtr_insns (insns, check_notes)
2563 static int pass = 0;
2565 /* This is fairly cheap, so always run it when optimizing. */
2569 int fbranch_count = 0;
2571 /* Walk all the insns in this function looking for fcmp & fbranch
2572 instructions. Keep track of how many of each we find. */
2573 insns = get_insns ();
2574 for (insn = insns; insn; insn = next_insn (insn))
2578 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2579 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2582 tmp = PATTERN (insn);
2584 /* It must be a set. */
2585 if (GET_CODE (tmp) != SET)
2588 /* If the destination is CCFP, then we've found an fcmp insn. */
2589 tmp = SET_DEST (tmp);
2590 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2596 tmp = PATTERN (insn);
2597 /* If this is an fbranch instruction, bump the fbranch counter. */
2598 if (GET_CODE (tmp) == SET
2599 && SET_DEST (tmp) == pc_rtx
2600 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2601 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2602 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2603 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2611 /* Find all floating point compare + branch insns. If possible,
2612 reverse the comparison & the branch to avoid add,tr insns. */
2613 for (insn = insns; insn; insn = next_insn (insn))
2617 /* Ignore anything that isn't an INSN. */
2618 if (GET_CODE (insn) != INSN)
2621 tmp = PATTERN (insn);
2623 /* It must be a set. */
2624 if (GET_CODE (tmp) != SET)
2627 /* The destination must be CCFP, which is register zero. */
2628 tmp = SET_DEST (tmp);
2629 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2632 /* INSN should be a set of CCFP.
2634 See if the result of this insn is used in a reversed FP
2635 conditional branch. If so, reverse our condition and
2636 the branch. Doing so avoids useless add,tr insns. */
2637 next = next_insn (insn);
2640 /* Jumps, calls and labels stop our search. */
2641 if (GET_CODE (next) == JUMP_INSN
2642 || GET_CODE (next) == CALL_INSN
2643 || GET_CODE (next) == CODE_LABEL)
2646 /* As does another fcmp insn. */
2647 if (GET_CODE (next) == INSN
2648 && GET_CODE (PATTERN (next)) == SET
2649 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2650 && REGNO (SET_DEST (PATTERN (next))) == 0)
2653 next = next_insn (next);
2656 /* Is NEXT_INSN a branch? */
2658 && GET_CODE (next) == JUMP_INSN)
2660 rtx pattern = PATTERN (next);
2662 /* If it a reversed fp conditional branch (eg uses add,tr)
2663 and CCFP dies, then reverse our conditional and the branch
2664 to avoid the add,tr. */
2665 if (GET_CODE (pattern) == SET
2666 && SET_DEST (pattern) == pc_rtx
2667 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2668 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2669 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2670 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2671 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2672 && (fcmp_count == fbranch_count
2674 && find_regno_note (next, REG_DEAD, 0))))
2676 /* Reverse the branch. */
2677 tmp = XEXP (SET_SRC (pattern), 1);
2678 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2679 XEXP (SET_SRC (pattern), 2) = tmp;
2680 INSN_CODE (next) = -1;
2682 /* Reverse our condition. */
2683 tmp = PATTERN (insn);
2684 PUT_CODE (XEXP (tmp, 1),
2685 reverse_condition_maybe_unordered (GET_CODE (XEXP (tmp,
2696 /* You may have trouble believing this, but this is the 32 bit HP-PA stack
2701 Variable arguments (optional; any number may be allocated)
2703 SP-(4*(N+9)) arg word N
2708 Fixed arguments (must be allocated; may remain unused)
2717 SP-32 External Data Pointer (DP)
2719 SP-24 External/stub RP (RP')
2723 SP-8 Calling Stub RP (RP'')
2728 SP-0 Stack Pointer (points to next available address)
2732 /* This function saves registers as follows. Registers marked with ' are
2733 this function's registers (as opposed to the previous function's).
2734 If a frame_pointer isn't needed, r4 is saved as a general register;
2735 the space for the frame pointer is still allocated, though, to keep
2741 SP (FP') Previous FP
2742 SP + 4 Alignment filler (sigh)
2743 SP + 8 Space for locals reserved here.
2747 SP + n All call saved register used.
2751 SP + o All call saved fp registers used.
2755 SP + p (SP') points to next available address.
2759 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2760 Handle case where DISP > 8k by using the add_high_const patterns.
2762 Note in DISP > 8k case, we will leave the high part of the address
2763 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2766 store_reg (reg, disp, base)
2767 int reg, disp, base;
2769 if (VAL_14_BITS_P (disp))
2770 emit_move_insn (gen_rtx_MEM (word_mode,
2771 plus_constant (gen_rtx_REG (Pmode, base),
2773 gen_rtx_REG (word_mode, reg));
2776 emit_move_insn (gen_rtx_REG (Pmode, 1),
2777 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, base),
2778 gen_rtx_HIGH (Pmode, GEN_INT (disp))));
2779 emit_move_insn (gen_rtx_MEM (word_mode,
2780 gen_rtx_LO_SUM (Pmode,
2781 gen_rtx_REG (Pmode, 1),
2783 gen_rtx_REG (word_mode, reg));
2787 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
2788 Handle case where DISP > 8k by using the add_high_const patterns.
2790 Note in DISP > 8k case, we will leave the high part of the address
2791 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2794 load_reg (reg, disp, base)
2795 int reg, disp, base;
2797 if (VAL_14_BITS_P (disp))
2798 emit_move_insn (gen_rtx_REG (word_mode, reg),
2799 gen_rtx_MEM (word_mode,
2800 plus_constant (gen_rtx_REG (Pmode, base),
2804 emit_move_insn (gen_rtx_REG (Pmode, 1),
2805 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, base),
2806 gen_rtx_HIGH (Pmode, GEN_INT (disp))));
2807 emit_move_insn (gen_rtx_REG (word_mode, reg),
2808 gen_rtx_MEM (word_mode,
2809 gen_rtx_LO_SUM (Pmode,
2810 gen_rtx_REG (Pmode, 1),
2815 /* Emit RTL to set REG to the value specified by BASE+DISP.
2816 Handle case where DISP > 8k by using the add_high_const patterns.
2818 Note in DISP > 8k case, we will leave the high part of the address
2819 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2822 set_reg_plus_d (reg, base, disp)
2823 int reg, base, disp;
2825 if (VAL_14_BITS_P (disp))
2826 emit_move_insn (gen_rtx_REG (Pmode, reg),
2827 plus_constant (gen_rtx_REG (Pmode, base), disp));
2830 emit_move_insn (gen_rtx_REG (Pmode, 1),
2831 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, base),
2832 gen_rtx_HIGH (Pmode, GEN_INT (disp))));
2833 emit_move_insn (gen_rtx_REG (Pmode, reg),
2834 gen_rtx_LO_SUM (Pmode,
2835 gen_rtx_REG (Pmode, 1),
2840 /* Global variables set by FUNCTION_PROLOGUE. */
2841 /* Size of frame. Need to know this to emit return insns from
2843 static int actual_fsize;
2844 static int local_fsize, save_fregs;
2847 compute_frame_size (size, fregs_live)
2853 /* Space for frame pointer + filler. If any frame is allocated
2854 we need to add this in because of STARTING_FRAME_OFFSET.
2856 Similar code also appears in hppa_expand_prologue. Change both
2857 of them at the same time. */
2858 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
2860 /* Account for space used by the callee general register saves. */
2861 for (i = 18; i >= 3; i--)
2862 if (regs_ever_live[i])
2863 fsize += UNITS_PER_WORD;
2865 /* Round the stack. */
2866 fsize = (fsize + 7) & ~7;
2868 /* Account for space used by the callee floating point register saves. */
2869 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
2870 if (regs_ever_live[i]
2871 || (! TARGET_64BIT && regs_ever_live[i + 1]))
2876 /* We always save both halves of the FP register, so always
2877 increment the frame size by 8 bytes. */
2881 /* The various ABIs include space for the outgoing parameters in the
2882 size of the current function's stack frame. */
2883 fsize += current_function_outgoing_args_size;
2885 /* Allocate space for the fixed frame marker. This space must be
2886 allocated for any function that makes calls or otherwise allocates
2888 if (!current_function_is_leaf || fsize)
2891 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
2894 rtx hp_profile_label_rtx;
2895 static char hp_profile_label_name[8];
2897 output_function_prologue (file, size)
2899 int size ATTRIBUTE_UNUSED;
2901 /* The function's label and associated .PROC must never be
2902 separated and must be output *after* any profiling declarations
2903 to avoid changing spaces/subspaces within a procedure. */
2904 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
2905 fputs ("\t.PROC\n", file);
2907 /* hppa_expand_prologue does the dirty work now. We just need
2908 to output the assembler directives which denote the start
2910 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
2911 if (regs_ever_live[2] || profile_flag)
2912 fputs (",CALLS,SAVE_RP", file);
2914 fputs (",NO_CALLS", file);
2916 if (frame_pointer_needed)
2917 fputs (",SAVE_SP", file);
2919 /* Pass on information about the number of callee register saves
2920 performed in the prologue.
2922 The compiler is supposed to pass the highest register number
2923 saved, the assembler then has to adjust that number before
2924 entering it into the unwind descriptor (to account for any
2925 caller saved registers with lower register numbers than the
2926 first callee saved register). */
2928 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
2931 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
2933 fputs ("\n\t.ENTRY\n", file);
2935 /* Horrid hack. emit_function_prologue will modify this RTL in
2936 place to get the expected results. */
2938 ASM_GENERATE_INTERNAL_LABEL (hp_profile_label_name, "LP",
2939 hp_profile_labelno);
2941 /* If we're using GAS and not using the portable runtime model, then
2942 we don't need to accumulate the total number of code bytes. */
2943 if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
2944 total_code_bytes = 0;
2945 else if (INSN_ADDRESSES_SET_P ())
2947 unsigned int old_total = total_code_bytes;
2949 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_insn()));
2950 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
2952 /* Be prepared to handle overflows. */
2953 total_code_bytes = old_total > total_code_bytes ? -1 : total_code_bytes;
2956 total_code_bytes = -1;
2958 remove_useless_addtr_insns (get_insns (), 0);
2962 hppa_expand_prologue()
2964 extern char call_used_regs[];
2965 int size = get_frame_size ();
2966 int merge_sp_adjust_with_store = 0;
2968 rtx tmpreg, size_rtx;
2974 /* Allocate space for frame pointer + filler. If any frame is allocated
2975 we need to add this in because of STARTING_FRAME_OFFSET.
2977 Similar code also appears in compute_frame_size. Change both
2978 of them at the same time. */
2979 local_fsize = size + (size || frame_pointer_needed
2980 ? STARTING_FRAME_OFFSET : 0);
2982 actual_fsize = compute_frame_size (size, &save_fregs);
2984 /* Compute a few things we will use often. */
2985 tmpreg = gen_rtx_REG (word_mode, 1);
2986 size_rtx = GEN_INT (actual_fsize);
2988 /* Save RP first. The calling conventions manual states RP will
2989 always be stored into the caller's frame at sp-20 or sp - 16
2990 depending on which ABI is in use. */
2991 if ((regs_ever_live[2] || profile_flag) && TARGET_64BIT)
2992 store_reg (2, -16, STACK_POINTER_REGNUM);
2994 if ((regs_ever_live[2] || profile_flag) && ! TARGET_64BIT)
2995 store_reg (2, -20, STACK_POINTER_REGNUM);
2997 /* Allocate the local frame and set up the frame pointer if needed. */
3000 if (frame_pointer_needed)
3002 /* Copy the old frame pointer temporarily into %r1. Set up the
3003 new stack pointer, then store away the saved old frame pointer
3004 into the stack at sp+actual_fsize and at the same time update
3005 the stack pointer by actual_fsize bytes. Two versions, first
3006 handles small (<8k) frames. The second handles large (>8k)
3008 emit_move_insn (tmpreg, frame_pointer_rtx);
3009 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3010 if (VAL_14_BITS_P (actual_fsize))
3011 emit_insn (gen_post_store (stack_pointer_rtx, tmpreg, size_rtx));
3014 /* It is incorrect to store the saved frame pointer at *sp,
3015 then increment sp (writes beyond the current stack boundary).
3017 So instead use stwm to store at *sp and post-increment the
3018 stack pointer as an atomic operation. Then increment sp to
3019 finish allocating the new frame. */
3020 emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
3022 set_reg_plus_d (STACK_POINTER_REGNUM,
3023 STACK_POINTER_REGNUM,
3027 /* no frame pointer needed. */
3030 /* In some cases we can perform the first callee register save
3031 and allocating the stack frame at the same time. If so, just
3032 make a note of it and defer allocating the frame until saving
3033 the callee registers. */
3034 if (VAL_14_BITS_P (-actual_fsize)
3038 merge_sp_adjust_with_store = 1;
3039 /* Can not optimize. Adjust the stack frame by actual_fsize bytes. */
3040 else if (actual_fsize != 0)
3041 set_reg_plus_d (STACK_POINTER_REGNUM,
3042 STACK_POINTER_REGNUM,
3047 /* The hppa calling conventions say that %r19, the pic offset
3048 register, is saved at sp - 32 (in this function's frame) when
3049 generating PIC code. FIXME: What is the correct thing to do
3050 for functions which make no calls and allocate no frame? Do
3051 we need to allocate a frame, or can we just omit the save? For
3052 now we'll just omit the save. */
3053 if (actual_fsize != 0 && flag_pic && !TARGET_64BIT)
3054 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3058 Instead of taking one argument, the counter label, as most normal
3059 mcounts do, _mcount appears to behave differently on the HPPA. It
3060 takes the return address of the caller, the address of this routine,
3061 and the address of the label. Also, it isn't magic, so
3062 argument registers have to be preserved. */
3065 int pc_offset, i, arg_offset, basereg, offsetadj;
3067 pc_offset = 4 + (frame_pointer_needed
3068 ? (VAL_14_BITS_P (actual_fsize) ? 12 : 20)
3069 : (VAL_14_BITS_P (actual_fsize) ? 4 : 8));
3071 /* When the function has a frame pointer, use it as the base
3072 register for saving/restore registers. Else use the stack
3073 pointer. Adjust the offset according to the frame size if
3074 this function does not have a frame pointer. */
3076 basereg = frame_pointer_needed ? FRAME_POINTER_REGNUM
3077 : STACK_POINTER_REGNUM;
3078 offsetadj = frame_pointer_needed ? 0 : actual_fsize;
3080 /* Horrid hack. emit_function_prologue will modify this RTL in
3081 place to get the expected results. sprintf here is just to
3082 put something in the name. */
3083 sprintf(hp_profile_label_name, "LP$%04d", -1);
3084 hp_profile_label_rtx = gen_rtx_SYMBOL_REF (Pmode,
3085 hp_profile_label_name);
3086 if (current_function_returns_struct)
3087 store_reg (STRUCT_VALUE_REGNUM, - 12 - offsetadj, basereg);
3088 if (current_function_needs_context)
3089 store_reg (STATIC_CHAIN_REGNUM, - 16 - offsetadj, basereg);
3091 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
3092 if (regs_ever_live [i])
3094 store_reg (i, arg_offset, basereg);
3095 /* Deal with arg_offset not fitting in 14 bits. */
3096 pc_offset += VAL_14_BITS_P (arg_offset) ? 4 : 8;
3099 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3100 emit_move_insn (tmpreg, gen_rtx_HIGH (Pmode, hp_profile_label_rtx));
3101 emit_move_insn (gen_rtx_REG (Pmode, 24),
3102 gen_rtx_LO_SUM (Pmode, tmpreg, hp_profile_label_rtx));
3103 /* %r25 is set from within the output pattern. */
3104 emit_insn (gen_call_profiler (GEN_INT (- pc_offset - 20)));
3106 /* Restore argument registers. */
3107 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
3108 if (regs_ever_live [i])
3109 load_reg (i, arg_offset, basereg);
3111 if (current_function_returns_struct)
3112 load_reg (STRUCT_VALUE_REGNUM, -12 - offsetadj, basereg);
3114 if (current_function_needs_context)
3115 load_reg (STATIC_CHAIN_REGNUM, -16 - offsetadj, basereg);
3118 /* Normal register save.
3120 Do not save the frame pointer in the frame_pointer_needed case. It
3121 was done earlier. */
3122 if (frame_pointer_needed)
3124 for (i = 18, offset = local_fsize; i >= 4; i--)
3125 if (regs_ever_live[i] && ! call_used_regs[i])
3127 store_reg (i, offset, FRAME_POINTER_REGNUM);
3128 offset += UNITS_PER_WORD;
3131 /* Account for %r3 which is saved in a special place. */
3134 /* No frame pointer needed. */
3137 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3138 if (regs_ever_live[i] && ! call_used_regs[i])
3140 /* If merge_sp_adjust_with_store is nonzero, then we can
3141 optimize the first GR save. */
3142 if (merge_sp_adjust_with_store)
3144 merge_sp_adjust_with_store = 0;
3145 emit_insn (gen_post_store (stack_pointer_rtx,
3146 gen_rtx_REG (word_mode, i),
3147 GEN_INT (-offset)));
3150 store_reg (i, offset, STACK_POINTER_REGNUM);
3151 offset += UNITS_PER_WORD;
3155 /* If we wanted to merge the SP adjustment with a GR save, but we never
3156 did any GR saves, then just emit the adjustment here. */
3157 if (merge_sp_adjust_with_store)
3158 set_reg_plus_d (STACK_POINTER_REGNUM,
3159 STACK_POINTER_REGNUM,
3163 /* Align pointer properly (doubleword boundary). */
3164 offset = (offset + 7) & ~7;
3166 /* Floating point register store. */
3169 /* First get the frame or stack pointer to the start of the FP register
3171 if (frame_pointer_needed)
3172 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
3174 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
3176 /* Now actually save the FP registers. */
3177 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3179 if (regs_ever_live[i]
3180 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3182 emit_move_insn (gen_rtx_MEM (DFmode,
3183 gen_rtx_POST_INC (DFmode, tmpreg)),
3184 gen_rtx_REG (DFmode, i));
3193 output_function_epilogue (file, size)
3195 int size ATTRIBUTE_UNUSED;
3197 rtx insn = get_last_insn ();
3199 /* hppa_expand_epilogue does the dirty work now. We just need
3200 to output the assembler directives which denote the end
3203 To make debuggers happy, emit a nop if the epilogue was completely
3204 eliminated due to a volatile call as the last insn in the
3205 current function. That way the return address (in %r2) will
3206 always point to a valid instruction in the current function. */
3208 /* Get the last real insn. */
3209 if (GET_CODE (insn) == NOTE)
3210 insn = prev_real_insn (insn);
3212 /* If it is a sequence, then look inside. */
3213 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3214 insn = XVECEXP (PATTERN (insn), 0, 0);
3216 /* If insn is a CALL_INSN, then it must be a call to a volatile
3217 function (otherwise there would be epilogue insns). */
3218 if (insn && GET_CODE (insn) == CALL_INSN)
3219 fputs ("\tnop\n", file);
3221 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3225 hppa_expand_epilogue ()
3229 int merge_sp_adjust_with_load = 0;
3231 /* We will use this often. */
3232 tmpreg = gen_rtx_REG (word_mode, 1);
3234 /* Try to restore RP early to avoid load/use interlocks when
3235 RP gets used in the return (bv) instruction. This appears to still
3236 be necessary even when we schedule the prologue and epilogue. */
3237 if (frame_pointer_needed
3239 && (regs_ever_live [2] || profile_flag))
3240 load_reg (2, -20, FRAME_POINTER_REGNUM);
3241 else if (TARGET_64BIT && frame_pointer_needed
3242 && (regs_ever_live[2] || profile_flag))
3243 load_reg (2, -16, FRAME_POINTER_REGNUM);
3244 else if (TARGET_64BIT
3245 && ! frame_pointer_needed
3246 && (regs_ever_live[2] || profile_flag)
3247 && VAL_14_BITS_P (actual_fsize + 20))
3248 load_reg (2, - (actual_fsize + 16), STACK_POINTER_REGNUM);
3249 /* No frame pointer, and stack is smaller than 8k. */
3250 else if (! frame_pointer_needed
3251 && VAL_14_BITS_P (actual_fsize + 20)
3252 && (regs_ever_live[2] || profile_flag))
3253 load_reg (2, - (actual_fsize + 20), STACK_POINTER_REGNUM);
3255 /* General register restores. */
3256 if (frame_pointer_needed)
3258 for (i = 18, offset = local_fsize; i >= 4; i--)
3259 if (regs_ever_live[i] && ! call_used_regs[i])
3261 load_reg (i, offset, FRAME_POINTER_REGNUM);
3262 offset += UNITS_PER_WORD;
3267 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3269 if (regs_ever_live[i] && ! call_used_regs[i])
3271 /* Only for the first load.
3272 merge_sp_adjust_with_load holds the register load
3273 with which we will merge the sp adjustment. */
3274 if (VAL_14_BITS_P (actual_fsize + 20)
3276 && ! merge_sp_adjust_with_load)
3277 merge_sp_adjust_with_load = i;
3279 load_reg (i, offset, STACK_POINTER_REGNUM);
3280 offset += UNITS_PER_WORD;
3285 /* Align pointer properly (doubleword boundary). */
3286 offset = (offset + 7) & ~7;
3288 /* FP register restores. */
3291 /* Adjust the register to index off of. */
3292 if (frame_pointer_needed)
3293 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
3295 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
3297 /* Actually do the restores now. */
3298 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3300 if (regs_ever_live[i]
3301 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3303 emit_move_insn (gen_rtx_REG (DFmode, i),
3304 gen_rtx_MEM (DFmode,
3305 gen_rtx_POST_INC (DFmode, tmpreg)));
3310 /* Emit a blockage insn here to keep these insns from being moved to
3311 an earlier spot in the epilogue, or into the main instruction stream.
3313 This is necessary as we must not cut the stack back before all the
3314 restores are finished. */
3315 emit_insn (gen_blockage ());
3316 /* No frame pointer, but we have a stack greater than 8k. We restore
3317 %r2 very late in this case. (All other cases are restored as early
3319 if (! frame_pointer_needed
3320 && ! VAL_14_BITS_P (actual_fsize + 20)
3322 && (regs_ever_live[2] || profile_flag))
3324 set_reg_plus_d (STACK_POINTER_REGNUM,
3325 STACK_POINTER_REGNUM,
3328 /* This used to try and be clever by not depending on the value in
3329 %r30 and instead use the value held in %r1 (so that the 2nd insn
3330 which sets %r30 could be put in the delay slot of the return insn).
3332 That won't work since if the stack is exactly 8k set_reg_plus_d
3333 doesn't set %r1, just %r30. */
3334 load_reg (2, - 20, STACK_POINTER_REGNUM);
3336 else if (! frame_pointer_needed
3337 && ! VAL_14_BITS_P (actual_fsize + 20)
3339 && (regs_ever_live[2] || profile_flag))
3341 set_reg_plus_d (STACK_POINTER_REGNUM,
3342 STACK_POINTER_REGNUM,
3345 /* This used to try and be clever by not depending on the value in
3346 %r30 and instead use the value held in %r1 (so that the 2nd insn
3347 which sets %r30 could be put in the delay slot of the return insn).
3349 That won't work since if the stack is exactly 8k set_reg_plus_d
3350 doesn't set %r1, just %r30. */
3351 load_reg (2, - 16, STACK_POINTER_REGNUM);
3354 /* Reset stack pointer (and possibly frame pointer). The stack
3355 pointer is initially set to fp + 64 to avoid a race condition. */
3356 else if (frame_pointer_needed)
3358 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64);
3359 emit_insn (gen_pre_load (frame_pointer_rtx,
3363 /* If we were deferring a callee register restore, do it now. */
3364 else if (! frame_pointer_needed && merge_sp_adjust_with_load)
3365 emit_insn (gen_pre_load (gen_rtx_REG (word_mode, merge_sp_adjust_with_load),
3367 GEN_INT (- actual_fsize)));
3368 else if (actual_fsize != 0)
3369 set_reg_plus_d (STACK_POINTER_REGNUM,
3370 STACK_POINTER_REGNUM,
3374 /* Set up a callee saved register for the pic offset table register. */
3375 void hppa_init_pic_save ()
3379 picreg = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM);
3380 PIC_OFFSET_TABLE_SAVE_RTX = gen_reg_rtx (Pmode);
3381 insn = gen_rtx_SET (VOIDmode, PIC_OFFSET_TABLE_SAVE_RTX, picreg);
3383 /* Emit the insn at the beginning of the function after the prologue. */
3384 push_topmost_sequence ();
3385 emit_insn_after (insn, last_parm_insn ? last_parm_insn : get_insns ());
3386 pop_topmost_sequence ();
3389 /* Fetch the return address for the frame COUNT steps up from
3390 the current frame, after the prologue. FRAMEADDR is the
3391 frame pointer of the COUNT frame.
3393 We want to ignore any export stub remnants here.
3395 The value returned is used in two different ways:
3397 1. To find a function's caller.
3399 2. To change the return address for a function.
3401 This function handles most instances of case 1; however, it will
3402 fail if there are two levels of stubs to execute on the return
3403 path. The only way I believe that can happen is if the return value
3404 needs a parameter relocation, which never happens for C code.
3406 This function handles most instances of case 2; however, it will
3407 fail if we did not originally have stub code on the return path
3408 but will need code on the new return path. This can happen if
3409 the caller & callee are both in the main program, but the new
3410 return location is in a shared library.
3412 To handle this correctly we need to set the return pointer at
3413 frame-20 to point to a return stub frame-24 to point to the
3414 location we wish to return to. */
3417 return_addr_rtx (count, frameaddr)
3418 int count ATTRIBUTE_UNUSED;
3425 saved_rp = gen_reg_rtx (Pmode);
3427 /* First, we start off with the normal return address pointer from
3431 return gen_rtx_MEM (Pmode, plus_constant (frameaddr, -16));
3433 emit_move_insn (saved_rp, plus_constant (frameaddr, -5 * UNITS_PER_WORD));
3435 /* Get pointer to the instruction stream. We have to mask out the
3436 privilege level from the two low order bits of the return address
3437 pointer here so that ins will point to the start of the first
3438 instruction that would have been executed if we returned. */
3439 ins = copy_to_reg (gen_rtx_AND (Pmode,
3440 copy_to_reg (gen_rtx_MEM (Pmode, saved_rp)),
3442 label = gen_label_rtx ();
3444 /* Check the instruction stream at the normal return address for the
3447 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3448 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3449 0x00011820 | stub+16: mtsp r1,sr0
3450 0xe0400002 | stub+20: be,n 0(sr0,rp)
3452 If it is an export stub, than our return address is really in
3455 emit_cmp_insn (gen_rtx_MEM (SImode, ins),
3456 GEN_INT (0x4bc23fd1),
3457 NE, NULL_RTX, SImode, 1, 0);
3458 emit_jump_insn (gen_bne (label));
3460 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3461 GEN_INT (0x004010a1),
3462 NE, NULL_RTX, SImode, 1, 0);
3463 emit_jump_insn (gen_bne (label));
3465 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3466 GEN_INT (0x00011820),
3467 NE, NULL_RTX, SImode, 1, 0);
3468 emit_jump_insn (gen_bne (label));
3470 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3471 GEN_INT (0xe0400002),
3472 NE, NULL_RTX, SImode, 1, 0);
3474 /* If there is no export stub then just use our initial guess of
3477 emit_jump_insn (gen_bne (label));
3479 /* Here we know that our return address pointer points to an export
3480 stub. We don't want to return the address of the export stub,
3481 but rather the return address that leads back into user code.
3482 That return address is stored at -24[frameaddr]. */
3484 emit_move_insn (saved_rp, plus_constant (frameaddr, -6 * UNITS_PER_WORD));
3487 return gen_rtx_MEM (Pmode, memory_address (Pmode, saved_rp));
3490 /* This is only valid once reload has completed because it depends on
3491 knowing exactly how much (if any) frame there is and...
3493 It's only valid if there is no frame marker to de-allocate and...
3495 It's only valid if %r2 hasn't been saved into the caller's frame
3496 (we're not profiling and %r2 isn't live anywhere). */
3498 hppa_can_use_return_insn_p ()
3500 return (reload_completed
3501 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3503 && ! regs_ever_live[2]
3504 && ! frame_pointer_needed);
3508 emit_bcond_fp (code, operand0)
3512 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3513 gen_rtx_IF_THEN_ELSE (VOIDmode,
3514 gen_rtx_fmt_ee (code,
3516 gen_rtx_REG (CCFPmode, 0),
3518 gen_rtx_LABEL_REF (VOIDmode, operand0),
3524 gen_cmp_fp (code, operand0, operand1)
3526 rtx operand0, operand1;
3528 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3529 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3532 /* Adjust the cost of a scheduling dependency. Return the new cost of
3533 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3536 pa_adjust_cost (insn, link, dep_insn, cost)
3542 enum attr_type attr_type;
3544 /* Don't adjust costs for a pa8000 chip. */
3545 if (pa_cpu >= PROCESSOR_8000)
3548 if (! recog_memoized (insn))
3551 attr_type = get_attr_type (insn);
3553 if (REG_NOTE_KIND (link) == 0)
3555 /* Data dependency; DEP_INSN writes a register that INSN reads some
3558 if (attr_type == TYPE_FPSTORE)
3560 rtx pat = PATTERN (insn);
3561 rtx dep_pat = PATTERN (dep_insn);
3562 if (GET_CODE (pat) == PARALLEL)
3564 /* This happens for the fstXs,mb patterns. */
3565 pat = XVECEXP (pat, 0, 0);
3567 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3568 /* If this happens, we have to extend this to schedule
3569 optimally. Return 0 for now. */
3572 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
3574 if (! recog_memoized (dep_insn))
3576 /* DEP_INSN is writing its result to the register
3577 being stored in the fpstore INSN. */
3578 switch (get_attr_type (dep_insn))
3581 /* This cost 3 cycles, not 2 as the md says for the
3590 case TYPE_FPSQRTSGL:
3591 case TYPE_FPSQRTDBL:
3592 /* In these important cases, we save one cycle compared to
3593 when flop instruction feed each other. */
3602 /* For other data dependencies, the default cost specified in the
3606 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3608 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3611 if (attr_type == TYPE_FPLOAD)
3613 rtx pat = PATTERN (insn);
3614 rtx dep_pat = PATTERN (dep_insn);
3615 if (GET_CODE (pat) == PARALLEL)
3617 /* This happens for the fldXs,mb patterns. */
3618 pat = XVECEXP (pat, 0, 0);
3620 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3621 /* If this happens, we have to extend this to schedule
3622 optimally. Return 0 for now. */
3625 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3627 if (! recog_memoized (dep_insn))
3629 switch (get_attr_type (dep_insn))
3636 case TYPE_FPSQRTSGL:
3637 case TYPE_FPSQRTDBL:
3638 /* A fpload can't be issued until one cycle before a
3639 preceding arithmetic operation has finished if
3640 the target of the fpload is any of the sources
3641 (or destination) of the arithmetic operation. */
3649 else if (attr_type == TYPE_FPALU)
3651 rtx pat = PATTERN (insn);
3652 rtx dep_pat = PATTERN (dep_insn);
3653 if (GET_CODE (pat) == PARALLEL)
3655 /* This happens for the fldXs,mb patterns. */
3656 pat = XVECEXP (pat, 0, 0);
3658 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3659 /* If this happens, we have to extend this to schedule
3660 optimally. Return 0 for now. */
3663 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3665 if (! recog_memoized (dep_insn))
3667 switch (get_attr_type (dep_insn))
3671 case TYPE_FPSQRTSGL:
3672 case TYPE_FPSQRTDBL:
3673 /* An ALU flop can't be issued until two cycles before a
3674 preceding divide or sqrt operation has finished if
3675 the target of the ALU flop is any of the sources
3676 (or destination) of the divide or sqrt operation. */
3685 /* For other anti dependencies, the cost is 0. */
3688 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3690 /* Output dependency; DEP_INSN writes a register that INSN writes some
3692 if (attr_type == TYPE_FPLOAD)
3694 rtx pat = PATTERN (insn);
3695 rtx dep_pat = PATTERN (dep_insn);
3696 if (GET_CODE (pat) == PARALLEL)
3698 /* This happens for the fldXs,mb patterns. */
3699 pat = XVECEXP (pat, 0, 0);
3701 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3702 /* If this happens, we have to extend this to schedule
3703 optimally. Return 0 for now. */
3706 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3708 if (! recog_memoized (dep_insn))
3710 switch (get_attr_type (dep_insn))
3717 case TYPE_FPSQRTSGL:
3718 case TYPE_FPSQRTDBL:
3719 /* A fpload can't be issued until one cycle before a
3720 preceding arithmetic operation has finished if
3721 the target of the fpload is the destination of the
3722 arithmetic operation. */
3730 else if (attr_type == TYPE_FPALU)
3732 rtx pat = PATTERN (insn);
3733 rtx dep_pat = PATTERN (dep_insn);
3734 if (GET_CODE (pat) == PARALLEL)
3736 /* This happens for the fldXs,mb patterns. */
3737 pat = XVECEXP (pat, 0, 0);
3739 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3740 /* If this happens, we have to extend this to schedule
3741 optimally. Return 0 for now. */
3744 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3746 if (! recog_memoized (dep_insn))
3748 switch (get_attr_type (dep_insn))
3752 case TYPE_FPSQRTSGL:
3753 case TYPE_FPSQRTDBL:
3754 /* An ALU flop can't be issued until two cycles before a
3755 preceding divide or sqrt operation has finished if
3756 the target of the ALU flop is also the target of
3757 the divide or sqrt operation. */
3766 /* For other output dependencies, the cost is 0. */
3773 /* Return any length adjustment needed by INSN which already has its length
3774 computed as LENGTH. Return zero if no adjustment is necessary.
3776 For the PA: function calls, millicode calls, and backwards short
3777 conditional branches with unfilled delay slots need an adjustment by +1
3778 (to account for the NOP which will be inserted into the instruction stream).
3780 Also compute the length of an inline block move here as it is too
3781 complicated to express as a length attribute in pa.md. */
3783 pa_adjust_insn_length (insn, length)
3787 rtx pat = PATTERN (insn);
3789 /* Call insns which are *not* indirect and have unfilled delay slots. */
3790 if (GET_CODE (insn) == CALL_INSN)
3793 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
3794 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
3796 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
3797 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
3803 /* Jumps inside switch tables which have unfilled delay slots
3804 also need adjustment. */
3805 else if (GET_CODE (insn) == JUMP_INSN
3806 && simplejump_p (insn)
3807 && GET_MODE (insn) == SImode)
3809 /* Millicode insn with an unfilled delay slot. */
3810 else if (GET_CODE (insn) == INSN
3811 && GET_CODE (pat) != SEQUENCE
3812 && GET_CODE (pat) != USE
3813 && GET_CODE (pat) != CLOBBER
3814 && get_attr_type (insn) == TYPE_MILLI)
3816 /* Block move pattern. */
3817 else if (GET_CODE (insn) == INSN
3818 && GET_CODE (pat) == PARALLEL
3819 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
3820 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
3821 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
3822 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
3823 return compute_movstrsi_length (insn) - 4;
3824 /* Conditional branch with an unfilled delay slot. */
3825 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
3827 /* Adjust a short backwards conditional with an unfilled delay slot. */
3828 if (GET_CODE (pat) == SET
3830 && ! forward_branch_p (insn))
3832 else if (GET_CODE (pat) == PARALLEL
3833 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
3836 /* Adjust dbra insn with short backwards conditional branch with
3837 unfilled delay slot -- only for case where counter is in a
3838 general register register. */
3839 else if (GET_CODE (pat) == PARALLEL
3840 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
3841 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
3842 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
3844 && ! forward_branch_p (insn))
3852 /* Print operand X (an rtx) in assembler syntax to file FILE.
3853 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3854 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3857 print_operand (file, x, code)
3865 /* Output a 'nop' if there's nothing for the delay slot. */
3866 if (dbr_sequence_length () == 0)
3867 fputs ("\n\tnop", file);
3870 /* Output an nullification completer if there's nothing for the */
3871 /* delay slot or nullification is requested. */
3872 if (dbr_sequence_length () == 0 ||
3874 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
3878 /* Print out the second register name of a register pair.
3879 I.e., R (6) => 7. */
3880 fputs (reg_names[REGNO (x)+1], file);
3883 /* A register or zero. */
3885 || (x == CONST0_RTX (DFmode))
3886 || (x == CONST0_RTX (SFmode)))
3888 fputs ("%r0", file);
3894 /* A register or zero (floating point). */
3896 || (x == CONST0_RTX (DFmode))
3897 || (x == CONST0_RTX (SFmode)))
3899 fputs ("%fr0", file);
3904 case 'C': /* Plain (C)ondition */
3906 switch (GET_CODE (x))
3909 fputs ("=", file); break;
3911 fputs ("<>", file); break;
3913 fputs (">", file); break;
3915 fputs (">=", file); break;
3917 fputs (">>=", file); break;
3919 fputs (">>", file); break;
3921 fputs ("<", file); break;
3923 fputs ("<=", file); break;
3925 fputs ("<<=", file); break;
3927 fputs ("<<", file); break;
3932 case 'N': /* Condition, (N)egated */
3933 switch (GET_CODE (x))
3936 fputs ("<>", file); break;
3938 fputs ("=", file); break;
3940 fputs ("<=", file); break;
3942 fputs ("<", file); break;
3944 fputs ("<<", file); break;
3946 fputs ("<<=", file); break;
3948 fputs (">=", file); break;
3950 fputs (">", file); break;
3952 fputs (">>", file); break;
3954 fputs (">>=", file); break;
3959 /* For floating point comparisons. Note that the output predicates are the
3960 complement of the desired mode. */
3962 switch (GET_CODE (x))
3965 fputs ("!=", file); break;
3967 fputs ("=", file); break;
3969 fputs ("!>", file); break;
3971 fputs ("!>=", file); break;
3973 fputs ("!<", file); break;
3975 fputs ("!<=", file); break;
3977 fputs ("!<>", file); break;
3979 fputs (">", file); break;
3981 fputs (">=", file); break;
3983 fputs ("<", file); break;
3985 fputs ("<=", file); break;
3987 fputs ("<>", file); break;
3989 fputs ("<=>", file); break;
3991 fputs ("!<=>", file); break;
3996 case 'S': /* Condition, operands are (S)wapped. */
3997 switch (GET_CODE (x))
4000 fputs ("=", file); break;
4002 fputs ("<>", file); break;
4004 fputs ("<", file); break;
4006 fputs ("<=", file); break;
4008 fputs ("<<=", file); break;
4010 fputs ("<<", file); break;
4012 fputs (">", file); break;
4014 fputs (">=", file); break;
4016 fputs (">>=", file); break;
4018 fputs (">>", file); break;
4023 case 'B': /* Condition, (B)oth swapped and negate. */
4024 switch (GET_CODE (x))
4027 fputs ("<>", file); break;
4029 fputs ("=", file); break;
4031 fputs (">=", file); break;
4033 fputs (">", file); break;
4035 fputs (">>", file); break;
4037 fputs (">>=", file); break;
4039 fputs ("<=", file); break;
4041 fputs ("<", file); break;
4043 fputs ("<<", file); break;
4045 fputs ("<<=", file); break;
4051 if (GET_CODE (x) == CONST_INT)
4053 fprintf (file, "%d", ~INTVAL (x));
4058 if (GET_CODE (x) == CONST_INT)
4060 fprintf (file, "%d", 64 - (INTVAL (x) & 63));
4065 if (GET_CODE (x) == CONST_INT)
4067 fprintf (file, "%d", 32 - (INTVAL (x) & 31));
4072 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4074 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4079 if (GET_CODE (x) == CONST_INT)
4081 fprintf (file, "%d", 63 - (INTVAL (x) & 63));
4086 if (GET_CODE (x) == CONST_INT)
4088 fprintf (file, "%d", 31 - (INTVAL (x) & 31));
4093 if (GET_CODE (x) == CONST_INT)
4098 switch (GET_CODE (XEXP (x, 0)))
4102 if (ASSEMBLER_DIALECT == 0)
4103 fputs ("s,mb", file);
4105 fputs (",mb", file);
4109 if (ASSEMBLER_DIALECT == 0)
4110 fputs ("s,ma", file);
4112 fputs (",ma", file);
4115 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4116 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4118 if (ASSEMBLER_DIALECT == 0)
4119 fputs ("x,s", file);
4123 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4127 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4133 output_global_address (file, x, 0);
4136 output_global_address (file, x, 1);
4138 case 0: /* Don't do anything special */
4143 compute_zdepwi_operands (INTVAL (x), op);
4144 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4150 compute_zdepdi_operands (INTVAL (x), op);
4151 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4155 /* We can get here from a .vtable_inherit due to our
4156 CONSTANT_ADDRESS_P rejecting perfectly good constant
4162 if (GET_CODE (x) == REG)
4164 fputs (reg_names [REGNO (x)], file);
4165 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4171 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4172 && (REGNO (x) & 1) == 0)
4175 else if (GET_CODE (x) == MEM)
4177 int size = GET_MODE_SIZE (GET_MODE (x));
4178 rtx base = NULL_RTX;
4179 switch (GET_CODE (XEXP (x, 0)))
4183 base = XEXP (XEXP (x, 0), 0);
4184 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4188 base = XEXP (XEXP (x, 0), 0);
4189 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4192 if (GET_CODE (XEXP (x, 0)) == PLUS
4193 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4194 fprintf (file, "%s(%s)",
4195 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4196 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4197 else if (GET_CODE (XEXP (x, 0)) == PLUS
4198 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4199 fprintf (file, "%s(%s)",
4200 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4201 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4203 output_address (XEXP (x, 0));
4208 output_addr_const (file, x);
4211 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4214 output_global_address (file, x, round_constant)
4220 /* Imagine (high (const (plus ...))). */
4221 if (GET_CODE (x) == HIGH)
4224 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4225 assemble_name (file, XSTR (x, 0));
4226 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4228 assemble_name (file, XSTR (x, 0));
4229 fputs ("-$global$", file);
4231 else if (GET_CODE (x) == CONST)
4233 const char *sep = "";
4234 int offset = 0; /* assembler wants -$global$ at end */
4235 rtx base = NULL_RTX;
4237 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4239 base = XEXP (XEXP (x, 0), 0);
4240 output_addr_const (file, base);
4242 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4243 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4246 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4248 base = XEXP (XEXP (x, 0), 1);
4249 output_addr_const (file, base);
4251 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4252 offset = INTVAL (XEXP (XEXP (x, 0),1));
4255 /* How bogus. The compiler is apparently responsible for
4256 rounding the constant if it uses an LR field selector.
4258 The linker and/or assembler seem a better place since
4259 they have to do this kind of thing already.
4261 If we fail to do this, HP's optimizing linker may eliminate
4262 an addil, but not update the ldw/stw/ldo instruction that
4263 uses the result of the addil. */
4265 offset = ((offset + 0x1000) & ~0x1fff);
4267 if (GET_CODE (XEXP (x, 0)) == PLUS)
4277 else if (GET_CODE (XEXP (x, 0)) == MINUS
4278 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4282 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4283 fputs ("-$global$", file);
4285 fprintf (file,"%s%d", sep, offset);
4288 output_addr_const (file, x);
4292 output_deferred_plabels (file)
4296 /* If we have deferred plabels, then we need to switch into the data
4297 section and align it to a 4 byte boundary before we output the
4298 deferred plabels. */
4299 if (n_deferred_plabels)
4302 ASM_OUTPUT_ALIGN (file, 2);
4305 /* Now output the deferred plabels. */
4306 for (i = 0; i < n_deferred_plabels; i++)
4308 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4309 assemble_integer (gen_rtx_SYMBOL_REF (VOIDmode,
4310 deferred_plabels[i].name), 4, 1);
4314 /* HP's millicode routines mean something special to the assembler.
4315 Keep track of which ones we have used. */
4317 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
4318 static void import_milli PARAMS ((enum millicodes));
4319 static char imported[(int)end1000];
4320 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4321 static char import_string[] = ".IMPORT $$....,MILLICODE";
4322 #define MILLI_START 10
4326 enum millicodes code;
4328 char str[sizeof (import_string)];
4330 if (!imported[(int)code])
4332 imported[(int)code] = 1;
4333 strcpy (str, import_string);
4334 strncpy (str + MILLI_START, milli_names[(int)code], 4);
4335 output_asm_insn (str, 0);
4339 /* The register constraints have put the operands and return value in
4340 the proper registers. */
4343 output_mul_insn (unsignedp, insn)
4344 int unsignedp ATTRIBUTE_UNUSED;
4347 import_milli (mulI);
4348 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4351 /* Emit the rtl for doing a division by a constant. */
4353 /* Do magic division millicodes exist for this value? */
4354 static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4357 /* We'll use an array to keep track of the magic millicodes and
4358 whether or not we've used them already. [n][0] is signed, [n][1] is
4361 static int div_milli[16][2];
4364 div_operand (op, mode)
4366 enum machine_mode mode;
4368 return (mode == SImode
4369 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4370 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4371 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4375 emit_hpdiv_const (operands, unsignedp)
4379 if (GET_CODE (operands[2]) == CONST_INT
4380 && INTVAL (operands[2]) > 0
4381 && INTVAL (operands[2]) < 16
4382 && magic_milli[INTVAL (operands[2])])
4384 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4387 (PARALLEL, VOIDmode,
4388 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4389 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4391 gen_rtx_REG (SImode, 26),
4393 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4394 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4395 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4396 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4397 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 31)))));
4398 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4405 output_div_insn (operands, unsignedp, insn)
4412 /* If the divisor is a constant, try to use one of the special
4414 if (GET_CODE (operands[0]) == CONST_INT)
4416 static char buf[100];
4417 divisor = INTVAL (operands[0]);
4418 if (!div_milli[divisor][unsignedp])
4420 div_milli[divisor][unsignedp] = 1;
4422 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4424 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4428 sprintf (buf, "$$divU_%d", INTVAL (operands[0]));
4429 return output_millicode_call (insn,
4430 gen_rtx_SYMBOL_REF (SImode, buf));
4434 sprintf (buf, "$$divI_%d", INTVAL (operands[0]));
4435 return output_millicode_call (insn,
4436 gen_rtx_SYMBOL_REF (SImode, buf));
4439 /* Divisor isn't a special constant. */
4444 import_milli (divU);
4445 return output_millicode_call (insn,
4446 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4450 import_milli (divI);
4451 return output_millicode_call (insn,
4452 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4457 /* Output a $$rem millicode to do mod. */
4460 output_mod_insn (unsignedp, insn)
4466 import_milli (remU);
4467 return output_millicode_call (insn,
4468 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4472 import_milli (remI);
4473 return output_millicode_call (insn,
4474 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4479 output_arg_descriptor (call_insn)
4482 const char *arg_regs[4];
4483 enum machine_mode arg_mode;
4485 int i, output_flag = 0;
4488 /* We neither need nor want argument location descriptors for the
4489 64bit runtime environment. */
4493 for (i = 0; i < 4; i++)
4496 /* Specify explicitly that no argument relocations should take place
4497 if using the portable runtime calling conventions. */
4498 if (TARGET_PORTABLE_RUNTIME)
4500 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4505 if (GET_CODE (call_insn) != CALL_INSN)
4507 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4509 rtx use = XEXP (link, 0);
4511 if (! (GET_CODE (use) == USE
4512 && GET_CODE (XEXP (use, 0)) == REG
4513 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4516 arg_mode = GET_MODE (XEXP (use, 0));
4517 regno = REGNO (XEXP (use, 0));
4518 if (regno >= 23 && regno <= 26)
4520 arg_regs[26 - regno] = "GR";
4521 if (arg_mode == DImode)
4522 arg_regs[25 - regno] = "GR";
4524 else if (regno >= 32 && regno <= 39)
4526 if (arg_mode == SFmode)
4527 arg_regs[(regno - 32) / 2] = "FR";
4530 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4531 arg_regs[(regno - 34) / 2] = "FR";
4532 arg_regs[(regno - 34) / 2 + 1] = "FU";
4534 arg_regs[(regno - 34) / 2] = "FU";
4535 arg_regs[(regno - 34) / 2 + 1] = "FR";
4540 fputs ("\t.CALL ", asm_out_file);
4541 for (i = 0; i < 4; i++)
4546 fputc (',', asm_out_file);
4547 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4550 fputc ('\n', asm_out_file);
4553 /* Return the class of any secondary reload register that is needed to
4554 move IN into a register in class CLASS using mode MODE.
4556 Profiling has showed this routine and its descendants account for
4557 a significant amount of compile time (~7%). So it has been
4558 optimized to reduce redundant computations and eliminate useless
4561 It might be worthwhile to try and make this a leaf function too. */
4564 secondary_reload_class (class, mode, in)
4565 enum reg_class class;
4566 enum machine_mode mode;
4569 int regno, is_symbolic;
4571 /* Trying to load a constant into a FP register during PIC code
4572 generation will require %r1 as a scratch register. */
4574 && GET_MODE_CLASS (mode) == MODE_INT
4575 && FP_REG_CLASS_P (class)
4576 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4579 /* Profiling showed the PA port spends about 1.3% of its compilation
4580 time in true_regnum from calls inside secondary_reload_class. */
4582 if (GET_CODE (in) == REG)
4585 if (regno >= FIRST_PSEUDO_REGISTER)
4586 regno = true_regnum (in);
4588 else if (GET_CODE (in) == SUBREG)
4589 regno = true_regnum (in);
4593 /* If we have something like (mem (mem (...)), we can safely assume the
4594 inner MEM will end up in a general register after reloading, so there's
4595 no need for a secondary reload. */
4596 if (GET_CODE (in) == MEM
4597 && GET_CODE (XEXP (in, 0)) == MEM)
4600 /* Handle out of range displacement for integer mode loads/stores of
4602 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
4603 && GET_MODE_CLASS (mode) == MODE_INT
4604 && FP_REG_CLASS_P (class))
4605 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
4606 return GENERAL_REGS;
4608 if (GET_CODE (in) == HIGH)
4611 /* Profiling has showed GCC spends about 2.6% of its compilation
4612 time in symbolic_operand from calls inside secondary_reload_class.
4614 We use an inline copy and only compute its return value once to avoid
4616 switch (GET_CODE (in))
4626 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
4627 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
4628 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
4638 && read_only_operand (in, VOIDmode))
4641 if (class != R1_REGS && is_symbolic)
4648 function_arg_padding (mode, type)
4649 enum machine_mode mode;
4654 if (mode == BLKmode)
4656 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4657 size = int_size_in_bytes (type) * BITS_PER_UNIT;
4659 return upward; /* Don't know if this is right, but */
4660 /* same as old definition. */
4663 size = GET_MODE_BITSIZE (mode);
4664 if (size < PARM_BOUNDARY)
4666 else if (size % PARM_BOUNDARY)
4673 /* Do what is necessary for `va_start'. We look at the current function
4674 to determine if stdargs or varargs is used and fill in an initial
4675 va_list. A pointer to this constructor is returned. */
4678 hppa_builtin_saveregs ()
4681 tree fntype = TREE_TYPE (current_function_decl);
4682 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
4683 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4684 != void_type_node)))
4685 ? UNITS_PER_WORD : 0);
4688 offset = plus_constant (current_function_arg_offset_rtx, argadj);
4690 offset = current_function_arg_offset_rtx;
4696 /* Adjust for varargs/stdarg differences. */
4698 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
4700 offset = current_function_arg_offset_rtx;
4702 /* We need to save %r26 .. %r19 inclusive starting at offset -64
4703 from the incoming arg pointer and growing to larger addresses. */
4704 for (i = 26, off = -64; i >= 19; i--, off += 8)
4705 emit_move_insn (gen_rtx_MEM (word_mode,
4706 plus_constant (arg_pointer_rtx, off)),
4707 gen_rtx_REG (word_mode, i));
4709 /* The incoming args pointer points just beyond the flushback area;
4710 normally this is not a serious concern. Howver, when we are doing
4711 varargs/stdargs we want to make the arg pointer point to the start
4712 of the incoming argument area. */
4713 emit_move_insn (virtual_incoming_args_rtx,
4714 plus_constant (arg_pointer_rtx, -64));
4716 /* Now return a pointer to the first anonymous argument. */
4717 return copy_to_reg (expand_binop (Pmode, add_optab,
4718 virtual_incoming_args_rtx,
4719 offset, 0, 0, OPTAB_LIB_WIDEN));
4722 /* Store general registers on the stack. */
4723 dest = gen_rtx_MEM (BLKmode,
4724 plus_constant (current_function_internal_arg_pointer,
4726 MEM_ALIAS_SET (dest) = get_varargs_alias_set ();
4727 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
4729 /* move_block_from_reg will emit code to store the argument registers
4730 individually as scalar stores.
4732 However, other insns may later load from the same addresses for
4733 a structure load (passing a struct to a varargs routine).
4735 The alias code assumes that such aliasing can never happen, so we
4736 have to keep memory referencing insns from moving up beyond the
4737 last argument register store. So we emit a blockage insn here. */
4738 emit_insn (gen_blockage ());
4740 if (current_function_check_memory_usage)
4741 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4743 GEN_INT (4 * UNITS_PER_WORD), TYPE_MODE (sizetype),
4744 GEN_INT (MEMORY_USE_RW),
4745 TYPE_MODE (integer_type_node));
4747 return copy_to_reg (expand_binop (Pmode, add_optab,
4748 current_function_internal_arg_pointer,
4749 offset, 0, 0, OPTAB_LIB_WIDEN));
4753 hppa_va_start (stdarg_p, valist, nextarg)
4754 int stdarg_p ATTRIBUTE_UNUSED;
4758 nextarg = expand_builtin_saveregs ();
4759 std_expand_builtin_va_start (1, valist, nextarg);
4763 hppa_va_arg (valist, type)
4766 HOST_WIDE_INT align, size, ofs;
4771 /* Every argument in PA64 is passed by value (including large structs).
4772 Arguments with size greater than 8 must be aligned 0 MOD 16. */
4774 size = int_size_in_bytes (type);
4775 if (size > UNITS_PER_WORD)
4777 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4778 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4779 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4780 build_int_2 (-2 * UNITS_PER_WORD, -1));
4781 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4782 TREE_SIDE_EFFECTS (t) = 1;
4783 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4785 return std_expand_builtin_va_arg (valist, type);
4788 /* Compute the rounded size of the type. */
4789 align = PARM_BOUNDARY / BITS_PER_UNIT;
4790 size = int_size_in_bytes (type);
4792 ptr = build_pointer_type (type);
4794 /* "Large" types are passed by reference. */
4797 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
4798 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4799 TREE_SIDE_EFFECTS (t) = 1;
4801 pptr = build_pointer_type (ptr);
4802 t = build1 (NOP_EXPR, pptr, t);
4803 TREE_SIDE_EFFECTS (t) = 1;
4805 t = build1 (INDIRECT_REF, ptr, t);
4806 TREE_SIDE_EFFECTS (t) = 1;
4810 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4811 build_int_2 (-size, -1));
4813 /* Copied from va-pa.h, but we probably don't need to align
4814 to word size, since we generate and preserve that invariant. */
4815 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
4816 build_int_2 ((size > 4 ? -8 : -4), -1));
4818 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4819 TREE_SIDE_EFFECTS (t) = 1;
4821 ofs = (8 - size) % 4;
4824 t = build (PLUS_EXPR, TREE_TYPE (valist), t, build_int_2 (ofs, 0));
4825 TREE_SIDE_EFFECTS (t) = 1;
4828 t = build1 (NOP_EXPR, ptr, t);
4829 TREE_SIDE_EFFECTS (t) = 1;
4833 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
4838 /* This routine handles all the normal conditional branch sequences we
4839 might need to generate. It handles compare immediate vs compare
4840 register, nullification of delay slots, varying length branches,
4841 negated branches, and all combinations of the above. It returns the
4842 output appropriate to emit the branch corresponding to all given
4846 output_cbranch (operands, nullify, length, negated, insn)
4848 int nullify, length, negated;
4851 static char buf[100];
4854 /* A conditional branch to the following instruction (eg the delay slot) is
4855 asking for a disaster. This can happen when not optimizing.
4857 In such cases it is safe to emit nothing. */
4859 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4862 /* If this is a long branch with its delay slot unfilled, set `nullify'
4863 as it can nullify the delay slot and save a nop. */
4864 if (length == 8 && dbr_sequence_length () == 0)
4867 /* If this is a short forward conditional branch which did not get
4868 its delay slot filled, the delay slot can still be nullified. */
4869 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4870 nullify = forward_branch_p (insn);
4872 /* A forward branch over a single nullified insn can be done with a
4873 comclr instruction. This avoids a single cycle penalty due to
4874 mis-predicted branch if we fall through (branch not taken). */
4876 && next_real_insn (insn) != 0
4877 && get_attr_length (next_real_insn (insn)) == 4
4878 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4884 /* All short conditional branches except backwards with an unfilled
4888 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
4890 strcpy (buf, "{com%I2b,|cmp%I2b,}");
4891 if (GET_MODE (operands[1]) == DImode)
4894 strcat (buf, "%B3");
4896 strcat (buf, "%S3");
4898 strcat (buf, " %2,%r1,%%r0");
4900 strcat (buf, ",n %2,%r1,%0");
4902 strcat (buf, " %2,%r1,%0");
4905 /* All long conditionals. Note an short backward branch with an
4906 unfilled delay slot is treated just like a long backward branch
4907 with an unfilled delay slot. */
4909 /* Handle weird backwards branch with a filled delay slot
4910 with is nullified. */
4911 if (dbr_sequence_length () != 0
4912 && ! forward_branch_p (insn)
4915 strcpy (buf, "{com%I2b,|cmp%I2b,}");
4916 if (GET_MODE (operands[1]) == DImode)
4919 strcat (buf, "%S3");
4921 strcat (buf, "%B3");
4922 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
4924 /* Handle short backwards branch with an unfilled delay slot.
4925 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
4926 taken and untaken branches. */
4927 else if (dbr_sequence_length () == 0
4928 && ! forward_branch_p (insn)
4929 && INSN_ADDRESSES_SET_P ()
4930 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
4931 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
4933 strcpy (buf, "{com%I2b,|cmp%I2b,}");
4934 if (GET_MODE (operands[1]) == DImode)
4937 strcat (buf, "%B3 %2,%r1,%0%#");
4939 strcat (buf, "%S3 %2,%r1,%0%#");
4943 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
4944 if (GET_MODE (operands[1]) == DImode)
4947 strcat (buf, "%S3");
4949 strcat (buf, "%B3");
4951 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
4953 strcat (buf, " %2,%r1,%%r0\n\tb %0");
4958 /* Very long branch. Right now we only handle these when not
4959 optimizing. See "jump" pattern in pa.md for details. */
4963 /* Create a reversed conditional branch which branches around
4964 the following insns. */
4966 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
4968 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
4969 if (GET_MODE (operands[1]) == DImode)
4973 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
4976 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
4978 output_asm_insn (buf, operands);
4980 /* Output an insn to save %r1. */
4981 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
4983 /* Now output a very long branch to the original target. */
4984 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
4986 /* Now restore the value of %r1 in the delay slot. We're not
4987 optimizing so we know nothing else can be in the delay slot. */
4988 return "ldw -16(%%r30),%%r1";
4991 /* Very long branch when generating PIC code. Right now we only
4992 handle these when not optimizing. See "jump" pattern in pa.md
4997 /* Create a reversed conditional branch which branches around
4998 the following insns. */
5000 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5002 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5003 if (GET_MODE (operands[1]) == DImode)
5006 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5008 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5010 output_asm_insn (buf, operands);
5012 /* Output an insn to save %r1. */
5013 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5015 /* Now output a very long PIC branch to the original target. */
5019 xoperands[0] = operands[0];
5020 xoperands[1] = operands[1];
5021 xoperands[2] = operands[2];
5022 xoperands[3] = operands[3];
5023 xoperands[4] = gen_label_rtx ();
5025 output_asm_insn ("{bl|b,l} .+8,%%r1\n\taddil L'%l0-%l4,%%r1",
5027 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5028 CODE_LABEL_NUMBER (xoperands[4]));
5029 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
5033 /* Now restore the value of %r1 in the delay slot. We're not
5034 optimizing so we know nothing else can be in the delay slot. */
5035 return "ldw -16(%%r30),%%r1";
5043 /* This routine handles all the branch-on-bit conditional branch sequences we
5044 might need to generate. It handles nullification of delay slots,
5045 varying length branches, negated branches and all combinations of the
5046 above. it returns the appropriate output template to emit the branch. */
5049 output_bb (operands, nullify, length, negated, insn, which)
5050 rtx *operands ATTRIBUTE_UNUSED;
5051 int nullify, length, negated;
5055 static char buf[100];
5058 /* A conditional branch to the following instruction (eg the delay slot) is
5059 asking for a disaster. I do not think this can happen as this pattern
5060 is only used when optimizing; jump optimization should eliminate the
5061 jump. But be prepared just in case. */
5063 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5066 /* If this is a long branch with its delay slot unfilled, set `nullify'
5067 as it can nullify the delay slot and save a nop. */
5068 if (length == 8 && dbr_sequence_length () == 0)
5071 /* If this is a short forward conditional branch which did not get
5072 its delay slot filled, the delay slot can still be nullified. */
5073 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5074 nullify = forward_branch_p (insn);
5076 /* A forward branch over a single nullified insn can be done with a
5077 extrs instruction. This avoids a single cycle penalty due to
5078 mis-predicted branch if we fall through (branch not taken). */
5081 && next_real_insn (insn) != 0
5082 && get_attr_length (next_real_insn (insn)) == 4
5083 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5090 /* All short conditional branches except backwards with an unfilled
5094 strcpy (buf, "{extrs,|extrw,s,}");
5096 strcpy (buf, "bb,");
5097 if (useskip && GET_MODE (operands[0]) == DImode)
5098 strcpy (buf, "extrd,s,*");
5099 else if (GET_MODE (operands[0]) == DImode)
5100 strcpy (buf, "bb,*");
5101 if ((which == 0 && negated)
5102 || (which == 1 && ! negated))
5107 strcat (buf, " %0,%1,1,%%r0");
5108 else if (nullify && negated)
5109 strcat (buf, ",n %0,%1,%3");
5110 else if (nullify && ! negated)
5111 strcat (buf, ",n %0,%1,%2");
5112 else if (! nullify && negated)
5113 strcat (buf, "%0,%1,%3");
5114 else if (! nullify && ! negated)
5115 strcat (buf, " %0,%1,%2");
5118 /* All long conditionals. Note an short backward branch with an
5119 unfilled delay slot is treated just like a long backward branch
5120 with an unfilled delay slot. */
5122 /* Handle weird backwards branch with a filled delay slot
5123 with is nullified. */
5124 if (dbr_sequence_length () != 0
5125 && ! forward_branch_p (insn)
5128 strcpy (buf, "bb,");
5129 if (GET_MODE (operands[0]) == DImode)
5131 if ((which == 0 && negated)
5132 || (which == 1 && ! negated))
5137 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5139 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5141 /* Handle short backwards branch with an unfilled delay slot.
5142 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5143 taken and untaken branches. */
5144 else if (dbr_sequence_length () == 0
5145 && ! forward_branch_p (insn)
5146 && INSN_ADDRESSES_SET_P ()
5147 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5148 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5150 strcpy (buf, "bb,");
5151 if (GET_MODE (operands[0]) == DImode)
5153 if ((which == 0 && negated)
5154 || (which == 1 && ! negated))
5159 strcat (buf, " %0,%1,%3%#");
5161 strcat (buf, " %0,%1,%2%#");
5165 strcpy (buf, "{extrs,|extrw,s,}");
5166 if (GET_MODE (operands[0]) == DImode)
5167 strcpy (buf, "extrd,s,*");
5168 if ((which == 0 && negated)
5169 || (which == 1 && ! negated))
5173 if (nullify && negated)
5174 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5175 else if (nullify && ! negated)
5176 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5178 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5180 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5190 /* This routine handles all the branch-on-variable-bit conditional branch
5191 sequences we might need to generate. It handles nullification of delay
5192 slots, varying length branches, negated branches and all combinations
5193 of the above. it returns the appropriate output template to emit the
5197 output_bvb (operands, nullify, length, negated, insn, which)
5198 rtx *operands ATTRIBUTE_UNUSED;
5199 int nullify, length, negated;
5203 static char buf[100];
5206 /* A conditional branch to the following instruction (eg the delay slot) is
5207 asking for a disaster. I do not think this can happen as this pattern
5208 is only used when optimizing; jump optimization should eliminate the
5209 jump. But be prepared just in case. */
5211 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5214 /* If this is a long branch with its delay slot unfilled, set `nullify'
5215 as it can nullify the delay slot and save a nop. */
5216 if (length == 8 && dbr_sequence_length () == 0)
5219 /* If this is a short forward conditional branch which did not get
5220 its delay slot filled, the delay slot can still be nullified. */
5221 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5222 nullify = forward_branch_p (insn);
5224 /* A forward branch over a single nullified insn can be done with a
5225 extrs instruction. This avoids a single cycle penalty due to
5226 mis-predicted branch if we fall through (branch not taken). */
5229 && next_real_insn (insn) != 0
5230 && get_attr_length (next_real_insn (insn)) == 4
5231 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5238 /* All short conditional branches except backwards with an unfilled
5242 strcpy (buf, "{vextrs,|extrw,s,}");
5244 strcpy (buf, "{bvb,|bb,}");
5245 if (useskip && GET_MODE (operands[0]) == DImode)
5246 strcpy (buf, "extrd,s,*}");
5247 else if (GET_MODE (operands[0]) == DImode)
5248 strcpy (buf, "bb,*");
5249 if ((which == 0 && negated)
5250 || (which == 1 && ! negated))
5255 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5256 else if (nullify && negated)
5257 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5258 else if (nullify && ! negated)
5259 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5260 else if (! nullify && negated)
5261 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5262 else if (! nullify && ! negated)
5263 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5266 /* All long conditionals. Note an short backward branch with an
5267 unfilled delay slot is treated just like a long backward branch
5268 with an unfilled delay slot. */
5270 /* Handle weird backwards branch with a filled delay slot
5271 with is nullified. */
5272 if (dbr_sequence_length () != 0
5273 && ! forward_branch_p (insn)
5276 strcpy (buf, "{bvb,|bb,}");
5277 if (GET_MODE (operands[0]) == DImode)
5279 if ((which == 0 && negated)
5280 || (which == 1 && ! negated))
5285 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5287 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5289 /* Handle short backwards branch with an unfilled delay slot.
5290 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5291 taken and untaken branches. */
5292 else if (dbr_sequence_length () == 0
5293 && ! forward_branch_p (insn)
5294 && INSN_ADDRESSES_SET_P ()
5295 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5296 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5298 strcpy (buf, "{bvb,|bb,}");
5299 if (GET_MODE (operands[0]) == DImode)
5301 if ((which == 0 && negated)
5302 || (which == 1 && ! negated))
5307 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5309 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5313 strcpy (buf, "{vextrs,|extrw,s,}");
5314 if (GET_MODE (operands[0]) == DImode)
5315 strcpy (buf, "extrd,s,*");
5316 if ((which == 0 && negated)
5317 || (which == 1 && ! negated))
5321 if (nullify && negated)
5322 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5323 else if (nullify && ! negated)
5324 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5326 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5328 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5338 /* Return the output template for emitting a dbra type insn.
5340 Note it may perform some output operations on its own before
5341 returning the final output string. */
5343 output_dbra (operands, insn, which_alternative)
5346 int which_alternative;
5349 /* A conditional branch to the following instruction (eg the delay slot) is
5350 asking for a disaster. Be prepared! */
5352 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5354 if (which_alternative == 0)
5355 return "ldo %1(%0),%0";
5356 else if (which_alternative == 1)
5358 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)",operands);
5359 output_asm_insn ("ldw -16(%%r30),%4",operands);
5360 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5361 return "{fldws|fldw} -16(%%r30),%0";
5365 output_asm_insn ("ldw %0,%4", operands);
5366 return "ldo %1(%4),%4\n\tstw %4,%0";
5370 if (which_alternative == 0)
5372 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5373 int length = get_attr_length (insn);
5375 /* If this is a long branch with its delay slot unfilled, set `nullify'
5376 as it can nullify the delay slot and save a nop. */
5377 if (length == 8 && dbr_sequence_length () == 0)
5380 /* If this is a short forward conditional branch which did not get
5381 its delay slot filled, the delay slot can still be nullified. */
5382 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5383 nullify = forward_branch_p (insn);
5385 /* Handle short versions first. */
5386 if (length == 4 && nullify)
5387 return "addib,%C2,n %1,%0,%3";
5388 else if (length == 4 && ! nullify)
5389 return "addib,%C2 %1,%0,%3";
5390 else if (length == 8)
5392 /* Handle weird backwards branch with a fulled delay slot
5393 which is nullified. */
5394 if (dbr_sequence_length () != 0
5395 && ! forward_branch_p (insn)
5397 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5398 /* Handle short backwards branch with an unfilled delay slot.
5399 Using a addb;nop rather than addi;bl saves 1 cycle for both
5400 taken and untaken branches. */
5401 else if (dbr_sequence_length () == 0
5402 && ! forward_branch_p (insn)
5403 && INSN_ADDRESSES_SET_P ()
5404 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5405 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5406 return "addib,%C2 %1,%0,%3%#";
5408 /* Handle normal cases. */
5410 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5412 return "addi,%N2 %1,%0,%0\n\tb %3";
5417 /* Deal with gross reload from FP register case. */
5418 else if (which_alternative == 1)
5420 /* Move loop counter from FP register to MEM then into a GR,
5421 increment the GR, store the GR into MEM, and finally reload
5422 the FP register from MEM from within the branch's delay slot. */
5423 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands);
5424 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5425 if (get_attr_length (insn) == 24)
5426 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5428 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5430 /* Deal with gross reload from memory case. */
5433 /* Reload loop counter from memory, the store back to memory
5434 happens in the branch's delay slot. */
5435 output_asm_insn ("ldw %0,%4", operands);
5436 if (get_attr_length (insn) == 12)
5437 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5439 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5443 /* Return the output template for emitting a dbra type insn.
5445 Note it may perform some output operations on its own before
5446 returning the final output string. */
5448 output_movb (operands, insn, which_alternative, reverse_comparison)
5451 int which_alternative;
5452 int reverse_comparison;
5455 /* A conditional branch to the following instruction (eg the delay slot) is
5456 asking for a disaster. Be prepared! */
5458 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5460 if (which_alternative == 0)
5461 return "copy %1,%0";
5462 else if (which_alternative == 1)
5464 output_asm_insn ("stw %1,-16(%%r30)",operands);
5465 return "{fldws|fldw} -16(%%r30),%0";
5467 else if (which_alternative == 2)
5473 /* Support the second variant. */
5474 if (reverse_comparison)
5475 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5477 if (which_alternative == 0)
5479 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5480 int length = get_attr_length (insn);
5482 /* If this is a long branch with its delay slot unfilled, set `nullify'
5483 as it can nullify the delay slot and save a nop. */
5484 if (length == 8 && dbr_sequence_length () == 0)
5487 /* If this is a short forward conditional branch which did not get
5488 its delay slot filled, the delay slot can still be nullified. */
5489 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5490 nullify = forward_branch_p (insn);
5492 /* Handle short versions first. */
5493 if (length == 4 && nullify)
5494 return "movb,%C2,n %1,%0,%3";
5495 else if (length == 4 && ! nullify)
5496 return "movb,%C2 %1,%0,%3";
5497 else if (length == 8)
5499 /* Handle weird backwards branch with a filled delay slot
5500 which is nullified. */
5501 if (dbr_sequence_length () != 0
5502 && ! forward_branch_p (insn)
5504 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5506 /* Handle short backwards branch with an unfilled delay slot.
5507 Using a movb;nop rather than or;bl saves 1 cycle for both
5508 taken and untaken branches. */
5509 else if (dbr_sequence_length () == 0
5510 && ! forward_branch_p (insn)
5511 && INSN_ADDRESSES_SET_P ()
5512 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5513 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5514 return "movb,%C2 %1,%0,%3%#";
5515 /* Handle normal cases. */
5517 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5519 return "or,%N2 %1,%%r0,%0\n\tb %3";
5524 /* Deal with gross reload from FP register case. */
5525 else if (which_alternative == 1)
5527 /* Move loop counter from FP register to MEM then into a GR,
5528 increment the GR, store the GR into MEM, and finally reload
5529 the FP register from MEM from within the branch's delay slot. */
5530 output_asm_insn ("stw %1,-16(%%r30)",operands);
5531 if (get_attr_length (insn) == 12)
5532 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
5534 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5536 /* Deal with gross reload from memory case. */
5537 else if (which_alternative == 2)
5539 /* Reload loop counter from memory, the store back to memory
5540 happens in the branch's delay slot. */
5541 if (get_attr_length (insn) == 8)
5542 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
5544 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5546 /* Handle SAR as a destination. */
5549 if (get_attr_length (insn) == 8)
5550 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
5552 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5557 /* INSN is a millicode call. It may have an unconditional jump in its delay
5560 CALL_DEST is the routine we are calling. */
5563 output_millicode_call (insn, call_dest)
5571 xoperands[3] = gen_rtx_REG (SImode, 31);
5573 xoperands[3] = gen_rtx_REG (SImode, 2);
5575 /* Handle common case -- empty delay slot or no jump in the delay slot,
5576 and we're sure that the branch will reach the beginning of the $CODE$
5578 if ((dbr_sequence_length () == 0
5579 && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
5580 || (dbr_sequence_length () != 0
5581 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5582 && get_attr_length (insn) == 4))
5584 xoperands[0] = call_dest;
5585 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
5589 /* This call may not reach the beginning of the $CODE$ subspace. */
5590 if (get_attr_length (insn) > 4)
5592 int delay_insn_deleted = 0;
5594 /* We need to emit an inline long-call branch. */
5595 if (dbr_sequence_length () != 0
5596 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5598 /* A non-jump insn in the delay slot. By definition we can
5599 emit this insn before the call. */
5600 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5602 /* Now delete the delay insn. */
5603 PUT_CODE (NEXT_INSN (insn), NOTE);
5604 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5605 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5606 delay_insn_deleted = 1;
5609 /* If we're allowed to use be/ble instructions, then this is the
5610 best sequence to use for a long millicode call. */
5611 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS
5612 || ! (flag_pic || TARGET_PORTABLE_RUNTIME))
5614 xoperands[0] = call_dest;
5615 output_asm_insn ("ldil L%%%0,%3", xoperands);
5616 output_asm_insn ("{ble|be,l} R%%%0(%%sr4,%3)", xoperands);
5617 output_asm_insn ("nop", xoperands);
5619 /* Pure portable runtime doesn't allow be/ble; we also don't have
5620 PIC support int he assembler/linker, so this sequence is needed. */
5621 else if (TARGET_PORTABLE_RUNTIME)
5623 xoperands[0] = call_dest;
5624 /* Get the address of our target into %r29. */
5625 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
5626 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
5628 /* Get our return address into %r31. */
5629 output_asm_insn ("blr %%r0,%3", xoperands);
5631 /* Jump to our target address in %r29. */
5632 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
5634 /* Empty delay slot. Note this insn gets fetched twice and
5635 executed once. To be safe we use a nop. */
5636 output_asm_insn ("nop", xoperands);
5639 /* PIC long millicode call sequence. */
5642 xoperands[0] = call_dest;
5643 xoperands[1] = gen_label_rtx ();
5644 /* Get our address + 8 into %r1. */
5645 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5647 /* Add %r1 to the offset of our target from the next insn. */
5648 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
5649 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5650 CODE_LABEL_NUMBER (xoperands[1]));
5651 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
5653 /* Get the return address into %r31. */
5654 output_asm_insn ("blr 0,%3", xoperands);
5656 /* Branch to our target which is in %r1. */
5657 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
5659 /* Empty delay slot. Note this insn gets fetched twice and
5660 executed once. To be safe we use a nop. */
5661 output_asm_insn ("nop", xoperands);
5664 /* If we had a jump in the call's delay slot, output it now. */
5665 if (dbr_sequence_length () != 0
5666 && !delay_insn_deleted)
5668 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5669 output_asm_insn ("b,n %0", xoperands);
5671 /* Now delete the delay insn. */
5672 PUT_CODE (NEXT_INSN (insn), NOTE);
5673 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5674 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5679 /* This call has an unconditional jump in its delay slot and the
5680 call is known to reach its target or the beginning of the current
5683 /* Use the containing sequence insn's address. */
5684 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5686 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
5687 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
5689 /* If the branch was too far away, emit a normal call followed
5690 by a nop, followed by the unconditional branch.
5692 If the branch is close, then adjust %r2 from within the
5693 call's delay slot. */
5695 xoperands[0] = call_dest;
5696 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5697 if (! VAL_14_BITS_P (distance))
5698 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
5701 xoperands[2] = gen_label_rtx ();
5702 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
5704 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5705 CODE_LABEL_NUMBER (xoperands[2]));
5708 /* Delete the jump. */
5709 PUT_CODE (NEXT_INSN (insn), NOTE);
5710 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5711 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5715 extern struct obstack permanent_obstack;
5717 /* INSN is either a function call. It may have an unconditional jump
5720 CALL_DEST is the routine we are calling. */
5723 output_call (insn, call_dest, sibcall)
5732 /* Handle common case -- empty delay slot or no jump in the delay slot,
5733 and we're sure that the branch will reach the beginning of the $CODE$
5735 if ((dbr_sequence_length () == 0
5736 && get_attr_length (insn) == 8)
5737 || (dbr_sequence_length () != 0
5738 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5739 && get_attr_length (insn) == 4))
5741 xoperands[0] = call_dest;
5742 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
5743 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
5747 /* This call may not reach the beginning of the $CODE$ subspace. */
5748 if (get_attr_length (insn) > 8)
5750 int delay_insn_deleted = 0;
5754 /* We need to emit an inline long-call branch. Furthermore,
5755 because we're changing a named function call into an indirect
5756 function call well after the parameters have been set up, we
5757 need to make sure any FP args appear in both the integer
5758 and FP registers. Also, we need move any delay slot insn
5759 out of the delay slot. And finally, we can't rely on the linker
5760 being able to fix the call to $$dyncall! -- Yuk!. */
5761 if (dbr_sequence_length () != 0
5762 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5764 /* A non-jump insn in the delay slot. By definition we can
5765 emit this insn before the call (and in fact before argument
5767 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5769 /* Now delete the delay insn. */
5770 PUT_CODE (NEXT_INSN (insn), NOTE);
5771 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5772 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5773 delay_insn_deleted = 1;
5776 /* Now copy any FP arguments into integer registers. */
5777 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
5779 int arg_mode, regno;
5780 rtx use = XEXP (link, 0);
5781 if (! (GET_CODE (use) == USE
5782 && GET_CODE (XEXP (use, 0)) == REG
5783 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5786 arg_mode = GET_MODE (XEXP (use, 0));
5787 regno = REGNO (XEXP (use, 0));
5788 /* Is it a floating point register? */
5789 if (regno >= 32 && regno <= 39)
5791 /* Copy from the FP register into an integer register
5793 if (arg_mode == SFmode)
5795 xoperands[0] = XEXP (use, 0);
5796 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
5797 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
5799 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5803 xoperands[0] = XEXP (use, 0);
5804 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
5805 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
5807 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
5808 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5813 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5814 we don't have any direct calls in that case. */
5817 const char *name = XSTR (call_dest, 0);
5819 /* See if we have already put this function on the list
5820 of deferred plabels. This list is generally small,
5821 so a liner search is not too ugly. If it proves too
5822 slow replace it with something faster. */
5823 for (i = 0; i < n_deferred_plabels; i++)
5824 if (strcmp (name, deferred_plabels[i].name) == 0)
5827 /* If the deferred plabel list is empty, or this entry was
5828 not found on the list, create a new entry on the list. */
5829 if (deferred_plabels == NULL || i == n_deferred_plabels)
5831 const char *real_name;
5833 if (deferred_plabels == 0)
5834 deferred_plabels = (struct deferred_plabel *)
5835 xmalloc (1 * sizeof (struct deferred_plabel));
5837 deferred_plabels = (struct deferred_plabel *)
5838 xrealloc (deferred_plabels,
5839 ((n_deferred_plabels + 1)
5840 * sizeof (struct deferred_plabel)));
5842 i = n_deferred_plabels++;
5843 deferred_plabels[i].internal_label = gen_label_rtx ();
5844 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
5846 strcpy (deferred_plabels[i].name, name);
5848 /* Gross. We have just implicitly taken the address of this
5849 function, mark it as such. */
5850 STRIP_NAME_ENCODING (real_name, name);
5851 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5854 /* We have to load the address of the function using a procedure
5855 label (plabel). Inline plabels can lose for PIC and other
5856 cases, so avoid them by creating a 32bit plabel in the data
5860 xoperands[0] = deferred_plabels[i].internal_label;
5861 xoperands[1] = gen_label_rtx ();
5863 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
5864 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
5865 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
5867 /* Get our address + 8 into %r1. */
5868 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5870 /* Add %r1 to the offset of dyncall from the next insn. */
5871 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
5872 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5873 CODE_LABEL_NUMBER (xoperands[1]));
5874 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
5876 /* Get the return address into %r31. */
5877 output_asm_insn ("blr %%r0,%%r31", xoperands);
5879 /* Branch to our target which is in %r1. */
5880 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5884 /* This call never returns, so we do not need to fix the
5886 output_asm_insn ("nop", xoperands);
5890 /* Copy the return address into %r2 also. */
5891 output_asm_insn ("copy %%r31,%%r2", xoperands);
5896 xoperands[0] = deferred_plabels[i].internal_label;
5898 /* Get the address of our target into %r22. */
5899 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
5900 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
5902 /* Get the high part of the address of $dyncall into %r2, then
5903 add in the low part in the branch instruction. */
5904 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
5905 output_asm_insn ("{ble|be,l} R%%$$dyncall(%%sr4,%%r2)",
5910 /* This call never returns, so we do not need to fix the
5912 output_asm_insn ("nop", xoperands);
5916 /* Copy the return address into %r2 also. */
5917 output_asm_insn ("copy %%r31,%%r2", xoperands);
5922 /* If we had a jump in the call's delay slot, output it now. */
5923 if (dbr_sequence_length () != 0
5924 && !delay_insn_deleted)
5926 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5927 output_asm_insn ("b,n %0", xoperands);
5929 /* Now delete the delay insn. */
5930 PUT_CODE (NEXT_INSN (insn), NOTE);
5931 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5932 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5937 /* This call has an unconditional jump in its delay slot and the
5938 call is known to reach its target or the beginning of the current
5941 /* Use the containing sequence insn's address. */
5942 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5944 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
5945 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
5947 /* If the branch was too far away, emit a normal call followed
5948 by a nop, followed by the unconditional branch.
5950 If the branch is close, then adjust %r2 from within the
5951 call's delay slot. */
5953 xoperands[0] = call_dest;
5954 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5955 if (! VAL_14_BITS_P (distance))
5956 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
5959 xoperands[3] = gen_label_rtx ();
5960 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
5962 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5963 CODE_LABEL_NUMBER (xoperands[3]));
5966 /* Delete the jump. */
5967 PUT_CODE (NEXT_INSN (insn), NOTE);
5968 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5969 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5973 /* In HPUX 8.0's shared library scheme, special relocations are needed
5974 for function labels if they might be passed to a function
5975 in a shared library (because shared libraries don't live in code
5976 space), and special magic is needed to construct their address. */
5979 hppa_encode_label (sym)
5982 const char *str = XSTR (sym, 0);
5983 int len = strlen (str) + 1;
5986 p = newstr = alloca (len + 1);
5995 XSTR (sym,0) = ggc_alloc_string (newstr, len);
5999 function_label_operand (op, mode)
6001 enum machine_mode mode ATTRIBUTE_UNUSED;
6003 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6006 /* Returns 1 if OP is a function label involved in a simple addition
6007 with a constant. Used to keep certain patterns from matching
6008 during instruction combination. */
6010 is_function_label_plus_const (op)
6013 /* Strip off any CONST. */
6014 if (GET_CODE (op) == CONST)
6017 return (GET_CODE (op) == PLUS
6018 && function_label_operand (XEXP (op, 0), Pmode)
6019 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6022 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6023 use in fmpyadd instructions. */
6025 fmpyaddoperands (operands)
6028 enum machine_mode mode = GET_MODE (operands[0]);
6030 /* Must be a floating point mode. */
6031 if (mode != SFmode && mode != DFmode)
6034 /* All modes must be the same. */
6035 if (! (mode == GET_MODE (operands[1])
6036 && mode == GET_MODE (operands[2])
6037 && mode == GET_MODE (operands[3])
6038 && mode == GET_MODE (operands[4])
6039 && mode == GET_MODE (operands[5])))
6042 /* All operands must be registers. */
6043 if (! (GET_CODE (operands[1]) == REG
6044 && GET_CODE (operands[2]) == REG
6045 && GET_CODE (operands[3]) == REG
6046 && GET_CODE (operands[4]) == REG
6047 && GET_CODE (operands[5]) == REG))
6050 /* Only 2 real operands to the addition. One of the input operands must
6051 be the same as the output operand. */
6052 if (! rtx_equal_p (operands[3], operands[4])
6053 && ! rtx_equal_p (operands[3], operands[5]))
6056 /* Inout operand of add can not conflict with any operands from multiply. */
6057 if (rtx_equal_p (operands[3], operands[0])
6058 || rtx_equal_p (operands[3], operands[1])
6059 || rtx_equal_p (operands[3], operands[2]))
6062 /* multiply can not feed into addition operands. */
6063 if (rtx_equal_p (operands[4], operands[0])
6064 || rtx_equal_p (operands[5], operands[0]))
6067 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6069 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6070 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6071 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6072 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6073 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6074 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6077 /* Passed. Operands are suitable for fmpyadd. */
6081 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6082 use in fmpysub instructions. */
6084 fmpysuboperands (operands)
6087 enum machine_mode mode = GET_MODE (operands[0]);
6089 /* Must be a floating point mode. */
6090 if (mode != SFmode && mode != DFmode)
6093 /* All modes must be the same. */
6094 if (! (mode == GET_MODE (operands[1])
6095 && mode == GET_MODE (operands[2])
6096 && mode == GET_MODE (operands[3])
6097 && mode == GET_MODE (operands[4])
6098 && mode == GET_MODE (operands[5])))
6101 /* All operands must be registers. */
6102 if (! (GET_CODE (operands[1]) == REG
6103 && GET_CODE (operands[2]) == REG
6104 && GET_CODE (operands[3]) == REG
6105 && GET_CODE (operands[4]) == REG
6106 && GET_CODE (operands[5]) == REG))
6109 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6110 operation, so operands[4] must be the same as operand[3]. */
6111 if (! rtx_equal_p (operands[3], operands[4]))
6114 /* multiply can not feed into subtraction. */
6115 if (rtx_equal_p (operands[5], operands[0]))
6118 /* Inout operand of sub can not conflict with any operands from multiply. */
6119 if (rtx_equal_p (operands[3], operands[0])
6120 || rtx_equal_p (operands[3], operands[1])
6121 || rtx_equal_p (operands[3], operands[2]))
6124 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6126 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6127 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6128 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6129 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6130 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6131 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6134 /* Passed. Operands are suitable for fmpysub. */
6139 plus_xor_ior_operator (op, mode)
6141 enum machine_mode mode ATTRIBUTE_UNUSED;
6143 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6144 || GET_CODE (op) == IOR);
6147 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6148 constants for shadd instructions. */
6150 shadd_constant_p (val)
6153 if (val == 2 || val == 4 || val == 8)
6159 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6160 the valid constant for shadd instructions. */
6162 shadd_operand (op, mode)
6164 enum machine_mode mode ATTRIBUTE_UNUSED;
6166 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6169 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6172 basereg_operand (op, mode)
6174 enum machine_mode mode;
6176 /* cse will create some unscaled indexed addresses, however; it
6177 generally isn't a win on the PA, so avoid creating unscaled
6178 indexed addresses until after cse is finished. */
6179 if (!cse_not_expected)
6182 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6183 we don't have to worry about the braindamaged implicit space
6184 register selection from the basereg. */
6185 if (TARGET_NO_SPACE_REGS)
6186 return (GET_CODE (op) == REG);
6188 /* While it's always safe to index off the frame pointer, it's not
6189 always profitable, particularly when the frame pointer is being
6191 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6194 return (GET_CODE (op) == REG
6196 && register_operand (op, mode));
6199 /* Return 1 if this operand is anything other than a hard register. */
6202 non_hard_reg_operand (op, mode)
6204 enum machine_mode mode ATTRIBUTE_UNUSED;
6206 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6209 /* Return 1 if INSN branches forward. Should be using insn_addresses
6210 to avoid walking through all the insns... */
6212 forward_branch_p (insn)
6215 rtx label = JUMP_LABEL (insn);
6222 insn = NEXT_INSN (insn);
6225 return (insn == label);
6228 /* Return 1 if OP is an equality comparison, else return 0. */
6230 eq_neq_comparison_operator (op, mode)
6232 enum machine_mode mode ATTRIBUTE_UNUSED;
6234 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6237 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6239 movb_comparison_operator (op, mode)
6241 enum machine_mode mode ATTRIBUTE_UNUSED;
6243 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6244 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6247 /* Return 1 if INSN is in the delay slot of a call instruction. */
6249 jump_in_call_delay (insn)
6253 if (GET_CODE (insn) != JUMP_INSN)
6256 if (PREV_INSN (insn)
6257 && PREV_INSN (PREV_INSN (insn))
6258 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6260 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6262 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6263 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6270 /* Output an unconditional move and branch insn. */
6273 output_parallel_movb (operands, length)
6277 /* These are the cases in which we win. */
6279 return "mov%I1b,tr %1,%0,%2";
6281 /* None of these cases wins, but they don't lose either. */
6282 if (dbr_sequence_length () == 0)
6284 /* Nothing in the delay slot, fake it by putting the combined
6285 insn (the copy or add) in the delay slot of a bl. */
6286 if (GET_CODE (operands[1]) == CONST_INT)
6287 return "b %2\n\tldi %1,%0";
6289 return "b %2\n\tcopy %1,%0";
6293 /* Something in the delay slot, but we've got a long branch. */
6294 if (GET_CODE (operands[1]) == CONST_INT)
6295 return "ldi %1,%0\n\tb %2";
6297 return "copy %1,%0\n\tb %2";
6301 /* Output an unconditional add and branch insn. */
6304 output_parallel_addb (operands, length)
6308 /* To make life easy we want operand0 to be the shared input/output
6309 operand and operand1 to be the readonly operand. */
6310 if (operands[0] == operands[1])
6311 operands[1] = operands[2];
6313 /* These are the cases in which we win. */
6315 return "add%I1b,tr %1,%0,%3";
6317 /* None of these cases win, but they don't lose either. */
6318 if (dbr_sequence_length () == 0)
6320 /* Nothing in the delay slot, fake it by putting the combined
6321 insn (the copy or add) in the delay slot of a bl. */
6322 return "b %3\n\tadd%I1 %1,%0,%0";
6326 /* Something in the delay slot, but we've got a long branch. */
6327 return "add%I1 %1,%0,%0\n\tb %3";
6331 /* Return nonzero if INSN (a jump insn) immediately follows a call to
6332 a named function. This is used to discourage creating parallel movb/addb
6333 insns since a jump which immediately follows a call can execute in the
6334 delay slot of the call.
6336 It is also used to avoid filling the delay slot of a jump which
6337 immediately follows a call since the jump can usually be eliminated
6338 completely by modifying RP in the delay slot of the call. */
6341 following_call (insn)
6344 /* We do not parallel movb,addb or place jumps into call delay slots when
6345 optimizing for the PA8000. */
6346 if (pa_cpu != PROCESSOR_8000)
6349 /* Find the previous real insn, skipping NOTEs. */
6350 insn = PREV_INSN (insn);
6351 while (insn && GET_CODE (insn) == NOTE)
6352 insn = PREV_INSN (insn);
6354 /* Check for CALL_INSNs and millicode calls. */
6356 && ((GET_CODE (insn) == CALL_INSN
6357 && get_attr_type (insn) != TYPE_DYNCALL)
6358 || (GET_CODE (insn) == INSN
6359 && GET_CODE (PATTERN (insn)) != SEQUENCE
6360 && GET_CODE (PATTERN (insn)) != USE
6361 && GET_CODE (PATTERN (insn)) != CLOBBER
6362 && get_attr_type (insn) == TYPE_MILLI)))
6368 /* We use this hook to perform a PA specific optimization which is difficult
6369 to do in earlier passes.
6371 We want the delay slots of branches within jump tables to be filled.
6372 None of the compiler passes at the moment even has the notion that a
6373 PA jump table doesn't contain addresses, but instead contains actual
6376 Because we actually jump into the table, the addresses of each entry
6377 must stay constant in relation to the beginning of the table (which
6378 itself must stay constant relative to the instruction to jump into
6379 it). I don't believe we can guarantee earlier passes of the compiler
6380 will adhere to those rules.
6382 So, late in the compilation process we find all the jump tables, and
6383 expand them into real code -- eg each entry in the jump table vector
6384 will get an appropriate label followed by a jump to the final target.
6386 Reorg and the final jump pass can then optimize these branches and
6387 fill their delay slots. We end up with smaller, more efficient code.
6389 The jump instructions within the table are special; we must be able
6390 to identify them during assembly output (if the jumps don't get filled
6391 we need to emit a nop rather than nullifying the delay slot)). We
6392 identify jumps in switch tables by marking the SET with DImode.
6394 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6395 insns. This serves two purposes, first it prevents jump.c from
6396 noticing that the last N entries in the table jump to the instruction
6397 immediately after the table and deleting the jumps. Second, those
6398 insns mark where we should emit .begin_brtab and .end_brtab directives
6399 when using GAS (allows for better link time optimizations). */
6407 remove_useless_addtr_insns (insns, 1);
6409 if (pa_cpu < PROCESSOR_8000)
6410 pa_combine_instructions (get_insns ());
6413 /* This is fairly cheap, so always run it if optimizing. */
6414 if (optimize > 0 && !TARGET_BIG_SWITCH)
6416 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6417 insns = get_insns ();
6418 for (insn = insns; insn; insn = NEXT_INSN (insn))
6420 rtx pattern, tmp, location;
6421 unsigned int length, i;
6423 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6424 if (GET_CODE (insn) != JUMP_INSN
6425 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6426 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6429 /* Emit marker for the beginning of the branch table. */
6430 emit_insn_before (gen_begin_brtab (), insn);
6432 pattern = PATTERN (insn);
6433 location = PREV_INSN (insn);
6434 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6436 for (i = 0; i < length; i++)
6438 /* Emit a label before each jump to keep jump.c from
6439 removing this code. */
6440 tmp = gen_label_rtx ();
6441 LABEL_NUSES (tmp) = 1;
6442 emit_label_after (tmp, location);
6443 location = NEXT_INSN (location);
6445 if (GET_CODE (pattern) == ADDR_VEC)
6447 /* Emit the jump itself. */
6448 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
6449 tmp = emit_jump_insn_after (tmp, location);
6450 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
6451 /* It is easy to rely on the branch table markers
6452 during assembly output to trigger the correct code
6453 for a switch table jump with an unfilled delay slot,
6455 However, that requires state and assumes that we look
6458 We can't make such assumptions when computing the length
6459 of instructions. Ugh. We could walk the insn chain to
6460 determine if this instruction is in a branch table, but
6461 that can get rather expensive, particularly during the
6462 branch shortening phase of the compiler.
6464 So instead we mark this jump as being special. This is
6465 far from ideal and knows that no code after this will
6466 muck around with the mode of the JUMP_INSN itself. */
6467 PUT_MODE (tmp, SImode);
6468 LABEL_NUSES (JUMP_LABEL (tmp))++;
6469 location = NEXT_INSN (location);
6473 /* Emit the jump itself. */
6474 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
6475 tmp = emit_jump_insn_after (tmp, location);
6476 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
6477 /* It is easy to rely on the branch table markers
6478 during assembly output to trigger the correct code
6479 for a switch table jump with an unfilled delay slot,
6481 However, that requires state and assumes that we look
6484 We can't make such assumptions when computing the length
6485 of instructions. Ugh. We could walk the insn chain to
6486 determine if this instruction is in a branch table, but
6487 that can get rather expensive, particularly during the
6488 branch shortening phase of the compiler.
6490 So instead we mark this jump as being special. This is
6491 far from ideal and knows that no code after this will
6492 muck around with the mode of the JUMP_INSN itself. */
6493 PUT_MODE (tmp, SImode);
6494 LABEL_NUSES (JUMP_LABEL (tmp))++;
6495 location = NEXT_INSN (location);
6498 /* Emit a BARRIER after the jump. */
6499 emit_barrier_after (location);
6500 location = NEXT_INSN (location);
6503 /* Emit marker for the end of the branch table. */
6504 emit_insn_before (gen_end_brtab (), location);
6505 location = NEXT_INSN (location);
6506 emit_barrier_after (location);
6508 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6514 /* Sill need an end_brtab insn. */
6515 insns = get_insns ();
6516 for (insn = insns; insn; insn = NEXT_INSN (insn))
6518 /* Find an ADDR_VEC insn. */
6519 if (GET_CODE (insn) != JUMP_INSN
6520 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6521 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6524 /* Now generate markers for the beginning and end of the
6526 emit_insn_before (gen_begin_brtab (), insn);
6527 emit_insn_after (gen_end_brtab (), insn);
6532 /* The PA has a number of odd instructions which can perform multiple
6533 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6534 it may be profitable to combine two instructions into one instruction
6535 with two outputs. It's not profitable PA2.0 machines because the
6536 two outputs would take two slots in the reorder buffers.
6538 This routine finds instructions which can be combined and combines
6539 them. We only support some of the potential combinations, and we
6540 only try common ways to find suitable instructions.
6542 * addb can add two registers or a register and a small integer
6543 and jump to a nearby (+-8k) location. Normally the jump to the
6544 nearby location is conditional on the result of the add, but by
6545 using the "true" condition we can make the jump unconditional.
6546 Thus addb can perform two independent operations in one insn.
6548 * movb is similar to addb in that it can perform a reg->reg
6549 or small immediate->reg copy and jump to a nearby (+-8k location).
6551 * fmpyadd and fmpysub can perform a FP multiply and either an
6552 FP add or FP sub if the operands of the multiply and add/sub are
6553 independent (there are other minor restrictions). Note both
6554 the fmpy and fadd/fsub can in theory move to better spots according
6555 to data dependencies, but for now we require the fmpy stay at a
6558 * Many of the memory operations can perform pre & post updates
6559 of index registers. GCC's pre/post increment/decrement addressing
6560 is far too simple to take advantage of all the possibilities. This
6561 pass may not be suitable since those insns may not be independent.
6563 * comclr can compare two ints or an int and a register, nullify
6564 the following instruction and zero some other register. This
6565 is more difficult to use as it's harder to find an insn which
6566 will generate a comclr than finding something like an unconditional
6567 branch. (conditional moves & long branches create comclr insns).
6569 * Most arithmetic operations can conditionally skip the next
6570 instruction. They can be viewed as "perform this operation
6571 and conditionally jump to this nearby location" (where nearby
6572 is an insns away). These are difficult to use due to the
6573 branch length restrictions. */
6576 pa_combine_instructions (insns)
6577 rtx insns ATTRIBUTE_UNUSED;
6581 /* This can get expensive since the basic algorithm is on the
6582 order of O(n^2) (or worse). Only do it for -O2 or higher
6583 levels of optimization. */
6587 /* Walk down the list of insns looking for "anchor" insns which
6588 may be combined with "floating" insns. As the name implies,
6589 "anchor" instructions don't move, while "floating" insns may
6591 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
6592 new = make_insn_raw (new);
6594 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
6596 enum attr_pa_combine_type anchor_attr;
6597 enum attr_pa_combine_type floater_attr;
6599 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6600 Also ignore any special USE insns. */
6601 if ((GET_CODE (anchor) != INSN
6602 && GET_CODE (anchor) != JUMP_INSN
6603 && GET_CODE (anchor) != CALL_INSN)
6604 || GET_CODE (PATTERN (anchor)) == USE
6605 || GET_CODE (PATTERN (anchor)) == CLOBBER
6606 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
6607 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
6610 anchor_attr = get_attr_pa_combine_type (anchor);
6611 /* See if anchor is an insn suitable for combination. */
6612 if (anchor_attr == PA_COMBINE_TYPE_FMPY
6613 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
6614 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6615 && ! forward_branch_p (anchor)))
6619 for (floater = PREV_INSN (anchor);
6621 floater = PREV_INSN (floater))
6623 if (GET_CODE (floater) == NOTE
6624 || (GET_CODE (floater) == INSN
6625 && (GET_CODE (PATTERN (floater)) == USE
6626 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6629 /* Anything except a regular INSN will stop our search. */
6630 if (GET_CODE (floater) != INSN
6631 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6632 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6638 /* See if FLOATER is suitable for combination with the
6640 floater_attr = get_attr_pa_combine_type (floater);
6641 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6642 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6643 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6644 && floater_attr == PA_COMBINE_TYPE_FMPY))
6646 /* If ANCHOR and FLOATER can be combined, then we're
6647 done with this pass. */
6648 if (pa_can_combine_p (new, anchor, floater, 0,
6649 SET_DEST (PATTERN (floater)),
6650 XEXP (SET_SRC (PATTERN (floater)), 0),
6651 XEXP (SET_SRC (PATTERN (floater)), 1)))
6655 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6656 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
6658 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
6660 if (pa_can_combine_p (new, anchor, floater, 0,
6661 SET_DEST (PATTERN (floater)),
6662 XEXP (SET_SRC (PATTERN (floater)), 0),
6663 XEXP (SET_SRC (PATTERN (floater)), 1)))
6668 if (pa_can_combine_p (new, anchor, floater, 0,
6669 SET_DEST (PATTERN (floater)),
6670 SET_SRC (PATTERN (floater)),
6671 SET_SRC (PATTERN (floater))))
6677 /* If we didn't find anything on the backwards scan try forwards. */
6679 && (anchor_attr == PA_COMBINE_TYPE_FMPY
6680 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
6682 for (floater = anchor; floater; floater = NEXT_INSN (floater))
6684 if (GET_CODE (floater) == NOTE
6685 || (GET_CODE (floater) == INSN
6686 && (GET_CODE (PATTERN (floater)) == USE
6687 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6691 /* Anything except a regular INSN will stop our search. */
6692 if (GET_CODE (floater) != INSN
6693 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6694 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6700 /* See if FLOATER is suitable for combination with the
6702 floater_attr = get_attr_pa_combine_type (floater);
6703 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6704 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6705 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6706 && floater_attr == PA_COMBINE_TYPE_FMPY))
6708 /* If ANCHOR and FLOATER can be combined, then we're
6709 done with this pass. */
6710 if (pa_can_combine_p (new, anchor, floater, 1,
6711 SET_DEST (PATTERN (floater)),
6712 XEXP (SET_SRC (PATTERN(floater)),0),
6713 XEXP(SET_SRC(PATTERN(floater)),1)))
6719 /* FLOATER will be nonzero if we found a suitable floating
6720 insn for combination with ANCHOR. */
6722 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6723 || anchor_attr == PA_COMBINE_TYPE_FMPY))
6725 /* Emit the new instruction and delete the old anchor. */
6726 emit_insn_before (gen_rtx_PARALLEL
6728 gen_rtvec (2, PATTERN (anchor),
6729 PATTERN (floater))),
6732 PUT_CODE (anchor, NOTE);
6733 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6734 NOTE_SOURCE_FILE (anchor) = 0;
6736 /* Emit a special USE insn for FLOATER, then delete
6737 the floating insn. */
6738 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6739 delete_insn (floater);
6744 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
6747 /* Emit the new_jump instruction and delete the old anchor. */
6749 = emit_jump_insn_before (gen_rtx_PARALLEL
6751 gen_rtvec (2, PATTERN (anchor),
6752 PATTERN (floater))),
6755 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
6756 PUT_CODE (anchor, NOTE);
6757 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6758 NOTE_SOURCE_FILE (anchor) = 0;
6760 /* Emit a special USE insn for FLOATER, then delete
6761 the floating insn. */
6762 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6763 delete_insn (floater);
6771 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
6772 rtx new, anchor, floater;
6774 rtx dest, src1, src2;
6776 int insn_code_number;
6779 /* Create a PARALLEL with the patterns of ANCHOR and
6780 FLOATER, try to recognize it, then test constraints
6781 for the resulting pattern.
6783 If the pattern doesn't match or the constraints
6784 aren't met keep searching for a suitable floater
6786 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
6787 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
6788 INSN_CODE (new) = -1;
6789 insn_code_number = recog_memoized (new);
6790 if (insn_code_number < 0
6791 || !constrain_operands (1))
6805 /* There's up to three operands to consider. One
6806 output and two inputs.
6808 The output must not be used between FLOATER & ANCHOR
6809 exclusive. The inputs must not be set between
6810 FLOATER and ANCHOR exclusive. */
6812 if (reg_used_between_p (dest, start, end))
6815 if (reg_set_between_p (src1, start, end))
6818 if (reg_set_between_p (src2, start, end))
6821 /* If we get here, then everything is good. */
6825 /* Return nonzero if references for INSN are delayed.
6827 Millicode insns are actually function calls with some special
6828 constraints on arguments and register usage.
6830 Millicode calls always expect their arguments in the integer argument
6831 registers, and always return their result in %r29 (ret1). They
6832 are expected to clobber their arguments, %r1, %r29, and %r31 and
6835 By considering this effects delayed reorg reorg can put insns
6836 which set the argument registers into the delay slot of the millicode
6837 call -- thus they act more like traditional CALL_INSNs.
6839 get_attr_type will try to recognize the given insn, so make sure to
6840 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
6843 insn_refs_are_delayed (insn)
6846 return ((GET_CODE (insn) == INSN
6847 && GET_CODE (PATTERN (insn)) != SEQUENCE
6848 && GET_CODE (PATTERN (insn)) != USE
6849 && GET_CODE (PATTERN (insn)) != CLOBBER
6850 && get_attr_type (insn) == TYPE_MILLI));
6853 /* Return the location of a parameter that is passed in a register or NULL
6854 if the parameter has any component that is passed in memory.
6856 This is new code and will be pushed to into the net sources after
6859 ??? We might want to restructure this so that it looks more like other
6862 function_arg (cum, mode, type, named, incoming)
6863 CUMULATIVE_ARGS *cum;
6864 enum machine_mode mode;
6866 int named ATTRIBUTE_UNUSED;
6869 int max_arg_words = (TARGET_64BIT ? 8 : 4);
6876 /* If this arg would be passed partially or totally on the stack, then
6877 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
6878 handle arguments which are split between regs and stack slots if
6879 the ABI mandates split arguments. */
6880 if (cum->words + FUNCTION_ARG_SIZE (mode, type) > max_arg_words
6881 || mode == VOIDmode)
6887 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
6889 if (cum->words + offset >= max_arg_words
6890 || mode == VOIDmode)
6894 /* The 32bit ABIs and the 64bit ABIs are rather different,
6895 particularly in their handling of FP registers. We might
6896 be able to cleverly share code between them, but I'm not
6897 going to bother in the hope that splitting them up results
6898 in code that is more easily understood.
6900 The 64bit code probably is very wrong for structure passing. */
6903 /* Advance the base registers to their current locations.
6905 Remember, gprs grow towards smaller register numbers while
6906 fprs grow to higher register numbers. Also remember FP regs
6907 are always 4 bytes wide, while the size of an integer register
6908 varies based on the size of the target word. */
6909 gpr_reg_base = 26 - cum->words;
6910 fpr_reg_base = 32 + cum->words;
6912 /* If the argument is more than a word long, then we need to align
6913 the base registers. Same caveats as above. */
6914 if (FUNCTION_ARG_SIZE (mode, type) > 1)
6916 if (mode != BLKmode)
6918 /* First deal with alignment of the doubleword. */
6919 gpr_reg_base -= (cum->words & 1);
6921 /* This seems backwards, but it is what HP specifies. We need
6922 gpr_reg_base to point to the smaller numbered register of
6923 the integer register pair. So if we have an even register
6924 number, then decrement the gpr base. */
6925 gpr_reg_base -= ((gpr_reg_base % 2) == 0);
6927 /* FP values behave sanely, except that each FP reg is only
6929 fpr_reg_base += ((fpr_reg_base % 2) == 0);
6934 int i, offset = 0, ub;
6935 ub = FUNCTION_ARG_SIZE (mode, type);
6937 MAX(0, max_arg_words - cum->words - (cum->words & 1)));
6938 gpr_reg_base -= (cum->words & 1);
6939 for (i = 0; i < ub; i++)
6941 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
6942 gen_rtx_REG (DImode,
6951 return XEXP (loc[0], 0);
6953 return gen_rtx_PARALLEL(mode, gen_rtvec_v(ub, loc));
6959 /* If the argument is larger than a word, then we know precisely
6960 which registers we must use. */
6961 if (FUNCTION_ARG_SIZE (mode, type) > 1)
6976 /* We have a single word (32 bits). A simple computation
6977 will get us the register #s we need. */
6978 gpr_reg_base = 26 - cum->words;
6979 fpr_reg_base = 32 + 2 * cum->words;
6983 if (TARGET_64BIT && mode == TFmode)
6989 gen_rtx_EXPR_LIST (VOIDmode,
6990 gen_rtx_REG (DImode, gpr_reg_base + 1),
6992 gen_rtx_EXPR_LIST (VOIDmode,
6993 gen_rtx_REG (DImode, gpr_reg_base),
6996 /* Determine if the register needs to be passed in both general and
6997 floating point registers. */
6998 if ((TARGET_PORTABLE_RUNTIME || TARGET_64BIT)
6999 /* If we are doing soft-float with portable runtime, then there
7000 is no need to worry about FP regs. */
7001 && ! TARGET_SOFT_FLOAT
7002 /* The parameter must be some kind of float, else we can just
7003 pass it in integer registers. */
7004 && FLOAT_MODE_P (mode)
7005 /* The target function must not have a prototype. */
7006 && cum->nargs_prototype <= 0
7007 /* libcalls do not need to pass items in both FP and general
7009 && type != NULL_TREE
7010 /* All this hair applies to outgoing args only. */
7017 gen_rtx_EXPR_LIST (VOIDmode,
7018 gen_rtx_REG (mode, fpr_reg_base),
7020 gen_rtx_EXPR_LIST (VOIDmode,
7021 gen_rtx_REG (mode, gpr_reg_base),
7026 /* See if we should pass this parameter in a general register. */
7027 if (TARGET_SOFT_FLOAT
7028 /* Indirect calls in the normal 32bit ABI require all arguments
7029 to be passed in general registers. */
7030 || (!TARGET_PORTABLE_RUNTIME
7033 /* If the parameter is not a floating point parameter, then
7034 it belongs in GPRs. */
7035 || !FLOAT_MODE_P (mode))
7036 retval = gen_rtx_REG (mode, gpr_reg_base);
7038 retval = gen_rtx_REG (mode, fpr_reg_base);
7044 /* If this arg would be passed totally in registers or totally on the stack,
7045 then this routine should return zero. It is currently called only for
7046 the 64-bit target. */
7048 function_arg_partial_nregs (cum, mode, type, named)
7049 CUMULATIVE_ARGS *cum;
7050 enum machine_mode mode;
7052 int named ATTRIBUTE_UNUSED;
7054 int max_arg_words = 8;
7057 if (FUNCTION_ARG_SIZE(mode, type) > 1 && (cum->words & 1))
7060 if (cum->words + offset + FUNCTION_ARG_SIZE(mode, type) <= max_arg_words)
7061 /* Arg fits fully into registers. */
7063 else if (cum->words + offset >= max_arg_words)
7064 /* Arg fully on the stack. */
7068 return max_arg_words - cum->words - offset;
7073 /* Return 1 if this is a comparison operator. This allows the use of
7074 MATCH_OPERATOR to recognize all the branch insns. */
7077 cmpib_comparison_operator (op, mode)
7079 enum machine_mode mode;
7081 return ((mode == VOIDmode || GET_MODE (op) == mode)
7082 && (GET_CODE (op) == EQ
7083 || GET_CODE (op) == NE
7084 || GET_CODE (op) == GT
7085 || GET_CODE (op) == GTU
7086 || GET_CODE (op) == GE
7087 || GET_CODE (op) == LT
7088 || GET_CODE (op) == LE
7089 || GET_CODE (op) == LEU));
7092 /* Mark ARG (which is really a struct deferred_plabel **) for GC. */
7095 mark_deferred_plabels (arg)
7098 struct deferred_plabel *dp = *(struct deferred_plabel **) arg;
7101 for (i = 0; i < n_deferred_plabels; ++i)
7102 ggc_mark_rtx (dp[i].internal_label);
7105 /* Called to register all of our global variables with the garbage
7111 ggc_add_rtx_root (&hppa_compare_op0, 1);
7112 ggc_add_rtx_root (&hppa_compare_op1, 1);
7113 ggc_add_rtx_root (&hp_profile_label_rtx, 1);
7114 ggc_add_root (&deferred_plabels, 1, sizeof (&deferred_plabels),
7115 &mark_deferred_plabels);