1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
40 #include "integrate.h"
48 #include "target-def.h"
50 #ifndef DO_FRAME_NOTES
51 #ifdef INCOMING_RETURN_ADDR_RTX
52 #define DO_FRAME_NOTES 1
54 #define DO_FRAME_NOTES 0
58 #ifndef FUNC_BEGIN_PROLOG_LABEL
59 #define FUNC_BEGIN_PROLOG_LABEL "LFBP"
62 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
63 static void pa_combine_instructions PARAMS ((rtx));
64 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
65 static int forward_branch_p PARAMS ((rtx));
66 static int shadd_constant_p PARAMS ((int));
67 static void pa_add_gc_roots PARAMS ((void));
68 static void mark_deferred_plabels PARAMS ((void *));
69 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
70 static int compute_movstrsi_length PARAMS ((rtx));
71 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
72 static void remove_useless_addtr_insns PARAMS ((rtx, int));
73 static rtx store_reg PARAMS ((int, int, int));
74 static rtx load_reg PARAMS ((int, int, int));
75 static rtx set_reg_plus_d PARAMS ((int, int, int));
76 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
77 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
78 static int pa_adjust_priority PARAMS ((rtx, int));
79 static int pa_issue_rate PARAMS ((void));
81 /* Save the operands last given to a compare for use when we
82 generate a scc or bcc insn. */
84 rtx hppa_compare_op0, hppa_compare_op1;
85 enum cmp_type hppa_branch_type;
87 /* Which cpu we are scheduling for. */
88 enum processor_type pa_cpu;
90 /* String to hold which cpu we are scheduling for. */
91 const char *pa_cpu_string;
93 /* Which architecture we are generating code for. */
94 enum architecture_type pa_arch;
96 /* String to hold which architecture we are generating code for. */
97 const char *pa_arch_string;
99 /* Counts for the number of callee-saved general and floating point
100 registers which were saved by the current function's prologue. */
101 static int gr_saved, fr_saved;
103 /* The number of the current function for which profile information
104 is to be collected. These numbers are used to create unique label
105 id's for labels emitted at the beginning of profiled functions. */
106 static unsigned int current_function_number = 0;
108 static rtx find_addr_reg PARAMS ((rtx));
110 /* Keep track of the number of bytes we have output in the CODE subspaces
111 during this compilation so we'll know when to emit inline long-calls. */
113 unsigned int total_code_bytes;
115 /* Variables to handle plabels that we discover are necessary at assembly
116 output time. They are output after the current function. */
118 struct deferred_plabel
122 } *deferred_plabels = 0;
123 int n_deferred_plabels = 0;
125 /* Initialize the GCC target structure. */
127 #undef TARGET_ASM_ALIGNED_HI_OP
128 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
129 #undef TARGET_ASM_ALIGNED_SI_OP
130 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
131 #undef TARGET_ASM_ALIGNED_DI_OP
132 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
133 #undef TARGET_ASM_UNALIGNED_HI_OP
134 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
135 #undef TARGET_ASM_UNALIGNED_SI_OP
136 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
137 #undef TARGET_ASM_UNALIGNED_DI_OP
138 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
139 #undef TARGET_ASM_INTEGER
140 #define TARGET_ASM_INTEGER pa_assemble_integer
142 #undef TARGET_ASM_FUNCTION_PROLOGUE
143 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
144 #undef TARGET_ASM_FUNCTION_EPILOGUE
145 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
147 #undef TARGET_SCHED_ADJUST_COST
148 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
149 #undef TARGET_SCHED_ADJUST_PRIORITY
150 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
151 #undef TARGET_SCHED_ISSUE_RATE
152 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
154 struct gcc_target targetm = TARGET_INITIALIZER;
159 /* Default to 7100LC scheduling. */
160 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
162 pa_cpu_string = "7100";
163 pa_cpu = PROCESSOR_7100;
165 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
167 pa_cpu_string = "700";
168 pa_cpu = PROCESSOR_700;
170 else if (pa_cpu_string == NULL
171 || ! strcmp (pa_cpu_string, "7100LC"))
173 pa_cpu_string = "7100LC";
174 pa_cpu = PROCESSOR_7100LC;
176 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
178 pa_cpu_string = "7200";
179 pa_cpu = PROCESSOR_7200;
181 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "8000"))
183 pa_cpu_string = "8000";
184 pa_cpu = PROCESSOR_8000;
188 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string);
191 /* Set the instruction set architecture. */
192 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
194 pa_arch_string = "1.0";
195 pa_arch = ARCHITECTURE_10;
196 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
198 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
200 pa_arch_string = "1.1";
201 pa_arch = ARCHITECTURE_11;
202 target_flags &= ~MASK_PA_20;
203 target_flags |= MASK_PA_11;
205 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
207 pa_arch_string = "2.0";
208 pa_arch = ARCHITECTURE_20;
209 target_flags |= MASK_PA_11 | MASK_PA_20;
211 else if (pa_arch_string)
213 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
216 if (flag_pic && TARGET_PORTABLE_RUNTIME)
218 warning ("PIC code generation is not supported in the portable runtime model\n");
221 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
223 warning ("PIC code generation is not compatible with fast indirect calls\n");
226 if (! TARGET_GAS && write_symbols != NO_DEBUG)
228 warning ("-g is only supported when using GAS on this processor,");
229 warning ("-g option disabled");
230 write_symbols = NO_DEBUG;
233 /* We only support the "big PIC" model now. And we always generate PIC
234 code when in 64bit mode. */
235 if (flag_pic == 1 || TARGET_64BIT)
238 /* We can't guarantee that .dword is available for 32-bit targets. */
239 if (UNITS_PER_WORD == 4)
240 targetm.asm_out.aligned_op.di = NULL;
242 /* The unaligned ops are only available when using GAS. */
245 targetm.asm_out.unaligned_op.hi = NULL;
246 targetm.asm_out.unaligned_op.si = NULL;
247 targetm.asm_out.unaligned_op.di = NULL;
250 /* Register global variables with the garbage collector. */
254 /* Return non-zero only if OP is a register of mode MODE,
257 reg_or_0_operand (op, mode)
259 enum machine_mode mode;
261 return (op == CONST0_RTX (mode) || register_operand (op, mode));
264 /* Return non-zero if OP is suitable for use in a call to a named
267 For 2.5 try to eliminate either call_operand_address or
268 function_label_operand, they perform very similar functions. */
270 call_operand_address (op, mode)
272 enum machine_mode mode ATTRIBUTE_UNUSED;
274 return (GET_MODE (op) == word_mode
275 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
278 /* Return 1 if X contains a symbolic expression. We know these
279 expressions will have one of a few well defined forms, so
280 we need only check those forms. */
282 symbolic_expression_p (x)
286 /* Strip off any HIGH. */
287 if (GET_CODE (x) == HIGH)
290 return (symbolic_operand (x, VOIDmode));
294 symbolic_operand (op, mode)
296 enum machine_mode mode ATTRIBUTE_UNUSED;
298 switch (GET_CODE (op))
305 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
306 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
307 && GET_CODE (XEXP (op, 1)) == CONST_INT);
313 /* Return truth value of statement that OP is a symbolic memory
314 operand of mode MODE. */
317 symbolic_memory_operand (op, mode)
319 enum machine_mode mode ATTRIBUTE_UNUSED;
321 if (GET_CODE (op) == SUBREG)
322 op = SUBREG_REG (op);
323 if (GET_CODE (op) != MEM)
326 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
327 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
330 /* Return 1 if the operand is either a register or a memory operand that is
334 reg_or_nonsymb_mem_operand (op, mode)
336 enum machine_mode mode;
338 if (register_operand (op, mode))
341 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
347 /* Return 1 if the operand is either a register, zero, or a memory operand
348 that is not symbolic. */
351 reg_or_0_or_nonsymb_mem_operand (op, mode)
353 enum machine_mode mode;
355 if (register_operand (op, mode))
358 if (op == CONST0_RTX (mode))
361 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
367 /* Accept any constant that can be moved in one instructions into a
370 cint_ok_for_move (intval)
371 HOST_WIDE_INT intval;
373 /* OK if ldo, ldil, or zdepi, can be used. */
374 return (CONST_OK_FOR_LETTER_P (intval, 'J')
375 || CONST_OK_FOR_LETTER_P (intval, 'N')
376 || CONST_OK_FOR_LETTER_P (intval, 'K'));
379 /* Accept anything that can be moved in one instruction into a general
382 move_operand (op, mode)
384 enum machine_mode mode;
386 if (register_operand (op, mode))
389 if (GET_CODE (op) == CONSTANT_P_RTX)
392 if (GET_CODE (op) == CONST_INT)
393 return cint_ok_for_move (INTVAL (op));
395 if (GET_CODE (op) == SUBREG)
396 op = SUBREG_REG (op);
397 if (GET_CODE (op) != MEM)
402 /* We consider a LO_SUM DLT reference a move_operand now since it has
403 been merged into the normal movsi/movdi patterns. */
404 if (GET_CODE (op) == LO_SUM
405 && GET_CODE (XEXP (op, 0)) == REG
406 && REG_OK_FOR_BASE_P (XEXP (op, 0))
407 && GET_CODE (XEXP (op, 1)) == UNSPEC
408 && GET_MODE (op) == Pmode)
411 /* Since move_operand is only used for source operands, we can always
412 allow scaled indexing! */
413 if (! TARGET_DISABLE_INDEXING
414 && GET_CODE (op) == PLUS
415 && ((GET_CODE (XEXP (op, 0)) == MULT
416 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
417 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
418 && INTVAL (XEXP (XEXP (op, 0), 1))
419 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
420 && GET_CODE (XEXP (op, 1)) == REG)
421 || (GET_CODE (XEXP (op, 1)) == MULT
422 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
423 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
424 && INTVAL (XEXP (XEXP (op, 1), 1))
425 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
426 && GET_CODE (XEXP (op, 0)) == REG)))
429 return memory_address_p (mode, op);
432 /* Accept REG and any CONST_INT that can be moved in one instruction into a
435 reg_or_cint_move_operand (op, mode)
437 enum machine_mode mode;
439 if (register_operand (op, mode))
442 if (GET_CODE (op) == CONST_INT)
443 return cint_ok_for_move (INTVAL (op));
449 pic_label_operand (op, mode)
451 enum machine_mode mode ATTRIBUTE_UNUSED;
456 switch (GET_CODE (op))
462 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
463 && GET_CODE (XEXP (op, 1)) == CONST_INT);
470 fp_reg_operand (op, mode)
472 enum machine_mode mode ATTRIBUTE_UNUSED;
474 return reg_renumber && FP_REG_P (op);
479 /* Return truth value of whether OP can be used as an operand in a
480 three operand arithmetic insn that accepts registers of mode MODE
481 or 14-bit signed integers. */
483 arith_operand (op, mode)
485 enum machine_mode mode;
487 return (register_operand (op, mode)
488 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
491 /* Return truth value of whether OP can be used as an operand in a
492 three operand arithmetic insn that accepts registers of mode MODE
493 or 11-bit signed integers. */
495 arith11_operand (op, mode)
497 enum machine_mode mode;
499 return (register_operand (op, mode)
500 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
503 /* A constant integer suitable for use in a PRE_MODIFY memory
506 pre_cint_operand (op, mode)
508 enum machine_mode mode ATTRIBUTE_UNUSED;
510 return (GET_CODE (op) == CONST_INT
511 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
514 /* A constant integer suitable for use in a POST_MODIFY memory
517 post_cint_operand (op, mode)
519 enum machine_mode mode ATTRIBUTE_UNUSED;
521 return (GET_CODE (op) == CONST_INT
522 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
526 arith_double_operand (op, mode)
528 enum machine_mode mode;
530 return (register_operand (op, mode)
531 || (GET_CODE (op) == CONST_DOUBLE
532 && GET_MODE (op) == mode
533 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
534 && ((CONST_DOUBLE_HIGH (op) >= 0)
535 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
538 /* Return truth value of whether OP is an integer which fits the
539 range constraining immediate operands in three-address insns, or
540 is an integer register. */
543 ireg_or_int5_operand (op, mode)
545 enum machine_mode mode ATTRIBUTE_UNUSED;
547 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
548 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
551 /* Return nonzero if OP is an integer register, else return zero. */
553 ireg_operand (op, mode)
555 enum machine_mode mode ATTRIBUTE_UNUSED;
557 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
560 /* Return truth value of whether OP is an integer which fits the
561 range constraining immediate operands in three-address insns. */
564 int5_operand (op, mode)
566 enum machine_mode mode ATTRIBUTE_UNUSED;
568 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
572 uint5_operand (op, mode)
574 enum machine_mode mode ATTRIBUTE_UNUSED;
576 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
580 int11_operand (op, mode)
582 enum machine_mode mode ATTRIBUTE_UNUSED;
584 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
588 uint32_operand (op, mode)
590 enum machine_mode mode ATTRIBUTE_UNUSED;
592 #if HOST_BITS_PER_WIDE_INT > 32
593 /* All allowed constants will fit a CONST_INT. */
594 return (GET_CODE (op) == CONST_INT
595 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
597 return (GET_CODE (op) == CONST_INT
598 || (GET_CODE (op) == CONST_DOUBLE
599 && CONST_DOUBLE_HIGH (op) == 0));
604 arith5_operand (op, mode)
606 enum machine_mode mode;
608 return register_operand (op, mode) || int5_operand (op, mode);
611 /* True iff zdepi can be used to generate this CONST_INT.
612 zdepi first sign extends a 5 bit signed number to a given field
613 length, then places this field anywhere in a zero. */
616 unsigned HOST_WIDE_INT x;
618 unsigned HOST_WIDE_INT lsb_mask, t;
620 /* This might not be obvious, but it's at least fast.
621 This function is critical; we don't have the time loops would take. */
623 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
624 /* Return true iff t is a power of two. */
625 return ((t & (t - 1)) == 0);
628 /* True iff depi or extru can be used to compute (reg & mask).
629 Accept bit pattern like these:
635 unsigned HOST_WIDE_INT mask;
638 mask += mask & -mask;
639 return (mask & (mask - 1)) == 0;
642 /* True iff depi or extru can be used to compute (reg & OP). */
644 and_operand (op, mode)
646 enum machine_mode mode;
648 return (register_operand (op, mode)
649 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
652 /* True iff depi can be used to compute (reg | MASK). */
655 unsigned HOST_WIDE_INT mask;
657 mask += mask & -mask;
658 return (mask & (mask - 1)) == 0;
661 /* True iff depi can be used to compute (reg | OP). */
663 ior_operand (op, mode)
665 enum machine_mode mode ATTRIBUTE_UNUSED;
667 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
671 lhs_lshift_operand (op, mode)
673 enum machine_mode mode;
675 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
678 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
679 Such values can be the left hand side x in (x << r), using the zvdepi
682 lhs_lshift_cint_operand (op, mode)
684 enum machine_mode mode ATTRIBUTE_UNUSED;
686 unsigned HOST_WIDE_INT x;
687 if (GET_CODE (op) != CONST_INT)
689 x = INTVAL (op) >> 4;
690 return (x & (x + 1)) == 0;
694 arith32_operand (op, mode)
696 enum machine_mode mode;
698 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
702 pc_or_label_operand (op, mode)
704 enum machine_mode mode ATTRIBUTE_UNUSED;
706 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
709 /* Legitimize PIC addresses. If the address is already
710 position-independent, we return ORIG. Newly generated
711 position-independent addresses go to REG. If we need more
712 than one register, we lose. */
715 legitimize_pic_address (orig, mode, reg)
717 enum machine_mode mode;
721 /* Labels need special handling. */
722 if (pic_label_operand (orig, mode))
724 /* We do not want to go through the movXX expanders here since that
725 would create recursion.
727 Nor do we really want to call a generator for a named pattern
728 since that requires multiple patterns if we want to support
731 So instead we just emit the raw set, which avoids the movXX
732 expanders completely. */
733 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
734 current_function_uses_pic_offset_table = 1;
737 if (GET_CODE (orig) == SYMBOL_REF)
743 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
744 gen_rtx_HIGH (word_mode, orig)));
746 = gen_rtx_MEM (Pmode,
747 gen_rtx_LO_SUM (Pmode, reg,
748 gen_rtx_UNSPEC (Pmode,
752 current_function_uses_pic_offset_table = 1;
753 RTX_UNCHANGING_P (pic_ref) = 1;
754 emit_move_insn (reg, pic_ref);
757 else if (GET_CODE (orig) == CONST)
761 if (GET_CODE (XEXP (orig, 0)) == PLUS
762 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
768 if (GET_CODE (XEXP (orig, 0)) == PLUS)
770 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
771 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
772 base == reg ? 0 : reg);
775 if (GET_CODE (orig) == CONST_INT)
777 if (INT_14_BITS (orig))
778 return plus_constant (base, INTVAL (orig));
779 orig = force_reg (Pmode, orig);
781 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
782 /* Likewise, should we set special REG_NOTEs here? */
787 /* Try machine-dependent ways of modifying an illegitimate address
788 to be legitimate. If we find one, return the new, valid address.
789 This macro is used in only one place: `memory_address' in explow.c.
791 OLDX is the address as it was before break_out_memory_refs was called.
792 In some cases it is useful to look at this to decide what needs to be done.
794 MODE and WIN are passed so that this macro can use
795 GO_IF_LEGITIMATE_ADDRESS.
797 It is always safe for this macro to do nothing. It exists to recognize
798 opportunities to optimize the output.
800 For the PA, transform:
802 memory(X + <large int>)
806 if (<large int> & mask) >= 16
807 Y = (<large int> & ~mask) + mask + 1 Round up.
809 Y = (<large int> & ~mask) Round down.
811 memory (Z + (<large int> - Y));
813 This is for CSE to find several similar references, and only use one Z.
815 X can either be a SYMBOL_REF or REG, but because combine can not
816 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
817 D will not fit in 14 bits.
819 MODE_FLOAT references allow displacements which fit in 5 bits, so use
822 MODE_INT references allow displacements which fit in 14 bits, so use
825 This relies on the fact that most mode MODE_FLOAT references will use FP
826 registers and most mode MODE_INT references will use integer registers.
827 (In the rare case of an FP register used in an integer MODE, we depend
828 on secondary reloads to clean things up.)
831 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
832 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
833 addressing modes to be used).
835 Put X and Z into registers. Then put the entire expression into
839 hppa_legitimize_address (x, oldx, mode)
840 rtx x, oldx ATTRIBUTE_UNUSED;
841 enum machine_mode mode;
846 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
848 /* Strip off CONST. */
849 if (GET_CODE (x) == CONST)
852 /* Special case. Get the SYMBOL_REF into a register and use indexing.
853 That should always be safe. */
854 if (GET_CODE (x) == PLUS
855 && GET_CODE (XEXP (x, 0)) == REG
856 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
858 rtx reg = force_reg (Pmode, XEXP (x, 1));
859 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
862 /* Note we must reject symbols which represent function addresses
863 since the assembler/linker can't handle arithmetic on plabels. */
864 if (GET_CODE (x) == PLUS
865 && GET_CODE (XEXP (x, 1)) == CONST_INT
866 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
867 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
868 || GET_CODE (XEXP (x, 0)) == REG))
870 rtx int_part, ptr_reg;
872 int offset = INTVAL (XEXP (x, 1));
875 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
876 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
878 /* Choose which way to round the offset. Round up if we
879 are >= halfway to the next boundary. */
880 if ((offset & mask) >= ((mask + 1) / 2))
881 newoffset = (offset & ~ mask) + mask + 1;
883 newoffset = (offset & ~ mask);
885 /* If the newoffset will not fit in 14 bits (ldo), then
886 handling this would take 4 or 5 instructions (2 to load
887 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
888 add the new offset and the SYMBOL_REF.) Combine can
889 not handle 4->2 or 5->2 combinations, so do not create
891 if (! VAL_14_BITS_P (newoffset)
892 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
894 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
897 gen_rtx_HIGH (Pmode, const_part));
900 gen_rtx_LO_SUM (Pmode,
901 tmp_reg, const_part));
905 if (! VAL_14_BITS_P (newoffset))
906 int_part = force_reg (Pmode, GEN_INT (newoffset));
908 int_part = GEN_INT (newoffset);
910 ptr_reg = force_reg (Pmode,
912 force_reg (Pmode, XEXP (x, 0)),
915 return plus_constant (ptr_reg, offset - newoffset);
918 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
920 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
921 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
922 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
923 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
924 || GET_CODE (XEXP (x, 1)) == SUBREG)
925 && GET_CODE (XEXP (x, 1)) != CONST)
927 int val = INTVAL (XEXP (XEXP (x, 0), 1));
931 if (GET_CODE (reg1) != REG)
932 reg1 = force_reg (Pmode, force_operand (reg1, 0));
934 reg2 = XEXP (XEXP (x, 0), 0);
935 if (GET_CODE (reg2) != REG)
936 reg2 = force_reg (Pmode, force_operand (reg2, 0));
938 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
945 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
947 Only do so for floating point modes since this is more speculative
948 and we lose if it's an integer store. */
949 if (GET_CODE (x) == PLUS
950 && GET_CODE (XEXP (x, 0)) == PLUS
951 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
952 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
953 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
954 && (mode == SFmode || mode == DFmode))
957 /* First, try and figure out what to use as a base register. */
958 rtx reg1, reg2, base, idx, orig_base;
960 reg1 = XEXP (XEXP (x, 0), 1);
965 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
966 then emit_move_sequence will turn on REG_POINTER so we'll know
967 it's a base register below. */
968 if (GET_CODE (reg1) != REG)
969 reg1 = force_reg (Pmode, force_operand (reg1, 0));
971 if (GET_CODE (reg2) != REG)
972 reg2 = force_reg (Pmode, force_operand (reg2, 0));
974 /* Figure out what the base and index are. */
976 if (GET_CODE (reg1) == REG
977 && REG_POINTER (reg1))
980 orig_base = XEXP (XEXP (x, 0), 1);
981 idx = gen_rtx_PLUS (Pmode,
983 XEXP (XEXP (XEXP (x, 0), 0), 0),
984 XEXP (XEXP (XEXP (x, 0), 0), 1)),
987 else if (GET_CODE (reg2) == REG
988 && REG_POINTER (reg2))
991 orig_base = XEXP (x, 1);
998 /* If the index adds a large constant, try to scale the
999 constant so that it can be loaded with only one insn. */
1000 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1001 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1002 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1003 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1005 /* Divide the CONST_INT by the scale factor, then add it to A. */
1006 int val = INTVAL (XEXP (idx, 1));
1008 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1009 reg1 = XEXP (XEXP (idx, 0), 0);
1010 if (GET_CODE (reg1) != REG)
1011 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1013 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1015 /* We can now generate a simple scaled indexed address. */
1018 (Pmode, gen_rtx_PLUS (Pmode,
1019 gen_rtx_MULT (Pmode, reg1,
1020 XEXP (XEXP (idx, 0), 1)),
1024 /* If B + C is still a valid base register, then add them. */
1025 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1026 && INTVAL (XEXP (idx, 1)) <= 4096
1027 && INTVAL (XEXP (idx, 1)) >= -4096)
1029 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1032 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1034 reg2 = XEXP (XEXP (idx, 0), 0);
1035 if (GET_CODE (reg2) != CONST_INT)
1036 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1038 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1039 gen_rtx_MULT (Pmode,
1045 /* Get the index into a register, then add the base + index and
1046 return a register holding the result. */
1048 /* First get A into a register. */
1049 reg1 = XEXP (XEXP (idx, 0), 0);
1050 if (GET_CODE (reg1) != REG)
1051 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1053 /* And get B into a register. */
1054 reg2 = XEXP (idx, 1);
1055 if (GET_CODE (reg2) != REG)
1056 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1058 reg1 = force_reg (Pmode,
1059 gen_rtx_PLUS (Pmode,
1060 gen_rtx_MULT (Pmode, reg1,
1061 XEXP (XEXP (idx, 0), 1)),
1064 /* Add the result to our base register and return. */
1065 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1069 /* Uh-oh. We might have an address for x[n-100000]. This needs
1070 special handling to avoid creating an indexed memory address
1071 with x-100000 as the base.
1073 If the constant part is small enough, then it's still safe because
1074 there is a guard page at the beginning and end of the data segment.
1076 Scaled references are common enough that we want to try and rearrange the
1077 terms so that we can use indexing for these addresses too. Only
1078 do the optimization for floatint point modes. */
1080 if (GET_CODE (x) == PLUS
1081 && symbolic_expression_p (XEXP (x, 1)))
1083 /* Ugly. We modify things here so that the address offset specified
1084 by the index expression is computed first, then added to x to form
1085 the entire address. */
1087 rtx regx1, regx2, regy1, regy2, y;
1089 /* Strip off any CONST. */
1091 if (GET_CODE (y) == CONST)
1094 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1096 /* See if this looks like
1097 (plus (mult (reg) (shadd_const))
1098 (const (plus (symbol_ref) (const_int))))
1100 Where const_int is small. In that case the const
1101 expression is a valid pointer for indexing.
1103 If const_int is big, but can be divided evenly by shadd_const
1104 and added to (reg). This allows more scaled indexed addresses. */
1105 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1106 && GET_CODE (XEXP (x, 0)) == MULT
1107 && GET_CODE (XEXP (y, 1)) == CONST_INT
1108 && INTVAL (XEXP (y, 1)) >= -4096
1109 && INTVAL (XEXP (y, 1)) <= 4095
1110 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1111 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1113 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1117 if (GET_CODE (reg1) != REG)
1118 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1120 reg2 = XEXP (XEXP (x, 0), 0);
1121 if (GET_CODE (reg2) != REG)
1122 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1124 return force_reg (Pmode,
1125 gen_rtx_PLUS (Pmode,
1126 gen_rtx_MULT (Pmode,
1131 else if ((mode == DFmode || mode == SFmode)
1132 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1133 && GET_CODE (XEXP (x, 0)) == MULT
1134 && GET_CODE (XEXP (y, 1)) == CONST_INT
1135 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1136 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1137 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1140 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1141 / INTVAL (XEXP (XEXP (x, 0), 1))));
1142 regx2 = XEXP (XEXP (x, 0), 0);
1143 if (GET_CODE (regx2) != REG)
1144 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1145 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1149 gen_rtx_PLUS (Pmode,
1150 gen_rtx_MULT (Pmode, regx2,
1151 XEXP (XEXP (x, 0), 1)),
1152 force_reg (Pmode, XEXP (y, 0))));
1154 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1155 && INTVAL (XEXP (y, 1)) >= -4096
1156 && INTVAL (XEXP (y, 1)) <= 4095)
1158 /* This is safe because of the guard page at the
1159 beginning and end of the data space. Just
1160 return the original address. */
1165 /* Doesn't look like one we can optimize. */
1166 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1167 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1168 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1169 regx1 = force_reg (Pmode,
1170 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1172 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1180 /* For the HPPA, REG and REG+CONST is cost 0
1181 and addresses involving symbolic constants are cost 2.
1183 PIC addresses are very expensive.
1185 It is no coincidence that this has the same structure
1186 as GO_IF_LEGITIMATE_ADDRESS. */
1188 hppa_address_cost (X)
1191 if (GET_CODE (X) == PLUS)
1193 else if (GET_CODE (X) == LO_SUM)
1195 else if (GET_CODE (X) == HIGH)
1200 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1201 new rtx with the correct mode. */
1203 force_mode (mode, orig)
1204 enum machine_mode mode;
1207 if (mode == GET_MODE (orig))
1210 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1213 return gen_rtx_REG (mode, REGNO (orig));
1216 /* Emit insns to move operands[1] into operands[0].
1218 Return 1 if we have written out everything that needs to be done to
1219 do the move. Otherwise, return 0 and the caller will emit the move
1222 Note SCRATCH_REG may not be in the proper mode depending on how it
1223 will be used. This routine is resposible for creating a new copy
1224 of SCRATCH_REG in the proper mode. */
1227 emit_move_sequence (operands, mode, scratch_reg)
1229 enum machine_mode mode;
1232 register rtx operand0 = operands[0];
1233 register rtx operand1 = operands[1];
1237 && reload_in_progress && GET_CODE (operand0) == REG
1238 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1239 operand0 = reg_equiv_mem[REGNO (operand0)];
1240 else if (scratch_reg
1241 && reload_in_progress && GET_CODE (operand0) == SUBREG
1242 && GET_CODE (SUBREG_REG (operand0)) == REG
1243 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1245 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1246 the code which tracks sets/uses for delete_output_reload. */
1247 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1248 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1249 SUBREG_BYTE (operand0));
1250 operand0 = alter_subreg (&temp);
1254 && reload_in_progress && GET_CODE (operand1) == REG
1255 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1256 operand1 = reg_equiv_mem[REGNO (operand1)];
1257 else if (scratch_reg
1258 && reload_in_progress && GET_CODE (operand1) == SUBREG
1259 && GET_CODE (SUBREG_REG (operand1)) == REG
1260 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1262 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1263 the code which tracks sets/uses for delete_output_reload. */
1264 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1265 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1266 SUBREG_BYTE (operand1));
1267 operand1 = alter_subreg (&temp);
1270 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1271 && ((tem = find_replacement (&XEXP (operand0, 0)))
1272 != XEXP (operand0, 0)))
1273 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1274 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1275 && ((tem = find_replacement (&XEXP (operand1, 0)))
1276 != XEXP (operand1, 0)))
1277 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1279 /* Handle secondary reloads for loads/stores of FP registers from
1280 REG+D addresses where D does not fit in 5 bits, including
1281 (subreg (mem (addr))) cases. */
1282 if (fp_reg_operand (operand0, mode)
1283 && ((GET_CODE (operand1) == MEM
1284 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1285 || ((GET_CODE (operand1) == SUBREG
1286 && GET_CODE (XEXP (operand1, 0)) == MEM
1287 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1290 if (GET_CODE (operand1) == SUBREG)
1291 operand1 = XEXP (operand1, 0);
1293 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1294 it in WORD_MODE regardless of what mode it was originally given
1296 scratch_reg = force_mode (word_mode, scratch_reg);
1298 /* D might not fit in 14 bits either; for such cases load D into
1300 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1302 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1303 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1305 XEXP (XEXP (operand1, 0), 0),
1309 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1310 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1311 gen_rtx_MEM (mode, scratch_reg)));
1314 else if (fp_reg_operand (operand1, mode)
1315 && ((GET_CODE (operand0) == MEM
1316 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1317 || ((GET_CODE (operand0) == SUBREG)
1318 && GET_CODE (XEXP (operand0, 0)) == MEM
1319 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1322 if (GET_CODE (operand0) == SUBREG)
1323 operand0 = XEXP (operand0, 0);
1325 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1326 it in WORD_MODE regardless of what mode it was originally given
1328 scratch_reg = force_mode (word_mode, scratch_reg);
1330 /* D might not fit in 14 bits either; for such cases load D into
1332 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1334 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1335 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1338 XEXP (XEXP (operand0, 0),
1343 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1344 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1348 /* Handle secondary reloads for loads of FP registers from constant
1349 expressions by forcing the constant into memory.
1351 use scratch_reg to hold the address of the memory location.
1353 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1354 NO_REGS when presented with a const_int and an register class
1355 containing only FP registers. Doing so unfortunately creates
1356 more problems than it solves. Fix this for 2.5. */
1357 else if (fp_reg_operand (operand0, mode)
1358 && CONSTANT_P (operand1)
1363 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1364 it in WORD_MODE regardless of what mode it was originally given
1366 scratch_reg = force_mode (word_mode, scratch_reg);
1368 /* Force the constant into memory and put the address of the
1369 memory location into scratch_reg. */
1370 xoperands[0] = scratch_reg;
1371 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1372 emit_move_sequence (xoperands, Pmode, 0);
1374 /* Now load the destination register. */
1375 emit_insn (gen_rtx_SET (mode, operand0,
1376 gen_rtx_MEM (mode, scratch_reg)));
1379 /* Handle secondary reloads for SAR. These occur when trying to load
1380 the SAR from memory, FP register, or with a constant. */
1381 else if (GET_CODE (operand0) == REG
1382 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1383 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1384 && (GET_CODE (operand1) == MEM
1385 || GET_CODE (operand1) == CONST_INT
1386 || (GET_CODE (operand1) == REG
1387 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1390 /* D might not fit in 14 bits either; for such cases load D into
1392 if (GET_CODE (operand1) == MEM
1393 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1395 /* We are reloading the address into the scratch register, so we
1396 want to make sure the scratch register is a full register. */
1397 scratch_reg = force_mode (word_mode, scratch_reg);
1399 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1400 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1403 XEXP (XEXP (operand1, 0),
1407 /* Now we are going to load the scratch register from memory,
1408 we want to load it in the same width as the original MEM,
1409 which must be the same as the width of the ultimate destination,
1411 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1413 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1418 /* We want to load the scratch register using the same mode as
1419 the ultimate destination. */
1420 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1422 emit_move_insn (scratch_reg, operand1);
1425 /* And emit the insn to set the ultimate destination. We know that
1426 the scratch register has the same mode as the destination at this
1428 emit_move_insn (operand0, scratch_reg);
1431 /* Handle most common case: storing into a register. */
1432 else if (register_operand (operand0, mode))
1434 if (register_operand (operand1, mode)
1435 || (GET_CODE (operand1) == CONST_INT
1436 && cint_ok_for_move (INTVAL (operand1)))
1437 || (operand1 == CONST0_RTX (mode))
1438 || (GET_CODE (operand1) == HIGH
1439 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1440 /* Only `general_operands' can come here, so MEM is ok. */
1441 || GET_CODE (operand1) == MEM)
1443 /* Run this case quickly. */
1444 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1448 else if (GET_CODE (operand0) == MEM)
1450 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1451 && !(reload_in_progress || reload_completed))
1453 rtx temp = gen_reg_rtx (DFmode);
1455 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1456 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1459 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1461 /* Run this case quickly. */
1462 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1465 if (! (reload_in_progress || reload_completed))
1467 operands[0] = validize_mem (operand0);
1468 operands[1] = operand1 = force_reg (mode, operand1);
1472 /* Simplify the source if we need to.
1473 Note we do have to handle function labels here, even though we do
1474 not consider them legitimate constants. Loop optimizations can
1475 call the emit_move_xxx with one as a source. */
1476 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1477 || function_label_operand (operand1, mode)
1478 || (GET_CODE (operand1) == HIGH
1479 && symbolic_operand (XEXP (operand1, 0), mode)))
1483 if (GET_CODE (operand1) == HIGH)
1486 operand1 = XEXP (operand1, 0);
1488 if (symbolic_operand (operand1, mode))
1490 /* Argh. The assembler and linker can't handle arithmetic
1493 So we force the plabel into memory, load operand0 from
1494 the memory location, then add in the constant part. */
1495 if ((GET_CODE (operand1) == CONST
1496 && GET_CODE (XEXP (operand1, 0)) == PLUS
1497 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1498 || function_label_operand (operand1, mode))
1500 rtx temp, const_part;
1502 /* Figure out what (if any) scratch register to use. */
1503 if (reload_in_progress || reload_completed)
1505 scratch_reg = scratch_reg ? scratch_reg : operand0;
1506 /* SCRATCH_REG will hold an address and maybe the actual
1507 data. We want it in WORD_MODE regardless of what mode it
1508 was originally given to us. */
1509 scratch_reg = force_mode (word_mode, scratch_reg);
1512 scratch_reg = gen_reg_rtx (Pmode);
1514 if (GET_CODE (operand1) == CONST)
1516 /* Save away the constant part of the expression. */
1517 const_part = XEXP (XEXP (operand1, 0), 1);
1518 if (GET_CODE (const_part) != CONST_INT)
1521 /* Force the function label into memory. */
1522 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1526 /* No constant part. */
1527 const_part = NULL_RTX;
1529 /* Force the function label into memory. */
1530 temp = force_const_mem (mode, operand1);
1534 /* Get the address of the memory location. PIC-ify it if
1536 temp = XEXP (temp, 0);
1538 temp = legitimize_pic_address (temp, mode, scratch_reg);
1540 /* Put the address of the memory location into our destination
1543 emit_move_sequence (operands, mode, scratch_reg);
1545 /* Now load from the memory location into our destination
1547 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1548 emit_move_sequence (operands, mode, scratch_reg);
1550 /* And add back in the constant part. */
1551 if (const_part != NULL_RTX)
1552 expand_inc (operand0, const_part);
1561 if (reload_in_progress || reload_completed)
1563 temp = scratch_reg ? scratch_reg : operand0;
1564 /* TEMP will hold an address and maybe the actual
1565 data. We want it in WORD_MODE regardless of what mode it
1566 was originally given to us. */
1567 temp = force_mode (word_mode, temp);
1570 temp = gen_reg_rtx (Pmode);
1572 /* (const (plus (symbol) (const_int))) must be forced to
1573 memory during/after reload if the const_int will not fit
1575 if (GET_CODE (operand1) == CONST
1576 && GET_CODE (XEXP (operand1, 0)) == PLUS
1577 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1578 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1579 && (reload_completed || reload_in_progress)
1582 operands[1] = force_const_mem (mode, operand1);
1583 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1585 emit_move_sequence (operands, mode, temp);
1589 operands[1] = legitimize_pic_address (operand1, mode, temp);
1590 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1593 /* On the HPPA, references to data space are supposed to use dp,
1594 register 27, but showing it in the RTL inhibits various cse
1595 and loop optimizations. */
1600 if (reload_in_progress || reload_completed)
1602 temp = scratch_reg ? scratch_reg : operand0;
1603 /* TEMP will hold an address and maybe the actual
1604 data. We want it in WORD_MODE regardless of what mode it
1605 was originally given to us. */
1606 temp = force_mode (word_mode, temp);
1609 temp = gen_reg_rtx (mode);
1611 /* Loading a SYMBOL_REF into a register makes that register
1612 safe to be used as the base in an indexed address.
1614 Don't mark hard registers though. That loses. */
1615 if (GET_CODE (operand0) == REG
1616 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1617 REG_POINTER (operand0) = 1;
1618 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1619 REG_POINTER (temp) = 1;
1621 set = gen_rtx_SET (mode, operand0, temp);
1623 set = gen_rtx_SET (VOIDmode,
1625 gen_rtx_LO_SUM (mode, temp, operand1));
1627 emit_insn (gen_rtx_SET (VOIDmode,
1629 gen_rtx_HIGH (mode, operand1)));
1635 else if (GET_CODE (operand1) != CONST_INT
1636 || ! cint_ok_for_move (INTVAL (operand1)))
1638 rtx extend = NULL_RTX;
1641 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1642 && HOST_BITS_PER_WIDE_INT > 32
1643 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1645 HOST_WIDE_INT val = INTVAL (operand1);
1648 /* Extract the low order 32 bits of the value and sign extend.
1649 If the new value is the same as the original value, we can
1650 can use the original value as-is. If the new value is
1651 different, we use it and insert the most-significant 32-bits
1652 of the original value into the final result. */
1653 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1654 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1657 #if HOST_BITS_PER_WIDE_INT > 32
1658 extend = GEN_INT (val >> 32);
1660 operand1 = GEN_INT (nval);
1664 if (reload_in_progress || reload_completed)
1667 temp = gen_reg_rtx (mode);
1669 if (GET_CODE (operand1) == CONST_INT)
1671 /* Directly break constant into low and high parts. This
1672 provides better optimization opportunities because various
1673 passes recognize constants split with PLUS but not LO_SUM.
1674 We use a 14-bit signed low part except when the addition
1675 of 0x4000 to the high part might change the sign of the
1677 HOST_WIDE_INT value = INTVAL (operand1);
1678 HOST_WIDE_INT low = value & 0x3fff;
1679 HOST_WIDE_INT high = value & ~ 0x3fff;
1683 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1691 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1692 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1696 emit_insn (gen_rtx_SET (VOIDmode, temp,
1697 gen_rtx_HIGH (mode, operand1)));
1698 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1701 emit_move_insn (operands[0], operands[1]);
1703 if (extend != NULL_RTX)
1704 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1710 /* Now have insn-emit do whatever it normally does. */
1714 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1715 it will need a link/runtime reloc). */
1723 switch (TREE_CODE (exp))
1730 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1731 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1736 case NON_LVALUE_EXPR:
1737 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1743 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1744 if (TREE_VALUE (link) != 0)
1745 reloc |= reloc_needed (TREE_VALUE (link));
1758 /* Does operand (which is a symbolic_operand) live in text space? If
1759 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1762 read_only_operand (operand, mode)
1764 enum machine_mode mode ATTRIBUTE_UNUSED;
1766 if (GET_CODE (operand) == CONST)
1767 operand = XEXP (XEXP (operand, 0), 0);
1770 if (GET_CODE (operand) == SYMBOL_REF)
1771 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1775 if (GET_CODE (operand) == SYMBOL_REF)
1776 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1782 /* Return the best assembler insn template
1783 for moving operands[1] into operands[0] as a fullword. */
1785 singlemove_string (operands)
1788 HOST_WIDE_INT intval;
1790 if (GET_CODE (operands[0]) == MEM)
1791 return "stw %r1,%0";
1792 if (GET_CODE (operands[1]) == MEM)
1794 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1799 if (GET_MODE (operands[1]) != SFmode)
1802 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1804 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1805 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1807 operands[1] = GEN_INT (i);
1808 /* Fall through to CONST_INT case. */
1810 if (GET_CODE (operands[1]) == CONST_INT)
1812 intval = INTVAL (operands[1]);
1814 if (VAL_14_BITS_P (intval))
1816 else if ((intval & 0x7ff) == 0)
1817 return "ldil L'%1,%0";
1818 else if (zdepi_cint_p (intval))
1819 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1821 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1823 return "copy %1,%0";
1827 /* Compute position (in OP[1]) and width (in OP[2])
1828 useful for copying IMM to a register using the zdepi
1829 instructions. Store the immediate value to insert in OP[0]. */
1831 compute_zdepwi_operands (imm, op)
1832 unsigned HOST_WIDE_INT imm;
1837 /* Find the least significant set bit in IMM. */
1838 for (lsb = 0; lsb < 32; lsb++)
1845 /* Choose variants based on *sign* of the 5-bit field. */
1846 if ((imm & 0x10) == 0)
1847 len = (lsb <= 28) ? 4 : 32 - lsb;
1850 /* Find the width of the bitstring in IMM. */
1851 for (len = 5; len < 32; len++)
1853 if ((imm & (1 << len)) == 0)
1857 /* Sign extend IMM as a 5-bit value. */
1858 imm = (imm & 0xf) - 0x10;
1866 /* Compute position (in OP[1]) and width (in OP[2])
1867 useful for copying IMM to a register using the depdi,z
1868 instructions. Store the immediate value to insert in OP[0]. */
1870 compute_zdepdi_operands (imm, op)
1871 unsigned HOST_WIDE_INT imm;
1874 HOST_WIDE_INT lsb, len;
1876 /* Find the least significant set bit in IMM. */
1877 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1884 /* Choose variants based on *sign* of the 5-bit field. */
1885 if ((imm & 0x10) == 0)
1886 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1887 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1890 /* Find the width of the bitstring in IMM. */
1891 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1893 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
1897 /* Sign extend IMM as a 5-bit value. */
1898 imm = (imm & 0xf) - 0x10;
1906 /* Output assembler code to perform a doubleword move insn
1907 with operands OPERANDS. */
1910 output_move_double (operands)
1913 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1915 rtx addreg0 = 0, addreg1 = 0;
1917 /* First classify both operands. */
1919 if (REG_P (operands[0]))
1921 else if (offsettable_memref_p (operands[0]))
1923 else if (GET_CODE (operands[0]) == MEM)
1928 if (REG_P (operands[1]))
1930 else if (CONSTANT_P (operands[1]))
1932 else if (offsettable_memref_p (operands[1]))
1934 else if (GET_CODE (operands[1]) == MEM)
1939 /* Check for the cases that the operand constraints are not
1940 supposed to allow to happen. Abort if we get one,
1941 because generating code for these cases is painful. */
1943 if (optype0 != REGOP && optype1 != REGOP)
1946 /* Handle auto decrementing and incrementing loads and stores
1947 specifically, since the structure of the function doesn't work
1948 for them without major modification. Do it better when we learn
1949 this port about the general inc/dec addressing of PA.
1950 (This was written by tege. Chide him if it doesn't work.) */
1952 if (optype0 == MEMOP)
1954 /* We have to output the address syntax ourselves, since print_operand
1955 doesn't deal with the addresses we want to use. Fix this later. */
1957 rtx addr = XEXP (operands[0], 0);
1958 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1960 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1962 operands[0] = XEXP (addr, 0);
1963 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1966 if (!reg_overlap_mentioned_p (high_reg, addr))
1968 /* No overlap between high target register and address
1969 register. (We do this in a non-obvious way to
1970 save a register file writeback) */
1971 if (GET_CODE (addr) == POST_INC)
1972 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
1973 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
1978 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1980 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1982 operands[0] = XEXP (addr, 0);
1983 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1986 if (!reg_overlap_mentioned_p (high_reg, addr))
1988 /* No overlap between high target register and address
1989 register. (We do this in a non-obvious way to
1990 save a register file writeback) */
1991 if (GET_CODE (addr) == PRE_INC)
1992 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
1993 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
1999 if (optype1 == MEMOP)
2001 /* We have to output the address syntax ourselves, since print_operand
2002 doesn't deal with the addresses we want to use. Fix this later. */
2004 rtx addr = XEXP (operands[1], 0);
2005 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2007 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2009 operands[1] = XEXP (addr, 0);
2010 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2013 if (!reg_overlap_mentioned_p (high_reg, addr))
2015 /* No overlap between high target register and address
2016 register. (We do this in a non-obvious way to
2017 save a register file writeback) */
2018 if (GET_CODE (addr) == POST_INC)
2019 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2020 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2024 /* This is an undefined situation. We should load into the
2025 address register *and* update that register. Probably
2026 we don't need to handle this at all. */
2027 if (GET_CODE (addr) == POST_INC)
2028 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2029 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2032 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2034 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2036 operands[1] = XEXP (addr, 0);
2037 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2040 if (!reg_overlap_mentioned_p (high_reg, addr))
2042 /* No overlap between high target register and address
2043 register. (We do this in a non-obvious way to
2044 save a register file writeback) */
2045 if (GET_CODE (addr) == PRE_INC)
2046 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2047 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2051 /* This is an undefined situation. We should load into the
2052 address register *and* update that register. Probably
2053 we don't need to handle this at all. */
2054 if (GET_CODE (addr) == PRE_INC)
2055 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2056 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2059 else if (GET_CODE (addr) == PLUS
2060 && GET_CODE (XEXP (addr, 0)) == MULT)
2062 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2064 if (!reg_overlap_mentioned_p (high_reg, addr))
2068 xoperands[0] = high_reg;
2069 xoperands[1] = XEXP (addr, 1);
2070 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2071 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2072 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2074 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2080 xoperands[0] = high_reg;
2081 xoperands[1] = XEXP (addr, 1);
2082 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2083 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2084 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2086 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2091 /* If an operand is an unoffsettable memory ref, find a register
2092 we can increment temporarily to make it refer to the second word. */
2094 if (optype0 == MEMOP)
2095 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2097 if (optype1 == MEMOP)
2098 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2100 /* Ok, we can do one word at a time.
2101 Normally we do the low-numbered word first.
2103 In either case, set up in LATEHALF the operands to use
2104 for the high-numbered word and in some cases alter the
2105 operands in OPERANDS to be suitable for the low-numbered word. */
2107 if (optype0 == REGOP)
2108 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2109 else if (optype0 == OFFSOP)
2110 latehalf[0] = adjust_address (operands[0], SImode, 4);
2112 latehalf[0] = operands[0];
2114 if (optype1 == REGOP)
2115 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2116 else if (optype1 == OFFSOP)
2117 latehalf[1] = adjust_address (operands[1], SImode, 4);
2118 else if (optype1 == CNSTOP)
2119 split_double (operands[1], &operands[1], &latehalf[1]);
2121 latehalf[1] = operands[1];
2123 /* If the first move would clobber the source of the second one,
2124 do them in the other order.
2126 This can happen in two cases:
2128 mem -> register where the first half of the destination register
2129 is the same register used in the memory's address. Reload
2130 can create such insns.
2132 mem in this case will be either register indirect or register
2133 indirect plus a valid offset.
2135 register -> register move where REGNO(dst) == REGNO(src + 1)
2136 someone (Tim/Tege?) claimed this can happen for parameter loads.
2138 Handle mem -> register case first. */
2139 if (optype0 == REGOP
2140 && (optype1 == MEMOP || optype1 == OFFSOP)
2141 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2144 /* Do the late half first. */
2146 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2147 output_asm_insn (singlemove_string (latehalf), latehalf);
2151 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2152 return singlemove_string (operands);
2155 /* Now handle register -> register case. */
2156 if (optype0 == REGOP && optype1 == REGOP
2157 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2159 output_asm_insn (singlemove_string (latehalf), latehalf);
2160 return singlemove_string (operands);
2163 /* Normal case: do the two words, low-numbered first. */
2165 output_asm_insn (singlemove_string (operands), operands);
2167 /* Make any unoffsettable addresses point at high-numbered word. */
2169 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2171 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2174 output_asm_insn (singlemove_string (latehalf), latehalf);
2176 /* Undo the adds we just did. */
2178 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2180 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2186 output_fp_move_double (operands)
2189 if (FP_REG_P (operands[0]))
2191 if (FP_REG_P (operands[1])
2192 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2193 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2195 output_asm_insn ("fldd%F1 %1,%0", operands);
2197 else if (FP_REG_P (operands[1]))
2199 output_asm_insn ("fstd%F0 %1,%0", operands);
2201 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2203 if (GET_CODE (operands[0]) == REG)
2206 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2207 xoperands[0] = operands[0];
2208 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2210 /* This is a pain. You have to be prepared to deal with an
2211 arbitrary address here including pre/post increment/decrement.
2213 so avoid this in the MD. */
2221 /* Return a REG that occurs in ADDR with coefficient 1.
2222 ADDR can be effectively incremented by incrementing REG. */
2225 find_addr_reg (addr)
2228 while (GET_CODE (addr) == PLUS)
2230 if (GET_CODE (XEXP (addr, 0)) == REG)
2231 addr = XEXP (addr, 0);
2232 else if (GET_CODE (XEXP (addr, 1)) == REG)
2233 addr = XEXP (addr, 1);
2234 else if (CONSTANT_P (XEXP (addr, 0)))
2235 addr = XEXP (addr, 1);
2236 else if (CONSTANT_P (XEXP (addr, 1)))
2237 addr = XEXP (addr, 0);
2241 if (GET_CODE (addr) == REG)
2246 /* Emit code to perform a block move.
2248 OPERANDS[0] is the destination pointer as a REG, clobbered.
2249 OPERANDS[1] is the source pointer as a REG, clobbered.
2250 OPERANDS[2] is a register for temporary storage.
2251 OPERANDS[4] is the size as a CONST_INT
2252 OPERANDS[3] is a register for temporary storage.
2253 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2254 OPERANDS[6] is another temporary register. */
2257 output_block_move (operands, size_is_constant)
2259 int size_is_constant ATTRIBUTE_UNUSED;
2261 int align = INTVAL (operands[5]);
2262 unsigned long n_bytes = INTVAL (operands[4]);
2264 /* We can't move more than four bytes at a time because the PA
2265 has no longer integer move insns. (Could use fp mem ops?) */
2269 /* Note that we know each loop below will execute at least twice
2270 (else we would have open-coded the copy). */
2274 /* Pre-adjust the loop counter. */
2275 operands[4] = GEN_INT (n_bytes - 8);
2276 output_asm_insn ("ldi %4,%2", operands);
2279 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2280 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2281 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2282 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2283 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2285 /* Handle the residual. There could be up to 7 bytes of
2286 residual to copy! */
2287 if (n_bytes % 8 != 0)
2289 operands[4] = GEN_INT (n_bytes % 4);
2290 if (n_bytes % 8 >= 4)
2291 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2292 if (n_bytes % 4 != 0)
2293 output_asm_insn ("ldw 0(%1),%6", operands);
2294 if (n_bytes % 8 >= 4)
2295 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2296 if (n_bytes % 4 != 0)
2297 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2302 /* Pre-adjust the loop counter. */
2303 operands[4] = GEN_INT (n_bytes - 4);
2304 output_asm_insn ("ldi %4,%2", operands);
2307 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2308 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2309 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2310 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2311 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2313 /* Handle the residual. */
2314 if (n_bytes % 4 != 0)
2316 if (n_bytes % 4 >= 2)
2317 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2318 if (n_bytes % 2 != 0)
2319 output_asm_insn ("ldb 0(%1),%6", operands);
2320 if (n_bytes % 4 >= 2)
2321 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2322 if (n_bytes % 2 != 0)
2323 output_asm_insn ("stb %6,0(%0)", operands);
2328 /* Pre-adjust the loop counter. */
2329 operands[4] = GEN_INT (n_bytes - 2);
2330 output_asm_insn ("ldi %4,%2", operands);
2333 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2334 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2335 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2336 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2337 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2339 /* Handle the residual. */
2340 if (n_bytes % 2 != 0)
2342 output_asm_insn ("ldb 0(%1),%3", operands);
2343 output_asm_insn ("stb %3,0(%0)", operands);
2352 /* Count the number of insns necessary to handle this block move.
2354 Basic structure is the same as emit_block_move, except that we
2355 count insns rather than emit them. */
2358 compute_movstrsi_length (insn)
2361 rtx pat = PATTERN (insn);
2362 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2363 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
2364 unsigned int n_insns = 0;
2366 /* We can't move more than four bytes at a time because the PA
2367 has no longer integer move insns. (Could use fp mem ops?) */
2371 /* The basic copying loop. */
2375 if (n_bytes % (2 * align) != 0)
2377 if ((n_bytes % (2 * align)) >= align)
2380 if ((n_bytes % align) != 0)
2384 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2390 output_and (operands)
2393 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2395 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2396 int ls0, ls1, ms0, p, len;
2398 for (ls0 = 0; ls0 < 32; ls0++)
2399 if ((mask & (1 << ls0)) == 0)
2402 for (ls1 = ls0; ls1 < 32; ls1++)
2403 if ((mask & (1 << ls1)) != 0)
2406 for (ms0 = ls1; ms0 < 32; ms0++)
2407 if ((mask & (1 << ms0)) == 0)
2420 operands[2] = GEN_INT (len);
2421 return "{extru|extrw,u} %1,31,%2,%0";
2425 /* We could use this `depi' for the case above as well, but `depi'
2426 requires one more register file access than an `extru'. */
2431 operands[2] = GEN_INT (p);
2432 operands[3] = GEN_INT (len);
2433 return "{depi|depwi} 0,%2,%3,%0";
2437 return "and %1,%2,%0";
2440 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2441 storing the result in operands[0]. */
2443 output_64bit_and (operands)
2446 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2448 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2449 int ls0, ls1, ms0, p, len;
2451 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2452 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2455 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2456 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2459 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2460 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2463 if (ms0 != HOST_BITS_PER_WIDE_INT)
2466 if (ls1 == HOST_BITS_PER_WIDE_INT)
2473 operands[2] = GEN_INT (len);
2474 return "extrd,u %1,63,%2,%0";
2478 /* We could use this `depi' for the case above as well, but `depi'
2479 requires one more register file access than an `extru'. */
2484 operands[2] = GEN_INT (p);
2485 operands[3] = GEN_INT (len);
2486 return "depdi 0,%2,%3,%0";
2490 return "and %1,%2,%0";
2494 output_ior (operands)
2497 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2498 int bs0, bs1, p, len;
2500 if (INTVAL (operands[2]) == 0)
2501 return "copy %1,%0";
2503 for (bs0 = 0; bs0 < 32; bs0++)
2504 if ((mask & (1 << bs0)) != 0)
2507 for (bs1 = bs0; bs1 < 32; bs1++)
2508 if ((mask & (1 << bs1)) == 0)
2511 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2517 operands[2] = GEN_INT (p);
2518 operands[3] = GEN_INT (len);
2519 return "{depi|depwi} -1,%2,%3,%0";
2522 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2523 storing the result in operands[0]. */
2525 output_64bit_ior (operands)
2528 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2529 int bs0, bs1, p, len;
2531 if (INTVAL (operands[2]) == 0)
2532 return "copy %1,%0";
2534 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2535 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2538 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2539 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2542 if (bs1 != HOST_BITS_PER_WIDE_INT
2543 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2549 operands[2] = GEN_INT (p);
2550 operands[3] = GEN_INT (len);
2551 return "depdi -1,%2,%3,%0";
2554 /* Target hook for assembling integer objects. This code handles
2555 aligned SI and DI integers specially, since function references must
2556 be preceded by P%. */
2559 pa_assemble_integer (x, size, aligned_p)
2564 if (size == UNITS_PER_WORD && aligned_p
2565 && function_label_operand (x, VOIDmode))
2567 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2568 output_addr_const (asm_out_file, x);
2569 fputc ('\n', asm_out_file);
2572 return default_assemble_integer (x, size, aligned_p);
2575 /* Output an ascii string. */
2577 output_ascii (file, p, size)
2584 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2586 /* The HP assembler can only take strings of 256 characters at one
2587 time. This is a limitation on input line length, *not* the
2588 length of the string. Sigh. Even worse, it seems that the
2589 restriction is in number of input characters (see \xnn &
2590 \whatever). So we have to do this very carefully. */
2592 fputs ("\t.STRING \"", file);
2595 for (i = 0; i < size; i += 4)
2599 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2601 register unsigned int c = (unsigned char) p[i + io];
2603 if (c == '\"' || c == '\\')
2604 partial_output[co++] = '\\';
2605 if (c >= ' ' && c < 0177)
2606 partial_output[co++] = c;
2610 partial_output[co++] = '\\';
2611 partial_output[co++] = 'x';
2612 hexd = c / 16 - 0 + '0';
2614 hexd -= '9' - 'a' + 1;
2615 partial_output[co++] = hexd;
2616 hexd = c % 16 - 0 + '0';
2618 hexd -= '9' - 'a' + 1;
2619 partial_output[co++] = hexd;
2622 if (chars_output + co > 243)
2624 fputs ("\"\n\t.STRING \"", file);
2627 fwrite (partial_output, 1, co, file);
2631 fputs ("\"\n", file);
2634 /* Try to rewrite floating point comparisons & branches to avoid
2635 useless add,tr insns.
2637 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2638 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2639 first attempt to remove useless add,tr insns. It is zero
2640 for the second pass as reorg sometimes leaves bogus REG_DEAD
2643 When CHECK_NOTES is zero we can only eliminate add,tr insns
2644 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2647 remove_useless_addtr_insns (insns, check_notes)
2652 static int pass = 0;
2654 /* This is fairly cheap, so always run it when optimizing. */
2658 int fbranch_count = 0;
2660 /* Walk all the insns in this function looking for fcmp & fbranch
2661 instructions. Keep track of how many of each we find. */
2662 insns = get_insns ();
2663 for (insn = insns; insn; insn = next_insn (insn))
2667 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2668 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2671 tmp = PATTERN (insn);
2673 /* It must be a set. */
2674 if (GET_CODE (tmp) != SET)
2677 /* If the destination is CCFP, then we've found an fcmp insn. */
2678 tmp = SET_DEST (tmp);
2679 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2685 tmp = PATTERN (insn);
2686 /* If this is an fbranch instruction, bump the fbranch counter. */
2687 if (GET_CODE (tmp) == SET
2688 && SET_DEST (tmp) == pc_rtx
2689 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2690 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2691 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2692 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2700 /* Find all floating point compare + branch insns. If possible,
2701 reverse the comparison & the branch to avoid add,tr insns. */
2702 for (insn = insns; insn; insn = next_insn (insn))
2706 /* Ignore anything that isn't an INSN. */
2707 if (GET_CODE (insn) != INSN)
2710 tmp = PATTERN (insn);
2712 /* It must be a set. */
2713 if (GET_CODE (tmp) != SET)
2716 /* The destination must be CCFP, which is register zero. */
2717 tmp = SET_DEST (tmp);
2718 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2721 /* INSN should be a set of CCFP.
2723 See if the result of this insn is used in a reversed FP
2724 conditional branch. If so, reverse our condition and
2725 the branch. Doing so avoids useless add,tr insns. */
2726 next = next_insn (insn);
2729 /* Jumps, calls and labels stop our search. */
2730 if (GET_CODE (next) == JUMP_INSN
2731 || GET_CODE (next) == CALL_INSN
2732 || GET_CODE (next) == CODE_LABEL)
2735 /* As does another fcmp insn. */
2736 if (GET_CODE (next) == INSN
2737 && GET_CODE (PATTERN (next)) == SET
2738 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2739 && REGNO (SET_DEST (PATTERN (next))) == 0)
2742 next = next_insn (next);
2745 /* Is NEXT_INSN a branch? */
2747 && GET_CODE (next) == JUMP_INSN)
2749 rtx pattern = PATTERN (next);
2751 /* If it a reversed fp conditional branch (eg uses add,tr)
2752 and CCFP dies, then reverse our conditional and the branch
2753 to avoid the add,tr. */
2754 if (GET_CODE (pattern) == SET
2755 && SET_DEST (pattern) == pc_rtx
2756 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2757 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2758 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2759 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2760 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2761 && (fcmp_count == fbranch_count
2763 && find_regno_note (next, REG_DEAD, 0))))
2765 /* Reverse the branch. */
2766 tmp = XEXP (SET_SRC (pattern), 1);
2767 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2768 XEXP (SET_SRC (pattern), 2) = tmp;
2769 INSN_CODE (next) = -1;
2771 /* Reverse our condition. */
2772 tmp = PATTERN (insn);
2773 PUT_CODE (XEXP (tmp, 1),
2774 (reverse_condition_maybe_unordered
2775 (GET_CODE (XEXP (tmp, 1)))));
2785 /* You may have trouble believing this, but this is the 32 bit HP-PA
2790 Variable arguments (optional; any number may be allocated)
2792 SP-(4*(N+9)) arg word N
2797 Fixed arguments (must be allocated; may remain unused)
2806 SP-32 External Data Pointer (DP)
2808 SP-24 External/stub RP (RP')
2812 SP-8 Calling Stub RP (RP'')
2817 SP-0 Stack Pointer (points to next available address)
2821 /* This function saves registers as follows. Registers marked with ' are
2822 this function's registers (as opposed to the previous function's).
2823 If a frame_pointer isn't needed, r4 is saved as a general register;
2824 the space for the frame pointer is still allocated, though, to keep
2830 SP (FP') Previous FP
2831 SP + 4 Alignment filler (sigh)
2832 SP + 8 Space for locals reserved here.
2836 SP + n All call saved register used.
2840 SP + o All call saved fp registers used.
2844 SP + p (SP') points to next available address.
2848 /* Global variables set by output_function_prologue(). */
2849 /* Size of frame. Need to know this to emit return insns from
2851 static int actual_fsize;
2852 static int local_fsize, save_fregs;
2854 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2855 Handle case where DISP > 8k by using the add_high_const patterns.
2857 Note in DISP > 8k case, we will leave the high part of the address
2858 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2861 store_reg (reg, disp, base)
2862 int reg, disp, base;
2864 rtx i, dest, src, basereg;
2866 src = gen_rtx_REG (word_mode, reg);
2867 basereg = gen_rtx_REG (Pmode, base);
2868 if (VAL_14_BITS_P (disp))
2870 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2871 i = emit_move_insn (dest, src);
2875 rtx delta = GEN_INT (disp);
2876 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
2877 rtx tmpreg = gen_rtx_REG (Pmode, 1);
2878 emit_move_insn (tmpreg, high);
2879 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
2880 i = emit_move_insn (dest, src);
2885 /* Emit RTL to set REG to the value specified by BASE+DISP.
2886 Handle case where DISP > 8k by using the add_high_const patterns.
2888 Note in DISP > 8k case, we will leave the high part of the address
2889 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2892 set_reg_plus_d (reg, base, disp)
2893 int reg, base, disp;
2897 if (VAL_14_BITS_P (disp))
2899 i = emit_move_insn (gen_rtx_REG (Pmode, reg),
2900 plus_constant (gen_rtx_REG (Pmode, base), disp));
2904 rtx delta = GEN_INT (disp);
2905 emit_move_insn (gen_rtx_REG (Pmode, 1),
2906 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, base),
2907 gen_rtx_HIGH (Pmode, delta)));
2908 i = emit_move_insn (gen_rtx_REG (Pmode, reg),
2909 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
2916 compute_frame_size (size, fregs_live)
2922 /* Space for frame pointer + filler. If any frame is allocated
2923 we need to add this in because of STARTING_FRAME_OFFSET.
2925 Similar code also appears in hppa_expand_prologue. Change both
2926 of them at the same time. */
2927 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
2929 /* Account for space used by the callee general register saves. */
2930 for (i = 18; i >= 3; i--)
2931 if (regs_ever_live[i])
2932 fsize += UNITS_PER_WORD;
2934 /* Round the stack. */
2935 fsize = (fsize + 7) & ~7;
2937 /* Account for space used by the callee floating point register saves. */
2938 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
2939 if (regs_ever_live[i]
2940 || (! TARGET_64BIT && regs_ever_live[i + 1]))
2945 /* We always save both halves of the FP register, so always
2946 increment the frame size by 8 bytes. */
2950 /* The various ABIs include space for the outgoing parameters in the
2951 size of the current function's stack frame. */
2952 fsize += current_function_outgoing_args_size;
2954 /* Allocate space for the fixed frame marker. This space must be
2955 allocated for any function that makes calls or otherwise allocates
2957 if (!current_function_is_leaf || fsize)
2958 fsize += TARGET_64BIT ? 16 : 32;
2960 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
2963 /* Generate the assembly code for function entry. FILE is a stdio
2964 stream to output the code to. SIZE is an int: how many units of
2965 temporary storage to allocate.
2967 Refer to the array `regs_ever_live' to determine which registers to
2968 save; `regs_ever_live[I]' is nonzero if register number I is ever
2969 used in the function. This function is responsible for knowing
2970 which registers should not be saved even if used. */
2972 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
2973 of memory. If any fpu reg is used in the function, we allocate
2974 such a block here, at the bottom of the frame, just in case it's needed.
2976 If this function is a leaf procedure, then we may choose not
2977 to do a "save" insn. The decision about whether or not
2978 to do this is made in regclass.c. */
2981 pa_output_function_prologue (file, size)
2983 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2985 /* The function's label and associated .PROC must never be
2986 separated and must be output *after* any profiling declarations
2987 to avoid changing spaces/subspaces within a procedure. */
2988 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
2989 fputs ("\t.PROC\n", file);
2991 /* hppa_expand_prologue does the dirty work now. We just need
2992 to output the assembler directives which denote the start
2994 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
2995 if (regs_ever_live[2])
2996 fputs (",CALLS,SAVE_RP", file);
2998 fputs (",NO_CALLS", file);
3000 if (frame_pointer_needed)
3001 fputs (",SAVE_SP", file);
3003 /* Pass on information about the number of callee register saves
3004 performed in the prologue.
3006 The compiler is supposed to pass the highest register number
3007 saved, the assembler then has to adjust that number before
3008 entering it into the unwind descriptor (to account for any
3009 caller saved registers with lower register numbers than the
3010 first callee saved register). */
3012 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3015 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3017 fputs ("\n\t.ENTRY\n", file);
3019 /* When profiling, we need a local label at the beginning of the
3020 prologue because GAS can't handle the difference of a global symbol
3021 and a local symbol. */
3022 if (current_function_profile)
3024 ASM_OUTPUT_INTERNAL_LABEL (file, FUNC_BEGIN_PROLOG_LABEL,
3025 current_function_number);
3026 current_function_number++;
3029 /* If we're using GAS and not using the portable runtime model, then
3030 we don't need to accumulate the total number of code bytes. */
3031 if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
3032 total_code_bytes = 0;
3033 else if (INSN_ADDRESSES_SET_P ())
3035 unsigned int old_total = total_code_bytes;
3037 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_insn ()));
3038 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3040 /* Be prepared to handle overflows. */
3041 if (old_total > total_code_bytes)
3042 total_code_bytes = -1;
3045 total_code_bytes = -1;
3047 remove_useless_addtr_insns (get_insns (), 0);
3055 RTX_FRAME_RELATED_P (insn) = 1; \
3059 #define FRP(INSN) INSN
3063 hppa_expand_prologue ()
3065 int size = get_frame_size ();
3066 int merge_sp_adjust_with_store = 0;
3068 rtx tmpreg, size_rtx;
3074 /* Allocate space for frame pointer + filler. If any frame is allocated
3075 we need to add this in because of STARTING_FRAME_OFFSET.
3077 Similar code also appears in compute_frame_size. Change both
3078 of them at the same time. */
3079 local_fsize = size + (size || frame_pointer_needed
3080 ? STARTING_FRAME_OFFSET : 0);
3082 actual_fsize = compute_frame_size (size, &save_fregs);
3084 /* Compute a few things we will use often. */
3085 tmpreg = gen_rtx_REG (word_mode, 1);
3086 size_rtx = GEN_INT (actual_fsize);
3088 /* Save RP first. The calling conventions manual states RP will
3089 always be stored into the caller's frame at sp - 20 or sp - 16
3090 depending on which ABI is in use. */
3091 if (regs_ever_live[2])
3092 FRP (store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM));
3094 /* Allocate the local frame and set up the frame pointer if needed. */
3095 if (actual_fsize != 0)
3097 if (frame_pointer_needed)
3099 /* Copy the old frame pointer temporarily into %r1. Set up the
3100 new stack pointer, then store away the saved old frame pointer
3101 into the stack at sp+actual_fsize and at the same time update
3102 the stack pointer by actual_fsize bytes. Two versions, first
3103 handles small (<8k) frames. The second handles large (>=8k)
3105 emit_move_insn (tmpreg, frame_pointer_rtx);
3106 FRP (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx));
3107 if (VAL_14_BITS_P (actual_fsize))
3109 rtx insn = emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
3114 RTX_FRAME_RELATED_P (insn) = 1;
3116 gen_rtx_SET (VOIDmode,
3117 gen_rtx_MEM (word_mode,
3120 gen_rtx_SET (VOIDmode,
3122 gen_rtx_PLUS (word_mode,
3126 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3127 gen_rtx_SEQUENCE (VOIDmode, vec),
3133 /* It is incorrect to store the saved frame pointer at *sp,
3134 then increment sp (writes beyond the current stack boundary).
3136 So instead use stwm to store at *sp and post-increment the
3137 stack pointer as an atomic operation. Then increment sp to
3138 finish allocating the new frame. */
3139 int adjust1 = 8192 - 64;
3140 int adjust2 = actual_fsize - adjust1;
3141 rtx delta = GEN_INT (adjust1);
3142 rtx insn = emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
3147 RTX_FRAME_RELATED_P (insn) = 1;
3149 gen_rtx_SET (VOIDmode,
3150 gen_rtx_MEM (word_mode,
3153 gen_rtx_SET (VOIDmode,
3155 gen_rtx_PLUS (word_mode,
3159 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3160 gen_rtx_SEQUENCE (VOIDmode, vec),
3164 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3165 STACK_POINTER_REGNUM,
3168 /* Prevent register spills from being scheduled before the
3169 stack pointer is raised. Necessary as we will be storing
3170 registers using the frame pointer as a base register, and
3171 we happen to set fp before raising sp. */
3172 emit_insn (gen_blockage ());
3174 /* no frame pointer needed. */
3177 /* In some cases we can perform the first callee register save
3178 and allocating the stack frame at the same time. If so, just
3179 make a note of it and defer allocating the frame until saving
3180 the callee registers. */
3181 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3182 merge_sp_adjust_with_store = 1;
3183 /* Can not optimize. Adjust the stack frame by actual_fsize
3186 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3187 STACK_POINTER_REGNUM,
3192 /* Normal register save.
3194 Do not save the frame pointer in the frame_pointer_needed case. It
3195 was done earlier. */
3196 if (frame_pointer_needed)
3198 for (i = 18, offset = local_fsize; i >= 4; i--)
3199 if (regs_ever_live[i] && ! call_used_regs[i])
3201 FRP (store_reg (i, offset, FRAME_POINTER_REGNUM));
3202 offset += UNITS_PER_WORD;
3205 /* Account for %r3 which is saved in a special place. */
3208 /* No frame pointer needed. */
3211 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3212 if (regs_ever_live[i] && ! call_used_regs[i])
3214 /* If merge_sp_adjust_with_store is nonzero, then we can
3215 optimize the first GR save. */
3216 if (merge_sp_adjust_with_store)
3218 rtx delta = GEN_INT (-offset);
3219 merge_sp_adjust_with_store = 0;
3220 FRP (emit_insn (gen_post_store (stack_pointer_rtx,
3221 gen_rtx_REG (word_mode, i),
3225 FRP (store_reg (i, offset, STACK_POINTER_REGNUM));
3226 offset += UNITS_PER_WORD;
3230 /* If we wanted to merge the SP adjustment with a GR save, but we never
3231 did any GR saves, then just emit the adjustment here. */
3232 if (merge_sp_adjust_with_store)
3233 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3234 STACK_POINTER_REGNUM,
3238 /* The hppa calling conventions say that %r19, the pic offset
3239 register, is saved at sp - 32 (in this function's frame)
3240 when generating PIC code. FIXME: What is the correct thing
3241 to do for functions which make no calls and allocate no
3242 frame? Do we need to allocate a frame, or can we just omit
3243 the save? For now we'll just omit the save. */
3244 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3245 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3247 /* Align pointer properly (doubleword boundary). */
3248 offset = (offset + 7) & ~7;
3250 /* Floating point register store. */
3253 /* First get the frame or stack pointer to the start of the FP register
3255 if (frame_pointer_needed)
3256 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset));
3258 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM, offset));
3260 /* Now actually save the FP registers. */
3261 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3263 if (regs_ever_live[i]
3264 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3267 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3268 reg = gen_rtx_REG (DFmode, i);
3269 FRP (emit_move_insn (addr, reg));
3276 /* ?!? Do we want frame notes in the epilogue yet? */
3277 #undef DO_FRAME_NOTES
3278 #define DO_FRAME_NOTES 0
3280 #define FRP(INSN) INSN
3282 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3283 Handle case where DISP > 8k by using the add_high_const patterns. */
3286 load_reg (reg, disp, base)
3287 int reg, disp, base;
3289 rtx i, src, dest, basereg;
3291 dest = gen_rtx_REG (word_mode, reg);
3292 basereg = gen_rtx_REG (Pmode, base);
3293 if (VAL_14_BITS_P (disp))
3295 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3296 i = emit_move_insn (dest, src);
3300 rtx delta = GEN_INT (disp);
3301 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3302 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3303 emit_move_insn (tmpreg, high);
3304 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3305 i = emit_move_insn (dest, src);
3310 /* This function generates the assembly code for function exit.
3311 Args are as for output_function_prologue ().
3313 The function epilogue should not depend on the current stack
3314 pointer! It should use the frame pointer only. This is mandatory
3315 because of alloca; we also take advantage of it to omit stack
3316 adjustments before returning. */
3319 pa_output_function_epilogue (file, size)
3321 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3323 rtx insn = get_last_insn ();
3325 /* hppa_expand_epilogue does the dirty work now. We just need
3326 to output the assembler directives which denote the end
3329 To make debuggers happy, emit a nop if the epilogue was completely
3330 eliminated due to a volatile call as the last insn in the
3331 current function. That way the return address (in %r2) will
3332 always point to a valid instruction in the current function. */
3334 /* Get the last real insn. */
3335 if (GET_CODE (insn) == NOTE)
3336 insn = prev_real_insn (insn);
3338 /* If it is a sequence, then look inside. */
3339 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3340 insn = XVECEXP (PATTERN (insn), 0, 0);
3342 /* If insn is a CALL_INSN, then it must be a call to a volatile
3343 function (otherwise there would be epilogue insns). */
3344 if (insn && GET_CODE (insn) == CALL_INSN)
3345 fputs ("\tnop\n", file);
3347 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3351 hppa_expand_epilogue ()
3355 int merge_sp_adjust_with_load = 0;
3358 /* We will use this often. */
3359 tmpreg = gen_rtx_REG (word_mode, 1);
3361 /* Try to restore RP early to avoid load/use interlocks when
3362 RP gets used in the return (bv) instruction. This appears to still
3363 be necessary even when we schedule the prologue and epilogue. */
3364 if (regs_ever_live [2])
3366 ret_off = TARGET_64BIT ? -16 : -20;
3367 if (frame_pointer_needed)
3369 FRP (load_reg (2, ret_off, FRAME_POINTER_REGNUM));
3374 /* No frame pointer, and stack is smaller than 8k. */
3375 if (VAL_14_BITS_P (ret_off - actual_fsize))
3377 FRP (load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM));
3383 /* General register restores. */
3384 if (frame_pointer_needed)
3386 for (i = 18, offset = local_fsize; i >= 4; i--)
3387 if (regs_ever_live[i] && ! call_used_regs[i])
3389 FRP (load_reg (i, offset, FRAME_POINTER_REGNUM));
3390 offset += UNITS_PER_WORD;
3395 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3397 if (regs_ever_live[i] && ! call_used_regs[i])
3399 /* Only for the first load.
3400 merge_sp_adjust_with_load holds the register load
3401 with which we will merge the sp adjustment. */
3402 if (merge_sp_adjust_with_load == 0
3404 && VAL_14_BITS_P (-actual_fsize))
3405 merge_sp_adjust_with_load = i;
3407 FRP (load_reg (i, offset, STACK_POINTER_REGNUM));
3408 offset += UNITS_PER_WORD;
3413 /* Align pointer properly (doubleword boundary). */
3414 offset = (offset + 7) & ~7;
3416 /* FP register restores. */
3419 /* Adjust the register to index off of. */
3420 if (frame_pointer_needed)
3421 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset));
3423 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM, offset));
3425 /* Actually do the restores now. */
3426 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3427 if (regs_ever_live[i]
3428 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3430 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3431 rtx dest = gen_rtx_REG (DFmode, i);
3432 FRP (emit_move_insn (dest, src));
3436 /* Emit a blockage insn here to keep these insns from being moved to
3437 an earlier spot in the epilogue, or into the main instruction stream.
3439 This is necessary as we must not cut the stack back before all the
3440 restores are finished. */
3441 emit_insn (gen_blockage ());
3443 /* Reset stack pointer (and possibly frame pointer). The stack
3444 pointer is initially set to fp + 64 to avoid a race condition. */
3445 if (frame_pointer_needed)
3447 rtx delta = GEN_INT (-64);
3448 FRP (set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64));
3449 FRP (emit_insn (gen_pre_load (frame_pointer_rtx,
3453 /* If we were deferring a callee register restore, do it now. */
3454 else if (merge_sp_adjust_with_load)
3456 rtx delta = GEN_INT (-actual_fsize);
3457 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3458 FRP (emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)));
3460 else if (actual_fsize != 0)
3461 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3462 STACK_POINTER_REGNUM,
3465 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3466 frame greater than 8k), do so now. */
3468 FRP (load_reg (2, ret_off, STACK_POINTER_REGNUM));
3472 hppa_pic_save_rtx ()
3474 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3478 hppa_profile_hook (label_no)
3479 int label_no ATTRIBUTE_UNUSED;
3481 rtx begin_label_rtx, call_insn;
3482 char begin_label_name[16];
3484 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3485 current_function_number);
3486 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3489 emit_move_insn (arg_pointer_rtx,
3490 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3493 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3495 #ifndef NO_PROFILE_COUNTERS
3497 rtx count_label_rtx, addr, r24;
3498 char count_label_name[16];
3500 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3501 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3507 current_function_uses_pic_offset_table = 1;
3508 tmpreg = gen_rtx_REG (Pmode, 1);
3509 emit_move_insn (tmpreg,
3510 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3511 gen_rtx_HIGH (Pmode, count_label_rtx)));
3512 addr = gen_rtx_MEM (Pmode,
3513 gen_rtx_LO_SUM (Pmode, tmpreg, count_label_rtx));
3517 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3518 emit_move_insn (tmpreg, gen_rtx_HIGH (Pmode, count_label_rtx));
3519 addr = gen_rtx_LO_SUM (Pmode, tmpreg, count_label_rtx);
3521 r24 = gen_rtx_REG (Pmode, 24);
3522 emit_move_insn (r24, addr);
3524 /* %r25 is set from within the output pattern. */
3526 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3527 GEN_INT (TARGET_64BIT ? 24 : 12),
3530 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3533 /* %r25 is set from within the output pattern. */
3535 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3536 GEN_INT (TARGET_64BIT ? 16 : 8),
3540 /* Indicate the _mcount call cannot throw, nor will it execute a
3542 REG_NOTES (call_insn)
3543 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3547 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3549 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3551 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3555 /* Fetch the return address for the frame COUNT steps up from
3556 the current frame, after the prologue. FRAMEADDR is the
3557 frame pointer of the COUNT frame.
3559 We want to ignore any export stub remnants here. To handle this,
3560 we examine the code at the return address, and if it is an export
3561 stub, we return a memory rtx for the stub return address stored
3564 The value returned is used in two different ways:
3566 1. To find a function's caller.
3568 2. To change the return address for a function.
3570 This function handles most instances of case 1; however, it will
3571 fail if there are two levels of stubs to execute on the return
3572 path. The only way I believe that can happen is if the return value
3573 needs a parameter relocation, which never happens for C code.
3575 This function handles most instances of case 2; however, it will
3576 fail if we did not originally have stub code on the return path
3577 but will need stub code on the new return path. This can happen if
3578 the caller & callee are both in the main program, but the new
3579 return location is in a shared library. */
3582 return_addr_rtx (count, frameaddr)
3594 rp = get_hard_reg_initial_val (Pmode, 2);
3596 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
3599 saved_rp = gen_reg_rtx (Pmode);
3600 emit_move_insn (saved_rp, rp);
3602 /* Get pointer to the instruction stream. We have to mask out the
3603 privilege level from the two low order bits of the return address
3604 pointer here so that ins will point to the start of the first
3605 instruction that would have been executed if we returned. */
3606 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
3607 label = gen_label_rtx ();
3609 /* Check the instruction stream at the normal return address for the
3612 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3613 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3614 0x00011820 | stub+16: mtsp r1,sr0
3615 0xe0400002 | stub+20: be,n 0(sr0,rp)
3617 If it is an export stub, than our return address is really in
3620 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
3621 NULL_RTX, SImode, 1);
3622 emit_jump_insn (gen_bne (label));
3624 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3625 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
3626 emit_jump_insn (gen_bne (label));
3628 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3629 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
3630 emit_jump_insn (gen_bne (label));
3632 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3633 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
3635 /* If there is no export stub then just use the value saved from
3636 the return pointer register. */
3638 emit_jump_insn (gen_bne (label));
3640 /* Here we know that our return address points to an export
3641 stub. We don't want to return the address of the export stub,
3642 but rather the return address of the export stub. That return
3643 address is stored at -24[frameaddr]. */
3645 emit_move_insn (saved_rp,
3647 memory_address (Pmode,
3648 plus_constant (frameaddr,
3655 /* This is only valid once reload has completed because it depends on
3656 knowing exactly how much (if any) frame there is and...
3658 It's only valid if there is no frame marker to de-allocate and...
3660 It's only valid if %r2 hasn't been saved into the caller's frame
3661 (we're not profiling and %r2 isn't live anywhere). */
3663 hppa_can_use_return_insn_p ()
3665 return (reload_completed
3666 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3667 && ! regs_ever_live[2]
3668 && ! frame_pointer_needed);
3672 emit_bcond_fp (code, operand0)
3676 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3677 gen_rtx_IF_THEN_ELSE (VOIDmode,
3678 gen_rtx_fmt_ee (code,
3680 gen_rtx_REG (CCFPmode, 0),
3682 gen_rtx_LABEL_REF (VOIDmode, operand0),
3688 gen_cmp_fp (code, operand0, operand1)
3690 rtx operand0, operand1;
3692 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3693 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3696 /* Adjust the cost of a scheduling dependency. Return the new cost of
3697 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3700 pa_adjust_cost (insn, link, dep_insn, cost)
3706 enum attr_type attr_type;
3708 /* Don't adjust costs for a pa8000 chip. */
3709 if (pa_cpu >= PROCESSOR_8000)
3712 if (! recog_memoized (insn))
3715 attr_type = get_attr_type (insn);
3717 if (REG_NOTE_KIND (link) == 0)
3719 /* Data dependency; DEP_INSN writes a register that INSN reads some
3722 if (attr_type == TYPE_FPSTORE)
3724 rtx pat = PATTERN (insn);
3725 rtx dep_pat = PATTERN (dep_insn);
3726 if (GET_CODE (pat) == PARALLEL)
3728 /* This happens for the fstXs,mb patterns. */
3729 pat = XVECEXP (pat, 0, 0);
3731 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3732 /* If this happens, we have to extend this to schedule
3733 optimally. Return 0 for now. */
3736 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
3738 if (! recog_memoized (dep_insn))
3740 /* DEP_INSN is writing its result to the register
3741 being stored in the fpstore INSN. */
3742 switch (get_attr_type (dep_insn))
3745 /* This cost 3 cycles, not 2 as the md says for the
3754 case TYPE_FPSQRTSGL:
3755 case TYPE_FPSQRTDBL:
3756 /* In these important cases, we save one cycle compared to
3757 when flop instruction feed each other. */
3766 /* For other data dependencies, the default cost specified in the
3770 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3772 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3775 if (attr_type == TYPE_FPLOAD)
3777 rtx pat = PATTERN (insn);
3778 rtx dep_pat = PATTERN (dep_insn);
3779 if (GET_CODE (pat) == PARALLEL)
3781 /* This happens for the fldXs,mb patterns. */
3782 pat = XVECEXP (pat, 0, 0);
3784 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3785 /* If this happens, we have to extend this to schedule
3786 optimally. Return 0 for now. */
3789 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3791 if (! recog_memoized (dep_insn))
3793 switch (get_attr_type (dep_insn))
3800 case TYPE_FPSQRTSGL:
3801 case TYPE_FPSQRTDBL:
3802 /* A fpload can't be issued until one cycle before a
3803 preceding arithmetic operation has finished if
3804 the target of the fpload is any of the sources
3805 (or destination) of the arithmetic operation. */
3813 else if (attr_type == TYPE_FPALU)
3815 rtx pat = PATTERN (insn);
3816 rtx dep_pat = PATTERN (dep_insn);
3817 if (GET_CODE (pat) == PARALLEL)
3819 /* This happens for the fldXs,mb patterns. */
3820 pat = XVECEXP (pat, 0, 0);
3822 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3823 /* If this happens, we have to extend this to schedule
3824 optimally. Return 0 for now. */
3827 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3829 if (! recog_memoized (dep_insn))
3831 switch (get_attr_type (dep_insn))
3835 case TYPE_FPSQRTSGL:
3836 case TYPE_FPSQRTDBL:
3837 /* An ALU flop can't be issued until two cycles before a
3838 preceding divide or sqrt operation has finished if
3839 the target of the ALU flop is any of the sources
3840 (or destination) of the divide or sqrt operation. */
3849 /* For other anti dependencies, the cost is 0. */
3852 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3854 /* Output dependency; DEP_INSN writes a register that INSN writes some
3856 if (attr_type == TYPE_FPLOAD)
3858 rtx pat = PATTERN (insn);
3859 rtx dep_pat = PATTERN (dep_insn);
3860 if (GET_CODE (pat) == PARALLEL)
3862 /* This happens for the fldXs,mb patterns. */
3863 pat = XVECEXP (pat, 0, 0);
3865 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3866 /* If this happens, we have to extend this to schedule
3867 optimally. Return 0 for now. */
3870 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3872 if (! recog_memoized (dep_insn))
3874 switch (get_attr_type (dep_insn))
3881 case TYPE_FPSQRTSGL:
3882 case TYPE_FPSQRTDBL:
3883 /* A fpload can't be issued until one cycle before a
3884 preceding arithmetic operation has finished if
3885 the target of the fpload is the destination of the
3886 arithmetic operation. */
3894 else if (attr_type == TYPE_FPALU)
3896 rtx pat = PATTERN (insn);
3897 rtx dep_pat = PATTERN (dep_insn);
3898 if (GET_CODE (pat) == PARALLEL)
3900 /* This happens for the fldXs,mb patterns. */
3901 pat = XVECEXP (pat, 0, 0);
3903 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3904 /* If this happens, we have to extend this to schedule
3905 optimally. Return 0 for now. */
3908 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3910 if (! recog_memoized (dep_insn))
3912 switch (get_attr_type (dep_insn))
3916 case TYPE_FPSQRTSGL:
3917 case TYPE_FPSQRTDBL:
3918 /* An ALU flop can't be issued until two cycles before a
3919 preceding divide or sqrt operation has finished if
3920 the target of the ALU flop is also the target of
3921 the divide or sqrt operation. */
3930 /* For other output dependencies, the cost is 0. */
3937 /* Adjust scheduling priorities. We use this to try and keep addil
3938 and the next use of %r1 close together. */
3940 pa_adjust_priority (insn, priority)
3944 rtx set = single_set (insn);
3948 src = SET_SRC (set);
3949 dest = SET_DEST (set);
3950 if (GET_CODE (src) == LO_SUM
3951 && symbolic_operand (XEXP (src, 1), VOIDmode)
3952 && ! read_only_operand (XEXP (src, 1), VOIDmode))
3955 else if (GET_CODE (src) == MEM
3956 && GET_CODE (XEXP (src, 0)) == LO_SUM
3957 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
3958 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
3961 else if (GET_CODE (dest) == MEM
3962 && GET_CODE (XEXP (dest, 0)) == LO_SUM
3963 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
3964 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
3970 /* The 700 can only issue a single insn at a time.
3971 The 7XXX processors can issue two insns at a time.
3972 The 8000 can issue 4 insns at a time. */
3978 case PROCESSOR_700: return 1;
3979 case PROCESSOR_7100: return 2;
3980 case PROCESSOR_7100LC: return 2;
3981 case PROCESSOR_7200: return 2;
3982 case PROCESSOR_8000: return 4;
3991 /* Return any length adjustment needed by INSN which already has its length
3992 computed as LENGTH. Return zero if no adjustment is necessary.
3994 For the PA: function calls, millicode calls, and backwards short
3995 conditional branches with unfilled delay slots need an adjustment by +1
3996 (to account for the NOP which will be inserted into the instruction stream).
3998 Also compute the length of an inline block move here as it is too
3999 complicated to express as a length attribute in pa.md. */
4001 pa_adjust_insn_length (insn, length)
4005 rtx pat = PATTERN (insn);
4007 /* Call insns which are *not* indirect and have unfilled delay slots. */
4008 if (GET_CODE (insn) == CALL_INSN)
4011 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4012 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4014 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4015 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4021 /* Jumps inside switch tables which have unfilled delay slots
4022 also need adjustment. */
4023 else if (GET_CODE (insn) == JUMP_INSN
4024 && simplejump_p (insn)
4025 && GET_MODE (insn) == SImode)
4027 /* Millicode insn with an unfilled delay slot. */
4028 else if (GET_CODE (insn) == INSN
4029 && GET_CODE (pat) != SEQUENCE
4030 && GET_CODE (pat) != USE
4031 && GET_CODE (pat) != CLOBBER
4032 && get_attr_type (insn) == TYPE_MILLI)
4034 /* Block move pattern. */
4035 else if (GET_CODE (insn) == INSN
4036 && GET_CODE (pat) == PARALLEL
4037 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4038 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4039 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4040 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4041 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4042 return compute_movstrsi_length (insn) - 4;
4043 /* Conditional branch with an unfilled delay slot. */
4044 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4046 /* Adjust a short backwards conditional with an unfilled delay slot. */
4047 if (GET_CODE (pat) == SET
4049 && ! forward_branch_p (insn))
4051 else if (GET_CODE (pat) == PARALLEL
4052 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4055 /* Adjust dbra insn with short backwards conditional branch with
4056 unfilled delay slot -- only for case where counter is in a
4057 general register register. */
4058 else if (GET_CODE (pat) == PARALLEL
4059 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4060 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4061 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4063 && ! forward_branch_p (insn))
4071 /* Print operand X (an rtx) in assembler syntax to file FILE.
4072 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4073 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4076 print_operand (file, x, code)
4084 /* Output a 'nop' if there's nothing for the delay slot. */
4085 if (dbr_sequence_length () == 0)
4086 fputs ("\n\tnop", file);
4089 /* Output an nullification completer if there's nothing for the */
4090 /* delay slot or nullification is requested. */
4091 if (dbr_sequence_length () == 0 ||
4093 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4097 /* Print out the second register name of a register pair.
4098 I.e., R (6) => 7. */
4099 fputs (reg_names[REGNO (x) + 1], file);
4102 /* A register or zero. */
4104 || (x == CONST0_RTX (DFmode))
4105 || (x == CONST0_RTX (SFmode)))
4107 fputs ("%r0", file);
4113 /* A register or zero (floating point). */
4115 || (x == CONST0_RTX (DFmode))
4116 || (x == CONST0_RTX (SFmode)))
4118 fputs ("%fr0", file);
4127 xoperands[0] = XEXP (XEXP (x, 0), 0);
4128 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4129 output_global_address (file, xoperands[1], 0);
4130 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4134 case 'C': /* Plain (C)ondition */
4136 switch (GET_CODE (x))
4139 fputs ("=", file); break;
4141 fputs ("<>", file); break;
4143 fputs (">", file); break;
4145 fputs (">=", file); break;
4147 fputs (">>=", file); break;
4149 fputs (">>", file); break;
4151 fputs ("<", file); break;
4153 fputs ("<=", file); break;
4155 fputs ("<<=", file); break;
4157 fputs ("<<", file); break;
4162 case 'N': /* Condition, (N)egated */
4163 switch (GET_CODE (x))
4166 fputs ("<>", file); break;
4168 fputs ("=", file); break;
4170 fputs ("<=", file); break;
4172 fputs ("<", file); break;
4174 fputs ("<<", file); break;
4176 fputs ("<<=", file); break;
4178 fputs (">=", file); break;
4180 fputs (">", file); break;
4182 fputs (">>", file); break;
4184 fputs (">>=", file); break;
4189 /* For floating point comparisons. Note that the output
4190 predicates are the complement of the desired mode. */
4192 switch (GET_CODE (x))
4195 fputs ("!=", file); break;
4197 fputs ("=", file); break;
4199 fputs ("!>", file); break;
4201 fputs ("!>=", file); break;
4203 fputs ("!<", file); break;
4205 fputs ("!<=", file); break;
4207 fputs ("!<>", file); break;
4209 fputs (">", file); break;
4211 fputs (">=", file); break;
4213 fputs ("<", file); break;
4215 fputs ("<=", file); break;
4217 fputs ("<>", file); break;
4219 fputs ("<=>", file); break;
4221 fputs ("!<=>", file); break;
4226 case 'S': /* Condition, operands are (S)wapped. */
4227 switch (GET_CODE (x))
4230 fputs ("=", file); break;
4232 fputs ("<>", file); break;
4234 fputs ("<", file); break;
4236 fputs ("<=", file); break;
4238 fputs ("<<=", file); break;
4240 fputs ("<<", file); break;
4242 fputs (">", file); break;
4244 fputs (">=", file); break;
4246 fputs (">>=", file); break;
4248 fputs (">>", file); break;
4253 case 'B': /* Condition, (B)oth swapped and negate. */
4254 switch (GET_CODE (x))
4257 fputs ("<>", file); break;
4259 fputs ("=", file); break;
4261 fputs (">=", file); break;
4263 fputs (">", file); break;
4265 fputs (">>", file); break;
4267 fputs (">>=", file); break;
4269 fputs ("<=", file); break;
4271 fputs ("<", file); break;
4273 fputs ("<<", file); break;
4275 fputs ("<<=", file); break;
4281 if (GET_CODE (x) == CONST_INT)
4283 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4288 if (GET_CODE (x) == CONST_INT)
4290 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4295 if (GET_CODE (x) == CONST_INT)
4297 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4302 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4304 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4309 if (GET_CODE (x) == CONST_INT)
4311 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4316 if (GET_CODE (x) == CONST_INT)
4318 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4323 if (GET_CODE (x) == CONST_INT)
4328 switch (GET_CODE (XEXP (x, 0)))
4332 if (ASSEMBLER_DIALECT == 0)
4333 fputs ("s,mb", file);
4335 fputs (",mb", file);
4339 if (ASSEMBLER_DIALECT == 0)
4340 fputs ("s,ma", file);
4342 fputs (",ma", file);
4345 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4346 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4348 if (ASSEMBLER_DIALECT == 0)
4349 fputs ("x,s", file);
4353 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4357 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4363 output_global_address (file, x, 0);
4366 output_global_address (file, x, 1);
4368 case 0: /* Don't do anything special */
4373 compute_zdepwi_operands (INTVAL (x), op);
4374 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4380 compute_zdepdi_operands (INTVAL (x), op);
4381 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4385 /* We can get here from a .vtable_inherit due to our
4386 CONSTANT_ADDRESS_P rejecting perfectly good constant
4392 if (GET_CODE (x) == REG)
4394 fputs (reg_names [REGNO (x)], file);
4395 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4401 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4402 && (REGNO (x) & 1) == 0)
4405 else if (GET_CODE (x) == MEM)
4407 int size = GET_MODE_SIZE (GET_MODE (x));
4408 rtx base = NULL_RTX;
4409 switch (GET_CODE (XEXP (x, 0)))
4413 base = XEXP (XEXP (x, 0), 0);
4414 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4418 base = XEXP (XEXP (x, 0), 0);
4419 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4422 if (GET_CODE (XEXP (x, 0)) == PLUS
4423 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4424 fprintf (file, "%s(%s)",
4425 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4426 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4427 else if (GET_CODE (XEXP (x, 0)) == PLUS
4428 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4429 fprintf (file, "%s(%s)",
4430 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4431 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4433 output_address (XEXP (x, 0));
4438 output_addr_const (file, x);
4441 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4444 output_global_address (file, x, round_constant)
4450 /* Imagine (high (const (plus ...))). */
4451 if (GET_CODE (x) == HIGH)
4454 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4455 assemble_name (file, XSTR (x, 0));
4456 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4458 assemble_name (file, XSTR (x, 0));
4459 fputs ("-$global$", file);
4461 else if (GET_CODE (x) == CONST)
4463 const char *sep = "";
4464 int offset = 0; /* assembler wants -$global$ at end */
4465 rtx base = NULL_RTX;
4467 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4469 base = XEXP (XEXP (x, 0), 0);
4470 output_addr_const (file, base);
4472 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4473 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4476 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4478 base = XEXP (XEXP (x, 0), 1);
4479 output_addr_const (file, base);
4481 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4482 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4485 /* How bogus. The compiler is apparently responsible for
4486 rounding the constant if it uses an LR field selector.
4488 The linker and/or assembler seem a better place since
4489 they have to do this kind of thing already.
4491 If we fail to do this, HP's optimizing linker may eliminate
4492 an addil, but not update the ldw/stw/ldo instruction that
4493 uses the result of the addil. */
4495 offset = ((offset + 0x1000) & ~0x1fff);
4497 if (GET_CODE (XEXP (x, 0)) == PLUS)
4507 else if (GET_CODE (XEXP (x, 0)) == MINUS
4508 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4512 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4513 fputs ("-$global$", file);
4515 fprintf (file, "%s%d", sep, offset);
4518 output_addr_const (file, x);
4522 output_deferred_plabels (file)
4526 /* If we have deferred plabels, then we need to switch into the data
4527 section and align it to a 4 byte boundary before we output the
4528 deferred plabels. */
4529 if (n_deferred_plabels)
4532 ASM_OUTPUT_ALIGN (file, 2);
4535 /* Now output the deferred plabels. */
4536 for (i = 0; i < n_deferred_plabels; i++)
4538 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4539 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4544 /* HP's millicode routines mean something special to the assembler.
4545 Keep track of which ones we have used. */
4547 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
4548 static void import_milli PARAMS ((enum millicodes));
4549 static char imported[(int) end1000];
4550 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4551 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4552 #define MILLI_START 10
4556 enum millicodes code;
4558 char str[sizeof (import_string)];
4560 if (!imported[(int) code])
4562 imported[(int) code] = 1;
4563 strcpy (str, import_string);
4564 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4565 output_asm_insn (str, 0);
4569 /* The register constraints have put the operands and return value in
4570 the proper registers. */
4573 output_mul_insn (unsignedp, insn)
4574 int unsignedp ATTRIBUTE_UNUSED;
4577 import_milli (mulI);
4578 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4581 /* Emit the rtl for doing a division by a constant. */
4583 /* Do magic division millicodes exist for this value? */
4584 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4587 /* We'll use an array to keep track of the magic millicodes and
4588 whether or not we've used them already. [n][0] is signed, [n][1] is
4591 static int div_milli[16][2];
4594 div_operand (op, mode)
4596 enum machine_mode mode;
4598 return (mode == SImode
4599 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4600 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4601 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4605 emit_hpdiv_const (operands, unsignedp)
4609 if (GET_CODE (operands[2]) == CONST_INT
4610 && INTVAL (operands[2]) > 0
4611 && INTVAL (operands[2]) < 16
4612 && magic_milli[INTVAL (operands[2])])
4614 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4616 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4619 (PARALLEL, VOIDmode,
4620 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4621 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4623 gen_rtx_REG (SImode, 26),
4625 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4626 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4627 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4628 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4629 gen_rtx_CLOBBER (VOIDmode, ret))));
4630 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4637 output_div_insn (operands, unsignedp, insn)
4644 /* If the divisor is a constant, try to use one of the special
4646 if (GET_CODE (operands[0]) == CONST_INT)
4648 static char buf[100];
4649 divisor = INTVAL (operands[0]);
4650 if (!div_milli[divisor][unsignedp])
4652 div_milli[divisor][unsignedp] = 1;
4654 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4656 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4660 sprintf (buf, "$$divU_");
4661 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4662 return output_millicode_call (insn,
4663 gen_rtx_SYMBOL_REF (SImode, buf));
4667 sprintf (buf, "$$divI_");
4668 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4669 return output_millicode_call (insn,
4670 gen_rtx_SYMBOL_REF (SImode, buf));
4673 /* Divisor isn't a special constant. */
4678 import_milli (divU);
4679 return output_millicode_call (insn,
4680 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4684 import_milli (divI);
4685 return output_millicode_call (insn,
4686 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4691 /* Output a $$rem millicode to do mod. */
4694 output_mod_insn (unsignedp, insn)
4700 import_milli (remU);
4701 return output_millicode_call (insn,
4702 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4706 import_milli (remI);
4707 return output_millicode_call (insn,
4708 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4713 output_arg_descriptor (call_insn)
4716 const char *arg_regs[4];
4717 enum machine_mode arg_mode;
4719 int i, output_flag = 0;
4722 /* We neither need nor want argument location descriptors for the
4723 64bit runtime environment or the ELF32 environment. */
4724 if (TARGET_64BIT || TARGET_ELF32)
4727 for (i = 0; i < 4; i++)
4730 /* Specify explicitly that no argument relocations should take place
4731 if using the portable runtime calling conventions. */
4732 if (TARGET_PORTABLE_RUNTIME)
4734 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4739 if (GET_CODE (call_insn) != CALL_INSN)
4741 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4743 rtx use = XEXP (link, 0);
4745 if (! (GET_CODE (use) == USE
4746 && GET_CODE (XEXP (use, 0)) == REG
4747 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4750 arg_mode = GET_MODE (XEXP (use, 0));
4751 regno = REGNO (XEXP (use, 0));
4752 if (regno >= 23 && regno <= 26)
4754 arg_regs[26 - regno] = "GR";
4755 if (arg_mode == DImode)
4756 arg_regs[25 - regno] = "GR";
4758 else if (regno >= 32 && regno <= 39)
4760 if (arg_mode == SFmode)
4761 arg_regs[(regno - 32) / 2] = "FR";
4764 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4765 arg_regs[(regno - 34) / 2] = "FR";
4766 arg_regs[(regno - 34) / 2 + 1] = "FU";
4768 arg_regs[(regno - 34) / 2] = "FU";
4769 arg_regs[(regno - 34) / 2 + 1] = "FR";
4774 fputs ("\t.CALL ", asm_out_file);
4775 for (i = 0; i < 4; i++)
4780 fputc (',', asm_out_file);
4781 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4784 fputc ('\n', asm_out_file);
4787 /* Return the class of any secondary reload register that is needed to
4788 move IN into a register in class CLASS using mode MODE.
4790 Profiling has showed this routine and its descendants account for
4791 a significant amount of compile time (~7%). So it has been
4792 optimized to reduce redundant computations and eliminate useless
4795 It might be worthwhile to try and make this a leaf function too. */
4798 secondary_reload_class (class, mode, in)
4799 enum reg_class class;
4800 enum machine_mode mode;
4803 int regno, is_symbolic;
4805 /* Trying to load a constant into a FP register during PIC code
4806 generation will require %r1 as a scratch register. */
4808 && GET_MODE_CLASS (mode) == MODE_INT
4809 && FP_REG_CLASS_P (class)
4810 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4813 /* Profiling showed the PA port spends about 1.3% of its compilation
4814 time in true_regnum from calls inside secondary_reload_class. */
4816 if (GET_CODE (in) == REG)
4819 if (regno >= FIRST_PSEUDO_REGISTER)
4820 regno = true_regnum (in);
4822 else if (GET_CODE (in) == SUBREG)
4823 regno = true_regnum (in);
4827 /* If we have something like (mem (mem (...)), we can safely assume the
4828 inner MEM will end up in a general register after reloading, so there's
4829 no need for a secondary reload. */
4830 if (GET_CODE (in) == MEM
4831 && GET_CODE (XEXP (in, 0)) == MEM)
4834 /* Handle out of range displacement for integer mode loads/stores of
4836 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
4837 && GET_MODE_CLASS (mode) == MODE_INT
4838 && FP_REG_CLASS_P (class))
4839 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
4840 return GENERAL_REGS;
4842 /* A SAR<->FP register copy requires a secondary register (GPR) as
4843 well as secondary memory. */
4844 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4845 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
4846 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
4847 return GENERAL_REGS;
4849 if (GET_CODE (in) == HIGH)
4852 /* Profiling has showed GCC spends about 2.6% of its compilation
4853 time in symbolic_operand from calls inside secondary_reload_class.
4855 We use an inline copy and only compute its return value once to avoid
4857 switch (GET_CODE (in))
4867 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
4868 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
4869 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
4879 && read_only_operand (in, VOIDmode))
4882 if (class != R1_REGS && is_symbolic)
4889 function_arg_padding (mode, type)
4890 enum machine_mode mode;
4895 if (mode == BLKmode)
4897 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4898 size = int_size_in_bytes (type) * BITS_PER_UNIT;
4900 return upward; /* Don't know if this is right, but */
4901 /* same as old definition. */
4904 size = GET_MODE_BITSIZE (mode);
4905 if (size < PARM_BOUNDARY)
4907 else if (size % PARM_BOUNDARY)
4914 /* Do what is necessary for `va_start'. We look at the current function
4915 to determine if stdargs or varargs is used and fill in an initial
4916 va_list. A pointer to this constructor is returned. */
4919 hppa_builtin_saveregs ()
4922 tree fntype = TREE_TYPE (current_function_decl);
4923 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
4924 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4925 != void_type_node)))
4926 ? UNITS_PER_WORD : 0);
4929 offset = plus_constant (current_function_arg_offset_rtx, argadj);
4931 offset = current_function_arg_offset_rtx;
4937 /* Adjust for varargs/stdarg differences. */
4939 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
4941 offset = current_function_arg_offset_rtx;
4943 /* We need to save %r26 .. %r19 inclusive starting at offset -64
4944 from the incoming arg pointer and growing to larger addresses. */
4945 for (i = 26, off = -64; i >= 19; i--, off += 8)
4946 emit_move_insn (gen_rtx_MEM (word_mode,
4947 plus_constant (arg_pointer_rtx, off)),
4948 gen_rtx_REG (word_mode, i));
4950 /* The incoming args pointer points just beyond the flushback area;
4951 normally this is not a serious concern. However, when we are doing
4952 varargs/stdargs we want to make the arg pointer point to the start
4953 of the incoming argument area. */
4954 emit_move_insn (virtual_incoming_args_rtx,
4955 plus_constant (arg_pointer_rtx, -64));
4957 /* Now return a pointer to the first anonymous argument. */
4958 return copy_to_reg (expand_binop (Pmode, add_optab,
4959 virtual_incoming_args_rtx,
4960 offset, 0, 0, OPTAB_LIB_WIDEN));
4963 /* Store general registers on the stack. */
4964 dest = gen_rtx_MEM (BLKmode,
4965 plus_constant (current_function_internal_arg_pointer,
4967 set_mem_alias_set (dest, get_varargs_alias_set ());
4968 set_mem_align (dest, BITS_PER_WORD);
4969 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
4971 /* move_block_from_reg will emit code to store the argument registers
4972 individually as scalar stores.
4974 However, other insns may later load from the same addresses for
4975 a structure load (passing a struct to a varargs routine).
4977 The alias code assumes that such aliasing can never happen, so we
4978 have to keep memory referencing insns from moving up beyond the
4979 last argument register store. So we emit a blockage insn here. */
4980 emit_insn (gen_blockage ());
4982 return copy_to_reg (expand_binop (Pmode, add_optab,
4983 current_function_internal_arg_pointer,
4984 offset, 0, 0, OPTAB_LIB_WIDEN));
4988 hppa_va_start (stdarg_p, valist, nextarg)
4989 int stdarg_p ATTRIBUTE_UNUSED;
4993 nextarg = expand_builtin_saveregs ();
4994 std_expand_builtin_va_start (1, valist, nextarg);
4998 hppa_va_arg (valist, type)
5001 HOST_WIDE_INT align, size, ofs;
5006 /* Every argument in PA64 is passed by value (including large structs).
5007 Arguments with size greater than 8 must be aligned 0 MOD 16. */
5009 size = int_size_in_bytes (type);
5010 if (size > UNITS_PER_WORD)
5012 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5013 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5014 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5015 build_int_2 (-2 * UNITS_PER_WORD, -1));
5016 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5017 TREE_SIDE_EFFECTS (t) = 1;
5018 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5020 return std_expand_builtin_va_arg (valist, type);
5023 /* Compute the rounded size of the type. */
5024 align = PARM_BOUNDARY / BITS_PER_UNIT;
5025 size = int_size_in_bytes (type);
5027 ptr = build_pointer_type (type);
5029 /* "Large" types are passed by reference. */
5032 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5033 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5034 TREE_SIDE_EFFECTS (t) = 1;
5036 pptr = build_pointer_type (ptr);
5037 t = build1 (NOP_EXPR, pptr, t);
5038 TREE_SIDE_EFFECTS (t) = 1;
5040 t = build1 (INDIRECT_REF, ptr, t);
5041 TREE_SIDE_EFFECTS (t) = 1;
5045 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5046 build_int_2 (-size, -1));
5048 /* Copied from va-pa.h, but we probably don't need to align
5049 to word size, since we generate and preserve that invariant. */
5050 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5051 build_int_2 ((size > 4 ? -8 : -4), -1));
5053 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5054 TREE_SIDE_EFFECTS (t) = 1;
5056 ofs = (8 - size) % 4;
5059 t = build (PLUS_EXPR, TREE_TYPE (valist), t, build_int_2 (ofs, 0));
5060 TREE_SIDE_EFFECTS (t) = 1;
5063 t = build1 (NOP_EXPR, ptr, t);
5064 TREE_SIDE_EFFECTS (t) = 1;
5068 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
5073 /* This routine handles all the normal conditional branch sequences we
5074 might need to generate. It handles compare immediate vs compare
5075 register, nullification of delay slots, varying length branches,
5076 negated branches, and all combinations of the above. It returns the
5077 output appropriate to emit the branch corresponding to all given
5081 output_cbranch (operands, nullify, length, negated, insn)
5083 int nullify, length, negated;
5086 static char buf[100];
5089 /* A conditional branch to the following instruction (eg the delay slot) is
5090 asking for a disaster. This can happen when not optimizing.
5092 In such cases it is safe to emit nothing. */
5094 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5097 /* If this is a long branch with its delay slot unfilled, set `nullify'
5098 as it can nullify the delay slot and save a nop. */
5099 if (length == 8 && dbr_sequence_length () == 0)
5102 /* If this is a short forward conditional branch which did not get
5103 its delay slot filled, the delay slot can still be nullified. */
5104 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5105 nullify = forward_branch_p (insn);
5107 /* A forward branch over a single nullified insn can be done with a
5108 comclr instruction. This avoids a single cycle penalty due to
5109 mis-predicted branch if we fall through (branch not taken). */
5111 && next_real_insn (insn) != 0
5112 && get_attr_length (next_real_insn (insn)) == 4
5113 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5119 /* All short conditional branches except backwards with an unfilled
5123 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5125 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5126 if (GET_MODE (operands[1]) == DImode)
5129 strcat (buf, "%B3");
5131 strcat (buf, "%S3");
5133 strcat (buf, " %2,%r1,%%r0");
5135 strcat (buf, ",n %2,%r1,%0");
5137 strcat (buf, " %2,%r1,%0");
5140 /* All long conditionals. Note an short backward branch with an
5141 unfilled delay slot is treated just like a long backward branch
5142 with an unfilled delay slot. */
5144 /* Handle weird backwards branch with a filled delay slot
5145 with is nullified. */
5146 if (dbr_sequence_length () != 0
5147 && ! forward_branch_p (insn)
5150 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5151 if (GET_MODE (operands[1]) == DImode)
5154 strcat (buf, "%S3");
5156 strcat (buf, "%B3");
5157 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5159 /* Handle short backwards branch with an unfilled delay slot.
5160 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5161 taken and untaken branches. */
5162 else if (dbr_sequence_length () == 0
5163 && ! forward_branch_p (insn)
5164 && INSN_ADDRESSES_SET_P ()
5165 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5166 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5168 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5169 if (GET_MODE (operands[1]) == DImode)
5172 strcat (buf, "%B3 %2,%r1,%0%#");
5174 strcat (buf, "%S3 %2,%r1,%0%#");
5178 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5179 if (GET_MODE (operands[1]) == DImode)
5182 strcat (buf, "%S3");
5184 strcat (buf, "%B3");
5186 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5188 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5193 /* Very long branch. Right now we only handle these when not
5194 optimizing. See "jump" pattern in pa.md for details. */
5198 /* Create a reversed conditional branch which branches around
5199 the following insns. */
5201 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5203 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5204 if (GET_MODE (operands[1]) == DImode)
5208 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5211 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5213 output_asm_insn (buf, operands);
5215 /* Output an insn to save %r1. */
5216 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5218 /* Now output a very long branch to the original target. */
5219 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5221 /* Now restore the value of %r1 in the delay slot. We're not
5222 optimizing so we know nothing else can be in the delay slot. */
5223 return "ldw -16(%%r30),%%r1";
5226 /* Very long branch when generating PIC code. Right now we only
5227 handle these when not optimizing. See "jump" pattern in pa.md
5232 /* Create a reversed conditional branch which branches around
5233 the following insns. */
5235 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5237 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5238 if (GET_MODE (operands[1]) == DImode)
5241 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5243 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5245 output_asm_insn (buf, operands);
5247 /* Output an insn to save %r1. */
5248 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5250 /* Now output a very long PIC branch to the original target. */
5254 xoperands[0] = operands[0];
5255 xoperands[1] = operands[1];
5256 xoperands[2] = operands[2];
5257 xoperands[3] = operands[3];
5258 xoperands[4] = gen_label_rtx ();
5260 output_asm_insn ("{bl|b,l} .+8,%%r1\n\taddil L'%l0-%l4,%%r1",
5262 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5263 CODE_LABEL_NUMBER (xoperands[4]));
5264 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
5268 /* Now restore the value of %r1 in the delay slot. We're not
5269 optimizing so we know nothing else can be in the delay slot. */
5270 return "ldw -16(%%r30),%%r1";
5278 /* This routine handles all the branch-on-bit conditional branch sequences we
5279 might need to generate. It handles nullification of delay slots,
5280 varying length branches, negated branches and all combinations of the
5281 above. it returns the appropriate output template to emit the branch. */
5284 output_bb (operands, nullify, length, negated, insn, which)
5285 rtx *operands ATTRIBUTE_UNUSED;
5286 int nullify, length, negated;
5290 static char buf[100];
5293 /* A conditional branch to the following instruction (eg the delay slot) is
5294 asking for a disaster. I do not think this can happen as this pattern
5295 is only used when optimizing; jump optimization should eliminate the
5296 jump. But be prepared just in case. */
5298 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5301 /* If this is a long branch with its delay slot unfilled, set `nullify'
5302 as it can nullify the delay slot and save a nop. */
5303 if (length == 8 && dbr_sequence_length () == 0)
5306 /* If this is a short forward conditional branch which did not get
5307 its delay slot filled, the delay slot can still be nullified. */
5308 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5309 nullify = forward_branch_p (insn);
5311 /* A forward branch over a single nullified insn can be done with a
5312 extrs instruction. This avoids a single cycle penalty due to
5313 mis-predicted branch if we fall through (branch not taken). */
5316 && next_real_insn (insn) != 0
5317 && get_attr_length (next_real_insn (insn)) == 4
5318 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5325 /* All short conditional branches except backwards with an unfilled
5329 strcpy (buf, "{extrs,|extrw,s,}");
5331 strcpy (buf, "bb,");
5332 if (useskip && GET_MODE (operands[0]) == DImode)
5333 strcpy (buf, "extrd,s,*");
5334 else if (GET_MODE (operands[0]) == DImode)
5335 strcpy (buf, "bb,*");
5336 if ((which == 0 && negated)
5337 || (which == 1 && ! negated))
5342 strcat (buf, " %0,%1,1,%%r0");
5343 else if (nullify && negated)
5344 strcat (buf, ",n %0,%1,%3");
5345 else if (nullify && ! negated)
5346 strcat (buf, ",n %0,%1,%2");
5347 else if (! nullify && negated)
5348 strcat (buf, "%0,%1,%3");
5349 else if (! nullify && ! negated)
5350 strcat (buf, " %0,%1,%2");
5353 /* All long conditionals. Note an short backward branch with an
5354 unfilled delay slot is treated just like a long backward branch
5355 with an unfilled delay slot. */
5357 /* Handle weird backwards branch with a filled delay slot
5358 with is nullified. */
5359 if (dbr_sequence_length () != 0
5360 && ! forward_branch_p (insn)
5363 strcpy (buf, "bb,");
5364 if (GET_MODE (operands[0]) == DImode)
5366 if ((which == 0 && negated)
5367 || (which == 1 && ! negated))
5372 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5374 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5376 /* Handle short backwards branch with an unfilled delay slot.
5377 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5378 taken and untaken branches. */
5379 else if (dbr_sequence_length () == 0
5380 && ! forward_branch_p (insn)
5381 && INSN_ADDRESSES_SET_P ()
5382 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5383 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5385 strcpy (buf, "bb,");
5386 if (GET_MODE (operands[0]) == DImode)
5388 if ((which == 0 && negated)
5389 || (which == 1 && ! negated))
5394 strcat (buf, " %0,%1,%3%#");
5396 strcat (buf, " %0,%1,%2%#");
5400 strcpy (buf, "{extrs,|extrw,s,}");
5401 if (GET_MODE (operands[0]) == DImode)
5402 strcpy (buf, "extrd,s,*");
5403 if ((which == 0 && negated)
5404 || (which == 1 && ! negated))
5408 if (nullify && negated)
5409 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5410 else if (nullify && ! negated)
5411 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5413 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5415 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5425 /* This routine handles all the branch-on-variable-bit conditional branch
5426 sequences we might need to generate. It handles nullification of delay
5427 slots, varying length branches, negated branches and all combinations
5428 of the above. it returns the appropriate output template to emit the
5432 output_bvb (operands, nullify, length, negated, insn, which)
5433 rtx *operands ATTRIBUTE_UNUSED;
5434 int nullify, length, negated;
5438 static char buf[100];
5441 /* A conditional branch to the following instruction (eg the delay slot) is
5442 asking for a disaster. I do not think this can happen as this pattern
5443 is only used when optimizing; jump optimization should eliminate the
5444 jump. But be prepared just in case. */
5446 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5449 /* If this is a long branch with its delay slot unfilled, set `nullify'
5450 as it can nullify the delay slot and save a nop. */
5451 if (length == 8 && dbr_sequence_length () == 0)
5454 /* If this is a short forward conditional branch which did not get
5455 its delay slot filled, the delay slot can still be nullified. */
5456 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5457 nullify = forward_branch_p (insn);
5459 /* A forward branch over a single nullified insn can be done with a
5460 extrs instruction. This avoids a single cycle penalty due to
5461 mis-predicted branch if we fall through (branch not taken). */
5464 && next_real_insn (insn) != 0
5465 && get_attr_length (next_real_insn (insn)) == 4
5466 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5473 /* All short conditional branches except backwards with an unfilled
5477 strcpy (buf, "{vextrs,|extrw,s,}");
5479 strcpy (buf, "{bvb,|bb,}");
5480 if (useskip && GET_MODE (operands[0]) == DImode)
5481 strcpy (buf, "extrd,s,*}");
5482 else if (GET_MODE (operands[0]) == DImode)
5483 strcpy (buf, "bb,*");
5484 if ((which == 0 && negated)
5485 || (which == 1 && ! negated))
5490 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5491 else if (nullify && negated)
5492 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5493 else if (nullify && ! negated)
5494 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5495 else if (! nullify && negated)
5496 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5497 else if (! nullify && ! negated)
5498 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5501 /* All long conditionals. Note an short backward branch with an
5502 unfilled delay slot is treated just like a long backward branch
5503 with an unfilled delay slot. */
5505 /* Handle weird backwards branch with a filled delay slot
5506 with is nullified. */
5507 if (dbr_sequence_length () != 0
5508 && ! forward_branch_p (insn)
5511 strcpy (buf, "{bvb,|bb,}");
5512 if (GET_MODE (operands[0]) == DImode)
5514 if ((which == 0 && negated)
5515 || (which == 1 && ! negated))
5520 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5522 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5524 /* Handle short backwards branch with an unfilled delay slot.
5525 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5526 taken and untaken branches. */
5527 else if (dbr_sequence_length () == 0
5528 && ! forward_branch_p (insn)
5529 && INSN_ADDRESSES_SET_P ()
5530 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5531 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5533 strcpy (buf, "{bvb,|bb,}");
5534 if (GET_MODE (operands[0]) == DImode)
5536 if ((which == 0 && negated)
5537 || (which == 1 && ! negated))
5542 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5544 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5548 strcpy (buf, "{vextrs,|extrw,s,}");
5549 if (GET_MODE (operands[0]) == DImode)
5550 strcpy (buf, "extrd,s,*");
5551 if ((which == 0 && negated)
5552 || (which == 1 && ! negated))
5556 if (nullify && negated)
5557 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5558 else if (nullify && ! negated)
5559 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5561 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5563 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5573 /* Return the output template for emitting a dbra type insn.
5575 Note it may perform some output operations on its own before
5576 returning the final output string. */
5578 output_dbra (operands, insn, which_alternative)
5581 int which_alternative;
5584 /* A conditional branch to the following instruction (eg the delay slot) is
5585 asking for a disaster. Be prepared! */
5587 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5589 if (which_alternative == 0)
5590 return "ldo %1(%0),%0";
5591 else if (which_alternative == 1)
5593 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5594 output_asm_insn ("ldw -16(%%r30),%4", operands);
5595 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5596 return "{fldws|fldw} -16(%%r30),%0";
5600 output_asm_insn ("ldw %0,%4", operands);
5601 return "ldo %1(%4),%4\n\tstw %4,%0";
5605 if (which_alternative == 0)
5607 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5608 int length = get_attr_length (insn);
5610 /* If this is a long branch with its delay slot unfilled, set `nullify'
5611 as it can nullify the delay slot and save a nop. */
5612 if (length == 8 && dbr_sequence_length () == 0)
5615 /* If this is a short forward conditional branch which did not get
5616 its delay slot filled, the delay slot can still be nullified. */
5617 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5618 nullify = forward_branch_p (insn);
5620 /* Handle short versions first. */
5621 if (length == 4 && nullify)
5622 return "addib,%C2,n %1,%0,%3";
5623 else if (length == 4 && ! nullify)
5624 return "addib,%C2 %1,%0,%3";
5625 else if (length == 8)
5627 /* Handle weird backwards branch with a fulled delay slot
5628 which is nullified. */
5629 if (dbr_sequence_length () != 0
5630 && ! forward_branch_p (insn)
5632 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5633 /* Handle short backwards branch with an unfilled delay slot.
5634 Using a addb;nop rather than addi;bl saves 1 cycle for both
5635 taken and untaken branches. */
5636 else if (dbr_sequence_length () == 0
5637 && ! forward_branch_p (insn)
5638 && INSN_ADDRESSES_SET_P ()
5639 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5640 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5641 return "addib,%C2 %1,%0,%3%#";
5643 /* Handle normal cases. */
5645 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5647 return "addi,%N2 %1,%0,%0\n\tb %3";
5652 /* Deal with gross reload from FP register case. */
5653 else if (which_alternative == 1)
5655 /* Move loop counter from FP register to MEM then into a GR,
5656 increment the GR, store the GR into MEM, and finally reload
5657 the FP register from MEM from within the branch's delay slot. */
5658 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5660 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5661 if (get_attr_length (insn) == 24)
5662 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5664 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5666 /* Deal with gross reload from memory case. */
5669 /* Reload loop counter from memory, the store back to memory
5670 happens in the branch's delay slot. */
5671 output_asm_insn ("ldw %0,%4", operands);
5672 if (get_attr_length (insn) == 12)
5673 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5675 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5679 /* Return the output template for emitting a dbra type insn.
5681 Note it may perform some output operations on its own before
5682 returning the final output string. */
5684 output_movb (operands, insn, which_alternative, reverse_comparison)
5687 int which_alternative;
5688 int reverse_comparison;
5691 /* A conditional branch to the following instruction (eg the delay slot) is
5692 asking for a disaster. Be prepared! */
5694 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5696 if (which_alternative == 0)
5697 return "copy %1,%0";
5698 else if (which_alternative == 1)
5700 output_asm_insn ("stw %1,-16(%%r30)", operands);
5701 return "{fldws|fldw} -16(%%r30),%0";
5703 else if (which_alternative == 2)
5709 /* Support the second variant. */
5710 if (reverse_comparison)
5711 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5713 if (which_alternative == 0)
5715 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5716 int length = get_attr_length (insn);
5718 /* If this is a long branch with its delay slot unfilled, set `nullify'
5719 as it can nullify the delay slot and save a nop. */
5720 if (length == 8 && dbr_sequence_length () == 0)
5723 /* If this is a short forward conditional branch which did not get
5724 its delay slot filled, the delay slot can still be nullified. */
5725 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5726 nullify = forward_branch_p (insn);
5728 /* Handle short versions first. */
5729 if (length == 4 && nullify)
5730 return "movb,%C2,n %1,%0,%3";
5731 else if (length == 4 && ! nullify)
5732 return "movb,%C2 %1,%0,%3";
5733 else if (length == 8)
5735 /* Handle weird backwards branch with a filled delay slot
5736 which is nullified. */
5737 if (dbr_sequence_length () != 0
5738 && ! forward_branch_p (insn)
5740 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5742 /* Handle short backwards branch with an unfilled delay slot.
5743 Using a movb;nop rather than or;bl saves 1 cycle for both
5744 taken and untaken branches. */
5745 else if (dbr_sequence_length () == 0
5746 && ! forward_branch_p (insn)
5747 && INSN_ADDRESSES_SET_P ()
5748 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5749 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5750 return "movb,%C2 %1,%0,%3%#";
5751 /* Handle normal cases. */
5753 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5755 return "or,%N2 %1,%%r0,%0\n\tb %3";
5760 /* Deal with gross reload from FP register case. */
5761 else if (which_alternative == 1)
5763 /* Move loop counter from FP register to MEM then into a GR,
5764 increment the GR, store the GR into MEM, and finally reload
5765 the FP register from MEM from within the branch's delay slot. */
5766 output_asm_insn ("stw %1,-16(%%r30)", operands);
5767 if (get_attr_length (insn) == 12)
5768 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
5770 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5772 /* Deal with gross reload from memory case. */
5773 else if (which_alternative == 2)
5775 /* Reload loop counter from memory, the store back to memory
5776 happens in the branch's delay slot. */
5777 if (get_attr_length (insn) == 8)
5778 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
5780 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5782 /* Handle SAR as a destination. */
5785 if (get_attr_length (insn) == 8)
5786 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
5788 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5793 /* INSN is a millicode call. It may have an unconditional jump in its delay
5796 CALL_DEST is the routine we are calling. */
5799 output_millicode_call (insn, call_dest)
5807 xoperands[3] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
5809 /* Handle common case -- empty delay slot or no jump in the delay slot,
5810 and we're sure that the branch will reach the beginning of the $CODE$
5812 if ((dbr_sequence_length () == 0
5813 && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
5814 || (dbr_sequence_length () != 0
5815 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5816 && get_attr_length (insn) == 4))
5818 xoperands[0] = call_dest;
5819 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
5823 /* This call may not reach the beginning of the $CODE$ subspace. */
5824 if (get_attr_length (insn) > 4)
5826 int delay_insn_deleted = 0;
5828 /* We need to emit an inline long-call branch. */
5829 if (dbr_sequence_length () != 0
5830 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5832 /* A non-jump insn in the delay slot. By definition we can
5833 emit this insn before the call. */
5834 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5836 /* Now delete the delay insn. */
5837 PUT_CODE (NEXT_INSN (insn), NOTE);
5838 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5839 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5840 delay_insn_deleted = 1;
5843 /* PIC long millicode call sequence. */
5846 xoperands[0] = call_dest;
5847 xoperands[1] = gen_label_rtx ();
5848 /* Get our address + 8 into %r1. */
5849 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5851 /* Add %r1 to the offset of our target from the next insn. */
5852 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
5853 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5854 CODE_LABEL_NUMBER (xoperands[1]));
5855 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
5857 /* Get the return address into %r31. */
5858 output_asm_insn ("blr 0,%3", xoperands);
5860 /* Branch to our target which is in %r1. */
5861 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
5863 /* Empty delay slot. Note this insn gets fetched twice and
5864 executed once. To be safe we use a nop. */
5865 output_asm_insn ("nop", xoperands);
5867 /* Pure portable runtime doesn't allow be/ble; we also don't have
5868 PIC support in the assembler/linker, so this sequence is needed. */
5869 else if (TARGET_PORTABLE_RUNTIME)
5871 xoperands[0] = call_dest;
5872 /* Get the address of our target into %r29. */
5873 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
5874 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
5876 /* Get our return address into %r31. */
5877 output_asm_insn ("blr %%r0,%3", xoperands);
5879 /* Jump to our target address in %r29. */
5880 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
5882 /* Empty delay slot. Note this insn gets fetched twice and
5883 executed once. To be safe we use a nop. */
5884 output_asm_insn ("nop", xoperands);
5886 /* If we're allowed to use be/ble instructions, then this is the
5887 best sequence to use for a long millicode call. */
5890 xoperands[0] = call_dest;
5891 output_asm_insn ("ldil L%%%0,%3", xoperands);
5892 output_asm_insn ("{ble|be,l} R%%%0(%%sr4,%3)", xoperands);
5893 output_asm_insn ("nop", xoperands);
5896 /* If we had a jump in the call's delay slot, output it now. */
5897 if (dbr_sequence_length () != 0
5898 && !delay_insn_deleted)
5900 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5901 output_asm_insn ("b,n %0", xoperands);
5903 /* Now delete the delay insn. */
5904 PUT_CODE (NEXT_INSN (insn), NOTE);
5905 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5906 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5911 /* This call has an unconditional jump in its delay slot and the
5912 call is known to reach its target or the beginning of the current
5915 /* Use the containing sequence insn's address. */
5916 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5918 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
5919 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
5921 /* If the branch was too far away, emit a normal call followed
5922 by a nop, followed by the unconditional branch.
5924 If the branch is close, then adjust %r2 from within the
5925 call's delay slot. */
5927 xoperands[0] = call_dest;
5928 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5929 if (! VAL_14_BITS_P (distance))
5930 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
5933 xoperands[2] = gen_label_rtx ();
5934 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
5936 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5937 CODE_LABEL_NUMBER (xoperands[2]));
5940 /* Delete the jump. */
5941 PUT_CODE (NEXT_INSN (insn), NOTE);
5942 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5943 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5947 extern struct obstack permanent_obstack;
5949 /* INSN is either a function call. It may have an unconditional jump
5952 CALL_DEST is the routine we are calling. */
5955 output_call (insn, call_dest, sibcall)
5964 /* Handle common case -- empty delay slot or no jump in the delay slot,
5965 and we're sure that the branch will reach the beginning of the $CODE$
5967 if ((dbr_sequence_length () == 0
5968 && get_attr_length (insn) == 8)
5969 || (dbr_sequence_length () != 0
5970 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5971 && get_attr_length (insn) == 4))
5973 xoperands[0] = call_dest;
5974 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
5975 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
5979 /* This call may not reach the beginning of the $CODE$ subspace. */
5980 if (get_attr_length (insn) > 8)
5982 int delay_insn_deleted = 0;
5986 /* We need to emit an inline long-call branch. Furthermore,
5987 because we're changing a named function call into an indirect
5988 function call well after the parameters have been set up, we
5989 need to make sure any FP args appear in both the integer
5990 and FP registers. Also, we need move any delay slot insn
5991 out of the delay slot. And finally, we can't rely on the linker
5992 being able to fix the call to $$dyncall! -- Yuk!. */
5993 if (dbr_sequence_length () != 0
5994 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5996 /* A non-jump insn in the delay slot. By definition we can
5997 emit this insn before the call (and in fact before argument
5999 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6001 /* Now delete the delay insn. */
6002 PUT_CODE (NEXT_INSN (insn), NOTE);
6003 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6004 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6005 delay_insn_deleted = 1;
6008 /* Now copy any FP arguments into integer registers. */
6009 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6011 int arg_mode, regno;
6012 rtx use = XEXP (link, 0);
6013 if (! (GET_CODE (use) == USE
6014 && GET_CODE (XEXP (use, 0)) == REG
6015 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6018 arg_mode = GET_MODE (XEXP (use, 0));
6019 regno = REGNO (XEXP (use, 0));
6020 /* Is it a floating point register? */
6021 if (regno >= 32 && regno <= 39)
6023 /* Copy from the FP register into an integer register
6025 if (arg_mode == SFmode)
6027 xoperands[0] = XEXP (use, 0);
6028 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6029 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
6031 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6035 xoperands[0] = XEXP (use, 0);
6036 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6037 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
6039 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6040 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6045 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
6046 we don't have any direct calls in that case. */
6049 const char *name = XSTR (call_dest, 0);
6051 /* See if we have already put this function on the list
6052 of deferred plabels. This list is generally small,
6053 so a liner search is not too ugly. If it proves too
6054 slow replace it with something faster. */
6055 for (i = 0; i < n_deferred_plabels; i++)
6056 if (strcmp (name, deferred_plabels[i].name) == 0)
6059 /* If the deferred plabel list is empty, or this entry was
6060 not found on the list, create a new entry on the list. */
6061 if (deferred_plabels == NULL || i == n_deferred_plabels)
6063 const char *real_name;
6065 if (deferred_plabels == 0)
6066 deferred_plabels = (struct deferred_plabel *)
6067 xmalloc (1 * sizeof (struct deferred_plabel));
6069 deferred_plabels = (struct deferred_plabel *)
6070 xrealloc (deferred_plabels,
6071 ((n_deferred_plabels + 1)
6072 * sizeof (struct deferred_plabel)));
6074 i = n_deferred_plabels++;
6075 deferred_plabels[i].internal_label = gen_label_rtx ();
6076 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
6078 strcpy (deferred_plabels[i].name, name);
6080 /* Gross. We have just implicitly taken the address of this
6081 function, mark it as such. */
6082 STRIP_NAME_ENCODING (real_name, name);
6083 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
6086 /* We have to load the address of the function using a procedure
6087 label (plabel). Inline plabels can lose for PIC and other
6088 cases, so avoid them by creating a 32bit plabel in the data
6092 xoperands[0] = deferred_plabels[i].internal_label;
6093 xoperands[1] = gen_label_rtx ();
6095 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
6096 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
6097 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
6099 /* Get our address + 8 into %r1. */
6100 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6102 /* Add %r1 to the offset of dyncall from the next insn. */
6103 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
6104 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6105 CODE_LABEL_NUMBER (xoperands[1]));
6106 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
6108 /* Get the return address into %r31. */
6109 output_asm_insn ("blr %%r0,%%r31", xoperands);
6111 /* Branch to our target which is in %r1. */
6112 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6116 /* This call never returns, so we do not need to fix the
6118 output_asm_insn ("nop", xoperands);
6122 /* Copy the return address into %r2 also. */
6123 output_asm_insn ("copy %%r31,%%r2", xoperands);
6128 xoperands[0] = deferred_plabels[i].internal_label;
6130 /* Get the address of our target into %r22. */
6131 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
6132 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
6134 /* Get the high part of the address of $dyncall into %r2, then
6135 add in the low part in the branch instruction. */
6136 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
6137 output_asm_insn ("{ble|be,l} R%%$$dyncall(%%sr4,%%r2)",
6142 /* This call never returns, so we do not need to fix the
6144 output_asm_insn ("nop", xoperands);
6148 /* Copy the return address into %r2 also. */
6149 output_asm_insn ("copy %%r31,%%r2", xoperands);
6154 /* If we had a jump in the call's delay slot, output it now. */
6155 if (dbr_sequence_length () != 0
6156 && !delay_insn_deleted)
6158 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6159 output_asm_insn ("b,n %0", xoperands);
6161 /* Now delete the delay insn. */
6162 PUT_CODE (NEXT_INSN (insn), NOTE);
6163 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6164 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6169 /* This call has an unconditional jump in its delay slot and the
6170 call is known to reach its target or the beginning of the current
6173 /* Use the containing sequence insn's address. */
6174 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6176 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6177 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6179 /* If the branch was too far away, emit a normal call followed
6180 by a nop, followed by the unconditional branch.
6182 If the branch is close, then adjust %r2 from within the
6183 call's delay slot. */
6185 xoperands[0] = call_dest;
6186 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6187 if (! VAL_14_BITS_P (distance))
6188 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
6191 xoperands[3] = gen_label_rtx ();
6192 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6194 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6195 CODE_LABEL_NUMBER (xoperands[3]));
6198 /* Delete the jump. */
6199 PUT_CODE (NEXT_INSN (insn), NOTE);
6200 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6201 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6205 /* In HPUX 8.0's shared library scheme, special relocations are needed
6206 for function labels if they might be passed to a function
6207 in a shared library (because shared libraries don't live in code
6208 space), and special magic is needed to construct their address. */
6211 hppa_encode_label (sym)
6214 const char *str = XSTR (sym, 0);
6215 int len = strlen (str) + 1;
6218 p = newstr = alloca (len + 1);
6227 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6231 function_label_operand (op, mode)
6233 enum machine_mode mode ATTRIBUTE_UNUSED;
6235 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6238 /* Returns 1 if OP is a function label involved in a simple addition
6239 with a constant. Used to keep certain patterns from matching
6240 during instruction combination. */
6242 is_function_label_plus_const (op)
6245 /* Strip off any CONST. */
6246 if (GET_CODE (op) == CONST)
6249 return (GET_CODE (op) == PLUS
6250 && function_label_operand (XEXP (op, 0), Pmode)
6251 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6254 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6255 use in fmpyadd instructions. */
6257 fmpyaddoperands (operands)
6260 enum machine_mode mode = GET_MODE (operands[0]);
6262 /* Must be a floating point mode. */
6263 if (mode != SFmode && mode != DFmode)
6266 /* All modes must be the same. */
6267 if (! (mode == GET_MODE (operands[1])
6268 && mode == GET_MODE (operands[2])
6269 && mode == GET_MODE (operands[3])
6270 && mode == GET_MODE (operands[4])
6271 && mode == GET_MODE (operands[5])))
6274 /* All operands must be registers. */
6275 if (! (GET_CODE (operands[1]) == REG
6276 && GET_CODE (operands[2]) == REG
6277 && GET_CODE (operands[3]) == REG
6278 && GET_CODE (operands[4]) == REG
6279 && GET_CODE (operands[5]) == REG))
6282 /* Only 2 real operands to the addition. One of the input operands must
6283 be the same as the output operand. */
6284 if (! rtx_equal_p (operands[3], operands[4])
6285 && ! rtx_equal_p (operands[3], operands[5]))
6288 /* Inout operand of add can not conflict with any operands from multiply. */
6289 if (rtx_equal_p (operands[3], operands[0])
6290 || rtx_equal_p (operands[3], operands[1])
6291 || rtx_equal_p (operands[3], operands[2]))
6294 /* multiply can not feed into addition operands. */
6295 if (rtx_equal_p (operands[4], operands[0])
6296 || rtx_equal_p (operands[5], operands[0]))
6299 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6301 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6302 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6303 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6304 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6305 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6306 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6309 /* Passed. Operands are suitable for fmpyadd. */
6313 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6314 use in fmpysub instructions. */
6316 fmpysuboperands (operands)
6319 enum machine_mode mode = GET_MODE (operands[0]);
6321 /* Must be a floating point mode. */
6322 if (mode != SFmode && mode != DFmode)
6325 /* All modes must be the same. */
6326 if (! (mode == GET_MODE (operands[1])
6327 && mode == GET_MODE (operands[2])
6328 && mode == GET_MODE (operands[3])
6329 && mode == GET_MODE (operands[4])
6330 && mode == GET_MODE (operands[5])))
6333 /* All operands must be registers. */
6334 if (! (GET_CODE (operands[1]) == REG
6335 && GET_CODE (operands[2]) == REG
6336 && GET_CODE (operands[3]) == REG
6337 && GET_CODE (operands[4]) == REG
6338 && GET_CODE (operands[5]) == REG))
6341 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6342 operation, so operands[4] must be the same as operand[3]. */
6343 if (! rtx_equal_p (operands[3], operands[4]))
6346 /* multiply can not feed into subtraction. */
6347 if (rtx_equal_p (operands[5], operands[0]))
6350 /* Inout operand of sub can not conflict with any operands from multiply. */
6351 if (rtx_equal_p (operands[3], operands[0])
6352 || rtx_equal_p (operands[3], operands[1])
6353 || rtx_equal_p (operands[3], operands[2]))
6356 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6358 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6359 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6360 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6361 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6362 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6363 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6366 /* Passed. Operands are suitable for fmpysub. */
6371 plus_xor_ior_operator (op, mode)
6373 enum machine_mode mode ATTRIBUTE_UNUSED;
6375 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6376 || GET_CODE (op) == IOR);
6379 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6380 constants for shadd instructions. */
6382 shadd_constant_p (val)
6385 if (val == 2 || val == 4 || val == 8)
6391 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6392 the valid constant for shadd instructions. */
6394 shadd_operand (op, mode)
6396 enum machine_mode mode ATTRIBUTE_UNUSED;
6398 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6401 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6404 basereg_operand (op, mode)
6406 enum machine_mode mode;
6408 /* cse will create some unscaled indexed addresses, however; it
6409 generally isn't a win on the PA, so avoid creating unscaled
6410 indexed addresses until after cse is finished. */
6411 if (!cse_not_expected)
6414 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6415 we don't have to worry about the braindamaged implicit space
6416 register selection from the basereg. */
6417 if (TARGET_NO_SPACE_REGS)
6418 return (GET_CODE (op) == REG);
6420 /* While it's always safe to index off the frame pointer, it's not
6421 always profitable, particularly when the frame pointer is being
6423 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6426 return (GET_CODE (op) == REG
6428 && register_operand (op, mode));
6431 /* Return 1 if this operand is anything other than a hard register. */
6434 non_hard_reg_operand (op, mode)
6436 enum machine_mode mode ATTRIBUTE_UNUSED;
6438 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6441 /* Return 1 if INSN branches forward. Should be using insn_addresses
6442 to avoid walking through all the insns... */
6444 forward_branch_p (insn)
6447 rtx label = JUMP_LABEL (insn);
6454 insn = NEXT_INSN (insn);
6457 return (insn == label);
6460 /* Return 1 if OP is an equality comparison, else return 0. */
6462 eq_neq_comparison_operator (op, mode)
6464 enum machine_mode mode ATTRIBUTE_UNUSED;
6466 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6469 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6471 movb_comparison_operator (op, mode)
6473 enum machine_mode mode ATTRIBUTE_UNUSED;
6475 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6476 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6479 /* Return 1 if INSN is in the delay slot of a call instruction. */
6481 jump_in_call_delay (insn)
6485 if (GET_CODE (insn) != JUMP_INSN)
6488 if (PREV_INSN (insn)
6489 && PREV_INSN (PREV_INSN (insn))
6490 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6492 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6494 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6495 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6502 /* Output an unconditional move and branch insn. */
6505 output_parallel_movb (operands, length)
6509 /* These are the cases in which we win. */
6511 return "mov%I1b,tr %1,%0,%2";
6513 /* None of these cases wins, but they don't lose either. */
6514 if (dbr_sequence_length () == 0)
6516 /* Nothing in the delay slot, fake it by putting the combined
6517 insn (the copy or add) in the delay slot of a bl. */
6518 if (GET_CODE (operands[1]) == CONST_INT)
6519 return "b %2\n\tldi %1,%0";
6521 return "b %2\n\tcopy %1,%0";
6525 /* Something in the delay slot, but we've got a long branch. */
6526 if (GET_CODE (operands[1]) == CONST_INT)
6527 return "ldi %1,%0\n\tb %2";
6529 return "copy %1,%0\n\tb %2";
6533 /* Output an unconditional add and branch insn. */
6536 output_parallel_addb (operands, length)
6540 /* To make life easy we want operand0 to be the shared input/output
6541 operand and operand1 to be the readonly operand. */
6542 if (operands[0] == operands[1])
6543 operands[1] = operands[2];
6545 /* These are the cases in which we win. */
6547 return "add%I1b,tr %1,%0,%3";
6549 /* None of these cases win, but they don't lose either. */
6550 if (dbr_sequence_length () == 0)
6552 /* Nothing in the delay slot, fake it by putting the combined
6553 insn (the copy or add) in the delay slot of a bl. */
6554 return "b %3\n\tadd%I1 %1,%0,%0";
6558 /* Something in the delay slot, but we've got a long branch. */
6559 return "add%I1 %1,%0,%0\n\tb %3";
6563 /* Return nonzero if INSN (a jump insn) immediately follows a call to
6564 a named function. This is used to discourage creating parallel movb/addb
6565 insns since a jump which immediately follows a call can execute in the
6566 delay slot of the call.
6568 It is also used to avoid filling the delay slot of a jump which
6569 immediately follows a call since the jump can usually be eliminated
6570 completely by modifying RP in the delay slot of the call. */
6573 following_call (insn)
6576 /* We do not parallel movb,addb or place jumps into call delay slots when
6577 optimizing for the PA8000. */
6578 if (pa_cpu != PROCESSOR_8000)
6581 /* Find the previous real insn, skipping NOTEs. */
6582 insn = PREV_INSN (insn);
6583 while (insn && GET_CODE (insn) == NOTE)
6584 insn = PREV_INSN (insn);
6586 /* Check for CALL_INSNs and millicode calls. */
6588 && ((GET_CODE (insn) == CALL_INSN
6589 && get_attr_type (insn) != TYPE_DYNCALL)
6590 || (GET_CODE (insn) == INSN
6591 && GET_CODE (PATTERN (insn)) != SEQUENCE
6592 && GET_CODE (PATTERN (insn)) != USE
6593 && GET_CODE (PATTERN (insn)) != CLOBBER
6594 && get_attr_type (insn) == TYPE_MILLI)))
6600 /* We use this hook to perform a PA specific optimization which is difficult
6601 to do in earlier passes.
6603 We want the delay slots of branches within jump tables to be filled.
6604 None of the compiler passes at the moment even has the notion that a
6605 PA jump table doesn't contain addresses, but instead contains actual
6608 Because we actually jump into the table, the addresses of each entry
6609 must stay constant in relation to the beginning of the table (which
6610 itself must stay constant relative to the instruction to jump into
6611 it). I don't believe we can guarantee earlier passes of the compiler
6612 will adhere to those rules.
6614 So, late in the compilation process we find all the jump tables, and
6615 expand them into real code -- eg each entry in the jump table vector
6616 will get an appropriate label followed by a jump to the final target.
6618 Reorg and the final jump pass can then optimize these branches and
6619 fill their delay slots. We end up with smaller, more efficient code.
6621 The jump instructions within the table are special; we must be able
6622 to identify them during assembly output (if the jumps don't get filled
6623 we need to emit a nop rather than nullifying the delay slot)). We
6624 identify jumps in switch tables by marking the SET with DImode.
6626 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6627 insns. This serves two purposes, first it prevents jump.c from
6628 noticing that the last N entries in the table jump to the instruction
6629 immediately after the table and deleting the jumps. Second, those
6630 insns mark where we should emit .begin_brtab and .end_brtab directives
6631 when using GAS (allows for better link time optimizations). */
6639 remove_useless_addtr_insns (insns, 1);
6641 if (pa_cpu < PROCESSOR_8000)
6642 pa_combine_instructions (get_insns ());
6645 /* This is fairly cheap, so always run it if optimizing. */
6646 if (optimize > 0 && !TARGET_BIG_SWITCH)
6648 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6649 insns = get_insns ();
6650 for (insn = insns; insn; insn = NEXT_INSN (insn))
6652 rtx pattern, tmp, location;
6653 unsigned int length, i;
6655 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6656 if (GET_CODE (insn) != JUMP_INSN
6657 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6658 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6661 /* Emit marker for the beginning of the branch table. */
6662 emit_insn_before (gen_begin_brtab (), insn);
6664 pattern = PATTERN (insn);
6665 location = PREV_INSN (insn);
6666 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6668 for (i = 0; i < length; i++)
6670 /* Emit a label before each jump to keep jump.c from
6671 removing this code. */
6672 tmp = gen_label_rtx ();
6673 LABEL_NUSES (tmp) = 1;
6674 emit_label_after (tmp, location);
6675 location = NEXT_INSN (location);
6677 if (GET_CODE (pattern) == ADDR_VEC)
6679 /* Emit the jump itself. */
6680 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
6681 tmp = emit_jump_insn_after (tmp, location);
6682 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
6683 /* It is easy to rely on the branch table markers
6684 during assembly output to trigger the correct code
6685 for a switch table jump with an unfilled delay slot,
6687 However, that requires state and assumes that we look
6690 We can't make such assumptions when computing the length
6691 of instructions. Ugh. We could walk the insn chain to
6692 determine if this instruction is in a branch table, but
6693 that can get rather expensive, particularly during the
6694 branch shortening phase of the compiler.
6696 So instead we mark this jump as being special. This is
6697 far from ideal and knows that no code after this will
6698 muck around with the mode of the JUMP_INSN itself. */
6699 PUT_MODE (tmp, SImode);
6700 LABEL_NUSES (JUMP_LABEL (tmp))++;
6701 location = NEXT_INSN (location);
6705 /* Emit the jump itself. */
6706 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
6707 tmp = emit_jump_insn_after (tmp, location);
6708 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
6709 /* It is easy to rely on the branch table markers
6710 during assembly output to trigger the correct code
6711 for a switch table jump with an unfilled delay slot,
6713 However, that requires state and assumes that we look
6716 We can't make such assumptions when computing the length
6717 of instructions. Ugh. We could walk the insn chain to
6718 determine if this instruction is in a branch table, but
6719 that can get rather expensive, particularly during the
6720 branch shortening phase of the compiler.
6722 So instead we mark this jump as being special. This is
6723 far from ideal and knows that no code after this will
6724 muck around with the mode of the JUMP_INSN itself. */
6725 PUT_MODE (tmp, SImode);
6726 LABEL_NUSES (JUMP_LABEL (tmp))++;
6727 location = NEXT_INSN (location);
6730 /* Emit a BARRIER after the jump. */
6731 emit_barrier_after (location);
6732 location = NEXT_INSN (location);
6735 /* Emit marker for the end of the branch table. */
6736 emit_insn_before (gen_end_brtab (), location);
6737 location = NEXT_INSN (location);
6738 emit_barrier_after (location);
6740 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6746 /* Sill need an end_brtab insn. */
6747 insns = get_insns ();
6748 for (insn = insns; insn; insn = NEXT_INSN (insn))
6750 /* Find an ADDR_VEC insn. */
6751 if (GET_CODE (insn) != JUMP_INSN
6752 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6753 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6756 /* Now generate markers for the beginning and end of the
6758 emit_insn_before (gen_begin_brtab (), insn);
6759 emit_insn_after (gen_end_brtab (), insn);
6764 /* The PA has a number of odd instructions which can perform multiple
6765 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6766 it may be profitable to combine two instructions into one instruction
6767 with two outputs. It's not profitable PA2.0 machines because the
6768 two outputs would take two slots in the reorder buffers.
6770 This routine finds instructions which can be combined and combines
6771 them. We only support some of the potential combinations, and we
6772 only try common ways to find suitable instructions.
6774 * addb can add two registers or a register and a small integer
6775 and jump to a nearby (+-8k) location. Normally the jump to the
6776 nearby location is conditional on the result of the add, but by
6777 using the "true" condition we can make the jump unconditional.
6778 Thus addb can perform two independent operations in one insn.
6780 * movb is similar to addb in that it can perform a reg->reg
6781 or small immediate->reg copy and jump to a nearby (+-8k location).
6783 * fmpyadd and fmpysub can perform a FP multiply and either an
6784 FP add or FP sub if the operands of the multiply and add/sub are
6785 independent (there are other minor restrictions). Note both
6786 the fmpy and fadd/fsub can in theory move to better spots according
6787 to data dependencies, but for now we require the fmpy stay at a
6790 * Many of the memory operations can perform pre & post updates
6791 of index registers. GCC's pre/post increment/decrement addressing
6792 is far too simple to take advantage of all the possibilities. This
6793 pass may not be suitable since those insns may not be independent.
6795 * comclr can compare two ints or an int and a register, nullify
6796 the following instruction and zero some other register. This
6797 is more difficult to use as it's harder to find an insn which
6798 will generate a comclr than finding something like an unconditional
6799 branch. (conditional moves & long branches create comclr insns).
6801 * Most arithmetic operations can conditionally skip the next
6802 instruction. They can be viewed as "perform this operation
6803 and conditionally jump to this nearby location" (where nearby
6804 is an insns away). These are difficult to use due to the
6805 branch length restrictions. */
6808 pa_combine_instructions (insns)
6809 rtx insns ATTRIBUTE_UNUSED;
6813 /* This can get expensive since the basic algorithm is on the
6814 order of O(n^2) (or worse). Only do it for -O2 or higher
6815 levels of optimization. */
6819 /* Walk down the list of insns looking for "anchor" insns which
6820 may be combined with "floating" insns. As the name implies,
6821 "anchor" instructions don't move, while "floating" insns may
6823 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
6824 new = make_insn_raw (new);
6826 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
6828 enum attr_pa_combine_type anchor_attr;
6829 enum attr_pa_combine_type floater_attr;
6831 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6832 Also ignore any special USE insns. */
6833 if ((GET_CODE (anchor) != INSN
6834 && GET_CODE (anchor) != JUMP_INSN
6835 && GET_CODE (anchor) != CALL_INSN)
6836 || GET_CODE (PATTERN (anchor)) == USE
6837 || GET_CODE (PATTERN (anchor)) == CLOBBER
6838 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
6839 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
6842 anchor_attr = get_attr_pa_combine_type (anchor);
6843 /* See if anchor is an insn suitable for combination. */
6844 if (anchor_attr == PA_COMBINE_TYPE_FMPY
6845 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
6846 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6847 && ! forward_branch_p (anchor)))
6851 for (floater = PREV_INSN (anchor);
6853 floater = PREV_INSN (floater))
6855 if (GET_CODE (floater) == NOTE
6856 || (GET_CODE (floater) == INSN
6857 && (GET_CODE (PATTERN (floater)) == USE
6858 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6861 /* Anything except a regular INSN will stop our search. */
6862 if (GET_CODE (floater) != INSN
6863 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6864 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6870 /* See if FLOATER is suitable for combination with the
6872 floater_attr = get_attr_pa_combine_type (floater);
6873 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6874 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6875 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6876 && floater_attr == PA_COMBINE_TYPE_FMPY))
6878 /* If ANCHOR and FLOATER can be combined, then we're
6879 done with this pass. */
6880 if (pa_can_combine_p (new, anchor, floater, 0,
6881 SET_DEST (PATTERN (floater)),
6882 XEXP (SET_SRC (PATTERN (floater)), 0),
6883 XEXP (SET_SRC (PATTERN (floater)), 1)))
6887 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6888 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
6890 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
6892 if (pa_can_combine_p (new, anchor, floater, 0,
6893 SET_DEST (PATTERN (floater)),
6894 XEXP (SET_SRC (PATTERN (floater)), 0),
6895 XEXP (SET_SRC (PATTERN (floater)), 1)))
6900 if (pa_can_combine_p (new, anchor, floater, 0,
6901 SET_DEST (PATTERN (floater)),
6902 SET_SRC (PATTERN (floater)),
6903 SET_SRC (PATTERN (floater))))
6909 /* If we didn't find anything on the backwards scan try forwards. */
6911 && (anchor_attr == PA_COMBINE_TYPE_FMPY
6912 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
6914 for (floater = anchor; floater; floater = NEXT_INSN (floater))
6916 if (GET_CODE (floater) == NOTE
6917 || (GET_CODE (floater) == INSN
6918 && (GET_CODE (PATTERN (floater)) == USE
6919 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6923 /* Anything except a regular INSN will stop our search. */
6924 if (GET_CODE (floater) != INSN
6925 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6926 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6932 /* See if FLOATER is suitable for combination with the
6934 floater_attr = get_attr_pa_combine_type (floater);
6935 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6936 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6937 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6938 && floater_attr == PA_COMBINE_TYPE_FMPY))
6940 /* If ANCHOR and FLOATER can be combined, then we're
6941 done with this pass. */
6942 if (pa_can_combine_p (new, anchor, floater, 1,
6943 SET_DEST (PATTERN (floater)),
6944 XEXP (SET_SRC (PATTERN (floater)),
6946 XEXP (SET_SRC (PATTERN (floater)),
6953 /* FLOATER will be nonzero if we found a suitable floating
6954 insn for combination with ANCHOR. */
6956 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6957 || anchor_attr == PA_COMBINE_TYPE_FMPY))
6959 /* Emit the new instruction and delete the old anchor. */
6960 emit_insn_before (gen_rtx_PARALLEL
6962 gen_rtvec (2, PATTERN (anchor),
6963 PATTERN (floater))),
6966 PUT_CODE (anchor, NOTE);
6967 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6968 NOTE_SOURCE_FILE (anchor) = 0;
6970 /* Emit a special USE insn for FLOATER, then delete
6971 the floating insn. */
6972 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6973 delete_insn (floater);
6978 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
6981 /* Emit the new_jump instruction and delete the old anchor. */
6983 = emit_jump_insn_before (gen_rtx_PARALLEL
6985 gen_rtvec (2, PATTERN (anchor),
6986 PATTERN (floater))),
6989 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
6990 PUT_CODE (anchor, NOTE);
6991 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6992 NOTE_SOURCE_FILE (anchor) = 0;
6994 /* Emit a special USE insn for FLOATER, then delete
6995 the floating insn. */
6996 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6997 delete_insn (floater);
7005 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
7006 rtx new, anchor, floater;
7008 rtx dest, src1, src2;
7010 int insn_code_number;
7013 /* Create a PARALLEL with the patterns of ANCHOR and
7014 FLOATER, try to recognize it, then test constraints
7015 for the resulting pattern.
7017 If the pattern doesn't match or the constraints
7018 aren't met keep searching for a suitable floater
7020 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
7021 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
7022 INSN_CODE (new) = -1;
7023 insn_code_number = recog_memoized (new);
7024 if (insn_code_number < 0
7025 || !constrain_operands (1))
7039 /* There's up to three operands to consider. One
7040 output and two inputs.
7042 The output must not be used between FLOATER & ANCHOR
7043 exclusive. The inputs must not be set between
7044 FLOATER and ANCHOR exclusive. */
7046 if (reg_used_between_p (dest, start, end))
7049 if (reg_set_between_p (src1, start, end))
7052 if (reg_set_between_p (src2, start, end))
7055 /* If we get here, then everything is good. */
7059 /* Return nonzero if references for INSN are delayed.
7061 Millicode insns are actually function calls with some special
7062 constraints on arguments and register usage.
7064 Millicode calls always expect their arguments in the integer argument
7065 registers, and always return their result in %r29 (ret1). They
7066 are expected to clobber their arguments, %r1, %r29, and the return
7067 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
7069 This function tells reorg that the references to arguments and
7070 millicode calls do not appear to happen until after the millicode call.
7071 This allows reorg to put insns which set the argument registers into the
7072 delay slot of the millicode call -- thus they act more like traditional
7075 Note we can not consider side effects of the insn to be delayed because
7076 the branch and link insn will clobber the return pointer. If we happened
7077 to use the return pointer in the delay slot of the call, then we lose.
7079 get_attr_type will try to recognize the given insn, so make sure to
7080 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
7083 insn_refs_are_delayed (insn)
7086 return ((GET_CODE (insn) == INSN
7087 && GET_CODE (PATTERN (insn)) != SEQUENCE
7088 && GET_CODE (PATTERN (insn)) != USE
7089 && GET_CODE (PATTERN (insn)) != CLOBBER
7090 && get_attr_type (insn) == TYPE_MILLI));
7093 /* Return the location of a parameter that is passed in a register or NULL
7094 if the parameter has any component that is passed in memory.
7096 This is new code and will be pushed to into the net sources after
7099 ??? We might want to restructure this so that it looks more like other
7102 function_arg (cum, mode, type, named, incoming)
7103 CUMULATIVE_ARGS *cum;
7104 enum machine_mode mode;
7106 int named ATTRIBUTE_UNUSED;
7109 int max_arg_words = (TARGET_64BIT ? 8 : 4);
7116 /* If this arg would be passed partially or totally on the stack, then
7117 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
7118 handle arguments which are split between regs and stack slots if
7119 the ABI mandates split arguments. */
7120 if (cum->words + FUNCTION_ARG_SIZE (mode, type) > max_arg_words
7121 || mode == VOIDmode)
7127 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7129 if (cum->words + offset >= max_arg_words
7130 || mode == VOIDmode)
7134 /* The 32bit ABIs and the 64bit ABIs are rather different,
7135 particularly in their handling of FP registers. We might
7136 be able to cleverly share code between them, but I'm not
7137 going to bother in the hope that splitting them up results
7138 in code that is more easily understood.
7140 The 64bit code probably is very wrong for structure passing. */
7143 /* Advance the base registers to their current locations.
7145 Remember, gprs grow towards smaller register numbers while
7146 fprs grow to higher register numbers. Also remember FP regs
7147 are always 4 bytes wide, while the size of an integer register
7148 varies based on the size of the target word. */
7149 gpr_reg_base = 26 - cum->words;
7150 fpr_reg_base = 32 + cum->words;
7152 /* If the argument is more than a word long, then we need to align
7153 the base registers. Same caveats as above. */
7154 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7156 if (mode != BLKmode)
7158 /* First deal with alignment of the doubleword. */
7159 gpr_reg_base -= (cum->words & 1);
7161 /* This seems backwards, but it is what HP specifies. We need
7162 gpr_reg_base to point to the smaller numbered register of
7163 the integer register pair. So if we have an even register
7164 number, then decrement the gpr base. */
7165 gpr_reg_base -= ((gpr_reg_base % 2) == 0);
7167 /* FP values behave sanely, except that each FP reg is only
7169 fpr_reg_base += ((fpr_reg_base % 2) == 0);
7174 int i, offset = 0, ub;
7175 ub = FUNCTION_ARG_SIZE (mode, type);
7177 MAX (0, max_arg_words - cum->words - (cum->words & 1)));
7178 gpr_reg_base -= (cum->words & 1);
7179 for (i = 0; i < ub; i++)
7181 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7182 gen_rtx_REG (DImode,
7191 return XEXP (loc[0], 0);
7193 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7199 /* If the argument is larger than a word, then we know precisely
7200 which registers we must use. */
7201 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7216 /* We have a single word (32 bits). A simple computation
7217 will get us the register #s we need. */
7218 gpr_reg_base = 26 - cum->words;
7219 fpr_reg_base = 32 + 2 * cum->words;
7223 if (TARGET_64BIT && mode == TFmode)
7229 gen_rtx_EXPR_LIST (VOIDmode,
7230 gen_rtx_REG (DImode, gpr_reg_base + 1),
7232 gen_rtx_EXPR_LIST (VOIDmode,
7233 gen_rtx_REG (DImode, gpr_reg_base),
7236 /* Determine if the argument needs to be passed in both general and
7237 floating point registers. */
7238 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7239 /* If we are doing soft-float with portable runtime, then there
7240 is no need to worry about FP regs. */
7241 && ! TARGET_SOFT_FLOAT
7242 /* The parameter must be some kind of float, else we can just
7243 pass it in integer registers. */
7244 && FLOAT_MODE_P (mode)
7245 /* The target function must not have a prototype. */
7246 && cum->nargs_prototype <= 0
7247 /* libcalls do not need to pass items in both FP and general
7249 && type != NULL_TREE
7250 /* All this hair applies to outgoing args only. */
7252 /* Also pass outgoing floating arguments in both registers in indirect
7253 calls with the 32 bit ABI and the HP assembler since there is no
7254 way to the specify argument locations in static functions. */
7259 && FLOAT_MODE_P (mode)))
7265 gen_rtx_EXPR_LIST (VOIDmode,
7266 gen_rtx_REG (mode, fpr_reg_base),
7268 gen_rtx_EXPR_LIST (VOIDmode,
7269 gen_rtx_REG (mode, gpr_reg_base),
7274 /* See if we should pass this parameter in a general register. */
7275 if (TARGET_SOFT_FLOAT
7276 /* Indirect calls in the normal 32bit ABI require all arguments
7277 to be passed in general registers. */
7278 || (!TARGET_PORTABLE_RUNTIME
7281 /* If the parameter is not a floating point parameter, then
7282 it belongs in GPRs. */
7283 || !FLOAT_MODE_P (mode))
7284 retval = gen_rtx_REG (mode, gpr_reg_base);
7286 retval = gen_rtx_REG (mode, fpr_reg_base);
7292 /* If this arg would be passed totally in registers or totally on the stack,
7293 then this routine should return zero. It is currently called only for
7294 the 64-bit target. */
7296 function_arg_partial_nregs (cum, mode, type, named)
7297 CUMULATIVE_ARGS *cum;
7298 enum machine_mode mode;
7300 int named ATTRIBUTE_UNUSED;
7302 unsigned int max_arg_words = 8;
7303 unsigned int offset = 0;
7305 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7308 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
7309 /* Arg fits fully into registers. */
7311 else if (cum->words + offset >= max_arg_words)
7312 /* Arg fully on the stack. */
7316 return max_arg_words - cum->words - offset;
7320 /* Return 1 if this is a comparison operator. This allows the use of
7321 MATCH_OPERATOR to recognize all the branch insns. */
7324 cmpib_comparison_operator (op, mode)
7326 enum machine_mode mode;
7328 return ((mode == VOIDmode || GET_MODE (op) == mode)
7329 && (GET_CODE (op) == EQ
7330 || GET_CODE (op) == NE
7331 || GET_CODE (op) == GT
7332 || GET_CODE (op) == GTU
7333 || GET_CODE (op) == GE
7334 || GET_CODE (op) == LT
7335 || GET_CODE (op) == LE
7336 || GET_CODE (op) == LEU));
7339 /* Mark ARG (which is really a struct deferred_plabel **) for GC. */
7342 mark_deferred_plabels (arg)
7345 struct deferred_plabel *dp = *(struct deferred_plabel **) arg;
7348 for (i = 0; i < n_deferred_plabels; ++i)
7349 ggc_mark_rtx (dp[i].internal_label);
7352 /* Called to register all of our global variables with the garbage
7358 ggc_add_rtx_root (&hppa_compare_op0, 1);
7359 ggc_add_rtx_root (&hppa_compare_op1, 1);
7360 ggc_add_root (&deferred_plabels, 1, sizeof (&deferred_plabels),
7361 &mark_deferred_plabels);