1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
40 #include "integrate.h"
48 #include "target-def.h"
50 #ifndef DO_FRAME_NOTES
51 #ifdef INCOMING_RETURN_ADDR_RTX
52 #define DO_FRAME_NOTES 1
54 #define DO_FRAME_NOTES 0
58 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
59 static void pa_combine_instructions PARAMS ((rtx));
60 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
61 static int forward_branch_p PARAMS ((rtx));
62 static int shadd_constant_p PARAMS ((int));
63 static void pa_add_gc_roots PARAMS ((void));
64 static void mark_deferred_plabels PARAMS ((void *));
65 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
66 static int compute_movstrsi_length PARAMS ((rtx));
67 static void remove_useless_addtr_insns PARAMS ((rtx, int));
68 static rtx store_reg PARAMS ((int, int, int));
69 static rtx load_reg PARAMS ((int, int, int));
70 static rtx set_reg_plus_d PARAMS ((int, int, int));
71 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
72 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
73 static int pa_adjust_priority PARAMS ((rtx, int));
74 static int pa_issue_rate PARAMS ((void));
76 /* Save the operands last given to a compare for use when we
77 generate a scc or bcc insn. */
79 rtx hppa_compare_op0, hppa_compare_op1;
80 enum cmp_type hppa_branch_type;
82 /* Which cpu we are scheduling for. */
83 enum processor_type pa_cpu;
85 /* String to hold which cpu we are scheduling for. */
86 const char *pa_cpu_string;
88 /* Which architecture we are generating code for. */
89 enum architecture_type pa_arch;
91 /* String to hold which architecture we are generating code for. */
92 const char *pa_arch_string;
94 /* Counts for the number of callee-saved general and floating point
95 registers which were saved by the current function's prologue. */
96 static int gr_saved, fr_saved;
98 static rtx find_addr_reg PARAMS ((rtx));
100 /* Keep track of the number of bytes we have output in the CODE subspaces
101 during this compilation so we'll know when to emit inline long-calls. */
103 unsigned int total_code_bytes;
105 /* Variables to handle plabels that we discover are necessary at assembly
106 output time. They are output after the current function. */
108 struct deferred_plabel
112 } *deferred_plabels = 0;
113 int n_deferred_plabels = 0;
115 /* Initialize the GCC target structure. */
116 #undef TARGET_ASM_FUNCTION_PROLOGUE
117 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
118 #undef TARGET_ASM_FUNCTION_EPILOGUE
119 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
121 #undef TARGET_SCHED_ADJUST_COST
122 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
123 #undef TARGET_SCHED_ADJUST_PRIORITY
124 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
125 #undef TARGET_SCHED_ISSUE_RATE
126 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
128 struct gcc_target targetm = TARGET_INITIALIZER;
133 /* Default to 7100LC scheduling. */
134 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
136 pa_cpu_string = "7100";
137 pa_cpu = PROCESSOR_7100;
139 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
141 pa_cpu_string = "700";
142 pa_cpu = PROCESSOR_700;
144 else if (pa_cpu_string == NULL
145 || ! strcmp (pa_cpu_string, "7100LC"))
147 pa_cpu_string = "7100LC";
148 pa_cpu = PROCESSOR_7100LC;
150 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
152 pa_cpu_string = "7200";
153 pa_cpu = PROCESSOR_7200;
155 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "8000"))
157 pa_cpu_string = "8000";
158 pa_cpu = PROCESSOR_8000;
162 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string);
165 /* Set the instruction set architecture. */
166 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
168 pa_arch_string = "1.0";
169 pa_arch = ARCHITECTURE_10;
170 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
172 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
174 pa_arch_string = "1.1";
175 pa_arch = ARCHITECTURE_11;
176 target_flags &= ~MASK_PA_20;
177 target_flags |= MASK_PA_11;
179 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
181 pa_arch_string = "2.0";
182 pa_arch = ARCHITECTURE_20;
183 target_flags |= MASK_PA_11 | MASK_PA_20;
185 else if (pa_arch_string)
187 warning ("Unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
190 if (flag_pic && TARGET_PORTABLE_RUNTIME)
192 warning ("PIC code generation is not supported in the portable runtime model\n");
195 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
197 warning ("PIC code generation is not compatible with fast indirect calls\n");
200 if (! TARGET_GAS && write_symbols != NO_DEBUG)
202 warning ("-g is only supported when using GAS on this processor,");
203 warning ("-g option disabled.");
204 write_symbols = NO_DEBUG;
207 /* We only support the "big PIC" model now. And we always generate PIC
208 code when in 64bit mode. */
209 if (flag_pic == 1 || TARGET_64BIT)
212 /* Register global variables with the garbage collector. */
216 /* Return non-zero only if OP is a register of mode MODE,
219 reg_or_0_operand (op, mode)
221 enum machine_mode mode;
223 return (op == CONST0_RTX (mode) || register_operand (op, mode));
226 /* Return non-zero if OP is suitable for use in a call to a named
229 For 2.5 try to eliminate either call_operand_address or
230 function_label_operand, they perform very similar functions. */
232 call_operand_address (op, mode)
234 enum machine_mode mode ATTRIBUTE_UNUSED;
236 return (GET_MODE (op) == word_mode
237 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
240 /* Return 1 if X contains a symbolic expression. We know these
241 expressions will have one of a few well defined forms, so
242 we need only check those forms. */
244 symbolic_expression_p (x)
248 /* Strip off any HIGH. */
249 if (GET_CODE (x) == HIGH)
252 return (symbolic_operand (x, VOIDmode));
256 symbolic_operand (op, mode)
258 enum machine_mode mode ATTRIBUTE_UNUSED;
260 switch (GET_CODE (op))
267 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
268 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
269 && GET_CODE (XEXP (op, 1)) == CONST_INT);
275 /* Return truth value of statement that OP is a symbolic memory
276 operand of mode MODE. */
279 symbolic_memory_operand (op, mode)
281 enum machine_mode mode ATTRIBUTE_UNUSED;
283 if (GET_CODE (op) == SUBREG)
284 op = SUBREG_REG (op);
285 if (GET_CODE (op) != MEM)
288 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
289 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
292 /* Return 1 if the operand is either a register or a memory operand that is
296 reg_or_nonsymb_mem_operand (op, mode)
298 enum machine_mode mode;
300 if (register_operand (op, mode))
303 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
309 /* Return 1 if the operand is either a register, zero, or a memory operand
310 that is not symbolic. */
313 reg_or_0_or_nonsymb_mem_operand (op, mode)
315 enum machine_mode mode;
317 if (register_operand (op, mode))
320 if (op == CONST0_RTX (mode))
323 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
329 /* Accept any constant that can be moved in one instructions into a
332 cint_ok_for_move (intval)
333 HOST_WIDE_INT intval;
335 /* OK if ldo, ldil, or zdepi, can be used. */
336 return (CONST_OK_FOR_LETTER_P (intval, 'J')
337 || CONST_OK_FOR_LETTER_P (intval, 'N')
338 || CONST_OK_FOR_LETTER_P (intval, 'K'));
341 /* Accept anything that can be moved in one instruction into a general
344 move_operand (op, mode)
346 enum machine_mode mode;
348 if (register_operand (op, mode))
351 if (GET_CODE (op) == CONSTANT_P_RTX)
354 if (GET_CODE (op) == CONST_INT)
355 return cint_ok_for_move (INTVAL (op));
357 if (GET_CODE (op) == SUBREG)
358 op = SUBREG_REG (op);
359 if (GET_CODE (op) != MEM)
364 /* We consider a LO_SUM DLT reference a move_operand now since it has
365 been merged into the normal movsi/movdi patterns. */
366 if (GET_CODE (op) == LO_SUM
367 && GET_CODE (XEXP (op, 0)) == REG
368 && REG_OK_FOR_BASE_P (XEXP (op, 0))
369 && GET_CODE (XEXP (op, 1)) == UNSPEC
370 && GET_MODE (op) == Pmode)
373 /* Since move_operand is only used for source operands, we can always
374 allow scaled indexing! */
375 if (! TARGET_DISABLE_INDEXING
376 && GET_CODE (op) == PLUS
377 && ((GET_CODE (XEXP (op, 0)) == MULT
378 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
379 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
380 && INTVAL (XEXP (XEXP (op, 0), 1))
381 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
382 && GET_CODE (XEXP (op, 1)) == REG)
383 || (GET_CODE (XEXP (op, 1)) == MULT
384 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
385 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
386 && INTVAL (XEXP (XEXP (op, 1), 1))
387 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
388 && GET_CODE (XEXP (op, 0)) == REG)))
391 return memory_address_p (mode, op);
394 /* Accept REG and any CONST_INT that can be moved in one instruction into a
397 reg_or_cint_move_operand (op, mode)
399 enum machine_mode mode;
401 if (register_operand (op, mode))
404 if (GET_CODE (op) == CONST_INT)
405 return cint_ok_for_move (INTVAL (op));
411 pic_label_operand (op, mode)
413 enum machine_mode mode ATTRIBUTE_UNUSED;
418 switch (GET_CODE (op))
424 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
425 && GET_CODE (XEXP (op, 1)) == CONST_INT);
432 fp_reg_operand (op, mode)
434 enum machine_mode mode ATTRIBUTE_UNUSED;
436 return reg_renumber && FP_REG_P (op);
441 /* Return truth value of whether OP can be used as an operand in a
442 three operand arithmetic insn that accepts registers of mode MODE
443 or 14-bit signed integers. */
445 arith_operand (op, mode)
447 enum machine_mode mode;
449 return (register_operand (op, mode)
450 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
453 /* Return truth value of whether OP can be used as an operand in a
454 three operand arithmetic insn that accepts registers of mode MODE
455 or 11-bit signed integers. */
457 arith11_operand (op, mode)
459 enum machine_mode mode;
461 return (register_operand (op, mode)
462 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
465 /* A constant integer suitable for use in a PRE_MODIFY memory
468 pre_cint_operand (op, mode)
470 enum machine_mode mode ATTRIBUTE_UNUSED;
472 return (GET_CODE (op) == CONST_INT
473 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
476 /* A constant integer suitable for use in a POST_MODIFY memory
479 post_cint_operand (op, mode)
481 enum machine_mode mode ATTRIBUTE_UNUSED;
483 return (GET_CODE (op) == CONST_INT
484 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
488 arith_double_operand (op, mode)
490 enum machine_mode mode;
492 return (register_operand (op, mode)
493 || (GET_CODE (op) == CONST_DOUBLE
494 && GET_MODE (op) == mode
495 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
496 && ((CONST_DOUBLE_HIGH (op) >= 0)
497 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
500 /* Return truth value of whether OP is an integer which fits the
501 range constraining immediate operands in three-address insns, or
502 is an integer register. */
505 ireg_or_int5_operand (op, mode)
507 enum machine_mode mode ATTRIBUTE_UNUSED;
509 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
510 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
513 /* Return nonzero if OP is an integer register, else return zero. */
515 ireg_operand (op, mode)
517 enum machine_mode mode ATTRIBUTE_UNUSED;
519 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
522 /* Return truth value of whether OP is an integer which fits the
523 range constraining immediate operands in three-address insns. */
526 int5_operand (op, mode)
528 enum machine_mode mode ATTRIBUTE_UNUSED;
530 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
534 uint5_operand (op, mode)
536 enum machine_mode mode ATTRIBUTE_UNUSED;
538 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
542 int11_operand (op, mode)
544 enum machine_mode mode ATTRIBUTE_UNUSED;
546 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
550 uint32_operand (op, mode)
552 enum machine_mode mode ATTRIBUTE_UNUSED;
554 #if HOST_BITS_PER_WIDE_INT > 32
555 /* All allowed constants will fit a CONST_INT. */
556 return (GET_CODE (op) == CONST_INT
557 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
559 return (GET_CODE (op) == CONST_INT
560 || (GET_CODE (op) == CONST_DOUBLE
561 && CONST_DOUBLE_HIGH (op) == 0));
566 arith5_operand (op, mode)
568 enum machine_mode mode;
570 return register_operand (op, mode) || int5_operand (op, mode);
573 /* True iff zdepi can be used to generate this CONST_INT.
574 zdepi first sign extends a 5 bit signed number to a given field
575 length, then places this field anywhere in a zero. */
578 unsigned HOST_WIDE_INT x;
580 unsigned HOST_WIDE_INT lsb_mask, t;
582 /* This might not be obvious, but it's at least fast.
583 This function is critical; we don't have the time loops would take. */
585 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
586 /* Return true iff t is a power of two. */
587 return ((t & (t - 1)) == 0);
590 /* True iff depi or extru can be used to compute (reg & mask).
591 Accept bit pattern like these:
597 unsigned HOST_WIDE_INT mask;
600 mask += mask & -mask;
601 return (mask & (mask - 1)) == 0;
604 /* True iff depi or extru can be used to compute (reg & OP). */
606 and_operand (op, mode)
608 enum machine_mode mode;
610 return (register_operand (op, mode)
611 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
614 /* True iff depi can be used to compute (reg | MASK). */
617 unsigned HOST_WIDE_INT mask;
619 mask += mask & -mask;
620 return (mask & (mask - 1)) == 0;
623 /* True iff depi can be used to compute (reg | OP). */
625 ior_operand (op, mode)
627 enum machine_mode mode ATTRIBUTE_UNUSED;
629 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
633 lhs_lshift_operand (op, mode)
635 enum machine_mode mode;
637 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
640 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
641 Such values can be the left hand side x in (x << r), using the zvdepi
644 lhs_lshift_cint_operand (op, mode)
646 enum machine_mode mode ATTRIBUTE_UNUSED;
648 unsigned HOST_WIDE_INT x;
649 if (GET_CODE (op) != CONST_INT)
651 x = INTVAL (op) >> 4;
652 return (x & (x + 1)) == 0;
656 arith32_operand (op, mode)
658 enum machine_mode mode;
660 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
664 pc_or_label_operand (op, mode)
666 enum machine_mode mode ATTRIBUTE_UNUSED;
668 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
671 /* Legitimize PIC addresses. If the address is already
672 position-independent, we return ORIG. Newly generated
673 position-independent addresses go to REG. If we need more
674 than one register, we lose. */
677 legitimize_pic_address (orig, mode, reg)
679 enum machine_mode mode;
683 /* Labels need special handling. */
684 if (pic_label_operand (orig, mode))
686 /* We do not want to go through the movXX expanders here since that
687 would create recursion.
689 Nor do we really want to call a generator for a named pattern
690 since that requires multiple patterns if we want to support
693 So instead we just emit the raw set, which avoids the movXX
694 expanders completely. */
695 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
696 current_function_uses_pic_offset_table = 1;
699 if (GET_CODE (orig) == SYMBOL_REF)
705 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
706 gen_rtx_HIGH (word_mode, orig)));
708 = gen_rtx_MEM (Pmode,
709 gen_rtx_LO_SUM (Pmode, reg,
710 gen_rtx_UNSPEC (Pmode,
714 current_function_uses_pic_offset_table = 1;
715 RTX_UNCHANGING_P (pic_ref) = 1;
716 emit_move_insn (reg, pic_ref);
719 else if (GET_CODE (orig) == CONST)
723 if (GET_CODE (XEXP (orig, 0)) == PLUS
724 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
730 if (GET_CODE (XEXP (orig, 0)) == PLUS)
732 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
733 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
734 base == reg ? 0 : reg);
737 if (GET_CODE (orig) == CONST_INT)
739 if (INT_14_BITS (orig))
740 return plus_constant (base, INTVAL (orig));
741 orig = force_reg (Pmode, orig);
743 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
744 /* Likewise, should we set special REG_NOTEs here? */
749 /* Try machine-dependent ways of modifying an illegitimate address
750 to be legitimate. If we find one, return the new, valid address.
751 This macro is used in only one place: `memory_address' in explow.c.
753 OLDX is the address as it was before break_out_memory_refs was called.
754 In some cases it is useful to look at this to decide what needs to be done.
756 MODE and WIN are passed so that this macro can use
757 GO_IF_LEGITIMATE_ADDRESS.
759 It is always safe for this macro to do nothing. It exists to recognize
760 opportunities to optimize the output.
762 For the PA, transform:
764 memory(X + <large int>)
768 if (<large int> & mask) >= 16
769 Y = (<large int> & ~mask) + mask + 1 Round up.
771 Y = (<large int> & ~mask) Round down.
773 memory (Z + (<large int> - Y));
775 This is for CSE to find several similar references, and only use one Z.
777 X can either be a SYMBOL_REF or REG, but because combine can not
778 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
779 D will not fit in 14 bits.
781 MODE_FLOAT references allow displacements which fit in 5 bits, so use
784 MODE_INT references allow displacements which fit in 14 bits, so use
787 This relies on the fact that most mode MODE_FLOAT references will use FP
788 registers and most mode MODE_INT references will use integer registers.
789 (In the rare case of an FP register used in an integer MODE, we depend
790 on secondary reloads to clean things up.)
793 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
794 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
795 addressing modes to be used).
797 Put X and Z into registers. Then put the entire expression into
801 hppa_legitimize_address (x, oldx, mode)
802 rtx x, oldx ATTRIBUTE_UNUSED;
803 enum machine_mode mode;
808 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
810 /* Strip off CONST. */
811 if (GET_CODE (x) == CONST)
814 /* Special case. Get the SYMBOL_REF into a register and use indexing.
815 That should always be safe. */
816 if (GET_CODE (x) == PLUS
817 && GET_CODE (XEXP (x, 0)) == REG
818 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
820 rtx reg = force_reg (Pmode, XEXP (x, 1));
821 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
824 /* Note we must reject symbols which represent function addresses
825 since the assembler/linker can't handle arithmetic on plabels. */
826 if (GET_CODE (x) == PLUS
827 && GET_CODE (XEXP (x, 1)) == CONST_INT
828 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
829 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
830 || GET_CODE (XEXP (x, 0)) == REG))
832 rtx int_part, ptr_reg;
834 int offset = INTVAL (XEXP (x, 1));
837 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
838 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
840 /* Choose which way to round the offset. Round up if we
841 are >= halfway to the next boundary. */
842 if ((offset & mask) >= ((mask + 1) / 2))
843 newoffset = (offset & ~ mask) + mask + 1;
845 newoffset = (offset & ~ mask);
847 /* If the newoffset will not fit in 14 bits (ldo), then
848 handling this would take 4 or 5 instructions (2 to load
849 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
850 add the new offset and the SYMBOL_REF.) Combine can
851 not handle 4->2 or 5->2 combinations, so do not create
853 if (! VAL_14_BITS_P (newoffset)
854 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
856 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
859 gen_rtx_HIGH (Pmode, const_part));
862 gen_rtx_LO_SUM (Pmode,
863 tmp_reg, const_part));
867 if (! VAL_14_BITS_P (newoffset))
868 int_part = force_reg (Pmode, GEN_INT (newoffset));
870 int_part = GEN_INT (newoffset);
872 ptr_reg = force_reg (Pmode,
874 force_reg (Pmode, XEXP (x, 0)),
877 return plus_constant (ptr_reg, offset - newoffset);
880 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
882 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
883 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
884 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
885 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
886 || GET_CODE (XEXP (x, 1)) == SUBREG)
887 && GET_CODE (XEXP (x, 1)) != CONST)
889 int val = INTVAL (XEXP (XEXP (x, 0), 1));
893 if (GET_CODE (reg1) != REG)
894 reg1 = force_reg (Pmode, force_operand (reg1, 0));
896 reg2 = XEXP (XEXP (x, 0), 0);
897 if (GET_CODE (reg2) != REG)
898 reg2 = force_reg (Pmode, force_operand (reg2, 0));
900 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
907 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
909 Only do so for floating point modes since this is more speculative
910 and we lose if it's an integer store. */
911 if (GET_CODE (x) == PLUS
912 && GET_CODE (XEXP (x, 0)) == PLUS
913 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
914 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
915 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
916 && (mode == SFmode || mode == DFmode))
919 /* First, try and figure out what to use as a base register. */
920 rtx reg1, reg2, base, idx, orig_base;
922 reg1 = XEXP (XEXP (x, 0), 1);
927 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
928 then emit_move_sequence will turn on REG_POINTER so we'll know
929 it's a base register below. */
930 if (GET_CODE (reg1) != REG)
931 reg1 = force_reg (Pmode, force_operand (reg1, 0));
933 if (GET_CODE (reg2) != REG)
934 reg2 = force_reg (Pmode, force_operand (reg2, 0));
936 /* Figure out what the base and index are. */
938 if (GET_CODE (reg1) == REG
939 && REG_POINTER (reg1))
942 orig_base = XEXP (XEXP (x, 0), 1);
943 idx = gen_rtx_PLUS (Pmode,
945 XEXP (XEXP (XEXP (x, 0), 0), 0),
946 XEXP (XEXP (XEXP (x, 0), 0), 1)),
949 else if (GET_CODE (reg2) == REG
950 && REG_POINTER (reg2))
953 orig_base = XEXP (x, 1);
960 /* If the index adds a large constant, try to scale the
961 constant so that it can be loaded with only one insn. */
962 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
963 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
964 / INTVAL (XEXP (XEXP (idx, 0), 1)))
965 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
967 /* Divide the CONST_INT by the scale factor, then add it to A. */
968 int val = INTVAL (XEXP (idx, 1));
970 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
971 reg1 = XEXP (XEXP (idx, 0), 0);
972 if (GET_CODE (reg1) != REG)
973 reg1 = force_reg (Pmode, force_operand (reg1, 0));
975 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
977 /* We can now generate a simple scaled indexed address. */
980 (Pmode, gen_rtx_PLUS (Pmode,
981 gen_rtx_MULT (Pmode, reg1,
982 XEXP (XEXP (idx, 0), 1)),
986 /* If B + C is still a valid base register, then add them. */
987 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
988 && INTVAL (XEXP (idx, 1)) <= 4096
989 && INTVAL (XEXP (idx, 1)) >= -4096)
991 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
994 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
996 reg2 = XEXP (XEXP (idx, 0), 0);
997 if (GET_CODE (reg2) != CONST_INT)
998 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1000 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1001 gen_rtx_MULT (Pmode,
1007 /* Get the index into a register, then add the base + index and
1008 return a register holding the result. */
1010 /* First get A into a register. */
1011 reg1 = XEXP (XEXP (idx, 0), 0);
1012 if (GET_CODE (reg1) != REG)
1013 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1015 /* And get B into a register. */
1016 reg2 = XEXP (idx, 1);
1017 if (GET_CODE (reg2) != REG)
1018 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1020 reg1 = force_reg (Pmode,
1021 gen_rtx_PLUS (Pmode,
1022 gen_rtx_MULT (Pmode, reg1,
1023 XEXP (XEXP (idx, 0), 1)),
1026 /* Add the result to our base register and return. */
1027 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1031 /* Uh-oh. We might have an address for x[n-100000]. This needs
1032 special handling to avoid creating an indexed memory address
1033 with x-100000 as the base.
1035 If the constant part is small enough, then it's still safe because
1036 there is a guard page at the beginning and end of the data segment.
1038 Scaled references are common enough that we want to try and rearrange the
1039 terms so that we can use indexing for these addresses too. Only
1040 do the optimization for floatint point modes. */
1042 if (GET_CODE (x) == PLUS
1043 && symbolic_expression_p (XEXP (x, 1)))
1045 /* Ugly. We modify things here so that the address offset specified
1046 by the index expression is computed first, then added to x to form
1047 the entire address. */
1049 rtx regx1, regx2, regy1, regy2, y;
1051 /* Strip off any CONST. */
1053 if (GET_CODE (y) == CONST)
1056 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1058 /* See if this looks like
1059 (plus (mult (reg) (shadd_const))
1060 (const (plus (symbol_ref) (const_int))))
1062 Where const_int is small. In that case the const
1063 expression is a valid pointer for indexing.
1065 If const_int is big, but can be divided evenly by shadd_const
1066 and added to (reg). This allows more scaled indexed addresses. */
1067 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1068 && GET_CODE (XEXP (x, 0)) == MULT
1069 && GET_CODE (XEXP (y, 1)) == CONST_INT
1070 && INTVAL (XEXP (y, 1)) >= -4096
1071 && INTVAL (XEXP (y, 1)) <= 4095
1072 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1073 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1075 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1079 if (GET_CODE (reg1) != REG)
1080 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1082 reg2 = XEXP (XEXP (x, 0), 0);
1083 if (GET_CODE (reg2) != REG)
1084 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1086 return force_reg (Pmode,
1087 gen_rtx_PLUS (Pmode,
1088 gen_rtx_MULT (Pmode,
1093 else if ((mode == DFmode || mode == SFmode)
1094 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1095 && GET_CODE (XEXP (x, 0)) == MULT
1096 && GET_CODE (XEXP (y, 1)) == CONST_INT
1097 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1098 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1099 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1102 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1103 / INTVAL (XEXP (XEXP (x, 0), 1))));
1104 regx2 = XEXP (XEXP (x, 0), 0);
1105 if (GET_CODE (regx2) != REG)
1106 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1107 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1111 gen_rtx_PLUS (Pmode,
1112 gen_rtx_MULT (Pmode, regx2,
1113 XEXP (XEXP (x, 0), 1)),
1114 force_reg (Pmode, XEXP (y, 0))));
1116 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1117 && INTVAL (XEXP (y, 1)) >= -4096
1118 && INTVAL (XEXP (y, 1)) <= 4095)
1120 /* This is safe because of the guard page at the
1121 beginning and end of the data space. Just
1122 return the original address. */
1127 /* Doesn't look like one we can optimize. */
1128 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1129 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1130 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1131 regx1 = force_reg (Pmode,
1132 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1134 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1142 /* For the HPPA, REG and REG+CONST is cost 0
1143 and addresses involving symbolic constants are cost 2.
1145 PIC addresses are very expensive.
1147 It is no coincidence that this has the same structure
1148 as GO_IF_LEGITIMATE_ADDRESS. */
1150 hppa_address_cost (X)
1153 if (GET_CODE (X) == PLUS)
1155 else if (GET_CODE (X) == LO_SUM)
1157 else if (GET_CODE (X) == HIGH)
1162 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1163 new rtx with the correct mode. */
1165 force_mode (mode, orig)
1166 enum machine_mode mode;
1169 if (mode == GET_MODE (orig))
1172 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1175 return gen_rtx_REG (mode, REGNO (orig));
1178 /* Emit insns to move operands[1] into operands[0].
1180 Return 1 if we have written out everything that needs to be done to
1181 do the move. Otherwise, return 0 and the caller will emit the move
1184 Note SCRATCH_REG may not be in the proper mode depending on how it
1185 will be used. This routine is resposible for creating a new copy
1186 of SCRATCH_REG in the proper mode. */
1189 emit_move_sequence (operands, mode, scratch_reg)
1191 enum machine_mode mode;
1194 register rtx operand0 = operands[0];
1195 register rtx operand1 = operands[1];
1199 && reload_in_progress && GET_CODE (operand0) == REG
1200 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1201 operand0 = reg_equiv_mem[REGNO (operand0)];
1202 else if (scratch_reg
1203 && reload_in_progress && GET_CODE (operand0) == SUBREG
1204 && GET_CODE (SUBREG_REG (operand0)) == REG
1205 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1207 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1208 the code which tracks sets/uses for delete_output_reload. */
1209 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1210 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1211 SUBREG_BYTE (operand0));
1212 operand0 = alter_subreg (temp);
1216 && reload_in_progress && GET_CODE (operand1) == REG
1217 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1218 operand1 = reg_equiv_mem[REGNO (operand1)];
1219 else if (scratch_reg
1220 && reload_in_progress && GET_CODE (operand1) == SUBREG
1221 && GET_CODE (SUBREG_REG (operand1)) == REG
1222 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1224 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1225 the code which tracks sets/uses for delete_output_reload. */
1226 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1227 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1228 SUBREG_BYTE (operand1));
1229 operand1 = alter_subreg (temp);
1232 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1233 && ((tem = find_replacement (&XEXP (operand0, 0)))
1234 != XEXP (operand0, 0)))
1235 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1236 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1237 && ((tem = find_replacement (&XEXP (operand1, 0)))
1238 != XEXP (operand1, 0)))
1239 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1241 /* Handle secondary reloads for loads/stores of FP registers from
1242 REG+D addresses where D does not fit in 5 bits, including
1243 (subreg (mem (addr))) cases. */
1244 if (fp_reg_operand (operand0, mode)
1245 && ((GET_CODE (operand1) == MEM
1246 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1247 || ((GET_CODE (operand1) == SUBREG
1248 && GET_CODE (XEXP (operand1, 0)) == MEM
1249 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1252 if (GET_CODE (operand1) == SUBREG)
1253 operand1 = XEXP (operand1, 0);
1255 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1256 it in WORD_MODE regardless of what mode it was originally given
1258 scratch_reg = force_mode (word_mode, scratch_reg);
1260 /* D might not fit in 14 bits either; for such cases load D into
1262 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1264 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1265 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1267 XEXP (XEXP (operand1, 0), 0),
1271 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1272 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1273 gen_rtx_MEM (mode, scratch_reg)));
1276 else if (fp_reg_operand (operand1, mode)
1277 && ((GET_CODE (operand0) == MEM
1278 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1279 || ((GET_CODE (operand0) == SUBREG)
1280 && GET_CODE (XEXP (operand0, 0)) == MEM
1281 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1284 if (GET_CODE (operand0) == SUBREG)
1285 operand0 = XEXP (operand0, 0);
1287 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1288 it in WORD_MODE regardless of what mode it was originally given
1290 scratch_reg = force_mode (word_mode, scratch_reg);
1292 /* D might not fit in 14 bits either; for such cases load D into
1294 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1296 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1297 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1300 XEXP (XEXP (operand0, 0),
1305 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1306 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1310 /* Handle secondary reloads for loads of FP registers from constant
1311 expressions by forcing the constant into memory.
1313 use scratch_reg to hold the address of the memory location.
1315 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1316 NO_REGS when presented with a const_int and an register class
1317 containing only FP registers. Doing so unfortunately creates
1318 more problems than it solves. Fix this for 2.5. */
1319 else if (fp_reg_operand (operand0, mode)
1320 && CONSTANT_P (operand1)
1325 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1326 it in WORD_MODE regardless of what mode it was originally given
1328 scratch_reg = force_mode (word_mode, scratch_reg);
1330 /* Force the constant into memory and put the address of the
1331 memory location into scratch_reg. */
1332 xoperands[0] = scratch_reg;
1333 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1334 emit_move_sequence (xoperands, Pmode, 0);
1336 /* Now load the destination register. */
1337 emit_insn (gen_rtx_SET (mode, operand0,
1338 gen_rtx_MEM (mode, scratch_reg)));
1341 /* Handle secondary reloads for SAR. These occur when trying to load
1342 the SAR from memory, FP register, or with a constant. */
1343 else if (GET_CODE (operand0) == REG
1344 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1345 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1346 && (GET_CODE (operand1) == MEM
1347 || GET_CODE (operand1) == CONST_INT
1348 || (GET_CODE (operand1) == REG
1349 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1352 /* D might not fit in 14 bits either; for such cases load D into
1354 if (GET_CODE (operand1) == MEM
1355 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1357 /* We are reloading the address into the scratch register, so we
1358 want to make sure the scratch register is a full register. */
1359 scratch_reg = force_mode (word_mode, scratch_reg);
1361 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1362 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1365 XEXP (XEXP (operand1, 0),
1369 /* Now we are going to load the scratch register from memory,
1370 we want to load it in the same width as the original MEM,
1371 which must be the same as the width of the ultimate destination,
1373 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1375 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1380 /* We want to load the scratch register using the same mode as
1381 the ultimate destination. */
1382 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1384 emit_move_insn (scratch_reg, operand1);
1387 /* And emit the insn to set the ultimate destination. We know that
1388 the scratch register has the same mode as the destination at this
1390 emit_move_insn (operand0, scratch_reg);
1393 /* Handle most common case: storing into a register. */
1394 else if (register_operand (operand0, mode))
1396 if (register_operand (operand1, mode)
1397 || (GET_CODE (operand1) == CONST_INT
1398 && cint_ok_for_move (INTVAL (operand1)))
1399 || (operand1 == CONST0_RTX (mode))
1400 || (GET_CODE (operand1) == HIGH
1401 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1402 /* Only `general_operands' can come here, so MEM is ok. */
1403 || GET_CODE (operand1) == MEM)
1405 /* Run this case quickly. */
1406 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1410 else if (GET_CODE (operand0) == MEM)
1412 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1413 && !(reload_in_progress || reload_completed))
1415 rtx temp = gen_reg_rtx (DFmode);
1417 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1418 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1421 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1423 /* Run this case quickly. */
1424 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1427 if (! (reload_in_progress || reload_completed))
1429 operands[0] = validize_mem (operand0);
1430 operands[1] = operand1 = force_reg (mode, operand1);
1434 /* Simplify the source if we need to.
1435 Note we do have to handle function labels here, even though we do
1436 not consider them legitimate constants. Loop optimizations can
1437 call the emit_move_xxx with one as a source. */
1438 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1439 || function_label_operand (operand1, mode)
1440 || (GET_CODE (operand1) == HIGH
1441 && symbolic_operand (XEXP (operand1, 0), mode)))
1445 if (GET_CODE (operand1) == HIGH)
1448 operand1 = XEXP (operand1, 0);
1450 if (symbolic_operand (operand1, mode))
1452 /* Argh. The assembler and linker can't handle arithmetic
1455 So we force the plabel into memory, load operand0 from
1456 the memory location, then add in the constant part. */
1457 if ((GET_CODE (operand1) == CONST
1458 && GET_CODE (XEXP (operand1, 0)) == PLUS
1459 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1460 || function_label_operand (operand1, mode))
1462 rtx temp, const_part;
1464 /* Figure out what (if any) scratch register to use. */
1465 if (reload_in_progress || reload_completed)
1467 scratch_reg = scratch_reg ? scratch_reg : operand0;
1468 /* SCRATCH_REG will hold an address and maybe the actual
1469 data. We want it in WORD_MODE regardless of what mode it
1470 was originally given to us. */
1471 scratch_reg = force_mode (word_mode, scratch_reg);
1474 scratch_reg = gen_reg_rtx (Pmode);
1476 if (GET_CODE (operand1) == CONST)
1478 /* Save away the constant part of the expression. */
1479 const_part = XEXP (XEXP (operand1, 0), 1);
1480 if (GET_CODE (const_part) != CONST_INT)
1483 /* Force the function label into memory. */
1484 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1488 /* No constant part. */
1489 const_part = NULL_RTX;
1491 /* Force the function label into memory. */
1492 temp = force_const_mem (mode, operand1);
1496 /* Get the address of the memory location. PIC-ify it if
1498 temp = XEXP (temp, 0);
1500 temp = legitimize_pic_address (temp, mode, scratch_reg);
1502 /* Put the address of the memory location into our destination
1505 emit_move_sequence (operands, mode, scratch_reg);
1507 /* Now load from the memory location into our destination
1509 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1510 emit_move_sequence (operands, mode, scratch_reg);
1512 /* And add back in the constant part. */
1513 if (const_part != NULL_RTX)
1514 expand_inc (operand0, const_part);
1523 if (reload_in_progress || reload_completed)
1525 temp = scratch_reg ? scratch_reg : operand0;
1526 /* TEMP will hold an address and maybe the actual
1527 data. We want it in WORD_MODE regardless of what mode it
1528 was originally given to us. */
1529 temp = force_mode (word_mode, temp);
1532 temp = gen_reg_rtx (Pmode);
1534 /* (const (plus (symbol) (const_int))) must be forced to
1535 memory during/after reload if the const_int will not fit
1537 if (GET_CODE (operand1) == CONST
1538 && GET_CODE (XEXP (operand1, 0)) == PLUS
1539 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1540 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1541 && (reload_completed || reload_in_progress)
1544 operands[1] = force_const_mem (mode, operand1);
1545 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1547 emit_move_sequence (operands, mode, temp);
1551 operands[1] = legitimize_pic_address (operand1, mode, temp);
1552 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1555 /* On the HPPA, references to data space are supposed to use dp,
1556 register 27, but showing it in the RTL inhibits various cse
1557 and loop optimizations. */
1562 if (reload_in_progress || reload_completed)
1564 temp = scratch_reg ? scratch_reg : operand0;
1565 /* TEMP will hold an address and maybe the actual
1566 data. We want it in WORD_MODE regardless of what mode it
1567 was originally given to us. */
1568 temp = force_mode (word_mode, temp);
1571 temp = gen_reg_rtx (mode);
1573 /* Loading a SYMBOL_REF into a register makes that register
1574 safe to be used as the base in an indexed address.
1576 Don't mark hard registers though. That loses. */
1577 if (GET_CODE (operand0) == REG
1578 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1579 REG_POINTER (operand0) = 1;
1580 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1581 REG_POINTER (temp) = 1;
1583 set = gen_rtx_SET (mode, operand0, temp);
1585 set = gen_rtx_SET (VOIDmode,
1587 gen_rtx_LO_SUM (mode, temp, operand1));
1589 emit_insn (gen_rtx_SET (VOIDmode,
1591 gen_rtx_HIGH (mode, operand1)));
1597 else if (GET_CODE (operand1) != CONST_INT
1598 || ! cint_ok_for_move (INTVAL (operand1)))
1600 rtx extend = NULL_RTX;
1603 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1604 && HOST_BITS_PER_WIDE_INT > 32
1605 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1607 HOST_WIDE_INT val = INTVAL (operand1);
1610 /* Extract the low order 32 bits of the value and sign extend.
1611 If the new value is the same as the original value, we can
1612 can use the original value as-is. If the new value is
1613 different, we use it and insert the most-significant 32-bits
1614 of the original value into the final result. */
1615 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1616 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1619 #if HOST_BITS_PER_WIDE_INT > 32
1620 extend = GEN_INT (val >> 32);
1622 operand1 = GEN_INT (nval);
1626 if (reload_in_progress || reload_completed)
1629 temp = gen_reg_rtx (mode);
1631 if (GET_CODE (operand1) == CONST_INT)
1633 /* Directly break constant into low and high parts. This
1634 provides better optimization opportunities because various
1635 passes recognize constants split with PLUS but not LO_SUM.
1636 We use a 14-bit signed low part except when the addition
1637 of 0x4000 to the high part might change the sign of the
1639 HOST_WIDE_INT value = INTVAL (operand1);
1640 HOST_WIDE_INT low = value & 0x3fff;
1641 HOST_WIDE_INT high = value & ~ 0x3fff;
1645 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1653 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1654 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1658 emit_insn (gen_rtx_SET (VOIDmode, temp,
1659 gen_rtx_HIGH (mode, operand1)));
1660 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1663 emit_move_insn (operands[0], operands[1]);
1665 if (extend != NULL_RTX)
1666 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1672 /* Now have insn-emit do whatever it normally does. */
1676 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1677 it will need a link/runtime reloc). */
1685 switch (TREE_CODE (exp))
1692 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1693 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1698 case NON_LVALUE_EXPR:
1699 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1705 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1706 if (TREE_VALUE (link) != 0)
1707 reloc |= reloc_needed (TREE_VALUE (link));
1720 /* Does operand (which is a symbolic_operand) live in text space? If
1721 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1724 read_only_operand (operand, mode)
1726 enum machine_mode mode ATTRIBUTE_UNUSED;
1728 if (GET_CODE (operand) == CONST)
1729 operand = XEXP (XEXP (operand, 0), 0);
1732 if (GET_CODE (operand) == SYMBOL_REF)
1733 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1737 if (GET_CODE (operand) == SYMBOL_REF)
1738 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1744 /* Return the best assembler insn template
1745 for moving operands[1] into operands[0] as a fullword. */
1747 singlemove_string (operands)
1750 HOST_WIDE_INT intval;
1752 if (GET_CODE (operands[0]) == MEM)
1753 return "stw %r1,%0";
1754 if (GET_CODE (operands[1]) == MEM)
1756 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1761 if (GET_MODE (operands[1]) != SFmode)
1764 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1766 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1767 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1769 operands[1] = GEN_INT (i);
1770 /* Fall through to CONST_INT case. */
1772 if (GET_CODE (operands[1]) == CONST_INT)
1774 intval = INTVAL (operands[1]);
1776 if (VAL_14_BITS_P (intval))
1778 else if ((intval & 0x7ff) == 0)
1779 return "ldil L'%1,%0";
1780 else if (zdepi_cint_p (intval))
1781 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1783 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1785 return "copy %1,%0";
1789 /* Compute position (in OP[1]) and width (in OP[2])
1790 useful for copying IMM to a register using the zdepi
1791 instructions. Store the immediate value to insert in OP[0]. */
1793 compute_zdepwi_operands (imm, op)
1794 unsigned HOST_WIDE_INT imm;
1799 /* Find the least significant set bit in IMM. */
1800 for (lsb = 0; lsb < 32; lsb++)
1807 /* Choose variants based on *sign* of the 5-bit field. */
1808 if ((imm & 0x10) == 0)
1809 len = (lsb <= 28) ? 4 : 32 - lsb;
1812 /* Find the width of the bitstring in IMM. */
1813 for (len = 5; len < 32; len++)
1815 if ((imm & (1 << len)) == 0)
1819 /* Sign extend IMM as a 5-bit value. */
1820 imm = (imm & 0xf) - 0x10;
1828 /* Compute position (in OP[1]) and width (in OP[2])
1829 useful for copying IMM to a register using the depdi,z
1830 instructions. Store the immediate value to insert in OP[0]. */
1832 compute_zdepdi_operands (imm, op)
1833 unsigned HOST_WIDE_INT imm;
1836 HOST_WIDE_INT lsb, len;
1838 /* Find the least significant set bit in IMM. */
1839 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1846 /* Choose variants based on *sign* of the 5-bit field. */
1847 if ((imm & 0x10) == 0)
1848 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1849 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1852 /* Find the width of the bitstring in IMM. */
1853 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1855 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
1859 /* Sign extend IMM as a 5-bit value. */
1860 imm = (imm & 0xf) - 0x10;
1868 /* Output assembler code to perform a doubleword move insn
1869 with operands OPERANDS. */
1872 output_move_double (operands)
1875 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1877 rtx addreg0 = 0, addreg1 = 0;
1879 /* First classify both operands. */
1881 if (REG_P (operands[0]))
1883 else if (offsettable_memref_p (operands[0]))
1885 else if (GET_CODE (operands[0]) == MEM)
1890 if (REG_P (operands[1]))
1892 else if (CONSTANT_P (operands[1]))
1894 else if (offsettable_memref_p (operands[1]))
1896 else if (GET_CODE (operands[1]) == MEM)
1901 /* Check for the cases that the operand constraints are not
1902 supposed to allow to happen. Abort if we get one,
1903 because generating code for these cases is painful. */
1905 if (optype0 != REGOP && optype1 != REGOP)
1908 /* Handle auto decrementing and incrementing loads and stores
1909 specifically, since the structure of the function doesn't work
1910 for them without major modification. Do it better when we learn
1911 this port about the general inc/dec addressing of PA.
1912 (This was written by tege. Chide him if it doesn't work.) */
1914 if (optype0 == MEMOP)
1916 /* We have to output the address syntax ourselves, since print_operand
1917 doesn't deal with the addresses we want to use. Fix this later. */
1919 rtx addr = XEXP (operands[0], 0);
1920 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1922 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1924 operands[0] = XEXP (addr, 0);
1925 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1928 if (!reg_overlap_mentioned_p (high_reg, addr))
1930 /* No overlap between high target register and address
1931 register. (We do this in a non-obvious way to
1932 save a register file writeback) */
1933 if (GET_CODE (addr) == POST_INC)
1934 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
1935 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
1940 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1942 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1944 operands[0] = XEXP (addr, 0);
1945 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1948 if (!reg_overlap_mentioned_p (high_reg, addr))
1950 /* No overlap between high target register and address
1951 register. (We do this in a non-obvious way to
1952 save a register file writeback) */
1953 if (GET_CODE (addr) == PRE_INC)
1954 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
1955 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
1961 if (optype1 == MEMOP)
1963 /* We have to output the address syntax ourselves, since print_operand
1964 doesn't deal with the addresses we want to use. Fix this later. */
1966 rtx addr = XEXP (operands[1], 0);
1967 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1969 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1971 operands[1] = XEXP (addr, 0);
1972 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1975 if (!reg_overlap_mentioned_p (high_reg, addr))
1977 /* No overlap between high target register and address
1978 register. (We do this in a non-obvious way to
1979 save a register file writeback) */
1980 if (GET_CODE (addr) == POST_INC)
1981 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
1982 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
1986 /* This is an undefined situation. We should load into the
1987 address register *and* update that register. Probably
1988 we don't need to handle this at all. */
1989 if (GET_CODE (addr) == POST_INC)
1990 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
1991 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
1994 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1996 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1998 operands[1] = XEXP (addr, 0);
1999 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2002 if (!reg_overlap_mentioned_p (high_reg, addr))
2004 /* No overlap between high target register and address
2005 register. (We do this in a non-obvious way to
2006 save a register file writeback) */
2007 if (GET_CODE (addr) == PRE_INC)
2008 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2009 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2013 /* This is an undefined situation. We should load into the
2014 address register *and* update that register. Probably
2015 we don't need to handle this at all. */
2016 if (GET_CODE (addr) == PRE_INC)
2017 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2018 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2021 else if (GET_CODE (addr) == PLUS
2022 && GET_CODE (XEXP (addr, 0)) == MULT)
2024 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2026 if (!reg_overlap_mentioned_p (high_reg, addr))
2030 xoperands[0] = high_reg;
2031 xoperands[1] = XEXP (addr, 1);
2032 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2033 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2034 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2036 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2042 xoperands[0] = high_reg;
2043 xoperands[1] = XEXP (addr, 1);
2044 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2045 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2046 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2048 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2053 /* If an operand is an unoffsettable memory ref, find a register
2054 we can increment temporarily to make it refer to the second word. */
2056 if (optype0 == MEMOP)
2057 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2059 if (optype1 == MEMOP)
2060 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2062 /* Ok, we can do one word at a time.
2063 Normally we do the low-numbered word first.
2065 In either case, set up in LATEHALF the operands to use
2066 for the high-numbered word and in some cases alter the
2067 operands in OPERANDS to be suitable for the low-numbered word. */
2069 if (optype0 == REGOP)
2070 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2071 else if (optype0 == OFFSOP)
2072 latehalf[0] = adjust_address (operands[0], SImode, 4);
2074 latehalf[0] = operands[0];
2076 if (optype1 == REGOP)
2077 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2078 else if (optype1 == OFFSOP)
2079 latehalf[1] = adjust_address (operands[1], SImode, 4);
2080 else if (optype1 == CNSTOP)
2081 split_double (operands[1], &operands[1], &latehalf[1]);
2083 latehalf[1] = operands[1];
2085 /* If the first move would clobber the source of the second one,
2086 do them in the other order.
2088 This can happen in two cases:
2090 mem -> register where the first half of the destination register
2091 is the same register used in the memory's address. Reload
2092 can create such insns.
2094 mem in this case will be either register indirect or register
2095 indirect plus a valid offset.
2097 register -> register move where REGNO(dst) == REGNO(src + 1)
2098 someone (Tim/Tege?) claimed this can happen for parameter loads.
2100 Handle mem -> register case first. */
2101 if (optype0 == REGOP
2102 && (optype1 == MEMOP || optype1 == OFFSOP)
2103 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2106 /* Do the late half first. */
2108 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2109 output_asm_insn (singlemove_string (latehalf), latehalf);
2113 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2114 return singlemove_string (operands);
2117 /* Now handle register -> register case. */
2118 if (optype0 == REGOP && optype1 == REGOP
2119 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2121 output_asm_insn (singlemove_string (latehalf), latehalf);
2122 return singlemove_string (operands);
2125 /* Normal case: do the two words, low-numbered first. */
2127 output_asm_insn (singlemove_string (operands), operands);
2129 /* Make any unoffsettable addresses point at high-numbered word. */
2131 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2133 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2136 output_asm_insn (singlemove_string (latehalf), latehalf);
2138 /* Undo the adds we just did. */
2140 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2142 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2148 output_fp_move_double (operands)
2151 if (FP_REG_P (operands[0]))
2153 if (FP_REG_P (operands[1])
2154 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2155 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2157 output_asm_insn ("fldd%F1 %1,%0", operands);
2159 else if (FP_REG_P (operands[1]))
2161 output_asm_insn ("fstd%F0 %1,%0", operands);
2163 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2165 if (GET_CODE (operands[0]) == REG)
2168 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2169 xoperands[0] = operands[0];
2170 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2172 /* This is a pain. You have to be prepared to deal with an
2173 arbitrary address here including pre/post increment/decrement.
2175 so avoid this in the MD. */
2183 /* Return a REG that occurs in ADDR with coefficient 1.
2184 ADDR can be effectively incremented by incrementing REG. */
2187 find_addr_reg (addr)
2190 while (GET_CODE (addr) == PLUS)
2192 if (GET_CODE (XEXP (addr, 0)) == REG)
2193 addr = XEXP (addr, 0);
2194 else if (GET_CODE (XEXP (addr, 1)) == REG)
2195 addr = XEXP (addr, 1);
2196 else if (CONSTANT_P (XEXP (addr, 0)))
2197 addr = XEXP (addr, 1);
2198 else if (CONSTANT_P (XEXP (addr, 1)))
2199 addr = XEXP (addr, 0);
2203 if (GET_CODE (addr) == REG)
2208 /* Emit code to perform a block move.
2210 OPERANDS[0] is the destination pointer as a REG, clobbered.
2211 OPERANDS[1] is the source pointer as a REG, clobbered.
2212 OPERANDS[2] is a register for temporary storage.
2213 OPERANDS[4] is the size as a CONST_INT
2214 OPERANDS[3] is a register for temporary storage.
2215 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2216 OPERANDS[6] is another temporary register. */
2219 output_block_move (operands, size_is_constant)
2221 int size_is_constant ATTRIBUTE_UNUSED;
2223 int align = INTVAL (operands[5]);
2224 unsigned long n_bytes = INTVAL (operands[4]);
2226 /* We can't move more than four bytes at a time because the PA
2227 has no longer integer move insns. (Could use fp mem ops?) */
2231 /* Note that we know each loop below will execute at least twice
2232 (else we would have open-coded the copy). */
2236 /* Pre-adjust the loop counter. */
2237 operands[4] = GEN_INT (n_bytes - 8);
2238 output_asm_insn ("ldi %4,%2", operands);
2241 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2242 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2243 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2244 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2245 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2247 /* Handle the residual. There could be up to 7 bytes of
2248 residual to copy! */
2249 if (n_bytes % 8 != 0)
2251 operands[4] = GEN_INT (n_bytes % 4);
2252 if (n_bytes % 8 >= 4)
2253 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2254 if (n_bytes % 4 != 0)
2255 output_asm_insn ("ldw 0(%1),%6", operands);
2256 if (n_bytes % 8 >= 4)
2257 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2258 if (n_bytes % 4 != 0)
2259 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2264 /* Pre-adjust the loop counter. */
2265 operands[4] = GEN_INT (n_bytes - 4);
2266 output_asm_insn ("ldi %4,%2", operands);
2269 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2270 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2271 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2272 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2273 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2275 /* Handle the residual. */
2276 if (n_bytes % 4 != 0)
2278 if (n_bytes % 4 >= 2)
2279 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2280 if (n_bytes % 2 != 0)
2281 output_asm_insn ("ldb 0(%1),%6", operands);
2282 if (n_bytes % 4 >= 2)
2283 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2284 if (n_bytes % 2 != 0)
2285 output_asm_insn ("stb %6,0(%0)", operands);
2290 /* Pre-adjust the loop counter. */
2291 operands[4] = GEN_INT (n_bytes - 2);
2292 output_asm_insn ("ldi %4,%2", operands);
2295 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2296 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2297 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2298 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2299 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2301 /* Handle the residual. */
2302 if (n_bytes % 2 != 0)
2304 output_asm_insn ("ldb 0(%1),%3", operands);
2305 output_asm_insn ("stb %3,0(%0)", operands);
2314 /* Count the number of insns necessary to handle this block move.
2316 Basic structure is the same as emit_block_move, except that we
2317 count insns rather than emit them. */
2320 compute_movstrsi_length (insn)
2323 rtx pat = PATTERN (insn);
2324 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2325 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
2326 unsigned int n_insns = 0;
2328 /* We can't move more than four bytes at a time because the PA
2329 has no longer integer move insns. (Could use fp mem ops?) */
2333 /* The basic copying loop. */
2337 if (n_bytes % (2 * align) != 0)
2339 if ((n_bytes % (2 * align)) >= align)
2342 if ((n_bytes % align) != 0)
2346 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2352 output_and (operands)
2355 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2357 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2358 int ls0, ls1, ms0, p, len;
2360 for (ls0 = 0; ls0 < 32; ls0++)
2361 if ((mask & (1 << ls0)) == 0)
2364 for (ls1 = ls0; ls1 < 32; ls1++)
2365 if ((mask & (1 << ls1)) != 0)
2368 for (ms0 = ls1; ms0 < 32; ms0++)
2369 if ((mask & (1 << ms0)) == 0)
2382 operands[2] = GEN_INT (len);
2383 return "{extru|extrw,u} %1,31,%2,%0";
2387 /* We could use this `depi' for the case above as well, but `depi'
2388 requires one more register file access than an `extru'. */
2393 operands[2] = GEN_INT (p);
2394 operands[3] = GEN_INT (len);
2395 return "{depi|depwi} 0,%2,%3,%0";
2399 return "and %1,%2,%0";
2402 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2403 storing the result in operands[0]. */
2405 output_64bit_and (operands)
2408 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2410 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2411 int ls0, ls1, ms0, p, len;
2413 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2414 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2417 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2418 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2421 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2422 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2425 if (ms0 != HOST_BITS_PER_WIDE_INT)
2428 if (ls1 == HOST_BITS_PER_WIDE_INT)
2435 operands[2] = GEN_INT (len);
2436 return "extrd,u %1,63,%2,%0";
2440 /* We could use this `depi' for the case above as well, but `depi'
2441 requires one more register file access than an `extru'. */
2446 operands[2] = GEN_INT (p);
2447 operands[3] = GEN_INT (len);
2448 return "depdi 0,%2,%3,%0";
2452 return "and %1,%2,%0";
2456 output_ior (operands)
2459 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2460 int bs0, bs1, p, len;
2462 if (INTVAL (operands[2]) == 0)
2463 return "copy %1,%0";
2465 for (bs0 = 0; bs0 < 32; bs0++)
2466 if ((mask & (1 << bs0)) != 0)
2469 for (bs1 = bs0; bs1 < 32; bs1++)
2470 if ((mask & (1 << bs1)) == 0)
2473 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2479 operands[2] = GEN_INT (p);
2480 operands[3] = GEN_INT (len);
2481 return "{depi|depwi} -1,%2,%3,%0";
2484 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2485 storing the result in operands[0]. */
2487 output_64bit_ior (operands)
2490 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2491 int bs0, bs1, p, len;
2493 if (INTVAL (operands[2]) == 0)
2494 return "copy %1,%0";
2496 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2497 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2500 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2501 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2504 if (bs1 != HOST_BITS_PER_WIDE_INT
2505 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2511 operands[2] = GEN_INT (p);
2512 operands[3] = GEN_INT (len);
2513 return "depdi -1,%2,%3,%0";
2516 /* Output an ascii string. */
2518 output_ascii (file, p, size)
2525 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2527 /* The HP assembler can only take strings of 256 characters at one
2528 time. This is a limitation on input line length, *not* the
2529 length of the string. Sigh. Even worse, it seems that the
2530 restriction is in number of input characters (see \xnn &
2531 \whatever). So we have to do this very carefully. */
2533 fputs ("\t.STRING \"", file);
2536 for (i = 0; i < size; i += 4)
2540 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2542 register unsigned int c = p[i + io];
2544 if (c == '\"' || c == '\\')
2545 partial_output[co++] = '\\';
2546 if (c >= ' ' && c < 0177)
2547 partial_output[co++] = c;
2551 partial_output[co++] = '\\';
2552 partial_output[co++] = 'x';
2553 hexd = c / 16 - 0 + '0';
2555 hexd -= '9' - 'a' + 1;
2556 partial_output[co++] = hexd;
2557 hexd = c % 16 - 0 + '0';
2559 hexd -= '9' - 'a' + 1;
2560 partial_output[co++] = hexd;
2563 if (chars_output + co > 243)
2565 fputs ("\"\n\t.STRING \"", file);
2568 fwrite (partial_output, 1, co, file);
2572 fputs ("\"\n", file);
2575 /* Try to rewrite floating point comparisons & branches to avoid
2576 useless add,tr insns.
2578 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2579 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2580 first attempt to remove useless add,tr insns. It is zero
2581 for the second pass as reorg sometimes leaves bogus REG_DEAD
2584 When CHECK_NOTES is zero we can only eliminate add,tr insns
2585 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2588 remove_useless_addtr_insns (insns, check_notes)
2593 static int pass = 0;
2595 /* This is fairly cheap, so always run it when optimizing. */
2599 int fbranch_count = 0;
2601 /* Walk all the insns in this function looking for fcmp & fbranch
2602 instructions. Keep track of how many of each we find. */
2603 insns = get_insns ();
2604 for (insn = insns; insn; insn = next_insn (insn))
2608 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2609 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2612 tmp = PATTERN (insn);
2614 /* It must be a set. */
2615 if (GET_CODE (tmp) != SET)
2618 /* If the destination is CCFP, then we've found an fcmp insn. */
2619 tmp = SET_DEST (tmp);
2620 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2626 tmp = PATTERN (insn);
2627 /* If this is an fbranch instruction, bump the fbranch counter. */
2628 if (GET_CODE (tmp) == SET
2629 && SET_DEST (tmp) == pc_rtx
2630 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2631 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2632 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2633 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2641 /* Find all floating point compare + branch insns. If possible,
2642 reverse the comparison & the branch to avoid add,tr insns. */
2643 for (insn = insns; insn; insn = next_insn (insn))
2647 /* Ignore anything that isn't an INSN. */
2648 if (GET_CODE (insn) != INSN)
2651 tmp = PATTERN (insn);
2653 /* It must be a set. */
2654 if (GET_CODE (tmp) != SET)
2657 /* The destination must be CCFP, which is register zero. */
2658 tmp = SET_DEST (tmp);
2659 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2662 /* INSN should be a set of CCFP.
2664 See if the result of this insn is used in a reversed FP
2665 conditional branch. If so, reverse our condition and
2666 the branch. Doing so avoids useless add,tr insns. */
2667 next = next_insn (insn);
2670 /* Jumps, calls and labels stop our search. */
2671 if (GET_CODE (next) == JUMP_INSN
2672 || GET_CODE (next) == CALL_INSN
2673 || GET_CODE (next) == CODE_LABEL)
2676 /* As does another fcmp insn. */
2677 if (GET_CODE (next) == INSN
2678 && GET_CODE (PATTERN (next)) == SET
2679 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2680 && REGNO (SET_DEST (PATTERN (next))) == 0)
2683 next = next_insn (next);
2686 /* Is NEXT_INSN a branch? */
2688 && GET_CODE (next) == JUMP_INSN)
2690 rtx pattern = PATTERN (next);
2692 /* If it a reversed fp conditional branch (eg uses add,tr)
2693 and CCFP dies, then reverse our conditional and the branch
2694 to avoid the add,tr. */
2695 if (GET_CODE (pattern) == SET
2696 && SET_DEST (pattern) == pc_rtx
2697 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2698 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2699 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2700 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2701 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2702 && (fcmp_count == fbranch_count
2704 && find_regno_note (next, REG_DEAD, 0))))
2706 /* Reverse the branch. */
2707 tmp = XEXP (SET_SRC (pattern), 1);
2708 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2709 XEXP (SET_SRC (pattern), 2) = tmp;
2710 INSN_CODE (next) = -1;
2712 /* Reverse our condition. */
2713 tmp = PATTERN (insn);
2714 PUT_CODE (XEXP (tmp, 1),
2715 (reverse_condition_maybe_unordered
2716 (GET_CODE (XEXP (tmp, 1)))));
2726 /* You may have trouble believing this, but this is the 32 bit HP-PA
2731 Variable arguments (optional; any number may be allocated)
2733 SP-(4*(N+9)) arg word N
2738 Fixed arguments (must be allocated; may remain unused)
2747 SP-32 External Data Pointer (DP)
2749 SP-24 External/stub RP (RP')
2753 SP-8 Calling Stub RP (RP'')
2758 SP-0 Stack Pointer (points to next available address)
2762 /* This function saves registers as follows. Registers marked with ' are
2763 this function's registers (as opposed to the previous function's).
2764 If a frame_pointer isn't needed, r4 is saved as a general register;
2765 the space for the frame pointer is still allocated, though, to keep
2771 SP (FP') Previous FP
2772 SP + 4 Alignment filler (sigh)
2773 SP + 8 Space for locals reserved here.
2777 SP + n All call saved register used.
2781 SP + o All call saved fp registers used.
2785 SP + p (SP') points to next available address.
2789 /* Global variables set by output_function_prologue(). */
2790 /* Size of frame. Need to know this to emit return insns from
2792 static int actual_fsize;
2793 static int local_fsize, save_fregs;
2795 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2796 Handle case where DISP > 8k by using the add_high_const patterns.
2798 Note in DISP > 8k case, we will leave the high part of the address
2799 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2802 store_reg (reg, disp, base)
2803 int reg, disp, base;
2805 rtx i, dest, src, basereg;
2807 src = gen_rtx_REG (word_mode, reg);
2808 basereg = gen_rtx_REG (Pmode, base);
2809 if (VAL_14_BITS_P (disp))
2811 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2812 i = emit_move_insn (dest, src);
2816 rtx delta = GEN_INT (disp);
2817 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
2818 rtx tmpreg = gen_rtx_REG (Pmode, 1);
2819 emit_move_insn (tmpreg, high);
2820 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
2821 i = emit_move_insn (dest, src);
2826 /* Emit RTL to set REG to the value specified by BASE+DISP.
2827 Handle case where DISP > 8k by using the add_high_const patterns.
2829 Note in DISP > 8k case, we will leave the high part of the address
2830 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2833 set_reg_plus_d (reg, base, disp)
2834 int reg, base, disp;
2838 if (VAL_14_BITS_P (disp))
2840 i = emit_move_insn (gen_rtx_REG (Pmode, reg),
2841 plus_constant (gen_rtx_REG (Pmode, base), disp));
2845 rtx delta = GEN_INT (disp);
2846 emit_move_insn (gen_rtx_REG (Pmode, 1),
2847 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, base),
2848 gen_rtx_HIGH (Pmode, delta)));
2849 i = emit_move_insn (gen_rtx_REG (Pmode, reg),
2850 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
2857 compute_frame_size (size, fregs_live)
2863 /* Space for frame pointer + filler. If any frame is allocated
2864 we need to add this in because of STARTING_FRAME_OFFSET.
2866 Similar code also appears in hppa_expand_prologue. Change both
2867 of them at the same time. */
2868 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
2870 /* Account for space used by the callee general register saves. */
2871 for (i = 18; i >= 3; i--)
2872 if (regs_ever_live[i])
2873 fsize += UNITS_PER_WORD;
2875 /* Round the stack. */
2876 fsize = (fsize + 7) & ~7;
2878 /* Account for space used by the callee floating point register saves. */
2879 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
2880 if (regs_ever_live[i]
2881 || (! TARGET_64BIT && regs_ever_live[i + 1]))
2886 /* We always save both halves of the FP register, so always
2887 increment the frame size by 8 bytes. */
2891 /* The various ABIs include space for the outgoing parameters in the
2892 size of the current function's stack frame. */
2893 fsize += current_function_outgoing_args_size;
2895 /* Allocate space for the fixed frame marker. This space must be
2896 allocated for any function that makes calls or otherwise allocates
2898 if (!current_function_is_leaf || fsize)
2899 fsize += TARGET_64BIT ? 16 : 32;
2901 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
2904 /* Generate the assembly code for function entry. FILE is a stdio
2905 stream to output the code to. SIZE is an int: how many units of
2906 temporary storage to allocate.
2908 Refer to the array `regs_ever_live' to determine which registers to
2909 save; `regs_ever_live[I]' is nonzero if register number I is ever
2910 used in the function. This function is responsible for knowing
2911 which registers should not be saved even if used. */
2913 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
2914 of memory. If any fpu reg is used in the function, we allocate
2915 such a block here, at the bottom of the frame, just in case it's needed.
2917 If this function is a leaf procedure, then we may choose not
2918 to do a "save" insn. The decision about whether or not
2919 to do this is made in regclass.c. */
2922 pa_output_function_prologue (file, size)
2924 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2926 /* The function's label and associated .PROC must never be
2927 separated and must be output *after* any profiling declarations
2928 to avoid changing spaces/subspaces within a procedure. */
2929 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
2930 fputs ("\t.PROC\n", file);
2932 /* hppa_expand_prologue does the dirty work now. We just need
2933 to output the assembler directives which denote the start
2935 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
2936 if (regs_ever_live[2])
2937 fputs (",CALLS,SAVE_RP", file);
2939 fputs (",NO_CALLS", file);
2941 if (frame_pointer_needed)
2942 fputs (",SAVE_SP", file);
2944 /* Pass on information about the number of callee register saves
2945 performed in the prologue.
2947 The compiler is supposed to pass the highest register number
2948 saved, the assembler then has to adjust that number before
2949 entering it into the unwind descriptor (to account for any
2950 caller saved registers with lower register numbers than the
2951 first callee saved register). */
2953 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
2956 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
2958 fputs ("\n\t.ENTRY\n", file);
2960 /* If we're using GAS and not using the portable runtime model, then
2961 we don't need to accumulate the total number of code bytes. */
2962 if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
2963 total_code_bytes = 0;
2964 else if (INSN_ADDRESSES_SET_P ())
2966 unsigned int old_total = total_code_bytes;
2968 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_insn ()));
2969 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
2971 /* Be prepared to handle overflows. */
2972 if (old_total > total_code_bytes)
2973 total_code_bytes = -1;
2976 total_code_bytes = -1;
2978 remove_useless_addtr_insns (get_insns (), 0);
2986 RTX_FRAME_RELATED_P (insn) = 1; \
2990 #define FRP(INSN) INSN
2994 hppa_expand_prologue ()
2996 extern char call_used_regs[];
2997 int size = get_frame_size ();
2998 int merge_sp_adjust_with_store = 0;
3000 rtx tmpreg, size_rtx;
3006 /* Allocate space for frame pointer + filler. If any frame is allocated
3007 we need to add this in because of STARTING_FRAME_OFFSET.
3009 Similar code also appears in compute_frame_size. Change both
3010 of them at the same time. */
3011 local_fsize = size + (size || frame_pointer_needed
3012 ? STARTING_FRAME_OFFSET : 0);
3014 actual_fsize = compute_frame_size (size, &save_fregs);
3016 /* Compute a few things we will use often. */
3017 tmpreg = gen_rtx_REG (word_mode, 1);
3018 size_rtx = GEN_INT (actual_fsize);
3020 /* Save RP first. The calling conventions manual states RP will
3021 always be stored into the caller's frame at sp - 20 or sp - 16
3022 depending on which ABI is in use. */
3023 if (regs_ever_live[2])
3024 FRP (store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM));
3026 /* Allocate the local frame and set up the frame pointer if needed. */
3027 if (actual_fsize != 0)
3029 if (frame_pointer_needed)
3031 /* Copy the old frame pointer temporarily into %r1. Set up the
3032 new stack pointer, then store away the saved old frame pointer
3033 into the stack at sp+actual_fsize and at the same time update
3034 the stack pointer by actual_fsize bytes. Two versions, first
3035 handles small (<8k) frames. The second handles large (>=8k)
3037 emit_move_insn (tmpreg, frame_pointer_rtx);
3038 FRP (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx));
3039 if (VAL_14_BITS_P (actual_fsize))
3041 rtx insn = emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
3046 RTX_FRAME_RELATED_P (insn) = 1;
3048 gen_rtx_SET (VOIDmode,
3049 gen_rtx_MEM (word_mode,
3052 gen_rtx_SET (VOIDmode,
3054 gen_rtx_PLUS (word_mode,
3058 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3059 gen_rtx_SEQUENCE (VOIDmode, vec),
3065 /* It is incorrect to store the saved frame pointer at *sp,
3066 then increment sp (writes beyond the current stack boundary).
3068 So instead use stwm to store at *sp and post-increment the
3069 stack pointer as an atomic operation. Then increment sp to
3070 finish allocating the new frame. */
3071 int adjust1 = 8192 - 64;
3072 int adjust2 = actual_fsize - adjust1;
3073 rtx delta = GEN_INT (adjust1);
3074 rtx insn = emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
3079 RTX_FRAME_RELATED_P (insn) = 1;
3081 gen_rtx_SET (VOIDmode,
3082 gen_rtx_MEM (word_mode,
3085 gen_rtx_SET (VOIDmode,
3087 gen_rtx_PLUS (word_mode,
3091 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3092 gen_rtx_SEQUENCE (VOIDmode, vec),
3096 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3097 STACK_POINTER_REGNUM,
3100 /* Prevent register spills from being scheduled before the
3101 stack pointer is raised. Necessary as we will be storing
3102 registers using the frame pointer as a base register, and
3103 we happen to set fp before raising sp. */
3104 emit_insn (gen_blockage ());
3106 /* no frame pointer needed. */
3109 /* In some cases we can perform the first callee register save
3110 and allocating the stack frame at the same time. If so, just
3111 make a note of it and defer allocating the frame until saving
3112 the callee registers. */
3113 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3114 merge_sp_adjust_with_store = 1;
3115 /* Can not optimize. Adjust the stack frame by actual_fsize
3118 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3119 STACK_POINTER_REGNUM,
3124 /* Normal register save.
3126 Do not save the frame pointer in the frame_pointer_needed case. It
3127 was done earlier. */
3128 if (frame_pointer_needed)
3130 for (i = 18, offset = local_fsize; i >= 4; i--)
3131 if (regs_ever_live[i] && ! call_used_regs[i])
3133 FRP (store_reg (i, offset, FRAME_POINTER_REGNUM));
3134 offset += UNITS_PER_WORD;
3137 /* Account for %r3 which is saved in a special place. */
3140 /* No frame pointer needed. */
3143 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3144 if (regs_ever_live[i] && ! call_used_regs[i])
3146 /* If merge_sp_adjust_with_store is nonzero, then we can
3147 optimize the first GR save. */
3148 if (merge_sp_adjust_with_store)
3150 rtx delta = GEN_INT (-offset);
3151 merge_sp_adjust_with_store = 0;
3152 FRP (emit_insn (gen_post_store (stack_pointer_rtx,
3153 gen_rtx_REG (word_mode, i),
3157 FRP (store_reg (i, offset, STACK_POINTER_REGNUM));
3158 offset += UNITS_PER_WORD;
3162 /* If we wanted to merge the SP adjustment with a GR save, but we never
3163 did any GR saves, then just emit the adjustment here. */
3164 if (merge_sp_adjust_with_store)
3165 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3166 STACK_POINTER_REGNUM,
3170 /* The hppa calling conventions say that %r19, the pic offset
3171 register, is saved at sp - 32 (in this function's frame)
3172 when generating PIC code. FIXME: What is the correct thing
3173 to do for functions which make no calls and allocate no
3174 frame? Do we need to allocate a frame, or can we just omit
3175 the save? For now we'll just omit the save. */
3176 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3177 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3179 /* Align pointer properly (doubleword boundary). */
3180 offset = (offset + 7) & ~7;
3182 /* Floating point register store. */
3185 /* First get the frame or stack pointer to the start of the FP register
3187 if (frame_pointer_needed)
3188 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset));
3190 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM, offset));
3192 /* Now actually save the FP registers. */
3193 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3195 if (regs_ever_live[i]
3196 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3199 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3200 reg = gen_rtx_REG (DFmode, i);
3201 FRP (emit_move_insn (addr, reg));
3208 /* ?!? Do we want frame notes in the epilogue yet? */
3209 #undef DO_FRAME_NOTES
3210 #define DO_FRAME_NOTES 0
3212 #define FRP(INSN) INSN
3214 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3215 Handle case where DISP > 8k by using the add_high_const patterns. */
3218 load_reg (reg, disp, base)
3219 int reg, disp, base;
3221 rtx i, src, dest, basereg;
3223 dest = gen_rtx_REG (word_mode, reg);
3224 basereg = gen_rtx_REG (Pmode, base);
3225 if (VAL_14_BITS_P (disp))
3227 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3228 i = emit_move_insn (dest, src);
3232 rtx delta = GEN_INT (disp);
3233 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3234 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3235 emit_move_insn (tmpreg, high);
3236 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3237 i = emit_move_insn (dest, src);
3242 /* This function generates the assembly code for function exit.
3243 Args are as for output_function_prologue ().
3245 The function epilogue should not depend on the current stack
3246 pointer! It should use the frame pointer only. This is mandatory
3247 because of alloca; we also take advantage of it to omit stack
3248 adjustments before returning. */
3251 pa_output_function_epilogue (file, size)
3253 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3255 rtx insn = get_last_insn ();
3257 /* hppa_expand_epilogue does the dirty work now. We just need
3258 to output the assembler directives which denote the end
3261 To make debuggers happy, emit a nop if the epilogue was completely
3262 eliminated due to a volatile call as the last insn in the
3263 current function. That way the return address (in %r2) will
3264 always point to a valid instruction in the current function. */
3266 /* Get the last real insn. */
3267 if (GET_CODE (insn) == NOTE)
3268 insn = prev_real_insn (insn);
3270 /* If it is a sequence, then look inside. */
3271 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3272 insn = XVECEXP (PATTERN (insn), 0, 0);
3274 /* If insn is a CALL_INSN, then it must be a call to a volatile
3275 function (otherwise there would be epilogue insns). */
3276 if (insn && GET_CODE (insn) == CALL_INSN)
3277 fputs ("\tnop\n", file);
3279 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3283 hppa_expand_epilogue ()
3287 int merge_sp_adjust_with_load = 0;
3290 /* We will use this often. */
3291 tmpreg = gen_rtx_REG (word_mode, 1);
3293 /* Try to restore RP early to avoid load/use interlocks when
3294 RP gets used in the return (bv) instruction. This appears to still
3295 be necessary even when we schedule the prologue and epilogue. */
3296 if (regs_ever_live [2])
3298 ret_off = TARGET_64BIT ? -16 : -20;
3299 if (frame_pointer_needed)
3301 FRP (load_reg (2, ret_off, FRAME_POINTER_REGNUM));
3306 /* No frame pointer, and stack is smaller than 8k. */
3307 if (VAL_14_BITS_P (ret_off - actual_fsize))
3309 FRP (load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM));
3315 /* General register restores. */
3316 if (frame_pointer_needed)
3318 for (i = 18, offset = local_fsize; i >= 4; i--)
3319 if (regs_ever_live[i] && ! call_used_regs[i])
3321 FRP (load_reg (i, offset, FRAME_POINTER_REGNUM));
3322 offset += UNITS_PER_WORD;
3327 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3329 if (regs_ever_live[i] && ! call_used_regs[i])
3331 /* Only for the first load.
3332 merge_sp_adjust_with_load holds the register load
3333 with which we will merge the sp adjustment. */
3334 if (merge_sp_adjust_with_load == 0
3336 && VAL_14_BITS_P (-actual_fsize))
3337 merge_sp_adjust_with_load = i;
3339 FRP (load_reg (i, offset, STACK_POINTER_REGNUM));
3340 offset += UNITS_PER_WORD;
3345 /* Align pointer properly (doubleword boundary). */
3346 offset = (offset + 7) & ~7;
3348 /* FP register restores. */
3351 /* Adjust the register to index off of. */
3352 if (frame_pointer_needed)
3353 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset));
3355 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM, offset));
3357 /* Actually do the restores now. */
3358 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3359 if (regs_ever_live[i]
3360 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3362 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3363 rtx dest = gen_rtx_REG (DFmode, i);
3364 FRP (emit_move_insn (dest, src));
3368 /* Emit a blockage insn here to keep these insns from being moved to
3369 an earlier spot in the epilogue, or into the main instruction stream.
3371 This is necessary as we must not cut the stack back before all the
3372 restores are finished. */
3373 emit_insn (gen_blockage ());
3375 /* Reset stack pointer (and possibly frame pointer). The stack
3376 pointer is initially set to fp + 64 to avoid a race condition. */
3377 if (frame_pointer_needed)
3379 rtx delta = GEN_INT (-64);
3380 FRP (set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64));
3381 FRP (emit_insn (gen_pre_load (frame_pointer_rtx,
3385 /* If we were deferring a callee register restore, do it now. */
3386 else if (merge_sp_adjust_with_load)
3388 rtx delta = GEN_INT (-actual_fsize);
3389 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3390 FRP (emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)));
3392 else if (actual_fsize != 0)
3393 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3394 STACK_POINTER_REGNUM,
3397 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3398 frame greater than 8k), do so now. */
3400 FRP (load_reg (2, ret_off, STACK_POINTER_REGNUM));
3404 hppa_pic_save_rtx ()
3406 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3410 hppa_profile_hook (label_no)
3411 int label_no ATTRIBUTE_UNUSED;
3415 /* No profiling for inline functions. We don't want extra calls to
3416 _mcount when the inline function is expanded. Even if that made
3417 sense, it wouldn't work here as there is no function label for
3418 the inline expansion. */
3419 if (DECL_INLINE (cfun->decl))
3423 emit_move_insn (arg_pointer_rtx,
3424 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3427 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3429 #ifndef NO_PROFILE_COUNTERS
3431 rtx count_label_rtx, addr, r24;
3432 char label_name[16];
3434 ASM_GENERATE_INTERNAL_LABEL (label_name, "LP", label_no);
3435 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (label_name));
3441 current_function_uses_pic_offset_table = 1;
3442 tmpreg = gen_rtx_REG (Pmode, 1);
3443 emit_move_insn (tmpreg,
3444 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3445 gen_rtx_HIGH (Pmode, count_label_rtx)));
3446 addr = gen_rtx_MEM (Pmode,
3447 gen_rtx_LO_SUM (Pmode, tmpreg, count_label_rtx));
3451 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3452 emit_move_insn (tmpreg, gen_rtx_HIGH (Pmode, count_label_rtx));
3453 addr = gen_rtx_LO_SUM (Pmode, tmpreg, count_label_rtx);
3455 r24 = gen_rtx_REG (Pmode, 24);
3456 emit_move_insn (r24, addr);
3458 /* %r25 is set from within the output pattern. */
3460 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3461 GEN_INT (TARGET_64BIT ? 24 : 12),
3462 XEXP (DECL_RTL (cfun->decl), 0)));
3464 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3467 /* %r25 is set from within the output pattern. */
3469 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3470 GEN_INT (TARGET_64BIT ? 16 : 8),
3471 XEXP (DECL_RTL (cfun->decl), 0)));
3474 /* Indicate the _mcount call cannot throw, nor will it execute a
3476 REG_NOTES (call_insn)
3477 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3481 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3483 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3485 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3489 /* Fetch the return address for the frame COUNT steps up from
3490 the current frame, after the prologue. FRAMEADDR is the
3491 frame pointer of the COUNT frame.
3493 We want to ignore any export stub remnants here. To handle this,
3494 we examine the code at the return address, and if it is an export
3495 stub, we return a memory rtx for the stub return address stored
3498 The value returned is used in two different ways:
3500 1. To find a function's caller.
3502 2. To change the return address for a function.
3504 This function handles most instances of case 1; however, it will
3505 fail if there are two levels of stubs to execute on the return
3506 path. The only way I believe that can happen is if the return value
3507 needs a parameter relocation, which never happens for C code.
3509 This function handles most instances of case 2; however, it will
3510 fail if we did not originally have stub code on the return path
3511 but will need stub code on the new return path. This can happen if
3512 the caller & callee are both in the main program, but the new
3513 return location is in a shared library. */
3516 return_addr_rtx (count, frameaddr)
3528 rp = get_hard_reg_initial_val (Pmode, 2);
3530 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
3533 saved_rp = gen_reg_rtx (Pmode);
3534 emit_move_insn (saved_rp, rp);
3536 /* Get pointer to the instruction stream. We have to mask out the
3537 privilege level from the two low order bits of the return address
3538 pointer here so that ins will point to the start of the first
3539 instruction that would have been executed if we returned. */
3540 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
3541 label = gen_label_rtx ();
3543 /* Check the instruction stream at the normal return address for the
3546 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3547 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3548 0x00011820 | stub+16: mtsp r1,sr0
3549 0xe0400002 | stub+20: be,n 0(sr0,rp)
3551 If it is an export stub, than our return address is really in
3554 emit_cmp_insn (gen_rtx_MEM (SImode, ins),
3555 GEN_INT (0x4bc23fd1),
3556 NE, NULL_RTX, SImode, 1, 0);
3557 emit_jump_insn (gen_bne (label));
3559 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3560 GEN_INT (0x004010a1),
3561 NE, NULL_RTX, SImode, 1, 0);
3562 emit_jump_insn (gen_bne (label));
3564 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3565 GEN_INT (0x00011820),
3566 NE, NULL_RTX, SImode, 1, 0);
3567 emit_jump_insn (gen_bne (label));
3569 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3570 GEN_INT (0xe0400002),
3571 NE, NULL_RTX, SImode, 1, 0);
3573 /* If there is no export stub then just use the value saved from
3574 the return pointer register. */
3576 emit_jump_insn (gen_bne (label));
3578 /* Here we know that our return address points to an export
3579 stub. We don't want to return the address of the export stub,
3580 but rather the return address of the export stub. That return
3581 address is stored at -24[frameaddr]. */
3583 emit_move_insn (saved_rp,
3585 memory_address (Pmode,
3586 plus_constant (frameaddr,
3593 /* This is only valid once reload has completed because it depends on
3594 knowing exactly how much (if any) frame there is and...
3596 It's only valid if there is no frame marker to de-allocate and...
3598 It's only valid if %r2 hasn't been saved into the caller's frame
3599 (we're not profiling and %r2 isn't live anywhere). */
3601 hppa_can_use_return_insn_p ()
3603 return (reload_completed
3604 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3605 && ! regs_ever_live[2]
3606 && ! frame_pointer_needed);
3610 emit_bcond_fp (code, operand0)
3614 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3615 gen_rtx_IF_THEN_ELSE (VOIDmode,
3616 gen_rtx_fmt_ee (code,
3618 gen_rtx_REG (CCFPmode, 0),
3620 gen_rtx_LABEL_REF (VOIDmode, operand0),
3626 gen_cmp_fp (code, operand0, operand1)
3628 rtx operand0, operand1;
3630 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3631 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3634 /* Adjust the cost of a scheduling dependency. Return the new cost of
3635 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3638 pa_adjust_cost (insn, link, dep_insn, cost)
3644 enum attr_type attr_type;
3646 /* Don't adjust costs for a pa8000 chip. */
3647 if (pa_cpu >= PROCESSOR_8000)
3650 if (! recog_memoized (insn))
3653 attr_type = get_attr_type (insn);
3655 if (REG_NOTE_KIND (link) == 0)
3657 /* Data dependency; DEP_INSN writes a register that INSN reads some
3660 if (attr_type == TYPE_FPSTORE)
3662 rtx pat = PATTERN (insn);
3663 rtx dep_pat = PATTERN (dep_insn);
3664 if (GET_CODE (pat) == PARALLEL)
3666 /* This happens for the fstXs,mb patterns. */
3667 pat = XVECEXP (pat, 0, 0);
3669 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3670 /* If this happens, we have to extend this to schedule
3671 optimally. Return 0 for now. */
3674 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
3676 if (! recog_memoized (dep_insn))
3678 /* DEP_INSN is writing its result to the register
3679 being stored in the fpstore INSN. */
3680 switch (get_attr_type (dep_insn))
3683 /* This cost 3 cycles, not 2 as the md says for the
3692 case TYPE_FPSQRTSGL:
3693 case TYPE_FPSQRTDBL:
3694 /* In these important cases, we save one cycle compared to
3695 when flop instruction feed each other. */
3704 /* For other data dependencies, the default cost specified in the
3708 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3710 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3713 if (attr_type == TYPE_FPLOAD)
3715 rtx pat = PATTERN (insn);
3716 rtx dep_pat = PATTERN (dep_insn);
3717 if (GET_CODE (pat) == PARALLEL)
3719 /* This happens for the fldXs,mb patterns. */
3720 pat = XVECEXP (pat, 0, 0);
3722 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3723 /* If this happens, we have to extend this to schedule
3724 optimally. Return 0 for now. */
3727 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3729 if (! recog_memoized (dep_insn))
3731 switch (get_attr_type (dep_insn))
3738 case TYPE_FPSQRTSGL:
3739 case TYPE_FPSQRTDBL:
3740 /* A fpload can't be issued until one cycle before a
3741 preceding arithmetic operation has finished if
3742 the target of the fpload is any of the sources
3743 (or destination) of the arithmetic operation. */
3751 else if (attr_type == TYPE_FPALU)
3753 rtx pat = PATTERN (insn);
3754 rtx dep_pat = PATTERN (dep_insn);
3755 if (GET_CODE (pat) == PARALLEL)
3757 /* This happens for the fldXs,mb patterns. */
3758 pat = XVECEXP (pat, 0, 0);
3760 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3761 /* If this happens, we have to extend this to schedule
3762 optimally. Return 0 for now. */
3765 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3767 if (! recog_memoized (dep_insn))
3769 switch (get_attr_type (dep_insn))
3773 case TYPE_FPSQRTSGL:
3774 case TYPE_FPSQRTDBL:
3775 /* An ALU flop can't be issued until two cycles before a
3776 preceding divide or sqrt operation has finished if
3777 the target of the ALU flop is any of the sources
3778 (or destination) of the divide or sqrt operation. */
3787 /* For other anti dependencies, the cost is 0. */
3790 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3792 /* Output dependency; DEP_INSN writes a register that INSN writes some
3794 if (attr_type == TYPE_FPLOAD)
3796 rtx pat = PATTERN (insn);
3797 rtx dep_pat = PATTERN (dep_insn);
3798 if (GET_CODE (pat) == PARALLEL)
3800 /* This happens for the fldXs,mb patterns. */
3801 pat = XVECEXP (pat, 0, 0);
3803 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3804 /* If this happens, we have to extend this to schedule
3805 optimally. Return 0 for now. */
3808 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3810 if (! recog_memoized (dep_insn))
3812 switch (get_attr_type (dep_insn))
3819 case TYPE_FPSQRTSGL:
3820 case TYPE_FPSQRTDBL:
3821 /* A fpload can't be issued until one cycle before a
3822 preceding arithmetic operation has finished if
3823 the target of the fpload is the destination of the
3824 arithmetic operation. */
3832 else if (attr_type == TYPE_FPALU)
3834 rtx pat = PATTERN (insn);
3835 rtx dep_pat = PATTERN (dep_insn);
3836 if (GET_CODE (pat) == PARALLEL)
3838 /* This happens for the fldXs,mb patterns. */
3839 pat = XVECEXP (pat, 0, 0);
3841 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3842 /* If this happens, we have to extend this to schedule
3843 optimally. Return 0 for now. */
3846 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3848 if (! recog_memoized (dep_insn))
3850 switch (get_attr_type (dep_insn))
3854 case TYPE_FPSQRTSGL:
3855 case TYPE_FPSQRTDBL:
3856 /* An ALU flop can't be issued until two cycles before a
3857 preceding divide or sqrt operation has finished if
3858 the target of the ALU flop is also the target of
3859 the divide or sqrt operation. */
3868 /* For other output dependencies, the cost is 0. */
3875 /* Adjust scheduling priorities. We use this to try and keep addil
3876 and the next use of %r1 close together. */
3878 pa_adjust_priority (insn, priority)
3882 rtx set = single_set (insn);
3886 src = SET_SRC (set);
3887 dest = SET_DEST (set);
3888 if (GET_CODE (src) == LO_SUM
3889 && symbolic_operand (XEXP (src, 1), VOIDmode)
3890 && ! read_only_operand (XEXP (src, 1), VOIDmode))
3893 else if (GET_CODE (src) == MEM
3894 && GET_CODE (XEXP (src, 0)) == LO_SUM
3895 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
3896 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
3899 else if (GET_CODE (dest) == MEM
3900 && GET_CODE (XEXP (dest, 0)) == LO_SUM
3901 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
3902 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
3908 /* The 700 can only issue a single insn at a time.
3909 The 7XXX processors can issue two insns at a time.
3910 The 8000 can issue 4 insns at a time. */
3916 case PROCESSOR_700: return 1;
3917 case PROCESSOR_7100: return 2;
3918 case PROCESSOR_7100LC: return 2;
3919 case PROCESSOR_7200: return 2;
3920 case PROCESSOR_8000: return 4;
3929 /* Return any length adjustment needed by INSN which already has its length
3930 computed as LENGTH. Return zero if no adjustment is necessary.
3932 For the PA: function calls, millicode calls, and backwards short
3933 conditional branches with unfilled delay slots need an adjustment by +1
3934 (to account for the NOP which will be inserted into the instruction stream).
3936 Also compute the length of an inline block move here as it is too
3937 complicated to express as a length attribute in pa.md. */
3939 pa_adjust_insn_length (insn, length)
3943 rtx pat = PATTERN (insn);
3945 /* Call insns which are *not* indirect and have unfilled delay slots. */
3946 if (GET_CODE (insn) == CALL_INSN)
3949 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
3950 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
3952 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
3953 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
3959 /* Jumps inside switch tables which have unfilled delay slots
3960 also need adjustment. */
3961 else if (GET_CODE (insn) == JUMP_INSN
3962 && simplejump_p (insn)
3963 && GET_MODE (insn) == SImode)
3965 /* Millicode insn with an unfilled delay slot. */
3966 else if (GET_CODE (insn) == INSN
3967 && GET_CODE (pat) != SEQUENCE
3968 && GET_CODE (pat) != USE
3969 && GET_CODE (pat) != CLOBBER
3970 && get_attr_type (insn) == TYPE_MILLI)
3972 /* Block move pattern. */
3973 else if (GET_CODE (insn) == INSN
3974 && GET_CODE (pat) == PARALLEL
3975 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3976 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
3977 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
3978 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
3979 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
3980 return compute_movstrsi_length (insn) - 4;
3981 /* Conditional branch with an unfilled delay slot. */
3982 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
3984 /* Adjust a short backwards conditional with an unfilled delay slot. */
3985 if (GET_CODE (pat) == SET
3987 && ! forward_branch_p (insn))
3989 else if (GET_CODE (pat) == PARALLEL
3990 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
3993 /* Adjust dbra insn with short backwards conditional branch with
3994 unfilled delay slot -- only for case where counter is in a
3995 general register register. */
3996 else if (GET_CODE (pat) == PARALLEL
3997 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
3998 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
3999 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4001 && ! forward_branch_p (insn))
4009 /* Print operand X (an rtx) in assembler syntax to file FILE.
4010 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4011 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4014 print_operand (file, x, code)
4022 /* Output a 'nop' if there's nothing for the delay slot. */
4023 if (dbr_sequence_length () == 0)
4024 fputs ("\n\tnop", file);
4027 /* Output an nullification completer if there's nothing for the */
4028 /* delay slot or nullification is requested. */
4029 if (dbr_sequence_length () == 0 ||
4031 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4035 /* Print out the second register name of a register pair.
4036 I.e., R (6) => 7. */
4037 fputs (reg_names[REGNO (x) + 1], file);
4040 /* A register or zero. */
4042 || (x == CONST0_RTX (DFmode))
4043 || (x == CONST0_RTX (SFmode)))
4045 fputs ("%r0", file);
4051 /* A register or zero (floating point). */
4053 || (x == CONST0_RTX (DFmode))
4054 || (x == CONST0_RTX (SFmode)))
4056 fputs ("%fr0", file);
4065 xoperands[0] = XEXP (XEXP (x, 0), 0);
4066 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4067 output_global_address (file, xoperands[1], 0);
4068 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4072 case 'C': /* Plain (C)ondition */
4074 switch (GET_CODE (x))
4077 fputs ("=", file); break;
4079 fputs ("<>", file); break;
4081 fputs (">", file); break;
4083 fputs (">=", file); break;
4085 fputs (">>=", file); break;
4087 fputs (">>", file); break;
4089 fputs ("<", file); break;
4091 fputs ("<=", file); break;
4093 fputs ("<<=", file); break;
4095 fputs ("<<", file); break;
4100 case 'N': /* Condition, (N)egated */
4101 switch (GET_CODE (x))
4104 fputs ("<>", file); break;
4106 fputs ("=", file); break;
4108 fputs ("<=", file); break;
4110 fputs ("<", file); break;
4112 fputs ("<<", file); break;
4114 fputs ("<<=", file); break;
4116 fputs (">=", file); break;
4118 fputs (">", file); break;
4120 fputs (">>", file); break;
4122 fputs (">>=", file); break;
4127 /* For floating point comparisons. Note that the output
4128 predicates are the complement of the desired mode. */
4130 switch (GET_CODE (x))
4133 fputs ("!=", file); break;
4135 fputs ("=", file); break;
4137 fputs ("!>", file); break;
4139 fputs ("!>=", file); break;
4141 fputs ("!<", file); break;
4143 fputs ("!<=", file); break;
4145 fputs ("!<>", file); break;
4147 fputs (">", file); break;
4149 fputs (">=", file); break;
4151 fputs ("<", file); break;
4153 fputs ("<=", file); break;
4155 fputs ("<>", file); break;
4157 fputs ("<=>", file); break;
4159 fputs ("!<=>", file); break;
4164 case 'S': /* Condition, operands are (S)wapped. */
4165 switch (GET_CODE (x))
4168 fputs ("=", file); break;
4170 fputs ("<>", file); break;
4172 fputs ("<", file); break;
4174 fputs ("<=", file); break;
4176 fputs ("<<=", file); break;
4178 fputs ("<<", file); break;
4180 fputs (">", file); break;
4182 fputs (">=", file); break;
4184 fputs (">>=", file); break;
4186 fputs (">>", file); break;
4191 case 'B': /* Condition, (B)oth swapped and negate. */
4192 switch (GET_CODE (x))
4195 fputs ("<>", file); break;
4197 fputs ("=", file); break;
4199 fputs (">=", file); break;
4201 fputs (">", file); break;
4203 fputs (">>", file); break;
4205 fputs (">>=", file); break;
4207 fputs ("<=", file); break;
4209 fputs ("<", file); break;
4211 fputs ("<<", file); break;
4213 fputs ("<<=", file); break;
4219 if (GET_CODE (x) == CONST_INT)
4221 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4226 if (GET_CODE (x) == CONST_INT)
4228 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4233 if (GET_CODE (x) == CONST_INT)
4235 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4240 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4242 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4247 if (GET_CODE (x) == CONST_INT)
4249 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4254 if (GET_CODE (x) == CONST_INT)
4256 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4261 if (GET_CODE (x) == CONST_INT)
4266 switch (GET_CODE (XEXP (x, 0)))
4270 if (ASSEMBLER_DIALECT == 0)
4271 fputs ("s,mb", file);
4273 fputs (",mb", file);
4277 if (ASSEMBLER_DIALECT == 0)
4278 fputs ("s,ma", file);
4280 fputs (",ma", file);
4283 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4284 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4286 if (ASSEMBLER_DIALECT == 0)
4287 fputs ("x,s", file);
4291 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4295 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4301 output_global_address (file, x, 0);
4304 output_global_address (file, x, 1);
4306 case 0: /* Don't do anything special */
4311 compute_zdepwi_operands (INTVAL (x), op);
4312 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4318 compute_zdepdi_operands (INTVAL (x), op);
4319 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4323 /* We can get here from a .vtable_inherit due to our
4324 CONSTANT_ADDRESS_P rejecting perfectly good constant
4330 if (GET_CODE (x) == REG)
4332 fputs (reg_names [REGNO (x)], file);
4333 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4339 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4340 && (REGNO (x) & 1) == 0)
4343 else if (GET_CODE (x) == MEM)
4345 int size = GET_MODE_SIZE (GET_MODE (x));
4346 rtx base = NULL_RTX;
4347 switch (GET_CODE (XEXP (x, 0)))
4351 base = XEXP (XEXP (x, 0), 0);
4352 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4356 base = XEXP (XEXP (x, 0), 0);
4357 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4360 if (GET_CODE (XEXP (x, 0)) == PLUS
4361 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4362 fprintf (file, "%s(%s)",
4363 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4364 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4365 else if (GET_CODE (XEXP (x, 0)) == PLUS
4366 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4367 fprintf (file, "%s(%s)",
4368 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4369 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4371 output_address (XEXP (x, 0));
4376 output_addr_const (file, x);
4379 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4382 output_global_address (file, x, round_constant)
4388 /* Imagine (high (const (plus ...))). */
4389 if (GET_CODE (x) == HIGH)
4392 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4393 assemble_name (file, XSTR (x, 0));
4394 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4396 assemble_name (file, XSTR (x, 0));
4397 fputs ("-$global$", file);
4399 else if (GET_CODE (x) == CONST)
4401 const char *sep = "";
4402 int offset = 0; /* assembler wants -$global$ at end */
4403 rtx base = NULL_RTX;
4405 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4407 base = XEXP (XEXP (x, 0), 0);
4408 output_addr_const (file, base);
4410 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4411 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4414 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4416 base = XEXP (XEXP (x, 0), 1);
4417 output_addr_const (file, base);
4419 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4420 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4423 /* How bogus. The compiler is apparently responsible for
4424 rounding the constant if it uses an LR field selector.
4426 The linker and/or assembler seem a better place since
4427 they have to do this kind of thing already.
4429 If we fail to do this, HP's optimizing linker may eliminate
4430 an addil, but not update the ldw/stw/ldo instruction that
4431 uses the result of the addil. */
4433 offset = ((offset + 0x1000) & ~0x1fff);
4435 if (GET_CODE (XEXP (x, 0)) == PLUS)
4445 else if (GET_CODE (XEXP (x, 0)) == MINUS
4446 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4450 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4451 fputs ("-$global$", file);
4453 fprintf (file, "%s%d", sep, offset);
4456 output_addr_const (file, x);
4460 output_deferred_plabels (file)
4464 /* If we have deferred plabels, then we need to switch into the data
4465 section and align it to a 4 byte boundary before we output the
4466 deferred plabels. */
4467 if (n_deferred_plabels)
4470 ASM_OUTPUT_ALIGN (file, 2);
4473 /* Now output the deferred plabels. */
4474 for (i = 0; i < n_deferred_plabels; i++)
4476 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4477 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4482 /* HP's millicode routines mean something special to the assembler.
4483 Keep track of which ones we have used. */
4485 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
4486 static void import_milli PARAMS ((enum millicodes));
4487 static char imported[(int) end1000];
4488 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4489 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4490 #define MILLI_START 10
4494 enum millicodes code;
4496 char str[sizeof (import_string)];
4498 if (!imported[(int) code])
4500 imported[(int) code] = 1;
4501 strcpy (str, import_string);
4502 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4503 output_asm_insn (str, 0);
4507 /* The register constraints have put the operands and return value in
4508 the proper registers. */
4511 output_mul_insn (unsignedp, insn)
4512 int unsignedp ATTRIBUTE_UNUSED;
4515 import_milli (mulI);
4516 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4519 /* Emit the rtl for doing a division by a constant. */
4521 /* Do magic division millicodes exist for this value? */
4522 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4525 /* We'll use an array to keep track of the magic millicodes and
4526 whether or not we've used them already. [n][0] is signed, [n][1] is
4529 static int div_milli[16][2];
4532 div_operand (op, mode)
4534 enum machine_mode mode;
4536 return (mode == SImode
4537 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4538 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4539 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4543 emit_hpdiv_const (operands, unsignedp)
4547 if (GET_CODE (operands[2]) == CONST_INT
4548 && INTVAL (operands[2]) > 0
4549 && INTVAL (operands[2]) < 16
4550 && magic_milli[INTVAL (operands[2])])
4552 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4554 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4557 (PARALLEL, VOIDmode,
4558 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4559 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4561 gen_rtx_REG (SImode, 26),
4563 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4564 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4565 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4566 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4567 gen_rtx_CLOBBER (VOIDmode, ret))));
4568 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4575 output_div_insn (operands, unsignedp, insn)
4582 /* If the divisor is a constant, try to use one of the special
4584 if (GET_CODE (operands[0]) == CONST_INT)
4586 static char buf[100];
4587 divisor = INTVAL (operands[0]);
4588 if (!div_milli[divisor][unsignedp])
4590 div_milli[divisor][unsignedp] = 1;
4592 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4594 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4598 sprintf (buf, "$$divU_");
4599 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4600 return output_millicode_call (insn,
4601 gen_rtx_SYMBOL_REF (SImode, buf));
4605 sprintf (buf, "$$divI_");
4606 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4607 return output_millicode_call (insn,
4608 gen_rtx_SYMBOL_REF (SImode, buf));
4611 /* Divisor isn't a special constant. */
4616 import_milli (divU);
4617 return output_millicode_call (insn,
4618 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4622 import_milli (divI);
4623 return output_millicode_call (insn,
4624 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4629 /* Output a $$rem millicode to do mod. */
4632 output_mod_insn (unsignedp, insn)
4638 import_milli (remU);
4639 return output_millicode_call (insn,
4640 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4644 import_milli (remI);
4645 return output_millicode_call (insn,
4646 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4651 output_arg_descriptor (call_insn)
4654 const char *arg_regs[4];
4655 enum machine_mode arg_mode;
4657 int i, output_flag = 0;
4660 /* We neither need nor want argument location descriptors for the
4661 64bit runtime environment or the ELF32 environment. */
4662 if (TARGET_64BIT || TARGET_ELF32)
4665 for (i = 0; i < 4; i++)
4668 /* Specify explicitly that no argument relocations should take place
4669 if using the portable runtime calling conventions. */
4670 if (TARGET_PORTABLE_RUNTIME)
4672 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4677 if (GET_CODE (call_insn) != CALL_INSN)
4679 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4681 rtx use = XEXP (link, 0);
4683 if (! (GET_CODE (use) == USE
4684 && GET_CODE (XEXP (use, 0)) == REG
4685 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4688 arg_mode = GET_MODE (XEXP (use, 0));
4689 regno = REGNO (XEXP (use, 0));
4690 if (regno >= 23 && regno <= 26)
4692 arg_regs[26 - regno] = "GR";
4693 if (arg_mode == DImode)
4694 arg_regs[25 - regno] = "GR";
4696 else if (regno >= 32 && regno <= 39)
4698 if (arg_mode == SFmode)
4699 arg_regs[(regno - 32) / 2] = "FR";
4702 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4703 arg_regs[(regno - 34) / 2] = "FR";
4704 arg_regs[(regno - 34) / 2 + 1] = "FU";
4706 arg_regs[(regno - 34) / 2] = "FU";
4707 arg_regs[(regno - 34) / 2 + 1] = "FR";
4712 fputs ("\t.CALL ", asm_out_file);
4713 for (i = 0; i < 4; i++)
4718 fputc (',', asm_out_file);
4719 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4722 fputc ('\n', asm_out_file);
4725 /* Return the class of any secondary reload register that is needed to
4726 move IN into a register in class CLASS using mode MODE.
4728 Profiling has showed this routine and its descendants account for
4729 a significant amount of compile time (~7%). So it has been
4730 optimized to reduce redundant computations and eliminate useless
4733 It might be worthwhile to try and make this a leaf function too. */
4736 secondary_reload_class (class, mode, in)
4737 enum reg_class class;
4738 enum machine_mode mode;
4741 int regno, is_symbolic;
4743 /* Trying to load a constant into a FP register during PIC code
4744 generation will require %r1 as a scratch register. */
4746 && GET_MODE_CLASS (mode) == MODE_INT
4747 && FP_REG_CLASS_P (class)
4748 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4751 /* Profiling showed the PA port spends about 1.3% of its compilation
4752 time in true_regnum from calls inside secondary_reload_class. */
4754 if (GET_CODE (in) == REG)
4757 if (regno >= FIRST_PSEUDO_REGISTER)
4758 regno = true_regnum (in);
4760 else if (GET_CODE (in) == SUBREG)
4761 regno = true_regnum (in);
4765 /* If we have something like (mem (mem (...)), we can safely assume the
4766 inner MEM will end up in a general register after reloading, so there's
4767 no need for a secondary reload. */
4768 if (GET_CODE (in) == MEM
4769 && GET_CODE (XEXP (in, 0)) == MEM)
4772 /* Handle out of range displacement for integer mode loads/stores of
4774 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
4775 && GET_MODE_CLASS (mode) == MODE_INT
4776 && FP_REG_CLASS_P (class))
4777 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
4778 return GENERAL_REGS;
4780 /* A SAR<->FP register copy requires a secondary register (GPR) as
4781 well as secondary memory. */
4782 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4783 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
4784 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
4785 return GENERAL_REGS;
4787 if (GET_CODE (in) == HIGH)
4790 /* Profiling has showed GCC spends about 2.6% of its compilation
4791 time in symbolic_operand from calls inside secondary_reload_class.
4793 We use an inline copy and only compute its return value once to avoid
4795 switch (GET_CODE (in))
4805 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
4806 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
4807 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
4817 && read_only_operand (in, VOIDmode))
4820 if (class != R1_REGS && is_symbolic)
4827 function_arg_padding (mode, type)
4828 enum machine_mode mode;
4833 if (mode == BLKmode)
4835 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4836 size = int_size_in_bytes (type) * BITS_PER_UNIT;
4838 return upward; /* Don't know if this is right, but */
4839 /* same as old definition. */
4842 size = GET_MODE_BITSIZE (mode);
4843 if (size < PARM_BOUNDARY)
4845 else if (size % PARM_BOUNDARY)
4852 /* Do what is necessary for `va_start'. We look at the current function
4853 to determine if stdargs or varargs is used and fill in an initial
4854 va_list. A pointer to this constructor is returned. */
4857 hppa_builtin_saveregs ()
4860 tree fntype = TREE_TYPE (current_function_decl);
4861 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
4862 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4863 != void_type_node)))
4864 ? UNITS_PER_WORD : 0);
4867 offset = plus_constant (current_function_arg_offset_rtx, argadj);
4869 offset = current_function_arg_offset_rtx;
4875 /* Adjust for varargs/stdarg differences. */
4877 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
4879 offset = current_function_arg_offset_rtx;
4881 /* We need to save %r26 .. %r19 inclusive starting at offset -64
4882 from the incoming arg pointer and growing to larger addresses. */
4883 for (i = 26, off = -64; i >= 19; i--, off += 8)
4884 emit_move_insn (gen_rtx_MEM (word_mode,
4885 plus_constant (arg_pointer_rtx, off)),
4886 gen_rtx_REG (word_mode, i));
4888 /* The incoming args pointer points just beyond the flushback area;
4889 normally this is not a serious concern. However, when we are doing
4890 varargs/stdargs we want to make the arg pointer point to the start
4891 of the incoming argument area. */
4892 emit_move_insn (virtual_incoming_args_rtx,
4893 plus_constant (arg_pointer_rtx, -64));
4895 /* Now return a pointer to the first anonymous argument. */
4896 return copy_to_reg (expand_binop (Pmode, add_optab,
4897 virtual_incoming_args_rtx,
4898 offset, 0, 0, OPTAB_LIB_WIDEN));
4901 /* Store general registers on the stack. */
4902 dest = gen_rtx_MEM (BLKmode,
4903 plus_constant (current_function_internal_arg_pointer,
4905 set_mem_alias_set (dest, get_varargs_alias_set ());
4906 set_mem_align (dest, BITS_PER_WORD);
4907 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
4909 /* move_block_from_reg will emit code to store the argument registers
4910 individually as scalar stores.
4912 However, other insns may later load from the same addresses for
4913 a structure load (passing a struct to a varargs routine).
4915 The alias code assumes that such aliasing can never happen, so we
4916 have to keep memory referencing insns from moving up beyond the
4917 last argument register store. So we emit a blockage insn here. */
4918 emit_insn (gen_blockage ());
4920 if (current_function_check_memory_usage)
4921 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4923 GEN_INT (4 * UNITS_PER_WORD), TYPE_MODE (sizetype),
4924 GEN_INT (MEMORY_USE_RW),
4925 TYPE_MODE (integer_type_node));
4927 return copy_to_reg (expand_binop (Pmode, add_optab,
4928 current_function_internal_arg_pointer,
4929 offset, 0, 0, OPTAB_LIB_WIDEN));
4933 hppa_va_start (stdarg_p, valist, nextarg)
4934 int stdarg_p ATTRIBUTE_UNUSED;
4938 nextarg = expand_builtin_saveregs ();
4939 std_expand_builtin_va_start (1, valist, nextarg);
4943 hppa_va_arg (valist, type)
4946 HOST_WIDE_INT align, size, ofs;
4951 /* Every argument in PA64 is passed by value (including large structs).
4952 Arguments with size greater than 8 must be aligned 0 MOD 16. */
4954 size = int_size_in_bytes (type);
4955 if (size > UNITS_PER_WORD)
4957 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4958 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4959 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4960 build_int_2 (-2 * UNITS_PER_WORD, -1));
4961 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4962 TREE_SIDE_EFFECTS (t) = 1;
4963 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4965 return std_expand_builtin_va_arg (valist, type);
4968 /* Compute the rounded size of the type. */
4969 align = PARM_BOUNDARY / BITS_PER_UNIT;
4970 size = int_size_in_bytes (type);
4972 ptr = build_pointer_type (type);
4974 /* "Large" types are passed by reference. */
4977 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
4978 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4979 TREE_SIDE_EFFECTS (t) = 1;
4981 pptr = build_pointer_type (ptr);
4982 t = build1 (NOP_EXPR, pptr, t);
4983 TREE_SIDE_EFFECTS (t) = 1;
4985 t = build1 (INDIRECT_REF, ptr, t);
4986 TREE_SIDE_EFFECTS (t) = 1;
4990 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4991 build_int_2 (-size, -1));
4993 /* Copied from va-pa.h, but we probably don't need to align
4994 to word size, since we generate and preserve that invariant. */
4995 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
4996 build_int_2 ((size > 4 ? -8 : -4), -1));
4998 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4999 TREE_SIDE_EFFECTS (t) = 1;
5001 ofs = (8 - size) % 4;
5004 t = build (PLUS_EXPR, TREE_TYPE (valist), t, build_int_2 (ofs, 0));
5005 TREE_SIDE_EFFECTS (t) = 1;
5008 t = build1 (NOP_EXPR, ptr, t);
5009 TREE_SIDE_EFFECTS (t) = 1;
5013 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
5018 /* This routine handles all the normal conditional branch sequences we
5019 might need to generate. It handles compare immediate vs compare
5020 register, nullification of delay slots, varying length branches,
5021 negated branches, and all combinations of the above. It returns the
5022 output appropriate to emit the branch corresponding to all given
5026 output_cbranch (operands, nullify, length, negated, insn)
5028 int nullify, length, negated;
5031 static char buf[100];
5034 /* A conditional branch to the following instruction (eg the delay slot) is
5035 asking for a disaster. This can happen when not optimizing.
5037 In such cases it is safe to emit nothing. */
5039 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5042 /* If this is a long branch with its delay slot unfilled, set `nullify'
5043 as it can nullify the delay slot and save a nop. */
5044 if (length == 8 && dbr_sequence_length () == 0)
5047 /* If this is a short forward conditional branch which did not get
5048 its delay slot filled, the delay slot can still be nullified. */
5049 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5050 nullify = forward_branch_p (insn);
5052 /* A forward branch over a single nullified insn can be done with a
5053 comclr instruction. This avoids a single cycle penalty due to
5054 mis-predicted branch if we fall through (branch not taken). */
5056 && next_real_insn (insn) != 0
5057 && get_attr_length (next_real_insn (insn)) == 4
5058 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5064 /* All short conditional branches except backwards with an unfilled
5068 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5070 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5071 if (GET_MODE (operands[1]) == DImode)
5074 strcat (buf, "%B3");
5076 strcat (buf, "%S3");
5078 strcat (buf, " %2,%r1,%%r0");
5080 strcat (buf, ",n %2,%r1,%0");
5082 strcat (buf, " %2,%r1,%0");
5085 /* All long conditionals. Note an short backward branch with an
5086 unfilled delay slot is treated just like a long backward branch
5087 with an unfilled delay slot. */
5089 /* Handle weird backwards branch with a filled delay slot
5090 with is nullified. */
5091 if (dbr_sequence_length () != 0
5092 && ! forward_branch_p (insn)
5095 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5096 if (GET_MODE (operands[1]) == DImode)
5099 strcat (buf, "%S3");
5101 strcat (buf, "%B3");
5102 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5104 /* Handle short backwards branch with an unfilled delay slot.
5105 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5106 taken and untaken branches. */
5107 else if (dbr_sequence_length () == 0
5108 && ! forward_branch_p (insn)
5109 && INSN_ADDRESSES_SET_P ()
5110 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5111 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5113 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5114 if (GET_MODE (operands[1]) == DImode)
5117 strcat (buf, "%B3 %2,%r1,%0%#");
5119 strcat (buf, "%S3 %2,%r1,%0%#");
5123 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5124 if (GET_MODE (operands[1]) == DImode)
5127 strcat (buf, "%S3");
5129 strcat (buf, "%B3");
5131 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5133 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5138 /* Very long branch. Right now we only handle these when not
5139 optimizing. See "jump" pattern in pa.md for details. */
5143 /* Create a reversed conditional branch which branches around
5144 the following insns. */
5146 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5148 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5149 if (GET_MODE (operands[1]) == DImode)
5153 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5156 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5158 output_asm_insn (buf, operands);
5160 /* Output an insn to save %r1. */
5161 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5163 /* Now output a very long branch to the original target. */
5164 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5166 /* Now restore the value of %r1 in the delay slot. We're not
5167 optimizing so we know nothing else can be in the delay slot. */
5168 return "ldw -16(%%r30),%%r1";
5171 /* Very long branch when generating PIC code. Right now we only
5172 handle these when not optimizing. See "jump" pattern in pa.md
5177 /* Create a reversed conditional branch which branches around
5178 the following insns. */
5180 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5182 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5183 if (GET_MODE (operands[1]) == DImode)
5186 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5188 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5190 output_asm_insn (buf, operands);
5192 /* Output an insn to save %r1. */
5193 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5195 /* Now output a very long PIC branch to the original target. */
5199 xoperands[0] = operands[0];
5200 xoperands[1] = operands[1];
5201 xoperands[2] = operands[2];
5202 xoperands[3] = operands[3];
5203 xoperands[4] = gen_label_rtx ();
5205 output_asm_insn ("{bl|b,l} .+8,%%r1\n\taddil L'%l0-%l4,%%r1",
5207 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5208 CODE_LABEL_NUMBER (xoperands[4]));
5209 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
5213 /* Now restore the value of %r1 in the delay slot. We're not
5214 optimizing so we know nothing else can be in the delay slot. */
5215 return "ldw -16(%%r30),%%r1";
5223 /* This routine handles all the branch-on-bit conditional branch sequences we
5224 might need to generate. It handles nullification of delay slots,
5225 varying length branches, negated branches and all combinations of the
5226 above. it returns the appropriate output template to emit the branch. */
5229 output_bb (operands, nullify, length, negated, insn, which)
5230 rtx *operands ATTRIBUTE_UNUSED;
5231 int nullify, length, negated;
5235 static char buf[100];
5238 /* A conditional branch to the following instruction (eg the delay slot) is
5239 asking for a disaster. I do not think this can happen as this pattern
5240 is only used when optimizing; jump optimization should eliminate the
5241 jump. But be prepared just in case. */
5243 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5246 /* If this is a long branch with its delay slot unfilled, set `nullify'
5247 as it can nullify the delay slot and save a nop. */
5248 if (length == 8 && dbr_sequence_length () == 0)
5251 /* If this is a short forward conditional branch which did not get
5252 its delay slot filled, the delay slot can still be nullified. */
5253 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5254 nullify = forward_branch_p (insn);
5256 /* A forward branch over a single nullified insn can be done with a
5257 extrs instruction. This avoids a single cycle penalty due to
5258 mis-predicted branch if we fall through (branch not taken). */
5261 && next_real_insn (insn) != 0
5262 && get_attr_length (next_real_insn (insn)) == 4
5263 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5270 /* All short conditional branches except backwards with an unfilled
5274 strcpy (buf, "{extrs,|extrw,s,}");
5276 strcpy (buf, "bb,");
5277 if (useskip && GET_MODE (operands[0]) == DImode)
5278 strcpy (buf, "extrd,s,*");
5279 else if (GET_MODE (operands[0]) == DImode)
5280 strcpy (buf, "bb,*");
5281 if ((which == 0 && negated)
5282 || (which == 1 && ! negated))
5287 strcat (buf, " %0,%1,1,%%r0");
5288 else if (nullify && negated)
5289 strcat (buf, ",n %0,%1,%3");
5290 else if (nullify && ! negated)
5291 strcat (buf, ",n %0,%1,%2");
5292 else if (! nullify && negated)
5293 strcat (buf, "%0,%1,%3");
5294 else if (! nullify && ! negated)
5295 strcat (buf, " %0,%1,%2");
5298 /* All long conditionals. Note an short backward branch with an
5299 unfilled delay slot is treated just like a long backward branch
5300 with an unfilled delay slot. */
5302 /* Handle weird backwards branch with a filled delay slot
5303 with is nullified. */
5304 if (dbr_sequence_length () != 0
5305 && ! forward_branch_p (insn)
5308 strcpy (buf, "bb,");
5309 if (GET_MODE (operands[0]) == DImode)
5311 if ((which == 0 && negated)
5312 || (which == 1 && ! negated))
5317 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5319 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5321 /* Handle short backwards branch with an unfilled delay slot.
5322 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5323 taken and untaken branches. */
5324 else if (dbr_sequence_length () == 0
5325 && ! forward_branch_p (insn)
5326 && INSN_ADDRESSES_SET_P ()
5327 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5328 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5330 strcpy (buf, "bb,");
5331 if (GET_MODE (operands[0]) == DImode)
5333 if ((which == 0 && negated)
5334 || (which == 1 && ! negated))
5339 strcat (buf, " %0,%1,%3%#");
5341 strcat (buf, " %0,%1,%2%#");
5345 strcpy (buf, "{extrs,|extrw,s,}");
5346 if (GET_MODE (operands[0]) == DImode)
5347 strcpy (buf, "extrd,s,*");
5348 if ((which == 0 && negated)
5349 || (which == 1 && ! negated))
5353 if (nullify && negated)
5354 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5355 else if (nullify && ! negated)
5356 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5358 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5360 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5370 /* This routine handles all the branch-on-variable-bit conditional branch
5371 sequences we might need to generate. It handles nullification of delay
5372 slots, varying length branches, negated branches and all combinations
5373 of the above. it returns the appropriate output template to emit the
5377 output_bvb (operands, nullify, length, negated, insn, which)
5378 rtx *operands ATTRIBUTE_UNUSED;
5379 int nullify, length, negated;
5383 static char buf[100];
5386 /* A conditional branch to the following instruction (eg the delay slot) is
5387 asking for a disaster. I do not think this can happen as this pattern
5388 is only used when optimizing; jump optimization should eliminate the
5389 jump. But be prepared just in case. */
5391 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5394 /* If this is a long branch with its delay slot unfilled, set `nullify'
5395 as it can nullify the delay slot and save a nop. */
5396 if (length == 8 && dbr_sequence_length () == 0)
5399 /* If this is a short forward conditional branch which did not get
5400 its delay slot filled, the delay slot can still be nullified. */
5401 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5402 nullify = forward_branch_p (insn);
5404 /* A forward branch over a single nullified insn can be done with a
5405 extrs instruction. This avoids a single cycle penalty due to
5406 mis-predicted branch if we fall through (branch not taken). */
5409 && next_real_insn (insn) != 0
5410 && get_attr_length (next_real_insn (insn)) == 4
5411 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5418 /* All short conditional branches except backwards with an unfilled
5422 strcpy (buf, "{vextrs,|extrw,s,}");
5424 strcpy (buf, "{bvb,|bb,}");
5425 if (useskip && GET_MODE (operands[0]) == DImode)
5426 strcpy (buf, "extrd,s,*}");
5427 else if (GET_MODE (operands[0]) == DImode)
5428 strcpy (buf, "bb,*");
5429 if ((which == 0 && negated)
5430 || (which == 1 && ! negated))
5435 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5436 else if (nullify && negated)
5437 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5438 else if (nullify && ! negated)
5439 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5440 else if (! nullify && negated)
5441 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5442 else if (! nullify && ! negated)
5443 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5446 /* All long conditionals. Note an short backward branch with an
5447 unfilled delay slot is treated just like a long backward branch
5448 with an unfilled delay slot. */
5450 /* Handle weird backwards branch with a filled delay slot
5451 with is nullified. */
5452 if (dbr_sequence_length () != 0
5453 && ! forward_branch_p (insn)
5456 strcpy (buf, "{bvb,|bb,}");
5457 if (GET_MODE (operands[0]) == DImode)
5459 if ((which == 0 && negated)
5460 || (which == 1 && ! negated))
5465 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5467 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5469 /* Handle short backwards branch with an unfilled delay slot.
5470 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5471 taken and untaken branches. */
5472 else if (dbr_sequence_length () == 0
5473 && ! forward_branch_p (insn)
5474 && INSN_ADDRESSES_SET_P ()
5475 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5476 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5478 strcpy (buf, "{bvb,|bb,}");
5479 if (GET_MODE (operands[0]) == DImode)
5481 if ((which == 0 && negated)
5482 || (which == 1 && ! negated))
5487 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5489 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5493 strcpy (buf, "{vextrs,|extrw,s,}");
5494 if (GET_MODE (operands[0]) == DImode)
5495 strcpy (buf, "extrd,s,*");
5496 if ((which == 0 && negated)
5497 || (which == 1 && ! negated))
5501 if (nullify && negated)
5502 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5503 else if (nullify && ! negated)
5504 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5506 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5508 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5518 /* Return the output template for emitting a dbra type insn.
5520 Note it may perform some output operations on its own before
5521 returning the final output string. */
5523 output_dbra (operands, insn, which_alternative)
5526 int which_alternative;
5529 /* A conditional branch to the following instruction (eg the delay slot) is
5530 asking for a disaster. Be prepared! */
5532 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5534 if (which_alternative == 0)
5535 return "ldo %1(%0),%0";
5536 else if (which_alternative == 1)
5538 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5539 output_asm_insn ("ldw -16(%%r30),%4", operands);
5540 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5541 return "{fldws|fldw} -16(%%r30),%0";
5545 output_asm_insn ("ldw %0,%4", operands);
5546 return "ldo %1(%4),%4\n\tstw %4,%0";
5550 if (which_alternative == 0)
5552 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5553 int length = get_attr_length (insn);
5555 /* If this is a long branch with its delay slot unfilled, set `nullify'
5556 as it can nullify the delay slot and save a nop. */
5557 if (length == 8 && dbr_sequence_length () == 0)
5560 /* If this is a short forward conditional branch which did not get
5561 its delay slot filled, the delay slot can still be nullified. */
5562 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5563 nullify = forward_branch_p (insn);
5565 /* Handle short versions first. */
5566 if (length == 4 && nullify)
5567 return "addib,%C2,n %1,%0,%3";
5568 else if (length == 4 && ! nullify)
5569 return "addib,%C2 %1,%0,%3";
5570 else if (length == 8)
5572 /* Handle weird backwards branch with a fulled delay slot
5573 which is nullified. */
5574 if (dbr_sequence_length () != 0
5575 && ! forward_branch_p (insn)
5577 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5578 /* Handle short backwards branch with an unfilled delay slot.
5579 Using a addb;nop rather than addi;bl saves 1 cycle for both
5580 taken and untaken branches. */
5581 else if (dbr_sequence_length () == 0
5582 && ! forward_branch_p (insn)
5583 && INSN_ADDRESSES_SET_P ()
5584 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5585 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5586 return "addib,%C2 %1,%0,%3%#";
5588 /* Handle normal cases. */
5590 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5592 return "addi,%N2 %1,%0,%0\n\tb %3";
5597 /* Deal with gross reload from FP register case. */
5598 else if (which_alternative == 1)
5600 /* Move loop counter from FP register to MEM then into a GR,
5601 increment the GR, store the GR into MEM, and finally reload
5602 the FP register from MEM from within the branch's delay slot. */
5603 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5605 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5606 if (get_attr_length (insn) == 24)
5607 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5609 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5611 /* Deal with gross reload from memory case. */
5614 /* Reload loop counter from memory, the store back to memory
5615 happens in the branch's delay slot. */
5616 output_asm_insn ("ldw %0,%4", operands);
5617 if (get_attr_length (insn) == 12)
5618 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5620 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5624 /* Return the output template for emitting a dbra type insn.
5626 Note it may perform some output operations on its own before
5627 returning the final output string. */
5629 output_movb (operands, insn, which_alternative, reverse_comparison)
5632 int which_alternative;
5633 int reverse_comparison;
5636 /* A conditional branch to the following instruction (eg the delay slot) is
5637 asking for a disaster. Be prepared! */
5639 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5641 if (which_alternative == 0)
5642 return "copy %1,%0";
5643 else if (which_alternative == 1)
5645 output_asm_insn ("stw %1,-16(%%r30)", operands);
5646 return "{fldws|fldw} -16(%%r30),%0";
5648 else if (which_alternative == 2)
5654 /* Support the second variant. */
5655 if (reverse_comparison)
5656 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5658 if (which_alternative == 0)
5660 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5661 int length = get_attr_length (insn);
5663 /* If this is a long branch with its delay slot unfilled, set `nullify'
5664 as it can nullify the delay slot and save a nop. */
5665 if (length == 8 && dbr_sequence_length () == 0)
5668 /* If this is a short forward conditional branch which did not get
5669 its delay slot filled, the delay slot can still be nullified. */
5670 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5671 nullify = forward_branch_p (insn);
5673 /* Handle short versions first. */
5674 if (length == 4 && nullify)
5675 return "movb,%C2,n %1,%0,%3";
5676 else if (length == 4 && ! nullify)
5677 return "movb,%C2 %1,%0,%3";
5678 else if (length == 8)
5680 /* Handle weird backwards branch with a filled delay slot
5681 which is nullified. */
5682 if (dbr_sequence_length () != 0
5683 && ! forward_branch_p (insn)
5685 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5687 /* Handle short backwards branch with an unfilled delay slot.
5688 Using a movb;nop rather than or;bl saves 1 cycle for both
5689 taken and untaken branches. */
5690 else if (dbr_sequence_length () == 0
5691 && ! forward_branch_p (insn)
5692 && INSN_ADDRESSES_SET_P ()
5693 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5694 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5695 return "movb,%C2 %1,%0,%3%#";
5696 /* Handle normal cases. */
5698 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5700 return "or,%N2 %1,%%r0,%0\n\tb %3";
5705 /* Deal with gross reload from FP register case. */
5706 else if (which_alternative == 1)
5708 /* Move loop counter from FP register to MEM then into a GR,
5709 increment the GR, store the GR into MEM, and finally reload
5710 the FP register from MEM from within the branch's delay slot. */
5711 output_asm_insn ("stw %1,-16(%%r30)", operands);
5712 if (get_attr_length (insn) == 12)
5713 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
5715 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5717 /* Deal with gross reload from memory case. */
5718 else if (which_alternative == 2)
5720 /* Reload loop counter from memory, the store back to memory
5721 happens in the branch's delay slot. */
5722 if (get_attr_length (insn) == 8)
5723 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
5725 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5727 /* Handle SAR as a destination. */
5730 if (get_attr_length (insn) == 8)
5731 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
5733 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5738 /* INSN is a millicode call. It may have an unconditional jump in its delay
5741 CALL_DEST is the routine we are calling. */
5744 output_millicode_call (insn, call_dest)
5752 xoperands[3] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
5754 /* Handle common case -- empty delay slot or no jump in the delay slot,
5755 and we're sure that the branch will reach the beginning of the $CODE$
5757 if ((dbr_sequence_length () == 0
5758 && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
5759 || (dbr_sequence_length () != 0
5760 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5761 && get_attr_length (insn) == 4))
5763 xoperands[0] = call_dest;
5764 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
5768 /* This call may not reach the beginning of the $CODE$ subspace. */
5769 if (get_attr_length (insn) > 4)
5771 int delay_insn_deleted = 0;
5773 /* We need to emit an inline long-call branch. */
5774 if (dbr_sequence_length () != 0
5775 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5777 /* A non-jump insn in the delay slot. By definition we can
5778 emit this insn before the call. */
5779 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5781 /* Now delete the delay insn. */
5782 PUT_CODE (NEXT_INSN (insn), NOTE);
5783 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5784 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5785 delay_insn_deleted = 1;
5788 /* PIC long millicode call sequence. */
5791 xoperands[0] = call_dest;
5792 xoperands[1] = gen_label_rtx ();
5793 /* Get our address + 8 into %r1. */
5794 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5796 /* Add %r1 to the offset of our target from the next insn. */
5797 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
5798 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5799 CODE_LABEL_NUMBER (xoperands[1]));
5800 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
5802 /* Get the return address into %r31. */
5803 output_asm_insn ("blr 0,%3", xoperands);
5805 /* Branch to our target which is in %r1. */
5806 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
5808 /* Empty delay slot. Note this insn gets fetched twice and
5809 executed once. To be safe we use a nop. */
5810 output_asm_insn ("nop", xoperands);
5812 /* Pure portable runtime doesn't allow be/ble; we also don't have
5813 PIC support in the assembler/linker, so this sequence is needed. */
5814 else if (TARGET_PORTABLE_RUNTIME)
5816 xoperands[0] = call_dest;
5817 /* Get the address of our target into %r29. */
5818 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
5819 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
5821 /* Get our return address into %r31. */
5822 output_asm_insn ("blr %%r0,%3", xoperands);
5824 /* Jump to our target address in %r29. */
5825 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
5827 /* Empty delay slot. Note this insn gets fetched twice and
5828 executed once. To be safe we use a nop. */
5829 output_asm_insn ("nop", xoperands);
5831 /* If we're allowed to use be/ble instructions, then this is the
5832 best sequence to use for a long millicode call. */
5835 xoperands[0] = call_dest;
5836 output_asm_insn ("ldil L%%%0,%3", xoperands);
5837 output_asm_insn ("{ble|be,l} R%%%0(%%sr4,%3)", xoperands);
5838 output_asm_insn ("nop", xoperands);
5841 /* If we had a jump in the call's delay slot, output it now. */
5842 if (dbr_sequence_length () != 0
5843 && !delay_insn_deleted)
5845 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5846 output_asm_insn ("b,n %0", xoperands);
5848 /* Now delete the delay insn. */
5849 PUT_CODE (NEXT_INSN (insn), NOTE);
5850 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5851 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5856 /* This call has an unconditional jump in its delay slot and the
5857 call is known to reach its target or the beginning of the current
5860 /* Use the containing sequence insn's address. */
5861 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5863 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
5864 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
5866 /* If the branch was too far away, emit a normal call followed
5867 by a nop, followed by the unconditional branch.
5869 If the branch is close, then adjust %r2 from within the
5870 call's delay slot. */
5872 xoperands[0] = call_dest;
5873 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5874 if (! VAL_14_BITS_P (distance))
5875 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
5878 xoperands[2] = gen_label_rtx ();
5879 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
5881 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5882 CODE_LABEL_NUMBER (xoperands[2]));
5885 /* Delete the jump. */
5886 PUT_CODE (NEXT_INSN (insn), NOTE);
5887 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5888 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5892 extern struct obstack permanent_obstack;
5894 /* INSN is either a function call. It may have an unconditional jump
5897 CALL_DEST is the routine we are calling. */
5900 output_call (insn, call_dest, sibcall)
5909 /* Handle common case -- empty delay slot or no jump in the delay slot,
5910 and we're sure that the branch will reach the beginning of the $CODE$
5912 if ((dbr_sequence_length () == 0
5913 && get_attr_length (insn) == 8)
5914 || (dbr_sequence_length () != 0
5915 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5916 && get_attr_length (insn) == 4))
5918 xoperands[0] = call_dest;
5919 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
5920 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
5924 /* This call may not reach the beginning of the $CODE$ subspace. */
5925 if (get_attr_length (insn) > 8)
5927 int delay_insn_deleted = 0;
5931 /* We need to emit an inline long-call branch. Furthermore,
5932 because we're changing a named function call into an indirect
5933 function call well after the parameters have been set up, we
5934 need to make sure any FP args appear in both the integer
5935 and FP registers. Also, we need move any delay slot insn
5936 out of the delay slot. And finally, we can't rely on the linker
5937 being able to fix the call to $$dyncall! -- Yuk!. */
5938 if (dbr_sequence_length () != 0
5939 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5941 /* A non-jump insn in the delay slot. By definition we can
5942 emit this insn before the call (and in fact before argument
5944 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5946 /* Now delete the delay insn. */
5947 PUT_CODE (NEXT_INSN (insn), NOTE);
5948 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5949 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5950 delay_insn_deleted = 1;
5953 /* Now copy any FP arguments into integer registers. */
5954 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
5956 int arg_mode, regno;
5957 rtx use = XEXP (link, 0);
5958 if (! (GET_CODE (use) == USE
5959 && GET_CODE (XEXP (use, 0)) == REG
5960 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5963 arg_mode = GET_MODE (XEXP (use, 0));
5964 regno = REGNO (XEXP (use, 0));
5965 /* Is it a floating point register? */
5966 if (regno >= 32 && regno <= 39)
5968 /* Copy from the FP register into an integer register
5970 if (arg_mode == SFmode)
5972 xoperands[0] = XEXP (use, 0);
5973 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
5974 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
5976 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5980 xoperands[0] = XEXP (use, 0);
5981 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
5982 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
5984 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
5985 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5990 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5991 we don't have any direct calls in that case. */
5994 const char *name = XSTR (call_dest, 0);
5996 /* See if we have already put this function on the list
5997 of deferred plabels. This list is generally small,
5998 so a liner search is not too ugly. If it proves too
5999 slow replace it with something faster. */
6000 for (i = 0; i < n_deferred_plabels; i++)
6001 if (strcmp (name, deferred_plabels[i].name) == 0)
6004 /* If the deferred plabel list is empty, or this entry was
6005 not found on the list, create a new entry on the list. */
6006 if (deferred_plabels == NULL || i == n_deferred_plabels)
6008 const char *real_name;
6010 if (deferred_plabels == 0)
6011 deferred_plabels = (struct deferred_plabel *)
6012 xmalloc (1 * sizeof (struct deferred_plabel));
6014 deferred_plabels = (struct deferred_plabel *)
6015 xrealloc (deferred_plabels,
6016 ((n_deferred_plabels + 1)
6017 * sizeof (struct deferred_plabel)));
6019 i = n_deferred_plabels++;
6020 deferred_plabels[i].internal_label = gen_label_rtx ();
6021 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
6023 strcpy (deferred_plabels[i].name, name);
6025 /* Gross. We have just implicitly taken the address of this
6026 function, mark it as such. */
6027 STRIP_NAME_ENCODING (real_name, name);
6028 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
6031 /* We have to load the address of the function using a procedure
6032 label (plabel). Inline plabels can lose for PIC and other
6033 cases, so avoid them by creating a 32bit plabel in the data
6037 xoperands[0] = deferred_plabels[i].internal_label;
6038 xoperands[1] = gen_label_rtx ();
6040 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
6041 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
6042 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
6044 /* Get our address + 8 into %r1. */
6045 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6047 /* Add %r1 to the offset of dyncall from the next insn. */
6048 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
6049 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6050 CODE_LABEL_NUMBER (xoperands[1]));
6051 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
6053 /* Get the return address into %r31. */
6054 output_asm_insn ("blr %%r0,%%r31", xoperands);
6056 /* Branch to our target which is in %r1. */
6057 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6061 /* This call never returns, so we do not need to fix the
6063 output_asm_insn ("nop", xoperands);
6067 /* Copy the return address into %r2 also. */
6068 output_asm_insn ("copy %%r31,%%r2", xoperands);
6073 xoperands[0] = deferred_plabels[i].internal_label;
6075 /* Get the address of our target into %r22. */
6076 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
6077 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
6079 /* Get the high part of the address of $dyncall into %r2, then
6080 add in the low part in the branch instruction. */
6081 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
6082 output_asm_insn ("{ble|be,l} R%%$$dyncall(%%sr4,%%r2)",
6087 /* This call never returns, so we do not need to fix the
6089 output_asm_insn ("nop", xoperands);
6093 /* Copy the return address into %r2 also. */
6094 output_asm_insn ("copy %%r31,%%r2", xoperands);
6099 /* If we had a jump in the call's delay slot, output it now. */
6100 if (dbr_sequence_length () != 0
6101 && !delay_insn_deleted)
6103 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6104 output_asm_insn ("b,n %0", xoperands);
6106 /* Now delete the delay insn. */
6107 PUT_CODE (NEXT_INSN (insn), NOTE);
6108 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6109 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6114 /* This call has an unconditional jump in its delay slot and the
6115 call is known to reach its target or the beginning of the current
6118 /* Use the containing sequence insn's address. */
6119 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6121 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6122 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6124 /* If the branch was too far away, emit a normal call followed
6125 by a nop, followed by the unconditional branch.
6127 If the branch is close, then adjust %r2 from within the
6128 call's delay slot. */
6130 xoperands[0] = call_dest;
6131 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6132 if (! VAL_14_BITS_P (distance))
6133 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
6136 xoperands[3] = gen_label_rtx ();
6137 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6139 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6140 CODE_LABEL_NUMBER (xoperands[3]));
6143 /* Delete the jump. */
6144 PUT_CODE (NEXT_INSN (insn), NOTE);
6145 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6146 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6150 /* In HPUX 8.0's shared library scheme, special relocations are needed
6151 for function labels if they might be passed to a function
6152 in a shared library (because shared libraries don't live in code
6153 space), and special magic is needed to construct their address. */
6156 hppa_encode_label (sym)
6159 const char *str = XSTR (sym, 0);
6160 int len = strlen (str) + 1;
6163 p = newstr = alloca (len + 1);
6172 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6176 function_label_operand (op, mode)
6178 enum machine_mode mode ATTRIBUTE_UNUSED;
6180 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6183 /* Returns 1 if OP is a function label involved in a simple addition
6184 with a constant. Used to keep certain patterns from matching
6185 during instruction combination. */
6187 is_function_label_plus_const (op)
6190 /* Strip off any CONST. */
6191 if (GET_CODE (op) == CONST)
6194 return (GET_CODE (op) == PLUS
6195 && function_label_operand (XEXP (op, 0), Pmode)
6196 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6199 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6200 use in fmpyadd instructions. */
6202 fmpyaddoperands (operands)
6205 enum machine_mode mode = GET_MODE (operands[0]);
6207 /* Must be a floating point mode. */
6208 if (mode != SFmode && mode != DFmode)
6211 /* All modes must be the same. */
6212 if (! (mode == GET_MODE (operands[1])
6213 && mode == GET_MODE (operands[2])
6214 && mode == GET_MODE (operands[3])
6215 && mode == GET_MODE (operands[4])
6216 && mode == GET_MODE (operands[5])))
6219 /* All operands must be registers. */
6220 if (! (GET_CODE (operands[1]) == REG
6221 && GET_CODE (operands[2]) == REG
6222 && GET_CODE (operands[3]) == REG
6223 && GET_CODE (operands[4]) == REG
6224 && GET_CODE (operands[5]) == REG))
6227 /* Only 2 real operands to the addition. One of the input operands must
6228 be the same as the output operand. */
6229 if (! rtx_equal_p (operands[3], operands[4])
6230 && ! rtx_equal_p (operands[3], operands[5]))
6233 /* Inout operand of add can not conflict with any operands from multiply. */
6234 if (rtx_equal_p (operands[3], operands[0])
6235 || rtx_equal_p (operands[3], operands[1])
6236 || rtx_equal_p (operands[3], operands[2]))
6239 /* multiply can not feed into addition operands. */
6240 if (rtx_equal_p (operands[4], operands[0])
6241 || rtx_equal_p (operands[5], operands[0]))
6244 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6246 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6247 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6248 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6249 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6250 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6251 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6254 /* Passed. Operands are suitable for fmpyadd. */
6258 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6259 use in fmpysub instructions. */
6261 fmpysuboperands (operands)
6264 enum machine_mode mode = GET_MODE (operands[0]);
6266 /* Must be a floating point mode. */
6267 if (mode != SFmode && mode != DFmode)
6270 /* All modes must be the same. */
6271 if (! (mode == GET_MODE (operands[1])
6272 && mode == GET_MODE (operands[2])
6273 && mode == GET_MODE (operands[3])
6274 && mode == GET_MODE (operands[4])
6275 && mode == GET_MODE (operands[5])))
6278 /* All operands must be registers. */
6279 if (! (GET_CODE (operands[1]) == REG
6280 && GET_CODE (operands[2]) == REG
6281 && GET_CODE (operands[3]) == REG
6282 && GET_CODE (operands[4]) == REG
6283 && GET_CODE (operands[5]) == REG))
6286 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6287 operation, so operands[4] must be the same as operand[3]. */
6288 if (! rtx_equal_p (operands[3], operands[4]))
6291 /* multiply can not feed into subtraction. */
6292 if (rtx_equal_p (operands[5], operands[0]))
6295 /* Inout operand of sub can not conflict with any operands from multiply. */
6296 if (rtx_equal_p (operands[3], operands[0])
6297 || rtx_equal_p (operands[3], operands[1])
6298 || rtx_equal_p (operands[3], operands[2]))
6301 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6303 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6304 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6305 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6306 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6307 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6308 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6311 /* Passed. Operands are suitable for fmpysub. */
6316 plus_xor_ior_operator (op, mode)
6318 enum machine_mode mode ATTRIBUTE_UNUSED;
6320 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6321 || GET_CODE (op) == IOR);
6324 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6325 constants for shadd instructions. */
6327 shadd_constant_p (val)
6330 if (val == 2 || val == 4 || val == 8)
6336 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6337 the valid constant for shadd instructions. */
6339 shadd_operand (op, mode)
6341 enum machine_mode mode ATTRIBUTE_UNUSED;
6343 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6346 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6349 basereg_operand (op, mode)
6351 enum machine_mode mode;
6353 /* cse will create some unscaled indexed addresses, however; it
6354 generally isn't a win on the PA, so avoid creating unscaled
6355 indexed addresses until after cse is finished. */
6356 if (!cse_not_expected)
6359 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6360 we don't have to worry about the braindamaged implicit space
6361 register selection from the basereg. */
6362 if (TARGET_NO_SPACE_REGS)
6363 return (GET_CODE (op) == REG);
6365 /* While it's always safe to index off the frame pointer, it's not
6366 always profitable, particularly when the frame pointer is being
6368 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6371 return (GET_CODE (op) == REG
6373 && register_operand (op, mode));
6376 /* Return 1 if this operand is anything other than a hard register. */
6379 non_hard_reg_operand (op, mode)
6381 enum machine_mode mode ATTRIBUTE_UNUSED;
6383 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6386 /* Return 1 if INSN branches forward. Should be using insn_addresses
6387 to avoid walking through all the insns... */
6389 forward_branch_p (insn)
6392 rtx label = JUMP_LABEL (insn);
6399 insn = NEXT_INSN (insn);
6402 return (insn == label);
6405 /* Return 1 if OP is an equality comparison, else return 0. */
6407 eq_neq_comparison_operator (op, mode)
6409 enum machine_mode mode ATTRIBUTE_UNUSED;
6411 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6414 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6416 movb_comparison_operator (op, mode)
6418 enum machine_mode mode ATTRIBUTE_UNUSED;
6420 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6421 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6424 /* Return 1 if INSN is in the delay slot of a call instruction. */
6426 jump_in_call_delay (insn)
6430 if (GET_CODE (insn) != JUMP_INSN)
6433 if (PREV_INSN (insn)
6434 && PREV_INSN (PREV_INSN (insn))
6435 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6437 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6439 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6440 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6447 /* Output an unconditional move and branch insn. */
6450 output_parallel_movb (operands, length)
6454 /* These are the cases in which we win. */
6456 return "mov%I1b,tr %1,%0,%2";
6458 /* None of these cases wins, but they don't lose either. */
6459 if (dbr_sequence_length () == 0)
6461 /* Nothing in the delay slot, fake it by putting the combined
6462 insn (the copy or add) in the delay slot of a bl. */
6463 if (GET_CODE (operands[1]) == CONST_INT)
6464 return "b %2\n\tldi %1,%0";
6466 return "b %2\n\tcopy %1,%0";
6470 /* Something in the delay slot, but we've got a long branch. */
6471 if (GET_CODE (operands[1]) == CONST_INT)
6472 return "ldi %1,%0\n\tb %2";
6474 return "copy %1,%0\n\tb %2";
6478 /* Output an unconditional add and branch insn. */
6481 output_parallel_addb (operands, length)
6485 /* To make life easy we want operand0 to be the shared input/output
6486 operand and operand1 to be the readonly operand. */
6487 if (operands[0] == operands[1])
6488 operands[1] = operands[2];
6490 /* These are the cases in which we win. */
6492 return "add%I1b,tr %1,%0,%3";
6494 /* None of these cases win, but they don't lose either. */
6495 if (dbr_sequence_length () == 0)
6497 /* Nothing in the delay slot, fake it by putting the combined
6498 insn (the copy or add) in the delay slot of a bl. */
6499 return "b %3\n\tadd%I1 %1,%0,%0";
6503 /* Something in the delay slot, but we've got a long branch. */
6504 return "add%I1 %1,%0,%0\n\tb %3";
6508 /* Return nonzero if INSN (a jump insn) immediately follows a call to
6509 a named function. This is used to discourage creating parallel movb/addb
6510 insns since a jump which immediately follows a call can execute in the
6511 delay slot of the call.
6513 It is also used to avoid filling the delay slot of a jump which
6514 immediately follows a call since the jump can usually be eliminated
6515 completely by modifying RP in the delay slot of the call. */
6518 following_call (insn)
6521 /* We do not parallel movb,addb or place jumps into call delay slots when
6522 optimizing for the PA8000. */
6523 if (pa_cpu != PROCESSOR_8000)
6526 /* Find the previous real insn, skipping NOTEs. */
6527 insn = PREV_INSN (insn);
6528 while (insn && GET_CODE (insn) == NOTE)
6529 insn = PREV_INSN (insn);
6531 /* Check for CALL_INSNs and millicode calls. */
6533 && ((GET_CODE (insn) == CALL_INSN
6534 && get_attr_type (insn) != TYPE_DYNCALL)
6535 || (GET_CODE (insn) == INSN
6536 && GET_CODE (PATTERN (insn)) != SEQUENCE
6537 && GET_CODE (PATTERN (insn)) != USE
6538 && GET_CODE (PATTERN (insn)) != CLOBBER
6539 && get_attr_type (insn) == TYPE_MILLI)))
6545 /* We use this hook to perform a PA specific optimization which is difficult
6546 to do in earlier passes.
6548 We want the delay slots of branches within jump tables to be filled.
6549 None of the compiler passes at the moment even has the notion that a
6550 PA jump table doesn't contain addresses, but instead contains actual
6553 Because we actually jump into the table, the addresses of each entry
6554 must stay constant in relation to the beginning of the table (which
6555 itself must stay constant relative to the instruction to jump into
6556 it). I don't believe we can guarantee earlier passes of the compiler
6557 will adhere to those rules.
6559 So, late in the compilation process we find all the jump tables, and
6560 expand them into real code -- eg each entry in the jump table vector
6561 will get an appropriate label followed by a jump to the final target.
6563 Reorg and the final jump pass can then optimize these branches and
6564 fill their delay slots. We end up with smaller, more efficient code.
6566 The jump instructions within the table are special; we must be able
6567 to identify them during assembly output (if the jumps don't get filled
6568 we need to emit a nop rather than nullifying the delay slot)). We
6569 identify jumps in switch tables by marking the SET with DImode.
6571 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6572 insns. This serves two purposes, first it prevents jump.c from
6573 noticing that the last N entries in the table jump to the instruction
6574 immediately after the table and deleting the jumps. Second, those
6575 insns mark where we should emit .begin_brtab and .end_brtab directives
6576 when using GAS (allows for better link time optimizations). */
6584 remove_useless_addtr_insns (insns, 1);
6586 if (pa_cpu < PROCESSOR_8000)
6587 pa_combine_instructions (get_insns ());
6590 /* This is fairly cheap, so always run it if optimizing. */
6591 if (optimize > 0 && !TARGET_BIG_SWITCH)
6593 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6594 insns = get_insns ();
6595 for (insn = insns; insn; insn = NEXT_INSN (insn))
6597 rtx pattern, tmp, location;
6598 unsigned int length, i;
6600 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6601 if (GET_CODE (insn) != JUMP_INSN
6602 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6603 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6606 /* Emit marker for the beginning of the branch table. */
6607 emit_insn_before (gen_begin_brtab (), insn);
6609 pattern = PATTERN (insn);
6610 location = PREV_INSN (insn);
6611 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6613 for (i = 0; i < length; i++)
6615 /* Emit a label before each jump to keep jump.c from
6616 removing this code. */
6617 tmp = gen_label_rtx ();
6618 LABEL_NUSES (tmp) = 1;
6619 emit_label_after (tmp, location);
6620 location = NEXT_INSN (location);
6622 if (GET_CODE (pattern) == ADDR_VEC)
6624 /* Emit the jump itself. */
6625 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
6626 tmp = emit_jump_insn_after (tmp, location);
6627 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
6628 /* It is easy to rely on the branch table markers
6629 during assembly output to trigger the correct code
6630 for a switch table jump with an unfilled delay slot,
6632 However, that requires state and assumes that we look
6635 We can't make such assumptions when computing the length
6636 of instructions. Ugh. We could walk the insn chain to
6637 determine if this instruction is in a branch table, but
6638 that can get rather expensive, particularly during the
6639 branch shortening phase of the compiler.
6641 So instead we mark this jump as being special. This is
6642 far from ideal and knows that no code after this will
6643 muck around with the mode of the JUMP_INSN itself. */
6644 PUT_MODE (tmp, SImode);
6645 LABEL_NUSES (JUMP_LABEL (tmp))++;
6646 location = NEXT_INSN (location);
6650 /* Emit the jump itself. */
6651 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
6652 tmp = emit_jump_insn_after (tmp, location);
6653 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
6654 /* It is easy to rely on the branch table markers
6655 during assembly output to trigger the correct code
6656 for a switch table jump with an unfilled delay slot,
6658 However, that requires state and assumes that we look
6661 We can't make such assumptions when computing the length
6662 of instructions. Ugh. We could walk the insn chain to
6663 determine if this instruction is in a branch table, but
6664 that can get rather expensive, particularly during the
6665 branch shortening phase of the compiler.
6667 So instead we mark this jump as being special. This is
6668 far from ideal and knows that no code after this will
6669 muck around with the mode of the JUMP_INSN itself. */
6670 PUT_MODE (tmp, SImode);
6671 LABEL_NUSES (JUMP_LABEL (tmp))++;
6672 location = NEXT_INSN (location);
6675 /* Emit a BARRIER after the jump. */
6676 emit_barrier_after (location);
6677 location = NEXT_INSN (location);
6680 /* Emit marker for the end of the branch table. */
6681 emit_insn_before (gen_end_brtab (), location);
6682 location = NEXT_INSN (location);
6683 emit_barrier_after (location);
6685 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6691 /* Sill need an end_brtab insn. */
6692 insns = get_insns ();
6693 for (insn = insns; insn; insn = NEXT_INSN (insn))
6695 /* Find an ADDR_VEC insn. */
6696 if (GET_CODE (insn) != JUMP_INSN
6697 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6698 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6701 /* Now generate markers for the beginning and end of the
6703 emit_insn_before (gen_begin_brtab (), insn);
6704 emit_insn_after (gen_end_brtab (), insn);
6709 /* The PA has a number of odd instructions which can perform multiple
6710 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6711 it may be profitable to combine two instructions into one instruction
6712 with two outputs. It's not profitable PA2.0 machines because the
6713 two outputs would take two slots in the reorder buffers.
6715 This routine finds instructions which can be combined and combines
6716 them. We only support some of the potential combinations, and we
6717 only try common ways to find suitable instructions.
6719 * addb can add two registers or a register and a small integer
6720 and jump to a nearby (+-8k) location. Normally the jump to the
6721 nearby location is conditional on the result of the add, but by
6722 using the "true" condition we can make the jump unconditional.
6723 Thus addb can perform two independent operations in one insn.
6725 * movb is similar to addb in that it can perform a reg->reg
6726 or small immediate->reg copy and jump to a nearby (+-8k location).
6728 * fmpyadd and fmpysub can perform a FP multiply and either an
6729 FP add or FP sub if the operands of the multiply and add/sub are
6730 independent (there are other minor restrictions). Note both
6731 the fmpy and fadd/fsub can in theory move to better spots according
6732 to data dependencies, but for now we require the fmpy stay at a
6735 * Many of the memory operations can perform pre & post updates
6736 of index registers. GCC's pre/post increment/decrement addressing
6737 is far too simple to take advantage of all the possibilities. This
6738 pass may not be suitable since those insns may not be independent.
6740 * comclr can compare two ints or an int and a register, nullify
6741 the following instruction and zero some other register. This
6742 is more difficult to use as it's harder to find an insn which
6743 will generate a comclr than finding something like an unconditional
6744 branch. (conditional moves & long branches create comclr insns).
6746 * Most arithmetic operations can conditionally skip the next
6747 instruction. They can be viewed as "perform this operation
6748 and conditionally jump to this nearby location" (where nearby
6749 is an insns away). These are difficult to use due to the
6750 branch length restrictions. */
6753 pa_combine_instructions (insns)
6754 rtx insns ATTRIBUTE_UNUSED;
6758 /* This can get expensive since the basic algorithm is on the
6759 order of O(n^2) (or worse). Only do it for -O2 or higher
6760 levels of optimization. */
6764 /* Walk down the list of insns looking for "anchor" insns which
6765 may be combined with "floating" insns. As the name implies,
6766 "anchor" instructions don't move, while "floating" insns may
6768 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
6769 new = make_insn_raw (new);
6771 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
6773 enum attr_pa_combine_type anchor_attr;
6774 enum attr_pa_combine_type floater_attr;
6776 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6777 Also ignore any special USE insns. */
6778 if ((GET_CODE (anchor) != INSN
6779 && GET_CODE (anchor) != JUMP_INSN
6780 && GET_CODE (anchor) != CALL_INSN)
6781 || GET_CODE (PATTERN (anchor)) == USE
6782 || GET_CODE (PATTERN (anchor)) == CLOBBER
6783 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
6784 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
6787 anchor_attr = get_attr_pa_combine_type (anchor);
6788 /* See if anchor is an insn suitable for combination. */
6789 if (anchor_attr == PA_COMBINE_TYPE_FMPY
6790 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
6791 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6792 && ! forward_branch_p (anchor)))
6796 for (floater = PREV_INSN (anchor);
6798 floater = PREV_INSN (floater))
6800 if (GET_CODE (floater) == NOTE
6801 || (GET_CODE (floater) == INSN
6802 && (GET_CODE (PATTERN (floater)) == USE
6803 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6806 /* Anything except a regular INSN will stop our search. */
6807 if (GET_CODE (floater) != INSN
6808 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6809 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6815 /* See if FLOATER is suitable for combination with the
6817 floater_attr = get_attr_pa_combine_type (floater);
6818 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6819 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6820 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6821 && floater_attr == PA_COMBINE_TYPE_FMPY))
6823 /* If ANCHOR and FLOATER can be combined, then we're
6824 done with this pass. */
6825 if (pa_can_combine_p (new, anchor, floater, 0,
6826 SET_DEST (PATTERN (floater)),
6827 XEXP (SET_SRC (PATTERN (floater)), 0),
6828 XEXP (SET_SRC (PATTERN (floater)), 1)))
6832 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6833 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
6835 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
6837 if (pa_can_combine_p (new, anchor, floater, 0,
6838 SET_DEST (PATTERN (floater)),
6839 XEXP (SET_SRC (PATTERN (floater)), 0),
6840 XEXP (SET_SRC (PATTERN (floater)), 1)))
6845 if (pa_can_combine_p (new, anchor, floater, 0,
6846 SET_DEST (PATTERN (floater)),
6847 SET_SRC (PATTERN (floater)),
6848 SET_SRC (PATTERN (floater))))
6854 /* If we didn't find anything on the backwards scan try forwards. */
6856 && (anchor_attr == PA_COMBINE_TYPE_FMPY
6857 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
6859 for (floater = anchor; floater; floater = NEXT_INSN (floater))
6861 if (GET_CODE (floater) == NOTE
6862 || (GET_CODE (floater) == INSN
6863 && (GET_CODE (PATTERN (floater)) == USE
6864 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6868 /* Anything except a regular INSN will stop our search. */
6869 if (GET_CODE (floater) != INSN
6870 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6871 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6877 /* See if FLOATER is suitable for combination with the
6879 floater_attr = get_attr_pa_combine_type (floater);
6880 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6881 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6882 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6883 && floater_attr == PA_COMBINE_TYPE_FMPY))
6885 /* If ANCHOR and FLOATER can be combined, then we're
6886 done with this pass. */
6887 if (pa_can_combine_p (new, anchor, floater, 1,
6888 SET_DEST (PATTERN (floater)),
6889 XEXP (SET_SRC (PATTERN (floater)),
6891 XEXP (SET_SRC (PATTERN (floater)),
6898 /* FLOATER will be nonzero if we found a suitable floating
6899 insn for combination with ANCHOR. */
6901 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6902 || anchor_attr == PA_COMBINE_TYPE_FMPY))
6904 /* Emit the new instruction and delete the old anchor. */
6905 emit_insn_before (gen_rtx_PARALLEL
6907 gen_rtvec (2, PATTERN (anchor),
6908 PATTERN (floater))),
6911 PUT_CODE (anchor, NOTE);
6912 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6913 NOTE_SOURCE_FILE (anchor) = 0;
6915 /* Emit a special USE insn for FLOATER, then delete
6916 the floating insn. */
6917 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6918 delete_insn (floater);
6923 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
6926 /* Emit the new_jump instruction and delete the old anchor. */
6928 = emit_jump_insn_before (gen_rtx_PARALLEL
6930 gen_rtvec (2, PATTERN (anchor),
6931 PATTERN (floater))),
6934 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
6935 PUT_CODE (anchor, NOTE);
6936 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6937 NOTE_SOURCE_FILE (anchor) = 0;
6939 /* Emit a special USE insn for FLOATER, then delete
6940 the floating insn. */
6941 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6942 delete_insn (floater);
6950 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
6951 rtx new, anchor, floater;
6953 rtx dest, src1, src2;
6955 int insn_code_number;
6958 /* Create a PARALLEL with the patterns of ANCHOR and
6959 FLOATER, try to recognize it, then test constraints
6960 for the resulting pattern.
6962 If the pattern doesn't match or the constraints
6963 aren't met keep searching for a suitable floater
6965 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
6966 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
6967 INSN_CODE (new) = -1;
6968 insn_code_number = recog_memoized (new);
6969 if (insn_code_number < 0
6970 || !constrain_operands (1))
6984 /* There's up to three operands to consider. One
6985 output and two inputs.
6987 The output must not be used between FLOATER & ANCHOR
6988 exclusive. The inputs must not be set between
6989 FLOATER and ANCHOR exclusive. */
6991 if (reg_used_between_p (dest, start, end))
6994 if (reg_set_between_p (src1, start, end))
6997 if (reg_set_between_p (src2, start, end))
7000 /* If we get here, then everything is good. */
7004 /* Return nonzero if references for INSN are delayed.
7006 Millicode insns are actually function calls with some special
7007 constraints on arguments and register usage.
7009 Millicode calls always expect their arguments in the integer argument
7010 registers, and always return their result in %r29 (ret1). They
7011 are expected to clobber their arguments, %r1, %r29, and the return
7012 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
7014 This function tells reorg that the references to arguments and
7015 millicode calls do not appear to happen until after the millicode call.
7016 This allows reorg to put insns which set the argument registers into the
7017 delay slot of the millicode call -- thus they act more like traditional
7020 Note we can not consider side effects of the insn to be delayed because
7021 the branch and link insn will clobber the return pointer. If we happened
7022 to use the return pointer in the delay slot of the call, then we lose.
7024 get_attr_type will try to recognize the given insn, so make sure to
7025 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
7028 insn_refs_are_delayed (insn)
7031 return ((GET_CODE (insn) == INSN
7032 && GET_CODE (PATTERN (insn)) != SEQUENCE
7033 && GET_CODE (PATTERN (insn)) != USE
7034 && GET_CODE (PATTERN (insn)) != CLOBBER
7035 && get_attr_type (insn) == TYPE_MILLI));
7038 /* Return the location of a parameter that is passed in a register or NULL
7039 if the parameter has any component that is passed in memory.
7041 This is new code and will be pushed to into the net sources after
7044 ??? We might want to restructure this so that it looks more like other
7047 function_arg (cum, mode, type, named, incoming)
7048 CUMULATIVE_ARGS *cum;
7049 enum machine_mode mode;
7051 int named ATTRIBUTE_UNUSED;
7054 int max_arg_words = (TARGET_64BIT ? 8 : 4);
7061 /* If this arg would be passed partially or totally on the stack, then
7062 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
7063 handle arguments which are split between regs and stack slots if
7064 the ABI mandates split arguments. */
7065 if (cum->words + FUNCTION_ARG_SIZE (mode, type) > max_arg_words
7066 || mode == VOIDmode)
7072 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7074 if (cum->words + offset >= max_arg_words
7075 || mode == VOIDmode)
7079 /* The 32bit ABIs and the 64bit ABIs are rather different,
7080 particularly in their handling of FP registers. We might
7081 be able to cleverly share code between them, but I'm not
7082 going to bother in the hope that splitting them up results
7083 in code that is more easily understood.
7085 The 64bit code probably is very wrong for structure passing. */
7088 /* Advance the base registers to their current locations.
7090 Remember, gprs grow towards smaller register numbers while
7091 fprs grow to higher register numbers. Also remember FP regs
7092 are always 4 bytes wide, while the size of an integer register
7093 varies based on the size of the target word. */
7094 gpr_reg_base = 26 - cum->words;
7095 fpr_reg_base = 32 + cum->words;
7097 /* If the argument is more than a word long, then we need to align
7098 the base registers. Same caveats as above. */
7099 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7101 if (mode != BLKmode)
7103 /* First deal with alignment of the doubleword. */
7104 gpr_reg_base -= (cum->words & 1);
7106 /* This seems backwards, but it is what HP specifies. We need
7107 gpr_reg_base to point to the smaller numbered register of
7108 the integer register pair. So if we have an even register
7109 number, then decrement the gpr base. */
7110 gpr_reg_base -= ((gpr_reg_base % 2) == 0);
7112 /* FP values behave sanely, except that each FP reg is only
7114 fpr_reg_base += ((fpr_reg_base % 2) == 0);
7119 int i, offset = 0, ub;
7120 ub = FUNCTION_ARG_SIZE (mode, type);
7122 MAX (0, max_arg_words - cum->words - (cum->words & 1)));
7123 gpr_reg_base -= (cum->words & 1);
7124 for (i = 0; i < ub; i++)
7126 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7127 gen_rtx_REG (DImode,
7136 return XEXP (loc[0], 0);
7138 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7144 /* If the argument is larger than a word, then we know precisely
7145 which registers we must use. */
7146 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7161 /* We have a single word (32 bits). A simple computation
7162 will get us the register #s we need. */
7163 gpr_reg_base = 26 - cum->words;
7164 fpr_reg_base = 32 + 2 * cum->words;
7168 if (TARGET_64BIT && mode == TFmode)
7174 gen_rtx_EXPR_LIST (VOIDmode,
7175 gen_rtx_REG (DImode, gpr_reg_base + 1),
7177 gen_rtx_EXPR_LIST (VOIDmode,
7178 gen_rtx_REG (DImode, gpr_reg_base),
7181 /* Determine if the argument needs to be passed in both general and
7182 floating point registers. */
7183 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7184 /* If we are doing soft-float with portable runtime, then there
7185 is no need to worry about FP regs. */
7186 && ! TARGET_SOFT_FLOAT
7187 /* The parameter must be some kind of float, else we can just
7188 pass it in integer registers. */
7189 && FLOAT_MODE_P (mode)
7190 /* The target function must not have a prototype. */
7191 && cum->nargs_prototype <= 0
7192 /* libcalls do not need to pass items in both FP and general
7194 && type != NULL_TREE
7195 /* All this hair applies to outgoing args only. */
7197 /* Also pass outgoing floating arguments in both registers in indirect
7198 calls with the 32 bit ABI and the HP assembler since there is no
7199 way to the specify argument locations in static functions. */
7204 && FLOAT_MODE_P (mode)))
7210 gen_rtx_EXPR_LIST (VOIDmode,
7211 gen_rtx_REG (mode, fpr_reg_base),
7213 gen_rtx_EXPR_LIST (VOIDmode,
7214 gen_rtx_REG (mode, gpr_reg_base),
7219 /* See if we should pass this parameter in a general register. */
7220 if (TARGET_SOFT_FLOAT
7221 /* Indirect calls in the normal 32bit ABI require all arguments
7222 to be passed in general registers. */
7223 || (!TARGET_PORTABLE_RUNTIME
7226 /* If the parameter is not a floating point parameter, then
7227 it belongs in GPRs. */
7228 || !FLOAT_MODE_P (mode))
7229 retval = gen_rtx_REG (mode, gpr_reg_base);
7231 retval = gen_rtx_REG (mode, fpr_reg_base);
7237 /* If this arg would be passed totally in registers or totally on the stack,
7238 then this routine should return zero. It is currently called only for
7239 the 64-bit target. */
7241 function_arg_partial_nregs (cum, mode, type, named)
7242 CUMULATIVE_ARGS *cum;
7243 enum machine_mode mode;
7245 int named ATTRIBUTE_UNUSED;
7247 unsigned int max_arg_words = 8;
7248 unsigned int offset = 0;
7250 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7253 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
7254 /* Arg fits fully into registers. */
7256 else if (cum->words + offset >= max_arg_words)
7257 /* Arg fully on the stack. */
7261 return max_arg_words - cum->words - offset;
7265 /* Return 1 if this is a comparison operator. This allows the use of
7266 MATCH_OPERATOR to recognize all the branch insns. */
7269 cmpib_comparison_operator (op, mode)
7271 enum machine_mode mode;
7273 return ((mode == VOIDmode || GET_MODE (op) == mode)
7274 && (GET_CODE (op) == EQ
7275 || GET_CODE (op) == NE
7276 || GET_CODE (op) == GT
7277 || GET_CODE (op) == GTU
7278 || GET_CODE (op) == GE
7279 || GET_CODE (op) == LT
7280 || GET_CODE (op) == LE
7281 || GET_CODE (op) == LEU));
7284 /* Mark ARG (which is really a struct deferred_plabel **) for GC. */
7287 mark_deferred_plabels (arg)
7290 struct deferred_plabel *dp = *(struct deferred_plabel **) arg;
7293 for (i = 0; i < n_deferred_plabels; ++i)
7294 ggc_mark_rtx (dp[i].internal_label);
7297 /* Called to register all of our global variables with the garbage
7303 ggc_add_rtx_root (&hppa_compare_op0, 1);
7304 ggc_add_rtx_root (&hppa_compare_op1, 1);
7305 ggc_add_root (&deferred_plabels, 1, sizeof (&deferred_plabels),
7306 &mark_deferred_plabels);