1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
40 #include "integrate.h"
48 #include "target-def.h"
50 #ifndef DO_FRAME_NOTES
51 #ifdef INCOMING_RETURN_ADDR_RTX
52 #define DO_FRAME_NOTES 1
54 #define DO_FRAME_NOTES 0
58 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
59 static void pa_combine_instructions PARAMS ((rtx));
60 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
61 static int forward_branch_p PARAMS ((rtx));
62 static int shadd_constant_p PARAMS ((int));
63 static void pa_add_gc_roots PARAMS ((void));
64 static void mark_deferred_plabels PARAMS ((void *));
65 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
66 static int compute_movstrsi_length PARAMS ((rtx));
67 static void remove_useless_addtr_insns PARAMS ((rtx, int));
68 static rtx store_reg PARAMS ((int, int, int));
69 static rtx load_reg PARAMS ((int, int, int));
70 static rtx set_reg_plus_d PARAMS ((int, int, int));
71 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
72 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
73 static int pa_adjust_priority PARAMS ((rtx, int));
74 static int pa_issue_rate PARAMS ((void));
76 /* Save the operands last given to a compare for use when we
77 generate a scc or bcc insn. */
79 rtx hppa_compare_op0, hppa_compare_op1;
80 enum cmp_type hppa_branch_type;
82 /* Which cpu we are scheduling for. */
83 enum processor_type pa_cpu;
85 /* String to hold which cpu we are scheduling for. */
86 const char *pa_cpu_string;
88 /* Which architecture we are generating code for. */
89 enum architecture_type pa_arch;
91 /* String to hold which architecture we are generating code for. */
92 const char *pa_arch_string;
94 /* Counts for the number of callee-saved general and floating point
95 registers which were saved by the current function's prologue. */
96 static int gr_saved, fr_saved;
98 static rtx find_addr_reg PARAMS ((rtx));
100 /* Keep track of the number of bytes we have output in the CODE subspaces
101 during this compilation so we'll know when to emit inline long-calls. */
103 unsigned int total_code_bytes;
105 /* Variables to handle plabels that we discover are necessary at assembly
106 output time. They are output after the current function. */
108 struct deferred_plabel
112 } *deferred_plabels = 0;
113 int n_deferred_plabels = 0;
115 /* Initialize the GCC target structure. */
116 #undef TARGET_ASM_FUNCTION_PROLOGUE
117 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
118 #undef TARGET_ASM_FUNCTION_EPILOGUE
119 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
121 #undef TARGET_SCHED_ADJUST_COST
122 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
123 #undef TARGET_SCHED_ADJUST_PRIORITY
124 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
125 #undef TARGET_SCHED_ISSUE_RATE
126 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
128 struct gcc_target targetm = TARGET_INITIALIZER;
133 /* Default to 7100LC scheduling. */
134 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
136 pa_cpu_string = "7100";
137 pa_cpu = PROCESSOR_7100;
139 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
141 pa_cpu_string = "700";
142 pa_cpu = PROCESSOR_700;
144 else if (pa_cpu_string == NULL
145 || ! strcmp (pa_cpu_string, "7100LC"))
147 pa_cpu_string = "7100LC";
148 pa_cpu = PROCESSOR_7100LC;
150 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
152 pa_cpu_string = "7200";
153 pa_cpu = PROCESSOR_7200;
155 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "8000"))
157 pa_cpu_string = "8000";
158 pa_cpu = PROCESSOR_8000;
162 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string);
165 /* Set the instruction set architecture. */
166 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
168 pa_arch_string = "1.0";
169 pa_arch = ARCHITECTURE_10;
170 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
172 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
174 pa_arch_string = "1.1";
175 pa_arch = ARCHITECTURE_11;
176 target_flags &= ~MASK_PA_20;
177 target_flags |= MASK_PA_11;
179 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
181 pa_arch_string = "2.0";
182 pa_arch = ARCHITECTURE_20;
183 target_flags |= MASK_PA_11 | MASK_PA_20;
185 else if (pa_arch_string)
187 warning ("Unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
190 if (flag_pic && TARGET_PORTABLE_RUNTIME)
192 warning ("PIC code generation is not supported in the portable runtime model\n");
195 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
197 warning ("PIC code generation is not compatible with fast indirect calls\n");
200 if (! TARGET_GAS && write_symbols != NO_DEBUG)
202 warning ("-g is only supported when using GAS on this processor,");
203 warning ("-g option disabled.");
204 write_symbols = NO_DEBUG;
207 /* We only support the "big PIC" model now. And we always generate PIC
208 code when in 64bit mode. */
209 if (flag_pic == 1 || TARGET_64BIT)
212 /* Register global variables with the garbage collector. */
216 /* Return non-zero only if OP is a register of mode MODE,
219 reg_or_0_operand (op, mode)
221 enum machine_mode mode;
223 return (op == CONST0_RTX (mode) || register_operand (op, mode));
226 /* Return non-zero if OP is suitable for use in a call to a named
229 For 2.5 try to eliminate either call_operand_address or
230 function_label_operand, they perform very similar functions. */
232 call_operand_address (op, mode)
234 enum machine_mode mode ATTRIBUTE_UNUSED;
236 return (GET_MODE (op) == word_mode
237 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
240 /* Return 1 if X contains a symbolic expression. We know these
241 expressions will have one of a few well defined forms, so
242 we need only check those forms. */
244 symbolic_expression_p (x)
248 /* Strip off any HIGH. */
249 if (GET_CODE (x) == HIGH)
252 return (symbolic_operand (x, VOIDmode));
256 symbolic_operand (op, mode)
258 enum machine_mode mode ATTRIBUTE_UNUSED;
260 switch (GET_CODE (op))
267 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
268 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
269 && GET_CODE (XEXP (op, 1)) == CONST_INT);
275 /* Return truth value of statement that OP is a symbolic memory
276 operand of mode MODE. */
279 symbolic_memory_operand (op, mode)
281 enum machine_mode mode ATTRIBUTE_UNUSED;
283 if (GET_CODE (op) == SUBREG)
284 op = SUBREG_REG (op);
285 if (GET_CODE (op) != MEM)
288 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
289 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
292 /* Return 1 if the operand is either a register or a memory operand that is
296 reg_or_nonsymb_mem_operand (op, mode)
298 enum machine_mode mode;
300 if (register_operand (op, mode))
303 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
309 /* Return 1 if the operand is either a register, zero, or a memory operand
310 that is not symbolic. */
313 reg_or_0_or_nonsymb_mem_operand (op, mode)
315 enum machine_mode mode;
317 if (register_operand (op, mode))
320 if (op == CONST0_RTX (mode))
323 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
329 /* Accept any constant that can be moved in one instructions into a
332 cint_ok_for_move (intval)
333 HOST_WIDE_INT intval;
335 /* OK if ldo, ldil, or zdepi, can be used. */
336 return (CONST_OK_FOR_LETTER_P (intval, 'J')
337 || CONST_OK_FOR_LETTER_P (intval, 'N')
338 || CONST_OK_FOR_LETTER_P (intval, 'K'));
341 /* Accept anything that can be moved in one instruction into a general
344 move_operand (op, mode)
346 enum machine_mode mode;
348 if (register_operand (op, mode))
351 if (GET_CODE (op) == CONSTANT_P_RTX)
354 if (GET_CODE (op) == CONST_INT)
355 return cint_ok_for_move (INTVAL (op));
357 if (GET_CODE (op) == SUBREG)
358 op = SUBREG_REG (op);
359 if (GET_CODE (op) != MEM)
364 /* We consider a LO_SUM DLT reference a move_operand now since it has
365 been merged into the normal movsi/movdi patterns. */
366 if (GET_CODE (op) == LO_SUM
367 && GET_CODE (XEXP (op, 0)) == REG
368 && REG_OK_FOR_BASE_P (XEXP (op, 0))
369 && GET_CODE (XEXP (op, 1)) == UNSPEC
370 && GET_MODE (op) == Pmode)
373 /* Since move_operand is only used for source operands, we can always
374 allow scaled indexing! */
375 if (! TARGET_DISABLE_INDEXING
376 && GET_CODE (op) == PLUS
377 && ((GET_CODE (XEXP (op, 0)) == MULT
378 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
379 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
380 && INTVAL (XEXP (XEXP (op, 0), 1))
381 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
382 && GET_CODE (XEXP (op, 1)) == REG)
383 || (GET_CODE (XEXP (op, 1)) == MULT
384 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
385 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
386 && INTVAL (XEXP (XEXP (op, 1), 1))
387 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
388 && GET_CODE (XEXP (op, 0)) == REG)))
391 return memory_address_p (mode, op);
394 /* Accept REG and any CONST_INT that can be moved in one instruction into a
397 reg_or_cint_move_operand (op, mode)
399 enum machine_mode mode;
401 if (register_operand (op, mode))
404 if (GET_CODE (op) == CONST_INT)
405 return cint_ok_for_move (INTVAL (op));
411 pic_label_operand (op, mode)
413 enum machine_mode mode ATTRIBUTE_UNUSED;
418 switch (GET_CODE (op))
424 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
425 && GET_CODE (XEXP (op, 1)) == CONST_INT);
432 fp_reg_operand (op, mode)
434 enum machine_mode mode ATTRIBUTE_UNUSED;
436 return reg_renumber && FP_REG_P (op);
441 /* Return truth value of whether OP can be used as an operand in a
442 three operand arithmetic insn that accepts registers of mode MODE
443 or 14-bit signed integers. */
445 arith_operand (op, mode)
447 enum machine_mode mode;
449 return (register_operand (op, mode)
450 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
453 /* Return truth value of whether OP can be used as an operand in a
454 three operand arithmetic insn that accepts registers of mode MODE
455 or 11-bit signed integers. */
457 arith11_operand (op, mode)
459 enum machine_mode mode;
461 return (register_operand (op, mode)
462 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
465 /* A constant integer suitable for use in a PRE_MODIFY memory
468 pre_cint_operand (op, mode)
470 enum machine_mode mode ATTRIBUTE_UNUSED;
472 return (GET_CODE (op) == CONST_INT
473 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
476 /* A constant integer suitable for use in a POST_MODIFY memory
479 post_cint_operand (op, mode)
481 enum machine_mode mode ATTRIBUTE_UNUSED;
483 return (GET_CODE (op) == CONST_INT
484 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
488 arith_double_operand (op, mode)
490 enum machine_mode mode;
492 return (register_operand (op, mode)
493 || (GET_CODE (op) == CONST_DOUBLE
494 && GET_MODE (op) == mode
495 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
496 && ((CONST_DOUBLE_HIGH (op) >= 0)
497 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
500 /* Return truth value of whether OP is a integer which fits the
501 range constraining immediate operands in three-address insns, or
502 is an integer register. */
505 ireg_or_int5_operand (op, mode)
507 enum machine_mode mode ATTRIBUTE_UNUSED;
509 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
510 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
513 /* Return nonzero if OP is an integer register, else return zero. */
515 ireg_operand (op, mode)
517 enum machine_mode mode ATTRIBUTE_UNUSED;
519 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
522 /* Return truth value of whether OP is a integer which fits the
523 range constraining immediate operands in three-address insns. */
526 int5_operand (op, mode)
528 enum machine_mode mode ATTRIBUTE_UNUSED;
530 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
534 uint5_operand (op, mode)
536 enum machine_mode mode ATTRIBUTE_UNUSED;
538 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
542 int11_operand (op, mode)
544 enum machine_mode mode ATTRIBUTE_UNUSED;
546 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
550 uint32_operand (op, mode)
552 enum machine_mode mode ATTRIBUTE_UNUSED;
554 #if HOST_BITS_PER_WIDE_INT > 32
555 /* All allowed constants will fit a CONST_INT. */
556 return (GET_CODE (op) == CONST_INT
557 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
559 return (GET_CODE (op) == CONST_INT
560 || (GET_CODE (op) == CONST_DOUBLE
561 && CONST_DOUBLE_HIGH (op) == 0));
566 arith5_operand (op, mode)
568 enum machine_mode mode;
570 return register_operand (op, mode) || int5_operand (op, mode);
573 /* True iff zdepi can be used to generate this CONST_INT.
574 zdepi first sign extends a 5 bit signed number to a given field
575 length, then places this field anywhere in a zero. */
578 unsigned HOST_WIDE_INT x;
580 unsigned HOST_WIDE_INT lsb_mask, t;
582 /* This might not be obvious, but it's at least fast.
583 This function is critical; we don't have the time loops would take. */
585 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
586 /* Return true iff t is a power of two. */
587 return ((t & (t - 1)) == 0);
590 /* True iff depi or extru can be used to compute (reg & mask).
591 Accept bit pattern like these:
597 unsigned HOST_WIDE_INT mask;
600 mask += mask & -mask;
601 return (mask & (mask - 1)) == 0;
604 /* True iff depi or extru can be used to compute (reg & OP). */
606 and_operand (op, mode)
608 enum machine_mode mode;
610 return (register_operand (op, mode)
611 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
614 /* True iff depi can be used to compute (reg | MASK). */
617 unsigned HOST_WIDE_INT mask;
619 mask += mask & -mask;
620 return (mask & (mask - 1)) == 0;
623 /* True iff depi can be used to compute (reg | OP). */
625 ior_operand (op, mode)
627 enum machine_mode mode ATTRIBUTE_UNUSED;
629 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
633 lhs_lshift_operand (op, mode)
635 enum machine_mode mode;
637 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
640 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
641 Such values can be the left hand side x in (x << r), using the zvdepi
644 lhs_lshift_cint_operand (op, mode)
646 enum machine_mode mode ATTRIBUTE_UNUSED;
648 unsigned HOST_WIDE_INT x;
649 if (GET_CODE (op) != CONST_INT)
651 x = INTVAL (op) >> 4;
652 return (x & (x + 1)) == 0;
656 arith32_operand (op, mode)
658 enum machine_mode mode;
660 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
664 pc_or_label_operand (op, mode)
666 enum machine_mode mode ATTRIBUTE_UNUSED;
668 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
671 /* Legitimize PIC addresses. If the address is already
672 position-independent, we return ORIG. Newly generated
673 position-independent addresses go to REG. If we need more
674 than one register, we lose. */
677 legitimize_pic_address (orig, mode, reg)
679 enum machine_mode mode;
683 /* Labels need special handling. */
684 if (pic_label_operand (orig, mode))
686 /* We do not want to go through the movXX expanders here since that
687 would create recursion.
689 Nor do we really want to call a generator for a named pattern
690 since that requires multiple patterns if we want to support
693 So instead we just emit the raw set, which avoids the movXX
694 expanders completely. */
695 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
696 current_function_uses_pic_offset_table = 1;
699 if (GET_CODE (orig) == SYMBOL_REF)
705 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
706 gen_rtx_HIGH (word_mode, orig)));
708 = gen_rtx_MEM (Pmode,
709 gen_rtx_LO_SUM (Pmode, reg,
710 gen_rtx_UNSPEC (Pmode,
714 current_function_uses_pic_offset_table = 1;
715 RTX_UNCHANGING_P (pic_ref) = 1;
716 emit_move_insn (reg, pic_ref);
719 else if (GET_CODE (orig) == CONST)
723 if (GET_CODE (XEXP (orig, 0)) == PLUS
724 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
730 if (GET_CODE (XEXP (orig, 0)) == PLUS)
732 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
733 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
734 base == reg ? 0 : reg);
737 if (GET_CODE (orig) == CONST_INT)
739 if (INT_14_BITS (orig))
740 return plus_constant (base, INTVAL (orig));
741 orig = force_reg (Pmode, orig);
743 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
744 /* Likewise, should we set special REG_NOTEs here? */
749 /* Try machine-dependent ways of modifying an illegitimate address
750 to be legitimate. If we find one, return the new, valid address.
751 This macro is used in only one place: `memory_address' in explow.c.
753 OLDX is the address as it was before break_out_memory_refs was called.
754 In some cases it is useful to look at this to decide what needs to be done.
756 MODE and WIN are passed so that this macro can use
757 GO_IF_LEGITIMATE_ADDRESS.
759 It is always safe for this macro to do nothing. It exists to recognize
760 opportunities to optimize the output.
762 For the PA, transform:
764 memory(X + <large int>)
768 if (<large int> & mask) >= 16
769 Y = (<large int> & ~mask) + mask + 1 Round up.
771 Y = (<large int> & ~mask) Round down.
773 memory (Z + (<large int> - Y));
775 This is for CSE to find several similar references, and only use one Z.
777 X can either be a SYMBOL_REF or REG, but because combine can not
778 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
779 D will not fit in 14 bits.
781 MODE_FLOAT references allow displacements which fit in 5 bits, so use
784 MODE_INT references allow displacements which fit in 14 bits, so use
787 This relies on the fact that most mode MODE_FLOAT references will use FP
788 registers and most mode MODE_INT references will use integer registers.
789 (In the rare case of an FP register used in an integer MODE, we depend
790 on secondary reloads to clean things up.)
793 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
794 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
795 addressing modes to be used).
797 Put X and Z into registers. Then put the entire expression into
801 hppa_legitimize_address (x, oldx, mode)
802 rtx x, oldx ATTRIBUTE_UNUSED;
803 enum machine_mode mode;
808 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
810 /* Strip off CONST. */
811 if (GET_CODE (x) == CONST)
814 /* Special case. Get the SYMBOL_REF into a register and use indexing.
815 That should always be safe. */
816 if (GET_CODE (x) == PLUS
817 && GET_CODE (XEXP (x, 0)) == REG
818 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
820 rtx reg = force_reg (Pmode, XEXP (x, 1));
821 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
824 /* Note we must reject symbols which represent function addresses
825 since the assembler/linker can't handle arithmetic on plabels. */
826 if (GET_CODE (x) == PLUS
827 && GET_CODE (XEXP (x, 1)) == CONST_INT
828 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
829 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
830 || GET_CODE (XEXP (x, 0)) == REG))
832 rtx int_part, ptr_reg;
834 int offset = INTVAL (XEXP (x, 1));
837 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
838 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
840 /* Choose which way to round the offset. Round up if we
841 are >= halfway to the next boundary. */
842 if ((offset & mask) >= ((mask + 1) / 2))
843 newoffset = (offset & ~ mask) + mask + 1;
845 newoffset = (offset & ~ mask);
847 /* If the newoffset will not fit in 14 bits (ldo), then
848 handling this would take 4 or 5 instructions (2 to load
849 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
850 add the new offset and the SYMBOL_REF.) Combine can
851 not handle 4->2 or 5->2 combinations, so do not create
853 if (! VAL_14_BITS_P (newoffset)
854 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
856 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
859 gen_rtx_HIGH (Pmode, const_part));
862 gen_rtx_LO_SUM (Pmode,
863 tmp_reg, const_part));
867 if (! VAL_14_BITS_P (newoffset))
868 int_part = force_reg (Pmode, GEN_INT (newoffset));
870 int_part = GEN_INT (newoffset);
872 ptr_reg = force_reg (Pmode,
874 force_reg (Pmode, XEXP (x, 0)),
877 return plus_constant (ptr_reg, offset - newoffset);
880 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
882 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
883 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
884 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
885 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
886 || GET_CODE (XEXP (x, 1)) == SUBREG)
887 && GET_CODE (XEXP (x, 1)) != CONST)
889 int val = INTVAL (XEXP (XEXP (x, 0), 1));
893 if (GET_CODE (reg1) != REG)
894 reg1 = force_reg (Pmode, force_operand (reg1, 0));
896 reg2 = XEXP (XEXP (x, 0), 0);
897 if (GET_CODE (reg2) != REG)
898 reg2 = force_reg (Pmode, force_operand (reg2, 0));
900 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
907 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
909 Only do so for floating point modes since this is more speculative
910 and we lose if it's an integer store. */
911 if (GET_CODE (x) == PLUS
912 && GET_CODE (XEXP (x, 0)) == PLUS
913 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
914 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
915 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
916 && (mode == SFmode || mode == DFmode))
919 /* First, try and figure out what to use as a base register. */
920 rtx reg1, reg2, base, idx, orig_base;
922 reg1 = XEXP (XEXP (x, 0), 1);
927 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
928 then emit_move_sequence will turn on REG_POINTER so we'll know
929 it's a base register below. */
930 if (GET_CODE (reg1) != REG)
931 reg1 = force_reg (Pmode, force_operand (reg1, 0));
933 if (GET_CODE (reg2) != REG)
934 reg2 = force_reg (Pmode, force_operand (reg2, 0));
936 /* Figure out what the base and index are. */
938 if (GET_CODE (reg1) == REG
939 && REG_POINTER (reg1))
942 orig_base = XEXP (XEXP (x, 0), 1);
943 idx = gen_rtx_PLUS (Pmode,
945 XEXP (XEXP (XEXP (x, 0), 0), 0),
946 XEXP (XEXP (XEXP (x, 0), 0), 1)),
949 else if (GET_CODE (reg2) == REG
950 && REG_POINTER (reg2))
953 orig_base = XEXP (x, 1);
960 /* If the index adds a large constant, try to scale the
961 constant so that it can be loaded with only one insn. */
962 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
963 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
964 / INTVAL (XEXP (XEXP (idx, 0), 1)))
965 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
967 /* Divide the CONST_INT by the scale factor, then add it to A. */
968 int val = INTVAL (XEXP (idx, 1));
970 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
971 reg1 = XEXP (XEXP (idx, 0), 0);
972 if (GET_CODE (reg1) != REG)
973 reg1 = force_reg (Pmode, force_operand (reg1, 0));
975 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
977 /* We can now generate a simple scaled indexed address. */
980 (Pmode, gen_rtx_PLUS (Pmode,
981 gen_rtx_MULT (Pmode, reg1,
982 XEXP (XEXP (idx, 0), 1)),
986 /* If B + C is still a valid base register, then add them. */
987 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
988 && INTVAL (XEXP (idx, 1)) <= 4096
989 && INTVAL (XEXP (idx, 1)) >= -4096)
991 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
994 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
996 reg2 = XEXP (XEXP (idx, 0), 0);
997 if (GET_CODE (reg2) != CONST_INT)
998 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1000 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1001 gen_rtx_MULT (Pmode,
1007 /* Get the index into a register, then add the base + index and
1008 return a register holding the result. */
1010 /* First get A into a register. */
1011 reg1 = XEXP (XEXP (idx, 0), 0);
1012 if (GET_CODE (reg1) != REG)
1013 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1015 /* And get B into a register. */
1016 reg2 = XEXP (idx, 1);
1017 if (GET_CODE (reg2) != REG)
1018 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1020 reg1 = force_reg (Pmode,
1021 gen_rtx_PLUS (Pmode,
1022 gen_rtx_MULT (Pmode, reg1,
1023 XEXP (XEXP (idx, 0), 1)),
1026 /* Add the result to our base register and return. */
1027 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1031 /* Uh-oh. We might have an address for x[n-100000]. This needs
1032 special handling to avoid creating an indexed memory address
1033 with x-100000 as the base.
1035 If the constant part is small enough, then it's still safe because
1036 there is a guard page at the beginning and end of the data segment.
1038 Scaled references are common enough that we want to try and rearrange the
1039 terms so that we can use indexing for these addresses too. Only
1040 do the optimization for floatint point modes. */
1042 if (GET_CODE (x) == PLUS
1043 && symbolic_expression_p (XEXP (x, 1)))
1045 /* Ugly. We modify things here so that the address offset specified
1046 by the index expression is computed first, then added to x to form
1047 the entire address. */
1049 rtx regx1, regx2, regy1, regy2, y;
1051 /* Strip off any CONST. */
1053 if (GET_CODE (y) == CONST)
1056 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1058 /* See if this looks like
1059 (plus (mult (reg) (shadd_const))
1060 (const (plus (symbol_ref) (const_int))))
1062 Where const_int is small. In that case the const
1063 expression is a valid pointer for indexing.
1065 If const_int is big, but can be divided evenly by shadd_const
1066 and added to (reg). This allows more scaled indexed addresses. */
1067 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1068 && GET_CODE (XEXP (x, 0)) == MULT
1069 && GET_CODE (XEXP (y, 1)) == CONST_INT
1070 && INTVAL (XEXP (y, 1)) >= -4096
1071 && INTVAL (XEXP (y, 1)) <= 4095
1072 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1073 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1075 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1079 if (GET_CODE (reg1) != REG)
1080 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1082 reg2 = XEXP (XEXP (x, 0), 0);
1083 if (GET_CODE (reg2) != REG)
1084 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1086 return force_reg (Pmode,
1087 gen_rtx_PLUS (Pmode,
1088 gen_rtx_MULT (Pmode,
1093 else if ((mode == DFmode || mode == SFmode)
1094 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1095 && GET_CODE (XEXP (x, 0)) == MULT
1096 && GET_CODE (XEXP (y, 1)) == CONST_INT
1097 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1098 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1099 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1102 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1103 / INTVAL (XEXP (XEXP (x, 0), 1))));
1104 regx2 = XEXP (XEXP (x, 0), 0);
1105 if (GET_CODE (regx2) != REG)
1106 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1107 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1111 gen_rtx_PLUS (Pmode,
1112 gen_rtx_MULT (Pmode, regx2,
1113 XEXP (XEXP (x, 0), 1)),
1114 force_reg (Pmode, XEXP (y, 0))));
1116 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1117 && INTVAL (XEXP (y, 1)) >= -4096
1118 && INTVAL (XEXP (y, 1)) <= 4095)
1120 /* This is safe because of the guard page at the
1121 beginning and end of the data space. Just
1122 return the original address. */
1127 /* Doesn't look like one we can optimize. */
1128 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1129 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1130 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1131 regx1 = force_reg (Pmode,
1132 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1134 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1142 /* For the HPPA, REG and REG+CONST is cost 0
1143 and addresses involving symbolic constants are cost 2.
1145 PIC addresses are very expensive.
1147 It is no coincidence that this has the same structure
1148 as GO_IF_LEGITIMATE_ADDRESS. */
1150 hppa_address_cost (X)
1153 if (GET_CODE (X) == PLUS)
1155 else if (GET_CODE (X) == LO_SUM)
1157 else if (GET_CODE (X) == HIGH)
1162 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1163 new rtx with the correct mode. */
1165 force_mode (mode, orig)
1166 enum machine_mode mode;
1169 if (mode == GET_MODE (orig))
1172 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1175 return gen_rtx_REG (mode, REGNO (orig));
1178 /* Emit insns to move operands[1] into operands[0].
1180 Return 1 if we have written out everything that needs to be done to
1181 do the move. Otherwise, return 0 and the caller will emit the move
1184 Note SCRATCH_REG may not be in the proper mode depending on how it
1185 will be used. This routine is resposible for creating a new copy
1186 of SCRATCH_REG in the proper mode. */
1189 emit_move_sequence (operands, mode, scratch_reg)
1191 enum machine_mode mode;
1194 register rtx operand0 = operands[0];
1195 register rtx operand1 = operands[1];
1199 && reload_in_progress && GET_CODE (operand0) == REG
1200 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1201 operand0 = reg_equiv_mem[REGNO (operand0)];
1202 else if (scratch_reg
1203 && reload_in_progress && GET_CODE (operand0) == SUBREG
1204 && GET_CODE (SUBREG_REG (operand0)) == REG
1205 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1207 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1208 the code which tracks sets/uses for delete_output_reload. */
1209 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1210 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1211 SUBREG_BYTE (operand0));
1212 operand0 = alter_subreg (temp);
1216 && reload_in_progress && GET_CODE (operand1) == REG
1217 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1218 operand1 = reg_equiv_mem[REGNO (operand1)];
1219 else if (scratch_reg
1220 && reload_in_progress && GET_CODE (operand1) == SUBREG
1221 && GET_CODE (SUBREG_REG (operand1)) == REG
1222 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1224 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1225 the code which tracks sets/uses for delete_output_reload. */
1226 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1227 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1228 SUBREG_BYTE (operand1));
1229 operand1 = alter_subreg (temp);
1232 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1233 && ((tem = find_replacement (&XEXP (operand0, 0)))
1234 != XEXP (operand0, 0)))
1235 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1236 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1237 && ((tem = find_replacement (&XEXP (operand1, 0)))
1238 != XEXP (operand1, 0)))
1239 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1241 /* Handle secondary reloads for loads/stores of FP registers from
1242 REG+D addresses where D does not fit in 5 bits, including
1243 (subreg (mem (addr))) cases. */
1244 if (fp_reg_operand (operand0, mode)
1245 && ((GET_CODE (operand1) == MEM
1246 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1247 || ((GET_CODE (operand1) == SUBREG
1248 && GET_CODE (XEXP (operand1, 0)) == MEM
1249 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1252 if (GET_CODE (operand1) == SUBREG)
1253 operand1 = XEXP (operand1, 0);
1255 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1256 it in WORD_MODE regardless of what mode it was originally given
1258 scratch_reg = force_mode (word_mode, scratch_reg);
1260 /* D might not fit in 14 bits either; for such cases load D into
1262 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1264 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1265 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1267 XEXP (XEXP (operand1, 0), 0),
1271 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1272 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1273 gen_rtx_MEM (mode, scratch_reg)));
1276 else if (fp_reg_operand (operand1, mode)
1277 && ((GET_CODE (operand0) == MEM
1278 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1279 || ((GET_CODE (operand0) == SUBREG)
1280 && GET_CODE (XEXP (operand0, 0)) == MEM
1281 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1284 if (GET_CODE (operand0) == SUBREG)
1285 operand0 = XEXP (operand0, 0);
1287 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1288 it in WORD_MODE regardless of what mode it was originally given
1290 scratch_reg = force_mode (word_mode, scratch_reg);
1292 /* D might not fit in 14 bits either; for such cases load D into
1294 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1296 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1297 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1300 XEXP (XEXP (operand0, 0),
1305 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1306 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1310 /* Handle secondary reloads for loads of FP registers from constant
1311 expressions by forcing the constant into memory.
1313 use scratch_reg to hold the address of the memory location.
1315 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1316 NO_REGS when presented with a const_int and an register class
1317 containing only FP registers. Doing so unfortunately creates
1318 more problems than it solves. Fix this for 2.5. */
1319 else if (fp_reg_operand (operand0, mode)
1320 && CONSTANT_P (operand1)
1325 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1326 it in WORD_MODE regardless of what mode it was originally given
1328 scratch_reg = force_mode (word_mode, scratch_reg);
1330 /* Force the constant into memory and put the address of the
1331 memory location into scratch_reg. */
1332 xoperands[0] = scratch_reg;
1333 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1334 emit_move_sequence (xoperands, Pmode, 0);
1336 /* Now load the destination register. */
1337 emit_insn (gen_rtx_SET (mode, operand0,
1338 gen_rtx_MEM (mode, scratch_reg)));
1341 /* Handle secondary reloads for SAR. These occur when trying to load
1342 the SAR from memory, FP register, or with a constant. */
1343 else if (GET_CODE (operand0) == REG
1344 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1345 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1346 && (GET_CODE (operand1) == MEM
1347 || GET_CODE (operand1) == CONST_INT
1348 || (GET_CODE (operand1) == REG
1349 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1352 /* D might not fit in 14 bits either; for such cases load D into
1354 if (GET_CODE (operand1) == MEM
1355 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1357 /* We are reloading the address into the scratch register, so we
1358 want to make sure the scratch register is a full register. */
1359 scratch_reg = force_mode (word_mode, scratch_reg);
1361 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1362 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1365 XEXP (XEXP (operand1, 0),
1369 /* Now we are going to load the scratch register from memory,
1370 we want to load it in the same width as the original MEM,
1371 which must be the same as the width of the ultimate destination,
1373 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1375 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1380 /* We want to load the scratch register using the same mode as
1381 the ultimate destination. */
1382 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1384 emit_move_insn (scratch_reg, operand1);
1387 /* And emit the insn to set the ultimate destination. We know that
1388 the scratch register has the same mode as the destination at this
1390 emit_move_insn (operand0, scratch_reg);
1393 /* Handle most common case: storing into a register. */
1394 else if (register_operand (operand0, mode))
1396 if (register_operand (operand1, mode)
1397 || (GET_CODE (operand1) == CONST_INT && INT_14_BITS (operand1))
1398 || (operand1 == CONST0_RTX (mode))
1399 || (GET_CODE (operand1) == HIGH
1400 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1401 /* Only `general_operands' can come here, so MEM is ok. */
1402 || GET_CODE (operand1) == MEM)
1404 /* Run this case quickly. */
1405 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1409 else if (GET_CODE (operand0) == MEM)
1411 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1412 && !(reload_in_progress || reload_completed))
1414 rtx temp = gen_reg_rtx (DFmode);
1416 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1417 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1420 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1422 /* Run this case quickly. */
1423 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1426 if (! (reload_in_progress || reload_completed))
1428 operands[0] = validize_mem (operand0);
1429 operands[1] = operand1 = force_reg (mode, operand1);
1433 /* Simplify the source if we need to.
1434 Note we do have to handle function labels here, even though we do
1435 not consider them legitimate constants. Loop optimizations can
1436 call the emit_move_xxx with one as a source. */
1437 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1438 || function_label_operand (operand1, mode)
1439 || (GET_CODE (operand1) == HIGH
1440 && symbolic_operand (XEXP (operand1, 0), mode)))
1444 if (GET_CODE (operand1) == HIGH)
1447 operand1 = XEXP (operand1, 0);
1449 if (symbolic_operand (operand1, mode))
1451 /* Argh. The assembler and linker can't handle arithmetic
1454 So we force the plabel into memory, load operand0 from
1455 the memory location, then add in the constant part. */
1456 if ((GET_CODE (operand1) == CONST
1457 && GET_CODE (XEXP (operand1, 0)) == PLUS
1458 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1459 || function_label_operand (operand1, mode))
1461 rtx temp, const_part;
1463 /* Figure out what (if any) scratch register to use. */
1464 if (reload_in_progress || reload_completed)
1466 scratch_reg = scratch_reg ? scratch_reg : operand0;
1467 /* SCRATCH_REG will hold an address and maybe the actual
1468 data. We want it in WORD_MODE regardless of what mode it
1469 was originally given to us. */
1470 scratch_reg = force_mode (word_mode, scratch_reg);
1473 scratch_reg = gen_reg_rtx (Pmode);
1475 if (GET_CODE (operand1) == CONST)
1477 /* Save away the constant part of the expression. */
1478 const_part = XEXP (XEXP (operand1, 0), 1);
1479 if (GET_CODE (const_part) != CONST_INT)
1482 /* Force the function label into memory. */
1483 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1487 /* No constant part. */
1488 const_part = NULL_RTX;
1490 /* Force the function label into memory. */
1491 temp = force_const_mem (mode, operand1);
1495 /* Get the address of the memory location. PIC-ify it if
1497 temp = XEXP (temp, 0);
1499 temp = legitimize_pic_address (temp, mode, scratch_reg);
1501 /* Put the address of the memory location into our destination
1504 emit_move_sequence (operands, mode, scratch_reg);
1506 /* Now load from the memory location into our destination
1508 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1509 emit_move_sequence (operands, mode, scratch_reg);
1511 /* And add back in the constant part. */
1512 if (const_part != NULL_RTX)
1513 expand_inc (operand0, const_part);
1522 if (reload_in_progress || reload_completed)
1524 temp = scratch_reg ? scratch_reg : operand0;
1525 /* TEMP will hold an address and maybe the actual
1526 data. We want it in WORD_MODE regardless of what mode it
1527 was originally given to us. */
1528 temp = force_mode (word_mode, temp);
1531 temp = gen_reg_rtx (Pmode);
1533 /* (const (plus (symbol) (const_int))) must be forced to
1534 memory during/after reload if the const_int will not fit
1536 if (GET_CODE (operand1) == CONST
1537 && GET_CODE (XEXP (operand1, 0)) == PLUS
1538 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1539 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1540 && (reload_completed || reload_in_progress)
1543 operands[1] = force_const_mem (mode, operand1);
1544 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1546 emit_move_sequence (operands, mode, temp);
1550 operands[1] = legitimize_pic_address (operand1, mode, temp);
1551 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1554 /* On the HPPA, references to data space are supposed to use dp,
1555 register 27, but showing it in the RTL inhibits various cse
1556 and loop optimizations. */
1561 if (reload_in_progress || reload_completed)
1563 temp = scratch_reg ? scratch_reg : operand0;
1564 /* TEMP will hold an address and maybe the actual
1565 data. We want it in WORD_MODE regardless of what mode it
1566 was originally given to us. */
1567 temp = force_mode (word_mode, temp);
1570 temp = gen_reg_rtx (mode);
1572 /* Loading a SYMBOL_REF into a register makes that register
1573 safe to be used as the base in an indexed address.
1575 Don't mark hard registers though. That loses. */
1576 if (GET_CODE (operand0) == REG
1577 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1578 REG_POINTER (operand0) = 1;
1579 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1580 REG_POINTER (temp) = 1;
1582 set = gen_rtx_SET (mode, operand0, temp);
1584 set = gen_rtx_SET (VOIDmode,
1586 gen_rtx_LO_SUM (mode, temp, operand1));
1588 emit_insn (gen_rtx_SET (VOIDmode,
1590 gen_rtx_HIGH (mode, operand1)));
1596 else if (GET_CODE (operand1) != CONST_INT
1597 || ! cint_ok_for_move (INTVAL (operand1)))
1600 int need_zero_extend = 0;
1602 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1603 && HOST_BITS_PER_WIDE_INT > 32
1604 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1606 HOST_WIDE_INT val = INTVAL (operand1);
1609 /* If the value is the same after a 32->64bit sign
1610 extension, then we can use it as-is. Else we will
1611 need to sign extend the constant from 32->64bits
1612 then zero extend the result from 32->64bits. */
1613 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1614 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1617 need_zero_extend = 1;
1618 operand1 = GEN_INT (nval);
1622 if (reload_in_progress || reload_completed)
1625 temp = gen_reg_rtx (mode);
1627 emit_insn (gen_rtx_SET (VOIDmode, temp,
1628 gen_rtx_HIGH (mode, operand1)));
1629 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1630 emit_move_insn (operands[0], operands[1]);
1632 if (need_zero_extend)
1634 emit_insn (gen_zero_extendsidi2 (operands[0],
1635 gen_rtx_SUBREG (SImode,
1643 /* Now have insn-emit do whatever it normally does. */
1647 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1648 it will need a link/runtime reloc). */
1656 switch (TREE_CODE (exp))
1663 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1664 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1669 case NON_LVALUE_EXPR:
1670 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1676 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1677 if (TREE_VALUE (link) != 0)
1678 reloc |= reloc_needed (TREE_VALUE (link));
1691 /* Does operand (which is a symbolic_operand) live in text space? If
1692 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1695 read_only_operand (operand, mode)
1697 enum machine_mode mode ATTRIBUTE_UNUSED;
1699 if (GET_CODE (operand) == CONST)
1700 operand = XEXP (XEXP (operand, 0), 0);
1703 if (GET_CODE (operand) == SYMBOL_REF)
1704 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1708 if (GET_CODE (operand) == SYMBOL_REF)
1709 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1715 /* Return the best assembler insn template
1716 for moving operands[1] into operands[0] as a fullword. */
1718 singlemove_string (operands)
1721 HOST_WIDE_INT intval;
1723 if (GET_CODE (operands[0]) == MEM)
1724 return "stw %r1,%0";
1725 if (GET_CODE (operands[1]) == MEM)
1727 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1732 if (GET_MODE (operands[1]) != SFmode)
1735 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1737 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1738 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1740 operands[1] = GEN_INT (i);
1741 /* Fall through to CONST_INT case. */
1743 if (GET_CODE (operands[1]) == CONST_INT)
1745 intval = INTVAL (operands[1]);
1747 if (VAL_14_BITS_P (intval))
1749 else if ((intval & 0x7ff) == 0)
1750 return "ldil L'%1,%0";
1751 else if (zdepi_cint_p (intval))
1752 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1754 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1756 return "copy %1,%0";
1760 /* Compute position (in OP[1]) and width (in OP[2])
1761 useful for copying IMM to a register using the zdepi
1762 instructions. Store the immediate value to insert in OP[0]. */
1764 compute_zdepwi_operands (imm, op)
1765 unsigned HOST_WIDE_INT imm;
1770 /* Find the least significant set bit in IMM. */
1771 for (lsb = 0; lsb < 32; lsb++)
1778 /* Choose variants based on *sign* of the 5-bit field. */
1779 if ((imm & 0x10) == 0)
1780 len = (lsb <= 28) ? 4 : 32 - lsb;
1783 /* Find the width of the bitstring in IMM. */
1784 for (len = 5; len < 32; len++)
1786 if ((imm & (1 << len)) == 0)
1790 /* Sign extend IMM as a 5-bit value. */
1791 imm = (imm & 0xf) - 0x10;
1799 /* Compute position (in OP[1]) and width (in OP[2])
1800 useful for copying IMM to a register using the depdi,z
1801 instructions. Store the immediate value to insert in OP[0]. */
1803 compute_zdepdi_operands (imm, op)
1804 unsigned HOST_WIDE_INT imm;
1807 HOST_WIDE_INT lsb, len;
1809 /* Find the least significant set bit in IMM. */
1810 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1817 /* Choose variants based on *sign* of the 5-bit field. */
1818 if ((imm & 0x10) == 0)
1819 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1820 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1823 /* Find the width of the bitstring in IMM. */
1824 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1826 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
1830 /* Sign extend IMM as a 5-bit value. */
1831 imm = (imm & 0xf) - 0x10;
1839 /* Output assembler code to perform a doubleword move insn
1840 with operands OPERANDS. */
1843 output_move_double (operands)
1846 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1848 rtx addreg0 = 0, addreg1 = 0;
1850 /* First classify both operands. */
1852 if (REG_P (operands[0]))
1854 else if (offsettable_memref_p (operands[0]))
1856 else if (GET_CODE (operands[0]) == MEM)
1861 if (REG_P (operands[1]))
1863 else if (CONSTANT_P (operands[1]))
1865 else if (offsettable_memref_p (operands[1]))
1867 else if (GET_CODE (operands[1]) == MEM)
1872 /* Check for the cases that the operand constraints are not
1873 supposed to allow to happen. Abort if we get one,
1874 because generating code for these cases is painful. */
1876 if (optype0 != REGOP && optype1 != REGOP)
1879 /* Handle auto decrementing and incrementing loads and stores
1880 specifically, since the structure of the function doesn't work
1881 for them without major modification. Do it better when we learn
1882 this port about the general inc/dec addressing of PA.
1883 (This was written by tege. Chide him if it doesn't work.) */
1885 if (optype0 == MEMOP)
1887 /* We have to output the address syntax ourselves, since print_operand
1888 doesn't deal with the addresses we want to use. Fix this later. */
1890 rtx addr = XEXP (operands[0], 0);
1891 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1893 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1895 operands[0] = XEXP (addr, 0);
1896 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1899 if (!reg_overlap_mentioned_p (high_reg, addr))
1901 /* No overlap between high target register and address
1902 register. (We do this in a non-obvious way to
1903 save a register file writeback) */
1904 if (GET_CODE (addr) == POST_INC)
1905 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
1906 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
1911 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1913 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1915 operands[0] = XEXP (addr, 0);
1916 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1919 if (!reg_overlap_mentioned_p (high_reg, addr))
1921 /* No overlap between high target register and address
1922 register. (We do this in a non-obvious way to
1923 save a register file writeback) */
1924 if (GET_CODE (addr) == PRE_INC)
1925 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
1926 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
1932 if (optype1 == MEMOP)
1934 /* We have to output the address syntax ourselves, since print_operand
1935 doesn't deal with the addresses we want to use. Fix this later. */
1937 rtx addr = XEXP (operands[1], 0);
1938 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1940 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1942 operands[1] = XEXP (addr, 0);
1943 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1946 if (!reg_overlap_mentioned_p (high_reg, addr))
1948 /* No overlap between high target register and address
1949 register. (We do this in a non-obvious way to
1950 save a register file writeback) */
1951 if (GET_CODE (addr) == POST_INC)
1952 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
1953 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0}";
1957 /* This is an undefined situation. We should load into the
1958 address register *and* update that register. Probably
1959 we don't need to handle this at all. */
1960 if (GET_CODE (addr) == POST_INC)
1961 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
1962 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
1965 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1967 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1969 operands[1] = XEXP (addr, 0);
1970 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1973 if (!reg_overlap_mentioned_p (high_reg, addr))
1975 /* No overlap between high target register and address
1976 register. (We do this in a non-obvious way to
1977 save a register file writeback) */
1978 if (GET_CODE (addr) == PRE_INC)
1979 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
1980 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
1984 /* This is an undefined situation. We should load into the
1985 address register *and* update that register. Probably
1986 we don't need to handle this at all. */
1987 if (GET_CODE (addr) == PRE_INC)
1988 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
1989 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
1992 else if (GET_CODE (addr) == PLUS
1993 && GET_CODE (XEXP (addr, 0)) == MULT)
1995 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1997 if (!reg_overlap_mentioned_p (high_reg, addr))
2001 xoperands[0] = high_reg;
2002 xoperands[1] = XEXP (addr, 1);
2003 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2004 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2005 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2007 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2013 xoperands[0] = high_reg;
2014 xoperands[1] = XEXP (addr, 1);
2015 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2016 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2017 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2019 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2024 /* If an operand is an unoffsettable memory ref, find a register
2025 we can increment temporarily to make it refer to the second word. */
2027 if (optype0 == MEMOP)
2028 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2030 if (optype1 == MEMOP)
2031 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2033 /* Ok, we can do one word at a time.
2034 Normally we do the low-numbered word first.
2036 In either case, set up in LATEHALF the operands to use
2037 for the high-numbered word and in some cases alter the
2038 operands in OPERANDS to be suitable for the low-numbered word. */
2040 if (optype0 == REGOP)
2041 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2042 else if (optype0 == OFFSOP)
2043 latehalf[0] = adjust_address (operands[0], SImode, 4);
2045 latehalf[0] = operands[0];
2047 if (optype1 == REGOP)
2048 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2049 else if (optype1 == OFFSOP)
2050 latehalf[1] = adjust_address (operands[1], SImode, 4);
2051 else if (optype1 == CNSTOP)
2052 split_double (operands[1], &operands[1], &latehalf[1]);
2054 latehalf[1] = operands[1];
2056 /* If the first move would clobber the source of the second one,
2057 do them in the other order.
2059 This can happen in two cases:
2061 mem -> register where the first half of the destination register
2062 is the same register used in the memory's address. Reload
2063 can create such insns.
2065 mem in this case will be either register indirect or register
2066 indirect plus a valid offset.
2068 register -> register move where REGNO(dst) == REGNO(src + 1)
2069 someone (Tim/Tege?) claimed this can happen for parameter loads.
2071 Handle mem -> register case first. */
2072 if (optype0 == REGOP
2073 && (optype1 == MEMOP || optype1 == OFFSOP)
2074 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2077 /* Do the late half first. */
2079 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2080 output_asm_insn (singlemove_string (latehalf), latehalf);
2084 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2085 return singlemove_string (operands);
2088 /* Now handle register -> register case. */
2089 if (optype0 == REGOP && optype1 == REGOP
2090 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2092 output_asm_insn (singlemove_string (latehalf), latehalf);
2093 return singlemove_string (operands);
2096 /* Normal case: do the two words, low-numbered first. */
2098 output_asm_insn (singlemove_string (operands), operands);
2100 /* Make any unoffsettable addresses point at high-numbered word. */
2102 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2104 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2107 output_asm_insn (singlemove_string (latehalf), latehalf);
2109 /* Undo the adds we just did. */
2111 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2113 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2119 output_fp_move_double (operands)
2122 if (FP_REG_P (operands[0]))
2124 if (FP_REG_P (operands[1])
2125 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2126 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2128 output_asm_insn ("fldd%F1 %1,%0", operands);
2130 else if (FP_REG_P (operands[1]))
2132 output_asm_insn ("fstd%F0 %1,%0", operands);
2134 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2136 if (GET_CODE (operands[0]) == REG)
2139 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2140 xoperands[0] = operands[0];
2141 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2143 /* This is a pain. You have to be prepared to deal with an
2144 arbitrary address here including pre/post increment/decrement.
2146 so avoid this in the MD. */
2154 /* Return a REG that occurs in ADDR with coefficient 1.
2155 ADDR can be effectively incremented by incrementing REG. */
2158 find_addr_reg (addr)
2161 while (GET_CODE (addr) == PLUS)
2163 if (GET_CODE (XEXP (addr, 0)) == REG)
2164 addr = XEXP (addr, 0);
2165 else if (GET_CODE (XEXP (addr, 1)) == REG)
2166 addr = XEXP (addr, 1);
2167 else if (CONSTANT_P (XEXP (addr, 0)))
2168 addr = XEXP (addr, 1);
2169 else if (CONSTANT_P (XEXP (addr, 1)))
2170 addr = XEXP (addr, 0);
2174 if (GET_CODE (addr) == REG)
2179 /* Emit code to perform a block move.
2181 OPERANDS[0] is the destination pointer as a REG, clobbered.
2182 OPERANDS[1] is the source pointer as a REG, clobbered.
2183 OPERANDS[2] is a register for temporary storage.
2184 OPERANDS[4] is the size as a CONST_INT
2185 OPERANDS[3] is a register for temporary storage.
2186 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2187 OPERANDS[6] is another temporary register. */
2190 output_block_move (operands, size_is_constant)
2192 int size_is_constant ATTRIBUTE_UNUSED;
2194 int align = INTVAL (operands[5]);
2195 unsigned long n_bytes = INTVAL (operands[4]);
2197 /* We can't move more than four bytes at a time because the PA
2198 has no longer integer move insns. (Could use fp mem ops?) */
2202 /* Note that we know each loop below will execute at least twice
2203 (else we would have open-coded the copy). */
2207 /* Pre-adjust the loop counter. */
2208 operands[4] = GEN_INT (n_bytes - 8);
2209 output_asm_insn ("ldi %4,%2", operands);
2212 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2213 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2214 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2215 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2216 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2218 /* Handle the residual. There could be up to 7 bytes of
2219 residual to copy! */
2220 if (n_bytes % 8 != 0)
2222 operands[4] = GEN_INT (n_bytes % 4);
2223 if (n_bytes % 8 >= 4)
2224 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2225 if (n_bytes % 4 != 0)
2226 output_asm_insn ("ldw 0(%1),%6", operands);
2227 if (n_bytes % 8 >= 4)
2228 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2229 if (n_bytes % 4 != 0)
2230 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2235 /* Pre-adjust the loop counter. */
2236 operands[4] = GEN_INT (n_bytes - 4);
2237 output_asm_insn ("ldi %4,%2", operands);
2240 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2241 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2242 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2243 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2244 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2246 /* Handle the residual. */
2247 if (n_bytes % 4 != 0)
2249 if (n_bytes % 4 >= 2)
2250 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2251 if (n_bytes % 2 != 0)
2252 output_asm_insn ("ldb 0(%1),%6", operands);
2253 if (n_bytes % 4 >= 2)
2254 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2255 if (n_bytes % 2 != 0)
2256 output_asm_insn ("stb %6,0(%0)", operands);
2261 /* Pre-adjust the loop counter. */
2262 operands[4] = GEN_INT (n_bytes - 2);
2263 output_asm_insn ("ldi %4,%2", operands);
2266 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2267 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2268 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2269 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2270 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2272 /* Handle the residual. */
2273 if (n_bytes % 2 != 0)
2275 output_asm_insn ("ldb 0(%1),%3", operands);
2276 output_asm_insn ("stb %3,0(%0)", operands);
2285 /* Count the number of insns necessary to handle this block move.
2287 Basic structure is the same as emit_block_move, except that we
2288 count insns rather than emit them. */
2291 compute_movstrsi_length (insn)
2294 rtx pat = PATTERN (insn);
2295 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2296 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
2297 unsigned int n_insns = 0;
2299 /* We can't move more than four bytes at a time because the PA
2300 has no longer integer move insns. (Could use fp mem ops?) */
2304 /* The basic copying loop. */
2308 if (n_bytes % (2 * align) != 0)
2310 if ((n_bytes % (2 * align)) >= align)
2313 if ((n_bytes % align) != 0)
2317 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2323 output_and (operands)
2326 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2328 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2329 int ls0, ls1, ms0, p, len;
2331 for (ls0 = 0; ls0 < 32; ls0++)
2332 if ((mask & (1 << ls0)) == 0)
2335 for (ls1 = ls0; ls1 < 32; ls1++)
2336 if ((mask & (1 << ls1)) != 0)
2339 for (ms0 = ls1; ms0 < 32; ms0++)
2340 if ((mask & (1 << ms0)) == 0)
2353 operands[2] = GEN_INT (len);
2354 return "{extru|extrw,u} %1,31,%2,%0";
2358 /* We could use this `depi' for the case above as well, but `depi'
2359 requires one more register file access than an `extru'. */
2364 operands[2] = GEN_INT (p);
2365 operands[3] = GEN_INT (len);
2366 return "{depi|depwi} 0,%2,%3,%0";
2370 return "and %1,%2,%0";
2373 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2374 storing the result in operands[0]. */
2376 output_64bit_and (operands)
2379 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2381 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2382 int ls0, ls1, ms0, p, len;
2384 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2385 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2388 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2389 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2392 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2393 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2396 if (ms0 != HOST_BITS_PER_WIDE_INT)
2399 if (ls1 == HOST_BITS_PER_WIDE_INT)
2406 operands[2] = GEN_INT (len);
2407 return "extrd,u %1,63,%2,%0";
2411 /* We could use this `depi' for the case above as well, but `depi'
2412 requires one more register file access than an `extru'. */
2417 operands[2] = GEN_INT (p);
2418 operands[3] = GEN_INT (len);
2419 return "depdi 0,%2,%3,%0";
2423 return "and %1,%2,%0";
2427 output_ior (operands)
2430 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2431 int bs0, bs1, p, len;
2433 if (INTVAL (operands[2]) == 0)
2434 return "copy %1,%0";
2436 for (bs0 = 0; bs0 < 32; bs0++)
2437 if ((mask & (1 << bs0)) != 0)
2440 for (bs1 = bs0; bs1 < 32; bs1++)
2441 if ((mask & (1 << bs1)) == 0)
2444 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2450 operands[2] = GEN_INT (p);
2451 operands[3] = GEN_INT (len);
2452 return "{depi|depwi} -1,%2,%3,%0";
2455 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2456 storing the result in operands[0]. */
2458 output_64bit_ior (operands)
2461 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2462 int bs0, bs1, p, len;
2464 if (INTVAL (operands[2]) == 0)
2465 return "copy %1,%0";
2467 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2468 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2471 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2472 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2475 if (bs1 != HOST_BITS_PER_WIDE_INT
2476 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2482 operands[2] = GEN_INT (p);
2483 operands[3] = GEN_INT (len);
2484 return "depdi -1,%2,%3,%0";
2487 /* Output an ascii string. */
2489 output_ascii (file, p, size)
2491 const unsigned char *p;
2496 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2498 /* The HP assembler can only take strings of 256 characters at one
2499 time. This is a limitation on input line length, *not* the
2500 length of the string. Sigh. Even worse, it seems that the
2501 restriction is in number of input characters (see \xnn &
2502 \whatever). So we have to do this very carefully. */
2504 fputs ("\t.STRING \"", file);
2507 for (i = 0; i < size; i += 4)
2511 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2513 register unsigned int c = p[i + io];
2515 if (c == '\"' || c == '\\')
2516 partial_output[co++] = '\\';
2517 if (c >= ' ' && c < 0177)
2518 partial_output[co++] = c;
2522 partial_output[co++] = '\\';
2523 partial_output[co++] = 'x';
2524 hexd = c / 16 - 0 + '0';
2526 hexd -= '9' - 'a' + 1;
2527 partial_output[co++] = hexd;
2528 hexd = c % 16 - 0 + '0';
2530 hexd -= '9' - 'a' + 1;
2531 partial_output[co++] = hexd;
2534 if (chars_output + co > 243)
2536 fputs ("\"\n\t.STRING \"", file);
2539 fwrite (partial_output, 1, co, file);
2543 fputs ("\"\n", file);
2546 /* Try to rewrite floating point comparisons & branches to avoid
2547 useless add,tr insns.
2549 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2550 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2551 first attempt to remove useless add,tr insns. It is zero
2552 for the second pass as reorg sometimes leaves bogus REG_DEAD
2555 When CHECK_NOTES is zero we can only eliminate add,tr insns
2556 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2559 remove_useless_addtr_insns (insns, check_notes)
2564 static int pass = 0;
2566 /* This is fairly cheap, so always run it when optimizing. */
2570 int fbranch_count = 0;
2572 /* Walk all the insns in this function looking for fcmp & fbranch
2573 instructions. Keep track of how many of each we find. */
2574 insns = get_insns ();
2575 for (insn = insns; insn; insn = next_insn (insn))
2579 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2580 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2583 tmp = PATTERN (insn);
2585 /* It must be a set. */
2586 if (GET_CODE (tmp) != SET)
2589 /* If the destination is CCFP, then we've found an fcmp insn. */
2590 tmp = SET_DEST (tmp);
2591 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2597 tmp = PATTERN (insn);
2598 /* If this is an fbranch instruction, bump the fbranch counter. */
2599 if (GET_CODE (tmp) == SET
2600 && SET_DEST (tmp) == pc_rtx
2601 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2602 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2603 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2604 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2612 /* Find all floating point compare + branch insns. If possible,
2613 reverse the comparison & the branch to avoid add,tr insns. */
2614 for (insn = insns; insn; insn = next_insn (insn))
2618 /* Ignore anything that isn't an INSN. */
2619 if (GET_CODE (insn) != INSN)
2622 tmp = PATTERN (insn);
2624 /* It must be a set. */
2625 if (GET_CODE (tmp) != SET)
2628 /* The destination must be CCFP, which is register zero. */
2629 tmp = SET_DEST (tmp);
2630 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2633 /* INSN should be a set of CCFP.
2635 See if the result of this insn is used in a reversed FP
2636 conditional branch. If so, reverse our condition and
2637 the branch. Doing so avoids useless add,tr insns. */
2638 next = next_insn (insn);
2641 /* Jumps, calls and labels stop our search. */
2642 if (GET_CODE (next) == JUMP_INSN
2643 || GET_CODE (next) == CALL_INSN
2644 || GET_CODE (next) == CODE_LABEL)
2647 /* As does another fcmp insn. */
2648 if (GET_CODE (next) == INSN
2649 && GET_CODE (PATTERN (next)) == SET
2650 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2651 && REGNO (SET_DEST (PATTERN (next))) == 0)
2654 next = next_insn (next);
2657 /* Is NEXT_INSN a branch? */
2659 && GET_CODE (next) == JUMP_INSN)
2661 rtx pattern = PATTERN (next);
2663 /* If it a reversed fp conditional branch (eg uses add,tr)
2664 and CCFP dies, then reverse our conditional and the branch
2665 to avoid the add,tr. */
2666 if (GET_CODE (pattern) == SET
2667 && SET_DEST (pattern) == pc_rtx
2668 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2669 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2670 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2671 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2672 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2673 && (fcmp_count == fbranch_count
2675 && find_regno_note (next, REG_DEAD, 0))))
2677 /* Reverse the branch. */
2678 tmp = XEXP (SET_SRC (pattern), 1);
2679 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2680 XEXP (SET_SRC (pattern), 2) = tmp;
2681 INSN_CODE (next) = -1;
2683 /* Reverse our condition. */
2684 tmp = PATTERN (insn);
2685 PUT_CODE (XEXP (tmp, 1),
2686 (reverse_condition_maybe_unordered
2687 (GET_CODE (XEXP (tmp, 1)))));
2697 /* You may have trouble believing this, but this is the 32 bit HP-PA
2702 Variable arguments (optional; any number may be allocated)
2704 SP-(4*(N+9)) arg word N
2709 Fixed arguments (must be allocated; may remain unused)
2718 SP-32 External Data Pointer (DP)
2720 SP-24 External/stub RP (RP')
2724 SP-8 Calling Stub RP (RP'')
2729 SP-0 Stack Pointer (points to next available address)
2733 /* This function saves registers as follows. Registers marked with ' are
2734 this function's registers (as opposed to the previous function's).
2735 If a frame_pointer isn't needed, r4 is saved as a general register;
2736 the space for the frame pointer is still allocated, though, to keep
2742 SP (FP') Previous FP
2743 SP + 4 Alignment filler (sigh)
2744 SP + 8 Space for locals reserved here.
2748 SP + n All call saved register used.
2752 SP + o All call saved fp registers used.
2756 SP + p (SP') points to next available address.
2760 /* Global variables set by output_function_prologue(). */
2761 /* Size of frame. Need to know this to emit return insns from
2763 static int actual_fsize;
2764 static int local_fsize, save_fregs;
2766 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2767 Handle case where DISP > 8k by using the add_high_const patterns.
2769 Note in DISP > 8k case, we will leave the high part of the address
2770 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2773 store_reg (reg, disp, base)
2774 int reg, disp, base;
2776 rtx i, dest, src, basereg;
2778 src = gen_rtx_REG (word_mode, reg);
2779 basereg = gen_rtx_REG (Pmode, base);
2780 if (VAL_14_BITS_P (disp))
2782 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2783 i = emit_move_insn (dest, src);
2787 rtx delta = GEN_INT (disp);
2788 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
2789 rtx tmpreg = gen_rtx_REG (Pmode, 1);
2790 emit_move_insn (tmpreg, high);
2791 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
2792 i = emit_move_insn (dest, src);
2797 /* Emit RTL to set REG to the value specified by BASE+DISP.
2798 Handle case where DISP > 8k by using the add_high_const patterns.
2800 Note in DISP > 8k case, we will leave the high part of the address
2801 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2804 set_reg_plus_d (reg, base, disp)
2805 int reg, base, disp;
2809 if (VAL_14_BITS_P (disp))
2811 i = emit_move_insn (gen_rtx_REG (Pmode, reg),
2812 plus_constant (gen_rtx_REG (Pmode, base), disp));
2816 rtx delta = GEN_INT (disp);
2817 emit_move_insn (gen_rtx_REG (Pmode, 1),
2818 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, base),
2819 gen_rtx_HIGH (Pmode, delta)));
2820 i = emit_move_insn (gen_rtx_REG (Pmode, reg),
2821 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
2828 compute_frame_size (size, fregs_live)
2834 /* Space for frame pointer + filler. If any frame is allocated
2835 we need to add this in because of STARTING_FRAME_OFFSET.
2837 Similar code also appears in hppa_expand_prologue. Change both
2838 of them at the same time. */
2839 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
2841 /* Account for space used by the callee general register saves. */
2842 for (i = 18; i >= 3; i--)
2843 if (regs_ever_live[i])
2844 fsize += UNITS_PER_WORD;
2846 /* Round the stack. */
2847 fsize = (fsize + 7) & ~7;
2849 /* Account for space used by the callee floating point register saves. */
2850 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
2851 if (regs_ever_live[i]
2852 || (! TARGET_64BIT && regs_ever_live[i + 1]))
2857 /* We always save both halves of the FP register, so always
2858 increment the frame size by 8 bytes. */
2862 /* The various ABIs include space for the outgoing parameters in the
2863 size of the current function's stack frame. */
2864 fsize += current_function_outgoing_args_size;
2866 /* Allocate space for the fixed frame marker. This space must be
2867 allocated for any function that makes calls or otherwise allocates
2869 if (!current_function_is_leaf || fsize)
2870 fsize += TARGET_64BIT ? 16 : 32;
2872 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
2875 /* Generate the assembly code for function entry. FILE is a stdio
2876 stream to output the code to. SIZE is an int: how many units of
2877 temporary storage to allocate.
2879 Refer to the array `regs_ever_live' to determine which registers to
2880 save; `regs_ever_live[I]' is nonzero if register number I is ever
2881 used in the function. This function is responsible for knowing
2882 which registers should not be saved even if used. */
2884 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
2885 of memory. If any fpu reg is used in the function, we allocate
2886 such a block here, at the bottom of the frame, just in case it's needed.
2888 If this function is a leaf procedure, then we may choose not
2889 to do a "save" insn. The decision about whether or not
2890 to do this is made in regclass.c. */
2893 pa_output_function_prologue (file, size)
2895 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2897 /* The function's label and associated .PROC must never be
2898 separated and must be output *after* any profiling declarations
2899 to avoid changing spaces/subspaces within a procedure. */
2900 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
2901 fputs ("\t.PROC\n", file);
2903 /* hppa_expand_prologue does the dirty work now. We just need
2904 to output the assembler directives which denote the start
2906 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
2907 if (regs_ever_live[2])
2908 fputs (",CALLS,SAVE_RP", file);
2910 fputs (",NO_CALLS", file);
2912 if (frame_pointer_needed)
2913 fputs (",SAVE_SP", file);
2915 /* Pass on information about the number of callee register saves
2916 performed in the prologue.
2918 The compiler is supposed to pass the highest register number
2919 saved, the assembler then has to adjust that number before
2920 entering it into the unwind descriptor (to account for any
2921 caller saved registers with lower register numbers than the
2922 first callee saved register). */
2924 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
2927 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
2929 fputs ("\n\t.ENTRY\n", file);
2931 /* If we're using GAS and not using the portable runtime model, then
2932 we don't need to accumulate the total number of code bytes. */
2933 if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
2934 total_code_bytes = 0;
2935 else if (INSN_ADDRESSES_SET_P ())
2937 unsigned int old_total = total_code_bytes;
2939 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_insn ()));
2940 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
2942 /* Be prepared to handle overflows. */
2943 if (old_total > total_code_bytes)
2944 total_code_bytes = -1;
2947 total_code_bytes = -1;
2949 remove_useless_addtr_insns (get_insns (), 0);
2957 RTX_FRAME_RELATED_P (insn) = 1; \
2961 #define FRP(INSN) INSN
2965 hppa_expand_prologue ()
2967 extern char call_used_regs[];
2968 int size = get_frame_size ();
2969 int merge_sp_adjust_with_store = 0;
2971 rtx tmpreg, size_rtx;
2977 /* Allocate space for frame pointer + filler. If any frame is allocated
2978 we need to add this in because of STARTING_FRAME_OFFSET.
2980 Similar code also appears in compute_frame_size. Change both
2981 of them at the same time. */
2982 local_fsize = size + (size || frame_pointer_needed
2983 ? STARTING_FRAME_OFFSET : 0);
2985 actual_fsize = compute_frame_size (size, &save_fregs);
2987 /* Compute a few things we will use often. */
2988 tmpreg = gen_rtx_REG (word_mode, 1);
2989 size_rtx = GEN_INT (actual_fsize);
2991 /* Save RP first. The calling conventions manual states RP will
2992 always be stored into the caller's frame at sp - 20 or sp - 16
2993 depending on which ABI is in use. */
2994 if (regs_ever_live[2])
2995 FRP (store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM));
2997 /* Allocate the local frame and set up the frame pointer if needed. */
2998 if (actual_fsize != 0)
3000 if (frame_pointer_needed)
3002 /* Copy the old frame pointer temporarily into %r1. Set up the
3003 new stack pointer, then store away the saved old frame pointer
3004 into the stack at sp+actual_fsize and at the same time update
3005 the stack pointer by actual_fsize bytes. Two versions, first
3006 handles small (<8k) frames. The second handles large (>=8k)
3008 emit_move_insn (tmpreg, frame_pointer_rtx);
3009 FRP (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx));
3010 if (VAL_14_BITS_P (actual_fsize))
3012 rtx insn = emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
3017 RTX_FRAME_RELATED_P (insn) = 1;
3019 gen_rtx_SET (VOIDmode,
3020 gen_rtx_MEM (word_mode,
3023 gen_rtx_SET (VOIDmode,
3025 gen_rtx_PLUS (word_mode,
3029 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3030 gen_rtx_SEQUENCE (VOIDmode, vec),
3036 /* It is incorrect to store the saved frame pointer at *sp,
3037 then increment sp (writes beyond the current stack boundary).
3039 So instead use stwm to store at *sp and post-increment the
3040 stack pointer as an atomic operation. Then increment sp to
3041 finish allocating the new frame. */
3042 int adjust1 = 8192 - 64;
3043 int adjust2 = actual_fsize - adjust1;
3044 rtx delta = GEN_INT (adjust1);
3045 rtx insn = emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
3050 RTX_FRAME_RELATED_P (insn) = 1;
3052 gen_rtx_SET (VOIDmode,
3053 gen_rtx_MEM (word_mode,
3056 gen_rtx_SET (VOIDmode,
3058 gen_rtx_PLUS (word_mode,
3062 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3063 gen_rtx_SEQUENCE (VOIDmode, vec),
3067 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3068 STACK_POINTER_REGNUM,
3071 /* Prevent register spills from being scheduled before the
3072 stack pointer is raised. Necessary as we will be storing
3073 registers using the frame pointer as a base register, and
3074 we happen to set fp before raising sp. */
3075 emit_insn (gen_blockage ());
3077 /* no frame pointer needed. */
3080 /* In some cases we can perform the first callee register save
3081 and allocating the stack frame at the same time. If so, just
3082 make a note of it and defer allocating the frame until saving
3083 the callee registers. */
3084 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3085 merge_sp_adjust_with_store = 1;
3086 /* Can not optimize. Adjust the stack frame by actual_fsize
3089 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3090 STACK_POINTER_REGNUM,
3095 /* Normal register save.
3097 Do not save the frame pointer in the frame_pointer_needed case. It
3098 was done earlier. */
3099 if (frame_pointer_needed)
3101 for (i = 18, offset = local_fsize; i >= 4; i--)
3102 if (regs_ever_live[i] && ! call_used_regs[i])
3104 FRP (store_reg (i, offset, FRAME_POINTER_REGNUM));
3105 offset += UNITS_PER_WORD;
3108 /* Account for %r3 which is saved in a special place. */
3111 /* No frame pointer needed. */
3114 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3115 if (regs_ever_live[i] && ! call_used_regs[i])
3117 /* If merge_sp_adjust_with_store is nonzero, then we can
3118 optimize the first GR save. */
3119 if (merge_sp_adjust_with_store)
3121 rtx delta = GEN_INT (-offset);
3122 merge_sp_adjust_with_store = 0;
3123 FRP (emit_insn (gen_post_store (stack_pointer_rtx,
3124 gen_rtx_REG (word_mode, i),
3128 FRP (store_reg (i, offset, STACK_POINTER_REGNUM));
3129 offset += UNITS_PER_WORD;
3133 /* If we wanted to merge the SP adjustment with a GR save, but we never
3134 did any GR saves, then just emit the adjustment here. */
3135 if (merge_sp_adjust_with_store)
3136 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3137 STACK_POINTER_REGNUM,
3141 /* The hppa calling conventions say that %r19, the pic offset
3142 register, is saved at sp - 32 (in this function's frame)
3143 when generating PIC code. FIXME: What is the correct thing
3144 to do for functions which make no calls and allocate no
3145 frame? Do we need to allocate a frame, or can we just omit
3146 the save? For now we'll just omit the save. */
3147 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3148 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3150 /* Align pointer properly (doubleword boundary). */
3151 offset = (offset + 7) & ~7;
3153 /* Floating point register store. */
3156 /* First get the frame or stack pointer to the start of the FP register
3158 if (frame_pointer_needed)
3159 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset));
3161 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM, offset));
3163 /* Now actually save the FP registers. */
3164 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3166 if (regs_ever_live[i]
3167 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3170 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3171 reg = gen_rtx_REG (DFmode, i);
3172 FRP (emit_move_insn (addr, reg));
3179 /* ?!? Do we want frame notes in the epilogue yet? */
3180 #undef DO_FRAME_NOTES
3181 #define DO_FRAME_NOTES 0
3183 #define FRP(INSN) INSN
3185 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3186 Handle case where DISP > 8k by using the add_high_const patterns. */
3189 load_reg (reg, disp, base)
3190 int reg, disp, base;
3192 rtx i, src, dest, basereg;
3194 dest = gen_rtx_REG (word_mode, reg);
3195 basereg = gen_rtx_REG (Pmode, base);
3196 if (VAL_14_BITS_P (disp))
3198 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3199 i = emit_move_insn (dest, src);
3203 rtx delta = GEN_INT (disp);
3204 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3205 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3206 emit_move_insn (tmpreg, high);
3207 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3208 i = emit_move_insn (dest, src);
3213 /* This function generates the assembly code for function exit.
3214 Args are as for output_function_prologue ().
3216 The function epilogue should not depend on the current stack
3217 pointer! It should use the frame pointer only. This is mandatory
3218 because of alloca; we also take advantage of it to omit stack
3219 adjustments before returning. */
3222 pa_output_function_epilogue (file, size)
3224 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3226 rtx insn = get_last_insn ();
3228 /* hppa_expand_epilogue does the dirty work now. We just need
3229 to output the assembler directives which denote the end
3232 To make debuggers happy, emit a nop if the epilogue was completely
3233 eliminated due to a volatile call as the last insn in the
3234 current function. That way the return address (in %r2) will
3235 always point to a valid instruction in the current function. */
3237 /* Get the last real insn. */
3238 if (GET_CODE (insn) == NOTE)
3239 insn = prev_real_insn (insn);
3241 /* If it is a sequence, then look inside. */
3242 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3243 insn = XVECEXP (PATTERN (insn), 0, 0);
3245 /* If insn is a CALL_INSN, then it must be a call to a volatile
3246 function (otherwise there would be epilogue insns). */
3247 if (insn && GET_CODE (insn) == CALL_INSN)
3248 fputs ("\tnop\n", file);
3250 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3254 hppa_expand_epilogue ()
3258 int merge_sp_adjust_with_load = 0;
3261 /* We will use this often. */
3262 tmpreg = gen_rtx_REG (word_mode, 1);
3264 /* Try to restore RP early to avoid load/use interlocks when
3265 RP gets used in the return (bv) instruction. This appears to still
3266 be necessary even when we schedule the prologue and epilogue. */
3267 if (regs_ever_live [2])
3269 ret_off = TARGET_64BIT ? -16 : -20;
3270 if (frame_pointer_needed)
3272 FRP (load_reg (2, ret_off, FRAME_POINTER_REGNUM));
3277 /* No frame pointer, and stack is smaller than 8k. */
3278 if (VAL_14_BITS_P (ret_off - actual_fsize))
3280 FRP (load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM));
3286 /* General register restores. */
3287 if (frame_pointer_needed)
3289 for (i = 18, offset = local_fsize; i >= 4; i--)
3290 if (regs_ever_live[i] && ! call_used_regs[i])
3292 FRP (load_reg (i, offset, FRAME_POINTER_REGNUM));
3293 offset += UNITS_PER_WORD;
3298 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3300 if (regs_ever_live[i] && ! call_used_regs[i])
3302 /* Only for the first load.
3303 merge_sp_adjust_with_load holds the register load
3304 with which we will merge the sp adjustment. */
3305 if (merge_sp_adjust_with_load == 0
3307 && VAL_14_BITS_P (-actual_fsize))
3308 merge_sp_adjust_with_load = i;
3310 FRP (load_reg (i, offset, STACK_POINTER_REGNUM));
3311 offset += UNITS_PER_WORD;
3316 /* Align pointer properly (doubleword boundary). */
3317 offset = (offset + 7) & ~7;
3319 /* FP register restores. */
3322 /* Adjust the register to index off of. */
3323 if (frame_pointer_needed)
3324 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset));
3326 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM, offset));
3328 /* Actually do the restores now. */
3329 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3330 if (regs_ever_live[i]
3331 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3333 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3334 rtx dest = gen_rtx_REG (DFmode, i);
3335 FRP (emit_move_insn (dest, src));
3339 /* Emit a blockage insn here to keep these insns from being moved to
3340 an earlier spot in the epilogue, or into the main instruction stream.
3342 This is necessary as we must not cut the stack back before all the
3343 restores are finished. */
3344 emit_insn (gen_blockage ());
3346 /* Reset stack pointer (and possibly frame pointer). The stack
3347 pointer is initially set to fp + 64 to avoid a race condition. */
3348 if (frame_pointer_needed)
3350 rtx delta = GEN_INT (-64);
3351 FRP (set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64));
3352 FRP (emit_insn (gen_pre_load (frame_pointer_rtx,
3356 /* If we were deferring a callee register restore, do it now. */
3357 else if (merge_sp_adjust_with_load)
3359 rtx delta = GEN_INT (-actual_fsize);
3360 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3361 FRP (emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)));
3363 else if (actual_fsize != 0)
3364 FRP (set_reg_plus_d (STACK_POINTER_REGNUM,
3365 STACK_POINTER_REGNUM,
3368 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3369 frame greater than 8k), do so now. */
3371 FRP (load_reg (2, ret_off, STACK_POINTER_REGNUM));
3375 hppa_pic_save_rtx ()
3377 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3381 hppa_profile_hook (label_no)
3382 int label_no ATTRIBUTE_UNUSED;
3386 /* No profiling for inline functions. We don't want extra calls to
3387 _mcount when the inline function is expanded. Even if that made
3388 sense, it wouldn't work here as there is no function label for
3389 the inline expansion. */
3390 if (DECL_INLINE (cfun->decl))
3394 emit_move_insn (arg_pointer_rtx,
3395 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3398 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3400 #ifndef NO_PROFILE_COUNTERS
3402 rtx count_label_rtx, addr, r24;
3403 char label_name[16];
3405 ASM_GENERATE_INTERNAL_LABEL (label_name, "LP", label_no);
3406 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (label_name));
3412 current_function_uses_pic_offset_table = 1;
3413 tmpreg = gen_rtx_REG (Pmode, 1);
3414 emit_move_insn (tmpreg,
3415 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3416 gen_rtx_HIGH (Pmode, count_label_rtx)));
3417 addr = gen_rtx_MEM (Pmode,
3418 gen_rtx_LO_SUM (Pmode, tmpreg, count_label_rtx));
3422 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3423 emit_move_insn (tmpreg, gen_rtx_HIGH (Pmode, count_label_rtx));
3424 addr = gen_rtx_LO_SUM (Pmode, tmpreg, count_label_rtx);
3426 r24 = gen_rtx_REG (Pmode, 24);
3427 emit_move_insn (r24, addr);
3429 /* %r25 is set from within the output pattern. */
3431 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3432 GEN_INT (TARGET_64BIT ? 24 : 12),
3433 XEXP (DECL_RTL (cfun->decl), 0)));
3435 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3438 /* %r25 is set from within the output pattern. */
3440 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3441 GEN_INT (TARGET_64BIT ? 16 : 8),
3442 XEXP (DECL_RTL (cfun->decl), 0)));
3445 /* Indicate the _mcount call cannot throw, nor will it execute a
3447 REG_NOTES (call_insn)
3448 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3452 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3454 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3456 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3460 /* Fetch the return address for the frame COUNT steps up from
3461 the current frame, after the prologue. FRAMEADDR is the
3462 frame pointer of the COUNT frame.
3464 We want to ignore any export stub remnants here.
3466 The value returned is used in two different ways:
3468 1. To find a function's caller.
3470 2. To change the return address for a function.
3472 This function handles most instances of case 1; however, it will
3473 fail if there are two levels of stubs to execute on the return
3474 path. The only way I believe that can happen is if the return value
3475 needs a parameter relocation, which never happens for C code.
3477 This function handles most instances of case 2; however, it will
3478 fail if we did not originally have stub code on the return path
3479 but will need code on the new return path. This can happen if
3480 the caller & callee are both in the main program, but the new
3481 return location is in a shared library.
3483 To handle this correctly we need to set the return pointer at
3484 frame-20 to point to a return stub frame-24 to point to the
3485 location we wish to return to. */
3488 return_addr_rtx (count, frameaddr)
3489 int count ATTRIBUTE_UNUSED;
3497 return gen_rtx_MEM (Pmode, plus_constant (frameaddr, -16));
3499 if (TARGET_NO_SPACE_REGS)
3500 return gen_rtx_MEM (Pmode, plus_constant (frameaddr, -20));
3502 /* First, we start off with the normal return address pointer from
3505 saved_rp = gen_reg_rtx (Pmode);
3506 emit_move_insn (saved_rp, plus_constant (frameaddr, -20));
3508 /* Get pointer to the instruction stream. We have to mask out the
3509 privilege level from the two low order bits of the return address
3510 pointer here so that ins will point to the start of the first
3511 instruction that would have been executed if we returned. */
3512 ins = copy_to_reg (gen_rtx_AND (Pmode,
3513 copy_to_reg (gen_rtx_MEM (Pmode, saved_rp)),
3515 label = gen_label_rtx ();
3517 /* Check the instruction stream at the normal return address for the
3520 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3521 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3522 0x00011820 | stub+16: mtsp r1,sr0
3523 0xe0400002 | stub+20: be,n 0(sr0,rp)
3525 If it is an export stub, than our return address is really in
3528 emit_cmp_insn (gen_rtx_MEM (SImode, ins),
3529 GEN_INT (0x4bc23fd1),
3530 NE, NULL_RTX, SImode, 1, 0);
3531 emit_jump_insn (gen_bne (label));
3533 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3534 GEN_INT (0x004010a1),
3535 NE, NULL_RTX, SImode, 1, 0);
3536 emit_jump_insn (gen_bne (label));
3538 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3539 GEN_INT (0x00011820),
3540 NE, NULL_RTX, SImode, 1, 0);
3541 emit_jump_insn (gen_bne (label));
3543 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3544 GEN_INT (0xe0400002),
3545 NE, NULL_RTX, SImode, 1, 0);
3547 /* If there is no export stub then just use our initial guess of
3550 emit_jump_insn (gen_bne (label));
3552 /* Here we know that our return address pointer points to an export
3553 stub. We don't want to return the address of the export stub,
3554 but rather the return address that leads back into user code.
3555 That return address is stored at -24[frameaddr]. */
3557 emit_move_insn (saved_rp, plus_constant (frameaddr, -24));
3560 return gen_rtx_MEM (Pmode, memory_address (Pmode, saved_rp));
3563 /* This is only valid once reload has completed because it depends on
3564 knowing exactly how much (if any) frame there is and...
3566 It's only valid if there is no frame marker to de-allocate and...
3568 It's only valid if %r2 hasn't been saved into the caller's frame
3569 (we're not profiling and %r2 isn't live anywhere). */
3571 hppa_can_use_return_insn_p ()
3573 return (reload_completed
3574 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3575 && ! regs_ever_live[2]
3576 && ! frame_pointer_needed);
3580 emit_bcond_fp (code, operand0)
3584 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3585 gen_rtx_IF_THEN_ELSE (VOIDmode,
3586 gen_rtx_fmt_ee (code,
3588 gen_rtx_REG (CCFPmode, 0),
3590 gen_rtx_LABEL_REF (VOIDmode, operand0),
3596 gen_cmp_fp (code, operand0, operand1)
3598 rtx operand0, operand1;
3600 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3601 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3604 /* Adjust the cost of a scheduling dependency. Return the new cost of
3605 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3608 pa_adjust_cost (insn, link, dep_insn, cost)
3614 enum attr_type attr_type;
3616 /* Don't adjust costs for a pa8000 chip. */
3617 if (pa_cpu >= PROCESSOR_8000)
3620 if (! recog_memoized (insn))
3623 attr_type = get_attr_type (insn);
3625 if (REG_NOTE_KIND (link) == 0)
3627 /* Data dependency; DEP_INSN writes a register that INSN reads some
3630 if (attr_type == TYPE_FPSTORE)
3632 rtx pat = PATTERN (insn);
3633 rtx dep_pat = PATTERN (dep_insn);
3634 if (GET_CODE (pat) == PARALLEL)
3636 /* This happens for the fstXs,mb patterns. */
3637 pat = XVECEXP (pat, 0, 0);
3639 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3640 /* If this happens, we have to extend this to schedule
3641 optimally. Return 0 for now. */
3644 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
3646 if (! recog_memoized (dep_insn))
3648 /* DEP_INSN is writing its result to the register
3649 being stored in the fpstore INSN. */
3650 switch (get_attr_type (dep_insn))
3653 /* This cost 3 cycles, not 2 as the md says for the
3662 case TYPE_FPSQRTSGL:
3663 case TYPE_FPSQRTDBL:
3664 /* In these important cases, we save one cycle compared to
3665 when flop instruction feed each other. */
3674 /* For other data dependencies, the default cost specified in the
3678 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3680 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3683 if (attr_type == TYPE_FPLOAD)
3685 rtx pat = PATTERN (insn);
3686 rtx dep_pat = PATTERN (dep_insn);
3687 if (GET_CODE (pat) == PARALLEL)
3689 /* This happens for the fldXs,mb patterns. */
3690 pat = XVECEXP (pat, 0, 0);
3692 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3693 /* If this happens, we have to extend this to schedule
3694 optimally. Return 0 for now. */
3697 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3699 if (! recog_memoized (dep_insn))
3701 switch (get_attr_type (dep_insn))
3708 case TYPE_FPSQRTSGL:
3709 case TYPE_FPSQRTDBL:
3710 /* A fpload can't be issued until one cycle before a
3711 preceding arithmetic operation has finished if
3712 the target of the fpload is any of the sources
3713 (or destination) of the arithmetic operation. */
3721 else if (attr_type == TYPE_FPALU)
3723 rtx pat = PATTERN (insn);
3724 rtx dep_pat = PATTERN (dep_insn);
3725 if (GET_CODE (pat) == PARALLEL)
3727 /* This happens for the fldXs,mb patterns. */
3728 pat = XVECEXP (pat, 0, 0);
3730 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3731 /* If this happens, we have to extend this to schedule
3732 optimally. Return 0 for now. */
3735 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3737 if (! recog_memoized (dep_insn))
3739 switch (get_attr_type (dep_insn))
3743 case TYPE_FPSQRTSGL:
3744 case TYPE_FPSQRTDBL:
3745 /* An ALU flop can't be issued until two cycles before a
3746 preceding divide or sqrt operation has finished if
3747 the target of the ALU flop is any of the sources
3748 (or destination) of the divide or sqrt operation. */
3757 /* For other anti dependencies, the cost is 0. */
3760 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3762 /* Output dependency; DEP_INSN writes a register that INSN writes some
3764 if (attr_type == TYPE_FPLOAD)
3766 rtx pat = PATTERN (insn);
3767 rtx dep_pat = PATTERN (dep_insn);
3768 if (GET_CODE (pat) == PARALLEL)
3770 /* This happens for the fldXs,mb patterns. */
3771 pat = XVECEXP (pat, 0, 0);
3773 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3774 /* If this happens, we have to extend this to schedule
3775 optimally. Return 0 for now. */
3778 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3780 if (! recog_memoized (dep_insn))
3782 switch (get_attr_type (dep_insn))
3789 case TYPE_FPSQRTSGL:
3790 case TYPE_FPSQRTDBL:
3791 /* A fpload can't be issued until one cycle before a
3792 preceding arithmetic operation has finished if
3793 the target of the fpload is the destination of the
3794 arithmetic operation. */
3802 else if (attr_type == TYPE_FPALU)
3804 rtx pat = PATTERN (insn);
3805 rtx dep_pat = PATTERN (dep_insn);
3806 if (GET_CODE (pat) == PARALLEL)
3808 /* This happens for the fldXs,mb patterns. */
3809 pat = XVECEXP (pat, 0, 0);
3811 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3812 /* If this happens, we have to extend this to schedule
3813 optimally. Return 0 for now. */
3816 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3818 if (! recog_memoized (dep_insn))
3820 switch (get_attr_type (dep_insn))
3824 case TYPE_FPSQRTSGL:
3825 case TYPE_FPSQRTDBL:
3826 /* An ALU flop can't be issued until two cycles before a
3827 preceding divide or sqrt operation has finished if
3828 the target of the ALU flop is also the target of
3829 the divide or sqrt operation. */
3838 /* For other output dependencies, the cost is 0. */
3845 /* Adjust scheduling priorities. We use this to try and keep addil
3846 and the next use of %r1 close together. */
3848 pa_adjust_priority (insn, priority)
3852 rtx set = single_set (insn);
3856 src = SET_SRC (set);
3857 dest = SET_DEST (set);
3858 if (GET_CODE (src) == LO_SUM
3859 && symbolic_operand (XEXP (src, 1), VOIDmode)
3860 && ! read_only_operand (XEXP (src, 1), VOIDmode))
3863 else if (GET_CODE (src) == MEM
3864 && GET_CODE (XEXP (src, 0)) == LO_SUM
3865 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
3866 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
3869 else if (GET_CODE (dest) == MEM
3870 && GET_CODE (XEXP (dest, 0)) == LO_SUM
3871 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
3872 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
3878 /* The 700 can only issue a single insn at a time.
3879 The 7XXX processors can issue two insns at a time.
3880 The 8000 can issue 4 insns at a time. */
3886 case PROCESSOR_700: return 1;
3887 case PROCESSOR_7100: return 2;
3888 case PROCESSOR_7100LC: return 2;
3889 case PROCESSOR_7200: return 2;
3890 case PROCESSOR_8000: return 4;
3899 /* Return any length adjustment needed by INSN which already has its length
3900 computed as LENGTH. Return zero if no adjustment is necessary.
3902 For the PA: function calls, millicode calls, and backwards short
3903 conditional branches with unfilled delay slots need an adjustment by +1
3904 (to account for the NOP which will be inserted into the instruction stream).
3906 Also compute the length of an inline block move here as it is too
3907 complicated to express as a length attribute in pa.md. */
3909 pa_adjust_insn_length (insn, length)
3913 rtx pat = PATTERN (insn);
3915 /* Call insns which are *not* indirect and have unfilled delay slots. */
3916 if (GET_CODE (insn) == CALL_INSN)
3919 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
3920 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
3922 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
3923 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
3929 /* Jumps inside switch tables which have unfilled delay slots
3930 also need adjustment. */
3931 else if (GET_CODE (insn) == JUMP_INSN
3932 && simplejump_p (insn)
3933 && GET_MODE (insn) == SImode)
3935 /* Millicode insn with an unfilled delay slot. */
3936 else if (GET_CODE (insn) == INSN
3937 && GET_CODE (pat) != SEQUENCE
3938 && GET_CODE (pat) != USE
3939 && GET_CODE (pat) != CLOBBER
3940 && get_attr_type (insn) == TYPE_MILLI)
3942 /* Block move pattern. */
3943 else if (GET_CODE (insn) == INSN
3944 && GET_CODE (pat) == PARALLEL
3945 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3946 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
3947 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
3948 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
3949 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
3950 return compute_movstrsi_length (insn) - 4;
3951 /* Conditional branch with an unfilled delay slot. */
3952 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
3954 /* Adjust a short backwards conditional with an unfilled delay slot. */
3955 if (GET_CODE (pat) == SET
3957 && ! forward_branch_p (insn))
3959 else if (GET_CODE (pat) == PARALLEL
3960 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
3963 /* Adjust dbra insn with short backwards conditional branch with
3964 unfilled delay slot -- only for case where counter is in a
3965 general register register. */
3966 else if (GET_CODE (pat) == PARALLEL
3967 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
3968 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
3969 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
3971 && ! forward_branch_p (insn))
3979 /* Print operand X (an rtx) in assembler syntax to file FILE.
3980 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3981 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3984 print_operand (file, x, code)
3992 /* Output a 'nop' if there's nothing for the delay slot. */
3993 if (dbr_sequence_length () == 0)
3994 fputs ("\n\tnop", file);
3997 /* Output an nullification completer if there's nothing for the */
3998 /* delay slot or nullification is requested. */
3999 if (dbr_sequence_length () == 0 ||
4001 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4005 /* Print out the second register name of a register pair.
4006 I.e., R (6) => 7. */
4007 fputs (reg_names[REGNO (x) + 1], file);
4010 /* A register or zero. */
4012 || (x == CONST0_RTX (DFmode))
4013 || (x == CONST0_RTX (SFmode)))
4015 fputs ("%r0", file);
4021 /* A register or zero (floating point). */
4023 || (x == CONST0_RTX (DFmode))
4024 || (x == CONST0_RTX (SFmode)))
4026 fputs ("%fr0", file);
4035 xoperands[0] = XEXP (XEXP (x, 0), 0);
4036 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4037 output_global_address (file, xoperands[1], 0);
4038 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4042 case 'C': /* Plain (C)ondition */
4044 switch (GET_CODE (x))
4047 fputs ("=", file); break;
4049 fputs ("<>", file); break;
4051 fputs (">", file); break;
4053 fputs (">=", file); break;
4055 fputs (">>=", file); break;
4057 fputs (">>", file); break;
4059 fputs ("<", file); break;
4061 fputs ("<=", file); break;
4063 fputs ("<<=", file); break;
4065 fputs ("<<", file); break;
4070 case 'N': /* Condition, (N)egated */
4071 switch (GET_CODE (x))
4074 fputs ("<>", file); break;
4076 fputs ("=", file); break;
4078 fputs ("<=", file); break;
4080 fputs ("<", file); break;
4082 fputs ("<<", file); break;
4084 fputs ("<<=", file); break;
4086 fputs (">=", file); break;
4088 fputs (">", file); break;
4090 fputs (">>", file); break;
4092 fputs (">>=", file); break;
4097 /* For floating point comparisons. Note that the output
4098 predicates are the complement of the desired mode. */
4100 switch (GET_CODE (x))
4103 fputs ("!=", file); break;
4105 fputs ("=", file); break;
4107 fputs ("!>", file); break;
4109 fputs ("!>=", file); break;
4111 fputs ("!<", file); break;
4113 fputs ("!<=", file); break;
4115 fputs ("!<>", file); break;
4117 fputs (">", file); break;
4119 fputs (">=", file); break;
4121 fputs ("<", file); break;
4123 fputs ("<=", file); break;
4125 fputs ("<>", file); break;
4127 fputs ("<=>", file); break;
4129 fputs ("!<=>", file); break;
4134 case 'S': /* Condition, operands are (S)wapped. */
4135 switch (GET_CODE (x))
4138 fputs ("=", file); break;
4140 fputs ("<>", file); break;
4142 fputs ("<", file); break;
4144 fputs ("<=", file); break;
4146 fputs ("<<=", file); break;
4148 fputs ("<<", file); break;
4150 fputs (">", file); break;
4152 fputs (">=", file); break;
4154 fputs (">>=", file); break;
4156 fputs (">>", file); break;
4161 case 'B': /* Condition, (B)oth swapped and negate. */
4162 switch (GET_CODE (x))
4165 fputs ("<>", file); break;
4167 fputs ("=", file); break;
4169 fputs (">=", file); break;
4171 fputs (">", file); break;
4173 fputs (">>", file); break;
4175 fputs (">>=", file); break;
4177 fputs ("<=", file); break;
4179 fputs ("<", file); break;
4181 fputs ("<<", file); break;
4183 fputs ("<<=", file); break;
4189 if (GET_CODE (x) == CONST_INT)
4191 fprintf (file, "%d", ~INTVAL (x));
4196 if (GET_CODE (x) == CONST_INT)
4198 fprintf (file, "%d", 64 - (INTVAL (x) & 63));
4203 if (GET_CODE (x) == CONST_INT)
4205 fprintf (file, "%d", 32 - (INTVAL (x) & 31));
4210 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4212 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4217 if (GET_CODE (x) == CONST_INT)
4219 fprintf (file, "%d", 63 - (INTVAL (x) & 63));
4224 if (GET_CODE (x) == CONST_INT)
4226 fprintf (file, "%d", 31 - (INTVAL (x) & 31));
4231 if (GET_CODE (x) == CONST_INT)
4236 switch (GET_CODE (XEXP (x, 0)))
4240 if (ASSEMBLER_DIALECT == 0)
4241 fputs ("s,mb", file);
4243 fputs (",mb", file);
4247 if (ASSEMBLER_DIALECT == 0)
4248 fputs ("s,ma", file);
4250 fputs (",ma", file);
4253 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4254 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4256 if (ASSEMBLER_DIALECT == 0)
4257 fputs ("x,s", file);
4261 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4265 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4271 output_global_address (file, x, 0);
4274 output_global_address (file, x, 1);
4276 case 0: /* Don't do anything special */
4281 compute_zdepwi_operands (INTVAL (x), op);
4282 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4288 compute_zdepdi_operands (INTVAL (x), op);
4289 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4293 /* We can get here from a .vtable_inherit due to our
4294 CONSTANT_ADDRESS_P rejecting perfectly good constant
4300 if (GET_CODE (x) == REG)
4302 fputs (reg_names [REGNO (x)], file);
4303 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4309 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4310 && (REGNO (x) & 1) == 0)
4313 else if (GET_CODE (x) == MEM)
4315 int size = GET_MODE_SIZE (GET_MODE (x));
4316 rtx base = NULL_RTX;
4317 switch (GET_CODE (XEXP (x, 0)))
4321 base = XEXP (XEXP (x, 0), 0);
4322 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4326 base = XEXP (XEXP (x, 0), 0);
4327 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4330 if (GET_CODE (XEXP (x, 0)) == PLUS
4331 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4332 fprintf (file, "%s(%s)",
4333 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4334 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4335 else if (GET_CODE (XEXP (x, 0)) == PLUS
4336 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4337 fprintf (file, "%s(%s)",
4338 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4339 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4341 output_address (XEXP (x, 0));
4346 output_addr_const (file, x);
4349 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4352 output_global_address (file, x, round_constant)
4358 /* Imagine (high (const (plus ...))). */
4359 if (GET_CODE (x) == HIGH)
4362 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4363 assemble_name (file, XSTR (x, 0));
4364 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4366 assemble_name (file, XSTR (x, 0));
4367 fputs ("-$global$", file);
4369 else if (GET_CODE (x) == CONST)
4371 const char *sep = "";
4372 int offset = 0; /* assembler wants -$global$ at end */
4373 rtx base = NULL_RTX;
4375 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4377 base = XEXP (XEXP (x, 0), 0);
4378 output_addr_const (file, base);
4380 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4381 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4384 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4386 base = XEXP (XEXP (x, 0), 1);
4387 output_addr_const (file, base);
4389 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4390 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4393 /* How bogus. The compiler is apparently responsible for
4394 rounding the constant if it uses an LR field selector.
4396 The linker and/or assembler seem a better place since
4397 they have to do this kind of thing already.
4399 If we fail to do this, HP's optimizing linker may eliminate
4400 an addil, but not update the ldw/stw/ldo instruction that
4401 uses the result of the addil. */
4403 offset = ((offset + 0x1000) & ~0x1fff);
4405 if (GET_CODE (XEXP (x, 0)) == PLUS)
4415 else if (GET_CODE (XEXP (x, 0)) == MINUS
4416 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4420 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4421 fputs ("-$global$", file);
4423 fprintf (file, "%s%d", sep, offset);
4426 output_addr_const (file, x);
4430 output_deferred_plabels (file)
4434 /* If we have deferred plabels, then we need to switch into the data
4435 section and align it to a 4 byte boundary before we output the
4436 deferred plabels. */
4437 if (n_deferred_plabels)
4440 ASM_OUTPUT_ALIGN (file, 2);
4443 /* Now output the deferred plabels. */
4444 for (i = 0; i < n_deferred_plabels; i++)
4446 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4447 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4452 /* HP's millicode routines mean something special to the assembler.
4453 Keep track of which ones we have used. */
4455 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
4456 static void import_milli PARAMS ((enum millicodes));
4457 static char imported[(int) end1000];
4458 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4459 static char import_string[] = ".IMPORT $$....,MILLICODE";
4460 #define MILLI_START 10
4464 enum millicodes code;
4466 char str[sizeof (import_string)];
4468 if (!imported[(int) code])
4470 imported[(int) code] = 1;
4471 strcpy (str, import_string);
4472 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4473 output_asm_insn (str, 0);
4477 /* The register constraints have put the operands and return value in
4478 the proper registers. */
4481 output_mul_insn (unsignedp, insn)
4482 int unsignedp ATTRIBUTE_UNUSED;
4485 import_milli (mulI);
4486 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4489 /* Emit the rtl for doing a division by a constant. */
4491 /* Do magic division millicodes exist for this value? */
4492 static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4495 /* We'll use an array to keep track of the magic millicodes and
4496 whether or not we've used them already. [n][0] is signed, [n][1] is
4499 static int div_milli[16][2];
4502 div_operand (op, mode)
4504 enum machine_mode mode;
4506 return (mode == SImode
4507 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4508 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4509 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4513 emit_hpdiv_const (operands, unsignedp)
4517 if (GET_CODE (operands[2]) == CONST_INT
4518 && INTVAL (operands[2]) > 0
4519 && INTVAL (operands[2]) < 16
4520 && magic_milli[INTVAL (operands[2])])
4522 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4524 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4527 (PARALLEL, VOIDmode,
4528 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4529 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4531 gen_rtx_REG (SImode, 26),
4533 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4534 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4535 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4536 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4537 gen_rtx_CLOBBER (VOIDmode, ret))));
4538 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4545 output_div_insn (operands, unsignedp, insn)
4552 /* If the divisor is a constant, try to use one of the special
4554 if (GET_CODE (operands[0]) == CONST_INT)
4556 static char buf[100];
4557 divisor = INTVAL (operands[0]);
4558 if (!div_milli[divisor][unsignedp])
4560 div_milli[divisor][unsignedp] = 1;
4562 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4564 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4568 sprintf (buf, "$$divU_%d", INTVAL (operands[0]));
4569 return output_millicode_call (insn,
4570 gen_rtx_SYMBOL_REF (SImode, buf));
4574 sprintf (buf, "$$divI_%d", INTVAL (operands[0]));
4575 return output_millicode_call (insn,
4576 gen_rtx_SYMBOL_REF (SImode, buf));
4579 /* Divisor isn't a special constant. */
4584 import_milli (divU);
4585 return output_millicode_call (insn,
4586 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4590 import_milli (divI);
4591 return output_millicode_call (insn,
4592 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4597 /* Output a $$rem millicode to do mod. */
4600 output_mod_insn (unsignedp, insn)
4606 import_milli (remU);
4607 return output_millicode_call (insn,
4608 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4612 import_milli (remI);
4613 return output_millicode_call (insn,
4614 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4619 output_arg_descriptor (call_insn)
4622 const char *arg_regs[4];
4623 enum machine_mode arg_mode;
4625 int i, output_flag = 0;
4628 /* We neither need nor want argument location descriptors for the
4629 64bit runtime environment or the ELF32 environment. */
4630 if (TARGET_64BIT || TARGET_ELF32)
4633 for (i = 0; i < 4; i++)
4636 /* Specify explicitly that no argument relocations should take place
4637 if using the portable runtime calling conventions. */
4638 if (TARGET_PORTABLE_RUNTIME)
4640 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4645 if (GET_CODE (call_insn) != CALL_INSN)
4647 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4649 rtx use = XEXP (link, 0);
4651 if (! (GET_CODE (use) == USE
4652 && GET_CODE (XEXP (use, 0)) == REG
4653 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4656 arg_mode = GET_MODE (XEXP (use, 0));
4657 regno = REGNO (XEXP (use, 0));
4658 if (regno >= 23 && regno <= 26)
4660 arg_regs[26 - regno] = "GR";
4661 if (arg_mode == DImode)
4662 arg_regs[25 - regno] = "GR";
4664 else if (regno >= 32 && regno <= 39)
4666 if (arg_mode == SFmode)
4667 arg_regs[(regno - 32) / 2] = "FR";
4670 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4671 arg_regs[(regno - 34) / 2] = "FR";
4672 arg_regs[(regno - 34) / 2 + 1] = "FU";
4674 arg_regs[(regno - 34) / 2] = "FU";
4675 arg_regs[(regno - 34) / 2 + 1] = "FR";
4680 fputs ("\t.CALL ", asm_out_file);
4681 for (i = 0; i < 4; i++)
4686 fputc (',', asm_out_file);
4687 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4690 fputc ('\n', asm_out_file);
4693 /* Return the class of any secondary reload register that is needed to
4694 move IN into a register in class CLASS using mode MODE.
4696 Profiling has showed this routine and its descendants account for
4697 a significant amount of compile time (~7%). So it has been
4698 optimized to reduce redundant computations and eliminate useless
4701 It might be worthwhile to try and make this a leaf function too. */
4704 secondary_reload_class (class, mode, in)
4705 enum reg_class class;
4706 enum machine_mode mode;
4709 int regno, is_symbolic;
4711 /* Trying to load a constant into a FP register during PIC code
4712 generation will require %r1 as a scratch register. */
4714 && GET_MODE_CLASS (mode) == MODE_INT
4715 && FP_REG_CLASS_P (class)
4716 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4719 /* Profiling showed the PA port spends about 1.3% of its compilation
4720 time in true_regnum from calls inside secondary_reload_class. */
4722 if (GET_CODE (in) == REG)
4725 if (regno >= FIRST_PSEUDO_REGISTER)
4726 regno = true_regnum (in);
4728 else if (GET_CODE (in) == SUBREG)
4729 regno = true_regnum (in);
4733 /* If we have something like (mem (mem (...)), we can safely assume the
4734 inner MEM will end up in a general register after reloading, so there's
4735 no need for a secondary reload. */
4736 if (GET_CODE (in) == MEM
4737 && GET_CODE (XEXP (in, 0)) == MEM)
4740 /* Handle out of range displacement for integer mode loads/stores of
4742 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
4743 && GET_MODE_CLASS (mode) == MODE_INT
4744 && FP_REG_CLASS_P (class))
4745 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
4746 return GENERAL_REGS;
4748 /* A SAR<->FP register copy requires a secondary register (GPR) as
4749 well as secondary memory. */
4750 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4751 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
4752 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
4753 return GENERAL_REGS;
4755 if (GET_CODE (in) == HIGH)
4758 /* Profiling has showed GCC spends about 2.6% of its compilation
4759 time in symbolic_operand from calls inside secondary_reload_class.
4761 We use an inline copy and only compute its return value once to avoid
4763 switch (GET_CODE (in))
4773 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
4774 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
4775 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
4785 && read_only_operand (in, VOIDmode))
4788 if (class != R1_REGS && is_symbolic)
4795 function_arg_padding (mode, type)
4796 enum machine_mode mode;
4801 if (mode == BLKmode)
4803 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4804 size = int_size_in_bytes (type) * BITS_PER_UNIT;
4806 return upward; /* Don't know if this is right, but */
4807 /* same as old definition. */
4810 size = GET_MODE_BITSIZE (mode);
4811 if (size < PARM_BOUNDARY)
4813 else if (size % PARM_BOUNDARY)
4820 /* Do what is necessary for `va_start'. We look at the current function
4821 to determine if stdargs or varargs is used and fill in an initial
4822 va_list. A pointer to this constructor is returned. */
4825 hppa_builtin_saveregs ()
4828 tree fntype = TREE_TYPE (current_function_decl);
4829 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
4830 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4831 != void_type_node)))
4832 ? UNITS_PER_WORD : 0);
4835 offset = plus_constant (current_function_arg_offset_rtx, argadj);
4837 offset = current_function_arg_offset_rtx;
4843 /* Adjust for varargs/stdarg differences. */
4845 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
4847 offset = current_function_arg_offset_rtx;
4849 /* We need to save %r26 .. %r19 inclusive starting at offset -64
4850 from the incoming arg pointer and growing to larger addresses. */
4851 for (i = 26, off = -64; i >= 19; i--, off += 8)
4852 emit_move_insn (gen_rtx_MEM (word_mode,
4853 plus_constant (arg_pointer_rtx, off)),
4854 gen_rtx_REG (word_mode, i));
4856 /* The incoming args pointer points just beyond the flushback area;
4857 normally this is not a serious concern. Howver, when we are doing
4858 varargs/stdargs we want to make the arg pointer point to the start
4859 of the incoming argument area. */
4860 emit_move_insn (virtual_incoming_args_rtx,
4861 plus_constant (arg_pointer_rtx, -64));
4863 /* Now return a pointer to the first anonymous argument. */
4864 return copy_to_reg (expand_binop (Pmode, add_optab,
4865 virtual_incoming_args_rtx,
4866 offset, 0, 0, OPTAB_LIB_WIDEN));
4869 /* Store general registers on the stack. */
4870 dest = gen_rtx_MEM (BLKmode,
4871 plus_constant (current_function_internal_arg_pointer,
4873 set_mem_alias_set (dest, get_varargs_alias_set ());
4874 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
4876 /* move_block_from_reg will emit code to store the argument registers
4877 individually as scalar stores.
4879 However, other insns may later load from the same addresses for
4880 a structure load (passing a struct to a varargs routine).
4882 The alias code assumes that such aliasing can never happen, so we
4883 have to keep memory referencing insns from moving up beyond the
4884 last argument register store. So we emit a blockage insn here. */
4885 emit_insn (gen_blockage ());
4887 if (current_function_check_memory_usage)
4888 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4890 GEN_INT (4 * UNITS_PER_WORD), TYPE_MODE (sizetype),
4891 GEN_INT (MEMORY_USE_RW),
4892 TYPE_MODE (integer_type_node));
4894 return copy_to_reg (expand_binop (Pmode, add_optab,
4895 current_function_internal_arg_pointer,
4896 offset, 0, 0, OPTAB_LIB_WIDEN));
4900 hppa_va_start (stdarg_p, valist, nextarg)
4901 int stdarg_p ATTRIBUTE_UNUSED;
4905 nextarg = expand_builtin_saveregs ();
4906 std_expand_builtin_va_start (1, valist, nextarg);
4910 hppa_va_arg (valist, type)
4913 HOST_WIDE_INT align, size, ofs;
4918 /* Every argument in PA64 is passed by value (including large structs).
4919 Arguments with size greater than 8 must be aligned 0 MOD 16. */
4921 size = int_size_in_bytes (type);
4922 if (size > UNITS_PER_WORD)
4924 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4925 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4926 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4927 build_int_2 (-2 * UNITS_PER_WORD, -1));
4928 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4929 TREE_SIDE_EFFECTS (t) = 1;
4930 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4932 return std_expand_builtin_va_arg (valist, type);
4935 /* Compute the rounded size of the type. */
4936 align = PARM_BOUNDARY / BITS_PER_UNIT;
4937 size = int_size_in_bytes (type);
4939 ptr = build_pointer_type (type);
4941 /* "Large" types are passed by reference. */
4944 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
4945 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4946 TREE_SIDE_EFFECTS (t) = 1;
4948 pptr = build_pointer_type (ptr);
4949 t = build1 (NOP_EXPR, pptr, t);
4950 TREE_SIDE_EFFECTS (t) = 1;
4952 t = build1 (INDIRECT_REF, ptr, t);
4953 TREE_SIDE_EFFECTS (t) = 1;
4957 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4958 build_int_2 (-size, -1));
4960 /* Copied from va-pa.h, but we probably don't need to align
4961 to word size, since we generate and preserve that invariant. */
4962 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
4963 build_int_2 ((size > 4 ? -8 : -4), -1));
4965 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4966 TREE_SIDE_EFFECTS (t) = 1;
4968 ofs = (8 - size) % 4;
4971 t = build (PLUS_EXPR, TREE_TYPE (valist), t, build_int_2 (ofs, 0));
4972 TREE_SIDE_EFFECTS (t) = 1;
4975 t = build1 (NOP_EXPR, ptr, t);
4976 TREE_SIDE_EFFECTS (t) = 1;
4980 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
4985 /* This routine handles all the normal conditional branch sequences we
4986 might need to generate. It handles compare immediate vs compare
4987 register, nullification of delay slots, varying length branches,
4988 negated branches, and all combinations of the above. It returns the
4989 output appropriate to emit the branch corresponding to all given
4993 output_cbranch (operands, nullify, length, negated, insn)
4995 int nullify, length, negated;
4998 static char buf[100];
5001 /* A conditional branch to the following instruction (eg the delay slot) is
5002 asking for a disaster. This can happen when not optimizing.
5004 In such cases it is safe to emit nothing. */
5006 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5009 /* If this is a long branch with its delay slot unfilled, set `nullify'
5010 as it can nullify the delay slot and save a nop. */
5011 if (length == 8 && dbr_sequence_length () == 0)
5014 /* If this is a short forward conditional branch which did not get
5015 its delay slot filled, the delay slot can still be nullified. */
5016 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5017 nullify = forward_branch_p (insn);
5019 /* A forward branch over a single nullified insn can be done with a
5020 comclr instruction. This avoids a single cycle penalty due to
5021 mis-predicted branch if we fall through (branch not taken). */
5023 && next_real_insn (insn) != 0
5024 && get_attr_length (next_real_insn (insn)) == 4
5025 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5031 /* All short conditional branches except backwards with an unfilled
5035 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5037 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5038 if (GET_MODE (operands[1]) == DImode)
5041 strcat (buf, "%B3");
5043 strcat (buf, "%S3");
5045 strcat (buf, " %2,%r1,%%r0");
5047 strcat (buf, ",n %2,%r1,%0");
5049 strcat (buf, " %2,%r1,%0");
5052 /* All long conditionals. Note an short backward branch with an
5053 unfilled delay slot is treated just like a long backward branch
5054 with an unfilled delay slot. */
5056 /* Handle weird backwards branch with a filled delay slot
5057 with is nullified. */
5058 if (dbr_sequence_length () != 0
5059 && ! forward_branch_p (insn)
5062 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5063 if (GET_MODE (operands[1]) == DImode)
5066 strcat (buf, "%S3");
5068 strcat (buf, "%B3");
5069 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5071 /* Handle short backwards branch with an unfilled delay slot.
5072 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5073 taken and untaken branches. */
5074 else if (dbr_sequence_length () == 0
5075 && ! forward_branch_p (insn)
5076 && INSN_ADDRESSES_SET_P ()
5077 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5078 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5080 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5081 if (GET_MODE (operands[1]) == DImode)
5084 strcat (buf, "%B3 %2,%r1,%0%#");
5086 strcat (buf, "%S3 %2,%r1,%0%#");
5090 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5091 if (GET_MODE (operands[1]) == DImode)
5094 strcat (buf, "%S3");
5096 strcat (buf, "%B3");
5098 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5100 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5105 /* Very long branch. Right now we only handle these when not
5106 optimizing. See "jump" pattern in pa.md for details. */
5110 /* Create a reversed conditional branch which branches around
5111 the following insns. */
5113 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5115 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5116 if (GET_MODE (operands[1]) == DImode)
5120 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5123 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5125 output_asm_insn (buf, operands);
5127 /* Output an insn to save %r1. */
5128 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5130 /* Now output a very long branch to the original target. */
5131 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5133 /* Now restore the value of %r1 in the delay slot. We're not
5134 optimizing so we know nothing else can be in the delay slot. */
5135 return "ldw -16(%%r30),%%r1";
5138 /* Very long branch when generating PIC code. Right now we only
5139 handle these when not optimizing. See "jump" pattern in pa.md
5144 /* Create a reversed conditional branch which branches around
5145 the following insns. */
5147 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5149 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5150 if (GET_MODE (operands[1]) == DImode)
5153 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5155 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5157 output_asm_insn (buf, operands);
5159 /* Output an insn to save %r1. */
5160 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5162 /* Now output a very long PIC branch to the original target. */
5166 xoperands[0] = operands[0];
5167 xoperands[1] = operands[1];
5168 xoperands[2] = operands[2];
5169 xoperands[3] = operands[3];
5170 xoperands[4] = gen_label_rtx ();
5172 output_asm_insn ("{bl|b,l} .+8,%%r1\n\taddil L'%l0-%l4,%%r1",
5174 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5175 CODE_LABEL_NUMBER (xoperands[4]));
5176 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
5180 /* Now restore the value of %r1 in the delay slot. We're not
5181 optimizing so we know nothing else can be in the delay slot. */
5182 return "ldw -16(%%r30),%%r1";
5190 /* This routine handles all the branch-on-bit conditional branch sequences we
5191 might need to generate. It handles nullification of delay slots,
5192 varying length branches, negated branches and all combinations of the
5193 above. it returns the appropriate output template to emit the branch. */
5196 output_bb (operands, nullify, length, negated, insn, which)
5197 rtx *operands ATTRIBUTE_UNUSED;
5198 int nullify, length, negated;
5202 static char buf[100];
5205 /* A conditional branch to the following instruction (eg the delay slot) is
5206 asking for a disaster. I do not think this can happen as this pattern
5207 is only used when optimizing; jump optimization should eliminate the
5208 jump. But be prepared just in case. */
5210 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5213 /* If this is a long branch with its delay slot unfilled, set `nullify'
5214 as it can nullify the delay slot and save a nop. */
5215 if (length == 8 && dbr_sequence_length () == 0)
5218 /* If this is a short forward conditional branch which did not get
5219 its delay slot filled, the delay slot can still be nullified. */
5220 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5221 nullify = forward_branch_p (insn);
5223 /* A forward branch over a single nullified insn can be done with a
5224 extrs instruction. This avoids a single cycle penalty due to
5225 mis-predicted branch if we fall through (branch not taken). */
5228 && next_real_insn (insn) != 0
5229 && get_attr_length (next_real_insn (insn)) == 4
5230 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5237 /* All short conditional branches except backwards with an unfilled
5241 strcpy (buf, "{extrs,|extrw,s,}");
5243 strcpy (buf, "bb,");
5244 if (useskip && GET_MODE (operands[0]) == DImode)
5245 strcpy (buf, "extrd,s,*");
5246 else if (GET_MODE (operands[0]) == DImode)
5247 strcpy (buf, "bb,*");
5248 if ((which == 0 && negated)
5249 || (which == 1 && ! negated))
5254 strcat (buf, " %0,%1,1,%%r0");
5255 else if (nullify && negated)
5256 strcat (buf, ",n %0,%1,%3");
5257 else if (nullify && ! negated)
5258 strcat (buf, ",n %0,%1,%2");
5259 else if (! nullify && negated)
5260 strcat (buf, "%0,%1,%3");
5261 else if (! nullify && ! negated)
5262 strcat (buf, " %0,%1,%2");
5265 /* All long conditionals. Note an short backward branch with an
5266 unfilled delay slot is treated just like a long backward branch
5267 with an unfilled delay slot. */
5269 /* Handle weird backwards branch with a filled delay slot
5270 with is nullified. */
5271 if (dbr_sequence_length () != 0
5272 && ! forward_branch_p (insn)
5275 strcpy (buf, "bb,");
5276 if (GET_MODE (operands[0]) == DImode)
5278 if ((which == 0 && negated)
5279 || (which == 1 && ! negated))
5284 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5286 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5288 /* Handle short backwards branch with an unfilled delay slot.
5289 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5290 taken and untaken branches. */
5291 else if (dbr_sequence_length () == 0
5292 && ! forward_branch_p (insn)
5293 && INSN_ADDRESSES_SET_P ()
5294 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5295 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5297 strcpy (buf, "bb,");
5298 if (GET_MODE (operands[0]) == DImode)
5300 if ((which == 0 && negated)
5301 || (which == 1 && ! negated))
5306 strcat (buf, " %0,%1,%3%#");
5308 strcat (buf, " %0,%1,%2%#");
5312 strcpy (buf, "{extrs,|extrw,s,}");
5313 if (GET_MODE (operands[0]) == DImode)
5314 strcpy (buf, "extrd,s,*");
5315 if ((which == 0 && negated)
5316 || (which == 1 && ! negated))
5320 if (nullify && negated)
5321 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5322 else if (nullify && ! negated)
5323 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5325 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5327 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5337 /* This routine handles all the branch-on-variable-bit conditional branch
5338 sequences we might need to generate. It handles nullification of delay
5339 slots, varying length branches, negated branches and all combinations
5340 of the above. it returns the appropriate output template to emit the
5344 output_bvb (operands, nullify, length, negated, insn, which)
5345 rtx *operands ATTRIBUTE_UNUSED;
5346 int nullify, length, negated;
5350 static char buf[100];
5353 /* A conditional branch to the following instruction (eg the delay slot) is
5354 asking for a disaster. I do not think this can happen as this pattern
5355 is only used when optimizing; jump optimization should eliminate the
5356 jump. But be prepared just in case. */
5358 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5361 /* If this is a long branch with its delay slot unfilled, set `nullify'
5362 as it can nullify the delay slot and save a nop. */
5363 if (length == 8 && dbr_sequence_length () == 0)
5366 /* If this is a short forward conditional branch which did not get
5367 its delay slot filled, the delay slot can still be nullified. */
5368 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5369 nullify = forward_branch_p (insn);
5371 /* A forward branch over a single nullified insn can be done with a
5372 extrs instruction. This avoids a single cycle penalty due to
5373 mis-predicted branch if we fall through (branch not taken). */
5376 && next_real_insn (insn) != 0
5377 && get_attr_length (next_real_insn (insn)) == 4
5378 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5385 /* All short conditional branches except backwards with an unfilled
5389 strcpy (buf, "{vextrs,|extrw,s,}");
5391 strcpy (buf, "{bvb,|bb,}");
5392 if (useskip && GET_MODE (operands[0]) == DImode)
5393 strcpy (buf, "extrd,s,*}");
5394 else if (GET_MODE (operands[0]) == DImode)
5395 strcpy (buf, "bb,*");
5396 if ((which == 0 && negated)
5397 || (which == 1 && ! negated))
5402 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5403 else if (nullify && negated)
5404 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5405 else if (nullify && ! negated)
5406 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5407 else if (! nullify && negated)
5408 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5409 else if (! nullify && ! negated)
5410 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5413 /* All long conditionals. Note an short backward branch with an
5414 unfilled delay slot is treated just like a long backward branch
5415 with an unfilled delay slot. */
5417 /* Handle weird backwards branch with a filled delay slot
5418 with is nullified. */
5419 if (dbr_sequence_length () != 0
5420 && ! forward_branch_p (insn)
5423 strcpy (buf, "{bvb,|bb,}");
5424 if (GET_MODE (operands[0]) == DImode)
5426 if ((which == 0 && negated)
5427 || (which == 1 && ! negated))
5432 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5434 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5436 /* Handle short backwards branch with an unfilled delay slot.
5437 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5438 taken and untaken branches. */
5439 else if (dbr_sequence_length () == 0
5440 && ! forward_branch_p (insn)
5441 && INSN_ADDRESSES_SET_P ()
5442 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5443 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5445 strcpy (buf, "{bvb,|bb,}");
5446 if (GET_MODE (operands[0]) == DImode)
5448 if ((which == 0 && negated)
5449 || (which == 1 && ! negated))
5454 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5456 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5460 strcpy (buf, "{vextrs,|extrw,s,}");
5461 if (GET_MODE (operands[0]) == DImode)
5462 strcpy (buf, "extrd,s,*");
5463 if ((which == 0 && negated)
5464 || (which == 1 && ! negated))
5468 if (nullify && negated)
5469 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5470 else if (nullify && ! negated)
5471 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5473 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5475 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5485 /* Return the output template for emitting a dbra type insn.
5487 Note it may perform some output operations on its own before
5488 returning the final output string. */
5490 output_dbra (operands, insn, which_alternative)
5493 int which_alternative;
5496 /* A conditional branch to the following instruction (eg the delay slot) is
5497 asking for a disaster. Be prepared! */
5499 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5501 if (which_alternative == 0)
5502 return "ldo %1(%0),%0";
5503 else if (which_alternative == 1)
5505 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5506 output_asm_insn ("ldw -16(%%r30),%4", operands);
5507 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5508 return "{fldws|fldw} -16(%%r30),%0";
5512 output_asm_insn ("ldw %0,%4", operands);
5513 return "ldo %1(%4),%4\n\tstw %4,%0";
5517 if (which_alternative == 0)
5519 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5520 int length = get_attr_length (insn);
5522 /* If this is a long branch with its delay slot unfilled, set `nullify'
5523 as it can nullify the delay slot and save a nop. */
5524 if (length == 8 && dbr_sequence_length () == 0)
5527 /* If this is a short forward conditional branch which did not get
5528 its delay slot filled, the delay slot can still be nullified. */
5529 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5530 nullify = forward_branch_p (insn);
5532 /* Handle short versions first. */
5533 if (length == 4 && nullify)
5534 return "addib,%C2,n %1,%0,%3";
5535 else if (length == 4 && ! nullify)
5536 return "addib,%C2 %1,%0,%3";
5537 else if (length == 8)
5539 /* Handle weird backwards branch with a fulled delay slot
5540 which is nullified. */
5541 if (dbr_sequence_length () != 0
5542 && ! forward_branch_p (insn)
5544 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5545 /* Handle short backwards branch with an unfilled delay slot.
5546 Using a addb;nop rather than addi;bl saves 1 cycle for both
5547 taken and untaken branches. */
5548 else if (dbr_sequence_length () == 0
5549 && ! forward_branch_p (insn)
5550 && INSN_ADDRESSES_SET_P ()
5551 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5552 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5553 return "addib,%C2 %1,%0,%3%#";
5555 /* Handle normal cases. */
5557 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5559 return "addi,%N2 %1,%0,%0\n\tb %3";
5564 /* Deal with gross reload from FP register case. */
5565 else if (which_alternative == 1)
5567 /* Move loop counter from FP register to MEM then into a GR,
5568 increment the GR, store the GR into MEM, and finally reload
5569 the FP register from MEM from within the branch's delay slot. */
5570 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5572 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5573 if (get_attr_length (insn) == 24)
5574 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5576 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5578 /* Deal with gross reload from memory case. */
5581 /* Reload loop counter from memory, the store back to memory
5582 happens in the branch's delay slot. */
5583 output_asm_insn ("ldw %0,%4", operands);
5584 if (get_attr_length (insn) == 12)
5585 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5587 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5591 /* Return the output template for emitting a dbra type insn.
5593 Note it may perform some output operations on its own before
5594 returning the final output string. */
5596 output_movb (operands, insn, which_alternative, reverse_comparison)
5599 int which_alternative;
5600 int reverse_comparison;
5603 /* A conditional branch to the following instruction (eg the delay slot) is
5604 asking for a disaster. Be prepared! */
5606 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5608 if (which_alternative == 0)
5609 return "copy %1,%0";
5610 else if (which_alternative == 1)
5612 output_asm_insn ("stw %1,-16(%%r30)", operands);
5613 return "{fldws|fldw} -16(%%r30),%0";
5615 else if (which_alternative == 2)
5621 /* Support the second variant. */
5622 if (reverse_comparison)
5623 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5625 if (which_alternative == 0)
5627 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5628 int length = get_attr_length (insn);
5630 /* If this is a long branch with its delay slot unfilled, set `nullify'
5631 as it can nullify the delay slot and save a nop. */
5632 if (length == 8 && dbr_sequence_length () == 0)
5635 /* If this is a short forward conditional branch which did not get
5636 its delay slot filled, the delay slot can still be nullified. */
5637 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5638 nullify = forward_branch_p (insn);
5640 /* Handle short versions first. */
5641 if (length == 4 && nullify)
5642 return "movb,%C2,n %1,%0,%3";
5643 else if (length == 4 && ! nullify)
5644 return "movb,%C2 %1,%0,%3";
5645 else if (length == 8)
5647 /* Handle weird backwards branch with a filled delay slot
5648 which is nullified. */
5649 if (dbr_sequence_length () != 0
5650 && ! forward_branch_p (insn)
5652 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5654 /* Handle short backwards branch with an unfilled delay slot.
5655 Using a movb;nop rather than or;bl saves 1 cycle for both
5656 taken and untaken branches. */
5657 else if (dbr_sequence_length () == 0
5658 && ! forward_branch_p (insn)
5659 && INSN_ADDRESSES_SET_P ()
5660 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5661 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5662 return "movb,%C2 %1,%0,%3%#";
5663 /* Handle normal cases. */
5665 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5667 return "or,%N2 %1,%%r0,%0\n\tb %3";
5672 /* Deal with gross reload from FP register case. */
5673 else if (which_alternative == 1)
5675 /* Move loop counter from FP register to MEM then into a GR,
5676 increment the GR, store the GR into MEM, and finally reload
5677 the FP register from MEM from within the branch's delay slot. */
5678 output_asm_insn ("stw %1,-16(%%r30)", operands);
5679 if (get_attr_length (insn) == 12)
5680 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
5682 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5684 /* Deal with gross reload from memory case. */
5685 else if (which_alternative == 2)
5687 /* Reload loop counter from memory, the store back to memory
5688 happens in the branch's delay slot. */
5689 if (get_attr_length (insn) == 8)
5690 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
5692 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5694 /* Handle SAR as a destination. */
5697 if (get_attr_length (insn) == 8)
5698 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
5700 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5705 /* INSN is a millicode call. It may have an unconditional jump in its delay
5708 CALL_DEST is the routine we are calling. */
5711 output_millicode_call (insn, call_dest)
5719 xoperands[3] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
5721 /* Handle common case -- empty delay slot or no jump in the delay slot,
5722 and we're sure that the branch will reach the beginning of the $CODE$
5724 if ((dbr_sequence_length () == 0
5725 && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
5726 || (dbr_sequence_length () != 0
5727 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5728 && get_attr_length (insn) == 4))
5730 xoperands[0] = call_dest;
5731 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
5735 /* This call may not reach the beginning of the $CODE$ subspace. */
5736 if (get_attr_length (insn) > 4)
5738 int delay_insn_deleted = 0;
5740 /* We need to emit an inline long-call branch. */
5741 if (dbr_sequence_length () != 0
5742 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5744 /* A non-jump insn in the delay slot. By definition we can
5745 emit this insn before the call. */
5746 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5748 /* Now delete the delay insn. */
5749 PUT_CODE (NEXT_INSN (insn), NOTE);
5750 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5751 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5752 delay_insn_deleted = 1;
5755 /* PIC long millicode call sequence. */
5758 xoperands[0] = call_dest;
5759 xoperands[1] = gen_label_rtx ();
5760 /* Get our address + 8 into %r1. */
5761 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5763 /* Add %r1 to the offset of our target from the next insn. */
5764 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
5765 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5766 CODE_LABEL_NUMBER (xoperands[1]));
5767 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
5769 /* Get the return address into %r31. */
5770 output_asm_insn ("blr 0,%3", xoperands);
5772 /* Branch to our target which is in %r1. */
5773 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
5775 /* Empty delay slot. Note this insn gets fetched twice and
5776 executed once. To be safe we use a nop. */
5777 output_asm_insn ("nop", xoperands);
5779 /* Pure portable runtime doesn't allow be/ble; we also don't have
5780 PIC support in the assembler/linker, so this sequence is needed. */
5781 else if (TARGET_PORTABLE_RUNTIME)
5783 xoperands[0] = call_dest;
5784 /* Get the address of our target into %r29. */
5785 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
5786 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
5788 /* Get our return address into %r31. */
5789 output_asm_insn ("blr %%r0,%3", xoperands);
5791 /* Jump to our target address in %r29. */
5792 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
5794 /* Empty delay slot. Note this insn gets fetched twice and
5795 executed once. To be safe we use a nop. */
5796 output_asm_insn ("nop", xoperands);
5798 /* If we're allowed to use be/ble instructions, then this is the
5799 best sequence to use for a long millicode call. */
5802 xoperands[0] = call_dest;
5803 output_asm_insn ("ldil L%%%0,%3", xoperands);
5804 output_asm_insn ("{ble|be,l} R%%%0(%%sr4,%3)", xoperands);
5805 output_asm_insn ("nop", xoperands);
5808 /* If we had a jump in the call's delay slot, output it now. */
5809 if (dbr_sequence_length () != 0
5810 && !delay_insn_deleted)
5812 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5813 output_asm_insn ("b,n %0", xoperands);
5815 /* Now delete the delay insn. */
5816 PUT_CODE (NEXT_INSN (insn), NOTE);
5817 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5818 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5823 /* This call has an unconditional jump in its delay slot and the
5824 call is known to reach its target or the beginning of the current
5827 /* Use the containing sequence insn's address. */
5828 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5830 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
5831 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
5833 /* If the branch was too far away, emit a normal call followed
5834 by a nop, followed by the unconditional branch.
5836 If the branch is close, then adjust %r2 from within the
5837 call's delay slot. */
5839 xoperands[0] = call_dest;
5840 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5841 if (! VAL_14_BITS_P (distance))
5842 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
5845 xoperands[2] = gen_label_rtx ();
5846 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
5848 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5849 CODE_LABEL_NUMBER (xoperands[2]));
5852 /* Delete the jump. */
5853 PUT_CODE (NEXT_INSN (insn), NOTE);
5854 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5855 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5859 extern struct obstack permanent_obstack;
5861 /* INSN is either a function call. It may have an unconditional jump
5864 CALL_DEST is the routine we are calling. */
5867 output_call (insn, call_dest, sibcall)
5876 /* Handle common case -- empty delay slot or no jump in the delay slot,
5877 and we're sure that the branch will reach the beginning of the $CODE$
5879 if ((dbr_sequence_length () == 0
5880 && get_attr_length (insn) == 8)
5881 || (dbr_sequence_length () != 0
5882 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5883 && get_attr_length (insn) == 4))
5885 xoperands[0] = call_dest;
5886 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
5887 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
5891 /* This call may not reach the beginning of the $CODE$ subspace. */
5892 if (get_attr_length (insn) > 8)
5894 int delay_insn_deleted = 0;
5898 /* We need to emit an inline long-call branch. Furthermore,
5899 because we're changing a named function call into an indirect
5900 function call well after the parameters have been set up, we
5901 need to make sure any FP args appear in both the integer
5902 and FP registers. Also, we need move any delay slot insn
5903 out of the delay slot. And finally, we can't rely on the linker
5904 being able to fix the call to $$dyncall! -- Yuk!. */
5905 if (dbr_sequence_length () != 0
5906 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5908 /* A non-jump insn in the delay slot. By definition we can
5909 emit this insn before the call (and in fact before argument
5911 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5913 /* Now delete the delay insn. */
5914 PUT_CODE (NEXT_INSN (insn), NOTE);
5915 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5916 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5917 delay_insn_deleted = 1;
5920 /* Now copy any FP arguments into integer registers. */
5921 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
5923 int arg_mode, regno;
5924 rtx use = XEXP (link, 0);
5925 if (! (GET_CODE (use) == USE
5926 && GET_CODE (XEXP (use, 0)) == REG
5927 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5930 arg_mode = GET_MODE (XEXP (use, 0));
5931 regno = REGNO (XEXP (use, 0));
5932 /* Is it a floating point register? */
5933 if (regno >= 32 && regno <= 39)
5935 /* Copy from the FP register into an integer register
5937 if (arg_mode == SFmode)
5939 xoperands[0] = XEXP (use, 0);
5940 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
5941 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
5943 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5947 xoperands[0] = XEXP (use, 0);
5948 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
5949 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
5951 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
5952 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5957 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5958 we don't have any direct calls in that case. */
5961 const char *name = XSTR (call_dest, 0);
5963 /* See if we have already put this function on the list
5964 of deferred plabels. This list is generally small,
5965 so a liner search is not too ugly. If it proves too
5966 slow replace it with something faster. */
5967 for (i = 0; i < n_deferred_plabels; i++)
5968 if (strcmp (name, deferred_plabels[i].name) == 0)
5971 /* If the deferred plabel list is empty, or this entry was
5972 not found on the list, create a new entry on the list. */
5973 if (deferred_plabels == NULL || i == n_deferred_plabels)
5975 const char *real_name;
5977 if (deferred_plabels == 0)
5978 deferred_plabels = (struct deferred_plabel *)
5979 xmalloc (1 * sizeof (struct deferred_plabel));
5981 deferred_plabels = (struct deferred_plabel *)
5982 xrealloc (deferred_plabels,
5983 ((n_deferred_plabels + 1)
5984 * sizeof (struct deferred_plabel)));
5986 i = n_deferred_plabels++;
5987 deferred_plabels[i].internal_label = gen_label_rtx ();
5988 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
5990 strcpy (deferred_plabels[i].name, name);
5992 /* Gross. We have just implicitly taken the address of this
5993 function, mark it as such. */
5994 STRIP_NAME_ENCODING (real_name, name);
5995 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5998 /* We have to load the address of the function using a procedure
5999 label (plabel). Inline plabels can lose for PIC and other
6000 cases, so avoid them by creating a 32bit plabel in the data
6004 xoperands[0] = deferred_plabels[i].internal_label;
6005 xoperands[1] = gen_label_rtx ();
6007 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
6008 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
6009 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
6011 /* Get our address + 8 into %r1. */
6012 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6014 /* Add %r1 to the offset of dyncall from the next insn. */
6015 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
6016 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6017 CODE_LABEL_NUMBER (xoperands[1]));
6018 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
6020 /* Get the return address into %r31. */
6021 output_asm_insn ("blr %%r0,%%r31", xoperands);
6023 /* Branch to our target which is in %r1. */
6024 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6028 /* This call never returns, so we do not need to fix the
6030 output_asm_insn ("nop", xoperands);
6034 /* Copy the return address into %r2 also. */
6035 output_asm_insn ("copy %%r31,%%r2", xoperands);
6040 xoperands[0] = deferred_plabels[i].internal_label;
6042 /* Get the address of our target into %r22. */
6043 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
6044 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
6046 /* Get the high part of the address of $dyncall into %r2, then
6047 add in the low part in the branch instruction. */
6048 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
6049 output_asm_insn ("{ble|be,l} R%%$$dyncall(%%sr4,%%r2)",
6054 /* This call never returns, so we do not need to fix the
6056 output_asm_insn ("nop", xoperands);
6060 /* Copy the return address into %r2 also. */
6061 output_asm_insn ("copy %%r31,%%r2", xoperands);
6066 /* If we had a jump in the call's delay slot, output it now. */
6067 if (dbr_sequence_length () != 0
6068 && !delay_insn_deleted)
6070 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6071 output_asm_insn ("b,n %0", xoperands);
6073 /* Now delete the delay insn. */
6074 PUT_CODE (NEXT_INSN (insn), NOTE);
6075 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6076 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6081 /* This call has an unconditional jump in its delay slot and the
6082 call is known to reach its target or the beginning of the current
6085 /* Use the containing sequence insn's address. */
6086 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6088 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6089 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6091 /* If the branch was too far away, emit a normal call followed
6092 by a nop, followed by the unconditional branch.
6094 If the branch is close, then adjust %r2 from within the
6095 call's delay slot. */
6097 xoperands[0] = call_dest;
6098 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6099 if (! VAL_14_BITS_P (distance))
6100 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
6103 xoperands[3] = gen_label_rtx ();
6104 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6106 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6107 CODE_LABEL_NUMBER (xoperands[3]));
6110 /* Delete the jump. */
6111 PUT_CODE (NEXT_INSN (insn), NOTE);
6112 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6113 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6117 /* In HPUX 8.0's shared library scheme, special relocations are needed
6118 for function labels if they might be passed to a function
6119 in a shared library (because shared libraries don't live in code
6120 space), and special magic is needed to construct their address. */
6123 hppa_encode_label (sym)
6126 const char *str = XSTR (sym, 0);
6127 int len = strlen (str) + 1;
6130 p = newstr = alloca (len + 1);
6139 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6143 function_label_operand (op, mode)
6145 enum machine_mode mode ATTRIBUTE_UNUSED;
6147 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6150 /* Returns 1 if OP is a function label involved in a simple addition
6151 with a constant. Used to keep certain patterns from matching
6152 during instruction combination. */
6154 is_function_label_plus_const (op)
6157 /* Strip off any CONST. */
6158 if (GET_CODE (op) == CONST)
6161 return (GET_CODE (op) == PLUS
6162 && function_label_operand (XEXP (op, 0), Pmode)
6163 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6166 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6167 use in fmpyadd instructions. */
6169 fmpyaddoperands (operands)
6172 enum machine_mode mode = GET_MODE (operands[0]);
6174 /* Must be a floating point mode. */
6175 if (mode != SFmode && mode != DFmode)
6178 /* All modes must be the same. */
6179 if (! (mode == GET_MODE (operands[1])
6180 && mode == GET_MODE (operands[2])
6181 && mode == GET_MODE (operands[3])
6182 && mode == GET_MODE (operands[4])
6183 && mode == GET_MODE (operands[5])))
6186 /* All operands must be registers. */
6187 if (! (GET_CODE (operands[1]) == REG
6188 && GET_CODE (operands[2]) == REG
6189 && GET_CODE (operands[3]) == REG
6190 && GET_CODE (operands[4]) == REG
6191 && GET_CODE (operands[5]) == REG))
6194 /* Only 2 real operands to the addition. One of the input operands must
6195 be the same as the output operand. */
6196 if (! rtx_equal_p (operands[3], operands[4])
6197 && ! rtx_equal_p (operands[3], operands[5]))
6200 /* Inout operand of add can not conflict with any operands from multiply. */
6201 if (rtx_equal_p (operands[3], operands[0])
6202 || rtx_equal_p (operands[3], operands[1])
6203 || rtx_equal_p (operands[3], operands[2]))
6206 /* multiply can not feed into addition operands. */
6207 if (rtx_equal_p (operands[4], operands[0])
6208 || rtx_equal_p (operands[5], operands[0]))
6211 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6213 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6214 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6215 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6216 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6217 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6218 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6221 /* Passed. Operands are suitable for fmpyadd. */
6225 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6226 use in fmpysub instructions. */
6228 fmpysuboperands (operands)
6231 enum machine_mode mode = GET_MODE (operands[0]);
6233 /* Must be a floating point mode. */
6234 if (mode != SFmode && mode != DFmode)
6237 /* All modes must be the same. */
6238 if (! (mode == GET_MODE (operands[1])
6239 && mode == GET_MODE (operands[2])
6240 && mode == GET_MODE (operands[3])
6241 && mode == GET_MODE (operands[4])
6242 && mode == GET_MODE (operands[5])))
6245 /* All operands must be registers. */
6246 if (! (GET_CODE (operands[1]) == REG
6247 && GET_CODE (operands[2]) == REG
6248 && GET_CODE (operands[3]) == REG
6249 && GET_CODE (operands[4]) == REG
6250 && GET_CODE (operands[5]) == REG))
6253 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6254 operation, so operands[4] must be the same as operand[3]. */
6255 if (! rtx_equal_p (operands[3], operands[4]))
6258 /* multiply can not feed into subtraction. */
6259 if (rtx_equal_p (operands[5], operands[0]))
6262 /* Inout operand of sub can not conflict with any operands from multiply. */
6263 if (rtx_equal_p (operands[3], operands[0])
6264 || rtx_equal_p (operands[3], operands[1])
6265 || rtx_equal_p (operands[3], operands[2]))
6268 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6270 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6271 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6272 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6273 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6274 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6275 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6278 /* Passed. Operands are suitable for fmpysub. */
6283 plus_xor_ior_operator (op, mode)
6285 enum machine_mode mode ATTRIBUTE_UNUSED;
6287 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6288 || GET_CODE (op) == IOR);
6291 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6292 constants for shadd instructions. */
6294 shadd_constant_p (val)
6297 if (val == 2 || val == 4 || val == 8)
6303 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6304 the valid constant for shadd instructions. */
6306 shadd_operand (op, mode)
6308 enum machine_mode mode ATTRIBUTE_UNUSED;
6310 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6313 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6316 basereg_operand (op, mode)
6318 enum machine_mode mode;
6320 /* cse will create some unscaled indexed addresses, however; it
6321 generally isn't a win on the PA, so avoid creating unscaled
6322 indexed addresses until after cse is finished. */
6323 if (!cse_not_expected)
6326 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6327 we don't have to worry about the braindamaged implicit space
6328 register selection from the basereg. */
6329 if (TARGET_NO_SPACE_REGS)
6330 return (GET_CODE (op) == REG);
6332 /* While it's always safe to index off the frame pointer, it's not
6333 always profitable, particularly when the frame pointer is being
6335 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6338 return (GET_CODE (op) == REG
6340 && register_operand (op, mode));
6343 /* Return 1 if this operand is anything other than a hard register. */
6346 non_hard_reg_operand (op, mode)
6348 enum machine_mode mode ATTRIBUTE_UNUSED;
6350 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6353 /* Return 1 if INSN branches forward. Should be using insn_addresses
6354 to avoid walking through all the insns... */
6356 forward_branch_p (insn)
6359 rtx label = JUMP_LABEL (insn);
6366 insn = NEXT_INSN (insn);
6369 return (insn == label);
6372 /* Return 1 if OP is an equality comparison, else return 0. */
6374 eq_neq_comparison_operator (op, mode)
6376 enum machine_mode mode ATTRIBUTE_UNUSED;
6378 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6381 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6383 movb_comparison_operator (op, mode)
6385 enum machine_mode mode ATTRIBUTE_UNUSED;
6387 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6388 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6391 /* Return 1 if INSN is in the delay slot of a call instruction. */
6393 jump_in_call_delay (insn)
6397 if (GET_CODE (insn) != JUMP_INSN)
6400 if (PREV_INSN (insn)
6401 && PREV_INSN (PREV_INSN (insn))
6402 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6404 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6406 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6407 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6414 /* Output an unconditional move and branch insn. */
6417 output_parallel_movb (operands, length)
6421 /* These are the cases in which we win. */
6423 return "mov%I1b,tr %1,%0,%2";
6425 /* None of these cases wins, but they don't lose either. */
6426 if (dbr_sequence_length () == 0)
6428 /* Nothing in the delay slot, fake it by putting the combined
6429 insn (the copy or add) in the delay slot of a bl. */
6430 if (GET_CODE (operands[1]) == CONST_INT)
6431 return "b %2\n\tldi %1,%0";
6433 return "b %2\n\tcopy %1,%0";
6437 /* Something in the delay slot, but we've got a long branch. */
6438 if (GET_CODE (operands[1]) == CONST_INT)
6439 return "ldi %1,%0\n\tb %2";
6441 return "copy %1,%0\n\tb %2";
6445 /* Output an unconditional add and branch insn. */
6448 output_parallel_addb (operands, length)
6452 /* To make life easy we want operand0 to be the shared input/output
6453 operand and operand1 to be the readonly operand. */
6454 if (operands[0] == operands[1])
6455 operands[1] = operands[2];
6457 /* These are the cases in which we win. */
6459 return "add%I1b,tr %1,%0,%3";
6461 /* None of these cases win, but they don't lose either. */
6462 if (dbr_sequence_length () == 0)
6464 /* Nothing in the delay slot, fake it by putting the combined
6465 insn (the copy or add) in the delay slot of a bl. */
6466 return "b %3\n\tadd%I1 %1,%0,%0";
6470 /* Something in the delay slot, but we've got a long branch. */
6471 return "add%I1 %1,%0,%0\n\tb %3";
6475 /* Return nonzero if INSN (a jump insn) immediately follows a call to
6476 a named function. This is used to discourage creating parallel movb/addb
6477 insns since a jump which immediately follows a call can execute in the
6478 delay slot of the call.
6480 It is also used to avoid filling the delay slot of a jump which
6481 immediately follows a call since the jump can usually be eliminated
6482 completely by modifying RP in the delay slot of the call. */
6485 following_call (insn)
6488 /* We do not parallel movb,addb or place jumps into call delay slots when
6489 optimizing for the PA8000. */
6490 if (pa_cpu != PROCESSOR_8000)
6493 /* Find the previous real insn, skipping NOTEs. */
6494 insn = PREV_INSN (insn);
6495 while (insn && GET_CODE (insn) == NOTE)
6496 insn = PREV_INSN (insn);
6498 /* Check for CALL_INSNs and millicode calls. */
6500 && ((GET_CODE (insn) == CALL_INSN
6501 && get_attr_type (insn) != TYPE_DYNCALL)
6502 || (GET_CODE (insn) == INSN
6503 && GET_CODE (PATTERN (insn)) != SEQUENCE
6504 && GET_CODE (PATTERN (insn)) != USE
6505 && GET_CODE (PATTERN (insn)) != CLOBBER
6506 && get_attr_type (insn) == TYPE_MILLI)))
6512 /* We use this hook to perform a PA specific optimization which is difficult
6513 to do in earlier passes.
6515 We want the delay slots of branches within jump tables to be filled.
6516 None of the compiler passes at the moment even has the notion that a
6517 PA jump table doesn't contain addresses, but instead contains actual
6520 Because we actually jump into the table, the addresses of each entry
6521 must stay constant in relation to the beginning of the table (which
6522 itself must stay constant relative to the instruction to jump into
6523 it). I don't believe we can guarantee earlier passes of the compiler
6524 will adhere to those rules.
6526 So, late in the compilation process we find all the jump tables, and
6527 expand them into real code -- eg each entry in the jump table vector
6528 will get an appropriate label followed by a jump to the final target.
6530 Reorg and the final jump pass can then optimize these branches and
6531 fill their delay slots. We end up with smaller, more efficient code.
6533 The jump instructions within the table are special; we must be able
6534 to identify them during assembly output (if the jumps don't get filled
6535 we need to emit a nop rather than nullifying the delay slot)). We
6536 identify jumps in switch tables by marking the SET with DImode.
6538 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6539 insns. This serves two purposes, first it prevents jump.c from
6540 noticing that the last N entries in the table jump to the instruction
6541 immediately after the table and deleting the jumps. Second, those
6542 insns mark where we should emit .begin_brtab and .end_brtab directives
6543 when using GAS (allows for better link time optimizations). */
6551 remove_useless_addtr_insns (insns, 1);
6553 if (pa_cpu < PROCESSOR_8000)
6554 pa_combine_instructions (get_insns ());
6557 /* This is fairly cheap, so always run it if optimizing. */
6558 if (optimize > 0 && !TARGET_BIG_SWITCH)
6560 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6561 insns = get_insns ();
6562 for (insn = insns; insn; insn = NEXT_INSN (insn))
6564 rtx pattern, tmp, location;
6565 unsigned int length, i;
6567 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6568 if (GET_CODE (insn) != JUMP_INSN
6569 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6570 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6573 /* Emit marker for the beginning of the branch table. */
6574 emit_insn_before (gen_begin_brtab (), insn);
6576 pattern = PATTERN (insn);
6577 location = PREV_INSN (insn);
6578 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6580 for (i = 0; i < length; i++)
6582 /* Emit a label before each jump to keep jump.c from
6583 removing this code. */
6584 tmp = gen_label_rtx ();
6585 LABEL_NUSES (tmp) = 1;
6586 emit_label_after (tmp, location);
6587 location = NEXT_INSN (location);
6589 if (GET_CODE (pattern) == ADDR_VEC)
6591 /* Emit the jump itself. */
6592 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
6593 tmp = emit_jump_insn_after (tmp, location);
6594 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
6595 /* It is easy to rely on the branch table markers
6596 during assembly output to trigger the correct code
6597 for a switch table jump with an unfilled delay slot,
6599 However, that requires state and assumes that we look
6602 We can't make such assumptions when computing the length
6603 of instructions. Ugh. We could walk the insn chain to
6604 determine if this instruction is in a branch table, but
6605 that can get rather expensive, particularly during the
6606 branch shortening phase of the compiler.
6608 So instead we mark this jump as being special. This is
6609 far from ideal and knows that no code after this will
6610 muck around with the mode of the JUMP_INSN itself. */
6611 PUT_MODE (tmp, SImode);
6612 LABEL_NUSES (JUMP_LABEL (tmp))++;
6613 location = NEXT_INSN (location);
6617 /* Emit the jump itself. */
6618 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
6619 tmp = emit_jump_insn_after (tmp, location);
6620 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
6621 /* It is easy to rely on the branch table markers
6622 during assembly output to trigger the correct code
6623 for a switch table jump with an unfilled delay slot,
6625 However, that requires state and assumes that we look
6628 We can't make such assumptions when computing the length
6629 of instructions. Ugh. We could walk the insn chain to
6630 determine if this instruction is in a branch table, but
6631 that can get rather expensive, particularly during the
6632 branch shortening phase of the compiler.
6634 So instead we mark this jump as being special. This is
6635 far from ideal and knows that no code after this will
6636 muck around with the mode of the JUMP_INSN itself. */
6637 PUT_MODE (tmp, SImode);
6638 LABEL_NUSES (JUMP_LABEL (tmp))++;
6639 location = NEXT_INSN (location);
6642 /* Emit a BARRIER after the jump. */
6643 emit_barrier_after (location);
6644 location = NEXT_INSN (location);
6647 /* Emit marker for the end of the branch table. */
6648 emit_insn_before (gen_end_brtab (), location);
6649 location = NEXT_INSN (location);
6650 emit_barrier_after (location);
6652 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6658 /* Sill need an end_brtab insn. */
6659 insns = get_insns ();
6660 for (insn = insns; insn; insn = NEXT_INSN (insn))
6662 /* Find an ADDR_VEC insn. */
6663 if (GET_CODE (insn) != JUMP_INSN
6664 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6665 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6668 /* Now generate markers for the beginning and end of the
6670 emit_insn_before (gen_begin_brtab (), insn);
6671 emit_insn_after (gen_end_brtab (), insn);
6676 /* The PA has a number of odd instructions which can perform multiple
6677 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6678 it may be profitable to combine two instructions into one instruction
6679 with two outputs. It's not profitable PA2.0 machines because the
6680 two outputs would take two slots in the reorder buffers.
6682 This routine finds instructions which can be combined and combines
6683 them. We only support some of the potential combinations, and we
6684 only try common ways to find suitable instructions.
6686 * addb can add two registers or a register and a small integer
6687 and jump to a nearby (+-8k) location. Normally the jump to the
6688 nearby location is conditional on the result of the add, but by
6689 using the "true" condition we can make the jump unconditional.
6690 Thus addb can perform two independent operations in one insn.
6692 * movb is similar to addb in that it can perform a reg->reg
6693 or small immediate->reg copy and jump to a nearby (+-8k location).
6695 * fmpyadd and fmpysub can perform a FP multiply and either an
6696 FP add or FP sub if the operands of the multiply and add/sub are
6697 independent (there are other minor restrictions). Note both
6698 the fmpy and fadd/fsub can in theory move to better spots according
6699 to data dependencies, but for now we require the fmpy stay at a
6702 * Many of the memory operations can perform pre & post updates
6703 of index registers. GCC's pre/post increment/decrement addressing
6704 is far too simple to take advantage of all the possibilities. This
6705 pass may not be suitable since those insns may not be independent.
6707 * comclr can compare two ints or an int and a register, nullify
6708 the following instruction and zero some other register. This
6709 is more difficult to use as it's harder to find an insn which
6710 will generate a comclr than finding something like an unconditional
6711 branch. (conditional moves & long branches create comclr insns).
6713 * Most arithmetic operations can conditionally skip the next
6714 instruction. They can be viewed as "perform this operation
6715 and conditionally jump to this nearby location" (where nearby
6716 is an insns away). These are difficult to use due to the
6717 branch length restrictions. */
6720 pa_combine_instructions (insns)
6721 rtx insns ATTRIBUTE_UNUSED;
6725 /* This can get expensive since the basic algorithm is on the
6726 order of O(n^2) (or worse). Only do it for -O2 or higher
6727 levels of optimization. */
6731 /* Walk down the list of insns looking for "anchor" insns which
6732 may be combined with "floating" insns. As the name implies,
6733 "anchor" instructions don't move, while "floating" insns may
6735 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
6736 new = make_insn_raw (new);
6738 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
6740 enum attr_pa_combine_type anchor_attr;
6741 enum attr_pa_combine_type floater_attr;
6743 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6744 Also ignore any special USE insns. */
6745 if ((GET_CODE (anchor) != INSN
6746 && GET_CODE (anchor) != JUMP_INSN
6747 && GET_CODE (anchor) != CALL_INSN)
6748 || GET_CODE (PATTERN (anchor)) == USE
6749 || GET_CODE (PATTERN (anchor)) == CLOBBER
6750 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
6751 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
6754 anchor_attr = get_attr_pa_combine_type (anchor);
6755 /* See if anchor is an insn suitable for combination. */
6756 if (anchor_attr == PA_COMBINE_TYPE_FMPY
6757 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
6758 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6759 && ! forward_branch_p (anchor)))
6763 for (floater = PREV_INSN (anchor);
6765 floater = PREV_INSN (floater))
6767 if (GET_CODE (floater) == NOTE
6768 || (GET_CODE (floater) == INSN
6769 && (GET_CODE (PATTERN (floater)) == USE
6770 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6773 /* Anything except a regular INSN will stop our search. */
6774 if (GET_CODE (floater) != INSN
6775 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6776 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6782 /* See if FLOATER is suitable for combination with the
6784 floater_attr = get_attr_pa_combine_type (floater);
6785 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6786 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6787 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6788 && floater_attr == PA_COMBINE_TYPE_FMPY))
6790 /* If ANCHOR and FLOATER can be combined, then we're
6791 done with this pass. */
6792 if (pa_can_combine_p (new, anchor, floater, 0,
6793 SET_DEST (PATTERN (floater)),
6794 XEXP (SET_SRC (PATTERN (floater)), 0),
6795 XEXP (SET_SRC (PATTERN (floater)), 1)))
6799 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6800 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
6802 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
6804 if (pa_can_combine_p (new, anchor, floater, 0,
6805 SET_DEST (PATTERN (floater)),
6806 XEXP (SET_SRC (PATTERN (floater)), 0),
6807 XEXP (SET_SRC (PATTERN (floater)), 1)))
6812 if (pa_can_combine_p (new, anchor, floater, 0,
6813 SET_DEST (PATTERN (floater)),
6814 SET_SRC (PATTERN (floater)),
6815 SET_SRC (PATTERN (floater))))
6821 /* If we didn't find anything on the backwards scan try forwards. */
6823 && (anchor_attr == PA_COMBINE_TYPE_FMPY
6824 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
6826 for (floater = anchor; floater; floater = NEXT_INSN (floater))
6828 if (GET_CODE (floater) == NOTE
6829 || (GET_CODE (floater) == INSN
6830 && (GET_CODE (PATTERN (floater)) == USE
6831 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6835 /* Anything except a regular INSN will stop our search. */
6836 if (GET_CODE (floater) != INSN
6837 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6838 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6844 /* See if FLOATER is suitable for combination with the
6846 floater_attr = get_attr_pa_combine_type (floater);
6847 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6848 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6849 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6850 && floater_attr == PA_COMBINE_TYPE_FMPY))
6852 /* If ANCHOR and FLOATER can be combined, then we're
6853 done with this pass. */
6854 if (pa_can_combine_p (new, anchor, floater, 1,
6855 SET_DEST (PATTERN (floater)),
6856 XEXP (SET_SRC (PATTERN (floater)),
6858 XEXP (SET_SRC (PATTERN (floater)),
6865 /* FLOATER will be nonzero if we found a suitable floating
6866 insn for combination with ANCHOR. */
6868 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6869 || anchor_attr == PA_COMBINE_TYPE_FMPY))
6871 /* Emit the new instruction and delete the old anchor. */
6872 emit_insn_before (gen_rtx_PARALLEL
6874 gen_rtvec (2, PATTERN (anchor),
6875 PATTERN (floater))),
6878 PUT_CODE (anchor, NOTE);
6879 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6880 NOTE_SOURCE_FILE (anchor) = 0;
6882 /* Emit a special USE insn for FLOATER, then delete
6883 the floating insn. */
6884 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6885 delete_insn (floater);
6890 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
6893 /* Emit the new_jump instruction and delete the old anchor. */
6895 = emit_jump_insn_before (gen_rtx_PARALLEL
6897 gen_rtvec (2, PATTERN (anchor),
6898 PATTERN (floater))),
6901 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
6902 PUT_CODE (anchor, NOTE);
6903 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6904 NOTE_SOURCE_FILE (anchor) = 0;
6906 /* Emit a special USE insn for FLOATER, then delete
6907 the floating insn. */
6908 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6909 delete_insn (floater);
6917 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
6918 rtx new, anchor, floater;
6920 rtx dest, src1, src2;
6922 int insn_code_number;
6925 /* Create a PARALLEL with the patterns of ANCHOR and
6926 FLOATER, try to recognize it, then test constraints
6927 for the resulting pattern.
6929 If the pattern doesn't match or the constraints
6930 aren't met keep searching for a suitable floater
6932 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
6933 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
6934 INSN_CODE (new) = -1;
6935 insn_code_number = recog_memoized (new);
6936 if (insn_code_number < 0
6937 || !constrain_operands (1))
6951 /* There's up to three operands to consider. One
6952 output and two inputs.
6954 The output must not be used between FLOATER & ANCHOR
6955 exclusive. The inputs must not be set between
6956 FLOATER and ANCHOR exclusive. */
6958 if (reg_used_between_p (dest, start, end))
6961 if (reg_set_between_p (src1, start, end))
6964 if (reg_set_between_p (src2, start, end))
6967 /* If we get here, then everything is good. */
6971 /* Return nonzero if references for INSN are delayed.
6973 Millicode insns are actually function calls with some special
6974 constraints on arguments and register usage.
6976 Millicode calls always expect their arguments in the integer argument
6977 registers, and always return their result in %r29 (ret1). They
6978 are expected to clobber their arguments, %r1, %r29, and the return
6979 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
6981 This function tells reorg that the references to arguments and
6982 millicode calls do not appear to happen until after the millicode call.
6983 This allows reorg to put insns which set the argument registers into the
6984 delay slot of the millicode call -- thus they act more like traditional
6987 Note we can not consider side effects of the insn to be delayed because
6988 the branch and link insn will clobber the return pointer. If we happened
6989 to use the return pointer in the delay slot of the call, then we lose.
6991 get_attr_type will try to recognize the given insn, so make sure to
6992 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
6995 insn_refs_are_delayed (insn)
6998 return ((GET_CODE (insn) == INSN
6999 && GET_CODE (PATTERN (insn)) != SEQUENCE
7000 && GET_CODE (PATTERN (insn)) != USE
7001 && GET_CODE (PATTERN (insn)) != CLOBBER
7002 && get_attr_type (insn) == TYPE_MILLI));
7005 /* Return the location of a parameter that is passed in a register or NULL
7006 if the parameter has any component that is passed in memory.
7008 This is new code and will be pushed to into the net sources after
7011 ??? We might want to restructure this so that it looks more like other
7014 function_arg (cum, mode, type, named, incoming)
7015 CUMULATIVE_ARGS *cum;
7016 enum machine_mode mode;
7018 int named ATTRIBUTE_UNUSED;
7021 int max_arg_words = (TARGET_64BIT ? 8 : 4);
7028 /* If this arg would be passed partially or totally on the stack, then
7029 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
7030 handle arguments which are split between regs and stack slots if
7031 the ABI mandates split arguments. */
7032 if (cum->words + FUNCTION_ARG_SIZE (mode, type) > max_arg_words
7033 || mode == VOIDmode)
7039 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7041 if (cum->words + offset >= max_arg_words
7042 || mode == VOIDmode)
7046 /* The 32bit ABIs and the 64bit ABIs are rather different,
7047 particularly in their handling of FP registers. We might
7048 be able to cleverly share code between them, but I'm not
7049 going to bother in the hope that splitting them up results
7050 in code that is more easily understood.
7052 The 64bit code probably is very wrong for structure passing. */
7055 /* Advance the base registers to their current locations.
7057 Remember, gprs grow towards smaller register numbers while
7058 fprs grow to higher register numbers. Also remember FP regs
7059 are always 4 bytes wide, while the size of an integer register
7060 varies based on the size of the target word. */
7061 gpr_reg_base = 26 - cum->words;
7062 fpr_reg_base = 32 + cum->words;
7064 /* If the argument is more than a word long, then we need to align
7065 the base registers. Same caveats as above. */
7066 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7068 if (mode != BLKmode)
7070 /* First deal with alignment of the doubleword. */
7071 gpr_reg_base -= (cum->words & 1);
7073 /* This seems backwards, but it is what HP specifies. We need
7074 gpr_reg_base to point to the smaller numbered register of
7075 the integer register pair. So if we have an even register
7076 number, then decrement the gpr base. */
7077 gpr_reg_base -= ((gpr_reg_base % 2) == 0);
7079 /* FP values behave sanely, except that each FP reg is only
7081 fpr_reg_base += ((fpr_reg_base % 2) == 0);
7086 int i, offset = 0, ub;
7087 ub = FUNCTION_ARG_SIZE (mode, type);
7089 MAX (0, max_arg_words - cum->words - (cum->words & 1)));
7090 gpr_reg_base -= (cum->words & 1);
7091 for (i = 0; i < ub; i++)
7093 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7094 gen_rtx_REG (DImode,
7103 return XEXP (loc[0], 0);
7105 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7111 /* If the argument is larger than a word, then we know precisely
7112 which registers we must use. */
7113 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7128 /* We have a single word (32 bits). A simple computation
7129 will get us the register #s we need. */
7130 gpr_reg_base = 26 - cum->words;
7131 fpr_reg_base = 32 + 2 * cum->words;
7135 if (TARGET_64BIT && mode == TFmode)
7141 gen_rtx_EXPR_LIST (VOIDmode,
7142 gen_rtx_REG (DImode, gpr_reg_base + 1),
7144 gen_rtx_EXPR_LIST (VOIDmode,
7145 gen_rtx_REG (DImode, gpr_reg_base),
7148 /* Determine if the argument needs to be passed in both general and
7149 floating point registers. */
7150 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7151 /* If we are doing soft-float with portable runtime, then there
7152 is no need to worry about FP regs. */
7153 && ! TARGET_SOFT_FLOAT
7154 /* The parameter must be some kind of float, else we can just
7155 pass it in integer registers. */
7156 && FLOAT_MODE_P (mode)
7157 /* The target function must not have a prototype. */
7158 && cum->nargs_prototype <= 0
7159 /* libcalls do not need to pass items in both FP and general
7161 && type != NULL_TREE
7162 /* All this hair applies to outgoing args only. */
7164 /* Also pass outgoing floating arguments in both registers in indirect
7165 calls with the 32 bit ABI and the HP assembler since there is no
7166 way to the specify argument locations in static functions. */
7171 && FLOAT_MODE_P (mode)))
7177 gen_rtx_EXPR_LIST (VOIDmode,
7178 gen_rtx_REG (mode, fpr_reg_base),
7180 gen_rtx_EXPR_LIST (VOIDmode,
7181 gen_rtx_REG (mode, gpr_reg_base),
7186 /* See if we should pass this parameter in a general register. */
7187 if (TARGET_SOFT_FLOAT
7188 /* Indirect calls in the normal 32bit ABI require all arguments
7189 to be passed in general registers. */
7190 || (!TARGET_PORTABLE_RUNTIME
7193 /* If the parameter is not a floating point parameter, then
7194 it belongs in GPRs. */
7195 || !FLOAT_MODE_P (mode))
7196 retval = gen_rtx_REG (mode, gpr_reg_base);
7198 retval = gen_rtx_REG (mode, fpr_reg_base);
7204 /* If this arg would be passed totally in registers or totally on the stack,
7205 then this routine should return zero. It is currently called only for
7206 the 64-bit target. */
7208 function_arg_partial_nregs (cum, mode, type, named)
7209 CUMULATIVE_ARGS *cum;
7210 enum machine_mode mode;
7212 int named ATTRIBUTE_UNUSED;
7214 unsigned int max_arg_words = 8;
7215 unsigned int offset = 0;
7217 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7220 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
7221 /* Arg fits fully into registers. */
7223 else if (cum->words + offset >= max_arg_words)
7224 /* Arg fully on the stack. */
7228 return max_arg_words - cum->words - offset;
7232 /* Return 1 if this is a comparison operator. This allows the use of
7233 MATCH_OPERATOR to recognize all the branch insns. */
7236 cmpib_comparison_operator (op, mode)
7238 enum machine_mode mode;
7240 return ((mode == VOIDmode || GET_MODE (op) == mode)
7241 && (GET_CODE (op) == EQ
7242 || GET_CODE (op) == NE
7243 || GET_CODE (op) == GT
7244 || GET_CODE (op) == GTU
7245 || GET_CODE (op) == GE
7246 || GET_CODE (op) == LT
7247 || GET_CODE (op) == LE
7248 || GET_CODE (op) == LEU));
7251 /* Mark ARG (which is really a struct deferred_plabel **) for GC. */
7254 mark_deferred_plabels (arg)
7257 struct deferred_plabel *dp = *(struct deferred_plabel **) arg;
7260 for (i = 0; i < n_deferred_plabels; ++i)
7261 ggc_mark_rtx (dp[i].internal_label);
7264 /* Called to register all of our global variables with the garbage
7270 ggc_add_rtx_root (&hppa_compare_op0, 1);
7271 ggc_add_rtx_root (&hppa_compare_op1, 1);
7272 ggc_add_root (&deferred_plabels, 1, sizeof (&deferred_plabels),
7273 &mark_deferred_plabels);