1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
41 #include "integrate.h"
50 #include "target-def.h"
52 static int hppa_use_dfa_pipeline_interface PARAMS ((void));
54 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
55 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
58 hppa_use_dfa_pipeline_interface ()
63 /* Return nonzero if there is a bypass for the output of
64 OUT_INSN and the fp store IN_INSN. */
66 hppa_fpstore_bypass_p (out_insn, in_insn)
67 rtx out_insn, in_insn;
69 enum machine_mode store_mode;
70 enum machine_mode other_mode;
73 if (recog_memoized (in_insn) < 0
74 || get_attr_type (in_insn) != TYPE_FPSTORE
75 || recog_memoized (out_insn) < 0)
78 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
80 set = single_set (out_insn);
84 other_mode = GET_MODE (SET_SRC (set));
86 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
90 #ifndef DO_FRAME_NOTES
91 #ifdef INCOMING_RETURN_ADDR_RTX
92 #define DO_FRAME_NOTES 1
94 #define DO_FRAME_NOTES 0
98 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
99 static void pa_combine_instructions PARAMS ((rtx));
100 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
101 static int forward_branch_p PARAMS ((rtx));
102 static int shadd_constant_p PARAMS ((int));
103 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
104 static int compute_movstrsi_length PARAMS ((rtx));
105 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
106 static void remove_useless_addtr_insns PARAMS ((rtx, int));
107 static void store_reg PARAMS ((int, int, int));
108 static void store_reg_modify PARAMS ((int, int, int));
109 static void load_reg PARAMS ((int, int, int));
110 static void set_reg_plus_d PARAMS ((int, int, int, int));
111 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
112 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
113 static int pa_adjust_priority PARAMS ((rtx, int));
114 static int pa_issue_rate PARAMS ((void));
115 static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
117 static void pa_encode_section_info PARAMS ((tree, int));
118 static const char *pa_strip_name_encoding PARAMS ((const char *));
120 /* Save the operands last given to a compare for use when we
121 generate a scc or bcc insn. */
123 rtx hppa_compare_op0, hppa_compare_op1;
124 enum cmp_type hppa_branch_type;
126 /* Which cpu we are scheduling for. */
127 enum processor_type pa_cpu;
129 /* String to hold which cpu we are scheduling for. */
130 const char *pa_cpu_string;
132 /* Which architecture we are generating code for. */
133 enum architecture_type pa_arch;
135 /* String to hold which architecture we are generating code for. */
136 const char *pa_arch_string;
138 /* Counts for the number of callee-saved general and floating point
139 registers which were saved by the current function's prologue. */
140 static int gr_saved, fr_saved;
142 static rtx find_addr_reg PARAMS ((rtx));
144 /* Keep track of the number of bytes we have output in the CODE subspaces
145 during this compilation so we'll know when to emit inline long-calls. */
147 unsigned int total_code_bytes;
149 /* Variables to handle plabels that we discover are necessary at assembly
150 output time. They are output after the current function. */
152 struct deferred_plabel GTY(())
157 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
159 static size_t n_deferred_plabels = 0;
161 /* Initialize the GCC target structure. */
163 #undef TARGET_ASM_ALIGNED_HI_OP
164 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
165 #undef TARGET_ASM_ALIGNED_SI_OP
166 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
167 #undef TARGET_ASM_ALIGNED_DI_OP
168 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
169 #undef TARGET_ASM_UNALIGNED_HI_OP
170 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
171 #undef TARGET_ASM_UNALIGNED_SI_OP
172 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
173 #undef TARGET_ASM_UNALIGNED_DI_OP
174 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
175 #undef TARGET_ASM_INTEGER
176 #define TARGET_ASM_INTEGER pa_assemble_integer
178 #undef TARGET_ASM_FUNCTION_PROLOGUE
179 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
180 #undef TARGET_ASM_FUNCTION_EPILOGUE
181 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
183 #undef TARGET_SCHED_ADJUST_COST
184 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
185 #undef TARGET_SCHED_ADJUST_PRIORITY
186 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
187 #undef TARGET_SCHED_ISSUE_RATE
188 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
190 #undef TARGET_ENCODE_SECTION_INFO
191 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
192 #undef TARGET_STRIP_NAME_ENCODING
193 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
195 struct gcc_target targetm = TARGET_INITIALIZER;
200 if (pa_cpu_string == NULL)
201 pa_cpu_string = TARGET_SCHED_DEFAULT;
203 if (! strcmp (pa_cpu_string, "8000"))
205 pa_cpu_string = "8000";
206 pa_cpu = PROCESSOR_8000;
208 else if (! strcmp (pa_cpu_string, "7100"))
210 pa_cpu_string = "7100";
211 pa_cpu = PROCESSOR_7100;
213 else if (! strcmp (pa_cpu_string, "700"))
215 pa_cpu_string = "700";
216 pa_cpu = PROCESSOR_700;
218 else if (! strcmp (pa_cpu_string, "7100LC"))
220 pa_cpu_string = "7100LC";
221 pa_cpu = PROCESSOR_7100LC;
223 else if (! strcmp (pa_cpu_string, "7200"))
225 pa_cpu_string = "7200";
226 pa_cpu = PROCESSOR_7200;
228 else if (! strcmp (pa_cpu_string, "7300"))
230 pa_cpu_string = "7300";
231 pa_cpu = PROCESSOR_7300;
235 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
238 /* Set the instruction set architecture. */
239 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
241 pa_arch_string = "1.0";
242 pa_arch = ARCHITECTURE_10;
243 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
245 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
247 pa_arch_string = "1.1";
248 pa_arch = ARCHITECTURE_11;
249 target_flags &= ~MASK_PA_20;
250 target_flags |= MASK_PA_11;
252 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
254 pa_arch_string = "2.0";
255 pa_arch = ARCHITECTURE_20;
256 target_flags |= MASK_PA_11 | MASK_PA_20;
258 else if (pa_arch_string)
260 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
263 /* Unconditional branches in the delay slot are not compatible with dwarf2
264 call frame information. There is no benefit in using this optimization
265 on PA8000 and later processors. */
266 if (pa_cpu >= PROCESSOR_8000
267 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
268 || flag_unwind_tables)
269 target_flags &= ~MASK_JUMP_IN_DELAY;
271 if (flag_pic && TARGET_PORTABLE_RUNTIME)
273 warning ("PIC code generation is not supported in the portable runtime model\n");
276 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
278 warning ("PIC code generation is not compatible with fast indirect calls\n");
281 if (! TARGET_GAS && write_symbols != NO_DEBUG)
283 warning ("-g is only supported when using GAS on this processor,");
284 warning ("-g option disabled");
285 write_symbols = NO_DEBUG;
288 /* We only support the "big PIC" model now. And we always generate PIC
289 code when in 64bit mode. */
290 if (flag_pic == 1 || TARGET_64BIT)
293 /* We can't guarantee that .dword is available for 32-bit targets. */
294 if (UNITS_PER_WORD == 4)
295 targetm.asm_out.aligned_op.di = NULL;
297 /* The unaligned ops are only available when using GAS. */
300 targetm.asm_out.unaligned_op.hi = NULL;
301 targetm.asm_out.unaligned_op.si = NULL;
302 targetm.asm_out.unaligned_op.di = NULL;
306 /* Return non-zero only if OP is a register of mode MODE,
309 reg_or_0_operand (op, mode)
311 enum machine_mode mode;
313 return (op == CONST0_RTX (mode) || register_operand (op, mode));
316 /* Return non-zero if OP is suitable for use in a call to a named
319 For 2.5 try to eliminate either call_operand_address or
320 function_label_operand, they perform very similar functions. */
322 call_operand_address (op, mode)
324 enum machine_mode mode ATTRIBUTE_UNUSED;
326 return (GET_MODE (op) == word_mode
327 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
330 /* Return 1 if X contains a symbolic expression. We know these
331 expressions will have one of a few well defined forms, so
332 we need only check those forms. */
334 symbolic_expression_p (x)
338 /* Strip off any HIGH. */
339 if (GET_CODE (x) == HIGH)
342 return (symbolic_operand (x, VOIDmode));
346 symbolic_operand (op, mode)
348 enum machine_mode mode ATTRIBUTE_UNUSED;
350 switch (GET_CODE (op))
357 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
358 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
359 && GET_CODE (XEXP (op, 1)) == CONST_INT);
365 /* Return truth value of statement that OP is a symbolic memory
366 operand of mode MODE. */
369 symbolic_memory_operand (op, mode)
371 enum machine_mode mode ATTRIBUTE_UNUSED;
373 if (GET_CODE (op) == SUBREG)
374 op = SUBREG_REG (op);
375 if (GET_CODE (op) != MEM)
378 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
379 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
382 /* Return 1 if the operand is either a register or a memory operand that is
386 reg_or_nonsymb_mem_operand (op, mode)
388 enum machine_mode mode;
390 if (register_operand (op, mode))
393 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
399 /* Return 1 if the operand is either a register, zero, or a memory operand
400 that is not symbolic. */
403 reg_or_0_or_nonsymb_mem_operand (op, mode)
405 enum machine_mode mode;
407 if (register_operand (op, mode))
410 if (op == CONST0_RTX (mode))
413 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
419 /* Return 1 if the operand is a register operand or a non-symbolic memory
420 operand after reload. This predicate is used for branch patterns that
421 internally handle register reloading. We need to accept non-symbolic
422 memory operands after reload to ensure that the pattern is still valid
423 if reload didn't find a hard register for the operand. */
426 reg_before_reload_operand (op, mode)
428 enum machine_mode mode;
430 /* Don't accept a SUBREG since it will need a reload. */
431 if (GET_CODE (op) == SUBREG)
434 if (register_operand (op, mode))
438 && memory_operand (op, mode)
439 && ! symbolic_memory_operand (op, mode))
445 /* Accept any constant that can be moved in one instruction into a
448 cint_ok_for_move (intval)
449 HOST_WIDE_INT intval;
451 /* OK if ldo, ldil, or zdepi, can be used. */
452 return (CONST_OK_FOR_LETTER_P (intval, 'J')
453 || CONST_OK_FOR_LETTER_P (intval, 'N')
454 || CONST_OK_FOR_LETTER_P (intval, 'K'));
457 /* Accept anything that can be moved in one instruction into a general
460 move_operand (op, mode)
462 enum machine_mode mode;
464 if (register_operand (op, mode))
467 if (GET_CODE (op) == CONSTANT_P_RTX)
470 if (GET_CODE (op) == CONST_INT)
471 return cint_ok_for_move (INTVAL (op));
473 if (GET_CODE (op) == SUBREG)
474 op = SUBREG_REG (op);
475 if (GET_CODE (op) != MEM)
480 /* We consider a LO_SUM DLT reference a move_operand now since it has
481 been merged into the normal movsi/movdi patterns. */
482 if (GET_CODE (op) == LO_SUM
483 && GET_CODE (XEXP (op, 0)) == REG
484 && REG_OK_FOR_BASE_P (XEXP (op, 0))
485 && GET_CODE (XEXP (op, 1)) == UNSPEC
486 && GET_MODE (op) == Pmode)
489 /* Since move_operand is only used for source operands, we can always
490 allow scaled indexing! */
491 if (! TARGET_DISABLE_INDEXING
492 && GET_CODE (op) == PLUS
493 && ((GET_CODE (XEXP (op, 0)) == MULT
494 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
495 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
496 && INTVAL (XEXP (XEXP (op, 0), 1))
497 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
498 && GET_CODE (XEXP (op, 1)) == REG)
499 || (GET_CODE (XEXP (op, 1)) == MULT
500 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
501 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
502 && INTVAL (XEXP (XEXP (op, 1), 1))
503 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
504 && GET_CODE (XEXP (op, 0)) == REG)))
507 return memory_address_p (mode, op);
510 /* Accept REG and any CONST_INT that can be moved in one instruction into a
513 reg_or_cint_move_operand (op, mode)
515 enum machine_mode mode;
517 if (register_operand (op, mode))
520 if (GET_CODE (op) == CONST_INT)
521 return cint_ok_for_move (INTVAL (op));
527 pic_label_operand (op, mode)
529 enum machine_mode mode ATTRIBUTE_UNUSED;
534 switch (GET_CODE (op))
540 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
541 && GET_CODE (XEXP (op, 1)) == CONST_INT);
548 fp_reg_operand (op, mode)
550 enum machine_mode mode ATTRIBUTE_UNUSED;
552 return reg_renumber && FP_REG_P (op);
557 /* Return truth value of whether OP can be used as an operand in a
558 three operand arithmetic insn that accepts registers of mode MODE
559 or 14-bit signed integers. */
561 arith_operand (op, mode)
563 enum machine_mode mode;
565 return (register_operand (op, mode)
566 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
569 /* Return truth value of whether OP can be used as an operand in a
570 three operand arithmetic insn that accepts registers of mode MODE
571 or 11-bit signed integers. */
573 arith11_operand (op, mode)
575 enum machine_mode mode;
577 return (register_operand (op, mode)
578 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
581 /* A constant integer suitable for use in a PRE_MODIFY memory
584 pre_cint_operand (op, mode)
586 enum machine_mode mode ATTRIBUTE_UNUSED;
588 return (GET_CODE (op) == CONST_INT
589 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
592 /* A constant integer suitable for use in a POST_MODIFY memory
595 post_cint_operand (op, mode)
597 enum machine_mode mode ATTRIBUTE_UNUSED;
599 return (GET_CODE (op) == CONST_INT
600 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
604 arith_double_operand (op, mode)
606 enum machine_mode mode;
608 return (register_operand (op, mode)
609 || (GET_CODE (op) == CONST_DOUBLE
610 && GET_MODE (op) == mode
611 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
612 && ((CONST_DOUBLE_HIGH (op) >= 0)
613 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
616 /* Return truth value of whether OP is an integer which fits the
617 range constraining immediate operands in three-address insns, or
618 is an integer register. */
621 ireg_or_int5_operand (op, mode)
623 enum machine_mode mode ATTRIBUTE_UNUSED;
625 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
626 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
629 /* Return nonzero if OP is an integer register, else return zero. */
631 ireg_operand (op, mode)
633 enum machine_mode mode ATTRIBUTE_UNUSED;
635 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
638 /* Return truth value of whether OP is an integer which fits the
639 range constraining immediate operands in three-address insns. */
642 int5_operand (op, mode)
644 enum machine_mode mode ATTRIBUTE_UNUSED;
646 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
650 uint5_operand (op, mode)
652 enum machine_mode mode ATTRIBUTE_UNUSED;
654 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
658 int11_operand (op, mode)
660 enum machine_mode mode ATTRIBUTE_UNUSED;
662 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
666 uint32_operand (op, mode)
668 enum machine_mode mode ATTRIBUTE_UNUSED;
670 #if HOST_BITS_PER_WIDE_INT > 32
671 /* All allowed constants will fit a CONST_INT. */
672 return (GET_CODE (op) == CONST_INT
673 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
675 return (GET_CODE (op) == CONST_INT
676 || (GET_CODE (op) == CONST_DOUBLE
677 && CONST_DOUBLE_HIGH (op) == 0));
682 arith5_operand (op, mode)
684 enum machine_mode mode;
686 return register_operand (op, mode) || int5_operand (op, mode);
689 /* True iff zdepi can be used to generate this CONST_INT.
690 zdepi first sign extends a 5 bit signed number to a given field
691 length, then places this field anywhere in a zero. */
694 unsigned HOST_WIDE_INT x;
696 unsigned HOST_WIDE_INT lsb_mask, t;
698 /* This might not be obvious, but it's at least fast.
699 This function is critical; we don't have the time loops would take. */
701 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
702 /* Return true iff t is a power of two. */
703 return ((t & (t - 1)) == 0);
706 /* True iff depi or extru can be used to compute (reg & mask).
707 Accept bit pattern like these:
713 unsigned HOST_WIDE_INT mask;
716 mask += mask & -mask;
717 return (mask & (mask - 1)) == 0;
720 /* True iff depi or extru can be used to compute (reg & OP). */
722 and_operand (op, mode)
724 enum machine_mode mode;
726 return (register_operand (op, mode)
727 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
730 /* True iff depi can be used to compute (reg | MASK). */
733 unsigned HOST_WIDE_INT mask;
735 mask += mask & -mask;
736 return (mask & (mask - 1)) == 0;
739 /* True iff depi can be used to compute (reg | OP). */
741 ior_operand (op, mode)
743 enum machine_mode mode ATTRIBUTE_UNUSED;
745 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
749 lhs_lshift_operand (op, mode)
751 enum machine_mode mode;
753 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
756 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
757 Such values can be the left hand side x in (x << r), using the zvdepi
760 lhs_lshift_cint_operand (op, mode)
762 enum machine_mode mode ATTRIBUTE_UNUSED;
764 unsigned HOST_WIDE_INT x;
765 if (GET_CODE (op) != CONST_INT)
767 x = INTVAL (op) >> 4;
768 return (x & (x + 1)) == 0;
772 arith32_operand (op, mode)
774 enum machine_mode mode;
776 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
780 pc_or_label_operand (op, mode)
782 enum machine_mode mode ATTRIBUTE_UNUSED;
784 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
787 /* Legitimize PIC addresses. If the address is already
788 position-independent, we return ORIG. Newly generated
789 position-independent addresses go to REG. If we need more
790 than one register, we lose. */
793 legitimize_pic_address (orig, mode, reg)
795 enum machine_mode mode;
799 /* Labels need special handling. */
800 if (pic_label_operand (orig, mode))
802 /* We do not want to go through the movXX expanders here since that
803 would create recursion.
805 Nor do we really want to call a generator for a named pattern
806 since that requires multiple patterns if we want to support
809 So instead we just emit the raw set, which avoids the movXX
810 expanders completely. */
811 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
812 current_function_uses_pic_offset_table = 1;
815 if (GET_CODE (orig) == SYMBOL_REF)
821 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
822 gen_rtx_HIGH (word_mode, orig)));
824 = gen_rtx_MEM (Pmode,
825 gen_rtx_LO_SUM (Pmode, reg,
826 gen_rtx_UNSPEC (Pmode,
830 current_function_uses_pic_offset_table = 1;
831 RTX_UNCHANGING_P (pic_ref) = 1;
832 emit_move_insn (reg, pic_ref);
835 else if (GET_CODE (orig) == CONST)
839 if (GET_CODE (XEXP (orig, 0)) == PLUS
840 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
846 if (GET_CODE (XEXP (orig, 0)) == PLUS)
848 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
849 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
850 base == reg ? 0 : reg);
853 if (GET_CODE (orig) == CONST_INT)
855 if (INT_14_BITS (orig))
856 return plus_constant (base, INTVAL (orig));
857 orig = force_reg (Pmode, orig);
859 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
860 /* Likewise, should we set special REG_NOTEs here? */
865 /* Try machine-dependent ways of modifying an illegitimate address
866 to be legitimate. If we find one, return the new, valid address.
867 This macro is used in only one place: `memory_address' in explow.c.
869 OLDX is the address as it was before break_out_memory_refs was called.
870 In some cases it is useful to look at this to decide what needs to be done.
872 MODE and WIN are passed so that this macro can use
873 GO_IF_LEGITIMATE_ADDRESS.
875 It is always safe for this macro to do nothing. It exists to recognize
876 opportunities to optimize the output.
878 For the PA, transform:
880 memory(X + <large int>)
884 if (<large int> & mask) >= 16
885 Y = (<large int> & ~mask) + mask + 1 Round up.
887 Y = (<large int> & ~mask) Round down.
889 memory (Z + (<large int> - Y));
891 This is for CSE to find several similar references, and only use one Z.
893 X can either be a SYMBOL_REF or REG, but because combine can not
894 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
895 D will not fit in 14 bits.
897 MODE_FLOAT references allow displacements which fit in 5 bits, so use
900 MODE_INT references allow displacements which fit in 14 bits, so use
903 This relies on the fact that most mode MODE_FLOAT references will use FP
904 registers and most mode MODE_INT references will use integer registers.
905 (In the rare case of an FP register used in an integer MODE, we depend
906 on secondary reloads to clean things up.)
909 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
910 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
911 addressing modes to be used).
913 Put X and Z into registers. Then put the entire expression into
917 hppa_legitimize_address (x, oldx, mode)
918 rtx x, oldx ATTRIBUTE_UNUSED;
919 enum machine_mode mode;
924 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
926 /* Strip off CONST. */
927 if (GET_CODE (x) == CONST)
930 /* Special case. Get the SYMBOL_REF into a register and use indexing.
931 That should always be safe. */
932 if (GET_CODE (x) == PLUS
933 && GET_CODE (XEXP (x, 0)) == REG
934 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
936 rtx reg = force_reg (Pmode, XEXP (x, 1));
937 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
940 /* Note we must reject symbols which represent function addresses
941 since the assembler/linker can't handle arithmetic on plabels. */
942 if (GET_CODE (x) == PLUS
943 && GET_CODE (XEXP (x, 1)) == CONST_INT
944 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
945 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
946 || GET_CODE (XEXP (x, 0)) == REG))
948 rtx int_part, ptr_reg;
950 int offset = INTVAL (XEXP (x, 1));
953 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
954 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
956 /* Choose which way to round the offset. Round up if we
957 are >= halfway to the next boundary. */
958 if ((offset & mask) >= ((mask + 1) / 2))
959 newoffset = (offset & ~ mask) + mask + 1;
961 newoffset = (offset & ~ mask);
963 /* If the newoffset will not fit in 14 bits (ldo), then
964 handling this would take 4 or 5 instructions (2 to load
965 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
966 add the new offset and the SYMBOL_REF.) Combine can
967 not handle 4->2 or 5->2 combinations, so do not create
969 if (! VAL_14_BITS_P (newoffset)
970 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
972 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
975 gen_rtx_HIGH (Pmode, const_part));
978 gen_rtx_LO_SUM (Pmode,
979 tmp_reg, const_part));
983 if (! VAL_14_BITS_P (newoffset))
984 int_part = force_reg (Pmode, GEN_INT (newoffset));
986 int_part = GEN_INT (newoffset);
988 ptr_reg = force_reg (Pmode,
990 force_reg (Pmode, XEXP (x, 0)),
993 return plus_constant (ptr_reg, offset - newoffset);
996 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
998 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
999 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1000 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1001 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
1002 || GET_CODE (XEXP (x, 1)) == SUBREG)
1003 && GET_CODE (XEXP (x, 1)) != CONST)
1005 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1009 if (GET_CODE (reg1) != REG)
1010 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1012 reg2 = XEXP (XEXP (x, 0), 0);
1013 if (GET_CODE (reg2) != REG)
1014 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1016 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1017 gen_rtx_MULT (Pmode,
1023 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1025 Only do so for floating point modes since this is more speculative
1026 and we lose if it's an integer store. */
1027 if (GET_CODE (x) == PLUS
1028 && GET_CODE (XEXP (x, 0)) == PLUS
1029 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1030 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1031 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1032 && (mode == SFmode || mode == DFmode))
1035 /* First, try and figure out what to use as a base register. */
1036 rtx reg1, reg2, base, idx, orig_base;
1038 reg1 = XEXP (XEXP (x, 0), 1);
1043 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1044 then emit_move_sequence will turn on REG_POINTER so we'll know
1045 it's a base register below. */
1046 if (GET_CODE (reg1) != REG)
1047 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1049 if (GET_CODE (reg2) != REG)
1050 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1052 /* Figure out what the base and index are. */
1054 if (GET_CODE (reg1) == REG
1055 && REG_POINTER (reg1))
1058 orig_base = XEXP (XEXP (x, 0), 1);
1059 idx = gen_rtx_PLUS (Pmode,
1060 gen_rtx_MULT (Pmode,
1061 XEXP (XEXP (XEXP (x, 0), 0), 0),
1062 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1065 else if (GET_CODE (reg2) == REG
1066 && REG_POINTER (reg2))
1069 orig_base = XEXP (x, 1);
1076 /* If the index adds a large constant, try to scale the
1077 constant so that it can be loaded with only one insn. */
1078 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1079 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1080 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1081 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1083 /* Divide the CONST_INT by the scale factor, then add it to A. */
1084 int val = INTVAL (XEXP (idx, 1));
1086 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1087 reg1 = XEXP (XEXP (idx, 0), 0);
1088 if (GET_CODE (reg1) != REG)
1089 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1091 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1093 /* We can now generate a simple scaled indexed address. */
1096 (Pmode, gen_rtx_PLUS (Pmode,
1097 gen_rtx_MULT (Pmode, reg1,
1098 XEXP (XEXP (idx, 0), 1)),
1102 /* If B + C is still a valid base register, then add them. */
1103 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1104 && INTVAL (XEXP (idx, 1)) <= 4096
1105 && INTVAL (XEXP (idx, 1)) >= -4096)
1107 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1110 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1112 reg2 = XEXP (XEXP (idx, 0), 0);
1113 if (GET_CODE (reg2) != CONST_INT)
1114 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1116 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1117 gen_rtx_MULT (Pmode,
1123 /* Get the index into a register, then add the base + index and
1124 return a register holding the result. */
1126 /* First get A into a register. */
1127 reg1 = XEXP (XEXP (idx, 0), 0);
1128 if (GET_CODE (reg1) != REG)
1129 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1131 /* And get B into a register. */
1132 reg2 = XEXP (idx, 1);
1133 if (GET_CODE (reg2) != REG)
1134 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1136 reg1 = force_reg (Pmode,
1137 gen_rtx_PLUS (Pmode,
1138 gen_rtx_MULT (Pmode, reg1,
1139 XEXP (XEXP (idx, 0), 1)),
1142 /* Add the result to our base register and return. */
1143 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1147 /* Uh-oh. We might have an address for x[n-100000]. This needs
1148 special handling to avoid creating an indexed memory address
1149 with x-100000 as the base.
1151 If the constant part is small enough, then it's still safe because
1152 there is a guard page at the beginning and end of the data segment.
1154 Scaled references are common enough that we want to try and rearrange the
1155 terms so that we can use indexing for these addresses too. Only
1156 do the optimization for floatint point modes. */
1158 if (GET_CODE (x) == PLUS
1159 && symbolic_expression_p (XEXP (x, 1)))
1161 /* Ugly. We modify things here so that the address offset specified
1162 by the index expression is computed first, then added to x to form
1163 the entire address. */
1165 rtx regx1, regx2, regy1, regy2, y;
1167 /* Strip off any CONST. */
1169 if (GET_CODE (y) == CONST)
1172 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1174 /* See if this looks like
1175 (plus (mult (reg) (shadd_const))
1176 (const (plus (symbol_ref) (const_int))))
1178 Where const_int is small. In that case the const
1179 expression is a valid pointer for indexing.
1181 If const_int is big, but can be divided evenly by shadd_const
1182 and added to (reg). This allows more scaled indexed addresses. */
1183 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1184 && GET_CODE (XEXP (x, 0)) == MULT
1185 && GET_CODE (XEXP (y, 1)) == CONST_INT
1186 && INTVAL (XEXP (y, 1)) >= -4096
1187 && INTVAL (XEXP (y, 1)) <= 4095
1188 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1189 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1191 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1195 if (GET_CODE (reg1) != REG)
1196 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1198 reg2 = XEXP (XEXP (x, 0), 0);
1199 if (GET_CODE (reg2) != REG)
1200 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1202 return force_reg (Pmode,
1203 gen_rtx_PLUS (Pmode,
1204 gen_rtx_MULT (Pmode,
1209 else if ((mode == DFmode || mode == SFmode)
1210 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1211 && GET_CODE (XEXP (x, 0)) == MULT
1212 && GET_CODE (XEXP (y, 1)) == CONST_INT
1213 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1214 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1215 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1218 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1219 / INTVAL (XEXP (XEXP (x, 0), 1))));
1220 regx2 = XEXP (XEXP (x, 0), 0);
1221 if (GET_CODE (regx2) != REG)
1222 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1223 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1227 gen_rtx_PLUS (Pmode,
1228 gen_rtx_MULT (Pmode, regx2,
1229 XEXP (XEXP (x, 0), 1)),
1230 force_reg (Pmode, XEXP (y, 0))));
1232 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1233 && INTVAL (XEXP (y, 1)) >= -4096
1234 && INTVAL (XEXP (y, 1)) <= 4095)
1236 /* This is safe because of the guard page at the
1237 beginning and end of the data space. Just
1238 return the original address. */
1243 /* Doesn't look like one we can optimize. */
1244 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1245 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1246 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1247 regx1 = force_reg (Pmode,
1248 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1250 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1258 /* For the HPPA, REG and REG+CONST is cost 0
1259 and addresses involving symbolic constants are cost 2.
1261 PIC addresses are very expensive.
1263 It is no coincidence that this has the same structure
1264 as GO_IF_LEGITIMATE_ADDRESS. */
1266 hppa_address_cost (X)
1269 if (GET_CODE (X) == PLUS)
1271 else if (GET_CODE (X) == LO_SUM)
1273 else if (GET_CODE (X) == HIGH)
1278 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1279 new rtx with the correct mode. */
1281 force_mode (mode, orig)
1282 enum machine_mode mode;
1285 if (mode == GET_MODE (orig))
1288 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1291 return gen_rtx_REG (mode, REGNO (orig));
1294 /* Emit insns to move operands[1] into operands[0].
1296 Return 1 if we have written out everything that needs to be done to
1297 do the move. Otherwise, return 0 and the caller will emit the move
1300 Note SCRATCH_REG may not be in the proper mode depending on how it
1301 will be used. This routine is resposible for creating a new copy
1302 of SCRATCH_REG in the proper mode. */
1305 emit_move_sequence (operands, mode, scratch_reg)
1307 enum machine_mode mode;
1310 register rtx operand0 = operands[0];
1311 register rtx operand1 = operands[1];
1315 && reload_in_progress && GET_CODE (operand0) == REG
1316 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1317 operand0 = reg_equiv_mem[REGNO (operand0)];
1318 else if (scratch_reg
1319 && reload_in_progress && GET_CODE (operand0) == SUBREG
1320 && GET_CODE (SUBREG_REG (operand0)) == REG
1321 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1323 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1324 the code which tracks sets/uses for delete_output_reload. */
1325 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1326 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1327 SUBREG_BYTE (operand0));
1328 operand0 = alter_subreg (&temp);
1332 && reload_in_progress && GET_CODE (operand1) == REG
1333 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1334 operand1 = reg_equiv_mem[REGNO (operand1)];
1335 else if (scratch_reg
1336 && reload_in_progress && GET_CODE (operand1) == SUBREG
1337 && GET_CODE (SUBREG_REG (operand1)) == REG
1338 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1340 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1341 the code which tracks sets/uses for delete_output_reload. */
1342 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1343 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1344 SUBREG_BYTE (operand1));
1345 operand1 = alter_subreg (&temp);
1348 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1349 && ((tem = find_replacement (&XEXP (operand0, 0)))
1350 != XEXP (operand0, 0)))
1351 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1352 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1353 && ((tem = find_replacement (&XEXP (operand1, 0)))
1354 != XEXP (operand1, 0)))
1355 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1357 /* Handle secondary reloads for loads/stores of FP registers from
1358 REG+D addresses where D does not fit in 5 bits, including
1359 (subreg (mem (addr))) cases. */
1360 if (fp_reg_operand (operand0, mode)
1361 && ((GET_CODE (operand1) == MEM
1362 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1363 || ((GET_CODE (operand1) == SUBREG
1364 && GET_CODE (XEXP (operand1, 0)) == MEM
1365 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1368 if (GET_CODE (operand1) == SUBREG)
1369 operand1 = XEXP (operand1, 0);
1371 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1372 it in WORD_MODE regardless of what mode it was originally given
1374 scratch_reg = force_mode (word_mode, scratch_reg);
1376 /* D might not fit in 14 bits either; for such cases load D into
1378 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1380 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1381 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1383 XEXP (XEXP (operand1, 0), 0),
1387 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1388 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1389 gen_rtx_MEM (mode, scratch_reg)));
1392 else if (fp_reg_operand (operand1, mode)
1393 && ((GET_CODE (operand0) == MEM
1394 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1395 || ((GET_CODE (operand0) == SUBREG)
1396 && GET_CODE (XEXP (operand0, 0)) == MEM
1397 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1400 if (GET_CODE (operand0) == SUBREG)
1401 operand0 = XEXP (operand0, 0);
1403 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1404 it in WORD_MODE regardless of what mode it was originally given
1406 scratch_reg = force_mode (word_mode, scratch_reg);
1408 /* D might not fit in 14 bits either; for such cases load D into
1410 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1412 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1413 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1416 XEXP (XEXP (operand0, 0),
1421 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1422 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1426 /* Handle secondary reloads for loads of FP registers from constant
1427 expressions by forcing the constant into memory.
1429 use scratch_reg to hold the address of the memory location.
1431 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1432 NO_REGS when presented with a const_int and an register class
1433 containing only FP registers. Doing so unfortunately creates
1434 more problems than it solves. Fix this for 2.5. */
1435 else if (fp_reg_operand (operand0, mode)
1436 && CONSTANT_P (operand1)
1441 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1442 it in WORD_MODE regardless of what mode it was originally given
1444 scratch_reg = force_mode (word_mode, scratch_reg);
1446 /* Force the constant into memory and put the address of the
1447 memory location into scratch_reg. */
1448 xoperands[0] = scratch_reg;
1449 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1450 emit_move_sequence (xoperands, Pmode, 0);
1452 /* Now load the destination register. */
1453 emit_insn (gen_rtx_SET (mode, operand0,
1454 gen_rtx_MEM (mode, scratch_reg)));
1457 /* Handle secondary reloads for SAR. These occur when trying to load
1458 the SAR from memory, FP register, or with a constant. */
1459 else if (GET_CODE (operand0) == REG
1460 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1461 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1462 && (GET_CODE (operand1) == MEM
1463 || GET_CODE (operand1) == CONST_INT
1464 || (GET_CODE (operand1) == REG
1465 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1468 /* D might not fit in 14 bits either; for such cases load D into
1470 if (GET_CODE (operand1) == MEM
1471 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1473 /* We are reloading the address into the scratch register, so we
1474 want to make sure the scratch register is a full register. */
1475 scratch_reg = force_mode (word_mode, scratch_reg);
1477 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1478 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1481 XEXP (XEXP (operand1, 0),
1485 /* Now we are going to load the scratch register from memory,
1486 we want to load it in the same width as the original MEM,
1487 which must be the same as the width of the ultimate destination,
1489 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1491 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1496 /* We want to load the scratch register using the same mode as
1497 the ultimate destination. */
1498 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1500 emit_move_insn (scratch_reg, operand1);
1503 /* And emit the insn to set the ultimate destination. We know that
1504 the scratch register has the same mode as the destination at this
1506 emit_move_insn (operand0, scratch_reg);
1509 /* Handle most common case: storing into a register. */
1510 else if (register_operand (operand0, mode))
1512 if (register_operand (operand1, mode)
1513 || (GET_CODE (operand1) == CONST_INT
1514 && cint_ok_for_move (INTVAL (operand1)))
1515 || (operand1 == CONST0_RTX (mode))
1516 || (GET_CODE (operand1) == HIGH
1517 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1518 /* Only `general_operands' can come here, so MEM is ok. */
1519 || GET_CODE (operand1) == MEM)
1521 /* Run this case quickly. */
1522 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1526 else if (GET_CODE (operand0) == MEM)
1528 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1529 && !(reload_in_progress || reload_completed))
1531 rtx temp = gen_reg_rtx (DFmode);
1533 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1534 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1537 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1539 /* Run this case quickly. */
1540 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1543 if (! (reload_in_progress || reload_completed))
1545 operands[0] = validize_mem (operand0);
1546 operands[1] = operand1 = force_reg (mode, operand1);
1550 /* Simplify the source if we need to.
1551 Note we do have to handle function labels here, even though we do
1552 not consider them legitimate constants. Loop optimizations can
1553 call the emit_move_xxx with one as a source. */
1554 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1555 || function_label_operand (operand1, mode)
1556 || (GET_CODE (operand1) == HIGH
1557 && symbolic_operand (XEXP (operand1, 0), mode)))
1561 if (GET_CODE (operand1) == HIGH)
1564 operand1 = XEXP (operand1, 0);
1566 if (symbolic_operand (operand1, mode))
1568 /* Argh. The assembler and linker can't handle arithmetic
1571 So we force the plabel into memory, load operand0 from
1572 the memory location, then add in the constant part. */
1573 if ((GET_CODE (operand1) == CONST
1574 && GET_CODE (XEXP (operand1, 0)) == PLUS
1575 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1576 || function_label_operand (operand1, mode))
1578 rtx temp, const_part;
1580 /* Figure out what (if any) scratch register to use. */
1581 if (reload_in_progress || reload_completed)
1583 scratch_reg = scratch_reg ? scratch_reg : operand0;
1584 /* SCRATCH_REG will hold an address and maybe the actual
1585 data. We want it in WORD_MODE regardless of what mode it
1586 was originally given to us. */
1587 scratch_reg = force_mode (word_mode, scratch_reg);
1590 scratch_reg = gen_reg_rtx (Pmode);
1592 if (GET_CODE (operand1) == CONST)
1594 /* Save away the constant part of the expression. */
1595 const_part = XEXP (XEXP (operand1, 0), 1);
1596 if (GET_CODE (const_part) != CONST_INT)
1599 /* Force the function label into memory. */
1600 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1604 /* No constant part. */
1605 const_part = NULL_RTX;
1607 /* Force the function label into memory. */
1608 temp = force_const_mem (mode, operand1);
1612 /* Get the address of the memory location. PIC-ify it if
1614 temp = XEXP (temp, 0);
1616 temp = legitimize_pic_address (temp, mode, scratch_reg);
1618 /* Put the address of the memory location into our destination
1621 emit_move_sequence (operands, mode, scratch_reg);
1623 /* Now load from the memory location into our destination
1625 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1626 emit_move_sequence (operands, mode, scratch_reg);
1628 /* And add back in the constant part. */
1629 if (const_part != NULL_RTX)
1630 expand_inc (operand0, const_part);
1639 if (reload_in_progress || reload_completed)
1641 temp = scratch_reg ? scratch_reg : operand0;
1642 /* TEMP will hold an address and maybe the actual
1643 data. We want it in WORD_MODE regardless of what mode it
1644 was originally given to us. */
1645 temp = force_mode (word_mode, temp);
1648 temp = gen_reg_rtx (Pmode);
1650 /* (const (plus (symbol) (const_int))) must be forced to
1651 memory during/after reload if the const_int will not fit
1653 if (GET_CODE (operand1) == CONST
1654 && GET_CODE (XEXP (operand1, 0)) == PLUS
1655 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1656 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1657 && (reload_completed || reload_in_progress)
1660 operands[1] = force_const_mem (mode, operand1);
1661 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1663 emit_move_sequence (operands, mode, temp);
1667 operands[1] = legitimize_pic_address (operand1, mode, temp);
1668 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1671 /* On the HPPA, references to data space are supposed to use dp,
1672 register 27, but showing it in the RTL inhibits various cse
1673 and loop optimizations. */
1678 if (reload_in_progress || reload_completed)
1680 temp = scratch_reg ? scratch_reg : operand0;
1681 /* TEMP will hold an address and maybe the actual
1682 data. We want it in WORD_MODE regardless of what mode it
1683 was originally given to us. */
1684 temp = force_mode (word_mode, temp);
1687 temp = gen_reg_rtx (mode);
1689 /* Loading a SYMBOL_REF into a register makes that register
1690 safe to be used as the base in an indexed address.
1692 Don't mark hard registers though. That loses. */
1693 if (GET_CODE (operand0) == REG
1694 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1695 REG_POINTER (operand0) = 1;
1696 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1697 REG_POINTER (temp) = 1;
1699 set = gen_rtx_SET (mode, operand0, temp);
1701 set = gen_rtx_SET (VOIDmode,
1703 gen_rtx_LO_SUM (mode, temp, operand1));
1705 emit_insn (gen_rtx_SET (VOIDmode,
1707 gen_rtx_HIGH (mode, operand1)));
1713 else if (GET_CODE (operand1) != CONST_INT
1714 || ! cint_ok_for_move (INTVAL (operand1)))
1716 rtx extend = NULL_RTX;
1719 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1720 && HOST_BITS_PER_WIDE_INT > 32
1721 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1723 HOST_WIDE_INT val = INTVAL (operand1);
1726 /* Extract the low order 32 bits of the value and sign extend.
1727 If the new value is the same as the original value, we can
1728 can use the original value as-is. If the new value is
1729 different, we use it and insert the most-significant 32-bits
1730 of the original value into the final result. */
1731 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1732 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1735 #if HOST_BITS_PER_WIDE_INT > 32
1736 extend = GEN_INT (val >> 32);
1738 operand1 = GEN_INT (nval);
1742 if (reload_in_progress || reload_completed)
1745 temp = gen_reg_rtx (mode);
1747 /* We don't directly split DImode constants on 32-bit targets
1748 because PLUS uses an 11-bit immediate and the insn sequence
1749 generated is not as efficient as the one using HIGH/LO_SUM. */
1750 if (GET_CODE (operand1) == CONST_INT
1751 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1753 /* Directly break constant into high and low parts. This
1754 provides better optimization opportunities because various
1755 passes recognize constants split with PLUS but not LO_SUM.
1756 We use a 14-bit signed low part except when the addition
1757 of 0x4000 to the high part might change the sign of the
1759 HOST_WIDE_INT value = INTVAL (operand1);
1760 HOST_WIDE_INT low = value & 0x3fff;
1761 HOST_WIDE_INT high = value & ~ 0x3fff;
1765 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1773 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1774 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1778 emit_insn (gen_rtx_SET (VOIDmode, temp,
1779 gen_rtx_HIGH (mode, operand1)));
1780 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1783 emit_move_insn (operands[0], operands[1]);
1785 if (extend != NULL_RTX)
1786 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1792 /* Now have insn-emit do whatever it normally does. */
1796 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1797 it will need a link/runtime reloc). */
1805 switch (TREE_CODE (exp))
1812 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1813 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1818 case NON_LVALUE_EXPR:
1819 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1825 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1826 if (TREE_VALUE (link) != 0)
1827 reloc |= reloc_needed (TREE_VALUE (link));
1840 /* Does operand (which is a symbolic_operand) live in text space?
1841 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
1845 read_only_operand (operand, mode)
1847 enum machine_mode mode ATTRIBUTE_UNUSED;
1849 if (GET_CODE (operand) == CONST)
1850 operand = XEXP (XEXP (operand, 0), 0);
1853 if (GET_CODE (operand) == SYMBOL_REF)
1854 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1858 if (GET_CODE (operand) == SYMBOL_REF)
1859 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1865 /* Return the best assembler insn template
1866 for moving operands[1] into operands[0] as a fullword. */
1868 singlemove_string (operands)
1871 HOST_WIDE_INT intval;
1873 if (GET_CODE (operands[0]) == MEM)
1874 return "stw %r1,%0";
1875 if (GET_CODE (operands[1]) == MEM)
1877 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1882 if (GET_MODE (operands[1]) != SFmode)
1885 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1887 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1888 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1890 operands[1] = GEN_INT (i);
1891 /* Fall through to CONST_INT case. */
1893 if (GET_CODE (operands[1]) == CONST_INT)
1895 intval = INTVAL (operands[1]);
1897 if (VAL_14_BITS_P (intval))
1899 else if ((intval & 0x7ff) == 0)
1900 return "ldil L'%1,%0";
1901 else if (zdepi_cint_p (intval))
1902 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1904 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1906 return "copy %1,%0";
1910 /* Compute position (in OP[1]) and width (in OP[2])
1911 useful for copying IMM to a register using the zdepi
1912 instructions. Store the immediate value to insert in OP[0]. */
1914 compute_zdepwi_operands (imm, op)
1915 unsigned HOST_WIDE_INT imm;
1920 /* Find the least significant set bit in IMM. */
1921 for (lsb = 0; lsb < 32; lsb++)
1928 /* Choose variants based on *sign* of the 5-bit field. */
1929 if ((imm & 0x10) == 0)
1930 len = (lsb <= 28) ? 4 : 32 - lsb;
1933 /* Find the width of the bitstring in IMM. */
1934 for (len = 5; len < 32; len++)
1936 if ((imm & (1 << len)) == 0)
1940 /* Sign extend IMM as a 5-bit value. */
1941 imm = (imm & 0xf) - 0x10;
1949 /* Compute position (in OP[1]) and width (in OP[2])
1950 useful for copying IMM to a register using the depdi,z
1951 instructions. Store the immediate value to insert in OP[0]. */
1953 compute_zdepdi_operands (imm, op)
1954 unsigned HOST_WIDE_INT imm;
1957 HOST_WIDE_INT lsb, len;
1959 /* Find the least significant set bit in IMM. */
1960 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1967 /* Choose variants based on *sign* of the 5-bit field. */
1968 if ((imm & 0x10) == 0)
1969 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1970 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1973 /* Find the width of the bitstring in IMM. */
1974 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1976 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
1980 /* Sign extend IMM as a 5-bit value. */
1981 imm = (imm & 0xf) - 0x10;
1989 /* Output assembler code to perform a doubleword move insn
1990 with operands OPERANDS. */
1993 output_move_double (operands)
1996 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1998 rtx addreg0 = 0, addreg1 = 0;
2000 /* First classify both operands. */
2002 if (REG_P (operands[0]))
2004 else if (offsettable_memref_p (operands[0]))
2006 else if (GET_CODE (operands[0]) == MEM)
2011 if (REG_P (operands[1]))
2013 else if (CONSTANT_P (operands[1]))
2015 else if (offsettable_memref_p (operands[1]))
2017 else if (GET_CODE (operands[1]) == MEM)
2022 /* Check for the cases that the operand constraints are not
2023 supposed to allow to happen. Abort if we get one,
2024 because generating code for these cases is painful. */
2026 if (optype0 != REGOP && optype1 != REGOP)
2029 /* Handle auto decrementing and incrementing loads and stores
2030 specifically, since the structure of the function doesn't work
2031 for them without major modification. Do it better when we learn
2032 this port about the general inc/dec addressing of PA.
2033 (This was written by tege. Chide him if it doesn't work.) */
2035 if (optype0 == MEMOP)
2037 /* We have to output the address syntax ourselves, since print_operand
2038 doesn't deal with the addresses we want to use. Fix this later. */
2040 rtx addr = XEXP (operands[0], 0);
2041 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2043 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2045 operands[0] = XEXP (addr, 0);
2046 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2049 if (!reg_overlap_mentioned_p (high_reg, addr))
2051 /* No overlap between high target register and address
2052 register. (We do this in a non-obvious way to
2053 save a register file writeback) */
2054 if (GET_CODE (addr) == POST_INC)
2055 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2056 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2061 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2063 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2065 operands[0] = XEXP (addr, 0);
2066 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2069 if (!reg_overlap_mentioned_p (high_reg, addr))
2071 /* No overlap between high target register and address
2072 register. (We do this in a non-obvious way to
2073 save a register file writeback) */
2074 if (GET_CODE (addr) == PRE_INC)
2075 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2076 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2082 if (optype1 == MEMOP)
2084 /* We have to output the address syntax ourselves, since print_operand
2085 doesn't deal with the addresses we want to use. Fix this later. */
2087 rtx addr = XEXP (operands[1], 0);
2088 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2090 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2092 operands[1] = XEXP (addr, 0);
2093 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2096 if (!reg_overlap_mentioned_p (high_reg, addr))
2098 /* No overlap between high target register and address
2099 register. (We do this in a non-obvious way to
2100 save a register file writeback) */
2101 if (GET_CODE (addr) == POST_INC)
2102 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2103 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2107 /* This is an undefined situation. We should load into the
2108 address register *and* update that register. Probably
2109 we don't need to handle this at all. */
2110 if (GET_CODE (addr) == POST_INC)
2111 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2112 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2115 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2117 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2119 operands[1] = XEXP (addr, 0);
2120 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2123 if (!reg_overlap_mentioned_p (high_reg, addr))
2125 /* No overlap between high target register and address
2126 register. (We do this in a non-obvious way to
2127 save a register file writeback) */
2128 if (GET_CODE (addr) == PRE_INC)
2129 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2130 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2134 /* This is an undefined situation. We should load into the
2135 address register *and* update that register. Probably
2136 we don't need to handle this at all. */
2137 if (GET_CODE (addr) == PRE_INC)
2138 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2139 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2142 else if (GET_CODE (addr) == PLUS
2143 && GET_CODE (XEXP (addr, 0)) == MULT)
2145 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2147 if (!reg_overlap_mentioned_p (high_reg, addr))
2151 xoperands[0] = high_reg;
2152 xoperands[1] = XEXP (addr, 1);
2153 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2154 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2155 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2157 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2163 xoperands[0] = high_reg;
2164 xoperands[1] = XEXP (addr, 1);
2165 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2166 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2167 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2169 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2174 /* If an operand is an unoffsettable memory ref, find a register
2175 we can increment temporarily to make it refer to the second word. */
2177 if (optype0 == MEMOP)
2178 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2180 if (optype1 == MEMOP)
2181 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2183 /* Ok, we can do one word at a time.
2184 Normally we do the low-numbered word first.
2186 In either case, set up in LATEHALF the operands to use
2187 for the high-numbered word and in some cases alter the
2188 operands in OPERANDS to be suitable for the low-numbered word. */
2190 if (optype0 == REGOP)
2191 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2192 else if (optype0 == OFFSOP)
2193 latehalf[0] = adjust_address (operands[0], SImode, 4);
2195 latehalf[0] = operands[0];
2197 if (optype1 == REGOP)
2198 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2199 else if (optype1 == OFFSOP)
2200 latehalf[1] = adjust_address (operands[1], SImode, 4);
2201 else if (optype1 == CNSTOP)
2202 split_double (operands[1], &operands[1], &latehalf[1]);
2204 latehalf[1] = operands[1];
2206 /* If the first move would clobber the source of the second one,
2207 do them in the other order.
2209 This can happen in two cases:
2211 mem -> register where the first half of the destination register
2212 is the same register used in the memory's address. Reload
2213 can create such insns.
2215 mem in this case will be either register indirect or register
2216 indirect plus a valid offset.
2218 register -> register move where REGNO(dst) == REGNO(src + 1)
2219 someone (Tim/Tege?) claimed this can happen for parameter loads.
2221 Handle mem -> register case first. */
2222 if (optype0 == REGOP
2223 && (optype1 == MEMOP || optype1 == OFFSOP)
2224 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2227 /* Do the late half first. */
2229 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2230 output_asm_insn (singlemove_string (latehalf), latehalf);
2234 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2235 return singlemove_string (operands);
2238 /* Now handle register -> register case. */
2239 if (optype0 == REGOP && optype1 == REGOP
2240 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2242 output_asm_insn (singlemove_string (latehalf), latehalf);
2243 return singlemove_string (operands);
2246 /* Normal case: do the two words, low-numbered first. */
2248 output_asm_insn (singlemove_string (operands), operands);
2250 /* Make any unoffsettable addresses point at high-numbered word. */
2252 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2254 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2257 output_asm_insn (singlemove_string (latehalf), latehalf);
2259 /* Undo the adds we just did. */
2261 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2263 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2269 output_fp_move_double (operands)
2272 if (FP_REG_P (operands[0]))
2274 if (FP_REG_P (operands[1])
2275 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2276 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2278 output_asm_insn ("fldd%F1 %1,%0", operands);
2280 else if (FP_REG_P (operands[1]))
2282 output_asm_insn ("fstd%F0 %1,%0", operands);
2284 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2286 if (GET_CODE (operands[0]) == REG)
2289 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2290 xoperands[0] = operands[0];
2291 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2293 /* This is a pain. You have to be prepared to deal with an
2294 arbitrary address here including pre/post increment/decrement.
2296 so avoid this in the MD. */
2304 /* Return a REG that occurs in ADDR with coefficient 1.
2305 ADDR can be effectively incremented by incrementing REG. */
2308 find_addr_reg (addr)
2311 while (GET_CODE (addr) == PLUS)
2313 if (GET_CODE (XEXP (addr, 0)) == REG)
2314 addr = XEXP (addr, 0);
2315 else if (GET_CODE (XEXP (addr, 1)) == REG)
2316 addr = XEXP (addr, 1);
2317 else if (CONSTANT_P (XEXP (addr, 0)))
2318 addr = XEXP (addr, 1);
2319 else if (CONSTANT_P (XEXP (addr, 1)))
2320 addr = XEXP (addr, 0);
2324 if (GET_CODE (addr) == REG)
2329 /* Emit code to perform a block move.
2331 OPERANDS[0] is the destination pointer as a REG, clobbered.
2332 OPERANDS[1] is the source pointer as a REG, clobbered.
2333 OPERANDS[2] is a register for temporary storage.
2334 OPERANDS[4] is the size as a CONST_INT
2335 OPERANDS[3] is a register for temporary storage.
2336 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2337 OPERANDS[6] is another temporary register. */
2340 output_block_move (operands, size_is_constant)
2342 int size_is_constant ATTRIBUTE_UNUSED;
2344 int align = INTVAL (operands[5]);
2345 unsigned long n_bytes = INTVAL (operands[4]);
2347 /* We can't move more than four bytes at a time because the PA
2348 has no longer integer move insns. (Could use fp mem ops?) */
2352 /* Note that we know each loop below will execute at least twice
2353 (else we would have open-coded the copy). */
2357 /* Pre-adjust the loop counter. */
2358 operands[4] = GEN_INT (n_bytes - 8);
2359 output_asm_insn ("ldi %4,%2", operands);
2362 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2363 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2364 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2365 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2366 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2368 /* Handle the residual. There could be up to 7 bytes of
2369 residual to copy! */
2370 if (n_bytes % 8 != 0)
2372 operands[4] = GEN_INT (n_bytes % 4);
2373 if (n_bytes % 8 >= 4)
2374 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2375 if (n_bytes % 4 != 0)
2376 output_asm_insn ("ldw 0(%1),%6", operands);
2377 if (n_bytes % 8 >= 4)
2378 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2379 if (n_bytes % 4 != 0)
2380 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2385 /* Pre-adjust the loop counter. */
2386 operands[4] = GEN_INT (n_bytes - 4);
2387 output_asm_insn ("ldi %4,%2", operands);
2390 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2391 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2392 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2393 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2394 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2396 /* Handle the residual. */
2397 if (n_bytes % 4 != 0)
2399 if (n_bytes % 4 >= 2)
2400 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2401 if (n_bytes % 2 != 0)
2402 output_asm_insn ("ldb 0(%1),%6", operands);
2403 if (n_bytes % 4 >= 2)
2404 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2405 if (n_bytes % 2 != 0)
2406 output_asm_insn ("stb %6,0(%0)", operands);
2411 /* Pre-adjust the loop counter. */
2412 operands[4] = GEN_INT (n_bytes - 2);
2413 output_asm_insn ("ldi %4,%2", operands);
2416 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2417 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2418 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2419 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2420 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2422 /* Handle the residual. */
2423 if (n_bytes % 2 != 0)
2425 output_asm_insn ("ldb 0(%1),%3", operands);
2426 output_asm_insn ("stb %3,0(%0)", operands);
2435 /* Count the number of insns necessary to handle this block move.
2437 Basic structure is the same as emit_block_move, except that we
2438 count insns rather than emit them. */
2441 compute_movstrsi_length (insn)
2444 rtx pat = PATTERN (insn);
2445 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2446 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2447 unsigned int n_insns = 0;
2449 /* We can't move more than four bytes at a time because the PA
2450 has no longer integer move insns. (Could use fp mem ops?) */
2454 /* The basic copying loop. */
2458 if (n_bytes % (2 * align) != 0)
2460 if ((n_bytes % (2 * align)) >= align)
2463 if ((n_bytes % align) != 0)
2467 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2473 output_and (operands)
2476 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2478 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2479 int ls0, ls1, ms0, p, len;
2481 for (ls0 = 0; ls0 < 32; ls0++)
2482 if ((mask & (1 << ls0)) == 0)
2485 for (ls1 = ls0; ls1 < 32; ls1++)
2486 if ((mask & (1 << ls1)) != 0)
2489 for (ms0 = ls1; ms0 < 32; ms0++)
2490 if ((mask & (1 << ms0)) == 0)
2503 operands[2] = GEN_INT (len);
2504 return "{extru|extrw,u} %1,31,%2,%0";
2508 /* We could use this `depi' for the case above as well, but `depi'
2509 requires one more register file access than an `extru'. */
2514 operands[2] = GEN_INT (p);
2515 operands[3] = GEN_INT (len);
2516 return "{depi|depwi} 0,%2,%3,%0";
2520 return "and %1,%2,%0";
2523 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2524 storing the result in operands[0]. */
2526 output_64bit_and (operands)
2529 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2531 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2532 int ls0, ls1, ms0, p, len;
2534 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2535 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2538 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2539 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2542 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2543 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2546 if (ms0 != HOST_BITS_PER_WIDE_INT)
2549 if (ls1 == HOST_BITS_PER_WIDE_INT)
2556 operands[2] = GEN_INT (len);
2557 return "extrd,u %1,63,%2,%0";
2561 /* We could use this `depi' for the case above as well, but `depi'
2562 requires one more register file access than an `extru'. */
2567 operands[2] = GEN_INT (p);
2568 operands[3] = GEN_INT (len);
2569 return "depdi 0,%2,%3,%0";
2573 return "and %1,%2,%0";
2577 output_ior (operands)
2580 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2581 int bs0, bs1, p, len;
2583 if (INTVAL (operands[2]) == 0)
2584 return "copy %1,%0";
2586 for (bs0 = 0; bs0 < 32; bs0++)
2587 if ((mask & (1 << bs0)) != 0)
2590 for (bs1 = bs0; bs1 < 32; bs1++)
2591 if ((mask & (1 << bs1)) == 0)
2594 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2600 operands[2] = GEN_INT (p);
2601 operands[3] = GEN_INT (len);
2602 return "{depi|depwi} -1,%2,%3,%0";
2605 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2606 storing the result in operands[0]. */
2608 output_64bit_ior (operands)
2611 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2612 int bs0, bs1, p, len;
2614 if (INTVAL (operands[2]) == 0)
2615 return "copy %1,%0";
2617 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2618 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2621 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2622 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2625 if (bs1 != HOST_BITS_PER_WIDE_INT
2626 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2632 operands[2] = GEN_INT (p);
2633 operands[3] = GEN_INT (len);
2634 return "depdi -1,%2,%3,%0";
2637 /* Target hook for assembling integer objects. This code handles
2638 aligned SI and DI integers specially, since function references must
2639 be preceded by P%. */
2642 pa_assemble_integer (x, size, aligned_p)
2647 if (size == UNITS_PER_WORD && aligned_p
2648 && function_label_operand (x, VOIDmode))
2650 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2651 output_addr_const (asm_out_file, x);
2652 fputc ('\n', asm_out_file);
2655 return default_assemble_integer (x, size, aligned_p);
2658 /* Output an ascii string. */
2660 output_ascii (file, p, size)
2667 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2669 /* The HP assembler can only take strings of 256 characters at one
2670 time. This is a limitation on input line length, *not* the
2671 length of the string. Sigh. Even worse, it seems that the
2672 restriction is in number of input characters (see \xnn &
2673 \whatever). So we have to do this very carefully. */
2675 fputs ("\t.STRING \"", file);
2678 for (i = 0; i < size; i += 4)
2682 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2684 register unsigned int c = (unsigned char) p[i + io];
2686 if (c == '\"' || c == '\\')
2687 partial_output[co++] = '\\';
2688 if (c >= ' ' && c < 0177)
2689 partial_output[co++] = c;
2693 partial_output[co++] = '\\';
2694 partial_output[co++] = 'x';
2695 hexd = c / 16 - 0 + '0';
2697 hexd -= '9' - 'a' + 1;
2698 partial_output[co++] = hexd;
2699 hexd = c % 16 - 0 + '0';
2701 hexd -= '9' - 'a' + 1;
2702 partial_output[co++] = hexd;
2705 if (chars_output + co > 243)
2707 fputs ("\"\n\t.STRING \"", file);
2710 fwrite (partial_output, 1, (size_t) co, file);
2714 fputs ("\"\n", file);
2717 /* Try to rewrite floating point comparisons & branches to avoid
2718 useless add,tr insns.
2720 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2721 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2722 first attempt to remove useless add,tr insns. It is zero
2723 for the second pass as reorg sometimes leaves bogus REG_DEAD
2726 When CHECK_NOTES is zero we can only eliminate add,tr insns
2727 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2730 remove_useless_addtr_insns (insns, check_notes)
2735 static int pass = 0;
2737 /* This is fairly cheap, so always run it when optimizing. */
2741 int fbranch_count = 0;
2743 /* Walk all the insns in this function looking for fcmp & fbranch
2744 instructions. Keep track of how many of each we find. */
2745 insns = get_insns ();
2746 for (insn = insns; insn; insn = next_insn (insn))
2750 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2751 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2754 tmp = PATTERN (insn);
2756 /* It must be a set. */
2757 if (GET_CODE (tmp) != SET)
2760 /* If the destination is CCFP, then we've found an fcmp insn. */
2761 tmp = SET_DEST (tmp);
2762 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2768 tmp = PATTERN (insn);
2769 /* If this is an fbranch instruction, bump the fbranch counter. */
2770 if (GET_CODE (tmp) == SET
2771 && SET_DEST (tmp) == pc_rtx
2772 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2773 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2774 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2775 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2783 /* Find all floating point compare + branch insns. If possible,
2784 reverse the comparison & the branch to avoid add,tr insns. */
2785 for (insn = insns; insn; insn = next_insn (insn))
2789 /* Ignore anything that isn't an INSN. */
2790 if (GET_CODE (insn) != INSN)
2793 tmp = PATTERN (insn);
2795 /* It must be a set. */
2796 if (GET_CODE (tmp) != SET)
2799 /* The destination must be CCFP, which is register zero. */
2800 tmp = SET_DEST (tmp);
2801 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2804 /* INSN should be a set of CCFP.
2806 See if the result of this insn is used in a reversed FP
2807 conditional branch. If so, reverse our condition and
2808 the branch. Doing so avoids useless add,tr insns. */
2809 next = next_insn (insn);
2812 /* Jumps, calls and labels stop our search. */
2813 if (GET_CODE (next) == JUMP_INSN
2814 || GET_CODE (next) == CALL_INSN
2815 || GET_CODE (next) == CODE_LABEL)
2818 /* As does another fcmp insn. */
2819 if (GET_CODE (next) == INSN
2820 && GET_CODE (PATTERN (next)) == SET
2821 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2822 && REGNO (SET_DEST (PATTERN (next))) == 0)
2825 next = next_insn (next);
2828 /* Is NEXT_INSN a branch? */
2830 && GET_CODE (next) == JUMP_INSN)
2832 rtx pattern = PATTERN (next);
2834 /* If it a reversed fp conditional branch (eg uses add,tr)
2835 and CCFP dies, then reverse our conditional and the branch
2836 to avoid the add,tr. */
2837 if (GET_CODE (pattern) == SET
2838 && SET_DEST (pattern) == pc_rtx
2839 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2840 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2841 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2842 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2843 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2844 && (fcmp_count == fbranch_count
2846 && find_regno_note (next, REG_DEAD, 0))))
2848 /* Reverse the branch. */
2849 tmp = XEXP (SET_SRC (pattern), 1);
2850 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2851 XEXP (SET_SRC (pattern), 2) = tmp;
2852 INSN_CODE (next) = -1;
2854 /* Reverse our condition. */
2855 tmp = PATTERN (insn);
2856 PUT_CODE (XEXP (tmp, 1),
2857 (reverse_condition_maybe_unordered
2858 (GET_CODE (XEXP (tmp, 1)))));
2868 /* You may have trouble believing this, but this is the 32 bit HP-PA
2873 Variable arguments (optional; any number may be allocated)
2875 SP-(4*(N+9)) arg word N
2880 Fixed arguments (must be allocated; may remain unused)
2889 SP-32 External Data Pointer (DP)
2891 SP-24 External/stub RP (RP')
2895 SP-8 Calling Stub RP (RP'')
2900 SP-0 Stack Pointer (points to next available address)
2904 /* This function saves registers as follows. Registers marked with ' are
2905 this function's registers (as opposed to the previous function's).
2906 If a frame_pointer isn't needed, r4 is saved as a general register;
2907 the space for the frame pointer is still allocated, though, to keep
2913 SP (FP') Previous FP
2914 SP + 4 Alignment filler (sigh)
2915 SP + 8 Space for locals reserved here.
2919 SP + n All call saved register used.
2923 SP + o All call saved fp registers used.
2927 SP + p (SP') points to next available address.
2931 /* Global variables set by output_function_prologue(). */
2932 /* Size of frame. Need to know this to emit return insns from
2934 static int actual_fsize;
2935 static int local_fsize, save_fregs;
2937 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2938 Handle case where DISP > 8k by using the add_high_const patterns.
2940 Note in DISP > 8k case, we will leave the high part of the address
2941 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2944 store_reg (reg, disp, base)
2945 int reg, disp, base;
2947 rtx insn, dest, src, basereg;
2949 src = gen_rtx_REG (word_mode, reg);
2950 basereg = gen_rtx_REG (Pmode, base);
2951 if (VAL_14_BITS_P (disp))
2953 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2954 insn = emit_move_insn (dest, src);
2958 rtx delta = GEN_INT (disp);
2959 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
2960 rtx tmpreg = gen_rtx_REG (Pmode, 1);
2961 emit_move_insn (tmpreg, high);
2962 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
2963 insn = emit_move_insn (dest, src);
2967 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2968 gen_rtx_SET (VOIDmode,
2969 gen_rtx_MEM (word_mode,
2970 gen_rtx_PLUS (word_mode, basereg,
2978 RTX_FRAME_RELATED_P (insn) = 1;
2981 /* Emit RTL to store REG at the memory location specified by BASE and then
2982 add MOD to BASE. MOD must be <= 8k. */
2985 store_reg_modify (base, reg, mod)
2988 rtx insn, basereg, srcreg, delta;
2990 if (! VAL_14_BITS_P (mod))
2993 basereg = gen_rtx_REG (Pmode, base);
2994 srcreg = gen_rtx_REG (word_mode, reg);
2995 delta = GEN_INT (mod);
2997 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3000 RTX_FRAME_RELATED_P (insn) = 1;
3002 /* RTX_FRAME_RELATED_P must be set on each frame related set
3003 in a parallel with more than one element. Don't set
3004 RTX_FRAME_RELATED_P in the first set if reg is temporary
3005 register 1. The effect of this operation is recorded in
3006 the initial copy. */
3009 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3010 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3014 /* The first element of a PARALLEL is always processed if it is
3015 a SET. Thus, we need an expression list for this case. */
3017 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3018 gen_rtx_SET (VOIDmode, basereg,
3019 gen_rtx_PLUS (word_mode, basereg, delta)),
3025 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3026 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3027 whether to add a frame note or not.
3029 In the DISP > 8k case, we leave the high part of the address in %r1.
3030 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3033 set_reg_plus_d (reg, base, disp, note)
3034 int reg, base, disp, note;
3038 if (VAL_14_BITS_P (disp))
3040 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3041 plus_constant (gen_rtx_REG (Pmode, base), disp));
3045 rtx basereg = gen_rtx_REG (Pmode, base);
3046 rtx delta = GEN_INT (disp);
3048 emit_move_insn (gen_rtx_REG (Pmode, 1),
3049 gen_rtx_PLUS (Pmode, basereg,
3050 gen_rtx_HIGH (Pmode, delta)));
3051 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3052 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
3056 if (DO_FRAME_NOTES && note)
3057 RTX_FRAME_RELATED_P (insn) = 1;
3061 compute_frame_size (size, fregs_live)
3067 /* Space for frame pointer + filler. If any frame is allocated
3068 we need to add this in because of STARTING_FRAME_OFFSET.
3070 Similar code also appears in hppa_expand_prologue. Change both
3071 of them at the same time. */
3072 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
3074 /* If the current function calls __builtin_eh_return, then we need
3075 to allocate stack space for registers that will hold data for
3076 the exception handler. */
3077 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3081 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3083 fsize += i * UNITS_PER_WORD;
3086 /* Account for space used by the callee general register saves. */
3087 for (i = 18; i >= 3; i--)
3088 if (regs_ever_live[i])
3089 fsize += UNITS_PER_WORD;
3091 /* Round the stack. */
3092 fsize = (fsize + 7) & ~7;
3094 /* Account for space used by the callee floating point register saves. */
3095 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3096 if (regs_ever_live[i]
3097 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3102 /* We always save both halves of the FP register, so always
3103 increment the frame size by 8 bytes. */
3107 /* The various ABIs include space for the outgoing parameters in the
3108 size of the current function's stack frame. */
3109 fsize += current_function_outgoing_args_size;
3111 /* Allocate space for the fixed frame marker. This space must be
3112 allocated for any function that makes calls or otherwise allocates
3114 if (!current_function_is_leaf || fsize)
3115 fsize += TARGET_64BIT ? 16 : 32;
3117 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
3120 /* Generate the assembly code for function entry. FILE is a stdio
3121 stream to output the code to. SIZE is an int: how many units of
3122 temporary storage to allocate.
3124 Refer to the array `regs_ever_live' to determine which registers to
3125 save; `regs_ever_live[I]' is nonzero if register number I is ever
3126 used in the function. This function is responsible for knowing
3127 which registers should not be saved even if used. */
3129 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3130 of memory. If any fpu reg is used in the function, we allocate
3131 such a block here, at the bottom of the frame, just in case it's needed.
3133 If this function is a leaf procedure, then we may choose not
3134 to do a "save" insn. The decision about whether or not
3135 to do this is made in regclass.c. */
3138 pa_output_function_prologue (file, size)
3140 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3142 /* The function's label and associated .PROC must never be
3143 separated and must be output *after* any profiling declarations
3144 to avoid changing spaces/subspaces within a procedure. */
3145 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3146 fputs ("\t.PROC\n", file);
3148 /* hppa_expand_prologue does the dirty work now. We just need
3149 to output the assembler directives which denote the start
3151 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
3152 if (regs_ever_live[2])
3153 fputs (",CALLS,SAVE_RP", file);
3155 fputs (",NO_CALLS", file);
3157 if (frame_pointer_needed)
3158 fputs (",SAVE_SP", file);
3160 /* Pass on information about the number of callee register saves
3161 performed in the prologue.
3163 The compiler is supposed to pass the highest register number
3164 saved, the assembler then has to adjust that number before
3165 entering it into the unwind descriptor (to account for any
3166 caller saved registers with lower register numbers than the
3167 first callee saved register). */
3169 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3172 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3174 fputs ("\n\t.ENTRY\n", file);
3176 /* If we're using GAS and SOM, and not using the portable runtime model,
3177 then we don't need to accumulate the total number of code bytes. */
3178 if ((TARGET_GAS && TARGET_SOM && ! TARGET_PORTABLE_RUNTIME)
3179 /* FIXME: we can't handle long calls for TARGET_64BIT. */
3181 total_code_bytes = 0;
3182 else if (INSN_ADDRESSES_SET_P ())
3184 unsigned int old_total = total_code_bytes;
3186 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_nonnote_insn ()));
3187 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3189 /* Be prepared to handle overflows. */
3190 if (old_total > total_code_bytes)
3191 total_code_bytes = -1;
3194 total_code_bytes = -1;
3196 remove_useless_addtr_insns (get_insns (), 0);
3200 hppa_expand_prologue ()
3202 int size = get_frame_size ();
3203 int merge_sp_adjust_with_store = 0;
3211 /* Allocate space for frame pointer + filler. If any frame is allocated
3212 we need to add this in because of STARTING_FRAME_OFFSET.
3214 Similar code also appears in compute_frame_size. Change both
3215 of them at the same time. */
3216 local_fsize = size + (size || frame_pointer_needed
3217 ? STARTING_FRAME_OFFSET : 0);
3219 actual_fsize = compute_frame_size (size, &save_fregs);
3221 /* Compute a few things we will use often. */
3222 tmpreg = gen_rtx_REG (word_mode, 1);
3224 /* Save RP first. The calling conventions manual states RP will
3225 always be stored into the caller's frame at sp - 20 or sp - 16
3226 depending on which ABI is in use. */
3227 if (regs_ever_live[2] || current_function_calls_eh_return)
3228 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3230 /* Allocate the local frame and set up the frame pointer if needed. */
3231 if (actual_fsize != 0)
3233 if (frame_pointer_needed)
3235 /* Copy the old frame pointer temporarily into %r1. Set up the
3236 new stack pointer, then store away the saved old frame pointer
3237 into the stack at sp and at the same time update the stack
3238 pointer by actual_fsize bytes. Two versions, first
3239 handles small (<8k) frames. The second handles large (>=8k)
3241 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3244 /* We need to record the frame pointer save here since the
3245 new frame pointer is set in the following insn. */
3246 RTX_FRAME_RELATED_P (insn) = 1;
3248 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3249 gen_rtx_SET (VOIDmode,
3250 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3255 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3257 RTX_FRAME_RELATED_P (insn) = 1;
3259 if (VAL_14_BITS_P (actual_fsize))
3260 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3263 /* It is incorrect to store the saved frame pointer at *sp,
3264 then increment sp (writes beyond the current stack boundary).
3266 So instead use stwm to store at *sp and post-increment the
3267 stack pointer as an atomic operation. Then increment sp to
3268 finish allocating the new frame. */
3269 int adjust1 = 8192 - 64;
3270 int adjust2 = actual_fsize - adjust1;
3272 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3273 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3277 /* Prevent register spills from being scheduled before the
3278 stack pointer is raised. Necessary as we will be storing
3279 registers using the frame pointer as a base register, and
3280 we happen to set fp before raising sp. */
3281 emit_insn (gen_blockage ());
3283 /* no frame pointer needed. */
3286 /* In some cases we can perform the first callee register save
3287 and allocating the stack frame at the same time. If so, just
3288 make a note of it and defer allocating the frame until saving
3289 the callee registers. */
3290 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3291 merge_sp_adjust_with_store = 1;
3292 /* Can not optimize. Adjust the stack frame by actual_fsize
3295 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3300 /* Normal register save.
3302 Do not save the frame pointer in the frame_pointer_needed case. It
3303 was done earlier. */
3304 if (frame_pointer_needed)
3306 offset = local_fsize;
3308 /* Saving the EH return data registers in the frame is the simplest
3309 way to get the frame unwind information emitted. We put them
3310 just before the general registers. */
3311 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3313 unsigned int i, regno;
3317 regno = EH_RETURN_DATA_REGNO (i);
3318 if (regno == INVALID_REGNUM)
3321 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3322 offset += UNITS_PER_WORD;
3326 for (i = 18; i >= 4; i--)
3327 if (regs_ever_live[i] && ! call_used_regs[i])
3329 store_reg (i, offset, FRAME_POINTER_REGNUM);
3330 offset += UNITS_PER_WORD;
3333 /* Account for %r3 which is saved in a special place. */
3336 /* No frame pointer needed. */
3339 offset = local_fsize - actual_fsize;
3341 /* Saving the EH return data registers in the frame is the simplest
3342 way to get the frame unwind information emitted. */
3343 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3345 unsigned int i, regno;
3349 regno = EH_RETURN_DATA_REGNO (i);
3350 if (regno == INVALID_REGNUM)
3353 /* If merge_sp_adjust_with_store is nonzero, then we can
3354 optimize the first save. */
3355 if (merge_sp_adjust_with_store)
3357 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3358 merge_sp_adjust_with_store = 0;
3361 store_reg (regno, offset, STACK_POINTER_REGNUM);
3362 offset += UNITS_PER_WORD;
3366 for (i = 18; i >= 3; i--)
3367 if (regs_ever_live[i] && ! call_used_regs[i])
3369 /* If merge_sp_adjust_with_store is nonzero, then we can
3370 optimize the first GR save. */
3371 if (merge_sp_adjust_with_store)
3373 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3374 merge_sp_adjust_with_store = 0;
3377 store_reg (i, offset, STACK_POINTER_REGNUM);
3378 offset += UNITS_PER_WORD;
3382 /* If we wanted to merge the SP adjustment with a GR save, but we never
3383 did any GR saves, then just emit the adjustment here. */
3384 if (merge_sp_adjust_with_store)
3385 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3389 /* The hppa calling conventions say that %r19, the pic offset
3390 register, is saved at sp - 32 (in this function's frame)
3391 when generating PIC code. FIXME: What is the correct thing
3392 to do for functions which make no calls and allocate no
3393 frame? Do we need to allocate a frame, or can we just omit
3394 the save? For now we'll just omit the save. */
3395 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3396 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3398 /* Align pointer properly (doubleword boundary). */
3399 offset = (offset + 7) & ~7;
3401 /* Floating point register store. */
3406 /* First get the frame or stack pointer to the start of the FP register
3408 if (frame_pointer_needed)
3410 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3411 base = frame_pointer_rtx;
3415 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3416 base = stack_pointer_rtx;
3419 /* Now actually save the FP registers. */
3420 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3422 if (regs_ever_live[i]
3423 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3425 rtx addr, insn, reg;
3426 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3427 reg = gen_rtx_REG (DFmode, i);
3428 insn = emit_move_insn (addr, reg);
3431 RTX_FRAME_RELATED_P (insn) = 1;
3434 rtx mem = gen_rtx_MEM (DFmode,
3435 plus_constant (base, offset));
3437 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3438 gen_rtx_SET (VOIDmode, mem, reg),
3443 rtx meml = gen_rtx_MEM (SFmode,
3444 plus_constant (base, offset));
3445 rtx memr = gen_rtx_MEM (SFmode,
3446 plus_constant (base, offset + 4));
3447 rtx regl = gen_rtx_REG (SFmode, i);
3448 rtx regr = gen_rtx_REG (SFmode, i + 1);
3449 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3450 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3453 RTX_FRAME_RELATED_P (setl) = 1;
3454 RTX_FRAME_RELATED_P (setr) = 1;
3455 vec = gen_rtvec (2, setl, setr);
3457 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3458 gen_rtx_SEQUENCE (VOIDmode, vec),
3462 offset += GET_MODE_SIZE (DFmode);
3468 /* FIXME: expand_call and expand_millicode_call need to be fixed to
3469 prevent insns with frame notes being scheduled in the delay slot
3470 of calls. This causes problems because the dwarf2 output code
3471 processes the insn list serially. For now, limit the migration
3472 of prologue insns with a blockage. */
3474 emit_insn (gen_blockage ());
3477 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3478 Handle case where DISP > 8k by using the add_high_const patterns. */
3481 load_reg (reg, disp, base)
3482 int reg, disp, base;
3484 rtx src, dest, basereg;
3486 dest = gen_rtx_REG (word_mode, reg);
3487 basereg = gen_rtx_REG (Pmode, base);
3488 if (VAL_14_BITS_P (disp))
3490 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3491 emit_move_insn (dest, src);
3495 rtx delta = GEN_INT (disp);
3496 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3497 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3498 emit_move_insn (tmpreg, high);
3499 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3500 emit_move_insn (dest, src);
3504 /* This function generates the assembly code for function exit.
3505 Args are as for output_function_prologue ().
3507 The function epilogue should not depend on the current stack
3508 pointer! It should use the frame pointer only. This is mandatory
3509 because of alloca; we also take advantage of it to omit stack
3510 adjustments before returning. */
3513 pa_output_function_epilogue (file, size)
3515 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3517 rtx insn = get_last_insn ();
3519 /* hppa_expand_epilogue does the dirty work now. We just need
3520 to output the assembler directives which denote the end
3523 To make debuggers happy, emit a nop if the epilogue was completely
3524 eliminated due to a volatile call as the last insn in the
3525 current function. That way the return address (in %r2) will
3526 always point to a valid instruction in the current function. */
3528 /* Get the last real insn. */
3529 if (GET_CODE (insn) == NOTE)
3530 insn = prev_real_insn (insn);
3532 /* If it is a sequence, then look inside. */
3533 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3534 insn = XVECEXP (PATTERN (insn), 0, 0);
3536 /* If insn is a CALL_INSN, then it must be a call to a volatile
3537 function (otherwise there would be epilogue insns). */
3538 if (insn && GET_CODE (insn) == CALL_INSN)
3539 fputs ("\tnop\n", file);
3541 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3545 hppa_expand_epilogue ()
3549 int merge_sp_adjust_with_load = 0;
3552 /* We will use this often. */
3553 tmpreg = gen_rtx_REG (word_mode, 1);
3555 /* Try to restore RP early to avoid load/use interlocks when
3556 RP gets used in the return (bv) instruction. This appears to still
3557 be necessary even when we schedule the prologue and epilogue. */
3558 if (regs_ever_live [2] || current_function_calls_eh_return)
3560 ret_off = TARGET_64BIT ? -16 : -20;
3561 if (frame_pointer_needed)
3563 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3568 /* No frame pointer, and stack is smaller than 8k. */
3569 if (VAL_14_BITS_P (ret_off - actual_fsize))
3571 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3577 /* General register restores. */
3578 if (frame_pointer_needed)
3580 offset = local_fsize;
3582 /* If the current function calls __builtin_eh_return, then we need
3583 to restore the saved EH data registers. */
3584 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3586 unsigned int i, regno;
3590 regno = EH_RETURN_DATA_REGNO (i);
3591 if (regno == INVALID_REGNUM)
3594 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3595 offset += UNITS_PER_WORD;
3599 for (i = 18; i >= 4; i--)
3600 if (regs_ever_live[i] && ! call_used_regs[i])
3602 load_reg (i, offset, FRAME_POINTER_REGNUM);
3603 offset += UNITS_PER_WORD;
3608 offset = local_fsize - actual_fsize;
3610 /* If the current function calls __builtin_eh_return, then we need
3611 to restore the saved EH data registers. */
3612 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3614 unsigned int i, regno;
3618 regno = EH_RETURN_DATA_REGNO (i);
3619 if (regno == INVALID_REGNUM)
3622 /* Only for the first load.
3623 merge_sp_adjust_with_load holds the register load
3624 with which we will merge the sp adjustment. */
3625 if (merge_sp_adjust_with_load == 0
3627 && VAL_14_BITS_P (-actual_fsize))
3628 merge_sp_adjust_with_load = regno;
3630 load_reg (regno, offset, STACK_POINTER_REGNUM);
3631 offset += UNITS_PER_WORD;
3635 for (i = 18; i >= 3; i--)
3637 if (regs_ever_live[i] && ! call_used_regs[i])
3639 /* Only for the first load.
3640 merge_sp_adjust_with_load holds the register load
3641 with which we will merge the sp adjustment. */
3642 if (merge_sp_adjust_with_load == 0
3644 && VAL_14_BITS_P (-actual_fsize))
3645 merge_sp_adjust_with_load = i;
3647 load_reg (i, offset, STACK_POINTER_REGNUM);
3648 offset += UNITS_PER_WORD;
3653 /* Align pointer properly (doubleword boundary). */
3654 offset = (offset + 7) & ~7;
3656 /* FP register restores. */
3659 /* Adjust the register to index off of. */
3660 if (frame_pointer_needed)
3661 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3663 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3665 /* Actually do the restores now. */
3666 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3667 if (regs_ever_live[i]
3668 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3670 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3671 rtx dest = gen_rtx_REG (DFmode, i);
3672 emit_move_insn (dest, src);
3676 /* Emit a blockage insn here to keep these insns from being moved to
3677 an earlier spot in the epilogue, or into the main instruction stream.
3679 This is necessary as we must not cut the stack back before all the
3680 restores are finished. */
3681 emit_insn (gen_blockage ());
3683 /* Reset stack pointer (and possibly frame pointer). The stack
3684 pointer is initially set to fp + 64 to avoid a race condition. */
3685 if (frame_pointer_needed)
3687 rtx delta = GEN_INT (-64);
3689 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
3690 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
3692 /* If we were deferring a callee register restore, do it now. */
3693 else if (merge_sp_adjust_with_load)
3695 rtx delta = GEN_INT (-actual_fsize);
3696 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3698 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
3700 else if (actual_fsize != 0)
3701 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3704 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3705 frame greater than 8k), do so now. */
3707 load_reg (2, ret_off, STACK_POINTER_REGNUM);
3709 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3711 rtx sa = EH_RETURN_STACKADJ_RTX;
3713 emit_insn (gen_blockage ());
3714 emit_insn (TARGET_64BIT
3715 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
3716 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
3721 hppa_pic_save_rtx ()
3723 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3727 hppa_profile_hook (label_no)
3730 rtx begin_label_rtx, call_insn;
3731 char begin_label_name[16];
3733 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3735 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3738 emit_move_insn (arg_pointer_rtx,
3739 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3742 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3744 #ifndef NO_PROFILE_COUNTERS
3746 rtx count_label_rtx, addr, r24;
3747 char count_label_name[16];
3749 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3750 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3752 addr = force_reg (Pmode, count_label_rtx);
3753 r24 = gen_rtx_REG (Pmode, 24);
3754 emit_move_insn (r24, addr);
3756 /* %r25 is set from within the output pattern. */
3758 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3759 GEN_INT (TARGET_64BIT ? 24 : 12),
3762 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3765 /* %r25 is set from within the output pattern. */
3767 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3768 GEN_INT (TARGET_64BIT ? 16 : 8),
3772 /* Indicate the _mcount call cannot throw, nor will it execute a
3774 REG_NOTES (call_insn)
3775 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3779 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3781 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3783 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3787 /* Fetch the return address for the frame COUNT steps up from
3788 the current frame, after the prologue. FRAMEADDR is the
3789 frame pointer of the COUNT frame.
3791 We want to ignore any export stub remnants here. To handle this,
3792 we examine the code at the return address, and if it is an export
3793 stub, we return a memory rtx for the stub return address stored
3796 The value returned is used in two different ways:
3798 1. To find a function's caller.
3800 2. To change the return address for a function.
3802 This function handles most instances of case 1; however, it will
3803 fail if there are two levels of stubs to execute on the return
3804 path. The only way I believe that can happen is if the return value
3805 needs a parameter relocation, which never happens for C code.
3807 This function handles most instances of case 2; however, it will
3808 fail if we did not originally have stub code on the return path
3809 but will need stub code on the new return path. This can happen if
3810 the caller & callee are both in the main program, but the new
3811 return location is in a shared library. */
3814 return_addr_rtx (count, frameaddr)
3826 rp = get_hard_reg_initial_val (Pmode, 2);
3828 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
3831 saved_rp = gen_reg_rtx (Pmode);
3832 emit_move_insn (saved_rp, rp);
3834 /* Get pointer to the instruction stream. We have to mask out the
3835 privilege level from the two low order bits of the return address
3836 pointer here so that ins will point to the start of the first
3837 instruction that would have been executed if we returned. */
3838 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
3839 label = gen_label_rtx ();
3841 /* Check the instruction stream at the normal return address for the
3844 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3845 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3846 0x00011820 | stub+16: mtsp r1,sr0
3847 0xe0400002 | stub+20: be,n 0(sr0,rp)
3849 If it is an export stub, than our return address is really in
3852 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
3853 NULL_RTX, SImode, 1);
3854 emit_jump_insn (gen_bne (label));
3856 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3857 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
3858 emit_jump_insn (gen_bne (label));
3860 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3861 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
3862 emit_jump_insn (gen_bne (label));
3864 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3865 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
3867 /* If there is no export stub then just use the value saved from
3868 the return pointer register. */
3870 emit_jump_insn (gen_bne (label));
3872 /* Here we know that our return address points to an export
3873 stub. We don't want to return the address of the export stub,
3874 but rather the return address of the export stub. That return
3875 address is stored at -24[frameaddr]. */
3877 emit_move_insn (saved_rp,
3879 memory_address (Pmode,
3880 plus_constant (frameaddr,
3887 /* This is only valid once reload has completed because it depends on
3888 knowing exactly how much (if any) frame there is and...
3890 It's only valid if there is no frame marker to de-allocate and...
3892 It's only valid if %r2 hasn't been saved into the caller's frame
3893 (we're not profiling and %r2 isn't live anywhere). */
3895 hppa_can_use_return_insn_p ()
3897 return (reload_completed
3898 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3899 && ! regs_ever_live[2]
3900 && ! frame_pointer_needed);
3904 emit_bcond_fp (code, operand0)
3908 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3909 gen_rtx_IF_THEN_ELSE (VOIDmode,
3910 gen_rtx_fmt_ee (code,
3912 gen_rtx_REG (CCFPmode, 0),
3914 gen_rtx_LABEL_REF (VOIDmode, operand0),
3920 gen_cmp_fp (code, operand0, operand1)
3922 rtx operand0, operand1;
3924 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3925 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3928 /* Adjust the cost of a scheduling dependency. Return the new cost of
3929 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3932 pa_adjust_cost (insn, link, dep_insn, cost)
3938 enum attr_type attr_type;
3940 /* Don't adjust costs for a pa8000 chip, also do not adjust any
3941 true dependencies as they are described with bypasses now. */
3942 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
3945 if (! recog_memoized (insn))
3948 attr_type = get_attr_type (insn);
3950 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3952 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3955 if (attr_type == TYPE_FPLOAD)
3957 rtx pat = PATTERN (insn);
3958 rtx dep_pat = PATTERN (dep_insn);
3959 if (GET_CODE (pat) == PARALLEL)
3961 /* This happens for the fldXs,mb patterns. */
3962 pat = XVECEXP (pat, 0, 0);
3964 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3965 /* If this happens, we have to extend this to schedule
3966 optimally. Return 0 for now. */
3969 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3971 if (! recog_memoized (dep_insn))
3973 switch (get_attr_type (dep_insn))
3980 case TYPE_FPSQRTSGL:
3981 case TYPE_FPSQRTDBL:
3982 /* A fpload can't be issued until one cycle before a
3983 preceding arithmetic operation has finished if
3984 the target of the fpload is any of the sources
3985 (or destination) of the arithmetic operation. */
3986 return insn_default_latency (dep_insn) - 1;
3993 else if (attr_type == TYPE_FPALU)
3995 rtx pat = PATTERN (insn);
3996 rtx dep_pat = PATTERN (dep_insn);
3997 if (GET_CODE (pat) == PARALLEL)
3999 /* This happens for the fldXs,mb patterns. */
4000 pat = XVECEXP (pat, 0, 0);
4002 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4003 /* If this happens, we have to extend this to schedule
4004 optimally. Return 0 for now. */
4007 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4009 if (! recog_memoized (dep_insn))
4011 switch (get_attr_type (dep_insn))
4015 case TYPE_FPSQRTSGL:
4016 case TYPE_FPSQRTDBL:
4017 /* An ALU flop can't be issued until two cycles before a
4018 preceding divide or sqrt operation has finished if
4019 the target of the ALU flop is any of the sources
4020 (or destination) of the divide or sqrt operation. */
4021 return insn_default_latency (dep_insn) - 2;
4029 /* For other anti dependencies, the cost is 0. */
4032 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4034 /* Output dependency; DEP_INSN writes a register that INSN writes some
4036 if (attr_type == TYPE_FPLOAD)
4038 rtx pat = PATTERN (insn);
4039 rtx dep_pat = PATTERN (dep_insn);
4040 if (GET_CODE (pat) == PARALLEL)
4042 /* This happens for the fldXs,mb patterns. */
4043 pat = XVECEXP (pat, 0, 0);
4045 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4046 /* If this happens, we have to extend this to schedule
4047 optimally. Return 0 for now. */
4050 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4052 if (! recog_memoized (dep_insn))
4054 switch (get_attr_type (dep_insn))
4061 case TYPE_FPSQRTSGL:
4062 case TYPE_FPSQRTDBL:
4063 /* A fpload can't be issued until one cycle before a
4064 preceding arithmetic operation has finished if
4065 the target of the fpload is the destination of the
4066 arithmetic operation.
4068 Exception: For PA7100LC, PA7200 and PA7300, the cost
4069 is 3 cycles, unless they bundle together. We also
4070 pay the penalty if the second insn is a fpload. */
4071 return insn_default_latency (dep_insn) - 1;
4078 else if (attr_type == TYPE_FPALU)
4080 rtx pat = PATTERN (insn);
4081 rtx dep_pat = PATTERN (dep_insn);
4082 if (GET_CODE (pat) == PARALLEL)
4084 /* This happens for the fldXs,mb patterns. */
4085 pat = XVECEXP (pat, 0, 0);
4087 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4088 /* If this happens, we have to extend this to schedule
4089 optimally. Return 0 for now. */
4092 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4094 if (! recog_memoized (dep_insn))
4096 switch (get_attr_type (dep_insn))
4100 case TYPE_FPSQRTSGL:
4101 case TYPE_FPSQRTDBL:
4102 /* An ALU flop can't be issued until two cycles before a
4103 preceding divide or sqrt operation has finished if
4104 the target of the ALU flop is also the target of
4105 the divide or sqrt operation. */
4106 return insn_default_latency (dep_insn) - 2;
4114 /* For other output dependencies, the cost is 0. */
4121 /* Adjust scheduling priorities. We use this to try and keep addil
4122 and the next use of %r1 close together. */
4124 pa_adjust_priority (insn, priority)
4128 rtx set = single_set (insn);
4132 src = SET_SRC (set);
4133 dest = SET_DEST (set);
4134 if (GET_CODE (src) == LO_SUM
4135 && symbolic_operand (XEXP (src, 1), VOIDmode)
4136 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4139 else if (GET_CODE (src) == MEM
4140 && GET_CODE (XEXP (src, 0)) == LO_SUM
4141 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4142 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4145 else if (GET_CODE (dest) == MEM
4146 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4147 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4148 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4154 /* The 700 can only issue a single insn at a time.
4155 The 7XXX processors can issue two insns at a time.
4156 The 8000 can issue 4 insns at a time. */
4162 case PROCESSOR_700: return 1;
4163 case PROCESSOR_7100: return 2;
4164 case PROCESSOR_7100LC: return 2;
4165 case PROCESSOR_7200: return 2;
4166 case PROCESSOR_7300: return 2;
4167 case PROCESSOR_8000: return 4;
4176 /* Return any length adjustment needed by INSN which already has its length
4177 computed as LENGTH. Return zero if no adjustment is necessary.
4179 For the PA: function calls, millicode calls, and backwards short
4180 conditional branches with unfilled delay slots need an adjustment by +1
4181 (to account for the NOP which will be inserted into the instruction stream).
4183 Also compute the length of an inline block move here as it is too
4184 complicated to express as a length attribute in pa.md. */
4186 pa_adjust_insn_length (insn, length)
4190 rtx pat = PATTERN (insn);
4192 /* Call insns which are *not* indirect and have unfilled delay slots. */
4193 if (GET_CODE (insn) == CALL_INSN)
4196 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4197 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4199 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4200 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4206 /* Jumps inside switch tables which have unfilled delay slots
4207 also need adjustment. */
4208 else if (GET_CODE (insn) == JUMP_INSN
4209 && simplejump_p (insn)
4210 && GET_MODE (insn) == SImode)
4212 /* Millicode insn with an unfilled delay slot. */
4213 else if (GET_CODE (insn) == INSN
4214 && GET_CODE (pat) != SEQUENCE
4215 && GET_CODE (pat) != USE
4216 && GET_CODE (pat) != CLOBBER
4217 && get_attr_type (insn) == TYPE_MILLI)
4219 /* Block move pattern. */
4220 else if (GET_CODE (insn) == INSN
4221 && GET_CODE (pat) == PARALLEL
4222 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4223 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4224 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4225 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4226 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4227 return compute_movstrsi_length (insn) - 4;
4228 /* Conditional branch with an unfilled delay slot. */
4229 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4231 /* Adjust a short backwards conditional with an unfilled delay slot. */
4232 if (GET_CODE (pat) == SET
4234 && ! forward_branch_p (insn))
4236 else if (GET_CODE (pat) == PARALLEL
4237 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4240 /* Adjust dbra insn with short backwards conditional branch with
4241 unfilled delay slot -- only for case where counter is in a
4242 general register register. */
4243 else if (GET_CODE (pat) == PARALLEL
4244 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4245 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4246 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4248 && ! forward_branch_p (insn))
4256 /* Print operand X (an rtx) in assembler syntax to file FILE.
4257 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4258 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4261 print_operand (file, x, code)
4269 /* Output a 'nop' if there's nothing for the delay slot. */
4270 if (dbr_sequence_length () == 0)
4271 fputs ("\n\tnop", file);
4274 /* Output an nullification completer if there's nothing for the */
4275 /* delay slot or nullification is requested. */
4276 if (dbr_sequence_length () == 0 ||
4278 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4282 /* Print out the second register name of a register pair.
4283 I.e., R (6) => 7. */
4284 fputs (reg_names[REGNO (x) + 1], file);
4287 /* A register or zero. */
4289 || (x == CONST0_RTX (DFmode))
4290 || (x == CONST0_RTX (SFmode)))
4292 fputs ("%r0", file);
4298 /* A register or zero (floating point). */
4300 || (x == CONST0_RTX (DFmode))
4301 || (x == CONST0_RTX (SFmode)))
4303 fputs ("%fr0", file);
4312 xoperands[0] = XEXP (XEXP (x, 0), 0);
4313 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4314 output_global_address (file, xoperands[1], 0);
4315 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4319 case 'C': /* Plain (C)ondition */
4321 switch (GET_CODE (x))
4324 fputs ("=", file); break;
4326 fputs ("<>", file); break;
4328 fputs (">", file); break;
4330 fputs (">=", file); break;
4332 fputs (">>=", file); break;
4334 fputs (">>", file); break;
4336 fputs ("<", file); break;
4338 fputs ("<=", file); break;
4340 fputs ("<<=", file); break;
4342 fputs ("<<", file); break;
4347 case 'N': /* Condition, (N)egated */
4348 switch (GET_CODE (x))
4351 fputs ("<>", file); break;
4353 fputs ("=", file); break;
4355 fputs ("<=", file); break;
4357 fputs ("<", file); break;
4359 fputs ("<<", file); break;
4361 fputs ("<<=", file); break;
4363 fputs (">=", file); break;
4365 fputs (">", file); break;
4367 fputs (">>", file); break;
4369 fputs (">>=", file); break;
4374 /* For floating point comparisons. Note that the output
4375 predicates are the complement of the desired mode. */
4377 switch (GET_CODE (x))
4380 fputs ("!=", file); break;
4382 fputs ("=", file); break;
4384 fputs ("!>", file); break;
4386 fputs ("!>=", file); break;
4388 fputs ("!<", file); break;
4390 fputs ("!<=", file); break;
4392 fputs ("!<>", file); break;
4394 fputs (">", file); break;
4396 fputs (">=", file); break;
4398 fputs ("<", file); break;
4400 fputs ("<=", file); break;
4402 fputs ("<>", file); break;
4404 fputs ("<=>", file); break;
4406 fputs ("!<=>", file); break;
4411 case 'S': /* Condition, operands are (S)wapped. */
4412 switch (GET_CODE (x))
4415 fputs ("=", file); break;
4417 fputs ("<>", file); break;
4419 fputs ("<", file); break;
4421 fputs ("<=", file); break;
4423 fputs ("<<=", file); break;
4425 fputs ("<<", file); break;
4427 fputs (">", file); break;
4429 fputs (">=", file); break;
4431 fputs (">>=", file); break;
4433 fputs (">>", file); break;
4438 case 'B': /* Condition, (B)oth swapped and negate. */
4439 switch (GET_CODE (x))
4442 fputs ("<>", file); break;
4444 fputs ("=", file); break;
4446 fputs (">=", file); break;
4448 fputs (">", file); break;
4450 fputs (">>", file); break;
4452 fputs (">>=", file); break;
4454 fputs ("<=", file); break;
4456 fputs ("<", file); break;
4458 fputs ("<<", file); break;
4460 fputs ("<<=", file); break;
4466 if (GET_CODE (x) == CONST_INT)
4468 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4473 if (GET_CODE (x) == CONST_INT)
4475 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4480 if (GET_CODE (x) == CONST_INT)
4482 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4487 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4489 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4494 if (GET_CODE (x) == CONST_INT)
4496 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4501 if (GET_CODE (x) == CONST_INT)
4503 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4508 if (GET_CODE (x) == CONST_INT)
4513 switch (GET_CODE (XEXP (x, 0)))
4517 if (ASSEMBLER_DIALECT == 0)
4518 fputs ("s,mb", file);
4520 fputs (",mb", file);
4524 if (ASSEMBLER_DIALECT == 0)
4525 fputs ("s,ma", file);
4527 fputs (",ma", file);
4530 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4531 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4533 if (ASSEMBLER_DIALECT == 0)
4534 fputs ("x,s", file);
4538 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4542 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4548 output_global_address (file, x, 0);
4551 output_global_address (file, x, 1);
4553 case 0: /* Don't do anything special */
4558 compute_zdepwi_operands (INTVAL (x), op);
4559 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4565 compute_zdepdi_operands (INTVAL (x), op);
4566 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4570 /* We can get here from a .vtable_inherit due to our
4571 CONSTANT_ADDRESS_P rejecting perfectly good constant
4577 if (GET_CODE (x) == REG)
4579 fputs (reg_names [REGNO (x)], file);
4580 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4586 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4587 && (REGNO (x) & 1) == 0)
4590 else if (GET_CODE (x) == MEM)
4592 int size = GET_MODE_SIZE (GET_MODE (x));
4593 rtx base = NULL_RTX;
4594 switch (GET_CODE (XEXP (x, 0)))
4598 base = XEXP (XEXP (x, 0), 0);
4599 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4603 base = XEXP (XEXP (x, 0), 0);
4604 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4607 if (GET_CODE (XEXP (x, 0)) == PLUS
4608 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4609 fprintf (file, "%s(%s)",
4610 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4611 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4612 else if (GET_CODE (XEXP (x, 0)) == PLUS
4613 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4614 fprintf (file, "%s(%s)",
4615 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4616 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4618 output_address (XEXP (x, 0));
4623 output_addr_const (file, x);
4626 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4629 output_global_address (file, x, round_constant)
4635 /* Imagine (high (const (plus ...))). */
4636 if (GET_CODE (x) == HIGH)
4639 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4640 assemble_name (file, XSTR (x, 0));
4641 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4643 assemble_name (file, XSTR (x, 0));
4644 fputs ("-$global$", file);
4646 else if (GET_CODE (x) == CONST)
4648 const char *sep = "";
4649 int offset = 0; /* assembler wants -$global$ at end */
4650 rtx base = NULL_RTX;
4652 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4654 base = XEXP (XEXP (x, 0), 0);
4655 output_addr_const (file, base);
4657 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4658 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4661 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4663 base = XEXP (XEXP (x, 0), 1);
4664 output_addr_const (file, base);
4666 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4667 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4670 /* How bogus. The compiler is apparently responsible for
4671 rounding the constant if it uses an LR field selector.
4673 The linker and/or assembler seem a better place since
4674 they have to do this kind of thing already.
4676 If we fail to do this, HP's optimizing linker may eliminate
4677 an addil, but not update the ldw/stw/ldo instruction that
4678 uses the result of the addil. */
4680 offset = ((offset + 0x1000) & ~0x1fff);
4682 if (GET_CODE (XEXP (x, 0)) == PLUS)
4692 else if (GET_CODE (XEXP (x, 0)) == MINUS
4693 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4697 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4698 fputs ("-$global$", file);
4700 fprintf (file, "%s%d", sep, offset);
4703 output_addr_const (file, x);
4707 output_deferred_plabels (file)
4711 /* If we have deferred plabels, then we need to switch into the data
4712 section and align it to a 4 byte boundary before we output the
4713 deferred plabels. */
4714 if (n_deferred_plabels)
4717 ASM_OUTPUT_ALIGN (file, 2);
4720 /* Now output the deferred plabels. */
4721 for (i = 0; i < n_deferred_plabels; i++)
4723 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4724 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4725 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
4729 /* HP's millicode routines mean something special to the assembler.
4730 Keep track of which ones we have used. */
4732 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
4733 static void import_milli PARAMS ((enum millicodes));
4734 static char imported[(int) end1000];
4735 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4736 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4737 #define MILLI_START 10
4741 enum millicodes code;
4743 char str[sizeof (import_string)];
4745 if (!imported[(int) code])
4747 imported[(int) code] = 1;
4748 strcpy (str, import_string);
4749 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4750 output_asm_insn (str, 0);
4754 /* The register constraints have put the operands and return value in
4755 the proper registers. */
4758 output_mul_insn (unsignedp, insn)
4759 int unsignedp ATTRIBUTE_UNUSED;
4762 import_milli (mulI);
4763 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4766 /* Emit the rtl for doing a division by a constant. */
4768 /* Do magic division millicodes exist for this value? */
4769 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4772 /* We'll use an array to keep track of the magic millicodes and
4773 whether or not we've used them already. [n][0] is signed, [n][1] is
4776 static int div_milli[16][2];
4779 div_operand (op, mode)
4781 enum machine_mode mode;
4783 return (mode == SImode
4784 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4785 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4786 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4790 emit_hpdiv_const (operands, unsignedp)
4794 if (GET_CODE (operands[2]) == CONST_INT
4795 && INTVAL (operands[2]) > 0
4796 && INTVAL (operands[2]) < 16
4797 && magic_milli[INTVAL (operands[2])])
4799 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4801 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4804 (PARALLEL, VOIDmode,
4805 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4806 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4808 gen_rtx_REG (SImode, 26),
4810 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4811 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4812 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4813 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4814 gen_rtx_CLOBBER (VOIDmode, ret))));
4815 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4822 output_div_insn (operands, unsignedp, insn)
4829 /* If the divisor is a constant, try to use one of the special
4831 if (GET_CODE (operands[0]) == CONST_INT)
4833 static char buf[100];
4834 divisor = INTVAL (operands[0]);
4835 if (!div_milli[divisor][unsignedp])
4837 div_milli[divisor][unsignedp] = 1;
4839 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4841 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4845 sprintf (buf, "$$divU_");
4846 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4847 return output_millicode_call (insn,
4848 gen_rtx_SYMBOL_REF (SImode, buf));
4852 sprintf (buf, "$$divI_");
4853 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4854 return output_millicode_call (insn,
4855 gen_rtx_SYMBOL_REF (SImode, buf));
4858 /* Divisor isn't a special constant. */
4863 import_milli (divU);
4864 return output_millicode_call (insn,
4865 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4869 import_milli (divI);
4870 return output_millicode_call (insn,
4871 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4876 /* Output a $$rem millicode to do mod. */
4879 output_mod_insn (unsignedp, insn)
4885 import_milli (remU);
4886 return output_millicode_call (insn,
4887 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4891 import_milli (remI);
4892 return output_millicode_call (insn,
4893 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4898 output_arg_descriptor (call_insn)
4901 const char *arg_regs[4];
4902 enum machine_mode arg_mode;
4904 int i, output_flag = 0;
4907 /* We neither need nor want argument location descriptors for the
4908 64bit runtime environment or the ELF32 environment. */
4909 if (TARGET_64BIT || TARGET_ELF32)
4912 for (i = 0; i < 4; i++)
4915 /* Specify explicitly that no argument relocations should take place
4916 if using the portable runtime calling conventions. */
4917 if (TARGET_PORTABLE_RUNTIME)
4919 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4924 if (GET_CODE (call_insn) != CALL_INSN)
4926 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4928 rtx use = XEXP (link, 0);
4930 if (! (GET_CODE (use) == USE
4931 && GET_CODE (XEXP (use, 0)) == REG
4932 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4935 arg_mode = GET_MODE (XEXP (use, 0));
4936 regno = REGNO (XEXP (use, 0));
4937 if (regno >= 23 && regno <= 26)
4939 arg_regs[26 - regno] = "GR";
4940 if (arg_mode == DImode)
4941 arg_regs[25 - regno] = "GR";
4943 else if (regno >= 32 && regno <= 39)
4945 if (arg_mode == SFmode)
4946 arg_regs[(regno - 32) / 2] = "FR";
4949 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4950 arg_regs[(regno - 34) / 2] = "FR";
4951 arg_regs[(regno - 34) / 2 + 1] = "FU";
4953 arg_regs[(regno - 34) / 2] = "FU";
4954 arg_regs[(regno - 34) / 2 + 1] = "FR";
4959 fputs ("\t.CALL ", asm_out_file);
4960 for (i = 0; i < 4; i++)
4965 fputc (',', asm_out_file);
4966 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4969 fputc ('\n', asm_out_file);
4972 /* Return the class of any secondary reload register that is needed to
4973 move IN into a register in class CLASS using mode MODE.
4975 Profiling has showed this routine and its descendants account for
4976 a significant amount of compile time (~7%). So it has been
4977 optimized to reduce redundant computations and eliminate useless
4980 It might be worthwhile to try and make this a leaf function too. */
4983 secondary_reload_class (class, mode, in)
4984 enum reg_class class;
4985 enum machine_mode mode;
4988 int regno, is_symbolic;
4990 /* Trying to load a constant into a FP register during PIC code
4991 generation will require %r1 as a scratch register. */
4993 && GET_MODE_CLASS (mode) == MODE_INT
4994 && FP_REG_CLASS_P (class)
4995 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4998 /* Profiling showed the PA port spends about 1.3% of its compilation
4999 time in true_regnum from calls inside secondary_reload_class. */
5001 if (GET_CODE (in) == REG)
5004 if (regno >= FIRST_PSEUDO_REGISTER)
5005 regno = true_regnum (in);
5007 else if (GET_CODE (in) == SUBREG)
5008 regno = true_regnum (in);
5012 /* If we have something like (mem (mem (...)), we can safely assume the
5013 inner MEM will end up in a general register after reloading, so there's
5014 no need for a secondary reload. */
5015 if (GET_CODE (in) == MEM
5016 && GET_CODE (XEXP (in, 0)) == MEM)
5019 /* Handle out of range displacement for integer mode loads/stores of
5021 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5022 && GET_MODE_CLASS (mode) == MODE_INT
5023 && FP_REG_CLASS_P (class))
5024 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5025 return GENERAL_REGS;
5027 /* A SAR<->FP register copy requires a secondary register (GPR) as
5028 well as secondary memory. */
5029 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5030 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5031 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5032 return GENERAL_REGS;
5034 if (GET_CODE (in) == HIGH)
5037 /* Profiling has showed GCC spends about 2.6% of its compilation
5038 time in symbolic_operand from calls inside secondary_reload_class.
5040 We use an inline copy and only compute its return value once to avoid
5042 switch (GET_CODE (in))
5052 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5053 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5054 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5064 && read_only_operand (in, VOIDmode))
5067 if (class != R1_REGS && is_symbolic)
5074 function_arg_padding (mode, type)
5075 enum machine_mode mode;
5080 if (mode == BLKmode)
5082 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
5083 size = int_size_in_bytes (type) * BITS_PER_UNIT;
5085 return upward; /* Don't know if this is right, but */
5086 /* same as old definition. */
5089 size = GET_MODE_BITSIZE (mode);
5090 if (size < PARM_BOUNDARY)
5092 else if (size % PARM_BOUNDARY)
5099 /* Do what is necessary for `va_start'. We look at the current function
5100 to determine if stdargs or varargs is used and fill in an initial
5101 va_list. A pointer to this constructor is returned. */
5104 hppa_builtin_saveregs ()
5107 tree fntype = TREE_TYPE (current_function_decl);
5108 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5109 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5110 != void_type_node)))
5111 ? UNITS_PER_WORD : 0);
5114 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5116 offset = current_function_arg_offset_rtx;
5122 /* Adjust for varargs/stdarg differences. */
5124 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5126 offset = current_function_arg_offset_rtx;
5128 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5129 from the incoming arg pointer and growing to larger addresses. */
5130 for (i = 26, off = -64; i >= 19; i--, off += 8)
5131 emit_move_insn (gen_rtx_MEM (word_mode,
5132 plus_constant (arg_pointer_rtx, off)),
5133 gen_rtx_REG (word_mode, i));
5135 /* The incoming args pointer points just beyond the flushback area;
5136 normally this is not a serious concern. However, when we are doing
5137 varargs/stdargs we want to make the arg pointer point to the start
5138 of the incoming argument area. */
5139 emit_move_insn (virtual_incoming_args_rtx,
5140 plus_constant (arg_pointer_rtx, -64));
5142 /* Now return a pointer to the first anonymous argument. */
5143 return copy_to_reg (expand_binop (Pmode, add_optab,
5144 virtual_incoming_args_rtx,
5145 offset, 0, 0, OPTAB_LIB_WIDEN));
5148 /* Store general registers on the stack. */
5149 dest = gen_rtx_MEM (BLKmode,
5150 plus_constant (current_function_internal_arg_pointer,
5152 set_mem_alias_set (dest, get_varargs_alias_set ());
5153 set_mem_align (dest, BITS_PER_WORD);
5154 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
5156 /* move_block_from_reg will emit code to store the argument registers
5157 individually as scalar stores.
5159 However, other insns may later load from the same addresses for
5160 a structure load (passing a struct to a varargs routine).
5162 The alias code assumes that such aliasing can never happen, so we
5163 have to keep memory referencing insns from moving up beyond the
5164 last argument register store. So we emit a blockage insn here. */
5165 emit_insn (gen_blockage ());
5167 return copy_to_reg (expand_binop (Pmode, add_optab,
5168 current_function_internal_arg_pointer,
5169 offset, 0, 0, OPTAB_LIB_WIDEN));
5173 hppa_va_start (stdarg_p, valist, nextarg)
5174 int stdarg_p ATTRIBUTE_UNUSED;
5178 nextarg = expand_builtin_saveregs ();
5179 std_expand_builtin_va_start (1, valist, nextarg);
5183 hppa_va_arg (valist, type)
5186 HOST_WIDE_INT align, size, ofs;
5191 /* Every argument in PA64 is passed by value (including large structs).
5192 Arguments with size greater than 8 must be aligned 0 MOD 16. */
5194 size = int_size_in_bytes (type);
5195 if (size > UNITS_PER_WORD)
5197 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5198 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5199 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5200 build_int_2 (-2 * UNITS_PER_WORD, -1));
5201 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5202 TREE_SIDE_EFFECTS (t) = 1;
5203 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5205 return std_expand_builtin_va_arg (valist, type);
5208 /* Compute the rounded size of the type. */
5209 align = PARM_BOUNDARY / BITS_PER_UNIT;
5210 size = int_size_in_bytes (type);
5212 ptr = build_pointer_type (type);
5214 /* "Large" types are passed by reference. */
5217 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5218 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5219 TREE_SIDE_EFFECTS (t) = 1;
5221 pptr = build_pointer_type (ptr);
5222 t = build1 (NOP_EXPR, pptr, t);
5223 TREE_SIDE_EFFECTS (t) = 1;
5225 t = build1 (INDIRECT_REF, ptr, t);
5226 TREE_SIDE_EFFECTS (t) = 1;
5230 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5231 build_int_2 (-size, -1));
5233 /* Copied from va-pa.h, but we probably don't need to align
5234 to word size, since we generate and preserve that invariant. */
5235 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5236 build_int_2 ((size > 4 ? -8 : -4), -1));
5238 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5239 TREE_SIDE_EFFECTS (t) = 1;
5241 ofs = (8 - size) % 4;
5244 t = build (PLUS_EXPR, TREE_TYPE (valist), t, build_int_2 (ofs, 0));
5245 TREE_SIDE_EFFECTS (t) = 1;
5248 t = build1 (NOP_EXPR, ptr, t);
5249 TREE_SIDE_EFFECTS (t) = 1;
5253 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
5258 /* This routine handles all the normal conditional branch sequences we
5259 might need to generate. It handles compare immediate vs compare
5260 register, nullification of delay slots, varying length branches,
5261 negated branches, and all combinations of the above. It returns the
5262 output appropriate to emit the branch corresponding to all given
5266 output_cbranch (operands, nullify, length, negated, insn)
5268 int nullify, length, negated;
5271 static char buf[100];
5274 /* A conditional branch to the following instruction (eg the delay slot) is
5275 asking for a disaster. This can happen when not optimizing.
5277 In such cases it is safe to emit nothing. */
5279 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5282 /* If this is a long branch with its delay slot unfilled, set `nullify'
5283 as it can nullify the delay slot and save a nop. */
5284 if (length == 8 && dbr_sequence_length () == 0)
5287 /* If this is a short forward conditional branch which did not get
5288 its delay slot filled, the delay slot can still be nullified. */
5289 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5290 nullify = forward_branch_p (insn);
5292 /* A forward branch over a single nullified insn can be done with a
5293 comclr instruction. This avoids a single cycle penalty due to
5294 mis-predicted branch if we fall through (branch not taken). */
5296 && next_real_insn (insn) != 0
5297 && get_attr_length (next_real_insn (insn)) == 4
5298 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5304 /* All short conditional branches except backwards with an unfilled
5308 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5310 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5311 if (GET_MODE (operands[1]) == DImode)
5314 strcat (buf, "%B3");
5316 strcat (buf, "%S3");
5318 strcat (buf, " %2,%r1,%%r0");
5320 strcat (buf, ",n %2,%r1,%0");
5322 strcat (buf, " %2,%r1,%0");
5325 /* All long conditionals. Note an short backward branch with an
5326 unfilled delay slot is treated just like a long backward branch
5327 with an unfilled delay slot. */
5329 /* Handle weird backwards branch with a filled delay slot
5330 with is nullified. */
5331 if (dbr_sequence_length () != 0
5332 && ! forward_branch_p (insn)
5335 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5336 if (GET_MODE (operands[1]) == DImode)
5339 strcat (buf, "%S3");
5341 strcat (buf, "%B3");
5342 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5344 /* Handle short backwards branch with an unfilled delay slot.
5345 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5346 taken and untaken branches. */
5347 else if (dbr_sequence_length () == 0
5348 && ! forward_branch_p (insn)
5349 && INSN_ADDRESSES_SET_P ()
5350 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5351 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5353 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5354 if (GET_MODE (operands[1]) == DImode)
5357 strcat (buf, "%B3 %2,%r1,%0%#");
5359 strcat (buf, "%S3 %2,%r1,%0%#");
5363 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5364 if (GET_MODE (operands[1]) == DImode)
5367 strcat (buf, "%S3");
5369 strcat (buf, "%B3");
5371 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5373 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5378 /* Very long branch. Right now we only handle these when not
5379 optimizing. See "jump" pattern in pa.md for details. */
5383 /* Create a reversed conditional branch which branches around
5384 the following insns. */
5386 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5388 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5389 if (GET_MODE (operands[1]) == DImode)
5393 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5396 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5398 output_asm_insn (buf, operands);
5400 /* Output an insn to save %r1. */
5401 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5403 /* Now output a very long branch to the original target. */
5404 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5406 /* Now restore the value of %r1 in the delay slot. We're not
5407 optimizing so we know nothing else can be in the delay slot. */
5408 return "ldw -16(%%r30),%%r1";
5411 /* Very long branch when generating PIC code. Right now we only
5412 handle these when not optimizing. See "jump" pattern in pa.md
5417 /* Create a reversed conditional branch which branches around
5418 the following insns. */
5420 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5422 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5423 if (GET_MODE (operands[1]) == DImode)
5426 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5428 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5430 output_asm_insn (buf, operands);
5432 /* Output an insn to save %r1. */
5433 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5435 /* Now output a very long PIC branch to the original target. */
5439 xoperands[0] = operands[0];
5440 xoperands[1] = operands[1];
5441 xoperands[2] = operands[2];
5442 xoperands[3] = operands[3];
5443 if (TARGET_SOM || ! TARGET_GAS)
5444 xoperands[4] = gen_label_rtx ();
5446 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5447 if (TARGET_SOM || ! TARGET_GAS)
5449 output_asm_insn ("addil L'%l0-%l4,%%r1", xoperands);
5450 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5451 CODE_LABEL_NUMBER (xoperands[4]));
5452 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1", xoperands);
5456 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
5457 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1",
5460 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5463 /* Now restore the value of %r1 in the delay slot. We're not
5464 optimizing so we know nothing else can be in the delay slot. */
5465 return "ldw -16(%%r30),%%r1";
5473 /* This routine handles all the branch-on-bit conditional branch sequences we
5474 might need to generate. It handles nullification of delay slots,
5475 varying length branches, negated branches and all combinations of the
5476 above. it returns the appropriate output template to emit the branch. */
5479 output_bb (operands, nullify, length, negated, insn, which)
5480 rtx *operands ATTRIBUTE_UNUSED;
5481 int nullify, length, negated;
5485 static char buf[100];
5488 /* A conditional branch to the following instruction (eg the delay slot) is
5489 asking for a disaster. I do not think this can happen as this pattern
5490 is only used when optimizing; jump optimization should eliminate the
5491 jump. But be prepared just in case. */
5493 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5496 /* If this is a long branch with its delay slot unfilled, set `nullify'
5497 as it can nullify the delay slot and save a nop. */
5498 if (length == 8 && dbr_sequence_length () == 0)
5501 /* If this is a short forward conditional branch which did not get
5502 its delay slot filled, the delay slot can still be nullified. */
5503 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5504 nullify = forward_branch_p (insn);
5506 /* A forward branch over a single nullified insn can be done with a
5507 extrs instruction. This avoids a single cycle penalty due to
5508 mis-predicted branch if we fall through (branch not taken). */
5511 && next_real_insn (insn) != 0
5512 && get_attr_length (next_real_insn (insn)) == 4
5513 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5520 /* All short conditional branches except backwards with an unfilled
5524 strcpy (buf, "{extrs,|extrw,s,}");
5526 strcpy (buf, "bb,");
5527 if (useskip && GET_MODE (operands[0]) == DImode)
5528 strcpy (buf, "extrd,s,*");
5529 else if (GET_MODE (operands[0]) == DImode)
5530 strcpy (buf, "bb,*");
5531 if ((which == 0 && negated)
5532 || (which == 1 && ! negated))
5537 strcat (buf, " %0,%1,1,%%r0");
5538 else if (nullify && negated)
5539 strcat (buf, ",n %0,%1,%3");
5540 else if (nullify && ! negated)
5541 strcat (buf, ",n %0,%1,%2");
5542 else if (! nullify && negated)
5543 strcat (buf, "%0,%1,%3");
5544 else if (! nullify && ! negated)
5545 strcat (buf, " %0,%1,%2");
5548 /* All long conditionals. Note an short backward branch with an
5549 unfilled delay slot is treated just like a long backward branch
5550 with an unfilled delay slot. */
5552 /* Handle weird backwards branch with a filled delay slot
5553 with is nullified. */
5554 if (dbr_sequence_length () != 0
5555 && ! forward_branch_p (insn)
5558 strcpy (buf, "bb,");
5559 if (GET_MODE (operands[0]) == DImode)
5561 if ((which == 0 && negated)
5562 || (which == 1 && ! negated))
5567 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5569 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5571 /* Handle short backwards branch with an unfilled delay slot.
5572 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5573 taken and untaken branches. */
5574 else if (dbr_sequence_length () == 0
5575 && ! forward_branch_p (insn)
5576 && INSN_ADDRESSES_SET_P ()
5577 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5578 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5580 strcpy (buf, "bb,");
5581 if (GET_MODE (operands[0]) == DImode)
5583 if ((which == 0 && negated)
5584 || (which == 1 && ! negated))
5589 strcat (buf, " %0,%1,%3%#");
5591 strcat (buf, " %0,%1,%2%#");
5595 strcpy (buf, "{extrs,|extrw,s,}");
5596 if (GET_MODE (operands[0]) == DImode)
5597 strcpy (buf, "extrd,s,*");
5598 if ((which == 0 && negated)
5599 || (which == 1 && ! negated))
5603 if (nullify && negated)
5604 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5605 else if (nullify && ! negated)
5606 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5608 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5610 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5620 /* This routine handles all the branch-on-variable-bit conditional branch
5621 sequences we might need to generate. It handles nullification of delay
5622 slots, varying length branches, negated branches and all combinations
5623 of the above. it returns the appropriate output template to emit the
5627 output_bvb (operands, nullify, length, negated, insn, which)
5628 rtx *operands ATTRIBUTE_UNUSED;
5629 int nullify, length, negated;
5633 static char buf[100];
5636 /* A conditional branch to the following instruction (eg the delay slot) is
5637 asking for a disaster. I do not think this can happen as this pattern
5638 is only used when optimizing; jump optimization should eliminate the
5639 jump. But be prepared just in case. */
5641 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5644 /* If this is a long branch with its delay slot unfilled, set `nullify'
5645 as it can nullify the delay slot and save a nop. */
5646 if (length == 8 && dbr_sequence_length () == 0)
5649 /* If this is a short forward conditional branch which did not get
5650 its delay slot filled, the delay slot can still be nullified. */
5651 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5652 nullify = forward_branch_p (insn);
5654 /* A forward branch over a single nullified insn can be done with a
5655 extrs instruction. This avoids a single cycle penalty due to
5656 mis-predicted branch if we fall through (branch not taken). */
5659 && next_real_insn (insn) != 0
5660 && get_attr_length (next_real_insn (insn)) == 4
5661 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5668 /* All short conditional branches except backwards with an unfilled
5672 strcpy (buf, "{vextrs,|extrw,s,}");
5674 strcpy (buf, "{bvb,|bb,}");
5675 if (useskip && GET_MODE (operands[0]) == DImode)
5676 strcpy (buf, "extrd,s,*}");
5677 else if (GET_MODE (operands[0]) == DImode)
5678 strcpy (buf, "bb,*");
5679 if ((which == 0 && negated)
5680 || (which == 1 && ! negated))
5685 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5686 else if (nullify && negated)
5687 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5688 else if (nullify && ! negated)
5689 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5690 else if (! nullify && negated)
5691 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5692 else if (! nullify && ! negated)
5693 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5696 /* All long conditionals. Note an short backward branch with an
5697 unfilled delay slot is treated just like a long backward branch
5698 with an unfilled delay slot. */
5700 /* Handle weird backwards branch with a filled delay slot
5701 with is nullified. */
5702 if (dbr_sequence_length () != 0
5703 && ! forward_branch_p (insn)
5706 strcpy (buf, "{bvb,|bb,}");
5707 if (GET_MODE (operands[0]) == DImode)
5709 if ((which == 0 && negated)
5710 || (which == 1 && ! negated))
5715 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5717 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5719 /* Handle short backwards branch with an unfilled delay slot.
5720 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5721 taken and untaken branches. */
5722 else if (dbr_sequence_length () == 0
5723 && ! forward_branch_p (insn)
5724 && INSN_ADDRESSES_SET_P ()
5725 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5726 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5728 strcpy (buf, "{bvb,|bb,}");
5729 if (GET_MODE (operands[0]) == DImode)
5731 if ((which == 0 && negated)
5732 || (which == 1 && ! negated))
5737 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5739 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5743 strcpy (buf, "{vextrs,|extrw,s,}");
5744 if (GET_MODE (operands[0]) == DImode)
5745 strcpy (buf, "extrd,s,*");
5746 if ((which == 0 && negated)
5747 || (which == 1 && ! negated))
5751 if (nullify && negated)
5752 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5753 else if (nullify && ! negated)
5754 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5756 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5758 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5768 /* Return the output template for emitting a dbra type insn.
5770 Note it may perform some output operations on its own before
5771 returning the final output string. */
5773 output_dbra (operands, insn, which_alternative)
5776 int which_alternative;
5779 /* A conditional branch to the following instruction (eg the delay slot) is
5780 asking for a disaster. Be prepared! */
5782 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5784 if (which_alternative == 0)
5785 return "ldo %1(%0),%0";
5786 else if (which_alternative == 1)
5788 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5789 output_asm_insn ("ldw -16(%%r30),%4", operands);
5790 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5791 return "{fldws|fldw} -16(%%r30),%0";
5795 output_asm_insn ("ldw %0,%4", operands);
5796 return "ldo %1(%4),%4\n\tstw %4,%0";
5800 if (which_alternative == 0)
5802 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5803 int length = get_attr_length (insn);
5805 /* If this is a long branch with its delay slot unfilled, set `nullify'
5806 as it can nullify the delay slot and save a nop. */
5807 if (length == 8 && dbr_sequence_length () == 0)
5810 /* If this is a short forward conditional branch which did not get
5811 its delay slot filled, the delay slot can still be nullified. */
5812 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5813 nullify = forward_branch_p (insn);
5815 /* Handle short versions first. */
5816 if (length == 4 && nullify)
5817 return "addib,%C2,n %1,%0,%3";
5818 else if (length == 4 && ! nullify)
5819 return "addib,%C2 %1,%0,%3";
5820 else if (length == 8)
5822 /* Handle weird backwards branch with a fulled delay slot
5823 which is nullified. */
5824 if (dbr_sequence_length () != 0
5825 && ! forward_branch_p (insn)
5827 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5828 /* Handle short backwards branch with an unfilled delay slot.
5829 Using a addb;nop rather than addi;bl saves 1 cycle for both
5830 taken and untaken branches. */
5831 else if (dbr_sequence_length () == 0
5832 && ! forward_branch_p (insn)
5833 && INSN_ADDRESSES_SET_P ()
5834 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5835 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5836 return "addib,%C2 %1,%0,%3%#";
5838 /* Handle normal cases. */
5840 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5842 return "addi,%N2 %1,%0,%0\n\tb %3";
5847 /* Deal with gross reload from FP register case. */
5848 else if (which_alternative == 1)
5850 /* Move loop counter from FP register to MEM then into a GR,
5851 increment the GR, store the GR into MEM, and finally reload
5852 the FP register from MEM from within the branch's delay slot. */
5853 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5855 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5856 if (get_attr_length (insn) == 24)
5857 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5859 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5861 /* Deal with gross reload from memory case. */
5864 /* Reload loop counter from memory, the store back to memory
5865 happens in the branch's delay slot. */
5866 output_asm_insn ("ldw %0,%4", operands);
5867 if (get_attr_length (insn) == 12)
5868 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5870 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5874 /* Return the output template for emitting a dbra type insn.
5876 Note it may perform some output operations on its own before
5877 returning the final output string. */
5879 output_movb (operands, insn, which_alternative, reverse_comparison)
5882 int which_alternative;
5883 int reverse_comparison;
5886 /* A conditional branch to the following instruction (eg the delay slot) is
5887 asking for a disaster. Be prepared! */
5889 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5891 if (which_alternative == 0)
5892 return "copy %1,%0";
5893 else if (which_alternative == 1)
5895 output_asm_insn ("stw %1,-16(%%r30)", operands);
5896 return "{fldws|fldw} -16(%%r30),%0";
5898 else if (which_alternative == 2)
5904 /* Support the second variant. */
5905 if (reverse_comparison)
5906 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5908 if (which_alternative == 0)
5910 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5911 int length = get_attr_length (insn);
5913 /* If this is a long branch with its delay slot unfilled, set `nullify'
5914 as it can nullify the delay slot and save a nop. */
5915 if (length == 8 && dbr_sequence_length () == 0)
5918 /* If this is a short forward conditional branch which did not get
5919 its delay slot filled, the delay slot can still be nullified. */
5920 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5921 nullify = forward_branch_p (insn);
5923 /* Handle short versions first. */
5924 if (length == 4 && nullify)
5925 return "movb,%C2,n %1,%0,%3";
5926 else if (length == 4 && ! nullify)
5927 return "movb,%C2 %1,%0,%3";
5928 else if (length == 8)
5930 /* Handle weird backwards branch with a filled delay slot
5931 which is nullified. */
5932 if (dbr_sequence_length () != 0
5933 && ! forward_branch_p (insn)
5935 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5937 /* Handle short backwards branch with an unfilled delay slot.
5938 Using a movb;nop rather than or;bl saves 1 cycle for both
5939 taken and untaken branches. */
5940 else if (dbr_sequence_length () == 0
5941 && ! forward_branch_p (insn)
5942 && INSN_ADDRESSES_SET_P ()
5943 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5944 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5945 return "movb,%C2 %1,%0,%3%#";
5946 /* Handle normal cases. */
5948 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5950 return "or,%N2 %1,%%r0,%0\n\tb %3";
5955 /* Deal with gross reload from FP register case. */
5956 else if (which_alternative == 1)
5958 /* Move loop counter from FP register to MEM then into a GR,
5959 increment the GR, store the GR into MEM, and finally reload
5960 the FP register from MEM from within the branch's delay slot. */
5961 output_asm_insn ("stw %1,-16(%%r30)", operands);
5962 if (get_attr_length (insn) == 12)
5963 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
5965 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5967 /* Deal with gross reload from memory case. */
5968 else if (which_alternative == 2)
5970 /* Reload loop counter from memory, the store back to memory
5971 happens in the branch's delay slot. */
5972 if (get_attr_length (insn) == 8)
5973 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
5975 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5977 /* Handle SAR as a destination. */
5980 if (get_attr_length (insn) == 8)
5981 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
5983 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5988 /* INSN is a millicode call. It may have an unconditional jump in its delay
5991 CALL_DEST is the routine we are calling. */
5994 output_millicode_call (insn, call_dest)
5998 int attr_length = get_attr_length (insn);
5999 int seq_length = dbr_sequence_length ();
6004 xoperands[3] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6006 /* Handle common case -- empty delay slot or no jump in the delay slot,
6007 and we're sure that the branch will reach the beginning of the $CODE$
6008 subspace. The within reach form of the $$sh_func_adrs call has
6009 a length of 28 and attribute type of multi. This length is the
6010 same as the maximum length of an out of reach PIC call to $$div. */
6011 if ((seq_length == 0
6012 && (attr_length == 8
6013 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6015 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6016 && attr_length == 4))
6018 xoperands[0] = call_dest;
6019 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
6023 /* This call may not reach the beginning of the $CODE$ subspace. */
6024 if (attr_length > 8)
6026 int delay_insn_deleted = 0;
6028 /* We need to emit an inline long-call branch. */
6030 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6032 /* A non-jump insn in the delay slot. By definition we can
6033 emit this insn before the call. */
6034 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6036 /* Now delete the delay insn. */
6037 PUT_CODE (NEXT_INSN (insn), NOTE);
6038 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6039 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6040 delay_insn_deleted = 1;
6043 /* PIC long millicode call sequence. */
6046 xoperands[0] = call_dest;
6047 if (TARGET_SOM || ! TARGET_GAS)
6048 xoperands[1] = gen_label_rtx ();
6050 /* Get our address + 8 into %r1. */
6051 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6053 if (TARGET_SOM || ! TARGET_GAS)
6055 /* Add %r1 to the offset of our target from the next insn. */
6056 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
6057 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6058 CODE_LABEL_NUMBER (xoperands[1]));
6059 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
6063 output_asm_insn ("addil L%%%0-$PIC_pcrel$0+4,%%r1", xoperands);
6064 output_asm_insn ("ldo R%%%0-$PIC_pcrel$0+8(%%r1),%%r1",
6068 /* Get the return address into %r31. */
6069 output_asm_insn ("blr 0,%3", xoperands);
6071 /* Branch to our target which is in %r1. */
6072 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
6074 /* Empty delay slot. Note this insn gets fetched twice and
6075 executed once. To be safe we use a nop. */
6076 output_asm_insn ("nop", xoperands);
6078 /* Pure portable runtime doesn't allow be/ble; we also don't have
6079 PIC support in the assembler/linker, so this sequence is needed. */
6080 else if (TARGET_PORTABLE_RUNTIME)
6082 xoperands[0] = call_dest;
6083 /* Get the address of our target into %r29. */
6084 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
6085 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
6087 /* Get our return address into %r31. */
6088 output_asm_insn ("blr %%r0,%3", xoperands);
6090 /* Jump to our target address in %r29. */
6091 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
6093 /* Empty delay slot. Note this insn gets fetched twice and
6094 executed once. To be safe we use a nop. */
6095 output_asm_insn ("nop", xoperands);
6097 /* If we're allowed to use be/ble instructions, then this is the
6098 best sequence to use for a long millicode call. */
6101 xoperands[0] = call_dest;
6102 output_asm_insn ("ldil L%%%0,%3", xoperands);
6104 output_asm_insn ("be,l R%%%0(%%sr4,%3),%%sr0,%%r31", xoperands);
6106 output_asm_insn ("ble R%%%0(%%sr4,%3)", xoperands);
6107 output_asm_insn ("nop", xoperands);
6110 /* If we had a jump in the call's delay slot, output it now. */
6111 if (seq_length != 0 && !delay_insn_deleted)
6113 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6114 output_asm_insn ("b,n %0", xoperands);
6116 /* Now delete the delay insn. */
6117 PUT_CODE (NEXT_INSN (insn), NOTE);
6118 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6119 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6124 /* This call has an unconditional jump in its delay slot and the
6125 call is known to reach its target or the beginning of the current
6128 /* Use the containing sequence insn's address. */
6129 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6131 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6132 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6134 /* If the branch was too far away, emit a normal call followed
6135 by a nop, followed by the unconditional branch.
6137 If the branch is close, then adjust %r2 from within the
6138 call's delay slot. */
6140 xoperands[0] = call_dest;
6141 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6142 if (! VAL_14_BITS_P (distance))
6143 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
6146 xoperands[2] = gen_label_rtx ();
6147 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
6149 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6150 CODE_LABEL_NUMBER (xoperands[2]));
6153 /* Delete the jump. */
6154 PUT_CODE (NEXT_INSN (insn), NOTE);
6155 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6156 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6160 extern struct obstack permanent_obstack;
6162 /* INSN is either a function call. It may have an unconditional jump
6165 CALL_DEST is the routine we are calling. */
6168 output_call (insn, call_dest, sibcall)
6173 int attr_length = get_attr_length (insn);
6174 int seq_length = dbr_sequence_length ();
6179 /* Handle common case -- empty delay slot or no jump in the delay slot,
6180 and we're sure that the branch will reach the beginning of the $CODE$
6182 if ((seq_length == 0 && attr_length == 12)
6184 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6185 && attr_length == 8))
6187 xoperands[0] = call_dest;
6188 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
6189 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
6193 /* This call may not reach the beginning of the $CODE$ subspace. */
6194 if (attr_length > 12)
6196 int delay_insn_deleted = 0;
6200 /* We need to emit an inline long-call branch. Furthermore,
6201 because we're changing a named function call into an indirect
6202 function call well after the parameters have been set up, we
6203 need to make sure any FP args appear in both the integer
6204 and FP registers. Also, we need move any delay slot insn
6205 out of the delay slot. And finally, we can't rely on the linker
6206 being able to fix the call to $$dyncall! -- Yuk!. */
6208 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6210 /* A non-jump insn in the delay slot. By definition we can
6211 emit this insn before the call (and in fact before argument
6213 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6215 /* Now delete the delay insn. */
6216 PUT_CODE (NEXT_INSN (insn), NOTE);
6217 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6218 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6219 delay_insn_deleted = 1;
6222 /* Now copy any FP arguments into integer registers. */
6223 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6225 int arg_mode, regno;
6226 rtx use = XEXP (link, 0);
6227 if (! (GET_CODE (use) == USE
6228 && GET_CODE (XEXP (use, 0)) == REG
6229 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6232 arg_mode = GET_MODE (XEXP (use, 0));
6233 regno = REGNO (XEXP (use, 0));
6234 /* Is it a floating point register? */
6235 if (regno >= 32 && regno <= 39)
6237 /* Copy from the FP register into an integer register
6239 if (arg_mode == SFmode)
6241 xoperands[0] = XEXP (use, 0);
6242 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6243 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
6245 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6249 xoperands[0] = XEXP (use, 0);
6250 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6251 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
6253 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6254 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6259 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
6260 we don't have any direct calls in that case. */
6263 const char *name = XSTR (call_dest, 0);
6265 /* See if we have already put this function on the list
6266 of deferred plabels. This list is generally small,
6267 so a liner search is not too ugly. If it proves too
6268 slow replace it with something faster. */
6269 for (i = 0; i < n_deferred_plabels; i++)
6270 if (strcmp (name, deferred_plabels[i].name) == 0)
6273 /* If the deferred plabel list is empty, or this entry was
6274 not found on the list, create a new entry on the list. */
6275 if (deferred_plabels == NULL || i == n_deferred_plabels)
6277 const char *real_name;
6279 if (deferred_plabels == 0)
6280 deferred_plabels = (struct deferred_plabel *)
6281 ggc_alloc (sizeof (struct deferred_plabel));
6283 deferred_plabels = (struct deferred_plabel *)
6284 ggc_realloc (deferred_plabels,
6285 ((n_deferred_plabels + 1)
6286 * sizeof (struct deferred_plabel)));
6288 i = n_deferred_plabels++;
6289 deferred_plabels[i].internal_label = gen_label_rtx ();
6290 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
6292 strcpy (deferred_plabels[i].name, name);
6294 /* Gross. We have just implicitly taken the address of this
6295 function, mark it as such. */
6296 real_name = (*targetm.strip_name_encoding) (name);
6297 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
6300 /* We have to load the address of the function using a procedure
6301 label (plabel). Inline plabels can lose for PIC and other
6302 cases, so avoid them by creating a 32bit plabel in the data
6306 xoperands[0] = deferred_plabels[i].internal_label;
6307 if (TARGET_SOM || ! TARGET_GAS)
6308 xoperands[1] = gen_label_rtx ();
6310 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
6311 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
6312 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
6314 /* Get our address + 8 into %r1. */
6315 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6317 if (TARGET_SOM || ! TARGET_GAS)
6319 /* Add %r1 to the offset of dyncall from the next insn. */
6320 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
6321 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6322 CODE_LABEL_NUMBER (xoperands[1]));
6323 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
6327 output_asm_insn ("addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1",
6329 output_asm_insn ("ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
6333 /* Get the return address into %r31. */
6334 output_asm_insn ("blr %%r0,%%r31", xoperands);
6336 /* Branch to our target which is in %r1. */
6337 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6341 /* This call never returns, so we do not need to fix the
6343 output_asm_insn ("nop", xoperands);
6347 /* Copy the return address into %r2 also. */
6348 output_asm_insn ("copy %%r31,%%r2", xoperands);
6353 xoperands[0] = deferred_plabels[i].internal_label;
6355 /* Get the address of our target into %r22. */
6356 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
6357 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
6359 /* Get the high part of the address of $dyncall into %r2, then
6360 add in the low part in the branch instruction. */
6361 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
6363 output_asm_insn ("be,l R%%$$dyncall(%%sr4,%%r2),%%sr0,%%r31",
6366 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands);
6370 /* This call never returns, so we do not need to fix the
6372 output_asm_insn ("nop", xoperands);
6376 /* Copy the return address into %r2 also. */
6377 output_asm_insn ("copy %%r31,%%r2", xoperands);
6382 /* If we had a jump in the call's delay slot, output it now. */
6383 if (seq_length != 0 && !delay_insn_deleted)
6385 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6386 output_asm_insn ("b,n %0", xoperands);
6388 /* Now delete the delay insn. */
6389 PUT_CODE (NEXT_INSN (insn), NOTE);
6390 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6391 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6396 /* This call has an unconditional jump in its delay slot and the
6397 call is known to reach its target or the beginning of the current
6400 /* Use the containing sequence insn's address. */
6401 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6403 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6404 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6406 /* If the branch is too far away, emit a normal call followed
6407 by a nop, followed by the unconditional branch. If the branch
6408 is close, then adjust %r2 in the call's delay slot. */
6410 xoperands[0] = call_dest;
6411 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6412 if (! VAL_14_BITS_P (distance))
6413 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
6416 xoperands[3] = gen_label_rtx ();
6417 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6419 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6420 CODE_LABEL_NUMBER (xoperands[3]));
6423 /* Delete the jump. */
6424 PUT_CODE (NEXT_INSN (insn), NOTE);
6425 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6426 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6430 /* In HPUX 8.0's shared library scheme, special relocations are needed
6431 for function labels if they might be passed to a function
6432 in a shared library (because shared libraries don't live in code
6433 space), and special magic is needed to construct their address. */
6436 hppa_encode_label (sym)
6439 const char *str = XSTR (sym, 0);
6440 int len = strlen (str) + 1;
6443 p = newstr = alloca (len + 1);
6452 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6456 pa_encode_section_info (decl, first)
6460 if (first && TEXT_SPACE_P (decl))
6463 if (TREE_CODE (decl) == FUNCTION_DECL
6464 || TREE_CODE (decl) == VAR_DECL)
6465 rtl = DECL_RTL (decl);
6467 rtl = TREE_CST_RTL (decl);
6468 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
6469 if (TREE_CODE (decl) == FUNCTION_DECL)
6470 hppa_encode_label (XEXP (DECL_RTL (decl), 0));
6474 /* This is sort of inverse to pa_encode_section_info. */
6477 pa_strip_name_encoding (str)
6480 return str + (*str == '*' || *str == '@');
6484 function_label_operand (op, mode)
6486 enum machine_mode mode ATTRIBUTE_UNUSED;
6488 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6491 /* Returns 1 if OP is a function label involved in a simple addition
6492 with a constant. Used to keep certain patterns from matching
6493 during instruction combination. */
6495 is_function_label_plus_const (op)
6498 /* Strip off any CONST. */
6499 if (GET_CODE (op) == CONST)
6502 return (GET_CODE (op) == PLUS
6503 && function_label_operand (XEXP (op, 0), Pmode)
6504 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6507 /* Output assembly code for a thunk to FUNCTION. */
6510 pa_asm_output_mi_thunk (file, thunk_fndecl, delta, function)
6513 HOST_WIDE_INT delta;
6516 const char *target_name = XSTR (XEXP (DECL_RTL (function), 0), 0);
6517 static unsigned int current_thunk_number;
6520 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
6521 lab = (*targetm.strip_name_encoding) (label);
6522 target_name = (*targetm.strip_name_encoding) (target_name);
6523 /* FIXME: total_code_bytes is not handled correctly in files with
6525 pa_output_function_prologue (file, 0);
6526 if (VAL_14_BITS_P (delta))
6528 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6530 fprintf (file, "\taddil LT%%%s,%%r19\n", lab);
6531 fprintf (file, "\tldw RT%%%s(%%r1),%%r22\n", lab);
6532 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6533 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6534 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6535 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6536 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6537 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6538 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
6539 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6540 fprintf (file, "(%%r26),%%r26\n");
6544 fprintf (file, "\tb %s\n\tldo ", target_name);
6545 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6546 fprintf (file, "(%%r26),%%r26\n");
6551 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6553 fprintf (file, "\taddil L%%");
6554 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6555 fprintf (file, ",%%r26\n\tldo R%%");
6556 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6557 fprintf (file, "(%%r1),%%r26\n");
6558 fprintf (file, "\taddil LT%%%s,%%r19\n", lab);
6559 fprintf (file, "\tldw RT%%%s(%%r1),%%r22\n", lab);
6560 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6561 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6562 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6563 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6564 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6565 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6566 fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n");
6570 fprintf (file, "\taddil L%%");
6571 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6572 fprintf (file, ",%%r26\n\tb %s\n\tldo R%%", target_name);
6573 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6574 fprintf (file, "(%%r1),%%r26\n");
6578 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
6579 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6582 fprintf (file, "\t.align 4\n");
6583 ASM_OUTPUT_INTERNAL_LABEL (file, "LTHN", current_thunk_number);
6584 fprintf (file, "\t.word P%%%s\n", target_name);
6585 function_section (thunk_fndecl);
6587 current_thunk_number++;
6590 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6591 use in fmpyadd instructions. */
6593 fmpyaddoperands (operands)
6596 enum machine_mode mode = GET_MODE (operands[0]);
6598 /* Must be a floating point mode. */
6599 if (mode != SFmode && mode != DFmode)
6602 /* All modes must be the same. */
6603 if (! (mode == GET_MODE (operands[1])
6604 && mode == GET_MODE (operands[2])
6605 && mode == GET_MODE (operands[3])
6606 && mode == GET_MODE (operands[4])
6607 && mode == GET_MODE (operands[5])))
6610 /* All operands must be registers. */
6611 if (! (GET_CODE (operands[1]) == REG
6612 && GET_CODE (operands[2]) == REG
6613 && GET_CODE (operands[3]) == REG
6614 && GET_CODE (operands[4]) == REG
6615 && GET_CODE (operands[5]) == REG))
6618 /* Only 2 real operands to the addition. One of the input operands must
6619 be the same as the output operand. */
6620 if (! rtx_equal_p (operands[3], operands[4])
6621 && ! rtx_equal_p (operands[3], operands[5]))
6624 /* Inout operand of add can not conflict with any operands from multiply. */
6625 if (rtx_equal_p (operands[3], operands[0])
6626 || rtx_equal_p (operands[3], operands[1])
6627 || rtx_equal_p (operands[3], operands[2]))
6630 /* multiply can not feed into addition operands. */
6631 if (rtx_equal_p (operands[4], operands[0])
6632 || rtx_equal_p (operands[5], operands[0]))
6635 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6637 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6638 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6639 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6640 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6641 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6642 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6645 /* Passed. Operands are suitable for fmpyadd. */
6649 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6650 use in fmpysub instructions. */
6652 fmpysuboperands (operands)
6655 enum machine_mode mode = GET_MODE (operands[0]);
6657 /* Must be a floating point mode. */
6658 if (mode != SFmode && mode != DFmode)
6661 /* All modes must be the same. */
6662 if (! (mode == GET_MODE (operands[1])
6663 && mode == GET_MODE (operands[2])
6664 && mode == GET_MODE (operands[3])
6665 && mode == GET_MODE (operands[4])
6666 && mode == GET_MODE (operands[5])))
6669 /* All operands must be registers. */
6670 if (! (GET_CODE (operands[1]) == REG
6671 && GET_CODE (operands[2]) == REG
6672 && GET_CODE (operands[3]) == REG
6673 && GET_CODE (operands[4]) == REG
6674 && GET_CODE (operands[5]) == REG))
6677 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6678 operation, so operands[4] must be the same as operand[3]. */
6679 if (! rtx_equal_p (operands[3], operands[4]))
6682 /* multiply can not feed into subtraction. */
6683 if (rtx_equal_p (operands[5], operands[0]))
6686 /* Inout operand of sub can not conflict with any operands from multiply. */
6687 if (rtx_equal_p (operands[3], operands[0])
6688 || rtx_equal_p (operands[3], operands[1])
6689 || rtx_equal_p (operands[3], operands[2]))
6692 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6694 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6695 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6696 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6697 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6698 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6699 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6702 /* Passed. Operands are suitable for fmpysub. */
6707 plus_xor_ior_operator (op, mode)
6709 enum machine_mode mode ATTRIBUTE_UNUSED;
6711 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6712 || GET_CODE (op) == IOR);
6715 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6716 constants for shadd instructions. */
6718 shadd_constant_p (val)
6721 if (val == 2 || val == 4 || val == 8)
6727 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6728 the valid constant for shadd instructions. */
6730 shadd_operand (op, mode)
6732 enum machine_mode mode ATTRIBUTE_UNUSED;
6734 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6737 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6740 basereg_operand (op, mode)
6742 enum machine_mode mode;
6744 /* cse will create some unscaled indexed addresses, however; it
6745 generally isn't a win on the PA, so avoid creating unscaled
6746 indexed addresses until after cse is finished. */
6747 if (!cse_not_expected)
6750 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6751 we don't have to worry about the braindamaged implicit space
6752 register selection from the basereg. */
6753 if (TARGET_NO_SPACE_REGS)
6754 return (GET_CODE (op) == REG);
6756 /* While it's always safe to index off the frame pointer, it's not
6757 always profitable, particularly when the frame pointer is being
6759 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6762 return (GET_CODE (op) == REG
6764 && register_operand (op, mode));
6767 /* Return 1 if this operand is anything other than a hard register. */
6770 non_hard_reg_operand (op, mode)
6772 enum machine_mode mode ATTRIBUTE_UNUSED;
6774 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6777 /* Return 1 if INSN branches forward. Should be using insn_addresses
6778 to avoid walking through all the insns... */
6780 forward_branch_p (insn)
6783 rtx label = JUMP_LABEL (insn);
6790 insn = NEXT_INSN (insn);
6793 return (insn == label);
6796 /* Return 1 if OP is an equality comparison, else return 0. */
6798 eq_neq_comparison_operator (op, mode)
6800 enum machine_mode mode ATTRIBUTE_UNUSED;
6802 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6805 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6807 movb_comparison_operator (op, mode)
6809 enum machine_mode mode ATTRIBUTE_UNUSED;
6811 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6812 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6815 /* Return 1 if INSN is in the delay slot of a call instruction. */
6817 jump_in_call_delay (insn)
6821 if (GET_CODE (insn) != JUMP_INSN)
6824 if (PREV_INSN (insn)
6825 && PREV_INSN (PREV_INSN (insn))
6826 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6828 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6830 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6831 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6838 /* Output an unconditional move and branch insn. */
6841 output_parallel_movb (operands, length)
6845 /* These are the cases in which we win. */
6847 return "mov%I1b,tr %1,%0,%2";
6849 /* None of these cases wins, but they don't lose either. */
6850 if (dbr_sequence_length () == 0)
6852 /* Nothing in the delay slot, fake it by putting the combined
6853 insn (the copy or add) in the delay slot of a bl. */
6854 if (GET_CODE (operands[1]) == CONST_INT)
6855 return "b %2\n\tldi %1,%0";
6857 return "b %2\n\tcopy %1,%0";
6861 /* Something in the delay slot, but we've got a long branch. */
6862 if (GET_CODE (operands[1]) == CONST_INT)
6863 return "ldi %1,%0\n\tb %2";
6865 return "copy %1,%0\n\tb %2";
6869 /* Output an unconditional add and branch insn. */
6872 output_parallel_addb (operands, length)
6876 /* To make life easy we want operand0 to be the shared input/output
6877 operand and operand1 to be the readonly operand. */
6878 if (operands[0] == operands[1])
6879 operands[1] = operands[2];
6881 /* These are the cases in which we win. */
6883 return "add%I1b,tr %1,%0,%3";
6885 /* None of these cases win, but they don't lose either. */
6886 if (dbr_sequence_length () == 0)
6888 /* Nothing in the delay slot, fake it by putting the combined
6889 insn (the copy or add) in the delay slot of a bl. */
6890 return "b %3\n\tadd%I1 %1,%0,%0";
6894 /* Something in the delay slot, but we've got a long branch. */
6895 return "add%I1 %1,%0,%0\n\tb %3";
6899 /* Return nonzero if INSN (a jump insn) immediately follows a call
6900 to a named function. This is used to avoid filling the delay slot
6901 of the jump since it can usually be eliminated by modifying RP in
6902 the delay slot of the call. */
6905 following_call (insn)
6908 if (! TARGET_JUMP_IN_DELAY)
6911 /* Find the previous real insn, skipping NOTEs. */
6912 insn = PREV_INSN (insn);
6913 while (insn && GET_CODE (insn) == NOTE)
6914 insn = PREV_INSN (insn);
6916 /* Check for CALL_INSNs and millicode calls. */
6918 && ((GET_CODE (insn) == CALL_INSN
6919 && get_attr_type (insn) != TYPE_DYNCALL)
6920 || (GET_CODE (insn) == INSN
6921 && GET_CODE (PATTERN (insn)) != SEQUENCE
6922 && GET_CODE (PATTERN (insn)) != USE
6923 && GET_CODE (PATTERN (insn)) != CLOBBER
6924 && get_attr_type (insn) == TYPE_MILLI)))
6930 /* We use this hook to perform a PA specific optimization which is difficult
6931 to do in earlier passes.
6933 We want the delay slots of branches within jump tables to be filled.
6934 None of the compiler passes at the moment even has the notion that a
6935 PA jump table doesn't contain addresses, but instead contains actual
6938 Because we actually jump into the table, the addresses of each entry
6939 must stay constant in relation to the beginning of the table (which
6940 itself must stay constant relative to the instruction to jump into
6941 it). I don't believe we can guarantee earlier passes of the compiler
6942 will adhere to those rules.
6944 So, late in the compilation process we find all the jump tables, and
6945 expand them into real code -- eg each entry in the jump table vector
6946 will get an appropriate label followed by a jump to the final target.
6948 Reorg and the final jump pass can then optimize these branches and
6949 fill their delay slots. We end up with smaller, more efficient code.
6951 The jump instructions within the table are special; we must be able
6952 to identify them during assembly output (if the jumps don't get filled
6953 we need to emit a nop rather than nullifying the delay slot)). We
6954 identify jumps in switch tables by marking the SET with DImode.
6956 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6957 insns. This serves two purposes, first it prevents jump.c from
6958 noticing that the last N entries in the table jump to the instruction
6959 immediately after the table and deleting the jumps. Second, those
6960 insns mark where we should emit .begin_brtab and .end_brtab directives
6961 when using GAS (allows for better link time optimizations). */
6969 remove_useless_addtr_insns (insns, 1);
6971 if (pa_cpu < PROCESSOR_8000)
6972 pa_combine_instructions (get_insns ());
6975 /* This is fairly cheap, so always run it if optimizing. */
6976 if (optimize > 0 && !TARGET_BIG_SWITCH)
6978 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6979 insns = get_insns ();
6980 for (insn = insns; insn; insn = NEXT_INSN (insn))
6982 rtx pattern, tmp, location;
6983 unsigned int length, i;
6985 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6986 if (GET_CODE (insn) != JUMP_INSN
6987 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6988 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6991 /* Emit marker for the beginning of the branch table. */
6992 emit_insn_before (gen_begin_brtab (), insn);
6994 pattern = PATTERN (insn);
6995 location = PREV_INSN (insn);
6996 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6998 for (i = 0; i < length; i++)
7000 /* Emit a label before each jump to keep jump.c from
7001 removing this code. */
7002 tmp = gen_label_rtx ();
7003 LABEL_NUSES (tmp) = 1;
7004 emit_label_after (tmp, location);
7005 location = NEXT_INSN (location);
7007 if (GET_CODE (pattern) == ADDR_VEC)
7009 /* Emit the jump itself. */
7010 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
7011 tmp = emit_jump_insn_after (tmp, location);
7012 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
7013 /* It is easy to rely on the branch table markers
7014 during assembly output to trigger the correct code
7015 for a switch table jump with an unfilled delay slot,
7017 However, that requires state and assumes that we look
7020 We can't make such assumptions when computing the length
7021 of instructions. Ugh. We could walk the insn chain to
7022 determine if this instruction is in a branch table, but
7023 that can get rather expensive, particularly during the
7024 branch shortening phase of the compiler.
7026 So instead we mark this jump as being special. This is
7027 far from ideal and knows that no code after this will
7028 muck around with the mode of the JUMP_INSN itself. */
7029 PUT_MODE (tmp, SImode);
7030 LABEL_NUSES (JUMP_LABEL (tmp))++;
7031 location = NEXT_INSN (location);
7035 /* Emit the jump itself. */
7036 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
7037 tmp = emit_jump_insn_after (tmp, location);
7038 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
7039 /* It is easy to rely on the branch table markers
7040 during assembly output to trigger the correct code
7041 for a switch table jump with an unfilled delay slot,
7043 However, that requires state and assumes that we look
7046 We can't make such assumptions when computing the length
7047 of instructions. Ugh. We could walk the insn chain to
7048 determine if this instruction is in a branch table, but
7049 that can get rather expensive, particularly during the
7050 branch shortening phase of the compiler.
7052 So instead we mark this jump as being special. This is
7053 far from ideal and knows that no code after this will
7054 muck around with the mode of the JUMP_INSN itself. */
7055 PUT_MODE (tmp, SImode);
7056 LABEL_NUSES (JUMP_LABEL (tmp))++;
7057 location = NEXT_INSN (location);
7060 /* Emit a BARRIER after the jump. */
7061 emit_barrier_after (location);
7062 location = NEXT_INSN (location);
7065 /* Emit marker for the end of the branch table. */
7066 emit_insn_before (gen_end_brtab (), location);
7067 location = NEXT_INSN (location);
7068 emit_barrier_after (location);
7070 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
7076 /* Sill need an end_brtab insn. */
7077 insns = get_insns ();
7078 for (insn = insns; insn; insn = NEXT_INSN (insn))
7080 /* Find an ADDR_VEC insn. */
7081 if (GET_CODE (insn) != JUMP_INSN
7082 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7083 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7086 /* Now generate markers for the beginning and end of the
7088 emit_insn_before (gen_begin_brtab (), insn);
7089 emit_insn_after (gen_end_brtab (), insn);
7094 /* The PA has a number of odd instructions which can perform multiple
7095 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
7096 it may be profitable to combine two instructions into one instruction
7097 with two outputs. It's not profitable PA2.0 machines because the
7098 two outputs would take two slots in the reorder buffers.
7100 This routine finds instructions which can be combined and combines
7101 them. We only support some of the potential combinations, and we
7102 only try common ways to find suitable instructions.
7104 * addb can add two registers or a register and a small integer
7105 and jump to a nearby (+-8k) location. Normally the jump to the
7106 nearby location is conditional on the result of the add, but by
7107 using the "true" condition we can make the jump unconditional.
7108 Thus addb can perform two independent operations in one insn.
7110 * movb is similar to addb in that it can perform a reg->reg
7111 or small immediate->reg copy and jump to a nearby (+-8k location).
7113 * fmpyadd and fmpysub can perform a FP multiply and either an
7114 FP add or FP sub if the operands of the multiply and add/sub are
7115 independent (there are other minor restrictions). Note both
7116 the fmpy and fadd/fsub can in theory move to better spots according
7117 to data dependencies, but for now we require the fmpy stay at a
7120 * Many of the memory operations can perform pre & post updates
7121 of index registers. GCC's pre/post increment/decrement addressing
7122 is far too simple to take advantage of all the possibilities. This
7123 pass may not be suitable since those insns may not be independent.
7125 * comclr can compare two ints or an int and a register, nullify
7126 the following instruction and zero some other register. This
7127 is more difficult to use as it's harder to find an insn which
7128 will generate a comclr than finding something like an unconditional
7129 branch. (conditional moves & long branches create comclr insns).
7131 * Most arithmetic operations can conditionally skip the next
7132 instruction. They can be viewed as "perform this operation
7133 and conditionally jump to this nearby location" (where nearby
7134 is an insns away). These are difficult to use due to the
7135 branch length restrictions. */
7138 pa_combine_instructions (insns)
7139 rtx insns ATTRIBUTE_UNUSED;
7143 /* This can get expensive since the basic algorithm is on the
7144 order of O(n^2) (or worse). Only do it for -O2 or higher
7145 levels of optimization. */
7149 /* Walk down the list of insns looking for "anchor" insns which
7150 may be combined with "floating" insns. As the name implies,
7151 "anchor" instructions don't move, while "floating" insns may
7153 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
7154 new = make_insn_raw (new);
7156 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
7158 enum attr_pa_combine_type anchor_attr;
7159 enum attr_pa_combine_type floater_attr;
7161 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
7162 Also ignore any special USE insns. */
7163 if ((GET_CODE (anchor) != INSN
7164 && GET_CODE (anchor) != JUMP_INSN
7165 && GET_CODE (anchor) != CALL_INSN)
7166 || GET_CODE (PATTERN (anchor)) == USE
7167 || GET_CODE (PATTERN (anchor)) == CLOBBER
7168 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
7169 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
7172 anchor_attr = get_attr_pa_combine_type (anchor);
7173 /* See if anchor is an insn suitable for combination. */
7174 if (anchor_attr == PA_COMBINE_TYPE_FMPY
7175 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
7176 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7177 && ! forward_branch_p (anchor)))
7181 for (floater = PREV_INSN (anchor);
7183 floater = PREV_INSN (floater))
7185 if (GET_CODE (floater) == NOTE
7186 || (GET_CODE (floater) == INSN
7187 && (GET_CODE (PATTERN (floater)) == USE
7188 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7191 /* Anything except a regular INSN will stop our search. */
7192 if (GET_CODE (floater) != INSN
7193 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7194 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7200 /* See if FLOATER is suitable for combination with the
7202 floater_attr = get_attr_pa_combine_type (floater);
7203 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7204 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7205 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7206 && floater_attr == PA_COMBINE_TYPE_FMPY))
7208 /* If ANCHOR and FLOATER can be combined, then we're
7209 done with this pass. */
7210 if (pa_can_combine_p (new, anchor, floater, 0,
7211 SET_DEST (PATTERN (floater)),
7212 XEXP (SET_SRC (PATTERN (floater)), 0),
7213 XEXP (SET_SRC (PATTERN (floater)), 1)))
7217 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7218 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
7220 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
7222 if (pa_can_combine_p (new, anchor, floater, 0,
7223 SET_DEST (PATTERN (floater)),
7224 XEXP (SET_SRC (PATTERN (floater)), 0),
7225 XEXP (SET_SRC (PATTERN (floater)), 1)))
7230 if (pa_can_combine_p (new, anchor, floater, 0,
7231 SET_DEST (PATTERN (floater)),
7232 SET_SRC (PATTERN (floater)),
7233 SET_SRC (PATTERN (floater))))
7239 /* If we didn't find anything on the backwards scan try forwards. */
7241 && (anchor_attr == PA_COMBINE_TYPE_FMPY
7242 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
7244 for (floater = anchor; floater; floater = NEXT_INSN (floater))
7246 if (GET_CODE (floater) == NOTE
7247 || (GET_CODE (floater) == INSN
7248 && (GET_CODE (PATTERN (floater)) == USE
7249 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7253 /* Anything except a regular INSN will stop our search. */
7254 if (GET_CODE (floater) != INSN
7255 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7256 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7262 /* See if FLOATER is suitable for combination with the
7264 floater_attr = get_attr_pa_combine_type (floater);
7265 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7266 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7267 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7268 && floater_attr == PA_COMBINE_TYPE_FMPY))
7270 /* If ANCHOR and FLOATER can be combined, then we're
7271 done with this pass. */
7272 if (pa_can_combine_p (new, anchor, floater, 1,
7273 SET_DEST (PATTERN (floater)),
7274 XEXP (SET_SRC (PATTERN (floater)),
7276 XEXP (SET_SRC (PATTERN (floater)),
7283 /* FLOATER will be nonzero if we found a suitable floating
7284 insn for combination with ANCHOR. */
7286 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7287 || anchor_attr == PA_COMBINE_TYPE_FMPY))
7289 /* Emit the new instruction and delete the old anchor. */
7290 emit_insn_before (gen_rtx_PARALLEL
7292 gen_rtvec (2, PATTERN (anchor),
7293 PATTERN (floater))),
7296 PUT_CODE (anchor, NOTE);
7297 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7298 NOTE_SOURCE_FILE (anchor) = 0;
7300 /* Emit a special USE insn for FLOATER, then delete
7301 the floating insn. */
7302 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7303 delete_insn (floater);
7308 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
7311 /* Emit the new_jump instruction and delete the old anchor. */
7313 = emit_jump_insn_before (gen_rtx_PARALLEL
7315 gen_rtvec (2, PATTERN (anchor),
7316 PATTERN (floater))),
7319 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
7320 PUT_CODE (anchor, NOTE);
7321 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7322 NOTE_SOURCE_FILE (anchor) = 0;
7324 /* Emit a special USE insn for FLOATER, then delete
7325 the floating insn. */
7326 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7327 delete_insn (floater);
7335 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
7336 rtx new, anchor, floater;
7338 rtx dest, src1, src2;
7340 int insn_code_number;
7343 /* Create a PARALLEL with the patterns of ANCHOR and
7344 FLOATER, try to recognize it, then test constraints
7345 for the resulting pattern.
7347 If the pattern doesn't match or the constraints
7348 aren't met keep searching for a suitable floater
7350 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
7351 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
7352 INSN_CODE (new) = -1;
7353 insn_code_number = recog_memoized (new);
7354 if (insn_code_number < 0
7355 || (extract_insn (new), ! constrain_operands (1)))
7369 /* There's up to three operands to consider. One
7370 output and two inputs.
7372 The output must not be used between FLOATER & ANCHOR
7373 exclusive. The inputs must not be set between
7374 FLOATER and ANCHOR exclusive. */
7376 if (reg_used_between_p (dest, start, end))
7379 if (reg_set_between_p (src1, start, end))
7382 if (reg_set_between_p (src2, start, end))
7385 /* If we get here, then everything is good. */
7389 /* Return nonzero if references for INSN are delayed.
7391 Millicode insns are actually function calls with some special
7392 constraints on arguments and register usage.
7394 Millicode calls always expect their arguments in the integer argument
7395 registers, and always return their result in %r29 (ret1). They
7396 are expected to clobber their arguments, %r1, %r29, and the return
7397 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
7399 This function tells reorg that the references to arguments and
7400 millicode calls do not appear to happen until after the millicode call.
7401 This allows reorg to put insns which set the argument registers into the
7402 delay slot of the millicode call -- thus they act more like traditional
7405 Note we can not consider side effects of the insn to be delayed because
7406 the branch and link insn will clobber the return pointer. If we happened
7407 to use the return pointer in the delay slot of the call, then we lose.
7409 get_attr_type will try to recognize the given insn, so make sure to
7410 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
7413 insn_refs_are_delayed (insn)
7416 return ((GET_CODE (insn) == INSN
7417 && GET_CODE (PATTERN (insn)) != SEQUENCE
7418 && GET_CODE (PATTERN (insn)) != USE
7419 && GET_CODE (PATTERN (insn)) != CLOBBER
7420 && get_attr_type (insn) == TYPE_MILLI));
7423 /* Return the location of a parameter that is passed in a register or NULL
7424 if the parameter has any component that is passed in memory.
7426 This is new code and will be pushed to into the net sources after
7429 ??? We might want to restructure this so that it looks more like other
7432 function_arg (cum, mode, type, named, incoming)
7433 CUMULATIVE_ARGS *cum;
7434 enum machine_mode mode;
7436 int named ATTRIBUTE_UNUSED;
7439 int max_arg_words = (TARGET_64BIT ? 8 : 4);
7446 /* If this arg would be passed partially or totally on the stack, then
7447 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
7448 handle arguments which are split between regs and stack slots if
7449 the ABI mandates split arguments. */
7450 if (cum->words + FUNCTION_ARG_SIZE (mode, type) > max_arg_words
7451 || mode == VOIDmode)
7457 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7459 if (cum->words + offset >= max_arg_words
7460 || mode == VOIDmode)
7464 /* The 32bit ABIs and the 64bit ABIs are rather different,
7465 particularly in their handling of FP registers. We might
7466 be able to cleverly share code between them, but I'm not
7467 going to bother in the hope that splitting them up results
7468 in code that is more easily understood.
7470 The 64bit code probably is very wrong for structure passing. */
7473 /* Advance the base registers to their current locations.
7475 Remember, gprs grow towards smaller register numbers while
7476 fprs grow to higher register numbers. Also remember FP regs
7477 are always 4 bytes wide, while the size of an integer register
7478 varies based on the size of the target word. */
7479 gpr_reg_base = 26 - cum->words;
7480 fpr_reg_base = 32 + cum->words;
7482 /* If the argument is more than a word long, then we need to align
7483 the base registers. Same caveats as above. */
7484 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7486 if (mode != BLKmode)
7488 /* First deal with alignment of the doubleword. */
7489 gpr_reg_base -= (cum->words & 1);
7491 /* This seems backwards, but it is what HP specifies. We need
7492 gpr_reg_base to point to the smaller numbered register of
7493 the integer register pair. So if we have an even register
7494 number, then decrement the gpr base. */
7495 gpr_reg_base -= ((gpr_reg_base % 2) == 0);
7497 /* FP values behave sanely, except that each FP reg is only
7499 fpr_reg_base += ((fpr_reg_base % 2) == 0);
7504 int i, offset = 0, ub;
7505 ub = FUNCTION_ARG_SIZE (mode, type);
7507 MAX (0, max_arg_words - cum->words - (cum->words & 1)));
7508 gpr_reg_base -= (cum->words & 1);
7509 for (i = 0; i < ub; i++)
7511 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7512 gen_rtx_REG (DImode,
7521 return XEXP (loc[0], 0);
7523 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7529 /* If the argument is larger than a word, then we know precisely
7530 which registers we must use. */
7531 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7546 /* We have a single word (32 bits). A simple computation
7547 will get us the register #s we need. */
7548 gpr_reg_base = 26 - cum->words;
7549 fpr_reg_base = 32 + 2 * cum->words;
7553 if (TARGET_64BIT && mode == TFmode)
7559 gen_rtx_EXPR_LIST (VOIDmode,
7560 gen_rtx_REG (DImode, gpr_reg_base + 1),
7562 gen_rtx_EXPR_LIST (VOIDmode,
7563 gen_rtx_REG (DImode, gpr_reg_base),
7566 /* Determine if the argument needs to be passed in both general and
7567 floating point registers. */
7568 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7569 /* If we are doing soft-float with portable runtime, then there
7570 is no need to worry about FP regs. */
7571 && ! TARGET_SOFT_FLOAT
7572 /* The parameter must be some kind of float, else we can just
7573 pass it in integer registers. */
7574 && FLOAT_MODE_P (mode)
7575 /* The target function must not have a prototype. */
7576 && cum->nargs_prototype <= 0
7577 /* libcalls do not need to pass items in both FP and general
7579 && type != NULL_TREE
7580 /* All this hair applies to outgoing args only. */
7582 /* Also pass outgoing floating arguments in both registers in indirect
7583 calls with the 32 bit ABI and the HP assembler since there is no
7584 way to the specify argument locations in static functions. */
7589 && FLOAT_MODE_P (mode)))
7595 gen_rtx_EXPR_LIST (VOIDmode,
7596 gen_rtx_REG (mode, fpr_reg_base),
7598 gen_rtx_EXPR_LIST (VOIDmode,
7599 gen_rtx_REG (mode, gpr_reg_base),
7604 /* See if we should pass this parameter in a general register. */
7605 if (TARGET_SOFT_FLOAT
7606 /* Indirect calls in the normal 32bit ABI require all arguments
7607 to be passed in general registers. */
7608 || (!TARGET_PORTABLE_RUNTIME
7612 /* If the parameter is not a floating point parameter, then
7613 it belongs in GPRs. */
7614 || !FLOAT_MODE_P (mode))
7615 retval = gen_rtx_REG (mode, gpr_reg_base);
7617 retval = gen_rtx_REG (mode, fpr_reg_base);
7623 /* If this arg would be passed totally in registers or totally on the stack,
7624 then this routine should return zero. It is currently called only for
7625 the 64-bit target. */
7627 function_arg_partial_nregs (cum, mode, type, named)
7628 CUMULATIVE_ARGS *cum;
7629 enum machine_mode mode;
7631 int named ATTRIBUTE_UNUSED;
7633 unsigned int max_arg_words = 8;
7634 unsigned int offset = 0;
7636 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7639 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
7640 /* Arg fits fully into registers. */
7642 else if (cum->words + offset >= max_arg_words)
7643 /* Arg fully on the stack. */
7647 return max_arg_words - cum->words - offset;
7651 /* Return 1 if this is a comparison operator. This allows the use of
7652 MATCH_OPERATOR to recognize all the branch insns. */
7655 cmpib_comparison_operator (op, mode)
7657 enum machine_mode mode;
7659 return ((mode == VOIDmode || GET_MODE (op) == mode)
7660 && (GET_CODE (op) == EQ
7661 || GET_CODE (op) == NE
7662 || GET_CODE (op) == GT
7663 || GET_CODE (op) == GTU
7664 || GET_CODE (op) == GE
7665 || GET_CODE (op) == LT
7666 || GET_CODE (op) == LE
7667 || GET_CODE (op) == LEU));
7670 /* On hpux10, the linker will give an error if we have a reference
7671 in the read-only data section to a symbol defined in a shared
7672 library. Therefore, expressions that might require a reloc can
7673 not be placed in the read-only data section. */
7676 pa_select_section (exp, reloc, align)
7679 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
7681 if (TREE_CODE (exp) == VAR_DECL
7682 && TREE_READONLY (exp)
7683 && !TREE_THIS_VOLATILE (exp)
7684 && DECL_INITIAL (exp)
7685 && (DECL_INITIAL (exp) == error_mark_node
7686 || TREE_CONSTANT (DECL_INITIAL (exp)))
7688 readonly_data_section ();
7689 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
7690 && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings)
7692 readonly_data_section ();