1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 static int hppa_use_dfa_pipeline_interface (void);
53 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
54 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
57 hppa_use_dfa_pipeline_interface (void)
62 /* Return nonzero if there is a bypass for the output of
63 OUT_INSN and the fp store IN_INSN. */
65 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
67 enum machine_mode store_mode;
68 enum machine_mode other_mode;
71 if (recog_memoized (in_insn) < 0
72 || get_attr_type (in_insn) != TYPE_FPSTORE
73 || recog_memoized (out_insn) < 0)
76 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
78 set = single_set (out_insn);
82 other_mode = GET_MODE (SET_SRC (set));
84 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
88 #ifndef DO_FRAME_NOTES
89 #ifdef INCOMING_RETURN_ADDR_RTX
90 #define DO_FRAME_NOTES 1
92 #define DO_FRAME_NOTES 0
96 static void copy_reg_pointer (rtx, rtx);
97 static int hppa_address_cost (rtx);
98 static bool hppa_rtx_costs (rtx, int, int, int *);
99 static inline rtx force_mode (enum machine_mode, rtx);
100 static void pa_reorg (void);
101 static void pa_combine_instructions (void);
102 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
103 static int forward_branch_p (rtx);
104 static int shadd_constant_p (int);
105 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
106 static int compute_movstr_length (rtx);
107 static int compute_clrstr_length (rtx);
108 static bool pa_assemble_integer (rtx, unsigned int, int);
109 static void remove_useless_addtr_insns (int);
110 static void store_reg (int, HOST_WIDE_INT, int);
111 static void store_reg_modify (int, int, HOST_WIDE_INT);
112 static void load_reg (int, HOST_WIDE_INT, int);
113 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
114 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
115 static void update_total_code_bytes (int);
116 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
117 static int pa_adjust_cost (rtx, rtx, rtx, int);
118 static int pa_adjust_priority (rtx, int);
119 static int pa_issue_rate (void);
120 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
122 static void pa_encode_section_info (tree, rtx, int);
123 static const char *pa_strip_name_encoding (const char *);
124 static bool pa_function_ok_for_sibcall (tree, tree);
125 static void pa_globalize_label (FILE *, const char *)
127 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
128 HOST_WIDE_INT, tree);
129 #if !defined(USE_COLLECT2)
130 static void pa_asm_out_constructor (rtx, int);
131 static void pa_asm_out_destructor (rtx, int);
133 static void pa_init_builtins (void);
134 static rtx hppa_builtin_saveregs (void);
135 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
136 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
137 static struct deferred_plabel *get_plabel (const char *)
139 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
140 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
141 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
142 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
143 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
144 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
145 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
146 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
147 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
148 static void output_deferred_plabels (void);
149 #ifdef HPUX_LONG_DOUBLE_LIBRARY
150 static void pa_hpux_init_libfuncs (void);
152 static rtx pa_struct_value_rtx (tree, int);
154 /* Save the operands last given to a compare for use when we
155 generate a scc or bcc insn. */
156 rtx hppa_compare_op0, hppa_compare_op1;
157 enum cmp_type hppa_branch_type;
159 /* Which cpu we are scheduling for. */
160 enum processor_type pa_cpu;
162 /* String to hold which cpu we are scheduling for. */
163 const char *pa_cpu_string;
165 /* Which architecture we are generating code for. */
166 enum architecture_type pa_arch;
168 /* String to hold which architecture we are generating code for. */
169 const char *pa_arch_string;
171 /* Counts for the number of callee-saved general and floating point
172 registers which were saved by the current function's prologue. */
173 static int gr_saved, fr_saved;
175 static rtx find_addr_reg (rtx);
177 /* Keep track of the number of bytes we have output in the CODE subspace
178 during this compilation so we'll know when to emit inline long-calls. */
179 unsigned long total_code_bytes;
181 /* The last address of the previous function plus the number of bytes in
182 associated thunks that have been output. This is used to determine if
183 a thunk can use an IA-relative branch to reach its target function. */
184 static int last_address;
186 /* Variables to handle plabels that we discover are necessary at assembly
187 output time. They are output after the current function. */
188 struct deferred_plabel GTY(())
193 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
195 static size_t n_deferred_plabels = 0;
198 /* Initialize the GCC target structure. */
200 #undef TARGET_ASM_ALIGNED_HI_OP
201 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
202 #undef TARGET_ASM_ALIGNED_SI_OP
203 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
204 #undef TARGET_ASM_ALIGNED_DI_OP
205 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
206 #undef TARGET_ASM_UNALIGNED_HI_OP
207 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
208 #undef TARGET_ASM_UNALIGNED_SI_OP
209 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
210 #undef TARGET_ASM_UNALIGNED_DI_OP
211 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
212 #undef TARGET_ASM_INTEGER
213 #define TARGET_ASM_INTEGER pa_assemble_integer
215 #undef TARGET_ASM_FUNCTION_PROLOGUE
216 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
217 #undef TARGET_ASM_FUNCTION_EPILOGUE
218 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
220 #undef TARGET_SCHED_ADJUST_COST
221 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
222 #undef TARGET_SCHED_ADJUST_PRIORITY
223 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
224 #undef TARGET_SCHED_ISSUE_RATE
225 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
227 #undef TARGET_ENCODE_SECTION_INFO
228 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
229 #undef TARGET_STRIP_NAME_ENCODING
230 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
232 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
233 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
235 #undef TARGET_ASM_OUTPUT_MI_THUNK
236 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
237 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
238 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
240 #undef TARGET_ASM_FILE_END
241 #define TARGET_ASM_FILE_END output_deferred_plabels
243 #if !defined(USE_COLLECT2)
244 #undef TARGET_ASM_CONSTRUCTOR
245 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
246 #undef TARGET_ASM_DESTRUCTOR
247 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
250 #undef TARGET_INIT_BUILTINS
251 #define TARGET_INIT_BUILTINS pa_init_builtins
253 #undef TARGET_RTX_COSTS
254 #define TARGET_RTX_COSTS hppa_rtx_costs
255 #undef TARGET_ADDRESS_COST
256 #define TARGET_ADDRESS_COST hppa_address_cost
258 #undef TARGET_MACHINE_DEPENDENT_REORG
259 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
261 #ifdef HPUX_LONG_DOUBLE_LIBRARY
262 #undef TARGET_INIT_LIBFUNCS
263 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
266 #undef TARGET_PROMOTE_FUNCTION_RETURN
267 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
268 #undef TARGET_PROMOTE_PROTOTYPES
269 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
271 #undef TARGET_STRUCT_VALUE_RTX
272 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
273 #undef TARGET_RETURN_IN_MEMORY
274 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
276 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
277 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
279 struct gcc_target targetm = TARGET_INITIALIZER;
282 override_options (void)
284 if (pa_cpu_string == NULL)
285 pa_cpu_string = TARGET_SCHED_DEFAULT;
287 if (! strcmp (pa_cpu_string, "8000"))
289 pa_cpu_string = "8000";
290 pa_cpu = PROCESSOR_8000;
292 else if (! strcmp (pa_cpu_string, "7100"))
294 pa_cpu_string = "7100";
295 pa_cpu = PROCESSOR_7100;
297 else if (! strcmp (pa_cpu_string, "700"))
299 pa_cpu_string = "700";
300 pa_cpu = PROCESSOR_700;
302 else if (! strcmp (pa_cpu_string, "7100LC"))
304 pa_cpu_string = "7100LC";
305 pa_cpu = PROCESSOR_7100LC;
307 else if (! strcmp (pa_cpu_string, "7200"))
309 pa_cpu_string = "7200";
310 pa_cpu = PROCESSOR_7200;
312 else if (! strcmp (pa_cpu_string, "7300"))
314 pa_cpu_string = "7300";
315 pa_cpu = PROCESSOR_7300;
319 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
322 /* Set the instruction set architecture. */
323 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
325 pa_arch_string = "1.0";
326 pa_arch = ARCHITECTURE_10;
327 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
329 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
331 pa_arch_string = "1.1";
332 pa_arch = ARCHITECTURE_11;
333 target_flags &= ~MASK_PA_20;
334 target_flags |= MASK_PA_11;
336 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
338 pa_arch_string = "2.0";
339 pa_arch = ARCHITECTURE_20;
340 target_flags |= MASK_PA_11 | MASK_PA_20;
342 else if (pa_arch_string)
344 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
347 /* Unconditional branches in the delay slot are not compatible with dwarf2
348 call frame information. There is no benefit in using this optimization
349 on PA8000 and later processors. */
350 if (pa_cpu >= PROCESSOR_8000
351 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
352 || flag_unwind_tables)
353 target_flags &= ~MASK_JUMP_IN_DELAY;
355 if (flag_pic && TARGET_PORTABLE_RUNTIME)
357 warning ("PIC code generation is not supported in the portable runtime model\n");
360 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
362 warning ("PIC code generation is not compatible with fast indirect calls\n");
365 if (! TARGET_GAS && write_symbols != NO_DEBUG)
367 warning ("-g is only supported when using GAS on this processor,");
368 warning ("-g option disabled");
369 write_symbols = NO_DEBUG;
372 /* We only support the "big PIC" model now. And we always generate PIC
373 code when in 64bit mode. */
374 if (flag_pic == 1 || TARGET_64BIT)
377 /* We can't guarantee that .dword is available for 32-bit targets. */
378 if (UNITS_PER_WORD == 4)
379 targetm.asm_out.aligned_op.di = NULL;
381 /* The unaligned ops are only available when using GAS. */
384 targetm.asm_out.unaligned_op.hi = NULL;
385 targetm.asm_out.unaligned_op.si = NULL;
386 targetm.asm_out.unaligned_op.di = NULL;
391 pa_init_builtins (void)
393 #ifdef DONT_HAVE_FPUTC_UNLOCKED
394 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
395 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
399 /* If FROM is a probable pointer register, mark TO as a probable
400 pointer register with the same pointer alignment as FROM. */
403 copy_reg_pointer (rtx to, rtx from)
405 if (REG_POINTER (from))
406 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
409 /* Return nonzero only if OP is a register of mode MODE,
412 reg_or_0_operand (rtx op, enum machine_mode mode)
414 return (op == CONST0_RTX (mode) || register_operand (op, mode));
417 /* Return nonzero if OP is suitable for use in a call to a named
420 For 2.5 try to eliminate either call_operand_address or
421 function_label_operand, they perform very similar functions. */
423 call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
425 return (GET_MODE (op) == word_mode
426 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
429 /* Return 1 if X contains a symbolic expression. We know these
430 expressions will have one of a few well defined forms, so
431 we need only check those forms. */
433 symbolic_expression_p (rtx x)
436 /* Strip off any HIGH. */
437 if (GET_CODE (x) == HIGH)
440 return (symbolic_operand (x, VOIDmode));
444 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
446 switch (GET_CODE (op))
453 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
454 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
455 && GET_CODE (XEXP (op, 1)) == CONST_INT);
461 /* Return truth value of statement that OP is a symbolic memory
462 operand of mode MODE. */
465 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
467 if (GET_CODE (op) == SUBREG)
468 op = SUBREG_REG (op);
469 if (GET_CODE (op) != MEM)
472 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
473 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
476 /* Return 1 if the operand is either a register, zero, or a memory operand
477 that is not symbolic. */
480 reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode)
482 if (register_operand (op, mode))
485 if (op == CONST0_RTX (mode))
488 if (GET_CODE (op) == SUBREG)
489 op = SUBREG_REG (op);
491 if (GET_CODE (op) != MEM)
494 /* Until problems with management of the REG_POINTER flag are resolved,
495 we need to delay creating move insns with unscaled indexed addresses
496 until CSE is not expected. */
497 if (!TARGET_NO_SPACE_REGS
499 && GET_CODE (XEXP (op, 0)) == PLUS
500 && REG_P (XEXP (XEXP (op, 0), 0))
501 && REG_P (XEXP (XEXP (op, 0), 1)))
504 return (!symbolic_memory_operand (op, mode)
505 && memory_address_p (mode, XEXP (op, 0)));
508 /* Return 1 if the operand is a register operand or a non-symbolic memory
509 operand after reload. This predicate is used for branch patterns that
510 internally handle register reloading. We need to accept non-symbolic
511 memory operands after reload to ensure that the pattern is still valid
512 if reload didn't find a hard register for the operand. */
515 reg_before_reload_operand (rtx op, enum machine_mode mode)
517 /* Don't accept a SUBREG since it will need a reload. */
518 if (GET_CODE (op) == SUBREG)
521 if (register_operand (op, mode))
525 && memory_operand (op, mode)
526 && !symbolic_memory_operand (op, mode))
532 /* Accept any constant that can be moved in one instruction into a
535 cint_ok_for_move (HOST_WIDE_INT intval)
537 /* OK if ldo, ldil, or zdepi, can be used. */
538 return (CONST_OK_FOR_LETTER_P (intval, 'J')
539 || CONST_OK_FOR_LETTER_P (intval, 'N')
540 || CONST_OK_FOR_LETTER_P (intval, 'K'));
543 /* Return 1 iff OP is an indexed memory operand. */
545 indexed_memory_operand (rtx op, enum machine_mode mode)
547 if (GET_MODE (op) != mode)
550 /* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
551 if (reload_completed && GET_CODE (op) == SUBREG)
552 op = SUBREG_REG (op);
554 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
559 return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op));
562 /* Accept anything that can be used as a destination operand for a
563 move instruction. We don't accept indexed memory operands since
564 they are supported only for floating point stores. */
566 move_dest_operand (rtx op, enum machine_mode mode)
568 if (register_operand (op, mode))
571 if (GET_MODE (op) != mode)
574 if (GET_CODE (op) == SUBREG)
575 op = SUBREG_REG (op);
577 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
582 return (memory_address_p (mode, op)
583 && !IS_INDEX_ADDR_P (op)
584 && !IS_LO_SUM_DLT_ADDR_P (op));
587 /* Accept anything that can be used as a source operand for a move
590 move_src_operand (rtx op, enum machine_mode mode)
592 if (register_operand (op, mode))
595 if (GET_CODE (op) == CONSTANT_P_RTX)
598 if (GET_CODE (op) == CONST_INT)
599 return cint_ok_for_move (INTVAL (op));
601 if (GET_MODE (op) != mode)
604 if (GET_CODE (op) == SUBREG)
605 op = SUBREG_REG (op);
607 if (GET_CODE (op) != MEM)
610 /* Until problems with management of the REG_POINTER flag are resolved,
611 we need to delay creating move insns with unscaled indexed addresses
612 until CSE is not expected. */
613 if (!TARGET_NO_SPACE_REGS
615 && GET_CODE (XEXP (op, 0)) == PLUS
616 && REG_P (XEXP (XEXP (op, 0), 0))
617 && REG_P (XEXP (XEXP (op, 0), 1)))
620 return memory_address_p (mode, XEXP (op, 0));
623 /* Accept REG and any CONST_INT that can be moved in one instruction into a
626 reg_or_cint_move_operand (rtx op, enum machine_mode mode)
628 if (register_operand (op, mode))
631 return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op)));
635 pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
640 switch (GET_CODE (op))
646 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
647 && GET_CODE (XEXP (op, 1)) == CONST_INT);
654 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
656 return reg_renumber && FP_REG_P (op);
661 /* Return truth value of whether OP can be used as an operand in a
662 three operand arithmetic insn that accepts registers of mode MODE
663 or 14-bit signed integers. */
665 arith_operand (rtx op, enum machine_mode mode)
667 return (register_operand (op, mode)
668 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
671 /* Return truth value of whether OP can be used as an operand in a
672 three operand arithmetic insn that accepts registers of mode MODE
673 or 11-bit signed integers. */
675 arith11_operand (rtx op, enum machine_mode mode)
677 return (register_operand (op, mode)
678 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
681 /* Return truth value of whether OP can be used as an operand in a
684 adddi3_operand (rtx op, enum machine_mode mode)
686 return (register_operand (op, mode)
687 || (GET_CODE (op) == CONST_INT
688 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
691 /* A constant integer suitable for use in a PRE_MODIFY memory
694 pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
696 return (GET_CODE (op) == CONST_INT
697 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
700 /* A constant integer suitable for use in a POST_MODIFY memory
703 post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
705 return (GET_CODE (op) == CONST_INT
706 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
710 arith_double_operand (rtx op, enum machine_mode mode)
712 return (register_operand (op, mode)
713 || (GET_CODE (op) == CONST_DOUBLE
714 && GET_MODE (op) == mode
715 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
716 && ((CONST_DOUBLE_HIGH (op) >= 0)
717 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
720 /* Return truth value of whether OP is an integer which fits the
721 range constraining immediate operands in three-address insns, or
722 is an integer register. */
725 ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
727 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
728 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
731 /* Return nonzero if OP is an integer register, else return zero. */
733 ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
735 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
738 /* Return truth value of whether OP is an integer which fits the
739 range constraining immediate operands in three-address insns. */
742 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
744 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
748 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
750 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
754 int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
756 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
760 uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
762 #if HOST_BITS_PER_WIDE_INT > 32
763 /* All allowed constants will fit a CONST_INT. */
764 return (GET_CODE (op) == CONST_INT
765 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
767 return (GET_CODE (op) == CONST_INT
768 || (GET_CODE (op) == CONST_DOUBLE
769 && CONST_DOUBLE_HIGH (op) == 0));
774 arith5_operand (rtx op, enum machine_mode mode)
776 return register_operand (op, mode) || int5_operand (op, mode);
779 /* True iff zdepi can be used to generate this CONST_INT.
780 zdepi first sign extends a 5 bit signed number to a given field
781 length, then places this field anywhere in a zero. */
783 zdepi_cint_p (unsigned HOST_WIDE_INT x)
785 unsigned HOST_WIDE_INT lsb_mask, t;
787 /* This might not be obvious, but it's at least fast.
788 This function is critical; we don't have the time loops would take. */
790 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
791 /* Return true iff t is a power of two. */
792 return ((t & (t - 1)) == 0);
795 /* True iff depi or extru can be used to compute (reg & mask).
796 Accept bit pattern like these:
801 and_mask_p (unsigned HOST_WIDE_INT mask)
804 mask += mask & -mask;
805 return (mask & (mask - 1)) == 0;
808 /* True iff depi or extru can be used to compute (reg & OP). */
810 and_operand (rtx op, enum machine_mode mode)
812 return (register_operand (op, mode)
813 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
816 /* True iff depi can be used to compute (reg | MASK). */
818 ior_mask_p (unsigned HOST_WIDE_INT mask)
820 mask += mask & -mask;
821 return (mask & (mask - 1)) == 0;
824 /* True iff depi can be used to compute (reg | OP). */
826 ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
828 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
832 lhs_lshift_operand (rtx op, enum machine_mode mode)
834 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
837 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
838 Such values can be the left hand side x in (x << r), using the zvdepi
841 lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
843 unsigned HOST_WIDE_INT x;
844 if (GET_CODE (op) != CONST_INT)
846 x = INTVAL (op) >> 4;
847 return (x & (x + 1)) == 0;
851 arith32_operand (rtx op, enum machine_mode mode)
853 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
857 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
859 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
862 /* Legitimize PIC addresses. If the address is already
863 position-independent, we return ORIG. Newly generated
864 position-independent addresses go to REG. If we need more
865 than one register, we lose. */
868 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
872 /* Labels need special handling. */
873 if (pic_label_operand (orig, mode))
875 /* We do not want to go through the movXX expanders here since that
876 would create recursion.
878 Nor do we really want to call a generator for a named pattern
879 since that requires multiple patterns if we want to support
882 So instead we just emit the raw set, which avoids the movXX
883 expanders completely. */
884 mark_reg_pointer (reg, BITS_PER_UNIT);
885 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
886 current_function_uses_pic_offset_table = 1;
889 if (GET_CODE (orig) == SYMBOL_REF)
896 /* Before reload, allocate a temporary register for the intermediate
897 result. This allows the sequence to be deleted when the final
898 result is unused and the insns are trivially dead. */
899 tmp_reg = ((reload_in_progress || reload_completed)
900 ? reg : gen_reg_rtx (Pmode));
902 emit_move_insn (tmp_reg,
903 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
904 gen_rtx_HIGH (word_mode, orig)));
906 = gen_rtx_MEM (Pmode,
907 gen_rtx_LO_SUM (Pmode, tmp_reg,
908 gen_rtx_UNSPEC (Pmode,
912 current_function_uses_pic_offset_table = 1;
913 MEM_NOTRAP_P (pic_ref) = 1;
914 RTX_UNCHANGING_P (pic_ref) = 1;
915 mark_reg_pointer (reg, BITS_PER_UNIT);
916 insn = emit_move_insn (reg, pic_ref);
918 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
919 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
923 else if (GET_CODE (orig) == CONST)
927 if (GET_CODE (XEXP (orig, 0)) == PLUS
928 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
934 if (GET_CODE (XEXP (orig, 0)) == PLUS)
936 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
937 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
938 base == reg ? 0 : reg);
943 if (GET_CODE (orig) == CONST_INT)
945 if (INT_14_BITS (orig))
946 return plus_constant (base, INTVAL (orig));
947 orig = force_reg (Pmode, orig);
949 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
950 /* Likewise, should we set special REG_NOTEs here? */
956 /* Try machine-dependent ways of modifying an illegitimate address
957 to be legitimate. If we find one, return the new, valid address.
958 This macro is used in only one place: `memory_address' in explow.c.
960 OLDX is the address as it was before break_out_memory_refs was called.
961 In some cases it is useful to look at this to decide what needs to be done.
963 MODE and WIN are passed so that this macro can use
964 GO_IF_LEGITIMATE_ADDRESS.
966 It is always safe for this macro to do nothing. It exists to recognize
967 opportunities to optimize the output.
969 For the PA, transform:
971 memory(X + <large int>)
975 if (<large int> & mask) >= 16
976 Y = (<large int> & ~mask) + mask + 1 Round up.
978 Y = (<large int> & ~mask) Round down.
980 memory (Z + (<large int> - Y));
982 This is for CSE to find several similar references, and only use one Z.
984 X can either be a SYMBOL_REF or REG, but because combine can not
985 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
986 D will not fit in 14 bits.
988 MODE_FLOAT references allow displacements which fit in 5 bits, so use
991 MODE_INT references allow displacements which fit in 14 bits, so use
994 This relies on the fact that most mode MODE_FLOAT references will use FP
995 registers and most mode MODE_INT references will use integer registers.
996 (In the rare case of an FP register used in an integer MODE, we depend
997 on secondary reloads to clean things up.)
1000 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1001 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1002 addressing modes to be used).
1004 Put X and Z into registers. Then put the entire expression into
1008 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1009 enum machine_mode mode)
1013 /* We need to canonicalize the order of operands in unscaled indexed
1014 addresses since the code that checks if an address is valid doesn't
1015 always try both orders. */
1016 if (!TARGET_NO_SPACE_REGS
1017 && GET_CODE (x) == PLUS
1018 && GET_MODE (x) == Pmode
1019 && REG_P (XEXP (x, 0))
1020 && REG_P (XEXP (x, 1))
1021 && REG_POINTER (XEXP (x, 0))
1022 && !REG_POINTER (XEXP (x, 1)))
1023 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1026 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1028 /* Strip off CONST. */
1029 if (GET_CODE (x) == CONST)
1032 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1033 That should always be safe. */
1034 if (GET_CODE (x) == PLUS
1035 && GET_CODE (XEXP (x, 0)) == REG
1036 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1038 rtx reg = force_reg (Pmode, XEXP (x, 1));
1039 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1042 /* Note we must reject symbols which represent function addresses
1043 since the assembler/linker can't handle arithmetic on plabels. */
1044 if (GET_CODE (x) == PLUS
1045 && GET_CODE (XEXP (x, 1)) == CONST_INT
1046 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1047 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1048 || GET_CODE (XEXP (x, 0)) == REG))
1050 rtx int_part, ptr_reg;
1052 int offset = INTVAL (XEXP (x, 1));
1055 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1056 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1058 /* Choose which way to round the offset. Round up if we
1059 are >= halfway to the next boundary. */
1060 if ((offset & mask) >= ((mask + 1) / 2))
1061 newoffset = (offset & ~ mask) + mask + 1;
1063 newoffset = (offset & ~ mask);
1065 /* If the newoffset will not fit in 14 bits (ldo), then
1066 handling this would take 4 or 5 instructions (2 to load
1067 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1068 add the new offset and the SYMBOL_REF.) Combine can
1069 not handle 4->2 or 5->2 combinations, so do not create
1071 if (! VAL_14_BITS_P (newoffset)
1072 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1074 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1077 gen_rtx_HIGH (Pmode, const_part));
1080 gen_rtx_LO_SUM (Pmode,
1081 tmp_reg, const_part));
1085 if (! VAL_14_BITS_P (newoffset))
1086 int_part = force_reg (Pmode, GEN_INT (newoffset));
1088 int_part = GEN_INT (newoffset);
1090 ptr_reg = force_reg (Pmode,
1091 gen_rtx_PLUS (Pmode,
1092 force_reg (Pmode, XEXP (x, 0)),
1095 return plus_constant (ptr_reg, offset - newoffset);
1098 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1100 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1101 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1102 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1103 && (OBJECT_P (XEXP (x, 1))
1104 || GET_CODE (XEXP (x, 1)) == SUBREG)
1105 && GET_CODE (XEXP (x, 1)) != CONST)
1107 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1111 if (GET_CODE (reg1) != REG)
1112 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1114 reg2 = XEXP (XEXP (x, 0), 0);
1115 if (GET_CODE (reg2) != REG)
1116 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1118 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1119 gen_rtx_MULT (Pmode,
1125 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1127 Only do so for floating point modes since this is more speculative
1128 and we lose if it's an integer store. */
1129 if (GET_CODE (x) == PLUS
1130 && GET_CODE (XEXP (x, 0)) == PLUS
1131 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1132 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1133 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1134 && (mode == SFmode || mode == DFmode))
1137 /* First, try and figure out what to use as a base register. */
1138 rtx reg1, reg2, base, idx, orig_base;
1140 reg1 = XEXP (XEXP (x, 0), 1);
1145 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1146 then emit_move_sequence will turn on REG_POINTER so we'll know
1147 it's a base register below. */
1148 if (GET_CODE (reg1) != REG)
1149 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1151 if (GET_CODE (reg2) != REG)
1152 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1154 /* Figure out what the base and index are. */
1156 if (GET_CODE (reg1) == REG
1157 && REG_POINTER (reg1))
1160 orig_base = XEXP (XEXP (x, 0), 1);
1161 idx = gen_rtx_PLUS (Pmode,
1162 gen_rtx_MULT (Pmode,
1163 XEXP (XEXP (XEXP (x, 0), 0), 0),
1164 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1167 else if (GET_CODE (reg2) == REG
1168 && REG_POINTER (reg2))
1171 orig_base = XEXP (x, 1);
1178 /* If the index adds a large constant, try to scale the
1179 constant so that it can be loaded with only one insn. */
1180 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1181 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1182 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1183 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1185 /* Divide the CONST_INT by the scale factor, then add it to A. */
1186 int val = INTVAL (XEXP (idx, 1));
1188 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1189 reg1 = XEXP (XEXP (idx, 0), 0);
1190 if (GET_CODE (reg1) != REG)
1191 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1193 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1195 /* We can now generate a simple scaled indexed address. */
1198 (Pmode, gen_rtx_PLUS (Pmode,
1199 gen_rtx_MULT (Pmode, reg1,
1200 XEXP (XEXP (idx, 0), 1)),
1204 /* If B + C is still a valid base register, then add them. */
1205 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1206 && INTVAL (XEXP (idx, 1)) <= 4096
1207 && INTVAL (XEXP (idx, 1)) >= -4096)
1209 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1212 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1214 reg2 = XEXP (XEXP (idx, 0), 0);
1215 if (GET_CODE (reg2) != CONST_INT)
1216 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1218 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1219 gen_rtx_MULT (Pmode,
1225 /* Get the index into a register, then add the base + index and
1226 return a register holding the result. */
1228 /* First get A into a register. */
1229 reg1 = XEXP (XEXP (idx, 0), 0);
1230 if (GET_CODE (reg1) != REG)
1231 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1233 /* And get B into a register. */
1234 reg2 = XEXP (idx, 1);
1235 if (GET_CODE (reg2) != REG)
1236 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1238 reg1 = force_reg (Pmode,
1239 gen_rtx_PLUS (Pmode,
1240 gen_rtx_MULT (Pmode, reg1,
1241 XEXP (XEXP (idx, 0), 1)),
1244 /* Add the result to our base register and return. */
1245 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1249 /* Uh-oh. We might have an address for x[n-100000]. This needs
1250 special handling to avoid creating an indexed memory address
1251 with x-100000 as the base.
1253 If the constant part is small enough, then it's still safe because
1254 there is a guard page at the beginning and end of the data segment.
1256 Scaled references are common enough that we want to try and rearrange the
1257 terms so that we can use indexing for these addresses too. Only
1258 do the optimization for floatint point modes. */
1260 if (GET_CODE (x) == PLUS
1261 && symbolic_expression_p (XEXP (x, 1)))
1263 /* Ugly. We modify things here so that the address offset specified
1264 by the index expression is computed first, then added to x to form
1265 the entire address. */
1267 rtx regx1, regx2, regy1, regy2, y;
1269 /* Strip off any CONST. */
1271 if (GET_CODE (y) == CONST)
1274 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1276 /* See if this looks like
1277 (plus (mult (reg) (shadd_const))
1278 (const (plus (symbol_ref) (const_int))))
1280 Where const_int is small. In that case the const
1281 expression is a valid pointer for indexing.
1283 If const_int is big, but can be divided evenly by shadd_const
1284 and added to (reg). This allows more scaled indexed addresses. */
1285 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1286 && GET_CODE (XEXP (x, 0)) == MULT
1287 && GET_CODE (XEXP (y, 1)) == CONST_INT
1288 && INTVAL (XEXP (y, 1)) >= -4096
1289 && INTVAL (XEXP (y, 1)) <= 4095
1290 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1291 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1293 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1297 if (GET_CODE (reg1) != REG)
1298 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1300 reg2 = XEXP (XEXP (x, 0), 0);
1301 if (GET_CODE (reg2) != REG)
1302 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1304 return force_reg (Pmode,
1305 gen_rtx_PLUS (Pmode,
1306 gen_rtx_MULT (Pmode,
1311 else if ((mode == DFmode || mode == SFmode)
1312 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1313 && GET_CODE (XEXP (x, 0)) == MULT
1314 && GET_CODE (XEXP (y, 1)) == CONST_INT
1315 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1316 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1317 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1320 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1321 / INTVAL (XEXP (XEXP (x, 0), 1))));
1322 regx2 = XEXP (XEXP (x, 0), 0);
1323 if (GET_CODE (regx2) != REG)
1324 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1325 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1329 gen_rtx_PLUS (Pmode,
1330 gen_rtx_MULT (Pmode, regx2,
1331 XEXP (XEXP (x, 0), 1)),
1332 force_reg (Pmode, XEXP (y, 0))));
1334 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1335 && INTVAL (XEXP (y, 1)) >= -4096
1336 && INTVAL (XEXP (y, 1)) <= 4095)
1338 /* This is safe because of the guard page at the
1339 beginning and end of the data space. Just
1340 return the original address. */
1345 /* Doesn't look like one we can optimize. */
1346 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1347 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1348 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1349 regx1 = force_reg (Pmode,
1350 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1352 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1360 /* For the HPPA, REG and REG+CONST is cost 0
1361 and addresses involving symbolic constants are cost 2.
1363 PIC addresses are very expensive.
1365 It is no coincidence that this has the same structure
1366 as GO_IF_LEGITIMATE_ADDRESS. */
1369 hppa_address_cost (rtx X)
1371 switch (GET_CODE (X))
1384 /* Compute a (partial) cost for rtx X. Return true if the complete
1385 cost has been computed, and false if subexpressions should be
1386 scanned. In either case, *TOTAL contains the cost result. */
1389 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1394 if (INTVAL (x) == 0)
1396 else if (INT_14_BITS (x))
1413 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1414 && outer_code != SET)
1421 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1422 *total = COSTS_N_INSNS (3);
1423 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1424 *total = COSTS_N_INSNS (8);
1426 *total = COSTS_N_INSNS (20);
1430 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1432 *total = COSTS_N_INSNS (14);
1440 *total = COSTS_N_INSNS (60);
1443 case PLUS: /* this includes shNadd insns */
1445 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1446 *total = COSTS_N_INSNS (3);
1448 *total = COSTS_N_INSNS (1);
1454 *total = COSTS_N_INSNS (1);
1462 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1463 new rtx with the correct mode. */
1465 force_mode (enum machine_mode mode, rtx orig)
1467 if (mode == GET_MODE (orig))
1470 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1473 return gen_rtx_REG (mode, REGNO (orig));
1476 /* Emit insns to move operands[1] into operands[0].
1478 Return 1 if we have written out everything that needs to be done to
1479 do the move. Otherwise, return 0 and the caller will emit the move
1482 Note SCRATCH_REG may not be in the proper mode depending on how it
1483 will be used. This routine is responsible for creating a new copy
1484 of SCRATCH_REG in the proper mode. */
1487 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1489 register rtx operand0 = operands[0];
1490 register rtx operand1 = operands[1];
1493 /* We can only handle indexed addresses in the destination operand
1494 of floating point stores. Thus, we need to break out indexed
1495 addresses from the destination operand. */
1496 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1498 /* This is only safe up to the beginning of life analysis. */
1502 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1503 operand0 = replace_equiv_address (operand0, tem);
1506 /* On targets with non-equivalent space registers, break out unscaled
1507 indexed addresses from the source operand before the final CSE.
1508 We have to do this because the REG_POINTER flag is not correctly
1509 carried through various optimization passes and CSE may substitute
1510 a pseudo without the pointer set for one with the pointer set. As
1511 a result, we loose various opportunities to create insns with
1512 unscaled indexed addresses. */
1513 if (!TARGET_NO_SPACE_REGS
1514 && !cse_not_expected
1515 && GET_CODE (operand1) == MEM
1516 && GET_CODE (XEXP (operand1, 0)) == PLUS
1517 && REG_P (XEXP (XEXP (operand1, 0), 0))
1518 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1520 = replace_equiv_address (operand1,
1521 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1524 && reload_in_progress && GET_CODE (operand0) == REG
1525 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1526 operand0 = reg_equiv_mem[REGNO (operand0)];
1527 else if (scratch_reg
1528 && reload_in_progress && GET_CODE (operand0) == SUBREG
1529 && GET_CODE (SUBREG_REG (operand0)) == REG
1530 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1532 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1533 the code which tracks sets/uses for delete_output_reload. */
1534 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1535 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1536 SUBREG_BYTE (operand0));
1537 operand0 = alter_subreg (&temp);
1541 && reload_in_progress && GET_CODE (operand1) == REG
1542 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1543 operand1 = reg_equiv_mem[REGNO (operand1)];
1544 else if (scratch_reg
1545 && reload_in_progress && GET_CODE (operand1) == SUBREG
1546 && GET_CODE (SUBREG_REG (operand1)) == REG
1547 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1549 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1550 the code which tracks sets/uses for delete_output_reload. */
1551 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1552 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1553 SUBREG_BYTE (operand1));
1554 operand1 = alter_subreg (&temp);
1557 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1558 && ((tem = find_replacement (&XEXP (operand0, 0)))
1559 != XEXP (operand0, 0)))
1560 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1562 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1563 && ((tem = find_replacement (&XEXP (operand1, 0)))
1564 != XEXP (operand1, 0)))
1565 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1567 /* Handle secondary reloads for loads/stores of FP registers from
1568 REG+D addresses where D does not fit in 5 bits, including
1569 (subreg (mem (addr))) cases. */
1571 && fp_reg_operand (operand0, mode)
1572 && ((GET_CODE (operand1) == MEM
1573 && !memory_address_p (DFmode, XEXP (operand1, 0)))
1574 || ((GET_CODE (operand1) == SUBREG
1575 && GET_CODE (XEXP (operand1, 0)) == MEM
1576 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))))
1578 if (GET_CODE (operand1) == SUBREG)
1579 operand1 = XEXP (operand1, 0);
1581 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1582 it in WORD_MODE regardless of what mode it was originally given
1584 scratch_reg = force_mode (word_mode, scratch_reg);
1586 /* D might not fit in 14 bits either; for such cases load D into
1588 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1590 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1591 emit_move_insn (scratch_reg,
1592 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1594 XEXP (XEXP (operand1, 0), 0),
1598 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1599 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1600 gen_rtx_MEM (mode, scratch_reg)));
1603 else if (scratch_reg
1604 && fp_reg_operand (operand1, mode)
1605 && ((GET_CODE (operand0) == MEM
1606 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1607 || ((GET_CODE (operand0) == SUBREG)
1608 && GET_CODE (XEXP (operand0, 0)) == MEM
1609 && !memory_address_p (DFmode,
1610 XEXP (XEXP (operand0, 0), 0)))))
1612 if (GET_CODE (operand0) == SUBREG)
1613 operand0 = XEXP (operand0, 0);
1615 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1616 it in WORD_MODE regardless of what mode it was originally given
1618 scratch_reg = force_mode (word_mode, scratch_reg);
1620 /* D might not fit in 14 bits either; for such cases load D into
1622 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1624 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1625 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1628 XEXP (XEXP (operand0, 0),
1633 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1634 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1638 /* Handle secondary reloads for loads of FP registers from constant
1639 expressions by forcing the constant into memory.
1641 Use scratch_reg to hold the address of the memory location.
1643 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1644 NO_REGS when presented with a const_int and a register class
1645 containing only FP registers. Doing so unfortunately creates
1646 more problems than it solves. Fix this for 2.5. */
1647 else if (scratch_reg
1648 && CONSTANT_P (operand1)
1649 && fp_reg_operand (operand0, mode))
1653 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1654 it in WORD_MODE regardless of what mode it was originally given
1656 scratch_reg = force_mode (word_mode, scratch_reg);
1658 /* Force the constant into memory and put the address of the
1659 memory location into scratch_reg. */
1660 xoperands[0] = scratch_reg;
1661 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1662 emit_move_sequence (xoperands, Pmode, 0);
1664 /* Now load the destination register. */
1665 emit_insn (gen_rtx_SET (mode, operand0,
1666 gen_rtx_MEM (mode, scratch_reg)));
1669 /* Handle secondary reloads for SAR. These occur when trying to load
1670 the SAR from memory, FP register, or with a constant. */
1671 else if (scratch_reg
1672 && GET_CODE (operand0) == REG
1673 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1674 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1675 && (GET_CODE (operand1) == MEM
1676 || GET_CODE (operand1) == CONST_INT
1677 || (GET_CODE (operand1) == REG
1678 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1680 /* D might not fit in 14 bits either; for such cases load D into
1682 if (GET_CODE (operand1) == MEM
1683 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1685 /* We are reloading the address into the scratch register, so we
1686 want to make sure the scratch register is a full register. */
1687 scratch_reg = force_mode (word_mode, scratch_reg);
1689 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1690 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1693 XEXP (XEXP (operand1, 0),
1697 /* Now we are going to load the scratch register from memory,
1698 we want to load it in the same width as the original MEM,
1699 which must be the same as the width of the ultimate destination,
1701 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1703 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1708 /* We want to load the scratch register using the same mode as
1709 the ultimate destination. */
1710 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1712 emit_move_insn (scratch_reg, operand1);
1715 /* And emit the insn to set the ultimate destination. We know that
1716 the scratch register has the same mode as the destination at this
1718 emit_move_insn (operand0, scratch_reg);
1721 /* Handle the most common case: storing into a register. */
1722 else if (register_operand (operand0, mode))
1724 if (register_operand (operand1, mode)
1725 || (GET_CODE (operand1) == CONST_INT
1726 && cint_ok_for_move (INTVAL (operand1)))
1727 || (operand1 == CONST0_RTX (mode))
1728 || (GET_CODE (operand1) == HIGH
1729 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1730 /* Only `general_operands' can come here, so MEM is ok. */
1731 || GET_CODE (operand1) == MEM)
1733 /* Various sets are created during RTL generation which don't
1734 have the REG_POINTER flag correctly set. After the CSE pass,
1735 instruction recognition can fail if we don't consistently
1736 set this flag when performing register copies. This should
1737 also improve the opportunities for creating insns that use
1738 unscaled indexing. */
1739 if (REG_P (operand0) && REG_P (operand1))
1741 if (REG_POINTER (operand1)
1742 && !REG_POINTER (operand0)
1743 && !HARD_REGISTER_P (operand0))
1744 copy_reg_pointer (operand0, operand1);
1745 else if (REG_POINTER (operand0)
1746 && !REG_POINTER (operand1)
1747 && !HARD_REGISTER_P (operand1))
1748 copy_reg_pointer (operand1, operand0);
1751 /* When MEMs are broken out, the REG_POINTER flag doesn't
1752 get set. In some cases, we can set the REG_POINTER flag
1753 from the declaration for the MEM. */
1754 if (REG_P (operand0)
1755 && GET_CODE (operand1) == MEM
1756 && !REG_POINTER (operand0))
1758 tree decl = MEM_EXPR (operand1);
1760 /* Set the register pointer flag and register alignment
1761 if the declaration for this memory reference is a
1762 pointer type. Fortran indirect argument references
1765 && !(flag_argument_noalias > 1
1766 && TREE_CODE (decl) == INDIRECT_REF
1767 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1771 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1773 if (TREE_CODE (decl) == COMPONENT_REF)
1774 decl = TREE_OPERAND (decl, 1);
1776 type = TREE_TYPE (decl);
1777 if (TREE_CODE (type) == ARRAY_TYPE)
1778 type = get_inner_array_type (type);
1780 if (POINTER_TYPE_P (type))
1784 type = TREE_TYPE (type);
1785 /* Using TYPE_ALIGN_OK is rather conservative as
1786 only the ada frontend actually sets it. */
1787 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1789 mark_reg_pointer (operand0, align);
1794 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1798 else if (GET_CODE (operand0) == MEM)
1800 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1801 && !(reload_in_progress || reload_completed))
1803 rtx temp = gen_reg_rtx (DFmode);
1805 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1806 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1809 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1811 /* Run this case quickly. */
1812 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1815 if (! (reload_in_progress || reload_completed))
1817 operands[0] = validize_mem (operand0);
1818 operands[1] = operand1 = force_reg (mode, operand1);
1822 /* Simplify the source if we need to.
1823 Note we do have to handle function labels here, even though we do
1824 not consider them legitimate constants. Loop optimizations can
1825 call the emit_move_xxx with one as a source. */
1826 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1827 || function_label_operand (operand1, mode)
1828 || (GET_CODE (operand1) == HIGH
1829 && symbolic_operand (XEXP (operand1, 0), mode)))
1833 if (GET_CODE (operand1) == HIGH)
1836 operand1 = XEXP (operand1, 0);
1838 if (symbolic_operand (operand1, mode))
1840 /* Argh. The assembler and linker can't handle arithmetic
1843 So we force the plabel into memory, load operand0 from
1844 the memory location, then add in the constant part. */
1845 if ((GET_CODE (operand1) == CONST
1846 && GET_CODE (XEXP (operand1, 0)) == PLUS
1847 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1848 || function_label_operand (operand1, mode))
1850 rtx temp, const_part;
1852 /* Figure out what (if any) scratch register to use. */
1853 if (reload_in_progress || reload_completed)
1855 scratch_reg = scratch_reg ? scratch_reg : operand0;
1856 /* SCRATCH_REG will hold an address and maybe the actual
1857 data. We want it in WORD_MODE regardless of what mode it
1858 was originally given to us. */
1859 scratch_reg = force_mode (word_mode, scratch_reg);
1862 scratch_reg = gen_reg_rtx (Pmode);
1864 if (GET_CODE (operand1) == CONST)
1866 /* Save away the constant part of the expression. */
1867 const_part = XEXP (XEXP (operand1, 0), 1);
1868 if (GET_CODE (const_part) != CONST_INT)
1871 /* Force the function label into memory. */
1872 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1876 /* No constant part. */
1877 const_part = NULL_RTX;
1879 /* Force the function label into memory. */
1880 temp = force_const_mem (mode, operand1);
1884 /* Get the address of the memory location. PIC-ify it if
1886 temp = XEXP (temp, 0);
1888 temp = legitimize_pic_address (temp, mode, scratch_reg);
1890 /* Put the address of the memory location into our destination
1893 emit_move_sequence (operands, mode, scratch_reg);
1895 /* Now load from the memory location into our destination
1897 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1898 emit_move_sequence (operands, mode, scratch_reg);
1900 /* And add back in the constant part. */
1901 if (const_part != NULL_RTX)
1902 expand_inc (operand0, const_part);
1911 if (reload_in_progress || reload_completed)
1913 temp = scratch_reg ? scratch_reg : operand0;
1914 /* TEMP will hold an address and maybe the actual
1915 data. We want it in WORD_MODE regardless of what mode it
1916 was originally given to us. */
1917 temp = force_mode (word_mode, temp);
1920 temp = gen_reg_rtx (Pmode);
1922 /* (const (plus (symbol) (const_int))) must be forced to
1923 memory during/after reload if the const_int will not fit
1925 if (GET_CODE (operand1) == CONST
1926 && GET_CODE (XEXP (operand1, 0)) == PLUS
1927 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1928 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1929 && (reload_completed || reload_in_progress)
1932 operands[1] = force_const_mem (mode, operand1);
1933 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1935 emit_move_sequence (operands, mode, temp);
1939 operands[1] = legitimize_pic_address (operand1, mode, temp);
1940 if (REG_P (operand0) && REG_P (operands[1]))
1941 copy_reg_pointer (operand0, operands[1]);
1942 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1945 /* On the HPPA, references to data space are supposed to use dp,
1946 register 27, but showing it in the RTL inhibits various cse
1947 and loop optimizations. */
1952 if (reload_in_progress || reload_completed)
1954 temp = scratch_reg ? scratch_reg : operand0;
1955 /* TEMP will hold an address and maybe the actual
1956 data. We want it in WORD_MODE regardless of what mode it
1957 was originally given to us. */
1958 temp = force_mode (word_mode, temp);
1961 temp = gen_reg_rtx (mode);
1963 /* Loading a SYMBOL_REF into a register makes that register
1964 safe to be used as the base in an indexed address.
1966 Don't mark hard registers though. That loses. */
1967 if (GET_CODE (operand0) == REG
1968 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1969 mark_reg_pointer (operand0, BITS_PER_UNIT);
1970 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1971 mark_reg_pointer (temp, BITS_PER_UNIT);
1974 set = gen_rtx_SET (mode, operand0, temp);
1976 set = gen_rtx_SET (VOIDmode,
1978 gen_rtx_LO_SUM (mode, temp, operand1));
1980 emit_insn (gen_rtx_SET (VOIDmode,
1982 gen_rtx_HIGH (mode, operand1)));
1988 else if (GET_CODE (operand1) != CONST_INT
1989 || !cint_ok_for_move (INTVAL (operand1)))
1993 HOST_WIDE_INT value = 0;
1994 HOST_WIDE_INT insv = 0;
1997 if (GET_CODE (operand1) == CONST_INT)
1998 value = INTVAL (operand1);
2001 && GET_CODE (operand1) == CONST_INT
2002 && HOST_BITS_PER_WIDE_INT > 32
2003 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2007 /* Extract the low order 32 bits of the value and sign extend.
2008 If the new value is the same as the original value, we can
2009 can use the original value as-is. If the new value is
2010 different, we use it and insert the most-significant 32-bits
2011 of the original value into the final result. */
2012 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2013 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2016 #if HOST_BITS_PER_WIDE_INT > 32
2017 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2021 operand1 = GEN_INT (nval);
2025 if (reload_in_progress || reload_completed)
2026 temp = scratch_reg ? scratch_reg : operand0;
2028 temp = gen_reg_rtx (mode);
2030 /* We don't directly split DImode constants on 32-bit targets
2031 because PLUS uses an 11-bit immediate and the insn sequence
2032 generated is not as efficient as the one using HIGH/LO_SUM. */
2033 if (GET_CODE (operand1) == CONST_INT
2034 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2037 /* Directly break constant into high and low parts. This
2038 provides better optimization opportunities because various
2039 passes recognize constants split with PLUS but not LO_SUM.
2040 We use a 14-bit signed low part except when the addition
2041 of 0x4000 to the high part might change the sign of the
2043 HOST_WIDE_INT low = value & 0x3fff;
2044 HOST_WIDE_INT high = value & ~ 0x3fff;
2048 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2056 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2057 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2061 emit_insn (gen_rtx_SET (VOIDmode, temp,
2062 gen_rtx_HIGH (mode, operand1)));
2063 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2066 insn = emit_move_insn (operands[0], operands[1]);
2068 /* Now insert the most significant 32 bits of the value
2069 into the register. When we don't have a second register
2070 available, it could take up to nine instructions to load
2071 a 64-bit integer constant. Prior to reload, we force
2072 constants that would take more than three instructions
2073 to load to the constant pool. During and after reload,
2074 we have to handle all possible values. */
2077 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2078 register and the value to be inserted is outside the
2079 range that can be loaded with three depdi instructions. */
2080 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2082 operand1 = GEN_INT (insv);
2084 emit_insn (gen_rtx_SET (VOIDmode, temp,
2085 gen_rtx_HIGH (mode, operand1)));
2086 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2087 emit_insn (gen_insv (operand0, GEN_INT (32),
2092 int len = 5, pos = 27;
2094 /* Insert the bits using the depdi instruction. */
2097 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2098 HOST_WIDE_INT sign = v5 < 0;
2100 /* Left extend the insertion. */
2101 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2102 while (pos > 0 && (insv & 1) == sign)
2104 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2109 emit_insn (gen_insv (operand0, GEN_INT (len),
2110 GEN_INT (pos), GEN_INT (v5)));
2112 len = pos > 0 && pos < 5 ? pos : 5;
2119 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
2124 /* Now have insn-emit do whatever it normally does. */
2128 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2129 it will need a link/runtime reloc). */
2132 reloc_needed (tree exp)
2136 switch (TREE_CODE (exp))
2143 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2144 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2149 case NON_LVALUE_EXPR:
2150 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2156 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
2157 if (TREE_VALUE (link) != 0)
2158 reloc |= reloc_needed (TREE_VALUE (link));
2171 /* Does operand (which is a symbolic_operand) live in text space?
2172 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2176 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2178 if (GET_CODE (operand) == CONST)
2179 operand = XEXP (XEXP (operand, 0), 0);
2182 if (GET_CODE (operand) == SYMBOL_REF)
2183 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2187 if (GET_CODE (operand) == SYMBOL_REF)
2188 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2194 /* Return the best assembler insn template
2195 for moving operands[1] into operands[0] as a fullword. */
2197 singlemove_string (rtx *operands)
2199 HOST_WIDE_INT intval;
2201 if (GET_CODE (operands[0]) == MEM)
2202 return "stw %r1,%0";
2203 if (GET_CODE (operands[1]) == MEM)
2205 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2210 if (GET_MODE (operands[1]) != SFmode)
2213 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2215 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2216 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2218 operands[1] = GEN_INT (i);
2219 /* Fall through to CONST_INT case. */
2221 if (GET_CODE (operands[1]) == CONST_INT)
2223 intval = INTVAL (operands[1]);
2225 if (VAL_14_BITS_P (intval))
2227 else if ((intval & 0x7ff) == 0)
2228 return "ldil L'%1,%0";
2229 else if (zdepi_cint_p (intval))
2230 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2232 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2234 return "copy %1,%0";
2238 /* Compute position (in OP[1]) and width (in OP[2])
2239 useful for copying IMM to a register using the zdepi
2240 instructions. Store the immediate value to insert in OP[0]. */
2242 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2246 /* Find the least significant set bit in IMM. */
2247 for (lsb = 0; lsb < 32; lsb++)
2254 /* Choose variants based on *sign* of the 5-bit field. */
2255 if ((imm & 0x10) == 0)
2256 len = (lsb <= 28) ? 4 : 32 - lsb;
2259 /* Find the width of the bitstring in IMM. */
2260 for (len = 5; len < 32; len++)
2262 if ((imm & (1 << len)) == 0)
2266 /* Sign extend IMM as a 5-bit value. */
2267 imm = (imm & 0xf) - 0x10;
2275 /* Compute position (in OP[1]) and width (in OP[2])
2276 useful for copying IMM to a register using the depdi,z
2277 instructions. Store the immediate value to insert in OP[0]. */
2279 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2281 HOST_WIDE_INT lsb, len;
2283 /* Find the least significant set bit in IMM. */
2284 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2291 /* Choose variants based on *sign* of the 5-bit field. */
2292 if ((imm & 0x10) == 0)
2293 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2294 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2297 /* Find the width of the bitstring in IMM. */
2298 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2300 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2304 /* Sign extend IMM as a 5-bit value. */
2305 imm = (imm & 0xf) - 0x10;
2313 /* Output assembler code to perform a doubleword move insn
2314 with operands OPERANDS. */
2317 output_move_double (rtx *operands)
2319 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2321 rtx addreg0 = 0, addreg1 = 0;
2323 /* First classify both operands. */
2325 if (REG_P (operands[0]))
2327 else if (offsettable_memref_p (operands[0]))
2329 else if (GET_CODE (operands[0]) == MEM)
2334 if (REG_P (operands[1]))
2336 else if (CONSTANT_P (operands[1]))
2338 else if (offsettable_memref_p (operands[1]))
2340 else if (GET_CODE (operands[1]) == MEM)
2345 /* Check for the cases that the operand constraints are not
2346 supposed to allow to happen. Abort if we get one,
2347 because generating code for these cases is painful. */
2349 if (optype0 != REGOP && optype1 != REGOP)
2352 /* Handle auto decrementing and incrementing loads and stores
2353 specifically, since the structure of the function doesn't work
2354 for them without major modification. Do it better when we learn
2355 this port about the general inc/dec addressing of PA.
2356 (This was written by tege. Chide him if it doesn't work.) */
2358 if (optype0 == MEMOP)
2360 /* We have to output the address syntax ourselves, since print_operand
2361 doesn't deal with the addresses we want to use. Fix this later. */
2363 rtx addr = XEXP (operands[0], 0);
2364 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2366 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2368 operands[0] = XEXP (addr, 0);
2369 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2372 if (!reg_overlap_mentioned_p (high_reg, addr))
2374 /* No overlap between high target register and address
2375 register. (We do this in a non-obvious way to
2376 save a register file writeback) */
2377 if (GET_CODE (addr) == POST_INC)
2378 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2379 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2384 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2386 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2388 operands[0] = XEXP (addr, 0);
2389 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2392 if (!reg_overlap_mentioned_p (high_reg, addr))
2394 /* No overlap between high target register and address
2395 register. (We do this in a non-obvious way to
2396 save a register file writeback) */
2397 if (GET_CODE (addr) == PRE_INC)
2398 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2399 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2405 if (optype1 == MEMOP)
2407 /* We have to output the address syntax ourselves, since print_operand
2408 doesn't deal with the addresses we want to use. Fix this later. */
2410 rtx addr = XEXP (operands[1], 0);
2411 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2413 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2415 operands[1] = XEXP (addr, 0);
2416 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2419 if (!reg_overlap_mentioned_p (high_reg, addr))
2421 /* No overlap between high target register and address
2422 register. (We do this in a non-obvious way to
2423 save a register file writeback) */
2424 if (GET_CODE (addr) == POST_INC)
2425 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2426 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2430 /* This is an undefined situation. We should load into the
2431 address register *and* update that register. Probably
2432 we don't need to handle this at all. */
2433 if (GET_CODE (addr) == POST_INC)
2434 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2435 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2438 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2440 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2442 operands[1] = XEXP (addr, 0);
2443 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2446 if (!reg_overlap_mentioned_p (high_reg, addr))
2448 /* No overlap between high target register and address
2449 register. (We do this in a non-obvious way to
2450 save a register file writeback) */
2451 if (GET_CODE (addr) == PRE_INC)
2452 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2453 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2457 /* This is an undefined situation. We should load into the
2458 address register *and* update that register. Probably
2459 we don't need to handle this at all. */
2460 if (GET_CODE (addr) == PRE_INC)
2461 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2462 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2465 else if (GET_CODE (addr) == PLUS
2466 && GET_CODE (XEXP (addr, 0)) == MULT)
2468 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2470 if (!reg_overlap_mentioned_p (high_reg, addr))
2474 xoperands[0] = high_reg;
2475 xoperands[1] = XEXP (addr, 1);
2476 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2477 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2478 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2480 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2486 xoperands[0] = high_reg;
2487 xoperands[1] = XEXP (addr, 1);
2488 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2489 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2490 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2492 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2497 /* If an operand is an unoffsettable memory ref, find a register
2498 we can increment temporarily to make it refer to the second word. */
2500 if (optype0 == MEMOP)
2501 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2503 if (optype1 == MEMOP)
2504 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2506 /* Ok, we can do one word at a time.
2507 Normally we do the low-numbered word first.
2509 In either case, set up in LATEHALF the operands to use
2510 for the high-numbered word and in some cases alter the
2511 operands in OPERANDS to be suitable for the low-numbered word. */
2513 if (optype0 == REGOP)
2514 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2515 else if (optype0 == OFFSOP)
2516 latehalf[0] = adjust_address (operands[0], SImode, 4);
2518 latehalf[0] = operands[0];
2520 if (optype1 == REGOP)
2521 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2522 else if (optype1 == OFFSOP)
2523 latehalf[1] = adjust_address (operands[1], SImode, 4);
2524 else if (optype1 == CNSTOP)
2525 split_double (operands[1], &operands[1], &latehalf[1]);
2527 latehalf[1] = operands[1];
2529 /* If the first move would clobber the source of the second one,
2530 do them in the other order.
2532 This can happen in two cases:
2534 mem -> register where the first half of the destination register
2535 is the same register used in the memory's address. Reload
2536 can create such insns.
2538 mem in this case will be either register indirect or register
2539 indirect plus a valid offset.
2541 register -> register move where REGNO(dst) == REGNO(src + 1)
2542 someone (Tim/Tege?) claimed this can happen for parameter loads.
2544 Handle mem -> register case first. */
2545 if (optype0 == REGOP
2546 && (optype1 == MEMOP || optype1 == OFFSOP)
2547 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2550 /* Do the late half first. */
2552 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2553 output_asm_insn (singlemove_string (latehalf), latehalf);
2557 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2558 return singlemove_string (operands);
2561 /* Now handle register -> register case. */
2562 if (optype0 == REGOP && optype1 == REGOP
2563 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2565 output_asm_insn (singlemove_string (latehalf), latehalf);
2566 return singlemove_string (operands);
2569 /* Normal case: do the two words, low-numbered first. */
2571 output_asm_insn (singlemove_string (operands), operands);
2573 /* Make any unoffsettable addresses point at high-numbered word. */
2575 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2577 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2580 output_asm_insn (singlemove_string (latehalf), latehalf);
2582 /* Undo the adds we just did. */
2584 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2586 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2592 output_fp_move_double (rtx *operands)
2594 if (FP_REG_P (operands[0]))
2596 if (FP_REG_P (operands[1])
2597 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2598 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2600 output_asm_insn ("fldd%F1 %1,%0", operands);
2602 else if (FP_REG_P (operands[1]))
2604 output_asm_insn ("fstd%F0 %1,%0", operands);
2606 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2608 if (GET_CODE (operands[0]) == REG)
2611 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2612 xoperands[0] = operands[0];
2613 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2615 /* This is a pain. You have to be prepared to deal with an
2616 arbitrary address here including pre/post increment/decrement.
2618 so avoid this in the MD. */
2626 /* Return a REG that occurs in ADDR with coefficient 1.
2627 ADDR can be effectively incremented by incrementing REG. */
2630 find_addr_reg (rtx addr)
2632 while (GET_CODE (addr) == PLUS)
2634 if (GET_CODE (XEXP (addr, 0)) == REG)
2635 addr = XEXP (addr, 0);
2636 else if (GET_CODE (XEXP (addr, 1)) == REG)
2637 addr = XEXP (addr, 1);
2638 else if (CONSTANT_P (XEXP (addr, 0)))
2639 addr = XEXP (addr, 1);
2640 else if (CONSTANT_P (XEXP (addr, 1)))
2641 addr = XEXP (addr, 0);
2645 if (GET_CODE (addr) == REG)
2650 /* Emit code to perform a block move.
2652 OPERANDS[0] is the destination pointer as a REG, clobbered.
2653 OPERANDS[1] is the source pointer as a REG, clobbered.
2654 OPERANDS[2] is a register for temporary storage.
2655 OPERANDS[3] is a register for temporary storage.
2656 OPERANDS[4] is the size as a CONST_INT
2657 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2658 OPERANDS[6] is another temporary register. */
2661 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2663 int align = INTVAL (operands[5]);
2664 unsigned long n_bytes = INTVAL (operands[4]);
2666 /* We can't move more than a word at a time because the PA
2667 has no longer integer move insns. (Could use fp mem ops?) */
2668 if (align > (TARGET_64BIT ? 8 : 4))
2669 align = (TARGET_64BIT ? 8 : 4);
2671 /* Note that we know each loop below will execute at least twice
2672 (else we would have open-coded the copy). */
2676 /* Pre-adjust the loop counter. */
2677 operands[4] = GEN_INT (n_bytes - 16);
2678 output_asm_insn ("ldi %4,%2", operands);
2681 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2682 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2683 output_asm_insn ("std,ma %3,8(%0)", operands);
2684 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2685 output_asm_insn ("std,ma %6,8(%0)", operands);
2687 /* Handle the residual. There could be up to 7 bytes of
2688 residual to copy! */
2689 if (n_bytes % 16 != 0)
2691 operands[4] = GEN_INT (n_bytes % 8);
2692 if (n_bytes % 16 >= 8)
2693 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2694 if (n_bytes % 8 != 0)
2695 output_asm_insn ("ldd 0(%1),%6", operands);
2696 if (n_bytes % 16 >= 8)
2697 output_asm_insn ("std,ma %3,8(%0)", operands);
2698 if (n_bytes % 8 != 0)
2699 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2704 /* Pre-adjust the loop counter. */
2705 operands[4] = GEN_INT (n_bytes - 8);
2706 output_asm_insn ("ldi %4,%2", operands);
2709 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2710 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2711 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2712 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2713 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2715 /* Handle the residual. There could be up to 7 bytes of
2716 residual to copy! */
2717 if (n_bytes % 8 != 0)
2719 operands[4] = GEN_INT (n_bytes % 4);
2720 if (n_bytes % 8 >= 4)
2721 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2722 if (n_bytes % 4 != 0)
2723 output_asm_insn ("ldw 0(%1),%6", operands);
2724 if (n_bytes % 8 >= 4)
2725 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2726 if (n_bytes % 4 != 0)
2727 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2732 /* Pre-adjust the loop counter. */
2733 operands[4] = GEN_INT (n_bytes - 4);
2734 output_asm_insn ("ldi %4,%2", operands);
2737 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2738 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2739 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2740 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2741 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2743 /* Handle the residual. */
2744 if (n_bytes % 4 != 0)
2746 if (n_bytes % 4 >= 2)
2747 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2748 if (n_bytes % 2 != 0)
2749 output_asm_insn ("ldb 0(%1),%6", operands);
2750 if (n_bytes % 4 >= 2)
2751 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2752 if (n_bytes % 2 != 0)
2753 output_asm_insn ("stb %6,0(%0)", operands);
2758 /* Pre-adjust the loop counter. */
2759 operands[4] = GEN_INT (n_bytes - 2);
2760 output_asm_insn ("ldi %4,%2", operands);
2763 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2764 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2765 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2766 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2767 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2769 /* Handle the residual. */
2770 if (n_bytes % 2 != 0)
2772 output_asm_insn ("ldb 0(%1),%3", operands);
2773 output_asm_insn ("stb %3,0(%0)", operands);
2782 /* Count the number of insns necessary to handle this block move.
2784 Basic structure is the same as emit_block_move, except that we
2785 count insns rather than emit them. */
2788 compute_movstr_length (rtx insn)
2790 rtx pat = PATTERN (insn);
2791 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2792 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2793 unsigned int n_insns = 0;
2795 /* We can't move more than four bytes at a time because the PA
2796 has no longer integer move insns. (Could use fp mem ops?) */
2797 if (align > (TARGET_64BIT ? 8 : 4))
2798 align = (TARGET_64BIT ? 8 : 4);
2800 /* The basic copying loop. */
2804 if (n_bytes % (2 * align) != 0)
2806 if ((n_bytes % (2 * align)) >= align)
2809 if ((n_bytes % align) != 0)
2813 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2817 /* Emit code to perform a block clear.
2819 OPERANDS[0] is the destination pointer as a REG, clobbered.
2820 OPERANDS[1] is a register for temporary storage.
2821 OPERANDS[2] is the size as a CONST_INT
2822 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2825 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2827 int align = INTVAL (operands[3]);
2828 unsigned long n_bytes = INTVAL (operands[2]);
2830 /* We can't clear more than a word at a time because the PA
2831 has no longer integer move insns. */
2832 if (align > (TARGET_64BIT ? 8 : 4))
2833 align = (TARGET_64BIT ? 8 : 4);
2835 /* Note that we know each loop below will execute at least twice
2836 (else we would have open-coded the copy). */
2840 /* Pre-adjust the loop counter. */
2841 operands[2] = GEN_INT (n_bytes - 16);
2842 output_asm_insn ("ldi %2,%1", operands);
2845 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2846 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2847 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2849 /* Handle the residual. There could be up to 7 bytes of
2850 residual to copy! */
2851 if (n_bytes % 16 != 0)
2853 operands[2] = GEN_INT (n_bytes % 8);
2854 if (n_bytes % 16 >= 8)
2855 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2856 if (n_bytes % 8 != 0)
2857 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2862 /* Pre-adjust the loop counter. */
2863 operands[2] = GEN_INT (n_bytes - 8);
2864 output_asm_insn ("ldi %2,%1", operands);
2867 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2868 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2869 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2871 /* Handle the residual. There could be up to 7 bytes of
2872 residual to copy! */
2873 if (n_bytes % 8 != 0)
2875 operands[2] = GEN_INT (n_bytes % 4);
2876 if (n_bytes % 8 >= 4)
2877 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2878 if (n_bytes % 4 != 0)
2879 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2884 /* Pre-adjust the loop counter. */
2885 operands[2] = GEN_INT (n_bytes - 4);
2886 output_asm_insn ("ldi %2,%1", operands);
2889 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2890 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2891 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2893 /* Handle the residual. */
2894 if (n_bytes % 4 != 0)
2896 if (n_bytes % 4 >= 2)
2897 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2898 if (n_bytes % 2 != 0)
2899 output_asm_insn ("stb %%r0,0(%0)", operands);
2904 /* Pre-adjust the loop counter. */
2905 operands[2] = GEN_INT (n_bytes - 2);
2906 output_asm_insn ("ldi %2,%1", operands);
2909 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2910 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2911 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2913 /* Handle the residual. */
2914 if (n_bytes % 2 != 0)
2915 output_asm_insn ("stb %%r0,0(%0)", operands);
2924 /* Count the number of insns necessary to handle this block move.
2926 Basic structure is the same as emit_block_move, except that we
2927 count insns rather than emit them. */
2930 compute_clrstr_length (rtx insn)
2932 rtx pat = PATTERN (insn);
2933 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2934 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2935 unsigned int n_insns = 0;
2937 /* We can't clear more than a word at a time because the PA
2938 has no longer integer move insns. */
2939 if (align > (TARGET_64BIT ? 8 : 4))
2940 align = (TARGET_64BIT ? 8 : 4);
2942 /* The basic loop. */
2946 if (n_bytes % (2 * align) != 0)
2948 if ((n_bytes % (2 * align)) >= align)
2951 if ((n_bytes % align) != 0)
2955 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2961 output_and (rtx *operands)
2963 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2965 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2966 int ls0, ls1, ms0, p, len;
2968 for (ls0 = 0; ls0 < 32; ls0++)
2969 if ((mask & (1 << ls0)) == 0)
2972 for (ls1 = ls0; ls1 < 32; ls1++)
2973 if ((mask & (1 << ls1)) != 0)
2976 for (ms0 = ls1; ms0 < 32; ms0++)
2977 if ((mask & (1 << ms0)) == 0)
2990 operands[2] = GEN_INT (len);
2991 return "{extru|extrw,u} %1,31,%2,%0";
2995 /* We could use this `depi' for the case above as well, but `depi'
2996 requires one more register file access than an `extru'. */
3001 operands[2] = GEN_INT (p);
3002 operands[3] = GEN_INT (len);
3003 return "{depi|depwi} 0,%2,%3,%0";
3007 return "and %1,%2,%0";
3010 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3011 storing the result in operands[0]. */
3013 output_64bit_and (rtx *operands)
3015 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3017 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3018 int ls0, ls1, ms0, p, len;
3020 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3021 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3024 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3025 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3028 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3029 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3032 if (ms0 != HOST_BITS_PER_WIDE_INT)
3035 if (ls1 == HOST_BITS_PER_WIDE_INT)
3042 operands[2] = GEN_INT (len);
3043 return "extrd,u %1,63,%2,%0";
3047 /* We could use this `depi' for the case above as well, but `depi'
3048 requires one more register file access than an `extru'. */
3053 operands[2] = GEN_INT (p);
3054 operands[3] = GEN_INT (len);
3055 return "depdi 0,%2,%3,%0";
3059 return "and %1,%2,%0";
3063 output_ior (rtx *operands)
3065 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3066 int bs0, bs1, p, len;
3068 if (INTVAL (operands[2]) == 0)
3069 return "copy %1,%0";
3071 for (bs0 = 0; bs0 < 32; bs0++)
3072 if ((mask & (1 << bs0)) != 0)
3075 for (bs1 = bs0; bs1 < 32; bs1++)
3076 if ((mask & (1 << bs1)) == 0)
3079 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3085 operands[2] = GEN_INT (p);
3086 operands[3] = GEN_INT (len);
3087 return "{depi|depwi} -1,%2,%3,%0";
3090 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3091 storing the result in operands[0]. */
3093 output_64bit_ior (rtx *operands)
3095 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3096 int bs0, bs1, p, len;
3098 if (INTVAL (operands[2]) == 0)
3099 return "copy %1,%0";
3101 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3102 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3105 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3106 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3109 if (bs1 != HOST_BITS_PER_WIDE_INT
3110 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3116 operands[2] = GEN_INT (p);
3117 operands[3] = GEN_INT (len);
3118 return "depdi -1,%2,%3,%0";
3121 /* Target hook for assembling integer objects. This code handles
3122 aligned SI and DI integers specially, since function references must
3123 be preceded by P%. */
3126 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3128 if (size == UNITS_PER_WORD && aligned_p
3129 && function_label_operand (x, VOIDmode))
3131 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3132 output_addr_const (asm_out_file, x);
3133 fputc ('\n', asm_out_file);
3136 return default_assemble_integer (x, size, aligned_p);
3139 /* Output an ascii string. */
3141 output_ascii (FILE *file, const char *p, int size)
3145 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3147 /* The HP assembler can only take strings of 256 characters at one
3148 time. This is a limitation on input line length, *not* the
3149 length of the string. Sigh. Even worse, it seems that the
3150 restriction is in number of input characters (see \xnn &
3151 \whatever). So we have to do this very carefully. */
3153 fputs ("\t.STRING \"", file);
3156 for (i = 0; i < size; i += 4)
3160 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3162 register unsigned int c = (unsigned char) p[i + io];
3164 if (c == '\"' || c == '\\')
3165 partial_output[co++] = '\\';
3166 if (c >= ' ' && c < 0177)
3167 partial_output[co++] = c;
3171 partial_output[co++] = '\\';
3172 partial_output[co++] = 'x';
3173 hexd = c / 16 - 0 + '0';
3175 hexd -= '9' - 'a' + 1;
3176 partial_output[co++] = hexd;
3177 hexd = c % 16 - 0 + '0';
3179 hexd -= '9' - 'a' + 1;
3180 partial_output[co++] = hexd;
3183 if (chars_output + co > 243)
3185 fputs ("\"\n\t.STRING \"", file);
3188 fwrite (partial_output, 1, (size_t) co, file);
3192 fputs ("\"\n", file);
3195 /* Try to rewrite floating point comparisons & branches to avoid
3196 useless add,tr insns.
3198 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3199 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3200 first attempt to remove useless add,tr insns. It is zero
3201 for the second pass as reorg sometimes leaves bogus REG_DEAD
3204 When CHECK_NOTES is zero we can only eliminate add,tr insns
3205 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3208 remove_useless_addtr_insns (int check_notes)
3211 static int pass = 0;
3213 /* This is fairly cheap, so always run it when optimizing. */
3217 int fbranch_count = 0;
3219 /* Walk all the insns in this function looking for fcmp & fbranch
3220 instructions. Keep track of how many of each we find. */
3221 for (insn = get_insns (); insn; insn = next_insn (insn))
3225 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3226 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3229 tmp = PATTERN (insn);
3231 /* It must be a set. */
3232 if (GET_CODE (tmp) != SET)
3235 /* If the destination is CCFP, then we've found an fcmp insn. */
3236 tmp = SET_DEST (tmp);
3237 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3243 tmp = PATTERN (insn);
3244 /* If this is an fbranch instruction, bump the fbranch counter. */
3245 if (GET_CODE (tmp) == SET
3246 && SET_DEST (tmp) == pc_rtx
3247 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3248 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3249 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3250 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3258 /* Find all floating point compare + branch insns. If possible,
3259 reverse the comparison & the branch to avoid add,tr insns. */
3260 for (insn = get_insns (); insn; insn = next_insn (insn))
3264 /* Ignore anything that isn't an INSN. */
3265 if (GET_CODE (insn) != INSN)
3268 tmp = PATTERN (insn);
3270 /* It must be a set. */
3271 if (GET_CODE (tmp) != SET)
3274 /* The destination must be CCFP, which is register zero. */
3275 tmp = SET_DEST (tmp);
3276 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3279 /* INSN should be a set of CCFP.
3281 See if the result of this insn is used in a reversed FP
3282 conditional branch. If so, reverse our condition and
3283 the branch. Doing so avoids useless add,tr insns. */
3284 next = next_insn (insn);
3287 /* Jumps, calls and labels stop our search. */
3288 if (GET_CODE (next) == JUMP_INSN
3289 || GET_CODE (next) == CALL_INSN
3290 || GET_CODE (next) == CODE_LABEL)
3293 /* As does another fcmp insn. */
3294 if (GET_CODE (next) == INSN
3295 && GET_CODE (PATTERN (next)) == SET
3296 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3297 && REGNO (SET_DEST (PATTERN (next))) == 0)
3300 next = next_insn (next);
3303 /* Is NEXT_INSN a branch? */
3305 && GET_CODE (next) == JUMP_INSN)
3307 rtx pattern = PATTERN (next);
3309 /* If it a reversed fp conditional branch (eg uses add,tr)
3310 and CCFP dies, then reverse our conditional and the branch
3311 to avoid the add,tr. */
3312 if (GET_CODE (pattern) == SET
3313 && SET_DEST (pattern) == pc_rtx
3314 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3315 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3316 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3317 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3318 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3319 && (fcmp_count == fbranch_count
3321 && find_regno_note (next, REG_DEAD, 0))))
3323 /* Reverse the branch. */
3324 tmp = XEXP (SET_SRC (pattern), 1);
3325 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3326 XEXP (SET_SRC (pattern), 2) = tmp;
3327 INSN_CODE (next) = -1;
3329 /* Reverse our condition. */
3330 tmp = PATTERN (insn);
3331 PUT_CODE (XEXP (tmp, 1),
3332 (reverse_condition_maybe_unordered
3333 (GET_CODE (XEXP (tmp, 1)))));
3343 /* You may have trouble believing this, but this is the 32 bit HP-PA
3348 Variable arguments (optional; any number may be allocated)
3350 SP-(4*(N+9)) arg word N
3355 Fixed arguments (must be allocated; may remain unused)
3364 SP-32 External Data Pointer (DP)
3366 SP-24 External/stub RP (RP')
3370 SP-8 Calling Stub RP (RP'')
3375 SP-0 Stack Pointer (points to next available address)
3379 /* This function saves registers as follows. Registers marked with ' are
3380 this function's registers (as opposed to the previous function's).
3381 If a frame_pointer isn't needed, r4 is saved as a general register;
3382 the space for the frame pointer is still allocated, though, to keep
3388 SP (FP') Previous FP
3389 SP + 4 Alignment filler (sigh)
3390 SP + 8 Space for locals reserved here.
3394 SP + n All call saved register used.
3398 SP + o All call saved fp registers used.
3402 SP + p (SP') points to next available address.
3406 /* Global variables set by output_function_prologue(). */
3407 /* Size of frame. Need to know this to emit return insns from
3409 static HOST_WIDE_INT actual_fsize, local_fsize;
3410 static int save_fregs;
3412 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3413 Handle case where DISP > 8k by using the add_high_const patterns.
3415 Note in DISP > 8k case, we will leave the high part of the address
3416 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3419 store_reg (int reg, HOST_WIDE_INT disp, int base)
3421 rtx insn, dest, src, basereg;
3423 src = gen_rtx_REG (word_mode, reg);
3424 basereg = gen_rtx_REG (Pmode, base);
3425 if (VAL_14_BITS_P (disp))
3427 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3428 insn = emit_move_insn (dest, src);
3430 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3432 rtx delta = GEN_INT (disp);
3433 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3435 emit_move_insn (tmpreg, delta);
3436 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3437 dest = gen_rtx_MEM (word_mode, tmpreg);
3438 insn = emit_move_insn (dest, src);
3442 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3443 gen_rtx_SET (VOIDmode,
3444 gen_rtx_MEM (word_mode,
3445 gen_rtx_PLUS (word_mode, basereg,
3453 rtx delta = GEN_INT (disp);
3454 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3455 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3457 emit_move_insn (tmpreg, high);
3458 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3459 insn = emit_move_insn (dest, src);
3463 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3464 gen_rtx_SET (VOIDmode,
3465 gen_rtx_MEM (word_mode,
3466 gen_rtx_PLUS (word_mode, basereg,
3474 RTX_FRAME_RELATED_P (insn) = 1;
3477 /* Emit RTL to store REG at the memory location specified by BASE and then
3478 add MOD to BASE. MOD must be <= 8k. */
3481 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3483 rtx insn, basereg, srcreg, delta;
3485 if (!VAL_14_BITS_P (mod))
3488 basereg = gen_rtx_REG (Pmode, base);
3489 srcreg = gen_rtx_REG (word_mode, reg);
3490 delta = GEN_INT (mod);
3492 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3495 RTX_FRAME_RELATED_P (insn) = 1;
3497 /* RTX_FRAME_RELATED_P must be set on each frame related set
3498 in a parallel with more than one element. Don't set
3499 RTX_FRAME_RELATED_P in the first set if reg is temporary
3500 register 1. The effect of this operation is recorded in
3501 the initial copy. */
3504 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3505 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3509 /* The first element of a PARALLEL is always processed if it is
3510 a SET. Thus, we need an expression list for this case. */
3512 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3513 gen_rtx_SET (VOIDmode, basereg,
3514 gen_rtx_PLUS (word_mode, basereg, delta)),
3520 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3521 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3522 whether to add a frame note or not.
3524 In the DISP > 8k case, we leave the high part of the address in %r1.
3525 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3528 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3532 if (VAL_14_BITS_P (disp))
3534 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3535 plus_constant (gen_rtx_REG (Pmode, base), disp));
3537 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3539 rtx basereg = gen_rtx_REG (Pmode, base);
3540 rtx delta = GEN_INT (disp);
3541 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3543 emit_move_insn (tmpreg, delta);
3544 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3545 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3549 rtx basereg = gen_rtx_REG (Pmode, base);
3550 rtx delta = GEN_INT (disp);
3551 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3553 emit_move_insn (tmpreg,
3554 gen_rtx_PLUS (Pmode, basereg,
3555 gen_rtx_HIGH (Pmode, delta)));
3556 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3557 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3560 if (DO_FRAME_NOTES && note)
3561 RTX_FRAME_RELATED_P (insn) = 1;
3565 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3570 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3571 be consistent with the rounding and size calculation done here.
3572 Change them at the same time. */
3574 /* We do our own stack alignment. First, round the size of the
3575 stack locals up to a word boundary. */
3576 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3578 /* Space for previous frame pointer + filler. If any frame is
3579 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3580 waste some space here for the sake of HP compatibility. The
3581 first slot is only used when the frame pointer is needed. */
3582 if (size || frame_pointer_needed)
3583 size += STARTING_FRAME_OFFSET;
3585 /* If the current function calls __builtin_eh_return, then we need
3586 to allocate stack space for registers that will hold data for
3587 the exception handler. */
3588 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3592 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3594 size += i * UNITS_PER_WORD;
3597 /* Account for space used by the callee general register saves. */
3598 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3599 if (regs_ever_live[i])
3600 size += UNITS_PER_WORD;
3602 /* Account for space used by the callee floating point register saves. */
3603 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3604 if (regs_ever_live[i]
3605 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3609 /* We always save both halves of the FP register, so always
3610 increment the frame size by 8 bytes. */
3614 /* If any of the floating registers are saved, account for the
3615 alignment needed for the floating point register save block. */
3618 size = (size + 7) & ~7;
3623 /* The various ABIs include space for the outgoing parameters in the
3624 size of the current function's stack frame. We don't need to align
3625 for the outgoing arguments as their alignment is set by the final
3626 rounding for the frame as a whole. */
3627 size += current_function_outgoing_args_size;
3629 /* Allocate space for the fixed frame marker. This space must be
3630 allocated for any function that makes calls or allocates
3632 if (!current_function_is_leaf || size)
3633 size += TARGET_64BIT ? 48 : 32;
3635 /* Finally, round to the preferred stack boundary. */
3636 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3637 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3640 /* Generate the assembly code for function entry. FILE is a stdio
3641 stream to output the code to. SIZE is an int: how many units of
3642 temporary storage to allocate.
3644 Refer to the array `regs_ever_live' to determine which registers to
3645 save; `regs_ever_live[I]' is nonzero if register number I is ever
3646 used in the function. This function is responsible for knowing
3647 which registers should not be saved even if used. */
3649 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3650 of memory. If any fpu reg is used in the function, we allocate
3651 such a block here, at the bottom of the frame, just in case it's needed.
3653 If this function is a leaf procedure, then we may choose not
3654 to do a "save" insn. The decision about whether or not
3655 to do this is made in regclass.c. */
3658 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3660 /* The function's label and associated .PROC must never be
3661 separated and must be output *after* any profiling declarations
3662 to avoid changing spaces/subspaces within a procedure. */
3663 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3664 fputs ("\t.PROC\n", file);
3666 /* hppa_expand_prologue does the dirty work now. We just need
3667 to output the assembler directives which denote the start
3669 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3670 if (regs_ever_live[2])
3671 fputs (",CALLS,SAVE_RP", file);
3673 fputs (",NO_CALLS", file);
3675 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3676 at the beginning of the frame and that it is used as the frame
3677 pointer for the frame. We do this because our current frame
3678 layout doesn't conform to that specified in the the HP runtime
3679 documentation and we need a way to indicate to programs such as
3680 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3681 isn't used by HP compilers but is supported by the assembler.
3682 However, SAVE_SP is supposed to indicate that the previous stack
3683 pointer has been saved in the frame marker. */
3684 if (frame_pointer_needed)
3685 fputs (",SAVE_SP", file);
3687 /* Pass on information about the number of callee register saves
3688 performed in the prologue.
3690 The compiler is supposed to pass the highest register number
3691 saved, the assembler then has to adjust that number before
3692 entering it into the unwind descriptor (to account for any
3693 caller saved registers with lower register numbers than the
3694 first callee saved register). */
3696 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3699 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3701 fputs ("\n\t.ENTRY\n", file);
3703 remove_useless_addtr_insns (0);
3707 hppa_expand_prologue (void)
3709 int merge_sp_adjust_with_store = 0;
3710 HOST_WIDE_INT size = get_frame_size ();
3711 HOST_WIDE_INT offset;
3719 /* Compute total size for frame pointer, filler, locals and rounding to
3720 the next word boundary. Similar code appears in compute_frame_size
3721 and must be changed in tandem with this code. */
3722 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3723 if (local_fsize || frame_pointer_needed)
3724 local_fsize += STARTING_FRAME_OFFSET;
3726 actual_fsize = compute_frame_size (size, &save_fregs);
3728 /* Compute a few things we will use often. */
3729 tmpreg = gen_rtx_REG (word_mode, 1);
3731 /* Save RP first. The calling conventions manual states RP will
3732 always be stored into the caller's frame at sp - 20 or sp - 16
3733 depending on which ABI is in use. */
3734 if (regs_ever_live[2] || current_function_calls_eh_return)
3735 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3737 /* Allocate the local frame and set up the frame pointer if needed. */
3738 if (actual_fsize != 0)
3740 if (frame_pointer_needed)
3742 /* Copy the old frame pointer temporarily into %r1. Set up the
3743 new stack pointer, then store away the saved old frame pointer
3744 into the stack at sp and at the same time update the stack
3745 pointer by actual_fsize bytes. Two versions, first
3746 handles small (<8k) frames. The second handles large (>=8k)
3748 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3751 /* We need to record the frame pointer save here since the
3752 new frame pointer is set in the following insn. */
3753 RTX_FRAME_RELATED_P (insn) = 1;
3755 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3756 gen_rtx_SET (VOIDmode,
3757 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3762 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3764 RTX_FRAME_RELATED_P (insn) = 1;
3766 if (VAL_14_BITS_P (actual_fsize))
3767 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3770 /* It is incorrect to store the saved frame pointer at *sp,
3771 then increment sp (writes beyond the current stack boundary).
3773 So instead use stwm to store at *sp and post-increment the
3774 stack pointer as an atomic operation. Then increment sp to
3775 finish allocating the new frame. */
3776 HOST_WIDE_INT adjust1 = 8192 - 64;
3777 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3779 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3780 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3784 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3785 we need to store the previous stack pointer (frame pointer)
3786 into the frame marker on targets that use the HP unwind
3787 library. This allows the HP unwind library to be used to
3788 unwind GCC frames. However, we are not fully compatible
3789 with the HP library because our frame layout differs from
3790 that specified in the HP runtime specification.
3792 We don't want a frame note on this instruction as the frame
3793 marker moves during dynamic stack allocation.
3795 This instruction also serves as a blockage to prevent
3796 register spills from being scheduled before the stack
3797 pointer is raised. This is necessary as we store
3798 registers using the frame pointer as a base register,
3799 and the frame pointer is set before sp is raised. */
3800 if (TARGET_HPUX_UNWIND_LIBRARY)
3802 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3803 GEN_INT (TARGET_64BIT ? -8 : -4));
3805 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3809 emit_insn (gen_blockage ());
3811 /* no frame pointer needed. */
3814 /* In some cases we can perform the first callee register save
3815 and allocating the stack frame at the same time. If so, just
3816 make a note of it and defer allocating the frame until saving
3817 the callee registers. */
3818 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3819 merge_sp_adjust_with_store = 1;
3820 /* Can not optimize. Adjust the stack frame by actual_fsize
3823 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3828 /* Normal register save.
3830 Do not save the frame pointer in the frame_pointer_needed case. It
3831 was done earlier. */
3832 if (frame_pointer_needed)
3834 offset = local_fsize;
3836 /* Saving the EH return data registers in the frame is the simplest
3837 way to get the frame unwind information emitted. We put them
3838 just before the general registers. */
3839 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3841 unsigned int i, regno;
3845 regno = EH_RETURN_DATA_REGNO (i);
3846 if (regno == INVALID_REGNUM)
3849 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3850 offset += UNITS_PER_WORD;
3854 for (i = 18; i >= 4; i--)
3855 if (regs_ever_live[i] && ! call_used_regs[i])
3857 store_reg (i, offset, FRAME_POINTER_REGNUM);
3858 offset += UNITS_PER_WORD;
3861 /* Account for %r3 which is saved in a special place. */
3864 /* No frame pointer needed. */
3867 offset = local_fsize - actual_fsize;
3869 /* Saving the EH return data registers in the frame is the simplest
3870 way to get the frame unwind information emitted. */
3871 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3873 unsigned int i, regno;
3877 regno = EH_RETURN_DATA_REGNO (i);
3878 if (regno == INVALID_REGNUM)
3881 /* If merge_sp_adjust_with_store is nonzero, then we can
3882 optimize the first save. */
3883 if (merge_sp_adjust_with_store)
3885 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3886 merge_sp_adjust_with_store = 0;
3889 store_reg (regno, offset, STACK_POINTER_REGNUM);
3890 offset += UNITS_PER_WORD;
3894 for (i = 18; i >= 3; i--)
3895 if (regs_ever_live[i] && ! call_used_regs[i])
3897 /* If merge_sp_adjust_with_store is nonzero, then we can
3898 optimize the first GR save. */
3899 if (merge_sp_adjust_with_store)
3901 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3902 merge_sp_adjust_with_store = 0;
3905 store_reg (i, offset, STACK_POINTER_REGNUM);
3906 offset += UNITS_PER_WORD;
3910 /* If we wanted to merge the SP adjustment with a GR save, but we never
3911 did any GR saves, then just emit the adjustment here. */
3912 if (merge_sp_adjust_with_store)
3913 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3917 /* The hppa calling conventions say that %r19, the pic offset
3918 register, is saved at sp - 32 (in this function's frame)
3919 when generating PIC code. FIXME: What is the correct thing
3920 to do for functions which make no calls and allocate no
3921 frame? Do we need to allocate a frame, or can we just omit
3922 the save? For now we'll just omit the save.
3924 We don't want a note on this insn as the frame marker can
3925 move if there is a dynamic stack allocation. */
3926 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3928 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3930 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3934 /* Align pointer properly (doubleword boundary). */
3935 offset = (offset + 7) & ~7;
3937 /* Floating point register store. */
3942 /* First get the frame or stack pointer to the start of the FP register
3944 if (frame_pointer_needed)
3946 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3947 base = frame_pointer_rtx;
3951 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3952 base = stack_pointer_rtx;
3955 /* Now actually save the FP registers. */
3956 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3958 if (regs_ever_live[i]
3959 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3961 rtx addr, insn, reg;
3962 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3963 reg = gen_rtx_REG (DFmode, i);
3964 insn = emit_move_insn (addr, reg);
3967 RTX_FRAME_RELATED_P (insn) = 1;
3970 rtx mem = gen_rtx_MEM (DFmode,
3971 plus_constant (base, offset));
3973 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3974 gen_rtx_SET (VOIDmode, mem, reg),
3979 rtx meml = gen_rtx_MEM (SFmode,
3980 plus_constant (base, offset));
3981 rtx memr = gen_rtx_MEM (SFmode,
3982 plus_constant (base, offset + 4));
3983 rtx regl = gen_rtx_REG (SFmode, i);
3984 rtx regr = gen_rtx_REG (SFmode, i + 1);
3985 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3986 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3989 RTX_FRAME_RELATED_P (setl) = 1;
3990 RTX_FRAME_RELATED_P (setr) = 1;
3991 vec = gen_rtvec (2, setl, setr);
3993 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3994 gen_rtx_SEQUENCE (VOIDmode, vec),
3998 offset += GET_MODE_SIZE (DFmode);
4005 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4006 Handle case where DISP > 8k by using the add_high_const patterns. */
4009 load_reg (int reg, HOST_WIDE_INT disp, int base)
4011 rtx dest = gen_rtx_REG (word_mode, reg);
4012 rtx basereg = gen_rtx_REG (Pmode, base);
4015 if (VAL_14_BITS_P (disp))
4016 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4017 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4019 rtx delta = GEN_INT (disp);
4020 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4022 emit_move_insn (tmpreg, delta);
4023 if (TARGET_DISABLE_INDEXING)
4025 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4026 src = gen_rtx_MEM (word_mode, tmpreg);
4029 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4033 rtx delta = GEN_INT (disp);
4034 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4035 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4037 emit_move_insn (tmpreg, high);
4038 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4041 emit_move_insn (dest, src);
4044 /* Update the total code bytes output to the text section. */
4047 update_total_code_bytes (int nbytes)
4049 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4050 && !IN_NAMED_SECTION_P (cfun->decl))
4052 if (INSN_ADDRESSES_SET_P ())
4054 unsigned long old_total = total_code_bytes;
4056 total_code_bytes += nbytes;
4058 /* Be prepared to handle overflows. */
4059 if (old_total > total_code_bytes)
4060 total_code_bytes = -1;
4063 total_code_bytes = -1;
4067 /* This function generates the assembly code for function exit.
4068 Args are as for output_function_prologue ().
4070 The function epilogue should not depend on the current stack
4071 pointer! It should use the frame pointer only. This is mandatory
4072 because of alloca; we also take advantage of it to omit stack
4073 adjustments before returning. */
4076 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4078 rtx insn = get_last_insn ();
4082 /* hppa_expand_epilogue does the dirty work now. We just need
4083 to output the assembler directives which denote the end
4086 To make debuggers happy, emit a nop if the epilogue was completely
4087 eliminated due to a volatile call as the last insn in the
4088 current function. That way the return address (in %r2) will
4089 always point to a valid instruction in the current function. */
4091 /* Get the last real insn. */
4092 if (GET_CODE (insn) == NOTE)
4093 insn = prev_real_insn (insn);
4095 /* If it is a sequence, then look inside. */
4096 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4097 insn = XVECEXP (PATTERN (insn), 0, 0);
4099 /* If insn is a CALL_INSN, then it must be a call to a volatile
4100 function (otherwise there would be epilogue insns). */
4101 if (insn && GET_CODE (insn) == CALL_INSN)
4103 fputs ("\tnop\n", file);
4107 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4109 if (INSN_ADDRESSES_SET_P ())
4111 insn = get_last_nonnote_insn ();
4112 last_address += INSN_ADDRESSES (INSN_UID (insn));
4114 last_address += insn_default_length (insn);
4115 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4116 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4119 /* Finally, update the total number of code bytes output so far. */
4120 update_total_code_bytes (last_address);
4124 hppa_expand_epilogue (void)
4127 HOST_WIDE_INT offset;
4128 HOST_WIDE_INT ret_off = 0;
4130 int merge_sp_adjust_with_load = 0;
4132 /* We will use this often. */
4133 tmpreg = gen_rtx_REG (word_mode, 1);
4135 /* Try to restore RP early to avoid load/use interlocks when
4136 RP gets used in the return (bv) instruction. This appears to still
4137 be necessary even when we schedule the prologue and epilogue. */
4138 if (regs_ever_live [2] || current_function_calls_eh_return)
4140 ret_off = TARGET_64BIT ? -16 : -20;
4141 if (frame_pointer_needed)
4143 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4148 /* No frame pointer, and stack is smaller than 8k. */
4149 if (VAL_14_BITS_P (ret_off - actual_fsize))
4151 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4157 /* General register restores. */
4158 if (frame_pointer_needed)
4160 offset = local_fsize;
4162 /* If the current function calls __builtin_eh_return, then we need
4163 to restore the saved EH data registers. */
4164 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4166 unsigned int i, regno;
4170 regno = EH_RETURN_DATA_REGNO (i);
4171 if (regno == INVALID_REGNUM)
4174 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4175 offset += UNITS_PER_WORD;
4179 for (i = 18; i >= 4; i--)
4180 if (regs_ever_live[i] && ! call_used_regs[i])
4182 load_reg (i, offset, FRAME_POINTER_REGNUM);
4183 offset += UNITS_PER_WORD;
4188 offset = local_fsize - actual_fsize;
4190 /* If the current function calls __builtin_eh_return, then we need
4191 to restore the saved EH data registers. */
4192 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4194 unsigned int i, regno;
4198 regno = EH_RETURN_DATA_REGNO (i);
4199 if (regno == INVALID_REGNUM)
4202 /* Only for the first load.
4203 merge_sp_adjust_with_load holds the register load
4204 with which we will merge the sp adjustment. */
4205 if (merge_sp_adjust_with_load == 0
4207 && VAL_14_BITS_P (-actual_fsize))
4208 merge_sp_adjust_with_load = regno;
4210 load_reg (regno, offset, STACK_POINTER_REGNUM);
4211 offset += UNITS_PER_WORD;
4215 for (i = 18; i >= 3; i--)
4217 if (regs_ever_live[i] && ! call_used_regs[i])
4219 /* Only for the first load.
4220 merge_sp_adjust_with_load holds the register load
4221 with which we will merge the sp adjustment. */
4222 if (merge_sp_adjust_with_load == 0
4224 && VAL_14_BITS_P (-actual_fsize))
4225 merge_sp_adjust_with_load = i;
4227 load_reg (i, offset, STACK_POINTER_REGNUM);
4228 offset += UNITS_PER_WORD;
4233 /* Align pointer properly (doubleword boundary). */
4234 offset = (offset + 7) & ~7;
4236 /* FP register restores. */
4239 /* Adjust the register to index off of. */
4240 if (frame_pointer_needed)
4241 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4243 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4245 /* Actually do the restores now. */
4246 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4247 if (regs_ever_live[i]
4248 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4250 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4251 rtx dest = gen_rtx_REG (DFmode, i);
4252 emit_move_insn (dest, src);
4256 /* Emit a blockage insn here to keep these insns from being moved to
4257 an earlier spot in the epilogue, or into the main instruction stream.
4259 This is necessary as we must not cut the stack back before all the
4260 restores are finished. */
4261 emit_insn (gen_blockage ());
4263 /* Reset stack pointer (and possibly frame pointer). The stack
4264 pointer is initially set to fp + 64 to avoid a race condition. */
4265 if (frame_pointer_needed)
4267 rtx delta = GEN_INT (-64);
4269 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4270 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4272 /* If we were deferring a callee register restore, do it now. */
4273 else if (merge_sp_adjust_with_load)
4275 rtx delta = GEN_INT (-actual_fsize);
4276 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4278 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4280 else if (actual_fsize != 0)
4281 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4284 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4285 frame greater than 8k), do so now. */
4287 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4289 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4291 rtx sa = EH_RETURN_STACKADJ_RTX;
4293 emit_insn (gen_blockage ());
4294 emit_insn (TARGET_64BIT
4295 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4296 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4301 hppa_pic_save_rtx (void)
4303 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4307 hppa_profile_hook (int label_no)
4309 /* We use SImode for the address of the function in both 32 and
4310 64-bit code to avoid having to provide DImode versions of the
4311 lcla2 and load_offset_label_address insn patterns. */
4312 rtx reg = gen_reg_rtx (SImode);
4313 rtx label_rtx = gen_label_rtx ();
4314 rtx begin_label_rtx, call_insn;
4315 char begin_label_name[16];
4317 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4319 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4322 emit_move_insn (arg_pointer_rtx,
4323 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4326 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4328 /* The address of the function is loaded into %r25 with a instruction-
4329 relative sequence that avoids the use of relocations. The sequence
4330 is split so that the load_offset_label_address instruction can
4331 occupy the delay slot of the call to _mcount. */
4333 emit_insn (gen_lcla2 (reg, label_rtx));
4335 emit_insn (gen_lcla1 (reg, label_rtx));
4337 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4338 reg, begin_label_rtx, label_rtx));
4340 #ifndef NO_PROFILE_COUNTERS
4342 rtx count_label_rtx, addr, r24;
4343 char count_label_name[16];
4345 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4346 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4348 addr = force_reg (Pmode, count_label_rtx);
4349 r24 = gen_rtx_REG (Pmode, 24);
4350 emit_move_insn (r24, addr);
4353 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4354 gen_rtx_SYMBOL_REF (Pmode,
4356 GEN_INT (TARGET_64BIT ? 24 : 12)));
4358 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4363 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4364 gen_rtx_SYMBOL_REF (Pmode,
4366 GEN_INT (TARGET_64BIT ? 16 : 8)));
4370 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4371 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4373 /* Indicate the _mcount call cannot throw, nor will it execute a
4375 REG_NOTES (call_insn)
4376 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4379 /* Fetch the return address for the frame COUNT steps up from
4380 the current frame, after the prologue. FRAMEADDR is the
4381 frame pointer of the COUNT frame.
4383 We want to ignore any export stub remnants here. To handle this,
4384 we examine the code at the return address, and if it is an export
4385 stub, we return a memory rtx for the stub return address stored
4388 The value returned is used in two different ways:
4390 1. To find a function's caller.
4392 2. To change the return address for a function.
4394 This function handles most instances of case 1; however, it will
4395 fail if there are two levels of stubs to execute on the return
4396 path. The only way I believe that can happen is if the return value
4397 needs a parameter relocation, which never happens for C code.
4399 This function handles most instances of case 2; however, it will
4400 fail if we did not originally have stub code on the return path
4401 but will need stub code on the new return path. This can happen if
4402 the caller & callee are both in the main program, but the new
4403 return location is in a shared library. */
4406 return_addr_rtx (int count, rtx frameaddr)
4416 rp = get_hard_reg_initial_val (Pmode, 2);
4418 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4421 saved_rp = gen_reg_rtx (Pmode);
4422 emit_move_insn (saved_rp, rp);
4424 /* Get pointer to the instruction stream. We have to mask out the
4425 privilege level from the two low order bits of the return address
4426 pointer here so that ins will point to the start of the first
4427 instruction that would have been executed if we returned. */
4428 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4429 label = gen_label_rtx ();
4431 /* Check the instruction stream at the normal return address for the
4434 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4435 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4436 0x00011820 | stub+16: mtsp r1,sr0
4437 0xe0400002 | stub+20: be,n 0(sr0,rp)
4439 If it is an export stub, than our return address is really in
4442 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4443 NULL_RTX, SImode, 1);
4444 emit_jump_insn (gen_bne (label));
4446 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4447 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4448 emit_jump_insn (gen_bne (label));
4450 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4451 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4452 emit_jump_insn (gen_bne (label));
4454 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4455 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4457 /* If there is no export stub then just use the value saved from
4458 the return pointer register. */
4460 emit_jump_insn (gen_bne (label));
4462 /* Here we know that our return address points to an export
4463 stub. We don't want to return the address of the export stub,
4464 but rather the return address of the export stub. That return
4465 address is stored at -24[frameaddr]. */
4467 emit_move_insn (saved_rp,
4469 memory_address (Pmode,
4470 plus_constant (frameaddr,
4477 /* This is only valid once reload has completed because it depends on
4478 knowing exactly how much (if any) frame there is and...
4480 It's only valid if there is no frame marker to de-allocate and...
4482 It's only valid if %r2 hasn't been saved into the caller's frame
4483 (we're not profiling and %r2 isn't live anywhere). */
4485 hppa_can_use_return_insn_p (void)
4487 return (reload_completed
4488 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4489 && ! regs_ever_live[2]
4490 && ! frame_pointer_needed);
4494 emit_bcond_fp (enum rtx_code code, rtx operand0)
4496 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4497 gen_rtx_IF_THEN_ELSE (VOIDmode,
4498 gen_rtx_fmt_ee (code,
4500 gen_rtx_REG (CCFPmode, 0),
4502 gen_rtx_LABEL_REF (VOIDmode, operand0),
4508 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4510 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4511 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4514 /* Adjust the cost of a scheduling dependency. Return the new cost of
4515 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4518 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4520 enum attr_type attr_type;
4522 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4523 true dependencies as they are described with bypasses now. */
4524 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4527 if (! recog_memoized (insn))
4530 attr_type = get_attr_type (insn);
4532 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4534 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4537 if (attr_type == TYPE_FPLOAD)
4539 rtx pat = PATTERN (insn);
4540 rtx dep_pat = PATTERN (dep_insn);
4541 if (GET_CODE (pat) == PARALLEL)
4543 /* This happens for the fldXs,mb patterns. */
4544 pat = XVECEXP (pat, 0, 0);
4546 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4547 /* If this happens, we have to extend this to schedule
4548 optimally. Return 0 for now. */
4551 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4553 if (! recog_memoized (dep_insn))
4555 switch (get_attr_type (dep_insn))
4562 case TYPE_FPSQRTSGL:
4563 case TYPE_FPSQRTDBL:
4564 /* A fpload can't be issued until one cycle before a
4565 preceding arithmetic operation has finished if
4566 the target of the fpload is any of the sources
4567 (or destination) of the arithmetic operation. */
4568 return insn_default_latency (dep_insn) - 1;
4575 else if (attr_type == TYPE_FPALU)
4577 rtx pat = PATTERN (insn);
4578 rtx dep_pat = PATTERN (dep_insn);
4579 if (GET_CODE (pat) == PARALLEL)
4581 /* This happens for the fldXs,mb patterns. */
4582 pat = XVECEXP (pat, 0, 0);
4584 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4585 /* If this happens, we have to extend this to schedule
4586 optimally. Return 0 for now. */
4589 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4591 if (! recog_memoized (dep_insn))
4593 switch (get_attr_type (dep_insn))
4597 case TYPE_FPSQRTSGL:
4598 case TYPE_FPSQRTDBL:
4599 /* An ALU flop can't be issued until two cycles before a
4600 preceding divide or sqrt operation has finished if
4601 the target of the ALU flop is any of the sources
4602 (or destination) of the divide or sqrt operation. */
4603 return insn_default_latency (dep_insn) - 2;
4611 /* For other anti dependencies, the cost is 0. */
4614 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4616 /* Output dependency; DEP_INSN writes a register that INSN writes some
4618 if (attr_type == TYPE_FPLOAD)
4620 rtx pat = PATTERN (insn);
4621 rtx dep_pat = PATTERN (dep_insn);
4622 if (GET_CODE (pat) == PARALLEL)
4624 /* This happens for the fldXs,mb patterns. */
4625 pat = XVECEXP (pat, 0, 0);
4627 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4628 /* If this happens, we have to extend this to schedule
4629 optimally. Return 0 for now. */
4632 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4634 if (! recog_memoized (dep_insn))
4636 switch (get_attr_type (dep_insn))
4643 case TYPE_FPSQRTSGL:
4644 case TYPE_FPSQRTDBL:
4645 /* A fpload can't be issued until one cycle before a
4646 preceding arithmetic operation has finished if
4647 the target of the fpload is the destination of the
4648 arithmetic operation.
4650 Exception: For PA7100LC, PA7200 and PA7300, the cost
4651 is 3 cycles, unless they bundle together. We also
4652 pay the penalty if the second insn is a fpload. */
4653 return insn_default_latency (dep_insn) - 1;
4660 else if (attr_type == TYPE_FPALU)
4662 rtx pat = PATTERN (insn);
4663 rtx dep_pat = PATTERN (dep_insn);
4664 if (GET_CODE (pat) == PARALLEL)
4666 /* This happens for the fldXs,mb patterns. */
4667 pat = XVECEXP (pat, 0, 0);
4669 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4670 /* If this happens, we have to extend this to schedule
4671 optimally. Return 0 for now. */
4674 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4676 if (! recog_memoized (dep_insn))
4678 switch (get_attr_type (dep_insn))
4682 case TYPE_FPSQRTSGL:
4683 case TYPE_FPSQRTDBL:
4684 /* An ALU flop can't be issued until two cycles before a
4685 preceding divide or sqrt operation has finished if
4686 the target of the ALU flop is also the target of
4687 the divide or sqrt operation. */
4688 return insn_default_latency (dep_insn) - 2;
4696 /* For other output dependencies, the cost is 0. */
4703 /* Adjust scheduling priorities. We use this to try and keep addil
4704 and the next use of %r1 close together. */
4706 pa_adjust_priority (rtx insn, int priority)
4708 rtx set = single_set (insn);
4712 src = SET_SRC (set);
4713 dest = SET_DEST (set);
4714 if (GET_CODE (src) == LO_SUM
4715 && symbolic_operand (XEXP (src, 1), VOIDmode)
4716 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4719 else if (GET_CODE (src) == MEM
4720 && GET_CODE (XEXP (src, 0)) == LO_SUM
4721 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4722 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4725 else if (GET_CODE (dest) == MEM
4726 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4727 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4728 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4734 /* The 700 can only issue a single insn at a time.
4735 The 7XXX processors can issue two insns at a time.
4736 The 8000 can issue 4 insns at a time. */
4738 pa_issue_rate (void)
4742 case PROCESSOR_700: return 1;
4743 case PROCESSOR_7100: return 2;
4744 case PROCESSOR_7100LC: return 2;
4745 case PROCESSOR_7200: return 2;
4746 case PROCESSOR_7300: return 2;
4747 case PROCESSOR_8000: return 4;
4756 /* Return any length adjustment needed by INSN which already has its length
4757 computed as LENGTH. Return zero if no adjustment is necessary.
4759 For the PA: function calls, millicode calls, and backwards short
4760 conditional branches with unfilled delay slots need an adjustment by +1
4761 (to account for the NOP which will be inserted into the instruction stream).
4763 Also compute the length of an inline block move here as it is too
4764 complicated to express as a length attribute in pa.md. */
4766 pa_adjust_insn_length (rtx insn, int length)
4768 rtx pat = PATTERN (insn);
4770 /* Jumps inside switch tables which have unfilled delay slots need
4772 if (GET_CODE (insn) == JUMP_INSN
4773 && GET_CODE (pat) == PARALLEL
4774 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4776 /* Millicode insn with an unfilled delay slot. */
4777 else if (GET_CODE (insn) == INSN
4778 && GET_CODE (pat) != SEQUENCE
4779 && GET_CODE (pat) != USE
4780 && GET_CODE (pat) != CLOBBER
4781 && get_attr_type (insn) == TYPE_MILLI)
4783 /* Block move pattern. */
4784 else if (GET_CODE (insn) == INSN
4785 && GET_CODE (pat) == PARALLEL
4786 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4787 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4788 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4789 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4790 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4791 return compute_movstr_length (insn) - 4;
4792 /* Block clear pattern. */
4793 else if (GET_CODE (insn) == INSN
4794 && GET_CODE (pat) == PARALLEL
4795 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4796 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4797 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4798 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4799 return compute_clrstr_length (insn) - 4;
4800 /* Conditional branch with an unfilled delay slot. */
4801 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4803 /* Adjust a short backwards conditional with an unfilled delay slot. */
4804 if (GET_CODE (pat) == SET
4806 && ! forward_branch_p (insn))
4808 else if (GET_CODE (pat) == PARALLEL
4809 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4812 /* Adjust dbra insn with short backwards conditional branch with
4813 unfilled delay slot -- only for case where counter is in a
4814 general register register. */
4815 else if (GET_CODE (pat) == PARALLEL
4816 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4817 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4818 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4820 && ! forward_branch_p (insn))
4828 /* Print operand X (an rtx) in assembler syntax to file FILE.
4829 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4830 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4833 print_operand (FILE *file, rtx x, int code)
4838 /* Output a 'nop' if there's nothing for the delay slot. */
4839 if (dbr_sequence_length () == 0)
4840 fputs ("\n\tnop", file);
4843 /* Output a nullification completer if there's nothing for the */
4844 /* delay slot or nullification is requested. */
4845 if (dbr_sequence_length () == 0 ||
4847 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4851 /* Print out the second register name of a register pair.
4852 I.e., R (6) => 7. */
4853 fputs (reg_names[REGNO (x) + 1], file);
4856 /* A register or zero. */
4858 || (x == CONST0_RTX (DFmode))
4859 || (x == CONST0_RTX (SFmode)))
4861 fputs ("%r0", file);
4867 /* A register or zero (floating point). */
4869 || (x == CONST0_RTX (DFmode))
4870 || (x == CONST0_RTX (SFmode)))
4872 fputs ("%fr0", file);
4881 xoperands[0] = XEXP (XEXP (x, 0), 0);
4882 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4883 output_global_address (file, xoperands[1], 0);
4884 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4888 case 'C': /* Plain (C)ondition */
4890 switch (GET_CODE (x))
4893 fputs ("=", file); break;
4895 fputs ("<>", file); break;
4897 fputs (">", file); break;
4899 fputs (">=", file); break;
4901 fputs (">>=", file); break;
4903 fputs (">>", file); break;
4905 fputs ("<", file); break;
4907 fputs ("<=", file); break;
4909 fputs ("<<=", file); break;
4911 fputs ("<<", file); break;
4916 case 'N': /* Condition, (N)egated */
4917 switch (GET_CODE (x))
4920 fputs ("<>", file); break;
4922 fputs ("=", file); break;
4924 fputs ("<=", file); break;
4926 fputs ("<", file); break;
4928 fputs ("<<", file); break;
4930 fputs ("<<=", file); break;
4932 fputs (">=", file); break;
4934 fputs (">", file); break;
4936 fputs (">>", file); break;
4938 fputs (">>=", file); break;
4943 /* For floating point comparisons. Note that the output
4944 predicates are the complement of the desired mode. */
4946 switch (GET_CODE (x))
4949 fputs ("!=", file); break;
4951 fputs ("=", file); break;
4953 fputs ("!>", file); break;
4955 fputs ("!>=", file); break;
4957 fputs ("!<", file); break;
4959 fputs ("!<=", file); break;
4961 fputs ("!<>", file); break;
4963 fputs (">", file); break;
4965 fputs (">=", file); break;
4967 fputs ("<", file); break;
4969 fputs ("<=", file); break;
4971 fputs ("<>", file); break;
4973 fputs ("<=>", file); break;
4975 fputs ("!<=>", file); break;
4980 case 'S': /* Condition, operands are (S)wapped. */
4981 switch (GET_CODE (x))
4984 fputs ("=", file); break;
4986 fputs ("<>", file); break;
4988 fputs ("<", file); break;
4990 fputs ("<=", file); break;
4992 fputs ("<<=", file); break;
4994 fputs ("<<", file); break;
4996 fputs (">", file); break;
4998 fputs (">=", file); break;
5000 fputs (">>=", file); break;
5002 fputs (">>", file); break;
5007 case 'B': /* Condition, (B)oth swapped and negate. */
5008 switch (GET_CODE (x))
5011 fputs ("<>", file); break;
5013 fputs ("=", file); break;
5015 fputs (">=", file); break;
5017 fputs (">", file); break;
5019 fputs (">>", file); break;
5021 fputs (">>=", file); break;
5023 fputs ("<=", file); break;
5025 fputs ("<", file); break;
5027 fputs ("<<", file); break;
5029 fputs ("<<=", file); break;
5035 if (GET_CODE (x) == CONST_INT)
5037 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5042 if (GET_CODE (x) == CONST_INT)
5044 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5049 if (GET_CODE (x) == CONST_INT)
5051 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5056 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
5058 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5063 if (GET_CODE (x) == CONST_INT)
5065 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5070 if (GET_CODE (x) == CONST_INT)
5072 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5077 if (GET_CODE (x) == CONST_INT)
5082 switch (GET_CODE (XEXP (x, 0)))
5086 if (ASSEMBLER_DIALECT == 0)
5087 fputs ("s,mb", file);
5089 fputs (",mb", file);
5093 if (ASSEMBLER_DIALECT == 0)
5094 fputs ("s,ma", file);
5096 fputs (",ma", file);
5099 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5100 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5102 if (ASSEMBLER_DIALECT == 0)
5105 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5106 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5108 if (ASSEMBLER_DIALECT == 0)
5109 fputs ("x,s", file);
5113 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5117 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5123 output_global_address (file, x, 0);
5126 output_global_address (file, x, 1);
5128 case 0: /* Don't do anything special */
5133 compute_zdepwi_operands (INTVAL (x), op);
5134 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5140 compute_zdepdi_operands (INTVAL (x), op);
5141 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5145 /* We can get here from a .vtable_inherit due to our
5146 CONSTANT_ADDRESS_P rejecting perfectly good constant
5152 if (GET_CODE (x) == REG)
5154 fputs (reg_names [REGNO (x)], file);
5155 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5161 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5162 && (REGNO (x) & 1) == 0)
5165 else if (GET_CODE (x) == MEM)
5167 int size = GET_MODE_SIZE (GET_MODE (x));
5168 rtx base = NULL_RTX;
5169 switch (GET_CODE (XEXP (x, 0)))
5173 base = XEXP (XEXP (x, 0), 0);
5174 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5178 base = XEXP (XEXP (x, 0), 0);
5179 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5182 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5183 fprintf (file, "%s(%s)",
5184 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5185 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5186 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5187 fprintf (file, "%s(%s)",
5188 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5189 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5190 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5191 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5193 /* Because the REG_POINTER flag can get lost during reload,
5194 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5195 index and base registers in the combined move patterns. */
5196 rtx base = XEXP (XEXP (x, 0), 1);
5197 rtx index = XEXP (XEXP (x, 0), 0);
5199 fprintf (file, "%s(%s)",
5200 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5203 output_address (XEXP (x, 0));
5206 output_address (XEXP (x, 0));
5211 output_addr_const (file, x);
5214 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5217 output_global_address (FILE *file, rtx x, int round_constant)
5220 /* Imagine (high (const (plus ...))). */
5221 if (GET_CODE (x) == HIGH)
5224 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5225 assemble_name (file, XSTR (x, 0));
5226 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5228 assemble_name (file, XSTR (x, 0));
5229 fputs ("-$global$", file);
5231 else if (GET_CODE (x) == CONST)
5233 const char *sep = "";
5234 int offset = 0; /* assembler wants -$global$ at end */
5235 rtx base = NULL_RTX;
5237 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
5239 base = XEXP (XEXP (x, 0), 0);
5240 output_addr_const (file, base);
5242 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
5243 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5246 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
5248 base = XEXP (XEXP (x, 0), 1);
5249 output_addr_const (file, base);
5251 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
5252 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5255 /* How bogus. The compiler is apparently responsible for
5256 rounding the constant if it uses an LR field selector.
5258 The linker and/or assembler seem a better place since
5259 they have to do this kind of thing already.
5261 If we fail to do this, HP's optimizing linker may eliminate
5262 an addil, but not update the ldw/stw/ldo instruction that
5263 uses the result of the addil. */
5265 offset = ((offset + 0x1000) & ~0x1fff);
5267 if (GET_CODE (XEXP (x, 0)) == PLUS)
5277 else if (GET_CODE (XEXP (x, 0)) == MINUS
5278 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5282 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5283 fputs ("-$global$", file);
5285 fprintf (file, "%s%d", sep, offset);
5288 output_addr_const (file, x);
5291 /* Output boilerplate text to appear at the beginning of the file.
5292 There are several possible versions. */
5293 #define aputs(x) fputs(x, asm_out_file)
5295 pa_file_start_level (void)
5298 aputs ("\t.LEVEL 2.0w\n");
5299 else if (TARGET_PA_20)
5300 aputs ("\t.LEVEL 2.0\n");
5301 else if (TARGET_PA_11)
5302 aputs ("\t.LEVEL 1.1\n");
5304 aputs ("\t.LEVEL 1.0\n");
5308 pa_file_start_space (int sortspace)
5310 aputs ("\t.SPACE $PRIVATE$");
5313 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5314 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5315 "\n\t.SPACE $TEXT$");
5318 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5319 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5323 pa_file_start_file (int want_version)
5325 if (write_symbols != NO_DEBUG)
5327 output_file_directive (asm_out_file, main_input_filename);
5329 aputs ("\t.version\t\"01.01\"\n");
5334 pa_file_start_mcount (const char *aswhat)
5337 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5341 pa_elf_file_start (void)
5343 pa_file_start_level ();
5344 pa_file_start_mcount ("ENTRY");
5345 pa_file_start_file (0);
5349 pa_som_file_start (void)
5351 pa_file_start_level ();
5352 pa_file_start_space (0);
5353 aputs ("\t.IMPORT $global$,DATA\n"
5354 "\t.IMPORT $$dyncall,MILLICODE\n");
5355 pa_file_start_mcount ("CODE");
5356 pa_file_start_file (0);
5360 pa_linux_file_start (void)
5362 pa_file_start_file (1);
5363 pa_file_start_level ();
5364 pa_file_start_mcount ("CODE");
5368 pa_hpux64_gas_file_start (void)
5370 pa_file_start_level ();
5371 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5373 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5375 pa_file_start_file (1);
5379 pa_hpux64_hpas_file_start (void)
5381 pa_file_start_level ();
5382 pa_file_start_space (1);
5383 pa_file_start_mcount ("CODE");
5384 pa_file_start_file (0);
5388 static struct deferred_plabel *
5389 get_plabel (const char *fname)
5393 /* See if we have already put this function on the list of deferred
5394 plabels. This list is generally small, so a liner search is not
5395 too ugly. If it proves too slow replace it with something faster. */
5396 for (i = 0; i < n_deferred_plabels; i++)
5397 if (strcmp (fname, deferred_plabels[i].name) == 0)
5400 /* If the deferred plabel list is empty, or this entry was not found
5401 on the list, create a new entry on the list. */
5402 if (deferred_plabels == NULL || i == n_deferred_plabels)
5404 const char *real_name;
5406 if (deferred_plabels == 0)
5407 deferred_plabels = (struct deferred_plabel *)
5408 ggc_alloc (sizeof (struct deferred_plabel));
5410 deferred_plabels = (struct deferred_plabel *)
5411 ggc_realloc (deferred_plabels,
5412 ((n_deferred_plabels + 1)
5413 * sizeof (struct deferred_plabel)));
5415 i = n_deferred_plabels++;
5416 deferred_plabels[i].internal_label = gen_label_rtx ();
5417 deferred_plabels[i].name = ggc_strdup (fname);
5419 /* Gross. We have just implicitly taken the address of this function,
5421 real_name = (*targetm.strip_name_encoding) (fname);
5422 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5425 return &deferred_plabels[i];
5429 output_deferred_plabels (void)
5432 /* If we have deferred plabels, then we need to switch into the data
5433 section and align it to a 4 byte boundary before we output the
5434 deferred plabels. */
5435 if (n_deferred_plabels)
5438 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5441 /* Now output the deferred plabels. */
5442 for (i = 0; i < n_deferred_plabels; i++)
5444 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5445 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5446 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
5447 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5451 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5452 /* Initialize optabs to point to HPUX long double emulation routines. */
5454 pa_hpux_init_libfuncs (void)
5456 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5457 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5458 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5459 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5460 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5461 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5462 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5463 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5464 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5466 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5467 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5468 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5469 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5470 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5471 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5473 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5474 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5475 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5476 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5478 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5479 ? "__U_Qfcnvfxt_quad_to_sgl"
5480 : "_U_Qfcnvfxt_quad_to_sgl");
5481 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5482 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5483 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5485 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5486 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5490 /* HP's millicode routines mean something special to the assembler.
5491 Keep track of which ones we have used. */
5493 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5494 static void import_milli (enum millicodes);
5495 static char imported[(int) end1000];
5496 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5497 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5498 #define MILLI_START 10
5501 import_milli (enum millicodes code)
5503 char str[sizeof (import_string)];
5505 if (!imported[(int) code])
5507 imported[(int) code] = 1;
5508 strcpy (str, import_string);
5509 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5510 output_asm_insn (str, 0);
5514 /* The register constraints have put the operands and return value in
5515 the proper registers. */
5518 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5520 import_milli (mulI);
5521 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5524 /* Emit the rtl for doing a division by a constant. */
5526 /* Do magic division millicodes exist for this value? */
5527 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5530 /* We'll use an array to keep track of the magic millicodes and
5531 whether or not we've used them already. [n][0] is signed, [n][1] is
5534 static int div_milli[16][2];
5537 div_operand (rtx op, enum machine_mode mode)
5539 return (mode == SImode
5540 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5541 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5542 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5546 emit_hpdiv_const (rtx *operands, int unsignedp)
5548 if (GET_CODE (operands[2]) == CONST_INT
5549 && INTVAL (operands[2]) > 0
5550 && INTVAL (operands[2]) < 16
5551 && magic_milli[INTVAL (operands[2])])
5553 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5555 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5559 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5560 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5562 gen_rtx_REG (SImode, 26),
5564 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5565 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5566 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5567 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5568 gen_rtx_CLOBBER (VOIDmode, ret))));
5569 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5576 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5580 /* If the divisor is a constant, try to use one of the special
5582 if (GET_CODE (operands[0]) == CONST_INT)
5584 static char buf[100];
5585 divisor = INTVAL (operands[0]);
5586 if (!div_milli[divisor][unsignedp])
5588 div_milli[divisor][unsignedp] = 1;
5590 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5592 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5596 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5597 INTVAL (operands[0]));
5598 return output_millicode_call (insn,
5599 gen_rtx_SYMBOL_REF (SImode, buf));
5603 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5604 INTVAL (operands[0]));
5605 return output_millicode_call (insn,
5606 gen_rtx_SYMBOL_REF (SImode, buf));
5609 /* Divisor isn't a special constant. */
5614 import_milli (divU);
5615 return output_millicode_call (insn,
5616 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5620 import_milli (divI);
5621 return output_millicode_call (insn,
5622 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5627 /* Output a $$rem millicode to do mod. */
5630 output_mod_insn (int unsignedp, rtx insn)
5634 import_milli (remU);
5635 return output_millicode_call (insn,
5636 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5640 import_milli (remI);
5641 return output_millicode_call (insn,
5642 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5647 output_arg_descriptor (rtx call_insn)
5649 const char *arg_regs[4];
5650 enum machine_mode arg_mode;
5652 int i, output_flag = 0;
5655 /* We neither need nor want argument location descriptors for the
5656 64bit runtime environment or the ELF32 environment. */
5657 if (TARGET_64BIT || TARGET_ELF32)
5660 for (i = 0; i < 4; i++)
5663 /* Specify explicitly that no argument relocations should take place
5664 if using the portable runtime calling conventions. */
5665 if (TARGET_PORTABLE_RUNTIME)
5667 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5672 if (GET_CODE (call_insn) != CALL_INSN)
5674 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5676 rtx use = XEXP (link, 0);
5678 if (! (GET_CODE (use) == USE
5679 && GET_CODE (XEXP (use, 0)) == REG
5680 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5683 arg_mode = GET_MODE (XEXP (use, 0));
5684 regno = REGNO (XEXP (use, 0));
5685 if (regno >= 23 && regno <= 26)
5687 arg_regs[26 - regno] = "GR";
5688 if (arg_mode == DImode)
5689 arg_regs[25 - regno] = "GR";
5691 else if (regno >= 32 && regno <= 39)
5693 if (arg_mode == SFmode)
5694 arg_regs[(regno - 32) / 2] = "FR";
5697 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5698 arg_regs[(regno - 34) / 2] = "FR";
5699 arg_regs[(regno - 34) / 2 + 1] = "FU";
5701 arg_regs[(regno - 34) / 2] = "FU";
5702 arg_regs[(regno - 34) / 2 + 1] = "FR";
5707 fputs ("\t.CALL ", asm_out_file);
5708 for (i = 0; i < 4; i++)
5713 fputc (',', asm_out_file);
5714 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5717 fputc ('\n', asm_out_file);
5720 /* Return the class of any secondary reload register that is needed to
5721 move IN into a register in class CLASS using mode MODE.
5723 Profiling has showed this routine and its descendants account for
5724 a significant amount of compile time (~7%). So it has been
5725 optimized to reduce redundant computations and eliminate useless
5728 It might be worthwhile to try and make this a leaf function too. */
5731 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5733 int regno, is_symbolic;
5735 /* Trying to load a constant into a FP register during PIC code
5736 generation will require %r1 as a scratch register. */
5738 && GET_MODE_CLASS (mode) == MODE_INT
5739 && FP_REG_CLASS_P (class)
5740 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5743 /* Profiling showed the PA port spends about 1.3% of its compilation
5744 time in true_regnum from calls inside secondary_reload_class. */
5746 if (GET_CODE (in) == REG)
5749 if (regno >= FIRST_PSEUDO_REGISTER)
5750 regno = true_regnum (in);
5752 else if (GET_CODE (in) == SUBREG)
5753 regno = true_regnum (in);
5757 /* If we have something like (mem (mem (...)), we can safely assume the
5758 inner MEM will end up in a general register after reloading, so there's
5759 no need for a secondary reload. */
5760 if (GET_CODE (in) == MEM
5761 && GET_CODE (XEXP (in, 0)) == MEM)
5764 /* Handle out of range displacement for integer mode loads/stores of
5766 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5767 && GET_MODE_CLASS (mode) == MODE_INT
5768 && FP_REG_CLASS_P (class))
5769 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5770 return GENERAL_REGS;
5772 /* A SAR<->FP register copy requires a secondary register (GPR) as
5773 well as secondary memory. */
5774 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5775 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5776 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5777 return GENERAL_REGS;
5779 if (GET_CODE (in) == HIGH)
5782 /* Profiling has showed GCC spends about 2.6% of its compilation
5783 time in symbolic_operand from calls inside secondary_reload_class.
5785 We use an inline copy and only compute its return value once to avoid
5787 switch (GET_CODE (in))
5797 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5798 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5799 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5809 && read_only_operand (in, VOIDmode))
5812 if (class != R1_REGS && is_symbolic)
5819 function_arg_padding (enum machine_mode mode, tree type)
5822 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5824 /* Return none if justification is not required. */
5826 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5827 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5830 /* The directions set here are ignored when a BLKmode argument larger
5831 than a word is placed in a register. Different code is used for
5832 the stack and registers. This makes it difficult to have a
5833 consistent data representation for both the stack and registers.
5834 For both runtimes, the justification and padding for arguments on
5835 the stack and in registers should be identical. */
5837 /* The 64-bit runtime specifies left justification for aggregates. */
5840 /* The 32-bit runtime architecture specifies right justification.
5841 When the argument is passed on the stack, the argument is padded
5842 with garbage on the left. The HP compiler pads with zeros. */
5846 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5853 /* Do what is necessary for `va_start'. We look at the current function
5854 to determine if stdargs or varargs is used and fill in an initial
5855 va_list. A pointer to this constructor is returned. */
5858 hppa_builtin_saveregs (void)
5861 tree fntype = TREE_TYPE (current_function_decl);
5862 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5863 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5864 != void_type_node)))
5865 ? UNITS_PER_WORD : 0);
5868 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5870 offset = current_function_arg_offset_rtx;
5876 /* Adjust for varargs/stdarg differences. */
5878 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5880 offset = current_function_arg_offset_rtx;
5882 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5883 from the incoming arg pointer and growing to larger addresses. */
5884 for (i = 26, off = -64; i >= 19; i--, off += 8)
5885 emit_move_insn (gen_rtx_MEM (word_mode,
5886 plus_constant (arg_pointer_rtx, off)),
5887 gen_rtx_REG (word_mode, i));
5889 /* The incoming args pointer points just beyond the flushback area;
5890 normally this is not a serious concern. However, when we are doing
5891 varargs/stdargs we want to make the arg pointer point to the start
5892 of the incoming argument area. */
5893 emit_move_insn (virtual_incoming_args_rtx,
5894 plus_constant (arg_pointer_rtx, -64));
5896 /* Now return a pointer to the first anonymous argument. */
5897 return copy_to_reg (expand_binop (Pmode, add_optab,
5898 virtual_incoming_args_rtx,
5899 offset, 0, 0, OPTAB_LIB_WIDEN));
5902 /* Store general registers on the stack. */
5903 dest = gen_rtx_MEM (BLKmode,
5904 plus_constant (current_function_internal_arg_pointer,
5906 set_mem_alias_set (dest, get_varargs_alias_set ());
5907 set_mem_align (dest, BITS_PER_WORD);
5908 move_block_from_reg (23, dest, 4);
5910 /* move_block_from_reg will emit code to store the argument registers
5911 individually as scalar stores.
5913 However, other insns may later load from the same addresses for
5914 a structure load (passing a struct to a varargs routine).
5916 The alias code assumes that such aliasing can never happen, so we
5917 have to keep memory referencing insns from moving up beyond the
5918 last argument register store. So we emit a blockage insn here. */
5919 emit_insn (gen_blockage ());
5921 return copy_to_reg (expand_binop (Pmode, add_optab,
5922 current_function_internal_arg_pointer,
5923 offset, 0, 0, OPTAB_LIB_WIDEN));
5927 hppa_va_start (tree valist, rtx nextarg)
5929 nextarg = expand_builtin_saveregs ();
5930 std_expand_builtin_va_start (valist, nextarg);
5934 hppa_va_arg (tree valist, tree type)
5936 HOST_WIDE_INT size = int_size_in_bytes (type);
5942 /* Every argument in PA64 is supposed to be passed by value
5943 (including large structs). However, as a GCC extension, we
5944 pass zero and variable sized arguments by reference. Empty
5945 structures are a GCC extension not supported by the HP
5946 compilers. Thus, passing them by reference isn't likely
5947 to conflict with the ABI. For variable sized arguments,
5948 GCC doesn't have the infrastructure to allocate these to
5951 /* Arguments with a size greater than 8 must be aligned 0 MOD 16. */
5953 if (size > UNITS_PER_WORD)
5955 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5956 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5957 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5958 build_int_2 (-2 * UNITS_PER_WORD, -1));
5959 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5960 TREE_SIDE_EFFECTS (t) = 1;
5961 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5965 return std_expand_builtin_va_arg (valist, type);
5968 ptr = build_pointer_type (type);
5970 /* Args grow upward. */
5971 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
5972 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5973 TREE_SIDE_EFFECTS (t) = 1;
5975 pptr = build_pointer_type (ptr);
5976 t = build1 (NOP_EXPR, pptr, t);
5977 TREE_SIDE_EFFECTS (t) = 1;
5979 t = build1 (INDIRECT_REF, ptr, t);
5980 TREE_SIDE_EFFECTS (t) = 1;
5983 else /* !TARGET_64BIT */
5985 ptr = build_pointer_type (type);
5987 /* "Large" and variable sized types are passed by reference. */
5988 if (size > 8 || size <= 0)
5990 /* Args grow downward. */
5991 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5992 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5993 TREE_SIDE_EFFECTS (t) = 1;
5995 pptr = build_pointer_type (ptr);
5996 t = build1 (NOP_EXPR, pptr, t);
5997 TREE_SIDE_EFFECTS (t) = 1;
5999 t = build1 (INDIRECT_REF, ptr, t);
6000 TREE_SIDE_EFFECTS (t) = 1;
6004 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
6005 build_int_2 (-size, -1));
6007 /* Copied from va-pa.h, but we probably don't need to align to
6008 word size, since we generate and preserve that invariant. */
6009 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
6010 build_int_2 ((size > 4 ? -8 : -4), -1));
6012 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6013 TREE_SIDE_EFFECTS (t) = 1;
6015 ofs = (8 - size) % 4;
6018 t = build (PLUS_EXPR, TREE_TYPE (valist), t,
6019 build_int_2 (ofs, 0));
6020 TREE_SIDE_EFFECTS (t) = 1;
6023 t = build1 (NOP_EXPR, ptr, t);
6024 TREE_SIDE_EFFECTS (t) = 1;
6029 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
6034 /* This routine handles all the normal conditional branch sequences we
6035 might need to generate. It handles compare immediate vs compare
6036 register, nullification of delay slots, varying length branches,
6037 negated branches, and all combinations of the above. It returns the
6038 output appropriate to emit the branch corresponding to all given
6042 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
6044 static char buf[100];
6048 /* A conditional branch to the following instruction (eg the delay slot)
6049 is asking for a disaster. This can happen when not optimizing and
6050 when jump optimization fails.
6052 While it is usually safe to emit nothing, this can fail if the
6053 preceding instruction is a nullified branch with an empty delay
6054 slot and the same branch target as this branch. We could check
6055 for this but jump optimization should eliminate nop jumps. It
6056 is always safe to emit a nop. */
6057 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6060 /* The doubleword form of the cmpib instruction doesn't have the LEU
6061 and GTU conditions while the cmpb instruction does. Since we accept
6062 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6063 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6064 operands[2] = gen_rtx_REG (DImode, 0);
6066 /* If this is a long branch with its delay slot unfilled, set `nullify'
6067 as it can nullify the delay slot and save a nop. */
6068 if (length == 8 && dbr_sequence_length () == 0)
6071 /* If this is a short forward conditional branch which did not get
6072 its delay slot filled, the delay slot can still be nullified. */
6073 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6074 nullify = forward_branch_p (insn);
6076 /* A forward branch over a single nullified insn can be done with a
6077 comclr instruction. This avoids a single cycle penalty due to
6078 mis-predicted branch if we fall through (branch not taken). */
6080 && next_real_insn (insn) != 0
6081 && get_attr_length (next_real_insn (insn)) == 4
6082 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6088 /* All short conditional branches except backwards with an unfilled
6092 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6094 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6095 if (GET_MODE (operands[1]) == DImode)
6098 strcat (buf, "%B3");
6100 strcat (buf, "%S3");
6102 strcat (buf, " %2,%r1,%%r0");
6104 strcat (buf, ",n %2,%r1,%0");
6106 strcat (buf, " %2,%r1,%0");
6109 /* All long conditionals. Note a short backward branch with an
6110 unfilled delay slot is treated just like a long backward branch
6111 with an unfilled delay slot. */
6113 /* Handle weird backwards branch with a filled delay slot
6114 with is nullified. */
6115 if (dbr_sequence_length () != 0
6116 && ! forward_branch_p (insn)
6119 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6120 if (GET_MODE (operands[1]) == DImode)
6123 strcat (buf, "%S3");
6125 strcat (buf, "%B3");
6126 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6128 /* Handle short backwards branch with an unfilled delay slot.
6129 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6130 taken and untaken branches. */
6131 else if (dbr_sequence_length () == 0
6132 && ! forward_branch_p (insn)
6133 && INSN_ADDRESSES_SET_P ()
6134 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6135 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6137 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6138 if (GET_MODE (operands[1]) == DImode)
6141 strcat (buf, "%B3 %2,%r1,%0%#");
6143 strcat (buf, "%S3 %2,%r1,%0%#");
6147 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6148 if (GET_MODE (operands[1]) == DImode)
6151 strcat (buf, "%S3");
6153 strcat (buf, "%B3");
6155 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6157 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6163 xoperands[0] = operands[0];
6164 xoperands[1] = operands[1];
6165 xoperands[2] = operands[2];
6166 xoperands[3] = operands[3];
6168 /* The reversed conditional branch must branch over one additional
6169 instruction if the delay slot is filled. If the delay slot
6170 is empty, the instruction after the reversed condition branch
6171 must be nullified. */
6172 nullify = dbr_sequence_length () == 0;
6173 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6175 /* Create a reversed conditional branch which branches around
6176 the following insns. */
6177 if (GET_MODE (operands[1]) != DImode)
6183 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6186 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6192 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6195 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6204 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6207 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6213 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6216 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6220 output_asm_insn (buf, xoperands);
6221 return output_lbranch (operands[0], insn);
6229 /* This routine handles long unconditional branches that exceed the
6230 maximum range of a simple branch instruction. */
6233 output_lbranch (rtx dest, rtx insn)
6237 xoperands[0] = dest;
6239 /* First, free up the delay slot. */
6240 if (dbr_sequence_length () != 0)
6242 /* We can't handle a jump in the delay slot. */
6243 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
6246 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6247 optimize, 0, 0, NULL);
6249 /* Now delete the delay insn. */
6250 PUT_CODE (NEXT_INSN (insn), NOTE);
6251 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6252 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6255 /* Output an insn to save %r1. The runtime documentation doesn't
6256 specify whether the "Clean Up" slot in the callers frame can
6257 be clobbered by the callee. It isn't copied by HP's builtin
6258 alloca, so this suggests that it can be clobbered if necessary.
6259 The "Static Link" location is copied by HP builtin alloca, so
6260 we avoid using it. Using the cleanup slot might be a problem
6261 if we have to interoperate with languages that pass cleanup
6262 information. However, it should be possible to handle these
6263 situations with GCC's asm feature.
6265 The "Current RP" slot is reserved for the called procedure, so
6266 we try to use it when we don't have a frame of our own. It's
6267 rather unlikely that we won't have a frame when we need to emit
6270 Really the way to go long term is a register scavenger; goto
6271 the target of the jump and find a register which we can use
6272 as a scratch to hold the value in %r1. Then, we wouldn't have
6273 to free up the delay slot or clobber a slot that may be needed
6274 for other purposes. */
6277 if (actual_fsize == 0 && !regs_ever_live[2])
6278 /* Use the return pointer slot in the frame marker. */
6279 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6281 /* Use the slot at -40 in the frame marker since HP builtin
6282 alloca doesn't copy it. */
6283 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6287 if (actual_fsize == 0 && !regs_ever_live[2])
6288 /* Use the return pointer slot in the frame marker. */
6289 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6291 /* Use the "Clean Up" slot in the frame marker. In GCC,
6292 the only other use of this location is for copying a
6293 floating point double argument from a floating-point
6294 register to two general registers. The copy is done
6295 as an "atomic" operation when outputting a call, so it
6296 won't interfere with our using the location here. */
6297 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6300 if (TARGET_PORTABLE_RUNTIME)
6302 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6303 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6304 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6308 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6309 if (TARGET_SOM || !TARGET_GAS)
6311 xoperands[1] = gen_label_rtx ();
6312 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6313 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6314 CODE_LABEL_NUMBER (xoperands[1]));
6315 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6319 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6320 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6322 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6325 /* Now output a very long branch to the original target. */
6326 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6328 /* Now restore the value of %r1 in the delay slot. */
6331 if (actual_fsize == 0 && !regs_ever_live[2])
6332 return "ldd -16(%%r30),%%r1";
6334 return "ldd -40(%%r30),%%r1";
6338 if (actual_fsize == 0 && !regs_ever_live[2])
6339 return "ldw -20(%%r30),%%r1";
6341 return "ldw -12(%%r30),%%r1";
6345 /* This routine handles all the branch-on-bit conditional branch sequences we
6346 might need to generate. It handles nullification of delay slots,
6347 varying length branches, negated branches and all combinations of the
6348 above. it returns the appropriate output template to emit the branch. */
6351 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6352 int negated, rtx insn, int which)
6354 static char buf[100];
6357 /* A conditional branch to the following instruction (eg the delay slot) is
6358 asking for a disaster. I do not think this can happen as this pattern
6359 is only used when optimizing; jump optimization should eliminate the
6360 jump. But be prepared just in case. */
6362 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6365 /* If this is a long branch with its delay slot unfilled, set `nullify'
6366 as it can nullify the delay slot and save a nop. */
6367 if (length == 8 && dbr_sequence_length () == 0)
6370 /* If this is a short forward conditional branch which did not get
6371 its delay slot filled, the delay slot can still be nullified. */
6372 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6373 nullify = forward_branch_p (insn);
6375 /* A forward branch over a single nullified insn can be done with a
6376 extrs instruction. This avoids a single cycle penalty due to
6377 mis-predicted branch if we fall through (branch not taken). */
6380 && next_real_insn (insn) != 0
6381 && get_attr_length (next_real_insn (insn)) == 4
6382 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6389 /* All short conditional branches except backwards with an unfilled
6393 strcpy (buf, "{extrs,|extrw,s,}");
6395 strcpy (buf, "bb,");
6396 if (useskip && GET_MODE (operands[0]) == DImode)
6397 strcpy (buf, "extrd,s,*");
6398 else if (GET_MODE (operands[0]) == DImode)
6399 strcpy (buf, "bb,*");
6400 if ((which == 0 && negated)
6401 || (which == 1 && ! negated))
6406 strcat (buf, " %0,%1,1,%%r0");
6407 else if (nullify && negated)
6408 strcat (buf, ",n %0,%1,%3");
6409 else if (nullify && ! negated)
6410 strcat (buf, ",n %0,%1,%2");
6411 else if (! nullify && negated)
6412 strcat (buf, "%0,%1,%3");
6413 else if (! nullify && ! negated)
6414 strcat (buf, " %0,%1,%2");
6417 /* All long conditionals. Note a short backward branch with an
6418 unfilled delay slot is treated just like a long backward branch
6419 with an unfilled delay slot. */
6421 /* Handle weird backwards branch with a filled delay slot
6422 with is nullified. */
6423 if (dbr_sequence_length () != 0
6424 && ! forward_branch_p (insn)
6427 strcpy (buf, "bb,");
6428 if (GET_MODE (operands[0]) == DImode)
6430 if ((which == 0 && negated)
6431 || (which == 1 && ! negated))
6436 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6438 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6440 /* Handle short backwards branch with an unfilled delay slot.
6441 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6442 taken and untaken branches. */
6443 else if (dbr_sequence_length () == 0
6444 && ! forward_branch_p (insn)
6445 && INSN_ADDRESSES_SET_P ()
6446 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6447 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6449 strcpy (buf, "bb,");
6450 if (GET_MODE (operands[0]) == DImode)
6452 if ((which == 0 && negated)
6453 || (which == 1 && ! negated))
6458 strcat (buf, " %0,%1,%3%#");
6460 strcat (buf, " %0,%1,%2%#");
6464 strcpy (buf, "{extrs,|extrw,s,}");
6465 if (GET_MODE (operands[0]) == DImode)
6466 strcpy (buf, "extrd,s,*");
6467 if ((which == 0 && negated)
6468 || (which == 1 && ! negated))
6472 if (nullify && negated)
6473 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6474 else if (nullify && ! negated)
6475 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6477 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6479 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6489 /* This routine handles all the branch-on-variable-bit conditional branch
6490 sequences we might need to generate. It handles nullification of delay
6491 slots, varying length branches, negated branches and all combinations
6492 of the above. it returns the appropriate output template to emit the
6496 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6497 int negated, rtx insn, int which)
6499 static char buf[100];
6502 /* A conditional branch to the following instruction (eg the delay slot) is
6503 asking for a disaster. I do not think this can happen as this pattern
6504 is only used when optimizing; jump optimization should eliminate the
6505 jump. But be prepared just in case. */
6507 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6510 /* If this is a long branch with its delay slot unfilled, set `nullify'
6511 as it can nullify the delay slot and save a nop. */
6512 if (length == 8 && dbr_sequence_length () == 0)
6515 /* If this is a short forward conditional branch which did not get
6516 its delay slot filled, the delay slot can still be nullified. */
6517 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6518 nullify = forward_branch_p (insn);
6520 /* A forward branch over a single nullified insn can be done with a
6521 extrs instruction. This avoids a single cycle penalty due to
6522 mis-predicted branch if we fall through (branch not taken). */
6525 && next_real_insn (insn) != 0
6526 && get_attr_length (next_real_insn (insn)) == 4
6527 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6534 /* All short conditional branches except backwards with an unfilled
6538 strcpy (buf, "{vextrs,|extrw,s,}");
6540 strcpy (buf, "{bvb,|bb,}");
6541 if (useskip && GET_MODE (operands[0]) == DImode)
6542 strcpy (buf, "extrd,s,*");
6543 else if (GET_MODE (operands[0]) == DImode)
6544 strcpy (buf, "bb,*");
6545 if ((which == 0 && negated)
6546 || (which == 1 && ! negated))
6551 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6552 else if (nullify && negated)
6553 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6554 else if (nullify && ! negated)
6555 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6556 else if (! nullify && negated)
6557 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6558 else if (! nullify && ! negated)
6559 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6562 /* All long conditionals. Note a short backward branch with an
6563 unfilled delay slot is treated just like a long backward branch
6564 with an unfilled delay slot. */
6566 /* Handle weird backwards branch with a filled delay slot
6567 with is nullified. */
6568 if (dbr_sequence_length () != 0
6569 && ! forward_branch_p (insn)
6572 strcpy (buf, "{bvb,|bb,}");
6573 if (GET_MODE (operands[0]) == DImode)
6575 if ((which == 0 && negated)
6576 || (which == 1 && ! negated))
6581 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6583 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6585 /* Handle short backwards branch with an unfilled delay slot.
6586 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6587 taken and untaken branches. */
6588 else if (dbr_sequence_length () == 0
6589 && ! forward_branch_p (insn)
6590 && INSN_ADDRESSES_SET_P ()
6591 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6592 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6594 strcpy (buf, "{bvb,|bb,}");
6595 if (GET_MODE (operands[0]) == DImode)
6597 if ((which == 0 && negated)
6598 || (which == 1 && ! negated))
6603 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6605 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6609 strcpy (buf, "{vextrs,|extrw,s,}");
6610 if (GET_MODE (operands[0]) == DImode)
6611 strcpy (buf, "extrd,s,*");
6612 if ((which == 0 && negated)
6613 || (which == 1 && ! negated))
6617 if (nullify && negated)
6618 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6619 else if (nullify && ! negated)
6620 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6622 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6624 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6634 /* Return the output template for emitting a dbra type insn.
6636 Note it may perform some output operations on its own before
6637 returning the final output string. */
6639 output_dbra (rtx *operands, rtx insn, int which_alternative)
6642 /* A conditional branch to the following instruction (eg the delay slot) is
6643 asking for a disaster. Be prepared! */
6645 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6647 if (which_alternative == 0)
6648 return "ldo %1(%0),%0";
6649 else if (which_alternative == 1)
6651 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6652 output_asm_insn ("ldw -16(%%r30),%4", operands);
6653 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6654 return "{fldws|fldw} -16(%%r30),%0";
6658 output_asm_insn ("ldw %0,%4", operands);
6659 return "ldo %1(%4),%4\n\tstw %4,%0";
6663 if (which_alternative == 0)
6665 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6666 int length = get_attr_length (insn);
6668 /* If this is a long branch with its delay slot unfilled, set `nullify'
6669 as it can nullify the delay slot and save a nop. */
6670 if (length == 8 && dbr_sequence_length () == 0)
6673 /* If this is a short forward conditional branch which did not get
6674 its delay slot filled, the delay slot can still be nullified. */
6675 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6676 nullify = forward_branch_p (insn);
6678 /* Handle short versions first. */
6679 if (length == 4 && nullify)
6680 return "addib,%C2,n %1,%0,%3";
6681 else if (length == 4 && ! nullify)
6682 return "addib,%C2 %1,%0,%3";
6683 else if (length == 8)
6685 /* Handle weird backwards branch with a fulled delay slot
6686 which is nullified. */
6687 if (dbr_sequence_length () != 0
6688 && ! forward_branch_p (insn)
6690 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6691 /* Handle short backwards branch with an unfilled delay slot.
6692 Using a addb;nop rather than addi;bl saves 1 cycle for both
6693 taken and untaken branches. */
6694 else if (dbr_sequence_length () == 0
6695 && ! forward_branch_p (insn)
6696 && INSN_ADDRESSES_SET_P ()
6697 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6698 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6699 return "addib,%C2 %1,%0,%3%#";
6701 /* Handle normal cases. */
6703 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6705 return "addi,%N2 %1,%0,%0\n\tb %3";
6710 /* Deal with gross reload from FP register case. */
6711 else if (which_alternative == 1)
6713 /* Move loop counter from FP register to MEM then into a GR,
6714 increment the GR, store the GR into MEM, and finally reload
6715 the FP register from MEM from within the branch's delay slot. */
6716 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6718 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6719 if (get_attr_length (insn) == 24)
6720 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6722 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6724 /* Deal with gross reload from memory case. */
6727 /* Reload loop counter from memory, the store back to memory
6728 happens in the branch's delay slot. */
6729 output_asm_insn ("ldw %0,%4", operands);
6730 if (get_attr_length (insn) == 12)
6731 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6733 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6737 /* Return the output template for emitting a dbra type insn.
6739 Note it may perform some output operations on its own before
6740 returning the final output string. */
6742 output_movb (rtx *operands, rtx insn, int which_alternative,
6743 int reverse_comparison)
6746 /* A conditional branch to the following instruction (eg the delay slot) is
6747 asking for a disaster. Be prepared! */
6749 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6751 if (which_alternative == 0)
6752 return "copy %1,%0";
6753 else if (which_alternative == 1)
6755 output_asm_insn ("stw %1,-16(%%r30)", operands);
6756 return "{fldws|fldw} -16(%%r30),%0";
6758 else if (which_alternative == 2)
6764 /* Support the second variant. */
6765 if (reverse_comparison)
6766 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6768 if (which_alternative == 0)
6770 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6771 int length = get_attr_length (insn);
6773 /* If this is a long branch with its delay slot unfilled, set `nullify'
6774 as it can nullify the delay slot and save a nop. */
6775 if (length == 8 && dbr_sequence_length () == 0)
6778 /* If this is a short forward conditional branch which did not get
6779 its delay slot filled, the delay slot can still be nullified. */
6780 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6781 nullify = forward_branch_p (insn);
6783 /* Handle short versions first. */
6784 if (length == 4 && nullify)
6785 return "movb,%C2,n %1,%0,%3";
6786 else if (length == 4 && ! nullify)
6787 return "movb,%C2 %1,%0,%3";
6788 else if (length == 8)
6790 /* Handle weird backwards branch with a filled delay slot
6791 which is nullified. */
6792 if (dbr_sequence_length () != 0
6793 && ! forward_branch_p (insn)
6795 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6797 /* Handle short backwards branch with an unfilled delay slot.
6798 Using a movb;nop rather than or;bl saves 1 cycle for both
6799 taken and untaken branches. */
6800 else if (dbr_sequence_length () == 0
6801 && ! forward_branch_p (insn)
6802 && INSN_ADDRESSES_SET_P ()
6803 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6804 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6805 return "movb,%C2 %1,%0,%3%#";
6806 /* Handle normal cases. */
6808 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6810 return "or,%N2 %1,%%r0,%0\n\tb %3";
6815 /* Deal with gross reload from FP register case. */
6816 else if (which_alternative == 1)
6818 /* Move loop counter from FP register to MEM then into a GR,
6819 increment the GR, store the GR into MEM, and finally reload
6820 the FP register from MEM from within the branch's delay slot. */
6821 output_asm_insn ("stw %1,-16(%%r30)", operands);
6822 if (get_attr_length (insn) == 12)
6823 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6825 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6827 /* Deal with gross reload from memory case. */
6828 else if (which_alternative == 2)
6830 /* Reload loop counter from memory, the store back to memory
6831 happens in the branch's delay slot. */
6832 if (get_attr_length (insn) == 8)
6833 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6835 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6837 /* Handle SAR as a destination. */
6840 if (get_attr_length (insn) == 8)
6841 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6843 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6847 /* Copy any FP arguments in INSN into integer registers. */
6849 copy_fp_args (rtx insn)
6854 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6856 int arg_mode, regno;
6857 rtx use = XEXP (link, 0);
6859 if (! (GET_CODE (use) == USE
6860 && GET_CODE (XEXP (use, 0)) == REG
6861 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6864 arg_mode = GET_MODE (XEXP (use, 0));
6865 regno = REGNO (XEXP (use, 0));
6867 /* Is it a floating point register? */
6868 if (regno >= 32 && regno <= 39)
6870 /* Copy the FP register into an integer register via memory. */
6871 if (arg_mode == SFmode)
6873 xoperands[0] = XEXP (use, 0);
6874 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6875 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6876 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6880 xoperands[0] = XEXP (use, 0);
6881 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6882 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6883 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6884 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6890 /* Compute length of the FP argument copy sequence for INSN. */
6892 length_fp_args (rtx insn)
6897 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6899 int arg_mode, regno;
6900 rtx use = XEXP (link, 0);
6902 if (! (GET_CODE (use) == USE
6903 && GET_CODE (XEXP (use, 0)) == REG
6904 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6907 arg_mode = GET_MODE (XEXP (use, 0));
6908 regno = REGNO (XEXP (use, 0));
6910 /* Is it a floating point register? */
6911 if (regno >= 32 && regno <= 39)
6913 if (arg_mode == SFmode)
6923 /* Return the attribute length for the millicode call instruction INSN.
6924 The length must match the code generated by output_millicode_call.
6925 We include the delay slot in the returned length as it is better to
6926 over estimate the length than to under estimate it. */
6929 attr_length_millicode_call (rtx insn)
6931 unsigned long distance = -1;
6932 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
6934 if (INSN_ADDRESSES_SET_P ())
6936 distance = (total + insn_current_reference_address (insn));
6937 if (distance < total)
6943 if (!TARGET_LONG_CALLS && distance < 7600000)
6948 else if (TARGET_PORTABLE_RUNTIME)
6952 if (!TARGET_LONG_CALLS && distance < 240000)
6955 if (TARGET_LONG_ABS_CALL && !flag_pic)
6962 /* INSN is a function call. It may have an unconditional jump
6965 CALL_DEST is the routine we are calling. */
6968 output_millicode_call (rtx insn, rtx call_dest)
6970 int attr_length = get_attr_length (insn);
6971 int seq_length = dbr_sequence_length ();
6976 xoperands[0] = call_dest;
6977 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6979 /* Handle the common case where we are sure that the branch will
6980 reach the beginning of the $CODE$ subspace. The within reach
6981 form of the $$sh_func_adrs call has a length of 28. Because
6982 it has an attribute type of multi, it never has a nonzero
6983 sequence length. The length of the $$sh_func_adrs is the same
6984 as certain out of reach PIC calls to other routines. */
6985 if (!TARGET_LONG_CALLS
6986 && ((seq_length == 0
6987 && (attr_length == 12
6988 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6989 || (seq_length != 0 && attr_length == 8)))
6991 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6997 /* It might seem that one insn could be saved by accessing
6998 the millicode function using the linkage table. However,
6999 this doesn't work in shared libraries and other dynamically
7000 loaded objects. Using a pc-relative sequence also avoids
7001 problems related to the implicit use of the gp register. */
7002 output_asm_insn ("b,l .+8,%%r1", xoperands);
7006 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7007 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7011 xoperands[1] = gen_label_rtx ();
7012 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7013 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7014 CODE_LABEL_NUMBER (xoperands[1]));
7015 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7018 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7020 else if (TARGET_PORTABLE_RUNTIME)
7022 /* Pure portable runtime doesn't allow be/ble; we also don't
7023 have PIC support in the assembler/linker, so this sequence
7026 /* Get the address of our target into %r1. */
7027 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7028 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7030 /* Get our return address into %r31. */
7031 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7032 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7034 /* Jump to our target address in %r1. */
7035 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7039 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7041 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7043 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7047 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7048 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7050 if (TARGET_SOM || !TARGET_GAS)
7052 /* The HP assembler can generate relocations for the
7053 difference of two symbols. GAS can do this for a
7054 millicode symbol but not an arbitrary external
7055 symbol when generating SOM output. */
7056 xoperands[1] = gen_label_rtx ();
7057 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7058 CODE_LABEL_NUMBER (xoperands[1]));
7059 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7060 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7064 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7065 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7069 /* Jump to our target address in %r1. */
7070 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7074 if (seq_length == 0)
7075 output_asm_insn ("nop", xoperands);
7077 /* We are done if there isn't a jump in the delay slot. */
7078 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7081 /* This call has an unconditional jump in its delay slot. */
7082 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7084 /* See if the return address can be adjusted. Use the containing
7085 sequence insn's address. */
7086 if (INSN_ADDRESSES_SET_P ())
7088 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7089 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7090 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7092 if (VAL_14_BITS_P (distance))
7094 xoperands[1] = gen_label_rtx ();
7095 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7096 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7097 CODE_LABEL_NUMBER (xoperands[1]));
7100 /* ??? This branch may not reach its target. */
7101 output_asm_insn ("nop\n\tb,n %0", xoperands);
7104 /* ??? This branch may not reach its target. */
7105 output_asm_insn ("nop\n\tb,n %0", xoperands);
7107 /* Delete the jump. */
7108 PUT_CODE (NEXT_INSN (insn), NOTE);
7109 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7110 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7115 /* Return the attribute length of the call instruction INSN. The SIBCALL
7116 flag indicates whether INSN is a regular call or a sibling call. The
7117 length returned must be longer than the code actually generated by
7118 output_call. Since branch shortening is done before delay branch
7119 sequencing, there is no way to determine whether or not the delay
7120 slot will be filled during branch shortening. Even when the delay
7121 slot is filled, we may have to add a nop if the delay slot contains
7122 a branch that can't reach its target. Thus, we always have to include
7123 the delay slot in the length estimate. This used to be done in
7124 pa_adjust_insn_length but we do it here now as some sequences always
7125 fill the delay slot and we can save four bytes in the estimate for
7129 attr_length_call (rtx insn, int sibcall)
7135 rtx pat = PATTERN (insn);
7136 unsigned long distance = -1;
7138 if (INSN_ADDRESSES_SET_P ())
7140 unsigned long total;
7142 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7143 distance = (total + insn_current_reference_address (insn));
7144 if (distance < total)
7148 /* Determine if this is a local call. */
7149 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7150 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7152 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7154 call_decl = SYMBOL_REF_DECL (call_dest);
7155 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7157 /* pc-relative branch. */
7158 if (!TARGET_LONG_CALLS
7159 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7160 || distance < 240000))
7163 /* 64-bit plabel sequence. */
7164 else if (TARGET_64BIT && !local_call)
7165 length += sibcall ? 28 : 24;
7167 /* non-pic long absolute branch sequence. */
7168 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7171 /* long pc-relative branch sequence. */
7172 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7173 || (TARGET_64BIT && !TARGET_GAS)
7174 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7178 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7182 /* 32-bit plabel sequence. */
7188 length += length_fp_args (insn);
7198 if (!TARGET_NO_SPACE_REGS)
7206 /* INSN is a function call. It may have an unconditional jump
7209 CALL_DEST is the routine we are calling. */
7212 output_call (rtx insn, rtx call_dest, int sibcall)
7214 int delay_insn_deleted = 0;
7215 int delay_slot_filled = 0;
7216 int seq_length = dbr_sequence_length ();
7217 tree call_decl = SYMBOL_REF_DECL (call_dest);
7218 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7221 xoperands[0] = call_dest;
7223 /* Handle the common case where we're sure that the branch will reach
7224 the beginning of the "$CODE$" subspace. This is the beginning of
7225 the current function if we are in a named section. */
7226 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7228 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7229 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7233 if (TARGET_64BIT && !local_call)
7235 /* ??? As far as I can tell, the HP linker doesn't support the
7236 long pc-relative sequence described in the 64-bit runtime
7237 architecture. So, we use a slightly longer indirect call. */
7238 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7240 xoperands[0] = p->internal_label;
7241 xoperands[1] = gen_label_rtx ();
7243 /* If this isn't a sibcall, we put the load of %r27 into the
7244 delay slot. We can't do this in a sibcall as we don't
7245 have a second call-clobbered scratch register available. */
7247 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7250 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7251 optimize, 0, 0, NULL);
7253 /* Now delete the delay insn. */
7254 PUT_CODE (NEXT_INSN (insn), NOTE);
7255 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7256 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7257 delay_insn_deleted = 1;
7260 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7261 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7262 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7266 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7267 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7268 output_asm_insn ("bve (%%r1)", xoperands);
7272 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7273 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7274 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7275 delay_slot_filled = 1;
7280 int indirect_call = 0;
7282 /* Emit a long call. There are several different sequences
7283 of increasing length and complexity. In most cases,
7284 they don't allow an instruction in the delay slot. */
7285 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7286 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7287 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7292 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7294 && (!TARGET_PA_20 || indirect_call))
7296 /* A non-jump insn in the delay slot. By definition we can
7297 emit this insn before the call (and in fact before argument
7299 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0,
7302 /* Now delete the delay insn. */
7303 PUT_CODE (NEXT_INSN (insn), NOTE);
7304 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7305 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7306 delay_insn_deleted = 1;
7309 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7311 /* This is the best sequence for making long calls in
7312 non-pic code. Unfortunately, GNU ld doesn't provide
7313 the stub needed for external calls, and GAS's support
7314 for this with the SOM linker is buggy. It is safe
7315 to use this for local calls. */
7316 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7318 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7322 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7325 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7327 output_asm_insn ("copy %%r31,%%r2", xoperands);
7328 delay_slot_filled = 1;
7333 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7334 || (TARGET_64BIT && !TARGET_GAS))
7336 /* The HP assembler and linker can handle relocations
7337 for the difference of two symbols. GAS and the HP
7338 linker can't do this when one of the symbols is
7340 xoperands[1] = gen_label_rtx ();
7341 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7342 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7343 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7344 CODE_LABEL_NUMBER (xoperands[1]));
7345 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7347 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7349 /* GAS currently can't generate the relocations that
7350 are needed for the SOM linker under HP-UX using this
7351 sequence. The GNU linker doesn't generate the stubs
7352 that are needed for external calls on TARGET_ELF32
7353 with this sequence. For now, we have to use a
7354 longer plabel sequence when using GAS. */
7355 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7356 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7358 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7363 /* Emit a long plabel-based call sequence. This is
7364 essentially an inline implementation of $$dyncall.
7365 We don't actually try to call $$dyncall as this is
7366 as difficult as calling the function itself. */
7367 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7369 xoperands[0] = p->internal_label;
7370 xoperands[1] = gen_label_rtx ();
7372 /* Since the call is indirect, FP arguments in registers
7373 need to be copied to the general registers. Then, the
7374 argument relocation stub will copy them back. */
7376 copy_fp_args (insn);
7380 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7381 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7382 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7386 output_asm_insn ("addil LR'%0-$global$,%%r27",
7388 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7392 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7393 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7394 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7395 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7397 if (!sibcall && !TARGET_PA_20)
7399 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7400 if (TARGET_NO_SPACE_REGS)
7401 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7403 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7410 output_asm_insn ("bve (%%r1)", xoperands);
7415 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7416 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7417 delay_slot_filled = 1;
7420 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7425 if (!TARGET_NO_SPACE_REGS)
7426 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7431 if (TARGET_NO_SPACE_REGS)
7432 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7434 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7438 if (TARGET_NO_SPACE_REGS)
7439 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7441 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7444 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7446 output_asm_insn ("copy %%r31,%%r2", xoperands);
7447 delay_slot_filled = 1;
7454 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7455 output_asm_insn ("nop", xoperands);
7457 /* We are done if there isn't a jump in the delay slot. */
7459 || delay_insn_deleted
7460 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7463 /* A sibcall should never have a branch in the delay slot. */
7467 /* This call has an unconditional jump in its delay slot. */
7468 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7470 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7472 /* See if the return address can be adjusted. Use the containing
7473 sequence insn's address. */
7474 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7475 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7476 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7478 if (VAL_14_BITS_P (distance))
7480 xoperands[1] = gen_label_rtx ();
7481 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7482 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7483 CODE_LABEL_NUMBER (xoperands[1]));
7486 output_asm_insn ("nop\n\tb,n %0", xoperands);
7489 output_asm_insn ("b,n %0", xoperands);
7491 /* Delete the jump. */
7492 PUT_CODE (NEXT_INSN (insn), NOTE);
7493 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7494 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7499 /* Return the attribute length of the indirect call instruction INSN.
7500 The length must match the code generated by output_indirect call.
7501 The returned length includes the delay slot. Currently, the delay
7502 slot of an indirect call sequence is not exposed and it is used by
7503 the sequence itself. */
7506 attr_length_indirect_call (rtx insn)
7508 unsigned long distance = -1;
7509 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7511 if (INSN_ADDRESSES_SET_P ())
7513 distance = (total + insn_current_reference_address (insn));
7514 if (distance < total)
7521 if (TARGET_FAST_INDIRECT_CALLS
7522 || (!TARGET_PORTABLE_RUNTIME
7523 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7529 if (TARGET_PORTABLE_RUNTIME)
7532 /* Out of reach, can use ble. */
7537 output_indirect_call (rtx insn, rtx call_dest)
7543 xoperands[0] = call_dest;
7544 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7545 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7549 /* First the special case for kernels, level 0 systems, etc. */
7550 if (TARGET_FAST_INDIRECT_CALLS)
7551 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7553 /* Now the normal case -- we can reach $$dyncall directly or
7554 we're sure that we can get there via a long-branch stub.
7556 No need to check target flags as the length uniquely identifies
7557 the remaining cases. */
7558 if (attr_length_indirect_call (insn) == 8)
7559 return ".CALL\tARGW0=GR\n\t{bl|b,l} $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7561 /* Long millicode call, but we are not generating PIC or portable runtime
7563 if (attr_length_indirect_call (insn) == 12)
7564 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7566 /* Long millicode call for portable runtime. */
7567 if (attr_length_indirect_call (insn) == 20)
7568 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7570 /* We need a long PIC call to $$dyncall. */
7571 xoperands[0] = NULL_RTX;
7572 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7573 if (TARGET_SOM || !TARGET_GAS)
7575 xoperands[0] = gen_label_rtx ();
7576 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7577 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7578 CODE_LABEL_NUMBER (xoperands[0]));
7579 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7583 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7584 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7587 output_asm_insn ("blr %%r0,%%r2", xoperands);
7588 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7592 /* Return the total length of the save and restore instructions needed for
7593 the data linkage table pointer (i.e., the PIC register) across the call
7594 instruction INSN. No-return calls do not require a save and restore.
7595 In addition, we may be able to avoid the save and restore for calls
7596 within the same translation unit. */
7599 attr_length_save_restore_dltp (rtx insn)
7601 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7607 /* In HPUX 8.0's shared library scheme, special relocations are needed
7608 for function labels if they might be passed to a function
7609 in a shared library (because shared libraries don't live in code
7610 space), and special magic is needed to construct their address. */
7613 hppa_encode_label (rtx sym)
7615 const char *str = XSTR (sym, 0);
7616 int len = strlen (str) + 1;
7619 p = newstr = alloca (len + 1);
7623 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7627 pa_encode_section_info (tree decl, rtx rtl, int first)
7629 if (first && TEXT_SPACE_P (decl))
7631 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7632 if (TREE_CODE (decl) == FUNCTION_DECL)
7633 hppa_encode_label (XEXP (rtl, 0));
7637 /* This is sort of inverse to pa_encode_section_info. */
7640 pa_strip_name_encoding (const char *str)
7642 str += (*str == '@');
7643 str += (*str == '*');
7648 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7650 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7653 /* Returns 1 if OP is a function label involved in a simple addition
7654 with a constant. Used to keep certain patterns from matching
7655 during instruction combination. */
7657 is_function_label_plus_const (rtx op)
7659 /* Strip off any CONST. */
7660 if (GET_CODE (op) == CONST)
7663 return (GET_CODE (op) == PLUS
7664 && function_label_operand (XEXP (op, 0), Pmode)
7665 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7668 /* Output assembly code for a thunk to FUNCTION. */
7671 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7672 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7675 const char *fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
7676 const char *tname = XSTR (XEXP (DECL_RTL (thunk_fndecl), 0), 0);
7677 int val_14 = VAL_14_BITS_P (delta);
7679 static unsigned int current_thunk_number;
7682 ASM_OUTPUT_LABEL (file, tname);
7683 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7685 fname = (*targetm.strip_name_encoding) (fname);
7686 tname = (*targetm.strip_name_encoding) (tname);
7688 /* Output the thunk. We know that the function is in the same
7689 translation unit (i.e., the same space) as the thunk, and that
7690 thunks are output after their method. Thus, we don't need an
7691 external branch to reach the function. With SOM and GAS,
7692 functions and thunks are effectively in different sections.
7693 Thus, we can always use a IA-relative branch and the linker
7694 will add a long branch stub if necessary.
7696 However, we have to be careful when generating PIC code on the
7697 SOM port to ensure that the sequence does not transfer to an
7698 import stub for the target function as this could clobber the
7699 return value saved at SP-24. This would also apply to the
7700 32-bit linux port if the multi-space model is implemented. */
7701 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7702 && !(flag_pic && TREE_PUBLIC (function))
7703 && (TARGET_GAS || last_address < 262132))
7704 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7705 && ((targetm.have_named_sections
7706 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7707 /* The GNU 64-bit linker has rather poor stub management.
7708 So, we use a long branch from thunks that aren't in
7709 the same section as the target function. */
7711 && (DECL_SECTION_NAME (thunk_fndecl)
7712 != DECL_SECTION_NAME (function)))
7713 || ((DECL_SECTION_NAME (thunk_fndecl)
7714 == DECL_SECTION_NAME (function))
7715 && last_address < 262132)))
7716 || (!targetm.have_named_sections && last_address < 262132))))
7720 fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC
7721 "(%%r26),%%r26\n", fname, delta);
7726 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7728 fprintf (file, "\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7729 "(%%r1),%%r26\n", fname, delta);
7733 else if (TARGET_64BIT)
7735 /* We only have one call-clobbered scratch register, so we can't
7736 make use of the delay slot if delta doesn't fit in 14 bits. */
7738 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7739 ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7740 "(%%r1),%%r26\n", delta, delta);
7742 fprintf (file, "\tb,l .+8,%%r1\n");
7746 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7747 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r1\n", fname);
7751 int off = val_14 ? 8 : 16;
7752 fprintf (file, "\taddil L'%s-%s-%d,%%r1\n", fname, tname, off);
7753 fprintf (file, "\tldo R'%s-%s-%d(%%r1),%%r1\n", fname, tname, off);
7758 fprintf (file, "\tbv %%r0(%%r1)\n\tldo ");
7759 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7764 fprintf (file, "\tbv,n %%r0(%%r1)\n");
7768 else if (TARGET_PORTABLE_RUNTIME)
7770 fprintf (file, "\tldil L'%s,%%r1\n", fname);
7771 fprintf (file, "\tldo R'%s(%%r1),%%r22\n", fname);
7775 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7776 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7781 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7783 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7784 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7788 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7790 /* The function is accessible from outside this module. The only
7791 way to avoid an import stub between the thunk and function is to
7792 call the function directly with an indirect sequence similar to
7793 that used by $$dyncall. This is possible because $$dyncall acts
7794 as the import stub in an indirect call. */
7797 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7798 lab = (*targetm.strip_name_encoding) (label);
7800 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7801 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7802 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7803 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7804 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7805 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7806 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7809 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7815 fprintf (file, "\tbve (%%r22)\n\tldo ");
7820 if (TARGET_NO_SPACE_REGS)
7822 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
7827 fprintf (file, "\tldsid (%%sr0,%%r22),%%r21\n");
7828 fprintf (file, "\tmtsp %%r21,%%sr0\n");
7829 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
7835 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7837 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7842 fprintf (file, "\tb,l .+8,%%r1\n");
7844 fprintf (file, "\tbl .+8,%%r1\n");
7846 if (TARGET_SOM || !TARGET_GAS)
7848 fprintf (file, "\taddil L'%s-%s-8,%%r1\n", fname, tname);
7849 fprintf (file, "\tldo R'%s-%s-8(%%r1),%%r22\n", fname, tname);
7853 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7854 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r22\n", fname);
7859 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7860 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7865 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7867 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7868 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7875 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC ",%%r26\n", delta);
7877 fprintf (file, "\tldil L'%s,%%r22\n", fname);
7878 fprintf (file, "\tbe R'%s(%%sr4,%%r22)\n\tldo ", fname);
7882 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7887 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7892 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7894 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7897 fprintf (file, "\t.align 4\n");
7898 ASM_OUTPUT_LABEL (file, label);
7899 fprintf (file, "\t.word P'%s\n", fname);
7900 function_section (thunk_fndecl);
7903 current_thunk_number++;
7904 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
7905 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
7906 last_address += nbytes;
7907 update_total_code_bytes (nbytes);
7910 /* Only direct calls to static functions are allowed to be sibling (tail)
7913 This restriction is necessary because some linker generated stubs will
7914 store return pointers into rp' in some cases which might clobber a
7915 live value already in rp'.
7917 In a sibcall the current function and the target function share stack
7918 space. Thus if the path to the current function and the path to the
7919 target function save a value in rp', they save the value into the
7920 same stack slot, which has undesirable consequences.
7922 Because of the deferred binding nature of shared libraries any function
7923 with external scope could be in a different load module and thus require
7924 rp' to be saved when calling that function. So sibcall optimizations
7925 can only be safe for static function.
7927 Note that GCC never needs return value relocations, so we don't have to
7928 worry about static calls with return value relocations (which require
7931 It is safe to perform a sibcall optimization when the target function
7932 will never return. */
7934 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7936 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7937 single subspace mode and the call is not indirect. As far as I know,
7938 there is no operating system support for the multiple subspace mode.
7939 It might be possible to support indirect calls if we didn't use
7940 $$dyncall (see the indirect sequence generated in output_call). */
7942 return (decl != NULL_TREE);
7944 /* Sibcalls are not ok because the arg pointer register is not a fixed
7945 register. This prevents the sibcall optimization from occurring. In
7946 addition, there are problems with stub placement using GNU ld. This
7947 is because a normal sibcall branch uses a 17-bit relocation while
7948 a regular call branch uses a 22-bit relocation. As a result, more
7949 care needs to be taken in the placement of long-branch stubs. */
7954 && !TARGET_PORTABLE_RUNTIME
7955 && !TREE_PUBLIC (decl));
7958 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7959 use in fmpyadd instructions. */
7961 fmpyaddoperands (rtx *operands)
7963 enum machine_mode mode = GET_MODE (operands[0]);
7965 /* Must be a floating point mode. */
7966 if (mode != SFmode && mode != DFmode)
7969 /* All modes must be the same. */
7970 if (! (mode == GET_MODE (operands[1])
7971 && mode == GET_MODE (operands[2])
7972 && mode == GET_MODE (operands[3])
7973 && mode == GET_MODE (operands[4])
7974 && mode == GET_MODE (operands[5])))
7977 /* All operands must be registers. */
7978 if (! (GET_CODE (operands[1]) == REG
7979 && GET_CODE (operands[2]) == REG
7980 && GET_CODE (operands[3]) == REG
7981 && GET_CODE (operands[4]) == REG
7982 && GET_CODE (operands[5]) == REG))
7985 /* Only 2 real operands to the addition. One of the input operands must
7986 be the same as the output operand. */
7987 if (! rtx_equal_p (operands[3], operands[4])
7988 && ! rtx_equal_p (operands[3], operands[5]))
7991 /* Inout operand of add can not conflict with any operands from multiply. */
7992 if (rtx_equal_p (operands[3], operands[0])
7993 || rtx_equal_p (operands[3], operands[1])
7994 || rtx_equal_p (operands[3], operands[2]))
7997 /* multiply can not feed into addition operands. */
7998 if (rtx_equal_p (operands[4], operands[0])
7999 || rtx_equal_p (operands[5], operands[0]))
8002 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8004 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8005 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8006 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8007 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8008 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8009 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8012 /* Passed. Operands are suitable for fmpyadd. */
8016 #if !defined(USE_COLLECT2)
8018 pa_asm_out_constructor (rtx symbol, int priority)
8020 if (!function_label_operand (symbol, VOIDmode))
8021 hppa_encode_label (symbol);
8023 #ifdef CTORS_SECTION_ASM_OP
8024 default_ctor_section_asm_out_constructor (symbol, priority);
8026 # ifdef TARGET_ASM_NAMED_SECTION
8027 default_named_section_asm_out_constructor (symbol, priority);
8029 default_stabs_asm_out_constructor (symbol, priority);
8035 pa_asm_out_destructor (rtx symbol, int priority)
8037 if (!function_label_operand (symbol, VOIDmode))
8038 hppa_encode_label (symbol);
8040 #ifdef DTORS_SECTION_ASM_OP
8041 default_dtor_section_asm_out_destructor (symbol, priority);
8043 # ifdef TARGET_ASM_NAMED_SECTION
8044 default_named_section_asm_out_destructor (symbol, priority);
8046 default_stabs_asm_out_destructor (symbol, priority);
8052 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8053 use in fmpysub instructions. */
8055 fmpysuboperands (rtx *operands)
8057 enum machine_mode mode = GET_MODE (operands[0]);
8059 /* Must be a floating point mode. */
8060 if (mode != SFmode && mode != DFmode)
8063 /* All modes must be the same. */
8064 if (! (mode == GET_MODE (operands[1])
8065 && mode == GET_MODE (operands[2])
8066 && mode == GET_MODE (operands[3])
8067 && mode == GET_MODE (operands[4])
8068 && mode == GET_MODE (operands[5])))
8071 /* All operands must be registers. */
8072 if (! (GET_CODE (operands[1]) == REG
8073 && GET_CODE (operands[2]) == REG
8074 && GET_CODE (operands[3]) == REG
8075 && GET_CODE (operands[4]) == REG
8076 && GET_CODE (operands[5]) == REG))
8079 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8080 operation, so operands[4] must be the same as operand[3]. */
8081 if (! rtx_equal_p (operands[3], operands[4]))
8084 /* multiply can not feed into subtraction. */
8085 if (rtx_equal_p (operands[5], operands[0]))
8088 /* Inout operand of sub can not conflict with any operands from multiply. */
8089 if (rtx_equal_p (operands[3], operands[0])
8090 || rtx_equal_p (operands[3], operands[1])
8091 || rtx_equal_p (operands[3], operands[2]))
8094 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8096 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8097 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8098 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8099 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8100 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8101 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8104 /* Passed. Operands are suitable for fmpysub. */
8109 plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8111 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
8112 || GET_CODE (op) == IOR);
8115 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8116 constants for shadd instructions. */
8118 shadd_constant_p (int val)
8120 if (val == 2 || val == 4 || val == 8)
8126 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
8127 the valid constant for shadd instructions. */
8129 shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8131 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
8134 /* Return 1 if OP is valid as a base or index register in a
8138 borx_reg_operand (rtx op, enum machine_mode mode)
8140 if (GET_CODE (op) != REG)
8143 /* We must reject virtual registers as the only expressions that
8144 can be instantiated are REG and REG+CONST. */
8145 if (op == virtual_incoming_args_rtx
8146 || op == virtual_stack_vars_rtx
8147 || op == virtual_stack_dynamic_rtx
8148 || op == virtual_outgoing_args_rtx
8149 || op == virtual_cfa_rtx)
8152 /* While it's always safe to index off the frame pointer, it's not
8153 profitable to do so when the frame pointer is being eliminated. */
8154 if (!reload_completed
8155 && flag_omit_frame_pointer
8156 && !current_function_calls_alloca
8157 && op == frame_pointer_rtx)
8160 return register_operand (op, mode);
8163 /* Return 1 if this operand is anything other than a hard register. */
8166 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8168 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8171 /* Return 1 if INSN branches forward. Should be using insn_addresses
8172 to avoid walking through all the insns... */
8174 forward_branch_p (rtx insn)
8176 rtx label = JUMP_LABEL (insn);
8183 insn = NEXT_INSN (insn);
8186 return (insn == label);
8189 /* Return 1 if OP is an equality comparison, else return 0. */
8191 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8193 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8196 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
8198 movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8200 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
8201 || GET_CODE (op) == LT || GET_CODE (op) == GE);
8204 /* Return 1 if INSN is in the delay slot of a call instruction. */
8206 jump_in_call_delay (rtx insn)
8209 if (GET_CODE (insn) != JUMP_INSN)
8212 if (PREV_INSN (insn)
8213 && PREV_INSN (PREV_INSN (insn))
8214 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8216 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8218 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8219 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8226 /* Output an unconditional move and branch insn. */
8229 output_parallel_movb (rtx *operands, int length)
8231 /* These are the cases in which we win. */
8233 return "mov%I1b,tr %1,%0,%2";
8235 /* None of these cases wins, but they don't lose either. */
8236 if (dbr_sequence_length () == 0)
8238 /* Nothing in the delay slot, fake it by putting the combined
8239 insn (the copy or add) in the delay slot of a bl. */
8240 if (GET_CODE (operands[1]) == CONST_INT)
8241 return "b %2\n\tldi %1,%0";
8243 return "b %2\n\tcopy %1,%0";
8247 /* Something in the delay slot, but we've got a long branch. */
8248 if (GET_CODE (operands[1]) == CONST_INT)
8249 return "ldi %1,%0\n\tb %2";
8251 return "copy %1,%0\n\tb %2";
8255 /* Output an unconditional add and branch insn. */
8258 output_parallel_addb (rtx *operands, int length)
8260 /* To make life easy we want operand0 to be the shared input/output
8261 operand and operand1 to be the readonly operand. */
8262 if (operands[0] == operands[1])
8263 operands[1] = operands[2];
8265 /* These are the cases in which we win. */
8267 return "add%I1b,tr %1,%0,%3";
8269 /* None of these cases win, but they don't lose either. */
8270 if (dbr_sequence_length () == 0)
8272 /* Nothing in the delay slot, fake it by putting the combined
8273 insn (the copy or add) in the delay slot of a bl. */
8274 return "b %3\n\tadd%I1 %1,%0,%0";
8278 /* Something in the delay slot, but we've got a long branch. */
8279 return "add%I1 %1,%0,%0\n\tb %3";
8283 /* Return nonzero if INSN (a jump insn) immediately follows a call
8284 to a named function. This is used to avoid filling the delay slot
8285 of the jump since it can usually be eliminated by modifying RP in
8286 the delay slot of the call. */
8289 following_call (rtx insn)
8291 if (! TARGET_JUMP_IN_DELAY)
8294 /* Find the previous real insn, skipping NOTEs. */
8295 insn = PREV_INSN (insn);
8296 while (insn && GET_CODE (insn) == NOTE)
8297 insn = PREV_INSN (insn);
8299 /* Check for CALL_INSNs and millicode calls. */
8301 && ((GET_CODE (insn) == CALL_INSN
8302 && get_attr_type (insn) != TYPE_DYNCALL)
8303 || (GET_CODE (insn) == INSN
8304 && GET_CODE (PATTERN (insn)) != SEQUENCE
8305 && GET_CODE (PATTERN (insn)) != USE
8306 && GET_CODE (PATTERN (insn)) != CLOBBER
8307 && get_attr_type (insn) == TYPE_MILLI)))
8313 /* We use this hook to perform a PA specific optimization which is difficult
8314 to do in earlier passes.
8316 We want the delay slots of branches within jump tables to be filled.
8317 None of the compiler passes at the moment even has the notion that a
8318 PA jump table doesn't contain addresses, but instead contains actual
8321 Because we actually jump into the table, the addresses of each entry
8322 must stay constant in relation to the beginning of the table (which
8323 itself must stay constant relative to the instruction to jump into
8324 it). I don't believe we can guarantee earlier passes of the compiler
8325 will adhere to those rules.
8327 So, late in the compilation process we find all the jump tables, and
8328 expand them into real code -- eg each entry in the jump table vector
8329 will get an appropriate label followed by a jump to the final target.
8331 Reorg and the final jump pass can then optimize these branches and
8332 fill their delay slots. We end up with smaller, more efficient code.
8334 The jump instructions within the table are special; we must be able
8335 to identify them during assembly output (if the jumps don't get filled
8336 we need to emit a nop rather than nullifying the delay slot)). We
8337 identify jumps in switch tables by using insns with the attribute
8338 type TYPE_BTABLE_BRANCH.
8340 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8341 insns. This serves two purposes, first it prevents jump.c from
8342 noticing that the last N entries in the table jump to the instruction
8343 immediately after the table and deleting the jumps. Second, those
8344 insns mark where we should emit .begin_brtab and .end_brtab directives
8345 when using GAS (allows for better link time optimizations). */
8352 remove_useless_addtr_insns (1);
8354 if (pa_cpu < PROCESSOR_8000)
8355 pa_combine_instructions ();
8358 /* This is fairly cheap, so always run it if optimizing. */
8359 if (optimize > 0 && !TARGET_BIG_SWITCH)
8361 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8362 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8364 rtx pattern, tmp, location, label;
8365 unsigned int length, i;
8367 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8368 if (GET_CODE (insn) != JUMP_INSN
8369 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8370 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8373 /* Emit marker for the beginning of the branch table. */
8374 emit_insn_before (gen_begin_brtab (), insn);
8376 pattern = PATTERN (insn);
8377 location = PREV_INSN (insn);
8378 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8380 for (i = 0; i < length; i++)
8382 /* Emit a label before each jump to keep jump.c from
8383 removing this code. */
8384 tmp = gen_label_rtx ();
8385 LABEL_NUSES (tmp) = 1;
8386 emit_label_after (tmp, location);
8387 location = NEXT_INSN (location);
8389 if (GET_CODE (pattern) == ADDR_VEC)
8390 label = XEXP (XVECEXP (pattern, 0, i), 0);
8392 label = XEXP (XVECEXP (pattern, 1, i), 0);
8394 tmp = gen_short_jump (label);
8396 /* Emit the jump itself. */
8397 tmp = emit_jump_insn_after (tmp, location);
8398 JUMP_LABEL (tmp) = label;
8399 LABEL_NUSES (label)++;
8400 location = NEXT_INSN (location);
8402 /* Emit a BARRIER after the jump. */
8403 emit_barrier_after (location);
8404 location = NEXT_INSN (location);
8407 /* Emit marker for the end of the branch table. */
8408 emit_insn_before (gen_end_brtab (), location);
8409 location = NEXT_INSN (location);
8410 emit_barrier_after (location);
8412 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8418 /* Still need brtab marker insns. FIXME: the presence of these
8419 markers disables output of the branch table to readonly memory,
8420 and any alignment directives that might be needed. Possibly,
8421 the begin_brtab insn should be output before the label for the
8422 table. This doesn't matter at the moment since the tables are
8423 always output in the text section. */
8424 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8426 /* Find an ADDR_VEC insn. */
8427 if (GET_CODE (insn) != JUMP_INSN
8428 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8429 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8432 /* Now generate markers for the beginning and end of the
8434 emit_insn_before (gen_begin_brtab (), insn);
8435 emit_insn_after (gen_end_brtab (), insn);
8440 /* The PA has a number of odd instructions which can perform multiple
8441 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8442 it may be profitable to combine two instructions into one instruction
8443 with two outputs. It's not profitable PA2.0 machines because the
8444 two outputs would take two slots in the reorder buffers.
8446 This routine finds instructions which can be combined and combines
8447 them. We only support some of the potential combinations, and we
8448 only try common ways to find suitable instructions.
8450 * addb can add two registers or a register and a small integer
8451 and jump to a nearby (+-8k) location. Normally the jump to the
8452 nearby location is conditional on the result of the add, but by
8453 using the "true" condition we can make the jump unconditional.
8454 Thus addb can perform two independent operations in one insn.
8456 * movb is similar to addb in that it can perform a reg->reg
8457 or small immediate->reg copy and jump to a nearby (+-8k location).
8459 * fmpyadd and fmpysub can perform a FP multiply and either an
8460 FP add or FP sub if the operands of the multiply and add/sub are
8461 independent (there are other minor restrictions). Note both
8462 the fmpy and fadd/fsub can in theory move to better spots according
8463 to data dependencies, but for now we require the fmpy stay at a
8466 * Many of the memory operations can perform pre & post updates
8467 of index registers. GCC's pre/post increment/decrement addressing
8468 is far too simple to take advantage of all the possibilities. This
8469 pass may not be suitable since those insns may not be independent.
8471 * comclr can compare two ints or an int and a register, nullify
8472 the following instruction and zero some other register. This
8473 is more difficult to use as it's harder to find an insn which
8474 will generate a comclr than finding something like an unconditional
8475 branch. (conditional moves & long branches create comclr insns).
8477 * Most arithmetic operations can conditionally skip the next
8478 instruction. They can be viewed as "perform this operation
8479 and conditionally jump to this nearby location" (where nearby
8480 is an insns away). These are difficult to use due to the
8481 branch length restrictions. */
8484 pa_combine_instructions (void)
8488 /* This can get expensive since the basic algorithm is on the
8489 order of O(n^2) (or worse). Only do it for -O2 or higher
8490 levels of optimization. */
8494 /* Walk down the list of insns looking for "anchor" insns which
8495 may be combined with "floating" insns. As the name implies,
8496 "anchor" instructions don't move, while "floating" insns may
8498 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8499 new = make_insn_raw (new);
8501 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8503 enum attr_pa_combine_type anchor_attr;
8504 enum attr_pa_combine_type floater_attr;
8506 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8507 Also ignore any special USE insns. */
8508 if ((GET_CODE (anchor) != INSN
8509 && GET_CODE (anchor) != JUMP_INSN
8510 && GET_CODE (anchor) != CALL_INSN)
8511 || GET_CODE (PATTERN (anchor)) == USE
8512 || GET_CODE (PATTERN (anchor)) == CLOBBER
8513 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8514 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8517 anchor_attr = get_attr_pa_combine_type (anchor);
8518 /* See if anchor is an insn suitable for combination. */
8519 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8520 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8521 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8522 && ! forward_branch_p (anchor)))
8526 for (floater = PREV_INSN (anchor);
8528 floater = PREV_INSN (floater))
8530 if (GET_CODE (floater) == NOTE
8531 || (GET_CODE (floater) == INSN
8532 && (GET_CODE (PATTERN (floater)) == USE
8533 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8536 /* Anything except a regular INSN will stop our search. */
8537 if (GET_CODE (floater) != INSN
8538 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8539 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8545 /* See if FLOATER is suitable for combination with the
8547 floater_attr = get_attr_pa_combine_type (floater);
8548 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8549 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8550 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8551 && floater_attr == PA_COMBINE_TYPE_FMPY))
8553 /* If ANCHOR and FLOATER can be combined, then we're
8554 done with this pass. */
8555 if (pa_can_combine_p (new, anchor, floater, 0,
8556 SET_DEST (PATTERN (floater)),
8557 XEXP (SET_SRC (PATTERN (floater)), 0),
8558 XEXP (SET_SRC (PATTERN (floater)), 1)))
8562 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8563 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8565 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8567 if (pa_can_combine_p (new, anchor, floater, 0,
8568 SET_DEST (PATTERN (floater)),
8569 XEXP (SET_SRC (PATTERN (floater)), 0),
8570 XEXP (SET_SRC (PATTERN (floater)), 1)))
8575 if (pa_can_combine_p (new, anchor, floater, 0,
8576 SET_DEST (PATTERN (floater)),
8577 SET_SRC (PATTERN (floater)),
8578 SET_SRC (PATTERN (floater))))
8584 /* If we didn't find anything on the backwards scan try forwards. */
8586 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8587 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8589 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8591 if (GET_CODE (floater) == NOTE
8592 || (GET_CODE (floater) == INSN
8593 && (GET_CODE (PATTERN (floater)) == USE
8594 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8598 /* Anything except a regular INSN will stop our search. */
8599 if (GET_CODE (floater) != INSN
8600 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8601 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8607 /* See if FLOATER is suitable for combination with the
8609 floater_attr = get_attr_pa_combine_type (floater);
8610 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8611 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8612 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8613 && floater_attr == PA_COMBINE_TYPE_FMPY))
8615 /* If ANCHOR and FLOATER can be combined, then we're
8616 done with this pass. */
8617 if (pa_can_combine_p (new, anchor, floater, 1,
8618 SET_DEST (PATTERN (floater)),
8619 XEXP (SET_SRC (PATTERN (floater)),
8621 XEXP (SET_SRC (PATTERN (floater)),
8628 /* FLOATER will be nonzero if we found a suitable floating
8629 insn for combination with ANCHOR. */
8631 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8632 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8634 /* Emit the new instruction and delete the old anchor. */
8635 emit_insn_before (gen_rtx_PARALLEL
8637 gen_rtvec (2, PATTERN (anchor),
8638 PATTERN (floater))),
8641 PUT_CODE (anchor, NOTE);
8642 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8643 NOTE_SOURCE_FILE (anchor) = 0;
8645 /* Emit a special USE insn for FLOATER, then delete
8646 the floating insn. */
8647 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8648 delete_insn (floater);
8653 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8656 /* Emit the new_jump instruction and delete the old anchor. */
8658 = emit_jump_insn_before (gen_rtx_PARALLEL
8660 gen_rtvec (2, PATTERN (anchor),
8661 PATTERN (floater))),
8664 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8665 PUT_CODE (anchor, NOTE);
8666 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8667 NOTE_SOURCE_FILE (anchor) = 0;
8669 /* Emit a special USE insn for FLOATER, then delete
8670 the floating insn. */
8671 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8672 delete_insn (floater);
8680 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8683 int insn_code_number;
8686 /* Create a PARALLEL with the patterns of ANCHOR and
8687 FLOATER, try to recognize it, then test constraints
8688 for the resulting pattern.
8690 If the pattern doesn't match or the constraints
8691 aren't met keep searching for a suitable floater
8693 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8694 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8695 INSN_CODE (new) = -1;
8696 insn_code_number = recog_memoized (new);
8697 if (insn_code_number < 0
8698 || (extract_insn (new), ! constrain_operands (1)))
8712 /* There's up to three operands to consider. One
8713 output and two inputs.
8715 The output must not be used between FLOATER & ANCHOR
8716 exclusive. The inputs must not be set between
8717 FLOATER and ANCHOR exclusive. */
8719 if (reg_used_between_p (dest, start, end))
8722 if (reg_set_between_p (src1, start, end))
8725 if (reg_set_between_p (src2, start, end))
8728 /* If we get here, then everything is good. */
8732 /* Return nonzero if references for INSN are delayed.
8734 Millicode insns are actually function calls with some special
8735 constraints on arguments and register usage.
8737 Millicode calls always expect their arguments in the integer argument
8738 registers, and always return their result in %r29 (ret1). They
8739 are expected to clobber their arguments, %r1, %r29, and the return
8740 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8742 This function tells reorg that the references to arguments and
8743 millicode calls do not appear to happen until after the millicode call.
8744 This allows reorg to put insns which set the argument registers into the
8745 delay slot of the millicode call -- thus they act more like traditional
8748 Note we can not consider side effects of the insn to be delayed because
8749 the branch and link insn will clobber the return pointer. If we happened
8750 to use the return pointer in the delay slot of the call, then we lose.
8752 get_attr_type will try to recognize the given insn, so make sure to
8753 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8756 insn_refs_are_delayed (rtx insn)
8758 return ((GET_CODE (insn) == INSN
8759 && GET_CODE (PATTERN (insn)) != SEQUENCE
8760 && GET_CODE (PATTERN (insn)) != USE
8761 && GET_CODE (PATTERN (insn)) != CLOBBER
8762 && get_attr_type (insn) == TYPE_MILLI));
8765 /* On the HP-PA the value is found in register(s) 28(-29), unless
8766 the mode is SF or DF. Then the value is returned in fr4 (32).
8768 This must perform the same promotions as PROMOTE_MODE, else
8769 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8771 Small structures must be returned in a PARALLEL on PA64 in order
8772 to match the HP Compiler ABI. */
8775 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8777 enum machine_mode valmode;
8779 /* Aggregates with a size less than or equal to 128 bits are returned
8780 in GR 28(-29). They are left justified. The pad bits are undefined.
8781 Larger aggregates are returned in memory. */
8782 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
8786 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8788 for (i = 0; i < ub; i++)
8790 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8791 gen_rtx_REG (DImode, 28 + i),
8796 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8799 if ((INTEGRAL_TYPE_P (valtype)
8800 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8801 || POINTER_TYPE_P (valtype))
8802 valmode = word_mode;
8804 valmode = TYPE_MODE (valtype);
8806 if (TREE_CODE (valtype) == REAL_TYPE
8807 && TYPE_MODE (valtype) != TFmode
8808 && !TARGET_SOFT_FLOAT)
8809 return gen_rtx_REG (valmode, 32);
8811 return gen_rtx_REG (valmode, 28);
8814 /* Return the location of a parameter that is passed in a register or NULL
8815 if the parameter has any component that is passed in memory.
8817 This is new code and will be pushed to into the net sources after
8820 ??? We might want to restructure this so that it looks more like other
8823 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8824 int named ATTRIBUTE_UNUSED)
8826 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8833 if (mode == VOIDmode)
8836 arg_size = FUNCTION_ARG_SIZE (mode, type);
8838 /* If this arg would be passed partially or totally on the stack, then
8839 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
8840 handle arguments which are split between regs and stack slots if
8841 the ABI mandates split arguments. */
8844 /* The 32-bit ABI does not split arguments. */
8845 if (cum->words + arg_size > max_arg_words)
8851 alignment = cum->words & 1;
8852 if (cum->words + alignment >= max_arg_words)
8856 /* The 32bit ABIs and the 64bit ABIs are rather different,
8857 particularly in their handling of FP registers. We might
8858 be able to cleverly share code between them, but I'm not
8859 going to bother in the hope that splitting them up results
8860 in code that is more easily understood. */
8864 /* Advance the base registers to their current locations.
8866 Remember, gprs grow towards smaller register numbers while
8867 fprs grow to higher register numbers. Also remember that
8868 although FP regs are 32-bit addressable, we pretend that
8869 the registers are 64-bits wide. */
8870 gpr_reg_base = 26 - cum->words;
8871 fpr_reg_base = 32 + cum->words;
8873 /* Arguments wider than one word and small aggregates need special
8877 || (type && AGGREGATE_TYPE_P (type)))
8879 /* Double-extended precision (80-bit), quad-precision (128-bit)
8880 and aggregates including complex numbers are aligned on
8881 128-bit boundaries. The first eight 64-bit argument slots
8882 are associated one-to-one, with general registers r26
8883 through r19, and also with floating-point registers fr4
8884 through fr11. Arguments larger than one word are always
8885 passed in general registers.
8887 Using a PARALLEL with a word mode register results in left
8888 justified data on a big-endian target. */
8891 int i, offset = 0, ub = arg_size;
8893 /* Align the base register. */
8894 gpr_reg_base -= alignment;
8896 ub = MIN (ub, max_arg_words - cum->words - alignment);
8897 for (i = 0; i < ub; i++)
8899 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8900 gen_rtx_REG (DImode, gpr_reg_base),
8906 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8911 /* If the argument is larger than a word, then we know precisely
8912 which registers we must use. */
8926 /* Structures 5 to 8 bytes in size are passed in the general
8927 registers in the same manner as other non floating-point
8928 objects. The data is right-justified and zero-extended
8931 This is magic. Normally, using a PARALLEL results in left
8932 justified data on a big-endian target. However, using a
8933 single double-word register provides the required right
8934 justification for 5 to 8 byte structures. This has nothing
8935 to do with the direction of padding specified for the argument.
8936 It has to do with how the data is widened and shifted into
8937 and from the register.
8939 Aside from adding load_multiple and store_multiple patterns,
8940 this is the only way that I have found to obtain right
8941 justification of BLKmode data when it has a size greater
8942 than one word. Splitting the operation into two SImode loads
8943 or returning a DImode REG results in left justified data. */
8944 if (mode == BLKmode)
8946 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8947 gen_rtx_REG (DImode, gpr_reg_base),
8949 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
8954 /* We have a single word (32 bits). A simple computation
8955 will get us the register #s we need. */
8956 gpr_reg_base = 26 - cum->words;
8957 fpr_reg_base = 32 + 2 * cum->words;
8961 /* Determine if the argument needs to be passed in both general and
8962 floating point registers. */
8963 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8964 /* If we are doing soft-float with portable runtime, then there
8965 is no need to worry about FP regs. */
8966 && !TARGET_SOFT_FLOAT
8967 /* The parameter must be some kind of float, else we can just
8968 pass it in integer registers. */
8969 && FLOAT_MODE_P (mode)
8970 /* The target function must not have a prototype. */
8971 && cum->nargs_prototype <= 0
8972 /* libcalls do not need to pass items in both FP and general
8974 && type != NULL_TREE
8975 /* All this hair applies to "outgoing" args only. This includes
8976 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8978 /* Also pass outgoing floating arguments in both registers in indirect
8979 calls with the 32 bit ABI and the HP assembler since there is no
8980 way to the specify argument locations in static functions. */
8985 && FLOAT_MODE_P (mode)))
8991 gen_rtx_EXPR_LIST (VOIDmode,
8992 gen_rtx_REG (mode, fpr_reg_base),
8994 gen_rtx_EXPR_LIST (VOIDmode,
8995 gen_rtx_REG (mode, gpr_reg_base),
9000 /* See if we should pass this parameter in a general register. */
9001 if (TARGET_SOFT_FLOAT
9002 /* Indirect calls in the normal 32bit ABI require all arguments
9003 to be passed in general registers. */
9004 || (!TARGET_PORTABLE_RUNTIME
9008 /* If the parameter is not a floating point parameter, then
9009 it belongs in GPRs. */
9010 || !FLOAT_MODE_P (mode))
9011 retval = gen_rtx_REG (mode, gpr_reg_base);
9013 retval = gen_rtx_REG (mode, fpr_reg_base);
9019 /* If this arg would be passed totally in registers or totally on the stack,
9020 then this routine should return zero. It is currently called only for
9021 the 64-bit target. */
9023 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9024 tree type, int named ATTRIBUTE_UNUSED)
9026 unsigned int max_arg_words = 8;
9027 unsigned int offset = 0;
9029 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9032 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9033 /* Arg fits fully into registers. */
9035 else if (cum->words + offset >= max_arg_words)
9036 /* Arg fully on the stack. */
9040 return max_arg_words - cum->words - offset;
9044 /* Return 1 if this is a comparison operator. This allows the use of
9045 MATCH_OPERATOR to recognize all the branch insns. */
9048 cmpib_comparison_operator (rtx op, enum machine_mode mode)
9050 return ((mode == VOIDmode || GET_MODE (op) == mode)
9051 && (GET_CODE (op) == EQ
9052 || GET_CODE (op) == NE
9053 || GET_CODE (op) == GT
9054 || GET_CODE (op) == GTU
9055 || GET_CODE (op) == GE
9056 || GET_CODE (op) == LT
9057 || GET_CODE (op) == LE
9058 || GET_CODE (op) == LEU));
9061 /* On hpux10, the linker will give an error if we have a reference
9062 in the read-only data section to a symbol defined in a shared
9063 library. Therefore, expressions that might require a reloc can
9064 not be placed in the read-only data section. */
9067 pa_select_section (tree exp, int reloc,
9068 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9070 if (TREE_CODE (exp) == VAR_DECL
9071 && TREE_READONLY (exp)
9072 && !TREE_THIS_VOLATILE (exp)
9073 && DECL_INITIAL (exp)
9074 && (DECL_INITIAL (exp) == error_mark_node
9075 || TREE_CONSTANT (DECL_INITIAL (exp)))
9077 readonly_data_section ();
9078 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
9080 readonly_data_section ();
9086 pa_globalize_label (FILE *stream, const char *name)
9088 /* We only handle DATA objects here, functions are globalized in
9089 ASM_DECLARE_FUNCTION_NAME. */
9090 if (! FUNCTION_NAME_P (name))
9092 fputs ("\t.EXPORT ", stream);
9093 assemble_name (stream, name);
9094 fputs (",DATA\n", stream);
9098 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9101 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9102 int incoming ATTRIBUTE_UNUSED)
9104 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9107 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9110 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9112 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9113 PA64 ABI says that objects larger than 128 bits are returned in memory.
9114 Note, int_size_in_bytes can return -1 if the size of the object is
9115 variable or larger than the maximum value that can be expressed as
9116 a HOST_WIDE_INT. It can also return zero for an empty type. The
9117 simplest way to handle variable and empty types is to pass them in
9118 memory. This avoids problems in defining the boundaries of argument
9119 slots, allocating registers, etc. */
9120 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9121 || int_size_in_bytes (type) <= 0);