1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 static void restore_unscaled_index_insn_codes PROTO((rtx));
43 static void record_unscaled_index_insn_codes PROTO((rtx));
44 static void pa_combine_instructions PROTO((rtx));
45 static int pa_can_combine_p PROTO((rtx, rtx, rtx, int, rtx, rtx, rtx));
46 static int forward_branch_p PROTO((rtx));
47 static int shadd_constant_p PROTO((int));
49 /* Save the operands last given to a compare for use when we
50 generate a scc or bcc insn. */
52 rtx hppa_compare_op0, hppa_compare_op1;
53 enum cmp_type hppa_branch_type;
55 /* Which cpu we are scheduling for. */
56 enum processor_type pa_cpu;
58 /* String to hold which cpu we are scheduling for. */
61 /* Which architecture we are generating code for. */
62 enum architecture_type pa_arch;
64 /* String to hold which architecture we are generating code for. */
67 /* Set by the FUNCTION_PROFILER macro. */
68 int hp_profile_labelno;
70 /* Counts for the number of callee-saved general and floating point
71 registers which were saved by the current function's prologue. */
72 static int gr_saved, fr_saved;
74 static rtx find_addr_reg ();
76 /* Keep track of the number of bytes we have output in the CODE subspaces
77 during this compilation so we'll know when to emit inline long-calls. */
79 unsigned int total_code_bytes;
81 /* Variables to handle plabels that we discover are necessary at assembly
82 output time. They are output after the current function. */
84 struct deferred_plabel
88 } *deferred_plabels = 0;
89 int n_deferred_plabels = 0;
91 /* Array indexed by INSN_UIDs holding the INSN_CODE of an insn which
92 uses an unscaled indexed address before delay slot scheduling. */
93 static int *unscaled_index_insn_codes;
95 /* Upper bound for the array. */
96 static int max_unscaled_index_insn_codes_uid;
101 /* Default to 7100LC scheduling. */
102 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
104 pa_cpu_string = "7100";
105 pa_cpu = PROCESSOR_7100;
107 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
109 pa_cpu_string = "700";
110 pa_cpu = PROCESSOR_700;
112 else if (pa_cpu_string == NULL
113 || ! strcmp (pa_cpu_string, "7100LC"))
115 pa_cpu_string = "7100LC";
116 pa_cpu = PROCESSOR_7100LC;
118 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
120 pa_cpu_string = "7200";
121 pa_cpu = PROCESSOR_7200;
123 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "8000"))
125 pa_cpu_string = "8000";
126 pa_cpu = PROCESSOR_8000;
130 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string);
133 /* Set the instruction set architecture. */
134 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
136 pa_arch_string = "1.0";
137 pa_arch = ARCHITECTURE_10;
138 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
140 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
142 pa_arch_string = "1.1";
143 pa_arch = ARCHITECTURE_11;
144 target_flags &= ~MASK_PA_20;
145 target_flags |= MASK_PA_11;
147 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
149 pa_arch_string = "2.0";
150 pa_arch = ARCHITECTURE_20;
151 target_flags |= MASK_PA_11 | MASK_PA_20;
153 else if (pa_arch_string)
155 warning ("Unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
158 if (flag_pic && TARGET_PORTABLE_RUNTIME)
160 warning ("PIC code generation is not supported in the portable runtime model\n");
163 if (flag_pic && (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS))
165 warning ("PIC code generation is not compatible with fast indirect calls\n");
168 if (flag_pic && profile_flag)
170 warning ("PIC code generation is not compatible with profiling\n");
173 if (! TARGET_GAS && write_symbols != NO_DEBUG)
175 warning ("-g is only supported when using GAS on this processor,");
176 warning ("-g option disabled.");
177 write_symbols = NO_DEBUG;
182 /* Return non-zero only if OP is a register of mode MODE,
185 reg_or_0_operand (op, mode)
187 enum machine_mode mode;
189 return (op == CONST0_RTX (mode) || register_operand (op, mode));
192 /* Return non-zero if OP is suitable for use in a call to a named
195 (???) For 2.5 try to eliminate either call_operand_address or
196 function_label_operand, they perform very similar functions. */
198 call_operand_address (op, mode)
200 enum machine_mode mode ATTRIBUTE_UNUSED;
202 return (CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
205 /* Return 1 if X contains a symbolic expression. We know these
206 expressions will have one of a few well defined forms, so
207 we need only check those forms. */
209 symbolic_expression_p (x)
213 /* Strip off any HIGH. */
214 if (GET_CODE (x) == HIGH)
217 return (symbolic_operand (x, VOIDmode));
221 symbolic_operand (op, mode)
223 enum machine_mode mode ATTRIBUTE_UNUSED;
225 switch (GET_CODE (op))
232 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
233 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
234 && GET_CODE (XEXP (op, 1)) == CONST_INT);
240 /* Return truth value of statement that OP is a symbolic memory
241 operand of mode MODE. */
244 symbolic_memory_operand (op, mode)
246 enum machine_mode mode ATTRIBUTE_UNUSED;
248 if (GET_CODE (op) == SUBREG)
249 op = SUBREG_REG (op);
250 if (GET_CODE (op) != MEM)
253 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
254 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
257 /* Return 1 if the operand is either a register or a memory operand that is
261 reg_or_nonsymb_mem_operand (op, mode)
263 enum machine_mode mode;
265 if (register_operand (op, mode))
268 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
274 /* Return 1 if the operand is either a register, zero, or a memory operand
275 that is not symbolic. */
278 reg_or_0_or_nonsymb_mem_operand (op, mode)
280 enum machine_mode mode;
282 if (register_operand (op, mode))
285 if (op == CONST0_RTX (mode))
288 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
294 /* Accept any constant that can be moved in one instructions into a
297 cint_ok_for_move (intval)
298 HOST_WIDE_INT intval;
300 /* OK if ldo, ldil, or zdepi, can be used. */
301 return (VAL_14_BITS_P (intval) || (intval & 0x7ff) == 0
302 || zdepi_cint_p (intval));
305 /* Accept anything that can be moved in one instruction into a general
308 move_operand (op, mode)
310 enum machine_mode mode;
312 if (register_operand (op, mode))
315 if (GET_CODE (op) == CONSTANT_P_RTX)
318 if (GET_CODE (op) == CONST_INT)
319 return cint_ok_for_move (INTVAL (op));
321 if (GET_CODE (op) == SUBREG)
322 op = SUBREG_REG (op);
323 if (GET_CODE (op) != MEM)
327 if (GET_CODE (op) == LO_SUM)
328 return (register_operand (XEXP (op, 0), Pmode)
329 && CONSTANT_P (XEXP (op, 1)));
331 /* Since move_operand is only used for source operands, we can always
332 allow scaled indexing! */
333 if (! TARGET_DISABLE_INDEXING
334 && GET_CODE (op) == PLUS
335 && ((GET_CODE (XEXP (op, 0)) == MULT
336 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
337 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
338 && INTVAL (XEXP (XEXP (op, 0), 1)) == GET_MODE_SIZE (mode)
339 && GET_CODE (XEXP (op, 1)) == REG)
340 || (GET_CODE (XEXP (op, 1)) == MULT
341 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
342 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
343 && INTVAL (XEXP (XEXP (op, 1), 1)) == GET_MODE_SIZE (mode)
344 && GET_CODE (XEXP (op, 0)) == REG)))
347 return memory_address_p (mode, op);
350 /* Accept REG and any CONST_INT that can be moved in one instruction into a
353 reg_or_cint_move_operand (op, mode)
355 enum machine_mode mode;
357 if (register_operand (op, mode))
360 if (GET_CODE (op) == CONST_INT)
361 return cint_ok_for_move (INTVAL (op));
367 pic_label_operand (op, mode)
369 enum machine_mode mode ATTRIBUTE_UNUSED;
374 switch (GET_CODE (op))
380 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
381 && GET_CODE (XEXP (op, 1)) == CONST_INT);
388 fp_reg_operand (op, mode)
390 enum machine_mode mode ATTRIBUTE_UNUSED;
392 return reg_renumber && FP_REG_P (op);
397 /* Return truth value of whether OP can be used as an operand in a
398 three operand arithmetic insn that accepts registers of mode MODE
399 or 14-bit signed integers. */
401 arith_operand (op, mode)
403 enum machine_mode mode;
405 return (register_operand (op, mode)
406 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
409 /* Return truth value of whether OP can be used as an operand in a
410 three operand arithmetic insn that accepts registers of mode MODE
411 or 11-bit signed integers. */
413 arith11_operand (op, mode)
415 enum machine_mode mode;
417 return (register_operand (op, mode)
418 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
421 /* A constant integer suitable for use in a PRE_MODIFY memory
424 pre_cint_operand (op, mode)
426 enum machine_mode mode ATTRIBUTE_UNUSED;
428 return (GET_CODE (op) == CONST_INT
429 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
432 /* A constant integer suitable for use in a POST_MODIFY memory
435 post_cint_operand (op, mode)
437 enum machine_mode mode ATTRIBUTE_UNUSED;
439 return (GET_CODE (op) == CONST_INT
440 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
444 arith_double_operand (op, mode)
446 enum machine_mode mode;
448 return (register_operand (op, mode)
449 || (GET_CODE (op) == CONST_DOUBLE
450 && GET_MODE (op) == mode
451 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
452 && ((CONST_DOUBLE_HIGH (op) >= 0)
453 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
456 /* Return truth value of whether OP is a integer which fits the
457 range constraining immediate operands in three-address insns, or
458 is an integer register. */
461 ireg_or_int5_operand (op, mode)
463 enum machine_mode mode ATTRIBUTE_UNUSED;
465 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
466 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
469 /* Return truth value of whether OP is a integer which fits the
470 range constraining immediate operands in three-address insns. */
473 int5_operand (op, mode)
475 enum machine_mode mode ATTRIBUTE_UNUSED;
477 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
481 uint5_operand (op, mode)
483 enum machine_mode mode ATTRIBUTE_UNUSED;
485 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
489 int11_operand (op, mode)
491 enum machine_mode mode ATTRIBUTE_UNUSED;
493 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
497 uint32_operand (op, mode)
499 enum machine_mode mode ATTRIBUTE_UNUSED;
501 #if HOST_BITS_PER_WIDE_INT > 32
502 /* All allowed constants will fit a CONST_INT. */
503 return (GET_CODE (op) == CONST_INT
504 && (INTVAL (op) >= 0 && INTVAL (op) < 0x100000000L));
506 return (GET_CODE (op) == CONST_INT
507 || (GET_CODE (op) == CONST_DOUBLE
508 && CONST_DOUBLE_HIGH (op) == 0));
513 arith5_operand (op, mode)
515 enum machine_mode mode;
517 return register_operand (op, mode) || int5_operand (op, mode);
520 /* True iff zdepi can be used to generate this CONST_INT. */
523 unsigned HOST_WIDE_INT x;
525 unsigned HOST_WIDE_INT lsb_mask, t;
527 /* This might not be obvious, but it's at least fast.
528 This function is critical; we don't have the time loops would take. */
530 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
531 /* Return true iff t is a power of two. */
532 return ((t & (t - 1)) == 0);
535 /* True iff depi or extru can be used to compute (reg & mask).
536 Accept bit pattern like these:
542 unsigned HOST_WIDE_INT mask;
545 mask += mask & -mask;
546 return (mask & (mask - 1)) == 0;
549 /* True iff depi or extru can be used to compute (reg & OP). */
551 and_operand (op, mode)
553 enum machine_mode mode;
555 return (register_operand (op, mode)
556 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
559 /* True iff depi can be used to compute (reg | MASK). */
562 unsigned HOST_WIDE_INT mask;
564 mask += mask & -mask;
565 return (mask & (mask - 1)) == 0;
568 /* True iff depi can be used to compute (reg | OP). */
570 ior_operand (op, mode)
572 enum machine_mode mode ATTRIBUTE_UNUSED;
574 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
578 lhs_lshift_operand (op, mode)
580 enum machine_mode mode;
582 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
585 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
586 Such values can be the left hand side x in (x << r), using the zvdepi
589 lhs_lshift_cint_operand (op, mode)
591 enum machine_mode mode ATTRIBUTE_UNUSED;
593 unsigned HOST_WIDE_INT x;
594 if (GET_CODE (op) != CONST_INT)
596 x = INTVAL (op) >> 4;
597 return (x & (x + 1)) == 0;
601 arith32_operand (op, mode)
603 enum machine_mode mode;
605 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
609 pc_or_label_operand (op, mode)
611 enum machine_mode mode ATTRIBUTE_UNUSED;
613 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
616 /* Legitimize PIC addresses. If the address is already
617 position-independent, we return ORIG. Newly generated
618 position-independent addresses go to REG. If we need more
619 than one register, we lose. */
622 legitimize_pic_address (orig, mode, reg)
624 enum machine_mode mode ATTRIBUTE_UNUSED;
628 /* Labels need special handling. */
629 if (pic_label_operand (orig))
631 emit_insn (gen_pic_load_label (reg, orig));
632 current_function_uses_pic_offset_table = 1;
635 if (GET_CODE (orig) == SYMBOL_REF)
642 emit_insn (gen_pic2_highpart (reg, pic_offset_table_rtx, orig));
644 = gen_rtx_MEM (Pmode,
645 gen_rtx_LO_SUM (Pmode, reg,
646 gen_rtx_UNSPEC (SImode,
651 pic_ref = gen_rtx_MEM (Pmode,
653 pic_offset_table_rtx, orig));
654 current_function_uses_pic_offset_table = 1;
655 RTX_UNCHANGING_P (pic_ref) = 1;
656 emit_move_insn (reg, pic_ref);
659 else if (GET_CODE (orig) == CONST)
663 if (GET_CODE (XEXP (orig, 0)) == PLUS
664 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
670 if (GET_CODE (XEXP (orig, 0)) == PLUS)
672 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
673 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
674 base == reg ? 0 : reg);
677 if (GET_CODE (orig) == CONST_INT)
679 if (INT_14_BITS (orig))
680 return plus_constant_for_output (base, INTVAL (orig));
681 orig = force_reg (Pmode, orig);
683 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
684 /* Likewise, should we set special REG_NOTEs here? */
689 /* Try machine-dependent ways of modifying an illegitimate address
690 to be legitimate. If we find one, return the new, valid address.
691 This macro is used in only one place: `memory_address' in explow.c.
693 OLDX is the address as it was before break_out_memory_refs was called.
694 In some cases it is useful to look at this to decide what needs to be done.
696 MODE and WIN are passed so that this macro can use
697 GO_IF_LEGITIMATE_ADDRESS.
699 It is always safe for this macro to do nothing. It exists to recognize
700 opportunities to optimize the output.
702 For the PA, transform:
704 memory(X + <large int>)
708 if (<large int> & mask) >= 16
709 Y = (<large int> & ~mask) + mask + 1 Round up.
711 Y = (<large int> & ~mask) Round down.
713 memory (Z + (<large int> - Y));
715 This is for CSE to find several similar references, and only use one Z.
717 X can either be a SYMBOL_REF or REG, but because combine can not
718 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
719 D will not fit in 14 bits.
721 MODE_FLOAT references allow displacements which fit in 5 bits, so use
724 MODE_INT references allow displacements which fit in 14 bits, so use
727 This relies on the fact that most mode MODE_FLOAT references will use FP
728 registers and most mode MODE_INT references will use integer registers.
729 (In the rare case of an FP register used in an integer MODE, we depend
730 on secondary reloads to clean things up.)
733 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
734 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
735 addressing modes to be used).
737 Put X and Z into registers. Then put the entire expression into
741 hppa_legitimize_address (x, oldx, mode)
742 rtx x, oldx ATTRIBUTE_UNUSED;
743 enum machine_mode mode;
748 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
750 /* Strip off CONST. */
751 if (GET_CODE (x) == CONST)
754 /* Special case. Get the SYMBOL_REF into a register and use indexing.
755 That should always be safe. */
756 if (GET_CODE (x) == PLUS
757 && GET_CODE (XEXP (x, 0)) == REG
758 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
760 rtx reg = force_reg (SImode, XEXP (x, 1));
761 return force_reg (SImode, gen_rtx_PLUS (SImode, reg, XEXP (x, 0)));
764 /* Note we must reject symbols which represent function addresses
765 since the assembler/linker can't handle arithmetic on plabels. */
766 if (GET_CODE (x) == PLUS
767 && GET_CODE (XEXP (x, 1)) == CONST_INT
768 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
769 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
770 || GET_CODE (XEXP (x, 0)) == REG))
772 rtx int_part, ptr_reg;
774 int offset = INTVAL (XEXP (x, 1));
775 int mask = GET_MODE_CLASS (mode) == MODE_FLOAT ? 0x1f : 0x3fff;
777 /* Choose which way to round the offset. Round up if we
778 are >= halfway to the next boundary. */
779 if ((offset & mask) >= ((mask + 1) / 2))
780 newoffset = (offset & ~ mask) + mask + 1;
782 newoffset = (offset & ~ mask);
784 /* If the newoffset will not fit in 14 bits (ldo), then
785 handling this would take 4 or 5 instructions (2 to load
786 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
787 add the new offset and the SYMBOL_REF.) Combine can
788 not handle 4->2 or 5->2 combinations, so do not create
790 if (! VAL_14_BITS_P (newoffset)
791 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
794 = gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (Pmode,
796 GEN_INT (newoffset)));
799 gen_rtx_HIGH (Pmode, const_part));
802 gen_rtx_LO_SUM (Pmode, tmp_reg, const_part));
806 if (! VAL_14_BITS_P (newoffset))
807 int_part = force_reg (Pmode, GEN_INT (newoffset));
809 int_part = GEN_INT (newoffset);
811 ptr_reg = force_reg (Pmode,
813 force_reg (Pmode, XEXP (x, 0)),
816 return plus_constant (ptr_reg, offset - newoffset);
819 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
821 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
822 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
823 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
824 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
825 || GET_CODE (XEXP (x, 1)) == SUBREG)
826 && GET_CODE (XEXP (x, 1)) != CONST)
828 int val = INTVAL (XEXP (XEXP (x, 0), 1));
832 if (GET_CODE (reg1) != REG)
833 reg1 = force_reg (Pmode, force_operand (reg1, 0));
835 reg2 = XEXP (XEXP (x, 0), 0);
836 if (GET_CODE (reg2) != REG)
837 reg2 = force_reg (Pmode, force_operand (reg2, 0));
839 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
840 gen_rtx_MULT (Pmode, reg2,
845 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
847 Only do so for floating point modes since this is more speculative
848 and we lose if it's an integer store. */
849 if (GET_CODE (x) == PLUS
850 && GET_CODE (XEXP (x, 0)) == PLUS
851 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
852 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
853 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
854 && (mode == SFmode || mode == DFmode))
857 /* First, try and figure out what to use as a base register. */
858 rtx reg1, reg2, base, idx, orig_base;
860 reg1 = XEXP (XEXP (x, 0), 1);
865 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
866 then emit_move_sequence will turn on REGNO_POINTER_FLAG so we'll
867 know it's a base register below. */
868 if (GET_CODE (reg1) != REG)
869 reg1 = force_reg (Pmode, force_operand (reg1, 0));
871 if (GET_CODE (reg2) != REG)
872 reg2 = force_reg (Pmode, force_operand (reg2, 0));
874 /* Figure out what the base and index are. */
876 if (GET_CODE (reg1) == REG
877 && REGNO_POINTER_FLAG (REGNO (reg1)))
880 orig_base = XEXP (XEXP (x, 0), 1);
881 idx = gen_rtx_PLUS (Pmode,
883 XEXP (XEXP (XEXP (x, 0), 0), 0),
884 XEXP (XEXP (XEXP (x, 0), 0), 1)),
887 else if (GET_CODE (reg2) == REG
888 && REGNO_POINTER_FLAG (REGNO (reg2)))
891 orig_base = XEXP (x, 1);
898 /* If the index adds a large constant, try to scale the
899 constant so that it can be loaded with only one insn. */
900 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
901 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
902 / INTVAL (XEXP (XEXP (idx, 0), 1)))
903 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
905 /* Divide the CONST_INT by the scale factor, then add it to A. */
906 int val = INTVAL (XEXP (idx, 1));
908 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
909 reg1 = XEXP (XEXP (idx, 0), 0);
910 if (GET_CODE (reg1) != REG)
911 reg1 = force_reg (Pmode, force_operand (reg1, 0));
913 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
915 /* We can now generate a simple scaled indexed address. */
916 return force_reg (Pmode,
918 gen_rtx_MULT (Pmode, reg1,
919 XEXP (XEXP (idx, 0), 1)),
923 /* If B + C is still a valid base register, then add them. */
924 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
925 && INTVAL (XEXP (idx, 1)) <= 4096
926 && INTVAL (XEXP (idx, 1)) >= -4096)
928 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
931 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
933 reg2 = XEXP (XEXP (idx, 0), 0);
934 if (GET_CODE (reg2) != CONST_INT)
935 reg2 = force_reg (Pmode, force_operand (reg2, 0));
937 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
938 gen_rtx_MULT (Pmode, reg2,
943 /* Get the index into a register, then add the base + index and
944 return a register holding the result. */
946 /* First get A into a register. */
947 reg1 = XEXP (XEXP (idx, 0), 0);
948 if (GET_CODE (reg1) != REG)
949 reg1 = force_reg (Pmode, force_operand (reg1, 0));
951 /* And get B into a register. */
952 reg2 = XEXP (idx, 1);
953 if (GET_CODE (reg2) != REG)
954 reg2 = force_reg (Pmode, force_operand (reg2, 0));
956 reg1 = force_reg (Pmode,
958 gen_rtx_MULT (Pmode, reg1,
959 XEXP (XEXP (idx, 0), 1)),
962 /* Add the result to our base register and return. */
963 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
967 /* Uh-oh. We might have an address for x[n-100000]. This needs
968 special handling to avoid creating an indexed memory address
969 with x-100000 as the base.
971 If the constant part is small enough, then it's still safe because
972 there is a guard page at the beginning and end of the data segment.
974 Scaled references are common enough that we want to try and rearrange the
975 terms so that we can use indexing for these addresses too. Only
976 do the optimization for floatint point modes. */
978 if (GET_CODE (x) == PLUS
979 && symbolic_expression_p (XEXP (x, 1)))
981 /* Ugly. We modify things here so that the address offset specified
982 by the index expression is computed first, then added to x to form
983 the entire address. */
985 rtx regx1, regx2, regy1, regy2, y;
987 /* Strip off any CONST. */
989 if (GET_CODE (y) == CONST)
992 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
994 /* See if this looks like
995 (plus (mult (reg) (shadd_const))
996 (const (plus (symbol_ref) (const_int))))
998 Where const_int is small. In that case the const
999 expression is a valid pointer for indexing.
1001 If const_int is big, but can be divided evenly by shadd_const
1002 and added to (reg). This allows more scaled indexed addresses. */
1003 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1004 && GET_CODE (XEXP (x, 0)) == MULT
1005 && GET_CODE (XEXP (y, 1)) == CONST_INT
1006 && INTVAL (XEXP (y, 1)) >= -4096
1007 && INTVAL (XEXP (y, 1)) <= 4095
1008 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1009 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1011 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1015 if (GET_CODE (reg1) != REG)
1016 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1018 reg2 = XEXP (XEXP (x, 0), 0);
1019 if (GET_CODE (reg2) != REG)
1020 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1022 return force_reg (Pmode,
1023 gen_rtx_PLUS (Pmode,
1024 gen_rtx_MULT (Pmode, reg2,
1028 else if ((mode == DFmode || mode == SFmode)
1029 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1030 && GET_CODE (XEXP (x, 0)) == MULT
1031 && GET_CODE (XEXP (y, 1)) == CONST_INT
1032 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1033 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1034 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1037 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1038 / INTVAL (XEXP (XEXP (x, 0), 1))));
1039 regx2 = XEXP (XEXP (x, 0), 0);
1040 if (GET_CODE (regx2) != REG)
1041 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1042 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1044 return force_reg (Pmode,
1045 gen_rtx_PLUS (Pmode,
1046 gen_rtx_MULT (Pmode, regx2,
1049 force_reg (Pmode, XEXP (y, 0))));
1051 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1052 && INTVAL (XEXP (y, 1)) >= -4096
1053 && INTVAL (XEXP (y, 1)) <= 4095)
1055 /* This is safe because of the guard page at the
1056 beginning and end of the data space. Just
1057 return the original address. */
1062 /* Doesn't look like one we can optimize. */
1063 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1064 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1065 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1066 regx1 = force_reg (Pmode,
1067 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1069 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1077 /* For the HPPA, REG and REG+CONST is cost 0
1078 and addresses involving symbolic constants are cost 2.
1080 PIC addresses are very expensive.
1082 It is no coincidence that this has the same structure
1083 as GO_IF_LEGITIMATE_ADDRESS. */
1085 hppa_address_cost (X)
1088 if (GET_CODE (X) == PLUS)
1090 else if (GET_CODE (X) == LO_SUM)
1092 else if (GET_CODE (X) == HIGH)
1097 /* Emit insns to move operands[1] into operands[0].
1099 Return 1 if we have written out everything that needs to be done to
1100 do the move. Otherwise, return 0 and the caller will emit the move
1104 emit_move_sequence (operands, mode, scratch_reg)
1106 enum machine_mode mode;
1109 register rtx operand0 = operands[0];
1110 register rtx operand1 = operands[1];
1114 && reload_in_progress && GET_CODE (operand0) == REG
1115 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1116 operand0 = reg_equiv_mem[REGNO (operand0)];
1117 else if (scratch_reg
1118 && reload_in_progress && GET_CODE (operand0) == SUBREG
1119 && GET_CODE (SUBREG_REG (operand0)) == REG
1120 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1122 SUBREG_REG (operand0) = reg_equiv_mem[REGNO (SUBREG_REG (operand0))];
1123 operand0 = alter_subreg (operand0);
1127 && reload_in_progress && GET_CODE (operand1) == REG
1128 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1129 operand1 = reg_equiv_mem[REGNO (operand1)];
1130 else if (scratch_reg
1131 && reload_in_progress && GET_CODE (operand1) == SUBREG
1132 && GET_CODE (SUBREG_REG (operand1)) == REG
1133 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1135 SUBREG_REG (operand1) = reg_equiv_mem[REGNO (SUBREG_REG (operand1))];
1136 operand1 = alter_subreg (operand1);
1139 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1140 && ((tem = find_replacement (&XEXP (operand0, 0)))
1141 != XEXP (operand0, 0)))
1142 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1143 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1144 && ((tem = find_replacement (&XEXP (operand1, 0)))
1145 != XEXP (operand1, 0)))
1146 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1148 /* Handle secondary reloads for loads/stores of FP registers from
1149 REG+D addresses where D does not fit in 5 bits, including
1150 (subreg (mem (addr))) cases. */
1151 if (fp_reg_operand (operand0, mode)
1152 && ((GET_CODE (operand1) == MEM
1153 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1154 || ((GET_CODE (operand1) == SUBREG
1155 && GET_CODE (XEXP (operand1, 0)) == MEM
1156 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1159 if (GET_CODE (operand1) == SUBREG)
1160 operand1 = XEXP (operand1, 0);
1162 scratch_reg = gen_rtx_REG (SImode, REGNO (scratch_reg));
1164 /* D might not fit in 14 bits either; for such cases load D into
1166 if (!memory_address_p (SImode, XEXP (operand1, 0)))
1168 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1169 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1171 XEXP (XEXP (operand1, 0), 0),
1175 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1176 emit_insn (gen_rtx_SET (VOIDmode, operand0, gen_rtx_MEM (mode,
1180 else if (fp_reg_operand (operand1, mode)
1181 && ((GET_CODE (operand0) == MEM
1182 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1183 || ((GET_CODE (operand0) == SUBREG)
1184 && GET_CODE (XEXP (operand0, 0)) == MEM
1185 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1188 if (GET_CODE (operand0) == SUBREG)
1189 operand0 = XEXP (operand0, 0);
1191 scratch_reg = gen_rtx_REG (SImode, REGNO (scratch_reg));
1192 /* D might not fit in 14 bits either; for such cases load D into
1194 if (!memory_address_p (SImode, XEXP (operand0, 0)))
1196 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1197 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1200 XEXP (XEXP (operand0, 0),
1205 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1206 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1210 /* Handle secondary reloads for loads of FP registers from constant
1211 expressions by forcing the constant into memory.
1213 use scratch_reg to hold the address of the memory location.
1215 ??? The proper fix is to change PREFERRED_RELOAD_CLASS to return
1216 NO_REGS when presented with a const_int and an register class
1217 containing only FP registers. Doing so unfortunately creates
1218 more problems than it solves. Fix this for 2.5. */
1219 else if (fp_reg_operand (operand0, mode)
1220 && CONSTANT_P (operand1)
1225 /* Force the constant into memory and put the address of the
1226 memory location into scratch_reg. */
1227 xoperands[0] = scratch_reg;
1228 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1229 emit_move_sequence (xoperands, Pmode, 0);
1231 /* Now load the destination register. */
1232 emit_insn (gen_rtx_SET (mode, operand0, gen_rtx_MEM (mode, scratch_reg)));
1235 /* Handle secondary reloads for SAR. These occur when trying to load
1236 the SAR from memory a FP register, or with a constant. */
1237 else if (GET_CODE (operand0) == REG
1238 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1239 && (GET_CODE (operand1) == MEM
1240 || GET_CODE (operand1) == CONST_INT
1241 || (GET_CODE (operand1) == REG
1242 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1245 /* D might not fit in 14 bits either; for such cases load D into
1247 if (GET_CODE (operand1) == MEM
1248 && !memory_address_p (SImode, XEXP (operand1, 0)))
1250 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1251 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1254 XEXP (XEXP (operand1, 0),
1257 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand1),
1261 emit_move_insn (scratch_reg, operand1);
1262 emit_move_insn (operand0, scratch_reg);
1265 /* Handle most common case: storing into a register. */
1266 else if (register_operand (operand0, mode))
1268 if (register_operand (operand1, mode)
1269 || (GET_CODE (operand1) == CONST_INT && INT_14_BITS (operand1))
1270 || (operand1 == CONST0_RTX (mode))
1271 || (GET_CODE (operand1) == HIGH
1272 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1273 /* Only `general_operands' can come here, so MEM is ok. */
1274 || GET_CODE (operand1) == MEM)
1276 /* Run this case quickly. */
1277 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1281 else if (GET_CODE (operand0) == MEM)
1283 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1284 && !(reload_in_progress || reload_completed))
1286 rtx temp = gen_reg_rtx (DFmode);
1288 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1289 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1292 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1294 /* Run this case quickly. */
1295 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1298 if (! (reload_in_progress || reload_completed))
1300 operands[0] = validize_mem (operand0);
1301 operands[1] = operand1 = force_reg (mode, operand1);
1305 /* Simplify the source if we need to.
1306 Note we do have to handle function labels here, even though we do
1307 not consider them legitimate constants. Loop optimizations can
1308 call the emit_move_xxx with one as a source. */
1309 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1310 || function_label_operand (operand1, mode)
1311 || (GET_CODE (operand1) == HIGH
1312 && symbolic_operand (XEXP (operand1, 0), mode)))
1316 if (GET_CODE (operand1) == HIGH)
1319 operand1 = XEXP (operand1, 0);
1321 if (symbolic_operand (operand1, mode))
1323 /* Argh. The assembler and linker can't handle arithmetic
1326 So we force the plabel into memory, load operand0 from
1327 the memory location, then add in the constant part. */
1328 if ((GET_CODE (operand1) == CONST
1329 && GET_CODE (XEXP (operand1, 0)) == PLUS
1330 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1331 || function_label_operand (operand1, mode))
1333 rtx temp, const_part;
1335 /* Figure out what (if any) scratch register to use. */
1336 if (reload_in_progress || reload_completed)
1337 scratch_reg = scratch_reg ? scratch_reg : operand0;
1339 scratch_reg = gen_reg_rtx (Pmode);
1341 if (GET_CODE (operand1) == CONST)
1343 /* Save away the constant part of the expression. */
1344 const_part = XEXP (XEXP (operand1, 0), 1);
1345 if (GET_CODE (const_part) != CONST_INT)
1348 /* Force the function label into memory. */
1349 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1353 /* No constant part. */
1354 const_part = NULL_RTX;
1356 /* Force the function label into memory. */
1357 temp = force_const_mem (mode, operand1);
1361 /* Get the address of the memory location. PIC-ify it if
1363 temp = XEXP (temp, 0);
1365 temp = legitimize_pic_address (temp, mode, scratch_reg);
1367 /* Put the address of the memory location into our destination
1370 emit_move_sequence (operands, mode, scratch_reg);
1372 /* Now load from the memory location into our destination
1374 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1375 emit_move_sequence (operands, mode, scratch_reg);
1377 /* And add back in the constant part. */
1378 if (const_part != NULL_RTX)
1379 expand_inc (operand0, const_part);
1388 if (reload_in_progress || reload_completed)
1389 temp = scratch_reg ? scratch_reg : operand0;
1391 temp = gen_reg_rtx (Pmode);
1393 /* (const (plus (symbol) (const_int))) must be forced to
1394 memory during/after reload if the const_int will not fit
1396 if (GET_CODE (operand1) == CONST
1397 && GET_CODE (XEXP (operand1, 0)) == PLUS
1398 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1399 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1400 && (reload_completed || reload_in_progress)
1403 operands[1] = force_const_mem (mode, operand1);
1404 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1406 emit_move_sequence (operands, mode, temp);
1410 operands[1] = legitimize_pic_address (operand1, mode, temp);
1411 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1414 /* On the HPPA, references to data space are supposed to use dp,
1415 register 27, but showing it in the RTL inhibits various cse
1416 and loop optimizations. */
1421 if (reload_in_progress || reload_completed)
1422 temp = scratch_reg ? scratch_reg : operand0;
1424 temp = gen_reg_rtx (mode);
1426 /* Loading a SYMBOL_REF into a register makes that register
1427 safe to be used as the base in an indexed address.
1429 Don't mark hard registers though. That loses. */
1430 if (GET_CODE (operand0) == REG
1431 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1432 REGNO_POINTER_FLAG (REGNO (operand0)) = 1;
1433 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1434 REGNO_POINTER_FLAG (REGNO (temp)) = 1;
1436 set = gen_rtx_SET (mode, operand0, temp);
1438 set = gen_rtx_SET (VOIDmode, operand0,
1439 gen_rtx_LO_SUM (mode, temp, operand1));
1441 emit_insn (gen_rtx_SET (VOIDmode,
1443 gen_rtx_HIGH (mode, operand1)));
1449 else if (GET_CODE (operand1) != CONST_INT
1450 || ! cint_ok_for_move (INTVAL (operand1)))
1454 if (reload_in_progress || reload_completed)
1457 temp = gen_reg_rtx (mode);
1459 emit_insn (gen_rtx_SET (VOIDmode, temp,
1460 gen_rtx_HIGH (mode, operand1)));
1461 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1464 /* Now have insn-emit do whatever it normally does. */
1468 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1469 it will need a link/runtime reloc). */
1477 switch (TREE_CODE (exp))
1484 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1485 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1490 case NON_LVALUE_EXPR:
1491 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1497 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1498 if (TREE_VALUE (link) != 0)
1499 reloc |= reloc_needed (TREE_VALUE (link));
1512 /* Does operand (which is a symbolic_operand) live in text space? If
1513 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1516 read_only_operand (operand)
1519 if (GET_CODE (operand) == CONST)
1520 operand = XEXP (XEXP (operand, 0), 0);
1523 if (GET_CODE (operand) == SYMBOL_REF)
1524 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1528 if (GET_CODE (operand) == SYMBOL_REF)
1529 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1535 /* Return the best assembler insn template
1536 for moving operands[1] into operands[0] as a fullword. */
1538 singlemove_string (operands)
1541 HOST_WIDE_INT intval;
1543 if (GET_CODE (operands[0]) == MEM)
1544 return "stw %r1,%0";
1545 if (GET_CODE (operands[1]) == MEM)
1547 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1552 if (GET_MODE (operands[1]) != SFmode)
1555 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1557 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1558 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1560 operands[1] = GEN_INT (i);
1561 /* Fall through to CONST_INT case. */
1563 if (GET_CODE (operands[1]) == CONST_INT)
1565 intval = INTVAL (operands[1]);
1567 if (VAL_14_BITS_P (intval))
1569 else if ((intval & 0x7ff) == 0)
1570 return "ldil L'%1,%0";
1571 else if (zdepi_cint_p (intval))
1572 return "zdepi %Z1,%0";
1574 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1576 return "copy %1,%0";
1580 /* Compute position (in OP[1]) and width (in OP[2])
1581 useful for copying IMM to a register using the zdepi
1582 instructions. Store the immediate value to insert in OP[0]. */
1584 compute_zdepi_operands (imm, op)
1585 unsigned HOST_WIDE_INT imm;
1590 /* Find the least significant set bit in IMM. */
1591 for (lsb = 0; lsb < 32; lsb++)
1598 /* Choose variants based on *sign* of the 5-bit field. */
1599 if ((imm & 0x10) == 0)
1600 len = (lsb <= 28) ? 4 : 32 - lsb;
1603 /* Find the width of the bitstring in IMM. */
1604 for (len = 5; len < 32; len++)
1606 if ((imm & (1 << len)) == 0)
1610 /* Sign extend IMM as a 5-bit value. */
1611 imm = (imm & 0xf) - 0x10;
1619 /* Output assembler code to perform a doubleword move insn
1620 with operands OPERANDS. */
1623 output_move_double (operands)
1626 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1628 rtx addreg0 = 0, addreg1 = 0;
1630 /* First classify both operands. */
1632 if (REG_P (operands[0]))
1634 else if (offsettable_memref_p (operands[0]))
1636 else if (GET_CODE (operands[0]) == MEM)
1641 if (REG_P (operands[1]))
1643 else if (CONSTANT_P (operands[1]))
1645 else if (offsettable_memref_p (operands[1]))
1647 else if (GET_CODE (operands[1]) == MEM)
1652 /* Check for the cases that the operand constraints are not
1653 supposed to allow to happen. Abort if we get one,
1654 because generating code for these cases is painful. */
1656 if (optype0 != REGOP && optype1 != REGOP)
1659 /* Handle auto decrementing and incrementing loads and stores
1660 specifically, since the structure of the function doesn't work
1661 for them without major modification. Do it better when we learn
1662 this port about the general inc/dec addressing of PA.
1663 (This was written by tege. Chide him if it doesn't work.) */
1665 if (optype0 == MEMOP)
1667 /* We have to output the address syntax ourselves, since print_operand
1668 doesn't deal with the addresses we want to use. Fix this later. */
1670 rtx addr = XEXP (operands[0], 0);
1671 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1673 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1675 operands[0] = XEXP (addr, 0);
1676 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1679 if (!reg_overlap_mentioned_p (high_reg, addr))
1681 /* No overlap between high target register and address
1682 register. (We do this in a non-obvious way to
1683 save a register file writeback) */
1684 if (GET_CODE (addr) == POST_INC)
1685 return "stws,ma %1,8(%0)\n\tstw %R1,-4(%0)";
1686 return "stws,ma %1,-8(%0)\n\tstw %R1,12(%0)";
1691 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1693 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1695 operands[0] = XEXP (addr, 0);
1696 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1699 if (!reg_overlap_mentioned_p (high_reg, addr))
1701 /* No overlap between high target register and address
1702 register. (We do this in a non-obvious way to
1703 save a register file writeback) */
1704 if (GET_CODE (addr) == PRE_INC)
1705 return "stws,mb %1,8(%0)\n\tstw %R1,4(%0)";
1706 return "stws,mb %1,-8(%0)\n\tstw %R1,4(%0)";
1712 if (optype1 == MEMOP)
1714 /* We have to output the address syntax ourselves, since print_operand
1715 doesn't deal with the addresses we want to use. Fix this later. */
1717 rtx addr = XEXP (operands[1], 0);
1718 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1720 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1722 operands[1] = XEXP (addr, 0);
1723 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1726 if (!reg_overlap_mentioned_p (high_reg, addr))
1728 /* No overlap between high target register and address
1729 register. (We do this in a non-obvious way to
1730 save a register file writeback) */
1731 if (GET_CODE (addr) == POST_INC)
1732 return "ldws,ma 8(%1),%0\n\tldw -4(%1),%R0";
1733 return "ldws,ma -8(%1),%0\n\tldw 12(%1),%R0";
1737 /* This is an undefined situation. We should load into the
1738 address register *and* update that register. Probably
1739 we don't need to handle this at all. */
1740 if (GET_CODE (addr) == POST_INC)
1741 return "ldw 4(%1),%R0\n\tldws,ma 8(%1),%0";
1742 return "ldw 4(%1),%R0\n\tldws,ma -8(%1),%0";
1745 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1747 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1749 operands[1] = XEXP (addr, 0);
1750 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1753 if (!reg_overlap_mentioned_p (high_reg, addr))
1755 /* No overlap between high target register and address
1756 register. (We do this in a non-obvious way to
1757 save a register file writeback) */
1758 if (GET_CODE (addr) == PRE_INC)
1759 return "ldws,mb 8(%1),%0\n\tldw 4(%1),%R0";
1760 return "ldws,mb -8(%1),%0\n\tldw 4(%1),%R0";
1764 /* This is an undefined situation. We should load into the
1765 address register *and* update that register. Probably
1766 we don't need to handle this at all. */
1767 if (GET_CODE (addr) == PRE_INC)
1768 return "ldw 12(%1),%R0\n\tldws,mb 8(%1),%0";
1769 return "ldw -4(%1),%R0\n\tldws,mb -8(%1),%0";
1772 else if (GET_CODE (addr) == PLUS
1773 && GET_CODE (XEXP (addr, 0)) == MULT)
1775 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1777 if (!reg_overlap_mentioned_p (high_reg, addr))
1781 xoperands[0] = high_reg;
1782 xoperands[1] = XEXP (addr, 1);
1783 xoperands[2] = XEXP (XEXP (addr, 0), 0);
1784 xoperands[3] = XEXP (XEXP (addr, 0), 1);
1785 output_asm_insn ("sh%O3addl %2,%1,%0", xoperands);
1786 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
1792 xoperands[0] = high_reg;
1793 xoperands[1] = XEXP (addr, 1);
1794 xoperands[2] = XEXP (XEXP (addr, 0), 0);
1795 xoperands[3] = XEXP (XEXP (addr, 0), 1);
1796 output_asm_insn ("sh%O3addl %2,%1,%R0", xoperands);
1797 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
1803 /* If an operand is an unoffsettable memory ref, find a register
1804 we can increment temporarily to make it refer to the second word. */
1806 if (optype0 == MEMOP)
1807 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1809 if (optype1 == MEMOP)
1810 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1812 /* Ok, we can do one word at a time.
1813 Normally we do the low-numbered word first.
1815 In either case, set up in LATEHALF the operands to use
1816 for the high-numbered word and in some cases alter the
1817 operands in OPERANDS to be suitable for the low-numbered word. */
1819 if (optype0 == REGOP)
1820 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1821 else if (optype0 == OFFSOP)
1822 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1824 latehalf[0] = operands[0];
1826 if (optype1 == REGOP)
1827 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1828 else if (optype1 == OFFSOP)
1829 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1830 else if (optype1 == CNSTOP)
1831 split_double (operands[1], &operands[1], &latehalf[1]);
1833 latehalf[1] = operands[1];
1835 /* If the first move would clobber the source of the second one,
1836 do them in the other order.
1838 This can happen in two cases:
1840 mem -> register where the first half of the destination register
1841 is the same register used in the memory's address. Reload
1842 can create such insns.
1844 mem in this case will be either register indirect or register
1845 indirect plus a valid offset.
1847 register -> register move where REGNO(dst) == REGNO(src + 1)
1848 someone (Tim/Tege?) claimed this can happen for parameter loads.
1850 Handle mem -> register case first. */
1851 if (optype0 == REGOP
1852 && (optype1 == MEMOP || optype1 == OFFSOP)
1853 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
1856 /* Do the late half first. */
1858 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1859 output_asm_insn (singlemove_string (latehalf), latehalf);
1863 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1864 return singlemove_string (operands);
1867 /* Now handle register -> register case. */
1868 if (optype0 == REGOP && optype1 == REGOP
1869 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1871 output_asm_insn (singlemove_string (latehalf), latehalf);
1872 return singlemove_string (operands);
1875 /* Normal case: do the two words, low-numbered first. */
1877 output_asm_insn (singlemove_string (operands), operands);
1879 /* Make any unoffsettable addresses point at high-numbered word. */
1881 output_asm_insn ("ldo 4(%0),%0", &addreg0);
1883 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1886 output_asm_insn (singlemove_string (latehalf), latehalf);
1888 /* Undo the adds we just did. */
1890 output_asm_insn ("ldo -4(%0),%0", &addreg0);
1892 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1898 output_fp_move_double (operands)
1901 if (FP_REG_P (operands[0]))
1903 if (FP_REG_P (operands[1])
1904 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1905 output_asm_insn ("fcpy,dbl %f1,%0", operands);
1907 output_asm_insn ("fldd%F1 %1,%0", operands);
1909 else if (FP_REG_P (operands[1]))
1911 output_asm_insn ("fstd%F0 %1,%0", operands);
1913 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1915 if (GET_CODE (operands[0]) == REG)
1918 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1919 xoperands[0] = operands[0];
1920 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
1922 /* This is a pain. You have to be prepared to deal with an
1923 arbitrary address here including pre/post increment/decrement.
1925 so avoid this in the MD. */
1933 /* Return a REG that occurs in ADDR with coefficient 1.
1934 ADDR can be effectively incremented by incrementing REG. */
1937 find_addr_reg (addr)
1940 while (GET_CODE (addr) == PLUS)
1942 if (GET_CODE (XEXP (addr, 0)) == REG)
1943 addr = XEXP (addr, 0);
1944 else if (GET_CODE (XEXP (addr, 1)) == REG)
1945 addr = XEXP (addr, 1);
1946 else if (CONSTANT_P (XEXP (addr, 0)))
1947 addr = XEXP (addr, 1);
1948 else if (CONSTANT_P (XEXP (addr, 1)))
1949 addr = XEXP (addr, 0);
1953 if (GET_CODE (addr) == REG)
1958 /* Emit code to perform a block move.
1960 OPERANDS[0] is the destination pointer as a REG, clobbered.
1961 OPERANDS[1] is the source pointer as a REG, clobbered.
1962 OPERANDS[2] is a register for temporary storage.
1963 OPERANDS[4] is the size as a CONST_INT
1964 OPERANDS[3] is a register for temporary storage.
1965 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
1966 OPERANDS[6] is another temporary register. */
1969 output_block_move (operands, size_is_constant)
1971 int size_is_constant ATTRIBUTE_UNUSED;
1973 int align = INTVAL (operands[5]);
1974 unsigned long n_bytes = INTVAL (operands[4]);
1976 /* We can't move more than four bytes at a time because the PA
1977 has no longer integer move insns. (Could use fp mem ops?) */
1981 /* Note that we know each loop below will execute at least twice
1982 (else we would have open-coded the copy). */
1986 /* Pre-adjust the loop counter. */
1987 operands[4] = GEN_INT (n_bytes - 8);
1988 output_asm_insn ("ldi %4,%2", operands);
1991 output_asm_insn ("ldws,ma 4(%1),%3", operands);
1992 output_asm_insn ("ldws,ma 4(%1),%6", operands);
1993 output_asm_insn ("stws,ma %3,4(%0)", operands);
1994 output_asm_insn ("addib,>= -8,%2,.-12", operands);
1995 output_asm_insn ("stws,ma %6,4(%0)", operands);
1997 /* Handle the residual. There could be up to 7 bytes of
1998 residual to copy! */
1999 if (n_bytes % 8 != 0)
2001 operands[4] = GEN_INT (n_bytes % 4);
2002 if (n_bytes % 8 >= 4)
2003 output_asm_insn ("ldws,ma 4(%1),%3", operands);
2004 if (n_bytes % 4 != 0)
2005 output_asm_insn ("ldw 0(%1),%6", operands);
2006 if (n_bytes % 8 >= 4)
2007 output_asm_insn ("stws,ma %3,4(%0)", operands);
2008 if (n_bytes % 4 != 0)
2009 output_asm_insn ("stbys,e %6,%4(%0)", operands);
2014 /* Pre-adjust the loop counter. */
2015 operands[4] = GEN_INT (n_bytes - 4);
2016 output_asm_insn ("ldi %4,%2", operands);
2019 output_asm_insn ("ldhs,ma 2(%1),%3", operands);
2020 output_asm_insn ("ldhs,ma 2(%1),%6", operands);
2021 output_asm_insn ("sths,ma %3,2(%0)", operands);
2022 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2023 output_asm_insn ("sths,ma %6,2(%0)", operands);
2025 /* Handle the residual. */
2026 if (n_bytes % 4 != 0)
2028 if (n_bytes % 4 >= 2)
2029 output_asm_insn ("ldhs,ma 2(%1),%3", operands);
2030 if (n_bytes % 2 != 0)
2031 output_asm_insn ("ldb 0(%1),%6", operands);
2032 if (n_bytes % 4 >= 2)
2033 output_asm_insn ("sths,ma %3,2(%0)", operands);
2034 if (n_bytes % 2 != 0)
2035 output_asm_insn ("stb %6,0(%0)", operands);
2040 /* Pre-adjust the loop counter. */
2041 operands[4] = GEN_INT (n_bytes - 2);
2042 output_asm_insn ("ldi %4,%2", operands);
2045 output_asm_insn ("ldbs,ma 1(%1),%3", operands);
2046 output_asm_insn ("ldbs,ma 1(%1),%6", operands);
2047 output_asm_insn ("stbs,ma %3,1(%0)", operands);
2048 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2049 output_asm_insn ("stbs,ma %6,1(%0)", operands);
2051 /* Handle the residual. */
2052 if (n_bytes % 2 != 0)
2054 output_asm_insn ("ldb 0(%1),%3", operands);
2055 output_asm_insn ("stb %3,0(%0)", operands);
2064 /* Count the number of insns necessary to handle this block move.
2066 Basic structure is the same as emit_block_move, except that we
2067 count insns rather than emit them. */
2070 compute_movstrsi_length (insn)
2073 rtx pat = PATTERN (insn);
2074 int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2075 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
2076 unsigned int n_insns = 0;
2078 /* We can't move more than four bytes at a time because the PA
2079 has no longer integer move insns. (Could use fp mem ops?) */
2083 /* The basic copying loop. */
2087 if (n_bytes % (2 * align) != 0)
2089 if ((n_bytes % (2 * align)) >= align)
2092 if ((n_bytes % align) != 0)
2096 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2102 output_and (operands)
2105 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2107 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2108 int ls0, ls1, ms0, p, len;
2110 for (ls0 = 0; ls0 < 32; ls0++)
2111 if ((mask & (1 << ls0)) == 0)
2114 for (ls1 = ls0; ls1 < 32; ls1++)
2115 if ((mask & (1 << ls1)) != 0)
2118 for (ms0 = ls1; ms0 < 32; ms0++)
2119 if ((mask & (1 << ms0)) == 0)
2132 operands[2] = GEN_INT (len);
2133 return "extru %1,31,%2,%0";
2137 /* We could use this `depi' for the case above as well, but `depi'
2138 requires one more register file access than an `extru'. */
2143 operands[2] = GEN_INT (p);
2144 operands[3] = GEN_INT (len);
2145 return "depi 0,%2,%3,%0";
2149 return "and %1,%2,%0";
2153 output_ior (operands)
2156 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2157 int bs0, bs1, p, len;
2159 if (INTVAL (operands[2]) == 0)
2160 return "copy %1,%0";
2162 for (bs0 = 0; bs0 < 32; bs0++)
2163 if ((mask & (1 << bs0)) != 0)
2166 for (bs1 = bs0; bs1 < 32; bs1++)
2167 if ((mask & (1 << bs1)) == 0)
2170 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2176 operands[2] = GEN_INT (p);
2177 operands[3] = GEN_INT (len);
2178 return "depi -1,%2,%3,%0";
2181 /* Output an ascii string. */
2183 output_ascii (file, p, size)
2190 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2192 /* The HP assembler can only take strings of 256 characters at one
2193 time. This is a limitation on input line length, *not* the
2194 length of the string. Sigh. Even worse, it seems that the
2195 restriction is in number of input characters (see \xnn &
2196 \whatever). So we have to do this very carefully. */
2198 fputs ("\t.STRING \"", file);
2201 for (i = 0; i < size; i += 4)
2205 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2207 register unsigned int c = p[i + io];
2209 if (c == '\"' || c == '\\')
2210 partial_output[co++] = '\\';
2211 if (c >= ' ' && c < 0177)
2212 partial_output[co++] = c;
2216 partial_output[co++] = '\\';
2217 partial_output[co++] = 'x';
2218 hexd = c / 16 - 0 + '0';
2220 hexd -= '9' - 'a' + 1;
2221 partial_output[co++] = hexd;
2222 hexd = c % 16 - 0 + '0';
2224 hexd -= '9' - 'a' + 1;
2225 partial_output[co++] = hexd;
2228 if (chars_output + co > 243)
2230 fputs ("\"\n\t.STRING \"", file);
2233 fwrite (partial_output, 1, co, file);
2237 fputs ("\"\n", file);
2240 /* Try to rewrite floating point comparisons & branches to avoid
2241 useless add,tr insns.
2243 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2244 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2245 first attempt to remove useless add,tr insns. It is zero
2246 for the second pass as reorg sometimes leaves bogus REG_DEAD
2249 When CHECK_NOTES is zero we can only eliminate add,tr insns
2250 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2253 remove_useless_addtr_insns (insns, check_notes)
2258 static int pass = 0;
2260 /* This is fairly cheap, so always run it when optimizing. */
2264 int fbranch_count = 0;
2266 /* Walk all the insns in this function looking for fcmp & fbranch
2267 instructions. Keep track of how many of each we find. */
2268 insns = get_insns ();
2269 for (insn = insns; insn; insn = next_insn (insn))
2273 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2274 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2277 tmp = PATTERN (insn);
2279 /* It must be a set. */
2280 if (GET_CODE (tmp) != SET)
2283 /* If the destination is CCFP, then we've found an fcmp insn. */
2284 tmp = SET_DEST (tmp);
2285 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2291 tmp = PATTERN (insn);
2292 /* If this is an fbranch instruction, bump the fbranch counter. */
2293 if (GET_CODE (tmp) == SET
2294 && SET_DEST (tmp) == pc_rtx
2295 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2296 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2297 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2298 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2306 /* Find all floating point compare + branch insns. If possible,
2307 reverse the comparison & the branch to avoid add,tr insns. */
2308 for (insn = insns; insn; insn = next_insn (insn))
2312 /* Ignore anything that isn't an INSN. */
2313 if (GET_CODE (insn) != INSN)
2316 tmp = PATTERN (insn);
2318 /* It must be a set. */
2319 if (GET_CODE (tmp) != SET)
2322 /* The destination must be CCFP, which is register zero. */
2323 tmp = SET_DEST (tmp);
2324 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2327 /* INSN should be a set of CCFP.
2329 See if the result of this insn is used in a reversed FP
2330 conditional branch. If so, reverse our condition and
2331 the branch. Doing so avoids useless add,tr insns. */
2332 next = next_insn (insn);
2335 /* Jumps, calls and labels stop our search. */
2336 if (GET_CODE (next) == JUMP_INSN
2337 || GET_CODE (next) == CALL_INSN
2338 || GET_CODE (next) == CODE_LABEL)
2341 /* As does another fcmp insn. */
2342 if (GET_CODE (next) == INSN
2343 && GET_CODE (PATTERN (next)) == SET
2344 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2345 && REGNO (SET_DEST (PATTERN (next))) == 0)
2348 next = next_insn (next);
2351 /* Is NEXT_INSN a branch? */
2353 && GET_CODE (next) == JUMP_INSN)
2355 rtx pattern = PATTERN (next);
2357 /* If it a reversed fp conditional branch (eg uses add,tr)
2358 and CCFP dies, then reverse our conditional and the branch
2359 to avoid the add,tr. */
2360 if (GET_CODE (pattern) == SET
2361 && SET_DEST (pattern) == pc_rtx
2362 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2363 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2364 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2365 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2366 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2367 && (fcmp_count == fbranch_count
2369 && find_regno_note (next, REG_DEAD, 0))))
2371 /* Reverse the branch. */
2372 tmp = XEXP (SET_SRC (pattern), 1);
2373 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2374 XEXP (SET_SRC (pattern), 2) = tmp;
2375 INSN_CODE (next) = -1;
2377 /* Reverse our condition. */
2378 tmp = PATTERN (insn);
2379 PUT_CODE (XEXP (tmp, 1),
2380 reverse_condition (GET_CODE (XEXP (tmp, 1))));
2390 /* You may have trouble believing this, but this is the HP-PA stack
2395 Variable arguments (optional; any number may be allocated)
2397 SP-(4*(N+9)) arg word N
2402 Fixed arguments (must be allocated; may remain unused)
2411 SP-32 External Data Pointer (DP)
2413 SP-24 External/stub RP (RP')
2417 SP-8 Calling Stub RP (RP'')
2422 SP-0 Stack Pointer (points to next available address)
2426 /* This function saves registers as follows. Registers marked with ' are
2427 this function's registers (as opposed to the previous function's).
2428 If a frame_pointer isn't needed, r4 is saved as a general register;
2429 the space for the frame pointer is still allocated, though, to keep
2435 SP (FP') Previous FP
2436 SP + 4 Alignment filler (sigh)
2437 SP + 8 Space for locals reserved here.
2441 SP + n All call saved register used.
2445 SP + o All call saved fp registers used.
2449 SP + p (SP') points to next available address.
2453 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2454 Handle case where DISP > 8k by using the add_high_const pattern.
2456 Note in DISP > 8k case, we will leave the high part of the address
2457 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2459 store_reg (reg, disp, base)
2460 int reg, disp, base;
2462 if (VAL_14_BITS_P (disp))
2464 emit_move_insn (gen_rtx_MEM (SImode,
2465 gen_rtx_PLUS (SImode,
2466 gen_rtx_REG (SImode, base),
2468 gen_rtx_REG (SImode, reg));
2472 emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
2473 gen_rtx_REG (SImode, base),
2475 emit_move_insn (gen_rtx_MEM (SImode,
2476 gen_rtx_LO_SUM (SImode,
2477 gen_rtx_REG (SImode, 1),
2479 gen_rtx_REG (SImode, reg));
2483 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
2484 Handle case where DISP > 8k by using the add_high_const pattern.
2486 Note in DISP > 8k case, we will leave the high part of the address
2487 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2489 load_reg (reg, disp, base)
2490 int reg, disp, base;
2492 if (VAL_14_BITS_P (disp))
2494 emit_move_insn (gen_rtx_REG (SImode, reg),
2495 gen_rtx_MEM (SImode,
2496 gen_rtx_PLUS (SImode,
2497 gen_rtx_REG (SImode, base),
2502 emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
2503 gen_rtx_REG (SImode, base),
2505 emit_move_insn (gen_rtx_REG (SImode, reg),
2506 gen_rtx_MEM (SImode,
2507 gen_rtx_LO_SUM (SImode,
2508 gen_rtx_REG (SImode, 1),
2513 /* Emit RTL to set REG to the value specified by BASE+DISP.
2514 Handle case where DISP > 8k by using the add_high_const pattern.
2516 Note in DISP > 8k case, we will leave the high part of the address
2517 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2519 set_reg_plus_d(reg, base, disp)
2520 int reg, base, disp;
2522 if (VAL_14_BITS_P (disp))
2524 emit_move_insn (gen_rtx_REG (SImode, reg),
2525 gen_rtx_PLUS (SImode,
2526 gen_rtx_REG (SImode, base),
2531 emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
2532 gen_rtx_REG (SImode, base),
2534 emit_move_insn (gen_rtx_REG (SImode, reg),
2535 gen_rtx_LO_SUM (SImode,
2536 gen_rtx_REG (SImode, 1),
2541 /* Global variables set by FUNCTION_PROLOGUE. */
2542 /* Size of frame. Need to know this to emit return insns from
2544 static int actual_fsize;
2545 static int local_fsize, save_fregs;
2548 compute_frame_size (size, fregs_live)
2552 extern int current_function_outgoing_args_size;
2555 /* 8 is space for frame pointer + filler. If any frame is allocated
2556 we need to add this in because of STARTING_FRAME_OFFSET. */
2557 fsize = size + (size || frame_pointer_needed ? 8 : 0);
2559 for (i = 18; i >= 3; i--)
2560 if (regs_ever_live[i])
2562 fsize += UNITS_PER_WORD;
2566 /* Round the stack. */
2567 fsize = (fsize + 7) & ~7;
2569 for (i = 66; i >= 48; i -= 2)
2570 if (regs_ever_live[i] || regs_ever_live[i + 1])
2579 fsize += current_function_outgoing_args_size;
2580 if (! leaf_function_p () || fsize)
2582 return (fsize + 63) & ~63;
2585 rtx hp_profile_label_rtx;
2586 static char hp_profile_label_name[8];
2588 output_function_prologue (file, size)
2590 int size ATTRIBUTE_UNUSED;
2592 /* The function's label and associated .PROC must never be
2593 separated and must be output *after* any profiling declarations
2594 to avoid changing spaces/subspaces within a procedure. */
2596 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
2598 fputs ("\t.PROC\n", file);
2600 /* hppa_expand_prologue does the dirty work now. We just need
2601 to output the assembler directives which denote the start
2603 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
2604 if (regs_ever_live[2] || profile_flag)
2605 fputs (",CALLS,SAVE_RP", file);
2607 fputs (",NO_CALLS", file);
2609 if (frame_pointer_needed)
2610 fputs (",SAVE_SP", file);
2612 /* Pass on information about the number of callee register saves
2613 performed in the prologue.
2615 The compiler is supposed to pass the highest register number
2616 saved, the assembler then has to adjust that number before
2617 entering it into the unwind descriptor (to account for any
2618 caller saved registers with lower register numbers than the
2619 first callee saved register). */
2621 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
2624 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
2626 fputs ("\n\t.ENTRY\n", file);
2628 /* Horrid hack. emit_function_prologue will modify this RTL in
2629 place to get the expected results. */
2631 ASM_GENERATE_INTERNAL_LABEL (hp_profile_label_name, "LP",
2632 hp_profile_labelno);
2634 /* If we're using GAS and not using the portable runtime model, then
2635 we don't need to accumulate the total number of code bytes. */
2636 if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
2637 total_code_bytes = 0;
2638 else if (insn_addresses)
2640 unsigned int old_total = total_code_bytes;
2642 total_code_bytes += insn_addresses[INSN_UID (get_last_insn())];
2643 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
2645 /* Be prepared to handle overflows. */
2646 total_code_bytes = old_total > total_code_bytes ? -1 : total_code_bytes;
2649 total_code_bytes = -1;
2651 remove_useless_addtr_insns (get_insns (), 0);
2653 /* Restore INSN_CODEs for insn which use unscaled indexed addresses. */
2654 restore_unscaled_index_insn_codes (get_insns ());
2658 hppa_expand_prologue()
2660 extern char call_used_regs[];
2661 int size = get_frame_size ();
2662 int merge_sp_adjust_with_store = 0;
2664 rtx tmpreg, size_rtx;
2669 local_fsize = size + (size || frame_pointer_needed ? 8 : 0);
2670 actual_fsize = compute_frame_size (size, &save_fregs);
2672 /* Compute a few things we will use often. */
2673 tmpreg = gen_rtx_REG (SImode, 1);
2674 size_rtx = GEN_INT (actual_fsize);
2676 /* Save RP first. The calling conventions manual states RP will
2677 always be stored into the caller's frame at sp-20. */
2678 if (regs_ever_live[2] || profile_flag)
2679 store_reg (2, -20, STACK_POINTER_REGNUM);
2681 /* Allocate the local frame and set up the frame pointer if needed. */
2684 if (frame_pointer_needed)
2686 /* Copy the old frame pointer temporarily into %r1. Set up the
2687 new stack pointer, then store away the saved old frame pointer
2688 into the stack at sp+actual_fsize and at the same time update
2689 the stack pointer by actual_fsize bytes. Two versions, first
2690 handles small (<8k) frames. The second handles large (>8k)
2692 emit_move_insn (tmpreg, frame_pointer_rtx);
2693 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2694 if (VAL_14_BITS_P (actual_fsize))
2695 emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, size_rtx));
2698 /* It is incorrect to store the saved frame pointer at *sp,
2699 then increment sp (writes beyond the current stack boundary).
2701 So instead use stwm to store at *sp and post-increment the
2702 stack pointer as an atomic operation. Then increment sp to
2703 finish allocating the new frame. */
2704 emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, GEN_INT (64)));
2705 set_reg_plus_d (STACK_POINTER_REGNUM,
2706 STACK_POINTER_REGNUM,
2710 /* no frame pointer needed. */
2713 /* In some cases we can perform the first callee register save
2714 and allocating the stack frame at the same time. If so, just
2715 make a note of it and defer allocating the frame until saving
2716 the callee registers. */
2717 if (VAL_14_BITS_P (-actual_fsize)
2721 merge_sp_adjust_with_store = 1;
2722 /* Can not optimize. Adjust the stack frame by actual_fsize bytes. */
2723 else if (actual_fsize != 0)
2724 set_reg_plus_d (STACK_POINTER_REGNUM,
2725 STACK_POINTER_REGNUM,
2730 /* The hppa calling conventions say that %r19, the pic offset
2731 register, is saved at sp - 32 (in this function's frame) when
2732 generating PIC code. FIXME: What is the correct thing to do
2733 for functions which make no calls and allocate no frame? Do
2734 we need to allocate a frame, or can we just omit the save? For
2735 now we'll just omit the save. */
2736 if (actual_fsize != 0 && flag_pic)
2737 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
2741 Instead of taking one argument, the counter label, as most normal
2742 mcounts do, _mcount appears to behave differently on the HPPA. It
2743 takes the return address of the caller, the address of this routine,
2744 and the address of the label. Also, it isn't magic, so
2745 argument registers have to be preserved. */
2748 int pc_offset, i, arg_offset, basereg, offsetadj;
2750 pc_offset = 4 + (frame_pointer_needed
2751 ? (VAL_14_BITS_P (actual_fsize) ? 12 : 20)
2752 : (VAL_14_BITS_P (actual_fsize) ? 4 : 8));
2754 /* When the function has a frame pointer, use it as the base
2755 register for saving/restore registers. Else use the stack
2756 pointer. Adjust the offset according to the frame size if
2757 this function does not have a frame pointer. */
2759 basereg = frame_pointer_needed ? FRAME_POINTER_REGNUM
2760 : STACK_POINTER_REGNUM;
2761 offsetadj = frame_pointer_needed ? 0 : actual_fsize;
2763 /* Horrid hack. emit_function_prologue will modify this RTL in
2764 place to get the expected results. sprintf here is just to
2765 put something in the name. */
2766 sprintf(hp_profile_label_name, "LP$%04d", -1);
2767 hp_profile_label_rtx = gen_rtx_SYMBOL_REF (SImode, hp_profile_label_name);
2768 if (current_function_returns_struct)
2769 store_reg (STRUCT_VALUE_REGNUM, - 12 - offsetadj, basereg);
2770 if (current_function_needs_context)
2771 store_reg (STATIC_CHAIN_REGNUM, - 16 - offsetadj, basereg);
2773 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2774 if (regs_ever_live [i])
2776 store_reg (i, arg_offset, basereg);
2777 /* Deal with arg_offset not fitting in 14 bits. */
2778 pc_offset += VAL_14_BITS_P (arg_offset) ? 4 : 8;
2781 emit_move_insn (gen_rtx_REG (SImode, 26), gen_rtx_REG (SImode, 2));
2782 emit_move_insn (tmpreg, gen_rtx_HIGH (SImode, hp_profile_label_rtx));
2783 emit_move_insn (gen_rtx_REG (SImode, 24),
2784 gen_rtx_LO_SUM (SImode, tmpreg, hp_profile_label_rtx));
2785 /* %r25 is set from within the output pattern. */
2786 emit_insn (gen_call_profiler (GEN_INT (- pc_offset - 20)));
2788 /* Restore argument registers. */
2789 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2790 if (regs_ever_live [i])
2791 load_reg (i, arg_offset, basereg);
2793 if (current_function_returns_struct)
2794 load_reg (STRUCT_VALUE_REGNUM, -12 - offsetadj, basereg);
2796 if (current_function_needs_context)
2797 load_reg (STATIC_CHAIN_REGNUM, -16 - offsetadj, basereg);
2800 /* Normal register save.
2802 Do not save the frame pointer in the frame_pointer_needed case. It
2803 was done earlier. */
2804 if (frame_pointer_needed)
2806 for (i = 18, offset = local_fsize; i >= 4; i--)
2807 if (regs_ever_live[i] && ! call_used_regs[i])
2809 store_reg (i, offset, FRAME_POINTER_REGNUM);
2810 offset += UNITS_PER_WORD;
2813 /* Account for %r3 which is saved in a special place. */
2816 /* No frame pointer needed. */
2819 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
2820 if (regs_ever_live[i] && ! call_used_regs[i])
2822 /* If merge_sp_adjust_with_store is nonzero, then we can
2823 optimize the first GR save. */
2824 if (merge_sp_adjust_with_store)
2826 merge_sp_adjust_with_store = 0;
2827 emit_insn (gen_post_stwm (stack_pointer_rtx,
2828 gen_rtx_REG (SImode, i),
2829 GEN_INT (-offset)));
2832 store_reg (i, offset, STACK_POINTER_REGNUM);
2833 offset += UNITS_PER_WORD;
2837 /* If we wanted to merge the SP adjustment with a GR save, but we never
2838 did any GR saves, then just emit the adjustment here. */
2839 if (merge_sp_adjust_with_store)
2840 set_reg_plus_d (STACK_POINTER_REGNUM,
2841 STACK_POINTER_REGNUM,
2845 /* Align pointer properly (doubleword boundary). */
2846 offset = (offset + 7) & ~7;
2848 /* Floating point register store. */
2851 /* First get the frame or stack pointer to the start of the FP register
2853 if (frame_pointer_needed)
2854 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
2856 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
2858 /* Now actually save the FP registers. */
2859 for (i = 66; i >= 48; i -= 2)
2861 if (regs_ever_live[i] || regs_ever_live[i + 1])
2863 emit_move_insn (gen_rtx_MEM (DFmode,
2864 gen_rtx_POST_INC (DFmode, tmpreg)),
2865 gen_rtx_REG (DFmode, i));
2871 /* When generating PIC code it is necessary to save/restore the
2872 PIC register around each function call. We used to do this
2873 in the call patterns themselves, but that implementation
2874 made incorrect assumptions about using global variables to hold
2875 per-function rtl code generated in the backend.
2877 So instead, we copy the PIC register into a reserved callee saved
2878 register in the prologue. Then after each call we reload the PIC
2879 register from the callee saved register. We also reload the PIC
2880 register from the callee saved register in the epilogue ensure the
2881 PIC register is valid at function exit.
2883 This may (depending on the exact characteristics of the function)
2884 even be more efficient.
2886 Avoid this if the callee saved register wasn't used (these are
2888 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM_SAVED])
2889 emit_move_insn (gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM_SAVED),
2890 gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM));
2895 output_function_epilogue (file, size)
2897 int size ATTRIBUTE_UNUSED;
2899 rtx insn = get_last_insn ();
2901 /* hppa_expand_epilogue does the dirty work now. We just need
2902 to output the assembler directives which denote the end
2905 To make debuggers happy, emit a nop if the epilogue was completely
2906 eliminated due to a volatile call as the last insn in the
2907 current function. That way the return address (in %r2) will
2908 always point to a valid instruction in the current function. */
2910 /* Get the last real insn. */
2911 if (GET_CODE (insn) == NOTE)
2912 insn = prev_real_insn (insn);
2914 /* If it is a sequence, then look inside. */
2915 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
2916 insn = XVECEXP (PATTERN (insn), 0, 0);
2918 /* If insn is a CALL_INSN, then it must be a call to a volatile
2919 function (otherwise there would be epilogue insns). */
2920 if (insn && GET_CODE (insn) == CALL_INSN)
2921 fputs ("\tnop\n", file);
2923 fputs ("\t.EXIT\n\t.PROCEND\n", file);
2925 /* Free up stuff we don't need anymore. */
2926 if (unscaled_index_insn_codes)
2927 free (unscaled_index_insn_codes);
2928 max_unscaled_index_insn_codes_uid = 0;
2932 hppa_expand_epilogue ()
2936 int merge_sp_adjust_with_load = 0;
2938 /* We will use this often. */
2939 tmpreg = gen_rtx_REG (SImode, 1);
2941 /* Try to restore RP early to avoid load/use interlocks when
2942 RP gets used in the return (bv) instruction. This appears to still
2943 be necessary even when we schedule the prologue and epilogue. */
2944 if (frame_pointer_needed
2945 && (regs_ever_live [2] || profile_flag))
2946 load_reg (2, -20, FRAME_POINTER_REGNUM);
2948 /* No frame pointer, and stack is smaller than 8k. */
2949 else if (! frame_pointer_needed
2950 && VAL_14_BITS_P (actual_fsize + 20)
2951 && (regs_ever_live[2] || profile_flag))
2952 load_reg (2, - (actual_fsize + 20), STACK_POINTER_REGNUM);
2954 /* General register restores. */
2955 if (frame_pointer_needed)
2957 for (i = 18, offset = local_fsize; i >= 4; i--)
2958 if (regs_ever_live[i] && ! call_used_regs[i])
2960 load_reg (i, offset, FRAME_POINTER_REGNUM);
2961 offset += UNITS_PER_WORD;
2966 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
2968 if (regs_ever_live[i] && ! call_used_regs[i])
2970 /* Only for the first load.
2971 merge_sp_adjust_with_load holds the register load
2972 with which we will merge the sp adjustment. */
2973 if (VAL_14_BITS_P (actual_fsize + 20)
2975 && ! merge_sp_adjust_with_load)
2976 merge_sp_adjust_with_load = i;
2978 load_reg (i, offset, STACK_POINTER_REGNUM);
2979 offset += UNITS_PER_WORD;
2984 /* Align pointer properly (doubleword boundary). */
2985 offset = (offset + 7) & ~7;
2987 /* FP register restores. */
2990 /* Adjust the register to index off of. */
2991 if (frame_pointer_needed)
2992 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
2994 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
2996 /* Actually do the restores now. */
2997 for (i = 66; i >= 48; i -= 2)
2999 if (regs_ever_live[i] || regs_ever_live[i + 1])
3001 emit_move_insn (gen_rtx_REG (DFmode, i),
3002 gen_rtx_MEM (DFmode,
3003 gen_rtx_POST_INC (DFmode, tmpreg)));
3008 /* Emit a blockage insn here to keep these insns from being moved to
3009 an earlier spot in the epilogue, or into the main instruction stream.
3011 This is necessary as we must not cut the stack back before all the
3012 restores are finished. */
3013 emit_insn (gen_blockage ());
3014 /* No frame pointer, but we have a stack greater than 8k. We restore
3015 %r2 very late in this case. (All other cases are restored as early
3017 if (! frame_pointer_needed
3018 && ! VAL_14_BITS_P (actual_fsize + 20)
3019 && (regs_ever_live[2] || profile_flag))
3021 set_reg_plus_d (STACK_POINTER_REGNUM,
3022 STACK_POINTER_REGNUM,
3025 /* This used to try and be clever by not depending on the value in
3026 %r30 and instead use the value held in %r1 (so that the 2nd insn
3027 which sets %r30 could be put in the delay slot of the return insn).
3029 That won't work since if the stack is exactly 8k set_reg_plus_d
3030 doesn't set %r1, just %r30. */
3031 load_reg (2, - 20, STACK_POINTER_REGNUM);
3034 /* Reset stack pointer (and possibly frame pointer). The stack
3035 pointer is initially set to fp + 64 to avoid a race condition. */
3036 else if (frame_pointer_needed)
3038 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64);
3039 emit_insn (gen_pre_ldwm (frame_pointer_rtx,
3043 /* If we were deferring a callee register restore, do it now. */
3044 else if (! frame_pointer_needed && merge_sp_adjust_with_load)
3045 emit_insn (gen_pre_ldwm (gen_rtx_REG (SImode, merge_sp_adjust_with_load),
3047 GEN_INT (- actual_fsize)));
3048 else if (actual_fsize != 0)
3049 set_reg_plus_d (STACK_POINTER_REGNUM,
3050 STACK_POINTER_REGNUM,
3054 /* Fetch the return address for the frame COUNT steps up from
3055 the current frame, after the prologue. FRAMEADDR is the
3056 frame pointer of the COUNT frame.
3058 We want to ignore any export stub remnants here.
3060 The value returned is used in two different ways:
3062 1. To find a function's caller.
3064 2. To change the return address for a function.
3066 This function handles most instances of case 1; however, it will
3067 fail if there are two levels of stubs to execute on the return
3068 path. The only way I believe that can happen is if the return value
3069 needs a parameter relocation, which never happens for C code.
3071 This function handles most instances of case 2; however, it will
3072 fail if we did not originally have stub code on the return path
3073 but will need code on the new return path. This can happen if
3074 the caller & callee are both in the main program, but the new
3075 return location is in a shared library.
3077 To handle this correctly we need to set the return pointer at
3078 frame-20 to point to a return stub frame-24 to point to the
3079 location we wish to return to. */
3082 return_addr_rtx (count, frameaddr)
3083 int count ATTRIBUTE_UNUSED;
3090 saved_rp = gen_reg_rtx (Pmode);
3092 /* First, we start off with the normal return address pointer from
3095 emit_move_insn (saved_rp, plus_constant (frameaddr, -5 * UNITS_PER_WORD));
3097 /* Get pointer to the instruction stream. We have to mask out the
3098 privilege level from the two low order bits of the return address
3099 pointer here so that ins will point to the start of the first
3100 instruction that would have been executed if we returned. */
3101 ins = copy_to_reg (gen_rtx_AND (Pmode,
3102 copy_to_reg (gen_rtx_MEM (Pmode, saved_rp)),
3104 label = gen_label_rtx ();
3106 /* Check the instruction stream at the normal return address for the
3109 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3110 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3111 0x00011820 | stub+16: mtsp r1,sr0
3112 0xe0400002 | stub+20: be,n 0(sr0,rp)
3114 If it is an export stub, than our return address is really in
3117 emit_cmp_insn (gen_rtx_MEM (SImode, ins),
3118 GEN_INT (0x4bc23fd1),
3119 NE, NULL_RTX, SImode, 1, 0);
3120 emit_jump_insn (gen_bne (label));
3122 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3123 GEN_INT (0x004010a1),
3124 NE, NULL_RTX, SImode, 1, 0);
3125 emit_jump_insn (gen_bne (label));
3127 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3128 GEN_INT (0x00011820),
3129 NE, NULL_RTX, SImode, 1, 0);
3130 emit_jump_insn (gen_bne (label));
3132 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3133 GEN_INT (0xe0400002),
3134 NE, NULL_RTX, SImode, 1, 0);
3136 /* If there is no export stub then just use our initial guess of
3139 emit_jump_insn (gen_bne (label));
3141 /* Here we know that our return address pointer points to an export
3142 stub. We don't want to return the address of the export stub,
3143 but rather the return address that leads back into user code.
3144 That return address is stored at -24[frameaddr]. */
3146 emit_move_insn (saved_rp, plus_constant (frameaddr, -6 * UNITS_PER_WORD));
3149 return gen_rtx_MEM (Pmode, memory_address (Pmode, saved_rp));
3152 /* This is only valid once reload has completed because it depends on
3153 knowing exactly how much (if any) frame there is and...
3155 It's only valid if there is no frame marker to de-allocate and...
3157 It's only valid if %r2 hasn't been saved into the caller's frame
3158 (we're not profiling and %r2 isn't live anywhere). */
3160 hppa_can_use_return_insn_p ()
3162 return (reload_completed
3163 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3165 && ! regs_ever_live[2]
3166 && ! frame_pointer_needed);
3170 emit_bcond_fp (code, operand0)
3174 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3175 gen_rtx_IF_THEN_ELSE (VOIDmode,
3176 gen_rtx_fmt_ee (code,
3178 gen_rtx_REG (CCFPmode, 0),
3180 gen_rtx_LABEL_REF (VOIDmode, operand0),
3186 gen_cmp_fp (code, operand0, operand1)
3188 rtx operand0, operand1;
3190 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3191 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3194 /* Adjust the cost of a scheduling dependency. Return the new cost of
3195 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3198 pa_adjust_cost (insn, link, dep_insn, cost)
3204 enum attr_type attr_type;
3206 /* Don't adjust costs for a pa8000 chip. */
3207 if (pa_cpu >= PROCESSOR_8000)
3210 if (! recog_memoized (insn))
3213 attr_type = get_attr_type (insn);
3215 if (REG_NOTE_KIND (link) == 0)
3217 /* Data dependency; DEP_INSN writes a register that INSN reads some
3220 if (attr_type == TYPE_FPSTORE)
3222 rtx pat = PATTERN (insn);
3223 rtx dep_pat = PATTERN (dep_insn);
3224 if (GET_CODE (pat) == PARALLEL)
3226 /* This happens for the fstXs,mb patterns. */
3227 pat = XVECEXP (pat, 0, 0);
3229 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3230 /* If this happens, we have to extend this to schedule
3231 optimally. Return 0 for now. */
3234 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
3236 if (! recog_memoized (dep_insn))
3238 /* DEP_INSN is writing its result to the register
3239 being stored in the fpstore INSN. */
3240 switch (get_attr_type (dep_insn))
3243 /* This cost 3 cycles, not 2 as the md says for the
3252 case TYPE_FPSQRTSGL:
3253 case TYPE_FPSQRTDBL:
3254 /* In these important cases, we save one cycle compared to
3255 when flop instruction feed each other. */
3264 /* For other data dependencies, the default cost specified in the
3268 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3270 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3273 if (attr_type == TYPE_FPLOAD)
3275 rtx pat = PATTERN (insn);
3276 rtx dep_pat = PATTERN (dep_insn);
3277 if (GET_CODE (pat) == PARALLEL)
3279 /* This happens for the fldXs,mb patterns. */
3280 pat = XVECEXP (pat, 0, 0);
3282 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3283 /* If this happens, we have to extend this to schedule
3284 optimally. Return 0 for now. */
3287 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3289 if (! recog_memoized (dep_insn))
3291 switch (get_attr_type (dep_insn))
3298 case TYPE_FPSQRTSGL:
3299 case TYPE_FPSQRTDBL:
3300 /* A fpload can't be issued until one cycle before a
3301 preceding arithmetic operation has finished if
3302 the target of the fpload is any of the sources
3303 (or destination) of the arithmetic operation. */
3311 else if (attr_type == TYPE_FPALU)
3313 rtx pat = PATTERN (insn);
3314 rtx dep_pat = PATTERN (dep_insn);
3315 if (GET_CODE (pat) == PARALLEL)
3317 /* This happens for the fldXs,mb patterns. */
3318 pat = XVECEXP (pat, 0, 0);
3320 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3321 /* If this happens, we have to extend this to schedule
3322 optimally. Return 0 for now. */
3325 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3327 if (! recog_memoized (dep_insn))
3329 switch (get_attr_type (dep_insn))
3333 case TYPE_FPSQRTSGL:
3334 case TYPE_FPSQRTDBL:
3335 /* An ALU flop can't be issued until two cycles before a
3336 preceding divide or sqrt operation has finished if
3337 the target of the ALU flop is any of the sources
3338 (or destination) of the divide or sqrt operation. */
3347 /* For other anti dependencies, the cost is 0. */
3350 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3352 /* Output dependency; DEP_INSN writes a register that INSN writes some
3354 if (attr_type == TYPE_FPLOAD)
3356 rtx pat = PATTERN (insn);
3357 rtx dep_pat = PATTERN (dep_insn);
3358 if (GET_CODE (pat) == PARALLEL)
3360 /* This happens for the fldXs,mb patterns. */
3361 pat = XVECEXP (pat, 0, 0);
3363 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3364 /* If this happens, we have to extend this to schedule
3365 optimally. Return 0 for now. */
3368 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3370 if (! recog_memoized (dep_insn))
3372 switch (get_attr_type (dep_insn))
3379 case TYPE_FPSQRTSGL:
3380 case TYPE_FPSQRTDBL:
3381 /* A fpload can't be issued until one cycle before a
3382 preceding arithmetic operation has finished if
3383 the target of the fpload is the destination of the
3384 arithmetic operation. */
3392 else if (attr_type == TYPE_FPALU)
3394 rtx pat = PATTERN (insn);
3395 rtx dep_pat = PATTERN (dep_insn);
3396 if (GET_CODE (pat) == PARALLEL)
3398 /* This happens for the fldXs,mb patterns. */
3399 pat = XVECEXP (pat, 0, 0);
3401 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3402 /* If this happens, we have to extend this to schedule
3403 optimally. Return 0 for now. */
3406 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3408 if (! recog_memoized (dep_insn))
3410 switch (get_attr_type (dep_insn))
3414 case TYPE_FPSQRTSGL:
3415 case TYPE_FPSQRTDBL:
3416 /* An ALU flop can't be issued until two cycles before a
3417 preceding divide or sqrt operation has finished if
3418 the target of the ALU flop is also the target of
3419 the divide or sqrt operation. */
3428 /* For other output dependencies, the cost is 0. */
3435 /* Return any length adjustment needed by INSN which already has its length
3436 computed as LENGTH. Return zero if no adjustment is necessary.
3438 For the PA: function calls, millicode calls, and backwards short
3439 conditional branches with unfilled delay slots need an adjustment by +1
3440 (to account for the NOP which will be inserted into the instruction stream).
3442 Also compute the length of an inline block move here as it is too
3443 complicated to express as a length attribute in pa.md. */
3445 pa_adjust_insn_length (insn, length)
3449 rtx pat = PATTERN (insn);
3451 /* Call insns which are *not* indirect and have unfilled delay slots. */
3452 if (GET_CODE (insn) == CALL_INSN)
3455 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
3456 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
3458 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
3459 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
3465 /* Jumps inside switch tables which have unfilled delay slots
3466 also need adjustment. */
3467 else if (GET_CODE (insn) == JUMP_INSN
3468 && simplejump_p (insn)
3469 && GET_MODE (insn) == SImode)
3471 /* Millicode insn with an unfilled delay slot. */
3472 else if (GET_CODE (insn) == INSN
3473 && GET_CODE (pat) != SEQUENCE
3474 && GET_CODE (pat) != USE
3475 && GET_CODE (pat) != CLOBBER
3476 && get_attr_type (insn) == TYPE_MILLI)
3478 /* Block move pattern. */
3479 else if (GET_CODE (insn) == INSN
3480 && GET_CODE (pat) == PARALLEL
3481 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
3482 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
3483 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
3484 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
3485 return compute_movstrsi_length (insn) - 4;
3486 /* Conditional branch with an unfilled delay slot. */
3487 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
3489 /* Adjust a short backwards conditional with an unfilled delay slot. */
3490 if (GET_CODE (pat) == SET
3492 && ! forward_branch_p (insn))
3494 else if (GET_CODE (pat) == PARALLEL
3495 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
3498 /* Adjust dbra insn with short backwards conditional branch with
3499 unfilled delay slot -- only for case where counter is in a
3500 general register register. */
3501 else if (GET_CODE (pat) == PARALLEL
3502 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
3503 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
3504 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
3506 && ! forward_branch_p (insn))
3514 /* Print operand X (an rtx) in assembler syntax to file FILE.
3515 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3516 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3519 print_operand (file, x, code)
3527 /* Output a 'nop' if there's nothing for the delay slot. */
3528 if (dbr_sequence_length () == 0)
3529 fputs ("\n\tnop", file);
3532 /* Output an nullification completer if there's nothing for the */
3533 /* delay slot or nullification is requested. */
3534 if (dbr_sequence_length () == 0 ||
3536 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
3540 /* Print out the second register name of a register pair.
3541 I.e., R (6) => 7. */
3542 fputs (reg_names[REGNO (x)+1], file);
3545 /* A register or zero. */
3547 || (x == CONST0_RTX (DFmode))
3548 || (x == CONST0_RTX (SFmode)))
3550 fputs ("%r0", file);
3556 /* A register or zero (floating point). */
3558 || (x == CONST0_RTX (DFmode))
3559 || (x == CONST0_RTX (SFmode)))
3561 fputs ("%fr0", file);
3566 case 'C': /* Plain (C)ondition */
3568 switch (GET_CODE (x))
3571 fputs ("=", file); break;
3573 fputs ("<>", file); break;
3575 fputs (">", file); break;
3577 fputs (">=", file); break;
3579 fputs (">>=", file); break;
3581 fputs (">>", file); break;
3583 fputs ("<", file); break;
3585 fputs ("<=", file); break;
3587 fputs ("<<=", file); break;
3589 fputs ("<<", file); break;
3594 case 'N': /* Condition, (N)egated */
3595 switch (GET_CODE (x))
3598 fputs ("<>", file); break;
3600 fputs ("=", file); break;
3602 fputs ("<=", file); break;
3604 fputs ("<", file); break;
3606 fputs ("<<", file); break;
3608 fputs ("<<=", file); break;
3610 fputs (">=", file); break;
3612 fputs (">", file); break;
3614 fputs (">>", file); break;
3616 fputs (">>=", file); break;
3621 /* For floating point comparisons. Need special conditions to deal
3622 with NaNs properly. */
3624 switch (GET_CODE (x))
3627 fputs ("!=", file); break;
3629 fputs ("=", file); break;
3631 fputs ("<=", file); break;
3633 fputs ("<", file); break;
3635 fputs (">=", file); break;
3637 fputs (">", file); break;
3642 case 'S': /* Condition, operands are (S)wapped. */
3643 switch (GET_CODE (x))
3646 fputs ("=", file); break;
3648 fputs ("<>", file); break;
3650 fputs ("<", file); break;
3652 fputs ("<=", file); break;
3654 fputs ("<<=", file); break;
3656 fputs ("<<", file); break;
3658 fputs (">", file); break;
3660 fputs (">=", file); break;
3662 fputs (">>=", file); break;
3664 fputs (">>", file); break;
3669 case 'B': /* Condition, (B)oth swapped and negate. */
3670 switch (GET_CODE (x))
3673 fputs ("<>", file); break;
3675 fputs ("=", file); break;
3677 fputs (">=", file); break;
3679 fputs (">", file); break;
3681 fputs (">>", file); break;
3683 fputs (">>=", file); break;
3685 fputs ("<=", file); break;
3687 fputs ("<", file); break;
3689 fputs ("<<", file); break;
3691 fputs ("<<=", file); break;
3697 if (GET_CODE (x) == CONST_INT)
3699 fprintf (file, "%d", ~INTVAL (x));
3704 if (GET_CODE (x) == CONST_INT)
3706 fprintf (file, "%d", 32 - (INTVAL (x) & 31));
3711 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
3713 fprintf (file, "%d", exact_log2 (INTVAL (x)));
3718 if (GET_CODE (x) == CONST_INT)
3720 fprintf (file, "%d", 31 - (INTVAL (x) & 31));
3725 if (GET_CODE (x) == CONST_INT)
3730 switch (GET_CODE (XEXP (x, 0)))
3734 fputs ("s,mb", file);
3738 fputs ("s,ma", file);
3741 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3742 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
3743 fputs ("x,s", file);
3744 else if (code == 'F')
3754 output_global_address (file, x, 0);
3757 output_global_address (file, x, 1);
3759 case 0: /* Don't do anything special */
3764 compute_zdepi_operands (INTVAL (x), op);
3765 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
3771 if (GET_CODE (x) == REG)
3773 fputs (reg_names [REGNO (x)], file);
3774 if (FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4 && (REGNO (x) & 1) == 0)
3777 else if (GET_CODE (x) == MEM)
3779 int size = GET_MODE_SIZE (GET_MODE (x));
3780 rtx base = XEXP (XEXP (x, 0), 0);
3781 switch (GET_CODE (XEXP (x, 0)))
3785 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
3789 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
3792 if (GET_CODE (XEXP (x, 0)) == PLUS
3793 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
3794 fprintf (file, "%s(%s)",
3795 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
3796 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
3797 else if (GET_CODE (XEXP (x, 0)) == PLUS
3798 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
3799 fprintf (file, "%s(%s)",
3800 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
3801 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
3803 output_address (XEXP (x, 0));
3808 output_addr_const (file, x);
3811 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
3814 output_global_address (file, x, round_constant)
3820 /* Imagine (high (const (plus ...))). */
3821 if (GET_CODE (x) == HIGH)
3824 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x))
3825 assemble_name (file, XSTR (x, 0));
3826 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
3828 assemble_name (file, XSTR (x, 0));
3829 fputs ("-$global$", file);
3831 else if (GET_CODE (x) == CONST)
3834 int offset = 0; /* assembler wants -$global$ at end */
3835 rtx base = NULL_RTX;
3837 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
3839 base = XEXP (XEXP (x, 0), 0);
3840 output_addr_const (file, base);
3842 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
3843 offset = INTVAL (XEXP (XEXP (x, 0), 0));
3846 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
3848 base = XEXP (XEXP (x, 0), 1);
3849 output_addr_const (file, base);
3851 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
3852 offset = INTVAL (XEXP (XEXP (x, 0),1));
3855 /* How bogus. The compiler is apparently responsible for
3856 rounding the constant if it uses an LR field selector.
3858 The linker and/or assembler seem a better place since
3859 they have to do this kind of thing already.
3861 If we fail to do this, HP's optimizing linker may eliminate
3862 an addil, but not update the ldw/stw/ldo instruction that
3863 uses the result of the addil. */
3865 offset = ((offset + 0x1000) & ~0x1fff);
3867 if (GET_CODE (XEXP (x, 0)) == PLUS)
3877 else if (GET_CODE (XEXP (x, 0)) == MINUS
3878 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3882 if (!read_only_operand (base) && !flag_pic)
3883 fputs ("-$global$", file);
3885 fprintf (file,"%s%d", sep, offset);
3888 output_addr_const (file, x);
3892 output_deferred_plabels (file)
3896 /* If we have deferred plabels, then we need to switch into the data
3897 section and align it to a 4 byte boundary before we output the
3898 deferred plabels. */
3899 if (n_deferred_plabels)
3902 ASM_OUTPUT_ALIGN (file, 2);
3905 /* Now output the deferred plabels. */
3906 for (i = 0; i < n_deferred_plabels; i++)
3908 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
3909 assemble_integer (gen_rtx_SYMBOL_REF (VOIDmode,
3910 deferred_plabels[i].name), 4, 1);
3914 /* HP's millicode routines mean something special to the assembler.
3915 Keep track of which ones we have used. */
3917 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
3918 static char imported[(int)end1000];
3919 static char *milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
3920 static char import_string[] = ".IMPORT $$....,MILLICODE";
3921 #define MILLI_START 10
3925 enum millicodes code;
3927 char str[sizeof (import_string)];
3929 if (!imported[(int)code])
3931 imported[(int)code] = 1;
3932 strcpy (str, import_string);
3933 strncpy (str + MILLI_START, milli_names[(int)code], 4);
3934 output_asm_insn (str, 0);
3938 /* The register constraints have put the operands and return value in
3939 the proper registers. */
3942 output_mul_insn (unsignedp, insn)
3943 int unsignedp ATTRIBUTE_UNUSED;
3946 import_milli (mulI);
3947 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (SImode, "$$mulI"));
3950 /* Emit the rtl for doing a division by a constant. */
3952 /* Do magic division millicodes exist for this value? */
3953 static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
3956 /* We'll use an array to keep track of the magic millicodes and
3957 whether or not we've used them already. [n][0] is signed, [n][1] is
3960 static int div_milli[16][2];
3963 div_operand (op, mode)
3965 enum machine_mode mode;
3967 return (mode == SImode
3968 && ((GET_CODE (op) == REG && REGNO (op) == 25)
3969 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
3970 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
3974 emit_hpdiv_const (operands, unsignedp)
3978 if (GET_CODE (operands[2]) == CONST_INT
3979 && INTVAL (operands[2]) > 0
3980 && INTVAL (operands[2]) < 16
3981 && magic_milli[INTVAL (operands[2])])
3983 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
3986 (PARALLEL, VOIDmode,
3987 gen_rtvec (5, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
3988 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
3990 gen_rtx_REG (SImode, 26),
3992 gen_rtx_CLOBBER (VOIDmode, operands[3]),
3993 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
3994 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
3995 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 31)))));
3996 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4003 output_div_insn (operands, unsignedp, insn)
4010 /* If the divisor is a constant, try to use one of the special
4012 if (GET_CODE (operands[0]) == CONST_INT)
4014 static char buf[100];
4015 divisor = INTVAL (operands[0]);
4016 if (!div_milli[divisor][unsignedp])
4018 div_milli[divisor][unsignedp] = 1;
4020 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4022 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4026 sprintf (buf, "$$divU_%d", INTVAL (operands[0]));
4027 return output_millicode_call (insn,
4028 gen_rtx_SYMBOL_REF (SImode, buf));
4032 sprintf (buf, "$$divI_%d", INTVAL (operands[0]));
4033 return output_millicode_call (insn,
4034 gen_rtx_SYMBOL_REF (SImode, buf));
4037 /* Divisor isn't a special constant. */
4042 import_milli (divU);
4043 return output_millicode_call (insn,
4044 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4048 import_milli (divI);
4049 return output_millicode_call (insn,
4050 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4055 /* Output a $$rem millicode to do mod. */
4058 output_mod_insn (unsignedp, insn)
4064 import_milli (remU);
4065 return output_millicode_call (insn,
4066 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4070 import_milli (remI);
4071 return output_millicode_call (insn,
4072 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4077 output_arg_descriptor (call_insn)
4081 enum machine_mode arg_mode;
4083 int i, output_flag = 0;
4086 for (i = 0; i < 4; i++)
4089 /* Specify explicitly that no argument relocations should take place
4090 if using the portable runtime calling conventions. */
4091 if (TARGET_PORTABLE_RUNTIME)
4093 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4098 if (GET_CODE (call_insn) != CALL_INSN)
4100 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4102 rtx use = XEXP (link, 0);
4104 if (! (GET_CODE (use) == USE
4105 && GET_CODE (XEXP (use, 0)) == REG
4106 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4109 arg_mode = GET_MODE (XEXP (use, 0));
4110 regno = REGNO (XEXP (use, 0));
4111 if (regno >= 23 && regno <= 26)
4113 arg_regs[26 - regno] = "GR";
4114 if (arg_mode == DImode)
4115 arg_regs[25 - regno] = "GR";
4117 else if (regno >= 32 && regno <= 39)
4119 if (arg_mode == SFmode)
4120 arg_regs[(regno - 32) / 2] = "FR";
4123 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4124 arg_regs[(regno - 34) / 2] = "FR";
4125 arg_regs[(regno - 34) / 2 + 1] = "FU";
4127 arg_regs[(regno - 34) / 2] = "FU";
4128 arg_regs[(regno - 34) / 2 + 1] = "FR";
4133 fputs ("\t.CALL ", asm_out_file);
4134 for (i = 0; i < 4; i++)
4139 fputc (',', asm_out_file);
4140 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4143 fputc ('\n', asm_out_file);
4146 /* Return the class of any secondary reload register that is needed to
4147 move IN into a register in class CLASS using mode MODE.
4149 Profiling has showed this routine and its descendants account for
4150 a significant amount of compile time (~7%). So it has been
4151 optimized to reduce redundant computations and eliminate useless
4154 It might be worthwhile to try and make this a leaf function too. */
4157 secondary_reload_class (class, mode, in)
4158 enum reg_class class;
4159 enum machine_mode mode;
4162 int regno, is_symbolic;
4164 /* Trying to load a constant into a FP register during PIC code
4165 generation will require %r1 as a scratch register. */
4167 && GET_MODE_CLASS (mode) == MODE_INT
4168 && FP_REG_CLASS_P (class)
4169 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4172 /* Profiling showed the PA port spends about 1.3% of its compilation
4173 time in true_regnum from calls inside secondary_reload_class. */
4175 if (GET_CODE (in) == REG)
4178 if (regno >= FIRST_PSEUDO_REGISTER)
4179 regno = true_regnum (in);
4181 else if (GET_CODE (in) == SUBREG)
4182 regno = true_regnum (in);
4186 /* If we have something like (mem (mem (...)), we can safely assume the
4187 inner MEM will end up in a general register after reloading, so there's
4188 no need for a secondary reload. */
4189 if (GET_CODE (in) == MEM
4190 && GET_CODE (XEXP (in, 0)) == MEM)
4193 /* Handle out of range displacement for integer mode loads/stores of
4195 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
4196 && GET_MODE_CLASS (mode) == MODE_INT
4197 && FP_REG_CLASS_P (class))
4198 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
4199 return GENERAL_REGS;
4201 if (GET_CODE (in) == HIGH)
4204 /* Profiling has showed GCC spends about 2.6% of its compilation
4205 time in symbolic_operand from calls inside secondary_reload_class.
4207 We use an inline copy and only compute its return value once to avoid
4209 switch (GET_CODE (in))
4219 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
4220 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
4221 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
4231 && read_only_operand (in))
4234 if (class != R1_REGS && is_symbolic)
4241 function_arg_padding (mode, type)
4242 enum machine_mode mode;
4247 if (mode == BLKmode)
4249 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4250 size = int_size_in_bytes (type) * BITS_PER_UNIT;
4252 return upward; /* Don't know if this is right, but */
4253 /* same as old definition. */
4256 size = GET_MODE_BITSIZE (mode);
4257 if (size < PARM_BOUNDARY)
4259 else if (size % PARM_BOUNDARY)
4266 /* Do what is necessary for `va_start'. The argument is ignored;
4267 We look at the current function to determine if stdargs or varargs
4268 is used and fill in an initial va_list. A pointer to this constructor
4272 hppa_builtin_saveregs (arglist)
4273 tree arglist ATTRIBUTE_UNUSED;
4276 tree fntype = TREE_TYPE (current_function_decl);
4277 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
4278 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4279 != void_type_node)))
4280 ? UNITS_PER_WORD : 0);
4283 offset = plus_constant (current_function_arg_offset_rtx, argadj);
4285 offset = current_function_arg_offset_rtx;
4287 /* Store general registers on the stack. */
4288 dest = gen_rtx_MEM (BLKmode,
4289 plus_constant (current_function_internal_arg_pointer,
4291 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
4293 /* move_block_from_reg will emit code to store the argument registers
4294 individually as scalar stores.
4296 However, other insns may later load from the same addresses for
4297 a structure load (passing a struct to a varargs routine).
4299 The alias code assumes that such aliasing can never happen, so we
4300 have to keep memory referencing insns from moving up beyond the
4301 last argument register store. So we emit a blockage insn here. */
4302 emit_insn (gen_blockage ());
4304 if (current_function_check_memory_usage)
4305 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4307 GEN_INT (4 * UNITS_PER_WORD), TYPE_MODE (sizetype),
4308 GEN_INT (MEMORY_USE_RW),
4309 TYPE_MODE (integer_type_node));
4311 return copy_to_reg (expand_binop (Pmode, add_optab,
4312 current_function_internal_arg_pointer,
4313 offset, 0, 0, OPTAB_LIB_WIDEN));
4316 /* This routine handles all the normal conditional branch sequences we
4317 might need to generate. It handles compare immediate vs compare
4318 register, nullification of delay slots, varying length branches,
4319 negated branches, and all combinations of the above. It returns the
4320 output appropriate to emit the branch corresponding to all given
4324 output_cbranch (operands, nullify, length, negated, insn)
4326 int nullify, length, negated;
4329 static char buf[100];
4332 /* A conditional branch to the following instruction (eg the delay slot) is
4333 asking for a disaster. This can happen when not optimizing.
4335 In such cases it is safe to emit nothing. */
4337 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4340 /* If this is a long branch with its delay slot unfilled, set `nullify'
4341 as it can nullify the delay slot and save a nop. */
4342 if (length == 8 && dbr_sequence_length () == 0)
4345 /* If this is a short forward conditional branch which did not get
4346 its delay slot filled, the delay slot can still be nullified. */
4347 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4348 nullify = forward_branch_p (insn);
4350 /* A forward branch over a single nullified insn can be done with a
4351 comclr instruction. This avoids a single cycle penalty due to
4352 mis-predicted branch if we fall through (branch not taken). */
4354 && next_real_insn (insn) != 0
4355 && get_attr_length (next_real_insn (insn)) == 4
4356 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4362 /* All short conditional branches except backwards with an unfilled
4366 strcpy (buf, "com%I2clr,");
4368 strcpy (buf, "com%I2b,");
4370 strcat (buf, "%B3");
4372 strcat (buf, "%S3");
4374 strcat (buf, " %2,%r1,%%r0");
4376 strcat (buf, ",n %2,%r1,%0");
4378 strcat (buf, " %2,%r1,%0");
4381 /* All long conditionals. Note an short backward branch with an
4382 unfilled delay slot is treated just like a long backward branch
4383 with an unfilled delay slot. */
4385 /* Handle weird backwards branch with a filled delay slot
4386 with is nullified. */
4387 if (dbr_sequence_length () != 0
4388 && ! forward_branch_p (insn)
4391 strcpy (buf, "com%I2b,");
4393 strcat (buf, "%S3");
4395 strcat (buf, "%B3");
4396 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
4398 /* Handle short backwards branch with an unfilled delay slot.
4399 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
4400 taken and untaken branches. */
4401 else if (dbr_sequence_length () == 0
4402 && ! forward_branch_p (insn)
4404 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4405 - insn_addresses[INSN_UID (insn)] - 8))
4407 strcpy (buf, "com%I2b,");
4409 strcat (buf, "%B3 %2,%r1,%0%#");
4411 strcat (buf, "%S3 %2,%r1,%0%#");
4415 strcpy (buf, "com%I2clr,");
4417 strcat (buf, "%S3");
4419 strcat (buf, "%B3");
4421 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
4423 strcat (buf, " %2,%r1,%%r0\n\tb %0");
4428 /* Very long branch. Right now we only handle these when not
4429 optimizing. See "jump" pattern in pa.md for details. */
4433 /* Create a reversed conditional branch which branches around
4434 the following insns. */
4436 strcpy (buf, "com%I2b,%S3,n %2,%r1,.+20");
4438 strcpy (buf, "com%I2b,%B3,n %2,%r1,.+20");
4439 output_asm_insn (buf, operands);
4441 /* Output an insn to save %r1. */
4442 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
4444 /* Now output a very long branch to the original target. */
4445 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
4447 /* Now restore the value of %r1 in the delay slot. We're not
4448 optimizing so we know nothing else can be in the delay slot. */
4449 return "ldw -16(%%r30),%%r1";
4452 /* Very long branch when generating PIC code. Right now we only
4453 handle these when not optimizing. See "jump" pattern in pa.md
4458 /* Create a reversed conditional branch which branches around
4459 the following insns. */
4461 strcpy (buf, "com%I2b,%S3,n %2,%r1,.+28");
4463 strcpy (buf, "com%I2b,%B3,n %2,%r1,.+28");
4464 output_asm_insn (buf, operands);
4466 /* Output an insn to save %r1. */
4467 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
4469 /* Now output a very long PIC branch to the original target. */
4473 xoperands[0] = operands[0];
4474 xoperands[1] = operands[1];
4475 xoperands[2] = operands[2];
4476 xoperands[3] = operands[3];
4477 xoperands[4] = gen_label_rtx ();
4479 output_asm_insn ("bl .+8,%%r1\n\taddil L'%l0-%l4,%%r1", xoperands);
4480 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4481 CODE_LABEL_NUMBER (xoperands[4]));
4482 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
4486 /* Now restore the value of %r1 in the delay slot. We're not
4487 optimizing so we know nothing else can be in the delay slot. */
4488 return "ldw -16(%%r30),%%r1";
4496 /* This routine handles all the branch-on-bit conditional branch sequences we
4497 might need to generate. It handles nullification of delay slots,
4498 varying length branches, negated branches and all combinations of the
4499 above. it returns the appropriate output template to emit the branch. */
4502 output_bb (operands, nullify, length, negated, insn, which)
4503 rtx *operands ATTRIBUTE_UNUSED;
4504 int nullify, length, negated;
4508 static char buf[100];
4511 /* A conditional branch to the following instruction (eg the delay slot) is
4512 asking for a disaster. I do not think this can happen as this pattern
4513 is only used when optimizing; jump optimization should eliminate the
4514 jump. But be prepared just in case. */
4516 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4519 /* If this is a long branch with its delay slot unfilled, set `nullify'
4520 as it can nullify the delay slot and save a nop. */
4521 if (length == 8 && dbr_sequence_length () == 0)
4524 /* If this is a short forward conditional branch which did not get
4525 its delay slot filled, the delay slot can still be nullified. */
4526 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4527 nullify = forward_branch_p (insn);
4529 /* A forward branch over a single nullified insn can be done with a
4530 extrs instruction. This avoids a single cycle penalty due to
4531 mis-predicted branch if we fall through (branch not taken). */
4534 && next_real_insn (insn) != 0
4535 && get_attr_length (next_real_insn (insn)) == 4
4536 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4543 /* All short conditional branches except backwards with an unfilled
4547 strcpy (buf, "extrs,");
4549 strcpy (buf, "bb,");
4550 if ((which == 0 && negated)
4551 || (which == 1 && ! negated))
4556 strcat (buf, " %0,%1,1,%%r0");
4557 else if (nullify && negated)
4558 strcat (buf, ",n %0,%1,%3");
4559 else if (nullify && ! negated)
4560 strcat (buf, ",n %0,%1,%2");
4561 else if (! nullify && negated)
4562 strcat (buf, "%0,%1,%3");
4563 else if (! nullify && ! negated)
4564 strcat (buf, " %0,%1,%2");
4567 /* All long conditionals. Note an short backward branch with an
4568 unfilled delay slot is treated just like a long backward branch
4569 with an unfilled delay slot. */
4571 /* Handle weird backwards branch with a filled delay slot
4572 with is nullified. */
4573 if (dbr_sequence_length () != 0
4574 && ! forward_branch_p (insn)
4577 strcpy (buf, "bb,");
4578 if ((which == 0 && negated)
4579 || (which == 1 && ! negated))
4584 strcat (buf, ",n %0,%1,.+12\n\tb %3");
4586 strcat (buf, ",n %0,%1,.+12\n\tb %2");
4588 /* Handle short backwards branch with an unfilled delay slot.
4589 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4590 taken and untaken branches. */
4591 else if (dbr_sequence_length () == 0
4592 && ! forward_branch_p (insn)
4594 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4595 - insn_addresses[INSN_UID (insn)] - 8))
4597 strcpy (buf, "bb,");
4598 if ((which == 0 && negated)
4599 || (which == 1 && ! negated))
4604 strcat (buf, " %0,%1,%3%#");
4606 strcat (buf, " %0,%1,%2%#");
4610 strcpy (buf, "extrs,");
4611 if ((which == 0 && negated)
4612 || (which == 1 && ! negated))
4616 if (nullify && negated)
4617 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
4618 else if (nullify && ! negated)
4619 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
4621 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
4623 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
4633 /* This routine handles all the branch-on-variable-bit conditional branch
4634 sequences we might need to generate. It handles nullification of delay
4635 slots, varying length branches, negated branches and all combinations
4636 of the above. it returns the appropriate output template to emit the
4640 output_bvb (operands, nullify, length, negated, insn, which)
4641 rtx *operands ATTRIBUTE_UNUSED;
4642 int nullify, length, negated;
4646 static char buf[100];
4649 /* A conditional branch to the following instruction (eg the delay slot) is
4650 asking for a disaster. I do not think this can happen as this pattern
4651 is only used when optimizing; jump optimization should eliminate the
4652 jump. But be prepared just in case. */
4654 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4657 /* If this is a long branch with its delay slot unfilled, set `nullify'
4658 as it can nullify the delay slot and save a nop. */
4659 if (length == 8 && dbr_sequence_length () == 0)
4662 /* If this is a short forward conditional branch which did not get
4663 its delay slot filled, the delay slot can still be nullified. */
4664 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4665 nullify = forward_branch_p (insn);
4667 /* A forward branch over a single nullified insn can be done with a
4668 extrs instruction. This avoids a single cycle penalty due to
4669 mis-predicted branch if we fall through (branch not taken). */
4672 && next_real_insn (insn) != 0
4673 && get_attr_length (next_real_insn (insn)) == 4
4674 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4681 /* All short conditional branches except backwards with an unfilled
4685 strcpy (buf, "vextrs,");
4687 strcpy (buf, "bvb,");
4688 if ((which == 0 && negated)
4689 || (which == 1 && ! negated))
4694 strcat (buf, " %0,1,%%r0");
4695 else if (nullify && negated)
4696 strcat (buf, ",n %0,%3");
4697 else if (nullify && ! negated)
4698 strcat (buf, ",n %0,%2");
4699 else if (! nullify && negated)
4700 strcat (buf, "%0,%3");
4701 else if (! nullify && ! negated)
4702 strcat (buf, " %0,%2");
4705 /* All long conditionals. Note an short backward branch with an
4706 unfilled delay slot is treated just like a long backward branch
4707 with an unfilled delay slot. */
4709 /* Handle weird backwards branch with a filled delay slot
4710 with is nullified. */
4711 if (dbr_sequence_length () != 0
4712 && ! forward_branch_p (insn)
4715 strcpy (buf, "bvb,");
4716 if ((which == 0 && negated)
4717 || (which == 1 && ! negated))
4722 strcat (buf, ",n %0,.+12\n\tb %3");
4724 strcat (buf, ",n %0,.+12\n\tb %2");
4726 /* Handle short backwards branch with an unfilled delay slot.
4727 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4728 taken and untaken branches. */
4729 else if (dbr_sequence_length () == 0
4730 && ! forward_branch_p (insn)
4732 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4733 - insn_addresses[INSN_UID (insn)] - 8))
4735 strcpy (buf, "bvb,");
4736 if ((which == 0 && negated)
4737 || (which == 1 && ! negated))
4742 strcat (buf, " %0,%3%#");
4744 strcat (buf, " %0,%2%#");
4748 strcpy (buf, "vextrs,");
4749 if ((which == 0 && negated)
4750 || (which == 1 && ! negated))
4754 if (nullify && negated)
4755 strcat (buf, " %0,1,%%r0\n\tb,n %3");
4756 else if (nullify && ! negated)
4757 strcat (buf, " %0,1,%%r0\n\tb,n %2");
4759 strcat (buf, " %0,1,%%r0\n\tb %3");
4761 strcat (buf, " %0,1,%%r0\n\tb %2");
4771 /* Return the output template for emitting a dbra type insn.
4773 Note it may perform some output operations on its own before
4774 returning the final output string. */
4776 output_dbra (operands, insn, which_alternative)
4779 int which_alternative;
4782 /* A conditional branch to the following instruction (eg the delay slot) is
4783 asking for a disaster. Be prepared! */
4785 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4787 if (which_alternative == 0)
4788 return "ldo %1(%0),%0";
4789 else if (which_alternative == 1)
4791 output_asm_insn ("fstws %0,-16(%%r30)",operands);
4792 output_asm_insn ("ldw -16(%%r30),%4",operands);
4793 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
4794 return "fldws -16(%%r30),%0";
4798 output_asm_insn ("ldw %0,%4", operands);
4799 return "ldo %1(%4),%4\n\tstw %4,%0";
4803 if (which_alternative == 0)
4805 int nullify = INSN_ANNULLED_BRANCH_P (insn);
4806 int length = get_attr_length (insn);
4808 /* If this is a long branch with its delay slot unfilled, set `nullify'
4809 as it can nullify the delay slot and save a nop. */
4810 if (length == 8 && dbr_sequence_length () == 0)
4813 /* If this is a short forward conditional branch which did not get
4814 its delay slot filled, the delay slot can still be nullified. */
4815 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4816 nullify = forward_branch_p (insn);
4818 /* Handle short versions first. */
4819 if (length == 4 && nullify)
4820 return "addib,%C2,n %1,%0,%3";
4821 else if (length == 4 && ! nullify)
4822 return "addib,%C2 %1,%0,%3";
4823 else if (length == 8)
4825 /* Handle weird backwards branch with a fulled delay slot
4826 which is nullified. */
4827 if (dbr_sequence_length () != 0
4828 && ! forward_branch_p (insn)
4830 return "addib,%N2,n %1,%0,.+12\n\tb %3";
4831 /* Handle short backwards branch with an unfilled delay slot.
4832 Using a addb;nop rather than addi;bl saves 1 cycle for both
4833 taken and untaken branches. */
4834 else if (dbr_sequence_length () == 0
4835 && ! forward_branch_p (insn)
4837 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4838 - insn_addresses[INSN_UID (insn)] - 8))
4839 return "addib,%C2 %1,%0,%3%#";
4841 /* Handle normal cases. */
4843 return "addi,%N2 %1,%0,%0\n\tb,n %3";
4845 return "addi,%N2 %1,%0,%0\n\tb %3";
4850 /* Deal with gross reload from FP register case. */
4851 else if (which_alternative == 1)
4853 /* Move loop counter from FP register to MEM then into a GR,
4854 increment the GR, store the GR into MEM, and finally reload
4855 the FP register from MEM from within the branch's delay slot. */
4856 output_asm_insn ("fstws %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands);
4857 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
4858 if (get_attr_length (insn) == 24)
4859 return "comb,%S2 %%r0,%4,%3\n\tfldws -16(%%r30),%0";
4861 return "comclr,%B2 %%r0,%4,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
4863 /* Deal with gross reload from memory case. */
4866 /* Reload loop counter from memory, the store back to memory
4867 happens in the branch's delay slot. */
4868 output_asm_insn ("ldw %0,%4", operands);
4869 if (get_attr_length (insn) == 12)
4870 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
4872 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
4876 /* Return the output template for emitting a dbra type insn.
4878 Note it may perform some output operations on its own before
4879 returning the final output string. */
4881 output_movb (operands, insn, which_alternative, reverse_comparison)
4884 int which_alternative;
4885 int reverse_comparison;
4888 /* A conditional branch to the following instruction (eg the delay slot) is
4889 asking for a disaster. Be prepared! */
4891 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4893 if (which_alternative == 0)
4894 return "copy %1,%0";
4895 else if (which_alternative == 1)
4897 output_asm_insn ("stw %1,-16(%%r30)",operands);
4898 return "fldws -16(%%r30),%0";
4900 else if (which_alternative == 2)
4906 /* Support the second variant. */
4907 if (reverse_comparison)
4908 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
4910 if (which_alternative == 0)
4912 int nullify = INSN_ANNULLED_BRANCH_P (insn);
4913 int length = get_attr_length (insn);
4915 /* If this is a long branch with its delay slot unfilled, set `nullify'
4916 as it can nullify the delay slot and save a nop. */
4917 if (length == 8 && dbr_sequence_length () == 0)
4920 /* If this is a short forward conditional branch which did not get
4921 its delay slot filled, the delay slot can still be nullified. */
4922 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4923 nullify = forward_branch_p (insn);
4925 /* Handle short versions first. */
4926 if (length == 4 && nullify)
4927 return "movb,%C2,n %1,%0,%3";
4928 else if (length == 4 && ! nullify)
4929 return "movb,%C2 %1,%0,%3";
4930 else if (length == 8)
4932 /* Handle weird backwards branch with a filled delay slot
4933 which is nullified. */
4934 if (dbr_sequence_length () != 0
4935 && ! forward_branch_p (insn)
4937 return "movb,%N2,n %1,%0,.+12\n\tb %3";
4939 /* Handle short backwards branch with an unfilled delay slot.
4940 Using a movb;nop rather than or;bl saves 1 cycle for both
4941 taken and untaken branches. */
4942 else if (dbr_sequence_length () == 0
4943 && ! forward_branch_p (insn)
4945 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4946 - insn_addresses[INSN_UID (insn)] - 8))
4947 return "movb,%C2 %1,%0,%3%#";
4948 /* Handle normal cases. */
4950 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
4952 return "or,%N2 %1,%%r0,%0\n\tb %3";
4957 /* Deal with gross reload from FP register case. */
4958 else if (which_alternative == 1)
4960 /* Move loop counter from FP register to MEM then into a GR,
4961 increment the GR, store the GR into MEM, and finally reload
4962 the FP register from MEM from within the branch's delay slot. */
4963 output_asm_insn ("stw %1,-16(%%r30)",operands);
4964 if (get_attr_length (insn) == 12)
4965 return "comb,%S2 %%r0,%1,%3\n\tfldws -16(%%r30),%0";
4967 return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
4969 /* Deal with gross reload from memory case. */
4970 else if (which_alternative == 2)
4972 /* Reload loop counter from memory, the store back to memory
4973 happens in the branch's delay slot. */
4974 if (get_attr_length (insn) == 8)
4975 return "comb,%S2 %%r0,%1,%3\n\tstw %1,%0";
4977 return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
4979 /* Handle SAR as a destination. */
4982 if (get_attr_length (insn) == 8)
4983 return "comb,%S2 %%r0,%1,%3\n\tmtsar %r1";
4985 return "comclr,%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
4990 /* INSN is a millicode call. It may have an unconditional jump in its delay
4993 CALL_DEST is the routine we are calling. */
4996 output_millicode_call (insn, call_dest)
5004 /* Handle common case -- empty delay slot or no jump in the delay slot,
5005 and we're sure that the branch will reach the beginning of the $CODE$
5007 if ((dbr_sequence_length () == 0
5008 && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
5009 || (dbr_sequence_length () != 0
5010 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5011 && get_attr_length (insn) == 4))
5013 xoperands[0] = call_dest;
5014 output_asm_insn ("bl %0,%%r31%#", xoperands);
5018 /* This call may not reach the beginning of the $CODE$ subspace. */
5019 if (get_attr_length (insn) > 4)
5021 int delay_insn_deleted = 0;
5024 /* We need to emit an inline long-call branch. */
5025 if (dbr_sequence_length () != 0
5026 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5028 /* A non-jump insn in the delay slot. By definition we can
5029 emit this insn before the call. */
5030 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5032 /* Now delete the delay insn. */
5033 PUT_CODE (NEXT_INSN (insn), NOTE);
5034 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5035 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5036 delay_insn_deleted = 1;
5039 /* If we're allowed to use be/ble instructions, then this is the
5040 best sequence to use for a long millicode call. */
5041 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS
5042 || ! (flag_pic || TARGET_PORTABLE_RUNTIME))
5044 xoperands[0] = call_dest;
5045 output_asm_insn ("ldil L%%%0,%%r31", xoperands);
5046 output_asm_insn ("ble R%%%0(%%sr4,%%r31)", xoperands);
5047 output_asm_insn ("nop", xoperands);
5049 /* Pure portable runtime doesn't allow be/ble; we also don't have
5050 PIC support int he assembler/linker, so this sequence is needed. */
5051 else if (TARGET_PORTABLE_RUNTIME)
5053 xoperands[0] = call_dest;
5054 /* Get the address of our target into %r29. */
5055 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
5056 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
5058 /* Get our return address into %r31. */
5059 output_asm_insn ("blr %%r0,%%r31", xoperands);
5061 /* Jump to our target address in %r29. */
5062 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
5064 /* Empty delay slot. Note this insn gets fetched twice and
5065 executed once. To be safe we use a nop. */
5066 output_asm_insn ("nop", xoperands);
5069 /* PIC long millicode call sequence. */
5072 xoperands[0] = call_dest;
5073 xoperands[1] = gen_label_rtx ();
5074 /* Get our address + 8 into %r1. */
5075 output_asm_insn ("bl .+8,%%r1", xoperands);
5077 /* Add %r1 to the offset of our target from the next insn. */
5078 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
5079 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5080 CODE_LABEL_NUMBER (xoperands[1]));
5081 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
5083 /* Get the return address into %r31. */
5084 output_asm_insn ("blr 0,%%r31", xoperands);
5086 /* Branch to our target which is in %r1. */
5087 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
5089 /* Empty delay slot. Note this insn gets fetched twice and
5090 executed once. To be safe we use a nop. */
5091 output_asm_insn ("nop", xoperands);
5094 /* If we had a jump in the call's delay slot, output it now. */
5095 if (dbr_sequence_length () != 0
5096 && !delay_insn_deleted)
5098 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5099 output_asm_insn ("b,n %0", xoperands);
5101 /* Now delete the delay insn. */
5102 PUT_CODE (NEXT_INSN (insn), NOTE);
5103 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5104 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5109 /* This call has an unconditional jump in its delay slot and the
5110 call is known to reach its target or the beginning of the current
5113 /* Use the containing sequence insn's address. */
5114 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5116 distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
5117 - insn_addresses[INSN_UID (seq_insn)] - 8;
5119 /* If the branch was too far away, emit a normal call followed
5120 by a nop, followed by the unconditional branch.
5122 If the branch is close, then adjust %r2 from within the
5123 call's delay slot. */
5125 xoperands[0] = call_dest;
5126 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5127 if (! VAL_14_BITS_P (distance))
5128 output_asm_insn ("bl %0,%%r31\n\tnop\n\tb,n %1", xoperands);
5131 xoperands[3] = gen_label_rtx ();
5132 output_asm_insn ("\n\tbl %0,%%r31\n\tldo %1-%3(%%r31),%%r31", xoperands);
5133 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5134 CODE_LABEL_NUMBER (xoperands[3]));
5137 /* Delete the jump. */
5138 PUT_CODE (NEXT_INSN (insn), NOTE);
5139 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5140 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5144 extern struct obstack permanent_obstack;
5145 extern struct obstack *saveable_obstack;
5146 extern struct obstack *rtl_obstack;
5147 extern struct obstack *current_obstack;
5149 /* INSN is either a function call. It may have an unconditional jump
5152 CALL_DEST is the routine we are calling. */
5155 output_call (insn, call_dest)
5163 /* Handle common case -- empty delay slot or no jump in the delay slot,
5164 and we're sure that the branch will reach the beginning of the $CODE$
5166 if ((dbr_sequence_length () == 0
5167 && get_attr_length (insn) == 8)
5168 || (dbr_sequence_length () != 0
5169 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5170 && get_attr_length (insn) == 4))
5172 xoperands[0] = call_dest;
5173 output_asm_insn ("bl %0,%%r2%#", xoperands);
5177 /* This call may not reach the beginning of the $CODE$ subspace. */
5178 if (get_attr_length (insn) > 8)
5180 int delay_insn_deleted = 0;
5184 /* We need to emit an inline long-call branch. Furthermore,
5185 because we're changing a named function call into an indirect
5186 function call well after the parameters have been set up, we
5187 need to make sure any FP args appear in both the integer
5188 and FP registers. Also, we need move any delay slot insn
5189 out of the delay slot. And finally, we can't rely on the linker
5190 being able to fix the call to $$dyncall! -- Yuk!. */
5191 if (dbr_sequence_length () != 0
5192 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5194 /* A non-jump insn in the delay slot. By definition we can
5195 emit this insn before the call (and in fact before argument
5197 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5199 /* Now delete the delay insn. */
5200 PUT_CODE (NEXT_INSN (insn), NOTE);
5201 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5202 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5203 delay_insn_deleted = 1;
5206 /* Now copy any FP arguments into integer registers. */
5207 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
5209 int arg_mode, regno;
5210 rtx use = XEXP (link, 0);
5211 if (! (GET_CODE (use) == USE
5212 && GET_CODE (XEXP (use, 0)) == REG
5213 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5216 arg_mode = GET_MODE (XEXP (use, 0));
5217 regno = REGNO (XEXP (use, 0));
5218 /* Is it a floating point register? */
5219 if (regno >= 32 && regno <= 39)
5221 /* Copy from the FP register into an integer register
5223 if (arg_mode == SFmode)
5225 xoperands[0] = XEXP (use, 0);
5226 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
5227 output_asm_insn ("fstws %0,-16(%%sr0,%%r30)", xoperands);
5228 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5232 xoperands[0] = XEXP (use, 0);
5233 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
5234 output_asm_insn ("fstds %0,-16(%%sr0,%%r30)", xoperands);
5235 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
5236 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5241 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5242 we don't have any direct calls in that case. */
5245 char *name = XSTR (call_dest, 0);
5247 /* See if we have already put this function on the list
5248 of deferred plabels. This list is generally small,
5249 so a liner search is not too ugly. If it proves too
5250 slow replace it with something faster. */
5251 for (i = 0; i < n_deferred_plabels; i++)
5252 if (strcmp (name, deferred_plabels[i].name) == 0)
5255 /* If the deferred plabel list is empty, or this entry was
5256 not found on the list, create a new entry on the list. */
5257 if (deferred_plabels == NULL || i == n_deferred_plabels)
5259 struct obstack *ambient_obstack = current_obstack;
5260 struct obstack *ambient_rtl_obstack = rtl_obstack;
5263 /* Any RTL we create here needs to live until the end of
5264 the compilation unit and therefore must live on the
5265 permanent obstack. */
5266 current_obstack = &permanent_obstack;
5267 rtl_obstack = &permanent_obstack;
5269 if (deferred_plabels == 0)
5270 deferred_plabels = (struct deferred_plabel *)
5271 xmalloc (1 * sizeof (struct deferred_plabel));
5273 deferred_plabels = (struct deferred_plabel *)
5274 xrealloc (deferred_plabels,
5275 ((n_deferred_plabels + 1)
5276 * sizeof (struct deferred_plabel)));
5278 i = n_deferred_plabels++;
5279 deferred_plabels[i].internal_label = gen_label_rtx ();
5280 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
5282 strcpy (deferred_plabels[i].name, name);
5284 /* Switch back to normal obstack allocation. */
5285 current_obstack = ambient_obstack;
5286 rtl_obstack = ambient_rtl_obstack;
5288 /* Gross. We have just implicitly taken the address of this
5289 function, mark it as such. */
5290 STRIP_NAME_ENCODING (real_name, name);
5291 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5294 /* We have to load the address of the function using a procedure
5295 label (plabel). Inline plabels can lose for PIC and other
5296 cases, so avoid them by creating a 32bit plabel in the data
5300 xoperands[0] = deferred_plabels[i].internal_label;
5301 xoperands[1] = gen_label_rtx ();
5303 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
5304 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
5305 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
5307 /* Get our address + 8 into %r1. */
5308 output_asm_insn ("bl .+8,%%r1", xoperands);
5310 /* Add %r1 to the offset of dyncall from the next insn. */
5311 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
5312 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5313 CODE_LABEL_NUMBER (xoperands[1]));
5314 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
5316 /* Get the return address into %r31. */
5317 output_asm_insn ("blr %%r0,%%r31", xoperands);
5319 /* Branch to our target which is in %r1. */
5320 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5322 /* Copy the return address into %r2 also. */
5323 output_asm_insn ("copy %%r31,%%r2", xoperands);
5327 xoperands[0] = deferred_plabels[i].internal_label;
5329 /* Get the address of our target into %r22. */
5330 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
5331 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
5333 /* Get the high part of the address of $dyncall into %r2, then
5334 add in the low part in the branch instruction. */
5335 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
5336 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands);
5338 /* Copy the return pointer into both %r31 and %r2. */
5339 output_asm_insn ("copy %%r31,%%r2", xoperands);
5343 /* If we had a jump in the call's delay slot, output it now. */
5344 if (dbr_sequence_length () != 0
5345 && !delay_insn_deleted)
5347 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5348 output_asm_insn ("b,n %0", xoperands);
5350 /* Now delete the delay insn. */
5351 PUT_CODE (NEXT_INSN (insn), NOTE);
5352 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5353 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5358 /* This call has an unconditional jump in its delay slot and the
5359 call is known to reach its target or the beginning of the current
5362 /* Use the containing sequence insn's address. */
5363 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5365 distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
5366 - insn_addresses[INSN_UID (seq_insn)] - 8;
5368 /* If the branch was too far away, emit a normal call followed
5369 by a nop, followed by the unconditional branch.
5371 If the branch is close, then adjust %r2 from within the
5372 call's delay slot. */
5374 xoperands[0] = call_dest;
5375 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5376 if (! VAL_14_BITS_P (distance))
5377 output_asm_insn ("bl %0,%%r2\n\tnop\n\tb,n %1", xoperands);
5380 xoperands[3] = gen_label_rtx ();
5381 output_asm_insn ("\n\tbl %0,%%r2\n\tldo %1-%3(%%r2),%%r2", xoperands);
5382 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5383 CODE_LABEL_NUMBER (xoperands[3]));
5386 /* Delete the jump. */
5387 PUT_CODE (NEXT_INSN (insn), NOTE);
5388 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5389 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5393 /* In HPUX 8.0's shared library scheme, special relocations are needed
5394 for function labels if they might be passed to a function
5395 in a shared library (because shared libraries don't live in code
5396 space), and special magic is needed to construct their address.
5398 For reasons too disgusting to describe storage for the new name
5399 is allocated either on the saveable_obstack (released at function
5400 exit) or on the permanent_obstack for things that can never change
5401 (libcall names for example). */
5404 hppa_encode_label (sym, permanent)
5408 char *str = XSTR (sym, 0);
5409 int len = strlen (str);
5412 newstr = obstack_alloc ((permanent ? &permanent_obstack : saveable_obstack),
5417 strcpy (newstr + 1, str);
5419 XSTR (sym,0) = newstr;
5423 function_label_operand (op, mode)
5425 enum machine_mode mode ATTRIBUTE_UNUSED;
5427 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
5430 /* Returns 1 if OP is a function label involved in a simple addition
5431 with a constant. Used to keep certain patterns from matching
5432 during instruction combination. */
5434 is_function_label_plus_const (op)
5437 /* Strip off any CONST. */
5438 if (GET_CODE (op) == CONST)
5441 return (GET_CODE (op) == PLUS
5442 && function_label_operand (XEXP (op, 0), Pmode)
5443 && GET_CODE (XEXP (op, 1)) == CONST_INT);
5446 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5447 use in fmpyadd instructions. */
5449 fmpyaddoperands (operands)
5452 enum machine_mode mode = GET_MODE (operands[0]);
5454 /* Must be a floating point mode. */
5455 if (mode != SFmode && mode != DFmode)
5458 /* All modes must be the same. */
5459 if (! (mode == GET_MODE (operands[1])
5460 && mode == GET_MODE (operands[2])
5461 && mode == GET_MODE (operands[3])
5462 && mode == GET_MODE (operands[4])
5463 && mode == GET_MODE (operands[5])))
5466 /* All operands must be registers. */
5467 if (! (GET_CODE (operands[1]) == REG
5468 && GET_CODE (operands[2]) == REG
5469 && GET_CODE (operands[3]) == REG
5470 && GET_CODE (operands[4]) == REG
5471 && GET_CODE (operands[5]) == REG))
5474 /* Only 2 real operands to the addition. One of the input operands must
5475 be the same as the output operand. */
5476 if (! rtx_equal_p (operands[3], operands[4])
5477 && ! rtx_equal_p (operands[3], operands[5]))
5480 /* Inout operand of add can not conflict with any operands from multiply. */
5481 if (rtx_equal_p (operands[3], operands[0])
5482 || rtx_equal_p (operands[3], operands[1])
5483 || rtx_equal_p (operands[3], operands[2]))
5486 /* multiply can not feed into addition operands. */
5487 if (rtx_equal_p (operands[4], operands[0])
5488 || rtx_equal_p (operands[5], operands[0]))
5491 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5493 && (REGNO (operands[0]) < 57
5494 || REGNO (operands[1]) < 57
5495 || REGNO (operands[2]) < 57
5496 || REGNO (operands[3]) < 57
5497 || REGNO (operands[4]) < 57
5498 || REGNO (operands[5]) < 57))
5501 /* Passed. Operands are suitable for fmpyadd. */
5505 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5506 use in fmpysub instructions. */
5508 fmpysuboperands (operands)
5511 enum machine_mode mode = GET_MODE (operands[0]);
5513 /* Must be a floating point mode. */
5514 if (mode != SFmode && mode != DFmode)
5517 /* All modes must be the same. */
5518 if (! (mode == GET_MODE (operands[1])
5519 && mode == GET_MODE (operands[2])
5520 && mode == GET_MODE (operands[3])
5521 && mode == GET_MODE (operands[4])
5522 && mode == GET_MODE (operands[5])))
5525 /* All operands must be registers. */
5526 if (! (GET_CODE (operands[1]) == REG
5527 && GET_CODE (operands[2]) == REG
5528 && GET_CODE (operands[3]) == REG
5529 && GET_CODE (operands[4]) == REG
5530 && GET_CODE (operands[5]) == REG))
5533 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
5534 operation, so operands[4] must be the same as operand[3]. */
5535 if (! rtx_equal_p (operands[3], operands[4]))
5538 /* multiply can not feed into subtraction. */
5539 if (rtx_equal_p (operands[5], operands[0]))
5542 /* Inout operand of sub can not conflict with any operands from multiply. */
5543 if (rtx_equal_p (operands[3], operands[0])
5544 || rtx_equal_p (operands[3], operands[1])
5545 || rtx_equal_p (operands[3], operands[2]))
5548 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5550 && (REGNO (operands[0]) < 57
5551 || REGNO (operands[1]) < 57
5552 || REGNO (operands[2]) < 57
5553 || REGNO (operands[3]) < 57
5554 || REGNO (operands[4]) < 57
5555 || REGNO (operands[5]) < 57))
5558 /* Passed. Operands are suitable for fmpysub. */
5563 plus_xor_ior_operator (op, mode)
5565 enum machine_mode mode ATTRIBUTE_UNUSED;
5567 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
5568 || GET_CODE (op) == IOR);
5571 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
5572 constants for shadd instructions. */
5574 shadd_constant_p (val)
5577 if (val == 2 || val == 4 || val == 8)
5583 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
5584 the valid constant for shadd instructions. */
5586 shadd_operand (op, mode)
5588 enum machine_mode mode ATTRIBUTE_UNUSED;
5590 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
5593 /* Return 1 if OP is valid as a base register in a reg + reg address. */
5596 basereg_operand (op, mode)
5598 enum machine_mode mode;
5600 /* cse will create some unscaled indexed addresses, however; it
5601 generally isn't a win on the PA, so avoid creating unscaled
5602 indexed addresses until after cse is finished. */
5603 if (!cse_not_expected)
5606 /* Once reload has started everything is considered valid. Reload should
5607 only create indexed addresses using the stack/frame pointer, and any
5608 others were checked for validity when created by the combine pass.
5610 Also allow any register when TARGET_NO_SPACE_REGS is in effect since
5611 we don't have to worry about the braindamaged implicit space register
5612 selection using the basereg only (rather than effective address)
5613 screwing us over. */
5614 if (TARGET_NO_SPACE_REGS || reload_in_progress || reload_completed)
5615 return (GET_CODE (op) == REG);
5617 /* Stack is always OK for indexing. */
5618 if (op == stack_pointer_rtx)
5621 /* While it's always safe to index off the frame pointer, it's not
5622 always profitable, particularly when the frame pointer is being
5624 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
5627 /* The only other valid OPs are pseudo registers with
5628 REGNO_POINTER_FLAG set. */
5629 if (GET_CODE (op) != REG
5630 || REGNO (op) < FIRST_PSEUDO_REGISTER
5631 || ! register_operand (op, mode))
5634 return REGNO_POINTER_FLAG (REGNO (op));
5637 /* Return 1 if this operand is anything other than a hard register. */
5640 non_hard_reg_operand (op, mode)
5642 enum machine_mode mode ATTRIBUTE_UNUSED;
5644 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
5647 /* Return 1 if INSN branches forward. Should be using insn_addresses
5648 to avoid walking through all the insns... */
5650 forward_branch_p (insn)
5653 rtx label = JUMP_LABEL (insn);
5660 insn = NEXT_INSN (insn);
5663 return (insn == label);
5666 /* Return 1 if OP is an equality comparison, else return 0. */
5668 eq_neq_comparison_operator (op, mode)
5670 enum machine_mode mode ATTRIBUTE_UNUSED;
5672 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
5675 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
5677 movb_comparison_operator (op, mode)
5679 enum machine_mode mode ATTRIBUTE_UNUSED;
5681 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
5682 || GET_CODE (op) == LT || GET_CODE (op) == GE);
5685 /* Return 1 if INSN is in the delay slot of a call instruction. */
5687 jump_in_call_delay (insn)
5691 if (GET_CODE (insn) != JUMP_INSN)
5694 if (PREV_INSN (insn)
5695 && PREV_INSN (PREV_INSN (insn))
5696 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
5698 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
5700 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
5701 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
5708 /* Output an unconditional move and branch insn. */
5711 output_parallel_movb (operands, length)
5715 /* These are the cases in which we win. */
5717 return "mov%I1b,tr %1,%0,%2";
5719 /* None of these cases wins, but they don't lose either. */
5720 if (dbr_sequence_length () == 0)
5722 /* Nothing in the delay slot, fake it by putting the combined
5723 insn (the copy or add) in the delay slot of a bl. */
5724 if (GET_CODE (operands[1]) == CONST_INT)
5725 return "b %2\n\tldi %1,%0";
5727 return "b %2\n\tcopy %1,%0";
5731 /* Something in the delay slot, but we've got a long branch. */
5732 if (GET_CODE (operands[1]) == CONST_INT)
5733 return "ldi %1,%0\n\tb %2";
5735 return "copy %1,%0\n\tb %2";
5739 /* Output an unconditional add and branch insn. */
5742 output_parallel_addb (operands, length)
5746 /* To make life easy we want operand0 to be the shared input/output
5747 operand and operand1 to be the readonly operand. */
5748 if (operands[0] == operands[1])
5749 operands[1] = operands[2];
5751 /* These are the cases in which we win. */
5753 return "add%I1b,tr %1,%0,%3";
5755 /* None of these cases win, but they don't lose either. */
5756 if (dbr_sequence_length () == 0)
5758 /* Nothing in the delay slot, fake it by putting the combined
5759 insn (the copy or add) in the delay slot of a bl. */
5760 return "b %3\n\tadd%I1 %1,%0,%0";
5764 /* Something in the delay slot, but we've got a long branch. */
5765 return "add%I1 %1,%0,%0\n\tb %3";
5769 /* Return nonzero if INSN (a jump insn) immediately follows a call to
5770 a named function. This is used to discourage creating parallel movb/addb
5771 insns since a jump which immediately follows a call can execute in the
5772 delay slot of the call.
5774 It is also used to avoid filling the delay slot of a jump which
5775 immediately follows a call since the jump can usually be eliminated
5776 completely by modifying RP in the delay slot of the call. */
5779 following_call (insn)
5782 /* Find the previous real insn, skipping NOTEs. */
5783 insn = PREV_INSN (insn);
5784 while (insn && GET_CODE (insn) == NOTE)
5785 insn = PREV_INSN (insn);
5787 /* Check for CALL_INSNs and millicode calls. */
5789 && ((GET_CODE (insn) == CALL_INSN
5790 && get_attr_type (insn) != TYPE_DYNCALL)
5791 || (GET_CODE (insn) == INSN
5792 && GET_CODE (PATTERN (insn)) != SEQUENCE
5793 && GET_CODE (PATTERN (insn)) != USE
5794 && GET_CODE (PATTERN (insn)) != CLOBBER
5795 && get_attr_type (insn) == TYPE_MILLI)))
5801 /* Restore any INSN_CODEs for insns with unscaled indexed addresses since
5802 the INSN_CODE might be clobberd by rerecognition triggered by reorg. */
5805 restore_unscaled_index_insn_codes (insns)
5810 for (insn = insns; insn; insn = NEXT_INSN (insn))
5812 if (INSN_UID (insn) < max_unscaled_index_insn_codes_uid
5813 && unscaled_index_insn_codes[INSN_UID (insn)] != -1)
5814 INSN_CODE (insn) = unscaled_index_insn_codes[INSN_UID (insn)];
5818 /* Severe braindamage:
5820 On the PA, address computations within MEM expressions are not
5821 commutative because of the implicit space register selection
5822 from the base register (instead of the entire effective address).
5824 Because of this mis-feature we have to know which register in a reg+reg
5825 address is the base and which is the index.
5827 Before reload, the base can be identified by REGNO_POINTER_FLAG. We use
5828 this to force base + index addresses to match a different insn than
5829 index + base addresses.
5831 We assume that no pass during or after reload creates new unscaled indexed
5832 addresses, so any unscaled indexed address we find after reload must have
5833 at one time been recognized a base + index or index + base and we accept
5834 any register as a base register.
5836 This scheme assumes that no pass during/after reload will rerecognize an
5837 insn with an unscaled indexed address. This failed due to a reorg call
5838 to rerecognize certain insns.
5840 So, we record if an insn uses an unscaled indexed address and which
5841 register is the base (via recording of the INSN_CODE for such insns).
5843 Just before we output code for the function, we make sure all the insns
5844 using unscaled indexed addresses have the same INSN_CODE as they did
5845 immediately before delay slot scheduling.
5847 This is extremely gross. Long term, I'd like to be able to look at
5848 REG_POINTER_FLAG to handle these kinds of problems. */
5851 record_unscaled_index_insn_codes (insns)
5856 max_unscaled_index_insn_codes_uid = get_max_uid ();
5857 unscaled_index_insn_codes
5858 = (int *)xmalloc (max_unscaled_index_insn_codes_uid * sizeof (int));
5859 memset (unscaled_index_insn_codes, -1,
5860 max_unscaled_index_insn_codes_uid * sizeof (int));
5862 for (insn = insns; insn; insn = NEXT_INSN (insn))
5864 rtx set = single_set (insn);
5867 /* Ignore anything that isn't a normal SET. */
5868 if (set == NULL_RTX)
5871 /* No insns can have more than one MEM. */
5872 if (GET_CODE (SET_SRC (set)) == MEM)
5873 mem = SET_SRC (set);
5875 if (GET_CODE (SET_DEST (set)) == MEM)
5876 mem = SET_DEST (set);
5878 /* If neither operand is a mem, then there's nothing to do. */
5879 if (mem == NULL_RTX)
5882 if (GET_CODE (XEXP (mem, 0)) != PLUS)
5885 /* If both are REGs (or SUBREGs), then record the insn code for
5887 if (REG_P (XEXP (XEXP (mem, 0), 0)) && REG_P (XEXP (XEXP (mem, 0), 1)))
5888 unscaled_index_insn_codes[INSN_UID (insn)] = INSN_CODE (insn);
5892 /* We use this hook to perform a PA specific optimization which is difficult
5893 to do in earlier passes.
5895 We want the delay slots of branches within jump tables to be filled.
5896 None of the compiler passes at the moment even has the notion that a
5897 PA jump table doesn't contain addresses, but instead contains actual
5900 Because we actually jump into the table, the addresses of each entry
5901 must stay constant in relation to the beginning of the table (which
5902 itself must stay constant relative to the instruction to jump into
5903 it). I don't believe we can guarantee earlier passes of the compiler
5904 will adhere to those rules.
5906 So, late in the compilation process we find all the jump tables, and
5907 expand them into real code -- eg each entry in the jump table vector
5908 will get an appropriate label followed by a jump to the final target.
5910 Reorg and the final jump pass can then optimize these branches and
5911 fill their delay slots. We end up with smaller, more efficient code.
5913 The jump instructions within the table are special; we must be able
5914 to identify them during assembly output (if the jumps don't get filled
5915 we need to emit a nop rather than nullifying the delay slot)). We
5916 identify jumps in switch tables by marking the SET with DImode.
5918 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
5919 insns. This serves two purposes, first it prevents jump.c from
5920 noticing that the last N entries in the table jump to the instruction
5921 immediately after the table and deleting the jumps. Second, those
5922 insns mark where we should emit .begin_brtab and .end_brtab directives
5923 when using GAS (allows for better link time optimizations). */
5931 /* Keep track of which insns have unscaled indexed addresses, and which
5932 register is the base address in such insns. */
5933 record_unscaled_index_insn_codes (insns);
5935 remove_useless_addtr_insns (insns, 1);
5937 if (pa_cpu < PROCESSOR_8000)
5938 pa_combine_instructions (get_insns ());
5941 /* This is fairly cheap, so always run it if optimizing. */
5942 if (optimize > 0 && !TARGET_BIG_SWITCH)
5944 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
5945 insns = get_insns ();
5946 for (insn = insns; insn; insn = NEXT_INSN (insn))
5948 rtx pattern, tmp, location;
5949 unsigned int length, i;
5951 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
5952 if (GET_CODE (insn) != JUMP_INSN
5953 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
5954 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
5957 /* Emit marker for the beginning of the branch table. */
5958 emit_insn_before (gen_begin_brtab (), insn);
5960 pattern = PATTERN (insn);
5961 location = PREV_INSN (insn);
5962 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
5964 for (i = 0; i < length; i++)
5966 /* Emit a label before each jump to keep jump.c from
5967 removing this code. */
5968 tmp = gen_label_rtx ();
5969 LABEL_NUSES (tmp) = 1;
5970 emit_label_after (tmp, location);
5971 location = NEXT_INSN (location);
5973 if (GET_CODE (pattern) == ADDR_VEC)
5975 /* Emit the jump itself. */
5976 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
5977 tmp = emit_jump_insn_after (tmp, location);
5978 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
5979 /* It is easy to rely on the branch table markers
5980 during assembly output to trigger the correct code
5981 for a switch table jump with an unfilled delay slot,
5983 However, that requires state and assumes that we look
5986 We can't make such assumptions when computing the length
5987 of instructions. Ugh. We could walk the insn chain to
5988 determine if this instruction is in a branch table, but
5989 that can get rather expensive, particularly during the
5990 branch shortening phase of the compiler.
5992 So instead we mark this jump as being special. This is
5993 far from ideal and knows that no code after this will
5994 muck around with the mode of the JUMP_INSN itself. */
5995 PUT_MODE (tmp, SImode);
5996 LABEL_NUSES (JUMP_LABEL (tmp))++;
5997 location = NEXT_INSN (location);
6001 /* Emit the jump itself. */
6002 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
6003 tmp = emit_jump_insn_after (tmp, location);
6004 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
6005 /* It is easy to rely on the branch table markers
6006 during assembly output to trigger the correct code
6007 for a switch table jump with an unfilled delay slot,
6009 However, that requires state and assumes that we look
6012 We can't make such assumptions when computing the length
6013 of instructions. Ugh. We could walk the insn chain to
6014 determine if this instruction is in a branch table, but
6015 that can get rather expensive, particularly during the
6016 branch shortening phase of the compiler.
6018 So instead we mark this jump as being special. This is
6019 far from ideal and knows that no code after this will
6020 muck around with the mode of the JUMP_INSN itself. */
6021 PUT_MODE (tmp, SImode);
6022 LABEL_NUSES (JUMP_LABEL (tmp))++;
6023 location = NEXT_INSN (location);
6026 /* Emit a BARRIER after the jump. */
6027 emit_barrier_after (location);
6028 location = NEXT_INSN (location);
6031 /* Emit marker for the end of the branch table. */
6032 emit_insn_before (gen_end_brtab (), location);
6033 location = NEXT_INSN (location);
6034 emit_barrier_after (location);
6036 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6042 /* Sill need an end_brtab insn. */
6043 insns = get_insns ();
6044 for (insn = insns; insn; insn = NEXT_INSN (insn))
6046 /* Find an ADDR_VEC insn. */
6047 if (GET_CODE (insn) != JUMP_INSN
6048 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6049 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6052 /* Now generate markers for the beginning and end of the
6054 emit_insn_before (gen_begin_brtab (), insn);
6055 emit_insn_after (gen_end_brtab (), insn);
6060 /* The PA has a number of odd instructions which can perform multiple
6061 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6062 it may be profitable to combine two instructions into one instruction
6063 with two outputs. It's not profitable PA2.0 machines because the
6064 two outputs would take two slots in the reorder buffers.
6066 This routine finds instructions which can be combined and combines
6067 them. We only support some of the potential combinations, and we
6068 only try common ways to find suitable instructions.
6070 * addb can add two registers or a register and a small integer
6071 and jump to a nearby (+-8k) location. Normally the jump to the
6072 nearby location is conditional on the result of the add, but by
6073 using the "true" condition we can make the jump unconditional.
6074 Thus addb can perform two independent operations in one insn.
6076 * movb is similar to addb in that it can perform a reg->reg
6077 or small immediate->reg copy and jump to a nearby (+-8k location).
6079 * fmpyadd and fmpysub can perform a FP multiply and either an
6080 FP add or FP sub if the operands of the multiply and add/sub are
6081 independent (there are other minor restrictions). Note both
6082 the fmpy and fadd/fsub can in theory move to better spots according
6083 to data dependencies, but for now we require the fmpy stay at a
6086 * Many of the memory operations can perform pre & post updates
6087 of index registers. GCC's pre/post increment/decrement addressing
6088 is far too simple to take advantage of all the possibilities. This
6089 pass may not be suitable since those insns may not be independent.
6091 * comclr can compare two ints or an int and a register, nullify
6092 the following instruction and zero some other register. This
6093 is more difficult to use as it's harder to find an insn which
6094 will generate a comclr than finding something like an unconditional
6095 branch. (conditional moves & long branches create comclr insns).
6097 * Most arithmetic operations can conditionally skip the next
6098 instruction. They can be viewed as "perform this operation
6099 and conditionally jump to this nearby location" (where nearby
6100 is an insns away). These are difficult to use due to the
6101 branch length restrictions. */
6104 pa_combine_instructions (insns)
6105 rtx insns ATTRIBUTE_UNUSED;
6109 /* This can get expensive since the basic algorithm is on the
6110 order of O(n^2) (or worse). Only do it for -O2 or higher
6111 levels of optimization. */
6115 /* Walk down the list of insns looking for "anchor" insns which
6116 may be combined with "floating" insns. As the name implies,
6117 "anchor" instructions don't move, while "floating" insns may
6119 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
6120 new = make_insn_raw (new);
6122 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
6124 enum attr_pa_combine_type anchor_attr;
6125 enum attr_pa_combine_type floater_attr;
6127 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6128 Also ignore any special USE insns. */
6129 if ((GET_CODE (anchor) != INSN
6130 && GET_CODE (anchor) != JUMP_INSN
6131 && GET_CODE (anchor) != CALL_INSN)
6132 || GET_CODE (PATTERN (anchor)) == USE
6133 || GET_CODE (PATTERN (anchor)) == CLOBBER
6134 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
6135 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
6138 anchor_attr = get_attr_pa_combine_type (anchor);
6139 /* See if anchor is an insn suitable for combination. */
6140 if (anchor_attr == PA_COMBINE_TYPE_FMPY
6141 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
6142 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6143 && ! forward_branch_p (anchor)))
6147 for (floater = PREV_INSN (anchor);
6149 floater = PREV_INSN (floater))
6151 if (GET_CODE (floater) == NOTE
6152 || (GET_CODE (floater) == INSN
6153 && (GET_CODE (PATTERN (floater)) == USE
6154 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6157 /* Anything except a regular INSN will stop our search. */
6158 if (GET_CODE (floater) != INSN
6159 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6160 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6166 /* See if FLOATER is suitable for combination with the
6168 floater_attr = get_attr_pa_combine_type (floater);
6169 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6170 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6171 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6172 && floater_attr == PA_COMBINE_TYPE_FMPY))
6174 /* If ANCHOR and FLOATER can be combined, then we're
6175 done with this pass. */
6176 if (pa_can_combine_p (new, anchor, floater, 0,
6177 SET_DEST (PATTERN (floater)),
6178 XEXP (SET_SRC (PATTERN (floater)), 0),
6179 XEXP (SET_SRC (PATTERN (floater)), 1)))
6183 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6184 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
6186 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
6188 if (pa_can_combine_p (new, anchor, floater, 0,
6189 SET_DEST (PATTERN (floater)),
6190 XEXP (SET_SRC (PATTERN (floater)), 0),
6191 XEXP (SET_SRC (PATTERN (floater)), 1)))
6196 if (pa_can_combine_p (new, anchor, floater, 0,
6197 SET_DEST (PATTERN (floater)),
6198 SET_SRC (PATTERN (floater)),
6199 SET_SRC (PATTERN (floater))))
6205 /* If we didn't find anything on the backwards scan try forwards. */
6207 && (anchor_attr == PA_COMBINE_TYPE_FMPY
6208 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
6210 for (floater = anchor; floater; floater = NEXT_INSN (floater))
6212 if (GET_CODE (floater) == NOTE
6213 || (GET_CODE (floater) == INSN
6214 && (GET_CODE (PATTERN (floater)) == USE
6215 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6219 /* Anything except a regular INSN will stop our search. */
6220 if (GET_CODE (floater) != INSN
6221 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6222 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6228 /* See if FLOATER is suitable for combination with the
6230 floater_attr = get_attr_pa_combine_type (floater);
6231 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6232 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6233 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6234 && floater_attr == PA_COMBINE_TYPE_FMPY))
6236 /* If ANCHOR and FLOATER can be combined, then we're
6237 done with this pass. */
6238 if (pa_can_combine_p (new, anchor, floater, 1,
6239 SET_DEST (PATTERN (floater)),
6240 XEXP (SET_SRC (PATTERN(floater)),0),
6241 XEXP(SET_SRC(PATTERN(floater)),1)))
6247 /* FLOATER will be nonzero if we found a suitable floating
6248 insn for combination with ANCHOR. */
6250 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6251 || anchor_attr == PA_COMBINE_TYPE_FMPY))
6253 /* Emit the new instruction and delete the old anchor. */
6254 emit_insn_before (gen_rtx_PARALLEL (VOIDmode,
6257 PATTERN (floater))),
6259 PUT_CODE (anchor, NOTE);
6260 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6261 NOTE_SOURCE_FILE (anchor) = 0;
6263 /* Emit a special USE insn for FLOATER, then delete
6264 the floating insn. */
6265 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6266 delete_insn (floater);
6271 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
6274 /* Emit the new_jump instruction and delete the old anchor. */
6275 temp = emit_jump_insn_before (gen_rtx_PARALLEL (VOIDmode,
6276 gen_rtvec (2, PATTERN (anchor),
6277 PATTERN (floater))),
6279 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
6280 PUT_CODE (anchor, NOTE);
6281 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6282 NOTE_SOURCE_FILE (anchor) = 0;
6284 /* Emit a special USE insn for FLOATER, then delete
6285 the floating insn. */
6286 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6287 delete_insn (floater);
6295 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
6296 rtx new, anchor, floater;
6298 rtx dest, src1, src2;
6300 int insn_code_number;
6303 /* Create a PARALLEL with the patterns of ANCHOR and
6304 FLOATER, try to recognize it, then test constraints
6305 for the resulting pattern.
6307 If the pattern doesn't match or the constraints
6308 aren't met keep searching for a suitable floater
6310 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
6311 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
6312 INSN_CODE (new) = -1;
6313 insn_code_number = recog_memoized (new);
6314 if (insn_code_number < 0
6315 || !constrain_operands (insn_code_number, 1))
6329 /* There's up to three operands to consider. One
6330 output and two inputs.
6332 The output must not be used between FLOATER & ANCHOR
6333 exclusive. The inputs must not be set between
6334 FLOATER and ANCHOR exclusive. */
6336 if (reg_used_between_p (dest, start, end))
6339 if (reg_set_between_p (src1, start, end))
6342 if (reg_set_between_p (src2, start, end))
6345 /* If we get here, then everything is good. */
6349 /* Return nonzero if sets and references for INSN are delayed.
6351 Millicode insns are actually function calls with some special
6352 constraints on arguments and register usage.
6354 Millicode calls always expect their arguments in the integer argument
6355 registers, and always return their result in %r29 (ret1). They
6356 are expected to clobber their arguments, %r1, %r29, and %r31 and
6359 By considering this effects delayed reorg reorg can put insns
6360 which set the argument registers into the delay slot of the millicode
6361 call -- thus they act more like traditional CALL_INSNs.
6363 get_attr_type will try to recognize the given insn, so make sure to
6364 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
6367 insn_sets_and_refs_are_delayed (insn)
6370 return ((GET_CODE (insn) == INSN
6371 && GET_CODE (PATTERN (insn)) != SEQUENCE
6372 && GET_CODE (PATTERN (insn)) != USE
6373 && GET_CODE (PATTERN (insn)) != CLOBBER
6374 && get_attr_type (insn) == TYPE_MILLI));