1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 static void restore_unscaled_index_insn_codes PROTO((rtx));
43 static void record_unscaled_index_insn_codes PROTO((rtx));
44 static void pa_combine_instructions PROTO((rtx));
45 static int pa_can_combine_p PROTO((rtx, rtx, rtx, int, rtx, rtx, rtx));
46 static int forward_branch_p PROTO((rtx));
47 static int shadd_constant_p PROTO((int));
49 /* Save the operands last given to a compare for use when we
50 generate a scc or bcc insn. */
52 rtx hppa_compare_op0, hppa_compare_op1;
53 enum cmp_type hppa_branch_type;
55 /* Which cpu we are scheduling for. */
56 enum processor_type pa_cpu;
58 /* String to hold which cpu we are scheduling for. */
61 /* Set by the FUNCTION_PROFILER macro. */
62 int hp_profile_labelno;
64 /* Counts for the number of callee-saved general and floating point
65 registers which were saved by the current function's prologue. */
66 static int gr_saved, fr_saved;
68 /* Whether or not the current function uses an out-of-line prologue
70 static int out_of_line_prologue_epilogue;
72 static rtx find_addr_reg ();
74 /* Keep track of the number of bytes we have output in the CODE subspaces
75 during this compilation so we'll know when to emit inline long-calls. */
77 unsigned int total_code_bytes;
79 /* Variables to handle plabels that we discover are necessary at assembly
80 output time. They are output after the current function. */
82 struct deferred_plabel
86 } *deferred_plabels = 0;
87 int n_deferred_plabels = 0;
89 /* Array indexed by INSN_UIDs holding the INSN_CODE of an insn which
90 uses an unscaled indexed address before delay slot scheduling. */
91 static int *unscaled_index_insn_codes;
93 /* Upper bound for the array. */
94 static int max_unscaled_index_insn_codes_uid;
99 /* Default to 7100LC scheduling. */
100 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
102 pa_cpu_string = "7100";
103 pa_cpu = PROCESSOR_7100;
105 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
107 pa_cpu_string = "700";
108 pa_cpu = PROCESSOR_700;
110 else if (pa_cpu_string == NULL
111 || ! strcmp (pa_cpu_string, "7100LC"))
113 pa_cpu_string = "7100LC";
114 pa_cpu = PROCESSOR_7100LC;
116 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
118 pa_cpu_string = "7200";
119 pa_cpu = PROCESSOR_7200;
121 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "8000"))
123 pa_cpu_string = "8000";
124 pa_cpu = PROCESSOR_8000;
128 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string);
131 if (flag_pic && TARGET_PORTABLE_RUNTIME)
133 warning ("PIC code generation is not supported in the portable runtime model\n");
136 if (flag_pic && (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS))
138 warning ("PIC code generation is not compatible with fast indirect calls\n");
141 if (flag_pic && profile_flag)
143 warning ("PIC code generation is not compatible with profiling\n");
146 if (TARGET_SPACE && (flag_pic || profile_flag))
148 warning ("Out of line entry/exit sequences are not compatible\n");
149 warning ("with PIC or profiling\n");
152 if (! TARGET_GAS && write_symbols != NO_DEBUG)
154 warning ("-g is only supported when using GAS on this processor,");
155 warning ("-g option disabled.");
156 write_symbols = NO_DEBUG;
161 /* Return non-zero only if OP is a register of mode MODE,
164 reg_or_0_operand (op, mode)
166 enum machine_mode mode;
168 return (op == CONST0_RTX (mode) || register_operand (op, mode));
171 /* Return non-zero if OP is suitable for use in a call to a named
174 (???) For 2.5 try to eliminate either call_operand_address or
175 function_label_operand, they perform very similar functions. */
177 call_operand_address (op, mode)
179 enum machine_mode mode ATTRIBUTE_UNUSED;
181 return (CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
184 /* Return 1 if X contains a symbolic expression. We know these
185 expressions will have one of a few well defined forms, so
186 we need only check those forms. */
188 symbolic_expression_p (x)
192 /* Strip off any HIGH. */
193 if (GET_CODE (x) == HIGH)
196 return (symbolic_operand (x, VOIDmode));
200 symbolic_operand (op, mode)
202 enum machine_mode mode ATTRIBUTE_UNUSED;
204 switch (GET_CODE (op))
211 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
212 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
213 && GET_CODE (XEXP (op, 1)) == CONST_INT);
219 /* Return truth value of statement that OP is a symbolic memory
220 operand of mode MODE. */
223 symbolic_memory_operand (op, mode)
225 enum machine_mode mode ATTRIBUTE_UNUSED;
227 if (GET_CODE (op) == SUBREG)
228 op = SUBREG_REG (op);
229 if (GET_CODE (op) != MEM)
232 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
233 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
236 /* Return 1 if the operand is either a register or a memory operand that is
240 reg_or_nonsymb_mem_operand (op, mode)
242 enum machine_mode mode;
244 if (register_operand (op, mode))
247 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
253 /* Return 1 if the operand is either a register, zero, or a memory operand
254 that is not symbolic. */
257 reg_or_0_or_nonsymb_mem_operand (op, mode)
259 enum machine_mode mode;
261 if (register_operand (op, mode))
264 if (op == CONST0_RTX (mode))
267 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
273 /* Accept any constant that can be moved in one instructions into a
276 cint_ok_for_move (intval)
277 HOST_WIDE_INT intval;
279 /* OK if ldo, ldil, or zdepi, can be used. */
280 return (VAL_14_BITS_P (intval) || (intval & 0x7ff) == 0
281 || zdepi_cint_p (intval));
284 /* Accept anything that can be moved in one instruction into a general
287 move_operand (op, mode)
289 enum machine_mode mode;
291 if (register_operand (op, mode))
294 if (GET_CODE (op) == CONSTANT_P_RTX)
297 if (GET_CODE (op) == CONST_INT)
298 return cint_ok_for_move (INTVAL (op));
300 if (GET_CODE (op) == SUBREG)
301 op = SUBREG_REG (op);
302 if (GET_CODE (op) != MEM)
306 if (GET_CODE (op) == LO_SUM)
307 return (register_operand (XEXP (op, 0), Pmode)
308 && CONSTANT_P (XEXP (op, 1)));
310 /* Since move_operand is only used for source operands, we can always
311 allow scaled indexing! */
312 if (! TARGET_DISABLE_INDEXING
313 && GET_CODE (op) == PLUS
314 && ((GET_CODE (XEXP (op, 0)) == MULT
315 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
316 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
317 && INTVAL (XEXP (XEXP (op, 0), 1)) == GET_MODE_SIZE (mode)
318 && GET_CODE (XEXP (op, 1)) == REG)
319 || (GET_CODE (XEXP (op, 1)) == MULT
320 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
321 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
322 && INTVAL (XEXP (XEXP (op, 1), 1)) == GET_MODE_SIZE (mode)
323 && GET_CODE (XEXP (op, 0)) == REG)))
326 return memory_address_p (mode, op);
329 /* Accept REG and any CONST_INT that can be moved in one instruction into a
332 reg_or_cint_move_operand (op, mode)
334 enum machine_mode mode;
336 if (register_operand (op, mode))
339 if (GET_CODE (op) == CONST_INT)
340 return cint_ok_for_move (INTVAL (op));
346 pic_label_operand (op, mode)
348 enum machine_mode mode ATTRIBUTE_UNUSED;
353 switch (GET_CODE (op))
359 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
360 && GET_CODE (XEXP (op, 1)) == CONST_INT);
367 fp_reg_operand (op, mode)
369 enum machine_mode mode ATTRIBUTE_UNUSED;
371 return reg_renumber && FP_REG_P (op);
376 /* Return truth value of whether OP can be used as an operand in a
377 three operand arithmetic insn that accepts registers of mode MODE
378 or 14-bit signed integers. */
380 arith_operand (op, mode)
382 enum machine_mode mode;
384 return (register_operand (op, mode)
385 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
388 /* Return truth value of whether OP can be used as an operand in a
389 three operand arithmetic insn that accepts registers of mode MODE
390 or 11-bit signed integers. */
392 arith11_operand (op, mode)
394 enum machine_mode mode;
396 return (register_operand (op, mode)
397 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
400 /* A constant integer suitable for use in a PRE_MODIFY memory
403 pre_cint_operand (op, mode)
405 enum machine_mode mode ATTRIBUTE_UNUSED;
407 return (GET_CODE (op) == CONST_INT
408 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
411 /* A constant integer suitable for use in a POST_MODIFY memory
414 post_cint_operand (op, mode)
416 enum machine_mode mode ATTRIBUTE_UNUSED;
418 return (GET_CODE (op) == CONST_INT
419 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
423 arith_double_operand (op, mode)
425 enum machine_mode mode;
427 return (register_operand (op, mode)
428 || (GET_CODE (op) == CONST_DOUBLE
429 && GET_MODE (op) == mode
430 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
431 && ((CONST_DOUBLE_HIGH (op) >= 0)
432 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
435 /* Return truth value of whether OP is a integer which fits the
436 range constraining immediate operands in three-address insns, or
437 is an integer register. */
440 ireg_or_int5_operand (op, mode)
442 enum machine_mode mode ATTRIBUTE_UNUSED;
444 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
445 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
448 /* Return truth value of whether OP is a integer which fits the
449 range constraining immediate operands in three-address insns. */
452 int5_operand (op, mode)
454 enum machine_mode mode ATTRIBUTE_UNUSED;
456 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
460 uint5_operand (op, mode)
462 enum machine_mode mode ATTRIBUTE_UNUSED;
464 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
468 int11_operand (op, mode)
470 enum machine_mode mode ATTRIBUTE_UNUSED;
472 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
476 uint32_operand (op, mode)
478 enum machine_mode mode ATTRIBUTE_UNUSED;
480 #if HOST_BITS_PER_WIDE_INT > 32
481 /* All allowed constants will fit a CONST_INT. */
482 return (GET_CODE (op) == CONST_INT
483 && (INTVAL (op) >= 0 && INTVAL (op) < 0x100000000L));
485 return (GET_CODE (op) == CONST_INT
486 || (GET_CODE (op) == CONST_DOUBLE
487 && CONST_DOUBLE_HIGH (op) == 0));
492 arith5_operand (op, mode)
494 enum machine_mode mode;
496 return register_operand (op, mode) || int5_operand (op, mode);
499 /* True iff zdepi can be used to generate this CONST_INT. */
502 unsigned HOST_WIDE_INT x;
504 unsigned HOST_WIDE_INT lsb_mask, t;
506 /* This might not be obvious, but it's at least fast.
507 This function is critical; we don't have the time loops would take. */
509 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
510 /* Return true iff t is a power of two. */
511 return ((t & (t - 1)) == 0);
514 /* True iff depi or extru can be used to compute (reg & mask).
515 Accept bit pattern like these:
521 unsigned HOST_WIDE_INT mask;
524 mask += mask & -mask;
525 return (mask & (mask - 1)) == 0;
528 /* True iff depi or extru can be used to compute (reg & OP). */
530 and_operand (op, mode)
532 enum machine_mode mode;
534 return (register_operand (op, mode)
535 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
538 /* True iff depi can be used to compute (reg | MASK). */
541 unsigned HOST_WIDE_INT mask;
543 mask += mask & -mask;
544 return (mask & (mask - 1)) == 0;
547 /* True iff depi can be used to compute (reg | OP). */
549 ior_operand (op, mode)
551 enum machine_mode mode ATTRIBUTE_UNUSED;
553 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
557 lhs_lshift_operand (op, mode)
559 enum machine_mode mode;
561 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
564 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
565 Such values can be the left hand side x in (x << r), using the zvdepi
568 lhs_lshift_cint_operand (op, mode)
570 enum machine_mode mode ATTRIBUTE_UNUSED;
572 unsigned HOST_WIDE_INT x;
573 if (GET_CODE (op) != CONST_INT)
575 x = INTVAL (op) >> 4;
576 return (x & (x + 1)) == 0;
580 arith32_operand (op, mode)
582 enum machine_mode mode;
584 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
588 pc_or_label_operand (op, mode)
590 enum machine_mode mode ATTRIBUTE_UNUSED;
592 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
595 /* Legitimize PIC addresses. If the address is already
596 position-independent, we return ORIG. Newly generated
597 position-independent addresses go to REG. If we need more
598 than one register, we lose. */
601 legitimize_pic_address (orig, mode, reg)
603 enum machine_mode mode ATTRIBUTE_UNUSED;
607 /* Labels need special handling. */
608 if (pic_label_operand (orig))
610 emit_insn (gen_pic_load_label (reg, orig));
611 current_function_uses_pic_offset_table = 1;
614 if (GET_CODE (orig) == SYMBOL_REF)
621 emit_insn (gen_pic2_highpart (reg, pic_offset_table_rtx, orig));
623 = gen_rtx_MEM (Pmode,
624 gen_rtx_LO_SUM (Pmode, reg,
625 gen_rtx_UNSPEC (SImode,
630 pic_ref = gen_rtx_MEM (Pmode,
632 pic_offset_table_rtx, orig));
633 current_function_uses_pic_offset_table = 1;
634 RTX_UNCHANGING_P (pic_ref) = 1;
635 emit_move_insn (reg, pic_ref);
638 else if (GET_CODE (orig) == CONST)
642 if (GET_CODE (XEXP (orig, 0)) == PLUS
643 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
649 if (GET_CODE (XEXP (orig, 0)) == PLUS)
651 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
652 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
653 base == reg ? 0 : reg);
656 if (GET_CODE (orig) == CONST_INT)
658 if (INT_14_BITS (orig))
659 return plus_constant_for_output (base, INTVAL (orig));
660 orig = force_reg (Pmode, orig);
662 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
663 /* Likewise, should we set special REG_NOTEs here? */
668 /* Try machine-dependent ways of modifying an illegitimate address
669 to be legitimate. If we find one, return the new, valid address.
670 This macro is used in only one place: `memory_address' in explow.c.
672 OLDX is the address as it was before break_out_memory_refs was called.
673 In some cases it is useful to look at this to decide what needs to be done.
675 MODE and WIN are passed so that this macro can use
676 GO_IF_LEGITIMATE_ADDRESS.
678 It is always safe for this macro to do nothing. It exists to recognize
679 opportunities to optimize the output.
681 For the PA, transform:
683 memory(X + <large int>)
687 if (<large int> & mask) >= 16
688 Y = (<large int> & ~mask) + mask + 1 Round up.
690 Y = (<large int> & ~mask) Round down.
692 memory (Z + (<large int> - Y));
694 This is for CSE to find several similar references, and only use one Z.
696 X can either be a SYMBOL_REF or REG, but because combine can not
697 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
698 D will not fit in 14 bits.
700 MODE_FLOAT references allow displacements which fit in 5 bits, so use
703 MODE_INT references allow displacements which fit in 14 bits, so use
706 This relies on the fact that most mode MODE_FLOAT references will use FP
707 registers and most mode MODE_INT references will use integer registers.
708 (In the rare case of an FP register used in an integer MODE, we depend
709 on secondary reloads to clean things up.)
712 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
713 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
714 addressing modes to be used).
716 Put X and Z into registers. Then put the entire expression into
720 hppa_legitimize_address (x, oldx, mode)
721 rtx x, oldx ATTRIBUTE_UNUSED;
722 enum machine_mode mode;
727 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
729 /* Strip off CONST. */
730 if (GET_CODE (x) == CONST)
733 /* Special case. Get the SYMBOL_REF into a register and use indexing.
734 That should always be safe. */
735 if (GET_CODE (x) == PLUS
736 && GET_CODE (XEXP (x, 0)) == REG
737 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
739 rtx reg = force_reg (SImode, XEXP (x, 1));
740 return force_reg (SImode, gen_rtx_PLUS (SImode, reg, XEXP (x, 0)));
743 /* Note we must reject symbols which represent function addresses
744 since the assembler/linker can't handle arithmetic on plabels. */
745 if (GET_CODE (x) == PLUS
746 && GET_CODE (XEXP (x, 1)) == CONST_INT
747 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
748 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
749 || GET_CODE (XEXP (x, 0)) == REG))
751 rtx int_part, ptr_reg;
753 int offset = INTVAL (XEXP (x, 1));
754 int mask = GET_MODE_CLASS (mode) == MODE_FLOAT ? 0x1f : 0x3fff;
756 /* Choose which way to round the offset. Round up if we
757 are >= halfway to the next boundary. */
758 if ((offset & mask) >= ((mask + 1) / 2))
759 newoffset = (offset & ~ mask) + mask + 1;
761 newoffset = (offset & ~ mask);
763 /* If the newoffset will not fit in 14 bits (ldo), then
764 handling this would take 4 or 5 instructions (2 to load
765 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
766 add the new offset and the SYMBOL_REF.) Combine can
767 not handle 4->2 or 5->2 combinations, so do not create
769 if (! VAL_14_BITS_P (newoffset)
770 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
773 = gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (Pmode,
775 GEN_INT (newoffset)));
778 gen_rtx_HIGH (Pmode, const_part));
781 gen_rtx_LO_SUM (Pmode, tmp_reg, const_part));
785 if (! VAL_14_BITS_P (newoffset))
786 int_part = force_reg (Pmode, GEN_INT (newoffset));
788 int_part = GEN_INT (newoffset);
790 ptr_reg = force_reg (Pmode,
792 force_reg (Pmode, XEXP (x, 0)),
795 return plus_constant (ptr_reg, offset - newoffset);
798 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
800 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
801 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
802 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
803 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
804 || GET_CODE (XEXP (x, 1)) == SUBREG)
805 && GET_CODE (XEXP (x, 1)) != CONST)
807 int val = INTVAL (XEXP (XEXP (x, 0), 1));
811 if (GET_CODE (reg1) != REG)
812 reg1 = force_reg (Pmode, force_operand (reg1, 0));
814 reg2 = XEXP (XEXP (x, 0), 0);
815 if (GET_CODE (reg2) != REG)
816 reg2 = force_reg (Pmode, force_operand (reg2, 0));
818 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
819 gen_rtx_MULT (Pmode, reg2,
824 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
826 Only do so for floating point modes since this is more speculative
827 and we lose if it's an integer store. */
828 if (GET_CODE (x) == PLUS
829 && GET_CODE (XEXP (x, 0)) == PLUS
830 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
831 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
832 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
833 && (mode == SFmode || mode == DFmode))
836 /* First, try and figure out what to use as a base register. */
837 rtx reg1, reg2, base, idx, orig_base;
839 reg1 = XEXP (XEXP (x, 0), 1);
844 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
845 then emit_move_sequence will turn on REGNO_POINTER_FLAG so we'll
846 know it's a base register below. */
847 if (GET_CODE (reg1) != REG)
848 reg1 = force_reg (Pmode, force_operand (reg1, 0));
850 if (GET_CODE (reg2) != REG)
851 reg2 = force_reg (Pmode, force_operand (reg2, 0));
853 /* Figure out what the base and index are. */
855 if (GET_CODE (reg1) == REG
856 && REGNO_POINTER_FLAG (REGNO (reg1)))
859 orig_base = XEXP (XEXP (x, 0), 1);
860 idx = gen_rtx_PLUS (Pmode,
862 XEXP (XEXP (XEXP (x, 0), 0), 0),
863 XEXP (XEXP (XEXP (x, 0), 0), 1)),
866 else if (GET_CODE (reg2) == REG
867 && REGNO_POINTER_FLAG (REGNO (reg2)))
870 orig_base = XEXP (x, 1);
877 /* If the index adds a large constant, try to scale the
878 constant so that it can be loaded with only one insn. */
879 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
880 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
881 / INTVAL (XEXP (XEXP (idx, 0), 1)))
882 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
884 /* Divide the CONST_INT by the scale factor, then add it to A. */
885 int val = INTVAL (XEXP (idx, 1));
887 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
888 reg1 = XEXP (XEXP (idx, 0), 0);
889 if (GET_CODE (reg1) != REG)
890 reg1 = force_reg (Pmode, force_operand (reg1, 0));
892 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
894 /* We can now generate a simple scaled indexed address. */
895 return force_reg (Pmode,
897 gen_rtx_MULT (Pmode, reg1,
898 XEXP (XEXP (idx, 0), 1)),
902 /* If B + C is still a valid base register, then add them. */
903 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
904 && INTVAL (XEXP (idx, 1)) <= 4096
905 && INTVAL (XEXP (idx, 1)) >= -4096)
907 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
910 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
912 reg2 = XEXP (XEXP (idx, 0), 0);
913 if (GET_CODE (reg2) != CONST_INT)
914 reg2 = force_reg (Pmode, force_operand (reg2, 0));
916 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
917 gen_rtx_MULT (Pmode, reg2,
922 /* Get the index into a register, then add the base + index and
923 return a register holding the result. */
925 /* First get A into a register. */
926 reg1 = XEXP (XEXP (idx, 0), 0);
927 if (GET_CODE (reg1) != REG)
928 reg1 = force_reg (Pmode, force_operand (reg1, 0));
930 /* And get B into a register. */
931 reg2 = XEXP (idx, 1);
932 if (GET_CODE (reg2) != REG)
933 reg2 = force_reg (Pmode, force_operand (reg2, 0));
935 reg1 = force_reg (Pmode,
937 gen_rtx_MULT (Pmode, reg1,
938 XEXP (XEXP (idx, 0), 1)),
941 /* Add the result to our base register and return. */
942 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
946 /* Uh-oh. We might have an address for x[n-100000]. This needs
947 special handling to avoid creating an indexed memory address
948 with x-100000 as the base.
950 If the constant part is small enough, then it's still safe because
951 there is a guard page at the beginning and end of the data segment.
953 Scaled references are common enough that we want to try and rearrange the
954 terms so that we can use indexing for these addresses too. Only
955 do the optimization for floatint point modes. */
957 if (GET_CODE (x) == PLUS
958 && symbolic_expression_p (XEXP (x, 1)))
960 /* Ugly. We modify things here so that the address offset specified
961 by the index expression is computed first, then added to x to form
962 the entire address. */
964 rtx regx1, regx2, regy1, regy2, y;
966 /* Strip off any CONST. */
968 if (GET_CODE (y) == CONST)
971 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
973 /* See if this looks like
974 (plus (mult (reg) (shadd_const))
975 (const (plus (symbol_ref) (const_int))))
977 Where const_int is small. In that case the const
978 expression is a valid pointer for indexing.
980 If const_int is big, but can be divided evenly by shadd_const
981 and added to (reg). This allows more scaled indexed addresses. */
982 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
983 && GET_CODE (XEXP (x, 0)) == MULT
984 && GET_CODE (XEXP (y, 1)) == CONST_INT
985 && INTVAL (XEXP (y, 1)) >= -4096
986 && INTVAL (XEXP (y, 1)) <= 4095
987 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
988 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
990 int val = INTVAL (XEXP (XEXP (x, 0), 1));
994 if (GET_CODE (reg1) != REG)
995 reg1 = force_reg (Pmode, force_operand (reg1, 0));
997 reg2 = XEXP (XEXP (x, 0), 0);
998 if (GET_CODE (reg2) != REG)
999 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1001 return force_reg (Pmode,
1002 gen_rtx_PLUS (Pmode,
1003 gen_rtx_MULT (Pmode, reg2,
1007 else if ((mode == DFmode || mode == SFmode)
1008 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1009 && GET_CODE (XEXP (x, 0)) == MULT
1010 && GET_CODE (XEXP (y, 1)) == CONST_INT
1011 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1012 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1013 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1016 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1017 / INTVAL (XEXP (XEXP (x, 0), 1))));
1018 regx2 = XEXP (XEXP (x, 0), 0);
1019 if (GET_CODE (regx2) != REG)
1020 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1021 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1023 return force_reg (Pmode,
1024 gen_rtx_PLUS (Pmode,
1025 gen_rtx_MULT (Pmode, regx2,
1028 force_reg (Pmode, XEXP (y, 0))));
1030 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1031 && INTVAL (XEXP (y, 1)) >= -4096
1032 && INTVAL (XEXP (y, 1)) <= 4095)
1034 /* This is safe because of the guard page at the
1035 beginning and end of the data space. Just
1036 return the original address. */
1041 /* Doesn't look like one we can optimize. */
1042 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1043 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1044 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1045 regx1 = force_reg (Pmode,
1046 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1048 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1056 /* For the HPPA, REG and REG+CONST is cost 0
1057 and addresses involving symbolic constants are cost 2.
1059 PIC addresses are very expensive.
1061 It is no coincidence that this has the same structure
1062 as GO_IF_LEGITIMATE_ADDRESS. */
1064 hppa_address_cost (X)
1067 if (GET_CODE (X) == PLUS)
1069 else if (GET_CODE (X) == LO_SUM)
1071 else if (GET_CODE (X) == HIGH)
1076 /* Emit insns to move operands[1] into operands[0].
1078 Return 1 if we have written out everything that needs to be done to
1079 do the move. Otherwise, return 0 and the caller will emit the move
1083 emit_move_sequence (operands, mode, scratch_reg)
1085 enum machine_mode mode;
1088 register rtx operand0 = operands[0];
1089 register rtx operand1 = operands[1];
1093 && reload_in_progress && GET_CODE (operand0) == REG
1094 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1095 operand0 = reg_equiv_mem[REGNO (operand0)];
1096 else if (scratch_reg
1097 && reload_in_progress && GET_CODE (operand0) == SUBREG
1098 && GET_CODE (SUBREG_REG (operand0)) == REG
1099 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1101 SUBREG_REG (operand0) = reg_equiv_mem[REGNO (SUBREG_REG (operand0))];
1102 operand0 = alter_subreg (operand0);
1106 && reload_in_progress && GET_CODE (operand1) == REG
1107 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1108 operand1 = reg_equiv_mem[REGNO (operand1)];
1109 else if (scratch_reg
1110 && reload_in_progress && GET_CODE (operand1) == SUBREG
1111 && GET_CODE (SUBREG_REG (operand1)) == REG
1112 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1114 SUBREG_REG (operand1) = reg_equiv_mem[REGNO (SUBREG_REG (operand1))];
1115 operand1 = alter_subreg (operand1);
1118 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1119 && ((tem = find_replacement (&XEXP (operand0, 0)))
1120 != XEXP (operand0, 0)))
1121 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1122 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1123 && ((tem = find_replacement (&XEXP (operand1, 0)))
1124 != XEXP (operand1, 0)))
1125 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1127 /* Handle secondary reloads for loads/stores of FP registers from
1128 REG+D addresses where D does not fit in 5 bits, including
1129 (subreg (mem (addr))) cases. */
1130 if (fp_reg_operand (operand0, mode)
1131 && ((GET_CODE (operand1) == MEM
1132 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1133 || ((GET_CODE (operand1) == SUBREG
1134 && GET_CODE (XEXP (operand1, 0)) == MEM
1135 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1138 if (GET_CODE (operand1) == SUBREG)
1139 operand1 = XEXP (operand1, 0);
1141 scratch_reg = gen_rtx_REG (SImode, REGNO (scratch_reg));
1143 /* D might not fit in 14 bits either; for such cases load D into
1145 if (!memory_address_p (SImode, XEXP (operand1, 0)))
1147 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1148 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1150 XEXP (XEXP (operand1, 0), 0),
1154 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1155 emit_insn (gen_rtx_SET (VOIDmode, operand0, gen_rtx_MEM (mode,
1159 else if (fp_reg_operand (operand1, mode)
1160 && ((GET_CODE (operand0) == MEM
1161 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1162 || ((GET_CODE (operand0) == SUBREG)
1163 && GET_CODE (XEXP (operand0, 0)) == MEM
1164 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1167 if (GET_CODE (operand0) == SUBREG)
1168 operand0 = XEXP (operand0, 0);
1170 scratch_reg = gen_rtx_REG (SImode, REGNO (scratch_reg));
1171 /* D might not fit in 14 bits either; for such cases load D into
1173 if (!memory_address_p (SImode, XEXP (operand0, 0)))
1175 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1176 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1179 XEXP (XEXP (operand0, 0),
1184 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1185 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1189 /* Handle secondary reloads for loads of FP registers from constant
1190 expressions by forcing the constant into memory.
1192 use scratch_reg to hold the address of the memory location.
1194 ??? The proper fix is to change PREFERRED_RELOAD_CLASS to return
1195 NO_REGS when presented with a const_int and an register class
1196 containing only FP registers. Doing so unfortunately creates
1197 more problems than it solves. Fix this for 2.5. */
1198 else if (fp_reg_operand (operand0, mode)
1199 && CONSTANT_P (operand1)
1204 /* Force the constant into memory and put the address of the
1205 memory location into scratch_reg. */
1206 xoperands[0] = scratch_reg;
1207 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1208 emit_move_sequence (xoperands, Pmode, 0);
1210 /* Now load the destination register. */
1211 emit_insn (gen_rtx_SET (mode, operand0, gen_rtx_MEM (mode, scratch_reg)));
1214 /* Handle secondary reloads for SAR. These occur when trying to load
1215 the SAR from memory a FP register, or with a constant. */
1216 else if (GET_CODE (operand0) == REG
1217 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1218 && (GET_CODE (operand1) == MEM
1219 || GET_CODE (operand1) == CONST_INT
1220 || (GET_CODE (operand1) == REG
1221 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1224 /* D might not fit in 14 bits either; for such cases load D into
1226 if (GET_CODE (operand1) == MEM
1227 && !memory_address_p (SImode, XEXP (operand1, 0)))
1229 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1230 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1233 XEXP (XEXP (operand1, 0),
1236 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand1),
1240 emit_move_insn (scratch_reg, operand1);
1241 emit_move_insn (operand0, scratch_reg);
1244 /* Handle most common case: storing into a register. */
1245 else if (register_operand (operand0, mode))
1247 if (register_operand (operand1, mode)
1248 || (GET_CODE (operand1) == CONST_INT && INT_14_BITS (operand1))
1249 || (operand1 == CONST0_RTX (mode))
1250 || (GET_CODE (operand1) == HIGH
1251 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1252 /* Only `general_operands' can come here, so MEM is ok. */
1253 || GET_CODE (operand1) == MEM)
1255 /* Run this case quickly. */
1256 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1260 else if (GET_CODE (operand0) == MEM)
1262 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1263 && !(reload_in_progress || reload_completed))
1265 rtx temp = gen_reg_rtx (DFmode);
1267 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1268 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1271 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1273 /* Run this case quickly. */
1274 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1277 if (! (reload_in_progress || reload_completed))
1279 operands[0] = validize_mem (operand0);
1280 operands[1] = operand1 = force_reg (mode, operand1);
1284 /* Simplify the source if we need to.
1285 Note we do have to handle function labels here, even though we do
1286 not consider them legitimate constants. Loop optimizations can
1287 call the emit_move_xxx with one as a source. */
1288 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1289 || function_label_operand (operand1, mode)
1290 || (GET_CODE (operand1) == HIGH
1291 && symbolic_operand (XEXP (operand1, 0), mode)))
1295 if (GET_CODE (operand1) == HIGH)
1298 operand1 = XEXP (operand1, 0);
1300 if (symbolic_operand (operand1, mode))
1302 /* Argh. The assembler and linker can't handle arithmetic
1305 So we force the plabel into memory, load operand0 from
1306 the memory location, then add in the constant part. */
1307 if ((GET_CODE (operand1) == CONST
1308 && GET_CODE (XEXP (operand1, 0)) == PLUS
1309 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1310 || function_label_operand (operand1, mode))
1312 rtx temp, const_part;
1314 /* Figure out what (if any) scratch register to use. */
1315 if (reload_in_progress || reload_completed)
1316 scratch_reg = scratch_reg ? scratch_reg : operand0;
1318 scratch_reg = gen_reg_rtx (Pmode);
1320 if (GET_CODE (operand1) == CONST)
1322 /* Save away the constant part of the expression. */
1323 const_part = XEXP (XEXP (operand1, 0), 1);
1324 if (GET_CODE (const_part) != CONST_INT)
1327 /* Force the function label into memory. */
1328 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1332 /* No constant part. */
1333 const_part = NULL_RTX;
1335 /* Force the function label into memory. */
1336 temp = force_const_mem (mode, operand1);
1340 /* Get the address of the memory location. PIC-ify it if
1342 temp = XEXP (temp, 0);
1344 temp = legitimize_pic_address (temp, mode, scratch_reg);
1346 /* Put the address of the memory location into our destination
1349 emit_move_sequence (operands, mode, scratch_reg);
1351 /* Now load from the memory location into our destination
1353 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1354 emit_move_sequence (operands, mode, scratch_reg);
1356 /* And add back in the constant part. */
1357 if (const_part != NULL_RTX)
1358 expand_inc (operand0, const_part);
1367 if (reload_in_progress || reload_completed)
1368 temp = scratch_reg ? scratch_reg : operand0;
1370 temp = gen_reg_rtx (Pmode);
1372 /* (const (plus (symbol) (const_int))) must be forced to
1373 memory during/after reload if the const_int will not fit
1375 if (GET_CODE (operand1) == CONST
1376 && GET_CODE (XEXP (operand1, 0)) == PLUS
1377 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1378 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1379 && (reload_completed || reload_in_progress)
1382 operands[1] = force_const_mem (mode, operand1);
1383 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1385 emit_move_sequence (operands, mode, temp);
1389 operands[1] = legitimize_pic_address (operand1, mode, temp);
1390 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1393 /* On the HPPA, references to data space are supposed to use dp,
1394 register 27, but showing it in the RTL inhibits various cse
1395 and loop optimizations. */
1400 if (reload_in_progress || reload_completed)
1401 temp = scratch_reg ? scratch_reg : operand0;
1403 temp = gen_reg_rtx (mode);
1405 /* Loading a SYMBOL_REF into a register makes that register
1406 safe to be used as the base in an indexed address.
1408 Don't mark hard registers though. That loses. */
1409 if (GET_CODE (operand0) == REG
1410 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1411 REGNO_POINTER_FLAG (REGNO (operand0)) = 1;
1412 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1413 REGNO_POINTER_FLAG (REGNO (temp)) = 1;
1415 set = gen_rtx_SET (mode, operand0, temp);
1417 set = gen_rtx_SET (VOIDmode, operand0,
1418 gen_rtx_LO_SUM (mode, temp, operand1));
1420 emit_insn (gen_rtx_SET (VOIDmode,
1422 gen_rtx_HIGH (mode, operand1)));
1428 else if (GET_CODE (operand1) != CONST_INT
1429 || ! cint_ok_for_move (INTVAL (operand1)))
1433 if (reload_in_progress || reload_completed)
1436 temp = gen_reg_rtx (mode);
1438 emit_insn (gen_rtx_SET (VOIDmode, temp,
1439 gen_rtx_HIGH (mode, operand1)));
1440 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1443 /* Now have insn-emit do whatever it normally does. */
1447 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1448 it will need a link/runtime reloc). */
1456 switch (TREE_CODE (exp))
1463 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1464 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1469 case NON_LVALUE_EXPR:
1470 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1476 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1477 if (TREE_VALUE (link) != 0)
1478 reloc |= reloc_needed (TREE_VALUE (link));
1491 /* Does operand (which is a symbolic_operand) live in text space? If
1492 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1495 read_only_operand (operand)
1498 if (GET_CODE (operand) == CONST)
1499 operand = XEXP (XEXP (operand, 0), 0);
1502 if (GET_CODE (operand) == SYMBOL_REF)
1503 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1507 if (GET_CODE (operand) == SYMBOL_REF)
1508 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1514 /* Return the best assembler insn template
1515 for moving operands[1] into operands[0] as a fullword. */
1517 singlemove_string (operands)
1520 HOST_WIDE_INT intval;
1522 if (GET_CODE (operands[0]) == MEM)
1523 return "stw %r1,%0";
1524 if (GET_CODE (operands[1]) == MEM)
1526 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1531 if (GET_MODE (operands[1]) != SFmode)
1534 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1536 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1537 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1539 operands[1] = GEN_INT (i);
1540 /* Fall through to CONST_INT case. */
1542 if (GET_CODE (operands[1]) == CONST_INT)
1544 intval = INTVAL (operands[1]);
1546 if (VAL_14_BITS_P (intval))
1548 else if ((intval & 0x7ff) == 0)
1549 return "ldil L'%1,%0";
1550 else if (zdepi_cint_p (intval))
1551 return "zdepi %Z1,%0";
1553 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1555 return "copy %1,%0";
1559 /* Compute position (in OP[1]) and width (in OP[2])
1560 useful for copying IMM to a register using the zdepi
1561 instructions. Store the immediate value to insert in OP[0]. */
1563 compute_zdepi_operands (imm, op)
1564 unsigned HOST_WIDE_INT imm;
1569 /* Find the least significant set bit in IMM. */
1570 for (lsb = 0; lsb < 32; lsb++)
1577 /* Choose variants based on *sign* of the 5-bit field. */
1578 if ((imm & 0x10) == 0)
1579 len = (lsb <= 28) ? 4 : 32 - lsb;
1582 /* Find the width of the bitstring in IMM. */
1583 for (len = 5; len < 32; len++)
1585 if ((imm & (1 << len)) == 0)
1589 /* Sign extend IMM as a 5-bit value. */
1590 imm = (imm & 0xf) - 0x10;
1598 /* Output assembler code to perform a doubleword move insn
1599 with operands OPERANDS. */
1602 output_move_double (operands)
1605 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1607 rtx addreg0 = 0, addreg1 = 0;
1609 /* First classify both operands. */
1611 if (REG_P (operands[0]))
1613 else if (offsettable_memref_p (operands[0]))
1615 else if (GET_CODE (operands[0]) == MEM)
1620 if (REG_P (operands[1]))
1622 else if (CONSTANT_P (operands[1]))
1624 else if (offsettable_memref_p (operands[1]))
1626 else if (GET_CODE (operands[1]) == MEM)
1631 /* Check for the cases that the operand constraints are not
1632 supposed to allow to happen. Abort if we get one,
1633 because generating code for these cases is painful. */
1635 if (optype0 != REGOP && optype1 != REGOP)
1638 /* Handle auto decrementing and incrementing loads and stores
1639 specifically, since the structure of the function doesn't work
1640 for them without major modification. Do it better when we learn
1641 this port about the general inc/dec addressing of PA.
1642 (This was written by tege. Chide him if it doesn't work.) */
1644 if (optype0 == MEMOP)
1646 /* We have to output the address syntax ourselves, since print_operand
1647 doesn't deal with the addresses we want to use. Fix this later. */
1649 rtx addr = XEXP (operands[0], 0);
1650 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1652 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1654 operands[0] = XEXP (addr, 0);
1655 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1658 if (!reg_overlap_mentioned_p (high_reg, addr))
1660 /* No overlap between high target register and address
1661 register. (We do this in a non-obvious way to
1662 save a register file writeback) */
1663 if (GET_CODE (addr) == POST_INC)
1664 return "stws,ma %1,8(%0)\n\tstw %R1,-4(%0)";
1665 return "stws,ma %1,-8(%0)\n\tstw %R1,12(%0)";
1670 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1672 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1674 operands[0] = XEXP (addr, 0);
1675 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1678 if (!reg_overlap_mentioned_p (high_reg, addr))
1680 /* No overlap between high target register and address
1681 register. (We do this in a non-obvious way to
1682 save a register file writeback) */
1683 if (GET_CODE (addr) == PRE_INC)
1684 return "stws,mb %1,8(%0)\n\tstw %R1,4(%0)";
1685 return "stws,mb %1,-8(%0)\n\tstw %R1,4(%0)";
1691 if (optype1 == MEMOP)
1693 /* We have to output the address syntax ourselves, since print_operand
1694 doesn't deal with the addresses we want to use. Fix this later. */
1696 rtx addr = XEXP (operands[1], 0);
1697 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1699 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1701 operands[1] = XEXP (addr, 0);
1702 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1705 if (!reg_overlap_mentioned_p (high_reg, addr))
1707 /* No overlap between high target register and address
1708 register. (We do this in a non-obvious way to
1709 save a register file writeback) */
1710 if (GET_CODE (addr) == POST_INC)
1711 return "ldws,ma 8(%1),%0\n\tldw -4(%1),%R0";
1712 return "ldws,ma -8(%1),%0\n\tldw 12(%1),%R0";
1716 /* This is an undefined situation. We should load into the
1717 address register *and* update that register. Probably
1718 we don't need to handle this at all. */
1719 if (GET_CODE (addr) == POST_INC)
1720 return "ldw 4(%1),%R0\n\tldws,ma 8(%1),%0";
1721 return "ldw 4(%1),%R0\n\tldws,ma -8(%1),%0";
1724 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1726 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1728 operands[1] = XEXP (addr, 0);
1729 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1732 if (!reg_overlap_mentioned_p (high_reg, addr))
1734 /* No overlap between high target register and address
1735 register. (We do this in a non-obvious way to
1736 save a register file writeback) */
1737 if (GET_CODE (addr) == PRE_INC)
1738 return "ldws,mb 8(%1),%0\n\tldw 4(%1),%R0";
1739 return "ldws,mb -8(%1),%0\n\tldw 4(%1),%R0";
1743 /* This is an undefined situation. We should load into the
1744 address register *and* update that register. Probably
1745 we don't need to handle this at all. */
1746 if (GET_CODE (addr) == PRE_INC)
1747 return "ldw 12(%1),%R0\n\tldws,mb 8(%1),%0";
1748 return "ldw -4(%1),%R0\n\tldws,mb -8(%1),%0";
1751 else if (GET_CODE (addr) == PLUS
1752 && GET_CODE (XEXP (addr, 0)) == MULT)
1754 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1756 if (!reg_overlap_mentioned_p (high_reg, addr))
1760 xoperands[0] = high_reg;
1761 xoperands[1] = XEXP (addr, 1);
1762 xoperands[2] = XEXP (XEXP (addr, 0), 0);
1763 xoperands[3] = XEXP (XEXP (addr, 0), 1);
1764 output_asm_insn ("sh%O3addl %2,%1,%0", xoperands);
1765 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
1771 xoperands[0] = high_reg;
1772 xoperands[1] = XEXP (addr, 1);
1773 xoperands[2] = XEXP (XEXP (addr, 0), 0);
1774 xoperands[3] = XEXP (XEXP (addr, 0), 1);
1775 output_asm_insn ("sh%O3addl %2,%1,%R0", xoperands);
1776 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
1782 /* If an operand is an unoffsettable memory ref, find a register
1783 we can increment temporarily to make it refer to the second word. */
1785 if (optype0 == MEMOP)
1786 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1788 if (optype1 == MEMOP)
1789 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1791 /* Ok, we can do one word at a time.
1792 Normally we do the low-numbered word first.
1794 In either case, set up in LATEHALF the operands to use
1795 for the high-numbered word and in some cases alter the
1796 operands in OPERANDS to be suitable for the low-numbered word. */
1798 if (optype0 == REGOP)
1799 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1800 else if (optype0 == OFFSOP)
1801 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1803 latehalf[0] = operands[0];
1805 if (optype1 == REGOP)
1806 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1807 else if (optype1 == OFFSOP)
1808 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1809 else if (optype1 == CNSTOP)
1810 split_double (operands[1], &operands[1], &latehalf[1]);
1812 latehalf[1] = operands[1];
1814 /* If the first move would clobber the source of the second one,
1815 do them in the other order.
1817 This can happen in two cases:
1819 mem -> register where the first half of the destination register
1820 is the same register used in the memory's address. Reload
1821 can create such insns.
1823 mem in this case will be either register indirect or register
1824 indirect plus a valid offset.
1826 register -> register move where REGNO(dst) == REGNO(src + 1)
1827 someone (Tim/Tege?) claimed this can happen for parameter loads.
1829 Handle mem -> register case first. */
1830 if (optype0 == REGOP
1831 && (optype1 == MEMOP || optype1 == OFFSOP)
1832 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
1835 /* Do the late half first. */
1837 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1838 output_asm_insn (singlemove_string (latehalf), latehalf);
1842 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1843 return singlemove_string (operands);
1846 /* Now handle register -> register case. */
1847 if (optype0 == REGOP && optype1 == REGOP
1848 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1850 output_asm_insn (singlemove_string (latehalf), latehalf);
1851 return singlemove_string (operands);
1854 /* Normal case: do the two words, low-numbered first. */
1856 output_asm_insn (singlemove_string (operands), operands);
1858 /* Make any unoffsettable addresses point at high-numbered word. */
1860 output_asm_insn ("ldo 4(%0),%0", &addreg0);
1862 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1865 output_asm_insn (singlemove_string (latehalf), latehalf);
1867 /* Undo the adds we just did. */
1869 output_asm_insn ("ldo -4(%0),%0", &addreg0);
1871 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1877 output_fp_move_double (operands)
1880 if (FP_REG_P (operands[0]))
1882 if (FP_REG_P (operands[1])
1883 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1884 output_asm_insn ("fcpy,dbl %r1,%0", operands);
1886 output_asm_insn ("fldd%F1 %1,%0", operands);
1888 else if (FP_REG_P (operands[1]))
1890 output_asm_insn ("fstd%F0 %1,%0", operands);
1892 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1894 if (GET_CODE (operands[0]) == REG)
1897 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1898 xoperands[0] = operands[0];
1899 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
1901 /* This is a pain. You have to be prepared to deal with an
1902 arbitrary address here including pre/post increment/decrement.
1904 so avoid this in the MD. */
1912 /* Return a REG that occurs in ADDR with coefficient 1.
1913 ADDR can be effectively incremented by incrementing REG. */
1916 find_addr_reg (addr)
1919 while (GET_CODE (addr) == PLUS)
1921 if (GET_CODE (XEXP (addr, 0)) == REG)
1922 addr = XEXP (addr, 0);
1923 else if (GET_CODE (XEXP (addr, 1)) == REG)
1924 addr = XEXP (addr, 1);
1925 else if (CONSTANT_P (XEXP (addr, 0)))
1926 addr = XEXP (addr, 1);
1927 else if (CONSTANT_P (XEXP (addr, 1)))
1928 addr = XEXP (addr, 0);
1932 if (GET_CODE (addr) == REG)
1937 /* Emit code to perform a block move.
1939 OPERANDS[0] is the destination pointer as a REG, clobbered.
1940 OPERANDS[1] is the source pointer as a REG, clobbered.
1941 OPERANDS[2] is a register for temporary storage.
1942 OPERANDS[4] is the size as a CONST_INT
1943 OPERANDS[3] is a register for temporary storage.
1944 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
1945 OPERANDS[6] is another temporary register. */
1948 output_block_move (operands, size_is_constant)
1950 int size_is_constant ATTRIBUTE_UNUSED;
1952 int align = INTVAL (operands[5]);
1953 unsigned long n_bytes = INTVAL (operands[4]);
1955 /* We can't move more than four bytes at a time because the PA
1956 has no longer integer move insns. (Could use fp mem ops?) */
1960 /* Note that we know each loop below will execute at least twice
1961 (else we would have open-coded the copy). */
1965 /* Pre-adjust the loop counter. */
1966 operands[4] = GEN_INT (n_bytes - 8);
1967 output_asm_insn ("ldi %4,%2", operands);
1970 output_asm_insn ("ldws,ma 4(%1),%3", operands);
1971 output_asm_insn ("ldws,ma 4(%1),%6", operands);
1972 output_asm_insn ("stws,ma %3,4(%0)", operands);
1973 output_asm_insn ("addib,>= -8,%2,.-12", operands);
1974 output_asm_insn ("stws,ma %6,4(%0)", operands);
1976 /* Handle the residual. There could be up to 7 bytes of
1977 residual to copy! */
1978 if (n_bytes % 8 != 0)
1980 operands[4] = GEN_INT (n_bytes % 4);
1981 if (n_bytes % 8 >= 4)
1982 output_asm_insn ("ldws,ma 4(%1),%3", operands);
1983 if (n_bytes % 4 != 0)
1984 output_asm_insn ("ldw 0(%1),%6", operands);
1985 if (n_bytes % 8 >= 4)
1986 output_asm_insn ("stws,ma %3,4(%0)", operands);
1987 if (n_bytes % 4 != 0)
1988 output_asm_insn ("stbys,e %6,%4(%0)", operands);
1993 /* Pre-adjust the loop counter. */
1994 operands[4] = GEN_INT (n_bytes - 4);
1995 output_asm_insn ("ldi %4,%2", operands);
1998 output_asm_insn ("ldhs,ma 2(%1),%3", operands);
1999 output_asm_insn ("ldhs,ma 2(%1),%6", operands);
2000 output_asm_insn ("sths,ma %3,2(%0)", operands);
2001 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2002 output_asm_insn ("sths,ma %6,2(%0)", operands);
2004 /* Handle the residual. */
2005 if (n_bytes % 4 != 0)
2007 if (n_bytes % 4 >= 2)
2008 output_asm_insn ("ldhs,ma 2(%1),%3", operands);
2009 if (n_bytes % 2 != 0)
2010 output_asm_insn ("ldb 0(%1),%6", operands);
2011 if (n_bytes % 4 >= 2)
2012 output_asm_insn ("sths,ma %3,2(%0)", operands);
2013 if (n_bytes % 2 != 0)
2014 output_asm_insn ("stb %6,0(%0)", operands);
2019 /* Pre-adjust the loop counter. */
2020 operands[4] = GEN_INT (n_bytes - 2);
2021 output_asm_insn ("ldi %4,%2", operands);
2024 output_asm_insn ("ldbs,ma 1(%1),%3", operands);
2025 output_asm_insn ("ldbs,ma 1(%1),%6", operands);
2026 output_asm_insn ("stbs,ma %3,1(%0)", operands);
2027 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2028 output_asm_insn ("stbs,ma %6,1(%0)", operands);
2030 /* Handle the residual. */
2031 if (n_bytes % 2 != 0)
2033 output_asm_insn ("ldb 0(%1),%3", operands);
2034 output_asm_insn ("stb %3,0(%0)", operands);
2043 /* Count the number of insns necessary to handle this block move.
2045 Basic structure is the same as emit_block_move, except that we
2046 count insns rather than emit them. */
2049 compute_movstrsi_length (insn)
2052 rtx pat = PATTERN (insn);
2053 int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2054 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
2055 unsigned int n_insns = 0;
2057 /* We can't move more than four bytes at a time because the PA
2058 has no longer integer move insns. (Could use fp mem ops?) */
2062 /* The basic copying loop. */
2066 if (n_bytes % (2 * align) != 0)
2068 if ((n_bytes % (2 * align)) >= align)
2071 if ((n_bytes % align) != 0)
2075 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2081 output_and (operands)
2084 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2086 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2087 int ls0, ls1, ms0, p, len;
2089 for (ls0 = 0; ls0 < 32; ls0++)
2090 if ((mask & (1 << ls0)) == 0)
2093 for (ls1 = ls0; ls1 < 32; ls1++)
2094 if ((mask & (1 << ls1)) != 0)
2097 for (ms0 = ls1; ms0 < 32; ms0++)
2098 if ((mask & (1 << ms0)) == 0)
2111 operands[2] = GEN_INT (len);
2112 return "extru %1,31,%2,%0";
2116 /* We could use this `depi' for the case above as well, but `depi'
2117 requires one more register file access than an `extru'. */
2122 operands[2] = GEN_INT (p);
2123 operands[3] = GEN_INT (len);
2124 return "depi 0,%2,%3,%0";
2128 return "and %1,%2,%0";
2132 output_ior (operands)
2135 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2136 int bs0, bs1, p, len;
2138 if (INTVAL (operands[2]) == 0)
2139 return "copy %1,%0";
2141 for (bs0 = 0; bs0 < 32; bs0++)
2142 if ((mask & (1 << bs0)) != 0)
2145 for (bs1 = bs0; bs1 < 32; bs1++)
2146 if ((mask & (1 << bs1)) == 0)
2149 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2155 operands[2] = GEN_INT (p);
2156 operands[3] = GEN_INT (len);
2157 return "depi -1,%2,%3,%0";
2160 /* Output an ascii string. */
2162 output_ascii (file, p, size)
2169 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2171 /* The HP assembler can only take strings of 256 characters at one
2172 time. This is a limitation on input line length, *not* the
2173 length of the string. Sigh. Even worse, it seems that the
2174 restriction is in number of input characters (see \xnn &
2175 \whatever). So we have to do this very carefully. */
2177 fputs ("\t.STRING \"", file);
2180 for (i = 0; i < size; i += 4)
2184 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2186 register unsigned int c = p[i + io];
2188 if (c == '\"' || c == '\\')
2189 partial_output[co++] = '\\';
2190 if (c >= ' ' && c < 0177)
2191 partial_output[co++] = c;
2195 partial_output[co++] = '\\';
2196 partial_output[co++] = 'x';
2197 hexd = c / 16 - 0 + '0';
2199 hexd -= '9' - 'a' + 1;
2200 partial_output[co++] = hexd;
2201 hexd = c % 16 - 0 + '0';
2203 hexd -= '9' - 'a' + 1;
2204 partial_output[co++] = hexd;
2207 if (chars_output + co > 243)
2209 fputs ("\"\n\t.STRING \"", file);
2212 fwrite (partial_output, 1, co, file);
2216 fputs ("\"\n", file);
2219 /* Try to rewrite floating point comparisons & branches to avoid
2220 useless add,tr insns.
2222 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2223 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2224 first attempt to remove useless add,tr insns. It is zero
2225 for the second pass as reorg sometimes leaves bogus REG_DEAD
2228 When CHECK_NOTES is zero we can only eliminate add,tr insns
2229 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2232 remove_useless_addtr_insns (insns, check_notes)
2237 static int pass = 0;
2239 /* This is fairly cheap, so always run it when optimizing. */
2243 int fbranch_count = 0;
2245 /* Walk all the insns in this function looking for fcmp & fbranch
2246 instructions. Keep track of how many of each we find. */
2247 insns = get_insns ();
2248 for (insn = insns; insn; insn = next_insn (insn))
2252 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2253 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2256 tmp = PATTERN (insn);
2258 /* It must be a set. */
2259 if (GET_CODE (tmp) != SET)
2262 /* If the destination is CCFP, then we've found an fcmp insn. */
2263 tmp = SET_DEST (tmp);
2264 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2270 tmp = PATTERN (insn);
2271 /* If this is an fbranch instruction, bump the fbranch counter. */
2272 if (GET_CODE (tmp) == SET
2273 && SET_DEST (tmp) == pc_rtx
2274 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2275 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2276 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2277 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2285 /* Find all floating point compare + branch insns. If possible,
2286 reverse the comparison & the branch to avoid add,tr insns. */
2287 for (insn = insns; insn; insn = next_insn (insn))
2291 /* Ignore anything that isn't an INSN. */
2292 if (GET_CODE (insn) != INSN)
2295 tmp = PATTERN (insn);
2297 /* It must be a set. */
2298 if (GET_CODE (tmp) != SET)
2301 /* The destination must be CCFP, which is register zero. */
2302 tmp = SET_DEST (tmp);
2303 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2306 /* INSN should be a set of CCFP.
2308 See if the result of this insn is used in a reversed FP
2309 conditional branch. If so, reverse our condition and
2310 the branch. Doing so avoids useless add,tr insns. */
2311 next = next_insn (insn);
2314 /* Jumps, calls and labels stop our search. */
2315 if (GET_CODE (next) == JUMP_INSN
2316 || GET_CODE (next) == CALL_INSN
2317 || GET_CODE (next) == CODE_LABEL)
2320 /* As does another fcmp insn. */
2321 if (GET_CODE (next) == INSN
2322 && GET_CODE (PATTERN (next)) == SET
2323 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2324 && REGNO (SET_DEST (PATTERN (next))) == 0)
2327 next = next_insn (next);
2330 /* Is NEXT_INSN a branch? */
2332 && GET_CODE (next) == JUMP_INSN)
2334 rtx pattern = PATTERN (next);
2336 /* If it a reversed fp conditional branch (eg uses add,tr)
2337 and CCFP dies, then reverse our conditional and the branch
2338 to avoid the add,tr. */
2339 if (GET_CODE (pattern) == SET
2340 && SET_DEST (pattern) == pc_rtx
2341 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2342 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2343 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2344 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2345 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2346 && (fcmp_count == fbranch_count
2348 && find_regno_note (next, REG_DEAD, 0))))
2350 /* Reverse the branch. */
2351 tmp = XEXP (SET_SRC (pattern), 1);
2352 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2353 XEXP (SET_SRC (pattern), 2) = tmp;
2354 INSN_CODE (next) = -1;
2356 /* Reverse our condition. */
2357 tmp = PATTERN (insn);
2358 PUT_CODE (XEXP (tmp, 1),
2359 reverse_condition (GET_CODE (XEXP (tmp, 1))));
2369 /* You may have trouble believing this, but this is the HP-PA stack
2374 Variable arguments (optional; any number may be allocated)
2376 SP-(4*(N+9)) arg word N
2381 Fixed arguments (must be allocated; may remain unused)
2390 SP-32 External Data Pointer (DP)
2392 SP-24 External/stub RP (RP')
2396 SP-8 Calling Stub RP (RP'')
2401 SP-0 Stack Pointer (points to next available address)
2405 /* This function saves registers as follows. Registers marked with ' are
2406 this function's registers (as opposed to the previous function's).
2407 If a frame_pointer isn't needed, r4 is saved as a general register;
2408 the space for the frame pointer is still allocated, though, to keep
2414 SP (FP') Previous FP
2415 SP + 4 Alignment filler (sigh)
2416 SP + 8 Space for locals reserved here.
2420 SP + n All call saved register used.
2424 SP + o All call saved fp registers used.
2428 SP + p (SP') points to next available address.
2432 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2433 Handle case where DISP > 8k by using the add_high_const pattern.
2435 Note in DISP > 8k case, we will leave the high part of the address
2436 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2438 store_reg (reg, disp, base)
2439 int reg, disp, base;
2441 if (VAL_14_BITS_P (disp))
2443 emit_move_insn (gen_rtx_MEM (SImode,
2444 gen_rtx_PLUS (SImode,
2445 gen_rtx_REG (SImode, base),
2447 gen_rtx_REG (SImode, reg));
2451 emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
2452 gen_rtx_REG (SImode, base),
2454 emit_move_insn (gen_rtx_MEM (SImode,
2455 gen_rtx_LO_SUM (SImode,
2456 gen_rtx_REG (SImode, 1),
2458 gen_rtx_REG (SImode, reg));
2462 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
2463 Handle case where DISP > 8k by using the add_high_const pattern.
2465 Note in DISP > 8k case, we will leave the high part of the address
2466 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2468 load_reg (reg, disp, base)
2469 int reg, disp, base;
2471 if (VAL_14_BITS_P (disp))
2473 emit_move_insn (gen_rtx_REG (SImode, reg),
2474 gen_rtx_MEM (SImode,
2475 gen_rtx_PLUS (SImode,
2476 gen_rtx_REG (SImode, base),
2481 emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
2482 gen_rtx_REG (SImode, base),
2484 emit_move_insn (gen_rtx_REG (SImode, reg),
2485 gen_rtx_MEM (SImode,
2486 gen_rtx_LO_SUM (SImode,
2487 gen_rtx_REG (SImode, 1),
2492 /* Emit RTL to set REG to the value specified by BASE+DISP.
2493 Handle case where DISP > 8k by using the add_high_const pattern.
2495 Note in DISP > 8k case, we will leave the high part of the address
2496 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2498 set_reg_plus_d(reg, base, disp)
2499 int reg, base, disp;
2501 if (VAL_14_BITS_P (disp))
2503 emit_move_insn (gen_rtx_REG (SImode, reg),
2504 gen_rtx_PLUS (SImode,
2505 gen_rtx_REG (SImode, base),
2510 emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
2511 gen_rtx_REG (SImode, base),
2513 emit_move_insn (gen_rtx_REG (SImode, reg),
2514 gen_rtx_LO_SUM (SImode,
2515 gen_rtx_REG (SImode, 1),
2520 /* Global variables set by FUNCTION_PROLOGUE. */
2521 /* Size of frame. Need to know this to emit return insns from
2523 static int actual_fsize;
2524 static int local_fsize, save_fregs;
2527 compute_frame_size (size, fregs_live)
2531 extern int current_function_outgoing_args_size;
2534 /* 8 is space for frame pointer + filler. If any frame is allocated
2535 we need to add this in because of STARTING_FRAME_OFFSET. */
2536 fsize = size + (size || frame_pointer_needed ? 8 : 0);
2538 /* We must leave enough space for all the callee saved registers
2539 from 3 .. highest used callee save register since we don't
2540 know if we're going to have an inline or out of line prologue
2542 for (i = 18; i >= 3; i--)
2543 if (regs_ever_live[i])
2545 fsize += 4 * (i - 2);
2549 /* Round the stack. */
2550 fsize = (fsize + 7) & ~7;
2552 /* We must leave enough space for all the callee saved registers
2553 from 3 .. highest used callee save register since we don't
2554 know if we're going to have an inline or out of line prologue
2556 for (i = 66; i >= 48; i -= 2)
2557 if (regs_ever_live[i] || regs_ever_live[i + 1])
2562 fsize += 4 * (i - 46);
2566 fsize += current_function_outgoing_args_size;
2567 if (! leaf_function_p () || fsize)
2569 return (fsize + 63) & ~63;
2572 rtx hp_profile_label_rtx;
2573 static char hp_profile_label_name[8];
2575 output_function_prologue (file, size)
2577 int size ATTRIBUTE_UNUSED;
2579 /* The function's label and associated .PROC must never be
2580 separated and must be output *after* any profiling declarations
2581 to avoid changing spaces/subspaces within a procedure. */
2582 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
2583 fputs ("\t.PROC\n", file);
2585 /* hppa_expand_prologue does the dirty work now. We just need
2586 to output the assembler directives which denote the start
2588 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
2589 if (regs_ever_live[2] || profile_flag)
2590 fputs (",CALLS,SAVE_RP", file);
2592 fputs (",NO_CALLS", file);
2594 if (frame_pointer_needed)
2595 fputs (",SAVE_SP", file);
2597 /* Pass on information about the number of callee register saves
2598 performed in the prologue.
2600 The compiler is supposed to pass the highest register number
2601 saved, the assembler then has to adjust that number before
2602 entering it into the unwind descriptor (to account for any
2603 caller saved registers with lower register numbers than the
2604 first callee saved register). */
2606 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
2609 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
2611 fputs ("\n\t.ENTRY\n", file);
2613 /* Horrid hack. emit_function_prologue will modify this RTL in
2614 place to get the expected results. */
2616 ASM_GENERATE_INTERNAL_LABEL (hp_profile_label_name, "LP",
2617 hp_profile_labelno);
2619 /* If we're using GAS and not using the portable runtime model, then
2620 we don't need to accumulate the total number of code bytes. */
2621 if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
2622 total_code_bytes = 0;
2623 else if (insn_addresses)
2625 unsigned int old_total = total_code_bytes;
2627 total_code_bytes += insn_addresses[INSN_UID (get_last_insn())];
2628 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
2630 /* Be prepared to handle overflows. */
2631 total_code_bytes = old_total > total_code_bytes ? -1 : total_code_bytes;
2634 total_code_bytes = -1;
2636 remove_useless_addtr_insns (get_insns (), 0);
2638 /* Restore INSN_CODEs for insn which use unscaled indexed addresses. */
2639 restore_unscaled_index_insn_codes (get_insns ());
2643 hppa_expand_prologue()
2645 extern char call_used_regs[];
2646 int size = get_frame_size ();
2647 int merge_sp_adjust_with_store = 0;
2649 rtx tmpreg, size_rtx;
2654 local_fsize = size + (size || frame_pointer_needed ? 8 : 0);
2655 actual_fsize = compute_frame_size (size, &save_fregs);
2657 /* Compute a few things we will use often. */
2658 tmpreg = gen_rtx_REG (SImode, 1);
2659 size_rtx = GEN_INT (actual_fsize);
2661 /* Handle out of line prologues and epilogues. */
2666 int outline_insn_count = 0;
2667 int inline_insn_count = 0;
2669 /* Count the number of insns for the inline and out of line
2670 variants so we can choose one appropriately.
2672 No need to screw with counting actual_fsize operations -- they're
2673 done for both inline and out of line prologues. */
2674 if (regs_ever_live[2])
2675 inline_insn_count += 1;
2677 if (! cint_ok_for_move (local_fsize))
2678 outline_insn_count += 2;
2680 outline_insn_count += 1;
2682 /* Put the register save info into %r22. */
2683 for (i = 18; i >= 3; i--)
2684 if (regs_ever_live[i] && ! call_used_regs[i])
2686 /* -1 because the stack adjustment is normally done in
2687 the same insn as a register save. */
2688 inline_insn_count += (i - 2) - 1;
2693 for (i = 66; i >= 48; i -= 2)
2694 if (regs_ever_live[i] || regs_ever_live[i + 1])
2696 /* +1 needed as we load %r1 with the start of the freg
2698 inline_insn_count += (i/2 - 23) + 1;
2699 saves |= ((i/2 - 12 ) << 16);
2703 if (frame_pointer_needed)
2704 inline_insn_count += 3;
2706 if (! cint_ok_for_move (saves))
2707 outline_insn_count += 2;
2709 outline_insn_count += 1;
2711 if (TARGET_PORTABLE_RUNTIME)
2712 outline_insn_count += 2;
2714 outline_insn_count += 1;
2716 /* If there's a lot of insns in the prologue, then do it as
2717 an out-of-line sequence. */
2718 if (inline_insn_count > outline_insn_count)
2720 /* Put the local_fisze into %r19. */
2721 operands[0] = gen_rtx_REG (SImode, 19);
2722 operands[1] = GEN_INT (local_fsize);
2723 emit_move_insn (operands[0], operands[1]);
2725 /* Put the stack size into %r21. */
2726 operands[0] = gen_rtx_REG (SImode, 21);
2727 operands[1] = size_rtx;
2728 emit_move_insn (operands[0], operands[1]);
2730 operands[0] = gen_rtx_REG (SImode, 22);
2731 operands[1] = GEN_INT (saves);
2732 emit_move_insn (operands[0], operands[1]);
2734 /* Now call the out-of-line prologue. */
2735 emit_insn (gen_outline_prologue_call ());
2736 emit_insn (gen_blockage ());
2738 /* Note that we're using an out-of-line prologue. */
2739 out_of_line_prologue_epilogue = 1;
2744 out_of_line_prologue_epilogue = 0;
2746 /* Save RP first. The calling conventions manual states RP will
2747 always be stored into the caller's frame at sp-20. */
2748 if (regs_ever_live[2] || profile_flag)
2749 store_reg (2, -20, STACK_POINTER_REGNUM);
2751 /* Allocate the local frame and set up the frame pointer if needed. */
2754 if (frame_pointer_needed)
2756 /* Copy the old frame pointer temporarily into %r1. Set up the
2757 new stack pointer, then store away the saved old frame pointer
2758 into the stack at sp+actual_fsize and at the same time update
2759 the stack pointer by actual_fsize bytes. Two versions, first
2760 handles small (<8k) frames. The second handles large (>8k)
2762 emit_move_insn (tmpreg, frame_pointer_rtx);
2763 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2764 if (VAL_14_BITS_P (actual_fsize))
2765 emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, size_rtx));
2768 /* It is incorrect to store the saved frame pointer at *sp,
2769 then increment sp (writes beyond the current stack boundary).
2771 So instead use stwm to store at *sp and post-increment the
2772 stack pointer as an atomic operation. Then increment sp to
2773 finish allocating the new frame. */
2774 emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, GEN_INT (64)));
2775 set_reg_plus_d (STACK_POINTER_REGNUM,
2776 STACK_POINTER_REGNUM,
2780 /* no frame pointer needed. */
2783 /* In some cases we can perform the first callee register save
2784 and allocating the stack frame at the same time. If so, just
2785 make a note of it and defer allocating the frame until saving
2786 the callee registers. */
2787 if (VAL_14_BITS_P (-actual_fsize)
2791 merge_sp_adjust_with_store = 1;
2792 /* Can not optimize. Adjust the stack frame by actual_fsize bytes. */
2793 else if (actual_fsize != 0)
2794 set_reg_plus_d (STACK_POINTER_REGNUM,
2795 STACK_POINTER_REGNUM,
2800 /* The hppa calling conventions say that %r19, the pic offset
2801 register, is saved at sp - 32 (in this function's frame) when
2802 generating PIC code. FIXME: What is the correct thing to do
2803 for functions which make no calls and allocate no frame? Do
2804 we need to allocate a frame, or can we just omit the save? For
2805 now we'll just omit the save. */
2806 if (actual_fsize != 0 && flag_pic)
2807 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
2811 Instead of taking one argument, the counter label, as most normal
2812 mcounts do, _mcount appears to behave differently on the HPPA. It
2813 takes the return address of the caller, the address of this routine,
2814 and the address of the label. Also, it isn't magic, so
2815 argument registers have to be preserved. */
2818 int pc_offset, i, arg_offset, basereg, offsetadj;
2820 pc_offset = 4 + (frame_pointer_needed
2821 ? (VAL_14_BITS_P (actual_fsize) ? 12 : 20)
2822 : (VAL_14_BITS_P (actual_fsize) ? 4 : 8));
2824 /* When the function has a frame pointer, use it as the base
2825 register for saving/restore registers. Else use the stack
2826 pointer. Adjust the offset according to the frame size if
2827 this function does not have a frame pointer. */
2829 basereg = frame_pointer_needed ? FRAME_POINTER_REGNUM
2830 : STACK_POINTER_REGNUM;
2831 offsetadj = frame_pointer_needed ? 0 : actual_fsize;
2833 /* Horrid hack. emit_function_prologue will modify this RTL in
2834 place to get the expected results. sprintf here is just to
2835 put something in the name. */
2836 sprintf(hp_profile_label_name, "LP$%04d", -1);
2837 hp_profile_label_rtx = gen_rtx_SYMBOL_REF (SImode, hp_profile_label_name);
2838 if (current_function_returns_struct)
2839 store_reg (STRUCT_VALUE_REGNUM, - 12 - offsetadj, basereg);
2840 if (current_function_needs_context)
2841 store_reg (STATIC_CHAIN_REGNUM, - 16 - offsetadj, basereg);
2843 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2844 if (regs_ever_live [i])
2846 store_reg (i, arg_offset, basereg);
2847 /* Deal with arg_offset not fitting in 14 bits. */
2848 pc_offset += VAL_14_BITS_P (arg_offset) ? 4 : 8;
2851 emit_move_insn (gen_rtx_REG (SImode, 26), gen_rtx_REG (SImode, 2));
2852 emit_move_insn (tmpreg, gen_rtx_HIGH (SImode, hp_profile_label_rtx));
2853 emit_move_insn (gen_rtx_REG (SImode, 24),
2854 gen_rtx_LO_SUM (SImode, tmpreg, hp_profile_label_rtx));
2855 /* %r25 is set from within the output pattern. */
2856 emit_insn (gen_call_profiler (GEN_INT (- pc_offset - 20)));
2858 /* Restore argument registers. */
2859 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2860 if (regs_ever_live [i])
2861 load_reg (i, arg_offset, basereg);
2863 if (current_function_returns_struct)
2864 load_reg (STRUCT_VALUE_REGNUM, -12 - offsetadj, basereg);
2866 if (current_function_needs_context)
2867 load_reg (STATIC_CHAIN_REGNUM, -16 - offsetadj, basereg);
2870 /* Normal register save.
2872 Do not save the frame pointer in the frame_pointer_needed case. It
2873 was done earlier. */
2874 if (frame_pointer_needed)
2876 for (i = 18, offset = local_fsize; i >= 4; i--)
2877 if (regs_ever_live[i] && ! call_used_regs[i])
2879 store_reg (i, offset, FRAME_POINTER_REGNUM);
2883 /* Account for %r3 which is saved in a special place. */
2886 /* No frame pointer needed. */
2889 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
2890 if (regs_ever_live[i] && ! call_used_regs[i])
2892 /* If merge_sp_adjust_with_store is nonzero, then we can
2893 optimize the first GR save. */
2894 if (merge_sp_adjust_with_store)
2896 merge_sp_adjust_with_store = 0;
2897 emit_insn (gen_post_stwm (stack_pointer_rtx,
2898 gen_rtx_REG (SImode, i),
2899 GEN_INT (-offset)));
2902 store_reg (i, offset, STACK_POINTER_REGNUM);
2907 /* If we wanted to merge the SP adjustment with a GR save, but we never
2908 did any GR saves, then just emit the adjustment here. */
2909 if (merge_sp_adjust_with_store)
2910 set_reg_plus_d (STACK_POINTER_REGNUM,
2911 STACK_POINTER_REGNUM,
2915 /* Align pointer properly (doubleword boundary). */
2916 offset = (offset + 7) & ~7;
2918 /* Floating point register store. */
2921 /* First get the frame or stack pointer to the start of the FP register
2923 if (frame_pointer_needed)
2924 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
2926 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
2928 /* Now actually save the FP registers. */
2929 for (i = 66; i >= 48; i -= 2)
2931 if (regs_ever_live[i] || regs_ever_live[i + 1])
2933 emit_move_insn (gen_rtx_MEM (DFmode,
2934 gen_rtx_POST_INC (DFmode, tmpreg)),
2935 gen_rtx_REG (DFmode, i));
2941 /* When generating PIC code it is necessary to save/restore the
2942 PIC register around each function call. We used to do this
2943 in the call patterns themselves, but that implementation
2944 made incorrect assumptions about using global variables to hold
2945 per-function rtl code generated in the backend.
2947 So instead, we copy the PIC register into a reserved callee saved
2948 register in the prologue. Then after each call we reload the PIC
2949 register from the callee saved register. We also reload the PIC
2950 register from the callee saved register in the epilogue ensure the
2951 PIC register is valid at function exit.
2953 This may (depending on the exact characteristics of the function)
2954 even be more efficient.
2956 Avoid this if the callee saved register wasn't used (these are
2958 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM_SAVED])
2959 emit_move_insn (gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM_SAVED),
2960 gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM));
2965 output_function_epilogue (file, size)
2967 int size ATTRIBUTE_UNUSED;
2969 rtx insn = get_last_insn ();
2971 /* hppa_expand_epilogue does the dirty work now. We just need
2972 to output the assembler directives which denote the end
2975 To make debuggers happy, emit a nop if the epilogue was completely
2976 eliminated due to a volatile call as the last insn in the
2977 current function. That way the return address (in %r2) will
2978 always point to a valid instruction in the current function. */
2980 /* Get the last real insn. */
2981 if (GET_CODE (insn) == NOTE)
2982 insn = prev_real_insn (insn);
2984 /* If it is a sequence, then look inside. */
2985 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
2986 insn = XVECEXP (PATTERN (insn), 0, 0);
2988 /* If insn is a CALL_INSN, then it must be a call to a volatile
2989 function (otherwise there would be epilogue insns). */
2990 if (insn && GET_CODE (insn) == CALL_INSN)
2991 fputs ("\tnop\n", file);
2993 fputs ("\t.EXIT\n\t.PROCEND\n", file);
2995 /* Free up stuff we don't need anymore. */
2996 if (unscaled_index_insn_codes)
2997 free (unscaled_index_insn_codes);
2998 max_unscaled_index_insn_codes_uid = 0;
3002 hppa_expand_epilogue ()
3006 int merge_sp_adjust_with_load = 0;
3008 /* Handle out of line prologues and epilogues. */
3009 if (TARGET_SPACE && out_of_line_prologue_epilogue)
3014 /* Put the register save info into %r22. */
3015 for (i = 18; i >= 3; i--)
3016 if (regs_ever_live[i] && ! call_used_regs[i])
3022 for (i = 66; i >= 48; i -= 2)
3023 if (regs_ever_live[i] || regs_ever_live[i + 1])
3025 saves |= ((i/2 - 12 ) << 16);
3029 emit_insn (gen_blockage ());
3031 /* Put the local_fisze into %r19. */
3032 operands[0] = gen_rtx_REG (SImode, 19);
3033 operands[1] = GEN_INT (local_fsize);
3034 emit_move_insn (operands[0], operands[1]);
3036 /* Put the stack size into %r21. */
3037 operands[0] = gen_rtx_REG (SImode, 21);
3038 operands[1] = GEN_INT (actual_fsize);
3039 emit_move_insn (operands[0], operands[1]);
3041 operands[0] = gen_rtx_REG (SImode, 22);
3042 operands[1] = GEN_INT (saves);
3043 emit_move_insn (operands[0], operands[1]);
3045 /* Now call the out-of-line epilogue. */
3046 emit_insn (gen_outline_epilogue_call ());
3050 /* We will use this often. */
3051 tmpreg = gen_rtx_REG (SImode, 1);
3053 /* Try to restore RP early to avoid load/use interlocks when
3054 RP gets used in the return (bv) instruction. This appears to still
3055 be necessary even when we schedule the prologue and epilogue. */
3056 if (frame_pointer_needed
3057 && (regs_ever_live [2] || profile_flag))
3058 load_reg (2, -20, FRAME_POINTER_REGNUM);
3060 /* No frame pointer, and stack is smaller than 8k. */
3061 else if (! frame_pointer_needed
3062 && VAL_14_BITS_P (actual_fsize + 20)
3063 && (regs_ever_live[2] || profile_flag))
3064 load_reg (2, - (actual_fsize + 20), STACK_POINTER_REGNUM);
3066 /* General register restores. */
3067 if (frame_pointer_needed)
3069 for (i = 18, offset = local_fsize; i >= 4; i--)
3070 if (regs_ever_live[i] && ! call_used_regs[i])
3072 load_reg (i, offset, FRAME_POINTER_REGNUM);
3078 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3080 if (regs_ever_live[i] && ! call_used_regs[i])
3082 /* Only for the first load.
3083 merge_sp_adjust_with_load holds the register load
3084 with which we will merge the sp adjustment. */
3085 if (VAL_14_BITS_P (actual_fsize + 20)
3087 && ! merge_sp_adjust_with_load)
3088 merge_sp_adjust_with_load = i;
3090 load_reg (i, offset, STACK_POINTER_REGNUM);
3096 /* Align pointer properly (doubleword boundary). */
3097 offset = (offset + 7) & ~7;
3099 /* FP register restores. */
3102 /* Adjust the register to index off of. */
3103 if (frame_pointer_needed)
3104 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
3106 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
3108 /* Actually do the restores now. */
3109 for (i = 66; i >= 48; i -= 2)
3111 if (regs_ever_live[i] || regs_ever_live[i + 1])
3113 emit_move_insn (gen_rtx_REG (DFmode, i),
3114 gen_rtx_MEM (DFmode,
3115 gen_rtx_POST_INC (DFmode, tmpreg)));
3120 /* Emit a blockage insn here to keep these insns from being moved to
3121 an earlier spot in the epilogue, or into the main instruction stream.
3123 This is necessary as we must not cut the stack back before all the
3124 restores are finished. */
3125 emit_insn (gen_blockage ());
3126 /* No frame pointer, but we have a stack greater than 8k. We restore
3127 %r2 very late in this case. (All other cases are restored as early
3129 if (! frame_pointer_needed
3130 && ! VAL_14_BITS_P (actual_fsize + 20)
3131 && (regs_ever_live[2] || profile_flag))
3133 set_reg_plus_d (STACK_POINTER_REGNUM,
3134 STACK_POINTER_REGNUM,
3137 /* This used to try and be clever by not depending on the value in
3138 %r30 and instead use the value held in %r1 (so that the 2nd insn
3139 which sets %r30 could be put in the delay slot of the return insn).
3141 That won't work since if the stack is exactly 8k set_reg_plus_d
3142 doesn't set %r1, just %r30. */
3143 load_reg (2, - 20, STACK_POINTER_REGNUM);
3146 /* Reset stack pointer (and possibly frame pointer). The stack
3147 pointer is initially set to fp + 64 to avoid a race condition. */
3148 else if (frame_pointer_needed)
3150 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64);
3151 emit_insn (gen_pre_ldwm (frame_pointer_rtx,
3155 /* If we were deferring a callee register restore, do it now. */
3156 else if (! frame_pointer_needed && merge_sp_adjust_with_load)
3157 emit_insn (gen_pre_ldwm (gen_rtx_REG (SImode, merge_sp_adjust_with_load),
3159 GEN_INT (- actual_fsize)));
3160 else if (actual_fsize != 0)
3161 set_reg_plus_d (STACK_POINTER_REGNUM,
3162 STACK_POINTER_REGNUM,
3166 /* Fetch the return address for the frame COUNT steps up from
3167 the current frame, after the prologue. FRAMEADDR is the
3168 frame pointer of the COUNT frame.
3170 We want to ignore any export stub remnants here.
3172 The value returned is used in two different ways:
3174 1. To find a function's caller.
3176 2. To change the return address for a function.
3178 This function handles most instances of case 1; however, it will
3179 fail if there are two levels of stubs to execute on the return
3180 path. The only way I believe that can happen is if the return value
3181 needs a parameter relocation, which never happens for C code.
3183 This function handles most instances of case 2; however, it will
3184 fail if we did not originally have stub code on the return path
3185 but will need code on the new return path. This can happen if
3186 the caller & callee are both in the main program, but the new
3187 return location is in a shared library.
3189 To handle this correctly we need to set the return pointer at
3190 frame-20 to point to a return stub frame-24 to point to the
3191 location we wish to return to. */
3194 return_addr_rtx (count, frameaddr)
3195 int count ATTRIBUTE_UNUSED;
3202 saved_rp = gen_reg_rtx (Pmode);
3204 /* First, we start off with the normal return address pointer from
3207 emit_move_insn (saved_rp, plus_constant (frameaddr, -5 * UNITS_PER_WORD));
3209 /* Get pointer to the instruction stream. We have to mask out the
3210 privilege level from the two low order bits of the return address
3211 pointer here so that ins will point to the start of the first
3212 instruction that would have been executed if we returned. */
3213 ins = copy_to_reg (gen_rtx_AND (Pmode,
3214 copy_to_reg (gen_rtx_MEM (Pmode, saved_rp)),
3216 label = gen_label_rtx ();
3218 /* Check the instruction stream at the normal return address for the
3221 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3222 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3223 0x00011820 | stub+16: mtsp r1,sr0
3224 0xe0400002 | stub+20: be,n 0(sr0,rp)
3226 If it is an export stub, than our return address is really in
3229 emit_cmp_insn (gen_rtx_MEM (SImode, ins),
3230 GEN_INT (0x4bc23fd1),
3231 NE, NULL_RTX, SImode, 1, 0);
3232 emit_jump_insn (gen_bne (label));
3234 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3235 GEN_INT (0x004010a1),
3236 NE, NULL_RTX, SImode, 1, 0);
3237 emit_jump_insn (gen_bne (label));
3239 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3240 GEN_INT (0x00011820),
3241 NE, NULL_RTX, SImode, 1, 0);
3242 emit_jump_insn (gen_bne (label));
3244 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3245 GEN_INT (0xe0400002),
3246 NE, NULL_RTX, SImode, 1, 0);
3248 /* If there is no export stub then just use our initial guess of
3251 emit_jump_insn (gen_bne (label));
3253 /* Here we know that our return address pointer points to an export
3254 stub. We don't want to return the address of the export stub,
3255 but rather the return address that leads back into user code.
3256 That return address is stored at -24[frameaddr]. */
3258 emit_move_insn (saved_rp, plus_constant (frameaddr, -6 * UNITS_PER_WORD));
3261 return gen_rtx_MEM (Pmode, memory_address (Pmode, saved_rp));
3264 /* This is only valid once reload has completed because it depends on
3265 knowing exactly how much (if any) frame there is and...
3267 It's only valid if there is no frame marker to de-allocate and...
3269 It's only valid if %r2 hasn't been saved into the caller's frame
3270 (we're not profiling and %r2 isn't live anywhere). */
3272 hppa_can_use_return_insn_p ()
3274 return (reload_completed
3275 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3277 && ! regs_ever_live[2]
3278 && ! frame_pointer_needed);
3282 emit_bcond_fp (code, operand0)
3286 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3287 gen_rtx_IF_THEN_ELSE (VOIDmode,
3288 gen_rtx_fmt_ee (code,
3290 gen_rtx_REG (CCFPmode, 0),
3292 gen_rtx_LABEL_REF (VOIDmode, operand0),
3298 gen_cmp_fp (code, operand0, operand1)
3300 rtx operand0, operand1;
3302 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3303 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3306 /* Adjust the cost of a scheduling dependency. Return the new cost of
3307 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3310 pa_adjust_cost (insn, link, dep_insn, cost)
3316 enum attr_type attr_type;
3318 /* Don't adjust costs for a pa8000 chip. */
3319 if (pa_cpu >= PROCESSOR_8000)
3322 if (! recog_memoized (insn))
3325 attr_type = get_attr_type (insn);
3327 if (REG_NOTE_KIND (link) == 0)
3329 /* Data dependency; DEP_INSN writes a register that INSN reads some
3332 if (attr_type == TYPE_FPSTORE)
3334 rtx pat = PATTERN (insn);
3335 rtx dep_pat = PATTERN (dep_insn);
3336 if (GET_CODE (pat) == PARALLEL)
3338 /* This happens for the fstXs,mb patterns. */
3339 pat = XVECEXP (pat, 0, 0);
3341 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3342 /* If this happens, we have to extend this to schedule
3343 optimally. Return 0 for now. */
3346 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
3348 if (! recog_memoized (dep_insn))
3350 /* DEP_INSN is writing its result to the register
3351 being stored in the fpstore INSN. */
3352 switch (get_attr_type (dep_insn))
3355 /* This cost 3 cycles, not 2 as the md says for the
3364 case TYPE_FPSQRTSGL:
3365 case TYPE_FPSQRTDBL:
3366 /* In these important cases, we save one cycle compared to
3367 when flop instruction feed each other. */
3376 /* For other data dependencies, the default cost specified in the
3380 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3382 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3385 if (attr_type == TYPE_FPLOAD)
3387 rtx pat = PATTERN (insn);
3388 rtx dep_pat = PATTERN (dep_insn);
3389 if (GET_CODE (pat) == PARALLEL)
3391 /* This happens for the fldXs,mb patterns. */
3392 pat = XVECEXP (pat, 0, 0);
3394 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3395 /* If this happens, we have to extend this to schedule
3396 optimally. Return 0 for now. */
3399 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3401 if (! recog_memoized (dep_insn))
3403 switch (get_attr_type (dep_insn))
3410 case TYPE_FPSQRTSGL:
3411 case TYPE_FPSQRTDBL:
3412 /* A fpload can't be issued until one cycle before a
3413 preceding arithmetic operation has finished if
3414 the target of the fpload is any of the sources
3415 (or destination) of the arithmetic operation. */
3423 else if (attr_type == TYPE_FPALU)
3425 rtx pat = PATTERN (insn);
3426 rtx dep_pat = PATTERN (dep_insn);
3427 if (GET_CODE (pat) == PARALLEL)
3429 /* This happens for the fldXs,mb patterns. */
3430 pat = XVECEXP (pat, 0, 0);
3432 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3433 /* If this happens, we have to extend this to schedule
3434 optimally. Return 0 for now. */
3437 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3439 if (! recog_memoized (dep_insn))
3441 switch (get_attr_type (dep_insn))
3445 case TYPE_FPSQRTSGL:
3446 case TYPE_FPSQRTDBL:
3447 /* An ALU flop can't be issued until two cycles before a
3448 preceding divide or sqrt operation has finished if
3449 the target of the ALU flop is any of the sources
3450 (or destination) of the divide or sqrt operation. */
3459 /* For other anti dependencies, the cost is 0. */
3462 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3464 /* Output dependency; DEP_INSN writes a register that INSN writes some
3466 if (attr_type == TYPE_FPLOAD)
3468 rtx pat = PATTERN (insn);
3469 rtx dep_pat = PATTERN (dep_insn);
3470 if (GET_CODE (pat) == PARALLEL)
3472 /* This happens for the fldXs,mb patterns. */
3473 pat = XVECEXP (pat, 0, 0);
3475 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3476 /* If this happens, we have to extend this to schedule
3477 optimally. Return 0 for now. */
3480 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3482 if (! recog_memoized (dep_insn))
3484 switch (get_attr_type (dep_insn))
3491 case TYPE_FPSQRTSGL:
3492 case TYPE_FPSQRTDBL:
3493 /* A fpload can't be issued until one cycle before a
3494 preceding arithmetic operation has finished if
3495 the target of the fpload is the destination of the
3496 arithmetic operation. */
3504 else if (attr_type == TYPE_FPALU)
3506 rtx pat = PATTERN (insn);
3507 rtx dep_pat = PATTERN (dep_insn);
3508 if (GET_CODE (pat) == PARALLEL)
3510 /* This happens for the fldXs,mb patterns. */
3511 pat = XVECEXP (pat, 0, 0);
3513 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3514 /* If this happens, we have to extend this to schedule
3515 optimally. Return 0 for now. */
3518 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3520 if (! recog_memoized (dep_insn))
3522 switch (get_attr_type (dep_insn))
3526 case TYPE_FPSQRTSGL:
3527 case TYPE_FPSQRTDBL:
3528 /* An ALU flop can't be issued until two cycles before a
3529 preceding divide or sqrt operation has finished if
3530 the target of the ALU flop is also the target of
3531 the divide or sqrt operation. */
3540 /* For other output dependencies, the cost is 0. */
3547 /* Return any length adjustment needed by INSN which already has its length
3548 computed as LENGTH. Return zero if no adjustment is necessary.
3550 For the PA: function calls, millicode calls, and backwards short
3551 conditional branches with unfilled delay slots need an adjustment by +1
3552 (to account for the NOP which will be inserted into the instruction stream).
3554 Also compute the length of an inline block move here as it is too
3555 complicated to express as a length attribute in pa.md. */
3557 pa_adjust_insn_length (insn, length)
3561 rtx pat = PATTERN (insn);
3563 /* Call insns which are *not* indirect and have unfilled delay slots. */
3564 if (GET_CODE (insn) == CALL_INSN)
3567 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
3568 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
3570 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
3571 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
3577 /* Jumps inside switch tables which have unfilled delay slots
3578 also need adjustment. */
3579 else if (GET_CODE (insn) == JUMP_INSN
3580 && simplejump_p (insn)
3581 && GET_MODE (insn) == SImode)
3583 /* Millicode insn with an unfilled delay slot. */
3584 else if (GET_CODE (insn) == INSN
3585 && GET_CODE (pat) != SEQUENCE
3586 && GET_CODE (pat) != USE
3587 && GET_CODE (pat) != CLOBBER
3588 && get_attr_type (insn) == TYPE_MILLI)
3590 /* Block move pattern. */
3591 else if (GET_CODE (insn) == INSN
3592 && GET_CODE (pat) == PARALLEL
3593 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
3594 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
3595 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
3596 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
3597 return compute_movstrsi_length (insn) - 4;
3598 /* Conditional branch with an unfilled delay slot. */
3599 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
3601 /* Adjust a short backwards conditional with an unfilled delay slot. */
3602 if (GET_CODE (pat) == SET
3604 && ! forward_branch_p (insn))
3606 else if (GET_CODE (pat) == PARALLEL
3607 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
3610 /* Adjust dbra insn with short backwards conditional branch with
3611 unfilled delay slot -- only for case where counter is in a
3612 general register register. */
3613 else if (GET_CODE (pat) == PARALLEL
3614 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
3615 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
3616 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
3618 && ! forward_branch_p (insn))
3626 /* Print operand X (an rtx) in assembler syntax to file FILE.
3627 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3628 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3631 print_operand (file, x, code)
3639 /* Output a 'nop' if there's nothing for the delay slot. */
3640 if (dbr_sequence_length () == 0)
3641 fputs ("\n\tnop", file);
3644 /* Output an nullification completer if there's nothing for the */
3645 /* delay slot or nullification is requested. */
3646 if (dbr_sequence_length () == 0 ||
3648 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
3652 /* Print out the second register name of a register pair.
3653 I.e., R (6) => 7. */
3654 fputs (reg_names[REGNO (x)+1], file);
3657 /* A register or zero. */
3659 || (x == CONST0_RTX (DFmode))
3660 || (x == CONST0_RTX (SFmode)))
3667 case 'C': /* Plain (C)ondition */
3669 switch (GET_CODE (x))
3672 fputs ("=", file); break;
3674 fputs ("<>", file); break;
3676 fputs (">", file); break;
3678 fputs (">=", file); break;
3680 fputs (">>=", file); break;
3682 fputs (">>", file); break;
3684 fputs ("<", file); break;
3686 fputs ("<=", file); break;
3688 fputs ("<<=", file); break;
3690 fputs ("<<", file); break;
3695 case 'N': /* Condition, (N)egated */
3696 switch (GET_CODE (x))
3699 fputs ("<>", file); break;
3701 fputs ("=", file); break;
3703 fputs ("<=", file); break;
3705 fputs ("<", file); break;
3707 fputs ("<<", file); break;
3709 fputs ("<<=", file); break;
3711 fputs (">=", file); break;
3713 fputs (">", file); break;
3715 fputs (">>", file); break;
3717 fputs (">>=", file); break;
3722 /* For floating point comparisons. Need special conditions to deal
3723 with NaNs properly. */
3725 switch (GET_CODE (x))
3728 fputs ("!=", file); break;
3730 fputs ("=", file); break;
3732 fputs ("<=", file); break;
3734 fputs ("<", file); break;
3736 fputs (">=", file); break;
3738 fputs (">", file); break;
3743 case 'S': /* Condition, operands are (S)wapped. */
3744 switch (GET_CODE (x))
3747 fputs ("=", file); break;
3749 fputs ("<>", file); break;
3751 fputs ("<", file); break;
3753 fputs ("<=", file); break;
3755 fputs ("<<=", file); break;
3757 fputs ("<<", file); break;
3759 fputs (">", file); break;
3761 fputs (">=", file); break;
3763 fputs (">>=", file); break;
3765 fputs (">>", file); break;
3770 case 'B': /* Condition, (B)oth swapped and negate. */
3771 switch (GET_CODE (x))
3774 fputs ("<>", file); break;
3776 fputs ("=", file); break;
3778 fputs (">=", file); break;
3780 fputs (">", file); break;
3782 fputs (">>", file); break;
3784 fputs (">>=", file); break;
3786 fputs ("<=", file); break;
3788 fputs ("<", file); break;
3790 fputs ("<<", file); break;
3792 fputs ("<<=", file); break;
3798 if (GET_CODE (x) == CONST_INT)
3800 fprintf (file, "%d", ~INTVAL (x));
3805 if (GET_CODE (x) == CONST_INT)
3807 fprintf (file, "%d", 32 - (INTVAL (x) & 31));
3812 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
3814 fprintf (file, "%d", exact_log2 (INTVAL (x)));
3819 if (GET_CODE (x) == CONST_INT)
3821 fprintf (file, "%d", 31 - (INTVAL (x) & 31));
3826 if (GET_CODE (x) == CONST_INT)
3831 switch (GET_CODE (XEXP (x, 0)))
3835 fputs ("s,mb", file);
3839 fputs ("s,ma", file);
3842 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3843 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
3844 fputs ("x,s", file);
3845 else if (code == 'F')
3855 output_global_address (file, x, 0);
3858 output_global_address (file, x, 1);
3860 case 0: /* Don't do anything special */
3865 compute_zdepi_operands (INTVAL (x), op);
3866 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
3872 if (GET_CODE (x) == REG)
3874 fputs (reg_names [REGNO (x)], file);
3875 if (FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4 && (REGNO (x) & 1) == 0)
3878 else if (GET_CODE (x) == MEM)
3880 int size = GET_MODE_SIZE (GET_MODE (x));
3881 rtx base = XEXP (XEXP (x, 0), 0);
3882 switch (GET_CODE (XEXP (x, 0)))
3886 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
3890 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
3893 if (GET_CODE (XEXP (x, 0)) == PLUS
3894 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
3895 fprintf (file, "%s(%s)",
3896 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
3897 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
3898 else if (GET_CODE (XEXP (x, 0)) == PLUS
3899 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
3900 fprintf (file, "%s(%s)",
3901 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
3902 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
3904 output_address (XEXP (x, 0));
3909 output_addr_const (file, x);
3912 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
3915 output_global_address (file, x, round_constant)
3921 /* Imagine (high (const (plus ...))). */
3922 if (GET_CODE (x) == HIGH)
3925 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x))
3926 assemble_name (file, XSTR (x, 0));
3927 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
3929 assemble_name (file, XSTR (x, 0));
3930 fputs ("-$global$", file);
3932 else if (GET_CODE (x) == CONST)
3935 int offset = 0; /* assembler wants -$global$ at end */
3936 rtx base = NULL_RTX;
3938 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
3940 base = XEXP (XEXP (x, 0), 0);
3941 output_addr_const (file, base);
3943 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
3944 offset = INTVAL (XEXP (XEXP (x, 0), 0));
3947 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
3949 base = XEXP (XEXP (x, 0), 1);
3950 output_addr_const (file, base);
3952 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
3953 offset = INTVAL (XEXP (XEXP (x, 0),1));
3956 /* How bogus. The compiler is apparently responsible for
3957 rounding the constant if it uses an LR field selector.
3959 The linker and/or assembler seem a better place since
3960 they have to do this kind of thing already.
3962 If we fail to do this, HP's optimizing linker may eliminate
3963 an addil, but not update the ldw/stw/ldo instruction that
3964 uses the result of the addil. */
3966 offset = ((offset + 0x1000) & ~0x1fff);
3968 if (GET_CODE (XEXP (x, 0)) == PLUS)
3978 else if (GET_CODE (XEXP (x, 0)) == MINUS
3979 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3983 if (!read_only_operand (base) && !flag_pic)
3984 fputs ("-$global$", file);
3986 fprintf (file,"%s%d", sep, offset);
3989 output_addr_const (file, x);
3993 output_deferred_plabels (file)
3997 /* If we have deferred plabels, then we need to switch into the data
3998 section and align it to a 4 byte boundary before we output the
3999 deferred plabels. */
4000 if (n_deferred_plabels)
4003 ASM_OUTPUT_ALIGN (file, 2);
4006 /* Now output the deferred plabels. */
4007 for (i = 0; i < n_deferred_plabels; i++)
4009 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4010 assemble_integer (gen_rtx_SYMBOL_REF (VOIDmode,
4011 deferred_plabels[i].name), 4, 1);
4015 /* HP's millicode routines mean something special to the assembler.
4016 Keep track of which ones we have used. */
4018 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
4019 static char imported[(int)end1000];
4020 static char *milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4021 static char import_string[] = ".IMPORT $$....,MILLICODE";
4022 #define MILLI_START 10
4026 enum millicodes code;
4028 char str[sizeof (import_string)];
4030 if (!imported[(int)code])
4032 imported[(int)code] = 1;
4033 strcpy (str, import_string);
4034 strncpy (str + MILLI_START, milli_names[(int)code], 4);
4035 output_asm_insn (str, 0);
4039 /* The register constraints have put the operands and return value in
4040 the proper registers. */
4043 output_mul_insn (unsignedp, insn)
4044 int unsignedp ATTRIBUTE_UNUSED;
4047 import_milli (mulI);
4048 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (SImode, "$$mulI"));
4051 /* Emit the rtl for doing a division by a constant. */
4053 /* Do magic division millicodes exist for this value? */
4054 static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4057 /* We'll use an array to keep track of the magic millicodes and
4058 whether or not we've used them already. [n][0] is signed, [n][1] is
4061 static int div_milli[16][2];
4064 div_operand (op, mode)
4066 enum machine_mode mode;
4068 return (mode == SImode
4069 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4070 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4071 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4075 emit_hpdiv_const (operands, unsignedp)
4079 if (GET_CODE (operands[2]) == CONST_INT
4080 && INTVAL (operands[2]) > 0
4081 && INTVAL (operands[2]) < 16
4082 && magic_milli[INTVAL (operands[2])])
4084 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4087 (PARALLEL, VOIDmode,
4088 gen_rtvec (5, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4089 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4091 gen_rtx_REG (SImode, 26),
4093 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4094 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4095 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4096 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 31)))));
4097 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4104 output_div_insn (operands, unsignedp, insn)
4111 /* If the divisor is a constant, try to use one of the special
4113 if (GET_CODE (operands[0]) == CONST_INT)
4115 static char buf[100];
4116 divisor = INTVAL (operands[0]);
4117 if (!div_milli[divisor][unsignedp])
4119 div_milli[divisor][unsignedp] = 1;
4121 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4123 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4127 sprintf (buf, "$$divU_%d", INTVAL (operands[0]));
4128 return output_millicode_call (insn,
4129 gen_rtx_SYMBOL_REF (SImode, buf));
4133 sprintf (buf, "$$divI_%d", INTVAL (operands[0]));
4134 return output_millicode_call (insn,
4135 gen_rtx_SYMBOL_REF (SImode, buf));
4138 /* Divisor isn't a special constant. */
4143 import_milli (divU);
4144 return output_millicode_call (insn,
4145 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4149 import_milli (divI);
4150 return output_millicode_call (insn,
4151 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4156 /* Output a $$rem millicode to do mod. */
4159 output_mod_insn (unsignedp, insn)
4165 import_milli (remU);
4166 return output_millicode_call (insn,
4167 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4171 import_milli (remI);
4172 return output_millicode_call (insn,
4173 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4178 output_arg_descriptor (call_insn)
4182 enum machine_mode arg_mode;
4184 int i, output_flag = 0;
4187 for (i = 0; i < 4; i++)
4190 /* Specify explicitly that no argument relocations should take place
4191 if using the portable runtime calling conventions. */
4192 if (TARGET_PORTABLE_RUNTIME)
4194 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4199 if (GET_CODE (call_insn) != CALL_INSN)
4201 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4203 rtx use = XEXP (link, 0);
4205 if (! (GET_CODE (use) == USE
4206 && GET_CODE (XEXP (use, 0)) == REG
4207 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4210 arg_mode = GET_MODE (XEXP (use, 0));
4211 regno = REGNO (XEXP (use, 0));
4212 if (regno >= 23 && regno <= 26)
4214 arg_regs[26 - regno] = "GR";
4215 if (arg_mode == DImode)
4216 arg_regs[25 - regno] = "GR";
4218 else if (regno >= 32 && regno <= 39)
4220 if (arg_mode == SFmode)
4221 arg_regs[(regno - 32) / 2] = "FR";
4224 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4225 arg_regs[(regno - 34) / 2] = "FR";
4226 arg_regs[(regno - 34) / 2 + 1] = "FU";
4228 arg_regs[(regno - 34) / 2] = "FU";
4229 arg_regs[(regno - 34) / 2 + 1] = "FR";
4234 fputs ("\t.CALL ", asm_out_file);
4235 for (i = 0; i < 4; i++)
4240 fputc (',', asm_out_file);
4241 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4244 fputc ('\n', asm_out_file);
4247 /* Return the class of any secondary reload register that is needed to
4248 move IN into a register in class CLASS using mode MODE.
4250 Profiling has showed this routine and its descendants account for
4251 a significant amount of compile time (~7%). So it has been
4252 optimized to reduce redundant computations and eliminate useless
4255 It might be worthwhile to try and make this a leaf function too. */
4258 secondary_reload_class (class, mode, in)
4259 enum reg_class class;
4260 enum machine_mode mode;
4263 int regno, is_symbolic;
4265 /* Trying to load a constant into a FP register during PIC code
4266 generation will require %r1 as a scratch register. */
4268 && GET_MODE_CLASS (mode) == MODE_INT
4269 && FP_REG_CLASS_P (class)
4270 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4273 /* Profiling showed the PA port spends about 1.3% of its compilation
4274 time in true_regnum from calls inside secondary_reload_class. */
4276 if (GET_CODE (in) == REG)
4279 if (regno >= FIRST_PSEUDO_REGISTER)
4280 regno = true_regnum (in);
4282 else if (GET_CODE (in) == SUBREG)
4283 regno = true_regnum (in);
4287 /* If we have something like (mem (mem (...)), we can safely assume the
4288 inner MEM will end up in a general register after reloading, so there's
4289 no need for a secondary reload. */
4290 if (GET_CODE (in) == MEM
4291 && GET_CODE (XEXP (in, 0)) == MEM)
4294 /* Handle out of range displacement for integer mode loads/stores of
4296 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
4297 && GET_MODE_CLASS (mode) == MODE_INT
4298 && FP_REG_CLASS_P (class))
4299 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
4300 return GENERAL_REGS;
4302 if (GET_CODE (in) == HIGH)
4305 /* Profiling has showed GCC spends about 2.6% of its compilation
4306 time in symbolic_operand from calls inside secondary_reload_class.
4308 We use an inline copy and only compute its return value once to avoid
4310 switch (GET_CODE (in))
4320 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
4321 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
4322 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
4332 && read_only_operand (in))
4335 if (class != R1_REGS && is_symbolic)
4342 function_arg_padding (mode, type)
4343 enum machine_mode mode;
4348 if (mode == BLKmode)
4350 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4351 size = int_size_in_bytes (type) * BITS_PER_UNIT;
4353 return upward; /* Don't know if this is right, but */
4354 /* same as old definition. */
4357 size = GET_MODE_BITSIZE (mode);
4358 if (size < PARM_BOUNDARY)
4360 else if (size % PARM_BOUNDARY)
4367 /* Do what is necessary for `va_start'. The argument is ignored;
4368 We look at the current function to determine if stdargs or varargs
4369 is used and fill in an initial va_list. A pointer to this constructor
4373 hppa_builtin_saveregs (arglist)
4374 tree arglist ATTRIBUTE_UNUSED;
4377 tree fntype = TREE_TYPE (current_function_decl);
4378 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
4379 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4380 != void_type_node)))
4381 ? UNITS_PER_WORD : 0);
4384 offset = plus_constant (current_function_arg_offset_rtx, argadj);
4386 offset = current_function_arg_offset_rtx;
4388 /* Store general registers on the stack. */
4389 dest = gen_rtx_MEM (BLKmode,
4390 plus_constant (current_function_internal_arg_pointer,
4392 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
4394 /* move_block_from_reg will emit code to store the argument registers
4395 individually as scalar stores.
4397 However, other insns may later load from the same addresses for
4398 a structure load (passing a struct to a varargs routine).
4400 The alias code assumes that such aliasing can never happen, so we
4401 have to keep memory referencing insns from moving up beyond the
4402 last argument register store. So we emit a blockage insn here. */
4403 emit_insn (gen_blockage ());
4405 if (current_function_check_memory_usage)
4406 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4408 GEN_INT (4 * UNITS_PER_WORD), TYPE_MODE (sizetype),
4409 GEN_INT (MEMORY_USE_RW),
4410 TYPE_MODE (integer_type_node));
4412 return copy_to_reg (expand_binop (Pmode, add_optab,
4413 current_function_internal_arg_pointer,
4414 offset, 0, 0, OPTAB_LIB_WIDEN));
4417 /* This routine handles all the normal conditional branch sequences we
4418 might need to generate. It handles compare immediate vs compare
4419 register, nullification of delay slots, varying length branches,
4420 negated branches, and all combinations of the above. It returns the
4421 output appropriate to emit the branch corresponding to all given
4425 output_cbranch (operands, nullify, length, negated, insn)
4427 int nullify, length, negated;
4430 static char buf[100];
4433 /* A conditional branch to the following instruction (eg the delay slot) is
4434 asking for a disaster. This can happen when not optimizing.
4436 In such cases it is safe to emit nothing. */
4438 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4441 /* If this is a long branch with its delay slot unfilled, set `nullify'
4442 as it can nullify the delay slot and save a nop. */
4443 if (length == 8 && dbr_sequence_length () == 0)
4446 /* If this is a short forward conditional branch which did not get
4447 its delay slot filled, the delay slot can still be nullified. */
4448 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4449 nullify = forward_branch_p (insn);
4451 /* A forward branch over a single nullified insn can be done with a
4452 comclr instruction. This avoids a single cycle penalty due to
4453 mis-predicted branch if we fall through (branch not taken). */
4455 && next_real_insn (insn) != 0
4456 && get_attr_length (next_real_insn (insn)) == 4
4457 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4463 /* All short conditional branches except backwards with an unfilled
4467 strcpy (buf, "com%I2clr,");
4469 strcpy (buf, "com%I2b,");
4471 strcat (buf, "%B3");
4473 strcat (buf, "%S3");
4475 strcat (buf, " %2,%r1,%%r0");
4477 strcat (buf, ",n %2,%r1,%0");
4479 strcat (buf, " %2,%r1,%0");
4482 /* All long conditionals. Note an short backward branch with an
4483 unfilled delay slot is treated just like a long backward branch
4484 with an unfilled delay slot. */
4486 /* Handle weird backwards branch with a filled delay slot
4487 with is nullified. */
4488 if (dbr_sequence_length () != 0
4489 && ! forward_branch_p (insn)
4492 strcpy (buf, "com%I2b,");
4494 strcat (buf, "%S3");
4496 strcat (buf, "%B3");
4497 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
4499 /* Handle short backwards branch with an unfilled delay slot.
4500 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
4501 taken and untaken branches. */
4502 else if (dbr_sequence_length () == 0
4503 && ! forward_branch_p (insn)
4505 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4506 - insn_addresses[INSN_UID (insn)] - 8))
4508 strcpy (buf, "com%I2b,");
4510 strcat (buf, "%B3 %2,%r1,%0%#");
4512 strcat (buf, "%S3 %2,%r1,%0%#");
4516 strcpy (buf, "com%I2clr,");
4518 strcat (buf, "%S3");
4520 strcat (buf, "%B3");
4522 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
4524 strcat (buf, " %2,%r1,%%r0\n\tb %0");
4529 /* Very long branch. Right now we only handle these when not
4530 optimizing. See "jump" pattern in pa.md for details. */
4534 /* Create a reversed conditional branch which branches around
4535 the following insns. */
4537 strcpy (buf, "com%I2b,%S3,n %2,%r1,.+20");
4539 strcpy (buf, "com%I2b,%B3,n %2,%r1,.+20");
4540 output_asm_insn (buf, operands);
4542 /* Output an insn to save %r1. */
4543 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
4545 /* Now output a very long branch to the original target. */
4546 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
4548 /* Now restore the value of %r1 in the delay slot. We're not
4549 optimizing so we know nothing else can be in the delay slot. */
4550 return "ldw -16(%%r30),%%r1";
4553 /* Very long branch when generating PIC code. Right now we only
4554 handle these when not optimizing. See "jump" pattern in pa.md
4559 /* Create a reversed conditional branch which branches around
4560 the following insns. */
4562 strcpy (buf, "com%I2b,%S3,n %2,%r1,.+28");
4564 strcpy (buf, "com%I2b,%B3,n %2,%r1,.+28");
4565 output_asm_insn (buf, operands);
4567 /* Output an insn to save %r1. */
4568 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
4570 /* Now output a very long PIC branch to the original target. */
4574 xoperands[0] = operands[0];
4575 xoperands[1] = operands[1];
4576 xoperands[2] = operands[2];
4577 xoperands[3] = operands[3];
4578 xoperands[4] = gen_label_rtx ();
4580 output_asm_insn ("bl .+8,%%r1\n\taddil L'%l0-%l4,%%r1", xoperands);
4581 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4582 CODE_LABEL_NUMBER (xoperands[4]));
4583 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
4587 /* Now restore the value of %r1 in the delay slot. We're not
4588 optimizing so we know nothing else can be in the delay slot. */
4589 return "ldw -16(%%r30),%%r1";
4597 /* This routine handles all the branch-on-bit conditional branch sequences we
4598 might need to generate. It handles nullification of delay slots,
4599 varying length branches, negated branches and all combinations of the
4600 above. it returns the appropriate output template to emit the branch. */
4603 output_bb (operands, nullify, length, negated, insn, which)
4604 rtx *operands ATTRIBUTE_UNUSED;
4605 int nullify, length, negated;
4609 static char buf[100];
4612 /* A conditional branch to the following instruction (eg the delay slot) is
4613 asking for a disaster. I do not think this can happen as this pattern
4614 is only used when optimizing; jump optimization should eliminate the
4615 jump. But be prepared just in case. */
4617 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4620 /* If this is a long branch with its delay slot unfilled, set `nullify'
4621 as it can nullify the delay slot and save a nop. */
4622 if (length == 8 && dbr_sequence_length () == 0)
4625 /* If this is a short forward conditional branch which did not get
4626 its delay slot filled, the delay slot can still be nullified. */
4627 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4628 nullify = forward_branch_p (insn);
4630 /* A forward branch over a single nullified insn can be done with a
4631 extrs instruction. This avoids a single cycle penalty due to
4632 mis-predicted branch if we fall through (branch not taken). */
4635 && next_real_insn (insn) != 0
4636 && get_attr_length (next_real_insn (insn)) == 4
4637 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4644 /* All short conditional branches except backwards with an unfilled
4648 strcpy (buf, "extrs,");
4650 strcpy (buf, "bb,");
4651 if ((which == 0 && negated)
4652 || (which == 1 && ! negated))
4657 strcat (buf, " %0,%1,1,%%r0");
4658 else if (nullify && negated)
4659 strcat (buf, ",n %0,%1,%3");
4660 else if (nullify && ! negated)
4661 strcat (buf, ",n %0,%1,%2");
4662 else if (! nullify && negated)
4663 strcat (buf, "%0,%1,%3");
4664 else if (! nullify && ! negated)
4665 strcat (buf, " %0,%1,%2");
4668 /* All long conditionals. Note an short backward branch with an
4669 unfilled delay slot is treated just like a long backward branch
4670 with an unfilled delay slot. */
4672 /* Handle weird backwards branch with a filled delay slot
4673 with is nullified. */
4674 if (dbr_sequence_length () != 0
4675 && ! forward_branch_p (insn)
4678 strcpy (buf, "bb,");
4679 if ((which == 0 && negated)
4680 || (which == 1 && ! negated))
4685 strcat (buf, ",n %0,%1,.+12\n\tb %3");
4687 strcat (buf, ",n %0,%1,.+12\n\tb %2");
4689 /* Handle short backwards branch with an unfilled delay slot.
4690 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4691 taken and untaken branches. */
4692 else if (dbr_sequence_length () == 0
4693 && ! forward_branch_p (insn)
4695 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4696 - insn_addresses[INSN_UID (insn)] - 8))
4698 strcpy (buf, "bb,");
4699 if ((which == 0 && negated)
4700 || (which == 1 && ! negated))
4705 strcat (buf, " %0,%1,%3%#");
4707 strcat (buf, " %0,%1,%2%#");
4711 strcpy (buf, "extrs,");
4712 if ((which == 0 && negated)
4713 || (which == 1 && ! negated))
4717 if (nullify && negated)
4718 strcat (buf, " %0,%1,1,%%r0\n\tbn %3");
4719 else if (nullify && ! negated)
4720 strcat (buf, " %0,%1,1,%%r0\n\tbn %2");
4722 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
4724 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
4734 /* This routine handles all the branch-on-variable-bit conditional branch
4735 sequences we might need to generate. It handles nullification of delay
4736 slots, varying length branches, negated branches and all combinations
4737 of the above. it returns the appropriate output template to emit the
4741 output_bvb (operands, nullify, length, negated, insn, which)
4742 rtx *operands ATTRIBUTE_UNUSED;
4743 int nullify, length, negated;
4747 static char buf[100];
4750 /* A conditional branch to the following instruction (eg the delay slot) is
4751 asking for a disaster. I do not think this can happen as this pattern
4752 is only used when optimizing; jump optimization should eliminate the
4753 jump. But be prepared just in case. */
4755 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4758 /* If this is a long branch with its delay slot unfilled, set `nullify'
4759 as it can nullify the delay slot and save a nop. */
4760 if (length == 8 && dbr_sequence_length () == 0)
4763 /* If this is a short forward conditional branch which did not get
4764 its delay slot filled, the delay slot can still be nullified. */
4765 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4766 nullify = forward_branch_p (insn);
4768 /* A forward branch over a single nullified insn can be done with a
4769 extrs instruction. This avoids a single cycle penalty due to
4770 mis-predicted branch if we fall through (branch not taken). */
4773 && next_real_insn (insn) != 0
4774 && get_attr_length (next_real_insn (insn)) == 4
4775 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4782 /* All short conditional branches except backwards with an unfilled
4786 strcpy (buf, "vextrs,");
4788 strcpy (buf, "bvb,");
4789 if ((which == 0 && negated)
4790 || (which == 1 && ! negated))
4795 strcat (buf, " %0,1,%%r0");
4796 else if (nullify && negated)
4797 strcat (buf, ",n %0,%3");
4798 else if (nullify && ! negated)
4799 strcat (buf, ",n %0,%2");
4800 else if (! nullify && negated)
4801 strcat (buf, "%0,%3");
4802 else if (! nullify && ! negated)
4803 strcat (buf, " %0,%2");
4806 /* All long conditionals. Note an short backward branch with an
4807 unfilled delay slot is treated just like a long backward branch
4808 with an unfilled delay slot. */
4810 /* Handle weird backwards branch with a filled delay slot
4811 with is nullified. */
4812 if (dbr_sequence_length () != 0
4813 && ! forward_branch_p (insn)
4816 strcpy (buf, "bvb,");
4817 if ((which == 0 && negated)
4818 || (which == 1 && ! negated))
4823 strcat (buf, ",n %0,.+12\n\tb %3");
4825 strcat (buf, ",n %0,.+12\n\tb %2");
4827 /* Handle short backwards branch with an unfilled delay slot.
4828 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4829 taken and untaken branches. */
4830 else if (dbr_sequence_length () == 0
4831 && ! forward_branch_p (insn)
4833 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4834 - insn_addresses[INSN_UID (insn)] - 8))
4836 strcpy (buf, "bvb,");
4837 if ((which == 0 && negated)
4838 || (which == 1 && ! negated))
4843 strcat (buf, " %0,%3%#");
4845 strcat (buf, " %0,%2%#");
4849 strcpy (buf, "vextrs,");
4850 if ((which == 0 && negated)
4851 || (which == 1 && ! negated))
4855 if (nullify && negated)
4856 strcat (buf, " %0,1,%%r0\n\tbn %3");
4857 else if (nullify && ! negated)
4858 strcat (buf, " %0,1,%%r0\n\tbn %2");
4860 strcat (buf, " %0,1,%%r0\n\tb %3");
4862 strcat (buf, " %0,1,%%r0\n\tb %2");
4872 /* Return the output template for emitting a dbra type insn.
4874 Note it may perform some output operations on its own before
4875 returning the final output string. */
4877 output_dbra (operands, insn, which_alternative)
4880 int which_alternative;
4883 /* A conditional branch to the following instruction (eg the delay slot) is
4884 asking for a disaster. Be prepared! */
4886 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4888 if (which_alternative == 0)
4889 return "ldo %1(%0),%0";
4890 else if (which_alternative == 1)
4892 output_asm_insn ("fstws %0,-16(%%r30)",operands);
4893 output_asm_insn ("ldw -16(%%r30),%4",operands);
4894 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
4895 return "fldws -16(%%r30),%0";
4899 output_asm_insn ("ldw %0,%4", operands);
4900 return "ldo %1(%4),%4\n\tstw %4,%0";
4904 if (which_alternative == 0)
4906 int nullify = INSN_ANNULLED_BRANCH_P (insn);
4907 int length = get_attr_length (insn);
4909 /* If this is a long branch with its delay slot unfilled, set `nullify'
4910 as it can nullify the delay slot and save a nop. */
4911 if (length == 8 && dbr_sequence_length () == 0)
4914 /* If this is a short forward conditional branch which did not get
4915 its delay slot filled, the delay slot can still be nullified. */
4916 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4917 nullify = forward_branch_p (insn);
4919 /* Handle short versions first. */
4920 if (length == 4 && nullify)
4921 return "addib,%C2,n %1,%0,%3";
4922 else if (length == 4 && ! nullify)
4923 return "addib,%C2 %1,%0,%3";
4924 else if (length == 8)
4926 /* Handle weird backwards branch with a fulled delay slot
4927 which is nullified. */
4928 if (dbr_sequence_length () != 0
4929 && ! forward_branch_p (insn)
4931 return "addib,%N2,n %1,%0,.+12\n\tb %3";
4932 /* Handle short backwards branch with an unfilled delay slot.
4933 Using a addb;nop rather than addi;bl saves 1 cycle for both
4934 taken and untaken branches. */
4935 else if (dbr_sequence_length () == 0
4936 && ! forward_branch_p (insn)
4938 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4939 - insn_addresses[INSN_UID (insn)] - 8))
4940 return "addib,%C2 %1,%0,%3%#";
4942 /* Handle normal cases. */
4944 return "addi,%N2 %1,%0,%0\n\tb,n %3";
4946 return "addi,%N2 %1,%0,%0\n\tb %3";
4951 /* Deal with gross reload from FP register case. */
4952 else if (which_alternative == 1)
4954 /* Move loop counter from FP register to MEM then into a GR,
4955 increment the GR, store the GR into MEM, and finally reload
4956 the FP register from MEM from within the branch's delay slot. */
4957 output_asm_insn ("fstws %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands);
4958 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
4959 if (get_attr_length (insn) == 24)
4960 return "comb,%S2 %%r0,%4,%3\n\tfldws -16(%%r30),%0";
4962 return "comclr,%B2 %%r0,%4,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
4964 /* Deal with gross reload from memory case. */
4967 /* Reload loop counter from memory, the store back to memory
4968 happens in the branch's delay slot. */
4969 output_asm_insn ("ldw %0,%4", operands);
4970 if (get_attr_length (insn) == 12)
4971 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
4973 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
4977 /* Return the output template for emitting a dbra type insn.
4979 Note it may perform some output operations on its own before
4980 returning the final output string. */
4982 output_movb (operands, insn, which_alternative, reverse_comparison)
4985 int which_alternative;
4986 int reverse_comparison;
4989 /* A conditional branch to the following instruction (eg the delay slot) is
4990 asking for a disaster. Be prepared! */
4992 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4994 if (which_alternative == 0)
4995 return "copy %1,%0";
4996 else if (which_alternative == 1)
4998 output_asm_insn ("stw %1,-16(%%r30)",operands);
4999 return "fldws -16(%%r30),%0";
5001 else if (which_alternative == 2)
5007 /* Support the second variant. */
5008 if (reverse_comparison)
5009 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5011 if (which_alternative == 0)
5013 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5014 int length = get_attr_length (insn);
5016 /* If this is a long branch with its delay slot unfilled, set `nullify'
5017 as it can nullify the delay slot and save a nop. */
5018 if (length == 8 && dbr_sequence_length () == 0)
5021 /* If this is a short forward conditional branch which did not get
5022 its delay slot filled, the delay slot can still be nullified. */
5023 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5024 nullify = forward_branch_p (insn);
5026 /* Handle short versions first. */
5027 if (length == 4 && nullify)
5028 return "movb,%C2,n %1,%0,%3";
5029 else if (length == 4 && ! nullify)
5030 return "movb,%C2 %1,%0,%3";
5031 else if (length == 8)
5033 /* Handle weird backwards branch with a filled delay slot
5034 which is nullified. */
5035 if (dbr_sequence_length () != 0
5036 && ! forward_branch_p (insn)
5038 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5040 /* Handle short backwards branch with an unfilled delay slot.
5041 Using a movb;nop rather than or;bl saves 1 cycle for both
5042 taken and untaken branches. */
5043 else if (dbr_sequence_length () == 0
5044 && ! forward_branch_p (insn)
5046 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
5047 - insn_addresses[INSN_UID (insn)] - 8))
5048 return "movb,%C2 %1,%0,%3%#";
5049 /* Handle normal cases. */
5051 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5053 return "or,%N2 %1,%%r0,%0\n\tb %3";
5058 /* Deal with gross reload from FP register case. */
5059 else if (which_alternative == 1)
5061 /* Move loop counter from FP register to MEM then into a GR,
5062 increment the GR, store the GR into MEM, and finally reload
5063 the FP register from MEM from within the branch's delay slot. */
5064 output_asm_insn ("stw %1,-16(%%r30)",operands);
5065 if (get_attr_length (insn) == 12)
5066 return "comb,%S2 %%r0,%1,%3\n\tfldws -16(%%r30),%0";
5068 return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
5070 /* Deal with gross reload from memory case. */
5071 else if (which_alternative == 2)
5073 /* Reload loop counter from memory, the store back to memory
5074 happens in the branch's delay slot. */
5075 if (get_attr_length (insn) == 8)
5076 return "comb,%S2 %%r0,%1,%3\n\tstw %1,%0";
5078 return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5080 /* Handle SAR as a destination. */
5083 if (get_attr_length (insn) == 8)
5084 return "comb,%S2 %%r0,%1,%3\n\tmtsar %r1";
5086 return "comclr,%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5091 /* INSN is a millicode call. It may have an unconditional jump in its delay
5094 CALL_DEST is the routine we are calling. */
5097 output_millicode_call (insn, call_dest)
5105 /* Handle common case -- empty delay slot or no jump in the delay slot,
5106 and we're sure that the branch will reach the beginning of the $CODE$
5108 if ((dbr_sequence_length () == 0
5109 && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
5110 || (dbr_sequence_length () != 0
5111 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5112 && get_attr_length (insn) == 4))
5114 xoperands[0] = call_dest;
5115 output_asm_insn ("bl %0,%%r31%#", xoperands);
5119 /* This call may not reach the beginning of the $CODE$ subspace. */
5120 if (get_attr_length (insn) > 4)
5122 int delay_insn_deleted = 0;
5125 /* We need to emit an inline long-call branch. */
5126 if (dbr_sequence_length () != 0
5127 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5129 /* A non-jump insn in the delay slot. By definition we can
5130 emit this insn before the call. */
5131 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5133 /* Now delete the delay insn. */
5134 PUT_CODE (NEXT_INSN (insn), NOTE);
5135 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5136 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5137 delay_insn_deleted = 1;
5140 /* If we're allowed to use be/ble instructions, then this is the
5141 best sequence to use for a long millicode call. */
5142 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS
5143 || ! (flag_pic || TARGET_PORTABLE_RUNTIME))
5145 xoperands[0] = call_dest;
5146 output_asm_insn ("ldil L%%%0,%%r31", xoperands);
5147 output_asm_insn ("ble R%%%0(%%sr4,%%r31)", xoperands);
5148 output_asm_insn ("nop", xoperands);
5150 /* Pure portable runtime doesn't allow be/ble; we also don't have
5151 PIC support int he assembler/linker, so this sequence is needed. */
5152 else if (TARGET_PORTABLE_RUNTIME)
5154 xoperands[0] = call_dest;
5155 /* Get the address of our target into %r29. */
5156 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
5157 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
5159 /* Get our return address into %r31. */
5160 output_asm_insn ("blr %%r0,%%r31", xoperands);
5162 /* Jump to our target address in %r29. */
5163 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
5165 /* Empty delay slot. Note this insn gets fetched twice and
5166 executed once. To be safe we use a nop. */
5167 output_asm_insn ("nop", xoperands);
5170 /* PIC long millicode call sequence. */
5173 xoperands[0] = call_dest;
5174 xoperands[1] = gen_label_rtx ();
5175 /* Get our address + 8 into %r1. */
5176 output_asm_insn ("bl .+8,%%r1", xoperands);
5178 /* Add %r1 to the offset of our target from the next insn. */
5179 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
5180 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5181 CODE_LABEL_NUMBER (xoperands[1]));
5182 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
5184 /* Get the return address into %r31. */
5185 output_asm_insn ("blr 0,%%r31", xoperands);
5187 /* Branch to our target which is in %r1. */
5188 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
5190 /* Empty delay slot. Note this insn gets fetched twice and
5191 executed once. To be safe we use a nop. */
5192 output_asm_insn ("nop", xoperands);
5195 /* If we had a jump in the call's delay slot, output it now. */
5196 if (dbr_sequence_length () != 0
5197 && !delay_insn_deleted)
5199 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5200 output_asm_insn ("b,n %0", xoperands);
5202 /* Now delete the delay insn. */
5203 PUT_CODE (NEXT_INSN (insn), NOTE);
5204 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5205 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5210 /* This call has an unconditional jump in its delay slot and the
5211 call is known to reach its target or the beginning of the current
5214 /* Use the containing sequence insn's address. */
5215 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5217 distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
5218 - insn_addresses[INSN_UID (seq_insn)] - 8;
5220 /* If the branch was too far away, emit a normal call followed
5221 by a nop, followed by the unconditional branch.
5223 If the branch is close, then adjust %r2 from within the
5224 call's delay slot. */
5226 xoperands[0] = call_dest;
5227 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5228 if (! VAL_14_BITS_P (distance))
5229 output_asm_insn ("bl %0,%%r31\n\tnop\n\tbl,n %1,%%r0", xoperands);
5232 xoperands[3] = gen_label_rtx ();
5233 output_asm_insn ("\n\tbl %0,%%r31\n\tldo %1-%3(%%r31),%%r31", xoperands);
5234 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5235 CODE_LABEL_NUMBER (xoperands[3]));
5238 /* Delete the jump. */
5239 PUT_CODE (NEXT_INSN (insn), NOTE);
5240 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5241 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5245 extern struct obstack permanent_obstack;
5246 extern struct obstack *saveable_obstack;
5247 extern struct obstack *rtl_obstack;
5248 extern struct obstack *current_obstack;
5250 /* INSN is either a function call. It may have an unconditional jump
5253 CALL_DEST is the routine we are calling. */
5256 output_call (insn, call_dest)
5264 /* Handle common case -- empty delay slot or no jump in the delay slot,
5265 and we're sure that the branch will reach the beginning of the $CODE$
5267 if ((dbr_sequence_length () == 0
5268 && get_attr_length (insn) == 8)
5269 || (dbr_sequence_length () != 0
5270 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5271 && get_attr_length (insn) == 4))
5273 xoperands[0] = call_dest;
5274 output_asm_insn ("bl %0,%%r2%#", xoperands);
5278 /* This call may not reach the beginning of the $CODE$ subspace. */
5279 if (get_attr_length (insn) > 8)
5281 int delay_insn_deleted = 0;
5285 /* We need to emit an inline long-call branch. Furthermore,
5286 because we're changing a named function call into an indirect
5287 function call well after the parameters have been set up, we
5288 need to make sure any FP args appear in both the integer
5289 and FP registers. Also, we need move any delay slot insn
5290 out of the delay slot. And finally, we can't rely on the linker
5291 being able to fix the call to $$dyncall! -- Yuk!. */
5292 if (dbr_sequence_length () != 0
5293 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5295 /* A non-jump insn in the delay slot. By definition we can
5296 emit this insn before the call (and in fact before argument
5298 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5300 /* Now delete the delay insn. */
5301 PUT_CODE (NEXT_INSN (insn), NOTE);
5302 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5303 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5304 delay_insn_deleted = 1;
5307 /* Now copy any FP arguments into integer registers. */
5308 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
5310 int arg_mode, regno;
5311 rtx use = XEXP (link, 0);
5312 if (! (GET_CODE (use) == USE
5313 && GET_CODE (XEXP (use, 0)) == REG
5314 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5317 arg_mode = GET_MODE (XEXP (use, 0));
5318 regno = REGNO (XEXP (use, 0));
5319 /* Is it a floating point register? */
5320 if (regno >= 32 && regno <= 39)
5322 /* Copy from the FP register into an integer register
5324 if (arg_mode == SFmode)
5326 xoperands[0] = XEXP (use, 0);
5327 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
5328 output_asm_insn ("fstws %0,-16(%%sr0,%%r30)", xoperands);
5329 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5333 xoperands[0] = XEXP (use, 0);
5334 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
5335 output_asm_insn ("fstds %0,-16(%%sr0,%%r30)", xoperands);
5336 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
5337 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5342 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5343 we don't have any direct calls in that case. */
5346 char *name = XSTR (call_dest, 0);
5348 /* See if we have already put this function on the list
5349 of deferred plabels. This list is generally small,
5350 so a liner search is not too ugly. If it proves too
5351 slow replace it with something faster. */
5352 for (i = 0; i < n_deferred_plabels; i++)
5353 if (strcmp (name, deferred_plabels[i].name) == 0)
5356 /* If the deferred plabel list is empty, or this entry was
5357 not found on the list, create a new entry on the list. */
5358 if (deferred_plabels == NULL || i == n_deferred_plabels)
5360 struct obstack *ambient_obstack = current_obstack;
5361 struct obstack *ambient_rtl_obstack = rtl_obstack;
5364 /* Any RTL we create here needs to live until the end of
5365 the compilation unit and therefore must live on the
5366 permanent obstack. */
5367 current_obstack = &permanent_obstack;
5368 rtl_obstack = &permanent_obstack;
5370 if (deferred_plabels == 0)
5371 deferred_plabels = (struct deferred_plabel *)
5372 xmalloc (1 * sizeof (struct deferred_plabel));
5374 deferred_plabels = (struct deferred_plabel *)
5375 xrealloc (deferred_plabels,
5376 ((n_deferred_plabels + 1)
5377 * sizeof (struct deferred_plabel)));
5379 i = n_deferred_plabels++;
5380 deferred_plabels[i].internal_label = gen_label_rtx ();
5381 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
5383 strcpy (deferred_plabels[i].name, name);
5385 /* Switch back to normal obstack allocation. */
5386 current_obstack = ambient_obstack;
5387 rtl_obstack = ambient_rtl_obstack;
5389 /* Gross. We have just implicitly taken the address of this
5390 function, mark it as such. */
5391 STRIP_NAME_ENCODING (real_name, name);
5392 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5395 /* We have to load the address of the function using a procedure
5396 label (plabel). Inline plabels can lose for PIC and other
5397 cases, so avoid them by creating a 32bit plabel in the data
5401 xoperands[0] = deferred_plabels[i].internal_label;
5402 xoperands[1] = gen_label_rtx ();
5404 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
5405 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
5406 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
5408 /* Get our address + 8 into %r1. */
5409 output_asm_insn ("bl .+8,%%r1", xoperands);
5411 /* Add %r1 to the offset of dyncall from the next insn. */
5412 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
5413 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5414 CODE_LABEL_NUMBER (xoperands[1]));
5415 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
5417 /* Get the return address into %r31. */
5418 output_asm_insn ("blr %%r0,%%r31", xoperands);
5420 /* Branch to our target which is in %r1. */
5421 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5423 /* Copy the return address into %r2 also. */
5424 output_asm_insn ("copy %%r31,%%r2", xoperands);
5428 xoperands[0] = deferred_plabels[i].internal_label;
5430 /* Get the address of our target into %r22. */
5431 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
5432 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
5434 /* Get the high part of the address of $dyncall into %r2, then
5435 add in the low part in the branch instruction. */
5436 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
5437 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands);
5439 /* Copy the return pointer into both %r31 and %r2. */
5440 output_asm_insn ("copy %%r31,%%r2", xoperands);
5444 /* If we had a jump in the call's delay slot, output it now. */
5445 if (dbr_sequence_length () != 0
5446 && !delay_insn_deleted)
5448 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5449 output_asm_insn ("b,n %0", xoperands);
5451 /* Now delete the delay insn. */
5452 PUT_CODE (NEXT_INSN (insn), NOTE);
5453 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5454 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5459 /* This call has an unconditional jump in its delay slot and the
5460 call is known to reach its target or the beginning of the current
5463 /* Use the containing sequence insn's address. */
5464 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5466 distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
5467 - insn_addresses[INSN_UID (seq_insn)] - 8;
5469 /* If the branch was too far away, emit a normal call followed
5470 by a nop, followed by the unconditional branch.
5472 If the branch is close, then adjust %r2 from within the
5473 call's delay slot. */
5475 xoperands[0] = call_dest;
5476 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5477 if (! VAL_14_BITS_P (distance))
5478 output_asm_insn ("bl %0,%%r2\n\tnop\n\tbl,n %1,%%r0", xoperands);
5481 xoperands[3] = gen_label_rtx ();
5482 output_asm_insn ("\n\tbl %0,%%r2\n\tldo %1-%3(%%r2),%%r2", xoperands);
5483 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5484 CODE_LABEL_NUMBER (xoperands[3]));
5487 /* Delete the jump. */
5488 PUT_CODE (NEXT_INSN (insn), NOTE);
5489 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5490 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5494 /* In HPUX 8.0's shared library scheme, special relocations are needed
5495 for function labels if they might be passed to a function
5496 in a shared library (because shared libraries don't live in code
5497 space), and special magic is needed to construct their address.
5499 For reasons too disgusting to describe storage for the new name
5500 is allocated either on the saveable_obstack (released at function
5501 exit) or on the permanent_obstack for things that can never change
5502 (libcall names for example). */
5505 hppa_encode_label (sym, permanent)
5509 char *str = XSTR (sym, 0);
5510 int len = strlen (str);
5513 newstr = obstack_alloc ((permanent ? &permanent_obstack : saveable_obstack),
5518 strcpy (newstr + 1, str);
5520 XSTR (sym,0) = newstr;
5524 function_label_operand (op, mode)
5526 enum machine_mode mode ATTRIBUTE_UNUSED;
5528 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
5531 /* Returns 1 if OP is a function label involved in a simple addition
5532 with a constant. Used to keep certain patterns from matching
5533 during instruction combination. */
5535 is_function_label_plus_const (op)
5538 /* Strip off any CONST. */
5539 if (GET_CODE (op) == CONST)
5542 return (GET_CODE (op) == PLUS
5543 && function_label_operand (XEXP (op, 0), Pmode)
5544 && GET_CODE (XEXP (op, 1)) == CONST_INT);
5547 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5548 use in fmpyadd instructions. */
5550 fmpyaddoperands (operands)
5553 enum machine_mode mode = GET_MODE (operands[0]);
5555 /* Must be a floating point mode. */
5556 if (mode != SFmode && mode != DFmode)
5559 /* All modes must be the same. */
5560 if (! (mode == GET_MODE (operands[1])
5561 && mode == GET_MODE (operands[2])
5562 && mode == GET_MODE (operands[3])
5563 && mode == GET_MODE (operands[4])
5564 && mode == GET_MODE (operands[5])))
5567 /* All operands must be registers. */
5568 if (! (GET_CODE (operands[1]) == REG
5569 && GET_CODE (operands[2]) == REG
5570 && GET_CODE (operands[3]) == REG
5571 && GET_CODE (operands[4]) == REG
5572 && GET_CODE (operands[5]) == REG))
5575 /* Only 2 real operands to the addition. One of the input operands must
5576 be the same as the output operand. */
5577 if (! rtx_equal_p (operands[3], operands[4])
5578 && ! rtx_equal_p (operands[3], operands[5]))
5581 /* Inout operand of add can not conflict with any operands from multiply. */
5582 if (rtx_equal_p (operands[3], operands[0])
5583 || rtx_equal_p (operands[3], operands[1])
5584 || rtx_equal_p (operands[3], operands[2]))
5587 /* multiply can not feed into addition operands. */
5588 if (rtx_equal_p (operands[4], operands[0])
5589 || rtx_equal_p (operands[5], operands[0]))
5592 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5594 && (REGNO (operands[0]) < 57
5595 || REGNO (operands[1]) < 57
5596 || REGNO (operands[2]) < 57
5597 || REGNO (operands[3]) < 57
5598 || REGNO (operands[4]) < 57
5599 || REGNO (operands[5]) < 57))
5602 /* Passed. Operands are suitable for fmpyadd. */
5606 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5607 use in fmpysub instructions. */
5609 fmpysuboperands (operands)
5612 enum machine_mode mode = GET_MODE (operands[0]);
5614 /* Must be a floating point mode. */
5615 if (mode != SFmode && mode != DFmode)
5618 /* All modes must be the same. */
5619 if (! (mode == GET_MODE (operands[1])
5620 && mode == GET_MODE (operands[2])
5621 && mode == GET_MODE (operands[3])
5622 && mode == GET_MODE (operands[4])
5623 && mode == GET_MODE (operands[5])))
5626 /* All operands must be registers. */
5627 if (! (GET_CODE (operands[1]) == REG
5628 && GET_CODE (operands[2]) == REG
5629 && GET_CODE (operands[3]) == REG
5630 && GET_CODE (operands[4]) == REG
5631 && GET_CODE (operands[5]) == REG))
5634 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
5635 operation, so operands[4] must be the same as operand[3]. */
5636 if (! rtx_equal_p (operands[3], operands[4]))
5639 /* multiply can not feed into subtraction. */
5640 if (rtx_equal_p (operands[5], operands[0]))
5643 /* Inout operand of sub can not conflict with any operands from multiply. */
5644 if (rtx_equal_p (operands[3], operands[0])
5645 || rtx_equal_p (operands[3], operands[1])
5646 || rtx_equal_p (operands[3], operands[2]))
5649 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5651 && (REGNO (operands[0]) < 57
5652 || REGNO (operands[1]) < 57
5653 || REGNO (operands[2]) < 57
5654 || REGNO (operands[3]) < 57
5655 || REGNO (operands[4]) < 57
5656 || REGNO (operands[5]) < 57))
5659 /* Passed. Operands are suitable for fmpysub. */
5664 plus_xor_ior_operator (op, mode)
5666 enum machine_mode mode ATTRIBUTE_UNUSED;
5668 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
5669 || GET_CODE (op) == IOR);
5672 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
5673 constants for shadd instructions. */
5675 shadd_constant_p (val)
5678 if (val == 2 || val == 4 || val == 8)
5684 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
5685 the valid constant for shadd instructions. */
5687 shadd_operand (op, mode)
5689 enum machine_mode mode ATTRIBUTE_UNUSED;
5691 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
5694 /* Return 1 if OP is valid as a base register in a reg + reg address. */
5697 basereg_operand (op, mode)
5699 enum machine_mode mode;
5701 /* cse will create some unscaled indexed addresses, however; it
5702 generally isn't a win on the PA, so avoid creating unscaled
5703 indexed addresses until after cse is finished. */
5704 if (!cse_not_expected)
5707 /* Once reload has started everything is considered valid. Reload should
5708 only create indexed addresses using the stack/frame pointer, and any
5709 others were checked for validity when created by the combine pass.
5711 Also allow any register when TARGET_NO_SPACE_REGS is in effect since
5712 we don't have to worry about the braindamaged implicit space register
5713 selection using the basereg only (rather than effective address)
5714 screwing us over. */
5715 if (TARGET_NO_SPACE_REGS || reload_in_progress || reload_completed)
5716 return (GET_CODE (op) == REG);
5718 /* Stack is always OK for indexing. */
5719 if (op == stack_pointer_rtx)
5722 /* While it's always safe to index off the frame pointer, it's not
5723 always profitable, particularly when the frame pointer is being
5725 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
5728 /* The only other valid OPs are pseudo registers with
5729 REGNO_POINTER_FLAG set. */
5730 if (GET_CODE (op) != REG
5731 || REGNO (op) < FIRST_PSEUDO_REGISTER
5732 || ! register_operand (op, mode))
5735 return REGNO_POINTER_FLAG (REGNO (op));
5738 /* Return 1 if this operand is anything other than a hard register. */
5741 non_hard_reg_operand (op, mode)
5743 enum machine_mode mode ATTRIBUTE_UNUSED;
5745 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
5748 /* Return 1 if INSN branches forward. Should be using insn_addresses
5749 to avoid walking through all the insns... */
5751 forward_branch_p (insn)
5754 rtx label = JUMP_LABEL (insn);
5761 insn = NEXT_INSN (insn);
5764 return (insn == label);
5767 /* Return 1 if OP is an equality comparison, else return 0. */
5769 eq_neq_comparison_operator (op, mode)
5771 enum machine_mode mode ATTRIBUTE_UNUSED;
5773 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
5776 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
5778 movb_comparison_operator (op, mode)
5780 enum machine_mode mode ATTRIBUTE_UNUSED;
5782 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
5783 || GET_CODE (op) == LT || GET_CODE (op) == GE);
5786 /* Return 1 if INSN is in the delay slot of a call instruction. */
5788 jump_in_call_delay (insn)
5792 if (GET_CODE (insn) != JUMP_INSN)
5795 if (PREV_INSN (insn)
5796 && PREV_INSN (PREV_INSN (insn))
5797 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
5799 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
5801 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
5802 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
5809 /* Output an unconditional move and branch insn. */
5812 output_parallel_movb (operands, length)
5816 /* These are the cases in which we win. */
5818 return "mov%I1b,tr %1,%0,%2";
5820 /* None of these cases wins, but they don't lose either. */
5821 if (dbr_sequence_length () == 0)
5823 /* Nothing in the delay slot, fake it by putting the combined
5824 insn (the copy or add) in the delay slot of a bl. */
5825 if (GET_CODE (operands[1]) == CONST_INT)
5826 return "b %2\n\tldi %1,%0";
5828 return "b %2\n\tcopy %1,%0";
5832 /* Something in the delay slot, but we've got a long branch. */
5833 if (GET_CODE (operands[1]) == CONST_INT)
5834 return "ldi %1,%0\n\tb %2";
5836 return "copy %1,%0\n\tb %2";
5840 /* Output an unconditional add and branch insn. */
5843 output_parallel_addb (operands, length)
5847 /* To make life easy we want operand0 to be the shared input/output
5848 operand and operand1 to be the readonly operand. */
5849 if (operands[0] == operands[1])
5850 operands[1] = operands[2];
5852 /* These are the cases in which we win. */
5854 return "add%I1b,tr %1,%0,%3";
5856 /* None of these cases win, but they don't lose either. */
5857 if (dbr_sequence_length () == 0)
5859 /* Nothing in the delay slot, fake it by putting the combined
5860 insn (the copy or add) in the delay slot of a bl. */
5861 return "b %3\n\tadd%I1 %1,%0,%0";
5865 /* Something in the delay slot, but we've got a long branch. */
5866 return "add%I1 %1,%0,%0\n\tb %3";
5870 /* Return nonzero if INSN (a jump insn) immediately follows a call to
5871 a named function. This is used to discourage creating parallel movb/addb
5872 insns since a jump which immediately follows a call can execute in the
5873 delay slot of the call.
5875 It is also used to avoid filling the delay slot of a jump which
5876 immediately follows a call since the jump can usually be eliminated
5877 completely by modifying RP in the delay slot of the call. */
5880 following_call (insn)
5883 /* Find the previous real insn, skipping NOTEs. */
5884 insn = PREV_INSN (insn);
5885 while (insn && GET_CODE (insn) == NOTE)
5886 insn = PREV_INSN (insn);
5888 /* Check for CALL_INSNs and millicode calls. */
5890 && ((GET_CODE (insn) == CALL_INSN
5891 && get_attr_type (insn) != TYPE_DYNCALL)
5892 || (GET_CODE (insn) == INSN
5893 && GET_CODE (PATTERN (insn)) != SEQUENCE
5894 && GET_CODE (PATTERN (insn)) != USE
5895 && GET_CODE (PATTERN (insn)) != CLOBBER
5896 && get_attr_type (insn) == TYPE_MILLI)))
5902 /* Restore any INSN_CODEs for insns with unscaled indexed addresses since
5903 the INSN_CODE might be clobberd by rerecognition triggered by reorg. */
5906 restore_unscaled_index_insn_codes (insns)
5911 for (insn = insns; insn; insn = NEXT_INSN (insn))
5913 if (INSN_UID (insn) < max_unscaled_index_insn_codes_uid
5914 && unscaled_index_insn_codes[INSN_UID (insn)] != -1)
5915 INSN_CODE (insn) = unscaled_index_insn_codes[INSN_UID (insn)];
5919 /* Severe braindamage:
5921 On the PA, address computations within MEM expressions are not
5922 commutative because of the implicit space register selection
5923 from the base register (instead of the entire effective address).
5925 Because of this mis-feature we have to know which register in a reg+reg
5926 address is the base and which is the index.
5928 Before reload, the base can be identified by REGNO_POINTER_FLAG. We use
5929 this to force base + index addresses to match a different insn than
5930 index + base addresses.
5932 We assume that no pass during or after reload creates new unscaled indexed
5933 addresses, so any unscaled indexed address we find after reload must have
5934 at one time been recognized a base + index or index + base and we accept
5935 any register as a base register.
5937 This scheme assumes that no pass during/after reload will rerecognize an
5938 insn with an unscaled indexed address. This failed due to a reorg call
5939 to rerecognize certain insns.
5941 So, we record if an insn uses an unscaled indexed address and which
5942 register is the base (via recording of the INSN_CODE for such insns).
5944 Just before we output code for the function, we make sure all the insns
5945 using unscaled indexed addresses have the same INSN_CODE as they did
5946 immediately before delay slot scheduling.
5948 This is extremely gross. Long term, I'd like to be able to look at
5949 REG_POINTER_FLAG to handle these kinds of problems. */
5952 record_unscaled_index_insn_codes (insns)
5957 max_unscaled_index_insn_codes_uid = get_max_uid ();
5958 unscaled_index_insn_codes
5959 = (int *)xmalloc (max_unscaled_index_insn_codes_uid * sizeof (int));
5960 memset (unscaled_index_insn_codes, -1,
5961 max_unscaled_index_insn_codes_uid * sizeof (int));
5963 for (insn = insns; insn; insn = NEXT_INSN (insn))
5965 rtx set = single_set (insn);
5968 /* Ignore anything that isn't a normal SET. */
5969 if (set == NULL_RTX)
5972 /* No insns can have more than one MEM. */
5973 if (GET_CODE (SET_SRC (set)) == MEM)
5974 mem = SET_SRC (set);
5976 if (GET_CODE (SET_DEST (set)) == MEM)
5977 mem = SET_DEST (set);
5979 /* If neither operand is a mem, then there's nothing to do. */
5980 if (mem == NULL_RTX)
5983 if (GET_CODE (XEXP (mem, 0)) != PLUS)
5986 /* If both are REGs (or SUBREGs), then record the insn code for
5988 if (REG_P (XEXP (XEXP (mem, 0), 0)) && REG_P (XEXP (XEXP (mem, 0), 1)))
5989 unscaled_index_insn_codes[INSN_UID (insn)] = INSN_CODE (insn);
5993 /* We use this hook to perform a PA specific optimization which is difficult
5994 to do in earlier passes.
5996 We want the delay slots of branches within jump tables to be filled.
5997 None of the compiler passes at the moment even has the notion that a
5998 PA jump table doesn't contain addresses, but instead contains actual
6001 Because we actually jump into the table, the addresses of each entry
6002 must stay constant in relation to the beginning of the table (which
6003 itself must stay constant relative to the instruction to jump into
6004 it). I don't believe we can guarantee earlier passes of the compiler
6005 will adhere to those rules.
6007 So, late in the compilation process we find all the jump tables, and
6008 expand them into real code -- eg each entry in the jump table vector
6009 will get an appropriate label followed by a jump to the final target.
6011 Reorg and the final jump pass can then optimize these branches and
6012 fill their delay slots. We end up with smaller, more efficient code.
6014 The jump instructions within the table are special; we must be able
6015 to identify them during assembly output (if the jumps don't get filled
6016 we need to emit a nop rather than nullifying the delay slot)). We
6017 identify jumps in switch tables by marking the SET with DImode.
6019 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6020 insns. This serves two purposes, first it prevents jump.c from
6021 noticing that the last N entries in the table jump to the instruction
6022 immediately after the table and deleting the jumps. Second, those
6023 insns mark where we should emit .begin_brtab and .end_brtab directives
6024 when using GAS (allows for better link time optimizations). */
6032 /* Keep track of which insns have unscaled indexed addresses, and which
6033 register is the base address in such insns. */
6034 record_unscaled_index_insn_codes (insns);
6036 remove_useless_addtr_insns (insns, 1);
6038 if (pa_cpu < PROCESSOR_8000)
6039 pa_combine_instructions (get_insns ());
6042 /* This is fairly cheap, so always run it if optimizing. */
6043 if (optimize > 0 && !TARGET_BIG_SWITCH)
6045 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6046 insns = get_insns ();
6047 for (insn = insns; insn; insn = NEXT_INSN (insn))
6049 rtx pattern, tmp, location;
6050 unsigned int length, i;
6052 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6053 if (GET_CODE (insn) != JUMP_INSN
6054 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6055 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6058 /* Emit marker for the beginning of the branch table. */
6059 emit_insn_before (gen_begin_brtab (), insn);
6061 pattern = PATTERN (insn);
6062 location = PREV_INSN (insn);
6063 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6065 for (i = 0; i < length; i++)
6067 /* Emit a label before each jump to keep jump.c from
6068 removing this code. */
6069 tmp = gen_label_rtx ();
6070 LABEL_NUSES (tmp) = 1;
6071 emit_label_after (tmp, location);
6072 location = NEXT_INSN (location);
6074 if (GET_CODE (pattern) == ADDR_VEC)
6076 /* Emit the jump itself. */
6077 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
6078 tmp = emit_jump_insn_after (tmp, location);
6079 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
6080 /* It is easy to rely on the branch table markers
6081 during assembly output to trigger the correct code
6082 for a switch table jump with an unfilled delay slot,
6084 However, that requires state and assumes that we look
6087 We can't make such assumptions when computing the length
6088 of instructions. Ugh. We could walk the insn chain to
6089 determine if this instruction is in a branch table, but
6090 that can get rather expensive, particularly during the
6091 branch shortening phase of the compiler.
6093 So instead we mark this jump as being special. This is
6094 far from ideal and knows that no code after this will
6095 muck around with the mode of the JUMP_INSN itself. */
6096 PUT_MODE (tmp, SImode);
6097 LABEL_NUSES (JUMP_LABEL (tmp))++;
6098 location = NEXT_INSN (location);
6102 /* Emit the jump itself. */
6103 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
6104 tmp = emit_jump_insn_after (tmp, location);
6105 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
6106 /* It is easy to rely on the branch table markers
6107 during assembly output to trigger the correct code
6108 for a switch table jump with an unfilled delay slot,
6110 However, that requires state and assumes that we look
6113 We can't make such assumptions when computing the length
6114 of instructions. Ugh. We could walk the insn chain to
6115 determine if this instruction is in a branch table, but
6116 that can get rather expensive, particularly during the
6117 branch shortening phase of the compiler.
6119 So instead we mark this jump as being special. This is
6120 far from ideal and knows that no code after this will
6121 muck around with the mode of the JUMP_INSN itself. */
6122 PUT_MODE (tmp, SImode);
6123 LABEL_NUSES (JUMP_LABEL (tmp))++;
6124 location = NEXT_INSN (location);
6127 /* Emit a BARRIER after the jump. */
6128 emit_barrier_after (location);
6129 location = NEXT_INSN (location);
6132 /* Emit marker for the end of the branch table. */
6133 emit_insn_before (gen_end_brtab (), location);
6134 location = NEXT_INSN (location);
6135 emit_barrier_after (location);
6137 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6143 /* Sill need an end_brtab insn. */
6144 insns = get_insns ();
6145 for (insn = insns; insn; insn = NEXT_INSN (insn))
6147 /* Find an ADDR_VEC insn. */
6148 if (GET_CODE (insn) != JUMP_INSN
6149 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6150 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6153 /* Now generate markers for the beginning and end of the
6155 emit_insn_before (gen_begin_brtab (), insn);
6156 emit_insn_after (gen_end_brtab (), insn);
6161 /* The PA has a number of odd instructions which can perform multiple
6162 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6163 it may be profitable to combine two instructions into one instruction
6164 with two outputs. It's not profitable PA2.0 machines because the
6165 two outputs would take two slots in the reorder buffers.
6167 This routine finds instructions which can be combined and combines
6168 them. We only support some of the potential combinations, and we
6169 only try common ways to find suitable instructions.
6171 * addb can add two registers or a register and a small integer
6172 and jump to a nearby (+-8k) location. Normally the jump to the
6173 nearby location is conditional on the result of the add, but by
6174 using the "true" condition we can make the jump unconditional.
6175 Thus addb can perform two independent operations in one insn.
6177 * movb is similar to addb in that it can perform a reg->reg
6178 or small immediate->reg copy and jump to a nearby (+-8k location).
6180 * fmpyadd and fmpysub can perform a FP multiply and either an
6181 FP add or FP sub if the operands of the multiply and add/sub are
6182 independent (there are other minor restrictions). Note both
6183 the fmpy and fadd/fsub can in theory move to better spots according
6184 to data dependencies, but for now we require the fmpy stay at a
6187 * Many of the memory operations can perform pre & post updates
6188 of index registers. GCC's pre/post increment/decrement addressing
6189 is far too simple to take advantage of all the possibilities. This
6190 pass may not be suitable since those insns may not be independent.
6192 * comclr can compare two ints or an int and a register, nullify
6193 the following instruction and zero some other register. This
6194 is more difficult to use as it's harder to find an insn which
6195 will generate a comclr than finding something like an unconditional
6196 branch. (conditional moves & long branches create comclr insns).
6198 * Most arithmetic operations can conditionally skip the next
6199 instruction. They can be viewed as "perform this operation
6200 and conditionally jump to this nearby location" (where nearby
6201 is an insns away). These are difficult to use due to the
6202 branch length restrictions. */
6205 pa_combine_instructions (insns)
6206 rtx insns ATTRIBUTE_UNUSED;
6210 /* This can get expensive since the basic algorithm is on the
6211 order of O(n^2) (or worse). Only do it for -O2 or higher
6212 levels of optimization. */
6216 /* Walk down the list of insns looking for "anchor" insns which
6217 may be combined with "floating" insns. As the name implies,
6218 "anchor" instructions don't move, while "floating" insns may
6220 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
6221 new = make_insn_raw (new);
6223 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
6225 enum attr_pa_combine_type anchor_attr;
6226 enum attr_pa_combine_type floater_attr;
6228 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6229 Also ignore any special USE insns. */
6230 if ((GET_CODE (anchor) != INSN
6231 && GET_CODE (anchor) != JUMP_INSN
6232 && GET_CODE (anchor) != CALL_INSN)
6233 || GET_CODE (PATTERN (anchor)) == USE
6234 || GET_CODE (PATTERN (anchor)) == CLOBBER
6235 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
6236 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
6239 anchor_attr = get_attr_pa_combine_type (anchor);
6240 /* See if anchor is an insn suitable for combination. */
6241 if (anchor_attr == PA_COMBINE_TYPE_FMPY
6242 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
6243 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6244 && ! forward_branch_p (anchor)))
6248 for (floater = PREV_INSN (anchor);
6250 floater = PREV_INSN (floater))
6252 if (GET_CODE (floater) == NOTE
6253 || (GET_CODE (floater) == INSN
6254 && (GET_CODE (PATTERN (floater)) == USE
6255 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6258 /* Anything except a regular INSN will stop our search. */
6259 if (GET_CODE (floater) != INSN
6260 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6261 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6267 /* See if FLOATER is suitable for combination with the
6269 floater_attr = get_attr_pa_combine_type (floater);
6270 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6271 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6272 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6273 && floater_attr == PA_COMBINE_TYPE_FMPY))
6275 /* If ANCHOR and FLOATER can be combined, then we're
6276 done with this pass. */
6277 if (pa_can_combine_p (new, anchor, floater, 0,
6278 SET_DEST (PATTERN (floater)),
6279 XEXP (SET_SRC (PATTERN (floater)), 0),
6280 XEXP (SET_SRC (PATTERN (floater)), 1)))
6284 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6285 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
6287 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
6289 if (pa_can_combine_p (new, anchor, floater, 0,
6290 SET_DEST (PATTERN (floater)),
6291 XEXP (SET_SRC (PATTERN (floater)), 0),
6292 XEXP (SET_SRC (PATTERN (floater)), 1)))
6297 if (pa_can_combine_p (new, anchor, floater, 0,
6298 SET_DEST (PATTERN (floater)),
6299 SET_SRC (PATTERN (floater)),
6300 SET_SRC (PATTERN (floater))))
6306 /* If we didn't find anything on the backwards scan try forwards. */
6308 && (anchor_attr == PA_COMBINE_TYPE_FMPY
6309 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
6311 for (floater = anchor; floater; floater = NEXT_INSN (floater))
6313 if (GET_CODE (floater) == NOTE
6314 || (GET_CODE (floater) == INSN
6315 && (GET_CODE (PATTERN (floater)) == USE
6316 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6320 /* Anything except a regular INSN will stop our search. */
6321 if (GET_CODE (floater) != INSN
6322 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6323 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6329 /* See if FLOATER is suitable for combination with the
6331 floater_attr = get_attr_pa_combine_type (floater);
6332 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6333 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6334 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6335 && floater_attr == PA_COMBINE_TYPE_FMPY))
6337 /* If ANCHOR and FLOATER can be combined, then we're
6338 done with this pass. */
6339 if (pa_can_combine_p (new, anchor, floater, 1,
6340 SET_DEST (PATTERN (floater)),
6341 XEXP (SET_SRC (PATTERN(floater)),0),
6342 XEXP(SET_SRC(PATTERN(floater)),1)))
6348 /* FLOATER will be nonzero if we found a suitable floating
6349 insn for combination with ANCHOR. */
6351 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6352 || anchor_attr == PA_COMBINE_TYPE_FMPY))
6354 /* Emit the new instruction and delete the old anchor. */
6355 emit_insn_before (gen_rtx_PARALLEL (VOIDmode,
6358 PATTERN (floater))),
6360 PUT_CODE (anchor, NOTE);
6361 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6362 NOTE_SOURCE_FILE (anchor) = 0;
6364 /* Emit a special USE insn for FLOATER, then delete
6365 the floating insn. */
6366 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6367 delete_insn (floater);
6372 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
6375 /* Emit the new_jump instruction and delete the old anchor. */
6376 temp = emit_jump_insn_before (gen_rtx_PARALLEL (VOIDmode,
6377 gen_rtvec (2, PATTERN (anchor),
6378 PATTERN (floater))),
6380 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
6381 PUT_CODE (anchor, NOTE);
6382 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6383 NOTE_SOURCE_FILE (anchor) = 0;
6385 /* Emit a special USE insn for FLOATER, then delete
6386 the floating insn. */
6387 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6388 delete_insn (floater);
6396 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
6397 rtx new, anchor, floater;
6399 rtx dest, src1, src2;
6401 int insn_code_number;
6404 /* Create a PARALLEL with the patterns of ANCHOR and
6405 FLOATER, try to recognize it, then test constraints
6406 for the resulting pattern.
6408 If the pattern doesn't match or the constraints
6409 aren't met keep searching for a suitable floater
6411 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
6412 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
6413 INSN_CODE (new) = -1;
6414 insn_code_number = recog_memoized (new);
6415 if (insn_code_number < 0
6416 || !constrain_operands (insn_code_number, 1))
6430 /* There's up to three operands to consider. One
6431 output and two inputs.
6433 The output must not be used between FLOATER & ANCHOR
6434 exclusive. The inputs must not be set between
6435 FLOATER and ANCHOR exclusive. */
6437 if (reg_used_between_p (dest, start, end))
6440 if (reg_set_between_p (src1, start, end))
6443 if (reg_set_between_p (src2, start, end))
6446 /* If we get here, then everything is good. */
6450 /* Return nonzero if sets and references for INSN are delayed.
6452 Millicode insns are actually function calls with some special
6453 constraints on arguments and register usage.
6455 Millicode calls always expect their arguments in the integer argument
6456 registers, and always return their result in %r29 (ret1). They
6457 are expected to clobber their arguments, %r1, %r29, and %r31 and
6460 By considering this effects delayed reorg reorg can put insns
6461 which set the argument registers into the delay slot of the millicode
6462 call -- thus they act more like traditional CALL_INSNs.
6464 get_attr_type will try to recognize the given insn, so make sure to
6465 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
6468 insn_sets_and_refs_are_delayed (insn)
6471 return ((GET_CODE (insn) == INSN
6472 && GET_CODE (PATTERN (insn)) != SEQUENCE
6473 && GET_CODE (PATTERN (insn)) != USE
6474 && GET_CODE (PATTERN (insn)) != CLOBBER
6475 && get_attr_type (insn) == TYPE_MILLI));