1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
39 /* Save the operands last given to a compare for use when we
40 generate a scc or bcc insn. */
42 rtx hppa_compare_op0, hppa_compare_op1;
43 enum cmp_type hppa_branch_type;
45 /* Which cpu we are scheduling for. */
46 enum processor_type pa_cpu;
48 /* String to hold which cpu we are scheduling for. */
51 /* Set by the FUNCTION_PROFILER macro. */
52 int hp_profile_labelno;
54 /* Counts for the number of callee-saved general and floating point
55 registers which were saved by the current function's prologue. */
56 static int gr_saved, fr_saved;
58 /* Whether or not the current function uses an out-of-line prologue
60 static int out_of_line_prologue_epilogue;
62 static rtx find_addr_reg ();
64 /* Kludgery. We hold the operands to a fmpy insn here so we can
65 compare them with the operands for an fadd/fsub to determine if
66 they can be combined into a fmpyadd/fmpysub insn.
68 This _WILL_ disappear as the code to combine independent insns
70 static rtx fmpy_operands[3];
72 /* Keep track of the number of bytes we have output in the CODE subspaces
73 during this compilation so we'll know when to emit inline long-calls. */
75 unsigned int total_code_bytes;
77 /* Variables to handle plabels that we discover are necessary at assembly
78 output time. They are output after the current function. */
84 } *deferred_plabels = 0;
85 int n_deferred_plabels = 0;
90 /* Default to 7100 scheduling. If the 7100LC scheduling ever
91 gets reasonably tuned, it should be the default since that
92 what most PAs sold now are. */
93 if (pa_cpu_string == NULL
94 || ! strcmp (pa_cpu_string, "7100"))
96 pa_cpu_string = "7100";
97 pa_cpu = PROCESSOR_7100;
99 else if (! strcmp (pa_cpu_string, "700"))
101 pa_cpu_string = "700";
102 pa_cpu = PROCESSOR_700;
104 else if (! strcmp (pa_cpu_string, "7100LC"))
106 pa_cpu_string = "7100LC";
107 pa_cpu = PROCESSOR_7100LC;
111 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100 and 7100LC\n", pa_cpu_string);
114 if (flag_pic && TARGET_PORTABLE_RUNTIME)
116 warning ("PIC code generation is not supported in the portable runtime model\n");
119 if (flag_pic && (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS))
121 warning ("PIC code generation is not compatable with fast indirect calls\n");
124 if (flag_pic && profile_flag)
126 warning ("PIC code generation is not compatable with profiling\n");
129 if (TARGET_SPACE && (flag_pic || profile_flag))
131 warning ("Out of line entry/exit sequences are not compatable\n");
132 warning ("with PIC or profiling\n");
135 if (! TARGET_GAS && write_symbols != NO_DEBUG)
137 warning ("-g is only supported when using GAS on this processor,");
138 warning ("-g option disabled.");
139 write_symbols = NO_DEBUG;
144 /* Return non-zero only if OP is a register of mode MODE,
147 reg_or_0_operand (op, mode)
149 enum machine_mode mode;
151 return (op == CONST0_RTX (mode) || register_operand (op, mode));
154 /* Return non-zero if OP is suitable for use in a call to a named
157 (???) For 2.5 try to eliminate either call_operand_address or
158 function_label_operand, they perform very similar functions. */
160 call_operand_address (op, mode)
162 enum machine_mode mode;
164 return (CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
167 /* Return 1 if X contains a symbolic expression. We know these
168 expressions will have one of a few well defined forms, so
169 we need only check those forms. */
171 symbolic_expression_p (x)
175 /* Strip off any HIGH. */
176 if (GET_CODE (x) == HIGH)
179 return (symbolic_operand (x, VOIDmode));
183 symbolic_operand (op, mode)
185 enum machine_mode mode;
187 switch (GET_CODE (op))
194 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
195 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
196 && GET_CODE (XEXP (op, 1)) == CONST_INT);
202 /* Return truth value of statement that OP is a symbolic memory
203 operand of mode MODE. */
206 symbolic_memory_operand (op, mode)
208 enum machine_mode mode;
210 if (GET_CODE (op) == SUBREG)
211 op = SUBREG_REG (op);
212 if (GET_CODE (op) != MEM)
215 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
216 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
219 /* Return 1 if the operand is either a register or a memory operand that is
223 reg_or_nonsymb_mem_operand (op, mode)
225 enum machine_mode mode;
227 if (register_operand (op, mode))
230 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
236 /* Return 1 if the operand is either a register, zero, or a memory operand
237 that is not symbolic. */
240 reg_or_0_or_nonsymb_mem_operand (op, mode)
242 enum machine_mode mode;
244 if (register_operand (op, mode))
247 if (op == CONST0_RTX (mode))
250 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
256 /* Accept any constant that can be moved in one instructions into a
259 cint_ok_for_move (intval)
260 HOST_WIDE_INT intval;
262 /* OK if ldo, ldil, or zdepi, can be used. */
263 return (VAL_14_BITS_P (intval) || (intval & 0x7ff) == 0
264 || zdepi_cint_p (intval));
267 /* Accept anything that can be moved in one instruction into a general
270 move_operand (op, mode)
272 enum machine_mode mode;
274 if (register_operand (op, mode))
277 if (GET_CODE (op) == CONST_INT)
278 return cint_ok_for_move (INTVAL (op));
280 if (GET_CODE (op) == SUBREG)
281 op = SUBREG_REG (op);
282 if (GET_CODE (op) != MEM)
286 if (GET_CODE (op) == LO_SUM)
287 return (register_operand (XEXP (op, 0), Pmode)
288 && CONSTANT_P (XEXP (op, 1)));
290 /* Since move_operand is only used for source operands, we can always
291 allow scaled indexing! */
292 if (GET_CODE (op) == PLUS
293 && ((GET_CODE (XEXP (op, 0)) == MULT
294 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
295 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
296 && INTVAL (XEXP (XEXP (op, 0), 1)) == GET_MODE_SIZE (mode)
297 && GET_CODE (XEXP (op, 1)) == REG)
298 || (GET_CODE (XEXP (op, 1)) == MULT
299 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
300 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
301 && INTVAL (XEXP (XEXP (op, 1), 1)) == GET_MODE_SIZE (mode)
302 && GET_CODE (XEXP (op, 0)) == REG)))
305 return memory_address_p (mode, op);
308 /* Accept REG and any CONST_INT that can be moved in one instruction into a
311 reg_or_cint_move_operand (op, mode)
313 enum machine_mode mode;
315 if (register_operand (op, mode))
318 if (GET_CODE (op) == CONST_INT)
319 return cint_ok_for_move (INTVAL (op));
325 pic_label_operand (op, mode)
327 enum machine_mode mode;
332 switch (GET_CODE (op))
338 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
339 && GET_CODE (XEXP (op, 1)) == CONST_INT);
346 fp_reg_operand (op, mode)
348 enum machine_mode mode;
350 return reg_renumber && FP_REG_P (op);
355 /* Return truth value of whether OP can be used as an operand in a
356 three operand arithmetic insn that accepts registers of mode MODE
357 or 14-bit signed integers. */
359 arith_operand (op, mode)
361 enum machine_mode mode;
363 return (register_operand (op, mode)
364 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
367 /* Return truth value of whether OP can be used as an operand in a
368 three operand arithmetic insn that accepts registers of mode MODE
369 or 11-bit signed integers. */
371 arith11_operand (op, mode)
373 enum machine_mode mode;
375 return (register_operand (op, mode)
376 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
379 /* A constant integer suitable for use in a PRE_MODIFY memory
382 pre_cint_operand (op, mode)
384 enum machine_mode mode;
386 return (GET_CODE (op) == CONST_INT
387 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
390 /* A constant integer suitable for use in a POST_MODIFY memory
393 post_cint_operand (op, mode)
395 enum machine_mode mode;
397 return (GET_CODE (op) == CONST_INT
398 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
402 arith_double_operand (op, mode)
404 enum machine_mode mode;
406 return (register_operand (op, mode)
407 || (GET_CODE (op) == CONST_DOUBLE
408 && GET_MODE (op) == mode
409 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
410 && (CONST_DOUBLE_HIGH (op) >= 0
411 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
414 /* Return truth value of whether OP is a integer which fits the
415 range constraining immediate operands in three-address insns, or
416 is an integer register. */
419 ireg_or_int5_operand (op, mode)
421 enum machine_mode mode;
423 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
424 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
427 /* Return truth value of whether OP is a integer which fits the
428 range constraining immediate operands in three-address insns. */
431 int5_operand (op, mode)
433 enum machine_mode mode;
435 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
439 uint5_operand (op, mode)
441 enum machine_mode mode;
443 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
447 int11_operand (op, mode)
449 enum machine_mode mode;
451 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
455 uint32_operand (op, mode)
457 enum machine_mode mode;
459 #if HOST_BITS_PER_WIDE_INT > 32
460 /* All allowed constants will fit a CONST_INT. */
461 return (GET_CODE (op) == CONST_INT
462 && (INTVAL (op) >= 0 && INTVAL (op) < 0x100000000L));
464 return (GET_CODE (op) == CONST_INT
465 || (GET_CODE (op) == CONST_DOUBLE
466 && CONST_DOUBLE_HIGH (op) == 0));
471 arith5_operand (op, mode)
473 enum machine_mode mode;
475 return register_operand (op, mode) || int5_operand (op, mode);
478 /* True iff zdepi can be used to generate this CONST_INT. */
481 unsigned HOST_WIDE_INT x;
483 unsigned HOST_WIDE_INT lsb_mask, t;
485 /* This might not be obvious, but it's at least fast.
486 This function is critical; we don't have the time loops would take. */
488 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
489 /* Return true iff t is a power of two. */
490 return ((t & (t - 1)) == 0);
493 /* True iff depi or extru can be used to compute (reg & mask).
494 Accept bit pattern like these:
500 unsigned HOST_WIDE_INT mask;
503 mask += mask & -mask;
504 return (mask & (mask - 1)) == 0;
507 /* True iff depi or extru can be used to compute (reg & OP). */
509 and_operand (op, mode)
511 enum machine_mode mode;
513 return (register_operand (op, mode)
514 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
517 /* True iff depi can be used to compute (reg | MASK). */
520 unsigned HOST_WIDE_INT mask;
522 mask += mask & -mask;
523 return (mask & (mask - 1)) == 0;
526 /* True iff depi can be used to compute (reg | OP). */
528 ior_operand (op, mode)
530 enum machine_mode mode;
532 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
536 lhs_lshift_operand (op, mode)
538 enum machine_mode mode;
540 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
543 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
544 Such values can be the left hand side x in (x << r), using the zvdepi
547 lhs_lshift_cint_operand (op, mode)
549 enum machine_mode mode;
551 unsigned HOST_WIDE_INT x;
552 if (GET_CODE (op) != CONST_INT)
554 x = INTVAL (op) >> 4;
555 return (x & (x + 1)) == 0;
559 arith32_operand (op, mode)
561 enum machine_mode mode;
563 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
567 pc_or_label_operand (op, mode)
569 enum machine_mode mode;
571 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
574 /* Legitimize PIC addresses. If the address is already
575 position-independent, we return ORIG. Newly generated
576 position-independent addresses go to REG. If we need more
577 than one register, we lose. */
580 legitimize_pic_address (orig, mode, reg)
582 enum machine_mode mode;
586 /* Labels need special handling. */
587 if (pic_label_operand (orig))
589 emit_insn (gen_pic_load_label (reg, orig));
590 current_function_uses_pic_offset_table = 1;
593 if (GET_CODE (orig) == SYMBOL_REF)
600 emit_insn (gen_pic2_highpart (reg, pic_offset_table_rtx, orig));
601 pic_ref = gen_rtx (MEM, Pmode,
602 gen_rtx (LO_SUM, Pmode, reg,
603 gen_rtx (UNSPEC, SImode, gen_rtvec (1, orig), 0)));
606 pic_ref = gen_rtx (MEM, Pmode,
607 gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig));
608 current_function_uses_pic_offset_table = 1;
609 RTX_UNCHANGING_P (pic_ref) = 1;
610 emit_move_insn (reg, pic_ref);
613 else if (GET_CODE (orig) == CONST)
617 if (GET_CODE (XEXP (orig, 0)) == PLUS
618 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
624 if (GET_CODE (XEXP (orig, 0)) == PLUS)
626 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
627 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
628 base == reg ? 0 : reg);
631 if (GET_CODE (orig) == CONST_INT)
633 if (INT_14_BITS (orig))
634 return plus_constant_for_output (base, INTVAL (orig));
635 orig = force_reg (Pmode, orig);
637 pic_ref = gen_rtx (PLUS, Pmode, base, orig);
638 /* Likewise, should we set special REG_NOTEs here? */
643 /* Try machine-dependent ways of modifying an illegitimate address
644 to be legitimate. If we find one, return the new, valid address.
645 This macro is used in only one place: `memory_address' in explow.c.
647 OLDX is the address as it was before break_out_memory_refs was called.
648 In some cases it is useful to look at this to decide what needs to be done.
650 MODE and WIN are passed so that this macro can use
651 GO_IF_LEGITIMATE_ADDRESS.
653 It is always safe for this macro to do nothing. It exists to recognize
654 opportunities to optimize the output.
656 For the PA, transform:
658 memory(X + <large int>)
662 if (<large int> & mask) >= 16
663 Y = (<large int> & ~mask) + mask + 1 Round up.
665 Y = (<large int> & ~mask) Round down.
667 memory (Z + (<large int> - Y));
669 This is for CSE to find several similar references, and only use one Z.
671 X can either be a SYMBOL_REF or REG, but because combine can not
672 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
673 D will not fit in 14 bits.
675 MODE_FLOAT references allow displacements which fit in 5 bits, so use
678 MODE_INT references allow displacements which fit in 14 bits, so use
681 This relies on the fact that most mode MODE_FLOAT references will use FP
682 registers and most mode MODE_INT references will use integer registers.
683 (In the rare case of an FP register used in an integer MODE, we depend
684 on secondary reloads to clean things up.)
687 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
688 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
689 addressing modes to be used).
691 Put X and Z into registers. Then put the entire expression into
695 hppa_legitimize_address (x, oldx, mode)
697 enum machine_mode mode;
702 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
704 /* Strip off CONST. */
705 if (GET_CODE (x) == CONST)
708 /* Special case. Get the SYMBOL_REF into a register and use indexing.
709 That should always be safe. */
710 if (GET_CODE (x) == PLUS
711 && GET_CODE (XEXP (x, 0)) == REG
712 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
714 rtx reg = force_reg (SImode, XEXP (x, 1));
715 return force_reg (SImode, gen_rtx (PLUS, SImode, reg, XEXP (x, 0)));
718 /* Note we must reject symbols which represent function addresses
719 since the assembler/linker can't handle arithmetic on plabels. */
720 if (GET_CODE (x) == PLUS
721 && GET_CODE (XEXP (x, 1)) == CONST_INT
722 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
723 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
724 || GET_CODE (XEXP (x, 0)) == REG))
726 rtx int_part, ptr_reg;
728 int offset = INTVAL (XEXP (x, 1));
729 int mask = GET_MODE_CLASS (mode) == MODE_FLOAT ? 0x1f : 0x3fff;
731 /* Choose which way to round the offset. Round up if we
732 are >= halfway to the next boundary. */
733 if ((offset & mask) >= ((mask + 1) / 2))
734 newoffset = (offset & ~ mask) + mask + 1;
736 newoffset = (offset & ~ mask);
738 /* If the newoffset will not fit in 14 bits (ldo), then
739 handling this would take 4 or 5 instructions (2 to load
740 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
741 add the new offset and the SYMBOL_REF.) Combine can
742 not handle 4->2 or 5->2 combinations, so do not create
744 if (! VAL_14_BITS_P (newoffset)
745 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
747 rtx const_part = gen_rtx (CONST, VOIDmode,
748 gen_rtx (PLUS, Pmode,
750 GEN_INT (newoffset)));
753 gen_rtx (HIGH, Pmode, const_part));
756 gen_rtx (LO_SUM, Pmode,
757 tmp_reg, const_part));
761 if (! VAL_14_BITS_P (newoffset))
762 int_part = force_reg (Pmode, GEN_INT (newoffset));
764 int_part = GEN_INT (newoffset);
766 ptr_reg = force_reg (Pmode,
767 gen_rtx (PLUS, Pmode,
768 force_reg (Pmode, XEXP (x, 0)),
771 return plus_constant (ptr_reg, offset - newoffset);
774 /* Try to arrange things so that indexing modes can be used, but
775 only do so if indexing is safe.
777 Indexing is safe when the second operand for the outer PLUS
778 is a REG, SUBREG, SYMBOL_REF or the like. */
780 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
781 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
782 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
783 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
784 || GET_CODE (XEXP (x, 1)) == SUBREG)
785 && GET_CODE (XEXP (x, 1)) != CONST)
787 int val = INTVAL (XEXP (XEXP (x, 0), 1));
789 reg1 = force_reg (Pmode, force_operand (XEXP (x, 1), 0));
790 reg2 = force_reg (Pmode,
791 force_operand (XEXP (XEXP (x, 0), 0), 0));
792 return force_reg (Pmode,
793 gen_rtx (PLUS, Pmode,
794 gen_rtx (MULT, Pmode, reg2,
799 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
801 Only do so for floating point modes since this is more speculative
802 and we lose if it's an integer store. */
803 if ((mode == DFmode || mode == SFmode)
804 && GET_CODE (x) == PLUS
805 && GET_CODE (XEXP (x, 0)) == PLUS
806 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
807 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
808 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))))
812 /* Add the two unscaled terms B and C; if either B or C isn't
813 a register or small constant int, then fail. */
814 regx1 = XEXP (XEXP (x, 0), 1);
815 if (! (GET_CODE (regx1) == REG
816 || (GET_CODE (regx1) == CONST_INT
817 && INT_14_BITS (regx1))))
821 if (! (GET_CODE (regx2) == REG
822 || (GET_CODE (regx2) == CONST_INT
823 && INT_14_BITS (regx2))))
826 /* Add them, make sure the result is in canonical form. */
827 if (GET_CODE (regx1) == REG)
828 regx1 = force_reg (Pmode, gen_rtx (PLUS, Pmode, regx1, regx2));
829 else if (GET_CODE (regx2) == REG)
830 regx1 = force_reg (Pmode, gen_rtx (PLUS, Pmode, regx2, regx1));
832 regx1 = force_reg (Pmode, gen_rtx (PLUS, Pmode,
833 force_reg (Pmode, regx1),
836 /* Get the term to scale in a register. */
837 regx2 = XEXP (XEXP (XEXP (x, 0), 0), 0);
838 if (GET_CODE (regx2) != REG)
839 regx2 = force_reg (Pmode, force_operand (regx2, 0));
841 /* And make an indexed address. */
842 regx2 = gen_rtx (PLUS, Pmode,
843 gen_rtx (MULT, Pmode, regx2,
844 XEXP (XEXP (XEXP (x, 0), 0), 1)),
848 return force_reg (Pmode, regx2);
851 /* Uh-oh. We might have an address for x[n-100000]. This needs
852 special handling to avoid creating an indexed memory address
853 with x-100000 as the base.
855 If the constant part is small enough, then it's still safe because
856 there is a guard page at the beginning and end of the data segment.
858 Scaled references are common enough that we want to try and rearrange the
859 terms so that we can use indexing for these addresses too. Only
860 do the optimization for floatint point modes. */
862 if (GET_CODE (x) == PLUS
863 && symbolic_expression_p (XEXP (x, 1)))
865 /* Ugly. We modify things here so that the address offset specified
866 by the index expression is computed first, then added to x to form
867 the entire address. */
869 rtx regx1, regx2, regy1, regy2, y;
871 /* Strip off any CONST. */
873 if (GET_CODE (y) == CONST)
876 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
878 /* See if this looks like
879 (plus (mult (reg) (shadd_const))
880 (const (plus (symbol_ref) (const_int))))
882 Where const_int can be divided evenly by shadd_const and
883 added to (reg). This allows more scaled indexed addresses. */
884 if ((mode == DFmode || mode == SFmode)
885 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
886 && GET_CODE (XEXP (y, 1)) == CONST_INT
887 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0)
890 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
891 / INTVAL (XEXP (XEXP (x, 0), 1))));
892 regx2 = XEXP (XEXP (x, 0), 0);
893 if (GET_CODE (regx2) != REG)
894 regx2 = force_reg (Pmode, force_operand (regx2, 0));
895 regx2 = force_reg (Pmode, gen_rtx (GET_CODE (y), Pmode,
897 return force_reg (Pmode,
898 gen_rtx (PLUS, Pmode,
899 gen_rtx (MULT, Pmode, regx2,
900 XEXP (XEXP (x, 0), 1)),
901 force_reg (Pmode, XEXP (y, 0))));
903 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
904 && INTVAL (XEXP (y, 1)) >= -4096
905 && INTVAL (XEXP (y, 1)) <= 4095)
907 /* This is safe because of the guard page at the
908 beginning and end of the data space. Just
909 return the original address. */
914 /* Doesn't look like one we can optimize. */
915 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
916 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
917 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
918 regx1 = force_reg (Pmode,
919 gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
920 return force_reg (Pmode, gen_rtx (PLUS, Pmode, regx1, regy1));
928 /* For the HPPA, REG and REG+CONST is cost 0
929 and addresses involving symbolic constants are cost 2.
931 PIC addresses are very expensive.
933 It is no coincidence that this has the same structure
934 as GO_IF_LEGITIMATE_ADDRESS. */
936 hppa_address_cost (X)
939 if (GET_CODE (X) == PLUS)
941 else if (GET_CODE (X) == LO_SUM)
943 else if (GET_CODE (X) == HIGH)
948 /* Emit insns to move operands[1] into operands[0].
950 Return 1 if we have written out everything that needs to be done to
951 do the move. Otherwise, return 0 and the caller will emit the move
955 emit_move_sequence (operands, mode, scratch_reg)
957 enum machine_mode mode;
960 register rtx operand0 = operands[0];
961 register rtx operand1 = operands[1];
963 /* Handle secondary reloads for loads/stores of FP registers from
964 REG+D addresses where D does not fit in 5 bits, including
965 (subreg (mem (addr))) cases. */
966 if (fp_reg_operand (operand0, mode)
967 && ((GET_CODE (operand1) == MEM
968 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
969 || ((GET_CODE (operand1) == SUBREG
970 && GET_CODE (XEXP (operand1, 0)) == MEM
971 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
974 if (GET_CODE (operand1) == SUBREG)
975 operand1 = XEXP (operand1, 0);
977 scratch_reg = gen_rtx (REG, SImode, REGNO (scratch_reg));
979 /* D might not fit in 14 bits either; for such cases load D into
981 if (!memory_address_p (SImode, XEXP (operand1, 0)))
983 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
984 emit_move_insn (scratch_reg, gen_rtx (GET_CODE (XEXP (operand1, 0)),
986 XEXP (XEXP (operand1, 0), 0),
990 emit_move_insn (scratch_reg, XEXP (operand1, 0));
991 emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (MEM, mode,
995 else if (fp_reg_operand (operand1, mode)
996 && ((GET_CODE (operand0) == MEM
997 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
998 || ((GET_CODE (operand0) == SUBREG)
999 && GET_CODE (XEXP (operand0, 0)) == MEM
1000 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1003 if (GET_CODE (operand0) == SUBREG)
1004 operand0 = XEXP (operand0, 0);
1006 scratch_reg = gen_rtx (REG, SImode, REGNO (scratch_reg));
1007 /* D might not fit in 14 bits either; for such cases load D into
1009 if (!memory_address_p (SImode, XEXP (operand0, 0)))
1011 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1012 emit_move_insn (scratch_reg, gen_rtx (GET_CODE (XEXP (operand0, 0)),
1014 XEXP (XEXP (operand0, 0), 0),
1018 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1019 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (MEM, mode, scratch_reg),
1023 /* Handle secondary reloads for loads of FP registers from constant
1024 expressions by forcing the constant into memory.
1026 use scratch_reg to hold the address of the memory location.
1028 ??? The proper fix is to change PREFERRED_RELOAD_CLASS to return
1029 NO_REGS when presented with a const_int and an register class
1030 containing only FP registers. Doing so unfortunately creates
1031 more problems than it solves. Fix this for 2.5. */
1032 else if (fp_reg_operand (operand0, mode)
1033 && CONSTANT_P (operand1)
1038 /* Force the constant into memory and put the address of the
1039 memory location into scratch_reg. */
1040 xoperands[0] = scratch_reg;
1041 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1042 emit_move_sequence (xoperands, Pmode, 0);
1044 /* Now load the destination register. */
1045 emit_insn (gen_rtx (SET, mode, operand0,
1046 gen_rtx (MEM, mode, scratch_reg)));
1049 /* Handle secondary reloads for SAR. These occur when trying to load
1050 the SAR from memory a FP register, or with a constant. */
1051 else if (GET_CODE (operand0) == REG
1052 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1053 && (GET_CODE (operand1) == MEM
1054 || GET_CODE (operand1) == CONST_INT
1055 || (GET_CODE (operand1) == REG
1056 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1059 emit_move_insn (scratch_reg, operand1);
1060 emit_move_insn (operand0, scratch_reg);
1063 /* Handle most common case: storing into a register. */
1064 else if (register_operand (operand0, mode))
1066 if (register_operand (operand1, mode)
1067 || (GET_CODE (operand1) == CONST_INT && INT_14_BITS (operand1))
1068 || (operand1 == CONST0_RTX (mode))
1069 || (GET_CODE (operand1) == HIGH
1070 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1071 /* Only `general_operands' can come here, so MEM is ok. */
1072 || GET_CODE (operand1) == MEM)
1074 /* Run this case quickly. */
1075 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
1079 else if (GET_CODE (operand0) == MEM)
1081 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1083 /* Run this case quickly. */
1084 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
1087 if (! (reload_in_progress || reload_completed))
1089 operands[0] = validize_mem (operand0);
1090 operands[1] = operand1 = force_reg (mode, operand1);
1094 /* Simplify the source if we need to. */
1095 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1096 || (GET_CODE (operand1) == HIGH
1097 && symbolic_operand (XEXP (operand1, 0), mode)))
1101 if (GET_CODE (operand1) == HIGH)
1104 operand1 = XEXP (operand1, 0);
1106 if (symbolic_operand (operand1, mode))
1108 rtx const_part = NULL;
1110 /* Argh. The assembler and linker can't handle arithmetic
1111 involving plabels. We'll have to split up operand1 here
1112 if it's a function label involved in an arithmetic
1113 expression. Luckily, this only happens with addition
1114 of constants to plabels, which simplifies the test.
1116 We add the constant back in just before returning to
1118 if (GET_CODE (operand1) == CONST
1119 && GET_CODE (XEXP (operand1, 0)) == PLUS
1120 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1122 /* Save away the constant part of the expression. */
1123 const_part = XEXP (XEXP (operand1, 0), 1);
1124 if (GET_CODE (const_part) != CONST_INT)
1127 /* Set operand1 to just the SYMBOL_REF. */
1128 operand1 = XEXP (XEXP (operand1, 0), 0);
1135 if (reload_in_progress || reload_completed)
1136 temp = scratch_reg ? scratch_reg : operand0;
1138 temp = gen_reg_rtx (Pmode);
1140 /* If operand1 is a function label, then we've got to
1141 force it to memory, then load op0 from memory. */
1142 if (function_label_operand (operand1, mode))
1144 operands[1] = force_const_mem (mode, operand1);
1145 emit_move_sequence (operands, mode, temp);
1147 /* Likewise for (const (plus (symbol) (const_int))) when
1148 generating pic code during or after reload and const_int
1149 will not fit in 14 bits. */
1150 else if (GET_CODE (operand1) == CONST
1151 && GET_CODE (XEXP (operand1, 0)) == PLUS
1152 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1153 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1154 && (reload_completed || reload_in_progress)
1157 operands[1] = force_const_mem (mode, operand1);
1158 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1160 emit_move_sequence (operands, mode, temp);
1164 operands[1] = legitimize_pic_address (operand1, mode, temp);
1165 emit_insn (gen_rtx (SET, VOIDmode, operand0, operands[1]));
1168 /* On the HPPA, references to data space are supposed to use dp,
1169 register 27, but showing it in the RTL inhibits various cse
1170 and loop optimizations. */
1175 if (reload_in_progress || reload_completed)
1176 temp = scratch_reg ? scratch_reg : operand0;
1178 temp = gen_reg_rtx (mode);
1180 /* Loading a SYMBOL_REF into a register makes that register
1181 safe to be used as the base in an indexed address.
1183 Don't mark hard registers though. That loses. */
1184 if (GET_CODE (operand0) == REG
1185 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1186 REGNO_POINTER_FLAG (REGNO (operand0)) = 1;
1187 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1188 REGNO_POINTER_FLAG (REGNO (temp)) = 1;
1190 set = gen_rtx (SET, mode, operand0, temp);
1192 set = gen_rtx (SET, VOIDmode,
1194 gen_rtx (LO_SUM, mode, temp, operand1));
1196 emit_insn (gen_rtx (SET, VOIDmode,
1198 gen_rtx (HIGH, mode, operand1)));
1203 /* Add back in the constant part if needed. */
1204 if (const_part != NULL)
1205 expand_inc (operand0, const_part);
1208 else if (GET_CODE (operand1) != CONST_INT
1209 || ! cint_ok_for_move (INTVAL (operand1)))
1213 if (reload_in_progress || reload_completed)
1216 temp = gen_reg_rtx (mode);
1218 emit_insn (gen_rtx (SET, VOIDmode, temp,
1219 gen_rtx (HIGH, mode, operand1)));
1220 operands[1] = gen_rtx (LO_SUM, mode, temp, operand1);
1223 /* Now have insn-emit do whatever it normally does. */
1227 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1228 it will need a link/runtime reloc. */
1236 switch (TREE_CODE (exp))
1243 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1244 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1249 case NON_LVALUE_EXPR:
1250 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1256 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1257 if (TREE_VALUE (link) != 0)
1258 reloc |= reloc_needed (TREE_VALUE (link));
1268 /* Does operand (which is a symbolic_operand) live in text space? If
1269 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1272 read_only_operand (operand)
1275 if (GET_CODE (operand) == CONST)
1276 operand = XEXP (XEXP (operand, 0), 0);
1279 if (GET_CODE (operand) == SYMBOL_REF)
1280 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1284 if (GET_CODE (operand) == SYMBOL_REF)
1285 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1291 /* Return the best assembler insn template
1292 for moving operands[1] into operands[0] as a fullword. */
1294 singlemove_string (operands)
1297 HOST_WIDE_INT intval;
1299 if (GET_CODE (operands[0]) == MEM)
1300 return "stw %r1,%0";
1301 if (GET_CODE (operands[1]) == MEM)
1303 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1308 if (GET_MODE (operands[1]) != SFmode)
1311 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1313 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1314 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1316 operands[1] = GEN_INT (i);
1317 /* Fall through to CONST_INT case. */
1319 if (GET_CODE (operands[1]) == CONST_INT)
1321 intval = INTVAL (operands[1]);
1323 if (VAL_14_BITS_P (intval))
1325 else if ((intval & 0x7ff) == 0)
1326 return "ldil L'%1,%0";
1327 else if (zdepi_cint_p (intval))
1328 return "zdepi %Z1,%0";
1330 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1332 return "copy %1,%0";
1336 /* Compute position (in OP[1]) and width (in OP[2])
1337 useful for copying IMM to a register using the zdepi
1338 instructions. Store the immediate value to insert in OP[0]. */
1340 compute_zdepi_operands (imm, op)
1341 unsigned HOST_WIDE_INT imm;
1346 /* Find the least significant set bit in IMM. */
1347 for (lsb = 0; lsb < 32; lsb++)
1354 /* Choose variants based on *sign* of the 5-bit field. */
1355 if ((imm & 0x10) == 0)
1356 len = (lsb <= 28) ? 4 : 32 - lsb;
1359 /* Find the width of the bitstring in IMM. */
1360 for (len = 5; len < 32; len++)
1362 if ((imm & (1 << len)) == 0)
1366 /* Sign extend IMM as a 5-bit value. */
1367 imm = (imm & 0xf) - 0x10;
1375 /* Output assembler code to perform a doubleword move insn
1376 with operands OPERANDS. */
1379 output_move_double (operands)
1382 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1384 rtx addreg0 = 0, addreg1 = 0;
1386 /* First classify both operands. */
1388 if (REG_P (operands[0]))
1390 else if (offsettable_memref_p (operands[0]))
1392 else if (GET_CODE (operands[0]) == MEM)
1397 if (REG_P (operands[1]))
1399 else if (CONSTANT_P (operands[1]))
1401 else if (offsettable_memref_p (operands[1]))
1403 else if (GET_CODE (operands[1]) == MEM)
1408 /* Check for the cases that the operand constraints are not
1409 supposed to allow to happen. Abort if we get one,
1410 because generating code for these cases is painful. */
1412 if (optype0 != REGOP && optype1 != REGOP)
1415 /* Handle auto decrementing and incrementing loads and stores
1416 specifically, since the structure of the function doesn't work
1417 for them without major modification. Do it better when we learn
1418 this port about the general inc/dec addressing of PA.
1419 (This was written by tege. Chide him if it doesn't work.) */
1421 if (optype0 == MEMOP)
1423 /* We have to output the address syntax ourselves, since print_operand
1424 doesn't deal with the addresses we want to use. Fix this later. */
1426 rtx addr = XEXP (operands[0], 0);
1427 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1429 rtx high_reg = gen_rtx (SUBREG, SImode, operands[1], 0);
1431 operands[0] = XEXP (addr, 0);
1432 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1435 if (!reg_overlap_mentioned_p (high_reg, addr))
1437 /* No overlap between high target register and address
1438 register. (We do this in a non-obvious way to
1439 save a register file writeback) */
1440 if (GET_CODE (addr) == POST_INC)
1441 return "stws,ma %1,8(0,%0)\n\tstw %R1,-4(0,%0)";
1442 return "stws,ma %1,-8(0,%0)\n\tstw %R1,12(0,%0)";
1447 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1449 rtx high_reg = gen_rtx (SUBREG, SImode, operands[1], 0);
1451 operands[0] = XEXP (addr, 0);
1452 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1455 if (!reg_overlap_mentioned_p (high_reg, addr))
1457 /* No overlap between high target register and address
1458 register. (We do this in a non-obvious way to
1459 save a register file writeback) */
1460 if (GET_CODE (addr) == PRE_INC)
1461 return "stws,mb %1,8(0,%0)\n\tstw %R1,4(0,%0)";
1462 return "stws,mb %1,-8(0,%0)\n\tstw %R1,4(0,%0)";
1468 if (optype1 == MEMOP)
1470 /* We have to output the address syntax ourselves, since print_operand
1471 doesn't deal with the addresses we want to use. Fix this later. */
1473 rtx addr = XEXP (operands[1], 0);
1474 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1476 rtx high_reg = gen_rtx (SUBREG, SImode, operands[0], 0);
1478 operands[1] = XEXP (addr, 0);
1479 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1482 if (!reg_overlap_mentioned_p (high_reg, addr))
1484 /* No overlap between high target register and address
1485 register. (We do this in a non-obvious way to
1486 save a register file writeback) */
1487 if (GET_CODE (addr) == POST_INC)
1488 return "ldws,ma 8(0,%1),%0\n\tldw -4(0,%1),%R0";
1489 return "ldws,ma -8(0,%1),%0\n\tldw 12(0,%1),%R0";
1493 /* This is an undefined situation. We should load into the
1494 address register *and* update that register. Probably
1495 we don't need to handle this at all. */
1496 if (GET_CODE (addr) == POST_INC)
1497 return "ldw 4(0,%1),%R0\n\tldws,ma 8(0,%1),%0";
1498 return "ldw 4(0,%1),%R0\n\tldws,ma -8(0,%1),%0";
1501 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1503 rtx high_reg = gen_rtx (SUBREG, SImode, operands[0], 0);
1505 operands[1] = XEXP (addr, 0);
1506 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1509 if (!reg_overlap_mentioned_p (high_reg, addr))
1511 /* No overlap between high target register and address
1512 register. (We do this in a non-obvious way to
1513 save a register file writeback) */
1514 if (GET_CODE (addr) == PRE_INC)
1515 return "ldws,mb 8(0,%1),%0\n\tldw 4(0,%1),%R0";
1516 return "ldws,mb -8(0,%1),%0\n\tldw 4(0,%1),%R0";
1520 /* This is an undefined situation. We should load into the
1521 address register *and* update that register. Probably
1522 we don't need to handle this at all. */
1523 if (GET_CODE (addr) == PRE_INC)
1524 return "ldw 12(0,%1),%R0\n\tldws,mb 8(0,%1),%0";
1525 return "ldw -4(0,%1),%R0\n\tldws,mb -8(0,%1),%0";
1530 /* If an operand is an unoffsettable memory ref, find a register
1531 we can increment temporarily to make it refer to the second word. */
1533 if (optype0 == MEMOP)
1534 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1536 if (optype1 == MEMOP)
1537 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1539 /* Ok, we can do one word at a time.
1540 Normally we do the low-numbered word first.
1542 In either case, set up in LATEHALF the operands to use
1543 for the high-numbered word and in some cases alter the
1544 operands in OPERANDS to be suitable for the low-numbered word. */
1546 if (optype0 == REGOP)
1547 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1548 else if (optype0 == OFFSOP)
1549 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1551 latehalf[0] = operands[0];
1553 if (optype1 == REGOP)
1554 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1555 else if (optype1 == OFFSOP)
1556 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1557 else if (optype1 == CNSTOP)
1558 split_double (operands[1], &operands[1], &latehalf[1]);
1560 latehalf[1] = operands[1];
1562 /* If the first move would clobber the source of the second one,
1563 do them in the other order.
1565 This can happen in two cases:
1567 mem -> register where the first half of the destination register
1568 is the same register used in the memory's address. Reload
1569 can create such insns.
1571 mem in this case will be either register indirect or register
1572 indirect plus a valid offset.
1574 register -> register move where REGNO(dst) == REGNO(src + 1)
1575 someone (Tim/Tege?) claimed this can happen for parameter loads.
1577 Handle mem -> register case first. */
1578 if (optype0 == REGOP
1579 && (optype1 == MEMOP || optype1 == OFFSOP)
1580 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
1583 /* Do the late half first. */
1585 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1586 output_asm_insn (singlemove_string (latehalf), latehalf);
1590 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1591 return singlemove_string (operands);
1594 /* Now handle register -> register case. */
1595 if (optype0 == REGOP && optype1 == REGOP
1596 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1598 output_asm_insn (singlemove_string (latehalf), latehalf);
1599 return singlemove_string (operands);
1602 /* Normal case: do the two words, low-numbered first. */
1604 output_asm_insn (singlemove_string (operands), operands);
1606 /* Make any unoffsettable addresses point at high-numbered word. */
1608 output_asm_insn ("ldo 4(%0),%0", &addreg0);
1610 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1613 output_asm_insn (singlemove_string (latehalf), latehalf);
1615 /* Undo the adds we just did. */
1617 output_asm_insn ("ldo -4(%0),%0", &addreg0);
1619 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1625 output_fp_move_double (operands)
1628 if (FP_REG_P (operands[0]))
1630 if (FP_REG_P (operands[1])
1631 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1632 output_asm_insn ("fcpy,dbl %r1,%0", operands);
1634 output_asm_insn ("fldd%F1 %1,%0", operands);
1636 else if (FP_REG_P (operands[1]))
1638 output_asm_insn ("fstd%F0 %1,%0", operands);
1640 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1642 if (GET_CODE (operands[0]) == REG)
1645 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1646 xoperands[0] = operands[0];
1647 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
1649 /* This is a pain. You have to be prepared to deal with an
1650 arbitrary address here including pre/post increment/decrement.
1652 so avoid this in the MD. */
1660 /* Return a REG that occurs in ADDR with coefficient 1.
1661 ADDR can be effectively incremented by incrementing REG. */
1664 find_addr_reg (addr)
1667 while (GET_CODE (addr) == PLUS)
1669 if (GET_CODE (XEXP (addr, 0)) == REG)
1670 addr = XEXP (addr, 0);
1671 else if (GET_CODE (XEXP (addr, 1)) == REG)
1672 addr = XEXP (addr, 1);
1673 else if (CONSTANT_P (XEXP (addr, 0)))
1674 addr = XEXP (addr, 1);
1675 else if (CONSTANT_P (XEXP (addr, 1)))
1676 addr = XEXP (addr, 0);
1680 if (GET_CODE (addr) == REG)
1685 /* Emit code to perform a block move.
1687 OPERANDS[0] is the destination pointer as a REG, clobbered.
1688 OPERANDS[1] is the source pointer as a REG, clobbered.
1689 OPERANDS[2] is a register for temporary storage.
1690 OPERANDS[4] is the size as a CONST_INT
1691 OPERANDS[3] is a register for temporary storage.
1692 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
1693 OPERNADS[6] is another temporary register. */
1696 output_block_move (operands, size_is_constant)
1698 int size_is_constant;
1700 int align = INTVAL (operands[5]);
1701 unsigned long n_bytes = INTVAL (operands[4]);
1703 /* We can't move more than four bytes at a time because the PA
1704 has no longer integer move insns. (Could use fp mem ops?) */
1708 /* Note that we know each loop below will execute at least twice
1709 (else we would have open-coded the copy). */
1713 /* Pre-adjust the loop counter. */
1714 operands[4] = GEN_INT (n_bytes - 8);
1715 output_asm_insn ("ldi %4,%2", operands);
1718 output_asm_insn ("ldws,ma 4(0,%1),%3", operands);
1719 output_asm_insn ("ldws,ma 4(0,%1),%6", operands);
1720 output_asm_insn ("stws,ma %3,4(0,%0)", operands);
1721 output_asm_insn ("addib,>= -8,%2,.-12", operands);
1722 output_asm_insn ("stws,ma %6,4(0,%0)", operands);
1724 /* Handle the residual. There could be up to 7 bytes of
1725 residual to copy! */
1726 if (n_bytes % 8 != 0)
1728 operands[4] = GEN_INT (n_bytes % 4);
1729 if (n_bytes % 8 >= 4)
1730 output_asm_insn ("ldws,ma 4(0,%1),%3", operands);
1731 if (n_bytes % 4 != 0)
1732 output_asm_insn ("ldw 0(0,%1),%6", operands);
1733 if (n_bytes % 8 >= 4)
1734 output_asm_insn ("stws,ma %3,4(0,%0)", operands);
1735 if (n_bytes % 4 != 0)
1736 output_asm_insn ("stbys,e %6,%4(0,%0)", operands);
1741 /* Pre-adjust the loop counter. */
1742 operands[4] = GEN_INT (n_bytes - 4);
1743 output_asm_insn ("ldi %4,%2", operands);
1746 output_asm_insn ("ldhs,ma 2(0,%1),%3", operands);
1747 output_asm_insn ("ldhs,ma 2(0,%1),%6", operands);
1748 output_asm_insn ("sths,ma %3,2(0,%0)", operands);
1749 output_asm_insn ("addib,>= -4,%2,.-12", operands);
1750 output_asm_insn ("sths,ma %6,2(0,%0)", operands);
1752 /* Handle the residual. */
1753 if (n_bytes % 4 != 0)
1755 if (n_bytes % 4 >= 2)
1756 output_asm_insn ("ldhs,ma 2(0,%1),%3", operands);
1757 if (n_bytes % 2 != 0)
1758 output_asm_insn ("ldb 0(0,%1),%6", operands);
1759 if (n_bytes % 4 >= 2)
1760 output_asm_insn ("sths,ma %3,2(0,%0)", operands);
1761 if (n_bytes % 2 != 0)
1762 output_asm_insn ("stb %6,0(0,%0)", operands);
1767 /* Pre-adjust the loop counter. */
1768 operands[4] = GEN_INT (n_bytes - 2);
1769 output_asm_insn ("ldi %4,%2", operands);
1772 output_asm_insn ("ldbs,ma 1(0,%1),%3", operands);
1773 output_asm_insn ("ldbs,ma 1(0,%1),%6", operands);
1774 output_asm_insn ("stbs,ma %3,1(0,%0)", operands);
1775 output_asm_insn ("addib,>= -2,%2,.-12", operands);
1776 output_asm_insn ("stbs,ma %6,1(0,%0)", operands);
1778 /* Handle the residual. */
1779 if (n_bytes % 2 != 0)
1781 output_asm_insn ("ldb 0(0,%1),%3", operands);
1782 output_asm_insn ("stb %3,0(0,%0)", operands);
1791 /* Count the number of insns necessary to handle this block move.
1793 Basic structure is the same as emit_block_move, except that we
1794 count insns rather than emit them. */
1797 compute_movstrsi_length (insn)
1800 rtx pat = PATTERN (insn);
1801 int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
1802 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
1803 unsigned int n_insns = 0;
1805 /* We can't move more than four bytes at a time because the PA
1806 has no longer integer move insns. (Could use fp mem ops?) */
1810 /* The basic opying loop. */
1814 if (n_bytes % (2 * align) != 0)
1816 /* Any residual caused by unrolling the copy loop. */
1817 if (n_bytes % (2 * align) > align)
1820 /* Any residual because the number of bytes was not a
1821 multiple of the alignment. */
1822 if (n_bytes % align != 0)
1826 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
1832 output_and (operands)
1835 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
1837 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
1838 int ls0, ls1, ms0, p, len;
1840 for (ls0 = 0; ls0 < 32; ls0++)
1841 if ((mask & (1 << ls0)) == 0)
1844 for (ls1 = ls0; ls1 < 32; ls1++)
1845 if ((mask & (1 << ls1)) != 0)
1848 for (ms0 = ls1; ms0 < 32; ms0++)
1849 if ((mask & (1 << ms0)) == 0)
1862 operands[2] = GEN_INT (len);
1863 return "extru %1,31,%2,%0";
1867 /* We could use this `depi' for the case above as well, but `depi'
1868 requires one more register file access than an `extru'. */
1873 operands[2] = GEN_INT (p);
1874 operands[3] = GEN_INT (len);
1875 return "depi 0,%2,%3,%0";
1879 return "and %1,%2,%0";
1883 output_ior (operands)
1886 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
1887 int bs0, bs1, p, len;
1889 if (INTVAL (operands[2]) == 0)
1890 return "copy %1,%0";
1892 for (bs0 = 0; bs0 < 32; bs0++)
1893 if ((mask & (1 << bs0)) != 0)
1896 for (bs1 = bs0; bs1 < 32; bs1++)
1897 if ((mask & (1 << bs1)) == 0)
1900 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
1906 operands[2] = GEN_INT (p);
1907 operands[3] = GEN_INT (len);
1908 return "depi -1,%2,%3,%0";
1911 /* Output an ascii string. */
1913 output_ascii (file, p, size)
1920 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
1922 /* The HP assembler can only take strings of 256 characters at one
1923 time. This is a limitation on input line length, *not* the
1924 length of the string. Sigh. Even worse, it seems that the
1925 restriction is in number of input characters (see \xnn &
1926 \whatever). So we have to do this very carefully. */
1928 fputs ("\t.STRING \"", file);
1931 for (i = 0; i < size; i += 4)
1935 for (io = 0, co = 0; io < MIN (4, size - i); io++)
1937 register unsigned int c = p[i + io];
1939 if (c == '\"' || c == '\\')
1940 partial_output[co++] = '\\';
1941 if (c >= ' ' && c < 0177)
1942 partial_output[co++] = c;
1946 partial_output[co++] = '\\';
1947 partial_output[co++] = 'x';
1948 hexd = c / 16 - 0 + '0';
1950 hexd -= '9' - 'a' + 1;
1951 partial_output[co++] = hexd;
1952 hexd = c % 16 - 0 + '0';
1954 hexd -= '9' - 'a' + 1;
1955 partial_output[co++] = hexd;
1958 if (chars_output + co > 243)
1960 fputs ("\"\n\t.STRING \"", file);
1963 fwrite (partial_output, 1, co, file);
1967 fputs ("\"\n", file);
1970 /* Try to rewrite floating point comparisons & branches to avoid
1971 useless add,tr insns.
1973 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
1974 to see if FPCC is dead. CHECK_NOTES is nonzero for the
1975 first attempt to remove useless add,tr insns. It is zero
1976 for the second pass as reorg sometimes leaves bogus REG_DEAD
1979 When CHECK_NOTES is zero we can only eliminate add,tr insns
1980 when there's a 1:1 correspondence between fcmp and ftest/fbranch
1983 remove_useless_addtr_insns (insns, check_notes)
1989 static int pass = 0;
1991 /* This is fairly cheap, so always run it when optimizing. */
1995 int fbranch_count = 0;
1997 /* Walk all the insns in this function looking for fcmp & fbranch
1998 instructions. Keep track of how many of each we find. */
1999 insns = get_insns ();
2000 for (insn = insns; insn; insn = next_insn (insn))
2004 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2005 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2008 tmp = PATTERN (insn);
2010 /* It must be a set. */
2011 if (GET_CODE (tmp) != SET)
2014 /* If the destination is CCFP, then we've found an fcmp insn. */
2015 tmp = SET_DEST (tmp);
2016 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2022 tmp = PATTERN (insn);
2023 /* If this is an fbranch instruction, bump the fbranch counter. */
2024 if (GET_CODE (tmp) == SET
2025 && SET_DEST (tmp) == pc_rtx
2026 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2027 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2028 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2029 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2037 /* Find all floating point compare + branch insns. If possible,
2038 reverse the comparison & the branch to avoid add,tr insns. */
2039 for (insn = insns; insn; insn = next_insn (insn))
2043 /* Ignore anything that isn't an INSN. */
2044 if (GET_CODE (insn) != INSN)
2047 tmp = PATTERN (insn);
2049 /* It must be a set. */
2050 if (GET_CODE (tmp) != SET)
2053 /* The destination must be CCFP, which is register zero. */
2054 tmp = SET_DEST (tmp);
2055 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2058 /* INSN should be a set of CCFP.
2060 See if the result of this insn is used in a reversed FP
2061 conditional branch. If so, reverse our condition and
2062 the branch. Doing so avoids useless add,tr insns. */
2063 next = next_insn (insn);
2066 /* Jumps, calls and labels stop our search. */
2067 if (GET_CODE (next) == JUMP_INSN
2068 || GET_CODE (next) == CALL_INSN
2069 || GET_CODE (next) == CODE_LABEL)
2072 /* As does another fcmp insn. */
2073 if (GET_CODE (next) == INSN
2074 && GET_CODE (PATTERN (next)) == SET
2075 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2076 && REGNO (SET_DEST (PATTERN (next))) == 0)
2079 next = next_insn (next);
2082 /* Is NEXT_INSN a branch? */
2084 && GET_CODE (next) == JUMP_INSN)
2086 rtx pattern = PATTERN (next);
2088 /* If it a reversed fp conditional branch (eg uses add,tr)
2089 and CCFP dies, then reverse our conditional and the branch
2090 to avoid the add,tr. */
2091 if (GET_CODE (pattern) == SET
2092 && SET_DEST (pattern) == pc_rtx
2093 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2094 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2095 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2096 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2097 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2098 && (fcmp_count == fbranch_count
2100 && find_regno_note (next, REG_DEAD, 0))))
2102 /* Reverse the branch. */
2103 tmp = XEXP (SET_SRC (pattern), 1);
2104 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2105 XEXP (SET_SRC (pattern), 2) = tmp;
2106 INSN_CODE (next) = -1;
2108 /* Reverse our condition. */
2109 tmp = PATTERN (insn);
2110 PUT_CODE (XEXP (tmp, 1),
2111 reverse_condition (GET_CODE (XEXP (tmp, 1))));
2121 /* You may have trouble believing this, but this is the HP-PA stack
2126 Variable arguments (optional; any number may be allocated)
2128 SP-(4*(N+9)) arg word N
2133 Fixed arguments (must be allocated; may remain unused)
2142 SP-32 External Data Pointer (DP)
2144 SP-24 External/stub RP (RP')
2148 SP-8 Calling Stub RP (RP'')
2153 SP-0 Stack Pointer (points to next available address)
2157 /* This function saves registers as follows. Registers marked with ' are
2158 this function's registers (as opposed to the previous function's).
2159 If a frame_pointer isn't needed, r4 is saved as a general register;
2160 the space for the frame pointer is still allocated, though, to keep
2166 SP (FP') Previous FP
2167 SP + 4 Alignment filler (sigh)
2168 SP + 8 Space for locals reserved here.
2172 SP + n All call saved register used.
2176 SP + o All call saved fp registers used.
2180 SP + p (SP') points to next available address.
2184 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2185 Handle case where DISP > 8k by using the add_high_const pattern.
2187 Note in DISP > 8k case, we will leave the high part of the address
2188 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2190 store_reg (reg, disp, base)
2191 int reg, disp, base;
2193 if (VAL_14_BITS_P (disp))
2195 emit_move_insn (gen_rtx (MEM, SImode,
2196 gen_rtx (PLUS, SImode,
2197 gen_rtx (REG, SImode, base),
2199 gen_rtx (REG, SImode, reg));
2203 emit_insn (gen_add_high_const (gen_rtx (REG, SImode, 1),
2204 gen_rtx (REG, SImode, base),
2206 emit_move_insn (gen_rtx (MEM, SImode,
2207 gen_rtx (LO_SUM, SImode,
2208 gen_rtx (REG, SImode, 1),
2210 gen_rtx (REG, SImode, reg));
2214 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
2215 Handle case where DISP > 8k by using the add_high_const pattern.
2217 Note in DISP > 8k case, we will leave the high part of the address
2218 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2220 load_reg (reg, disp, base)
2221 int reg, disp, base;
2223 if (VAL_14_BITS_P (disp))
2225 emit_move_insn (gen_rtx (REG, SImode, reg),
2226 gen_rtx (MEM, SImode,
2227 gen_rtx (PLUS, SImode,
2228 gen_rtx (REG, SImode, base),
2233 emit_insn (gen_add_high_const (gen_rtx (REG, SImode, 1),
2234 gen_rtx (REG, SImode, base),
2236 emit_move_insn (gen_rtx (REG, SImode, reg),
2237 gen_rtx (MEM, SImode,
2238 gen_rtx (LO_SUM, SImode,
2239 gen_rtx (REG, SImode, 1),
2244 /* Emit RTL to set REG to the value specified by BASE+DISP.
2245 Handle case where DISP > 8k by using the add_high_const pattern.
2247 Note in DISP > 8k case, we will leave the high part of the address
2248 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2250 set_reg_plus_d(reg, base, disp)
2251 int reg, base, disp;
2253 if (VAL_14_BITS_P (disp))
2255 emit_move_insn (gen_rtx (REG, SImode, reg),
2256 gen_rtx (PLUS, SImode,
2257 gen_rtx (REG, SImode, base),
2262 emit_insn (gen_add_high_const (gen_rtx (REG, SImode, 1),
2263 gen_rtx (REG, SImode, base),
2265 emit_move_insn (gen_rtx (REG, SImode, reg),
2266 gen_rtx (LO_SUM, SImode,
2267 gen_rtx (REG, SImode, 1),
2272 /* Global variables set by FUNCTION_PROLOGUE. */
2273 /* Size of frame. Need to know this to emit return insns from
2275 static int actual_fsize;
2276 static int local_fsize, save_fregs;
2279 compute_frame_size (size, fregs_live)
2283 extern int current_function_outgoing_args_size;
2286 /* 8 is space for frame pointer + filler. If any frame is allocated
2287 we need to add this in because of STARTING_FRAME_OFFSET. */
2288 fsize = size + (size || frame_pointer_needed ? 8 : 0);
2290 /* We must leave enough space for all the callee saved registers
2291 from 3 .. highest used callee save register since we don't
2292 know if we're going to have an inline or out of line prologue
2294 for (i = 18; i >= 3; i--)
2295 if (regs_ever_live[i])
2297 fsize += 4 * (i - 2);
2301 /* Round the stack. */
2302 fsize = (fsize + 7) & ~7;
2304 /* We must leave enough space for all the callee saved registers
2305 from 3 .. highest used callee save register since we don't
2306 know if we're going to have an inline or out of line prologue
2308 for (i = 66; i >= 48; i -= 2)
2309 if (regs_ever_live[i] || regs_ever_live[i + 1])
2314 fsize += 4 * (i - 46);
2318 fsize += current_function_outgoing_args_size;
2319 if (! leaf_function_p () || fsize)
2321 return (fsize + 63) & ~63;
2324 rtx hp_profile_label_rtx;
2325 static char hp_profile_label_name[8];
2327 output_function_prologue (file, size)
2331 /* The function's label and associated .PROC must never be
2332 separated and must be output *after* any profiling declarations
2333 to avoid changing spaces/subspaces within a procedure. */
2334 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
2335 fputs ("\t.PROC\n", file);
2337 /* hppa_expand_prologue does the dirty work now. We just need
2338 to output the assembler directives which denote the start
2340 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
2341 if (regs_ever_live[2] || profile_flag)
2342 fputs (",CALLS,SAVE_RP", file);
2344 fputs (",NO_CALLS", file);
2346 if (frame_pointer_needed)
2347 fputs (",SAVE_SP", file);
2349 /* Pass on information about the number of callee register saves
2350 performed in the prologue.
2352 The compiler is supposed to pass the highest register number
2353 saved, the assembler then has to adjust that number before
2354 entering it into the unwind descriptor (to account for any
2355 caller saved registers with lower register numbers than the
2356 first callee saved register). */
2358 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
2361 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
2363 fputs ("\n\t.ENTRY\n", file);
2365 /* Horrid hack. emit_function_prologue will modify this RTL in
2366 place to get the expected results. */
2368 ASM_GENERATE_INTERNAL_LABEL (hp_profile_label_name, "LP",
2369 hp_profile_labelno);
2371 /* If we're using GAS and not using the portable runtime model, then
2372 we don't need to accumulate the total number of code bytes. */
2373 if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
2374 total_code_bytes = 0;
2375 else if (insn_addresses)
2377 unsigned int old_total = total_code_bytes;
2379 total_code_bytes += insn_addresses[INSN_UID (get_last_insn())];
2380 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
2382 /* Be prepared to handle overflows. */
2383 total_code_bytes = old_total > total_code_bytes ? -1 : total_code_bytes;
2386 total_code_bytes = -1;
2388 remove_useless_addtr_insns (get_insns (), 0);
2392 hppa_expand_prologue()
2394 extern char call_used_regs[];
2395 int size = get_frame_size ();
2396 int merge_sp_adjust_with_store = 0;
2398 rtx tmpreg, size_rtx;
2403 local_fsize = size + (size || frame_pointer_needed ? 8 : 0);
2404 actual_fsize = compute_frame_size (size, &save_fregs);
2406 /* Compute a few things we will use often. */
2407 tmpreg = gen_rtx (REG, SImode, 1);
2408 size_rtx = GEN_INT (actual_fsize);
2410 /* Handle out of line prologues and epilogues. */
2415 int outline_insn_count = 0;
2416 int inline_insn_count = 0;
2418 /* Count the number of insns for the inline and out of line
2419 variants so we can choose one appropriately.
2421 No need to screw with counting actual_fsize operations -- they're
2422 done for both inline and out of line prologues. */
2423 if (regs_ever_live[2])
2424 inline_insn_count += 1;
2426 if (! cint_ok_for_move (local_fsize))
2427 outline_insn_count += 2;
2429 outline_insn_count += 1;
2431 /* Put the register save info into %r22. */
2432 for (i = 18; i >= 3; i--)
2433 if (regs_ever_live[i] && ! call_used_regs[i])
2435 /* -1 because the stack adjustment is normally done in
2436 the same insn as a register save. */
2437 inline_insn_count += (i - 2) - 1;
2442 for (i = 66; i >= 48; i -= 2)
2443 if (regs_ever_live[i] || regs_ever_live[i + 1])
2445 /* +1 needed as we load %r1 with the start of the freg
2447 inline_insn_count += (i/2 - 23) + 1;
2448 saves |= ((i/2 - 12 ) << 16);
2452 if (frame_pointer_needed)
2453 inline_insn_count += 3;
2455 if (! cint_ok_for_move (saves))
2456 outline_insn_count += 2;
2458 outline_insn_count += 1;
2460 if (TARGET_PORTABLE_RUNTIME)
2461 outline_insn_count += 2;
2463 outline_insn_count += 1;
2465 /* If there's a lot of insns in the prologue, then do it as
2466 an out-of-line sequence. */
2467 if (inline_insn_count > outline_insn_count)
2469 /* Put the local_fisze into %r19. */
2470 operands[0] = gen_rtx (REG, SImode, 19);
2471 operands[1] = GEN_INT (local_fsize);
2472 emit_move_insn (operands[0], operands[1]);
2474 /* Put the stack size into %r21. */
2475 operands[0] = gen_rtx (REG, SImode, 21);
2476 operands[1] = size_rtx;
2477 emit_move_insn (operands[0], operands[1]);
2479 operands[0] = gen_rtx (REG, SImode, 22);
2480 operands[1] = GEN_INT (saves);
2481 emit_move_insn (operands[0], operands[1]);
2483 /* Now call the out-of-line prologue. */
2484 emit_insn (gen_outline_prologue_call ());
2485 emit_insn (gen_blockage ());
2487 /* Note that we're using an out-of-line prologue. */
2488 out_of_line_prologue_epilogue = 1;
2493 out_of_line_prologue_epilogue = 0;
2495 /* Save RP first. The calling conventions manual states RP will
2496 always be stored into the caller's frame at sp-20. */
2497 if (regs_ever_live[2] || profile_flag)
2498 store_reg (2, -20, STACK_POINTER_REGNUM);
2500 /* Allocate the local frame and set up the frame pointer if needed. */
2502 if (frame_pointer_needed)
2504 /* Copy the old frame pointer temporarily into %r1. Set up the
2505 new stack pointer, then store away the saved old frame pointer
2506 into the stack at sp+actual_fsize and at the same time update
2507 the stack pointer by actual_fsize bytes. Two versions, first
2508 handles small (<8k) frames. The second handles large (>8k)
2510 emit_move_insn (tmpreg, frame_pointer_rtx);
2511 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2512 if (VAL_14_BITS_P (actual_fsize))
2513 emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, size_rtx));
2516 /* It is incorrect to store the saved frame pointer at *sp,
2517 then increment sp (writes beyond the current stack boundary).
2519 So instead use stwm to store at *sp and post-increment the
2520 stack pointer as an atomic operation. Then increment sp to
2521 finish allocating the new frame. */
2522 emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, GEN_INT (64)));
2523 set_reg_plus_d (STACK_POINTER_REGNUM,
2524 STACK_POINTER_REGNUM,
2528 /* no frame pointer needed. */
2531 /* In some cases we can perform the first callee register save
2532 and allocating the stack frame at the same time. If so, just
2533 make a note of it and defer allocating the frame until saving
2534 the callee registers. */
2535 if (VAL_14_BITS_P (-actual_fsize)
2539 merge_sp_adjust_with_store = 1;
2540 /* Can not optimize. Adjust the stack frame by actual_fsize bytes. */
2541 else if (actual_fsize != 0)
2542 set_reg_plus_d (STACK_POINTER_REGNUM,
2543 STACK_POINTER_REGNUM,
2546 /* The hppa calling conventions say that that %r19, the pic offset
2547 register, is saved at sp - 32 (in this function's frame) when
2548 generating PIC code. FIXME: What is the correct thing to do
2549 for functions which make no calls and allocate no frame? Do
2550 we need to allocate a frame, or can we just omit the save? For
2551 now we'll just omit the save. */
2552 if (actual_fsize != 0 && flag_pic)
2553 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
2557 Instead of taking one argument, the counter label, as most normal
2558 mcounts do, _mcount appears to behave differently on the HPPA. It
2559 takes the return address of the caller, the address of this routine,
2560 and the address of the label. Also, it isn't magic, so
2561 argument registers have to be preserved. */
2564 int pc_offset, i, arg_offset, basereg, offsetadj;
2566 pc_offset = 4 + (frame_pointer_needed
2567 ? (VAL_14_BITS_P (actual_fsize) ? 12 : 20)
2568 : (VAL_14_BITS_P (actual_fsize) ? 4 : 8));
2570 /* When the function has a frame pointer, use it as the base
2571 register for saving/restore registers. Else use the stack
2572 pointer. Adjust the offset according to the frame size if
2573 this function does not have a frame pointer. */
2575 basereg = frame_pointer_needed ? FRAME_POINTER_REGNUM
2576 : STACK_POINTER_REGNUM;
2577 offsetadj = frame_pointer_needed ? 0 : actual_fsize;
2579 /* Horrid hack. emit_function_prologue will modify this RTL in
2580 place to get the expected results. sprintf here is just to
2581 put something in the name. */
2582 sprintf(hp_profile_label_name, "LP$%04d", -1);
2583 hp_profile_label_rtx = gen_rtx (SYMBOL_REF, SImode,
2584 hp_profile_label_name);
2585 if (current_function_returns_struct)
2586 store_reg (STRUCT_VALUE_REGNUM, - 12 - offsetadj, basereg);
2588 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2589 if (regs_ever_live [i])
2591 store_reg (i, arg_offset, basereg);
2592 /* Deal with arg_offset not fitting in 14 bits. */
2593 pc_offset += VAL_14_BITS_P (arg_offset) ? 4 : 8;
2596 emit_move_insn (gen_rtx (REG, SImode, 26), gen_rtx (REG, SImode, 2));
2597 emit_move_insn (tmpreg, gen_rtx (HIGH, SImode, hp_profile_label_rtx));
2598 emit_move_insn (gen_rtx (REG, SImode, 24),
2599 gen_rtx (LO_SUM, SImode, tmpreg, hp_profile_label_rtx));
2600 /* %r25 is set from within the output pattern. */
2601 emit_insn (gen_call_profiler (GEN_INT (- pc_offset - 20)));
2603 /* Restore argument registers. */
2604 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2605 if (regs_ever_live [i])
2606 load_reg (i, arg_offset, basereg);
2608 if (current_function_returns_struct)
2609 load_reg (STRUCT_VALUE_REGNUM, -12 - offsetadj, basereg);
2613 /* Normal register save.
2615 Do not save the frame pointer in the frame_pointer_needed case. It
2616 was done earlier. */
2617 if (frame_pointer_needed)
2619 for (i = 18, offset = local_fsize; i >= 4; i--)
2620 if (regs_ever_live[i] && ! call_used_regs[i])
2622 store_reg (i, offset, FRAME_POINTER_REGNUM);
2626 /* Account for %r3 which is saved in a special place. */
2629 /* No frame pointer needed. */
2632 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
2633 if (regs_ever_live[i] && ! call_used_regs[i])
2635 /* If merge_sp_adjust_with_store is nonzero, then we can
2636 optimize the first GR save. */
2637 if (merge_sp_adjust_with_store)
2639 merge_sp_adjust_with_store = 0;
2640 emit_insn (gen_post_stwm (stack_pointer_rtx,
2641 gen_rtx (REG, SImode, i),
2642 GEN_INT (-offset)));
2645 store_reg (i, offset, STACK_POINTER_REGNUM);
2650 /* If we wanted to merge the SP adjustment with a GR save, but we never
2651 did any GR saves, then just emit the adjustment here. */
2652 if (merge_sp_adjust_with_store)
2653 set_reg_plus_d (STACK_POINTER_REGNUM,
2654 STACK_POINTER_REGNUM,
2658 /* Align pointer properly (doubleword boundary). */
2659 offset = (offset + 7) & ~7;
2661 /* Floating point register store. */
2664 /* First get the frame or stack pointer to the start of the FP register
2666 if (frame_pointer_needed)
2667 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
2669 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
2671 /* Now actually save the FP registers. */
2672 for (i = 66; i >= 48; i -= 2)
2674 if (regs_ever_live[i] || regs_ever_live[i + 1])
2676 emit_move_insn (gen_rtx (MEM, DFmode,
2677 gen_rtx (POST_INC, DFmode, tmpreg)),
2678 gen_rtx (REG, DFmode, i));
2684 /* When generating PIC code it is necessary to save/restore the
2685 PIC register around each function call. We used to do this
2686 in the call patterns themselves, but that implementation
2687 made incorrect assumptions about using global variables to hold
2688 per-function rtl code generated in the backend.
2690 So instead, we copy the PIC register into a reserved callee saved
2691 register in the prologue. Then after each call we reload the PIC
2692 register from the callee saved register. We also reload the PIC
2693 register from the callee saved register in the epilogue ensure the
2694 PIC register is valid at function exit.
2696 This may (depending on the exact characteristics of the function)
2697 even be more efficient.
2699 Avoid this if the callee saved register wasn't used (these are
2701 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM_SAVED])
2702 emit_move_insn (gen_rtx (REG, SImode, PIC_OFFSET_TABLE_REGNUM_SAVED),
2703 gen_rtx (REG, SImode, PIC_OFFSET_TABLE_REGNUM));
2708 output_function_epilogue (file, size)
2712 rtx insn = get_last_insn ();
2715 /* hppa_expand_epilogue does the dirty work now. We just need
2716 to output the assembler directives which denote the end
2719 To make debuggers happy, emit a nop if the epilogue was completely
2720 eliminated due to a volatile call as the last insn in the
2721 current function. That way the return address (in %r2) will
2722 always point to a valid instruction in the current function. */
2724 /* Get the last real insn. */
2725 if (GET_CODE (insn) == NOTE)
2726 insn = prev_real_insn (insn);
2728 /* If it is a sequence, then look inside. */
2729 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
2730 insn = XVECEXP (PATTERN (insn), 0, 0);
2732 /* If insn is a CALL_INSN, then it must be a call to a volatile
2733 function (otherwise there would be epilogue insns). */
2734 if (insn && GET_CODE (insn) == CALL_INSN)
2735 fputs ("\tnop\n", file);
2737 fputs ("\t.EXIT\n\t.PROCEND\n", file);
2739 /* If we have deferred plabels, then we need to switch into the data
2740 section and align it to a 4 byte boundary before we output the
2741 deferred plabels. */
2742 if (n_deferred_plabels)
2745 ASM_OUTPUT_ALIGN (file, 2);
2748 /* Now output the deferred plabels. */
2749 for (i = 0; i < n_deferred_plabels; i++)
2751 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
2752 assemble_integer (deferred_plabels[i].symbol, 4, 1);
2754 n_deferred_plabels = 0;
2758 hppa_expand_epilogue ()
2762 int merge_sp_adjust_with_load = 0;
2764 /* Handle out of line prologues and epilogues. */
2765 if (TARGET_SPACE && out_of_line_prologue_epilogue)
2770 /* Put the register save info into %r22. */
2771 for (i = 18; i >= 3; i--)
2772 if (regs_ever_live[i] && ! call_used_regs[i])
2778 for (i = 66; i >= 48; i -= 2)
2779 if (regs_ever_live[i] || regs_ever_live[i + 1])
2781 saves |= ((i/2 - 12 ) << 16);
2785 emit_insn (gen_blockage ());
2787 /* Put the local_fisze into %r19. */
2788 operands[0] = gen_rtx (REG, SImode, 19);
2789 operands[1] = GEN_INT (local_fsize);
2790 emit_move_insn (operands[0], operands[1]);
2792 /* Put the stack size into %r21. */
2793 operands[0] = gen_rtx (REG, SImode, 21);
2794 operands[1] = GEN_INT (actual_fsize);
2795 emit_move_insn (operands[0], operands[1]);
2797 operands[0] = gen_rtx (REG, SImode, 22);
2798 operands[1] = GEN_INT (saves);
2799 emit_move_insn (operands[0], operands[1]);
2801 /* Now call the out-of-line epilogue. */
2802 emit_insn (gen_outline_epilogue_call ());
2806 /* We will use this often. */
2807 tmpreg = gen_rtx (REG, SImode, 1);
2809 /* Try to restore RP early to avoid load/use interlocks when
2810 RP gets used in the return (bv) instruction. This appears to still
2811 be necessary even when we schedule the prologue and epilogue. */
2812 if (frame_pointer_needed
2813 && (regs_ever_live [2] || profile_flag))
2814 load_reg (2, -20, FRAME_POINTER_REGNUM);
2816 /* No frame pointer, and stack is smaller than 8k. */
2817 else if (! frame_pointer_needed
2818 && VAL_14_BITS_P (actual_fsize + 20)
2819 && (regs_ever_live[2] || profile_flag))
2820 load_reg (2, - (actual_fsize + 20), STACK_POINTER_REGNUM);
2822 /* General register restores. */
2823 if (frame_pointer_needed)
2825 for (i = 18, offset = local_fsize; i >= 4; i--)
2826 if (regs_ever_live[i] && ! call_used_regs[i])
2828 load_reg (i, offset, FRAME_POINTER_REGNUM);
2834 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
2836 if (regs_ever_live[i] && ! call_used_regs[i])
2838 /* Only for the first load.
2839 merge_sp_adjust_with_load holds the register load
2840 with which we will merge the sp adjustment. */
2841 if (VAL_14_BITS_P (actual_fsize + 20)
2843 && ! merge_sp_adjust_with_load)
2844 merge_sp_adjust_with_load = i;
2846 load_reg (i, offset, STACK_POINTER_REGNUM);
2852 /* Align pointer properly (doubleword boundary). */
2853 offset = (offset + 7) & ~7;
2855 /* FP register restores. */
2858 /* Adjust the register to index off of. */
2859 if (frame_pointer_needed)
2860 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
2862 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
2864 /* Actually do the restores now. */
2865 for (i = 66; i >= 48; i -= 2)
2867 if (regs_ever_live[i] || regs_ever_live[i + 1])
2869 emit_move_insn (gen_rtx (REG, DFmode, i),
2870 gen_rtx (MEM, DFmode,
2871 gen_rtx (POST_INC, DFmode, tmpreg)));
2876 /* Emit a blockage insn here to keep these insns from being moved to
2877 an earlier spot in the epilogue, or into the main instruction stream.
2879 This is necessary as we must not cut the stack back before all the
2880 restores are finished. */
2881 emit_insn (gen_blockage ());
2882 /* No frame pointer, but we have a stack greater than 8k. We restore
2883 %r2 very late in this case. (All other cases are restored as early
2885 if (! frame_pointer_needed
2886 && ! VAL_14_BITS_P (actual_fsize + 20)
2887 && (regs_ever_live[2] || profile_flag))
2889 set_reg_plus_d (STACK_POINTER_REGNUM,
2890 STACK_POINTER_REGNUM,
2893 /* This used to try and be clever by not depending on the value in
2894 %r30 and instead use the value held in %r1 (so that the 2nd insn
2895 which sets %r30 could be put in the delay slot of the return insn).
2897 That won't work since if the stack is exactly 8k set_reg_plus_d
2898 doesn't set %r1, just %r30. */
2899 load_reg (2, - 20, STACK_POINTER_REGNUM);
2902 /* Reset stack pointer (and possibly frame pointer). The stack
2903 pointer is initially set to fp + 64 to avoid a race condition. */
2904 else if (frame_pointer_needed)
2906 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64);
2907 emit_insn (gen_pre_ldwm (frame_pointer_rtx,
2911 /* If we were deferring a callee register restore, do it now. */
2912 else if (! frame_pointer_needed && merge_sp_adjust_with_load)
2913 emit_insn (gen_pre_ldwm (gen_rtx (REG, SImode,
2914 merge_sp_adjust_with_load),
2916 GEN_INT (- actual_fsize)));
2917 else if (actual_fsize != 0)
2918 set_reg_plus_d (STACK_POINTER_REGNUM,
2919 STACK_POINTER_REGNUM,
2923 /* This is only valid once reload has completed because it depends on
2924 knowing exactly how much (if any) frame there is and...
2926 It's only valid if there is no frame marker to de-allocate and...
2928 It's only valid if %r2 hasn't been saved into the caller's frame
2929 (we're not profiling and %r2 isn't live anywhere). */
2931 hppa_can_use_return_insn_p ()
2933 return (reload_completed
2934 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
2936 && ! regs_ever_live[2]
2937 && ! frame_pointer_needed);
2941 emit_bcond_fp (code, operand0)
2945 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
2946 gen_rtx (IF_THEN_ELSE, VOIDmode,
2947 gen_rtx (code, VOIDmode,
2948 gen_rtx (REG, CCFPmode, 0),
2950 gen_rtx (LABEL_REF, VOIDmode, operand0),
2956 gen_cmp_fp (code, operand0, operand1)
2958 rtx operand0, operand1;
2960 return gen_rtx (SET, VOIDmode, gen_rtx (REG, CCFPmode, 0),
2961 gen_rtx (code, CCFPmode, operand0, operand1));
2964 /* Adjust the cost of a scheduling dependency. Return the new cost of
2965 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
2968 pa_adjust_cost (insn, link, dep_insn, cost)
2974 if (! recog_memoized (insn))
2977 if (REG_NOTE_KIND (link) == 0)
2979 /* Data dependency; DEP_INSN writes a register that INSN reads some
2982 if (get_attr_type (insn) == TYPE_FPSTORE)
2984 rtx pat = PATTERN (insn);
2985 rtx dep_pat = PATTERN (dep_insn);
2986 if (GET_CODE (pat) == PARALLEL)
2988 /* This happens for the fstXs,mb patterns. */
2989 pat = XVECEXP (pat, 0, 0);
2991 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
2992 /* If this happens, we have to extend this to schedule
2993 optimally. Return 0 for now. */
2996 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
2998 if (! recog_memoized (dep_insn))
3000 /* DEP_INSN is writing its result to the register
3001 being stored in the fpstore INSN. */
3002 switch (get_attr_type (dep_insn))
3005 /* This cost 3 cycles, not 2 as the md says for the
3006 700 and 7100. Note scaling of cost for 7100. */
3007 return cost + (pa_cpu == PROCESSOR_700) ? 1 : 2;
3014 case TYPE_FPSQRTSGL:
3015 case TYPE_FPSQRTDBL:
3016 /* In these important cases, we save one cycle compared to
3017 when flop instruction feed each other. */
3018 return cost - (pa_cpu == PROCESSOR_700) ? 1 : 2;
3026 /* For other data dependencies, the default cost specified in the
3030 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3032 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3035 if (get_attr_type (insn) == TYPE_FPLOAD)
3037 rtx pat = PATTERN (insn);
3038 rtx dep_pat = PATTERN (dep_insn);
3039 if (GET_CODE (pat) == PARALLEL)
3041 /* This happens for the fldXs,mb patterns. */
3042 pat = XVECEXP (pat, 0, 0);
3044 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3045 /* If this happens, we have to extend this to schedule
3046 optimally. Return 0 for now. */
3049 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3051 if (! recog_memoized (dep_insn))
3053 switch (get_attr_type (dep_insn))
3060 case TYPE_FPSQRTSGL:
3061 case TYPE_FPSQRTDBL:
3062 /* A fpload can't be issued until one cycle before a
3063 preceding arithmetic operation has finished if
3064 the target of the fpload is any of the sources
3065 (or destination) of the arithmetic operation. */
3066 return cost - (pa_cpu == PROCESSOR_700) ? 1 : 2;
3073 else if (get_attr_type (insn) == TYPE_FPALU)
3075 rtx pat = PATTERN (insn);
3076 rtx dep_pat = PATTERN (dep_insn);
3077 if (GET_CODE (pat) == PARALLEL)
3079 /* This happens for the fldXs,mb patterns. */
3080 pat = XVECEXP (pat, 0, 0);
3082 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3083 /* If this happens, we have to extend this to schedule
3084 optimally. Return 0 for now. */
3087 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3089 if (! recog_memoized (dep_insn))
3091 switch (get_attr_type (dep_insn))
3095 case TYPE_FPSQRTSGL:
3096 case TYPE_FPSQRTDBL:
3097 /* An ALU flop can't be issued until two cycles before a
3098 preceding divide or sqrt operation has finished if
3099 the target of the ALU flop is any of the sources
3100 (or destination) of the divide or sqrt operation. */
3101 return cost - (pa_cpu == PROCESSOR_700) ? 2 : 4;
3109 /* For other anti dependencies, the cost is 0. */
3112 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3114 /* Output dependency; DEP_INSN writes a register that INSN writes some
3116 if (get_attr_type (insn) == TYPE_FPLOAD)
3118 rtx pat = PATTERN (insn);
3119 rtx dep_pat = PATTERN (dep_insn);
3120 if (GET_CODE (pat) == PARALLEL)
3122 /* This happens for the fldXs,mb patterns. */
3123 pat = XVECEXP (pat, 0, 0);
3125 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3126 /* If this happens, we have to extend this to schedule
3127 optimally. Return 0 for now. */
3130 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3132 if (! recog_memoized (dep_insn))
3134 switch (get_attr_type (dep_insn))
3141 case TYPE_FPSQRTSGL:
3142 case TYPE_FPSQRTDBL:
3143 /* A fpload can't be issued until one cycle before a
3144 preceding arithmetic operation has finished if
3145 the target of the fpload is the destination of the
3146 arithmetic operation. */
3147 return cost - (pa_cpu == PROCESSOR_700) ? 1 : 2;
3154 else if (get_attr_type (insn) == TYPE_FPALU)
3156 rtx pat = PATTERN (insn);
3157 rtx dep_pat = PATTERN (dep_insn);
3158 if (GET_CODE (pat) == PARALLEL)
3160 /* This happens for the fldXs,mb patterns. */
3161 pat = XVECEXP (pat, 0, 0);
3163 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3164 /* If this happens, we have to extend this to schedule
3165 optimally. Return 0 for now. */
3168 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3170 if (! recog_memoized (dep_insn))
3172 switch (get_attr_type (dep_insn))
3176 case TYPE_FPSQRTSGL:
3177 case TYPE_FPSQRTDBL:
3178 /* An ALU flop can't be issued until two cycles before a
3179 preceding divide or sqrt operation has finished if
3180 the target of the ALU flop is also the target of
3181 of the divide or sqrt operation. */
3182 return cost - (pa_cpu == PROCESSOR_700) ? 2 : 4;
3190 /* For other output dependencies, the cost is 0. */
3197 /* Return any length adjustment needed by INSN which already has its length
3198 computed as LENGTH. Return zero if no adjustment is necessary.
3200 For the PA: function calls, millicode calls, and backwards short
3201 conditional branches with unfilled delay slots need an adjustment by +1
3202 (to account for the NOP which will be inserted into the instruction stream).
3204 Also compute the length of an inline block move here as it is too
3205 complicated to express as a length attribute in pa.md. */
3207 pa_adjust_insn_length (insn, length)
3211 rtx pat = PATTERN (insn);
3213 /* Call insns which are *not* indirect and have unfilled delay slots. */
3214 if (GET_CODE (insn) == CALL_INSN)
3217 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
3218 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
3220 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
3221 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
3227 /* Jumps inside switch tables which have unfilled delay slots
3228 also need adjustment. */
3229 else if (GET_CODE (insn) == JUMP_INSN
3230 && simplejump_p (insn)
3231 && GET_MODE (PATTERN (insn)) == DImode)
3233 /* Millicode insn with an unfilled delay slot. */
3234 else if (GET_CODE (insn) == INSN
3235 && GET_CODE (pat) != SEQUENCE
3236 && GET_CODE (pat) != USE
3237 && GET_CODE (pat) != CLOBBER
3238 && get_attr_type (insn) == TYPE_MILLI)
3240 /* Block move pattern. */
3241 else if (GET_CODE (insn) == INSN
3242 && GET_CODE (pat) == PARALLEL
3243 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
3244 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
3245 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
3246 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
3247 return compute_movstrsi_length (insn) - 4;
3248 /* Conditional branch with an unfilled delay slot. */
3249 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
3251 /* Adjust a short backwards conditional with an unfilled delay slot. */
3252 if (GET_CODE (pat) == SET
3254 && ! forward_branch_p (insn))
3256 else if (GET_CODE (pat) == PARALLEL
3257 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
3260 /* Adjust dbra insn with short backwards conditional branch with
3261 unfilled delay slot -- only for case where counter is in a
3262 general register register. */
3263 else if (GET_CODE (pat) == PARALLEL
3264 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
3265 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
3266 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
3268 && ! forward_branch_p (insn))
3276 /* Print operand X (an rtx) in assembler syntax to file FILE.
3277 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3278 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3281 print_operand (file, x, code)
3289 /* Output a 'nop' if there's nothing for the delay slot. */
3290 if (dbr_sequence_length () == 0)
3291 fputs ("\n\tnop", file);
3294 /* Output an nullification completer if there's nothing for the */
3295 /* delay slot or nullification is requested. */
3296 if (dbr_sequence_length () == 0 ||
3298 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
3302 /* Print out the second register name of a register pair.
3303 I.e., R (6) => 7. */
3304 fputs (reg_names[REGNO (x)+1], file);
3307 /* A register or zero. */
3309 || (x == CONST0_RTX (DFmode))
3310 || (x == CONST0_RTX (SFmode)))
3317 case 'C': /* Plain (C)ondition */
3319 switch (GET_CODE (x))
3322 fputs ("=", file); break;
3324 fputs ("<>", file); break;
3326 fputs (">", file); break;
3328 fputs (">=", file); break;
3330 fputs (">>=", file); break;
3332 fputs (">>", file); break;
3334 fputs ("<", file); break;
3336 fputs ("<=", file); break;
3338 fputs ("<<=", file); break;
3340 fputs ("<<", file); break;
3345 case 'N': /* Condition, (N)egated */
3346 switch (GET_CODE (x))
3349 fputs ("<>", file); break;
3351 fputs ("=", file); break;
3353 fputs ("<=", file); break;
3355 fputs ("<", file); break;
3357 fputs ("<<", file); break;
3359 fputs ("<<=", file); break;
3361 fputs (">=", file); break;
3363 fputs (">", file); break;
3365 fputs (">>", file); break;
3367 fputs (">>=", file); break;
3372 /* For floating point comparisons. Need special conditions to deal
3373 with NaNs properly. */
3375 switch (GET_CODE (x))
3378 fputs ("!=", file); break;
3380 fputs ("=", file); break;
3382 fputs ("!>", file); break;
3384 fputs ("!>=", file); break;
3386 fputs ("!<", file); break;
3388 fputs ("!<=", file); break;
3393 case 'S': /* Condition, operands are (S)wapped. */
3394 switch (GET_CODE (x))
3397 fputs ("=", file); break;
3399 fputs ("<>", file); break;
3401 fputs ("<", file); break;
3403 fputs ("<=", file); break;
3405 fputs ("<<=", file); break;
3407 fputs ("<<", file); break;
3409 fputs (">", file); break;
3411 fputs (">=", file); break;
3413 fputs (">>=", file); break;
3415 fputs (">>", file); break;
3420 case 'B': /* Condition, (B)oth swapped and negate. */
3421 switch (GET_CODE (x))
3424 fputs ("<>", file); break;
3426 fputs ("=", file); break;
3428 fputs (">=", file); break;
3430 fputs (">", file); break;
3432 fputs (">>", file); break;
3434 fputs (">>=", file); break;
3436 fputs ("<=", file); break;
3438 fputs ("<", file); break;
3440 fputs ("<<", file); break;
3442 fputs ("<<=", file); break;
3448 if (GET_CODE (x) == CONST_INT)
3450 fprintf (file, "%d", ~INTVAL (x));
3455 if (GET_CODE (x) == CONST_INT)
3457 fprintf (file, "%d", 32 - (INTVAL (x) & 31));
3462 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
3464 fprintf (file, "%d", exact_log2 (INTVAL (x)));
3469 if (GET_CODE (x) == CONST_INT)
3471 fprintf (file, "%d", 31 - (INTVAL (x) & 31));
3476 if (GET_CODE (x) == CONST_INT)
3481 switch (GET_CODE (XEXP (x, 0)))
3485 fputs ("s,mb", file);
3489 fputs ("s,ma", file);
3492 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3493 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
3494 fputs ("x,s", file);
3495 else if (code == 'F')
3505 output_global_address (file, x, 0);
3508 output_global_address (file, x, 1);
3510 case 0: /* Don't do anything special */
3515 compute_zdepi_operands (INTVAL (x), op);
3516 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
3522 if (GET_CODE (x) == REG)
3524 fputs (reg_names [REGNO (x)], file);
3525 if (FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4 && (REGNO (x) & 1) == 0)
3528 else if (GET_CODE (x) == MEM)
3530 int size = GET_MODE_SIZE (GET_MODE (x));
3531 rtx base = XEXP (XEXP (x, 0), 0);
3532 switch (GET_CODE (XEXP (x, 0)))
3536 fprintf (file, "-%d(0,%s)", size, reg_names [REGNO (base)]);
3540 fprintf (file, "%d(0,%s)", size, reg_names [REGNO (base)]);
3543 if (GET_CODE (XEXP (x, 0)) == PLUS
3544 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
3545 fprintf (file, "%s(0,%s)",
3546 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
3547 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
3548 else if (GET_CODE (XEXP (x, 0)) == PLUS
3549 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
3550 fprintf (file, "%s(0,%s)",
3551 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
3552 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
3554 output_address (XEXP (x, 0));
3559 output_addr_const (file, x);
3562 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
3565 output_global_address (file, x, round_constant)
3571 /* Imagine (high (const (plus ...))). */
3572 if (GET_CODE (x) == HIGH)
3575 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x))
3576 assemble_name (file, XSTR (x, 0));
3577 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
3579 assemble_name (file, XSTR (x, 0));
3580 fputs ("-$global$", file);
3582 else if (GET_CODE (x) == CONST)
3585 int offset = 0; /* assembler wants -$global$ at end */
3588 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
3590 base = XEXP (XEXP (x, 0), 0);
3591 output_addr_const (file, base);
3593 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
3594 offset = INTVAL (XEXP (XEXP (x, 0), 0));
3597 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
3599 base = XEXP (XEXP (x, 0), 1);
3600 output_addr_const (file, base);
3602 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
3603 offset = INTVAL (XEXP (XEXP (x, 0),1));
3606 /* How bogus. The compiler is apparently responsible for
3607 rounding the constant if it uses an LR field selector.
3609 The linker and/or assembler seem a better place since
3610 they have to do this kind of thing already.
3612 If we fail to do this, HP's optimizing linker may eliminate
3613 an addil, but not update the ldw/stw/ldo instruction that
3614 uses the result of the addil. */
3616 offset = ((offset + 0x1000) & ~0x1fff);
3618 if (GET_CODE (XEXP (x, 0)) == PLUS)
3628 else if (GET_CODE (XEXP (x, 0)) == MINUS
3629 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3633 if (!read_only_operand (base) && !flag_pic)
3634 fputs ("-$global$", file);
3636 fprintf (file,"%s%d", sep, offset);
3639 output_addr_const (file, x);
3642 /* HP's millicode routines mean something special to the assembler.
3643 Keep track of which ones we have used. */
3645 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
3646 static char imported[(int)end1000];
3647 static char *milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
3648 static char import_string[] = ".IMPORT $$....,MILLICODE";
3649 #define MILLI_START 10
3653 enum millicodes code;
3655 char str[sizeof (import_string)];
3657 if (!imported[(int)code])
3659 imported[(int)code] = 1;
3660 strcpy (str, import_string);
3661 strncpy (str + MILLI_START, milli_names[(int)code], 4);
3662 output_asm_insn (str, 0);
3666 /* The register constraints have put the operands and return value in
3667 the proper registers. */
3670 output_mul_insn (unsignedp, insn)
3674 import_milli (mulI);
3675 return output_millicode_call (insn, gen_rtx (SYMBOL_REF, SImode, "$$mulI"));
3678 /* Emit the rtl for doing a division by a constant. */
3680 /* Do magic division millicodes exist for this value? */
3681 static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
3684 /* We'll use an array to keep track of the magic millicodes and
3685 whether or not we've used them already. [n][0] is signed, [n][1] is
3688 static int div_milli[16][2];
3691 div_operand (op, mode)
3693 enum machine_mode mode;
3695 return (mode == SImode
3696 && ((GET_CODE (op) == REG && REGNO (op) == 25)
3697 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
3698 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
3702 emit_hpdiv_const (operands, unsignedp)
3706 if (GET_CODE (operands[2]) == CONST_INT
3707 && INTVAL (operands[2]) > 0
3708 && INTVAL (operands[2]) < 16
3709 && magic_milli[INTVAL (operands[2])])
3711 emit_move_insn ( gen_rtx (REG, SImode, 26), operands[1]);
3714 (PARALLEL, VOIDmode,
3715 gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
3716 gen_rtx (unsignedp ? UDIV : DIV, SImode,
3717 gen_rtx (REG, SImode, 26),
3719 gen_rtx (CLOBBER, VOIDmode, operands[3]),
3720 gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
3721 gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
3722 gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
3723 emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
3730 output_div_insn (operands, unsignedp, insn)
3737 /* If the divisor is a constant, try to use one of the special
3739 if (GET_CODE (operands[0]) == CONST_INT)
3741 static char buf[100];
3742 divisor = INTVAL (operands[0]);
3743 if (!div_milli[divisor][unsignedp])
3745 div_milli[divisor][unsignedp] = 1;
3747 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
3749 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
3753 sprintf (buf, "$$divU_%d", INTVAL (operands[0]));
3754 return output_millicode_call (insn,
3755 gen_rtx (SYMBOL_REF, SImode, buf));
3759 sprintf (buf, "$$divI_%d", INTVAL (operands[0]));
3760 return output_millicode_call (insn,
3761 gen_rtx (SYMBOL_REF, SImode, buf));
3764 /* Divisor isn't a special constant. */
3769 import_milli (divU);
3770 return output_millicode_call (insn,
3771 gen_rtx (SYMBOL_REF, SImode, "$$divU"));
3775 import_milli (divI);
3776 return output_millicode_call (insn,
3777 gen_rtx (SYMBOL_REF, SImode, "$$divI"));
3782 /* Output a $$rem millicode to do mod. */
3785 output_mod_insn (unsignedp, insn)
3791 import_milli (remU);
3792 return output_millicode_call (insn,
3793 gen_rtx (SYMBOL_REF, SImode, "$$remU"));
3797 import_milli (remI);
3798 return output_millicode_call (insn,
3799 gen_rtx (SYMBOL_REF, SImode, "$$remI"));
3804 output_arg_descriptor (call_insn)
3808 enum machine_mode arg_mode;
3810 int i, output_flag = 0;
3813 for (i = 0; i < 4; i++)
3816 /* Specify explicitly that no argument relocations should take place
3817 if using the portable runtime calling conventions. */
3818 if (TARGET_PORTABLE_RUNTIME)
3820 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
3825 if (GET_CODE (call_insn) != CALL_INSN)
3827 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
3829 rtx use = XEXP (link, 0);
3831 if (! (GET_CODE (use) == USE
3832 && GET_CODE (XEXP (use, 0)) == REG
3833 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
3836 arg_mode = GET_MODE (XEXP (use, 0));
3837 regno = REGNO (XEXP (use, 0));
3838 if (regno >= 23 && regno <= 26)
3840 arg_regs[26 - regno] = "GR";
3841 if (arg_mode == DImode)
3842 arg_regs[25 - regno] = "GR";
3844 else if (regno >= 32 && regno <= 39)
3846 if (arg_mode == SFmode)
3847 arg_regs[(regno - 32) / 2] = "FR";
3850 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
3851 arg_regs[(regno - 34) / 2] = "FR";
3852 arg_regs[(regno - 34) / 2 + 1] = "FU";
3854 arg_regs[(regno - 34) / 2] = "FU";
3855 arg_regs[(regno - 34) / 2 + 1] = "FR";
3860 fputs ("\t.CALL ", asm_out_file);
3861 for (i = 0; i < 4; i++)
3866 fputc (',', asm_out_file);
3867 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
3870 fputc ('\n', asm_out_file);
3873 /* Return the class of any secondary reload register that is needed to
3874 move IN into a register in class CLASS using mode MODE.
3876 Profiling has showed this routine and its descendants account for
3877 a significant amount of compile time (~7%). So it has been
3878 optimized to reduce redundant computations and eliminate useless
3881 It might be worthwhile to try and make this a leaf function too. */
3884 secondary_reload_class (class, mode, in)
3885 enum reg_class class;
3886 enum machine_mode mode;
3889 int regno, is_symbolic;
3891 /* Trying to load a constant into a FP register during PIC code
3892 generation will require %r1 as a scratch register. */
3894 && GET_MODE_CLASS (mode) == MODE_INT
3895 && FP_REG_CLASS_P (class)
3896 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
3899 /* Profiling showed the PA port spends about 1.3% of its compilation
3900 time in true_regnum from calls inside secondary_reload_class. */
3902 if (GET_CODE (in) == REG)
3905 if (regno >= FIRST_PSEUDO_REGISTER)
3906 regno = true_regnum (in);
3908 else if (GET_CODE (in) == SUBREG)
3909 regno = true_regnum (in);
3913 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
3914 && GET_MODE_CLASS (mode) == MODE_INT
3915 && FP_REG_CLASS_P (class))
3916 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
3917 return GENERAL_REGS;
3919 if (GET_CODE (in) == HIGH)
3922 /* Profiling has showed GCC spends about 2.6% of its compilation
3923 time in symbolic_operand from calls inside secondary_reload_class.
3925 We use an inline copy and only compute its return value once to avoid
3927 switch (GET_CODE (in))
3937 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
3938 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
3939 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
3948 && read_only_operand (in))
3951 if (class != R1_REGS && is_symbolic)
3958 function_arg_padding (mode, type)
3959 enum machine_mode mode;
3964 if (mode == BLKmode)
3966 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
3967 size = int_size_in_bytes (type) * BITS_PER_UNIT;
3969 return upward; /* Don't know if this is right, but */
3970 /* same as old definition. */
3973 size = GET_MODE_BITSIZE (mode);
3974 if (size < PARM_BOUNDARY)
3976 else if (size % PARM_BOUNDARY)
3983 /* Do what is necessary for `va_start'. The argument is ignored;
3984 We look at the current function to determine if stdargs or varargs
3985 is used and fill in an initial va_list. A pointer to this constructor
3989 hppa_builtin_saveregs (arglist)
3993 tree fntype = TREE_TYPE (current_function_decl);
3994 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
3995 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3996 != void_type_node)))
3997 ? UNITS_PER_WORD : 0);
4000 offset = plus_constant (current_function_arg_offset_rtx, argadj);
4002 offset = current_function_arg_offset_rtx;
4004 /* Store general registers on the stack. */
4005 move_block_from_reg (23,
4006 gen_rtx (MEM, BLKmode,
4008 (current_function_internal_arg_pointer, -16)),
4009 4, 4 * UNITS_PER_WORD);
4010 return copy_to_reg (expand_binop (Pmode, add_optab,
4011 current_function_internal_arg_pointer,
4012 offset, 0, 0, OPTAB_LIB_WIDEN));
4015 /* This routine handles all the normal conditional branch sequences we
4016 might need to generate. It handles compare immediate vs compare
4017 register, nullification of delay slots, varying length branches,
4018 negated branches, and all combinations of the above. It returns the
4019 output appropriate to emit the branch corresponding to all given
4023 output_cbranch (operands, nullify, length, negated, insn)
4025 int nullify, length, negated;
4028 static char buf[100];
4031 /* A conditional branch to the following instruction (eg the delay slot) is
4032 asking for a disaster. This can happen when not optimizing.
4034 In such cases it is safe to emit nothing. */
4036 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4039 /* If this is a long branch with its delay slot unfilled, set `nullify'
4040 as it can nullify the delay slot and save a nop. */
4041 if (length == 8 && dbr_sequence_length () == 0)
4044 /* If this is a short forward conditional branch which did not get
4045 its delay slot filled, the delay slot can still be nullified. */
4046 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4047 nullify = forward_branch_p (insn);
4049 /* A forward branch over a single nullified insn can be done with a
4050 comclr instruction. This avoids a single cycle penalty due to
4051 mis-predicted branch if we fall through (branch not taken). */
4053 && next_real_insn (insn) != 0
4054 && get_attr_length (next_real_insn (insn)) == 4
4055 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4061 /* All short conditional branches except backwards with an unfilled
4065 strcpy (buf, "com%I2clr,");
4067 strcpy (buf, "com%I2b,");
4069 strcat (buf, "%B3");
4071 strcat (buf, "%S3");
4073 strcat (buf, " %2,%1,0");
4075 strcat (buf, ",n %2,%1,%0");
4077 strcat (buf, " %2,%1,%0");
4080 /* All long conditionals. Note an short backward branch with an
4081 unfilled delay slot is treated just like a long backward branch
4082 with an unfilled delay slot. */
4084 /* Handle weird backwards branch with a filled delay slot
4085 with is nullified. */
4086 if (dbr_sequence_length () != 0
4087 && ! forward_branch_p (insn)
4090 strcpy (buf, "com%I2b,");
4092 strcat (buf, "%S3");
4094 strcat (buf, "%B3");
4095 strcat (buf, ",n %2,%1,.+12\n\tbl %0,0");
4097 /* Handle short backwards branch with an unfilled delay slot.
4098 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
4099 taken and untaken branches. */
4100 else if (dbr_sequence_length () == 0
4101 && ! forward_branch_p (insn)
4103 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4104 - insn_addresses[INSN_UID (insn)] - 8))
4106 strcpy (buf, "com%I2b,");
4108 strcat (buf, "%B3 %2,%1,%0%#");
4110 strcat (buf, "%S3 %2,%1,%0%#");
4114 strcpy (buf, "com%I2clr,");
4116 strcat (buf, "%S3");
4118 strcat (buf, "%B3");
4120 strcat (buf, " %2,%1,0\n\tbl,n %0,0");
4122 strcat (buf, " %2,%1,0\n\tbl %0,0");
4132 /* This routine handles all the branch-on-bit conditional branch sequences we
4133 might need to generate. It handles nullification of delay slots,
4134 varying length branches, negated branches and all combinations of the
4135 above. it returns the appropriate output template to emit the branch. */
4138 output_bb (operands, nullify, length, negated, insn, which)
4140 int nullify, length, negated;
4144 static char buf[100];
4147 /* A conditional branch to the following instruction (eg the delay slot) is
4148 asking for a disaster. I do not think this can happen as this pattern
4149 is only used when optimizing; jump optimization should eliminate the
4150 jump. But be prepared just in case. */
4152 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4155 /* If this is a long branch with its delay slot unfilled, set `nullify'
4156 as it can nullify the delay slot and save a nop. */
4157 if (length == 8 && dbr_sequence_length () == 0)
4160 /* If this is a short forward conditional branch which did not get
4161 its delay slot filled, the delay slot can still be nullified. */
4162 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4163 nullify = forward_branch_p (insn);
4165 /* A forward branch over a single nullified insn can be done with a
4166 extrs instruction. This avoids a single cycle penalty due to
4167 mis-predicted branch if we fall through (branch not taken). */
4170 && next_real_insn (insn) != 0
4171 && get_attr_length (next_real_insn (insn)) == 4
4172 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4179 /* All short conditional branches except backwards with an unfilled
4183 strcpy (buf, "extrs,");
4185 strcpy (buf, "bb,");
4186 if ((which == 0 && negated)
4187 || (which == 1 && ! negated))
4192 strcat (buf, " %0,%1,1,0");
4193 else if (nullify && negated)
4194 strcat (buf, ",n %0,%1,%3");
4195 else if (nullify && ! negated)
4196 strcat (buf, ",n %0,%1,%2");
4197 else if (! nullify && negated)
4198 strcat (buf, "%0,%1,%3");
4199 else if (! nullify && ! negated)
4200 strcat (buf, " %0,%1,%2");
4203 /* All long conditionals. Note an short backward branch with an
4204 unfilled delay slot is treated just like a long backward branch
4205 with an unfilled delay slot. */
4207 /* Handle weird backwards branch with a filled delay slot
4208 with is nullified. */
4209 if (dbr_sequence_length () != 0
4210 && ! forward_branch_p (insn)
4213 strcpy (buf, "bb,");
4214 if ((which == 0 && negated)
4215 || (which == 1 && ! negated))
4220 strcat (buf, ",n %0,%1,.+12\n\tbl %3,0");
4222 strcat (buf, ",n %0,%1,.+12\n\tbl %2,0");
4224 /* Handle short backwards branch with an unfilled delay slot.
4225 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4226 taken and untaken branches. */
4227 else if (dbr_sequence_length () == 0
4228 && ! forward_branch_p (insn)
4230 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4231 - insn_addresses[INSN_UID (insn)] - 8))
4233 strcpy (buf, "bb,");
4234 if ((which == 0 && negated)
4235 || (which == 1 && ! negated))
4240 strcat (buf, " %0,%1,%3%#");
4242 strcat (buf, " %0,%1,%2%#");
4246 strcpy (buf, "extrs,");
4247 if ((which == 0 && negated)
4248 || (which == 1 && ! negated))
4252 if (nullify && negated)
4253 strcat (buf, " %0,%1,1,0\n\tbl,n %3,0");
4254 else if (nullify && ! negated)
4255 strcat (buf, " %0,%1,1,0\n\tbl,n %2,0");
4257 strcat (buf, " %0,%1,1,0\n\tbl %3,0");
4259 strcat (buf, " %0,%1,1,0\n\tbl %2,0");
4269 /* This routine handles all the branch-on-variable-bit conditional branch
4270 sequences we might need to generate. It handles nullification of delay
4271 slots, varying length branches, negated branches and all combinations
4272 of the above. it returns the appropriate output template to emit the
4276 output_bvb (operands, nullify, length, negated, insn, which)
4278 int nullify, length, negated;
4282 static char buf[100];
4285 /* A conditional branch to the following instruction (eg the delay slot) is
4286 asking for a disaster. I do not think this can happen as this pattern
4287 is only used when optimizing; jump optimization should eliminate the
4288 jump. But be prepared just in case. */
4290 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4293 /* If this is a long branch with its delay slot unfilled, set `nullify'
4294 as it can nullify the delay slot and save a nop. */
4295 if (length == 8 && dbr_sequence_length () == 0)
4298 /* If this is a short forward conditional branch which did not get
4299 its delay slot filled, the delay slot can still be nullified. */
4300 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4301 nullify = forward_branch_p (insn);
4303 /* A forward branch over a single nullified insn can be done with a
4304 extrs instruction. This avoids a single cycle penalty due to
4305 mis-predicted branch if we fall through (branch not taken). */
4308 && next_real_insn (insn) != 0
4309 && get_attr_length (next_real_insn (insn)) == 4
4310 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4317 /* All short conditional branches except backwards with an unfilled
4321 strcpy (buf, "vextrs,");
4323 strcpy (buf, "bvb,");
4324 if ((which == 0 && negated)
4325 || (which == 1 && ! negated))
4330 strcat (buf, " %0,1,0");
4331 else if (nullify && negated)
4332 strcat (buf, ",n %0,%3");
4333 else if (nullify && ! negated)
4334 strcat (buf, ",n %0,%2");
4335 else if (! nullify && negated)
4336 strcat (buf, "%0,%3");
4337 else if (! nullify && ! negated)
4338 strcat (buf, " %0,%2");
4341 /* All long conditionals. Note an short backward branch with an
4342 unfilled delay slot is treated just like a long backward branch
4343 with an unfilled delay slot. */
4345 /* Handle weird backwards branch with a filled delay slot
4346 with is nullified. */
4347 if (dbr_sequence_length () != 0
4348 && ! forward_branch_p (insn)
4351 strcpy (buf, "bvb,");
4352 if ((which == 0 && negated)
4353 || (which == 1 && ! negated))
4358 strcat (buf, ",n %0,.+12\n\tbl %3,0");
4360 strcat (buf, ",n %0,.+12\n\tbl %2,0");
4362 /* Handle short backwards branch with an unfilled delay slot.
4363 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4364 taken and untaken branches. */
4365 else if (dbr_sequence_length () == 0
4366 && ! forward_branch_p (insn)
4368 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4369 - insn_addresses[INSN_UID (insn)] - 8))
4371 strcpy (buf, "bvb,");
4372 if ((which == 0 && negated)
4373 || (which == 1 && ! negated))
4378 strcat (buf, " %0,%3%#");
4380 strcat (buf, " %0,%2%#");
4384 strcpy (buf, "vextrs,");
4385 if ((which == 0 && negated)
4386 || (which == 1 && ! negated))
4390 if (nullify && negated)
4391 strcat (buf, " %0,1,0\n\tbl,n %3,0");
4392 else if (nullify && ! negated)
4393 strcat (buf, " %0,1,0\n\tbl,n %2,0");
4395 strcat (buf, " %0,1,0\n\tbl %3,0");
4397 strcat (buf, " %0,1,0\n\tbl %2,0");
4407 /* Return the output template for emitting a dbra type insn.
4409 Note it may perform some output operations on its own before
4410 returning the final output string. */
4412 output_dbra (operands, insn, which_alternative)
4415 int which_alternative;
4418 /* A conditional branch to the following instruction (eg the delay slot) is
4419 asking for a disaster. Be prepared! */
4421 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4423 if (which_alternative == 0)
4424 return "ldo %1(%0),%0";
4425 else if (which_alternative == 1)
4427 output_asm_insn ("fstws %0,-16(0,%%r30)",operands);
4428 output_asm_insn ("ldw -16(0,%%r30),%4",operands);
4429 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands);
4430 return "fldws -16(0,%%r30),%0";
4434 output_asm_insn ("ldw %0,%4", operands);
4435 return "ldo %1(%4),%4\n\tstw %4,%0";
4439 if (which_alternative == 0)
4441 int nullify = INSN_ANNULLED_BRANCH_P (insn);
4442 int length = get_attr_length (insn);
4444 /* If this is a long branch with its delay slot unfilled, set `nullify'
4445 as it can nullify the delay slot and save a nop. */
4446 if (length == 8 && dbr_sequence_length () == 0)
4449 /* If this is a short forward conditional branch which did not get
4450 its delay slot filled, the delay slot can still be nullified. */
4451 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4452 nullify = forward_branch_p (insn);
4454 /* Handle short versions first. */
4455 if (length == 4 && nullify)
4456 return "addib,%C2,n %1,%0,%3";
4457 else if (length == 4 && ! nullify)
4458 return "addib,%C2 %1,%0,%3";
4459 else if (length == 8)
4461 /* Handle weird backwards branch with a fulled delay slot
4462 which is nullified. */
4463 if (dbr_sequence_length () != 0
4464 && ! forward_branch_p (insn)
4466 return "addib,%N2,n %1,%0,.+12\n\tbl %3,0";
4467 /* Handle short backwards branch with an unfilled delay slot.
4468 Using a addb;nop rather than addi;bl saves 1 cycle for both
4469 taken and untaken branches. */
4470 else if (dbr_sequence_length () == 0
4471 && ! forward_branch_p (insn)
4473 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4474 - insn_addresses[INSN_UID (insn)] - 8))
4475 return "addib,%C2 %1,%0,%3%#";
4477 /* Handle normal cases. */
4479 return "addi,%N2 %1,%0,%0\n\tbl,n %3,0";
4481 return "addi,%N2 %1,%0,%0\n\tbl %3,0";
4486 /* Deal with gross reload from FP register case. */
4487 else if (which_alternative == 1)
4489 /* Move loop counter from FP register to MEM then into a GR,
4490 increment the GR, store the GR into MEM, and finally reload
4491 the FP register from MEM from within the branch's delay slot. */
4492 output_asm_insn ("fstws %0,-16(0,%%r30)\n\tldw -16(0,%%r30),%4",operands);
4493 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands);
4494 if (get_attr_length (insn) == 24)
4495 return "comb,%S2 0,%4,%3\n\tfldws -16(0,%%r30),%0";
4497 return "comclr,%B2 0,%4,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
4499 /* Deal with gross reload from memory case. */
4502 /* Reload loop counter from memory, the store back to memory
4503 happens in the branch's delay slot. */
4504 output_asm_insn ("ldw %0,%4", operands);
4505 if (get_attr_length (insn) == 12)
4506 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
4508 return "addi,%N2 %1,%4,%4\n\tbl %3,0\n\tstw %4,%0";
4512 /* Return the output template for emitting a dbra type insn.
4514 Note it may perform some output operations on its own before
4515 returning the final output string. */
4517 output_movb (operands, insn, which_alternative, reverse_comparison)
4520 int which_alternative;
4521 int reverse_comparison;
4524 /* A conditional branch to the following instruction (eg the delay slot) is
4525 asking for a disaster. Be prepared! */
4527 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4529 if (which_alternative == 0)
4530 return "copy %1,%0";
4531 else if (which_alternative == 1)
4533 output_asm_insn ("stw %1,-16(0,%%r30)",operands);
4534 return "fldws -16(0,%%r30),%0";
4536 else if (which_alternative == 2)
4542 /* Support the second variant. */
4543 if (reverse_comparison)
4544 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
4546 if (which_alternative == 0)
4548 int nullify = INSN_ANNULLED_BRANCH_P (insn);
4549 int length = get_attr_length (insn);
4551 /* If this is a long branch with its delay slot unfilled, set `nullify'
4552 as it can nullify the delay slot and save a nop. */
4553 if (length == 8 && dbr_sequence_length () == 0)
4556 /* If this is a short forward conditional branch which did not get
4557 its delay slot filled, the delay slot can still be nullified. */
4558 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4559 nullify = forward_branch_p (insn);
4561 /* Handle short versions first. */
4562 if (length == 4 && nullify)
4563 return "movb,%C2,n %1,%0,%3";
4564 else if (length == 4 && ! nullify)
4565 return "movb,%C2 %1,%0,%3";
4566 else if (length == 8)
4568 /* Handle weird backwards branch with a filled delay slot
4569 which is nullified. */
4570 if (dbr_sequence_length () != 0
4571 && ! forward_branch_p (insn)
4573 return "movb,%N2,n %1,%0,.+12\n\tbl %3,0";
4575 /* Handle short backwards branch with an unfilled delay slot.
4576 Using a movb;nop rather than or;bl saves 1 cycle for both
4577 taken and untaken branches. */
4578 else if (dbr_sequence_length () == 0
4579 && ! forward_branch_p (insn)
4581 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4582 - insn_addresses[INSN_UID (insn)] - 8))
4583 return "movb,%C2 %1,%0,%3%#";
4584 /* Handle normal cases. */
4586 return "or,%N2 %1,%%r0,%0\n\tbl,n %3,0";
4588 return "or,%N2 %1,%%r0,%0\n\tbl %3,0";
4593 /* Deal with gross reload from FP register case. */
4594 else if (which_alternative == 1)
4596 /* Move loop counter from FP register to MEM then into a GR,
4597 increment the GR, store the GR into MEM, and finally reload
4598 the FP register from MEM from within the branch's delay slot. */
4599 output_asm_insn ("stw %1,-16(0,%%r30)",operands);
4600 if (get_attr_length (insn) == 12)
4601 return "comb,%S2 0,%1,%3\n\tfldws -16(0,%%r30),%0";
4603 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
4605 /* Deal with gross reload from memory case. */
4606 else if (which_alternative == 2)
4608 /* Reload loop counter from memory, the store back to memory
4609 happens in the branch's delay slot. */
4610 if (get_attr_length (insn) == 8)
4611 return "comb,%S2 0,%1,%3\n\tstw %1,%0";
4613 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tstw %1,%0";
4615 /* Handle SAR as a destination. */
4618 if (get_attr_length (insn) == 8)
4619 return "comb,%S2 0,%1,%3\n\tmtsar %r1";
4621 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tmtsar %r1";
4626 /* INSN is a millicode call. It may have an unconditional jump in its delay
4629 CALL_DEST is the routine we are calling. */
4632 output_millicode_call (insn, call_dest)
4640 /* Handle common case -- empty delay slot or no jump in the delay slot,
4641 and we're sure that the branch will reach the beginning of the $CODE$
4643 if ((dbr_sequence_length () == 0
4644 && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
4645 || (dbr_sequence_length () != 0
4646 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
4647 && get_attr_length (insn) == 4))
4649 xoperands[0] = call_dest;
4650 output_asm_insn ("bl %0,%%r31%#", xoperands);
4654 /* This call may not reach the beginning of the $CODE$ subspace. */
4655 if (get_attr_length (insn) > 4)
4657 int delay_insn_deleted = 0;
4661 /* We need to emit an inline long-call branch. */
4662 if (dbr_sequence_length () != 0
4663 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
4665 /* A non-jump insn in the delay slot. By definition we can
4666 emit this insn before the call. */
4667 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
4669 /* Now delete the delay insn. */
4670 PUT_CODE (NEXT_INSN (insn), NOTE);
4671 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
4672 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
4673 delay_insn_deleted = 1;
4676 /* If we're allowed to use be/ble instructions, then this is the
4677 best sequence to use for a long millicode call. */
4678 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS
4679 || ! (flag_pic || TARGET_PORTABLE_RUNTIME))
4681 xoperands[0] = call_dest;
4682 output_asm_insn ("ldil L%%%0,%%r31", xoperands);
4683 output_asm_insn ("ble R%%%0(%%sr4,%%r31)", xoperands);
4684 output_asm_insn ("nop", xoperands);
4686 /* Pure portable runtime doesn't allow be/ble; we also don't have
4687 PIC support int he assembler/linker, so this sequence is needed. */
4688 else if (TARGET_PORTABLE_RUNTIME)
4690 xoperands[0] = call_dest;
4691 /* Get the address of our target into %r29. */
4692 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
4693 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
4695 /* Get our return address into %r31. */
4696 output_asm_insn ("blr 0,%%r31", xoperands);
4698 /* Jump to our target address in %r29. */
4699 output_asm_insn ("bv,n 0(%%r29)", xoperands);
4701 /* Empty delay slot. Note this insn gets fetched twice and
4702 executed once. To be safe we use a nop. */
4703 output_asm_insn ("nop", xoperands);
4706 /* PIC long millicode call sequence. */
4709 xoperands[0] = call_dest;
4710 xoperands[1] = gen_label_rtx ();
4711 /* Get our address + 8 into %r1. */
4712 output_asm_insn ("bl .+8,%%r1", xoperands);
4714 /* Add %r1 to the offset of our target from the next insn. */
4715 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
4716 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4717 CODE_LABEL_NUMBER (xoperands[1]));
4718 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
4720 /* Get the return address into %r31. */
4721 output_asm_insn ("blr 0,%%r31", xoperands);
4723 /* Branch to our target which is in %r1. */
4724 output_asm_insn ("bv,n 0(%%r1)", xoperands);
4726 /* Empty delay slot. Note this insn gets fetched twice and
4727 executed once. To be safe we use a nop. */
4728 output_asm_insn ("nop", xoperands);
4731 /* If we had a jump in the call's delay slot, output it now. */
4732 if (dbr_sequence_length () != 0
4733 && !delay_insn_deleted)
4735 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
4736 output_asm_insn ("b,n %0", xoperands);
4738 /* Now delete the delay insn. */
4739 PUT_CODE (NEXT_INSN (insn), NOTE);
4740 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
4741 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
4746 /* This call has an unconditional jump in its delay slot and the
4747 call is known to reach its target or the beginning of the current
4750 /* Use the containing sequence insn's address. */
4751 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
4753 distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
4754 - insn_addresses[INSN_UID (seq_insn)] - 8;
4756 /* If the branch was too far away, emit a normal call followed
4757 by a nop, followed by the unconditional branch.
4759 If the branch is close, then adjust %r2 from within the
4760 call's delay slot. */
4762 xoperands[0] = call_dest;
4763 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
4764 if (! VAL_14_BITS_P (distance))
4765 output_asm_insn ("bl %0,%%r31\n\tnop\n\tbl,n %1,%%r0", xoperands);
4768 xoperands[3] = gen_label_rtx ();
4769 output_asm_insn ("\n\tbl %0,%%r31\n\tldo %1-%3(%%r31),%%r31", xoperands);
4770 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4771 CODE_LABEL_NUMBER (xoperands[3]));
4774 /* Delete the jump. */
4775 PUT_CODE (NEXT_INSN (insn), NOTE);
4776 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
4777 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
4781 /* INSN is either a function call. It may have an unconditional jump
4784 CALL_DEST is the routine we are calling. */
4787 output_call (insn, call_dest)
4795 /* Handle common case -- empty delay slot or no jump in the delay slot,
4796 and we're sure that the branch will reach the beginning of the $CODE$
4798 if ((dbr_sequence_length () == 0
4799 && get_attr_length (insn) == 8)
4800 || (dbr_sequence_length () != 0
4801 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
4802 && get_attr_length (insn) == 4))
4804 xoperands[0] = call_dest;
4805 output_asm_insn ("bl %0,%%r2%#", xoperands);
4809 /* This call may not reach the beginning of the $CODE$ subspace. */
4810 if (get_attr_length (insn) > 8)
4812 int delay_insn_deleted = 0;
4816 /* We need to emit an inline long-call branch. Furthermore,
4817 because we're changing a named function call into an indirect
4818 function call well after the parameters have been set up, we
4819 need to make sure any FP args appear in both the integer
4820 and FP registers. Also, we need move any delay slot insn
4821 out of the delay slot. And finally, we can't rely on the linker
4822 being able to fix the call to $$dyncall! -- Yuk!. */
4823 if (dbr_sequence_length () != 0
4824 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
4826 /* A non-jump insn in the delay slot. By definition we can
4827 emit this insn before the call (and in fact before argument
4829 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
4831 /* Now delete the delay insn. */
4832 PUT_CODE (NEXT_INSN (insn), NOTE);
4833 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
4834 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
4835 delay_insn_deleted = 1;
4838 /* Now copy any FP arguments into integer registers. */
4839 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
4841 int arg_mode, regno;
4842 rtx use = XEXP (link, 0);
4843 if (! (GET_CODE (use) == USE
4844 && GET_CODE (XEXP (use, 0)) == REG
4845 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4848 arg_mode = GET_MODE (XEXP (use, 0));
4849 regno = REGNO (XEXP (use, 0));
4850 /* Is it a floating point register? */
4851 if (regno >= 32 && regno <= 39)
4853 /* Copy from the FP register into an integer register
4855 if (arg_mode == SFmode)
4857 xoperands[0] = XEXP (use, 0);
4858 xoperands[1] = gen_rtx (REG, SImode, 26 - (regno - 32) / 2);
4859 output_asm_insn ("fstws %0,-16(%%sr0,%%r30)", xoperands);
4860 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
4864 xoperands[0] = XEXP (use, 0);
4865 xoperands[1] = gen_rtx (REG, DImode, 25 - (regno - 34) / 2);
4866 output_asm_insn ("fstds %0,-16(%%sr0,%%r30)", xoperands);
4867 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
4868 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
4874 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
4875 we don't have any direct calls in that case. */
4878 /* We have to load the address of the function using a procedure
4879 label (plabel). The LP and RP relocs don't work reliably for PIC,
4880 so we make a plain 32 bit plabel in the data segment instead. We
4881 have to defer outputting it of course... Not pretty. */
4883 xoperands[0] = gen_label_rtx ();
4884 xoperands[1] = gen_label_rtx ();
4885 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
4886 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
4887 output_asm_insn ("ldw 0(0,%%r22),%%r22", xoperands);
4889 if (deferred_plabels == 0)
4890 deferred_plabels = (struct defer_plab *)
4891 xmalloc (1 * sizeof (struct defer_plab));
4893 deferred_plabels = (struct defer_plab *)
4894 xrealloc (deferred_plabels,
4895 (n_deferred_plabels + 1) * sizeof (struct defer_plab));
4896 deferred_plabels[n_deferred_plabels].internal_label = xoperands[0];
4897 deferred_plabels[n_deferred_plabels].symbol = call_dest;
4898 n_deferred_plabels++;
4900 /* Get our address + 8 into %r1. */
4901 output_asm_insn ("bl .+8,%%r1", xoperands);
4903 /* Add %r1 to the offset of dyncall from the next insn. */
4904 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
4905 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4906 CODE_LABEL_NUMBER (xoperands[1]));
4907 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
4909 /* Get the return address into %r31. */
4910 output_asm_insn ("blr 0,%%r31", xoperands);
4912 /* Branch to our target which is in %r1. */
4913 output_asm_insn ("bv 0(%%r1)", xoperands);
4915 /* Copy the return address into %r2 also. */
4916 output_asm_insn ("copy %%r31,%%r2", xoperands);
4920 /* No PIC stuff to worry about. We can use ldil;ble. */
4921 xoperands[0] = call_dest;
4923 /* Get the address of our target into %r22. */
4924 output_asm_insn ("ldil LP%%%0,%%r22", xoperands);
4925 output_asm_insn ("ldo RP%%%0(%%r22),%%r22", xoperands);
4927 /* Get the high part of the address of $dyncall into %r2, then
4928 add in the low part in the branch instruction. */
4929 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
4930 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands);
4932 /* Copy the return pointer into both %r31 and %r2. */
4933 output_asm_insn ("copy %%r31,%%r2", xoperands);
4936 /* If we had a jump in the call's delay slot, output it now. */
4937 if (dbr_sequence_length () != 0
4938 && !delay_insn_deleted)
4940 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
4941 output_asm_insn ("b,n %0", xoperands);
4943 /* Now delete the delay insn. */
4944 PUT_CODE (NEXT_INSN (insn), NOTE);
4945 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
4946 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
4951 /* This call has an unconditional jump in its delay slot and the
4952 call is known to reach its target or the beginning of the current
4955 /* Use the containing sequence insn's address. */
4956 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
4958 distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
4959 - insn_addresses[INSN_UID (seq_insn)] - 8;
4961 /* If the branch was too far away, emit a normal call followed
4962 by a nop, followed by the unconditional branch.
4964 If the branch is close, then adjust %r2 from within the
4965 call's delay slot. */
4967 xoperands[0] = call_dest;
4968 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
4969 if (! VAL_14_BITS_P (distance))
4970 output_asm_insn ("bl %0,%%r2\n\tnop\n\tbl,n %1,%%r0", xoperands);
4973 xoperands[3] = gen_label_rtx ();
4974 output_asm_insn ("\n\tbl %0,%%r2\n\tldo %1-%3(%%r2),%%r2", xoperands);
4975 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4976 CODE_LABEL_NUMBER (xoperands[3]));
4979 /* Delete the jump. */
4980 PUT_CODE (NEXT_INSN (insn), NOTE);
4981 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
4982 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
4986 extern struct obstack permanent_obstack;
4987 extern struct obstack *saveable_obstack;
4989 /* In HPUX 8.0's shared library scheme, special relocations are needed
4990 for function labels if they might be passed to a function
4991 in a shared library (because shared libraries don't live in code
4992 space), and special magic is needed to construct their address.
4994 For reasons too disgusting to describe storage for the new name
4995 is allocated either on the saveable_obstack (released at function
4996 exit) or on the permanent_obstack for things that can never change
4997 (libcall names for example). */
5000 hppa_encode_label (sym, permanent)
5004 char *str = XSTR (sym, 0);
5005 int len = strlen (str);
5008 newstr = obstack_alloc ((permanent ? &permanent_obstack : saveable_obstack),
5013 strcpy (newstr + 1, str);
5015 XSTR (sym,0) = newstr;
5019 function_label_operand (op, mode)
5021 enum machine_mode mode;
5023 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
5026 /* Returns 1 if OP is a function label involved in a simple addition
5027 with a constant. Used to keep certain patterns from matching
5028 during instruction combination. */
5030 is_function_label_plus_const (op)
5033 /* Strip off any CONST. */
5034 if (GET_CODE (op) == CONST)
5037 return (GET_CODE (op) == PLUS
5038 && function_label_operand (XEXP (op, 0), Pmode)
5039 && GET_CODE (XEXP (op, 1)) == CONST_INT);
5042 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5043 use in fmpyadd instructions. */
5045 fmpyaddoperands (operands)
5048 enum machine_mode mode = GET_MODE (operands[0]);
5050 /* Must be a floating point mode. */
5051 if (mode != SFmode && mode != DFmode)
5054 /* All modes must be the same. */
5055 if (! (mode == GET_MODE (operands[1])
5056 && mode == GET_MODE (operands[2])
5057 && mode == GET_MODE (operands[3])
5058 && mode == GET_MODE (operands[4])
5059 && mode == GET_MODE (operands[5])))
5062 /* All operands must be registers. */
5063 if (! (GET_CODE (operands[1]) == REG
5064 && GET_CODE (operands[2]) == REG
5065 && GET_CODE (operands[3]) == REG
5066 && GET_CODE (operands[4]) == REG
5067 && GET_CODE (operands[5]) == REG))
5070 /* Only 2 real operands to the addition. One of the input operands must
5071 be the same as the output operand. */
5072 if (! rtx_equal_p (operands[3], operands[4])
5073 && ! rtx_equal_p (operands[3], operands[5]))
5076 /* Inout operand of add can not conflict with any operands from multiply. */
5077 if (rtx_equal_p (operands[3], operands[0])
5078 || rtx_equal_p (operands[3], operands[1])
5079 || rtx_equal_p (operands[3], operands[2]))
5082 /* multiply can not feed into addition operands. */
5083 if (rtx_equal_p (operands[4], operands[0])
5084 || rtx_equal_p (operands[5], operands[0]))
5087 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5089 && (REGNO (operands[0]) < 57
5090 || REGNO (operands[1]) < 57
5091 || REGNO (operands[2]) < 57
5092 || REGNO (operands[3]) < 57
5093 || REGNO (operands[4]) < 57
5094 || REGNO (operands[5]) < 57))
5097 /* Passed. Operands are suitable for fmpyadd. */
5101 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5102 use in fmpysub instructions. */
5104 fmpysuboperands (operands)
5107 enum machine_mode mode = GET_MODE (operands[0]);
5109 /* Must be a floating point mode. */
5110 if (mode != SFmode && mode != DFmode)
5113 /* All modes must be the same. */
5114 if (! (mode == GET_MODE (operands[1])
5115 && mode == GET_MODE (operands[2])
5116 && mode == GET_MODE (operands[3])
5117 && mode == GET_MODE (operands[4])
5118 && mode == GET_MODE (operands[5])))
5121 /* All operands must be registers. */
5122 if (! (GET_CODE (operands[1]) == REG
5123 && GET_CODE (operands[2]) == REG
5124 && GET_CODE (operands[3]) == REG
5125 && GET_CODE (operands[4]) == REG
5126 && GET_CODE (operands[5]) == REG))
5129 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
5130 operation, so operands[4] must be the same as operand[3]. */
5131 if (! rtx_equal_p (operands[3], operands[4]))
5134 /* multiply can not feed into subtraction. */
5135 if (rtx_equal_p (operands[5], operands[0]))
5138 /* Inout operand of sub can not conflict with any operands from multiply. */
5139 if (rtx_equal_p (operands[3], operands[0])
5140 || rtx_equal_p (operands[3], operands[1])
5141 || rtx_equal_p (operands[3], operands[2]))
5144 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5146 && (REGNO (operands[0]) < 57
5147 || REGNO (operands[1]) < 57
5148 || REGNO (operands[2]) < 57
5149 || REGNO (operands[3]) < 57
5150 || REGNO (operands[4]) < 57
5151 || REGNO (operands[5]) < 57))
5154 /* Passed. Operands are suitable for fmpysub. */
5159 plus_xor_ior_operator (op, mode)
5161 enum machine_mode mode;
5163 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
5164 || GET_CODE (op) == IOR);
5167 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
5168 constants for shadd instructions. */
5170 shadd_constant_p (val)
5173 if (val == 2 || val == 4 || val == 8)
5179 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
5180 the valid constant for shadd instructions. */
5182 shadd_operand (op, mode)
5184 enum machine_mode mode;
5186 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
5189 /* Return 1 if OP is valid as a base register in a reg + reg address. */
5192 basereg_operand (op, mode)
5194 enum machine_mode mode;
5196 /* cse will create some unscaled indexed addresses, however; it
5197 generally isn't a win on the PA, so avoid creating unscaled
5198 indexed addresses until after cse is finished. */
5199 if (!cse_not_expected)
5202 /* Once reload has started everything is considered valid. Reload should
5203 only create indexed addresses using the stack/frame pointer, and any
5204 others were checked for validity when created by the combine pass.
5206 Also allow any register when TARGET_NO_SPACE_REGS is in effect since
5207 we don't have to worry about the braindamaged implicit space register
5208 selection using the basereg only (rather than effective address)
5209 screwing us over. */
5210 if (TARGET_NO_SPACE_REGS || reload_in_progress || reload_completed)
5211 return (GET_CODE (op) == REG);
5213 /* Stack is always OK for indexing. */
5214 if (op == stack_pointer_rtx)
5217 /* While it's always safe to index off the frame pointer, it's not
5218 always profitable, particularly when the frame pointer is being
5220 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
5223 /* The only other valid OPs are pseudo registers with
5224 REGNO_POINTER_FLAG set. */
5225 if (GET_CODE (op) != REG
5226 || REGNO (op) < FIRST_PSEUDO_REGISTER
5227 || ! register_operand (op, mode))
5230 return REGNO_POINTER_FLAG (REGNO (op));
5233 /* Return 1 if this operand is anything other than a hard register. */
5236 non_hard_reg_operand (op, mode)
5238 enum machine_mode mode;
5240 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
5243 /* Return 1 if INSN branches forward. Should be using insn_addresses
5244 to avoid walking through all the insns... */
5246 forward_branch_p (insn)
5249 rtx label = JUMP_LABEL (insn);
5256 insn = NEXT_INSN (insn);
5259 return (insn == label);
5262 /* Return 1 if OP is an equality comparison, else return 0. */
5264 eq_neq_comparison_operator (op, mode)
5266 enum machine_mode mode;
5268 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
5271 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
5273 movb_comparison_operator (op, mode)
5275 enum machine_mode mode;
5277 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
5278 || GET_CODE (op) == LT || GET_CODE (op) == GE);
5281 /* Return 1 if INSN is in the delay slot of a call instruction. */
5283 jump_in_call_delay (insn)
5287 if (GET_CODE (insn) != JUMP_INSN)
5290 if (PREV_INSN (insn)
5291 && PREV_INSN (PREV_INSN (insn))
5292 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
5294 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
5296 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
5297 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
5304 /* Output an unconditional move and branch insn. */
5307 output_parallel_movb (operands, length)
5311 /* These are the cases in which we win. */
5313 return "mov%I1b,tr %1,%0,%2";
5315 /* None of these cases wins, but they don't lose either. */
5316 if (dbr_sequence_length () == 0)
5318 /* Nothing in the delay slot, fake it by putting the combined
5319 insn (the copy or add) in the delay slot of a bl. */
5320 if (GET_CODE (operands[1]) == CONST_INT)
5321 return "bl %2,0\n\tldi %1,%0";
5323 return "bl %2,0\n\tcopy %1,%0";
5327 /* Something in the delay slot, but we've got a long branch. */
5328 if (GET_CODE (operands[1]) == CONST_INT)
5329 return "ldi %1,%0\n\tbl %2,0";
5331 return "copy %1,%0\n\tbl %2,0";
5335 /* Output an unconditional add and branch insn. */
5338 output_parallel_addb (operands, length)
5342 /* To make life easy we want operand0 to be the shared input/output
5343 operand and operand1 to be the readonly operand. */
5344 if (operands[0] == operands[1])
5345 operands[1] = operands[2];
5347 /* These are the cases in which we win. */
5349 return "add%I1b,tr %1,%0,%3";
5351 /* None of these cases win, but they don't lose either. */
5352 if (dbr_sequence_length () == 0)
5354 /* Nothing in the delay slot, fake it by putting the combined
5355 insn (the copy or add) in the delay slot of a bl. */
5356 return "bl %3,0\n\tadd%I1 %1,%0,%0";
5360 /* Something in the delay slot, but we've got a long branch. */
5361 return "add%I1 %1,%0,%0\n\tbl %3,0";
5365 /* Return nonzero if INSN represents an integer add which might be
5366 combinable with an unconditional branch. */
5368 combinable_add (insn)
5371 rtx src, dest, prev, pattern = PATTERN (insn);
5373 /* Must be a (set (reg) (plus (reg) (reg/5_bit_int))) */
5374 if (GET_CODE (pattern) != SET
5375 || GET_CODE (SET_SRC (pattern)) != PLUS
5376 || GET_CODE (SET_DEST (pattern)) != REG)
5379 src = SET_SRC (pattern);
5380 dest = SET_DEST (pattern);
5382 /* Must be an integer add. */
5383 if (GET_MODE (src) != SImode
5384 || GET_MODE (dest) != SImode)
5387 /* Each operand must be an integer register and/or 5 bit immediate. */
5388 if (!ireg_or_int5_operand (dest, VOIDmode)
5389 || !ireg_or_int5_operand (XEXP (src, 0), VOIDmode)
5390 || !ireg_or_int5_operand (XEXP (src, 1), VOIDmode))
5393 /* The destination must also be one of the sources. */
5394 return (dest == XEXP (src, 0) || dest == XEXP (src, 1));
5397 /* Return nonzero if INSN represents an integer load/copy which might be
5398 combinable with an unconditional branch. */
5400 combinable_copy (insn)
5403 rtx src, dest, pattern = PATTERN (insn);
5404 enum machine_mode mode;
5406 /* Must be a (set (reg) (reg/5_bit_int)). */
5407 if (GET_CODE (pattern) != SET)
5410 src = SET_SRC (pattern);
5411 dest = SET_DEST (pattern);
5413 /* Must be a mode that corresponds to a single integer register. */
5414 mode = GET_MODE (dest);
5421 /* Each operand must be a register or 5 bit integer. */
5422 if (!ireg_or_int5_operand (dest, VOIDmode)
5423 || !ireg_or_int5_operand (src, VOIDmode))
5429 /* Return nonzero if INSN (a jump insn) immediately follows a call. This
5430 is used to discourage creating parallel movb/addb insns since a jump
5431 which immediately follows a call can execute in the delay slot of the
5434 following_call (insn)
5437 /* Find the previous real insn, skipping NOTEs. */
5438 insn = PREV_INSN (insn);
5439 while (insn && GET_CODE (insn) == NOTE)
5440 insn = PREV_INSN (insn);
5442 /* Check for CALL_INSNs and millicode calls. */
5444 && (GET_CODE (insn) == CALL_INSN
5445 || (GET_CODE (insn) == INSN
5446 && GET_CODE (PATTERN (insn)) != SEQUENCE
5447 && GET_CODE (PATTERN (insn)) != USE
5448 && GET_CODE (PATTERN (insn)) != CLOBBER
5449 && get_attr_type (insn) == TYPE_MILLI)))
5455 /* Return nonzero if this is a floating point multiply (fmpy) which
5456 could be combined with a suitable floating point add or sub insn. */
5458 combinable_fmpy (insn)
5461 rtx src, dest, pattern = PATTERN (insn);
5462 enum machine_mode mode;
5464 /* Only on 1.1 and later cpus. */
5468 /* Must be a (set (reg) (mult (reg) (reg))). */
5469 if (GET_CODE (pattern) != SET
5470 || GET_CODE (SET_SRC (pattern)) != MULT
5471 || GET_CODE (SET_DEST (pattern)) != REG)
5474 src = SET_SRC (pattern);
5475 dest = SET_DEST (pattern);
5477 /* Must be registers. */
5478 if (GET_CODE (XEXP (src, 0)) != REG
5479 || GET_CODE (XEXP (src, 1)) != REG)
5482 /* Must be a floating point mode. Must match the mode of the fmul. */
5483 mode = GET_MODE (dest);
5484 if (mode != DFmode && mode != SFmode)
5487 /* SFmode limits the registers which can be used to the upper
5488 32 32bit FP registers. */
5490 && (REGNO (dest) < 57
5491 || REGNO (XEXP (src, 0)) < 57
5492 || REGNO (XEXP (src, 1)) < 57))
5495 /* Save our operands, we'll need to verify they don't conflict with
5496 those in the fadd or fsub. XXX This needs to disasppear soon. */
5497 fmpy_operands[0] = dest;
5498 fmpy_operands[1] = XEXP (src, 0);
5499 fmpy_operands[2] = XEXP (src, 1);
5504 /* Return nonzero if INSN is a floating point add suitable for combining
5505 with the most recently examined floating point multiply. */
5507 combinable_fadd (insn)
5510 rtx src, dest, pattern = PATTERN (insn);
5511 enum machine_mode mode;
5513 /* Must be a (set (reg) (plus (reg) (reg))). */
5514 if (GET_CODE (pattern) != SET
5515 || GET_CODE (SET_SRC (pattern)) != PLUS
5516 || GET_CODE (SET_DEST (pattern)) != REG)
5519 src = SET_SRC (pattern);
5520 dest = SET_DEST (pattern);
5522 /* Must be registers. */
5523 if (GET_CODE (XEXP (src, 0)) != REG
5524 || GET_CODE (XEXP (src, 1)) != REG)
5527 /* Must be a floating point mode. Must match the mode of the fmul. */
5528 mode = GET_MODE (dest);
5529 if (mode != DFmode && mode != SFmode)
5532 if (mode != GET_MODE (fmpy_operands[0]))
5535 /* SFmode limits the registers which can be used to the upper
5536 32 32bit FP registers. */
5538 && (REGNO (dest) < 57
5539 || REGNO (XEXP (src, 0)) < 57
5540 || REGNO (XEXP (src, 1)) < 57))
5543 /* Only 2 real operands to the addition. One of the input operands
5544 must be the same as the output operand. */
5545 if (! rtx_equal_p (dest, XEXP (src, 0))
5546 && ! rtx_equal_p (dest, XEXP (src, 1)))
5549 /* Inout operand of the add can not conflict with any operands from the
5551 if (rtx_equal_p (dest, fmpy_operands[0])
5552 || rtx_equal_p (dest, fmpy_operands[1])
5553 || rtx_equal_p (dest, fmpy_operands[2]))
5556 /* The multiply can not feed into the addition. */
5557 if (rtx_equal_p (fmpy_operands[0], XEXP (src, 0))
5558 || rtx_equal_p (fmpy_operands[0], XEXP (src, 1)))
5564 /* Return nonzero if INSN is a floating point sub suitable for combining
5565 with the most recently examined floating point multiply. */
5567 combinable_fsub (insn)
5570 rtx src, dest, pattern = PATTERN (insn);
5571 enum machine_mode mode;
5573 /* Must be (set (reg) (minus (reg) (reg))). */
5574 if (GET_CODE (pattern) != SET
5575 || GET_CODE (SET_SRC (pattern)) != MINUS
5576 || GET_CODE (SET_DEST (pattern)) != REG)
5579 src = SET_SRC (pattern);
5580 dest = SET_DEST (pattern);
5582 if (GET_CODE (XEXP (src, 0)) != REG
5583 || GET_CODE (XEXP (src, 1)) != REG)
5586 /* Must be a floating point mode. Must match the mode of the fmul. */
5587 mode = GET_MODE (dest);
5588 if (mode != DFmode && mode != SFmode)
5591 if (mode != GET_MODE (fmpy_operands[0]))
5594 /* SFmode limits the registers which can be used to the upper
5595 32 32bit FP registers. */
5596 if (mode == SFmode && (REGNO (dest) < 57 || REGNO (XEXP (src, 1)) < 57))
5599 /* Only 2 real operands to the subtraction. Output must be the
5600 same as the first operand of the MINUS. */
5601 if (! rtx_equal_p (dest, XEXP (src, 0)))
5604 /* Inout operand of the sub can not conflict with any operands from the
5606 if (rtx_equal_p (dest, fmpy_operands[0])
5607 || rtx_equal_p (dest, fmpy_operands[1])
5608 || rtx_equal_p (dest, fmpy_operands[2]))
5611 /* The multiply can not feed into the subtraction. */
5612 if (rtx_equal_p (fmpy_operands[0], XEXP (src, 0))
5613 || rtx_equal_p (fmpy_operands[0], XEXP (src, 1)))
5619 /* We use this hook to perform a PA specific optimization which is difficult
5620 to do in earlier passes.
5622 We want the delay slots of branches within jump tables to be filled.
5623 None of the compiler passes at the moment even has the notion that a
5624 PA jump table doesn't contain addresses, but instead contains actual
5627 Because we actually jump into the table, the addresses of each entry
5628 must stay constant in relation to the beginning of the table (which
5629 itself must stay constant relative to the instruction to jump into
5630 it). I don't believe we can guarantee earlier passes of the compiler
5631 will adhere to those rules.
5633 So, late in the compilation process we find all the jump tables, and
5634 expand them into real code -- eg each entry in the jump table vector
5635 will get an appropriate label followed by a jump to the final target.
5637 Reorg and the final jump pass can then optimize these branches and
5638 fill their delay slots. We end up with smaller, more efficient code.
5640 The jump instructions within the table are special; we must be able
5641 to identify them during assembly output (if the jumps don't get filled
5642 we need to emit a nop rather than nullifying the delay slot)). We
5643 identify jumps in switch tables by marking the SET with DImode. */
5650 remove_useless_addtr_insns (insns, 1);
5652 /* This is fairly cheap, so always run it if optimizing. */
5655 /* Find and explode all ADDR_VEC insns. */
5656 insns = get_insns ();
5657 for (insn = insns; insn; insn = NEXT_INSN (insn))
5659 rtx pattern, tmp, location;
5660 unsigned int length, i;
5662 /* Find an ADDR_VEC insn to explode. */
5663 if (GET_CODE (insn) != JUMP_INSN
5664 || GET_CODE (PATTERN (insn)) != ADDR_VEC)
5667 /* If needed, emit marker for the beginning of the branch table. */
5669 emit_insn_before (gen_begin_brtab (), insn);
5671 pattern = PATTERN (insn);
5672 location = PREV_INSN (insn);
5673 length = XVECLEN (pattern, 0);
5675 for (i = 0; i < length; i++)
5677 /* Emit the jump itself. */
5678 tmp = gen_switch_jump (XEXP (XVECEXP (pattern, 0, i), 0));
5679 tmp = emit_jump_insn_after (tmp, location);
5680 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
5681 LABEL_NUSES (JUMP_LABEL (tmp))++;
5683 /* Emit a BARRIER after the jump. */
5684 location = NEXT_INSN (location);
5685 emit_barrier_after (location);
5687 /* Put a CODE_LABEL before each so jump.c does not optimize
5689 location = NEXT_INSN (location);
5690 tmp = gen_label_rtx ();
5691 LABEL_NUSES (tmp) = 1;
5692 emit_label_after (tmp, location);
5693 location = NEXT_INSN (location);
5696 /* If needed, emit marker for the end of the branch table. */
5698 emit_insn_before (gen_end_brtab (), location);
5699 /* Delete the ADDR_VEC. */
5703 else if (TARGET_GAS)
5705 /* Sill need an end_brtab insn. */
5706 insns = get_insns ();
5707 for (insn = insns; insn; insn = NEXT_INSN (insn))
5709 /* Find an ADDR_VEC insn. */
5710 if (GET_CODE (insn) != JUMP_INSN
5711 || GET_CODE (PATTERN (insn)) != ADDR_VEC)
5714 /* Now generate markers for the beginning and end of the
5716 emit_insn_before (gen_begin_brtab (), insn);
5717 emit_insn_after (gen_end_brtab (), insn);