1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
41 #include "integrate.h"
50 #include "target-def.h"
52 static int hppa_use_dfa_pipeline_interface PARAMS ((void));
54 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
55 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
58 hppa_use_dfa_pipeline_interface ()
63 /* Return nonzero if there is a bypass for the output of
64 OUT_INSN and the fp store IN_INSN. */
66 hppa_fpstore_bypass_p (out_insn, in_insn)
67 rtx out_insn, in_insn;
69 enum machine_mode store_mode;
70 enum machine_mode other_mode;
73 if (recog_memoized (in_insn) < 0
74 || get_attr_type (in_insn) != TYPE_FPSTORE
75 || recog_memoized (out_insn) < 0)
78 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
80 set = single_set (out_insn);
84 other_mode = GET_MODE (SET_SRC (set));
86 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
90 #ifndef DO_FRAME_NOTES
91 #ifdef INCOMING_RETURN_ADDR_RTX
92 #define DO_FRAME_NOTES 1
94 #define DO_FRAME_NOTES 0
98 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
99 static void pa_combine_instructions PARAMS ((rtx));
100 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
101 static int forward_branch_p PARAMS ((rtx));
102 static int shadd_constant_p PARAMS ((int));
103 static void pa_add_gc_roots PARAMS ((void));
104 static void mark_deferred_plabels PARAMS ((void *));
105 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
106 static int compute_movstrsi_length PARAMS ((rtx));
107 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
108 static void remove_useless_addtr_insns PARAMS ((rtx, int));
109 static void store_reg PARAMS ((int, int, int));
110 static void store_reg_modify PARAMS ((int, int, int));
111 static void load_reg PARAMS ((int, int, int));
112 static void set_reg_plus_d PARAMS ((int, int, int, int));
113 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
114 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
115 static int pa_adjust_priority PARAMS ((rtx, int));
116 static int pa_issue_rate PARAMS ((void));
118 /* Save the operands last given to a compare for use when we
119 generate a scc or bcc insn. */
121 rtx hppa_compare_op0, hppa_compare_op1;
122 enum cmp_type hppa_branch_type;
124 /* Which cpu we are scheduling for. */
125 enum processor_type pa_cpu;
127 /* String to hold which cpu we are scheduling for. */
128 const char *pa_cpu_string;
130 /* Which architecture we are generating code for. */
131 enum architecture_type pa_arch;
133 /* String to hold which architecture we are generating code for. */
134 const char *pa_arch_string;
136 /* Counts for the number of callee-saved general and floating point
137 registers which were saved by the current function's prologue. */
138 static int gr_saved, fr_saved;
140 static rtx find_addr_reg PARAMS ((rtx));
142 /* Keep track of the number of bytes we have output in the CODE subspaces
143 during this compilation so we'll know when to emit inline long-calls. */
145 unsigned int total_code_bytes;
147 /* Variables to handle plabels that we discover are necessary at assembly
148 output time. They are output after the current function. */
150 struct deferred_plabel
154 } *deferred_plabels = 0;
155 int n_deferred_plabels = 0;
157 /* Initialize the GCC target structure. */
159 #undef TARGET_ASM_ALIGNED_HI_OP
160 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
161 #undef TARGET_ASM_ALIGNED_SI_OP
162 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
163 #undef TARGET_ASM_ALIGNED_DI_OP
164 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
165 #undef TARGET_ASM_UNALIGNED_HI_OP
166 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
167 #undef TARGET_ASM_UNALIGNED_SI_OP
168 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
169 #undef TARGET_ASM_UNALIGNED_DI_OP
170 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
171 #undef TARGET_ASM_INTEGER
172 #define TARGET_ASM_INTEGER pa_assemble_integer
174 #undef TARGET_ASM_FUNCTION_PROLOGUE
175 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
176 #undef TARGET_ASM_FUNCTION_EPILOGUE
177 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
179 #undef TARGET_SCHED_ADJUST_COST
180 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
181 #undef TARGET_SCHED_ADJUST_PRIORITY
182 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
183 #undef TARGET_SCHED_ISSUE_RATE
184 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
186 struct gcc_target targetm = TARGET_INITIALIZER;
191 /* Default to 8000 scheduling. */
192 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
194 pa_cpu_string = "7100";
195 pa_cpu = PROCESSOR_7100;
197 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
199 pa_cpu_string = "700";
200 pa_cpu = PROCESSOR_700;
202 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100LC"))
204 pa_cpu_string = "7100LC";
205 pa_cpu = PROCESSOR_7100LC;
207 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
209 pa_cpu_string = "7200";
210 pa_cpu = PROCESSOR_7200;
212 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7300"))
214 pa_cpu_string = "7300";
215 pa_cpu = PROCESSOR_7300;
217 else if (pa_cpu_string == NULL
218 || ! strcmp (pa_cpu_string, "8000"))
220 pa_cpu_string = "8000";
221 pa_cpu = PROCESSOR_8000;
225 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
228 /* Set the instruction set architecture. */
229 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
231 pa_arch_string = "1.0";
232 pa_arch = ARCHITECTURE_10;
233 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
235 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
237 pa_arch_string = "1.1";
238 pa_arch = ARCHITECTURE_11;
239 target_flags &= ~MASK_PA_20;
240 target_flags |= MASK_PA_11;
242 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
244 pa_arch_string = "2.0";
245 pa_arch = ARCHITECTURE_20;
246 target_flags |= MASK_PA_11 | MASK_PA_20;
248 else if (pa_arch_string)
250 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
253 /* Unconditional branches in the delay slot are not compatible with dwarf2
254 call frame information. There is no benefit in using this optimization
255 on PA8000 and later processors. */
256 if (pa_cpu >= PROCESSOR_8000
257 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
258 || flag_unwind_tables)
259 target_flags &= ~MASK_JUMP_IN_DELAY;
261 if (flag_pic && TARGET_PORTABLE_RUNTIME)
263 warning ("PIC code generation is not supported in the portable runtime model\n");
266 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
268 warning ("PIC code generation is not compatible with fast indirect calls\n");
271 if (! TARGET_GAS && write_symbols != NO_DEBUG)
273 warning ("-g is only supported when using GAS on this processor,");
274 warning ("-g option disabled");
275 write_symbols = NO_DEBUG;
278 /* We only support the "big PIC" model now. And we always generate PIC
279 code when in 64bit mode. */
280 if (flag_pic == 1 || TARGET_64BIT)
283 /* We can't guarantee that .dword is available for 32-bit targets. */
284 if (UNITS_PER_WORD == 4)
285 targetm.asm_out.aligned_op.di = NULL;
287 /* The unaligned ops are only available when using GAS. */
290 targetm.asm_out.unaligned_op.hi = NULL;
291 targetm.asm_out.unaligned_op.si = NULL;
292 targetm.asm_out.unaligned_op.di = NULL;
295 /* Register global variables with the garbage collector. */
299 /* Return non-zero only if OP is a register of mode MODE,
302 reg_or_0_operand (op, mode)
304 enum machine_mode mode;
306 return (op == CONST0_RTX (mode) || register_operand (op, mode));
309 /* Return non-zero if OP is suitable for use in a call to a named
312 For 2.5 try to eliminate either call_operand_address or
313 function_label_operand, they perform very similar functions. */
315 call_operand_address (op, mode)
317 enum machine_mode mode ATTRIBUTE_UNUSED;
319 return (GET_MODE (op) == word_mode
320 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
323 /* Return 1 if X contains a symbolic expression. We know these
324 expressions will have one of a few well defined forms, so
325 we need only check those forms. */
327 symbolic_expression_p (x)
331 /* Strip off any HIGH. */
332 if (GET_CODE (x) == HIGH)
335 return (symbolic_operand (x, VOIDmode));
339 symbolic_operand (op, mode)
341 enum machine_mode mode ATTRIBUTE_UNUSED;
343 switch (GET_CODE (op))
350 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
351 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
352 && GET_CODE (XEXP (op, 1)) == CONST_INT);
358 /* Return truth value of statement that OP is a symbolic memory
359 operand of mode MODE. */
362 symbolic_memory_operand (op, mode)
364 enum machine_mode mode ATTRIBUTE_UNUSED;
366 if (GET_CODE (op) == SUBREG)
367 op = SUBREG_REG (op);
368 if (GET_CODE (op) != MEM)
371 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
372 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
375 /* Return 1 if the operand is either a register or a memory operand that is
379 reg_or_nonsymb_mem_operand (op, mode)
381 enum machine_mode mode;
383 if (register_operand (op, mode))
386 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
392 /* Return 1 if the operand is either a register, zero, or a memory operand
393 that is not symbolic. */
396 reg_or_0_or_nonsymb_mem_operand (op, mode)
398 enum machine_mode mode;
400 if (register_operand (op, mode))
403 if (op == CONST0_RTX (mode))
406 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
412 /* Return 1 if the operand is a register operand or a non-symbolic memory
413 operand after reload. This predicate is used for branch patterns that
414 internally handle register reloading. We need to accept non-symbolic
415 memory operands after reload to ensure that the pattern is still valid
416 if reload didn't find a hard register for the operand. */
419 reg_before_reload_operand (op, mode)
421 enum machine_mode mode;
423 /* Don't accept a SUBREG since it will need a reload. */
424 if (GET_CODE (op) == SUBREG)
427 if (register_operand (op, mode))
431 && memory_operand (op, mode)
432 && ! symbolic_memory_operand (op, mode))
438 /* Accept any constant that can be moved in one instructions into a
441 cint_ok_for_move (intval)
442 HOST_WIDE_INT intval;
444 /* OK if ldo, ldil, or zdepi, can be used. */
445 return (CONST_OK_FOR_LETTER_P (intval, 'J')
446 || CONST_OK_FOR_LETTER_P (intval, 'N')
447 || CONST_OK_FOR_LETTER_P (intval, 'K'));
450 /* Accept anything that can be moved in one instruction into a general
453 move_operand (op, mode)
455 enum machine_mode mode;
457 if (register_operand (op, mode))
460 if (GET_CODE (op) == CONSTANT_P_RTX)
463 if (GET_CODE (op) == CONST_INT)
464 return cint_ok_for_move (INTVAL (op));
466 if (GET_CODE (op) == SUBREG)
467 op = SUBREG_REG (op);
468 if (GET_CODE (op) != MEM)
473 /* We consider a LO_SUM DLT reference a move_operand now since it has
474 been merged into the normal movsi/movdi patterns. */
475 if (GET_CODE (op) == LO_SUM
476 && GET_CODE (XEXP (op, 0)) == REG
477 && REG_OK_FOR_BASE_P (XEXP (op, 0))
478 && GET_CODE (XEXP (op, 1)) == UNSPEC
479 && GET_MODE (op) == Pmode)
482 /* Since move_operand is only used for source operands, we can always
483 allow scaled indexing! */
484 if (! TARGET_DISABLE_INDEXING
485 && GET_CODE (op) == PLUS
486 && ((GET_CODE (XEXP (op, 0)) == MULT
487 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
488 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
489 && INTVAL (XEXP (XEXP (op, 0), 1))
490 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
491 && GET_CODE (XEXP (op, 1)) == REG)
492 || (GET_CODE (XEXP (op, 1)) == MULT
493 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
494 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
495 && INTVAL (XEXP (XEXP (op, 1), 1))
496 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
497 && GET_CODE (XEXP (op, 0)) == REG)))
500 return memory_address_p (mode, op);
503 /* Accept REG and any CONST_INT that can be moved in one instruction into a
506 reg_or_cint_move_operand (op, mode)
508 enum machine_mode mode;
510 if (register_operand (op, mode))
513 if (GET_CODE (op) == CONST_INT)
514 return cint_ok_for_move (INTVAL (op));
520 pic_label_operand (op, mode)
522 enum machine_mode mode ATTRIBUTE_UNUSED;
527 switch (GET_CODE (op))
533 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
534 && GET_CODE (XEXP (op, 1)) == CONST_INT);
541 fp_reg_operand (op, mode)
543 enum machine_mode mode ATTRIBUTE_UNUSED;
545 return reg_renumber && FP_REG_P (op);
550 /* Return truth value of whether OP can be used as an operand in a
551 three operand arithmetic insn that accepts registers of mode MODE
552 or 14-bit signed integers. */
554 arith_operand (op, mode)
556 enum machine_mode mode;
558 return (register_operand (op, mode)
559 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
562 /* Return truth value of whether OP can be used as an operand in a
563 three operand arithmetic insn that accepts registers of mode MODE
564 or 11-bit signed integers. */
566 arith11_operand (op, mode)
568 enum machine_mode mode;
570 return (register_operand (op, mode)
571 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
574 /* A constant integer suitable for use in a PRE_MODIFY memory
577 pre_cint_operand (op, mode)
579 enum machine_mode mode ATTRIBUTE_UNUSED;
581 return (GET_CODE (op) == CONST_INT
582 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
585 /* A constant integer suitable for use in a POST_MODIFY memory
588 post_cint_operand (op, mode)
590 enum machine_mode mode ATTRIBUTE_UNUSED;
592 return (GET_CODE (op) == CONST_INT
593 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
597 arith_double_operand (op, mode)
599 enum machine_mode mode;
601 return (register_operand (op, mode)
602 || (GET_CODE (op) == CONST_DOUBLE
603 && GET_MODE (op) == mode
604 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
605 && ((CONST_DOUBLE_HIGH (op) >= 0)
606 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
609 /* Return truth value of whether OP is an integer which fits the
610 range constraining immediate operands in three-address insns, or
611 is an integer register. */
614 ireg_or_int5_operand (op, mode)
616 enum machine_mode mode ATTRIBUTE_UNUSED;
618 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
619 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
622 /* Return nonzero if OP is an integer register, else return zero. */
624 ireg_operand (op, mode)
626 enum machine_mode mode ATTRIBUTE_UNUSED;
628 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
631 /* Return truth value of whether OP is an integer which fits the
632 range constraining immediate operands in three-address insns. */
635 int5_operand (op, mode)
637 enum machine_mode mode ATTRIBUTE_UNUSED;
639 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
643 uint5_operand (op, mode)
645 enum machine_mode mode ATTRIBUTE_UNUSED;
647 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
651 int11_operand (op, mode)
653 enum machine_mode mode ATTRIBUTE_UNUSED;
655 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
659 uint32_operand (op, mode)
661 enum machine_mode mode ATTRIBUTE_UNUSED;
663 #if HOST_BITS_PER_WIDE_INT > 32
664 /* All allowed constants will fit a CONST_INT. */
665 return (GET_CODE (op) == CONST_INT
666 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
668 return (GET_CODE (op) == CONST_INT
669 || (GET_CODE (op) == CONST_DOUBLE
670 && CONST_DOUBLE_HIGH (op) == 0));
675 arith5_operand (op, mode)
677 enum machine_mode mode;
679 return register_operand (op, mode) || int5_operand (op, mode);
682 /* True iff zdepi can be used to generate this CONST_INT.
683 zdepi first sign extends a 5 bit signed number to a given field
684 length, then places this field anywhere in a zero. */
687 unsigned HOST_WIDE_INT x;
689 unsigned HOST_WIDE_INT lsb_mask, t;
691 /* This might not be obvious, but it's at least fast.
692 This function is critical; we don't have the time loops would take. */
694 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
695 /* Return true iff t is a power of two. */
696 return ((t & (t - 1)) == 0);
699 /* True iff depi or extru can be used to compute (reg & mask).
700 Accept bit pattern like these:
706 unsigned HOST_WIDE_INT mask;
709 mask += mask & -mask;
710 return (mask & (mask - 1)) == 0;
713 /* True iff depi or extru can be used to compute (reg & OP). */
715 and_operand (op, mode)
717 enum machine_mode mode;
719 return (register_operand (op, mode)
720 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
723 /* True iff depi can be used to compute (reg | MASK). */
726 unsigned HOST_WIDE_INT mask;
728 mask += mask & -mask;
729 return (mask & (mask - 1)) == 0;
732 /* True iff depi can be used to compute (reg | OP). */
734 ior_operand (op, mode)
736 enum machine_mode mode ATTRIBUTE_UNUSED;
738 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
742 lhs_lshift_operand (op, mode)
744 enum machine_mode mode;
746 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
749 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
750 Such values can be the left hand side x in (x << r), using the zvdepi
753 lhs_lshift_cint_operand (op, mode)
755 enum machine_mode mode ATTRIBUTE_UNUSED;
757 unsigned HOST_WIDE_INT x;
758 if (GET_CODE (op) != CONST_INT)
760 x = INTVAL (op) >> 4;
761 return (x & (x + 1)) == 0;
765 arith32_operand (op, mode)
767 enum machine_mode mode;
769 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
773 pc_or_label_operand (op, mode)
775 enum machine_mode mode ATTRIBUTE_UNUSED;
777 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
780 /* Legitimize PIC addresses. If the address is already
781 position-independent, we return ORIG. Newly generated
782 position-independent addresses go to REG. If we need more
783 than one register, we lose. */
786 legitimize_pic_address (orig, mode, reg)
788 enum machine_mode mode;
792 /* Labels need special handling. */
793 if (pic_label_operand (orig, mode))
795 /* We do not want to go through the movXX expanders here since that
796 would create recursion.
798 Nor do we really want to call a generator for a named pattern
799 since that requires multiple patterns if we want to support
802 So instead we just emit the raw set, which avoids the movXX
803 expanders completely. */
804 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
805 current_function_uses_pic_offset_table = 1;
808 if (GET_CODE (orig) == SYMBOL_REF)
814 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
815 gen_rtx_HIGH (word_mode, orig)));
817 = gen_rtx_MEM (Pmode,
818 gen_rtx_LO_SUM (Pmode, reg,
819 gen_rtx_UNSPEC (Pmode,
823 current_function_uses_pic_offset_table = 1;
824 RTX_UNCHANGING_P (pic_ref) = 1;
825 emit_move_insn (reg, pic_ref);
828 else if (GET_CODE (orig) == CONST)
832 if (GET_CODE (XEXP (orig, 0)) == PLUS
833 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
839 if (GET_CODE (XEXP (orig, 0)) == PLUS)
841 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
842 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
843 base == reg ? 0 : reg);
846 if (GET_CODE (orig) == CONST_INT)
848 if (INT_14_BITS (orig))
849 return plus_constant (base, INTVAL (orig));
850 orig = force_reg (Pmode, orig);
852 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
853 /* Likewise, should we set special REG_NOTEs here? */
858 /* Try machine-dependent ways of modifying an illegitimate address
859 to be legitimate. If we find one, return the new, valid address.
860 This macro is used in only one place: `memory_address' in explow.c.
862 OLDX is the address as it was before break_out_memory_refs was called.
863 In some cases it is useful to look at this to decide what needs to be done.
865 MODE and WIN are passed so that this macro can use
866 GO_IF_LEGITIMATE_ADDRESS.
868 It is always safe for this macro to do nothing. It exists to recognize
869 opportunities to optimize the output.
871 For the PA, transform:
873 memory(X + <large int>)
877 if (<large int> & mask) >= 16
878 Y = (<large int> & ~mask) + mask + 1 Round up.
880 Y = (<large int> & ~mask) Round down.
882 memory (Z + (<large int> - Y));
884 This is for CSE to find several similar references, and only use one Z.
886 X can either be a SYMBOL_REF or REG, but because combine can not
887 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
888 D will not fit in 14 bits.
890 MODE_FLOAT references allow displacements which fit in 5 bits, so use
893 MODE_INT references allow displacements which fit in 14 bits, so use
896 This relies on the fact that most mode MODE_FLOAT references will use FP
897 registers and most mode MODE_INT references will use integer registers.
898 (In the rare case of an FP register used in an integer MODE, we depend
899 on secondary reloads to clean things up.)
902 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
903 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
904 addressing modes to be used).
906 Put X and Z into registers. Then put the entire expression into
910 hppa_legitimize_address (x, oldx, mode)
911 rtx x, oldx ATTRIBUTE_UNUSED;
912 enum machine_mode mode;
917 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
919 /* Strip off CONST. */
920 if (GET_CODE (x) == CONST)
923 /* Special case. Get the SYMBOL_REF into a register and use indexing.
924 That should always be safe. */
925 if (GET_CODE (x) == PLUS
926 && GET_CODE (XEXP (x, 0)) == REG
927 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
929 rtx reg = force_reg (Pmode, XEXP (x, 1));
930 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
933 /* Note we must reject symbols which represent function addresses
934 since the assembler/linker can't handle arithmetic on plabels. */
935 if (GET_CODE (x) == PLUS
936 && GET_CODE (XEXP (x, 1)) == CONST_INT
937 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
938 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
939 || GET_CODE (XEXP (x, 0)) == REG))
941 rtx int_part, ptr_reg;
943 int offset = INTVAL (XEXP (x, 1));
946 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
947 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
949 /* Choose which way to round the offset. Round up if we
950 are >= halfway to the next boundary. */
951 if ((offset & mask) >= ((mask + 1) / 2))
952 newoffset = (offset & ~ mask) + mask + 1;
954 newoffset = (offset & ~ mask);
956 /* If the newoffset will not fit in 14 bits (ldo), then
957 handling this would take 4 or 5 instructions (2 to load
958 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
959 add the new offset and the SYMBOL_REF.) Combine can
960 not handle 4->2 or 5->2 combinations, so do not create
962 if (! VAL_14_BITS_P (newoffset)
963 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
965 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
968 gen_rtx_HIGH (Pmode, const_part));
971 gen_rtx_LO_SUM (Pmode,
972 tmp_reg, const_part));
976 if (! VAL_14_BITS_P (newoffset))
977 int_part = force_reg (Pmode, GEN_INT (newoffset));
979 int_part = GEN_INT (newoffset);
981 ptr_reg = force_reg (Pmode,
983 force_reg (Pmode, XEXP (x, 0)),
986 return plus_constant (ptr_reg, offset - newoffset);
989 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
991 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
992 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
993 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
994 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
995 || GET_CODE (XEXP (x, 1)) == SUBREG)
996 && GET_CODE (XEXP (x, 1)) != CONST)
998 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1002 if (GET_CODE (reg1) != REG)
1003 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1005 reg2 = XEXP (XEXP (x, 0), 0);
1006 if (GET_CODE (reg2) != REG)
1007 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1009 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1010 gen_rtx_MULT (Pmode,
1016 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1018 Only do so for floating point modes since this is more speculative
1019 and we lose if it's an integer store. */
1020 if (GET_CODE (x) == PLUS
1021 && GET_CODE (XEXP (x, 0)) == PLUS
1022 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1023 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1024 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1025 && (mode == SFmode || mode == DFmode))
1028 /* First, try and figure out what to use as a base register. */
1029 rtx reg1, reg2, base, idx, orig_base;
1031 reg1 = XEXP (XEXP (x, 0), 1);
1036 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1037 then emit_move_sequence will turn on REG_POINTER so we'll know
1038 it's a base register below. */
1039 if (GET_CODE (reg1) != REG)
1040 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1042 if (GET_CODE (reg2) != REG)
1043 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1045 /* Figure out what the base and index are. */
1047 if (GET_CODE (reg1) == REG
1048 && REG_POINTER (reg1))
1051 orig_base = XEXP (XEXP (x, 0), 1);
1052 idx = gen_rtx_PLUS (Pmode,
1053 gen_rtx_MULT (Pmode,
1054 XEXP (XEXP (XEXP (x, 0), 0), 0),
1055 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1058 else if (GET_CODE (reg2) == REG
1059 && REG_POINTER (reg2))
1062 orig_base = XEXP (x, 1);
1069 /* If the index adds a large constant, try to scale the
1070 constant so that it can be loaded with only one insn. */
1071 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1072 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1073 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1074 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1076 /* Divide the CONST_INT by the scale factor, then add it to A. */
1077 int val = INTVAL (XEXP (idx, 1));
1079 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1080 reg1 = XEXP (XEXP (idx, 0), 0);
1081 if (GET_CODE (reg1) != REG)
1082 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1084 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1086 /* We can now generate a simple scaled indexed address. */
1089 (Pmode, gen_rtx_PLUS (Pmode,
1090 gen_rtx_MULT (Pmode, reg1,
1091 XEXP (XEXP (idx, 0), 1)),
1095 /* If B + C is still a valid base register, then add them. */
1096 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1097 && INTVAL (XEXP (idx, 1)) <= 4096
1098 && INTVAL (XEXP (idx, 1)) >= -4096)
1100 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1103 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1105 reg2 = XEXP (XEXP (idx, 0), 0);
1106 if (GET_CODE (reg2) != CONST_INT)
1107 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1109 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1110 gen_rtx_MULT (Pmode,
1116 /* Get the index into a register, then add the base + index and
1117 return a register holding the result. */
1119 /* First get A into a register. */
1120 reg1 = XEXP (XEXP (idx, 0), 0);
1121 if (GET_CODE (reg1) != REG)
1122 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1124 /* And get B into a register. */
1125 reg2 = XEXP (idx, 1);
1126 if (GET_CODE (reg2) != REG)
1127 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1129 reg1 = force_reg (Pmode,
1130 gen_rtx_PLUS (Pmode,
1131 gen_rtx_MULT (Pmode, reg1,
1132 XEXP (XEXP (idx, 0), 1)),
1135 /* Add the result to our base register and return. */
1136 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1140 /* Uh-oh. We might have an address for x[n-100000]. This needs
1141 special handling to avoid creating an indexed memory address
1142 with x-100000 as the base.
1144 If the constant part is small enough, then it's still safe because
1145 there is a guard page at the beginning and end of the data segment.
1147 Scaled references are common enough that we want to try and rearrange the
1148 terms so that we can use indexing for these addresses too. Only
1149 do the optimization for floatint point modes. */
1151 if (GET_CODE (x) == PLUS
1152 && symbolic_expression_p (XEXP (x, 1)))
1154 /* Ugly. We modify things here so that the address offset specified
1155 by the index expression is computed first, then added to x to form
1156 the entire address. */
1158 rtx regx1, regx2, regy1, regy2, y;
1160 /* Strip off any CONST. */
1162 if (GET_CODE (y) == CONST)
1165 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1167 /* See if this looks like
1168 (plus (mult (reg) (shadd_const))
1169 (const (plus (symbol_ref) (const_int))))
1171 Where const_int is small. In that case the const
1172 expression is a valid pointer for indexing.
1174 If const_int is big, but can be divided evenly by shadd_const
1175 and added to (reg). This allows more scaled indexed addresses. */
1176 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1177 && GET_CODE (XEXP (x, 0)) == MULT
1178 && GET_CODE (XEXP (y, 1)) == CONST_INT
1179 && INTVAL (XEXP (y, 1)) >= -4096
1180 && INTVAL (XEXP (y, 1)) <= 4095
1181 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1182 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1184 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1188 if (GET_CODE (reg1) != REG)
1189 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1191 reg2 = XEXP (XEXP (x, 0), 0);
1192 if (GET_CODE (reg2) != REG)
1193 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1195 return force_reg (Pmode,
1196 gen_rtx_PLUS (Pmode,
1197 gen_rtx_MULT (Pmode,
1202 else if ((mode == DFmode || mode == SFmode)
1203 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1204 && GET_CODE (XEXP (x, 0)) == MULT
1205 && GET_CODE (XEXP (y, 1)) == CONST_INT
1206 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1207 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1208 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1211 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1212 / INTVAL (XEXP (XEXP (x, 0), 1))));
1213 regx2 = XEXP (XEXP (x, 0), 0);
1214 if (GET_CODE (regx2) != REG)
1215 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1216 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1220 gen_rtx_PLUS (Pmode,
1221 gen_rtx_MULT (Pmode, regx2,
1222 XEXP (XEXP (x, 0), 1)),
1223 force_reg (Pmode, XEXP (y, 0))));
1225 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1226 && INTVAL (XEXP (y, 1)) >= -4096
1227 && INTVAL (XEXP (y, 1)) <= 4095)
1229 /* This is safe because of the guard page at the
1230 beginning and end of the data space. Just
1231 return the original address. */
1236 /* Doesn't look like one we can optimize. */
1237 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1238 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1239 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1240 regx1 = force_reg (Pmode,
1241 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1243 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1251 /* For the HPPA, REG and REG+CONST is cost 0
1252 and addresses involving symbolic constants are cost 2.
1254 PIC addresses are very expensive.
1256 It is no coincidence that this has the same structure
1257 as GO_IF_LEGITIMATE_ADDRESS. */
1259 hppa_address_cost (X)
1262 if (GET_CODE (X) == PLUS)
1264 else if (GET_CODE (X) == LO_SUM)
1266 else if (GET_CODE (X) == HIGH)
1271 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1272 new rtx with the correct mode. */
1274 force_mode (mode, orig)
1275 enum machine_mode mode;
1278 if (mode == GET_MODE (orig))
1281 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1284 return gen_rtx_REG (mode, REGNO (orig));
1287 /* Emit insns to move operands[1] into operands[0].
1289 Return 1 if we have written out everything that needs to be done to
1290 do the move. Otherwise, return 0 and the caller will emit the move
1293 Note SCRATCH_REG may not be in the proper mode depending on how it
1294 will be used. This routine is resposible for creating a new copy
1295 of SCRATCH_REG in the proper mode. */
1298 emit_move_sequence (operands, mode, scratch_reg)
1300 enum machine_mode mode;
1303 register rtx operand0 = operands[0];
1304 register rtx operand1 = operands[1];
1308 && reload_in_progress && GET_CODE (operand0) == REG
1309 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1310 operand0 = reg_equiv_mem[REGNO (operand0)];
1311 else if (scratch_reg
1312 && reload_in_progress && GET_CODE (operand0) == SUBREG
1313 && GET_CODE (SUBREG_REG (operand0)) == REG
1314 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1316 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1317 the code which tracks sets/uses for delete_output_reload. */
1318 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1319 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1320 SUBREG_BYTE (operand0));
1321 operand0 = alter_subreg (&temp);
1325 && reload_in_progress && GET_CODE (operand1) == REG
1326 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1327 operand1 = reg_equiv_mem[REGNO (operand1)];
1328 else if (scratch_reg
1329 && reload_in_progress && GET_CODE (operand1) == SUBREG
1330 && GET_CODE (SUBREG_REG (operand1)) == REG
1331 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1333 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1334 the code which tracks sets/uses for delete_output_reload. */
1335 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1336 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1337 SUBREG_BYTE (operand1));
1338 operand1 = alter_subreg (&temp);
1341 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1342 && ((tem = find_replacement (&XEXP (operand0, 0)))
1343 != XEXP (operand0, 0)))
1344 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1345 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1346 && ((tem = find_replacement (&XEXP (operand1, 0)))
1347 != XEXP (operand1, 0)))
1348 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1350 /* Handle secondary reloads for loads/stores of FP registers from
1351 REG+D addresses where D does not fit in 5 bits, including
1352 (subreg (mem (addr))) cases. */
1353 if (fp_reg_operand (operand0, mode)
1354 && ((GET_CODE (operand1) == MEM
1355 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1356 || ((GET_CODE (operand1) == SUBREG
1357 && GET_CODE (XEXP (operand1, 0)) == MEM
1358 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1361 if (GET_CODE (operand1) == SUBREG)
1362 operand1 = XEXP (operand1, 0);
1364 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1365 it in WORD_MODE regardless of what mode it was originally given
1367 scratch_reg = force_mode (word_mode, scratch_reg);
1369 /* D might not fit in 14 bits either; for such cases load D into
1371 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1373 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1374 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1376 XEXP (XEXP (operand1, 0), 0),
1380 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1381 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1382 gen_rtx_MEM (mode, scratch_reg)));
1385 else if (fp_reg_operand (operand1, mode)
1386 && ((GET_CODE (operand0) == MEM
1387 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1388 || ((GET_CODE (operand0) == SUBREG)
1389 && GET_CODE (XEXP (operand0, 0)) == MEM
1390 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1393 if (GET_CODE (operand0) == SUBREG)
1394 operand0 = XEXP (operand0, 0);
1396 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1397 it in WORD_MODE regardless of what mode it was originally given
1399 scratch_reg = force_mode (word_mode, scratch_reg);
1401 /* D might not fit in 14 bits either; for such cases load D into
1403 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1405 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1406 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1409 XEXP (XEXP (operand0, 0),
1414 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1415 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1419 /* Handle secondary reloads for loads of FP registers from constant
1420 expressions by forcing the constant into memory.
1422 use scratch_reg to hold the address of the memory location.
1424 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1425 NO_REGS when presented with a const_int and an register class
1426 containing only FP registers. Doing so unfortunately creates
1427 more problems than it solves. Fix this for 2.5. */
1428 else if (fp_reg_operand (operand0, mode)
1429 && CONSTANT_P (operand1)
1434 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1435 it in WORD_MODE regardless of what mode it was originally given
1437 scratch_reg = force_mode (word_mode, scratch_reg);
1439 /* Force the constant into memory and put the address of the
1440 memory location into scratch_reg. */
1441 xoperands[0] = scratch_reg;
1442 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1443 emit_move_sequence (xoperands, Pmode, 0);
1445 /* Now load the destination register. */
1446 emit_insn (gen_rtx_SET (mode, operand0,
1447 gen_rtx_MEM (mode, scratch_reg)));
1450 /* Handle secondary reloads for SAR. These occur when trying to load
1451 the SAR from memory, FP register, or with a constant. */
1452 else if (GET_CODE (operand0) == REG
1453 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1454 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1455 && (GET_CODE (operand1) == MEM
1456 || GET_CODE (operand1) == CONST_INT
1457 || (GET_CODE (operand1) == REG
1458 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1461 /* D might not fit in 14 bits either; for such cases load D into
1463 if (GET_CODE (operand1) == MEM
1464 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1466 /* We are reloading the address into the scratch register, so we
1467 want to make sure the scratch register is a full register. */
1468 scratch_reg = force_mode (word_mode, scratch_reg);
1470 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1471 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1474 XEXP (XEXP (operand1, 0),
1478 /* Now we are going to load the scratch register from memory,
1479 we want to load it in the same width as the original MEM,
1480 which must be the same as the width of the ultimate destination,
1482 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1484 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1489 /* We want to load the scratch register using the same mode as
1490 the ultimate destination. */
1491 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1493 emit_move_insn (scratch_reg, operand1);
1496 /* And emit the insn to set the ultimate destination. We know that
1497 the scratch register has the same mode as the destination at this
1499 emit_move_insn (operand0, scratch_reg);
1502 /* Handle most common case: storing into a register. */
1503 else if (register_operand (operand0, mode))
1505 if (register_operand (operand1, mode)
1506 || (GET_CODE (operand1) == CONST_INT
1507 && cint_ok_for_move (INTVAL (operand1)))
1508 || (operand1 == CONST0_RTX (mode))
1509 || (GET_CODE (operand1) == HIGH
1510 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1511 /* Only `general_operands' can come here, so MEM is ok. */
1512 || GET_CODE (operand1) == MEM)
1514 /* Run this case quickly. */
1515 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1519 else if (GET_CODE (operand0) == MEM)
1521 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1522 && !(reload_in_progress || reload_completed))
1524 rtx temp = gen_reg_rtx (DFmode);
1526 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1527 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1530 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1532 /* Run this case quickly. */
1533 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1536 if (! (reload_in_progress || reload_completed))
1538 operands[0] = validize_mem (operand0);
1539 operands[1] = operand1 = force_reg (mode, operand1);
1543 /* Simplify the source if we need to.
1544 Note we do have to handle function labels here, even though we do
1545 not consider them legitimate constants. Loop optimizations can
1546 call the emit_move_xxx with one as a source. */
1547 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1548 || function_label_operand (operand1, mode)
1549 || (GET_CODE (operand1) == HIGH
1550 && symbolic_operand (XEXP (operand1, 0), mode)))
1554 if (GET_CODE (operand1) == HIGH)
1557 operand1 = XEXP (operand1, 0);
1559 if (symbolic_operand (operand1, mode))
1561 /* Argh. The assembler and linker can't handle arithmetic
1564 So we force the plabel into memory, load operand0 from
1565 the memory location, then add in the constant part. */
1566 if ((GET_CODE (operand1) == CONST
1567 && GET_CODE (XEXP (operand1, 0)) == PLUS
1568 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1569 || function_label_operand (operand1, mode))
1571 rtx temp, const_part;
1573 /* Figure out what (if any) scratch register to use. */
1574 if (reload_in_progress || reload_completed)
1576 scratch_reg = scratch_reg ? scratch_reg : operand0;
1577 /* SCRATCH_REG will hold an address and maybe the actual
1578 data. We want it in WORD_MODE regardless of what mode it
1579 was originally given to us. */
1580 scratch_reg = force_mode (word_mode, scratch_reg);
1583 scratch_reg = gen_reg_rtx (Pmode);
1585 if (GET_CODE (operand1) == CONST)
1587 /* Save away the constant part of the expression. */
1588 const_part = XEXP (XEXP (operand1, 0), 1);
1589 if (GET_CODE (const_part) != CONST_INT)
1592 /* Force the function label into memory. */
1593 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1597 /* No constant part. */
1598 const_part = NULL_RTX;
1600 /* Force the function label into memory. */
1601 temp = force_const_mem (mode, operand1);
1605 /* Get the address of the memory location. PIC-ify it if
1607 temp = XEXP (temp, 0);
1609 temp = legitimize_pic_address (temp, mode, scratch_reg);
1611 /* Put the address of the memory location into our destination
1614 emit_move_sequence (operands, mode, scratch_reg);
1616 /* Now load from the memory location into our destination
1618 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1619 emit_move_sequence (operands, mode, scratch_reg);
1621 /* And add back in the constant part. */
1622 if (const_part != NULL_RTX)
1623 expand_inc (operand0, const_part);
1632 if (reload_in_progress || reload_completed)
1634 temp = scratch_reg ? scratch_reg : operand0;
1635 /* TEMP will hold an address and maybe the actual
1636 data. We want it in WORD_MODE regardless of what mode it
1637 was originally given to us. */
1638 temp = force_mode (word_mode, temp);
1641 temp = gen_reg_rtx (Pmode);
1643 /* (const (plus (symbol) (const_int))) must be forced to
1644 memory during/after reload if the const_int will not fit
1646 if (GET_CODE (operand1) == CONST
1647 && GET_CODE (XEXP (operand1, 0)) == PLUS
1648 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1649 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1650 && (reload_completed || reload_in_progress)
1653 operands[1] = force_const_mem (mode, operand1);
1654 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1656 emit_move_sequence (operands, mode, temp);
1660 operands[1] = legitimize_pic_address (operand1, mode, temp);
1661 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1664 /* On the HPPA, references to data space are supposed to use dp,
1665 register 27, but showing it in the RTL inhibits various cse
1666 and loop optimizations. */
1671 if (reload_in_progress || reload_completed)
1673 temp = scratch_reg ? scratch_reg : operand0;
1674 /* TEMP will hold an address and maybe the actual
1675 data. We want it in WORD_MODE regardless of what mode it
1676 was originally given to us. */
1677 temp = force_mode (word_mode, temp);
1680 temp = gen_reg_rtx (mode);
1682 /* Loading a SYMBOL_REF into a register makes that register
1683 safe to be used as the base in an indexed address.
1685 Don't mark hard registers though. That loses. */
1686 if (GET_CODE (operand0) == REG
1687 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1688 REG_POINTER (operand0) = 1;
1689 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1690 REG_POINTER (temp) = 1;
1692 set = gen_rtx_SET (mode, operand0, temp);
1694 set = gen_rtx_SET (VOIDmode,
1696 gen_rtx_LO_SUM (mode, temp, operand1));
1698 emit_insn (gen_rtx_SET (VOIDmode,
1700 gen_rtx_HIGH (mode, operand1)));
1706 else if (GET_CODE (operand1) != CONST_INT
1707 || ! cint_ok_for_move (INTVAL (operand1)))
1709 rtx extend = NULL_RTX;
1712 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1713 && HOST_BITS_PER_WIDE_INT > 32
1714 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1716 HOST_WIDE_INT val = INTVAL (operand1);
1719 /* Extract the low order 32 bits of the value and sign extend.
1720 If the new value is the same as the original value, we can
1721 can use the original value as-is. If the new value is
1722 different, we use it and insert the most-significant 32-bits
1723 of the original value into the final result. */
1724 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1725 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1728 #if HOST_BITS_PER_WIDE_INT > 32
1729 extend = GEN_INT (val >> 32);
1731 operand1 = GEN_INT (nval);
1735 if (reload_in_progress || reload_completed)
1738 temp = gen_reg_rtx (mode);
1740 if (GET_CODE (operand1) == CONST_INT)
1742 /* Directly break constant into low and high parts. This
1743 provides better optimization opportunities because various
1744 passes recognize constants split with PLUS but not LO_SUM.
1745 We use a 14-bit signed low part except when the addition
1746 of 0x4000 to the high part might change the sign of the
1748 HOST_WIDE_INT value = INTVAL (operand1);
1749 HOST_WIDE_INT low = value & 0x3fff;
1750 HOST_WIDE_INT high = value & ~ 0x3fff;
1754 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1762 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1763 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1767 emit_insn (gen_rtx_SET (VOIDmode, temp,
1768 gen_rtx_HIGH (mode, operand1)));
1769 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1772 emit_move_insn (operands[0], operands[1]);
1774 if (extend != NULL_RTX)
1775 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1781 /* Now have insn-emit do whatever it normally does. */
1785 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1786 it will need a link/runtime reloc). */
1794 switch (TREE_CODE (exp))
1801 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1802 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1807 case NON_LVALUE_EXPR:
1808 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1814 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1815 if (TREE_VALUE (link) != 0)
1816 reloc |= reloc_needed (TREE_VALUE (link));
1829 /* Does operand (which is a symbolic_operand) live in text space? If
1830 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1833 read_only_operand (operand, mode)
1835 enum machine_mode mode ATTRIBUTE_UNUSED;
1837 if (GET_CODE (operand) == CONST)
1838 operand = XEXP (XEXP (operand, 0), 0);
1841 if (GET_CODE (operand) == SYMBOL_REF)
1842 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1846 if (GET_CODE (operand) == SYMBOL_REF)
1847 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1853 /* Return the best assembler insn template
1854 for moving operands[1] into operands[0] as a fullword. */
1856 singlemove_string (operands)
1859 HOST_WIDE_INT intval;
1861 if (GET_CODE (operands[0]) == MEM)
1862 return "stw %r1,%0";
1863 if (GET_CODE (operands[1]) == MEM)
1865 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1870 if (GET_MODE (operands[1]) != SFmode)
1873 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1875 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1876 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1878 operands[1] = GEN_INT (i);
1879 /* Fall through to CONST_INT case. */
1881 if (GET_CODE (operands[1]) == CONST_INT)
1883 intval = INTVAL (operands[1]);
1885 if (VAL_14_BITS_P (intval))
1887 else if ((intval & 0x7ff) == 0)
1888 return "ldil L'%1,%0";
1889 else if (zdepi_cint_p (intval))
1890 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1892 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1894 return "copy %1,%0";
1898 /* Compute position (in OP[1]) and width (in OP[2])
1899 useful for copying IMM to a register using the zdepi
1900 instructions. Store the immediate value to insert in OP[0]. */
1902 compute_zdepwi_operands (imm, op)
1903 unsigned HOST_WIDE_INT imm;
1908 /* Find the least significant set bit in IMM. */
1909 for (lsb = 0; lsb < 32; lsb++)
1916 /* Choose variants based on *sign* of the 5-bit field. */
1917 if ((imm & 0x10) == 0)
1918 len = (lsb <= 28) ? 4 : 32 - lsb;
1921 /* Find the width of the bitstring in IMM. */
1922 for (len = 5; len < 32; len++)
1924 if ((imm & (1 << len)) == 0)
1928 /* Sign extend IMM as a 5-bit value. */
1929 imm = (imm & 0xf) - 0x10;
1937 /* Compute position (in OP[1]) and width (in OP[2])
1938 useful for copying IMM to a register using the depdi,z
1939 instructions. Store the immediate value to insert in OP[0]. */
1941 compute_zdepdi_operands (imm, op)
1942 unsigned HOST_WIDE_INT imm;
1945 HOST_WIDE_INT lsb, len;
1947 /* Find the least significant set bit in IMM. */
1948 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1955 /* Choose variants based on *sign* of the 5-bit field. */
1956 if ((imm & 0x10) == 0)
1957 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1958 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1961 /* Find the width of the bitstring in IMM. */
1962 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1964 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
1968 /* Sign extend IMM as a 5-bit value. */
1969 imm = (imm & 0xf) - 0x10;
1977 /* Output assembler code to perform a doubleword move insn
1978 with operands OPERANDS. */
1981 output_move_double (operands)
1984 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1986 rtx addreg0 = 0, addreg1 = 0;
1988 /* First classify both operands. */
1990 if (REG_P (operands[0]))
1992 else if (offsettable_memref_p (operands[0]))
1994 else if (GET_CODE (operands[0]) == MEM)
1999 if (REG_P (operands[1]))
2001 else if (CONSTANT_P (operands[1]))
2003 else if (offsettable_memref_p (operands[1]))
2005 else if (GET_CODE (operands[1]) == MEM)
2010 /* Check for the cases that the operand constraints are not
2011 supposed to allow to happen. Abort if we get one,
2012 because generating code for these cases is painful. */
2014 if (optype0 != REGOP && optype1 != REGOP)
2017 /* Handle auto decrementing and incrementing loads and stores
2018 specifically, since the structure of the function doesn't work
2019 for them without major modification. Do it better when we learn
2020 this port about the general inc/dec addressing of PA.
2021 (This was written by tege. Chide him if it doesn't work.) */
2023 if (optype0 == MEMOP)
2025 /* We have to output the address syntax ourselves, since print_operand
2026 doesn't deal with the addresses we want to use. Fix this later. */
2028 rtx addr = XEXP (operands[0], 0);
2029 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2031 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2033 operands[0] = XEXP (addr, 0);
2034 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2037 if (!reg_overlap_mentioned_p (high_reg, addr))
2039 /* No overlap between high target register and address
2040 register. (We do this in a non-obvious way to
2041 save a register file writeback) */
2042 if (GET_CODE (addr) == POST_INC)
2043 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2044 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2049 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2051 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2053 operands[0] = XEXP (addr, 0);
2054 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2057 if (!reg_overlap_mentioned_p (high_reg, addr))
2059 /* No overlap between high target register and address
2060 register. (We do this in a non-obvious way to
2061 save a register file writeback) */
2062 if (GET_CODE (addr) == PRE_INC)
2063 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2064 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2070 if (optype1 == MEMOP)
2072 /* We have to output the address syntax ourselves, since print_operand
2073 doesn't deal with the addresses we want to use. Fix this later. */
2075 rtx addr = XEXP (operands[1], 0);
2076 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2078 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2080 operands[1] = XEXP (addr, 0);
2081 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2084 if (!reg_overlap_mentioned_p (high_reg, addr))
2086 /* No overlap between high target register and address
2087 register. (We do this in a non-obvious way to
2088 save a register file writeback) */
2089 if (GET_CODE (addr) == POST_INC)
2090 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2091 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2095 /* This is an undefined situation. We should load into the
2096 address register *and* update that register. Probably
2097 we don't need to handle this at all. */
2098 if (GET_CODE (addr) == POST_INC)
2099 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2100 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2103 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2105 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2107 operands[1] = XEXP (addr, 0);
2108 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2111 if (!reg_overlap_mentioned_p (high_reg, addr))
2113 /* No overlap between high target register and address
2114 register. (We do this in a non-obvious way to
2115 save a register file writeback) */
2116 if (GET_CODE (addr) == PRE_INC)
2117 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2118 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2122 /* This is an undefined situation. We should load into the
2123 address register *and* update that register. Probably
2124 we don't need to handle this at all. */
2125 if (GET_CODE (addr) == PRE_INC)
2126 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2127 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2130 else if (GET_CODE (addr) == PLUS
2131 && GET_CODE (XEXP (addr, 0)) == MULT)
2133 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2135 if (!reg_overlap_mentioned_p (high_reg, addr))
2139 xoperands[0] = high_reg;
2140 xoperands[1] = XEXP (addr, 1);
2141 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2142 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2143 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2145 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2151 xoperands[0] = high_reg;
2152 xoperands[1] = XEXP (addr, 1);
2153 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2154 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2155 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2157 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2162 /* If an operand is an unoffsettable memory ref, find a register
2163 we can increment temporarily to make it refer to the second word. */
2165 if (optype0 == MEMOP)
2166 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2168 if (optype1 == MEMOP)
2169 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2171 /* Ok, we can do one word at a time.
2172 Normally we do the low-numbered word first.
2174 In either case, set up in LATEHALF the operands to use
2175 for the high-numbered word and in some cases alter the
2176 operands in OPERANDS to be suitable for the low-numbered word. */
2178 if (optype0 == REGOP)
2179 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2180 else if (optype0 == OFFSOP)
2181 latehalf[0] = adjust_address (operands[0], SImode, 4);
2183 latehalf[0] = operands[0];
2185 if (optype1 == REGOP)
2186 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2187 else if (optype1 == OFFSOP)
2188 latehalf[1] = adjust_address (operands[1], SImode, 4);
2189 else if (optype1 == CNSTOP)
2190 split_double (operands[1], &operands[1], &latehalf[1]);
2192 latehalf[1] = operands[1];
2194 /* If the first move would clobber the source of the second one,
2195 do them in the other order.
2197 This can happen in two cases:
2199 mem -> register where the first half of the destination register
2200 is the same register used in the memory's address. Reload
2201 can create such insns.
2203 mem in this case will be either register indirect or register
2204 indirect plus a valid offset.
2206 register -> register move where REGNO(dst) == REGNO(src + 1)
2207 someone (Tim/Tege?) claimed this can happen for parameter loads.
2209 Handle mem -> register case first. */
2210 if (optype0 == REGOP
2211 && (optype1 == MEMOP || optype1 == OFFSOP)
2212 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2215 /* Do the late half first. */
2217 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2218 output_asm_insn (singlemove_string (latehalf), latehalf);
2222 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2223 return singlemove_string (operands);
2226 /* Now handle register -> register case. */
2227 if (optype0 == REGOP && optype1 == REGOP
2228 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2230 output_asm_insn (singlemove_string (latehalf), latehalf);
2231 return singlemove_string (operands);
2234 /* Normal case: do the two words, low-numbered first. */
2236 output_asm_insn (singlemove_string (operands), operands);
2238 /* Make any unoffsettable addresses point at high-numbered word. */
2240 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2242 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2245 output_asm_insn (singlemove_string (latehalf), latehalf);
2247 /* Undo the adds we just did. */
2249 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2251 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2257 output_fp_move_double (operands)
2260 if (FP_REG_P (operands[0]))
2262 if (FP_REG_P (operands[1])
2263 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2264 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2266 output_asm_insn ("fldd%F1 %1,%0", operands);
2268 else if (FP_REG_P (operands[1]))
2270 output_asm_insn ("fstd%F0 %1,%0", operands);
2272 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2274 if (GET_CODE (operands[0]) == REG)
2277 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2278 xoperands[0] = operands[0];
2279 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2281 /* This is a pain. You have to be prepared to deal with an
2282 arbitrary address here including pre/post increment/decrement.
2284 so avoid this in the MD. */
2292 /* Return a REG that occurs in ADDR with coefficient 1.
2293 ADDR can be effectively incremented by incrementing REG. */
2296 find_addr_reg (addr)
2299 while (GET_CODE (addr) == PLUS)
2301 if (GET_CODE (XEXP (addr, 0)) == REG)
2302 addr = XEXP (addr, 0);
2303 else if (GET_CODE (XEXP (addr, 1)) == REG)
2304 addr = XEXP (addr, 1);
2305 else if (CONSTANT_P (XEXP (addr, 0)))
2306 addr = XEXP (addr, 1);
2307 else if (CONSTANT_P (XEXP (addr, 1)))
2308 addr = XEXP (addr, 0);
2312 if (GET_CODE (addr) == REG)
2317 /* Emit code to perform a block move.
2319 OPERANDS[0] is the destination pointer as a REG, clobbered.
2320 OPERANDS[1] is the source pointer as a REG, clobbered.
2321 OPERANDS[2] is a register for temporary storage.
2322 OPERANDS[4] is the size as a CONST_INT
2323 OPERANDS[3] is a register for temporary storage.
2324 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2325 OPERANDS[6] is another temporary register. */
2328 output_block_move (operands, size_is_constant)
2330 int size_is_constant ATTRIBUTE_UNUSED;
2332 int align = INTVAL (operands[5]);
2333 unsigned long n_bytes = INTVAL (operands[4]);
2335 /* We can't move more than four bytes at a time because the PA
2336 has no longer integer move insns. (Could use fp mem ops?) */
2340 /* Note that we know each loop below will execute at least twice
2341 (else we would have open-coded the copy). */
2345 /* Pre-adjust the loop counter. */
2346 operands[4] = GEN_INT (n_bytes - 8);
2347 output_asm_insn ("ldi %4,%2", operands);
2350 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2351 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2352 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2353 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2354 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2356 /* Handle the residual. There could be up to 7 bytes of
2357 residual to copy! */
2358 if (n_bytes % 8 != 0)
2360 operands[4] = GEN_INT (n_bytes % 4);
2361 if (n_bytes % 8 >= 4)
2362 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2363 if (n_bytes % 4 != 0)
2364 output_asm_insn ("ldw 0(%1),%6", operands);
2365 if (n_bytes % 8 >= 4)
2366 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2367 if (n_bytes % 4 != 0)
2368 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2373 /* Pre-adjust the loop counter. */
2374 operands[4] = GEN_INT (n_bytes - 4);
2375 output_asm_insn ("ldi %4,%2", operands);
2378 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2379 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2380 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2381 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2382 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2384 /* Handle the residual. */
2385 if (n_bytes % 4 != 0)
2387 if (n_bytes % 4 >= 2)
2388 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2389 if (n_bytes % 2 != 0)
2390 output_asm_insn ("ldb 0(%1),%6", operands);
2391 if (n_bytes % 4 >= 2)
2392 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2393 if (n_bytes % 2 != 0)
2394 output_asm_insn ("stb %6,0(%0)", operands);
2399 /* Pre-adjust the loop counter. */
2400 operands[4] = GEN_INT (n_bytes - 2);
2401 output_asm_insn ("ldi %4,%2", operands);
2404 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2405 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2406 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2407 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2408 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2410 /* Handle the residual. */
2411 if (n_bytes % 2 != 0)
2413 output_asm_insn ("ldb 0(%1),%3", operands);
2414 output_asm_insn ("stb %3,0(%0)", operands);
2423 /* Count the number of insns necessary to handle this block move.
2425 Basic structure is the same as emit_block_move, except that we
2426 count insns rather than emit them. */
2429 compute_movstrsi_length (insn)
2432 rtx pat = PATTERN (insn);
2433 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2434 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2435 unsigned int n_insns = 0;
2437 /* We can't move more than four bytes at a time because the PA
2438 has no longer integer move insns. (Could use fp mem ops?) */
2442 /* The basic copying loop. */
2446 if (n_bytes % (2 * align) != 0)
2448 if ((n_bytes % (2 * align)) >= align)
2451 if ((n_bytes % align) != 0)
2455 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2461 output_and (operands)
2464 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2466 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2467 int ls0, ls1, ms0, p, len;
2469 for (ls0 = 0; ls0 < 32; ls0++)
2470 if ((mask & (1 << ls0)) == 0)
2473 for (ls1 = ls0; ls1 < 32; ls1++)
2474 if ((mask & (1 << ls1)) != 0)
2477 for (ms0 = ls1; ms0 < 32; ms0++)
2478 if ((mask & (1 << ms0)) == 0)
2491 operands[2] = GEN_INT (len);
2492 return "{extru|extrw,u} %1,31,%2,%0";
2496 /* We could use this `depi' for the case above as well, but `depi'
2497 requires one more register file access than an `extru'. */
2502 operands[2] = GEN_INT (p);
2503 operands[3] = GEN_INT (len);
2504 return "{depi|depwi} 0,%2,%3,%0";
2508 return "and %1,%2,%0";
2511 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2512 storing the result in operands[0]. */
2514 output_64bit_and (operands)
2517 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2519 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2520 int ls0, ls1, ms0, p, len;
2522 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2523 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2526 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2527 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2530 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2531 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2534 if (ms0 != HOST_BITS_PER_WIDE_INT)
2537 if (ls1 == HOST_BITS_PER_WIDE_INT)
2544 operands[2] = GEN_INT (len);
2545 return "extrd,u %1,63,%2,%0";
2549 /* We could use this `depi' for the case above as well, but `depi'
2550 requires one more register file access than an `extru'. */
2555 operands[2] = GEN_INT (p);
2556 operands[3] = GEN_INT (len);
2557 return "depdi 0,%2,%3,%0";
2561 return "and %1,%2,%0";
2565 output_ior (operands)
2568 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2569 int bs0, bs1, p, len;
2571 if (INTVAL (operands[2]) == 0)
2572 return "copy %1,%0";
2574 for (bs0 = 0; bs0 < 32; bs0++)
2575 if ((mask & (1 << bs0)) != 0)
2578 for (bs1 = bs0; bs1 < 32; bs1++)
2579 if ((mask & (1 << bs1)) == 0)
2582 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2588 operands[2] = GEN_INT (p);
2589 operands[3] = GEN_INT (len);
2590 return "{depi|depwi} -1,%2,%3,%0";
2593 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2594 storing the result in operands[0]. */
2596 output_64bit_ior (operands)
2599 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2600 int bs0, bs1, p, len;
2602 if (INTVAL (operands[2]) == 0)
2603 return "copy %1,%0";
2605 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2606 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2609 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2610 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2613 if (bs1 != HOST_BITS_PER_WIDE_INT
2614 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2620 operands[2] = GEN_INT (p);
2621 operands[3] = GEN_INT (len);
2622 return "depdi -1,%2,%3,%0";
2625 /* Target hook for assembling integer objects. This code handles
2626 aligned SI and DI integers specially, since function references must
2627 be preceded by P%. */
2630 pa_assemble_integer (x, size, aligned_p)
2635 if (size == UNITS_PER_WORD && aligned_p
2636 && function_label_operand (x, VOIDmode))
2638 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2639 output_addr_const (asm_out_file, x);
2640 fputc ('\n', asm_out_file);
2643 return default_assemble_integer (x, size, aligned_p);
2646 /* Output an ascii string. */
2648 output_ascii (file, p, size)
2655 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2657 /* The HP assembler can only take strings of 256 characters at one
2658 time. This is a limitation on input line length, *not* the
2659 length of the string. Sigh. Even worse, it seems that the
2660 restriction is in number of input characters (see \xnn &
2661 \whatever). So we have to do this very carefully. */
2663 fputs ("\t.STRING \"", file);
2666 for (i = 0; i < size; i += 4)
2670 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2672 register unsigned int c = (unsigned char) p[i + io];
2674 if (c == '\"' || c == '\\')
2675 partial_output[co++] = '\\';
2676 if (c >= ' ' && c < 0177)
2677 partial_output[co++] = c;
2681 partial_output[co++] = '\\';
2682 partial_output[co++] = 'x';
2683 hexd = c / 16 - 0 + '0';
2685 hexd -= '9' - 'a' + 1;
2686 partial_output[co++] = hexd;
2687 hexd = c % 16 - 0 + '0';
2689 hexd -= '9' - 'a' + 1;
2690 partial_output[co++] = hexd;
2693 if (chars_output + co > 243)
2695 fputs ("\"\n\t.STRING \"", file);
2698 fwrite (partial_output, 1, (size_t) co, file);
2702 fputs ("\"\n", file);
2705 /* Try to rewrite floating point comparisons & branches to avoid
2706 useless add,tr insns.
2708 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2709 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2710 first attempt to remove useless add,tr insns. It is zero
2711 for the second pass as reorg sometimes leaves bogus REG_DEAD
2714 When CHECK_NOTES is zero we can only eliminate add,tr insns
2715 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2718 remove_useless_addtr_insns (insns, check_notes)
2723 static int pass = 0;
2725 /* This is fairly cheap, so always run it when optimizing. */
2729 int fbranch_count = 0;
2731 /* Walk all the insns in this function looking for fcmp & fbranch
2732 instructions. Keep track of how many of each we find. */
2733 insns = get_insns ();
2734 for (insn = insns; insn; insn = next_insn (insn))
2738 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2739 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2742 tmp = PATTERN (insn);
2744 /* It must be a set. */
2745 if (GET_CODE (tmp) != SET)
2748 /* If the destination is CCFP, then we've found an fcmp insn. */
2749 tmp = SET_DEST (tmp);
2750 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2756 tmp = PATTERN (insn);
2757 /* If this is an fbranch instruction, bump the fbranch counter. */
2758 if (GET_CODE (tmp) == SET
2759 && SET_DEST (tmp) == pc_rtx
2760 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2761 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2762 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2763 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2771 /* Find all floating point compare + branch insns. If possible,
2772 reverse the comparison & the branch to avoid add,tr insns. */
2773 for (insn = insns; insn; insn = next_insn (insn))
2777 /* Ignore anything that isn't an INSN. */
2778 if (GET_CODE (insn) != INSN)
2781 tmp = PATTERN (insn);
2783 /* It must be a set. */
2784 if (GET_CODE (tmp) != SET)
2787 /* The destination must be CCFP, which is register zero. */
2788 tmp = SET_DEST (tmp);
2789 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2792 /* INSN should be a set of CCFP.
2794 See if the result of this insn is used in a reversed FP
2795 conditional branch. If so, reverse our condition and
2796 the branch. Doing so avoids useless add,tr insns. */
2797 next = next_insn (insn);
2800 /* Jumps, calls and labels stop our search. */
2801 if (GET_CODE (next) == JUMP_INSN
2802 || GET_CODE (next) == CALL_INSN
2803 || GET_CODE (next) == CODE_LABEL)
2806 /* As does another fcmp insn. */
2807 if (GET_CODE (next) == INSN
2808 && GET_CODE (PATTERN (next)) == SET
2809 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2810 && REGNO (SET_DEST (PATTERN (next))) == 0)
2813 next = next_insn (next);
2816 /* Is NEXT_INSN a branch? */
2818 && GET_CODE (next) == JUMP_INSN)
2820 rtx pattern = PATTERN (next);
2822 /* If it a reversed fp conditional branch (eg uses add,tr)
2823 and CCFP dies, then reverse our conditional and the branch
2824 to avoid the add,tr. */
2825 if (GET_CODE (pattern) == SET
2826 && SET_DEST (pattern) == pc_rtx
2827 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2828 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2829 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2830 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2831 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2832 && (fcmp_count == fbranch_count
2834 && find_regno_note (next, REG_DEAD, 0))))
2836 /* Reverse the branch. */
2837 tmp = XEXP (SET_SRC (pattern), 1);
2838 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2839 XEXP (SET_SRC (pattern), 2) = tmp;
2840 INSN_CODE (next) = -1;
2842 /* Reverse our condition. */
2843 tmp = PATTERN (insn);
2844 PUT_CODE (XEXP (tmp, 1),
2845 (reverse_condition_maybe_unordered
2846 (GET_CODE (XEXP (tmp, 1)))));
2856 /* You may have trouble believing this, but this is the 32 bit HP-PA
2861 Variable arguments (optional; any number may be allocated)
2863 SP-(4*(N+9)) arg word N
2868 Fixed arguments (must be allocated; may remain unused)
2877 SP-32 External Data Pointer (DP)
2879 SP-24 External/stub RP (RP')
2883 SP-8 Calling Stub RP (RP'')
2888 SP-0 Stack Pointer (points to next available address)
2892 /* This function saves registers as follows. Registers marked with ' are
2893 this function's registers (as opposed to the previous function's).
2894 If a frame_pointer isn't needed, r4 is saved as a general register;
2895 the space for the frame pointer is still allocated, though, to keep
2901 SP (FP') Previous FP
2902 SP + 4 Alignment filler (sigh)
2903 SP + 8 Space for locals reserved here.
2907 SP + n All call saved register used.
2911 SP + o All call saved fp registers used.
2915 SP + p (SP') points to next available address.
2919 /* Global variables set by output_function_prologue(). */
2920 /* Size of frame. Need to know this to emit return insns from
2922 static int actual_fsize;
2923 static int local_fsize, save_fregs;
2925 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2926 Handle case where DISP > 8k by using the add_high_const patterns.
2928 Note in DISP > 8k case, we will leave the high part of the address
2929 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2932 store_reg (reg, disp, base)
2933 int reg, disp, base;
2935 rtx insn, dest, src, basereg;
2937 src = gen_rtx_REG (word_mode, reg);
2938 basereg = gen_rtx_REG (Pmode, base);
2939 if (VAL_14_BITS_P (disp))
2941 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2942 insn = emit_move_insn (dest, src);
2946 rtx delta = GEN_INT (disp);
2947 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
2948 rtx tmpreg = gen_rtx_REG (Pmode, 1);
2949 emit_move_insn (tmpreg, high);
2950 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
2951 insn = emit_move_insn (dest, src);
2955 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2956 gen_rtx_SET (VOIDmode,
2957 gen_rtx_MEM (word_mode,
2958 gen_rtx_PLUS (word_mode, basereg,
2966 RTX_FRAME_RELATED_P (insn) = 1;
2969 /* Emit RTL to store REG at the memory location specified by BASE and then
2970 add MOD to BASE. MOD must be <= 8k. */
2973 store_reg_modify (base, reg, mod)
2976 rtx insn, basereg, srcreg, delta;
2978 if (! VAL_14_BITS_P (mod))
2981 basereg = gen_rtx_REG (Pmode, base);
2982 srcreg = gen_rtx_REG (word_mode, reg);
2983 delta = GEN_INT (mod);
2985 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
2988 RTX_FRAME_RELATED_P (insn) = 1;
2990 /* RTX_FRAME_RELATED_P must be set on each frame related set
2991 in a parallel with more than one element. Don't set
2992 RTX_FRAME_RELATED_P in the first set if reg is temporary
2993 register 1. The effect of this operation is recorded in
2994 the initial copy. */
2997 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
2998 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3002 /* The first element of a PARALLEL is always processed if it is
3003 a SET. Thus, we need an expression list for this case. */
3005 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3006 gen_rtx_SET (VOIDmode, basereg,
3007 gen_rtx_PLUS (word_mode, basereg, delta)),
3013 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3014 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3015 whether to add a frame note or not.
3017 In the DISP > 8k case, we leave the high part of the address in %r1.
3018 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3021 set_reg_plus_d (reg, base, disp, note)
3022 int reg, base, disp, note;
3026 if (VAL_14_BITS_P (disp))
3028 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3029 plus_constant (gen_rtx_REG (Pmode, base), disp));
3033 rtx basereg = gen_rtx_REG (Pmode, base);
3034 rtx delta = GEN_INT (disp);
3036 emit_move_insn (gen_rtx_REG (Pmode, 1),
3037 gen_rtx_PLUS (Pmode, basereg,
3038 gen_rtx_HIGH (Pmode, delta)));
3039 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3040 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
3044 if (DO_FRAME_NOTES && note)
3045 RTX_FRAME_RELATED_P (insn) = 1;
3049 compute_frame_size (size, fregs_live)
3055 /* Space for frame pointer + filler. If any frame is allocated
3056 we need to add this in because of STARTING_FRAME_OFFSET.
3058 Similar code also appears in hppa_expand_prologue. Change both
3059 of them at the same time. */
3060 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
3062 /* If the current function calls __builtin_eh_return, then we need
3063 to allocate stack space for registers that will hold data for
3064 the exception handler. */
3065 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3069 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3071 fsize += i * UNITS_PER_WORD;
3074 /* Account for space used by the callee general register saves. */
3075 for (i = 18; i >= 3; i--)
3076 if (regs_ever_live[i])
3077 fsize += UNITS_PER_WORD;
3079 /* Round the stack. */
3080 fsize = (fsize + 7) & ~7;
3082 /* Account for space used by the callee floating point register saves. */
3083 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3084 if (regs_ever_live[i]
3085 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3090 /* We always save both halves of the FP register, so always
3091 increment the frame size by 8 bytes. */
3095 /* The various ABIs include space for the outgoing parameters in the
3096 size of the current function's stack frame. */
3097 fsize += current_function_outgoing_args_size;
3099 /* Allocate space for the fixed frame marker. This space must be
3100 allocated for any function that makes calls or otherwise allocates
3102 if (!current_function_is_leaf || fsize)
3103 fsize += TARGET_64BIT ? 16 : 32;
3105 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
3108 /* Generate the assembly code for function entry. FILE is a stdio
3109 stream to output the code to. SIZE is an int: how many units of
3110 temporary storage to allocate.
3112 Refer to the array `regs_ever_live' to determine which registers to
3113 save; `regs_ever_live[I]' is nonzero if register number I is ever
3114 used in the function. This function is responsible for knowing
3115 which registers should not be saved even if used. */
3117 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3118 of memory. If any fpu reg is used in the function, we allocate
3119 such a block here, at the bottom of the frame, just in case it's needed.
3121 If this function is a leaf procedure, then we may choose not
3122 to do a "save" insn. The decision about whether or not
3123 to do this is made in regclass.c. */
3126 pa_output_function_prologue (file, size)
3128 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3130 /* The function's label and associated .PROC must never be
3131 separated and must be output *after* any profiling declarations
3132 to avoid changing spaces/subspaces within a procedure. */
3133 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3134 fputs ("\t.PROC\n", file);
3136 /* hppa_expand_prologue does the dirty work now. We just need
3137 to output the assembler directives which denote the start
3139 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
3140 if (regs_ever_live[2])
3141 fputs (",CALLS,SAVE_RP", file);
3143 fputs (",NO_CALLS", file);
3145 if (frame_pointer_needed)
3146 fputs (",SAVE_SP", file);
3148 /* Pass on information about the number of callee register saves
3149 performed in the prologue.
3151 The compiler is supposed to pass the highest register number
3152 saved, the assembler then has to adjust that number before
3153 entering it into the unwind descriptor (to account for any
3154 caller saved registers with lower register numbers than the
3155 first callee saved register). */
3157 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3160 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3162 fputs ("\n\t.ENTRY\n", file);
3164 /* If we're using GAS and SOM, and not using the portable runtime model,
3165 then we don't need to accumulate the total number of code bytes. */
3166 if ((TARGET_GAS && TARGET_SOM && ! TARGET_PORTABLE_RUNTIME)
3167 /* FIXME: we can't handle long calls for TARGET_64BIT. */
3169 total_code_bytes = 0;
3170 else if (INSN_ADDRESSES_SET_P ())
3172 unsigned int old_total = total_code_bytes;
3174 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_insn ()));
3175 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3177 /* Be prepared to handle overflows. */
3178 if (old_total > total_code_bytes)
3179 total_code_bytes = -1;
3182 total_code_bytes = -1;
3184 remove_useless_addtr_insns (get_insns (), 0);
3188 hppa_expand_prologue ()
3190 int size = get_frame_size ();
3191 int merge_sp_adjust_with_store = 0;
3199 /* Allocate space for frame pointer + filler. If any frame is allocated
3200 we need to add this in because of STARTING_FRAME_OFFSET.
3202 Similar code also appears in compute_frame_size. Change both
3203 of them at the same time. */
3204 local_fsize = size + (size || frame_pointer_needed
3205 ? STARTING_FRAME_OFFSET : 0);
3207 actual_fsize = compute_frame_size (size, &save_fregs);
3209 /* Compute a few things we will use often. */
3210 tmpreg = gen_rtx_REG (word_mode, 1);
3212 /* Save RP first. The calling conventions manual states RP will
3213 always be stored into the caller's frame at sp - 20 or sp - 16
3214 depending on which ABI is in use. */
3215 if (regs_ever_live[2] || current_function_calls_eh_return)
3216 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3218 /* Allocate the local frame and set up the frame pointer if needed. */
3219 if (actual_fsize != 0)
3221 if (frame_pointer_needed)
3223 /* Copy the old frame pointer temporarily into %r1. Set up the
3224 new stack pointer, then store away the saved old frame pointer
3225 into the stack at sp and at the same time update the stack
3226 pointer by actual_fsize bytes. Two versions, first
3227 handles small (<8k) frames. The second handles large (>=8k)
3229 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3232 /* We need to record the frame pointer save here since the
3233 new frame pointer is set in the following insn. */
3234 RTX_FRAME_RELATED_P (insn) = 1;
3236 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3237 gen_rtx_SET (VOIDmode,
3238 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3243 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3245 RTX_FRAME_RELATED_P (insn) = 1;
3247 if (VAL_14_BITS_P (actual_fsize))
3248 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3251 /* It is incorrect to store the saved frame pointer at *sp,
3252 then increment sp (writes beyond the current stack boundary).
3254 So instead use stwm to store at *sp and post-increment the
3255 stack pointer as an atomic operation. Then increment sp to
3256 finish allocating the new frame. */
3257 int adjust1 = 8192 - 64;
3258 int adjust2 = actual_fsize - adjust1;
3260 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3261 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3265 /* Prevent register spills from being scheduled before the
3266 stack pointer is raised. Necessary as we will be storing
3267 registers using the frame pointer as a base register, and
3268 we happen to set fp before raising sp. */
3269 emit_insn (gen_blockage ());
3271 /* no frame pointer needed. */
3274 /* In some cases we can perform the first callee register save
3275 and allocating the stack frame at the same time. If so, just
3276 make a note of it and defer allocating the frame until saving
3277 the callee registers. */
3278 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3279 merge_sp_adjust_with_store = 1;
3280 /* Can not optimize. Adjust the stack frame by actual_fsize
3283 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3288 /* Normal register save.
3290 Do not save the frame pointer in the frame_pointer_needed case. It
3291 was done earlier. */
3292 if (frame_pointer_needed)
3294 offset = local_fsize;
3296 /* Saving the EH return data registers in the frame is the simplest
3297 way to get the frame unwind information emitted. We put them
3298 just before the general registers. */
3299 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3301 unsigned int i, regno;
3305 regno = EH_RETURN_DATA_REGNO (i);
3306 if (regno == INVALID_REGNUM)
3309 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3310 offset += UNITS_PER_WORD;
3314 for (i = 18; i >= 4; i--)
3315 if (regs_ever_live[i] && ! call_used_regs[i])
3317 store_reg (i, offset, FRAME_POINTER_REGNUM);
3318 offset += UNITS_PER_WORD;
3321 /* Account for %r3 which is saved in a special place. */
3324 /* No frame pointer needed. */
3327 offset = local_fsize - actual_fsize;
3329 /* Saving the EH return data registers in the frame is the simplest
3330 way to get the frame unwind information emitted. */
3331 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3333 unsigned int i, regno;
3337 regno = EH_RETURN_DATA_REGNO (i);
3338 if (regno == INVALID_REGNUM)
3341 /* If merge_sp_adjust_with_store is nonzero, then we can
3342 optimize the first save. */
3343 if (merge_sp_adjust_with_store)
3345 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3346 merge_sp_adjust_with_store = 0;
3349 store_reg (regno, offset, STACK_POINTER_REGNUM);
3350 offset += UNITS_PER_WORD;
3354 for (i = 18; i >= 3; i--)
3355 if (regs_ever_live[i] && ! call_used_regs[i])
3357 /* If merge_sp_adjust_with_store is nonzero, then we can
3358 optimize the first GR save. */
3359 if (merge_sp_adjust_with_store)
3361 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3362 merge_sp_adjust_with_store = 0;
3365 store_reg (i, offset, STACK_POINTER_REGNUM);
3366 offset += UNITS_PER_WORD;
3370 /* If we wanted to merge the SP adjustment with a GR save, but we never
3371 did any GR saves, then just emit the adjustment here. */
3372 if (merge_sp_adjust_with_store)
3373 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3377 /* The hppa calling conventions say that %r19, the pic offset
3378 register, is saved at sp - 32 (in this function's frame)
3379 when generating PIC code. FIXME: What is the correct thing
3380 to do for functions which make no calls and allocate no
3381 frame? Do we need to allocate a frame, or can we just omit
3382 the save? For now we'll just omit the save. */
3383 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3384 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3386 /* Align pointer properly (doubleword boundary). */
3387 offset = (offset + 7) & ~7;
3389 /* Floating point register store. */
3394 /* First get the frame or stack pointer to the start of the FP register
3396 if (frame_pointer_needed)
3398 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3399 base = frame_pointer_rtx;
3403 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3404 base = stack_pointer_rtx;
3407 /* Now actually save the FP registers. */
3408 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3410 if (regs_ever_live[i]
3411 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3413 rtx addr, insn, reg;
3414 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3415 reg = gen_rtx_REG (DFmode, i);
3416 insn = emit_move_insn (addr, reg);
3419 RTX_FRAME_RELATED_P (insn) = 1;
3422 rtx mem = gen_rtx_MEM (DFmode,
3423 plus_constant (base, offset));
3425 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3426 gen_rtx_SET (VOIDmode, mem, reg),
3431 rtx meml = gen_rtx_MEM (SFmode,
3432 plus_constant (base, offset));
3433 rtx memr = gen_rtx_MEM (SFmode,
3434 plus_constant (base, offset + 4));
3435 rtx regl = gen_rtx_REG (SFmode, i);
3436 rtx regr = gen_rtx_REG (SFmode, i + 1);
3437 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3438 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3441 RTX_FRAME_RELATED_P (setl) = 1;
3442 RTX_FRAME_RELATED_P (setr) = 1;
3443 vec = gen_rtvec (2, setl, setr);
3445 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3446 gen_rtx_SEQUENCE (VOIDmode, vec),
3450 offset += GET_MODE_SIZE (DFmode);
3456 /* FIXME: expand_call and expand_millicode_call need to be fixed to
3457 prevent insns with frame notes being scheduled in the delay slot
3458 of calls. This causes problems because the dwarf2 output code
3459 processes the insn list serially. For now, limit the migration
3460 of prologue insns with a blockage. */
3462 emit_insn (gen_blockage ());
3465 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3466 Handle case where DISP > 8k by using the add_high_const patterns. */
3469 load_reg (reg, disp, base)
3470 int reg, disp, base;
3472 rtx src, dest, basereg;
3474 dest = gen_rtx_REG (word_mode, reg);
3475 basereg = gen_rtx_REG (Pmode, base);
3476 if (VAL_14_BITS_P (disp))
3478 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3479 emit_move_insn (dest, src);
3483 rtx delta = GEN_INT (disp);
3484 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3485 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3486 emit_move_insn (tmpreg, high);
3487 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3488 emit_move_insn (dest, src);
3492 /* This function generates the assembly code for function exit.
3493 Args are as for output_function_prologue ().
3495 The function epilogue should not depend on the current stack
3496 pointer! It should use the frame pointer only. This is mandatory
3497 because of alloca; we also take advantage of it to omit stack
3498 adjustments before returning. */
3501 pa_output_function_epilogue (file, size)
3503 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3505 rtx insn = get_last_insn ();
3507 /* hppa_expand_epilogue does the dirty work now. We just need
3508 to output the assembler directives which denote the end
3511 To make debuggers happy, emit a nop if the epilogue was completely
3512 eliminated due to a volatile call as the last insn in the
3513 current function. That way the return address (in %r2) will
3514 always point to a valid instruction in the current function. */
3516 /* Get the last real insn. */
3517 if (GET_CODE (insn) == NOTE)
3518 insn = prev_real_insn (insn);
3520 /* If it is a sequence, then look inside. */
3521 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3522 insn = XVECEXP (PATTERN (insn), 0, 0);
3524 /* If insn is a CALL_INSN, then it must be a call to a volatile
3525 function (otherwise there would be epilogue insns). */
3526 if (insn && GET_CODE (insn) == CALL_INSN)
3527 fputs ("\tnop\n", file);
3529 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3533 hppa_expand_epilogue ()
3537 int merge_sp_adjust_with_load = 0;
3540 /* We will use this often. */
3541 tmpreg = gen_rtx_REG (word_mode, 1);
3543 /* Try to restore RP early to avoid load/use interlocks when
3544 RP gets used in the return (bv) instruction. This appears to still
3545 be necessary even when we schedule the prologue and epilogue. */
3546 if (regs_ever_live [2] || current_function_calls_eh_return)
3548 ret_off = TARGET_64BIT ? -16 : -20;
3549 if (frame_pointer_needed)
3551 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3556 /* No frame pointer, and stack is smaller than 8k. */
3557 if (VAL_14_BITS_P (ret_off - actual_fsize))
3559 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3565 /* General register restores. */
3566 if (frame_pointer_needed)
3568 offset = local_fsize;
3570 /* If the current function calls __builtin_eh_return, then we need
3571 to restore the saved EH data registers. */
3572 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3574 unsigned int i, regno;
3578 regno = EH_RETURN_DATA_REGNO (i);
3579 if (regno == INVALID_REGNUM)
3582 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3583 offset += UNITS_PER_WORD;
3587 for (i = 18; i >= 4; i--)
3588 if (regs_ever_live[i] && ! call_used_regs[i])
3590 load_reg (i, offset, FRAME_POINTER_REGNUM);
3591 offset += UNITS_PER_WORD;
3596 offset = local_fsize - actual_fsize;
3598 /* If the current function calls __builtin_eh_return, then we need
3599 to restore the saved EH data registers. */
3600 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3602 unsigned int i, regno;
3606 regno = EH_RETURN_DATA_REGNO (i);
3607 if (regno == INVALID_REGNUM)
3610 /* Only for the first load.
3611 merge_sp_adjust_with_load holds the register load
3612 with which we will merge the sp adjustment. */
3613 if (merge_sp_adjust_with_load == 0
3615 && VAL_14_BITS_P (-actual_fsize))
3616 merge_sp_adjust_with_load = regno;
3618 load_reg (regno, offset, STACK_POINTER_REGNUM);
3619 offset += UNITS_PER_WORD;
3623 for (i = 18; i >= 3; i--)
3625 if (regs_ever_live[i] && ! call_used_regs[i])
3627 /* Only for the first load.
3628 merge_sp_adjust_with_load holds the register load
3629 with which we will merge the sp adjustment. */
3630 if (merge_sp_adjust_with_load == 0
3632 && VAL_14_BITS_P (-actual_fsize))
3633 merge_sp_adjust_with_load = i;
3635 load_reg (i, offset, STACK_POINTER_REGNUM);
3636 offset += UNITS_PER_WORD;
3641 /* Align pointer properly (doubleword boundary). */
3642 offset = (offset + 7) & ~7;
3644 /* FP register restores. */
3647 /* Adjust the register to index off of. */
3648 if (frame_pointer_needed)
3649 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3651 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3653 /* Actually do the restores now. */
3654 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3655 if (regs_ever_live[i]
3656 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3658 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3659 rtx dest = gen_rtx_REG (DFmode, i);
3660 emit_move_insn (dest, src);
3664 /* Emit a blockage insn here to keep these insns from being moved to
3665 an earlier spot in the epilogue, or into the main instruction stream.
3667 This is necessary as we must not cut the stack back before all the
3668 restores are finished. */
3669 emit_insn (gen_blockage ());
3671 /* Reset stack pointer (and possibly frame pointer). The stack
3672 pointer is initially set to fp + 64 to avoid a race condition. */
3673 if (frame_pointer_needed)
3675 rtx delta = GEN_INT (-64);
3677 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
3678 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
3680 /* If we were deferring a callee register restore, do it now. */
3681 else if (merge_sp_adjust_with_load)
3683 rtx delta = GEN_INT (-actual_fsize);
3684 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3686 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
3688 else if (actual_fsize != 0)
3689 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3692 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3693 frame greater than 8k), do so now. */
3695 load_reg (2, ret_off, STACK_POINTER_REGNUM);
3697 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3699 rtx sa = EH_RETURN_STACKADJ_RTX;
3701 emit_insn (gen_blockage ());
3702 emit_insn (TARGET_64BIT
3703 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
3704 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
3709 hppa_pic_save_rtx ()
3711 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3715 hppa_profile_hook (label_no)
3718 rtx begin_label_rtx, call_insn;
3719 char begin_label_name[16];
3721 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3723 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3726 emit_move_insn (arg_pointer_rtx,
3727 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3730 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3732 #ifndef NO_PROFILE_COUNTERS
3734 rtx count_label_rtx, addr, r24;
3735 char count_label_name[16];
3737 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3738 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3740 addr = force_reg (Pmode, count_label_rtx);
3741 r24 = gen_rtx_REG (Pmode, 24);
3742 emit_move_insn (r24, addr);
3744 /* %r25 is set from within the output pattern. */
3746 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3747 GEN_INT (TARGET_64BIT ? 24 : 12),
3750 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3753 /* %r25 is set from within the output pattern. */
3755 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3756 GEN_INT (TARGET_64BIT ? 16 : 8),
3760 /* Indicate the _mcount call cannot throw, nor will it execute a
3762 REG_NOTES (call_insn)
3763 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3767 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3769 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3771 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3775 /* Fetch the return address for the frame COUNT steps up from
3776 the current frame, after the prologue. FRAMEADDR is the
3777 frame pointer of the COUNT frame.
3779 We want to ignore any export stub remnants here. To handle this,
3780 we examine the code at the return address, and if it is an export
3781 stub, we return a memory rtx for the stub return address stored
3784 The value returned is used in two different ways:
3786 1. To find a function's caller.
3788 2. To change the return address for a function.
3790 This function handles most instances of case 1; however, it will
3791 fail if there are two levels of stubs to execute on the return
3792 path. The only way I believe that can happen is if the return value
3793 needs a parameter relocation, which never happens for C code.
3795 This function handles most instances of case 2; however, it will
3796 fail if we did not originally have stub code on the return path
3797 but will need stub code on the new return path. This can happen if
3798 the caller & callee are both in the main program, but the new
3799 return location is in a shared library. */
3802 return_addr_rtx (count, frameaddr)
3814 rp = get_hard_reg_initial_val (Pmode, 2);
3816 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
3819 saved_rp = gen_reg_rtx (Pmode);
3820 emit_move_insn (saved_rp, rp);
3822 /* Get pointer to the instruction stream. We have to mask out the
3823 privilege level from the two low order bits of the return address
3824 pointer here so that ins will point to the start of the first
3825 instruction that would have been executed if we returned. */
3826 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
3827 label = gen_label_rtx ();
3829 /* Check the instruction stream at the normal return address for the
3832 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3833 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3834 0x00011820 | stub+16: mtsp r1,sr0
3835 0xe0400002 | stub+20: be,n 0(sr0,rp)
3837 If it is an export stub, than our return address is really in
3840 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
3841 NULL_RTX, SImode, 1);
3842 emit_jump_insn (gen_bne (label));
3844 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3845 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
3846 emit_jump_insn (gen_bne (label));
3848 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3849 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
3850 emit_jump_insn (gen_bne (label));
3852 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3853 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
3855 /* If there is no export stub then just use the value saved from
3856 the return pointer register. */
3858 emit_jump_insn (gen_bne (label));
3860 /* Here we know that our return address points to an export
3861 stub. We don't want to return the address of the export stub,
3862 but rather the return address of the export stub. That return
3863 address is stored at -24[frameaddr]. */
3865 emit_move_insn (saved_rp,
3867 memory_address (Pmode,
3868 plus_constant (frameaddr,
3875 /* This is only valid once reload has completed because it depends on
3876 knowing exactly how much (if any) frame there is and...
3878 It's only valid if there is no frame marker to de-allocate and...
3880 It's only valid if %r2 hasn't been saved into the caller's frame
3881 (we're not profiling and %r2 isn't live anywhere). */
3883 hppa_can_use_return_insn_p ()
3885 return (reload_completed
3886 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3887 && ! regs_ever_live[2]
3888 && ! frame_pointer_needed);
3892 emit_bcond_fp (code, operand0)
3896 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3897 gen_rtx_IF_THEN_ELSE (VOIDmode,
3898 gen_rtx_fmt_ee (code,
3900 gen_rtx_REG (CCFPmode, 0),
3902 gen_rtx_LABEL_REF (VOIDmode, operand0),
3908 gen_cmp_fp (code, operand0, operand1)
3910 rtx operand0, operand1;
3912 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3913 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3916 /* Adjust the cost of a scheduling dependency. Return the new cost of
3917 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3920 pa_adjust_cost (insn, link, dep_insn, cost)
3926 enum attr_type attr_type;
3928 /* Don't adjust costs for a pa8000 chip, also do not adjust any
3929 true dependencies as they are described with bypasses now. */
3930 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
3933 if (! recog_memoized (insn))
3936 attr_type = get_attr_type (insn);
3938 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3940 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3943 if (attr_type == TYPE_FPLOAD)
3945 rtx pat = PATTERN (insn);
3946 rtx dep_pat = PATTERN (dep_insn);
3947 if (GET_CODE (pat) == PARALLEL)
3949 /* This happens for the fldXs,mb patterns. */
3950 pat = XVECEXP (pat, 0, 0);
3952 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3953 /* If this happens, we have to extend this to schedule
3954 optimally. Return 0 for now. */
3957 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3959 if (! recog_memoized (dep_insn))
3961 switch (get_attr_type (dep_insn))
3968 case TYPE_FPSQRTSGL:
3969 case TYPE_FPSQRTDBL:
3970 /* A fpload can't be issued until one cycle before a
3971 preceding arithmetic operation has finished if
3972 the target of the fpload is any of the sources
3973 (or destination) of the arithmetic operation. */
3974 return insn_default_latency (dep_insn) - 1;
3981 else if (attr_type == TYPE_FPALU)
3983 rtx pat = PATTERN (insn);
3984 rtx dep_pat = PATTERN (dep_insn);
3985 if (GET_CODE (pat) == PARALLEL)
3987 /* This happens for the fldXs,mb patterns. */
3988 pat = XVECEXP (pat, 0, 0);
3990 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3991 /* If this happens, we have to extend this to schedule
3992 optimally. Return 0 for now. */
3995 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3997 if (! recog_memoized (dep_insn))
3999 switch (get_attr_type (dep_insn))
4003 case TYPE_FPSQRTSGL:
4004 case TYPE_FPSQRTDBL:
4005 /* An ALU flop can't be issued until two cycles before a
4006 preceding divide or sqrt operation has finished if
4007 the target of the ALU flop is any of the sources
4008 (or destination) of the divide or sqrt operation. */
4009 return insn_default_latency (dep_insn) - 2;
4017 /* For other anti dependencies, the cost is 0. */
4020 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4022 /* Output dependency; DEP_INSN writes a register that INSN writes some
4024 if (attr_type == TYPE_FPLOAD)
4026 rtx pat = PATTERN (insn);
4027 rtx dep_pat = PATTERN (dep_insn);
4028 if (GET_CODE (pat) == PARALLEL)
4030 /* This happens for the fldXs,mb patterns. */
4031 pat = XVECEXP (pat, 0, 0);
4033 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4034 /* If this happens, we have to extend this to schedule
4035 optimally. Return 0 for now. */
4038 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4040 if (! recog_memoized (dep_insn))
4042 switch (get_attr_type (dep_insn))
4049 case TYPE_FPSQRTSGL:
4050 case TYPE_FPSQRTDBL:
4051 /* A fpload can't be issued until one cycle before a
4052 preceding arithmetic operation has finished if
4053 the target of the fpload is the destination of the
4054 arithmetic operation.
4056 Exception: For PA7100LC, PA7200 and PA7300, the cost
4057 is 3 cycles, unless they bundle together. We also
4058 pay the penalty if the second insn is a fpload. */
4059 return insn_default_latency (dep_insn) - 1;
4066 else if (attr_type == TYPE_FPALU)
4068 rtx pat = PATTERN (insn);
4069 rtx dep_pat = PATTERN (dep_insn);
4070 if (GET_CODE (pat) == PARALLEL)
4072 /* This happens for the fldXs,mb patterns. */
4073 pat = XVECEXP (pat, 0, 0);
4075 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4076 /* If this happens, we have to extend this to schedule
4077 optimally. Return 0 for now. */
4080 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4082 if (! recog_memoized (dep_insn))
4084 switch (get_attr_type (dep_insn))
4088 case TYPE_FPSQRTSGL:
4089 case TYPE_FPSQRTDBL:
4090 /* An ALU flop can't be issued until two cycles before a
4091 preceding divide or sqrt operation has finished if
4092 the target of the ALU flop is also the target of
4093 the divide or sqrt operation. */
4094 return insn_default_latency (dep_insn) - 2;
4102 /* For other output dependencies, the cost is 0. */
4109 /* Adjust scheduling priorities. We use this to try and keep addil
4110 and the next use of %r1 close together. */
4112 pa_adjust_priority (insn, priority)
4116 rtx set = single_set (insn);
4120 src = SET_SRC (set);
4121 dest = SET_DEST (set);
4122 if (GET_CODE (src) == LO_SUM
4123 && symbolic_operand (XEXP (src, 1), VOIDmode)
4124 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4127 else if (GET_CODE (src) == MEM
4128 && GET_CODE (XEXP (src, 0)) == LO_SUM
4129 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4130 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4133 else if (GET_CODE (dest) == MEM
4134 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4135 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4136 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4142 /* The 700 can only issue a single insn at a time.
4143 The 7XXX processors can issue two insns at a time.
4144 The 8000 can issue 4 insns at a time. */
4150 case PROCESSOR_700: return 1;
4151 case PROCESSOR_7100: return 2;
4152 case PROCESSOR_7100LC: return 2;
4153 case PROCESSOR_7200: return 2;
4154 case PROCESSOR_7300: return 2;
4155 case PROCESSOR_8000: return 4;
4164 /* Return any length adjustment needed by INSN which already has its length
4165 computed as LENGTH. Return zero if no adjustment is necessary.
4167 For the PA: function calls, millicode calls, and backwards short
4168 conditional branches with unfilled delay slots need an adjustment by +1
4169 (to account for the NOP which will be inserted into the instruction stream).
4171 Also compute the length of an inline block move here as it is too
4172 complicated to express as a length attribute in pa.md. */
4174 pa_adjust_insn_length (insn, length)
4178 rtx pat = PATTERN (insn);
4180 /* Call insns which are *not* indirect and have unfilled delay slots. */
4181 if (GET_CODE (insn) == CALL_INSN)
4184 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4185 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4187 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4188 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4194 /* Jumps inside switch tables which have unfilled delay slots
4195 also need adjustment. */
4196 else if (GET_CODE (insn) == JUMP_INSN
4197 && simplejump_p (insn)
4198 && GET_MODE (insn) == SImode)
4200 /* Millicode insn with an unfilled delay slot. */
4201 else if (GET_CODE (insn) == INSN
4202 && GET_CODE (pat) != SEQUENCE
4203 && GET_CODE (pat) != USE
4204 && GET_CODE (pat) != CLOBBER
4205 && get_attr_type (insn) == TYPE_MILLI)
4207 /* Block move pattern. */
4208 else if (GET_CODE (insn) == INSN
4209 && GET_CODE (pat) == PARALLEL
4210 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4211 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4212 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4213 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4214 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4215 return compute_movstrsi_length (insn) - 4;
4216 /* Conditional branch with an unfilled delay slot. */
4217 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4219 /* Adjust a short backwards conditional with an unfilled delay slot. */
4220 if (GET_CODE (pat) == SET
4222 && ! forward_branch_p (insn))
4224 else if (GET_CODE (pat) == PARALLEL
4225 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4228 /* Adjust dbra insn with short backwards conditional branch with
4229 unfilled delay slot -- only for case where counter is in a
4230 general register register. */
4231 else if (GET_CODE (pat) == PARALLEL
4232 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4233 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4234 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4236 && ! forward_branch_p (insn))
4244 /* Print operand X (an rtx) in assembler syntax to file FILE.
4245 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4246 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4249 print_operand (file, x, code)
4257 /* Output a 'nop' if there's nothing for the delay slot. */
4258 if (dbr_sequence_length () == 0)
4259 fputs ("\n\tnop", file);
4262 /* Output an nullification completer if there's nothing for the */
4263 /* delay slot or nullification is requested. */
4264 if (dbr_sequence_length () == 0 ||
4266 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4270 /* Print out the second register name of a register pair.
4271 I.e., R (6) => 7. */
4272 fputs (reg_names[REGNO (x) + 1], file);
4275 /* A register or zero. */
4277 || (x == CONST0_RTX (DFmode))
4278 || (x == CONST0_RTX (SFmode)))
4280 fputs ("%r0", file);
4286 /* A register or zero (floating point). */
4288 || (x == CONST0_RTX (DFmode))
4289 || (x == CONST0_RTX (SFmode)))
4291 fputs ("%fr0", file);
4300 xoperands[0] = XEXP (XEXP (x, 0), 0);
4301 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4302 output_global_address (file, xoperands[1], 0);
4303 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4307 case 'C': /* Plain (C)ondition */
4309 switch (GET_CODE (x))
4312 fputs ("=", file); break;
4314 fputs ("<>", file); break;
4316 fputs (">", file); break;
4318 fputs (">=", file); break;
4320 fputs (">>=", file); break;
4322 fputs (">>", file); break;
4324 fputs ("<", file); break;
4326 fputs ("<=", file); break;
4328 fputs ("<<=", file); break;
4330 fputs ("<<", file); break;
4335 case 'N': /* Condition, (N)egated */
4336 switch (GET_CODE (x))
4339 fputs ("<>", file); break;
4341 fputs ("=", file); break;
4343 fputs ("<=", file); break;
4345 fputs ("<", file); break;
4347 fputs ("<<", file); break;
4349 fputs ("<<=", file); break;
4351 fputs (">=", file); break;
4353 fputs (">", file); break;
4355 fputs (">>", file); break;
4357 fputs (">>=", file); break;
4362 /* For floating point comparisons. Note that the output
4363 predicates are the complement of the desired mode. */
4365 switch (GET_CODE (x))
4368 fputs ("!=", file); break;
4370 fputs ("=", file); break;
4372 fputs ("!>", file); break;
4374 fputs ("!>=", file); break;
4376 fputs ("!<", file); break;
4378 fputs ("!<=", file); break;
4380 fputs ("!<>", file); break;
4382 fputs (">", file); break;
4384 fputs (">=", file); break;
4386 fputs ("<", file); break;
4388 fputs ("<=", file); break;
4390 fputs ("<>", file); break;
4392 fputs ("<=>", file); break;
4394 fputs ("!<=>", file); break;
4399 case 'S': /* Condition, operands are (S)wapped. */
4400 switch (GET_CODE (x))
4403 fputs ("=", file); break;
4405 fputs ("<>", file); break;
4407 fputs ("<", file); break;
4409 fputs ("<=", file); break;
4411 fputs ("<<=", file); break;
4413 fputs ("<<", file); break;
4415 fputs (">", file); break;
4417 fputs (">=", file); break;
4419 fputs (">>=", file); break;
4421 fputs (">>", file); break;
4426 case 'B': /* Condition, (B)oth swapped and negate. */
4427 switch (GET_CODE (x))
4430 fputs ("<>", file); break;
4432 fputs ("=", file); break;
4434 fputs (">=", file); break;
4436 fputs (">", file); break;
4438 fputs (">>", file); break;
4440 fputs (">>=", file); break;
4442 fputs ("<=", file); break;
4444 fputs ("<", file); break;
4446 fputs ("<<", file); break;
4448 fputs ("<<=", file); break;
4454 if (GET_CODE (x) == CONST_INT)
4456 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4461 if (GET_CODE (x) == CONST_INT)
4463 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4468 if (GET_CODE (x) == CONST_INT)
4470 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4475 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4477 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4482 if (GET_CODE (x) == CONST_INT)
4484 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4489 if (GET_CODE (x) == CONST_INT)
4491 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4496 if (GET_CODE (x) == CONST_INT)
4501 switch (GET_CODE (XEXP (x, 0)))
4505 if (ASSEMBLER_DIALECT == 0)
4506 fputs ("s,mb", file);
4508 fputs (",mb", file);
4512 if (ASSEMBLER_DIALECT == 0)
4513 fputs ("s,ma", file);
4515 fputs (",ma", file);
4518 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4519 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4521 if (ASSEMBLER_DIALECT == 0)
4522 fputs ("x,s", file);
4526 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4530 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4536 output_global_address (file, x, 0);
4539 output_global_address (file, x, 1);
4541 case 0: /* Don't do anything special */
4546 compute_zdepwi_operands (INTVAL (x), op);
4547 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4553 compute_zdepdi_operands (INTVAL (x), op);
4554 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4558 /* We can get here from a .vtable_inherit due to our
4559 CONSTANT_ADDRESS_P rejecting perfectly good constant
4565 if (GET_CODE (x) == REG)
4567 fputs (reg_names [REGNO (x)], file);
4568 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4574 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4575 && (REGNO (x) & 1) == 0)
4578 else if (GET_CODE (x) == MEM)
4580 int size = GET_MODE_SIZE (GET_MODE (x));
4581 rtx base = NULL_RTX;
4582 switch (GET_CODE (XEXP (x, 0)))
4586 base = XEXP (XEXP (x, 0), 0);
4587 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4591 base = XEXP (XEXP (x, 0), 0);
4592 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4595 if (GET_CODE (XEXP (x, 0)) == PLUS
4596 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4597 fprintf (file, "%s(%s)",
4598 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4599 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4600 else if (GET_CODE (XEXP (x, 0)) == PLUS
4601 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4602 fprintf (file, "%s(%s)",
4603 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4604 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4606 output_address (XEXP (x, 0));
4611 output_addr_const (file, x);
4614 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4617 output_global_address (file, x, round_constant)
4623 /* Imagine (high (const (plus ...))). */
4624 if (GET_CODE (x) == HIGH)
4627 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4628 assemble_name (file, XSTR (x, 0));
4629 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4631 assemble_name (file, XSTR (x, 0));
4632 fputs ("-$global$", file);
4634 else if (GET_CODE (x) == CONST)
4636 const char *sep = "";
4637 int offset = 0; /* assembler wants -$global$ at end */
4638 rtx base = NULL_RTX;
4640 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4642 base = XEXP (XEXP (x, 0), 0);
4643 output_addr_const (file, base);
4645 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4646 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4649 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4651 base = XEXP (XEXP (x, 0), 1);
4652 output_addr_const (file, base);
4654 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4655 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4658 /* How bogus. The compiler is apparently responsible for
4659 rounding the constant if it uses an LR field selector.
4661 The linker and/or assembler seem a better place since
4662 they have to do this kind of thing already.
4664 If we fail to do this, HP's optimizing linker may eliminate
4665 an addil, but not update the ldw/stw/ldo instruction that
4666 uses the result of the addil. */
4668 offset = ((offset + 0x1000) & ~0x1fff);
4670 if (GET_CODE (XEXP (x, 0)) == PLUS)
4680 else if (GET_CODE (XEXP (x, 0)) == MINUS
4681 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4685 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4686 fputs ("-$global$", file);
4688 fprintf (file, "%s%d", sep, offset);
4691 output_addr_const (file, x);
4695 output_deferred_plabels (file)
4699 /* If we have deferred plabels, then we need to switch into the data
4700 section and align it to a 4 byte boundary before we output the
4701 deferred plabels. */
4702 if (n_deferred_plabels)
4705 ASM_OUTPUT_ALIGN (file, 2);
4708 /* Now output the deferred plabels. */
4709 for (i = 0; i < n_deferred_plabels; i++)
4711 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4712 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4713 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
4717 /* HP's millicode routines mean something special to the assembler.
4718 Keep track of which ones we have used. */
4720 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
4721 static void import_milli PARAMS ((enum millicodes));
4722 static char imported[(int) end1000];
4723 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4724 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4725 #define MILLI_START 10
4729 enum millicodes code;
4731 char str[sizeof (import_string)];
4733 if (!imported[(int) code])
4735 imported[(int) code] = 1;
4736 strcpy (str, import_string);
4737 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4738 output_asm_insn (str, 0);
4742 /* The register constraints have put the operands and return value in
4743 the proper registers. */
4746 output_mul_insn (unsignedp, insn)
4747 int unsignedp ATTRIBUTE_UNUSED;
4750 import_milli (mulI);
4751 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4754 /* Emit the rtl for doing a division by a constant. */
4756 /* Do magic division millicodes exist for this value? */
4757 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4760 /* We'll use an array to keep track of the magic millicodes and
4761 whether or not we've used them already. [n][0] is signed, [n][1] is
4764 static int div_milli[16][2];
4767 div_operand (op, mode)
4769 enum machine_mode mode;
4771 return (mode == SImode
4772 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4773 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4774 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4778 emit_hpdiv_const (operands, unsignedp)
4782 if (GET_CODE (operands[2]) == CONST_INT
4783 && INTVAL (operands[2]) > 0
4784 && INTVAL (operands[2]) < 16
4785 && magic_milli[INTVAL (operands[2])])
4787 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4789 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4792 (PARALLEL, VOIDmode,
4793 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4794 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4796 gen_rtx_REG (SImode, 26),
4798 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4799 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4800 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4801 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4802 gen_rtx_CLOBBER (VOIDmode, ret))));
4803 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4810 output_div_insn (operands, unsignedp, insn)
4817 /* If the divisor is a constant, try to use one of the special
4819 if (GET_CODE (operands[0]) == CONST_INT)
4821 static char buf[100];
4822 divisor = INTVAL (operands[0]);
4823 if (!div_milli[divisor][unsignedp])
4825 div_milli[divisor][unsignedp] = 1;
4827 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4829 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4833 sprintf (buf, "$$divU_");
4834 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4835 return output_millicode_call (insn,
4836 gen_rtx_SYMBOL_REF (SImode, buf));
4840 sprintf (buf, "$$divI_");
4841 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4842 return output_millicode_call (insn,
4843 gen_rtx_SYMBOL_REF (SImode, buf));
4846 /* Divisor isn't a special constant. */
4851 import_milli (divU);
4852 return output_millicode_call (insn,
4853 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4857 import_milli (divI);
4858 return output_millicode_call (insn,
4859 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4864 /* Output a $$rem millicode to do mod. */
4867 output_mod_insn (unsignedp, insn)
4873 import_milli (remU);
4874 return output_millicode_call (insn,
4875 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4879 import_milli (remI);
4880 return output_millicode_call (insn,
4881 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4886 output_arg_descriptor (call_insn)
4889 const char *arg_regs[4];
4890 enum machine_mode arg_mode;
4892 int i, output_flag = 0;
4895 /* We neither need nor want argument location descriptors for the
4896 64bit runtime environment or the ELF32 environment. */
4897 if (TARGET_64BIT || TARGET_ELF32)
4900 for (i = 0; i < 4; i++)
4903 /* Specify explicitly that no argument relocations should take place
4904 if using the portable runtime calling conventions. */
4905 if (TARGET_PORTABLE_RUNTIME)
4907 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4912 if (GET_CODE (call_insn) != CALL_INSN)
4914 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4916 rtx use = XEXP (link, 0);
4918 if (! (GET_CODE (use) == USE
4919 && GET_CODE (XEXP (use, 0)) == REG
4920 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4923 arg_mode = GET_MODE (XEXP (use, 0));
4924 regno = REGNO (XEXP (use, 0));
4925 if (regno >= 23 && regno <= 26)
4927 arg_regs[26 - regno] = "GR";
4928 if (arg_mode == DImode)
4929 arg_regs[25 - regno] = "GR";
4931 else if (regno >= 32 && regno <= 39)
4933 if (arg_mode == SFmode)
4934 arg_regs[(regno - 32) / 2] = "FR";
4937 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4938 arg_regs[(regno - 34) / 2] = "FR";
4939 arg_regs[(regno - 34) / 2 + 1] = "FU";
4941 arg_regs[(regno - 34) / 2] = "FU";
4942 arg_regs[(regno - 34) / 2 + 1] = "FR";
4947 fputs ("\t.CALL ", asm_out_file);
4948 for (i = 0; i < 4; i++)
4953 fputc (',', asm_out_file);
4954 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4957 fputc ('\n', asm_out_file);
4960 /* Return the class of any secondary reload register that is needed to
4961 move IN into a register in class CLASS using mode MODE.
4963 Profiling has showed this routine and its descendants account for
4964 a significant amount of compile time (~7%). So it has been
4965 optimized to reduce redundant computations and eliminate useless
4968 It might be worthwhile to try and make this a leaf function too. */
4971 secondary_reload_class (class, mode, in)
4972 enum reg_class class;
4973 enum machine_mode mode;
4976 int regno, is_symbolic;
4978 /* Trying to load a constant into a FP register during PIC code
4979 generation will require %r1 as a scratch register. */
4981 && GET_MODE_CLASS (mode) == MODE_INT
4982 && FP_REG_CLASS_P (class)
4983 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4986 /* Profiling showed the PA port spends about 1.3% of its compilation
4987 time in true_regnum from calls inside secondary_reload_class. */
4989 if (GET_CODE (in) == REG)
4992 if (regno >= FIRST_PSEUDO_REGISTER)
4993 regno = true_regnum (in);
4995 else if (GET_CODE (in) == SUBREG)
4996 regno = true_regnum (in);
5000 /* If we have something like (mem (mem (...)), we can safely assume the
5001 inner MEM will end up in a general register after reloading, so there's
5002 no need for a secondary reload. */
5003 if (GET_CODE (in) == MEM
5004 && GET_CODE (XEXP (in, 0)) == MEM)
5007 /* Handle out of range displacement for integer mode loads/stores of
5009 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5010 && GET_MODE_CLASS (mode) == MODE_INT
5011 && FP_REG_CLASS_P (class))
5012 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5013 return GENERAL_REGS;
5015 /* A SAR<->FP register copy requires a secondary register (GPR) as
5016 well as secondary memory. */
5017 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5018 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5019 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5020 return GENERAL_REGS;
5022 if (GET_CODE (in) == HIGH)
5025 /* Profiling has showed GCC spends about 2.6% of its compilation
5026 time in symbolic_operand from calls inside secondary_reload_class.
5028 We use an inline copy and only compute its return value once to avoid
5030 switch (GET_CODE (in))
5040 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5041 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5042 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5052 && read_only_operand (in, VOIDmode))
5055 if (class != R1_REGS && is_symbolic)
5062 function_arg_padding (mode, type)
5063 enum machine_mode mode;
5068 if (mode == BLKmode)
5070 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
5071 size = int_size_in_bytes (type) * BITS_PER_UNIT;
5073 return upward; /* Don't know if this is right, but */
5074 /* same as old definition. */
5077 size = GET_MODE_BITSIZE (mode);
5078 if (size < PARM_BOUNDARY)
5080 else if (size % PARM_BOUNDARY)
5087 /* Do what is necessary for `va_start'. We look at the current function
5088 to determine if stdargs or varargs is used and fill in an initial
5089 va_list. A pointer to this constructor is returned. */
5092 hppa_builtin_saveregs ()
5095 tree fntype = TREE_TYPE (current_function_decl);
5096 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5097 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5098 != void_type_node)))
5099 ? UNITS_PER_WORD : 0);
5102 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5104 offset = current_function_arg_offset_rtx;
5110 /* Adjust for varargs/stdarg differences. */
5112 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5114 offset = current_function_arg_offset_rtx;
5116 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5117 from the incoming arg pointer and growing to larger addresses. */
5118 for (i = 26, off = -64; i >= 19; i--, off += 8)
5119 emit_move_insn (gen_rtx_MEM (word_mode,
5120 plus_constant (arg_pointer_rtx, off)),
5121 gen_rtx_REG (word_mode, i));
5123 /* The incoming args pointer points just beyond the flushback area;
5124 normally this is not a serious concern. However, when we are doing
5125 varargs/stdargs we want to make the arg pointer point to the start
5126 of the incoming argument area. */
5127 emit_move_insn (virtual_incoming_args_rtx,
5128 plus_constant (arg_pointer_rtx, -64));
5130 /* Now return a pointer to the first anonymous argument. */
5131 return copy_to_reg (expand_binop (Pmode, add_optab,
5132 virtual_incoming_args_rtx,
5133 offset, 0, 0, OPTAB_LIB_WIDEN));
5136 /* Store general registers on the stack. */
5137 dest = gen_rtx_MEM (BLKmode,
5138 plus_constant (current_function_internal_arg_pointer,
5140 set_mem_alias_set (dest, get_varargs_alias_set ());
5141 set_mem_align (dest, BITS_PER_WORD);
5142 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
5144 /* move_block_from_reg will emit code to store the argument registers
5145 individually as scalar stores.
5147 However, other insns may later load from the same addresses for
5148 a structure load (passing a struct to a varargs routine).
5150 The alias code assumes that such aliasing can never happen, so we
5151 have to keep memory referencing insns from moving up beyond the
5152 last argument register store. So we emit a blockage insn here. */
5153 emit_insn (gen_blockage ());
5155 return copy_to_reg (expand_binop (Pmode, add_optab,
5156 current_function_internal_arg_pointer,
5157 offset, 0, 0, OPTAB_LIB_WIDEN));
5161 hppa_va_start (stdarg_p, valist, nextarg)
5162 int stdarg_p ATTRIBUTE_UNUSED;
5166 nextarg = expand_builtin_saveregs ();
5167 std_expand_builtin_va_start (1, valist, nextarg);
5171 hppa_va_arg (valist, type)
5174 HOST_WIDE_INT align, size, ofs;
5179 /* Every argument in PA64 is passed by value (including large structs).
5180 Arguments with size greater than 8 must be aligned 0 MOD 16. */
5182 size = int_size_in_bytes (type);
5183 if (size > UNITS_PER_WORD)
5185 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5186 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5187 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5188 build_int_2 (-2 * UNITS_PER_WORD, -1));
5189 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5190 TREE_SIDE_EFFECTS (t) = 1;
5191 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5193 return std_expand_builtin_va_arg (valist, type);
5196 /* Compute the rounded size of the type. */
5197 align = PARM_BOUNDARY / BITS_PER_UNIT;
5198 size = int_size_in_bytes (type);
5200 ptr = build_pointer_type (type);
5202 /* "Large" types are passed by reference. */
5205 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5206 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5207 TREE_SIDE_EFFECTS (t) = 1;
5209 pptr = build_pointer_type (ptr);
5210 t = build1 (NOP_EXPR, pptr, t);
5211 TREE_SIDE_EFFECTS (t) = 1;
5213 t = build1 (INDIRECT_REF, ptr, t);
5214 TREE_SIDE_EFFECTS (t) = 1;
5218 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5219 build_int_2 (-size, -1));
5221 /* Copied from va-pa.h, but we probably don't need to align
5222 to word size, since we generate and preserve that invariant. */
5223 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5224 build_int_2 ((size > 4 ? -8 : -4), -1));
5226 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5227 TREE_SIDE_EFFECTS (t) = 1;
5229 ofs = (8 - size) % 4;
5232 t = build (PLUS_EXPR, TREE_TYPE (valist), t, build_int_2 (ofs, 0));
5233 TREE_SIDE_EFFECTS (t) = 1;
5236 t = build1 (NOP_EXPR, ptr, t);
5237 TREE_SIDE_EFFECTS (t) = 1;
5241 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
5246 /* This routine handles all the normal conditional branch sequences we
5247 might need to generate. It handles compare immediate vs compare
5248 register, nullification of delay slots, varying length branches,
5249 negated branches, and all combinations of the above. It returns the
5250 output appropriate to emit the branch corresponding to all given
5254 output_cbranch (operands, nullify, length, negated, insn)
5256 int nullify, length, negated;
5259 static char buf[100];
5262 /* A conditional branch to the following instruction (eg the delay slot) is
5263 asking for a disaster. This can happen when not optimizing.
5265 In such cases it is safe to emit nothing. */
5267 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5270 /* If this is a long branch with its delay slot unfilled, set `nullify'
5271 as it can nullify the delay slot and save a nop. */
5272 if (length == 8 && dbr_sequence_length () == 0)
5275 /* If this is a short forward conditional branch which did not get
5276 its delay slot filled, the delay slot can still be nullified. */
5277 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5278 nullify = forward_branch_p (insn);
5280 /* A forward branch over a single nullified insn can be done with a
5281 comclr instruction. This avoids a single cycle penalty due to
5282 mis-predicted branch if we fall through (branch not taken). */
5284 && next_real_insn (insn) != 0
5285 && get_attr_length (next_real_insn (insn)) == 4
5286 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5292 /* All short conditional branches except backwards with an unfilled
5296 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5298 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5299 if (GET_MODE (operands[1]) == DImode)
5302 strcat (buf, "%B3");
5304 strcat (buf, "%S3");
5306 strcat (buf, " %2,%r1,%%r0");
5308 strcat (buf, ",n %2,%r1,%0");
5310 strcat (buf, " %2,%r1,%0");
5313 /* All long conditionals. Note an short backward branch with an
5314 unfilled delay slot is treated just like a long backward branch
5315 with an unfilled delay slot. */
5317 /* Handle weird backwards branch with a filled delay slot
5318 with is nullified. */
5319 if (dbr_sequence_length () != 0
5320 && ! forward_branch_p (insn)
5323 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5324 if (GET_MODE (operands[1]) == DImode)
5327 strcat (buf, "%S3");
5329 strcat (buf, "%B3");
5330 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5332 /* Handle short backwards branch with an unfilled delay slot.
5333 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5334 taken and untaken branches. */
5335 else if (dbr_sequence_length () == 0
5336 && ! forward_branch_p (insn)
5337 && INSN_ADDRESSES_SET_P ()
5338 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5339 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5341 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5342 if (GET_MODE (operands[1]) == DImode)
5345 strcat (buf, "%B3 %2,%r1,%0%#");
5347 strcat (buf, "%S3 %2,%r1,%0%#");
5351 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5352 if (GET_MODE (operands[1]) == DImode)
5355 strcat (buf, "%S3");
5357 strcat (buf, "%B3");
5359 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5361 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5366 /* Very long branch. Right now we only handle these when not
5367 optimizing. See "jump" pattern in pa.md for details. */
5371 /* Create a reversed conditional branch which branches around
5372 the following insns. */
5374 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5376 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5377 if (GET_MODE (operands[1]) == DImode)
5381 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5384 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5386 output_asm_insn (buf, operands);
5388 /* Output an insn to save %r1. */
5389 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5391 /* Now output a very long branch to the original target. */
5392 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5394 /* Now restore the value of %r1 in the delay slot. We're not
5395 optimizing so we know nothing else can be in the delay slot. */
5396 return "ldw -16(%%r30),%%r1";
5399 /* Very long branch when generating PIC code. Right now we only
5400 handle these when not optimizing. See "jump" pattern in pa.md
5405 /* Create a reversed conditional branch which branches around
5406 the following insns. */
5408 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5410 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5411 if (GET_MODE (operands[1]) == DImode)
5414 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5416 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5418 output_asm_insn (buf, operands);
5420 /* Output an insn to save %r1. */
5421 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5423 /* Now output a very long PIC branch to the original target. */
5427 xoperands[0] = operands[0];
5428 xoperands[1] = operands[1];
5429 xoperands[2] = operands[2];
5430 xoperands[3] = operands[3];
5431 if (TARGET_SOM || ! TARGET_GAS)
5432 xoperands[4] = gen_label_rtx ();
5434 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5435 if (TARGET_SOM || ! TARGET_GAS)
5437 output_asm_insn ("addil L'%l0-%l4,%%r1", xoperands);
5438 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5439 CODE_LABEL_NUMBER (xoperands[4]));
5440 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1", xoperands);
5444 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
5445 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1",
5448 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5451 /* Now restore the value of %r1 in the delay slot. We're not
5452 optimizing so we know nothing else can be in the delay slot. */
5453 return "ldw -16(%%r30),%%r1";
5461 /* This routine handles all the branch-on-bit conditional branch sequences we
5462 might need to generate. It handles nullification of delay slots,
5463 varying length branches, negated branches and all combinations of the
5464 above. it returns the appropriate output template to emit the branch. */
5467 output_bb (operands, nullify, length, negated, insn, which)
5468 rtx *operands ATTRIBUTE_UNUSED;
5469 int nullify, length, negated;
5473 static char buf[100];
5476 /* A conditional branch to the following instruction (eg the delay slot) is
5477 asking for a disaster. I do not think this can happen as this pattern
5478 is only used when optimizing; jump optimization should eliminate the
5479 jump. But be prepared just in case. */
5481 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5484 /* If this is a long branch with its delay slot unfilled, set `nullify'
5485 as it can nullify the delay slot and save a nop. */
5486 if (length == 8 && dbr_sequence_length () == 0)
5489 /* If this is a short forward conditional branch which did not get
5490 its delay slot filled, the delay slot can still be nullified. */
5491 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5492 nullify = forward_branch_p (insn);
5494 /* A forward branch over a single nullified insn can be done with a
5495 extrs instruction. This avoids a single cycle penalty due to
5496 mis-predicted branch if we fall through (branch not taken). */
5499 && next_real_insn (insn) != 0
5500 && get_attr_length (next_real_insn (insn)) == 4
5501 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5508 /* All short conditional branches except backwards with an unfilled
5512 strcpy (buf, "{extrs,|extrw,s,}");
5514 strcpy (buf, "bb,");
5515 if (useskip && GET_MODE (operands[0]) == DImode)
5516 strcpy (buf, "extrd,s,*");
5517 else if (GET_MODE (operands[0]) == DImode)
5518 strcpy (buf, "bb,*");
5519 if ((which == 0 && negated)
5520 || (which == 1 && ! negated))
5525 strcat (buf, " %0,%1,1,%%r0");
5526 else if (nullify && negated)
5527 strcat (buf, ",n %0,%1,%3");
5528 else if (nullify && ! negated)
5529 strcat (buf, ",n %0,%1,%2");
5530 else if (! nullify && negated)
5531 strcat (buf, "%0,%1,%3");
5532 else if (! nullify && ! negated)
5533 strcat (buf, " %0,%1,%2");
5536 /* All long conditionals. Note an short backward branch with an
5537 unfilled delay slot is treated just like a long backward branch
5538 with an unfilled delay slot. */
5540 /* Handle weird backwards branch with a filled delay slot
5541 with is nullified. */
5542 if (dbr_sequence_length () != 0
5543 && ! forward_branch_p (insn)
5546 strcpy (buf, "bb,");
5547 if (GET_MODE (operands[0]) == DImode)
5549 if ((which == 0 && negated)
5550 || (which == 1 && ! negated))
5555 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5557 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5559 /* Handle short backwards branch with an unfilled delay slot.
5560 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5561 taken and untaken branches. */
5562 else if (dbr_sequence_length () == 0
5563 && ! forward_branch_p (insn)
5564 && INSN_ADDRESSES_SET_P ()
5565 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5566 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5568 strcpy (buf, "bb,");
5569 if (GET_MODE (operands[0]) == DImode)
5571 if ((which == 0 && negated)
5572 || (which == 1 && ! negated))
5577 strcat (buf, " %0,%1,%3%#");
5579 strcat (buf, " %0,%1,%2%#");
5583 strcpy (buf, "{extrs,|extrw,s,}");
5584 if (GET_MODE (operands[0]) == DImode)
5585 strcpy (buf, "extrd,s,*");
5586 if ((which == 0 && negated)
5587 || (which == 1 && ! negated))
5591 if (nullify && negated)
5592 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5593 else if (nullify && ! negated)
5594 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5596 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5598 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5608 /* This routine handles all the branch-on-variable-bit conditional branch
5609 sequences we might need to generate. It handles nullification of delay
5610 slots, varying length branches, negated branches and all combinations
5611 of the above. it returns the appropriate output template to emit the
5615 output_bvb (operands, nullify, length, negated, insn, which)
5616 rtx *operands ATTRIBUTE_UNUSED;
5617 int nullify, length, negated;
5621 static char buf[100];
5624 /* A conditional branch to the following instruction (eg the delay slot) is
5625 asking for a disaster. I do not think this can happen as this pattern
5626 is only used when optimizing; jump optimization should eliminate the
5627 jump. But be prepared just in case. */
5629 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5632 /* If this is a long branch with its delay slot unfilled, set `nullify'
5633 as it can nullify the delay slot and save a nop. */
5634 if (length == 8 && dbr_sequence_length () == 0)
5637 /* If this is a short forward conditional branch which did not get
5638 its delay slot filled, the delay slot can still be nullified. */
5639 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5640 nullify = forward_branch_p (insn);
5642 /* A forward branch over a single nullified insn can be done with a
5643 extrs instruction. This avoids a single cycle penalty due to
5644 mis-predicted branch if we fall through (branch not taken). */
5647 && next_real_insn (insn) != 0
5648 && get_attr_length (next_real_insn (insn)) == 4
5649 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5656 /* All short conditional branches except backwards with an unfilled
5660 strcpy (buf, "{vextrs,|extrw,s,}");
5662 strcpy (buf, "{bvb,|bb,}");
5663 if (useskip && GET_MODE (operands[0]) == DImode)
5664 strcpy (buf, "extrd,s,*}");
5665 else if (GET_MODE (operands[0]) == DImode)
5666 strcpy (buf, "bb,*");
5667 if ((which == 0 && negated)
5668 || (which == 1 && ! negated))
5673 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5674 else if (nullify && negated)
5675 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5676 else if (nullify && ! negated)
5677 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5678 else if (! nullify && negated)
5679 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5680 else if (! nullify && ! negated)
5681 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5684 /* All long conditionals. Note an short backward branch with an
5685 unfilled delay slot is treated just like a long backward branch
5686 with an unfilled delay slot. */
5688 /* Handle weird backwards branch with a filled delay slot
5689 with is nullified. */
5690 if (dbr_sequence_length () != 0
5691 && ! forward_branch_p (insn)
5694 strcpy (buf, "{bvb,|bb,}");
5695 if (GET_MODE (operands[0]) == DImode)
5697 if ((which == 0 && negated)
5698 || (which == 1 && ! negated))
5703 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5705 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5707 /* Handle short backwards branch with an unfilled delay slot.
5708 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5709 taken and untaken branches. */
5710 else if (dbr_sequence_length () == 0
5711 && ! forward_branch_p (insn)
5712 && INSN_ADDRESSES_SET_P ()
5713 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5714 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5716 strcpy (buf, "{bvb,|bb,}");
5717 if (GET_MODE (operands[0]) == DImode)
5719 if ((which == 0 && negated)
5720 || (which == 1 && ! negated))
5725 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5727 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5731 strcpy (buf, "{vextrs,|extrw,s,}");
5732 if (GET_MODE (operands[0]) == DImode)
5733 strcpy (buf, "extrd,s,*");
5734 if ((which == 0 && negated)
5735 || (which == 1 && ! negated))
5739 if (nullify && negated)
5740 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5741 else if (nullify && ! negated)
5742 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5744 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5746 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5756 /* Return the output template for emitting a dbra type insn.
5758 Note it may perform some output operations on its own before
5759 returning the final output string. */
5761 output_dbra (operands, insn, which_alternative)
5764 int which_alternative;
5767 /* A conditional branch to the following instruction (eg the delay slot) is
5768 asking for a disaster. Be prepared! */
5770 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5772 if (which_alternative == 0)
5773 return "ldo %1(%0),%0";
5774 else if (which_alternative == 1)
5776 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5777 output_asm_insn ("ldw -16(%%r30),%4", operands);
5778 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5779 return "{fldws|fldw} -16(%%r30),%0";
5783 output_asm_insn ("ldw %0,%4", operands);
5784 return "ldo %1(%4),%4\n\tstw %4,%0";
5788 if (which_alternative == 0)
5790 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5791 int length = get_attr_length (insn);
5793 /* If this is a long branch with its delay slot unfilled, set `nullify'
5794 as it can nullify the delay slot and save a nop. */
5795 if (length == 8 && dbr_sequence_length () == 0)
5798 /* If this is a short forward conditional branch which did not get
5799 its delay slot filled, the delay slot can still be nullified. */
5800 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5801 nullify = forward_branch_p (insn);
5803 /* Handle short versions first. */
5804 if (length == 4 && nullify)
5805 return "addib,%C2,n %1,%0,%3";
5806 else if (length == 4 && ! nullify)
5807 return "addib,%C2 %1,%0,%3";
5808 else if (length == 8)
5810 /* Handle weird backwards branch with a fulled delay slot
5811 which is nullified. */
5812 if (dbr_sequence_length () != 0
5813 && ! forward_branch_p (insn)
5815 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5816 /* Handle short backwards branch with an unfilled delay slot.
5817 Using a addb;nop rather than addi;bl saves 1 cycle for both
5818 taken and untaken branches. */
5819 else if (dbr_sequence_length () == 0
5820 && ! forward_branch_p (insn)
5821 && INSN_ADDRESSES_SET_P ()
5822 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5823 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5824 return "addib,%C2 %1,%0,%3%#";
5826 /* Handle normal cases. */
5828 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5830 return "addi,%N2 %1,%0,%0\n\tb %3";
5835 /* Deal with gross reload from FP register case. */
5836 else if (which_alternative == 1)
5838 /* Move loop counter from FP register to MEM then into a GR,
5839 increment the GR, store the GR into MEM, and finally reload
5840 the FP register from MEM from within the branch's delay slot. */
5841 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5843 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5844 if (get_attr_length (insn) == 24)
5845 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5847 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5849 /* Deal with gross reload from memory case. */
5852 /* Reload loop counter from memory, the store back to memory
5853 happens in the branch's delay slot. */
5854 output_asm_insn ("ldw %0,%4", operands);
5855 if (get_attr_length (insn) == 12)
5856 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5858 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5862 /* Return the output template for emitting a dbra type insn.
5864 Note it may perform some output operations on its own before
5865 returning the final output string. */
5867 output_movb (operands, insn, which_alternative, reverse_comparison)
5870 int which_alternative;
5871 int reverse_comparison;
5874 /* A conditional branch to the following instruction (eg the delay slot) is
5875 asking for a disaster. Be prepared! */
5877 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5879 if (which_alternative == 0)
5880 return "copy %1,%0";
5881 else if (which_alternative == 1)
5883 output_asm_insn ("stw %1,-16(%%r30)", operands);
5884 return "{fldws|fldw} -16(%%r30),%0";
5886 else if (which_alternative == 2)
5892 /* Support the second variant. */
5893 if (reverse_comparison)
5894 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5896 if (which_alternative == 0)
5898 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5899 int length = get_attr_length (insn);
5901 /* If this is a long branch with its delay slot unfilled, set `nullify'
5902 as it can nullify the delay slot and save a nop. */
5903 if (length == 8 && dbr_sequence_length () == 0)
5906 /* If this is a short forward conditional branch which did not get
5907 its delay slot filled, the delay slot can still be nullified. */
5908 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5909 nullify = forward_branch_p (insn);
5911 /* Handle short versions first. */
5912 if (length == 4 && nullify)
5913 return "movb,%C2,n %1,%0,%3";
5914 else if (length == 4 && ! nullify)
5915 return "movb,%C2 %1,%0,%3";
5916 else if (length == 8)
5918 /* Handle weird backwards branch with a filled delay slot
5919 which is nullified. */
5920 if (dbr_sequence_length () != 0
5921 && ! forward_branch_p (insn)
5923 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5925 /* Handle short backwards branch with an unfilled delay slot.
5926 Using a movb;nop rather than or;bl saves 1 cycle for both
5927 taken and untaken branches. */
5928 else if (dbr_sequence_length () == 0
5929 && ! forward_branch_p (insn)
5930 && INSN_ADDRESSES_SET_P ()
5931 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5932 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5933 return "movb,%C2 %1,%0,%3%#";
5934 /* Handle normal cases. */
5936 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5938 return "or,%N2 %1,%%r0,%0\n\tb %3";
5943 /* Deal with gross reload from FP register case. */
5944 else if (which_alternative == 1)
5946 /* Move loop counter from FP register to MEM then into a GR,
5947 increment the GR, store the GR into MEM, and finally reload
5948 the FP register from MEM from within the branch's delay slot. */
5949 output_asm_insn ("stw %1,-16(%%r30)", operands);
5950 if (get_attr_length (insn) == 12)
5951 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
5953 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5955 /* Deal with gross reload from memory case. */
5956 else if (which_alternative == 2)
5958 /* Reload loop counter from memory, the store back to memory
5959 happens in the branch's delay slot. */
5960 if (get_attr_length (insn) == 8)
5961 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
5963 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5965 /* Handle SAR as a destination. */
5968 if (get_attr_length (insn) == 8)
5969 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
5971 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5976 /* INSN is a millicode call. It may have an unconditional jump in its delay
5979 CALL_DEST is the routine we are calling. */
5982 output_millicode_call (insn, call_dest)
5986 int attr_length = get_attr_length (insn);
5987 int seq_length = dbr_sequence_length ();
5992 xoperands[3] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
5994 /* Handle common case -- empty delay slot or no jump in the delay slot,
5995 and we're sure that the branch will reach the beginning of the $CODE$
5996 subspace. The within reach form of the $$sh_func_adrs call has
5997 a length of 28 and attribute type of multi. This length is the
5998 same as the maximum length of an out of reach PIC call to $$div. */
5999 if ((seq_length == 0
6000 && (attr_length == 8
6001 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6003 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6004 && attr_length == 4))
6006 xoperands[0] = call_dest;
6007 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
6011 /* This call may not reach the beginning of the $CODE$ subspace. */
6012 if (attr_length > 8)
6014 int delay_insn_deleted = 0;
6016 /* We need to emit an inline long-call branch. */
6018 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6020 /* A non-jump insn in the delay slot. By definition we can
6021 emit this insn before the call. */
6022 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6024 /* Now delete the delay insn. */
6025 PUT_CODE (NEXT_INSN (insn), NOTE);
6026 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6027 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6028 delay_insn_deleted = 1;
6031 /* PIC long millicode call sequence. */
6034 xoperands[0] = call_dest;
6035 if (TARGET_SOM || ! TARGET_GAS)
6036 xoperands[1] = gen_label_rtx ();
6038 /* Get our address + 8 into %r1. */
6039 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6041 if (TARGET_SOM || ! TARGET_GAS)
6043 /* Add %r1 to the offset of our target from the next insn. */
6044 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
6045 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6046 CODE_LABEL_NUMBER (xoperands[1]));
6047 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
6051 output_asm_insn ("addil L%%%0-$PIC_pcrel$0+4,%%r1", xoperands);
6052 output_asm_insn ("ldo R%%%0-$PIC_pcrel$0+8(%%r1),%%r1",
6056 /* Get the return address into %r31. */
6057 output_asm_insn ("blr 0,%3", xoperands);
6059 /* Branch to our target which is in %r1. */
6060 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
6062 /* Empty delay slot. Note this insn gets fetched twice and
6063 executed once. To be safe we use a nop. */
6064 output_asm_insn ("nop", xoperands);
6066 /* Pure portable runtime doesn't allow be/ble; we also don't have
6067 PIC support in the assembler/linker, so this sequence is needed. */
6068 else if (TARGET_PORTABLE_RUNTIME)
6070 xoperands[0] = call_dest;
6071 /* Get the address of our target into %r29. */
6072 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
6073 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
6075 /* Get our return address into %r31. */
6076 output_asm_insn ("blr %%r0,%3", xoperands);
6078 /* Jump to our target address in %r29. */
6079 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
6081 /* Empty delay slot. Note this insn gets fetched twice and
6082 executed once. To be safe we use a nop. */
6083 output_asm_insn ("nop", xoperands);
6085 /* If we're allowed to use be/ble instructions, then this is the
6086 best sequence to use for a long millicode call. */
6089 xoperands[0] = call_dest;
6090 output_asm_insn ("ldil L%%%0,%3", xoperands);
6091 output_asm_insn ("{ble|be,l} R%%%0(%%sr4,%3)", xoperands);
6092 output_asm_insn ("nop", xoperands);
6095 /* If we had a jump in the call's delay slot, output it now. */
6096 if (seq_length != 0 && !delay_insn_deleted)
6098 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6099 output_asm_insn ("b,n %0", xoperands);
6101 /* Now delete the delay insn. */
6102 PUT_CODE (NEXT_INSN (insn), NOTE);
6103 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6104 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6109 /* This call has an unconditional jump in its delay slot and the
6110 call is known to reach its target or the beginning of the current
6113 /* Use the containing sequence insn's address. */
6114 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6116 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6117 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6119 /* If the branch was too far away, emit a normal call followed
6120 by a nop, followed by the unconditional branch.
6122 If the branch is close, then adjust %r2 from within the
6123 call's delay slot. */
6125 xoperands[0] = call_dest;
6126 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6127 if (! VAL_14_BITS_P (distance))
6128 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
6131 xoperands[2] = gen_label_rtx ();
6132 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
6134 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6135 CODE_LABEL_NUMBER (xoperands[2]));
6138 /* Delete the jump. */
6139 PUT_CODE (NEXT_INSN (insn), NOTE);
6140 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6141 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6145 extern struct obstack permanent_obstack;
6147 /* INSN is either a function call. It may have an unconditional jump
6150 CALL_DEST is the routine we are calling. */
6153 output_call (insn, call_dest, sibcall)
6158 int attr_length = get_attr_length (insn);
6159 int seq_length = dbr_sequence_length ();
6164 /* Handle common case -- empty delay slot or no jump in the delay slot,
6165 and we're sure that the branch will reach the beginning of the $CODE$
6167 if ((seq_length == 0 && attr_length == 12)
6169 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6170 && attr_length == 8))
6172 xoperands[0] = call_dest;
6173 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
6174 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
6178 /* This call may not reach the beginning of the $CODE$ subspace. */
6179 if (attr_length > 12)
6181 int delay_insn_deleted = 0;
6185 /* We need to emit an inline long-call branch. Furthermore,
6186 because we're changing a named function call into an indirect
6187 function call well after the parameters have been set up, we
6188 need to make sure any FP args appear in both the integer
6189 and FP registers. Also, we need move any delay slot insn
6190 out of the delay slot. And finally, we can't rely on the linker
6191 being able to fix the call to $$dyncall! -- Yuk!. */
6193 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6195 /* A non-jump insn in the delay slot. By definition we can
6196 emit this insn before the call (and in fact before argument
6198 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6200 /* Now delete the delay insn. */
6201 PUT_CODE (NEXT_INSN (insn), NOTE);
6202 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6203 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6204 delay_insn_deleted = 1;
6207 /* Now copy any FP arguments into integer registers. */
6208 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6210 int arg_mode, regno;
6211 rtx use = XEXP (link, 0);
6212 if (! (GET_CODE (use) == USE
6213 && GET_CODE (XEXP (use, 0)) == REG
6214 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6217 arg_mode = GET_MODE (XEXP (use, 0));
6218 regno = REGNO (XEXP (use, 0));
6219 /* Is it a floating point register? */
6220 if (regno >= 32 && regno <= 39)
6222 /* Copy from the FP register into an integer register
6224 if (arg_mode == SFmode)
6226 xoperands[0] = XEXP (use, 0);
6227 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6228 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
6230 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6234 xoperands[0] = XEXP (use, 0);
6235 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6236 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
6238 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6239 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6244 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
6245 we don't have any direct calls in that case. */
6248 const char *name = XSTR (call_dest, 0);
6250 /* See if we have already put this function on the list
6251 of deferred plabels. This list is generally small,
6252 so a liner search is not too ugly. If it proves too
6253 slow replace it with something faster. */
6254 for (i = 0; i < n_deferred_plabels; i++)
6255 if (strcmp (name, deferred_plabels[i].name) == 0)
6258 /* If the deferred plabel list is empty, or this entry was
6259 not found on the list, create a new entry on the list. */
6260 if (deferred_plabels == NULL || i == n_deferred_plabels)
6262 const char *real_name;
6264 if (deferred_plabels == 0)
6265 deferred_plabels = (struct deferred_plabel *)
6266 xmalloc (1 * sizeof (struct deferred_plabel));
6268 deferred_plabels = (struct deferred_plabel *)
6269 xrealloc (deferred_plabels,
6270 ((n_deferred_plabels + 1)
6271 * sizeof (struct deferred_plabel)));
6273 i = n_deferred_plabels++;
6274 deferred_plabels[i].internal_label = gen_label_rtx ();
6275 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
6277 strcpy (deferred_plabels[i].name, name);
6279 /* Gross. We have just implicitly taken the address of this
6280 function, mark it as such. */
6281 STRIP_NAME_ENCODING (real_name, name);
6282 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
6285 /* We have to load the address of the function using a procedure
6286 label (plabel). Inline plabels can lose for PIC and other
6287 cases, so avoid them by creating a 32bit plabel in the data
6291 xoperands[0] = deferred_plabels[i].internal_label;
6292 if (TARGET_SOM || ! TARGET_GAS)
6293 xoperands[1] = gen_label_rtx ();
6295 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
6296 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
6297 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
6299 /* Get our address + 8 into %r1. */
6300 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6302 if (TARGET_SOM || ! TARGET_GAS)
6304 /* Add %r1 to the offset of dyncall from the next insn. */
6305 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
6306 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6307 CODE_LABEL_NUMBER (xoperands[1]));
6308 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
6312 output_asm_insn ("addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1",
6314 output_asm_insn ("ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
6318 /* Get the return address into %r31. */
6319 output_asm_insn ("blr %%r0,%%r31", xoperands);
6321 /* Branch to our target which is in %r1. */
6322 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6326 /* This call never returns, so we do not need to fix the
6328 output_asm_insn ("nop", xoperands);
6332 /* Copy the return address into %r2 also. */
6333 output_asm_insn ("copy %%r31,%%r2", xoperands);
6338 xoperands[0] = deferred_plabels[i].internal_label;
6340 /* Get the address of our target into %r22. */
6341 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
6342 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
6344 /* Get the high part of the address of $dyncall into %r2, then
6345 add in the low part in the branch instruction. */
6346 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
6347 output_asm_insn ("{ble|be,l} R%%$$dyncall(%%sr4,%%r2)",
6352 /* This call never returns, so we do not need to fix the
6354 output_asm_insn ("nop", xoperands);
6358 /* Copy the return address into %r2 also. */
6359 output_asm_insn ("copy %%r31,%%r2", xoperands);
6364 /* If we had a jump in the call's delay slot, output it now. */
6365 if (seq_length != 0 && !delay_insn_deleted)
6367 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6368 output_asm_insn ("b,n %0", xoperands);
6370 /* Now delete the delay insn. */
6371 PUT_CODE (NEXT_INSN (insn), NOTE);
6372 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6373 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6378 /* This call has an unconditional jump in its delay slot and the
6379 call is known to reach its target or the beginning of the current
6382 /* Use the containing sequence insn's address. */
6383 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6385 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6386 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6388 /* If the branch is too far away, emit a normal call followed
6389 by a nop, followed by the unconditional branch. If the branch
6390 is close, then adjust %r2 in the call's delay slot. */
6392 xoperands[0] = call_dest;
6393 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6394 if (! VAL_14_BITS_P (distance))
6395 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
6398 xoperands[3] = gen_label_rtx ();
6399 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6401 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6402 CODE_LABEL_NUMBER (xoperands[3]));
6405 /* Delete the jump. */
6406 PUT_CODE (NEXT_INSN (insn), NOTE);
6407 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6408 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6412 /* In HPUX 8.0's shared library scheme, special relocations are needed
6413 for function labels if they might be passed to a function
6414 in a shared library (because shared libraries don't live in code
6415 space), and special magic is needed to construct their address. */
6418 hppa_encode_label (sym)
6421 const char *str = XSTR (sym, 0);
6422 int len = strlen (str) + 1;
6425 p = newstr = alloca (len + 1);
6434 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6438 function_label_operand (op, mode)
6440 enum machine_mode mode ATTRIBUTE_UNUSED;
6442 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6445 /* Returns 1 if OP is a function label involved in a simple addition
6446 with a constant. Used to keep certain patterns from matching
6447 during instruction combination. */
6449 is_function_label_plus_const (op)
6452 /* Strip off any CONST. */
6453 if (GET_CODE (op) == CONST)
6456 return (GET_CODE (op) == PLUS
6457 && function_label_operand (XEXP (op, 0), Pmode)
6458 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6461 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6462 use in fmpyadd instructions. */
6464 fmpyaddoperands (operands)
6467 enum machine_mode mode = GET_MODE (operands[0]);
6469 /* Must be a floating point mode. */
6470 if (mode != SFmode && mode != DFmode)
6473 /* All modes must be the same. */
6474 if (! (mode == GET_MODE (operands[1])
6475 && mode == GET_MODE (operands[2])
6476 && mode == GET_MODE (operands[3])
6477 && mode == GET_MODE (operands[4])
6478 && mode == GET_MODE (operands[5])))
6481 /* All operands must be registers. */
6482 if (! (GET_CODE (operands[1]) == REG
6483 && GET_CODE (operands[2]) == REG
6484 && GET_CODE (operands[3]) == REG
6485 && GET_CODE (operands[4]) == REG
6486 && GET_CODE (operands[5]) == REG))
6489 /* Only 2 real operands to the addition. One of the input operands must
6490 be the same as the output operand. */
6491 if (! rtx_equal_p (operands[3], operands[4])
6492 && ! rtx_equal_p (operands[3], operands[5]))
6495 /* Inout operand of add can not conflict with any operands from multiply. */
6496 if (rtx_equal_p (operands[3], operands[0])
6497 || rtx_equal_p (operands[3], operands[1])
6498 || rtx_equal_p (operands[3], operands[2]))
6501 /* multiply can not feed into addition operands. */
6502 if (rtx_equal_p (operands[4], operands[0])
6503 || rtx_equal_p (operands[5], operands[0]))
6506 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6508 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6509 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6510 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6511 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6512 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6513 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6516 /* Passed. Operands are suitable for fmpyadd. */
6520 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6521 use in fmpysub instructions. */
6523 fmpysuboperands (operands)
6526 enum machine_mode mode = GET_MODE (operands[0]);
6528 /* Must be a floating point mode. */
6529 if (mode != SFmode && mode != DFmode)
6532 /* All modes must be the same. */
6533 if (! (mode == GET_MODE (operands[1])
6534 && mode == GET_MODE (operands[2])
6535 && mode == GET_MODE (operands[3])
6536 && mode == GET_MODE (operands[4])
6537 && mode == GET_MODE (operands[5])))
6540 /* All operands must be registers. */
6541 if (! (GET_CODE (operands[1]) == REG
6542 && GET_CODE (operands[2]) == REG
6543 && GET_CODE (operands[3]) == REG
6544 && GET_CODE (operands[4]) == REG
6545 && GET_CODE (operands[5]) == REG))
6548 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6549 operation, so operands[4] must be the same as operand[3]. */
6550 if (! rtx_equal_p (operands[3], operands[4]))
6553 /* multiply can not feed into subtraction. */
6554 if (rtx_equal_p (operands[5], operands[0]))
6557 /* Inout operand of sub can not conflict with any operands from multiply. */
6558 if (rtx_equal_p (operands[3], operands[0])
6559 || rtx_equal_p (operands[3], operands[1])
6560 || rtx_equal_p (operands[3], operands[2]))
6563 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6565 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6566 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6567 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6568 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6569 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6570 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6573 /* Passed. Operands are suitable for fmpysub. */
6578 plus_xor_ior_operator (op, mode)
6580 enum machine_mode mode ATTRIBUTE_UNUSED;
6582 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6583 || GET_CODE (op) == IOR);
6586 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6587 constants for shadd instructions. */
6589 shadd_constant_p (val)
6592 if (val == 2 || val == 4 || val == 8)
6598 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6599 the valid constant for shadd instructions. */
6601 shadd_operand (op, mode)
6603 enum machine_mode mode ATTRIBUTE_UNUSED;
6605 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6608 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6611 basereg_operand (op, mode)
6613 enum machine_mode mode;
6615 /* cse will create some unscaled indexed addresses, however; it
6616 generally isn't a win on the PA, so avoid creating unscaled
6617 indexed addresses until after cse is finished. */
6618 if (!cse_not_expected)
6621 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6622 we don't have to worry about the braindamaged implicit space
6623 register selection from the basereg. */
6624 if (TARGET_NO_SPACE_REGS)
6625 return (GET_CODE (op) == REG);
6627 /* While it's always safe to index off the frame pointer, it's not
6628 always profitable, particularly when the frame pointer is being
6630 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6633 return (GET_CODE (op) == REG
6635 && register_operand (op, mode));
6638 /* Return 1 if this operand is anything other than a hard register. */
6641 non_hard_reg_operand (op, mode)
6643 enum machine_mode mode ATTRIBUTE_UNUSED;
6645 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6648 /* Return 1 if INSN branches forward. Should be using insn_addresses
6649 to avoid walking through all the insns... */
6651 forward_branch_p (insn)
6654 rtx label = JUMP_LABEL (insn);
6661 insn = NEXT_INSN (insn);
6664 return (insn == label);
6667 /* Return 1 if OP is an equality comparison, else return 0. */
6669 eq_neq_comparison_operator (op, mode)
6671 enum machine_mode mode ATTRIBUTE_UNUSED;
6673 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6676 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6678 movb_comparison_operator (op, mode)
6680 enum machine_mode mode ATTRIBUTE_UNUSED;
6682 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6683 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6686 /* Return 1 if INSN is in the delay slot of a call instruction. */
6688 jump_in_call_delay (insn)
6692 if (GET_CODE (insn) != JUMP_INSN)
6695 if (PREV_INSN (insn)
6696 && PREV_INSN (PREV_INSN (insn))
6697 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6699 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6701 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6702 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6709 /* Output an unconditional move and branch insn. */
6712 output_parallel_movb (operands, length)
6716 /* These are the cases in which we win. */
6718 return "mov%I1b,tr %1,%0,%2";
6720 /* None of these cases wins, but they don't lose either. */
6721 if (dbr_sequence_length () == 0)
6723 /* Nothing in the delay slot, fake it by putting the combined
6724 insn (the copy or add) in the delay slot of a bl. */
6725 if (GET_CODE (operands[1]) == CONST_INT)
6726 return "b %2\n\tldi %1,%0";
6728 return "b %2\n\tcopy %1,%0";
6732 /* Something in the delay slot, but we've got a long branch. */
6733 if (GET_CODE (operands[1]) == CONST_INT)
6734 return "ldi %1,%0\n\tb %2";
6736 return "copy %1,%0\n\tb %2";
6740 /* Output an unconditional add and branch insn. */
6743 output_parallel_addb (operands, length)
6747 /* To make life easy we want operand0 to be the shared input/output
6748 operand and operand1 to be the readonly operand. */
6749 if (operands[0] == operands[1])
6750 operands[1] = operands[2];
6752 /* These are the cases in which we win. */
6754 return "add%I1b,tr %1,%0,%3";
6756 /* None of these cases win, but they don't lose either. */
6757 if (dbr_sequence_length () == 0)
6759 /* Nothing in the delay slot, fake it by putting the combined
6760 insn (the copy or add) in the delay slot of a bl. */
6761 return "b %3\n\tadd%I1 %1,%0,%0";
6765 /* Something in the delay slot, but we've got a long branch. */
6766 return "add%I1 %1,%0,%0\n\tb %3";
6770 /* Return nonzero if INSN (a jump insn) immediately follows a call
6771 to a named function. This is used to avoid filling the delay slot
6772 of the jump since it can usually be eliminated by modifying RP in
6773 the delay slot of the call. */
6776 following_call (insn)
6779 /* We do not place jumps into call delay slots when optimizing for the
6780 PA8000 processor or when generating dwarf2 call frame information. */
6781 if (pa_cpu >= PROCESSOR_8000
6782 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
6783 || flag_unwind_tables)
6786 /* Find the previous real insn, skipping NOTEs. */
6787 insn = PREV_INSN (insn);
6788 while (insn && GET_CODE (insn) == NOTE)
6789 insn = PREV_INSN (insn);
6791 /* Check for CALL_INSNs and millicode calls. */
6793 && ((GET_CODE (insn) == CALL_INSN
6794 && get_attr_type (insn) != TYPE_DYNCALL)
6795 || (GET_CODE (insn) == INSN
6796 && GET_CODE (PATTERN (insn)) != SEQUENCE
6797 && GET_CODE (PATTERN (insn)) != USE
6798 && GET_CODE (PATTERN (insn)) != CLOBBER
6799 && get_attr_type (insn) == TYPE_MILLI)))
6805 /* We use this hook to perform a PA specific optimization which is difficult
6806 to do in earlier passes.
6808 We want the delay slots of branches within jump tables to be filled.
6809 None of the compiler passes at the moment even has the notion that a
6810 PA jump table doesn't contain addresses, but instead contains actual
6813 Because we actually jump into the table, the addresses of each entry
6814 must stay constant in relation to the beginning of the table (which
6815 itself must stay constant relative to the instruction to jump into
6816 it). I don't believe we can guarantee earlier passes of the compiler
6817 will adhere to those rules.
6819 So, late in the compilation process we find all the jump tables, and
6820 expand them into real code -- eg each entry in the jump table vector
6821 will get an appropriate label followed by a jump to the final target.
6823 Reorg and the final jump pass can then optimize these branches and
6824 fill their delay slots. We end up with smaller, more efficient code.
6826 The jump instructions within the table are special; we must be able
6827 to identify them during assembly output (if the jumps don't get filled
6828 we need to emit a nop rather than nullifying the delay slot)). We
6829 identify jumps in switch tables by marking the SET with DImode.
6831 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6832 insns. This serves two purposes, first it prevents jump.c from
6833 noticing that the last N entries in the table jump to the instruction
6834 immediately after the table and deleting the jumps. Second, those
6835 insns mark where we should emit .begin_brtab and .end_brtab directives
6836 when using GAS (allows for better link time optimizations). */
6844 remove_useless_addtr_insns (insns, 1);
6846 if (pa_cpu < PROCESSOR_8000)
6847 pa_combine_instructions (get_insns ());
6850 /* This is fairly cheap, so always run it if optimizing. */
6851 if (optimize > 0 && !TARGET_BIG_SWITCH)
6853 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6854 insns = get_insns ();
6855 for (insn = insns; insn; insn = NEXT_INSN (insn))
6857 rtx pattern, tmp, location;
6858 unsigned int length, i;
6860 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6861 if (GET_CODE (insn) != JUMP_INSN
6862 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6863 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6866 /* Emit marker for the beginning of the branch table. */
6867 emit_insn_before (gen_begin_brtab (), insn);
6869 pattern = PATTERN (insn);
6870 location = PREV_INSN (insn);
6871 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6873 for (i = 0; i < length; i++)
6875 /* Emit a label before each jump to keep jump.c from
6876 removing this code. */
6877 tmp = gen_label_rtx ();
6878 LABEL_NUSES (tmp) = 1;
6879 emit_label_after (tmp, location);
6880 location = NEXT_INSN (location);
6882 if (GET_CODE (pattern) == ADDR_VEC)
6884 /* Emit the jump itself. */
6885 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
6886 tmp = emit_jump_insn_after (tmp, location);
6887 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
6888 /* It is easy to rely on the branch table markers
6889 during assembly output to trigger the correct code
6890 for a switch table jump with an unfilled delay slot,
6892 However, that requires state and assumes that we look
6895 We can't make such assumptions when computing the length
6896 of instructions. Ugh. We could walk the insn chain to
6897 determine if this instruction is in a branch table, but
6898 that can get rather expensive, particularly during the
6899 branch shortening phase of the compiler.
6901 So instead we mark this jump as being special. This is
6902 far from ideal and knows that no code after this will
6903 muck around with the mode of the JUMP_INSN itself. */
6904 PUT_MODE (tmp, SImode);
6905 LABEL_NUSES (JUMP_LABEL (tmp))++;
6906 location = NEXT_INSN (location);
6910 /* Emit the jump itself. */
6911 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
6912 tmp = emit_jump_insn_after (tmp, location);
6913 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
6914 /* It is easy to rely on the branch table markers
6915 during assembly output to trigger the correct code
6916 for a switch table jump with an unfilled delay slot,
6918 However, that requires state and assumes that we look
6921 We can't make such assumptions when computing the length
6922 of instructions. Ugh. We could walk the insn chain to
6923 determine if this instruction is in a branch table, but
6924 that can get rather expensive, particularly during the
6925 branch shortening phase of the compiler.
6927 So instead we mark this jump as being special. This is
6928 far from ideal and knows that no code after this will
6929 muck around with the mode of the JUMP_INSN itself. */
6930 PUT_MODE (tmp, SImode);
6931 LABEL_NUSES (JUMP_LABEL (tmp))++;
6932 location = NEXT_INSN (location);
6935 /* Emit a BARRIER after the jump. */
6936 emit_barrier_after (location);
6937 location = NEXT_INSN (location);
6940 /* Emit marker for the end of the branch table. */
6941 emit_insn_before (gen_end_brtab (), location);
6942 location = NEXT_INSN (location);
6943 emit_barrier_after (location);
6945 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6951 /* Sill need an end_brtab insn. */
6952 insns = get_insns ();
6953 for (insn = insns; insn; insn = NEXT_INSN (insn))
6955 /* Find an ADDR_VEC insn. */
6956 if (GET_CODE (insn) != JUMP_INSN
6957 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6958 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6961 /* Now generate markers for the beginning and end of the
6963 emit_insn_before (gen_begin_brtab (), insn);
6964 emit_insn_after (gen_end_brtab (), insn);
6969 /* The PA has a number of odd instructions which can perform multiple
6970 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6971 it may be profitable to combine two instructions into one instruction
6972 with two outputs. It's not profitable PA2.0 machines because the
6973 two outputs would take two slots in the reorder buffers.
6975 This routine finds instructions which can be combined and combines
6976 them. We only support some of the potential combinations, and we
6977 only try common ways to find suitable instructions.
6979 * addb can add two registers or a register and a small integer
6980 and jump to a nearby (+-8k) location. Normally the jump to the
6981 nearby location is conditional on the result of the add, but by
6982 using the "true" condition we can make the jump unconditional.
6983 Thus addb can perform two independent operations in one insn.
6985 * movb is similar to addb in that it can perform a reg->reg
6986 or small immediate->reg copy and jump to a nearby (+-8k location).
6988 * fmpyadd and fmpysub can perform a FP multiply and either an
6989 FP add or FP sub if the operands of the multiply and add/sub are
6990 independent (there are other minor restrictions). Note both
6991 the fmpy and fadd/fsub can in theory move to better spots according
6992 to data dependencies, but for now we require the fmpy stay at a
6995 * Many of the memory operations can perform pre & post updates
6996 of index registers. GCC's pre/post increment/decrement addressing
6997 is far too simple to take advantage of all the possibilities. This
6998 pass may not be suitable since those insns may not be independent.
7000 * comclr can compare two ints or an int and a register, nullify
7001 the following instruction and zero some other register. This
7002 is more difficult to use as it's harder to find an insn which
7003 will generate a comclr than finding something like an unconditional
7004 branch. (conditional moves & long branches create comclr insns).
7006 * Most arithmetic operations can conditionally skip the next
7007 instruction. They can be viewed as "perform this operation
7008 and conditionally jump to this nearby location" (where nearby
7009 is an insns away). These are difficult to use due to the
7010 branch length restrictions. */
7013 pa_combine_instructions (insns)
7014 rtx insns ATTRIBUTE_UNUSED;
7018 /* This can get expensive since the basic algorithm is on the
7019 order of O(n^2) (or worse). Only do it for -O2 or higher
7020 levels of optimization. */
7024 /* Walk down the list of insns looking for "anchor" insns which
7025 may be combined with "floating" insns. As the name implies,
7026 "anchor" instructions don't move, while "floating" insns may
7028 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
7029 new = make_insn_raw (new);
7031 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
7033 enum attr_pa_combine_type anchor_attr;
7034 enum attr_pa_combine_type floater_attr;
7036 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
7037 Also ignore any special USE insns. */
7038 if ((GET_CODE (anchor) != INSN
7039 && GET_CODE (anchor) != JUMP_INSN
7040 && GET_CODE (anchor) != CALL_INSN)
7041 || GET_CODE (PATTERN (anchor)) == USE
7042 || GET_CODE (PATTERN (anchor)) == CLOBBER
7043 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
7044 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
7047 anchor_attr = get_attr_pa_combine_type (anchor);
7048 /* See if anchor is an insn suitable for combination. */
7049 if (anchor_attr == PA_COMBINE_TYPE_FMPY
7050 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
7051 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7052 && ! forward_branch_p (anchor)))
7056 for (floater = PREV_INSN (anchor);
7058 floater = PREV_INSN (floater))
7060 if (GET_CODE (floater) == NOTE
7061 || (GET_CODE (floater) == INSN
7062 && (GET_CODE (PATTERN (floater)) == USE
7063 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7066 /* Anything except a regular INSN will stop our search. */
7067 if (GET_CODE (floater) != INSN
7068 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7069 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7075 /* See if FLOATER is suitable for combination with the
7077 floater_attr = get_attr_pa_combine_type (floater);
7078 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7079 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7080 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7081 && floater_attr == PA_COMBINE_TYPE_FMPY))
7083 /* If ANCHOR and FLOATER can be combined, then we're
7084 done with this pass. */
7085 if (pa_can_combine_p (new, anchor, floater, 0,
7086 SET_DEST (PATTERN (floater)),
7087 XEXP (SET_SRC (PATTERN (floater)), 0),
7088 XEXP (SET_SRC (PATTERN (floater)), 1)))
7092 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7093 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
7095 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
7097 if (pa_can_combine_p (new, anchor, floater, 0,
7098 SET_DEST (PATTERN (floater)),
7099 XEXP (SET_SRC (PATTERN (floater)), 0),
7100 XEXP (SET_SRC (PATTERN (floater)), 1)))
7105 if (pa_can_combine_p (new, anchor, floater, 0,
7106 SET_DEST (PATTERN (floater)),
7107 SET_SRC (PATTERN (floater)),
7108 SET_SRC (PATTERN (floater))))
7114 /* If we didn't find anything on the backwards scan try forwards. */
7116 && (anchor_attr == PA_COMBINE_TYPE_FMPY
7117 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
7119 for (floater = anchor; floater; floater = NEXT_INSN (floater))
7121 if (GET_CODE (floater) == NOTE
7122 || (GET_CODE (floater) == INSN
7123 && (GET_CODE (PATTERN (floater)) == USE
7124 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7128 /* Anything except a regular INSN will stop our search. */
7129 if (GET_CODE (floater) != INSN
7130 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7131 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7137 /* See if FLOATER is suitable for combination with the
7139 floater_attr = get_attr_pa_combine_type (floater);
7140 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7141 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7142 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7143 && floater_attr == PA_COMBINE_TYPE_FMPY))
7145 /* If ANCHOR and FLOATER can be combined, then we're
7146 done with this pass. */
7147 if (pa_can_combine_p (new, anchor, floater, 1,
7148 SET_DEST (PATTERN (floater)),
7149 XEXP (SET_SRC (PATTERN (floater)),
7151 XEXP (SET_SRC (PATTERN (floater)),
7158 /* FLOATER will be nonzero if we found a suitable floating
7159 insn for combination with ANCHOR. */
7161 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7162 || anchor_attr == PA_COMBINE_TYPE_FMPY))
7164 /* Emit the new instruction and delete the old anchor. */
7165 emit_insn_before (gen_rtx_PARALLEL
7167 gen_rtvec (2, PATTERN (anchor),
7168 PATTERN (floater))),
7171 PUT_CODE (anchor, NOTE);
7172 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7173 NOTE_SOURCE_FILE (anchor) = 0;
7175 /* Emit a special USE insn for FLOATER, then delete
7176 the floating insn. */
7177 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7178 delete_insn (floater);
7183 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
7186 /* Emit the new_jump instruction and delete the old anchor. */
7188 = emit_jump_insn_before (gen_rtx_PARALLEL
7190 gen_rtvec (2, PATTERN (anchor),
7191 PATTERN (floater))),
7194 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
7195 PUT_CODE (anchor, NOTE);
7196 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7197 NOTE_SOURCE_FILE (anchor) = 0;
7199 /* Emit a special USE insn for FLOATER, then delete
7200 the floating insn. */
7201 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7202 delete_insn (floater);
7210 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
7211 rtx new, anchor, floater;
7213 rtx dest, src1, src2;
7215 int insn_code_number;
7218 /* Create a PARALLEL with the patterns of ANCHOR and
7219 FLOATER, try to recognize it, then test constraints
7220 for the resulting pattern.
7222 If the pattern doesn't match or the constraints
7223 aren't met keep searching for a suitable floater
7225 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
7226 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
7227 INSN_CODE (new) = -1;
7228 insn_code_number = recog_memoized (new);
7229 if (insn_code_number < 0
7230 || (extract_insn (new), ! constrain_operands (1)))
7244 /* There's up to three operands to consider. One
7245 output and two inputs.
7247 The output must not be used between FLOATER & ANCHOR
7248 exclusive. The inputs must not be set between
7249 FLOATER and ANCHOR exclusive. */
7251 if (reg_used_between_p (dest, start, end))
7254 if (reg_set_between_p (src1, start, end))
7257 if (reg_set_between_p (src2, start, end))
7260 /* If we get here, then everything is good. */
7264 /* Return nonzero if references for INSN are delayed.
7266 Millicode insns are actually function calls with some special
7267 constraints on arguments and register usage.
7269 Millicode calls always expect their arguments in the integer argument
7270 registers, and always return their result in %r29 (ret1). They
7271 are expected to clobber their arguments, %r1, %r29, and the return
7272 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
7274 This function tells reorg that the references to arguments and
7275 millicode calls do not appear to happen until after the millicode call.
7276 This allows reorg to put insns which set the argument registers into the
7277 delay slot of the millicode call -- thus they act more like traditional
7280 Note we can not consider side effects of the insn to be delayed because
7281 the branch and link insn will clobber the return pointer. If we happened
7282 to use the return pointer in the delay slot of the call, then we lose.
7284 get_attr_type will try to recognize the given insn, so make sure to
7285 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
7288 insn_refs_are_delayed (insn)
7291 return ((GET_CODE (insn) == INSN
7292 && GET_CODE (PATTERN (insn)) != SEQUENCE
7293 && GET_CODE (PATTERN (insn)) != USE
7294 && GET_CODE (PATTERN (insn)) != CLOBBER
7295 && get_attr_type (insn) == TYPE_MILLI));
7298 /* Return the location of a parameter that is passed in a register or NULL
7299 if the parameter has any component that is passed in memory.
7301 This is new code and will be pushed to into the net sources after
7304 ??? We might want to restructure this so that it looks more like other
7307 function_arg (cum, mode, type, named, incoming)
7308 CUMULATIVE_ARGS *cum;
7309 enum machine_mode mode;
7311 int named ATTRIBUTE_UNUSED;
7314 int max_arg_words = (TARGET_64BIT ? 8 : 4);
7321 /* If this arg would be passed partially or totally on the stack, then
7322 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
7323 handle arguments which are split between regs and stack slots if
7324 the ABI mandates split arguments. */
7325 if (cum->words + FUNCTION_ARG_SIZE (mode, type) > max_arg_words
7326 || mode == VOIDmode)
7332 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7334 if (cum->words + offset >= max_arg_words
7335 || mode == VOIDmode)
7339 /* The 32bit ABIs and the 64bit ABIs are rather different,
7340 particularly in their handling of FP registers. We might
7341 be able to cleverly share code between them, but I'm not
7342 going to bother in the hope that splitting them up results
7343 in code that is more easily understood.
7345 The 64bit code probably is very wrong for structure passing. */
7348 /* Advance the base registers to their current locations.
7350 Remember, gprs grow towards smaller register numbers while
7351 fprs grow to higher register numbers. Also remember FP regs
7352 are always 4 bytes wide, while the size of an integer register
7353 varies based on the size of the target word. */
7354 gpr_reg_base = 26 - cum->words;
7355 fpr_reg_base = 32 + cum->words;
7357 /* If the argument is more than a word long, then we need to align
7358 the base registers. Same caveats as above. */
7359 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7361 if (mode != BLKmode)
7363 /* First deal with alignment of the doubleword. */
7364 gpr_reg_base -= (cum->words & 1);
7366 /* This seems backwards, but it is what HP specifies. We need
7367 gpr_reg_base to point to the smaller numbered register of
7368 the integer register pair. So if we have an even register
7369 number, then decrement the gpr base. */
7370 gpr_reg_base -= ((gpr_reg_base % 2) == 0);
7372 /* FP values behave sanely, except that each FP reg is only
7374 fpr_reg_base += ((fpr_reg_base % 2) == 0);
7379 int i, offset = 0, ub;
7380 ub = FUNCTION_ARG_SIZE (mode, type);
7382 MAX (0, max_arg_words - cum->words - (cum->words & 1)));
7383 gpr_reg_base -= (cum->words & 1);
7384 for (i = 0; i < ub; i++)
7386 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7387 gen_rtx_REG (DImode,
7396 return XEXP (loc[0], 0);
7398 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7404 /* If the argument is larger than a word, then we know precisely
7405 which registers we must use. */
7406 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7421 /* We have a single word (32 bits). A simple computation
7422 will get us the register #s we need. */
7423 gpr_reg_base = 26 - cum->words;
7424 fpr_reg_base = 32 + 2 * cum->words;
7428 if (TARGET_64BIT && mode == TFmode)
7434 gen_rtx_EXPR_LIST (VOIDmode,
7435 gen_rtx_REG (DImode, gpr_reg_base + 1),
7437 gen_rtx_EXPR_LIST (VOIDmode,
7438 gen_rtx_REG (DImode, gpr_reg_base),
7441 /* Determine if the argument needs to be passed in both general and
7442 floating point registers. */
7443 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7444 /* If we are doing soft-float with portable runtime, then there
7445 is no need to worry about FP regs. */
7446 && ! TARGET_SOFT_FLOAT
7447 /* The parameter must be some kind of float, else we can just
7448 pass it in integer registers. */
7449 && FLOAT_MODE_P (mode)
7450 /* The target function must not have a prototype. */
7451 && cum->nargs_prototype <= 0
7452 /* libcalls do not need to pass items in both FP and general
7454 && type != NULL_TREE
7455 /* All this hair applies to outgoing args only. */
7457 /* Also pass outgoing floating arguments in both registers in indirect
7458 calls with the 32 bit ABI and the HP assembler since there is no
7459 way to the specify argument locations in static functions. */
7464 && FLOAT_MODE_P (mode)))
7470 gen_rtx_EXPR_LIST (VOIDmode,
7471 gen_rtx_REG (mode, fpr_reg_base),
7473 gen_rtx_EXPR_LIST (VOIDmode,
7474 gen_rtx_REG (mode, gpr_reg_base),
7479 /* See if we should pass this parameter in a general register. */
7480 if (TARGET_SOFT_FLOAT
7481 /* Indirect calls in the normal 32bit ABI require all arguments
7482 to be passed in general registers. */
7483 || (!TARGET_PORTABLE_RUNTIME
7487 /* If the parameter is not a floating point parameter, then
7488 it belongs in GPRs. */
7489 || !FLOAT_MODE_P (mode))
7490 retval = gen_rtx_REG (mode, gpr_reg_base);
7492 retval = gen_rtx_REG (mode, fpr_reg_base);
7498 /* If this arg would be passed totally in registers or totally on the stack,
7499 then this routine should return zero. It is currently called only for
7500 the 64-bit target. */
7502 function_arg_partial_nregs (cum, mode, type, named)
7503 CUMULATIVE_ARGS *cum;
7504 enum machine_mode mode;
7506 int named ATTRIBUTE_UNUSED;
7508 unsigned int max_arg_words = 8;
7509 unsigned int offset = 0;
7511 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7514 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
7515 /* Arg fits fully into registers. */
7517 else if (cum->words + offset >= max_arg_words)
7518 /* Arg fully on the stack. */
7522 return max_arg_words - cum->words - offset;
7526 /* Return 1 if this is a comparison operator. This allows the use of
7527 MATCH_OPERATOR to recognize all the branch insns. */
7530 cmpib_comparison_operator (op, mode)
7532 enum machine_mode mode;
7534 return ((mode == VOIDmode || GET_MODE (op) == mode)
7535 && (GET_CODE (op) == EQ
7536 || GET_CODE (op) == NE
7537 || GET_CODE (op) == GT
7538 || GET_CODE (op) == GTU
7539 || GET_CODE (op) == GE
7540 || GET_CODE (op) == LT
7541 || GET_CODE (op) == LE
7542 || GET_CODE (op) == LEU));
7545 /* Mark ARG (which is really a struct deferred_plabel **) for GC. */
7548 mark_deferred_plabels (arg)
7551 struct deferred_plabel *dp = *(struct deferred_plabel **) arg;
7554 for (i = 0; i < n_deferred_plabels; ++i)
7555 ggc_mark_rtx (dp[i].internal_label);
7558 /* Called to register all of our global variables with the garbage
7564 ggc_add_rtx_root (&hppa_compare_op0, 1);
7565 ggc_add_rtx_root (&hppa_compare_op1, 1);
7566 ggc_add_root (&deferred_plabels, 1, sizeof (&deferred_plabels),
7567 &mark_deferred_plabels);