1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static bool pa_handle_option (size_t, const char *, int);
88 static int hppa_address_cost (rtx);
89 static bool hppa_rtx_costs (rtx, int, int, int *);
90 static inline rtx force_mode (enum machine_mode, rtx);
91 static void pa_reorg (void);
92 static void pa_combine_instructions (void);
93 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
94 static int forward_branch_p (rtx);
95 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
96 static int compute_movmem_length (rtx);
97 static int compute_clrmem_length (rtx);
98 static bool pa_assemble_integer (rtx, unsigned int, int);
99 static void remove_useless_addtr_insns (int);
100 static void store_reg (int, HOST_WIDE_INT, int);
101 static void store_reg_modify (int, int, HOST_WIDE_INT);
102 static void load_reg (int, HOST_WIDE_INT, int);
103 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
104 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
105 static void update_total_code_bytes (int);
106 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
107 static int pa_adjust_cost (rtx, rtx, rtx, int);
108 static int pa_adjust_priority (rtx, int);
109 static int pa_issue_rate (void);
110 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
112 static void pa_encode_section_info (tree, rtx, int);
113 static const char *pa_strip_name_encoding (const char *);
114 static bool pa_function_ok_for_sibcall (tree, tree);
115 static void pa_globalize_label (FILE *, const char *)
117 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
118 HOST_WIDE_INT, tree);
119 #if !defined(USE_COLLECT2)
120 static void pa_asm_out_constructor (rtx, int);
121 static void pa_asm_out_destructor (rtx, int);
123 static void pa_init_builtins (void);
124 static rtx hppa_builtin_saveregs (void);
125 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
126 static bool pa_scalar_mode_supported_p (enum machine_mode);
127 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
128 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
129 static struct deferred_plabel *get_plabel (rtx) ATTRIBUTE_UNUSED;
130 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
134 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
135 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
139 static void output_deferred_plabels (void);
140 #ifdef ASM_OUTPUT_EXTERNAL_REAL
141 static void pa_hpux_file_end (void);
143 #ifdef HPUX_LONG_DOUBLE_LIBRARY
144 static void pa_hpux_init_libfuncs (void);
146 static rtx pa_struct_value_rtx (tree, int);
147 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
149 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
151 static struct machine_function * pa_init_machine_status (void);
154 /* Save the operands last given to a compare for use when we
155 generate a scc or bcc insn. */
156 rtx hppa_compare_op0, hppa_compare_op1;
157 enum cmp_type hppa_branch_type;
159 /* Which cpu we are scheduling for. */
160 enum processor_type pa_cpu = TARGET_SCHED_DEFAULT;
162 /* The UNIX standard to use for predefines and linking. */
163 int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993;
165 /* Counts for the number of callee-saved general and floating point
166 registers which were saved by the current function's prologue. */
167 static int gr_saved, fr_saved;
169 static rtx find_addr_reg (rtx);
171 /* Keep track of the number of bytes we have output in the CODE subspace
172 during this compilation so we'll know when to emit inline long-calls. */
173 unsigned long total_code_bytes;
175 /* The last address of the previous function plus the number of bytes in
176 associated thunks that have been output. This is used to determine if
177 a thunk can use an IA-relative branch to reach its target function. */
178 static int last_address;
180 /* Variables to handle plabels that we discover are necessary at assembly
181 output time. They are output after the current function. */
182 struct deferred_plabel GTY(())
187 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
189 static size_t n_deferred_plabels = 0;
192 /* Initialize the GCC target structure. */
194 #undef TARGET_ASM_ALIGNED_HI_OP
195 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
196 #undef TARGET_ASM_ALIGNED_SI_OP
197 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
198 #undef TARGET_ASM_ALIGNED_DI_OP
199 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
200 #undef TARGET_ASM_UNALIGNED_HI_OP
201 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
202 #undef TARGET_ASM_UNALIGNED_SI_OP
203 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
204 #undef TARGET_ASM_UNALIGNED_DI_OP
205 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
206 #undef TARGET_ASM_INTEGER
207 #define TARGET_ASM_INTEGER pa_assemble_integer
209 #undef TARGET_ASM_FUNCTION_PROLOGUE
210 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
211 #undef TARGET_ASM_FUNCTION_EPILOGUE
212 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
214 #undef TARGET_SCHED_ADJUST_COST
215 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
216 #undef TARGET_SCHED_ADJUST_PRIORITY
217 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
218 #undef TARGET_SCHED_ISSUE_RATE
219 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
221 #undef TARGET_ENCODE_SECTION_INFO
222 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
223 #undef TARGET_STRIP_NAME_ENCODING
224 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
226 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
227 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
229 #undef TARGET_ASM_OUTPUT_MI_THUNK
230 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
231 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
232 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
234 #undef TARGET_ASM_FILE_END
235 #ifdef ASM_OUTPUT_EXTERNAL_REAL
236 #define TARGET_ASM_FILE_END pa_hpux_file_end
238 #define TARGET_ASM_FILE_END output_deferred_plabels
241 #if !defined(USE_COLLECT2)
242 #undef TARGET_ASM_CONSTRUCTOR
243 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
244 #undef TARGET_ASM_DESTRUCTOR
245 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
248 #undef TARGET_DEFAULT_TARGET_FLAGS
249 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
250 #undef TARGET_HANDLE_OPTION
251 #define TARGET_HANDLE_OPTION pa_handle_option
253 #undef TARGET_INIT_BUILTINS
254 #define TARGET_INIT_BUILTINS pa_init_builtins
256 #undef TARGET_RTX_COSTS
257 #define TARGET_RTX_COSTS hppa_rtx_costs
258 #undef TARGET_ADDRESS_COST
259 #define TARGET_ADDRESS_COST hppa_address_cost
261 #undef TARGET_MACHINE_DEPENDENT_REORG
262 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
264 #ifdef HPUX_LONG_DOUBLE_LIBRARY
265 #undef TARGET_INIT_LIBFUNCS
266 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
269 #undef TARGET_PROMOTE_FUNCTION_RETURN
270 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
271 #undef TARGET_PROMOTE_PROTOTYPES
272 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
274 #undef TARGET_STRUCT_VALUE_RTX
275 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
276 #undef TARGET_RETURN_IN_MEMORY
277 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
278 #undef TARGET_MUST_PASS_IN_STACK
279 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
280 #undef TARGET_PASS_BY_REFERENCE
281 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
282 #undef TARGET_CALLEE_COPIES
283 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
284 #undef TARGET_ARG_PARTIAL_BYTES
285 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
287 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
288 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
289 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
290 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
292 #undef TARGET_SCALAR_MODE_SUPPORTED_P
293 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
295 #undef TARGET_CANNOT_FORCE_CONST_MEM
296 #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p
298 struct gcc_target targetm = TARGET_INITIALIZER;
300 /* Parse the -mfixed-range= option string. */
303 fix_range (const char *const_str)
306 char *str, *dash, *comma;
308 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
309 REG2 are either register names or register numbers. The effect
310 of this option is to mark the registers in the range from REG1 to
311 REG2 as ``fixed'' so they won't be used by the compiler. This is
312 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
314 i = strlen (const_str);
315 str = (char *) alloca (i + 1);
316 memcpy (str, const_str, i + 1);
320 dash = strchr (str, '-');
323 warning (0, "value of -mfixed-range must have form REG1-REG2");
328 comma = strchr (dash + 1, ',');
332 first = decode_reg_name (str);
335 warning (0, "unknown register name: %s", str);
339 last = decode_reg_name (dash + 1);
342 warning (0, "unknown register name: %s", dash + 1);
350 warning (0, "%s-%s is an empty range", str, dash + 1);
354 for (i = first; i <= last; ++i)
355 fixed_regs[i] = call_used_regs[i] = 1;
364 /* Check if all floating point registers have been fixed. */
365 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
370 target_flags |= MASK_DISABLE_FPREGS;
373 /* Implement TARGET_HANDLE_OPTION. */
376 pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
381 case OPT_mpa_risc_1_0:
383 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
387 case OPT_mpa_risc_1_1:
389 target_flags &= ~MASK_PA_20;
390 target_flags |= MASK_PA_11;
393 case OPT_mpa_risc_2_0:
395 target_flags |= MASK_PA_11 | MASK_PA_20;
399 if (strcmp (arg, "8000") == 0)
400 pa_cpu = PROCESSOR_8000;
401 else if (strcmp (arg, "7100") == 0)
402 pa_cpu = PROCESSOR_7100;
403 else if (strcmp (arg, "700") == 0)
404 pa_cpu = PROCESSOR_700;
405 else if (strcmp (arg, "7100LC") == 0)
406 pa_cpu = PROCESSOR_7100LC;
407 else if (strcmp (arg, "7200") == 0)
408 pa_cpu = PROCESSOR_7200;
409 else if (strcmp (arg, "7300") == 0)
410 pa_cpu = PROCESSOR_7300;
415 case OPT_mfixed_range_:
425 #if TARGET_HPUX_10_10
431 #if TARGET_HPUX_11_11
443 override_options (void)
445 /* Unconditional branches in the delay slot are not compatible with dwarf2
446 call frame information. There is no benefit in using this optimization
447 on PA8000 and later processors. */
448 if (pa_cpu >= PROCESSOR_8000
449 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
450 || flag_unwind_tables)
451 target_flags &= ~MASK_JUMP_IN_DELAY;
453 if (flag_pic && TARGET_PORTABLE_RUNTIME)
455 warning (0, "PIC code generation is not supported in the portable runtime model");
458 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
460 warning (0, "PIC code generation is not compatible with fast indirect calls");
463 if (! TARGET_GAS && write_symbols != NO_DEBUG)
465 warning (0, "-g is only supported when using GAS on this processor,");
466 warning (0, "-g option disabled");
467 write_symbols = NO_DEBUG;
470 /* We only support the "big PIC" model now. And we always generate PIC
471 code when in 64bit mode. */
472 if (flag_pic == 1 || TARGET_64BIT)
475 /* We can't guarantee that .dword is available for 32-bit targets. */
476 if (UNITS_PER_WORD == 4)
477 targetm.asm_out.aligned_op.di = NULL;
479 /* The unaligned ops are only available when using GAS. */
482 targetm.asm_out.unaligned_op.hi = NULL;
483 targetm.asm_out.unaligned_op.si = NULL;
484 targetm.asm_out.unaligned_op.di = NULL;
487 init_machine_status = pa_init_machine_status;
491 pa_init_builtins (void)
493 #ifdef DONT_HAVE_FPUTC_UNLOCKED
494 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
495 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
499 /* Function to init struct machine_function.
500 This will be called, via a pointer variable,
501 from push_function_context. */
503 static struct machine_function *
504 pa_init_machine_status (void)
506 return ggc_alloc_cleared (sizeof (machine_function));
509 /* If FROM is a probable pointer register, mark TO as a probable
510 pointer register with the same pointer alignment as FROM. */
513 copy_reg_pointer (rtx to, rtx from)
515 if (REG_POINTER (from))
516 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
519 /* Return 1 if X contains a symbolic expression. We know these
520 expressions will have one of a few well defined forms, so
521 we need only check those forms. */
523 symbolic_expression_p (rtx x)
526 /* Strip off any HIGH. */
527 if (GET_CODE (x) == HIGH)
530 return (symbolic_operand (x, VOIDmode));
533 /* Accept any constant that can be moved in one instruction into a
536 cint_ok_for_move (HOST_WIDE_INT intval)
538 /* OK if ldo, ldil, or zdepi, can be used. */
539 return (CONST_OK_FOR_LETTER_P (intval, 'J')
540 || CONST_OK_FOR_LETTER_P (intval, 'N')
541 || CONST_OK_FOR_LETTER_P (intval, 'K'));
544 /* Return truth value of whether OP can be used as an operand in a
547 adddi3_operand (rtx op, enum machine_mode mode)
549 return (register_operand (op, mode)
550 || (GET_CODE (op) == CONST_INT
551 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
554 /* True iff zdepi can be used to generate this CONST_INT.
555 zdepi first sign extends a 5 bit signed number to a given field
556 length, then places this field anywhere in a zero. */
558 zdepi_cint_p (unsigned HOST_WIDE_INT x)
560 unsigned HOST_WIDE_INT lsb_mask, t;
562 /* This might not be obvious, but it's at least fast.
563 This function is critical; we don't have the time loops would take. */
565 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
566 /* Return true iff t is a power of two. */
567 return ((t & (t - 1)) == 0);
570 /* True iff depi or extru can be used to compute (reg & mask).
571 Accept bit pattern like these:
576 and_mask_p (unsigned HOST_WIDE_INT mask)
579 mask += mask & -mask;
580 return (mask & (mask - 1)) == 0;
583 /* True iff depi can be used to compute (reg | MASK). */
585 ior_mask_p (unsigned HOST_WIDE_INT mask)
587 mask += mask & -mask;
588 return (mask & (mask - 1)) == 0;
591 /* Legitimize PIC addresses. If the address is already
592 position-independent, we return ORIG. Newly generated
593 position-independent addresses go to REG. If we need more
594 than one register, we lose. */
597 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
601 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
603 /* Labels need special handling. */
604 if (pic_label_operand (orig, mode))
606 /* We do not want to go through the movXX expanders here since that
607 would create recursion.
609 Nor do we really want to call a generator for a named pattern
610 since that requires multiple patterns if we want to support
613 So instead we just emit the raw set, which avoids the movXX
614 expanders completely. */
615 mark_reg_pointer (reg, BITS_PER_UNIT);
616 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
617 current_function_uses_pic_offset_table = 1;
620 if (GET_CODE (orig) == SYMBOL_REF)
626 /* Before reload, allocate a temporary register for the intermediate
627 result. This allows the sequence to be deleted when the final
628 result is unused and the insns are trivially dead. */
629 tmp_reg = ((reload_in_progress || reload_completed)
630 ? reg : gen_reg_rtx (Pmode));
632 emit_move_insn (tmp_reg,
633 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
634 gen_rtx_HIGH (word_mode, orig)));
636 = gen_const_mem (Pmode,
637 gen_rtx_LO_SUM (Pmode, tmp_reg,
638 gen_rtx_UNSPEC (Pmode,
642 current_function_uses_pic_offset_table = 1;
643 mark_reg_pointer (reg, BITS_PER_UNIT);
644 insn = emit_move_insn (reg, pic_ref);
646 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
647 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
651 else if (GET_CODE (orig) == CONST)
655 if (GET_CODE (XEXP (orig, 0)) == PLUS
656 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
660 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
662 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
663 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
664 base == reg ? 0 : reg);
666 if (GET_CODE (orig) == CONST_INT)
668 if (INT_14_BITS (orig))
669 return plus_constant (base, INTVAL (orig));
670 orig = force_reg (Pmode, orig);
672 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
673 /* Likewise, should we set special REG_NOTEs here? */
679 static GTY(()) rtx gen_tls_tga;
682 gen_tls_get_addr (void)
685 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
690 hppa_tls_call (rtx arg)
694 ret = gen_reg_rtx (Pmode);
695 emit_library_call_value (gen_tls_get_addr (), ret,
696 LCT_CONST, Pmode, 1, arg, Pmode);
702 legitimize_tls_address (rtx addr)
704 rtx ret, insn, tmp, t1, t2, tp;
705 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
709 case TLS_MODEL_GLOBAL_DYNAMIC:
710 tmp = gen_reg_rtx (Pmode);
711 emit_insn (gen_tgd_load (tmp, addr));
712 ret = hppa_tls_call (tmp);
715 case TLS_MODEL_LOCAL_DYNAMIC:
716 ret = gen_reg_rtx (Pmode);
717 tmp = gen_reg_rtx (Pmode);
719 emit_insn (gen_tld_load (tmp, addr));
720 t1 = hppa_tls_call (tmp);
723 t2 = gen_reg_rtx (Pmode);
724 emit_libcall_block (insn, t2, t1,
725 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
727 emit_insn (gen_tld_offset_load (ret, addr, t2));
730 case TLS_MODEL_INITIAL_EXEC:
731 tp = gen_reg_rtx (Pmode);
732 tmp = gen_reg_rtx (Pmode);
733 ret = gen_reg_rtx (Pmode);
734 emit_insn (gen_tp_load (tp));
735 emit_insn (gen_tie_load (tmp, addr));
736 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
739 case TLS_MODEL_LOCAL_EXEC:
740 tp = gen_reg_rtx (Pmode);
741 ret = gen_reg_rtx (Pmode);
742 emit_insn (gen_tp_load (tp));
743 emit_insn (gen_tle_load (ret, addr, tp));
753 /* Try machine-dependent ways of modifying an illegitimate address
754 to be legitimate. If we find one, return the new, valid address.
755 This macro is used in only one place: `memory_address' in explow.c.
757 OLDX is the address as it was before break_out_memory_refs was called.
758 In some cases it is useful to look at this to decide what needs to be done.
760 MODE and WIN are passed so that this macro can use
761 GO_IF_LEGITIMATE_ADDRESS.
763 It is always safe for this macro to do nothing. It exists to recognize
764 opportunities to optimize the output.
766 For the PA, transform:
768 memory(X + <large int>)
772 if (<large int> & mask) >= 16
773 Y = (<large int> & ~mask) + mask + 1 Round up.
775 Y = (<large int> & ~mask) Round down.
777 memory (Z + (<large int> - Y));
779 This is for CSE to find several similar references, and only use one Z.
781 X can either be a SYMBOL_REF or REG, but because combine cannot
782 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
783 D will not fit in 14 bits.
785 MODE_FLOAT references allow displacements which fit in 5 bits, so use
788 MODE_INT references allow displacements which fit in 14 bits, so use
791 This relies on the fact that most mode MODE_FLOAT references will use FP
792 registers and most mode MODE_INT references will use integer registers.
793 (In the rare case of an FP register used in an integer MODE, we depend
794 on secondary reloads to clean things up.)
797 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
798 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
799 addressing modes to be used).
801 Put X and Z into registers. Then put the entire expression into
805 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
806 enum machine_mode mode)
810 /* We need to canonicalize the order of operands in unscaled indexed
811 addresses since the code that checks if an address is valid doesn't
812 always try both orders. */
813 if (!TARGET_NO_SPACE_REGS
814 && GET_CODE (x) == PLUS
815 && GET_MODE (x) == Pmode
816 && REG_P (XEXP (x, 0))
817 && REG_P (XEXP (x, 1))
818 && REG_POINTER (XEXP (x, 0))
819 && !REG_POINTER (XEXP (x, 1)))
820 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
822 if (PA_SYMBOL_REF_TLS_P (x))
823 return legitimize_tls_address (x);
825 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
827 /* Strip off CONST. */
828 if (GET_CODE (x) == CONST)
831 /* Special case. Get the SYMBOL_REF into a register and use indexing.
832 That should always be safe. */
833 if (GET_CODE (x) == PLUS
834 && GET_CODE (XEXP (x, 0)) == REG
835 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
837 rtx reg = force_reg (Pmode, XEXP (x, 1));
838 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
841 /* Note we must reject symbols which represent function addresses
842 since the assembler/linker can't handle arithmetic on plabels. */
843 if (GET_CODE (x) == PLUS
844 && GET_CODE (XEXP (x, 1)) == CONST_INT
845 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
846 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
847 || GET_CODE (XEXP (x, 0)) == REG))
849 rtx int_part, ptr_reg;
851 int offset = INTVAL (XEXP (x, 1));
854 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
855 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
857 /* Choose which way to round the offset. Round up if we
858 are >= halfway to the next boundary. */
859 if ((offset & mask) >= ((mask + 1) / 2))
860 newoffset = (offset & ~ mask) + mask + 1;
862 newoffset = (offset & ~ mask);
864 /* If the newoffset will not fit in 14 bits (ldo), then
865 handling this would take 4 or 5 instructions (2 to load
866 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
867 add the new offset and the SYMBOL_REF.) Combine can
868 not handle 4->2 or 5->2 combinations, so do not create
870 if (! VAL_14_BITS_P (newoffset)
871 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
873 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
876 gen_rtx_HIGH (Pmode, const_part));
879 gen_rtx_LO_SUM (Pmode,
880 tmp_reg, const_part));
884 if (! VAL_14_BITS_P (newoffset))
885 int_part = force_reg (Pmode, GEN_INT (newoffset));
887 int_part = GEN_INT (newoffset);
889 ptr_reg = force_reg (Pmode,
891 force_reg (Pmode, XEXP (x, 0)),
894 return plus_constant (ptr_reg, offset - newoffset);
897 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
899 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
900 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
901 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
902 && (OBJECT_P (XEXP (x, 1))
903 || GET_CODE (XEXP (x, 1)) == SUBREG)
904 && GET_CODE (XEXP (x, 1)) != CONST)
906 int val = INTVAL (XEXP (XEXP (x, 0), 1));
910 if (GET_CODE (reg1) != REG)
911 reg1 = force_reg (Pmode, force_operand (reg1, 0));
913 reg2 = XEXP (XEXP (x, 0), 0);
914 if (GET_CODE (reg2) != REG)
915 reg2 = force_reg (Pmode, force_operand (reg2, 0));
917 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
924 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
926 Only do so for floating point modes since this is more speculative
927 and we lose if it's an integer store. */
928 if (GET_CODE (x) == PLUS
929 && GET_CODE (XEXP (x, 0)) == PLUS
930 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
931 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
932 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
933 && (mode == SFmode || mode == DFmode))
936 /* First, try and figure out what to use as a base register. */
937 rtx reg1, reg2, base, idx, orig_base;
939 reg1 = XEXP (XEXP (x, 0), 1);
944 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
945 then emit_move_sequence will turn on REG_POINTER so we'll know
946 it's a base register below. */
947 if (GET_CODE (reg1) != REG)
948 reg1 = force_reg (Pmode, force_operand (reg1, 0));
950 if (GET_CODE (reg2) != REG)
951 reg2 = force_reg (Pmode, force_operand (reg2, 0));
953 /* Figure out what the base and index are. */
955 if (GET_CODE (reg1) == REG
956 && REG_POINTER (reg1))
959 orig_base = XEXP (XEXP (x, 0), 1);
960 idx = gen_rtx_PLUS (Pmode,
962 XEXP (XEXP (XEXP (x, 0), 0), 0),
963 XEXP (XEXP (XEXP (x, 0), 0), 1)),
966 else if (GET_CODE (reg2) == REG
967 && REG_POINTER (reg2))
970 orig_base = XEXP (x, 1);
977 /* If the index adds a large constant, try to scale the
978 constant so that it can be loaded with only one insn. */
979 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
980 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
981 / INTVAL (XEXP (XEXP (idx, 0), 1)))
982 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
984 /* Divide the CONST_INT by the scale factor, then add it to A. */
985 int val = INTVAL (XEXP (idx, 1));
987 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
988 reg1 = XEXP (XEXP (idx, 0), 0);
989 if (GET_CODE (reg1) != REG)
990 reg1 = force_reg (Pmode, force_operand (reg1, 0));
992 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
994 /* We can now generate a simple scaled indexed address. */
997 (Pmode, gen_rtx_PLUS (Pmode,
998 gen_rtx_MULT (Pmode, reg1,
999 XEXP (XEXP (idx, 0), 1)),
1003 /* If B + C is still a valid base register, then add them. */
1004 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1005 && INTVAL (XEXP (idx, 1)) <= 4096
1006 && INTVAL (XEXP (idx, 1)) >= -4096)
1008 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1011 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1013 reg2 = XEXP (XEXP (idx, 0), 0);
1014 if (GET_CODE (reg2) != CONST_INT)
1015 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1017 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1018 gen_rtx_MULT (Pmode,
1024 /* Get the index into a register, then add the base + index and
1025 return a register holding the result. */
1027 /* First get A into a register. */
1028 reg1 = XEXP (XEXP (idx, 0), 0);
1029 if (GET_CODE (reg1) != REG)
1030 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1032 /* And get B into a register. */
1033 reg2 = XEXP (idx, 1);
1034 if (GET_CODE (reg2) != REG)
1035 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1037 reg1 = force_reg (Pmode,
1038 gen_rtx_PLUS (Pmode,
1039 gen_rtx_MULT (Pmode, reg1,
1040 XEXP (XEXP (idx, 0), 1)),
1043 /* Add the result to our base register and return. */
1044 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1048 /* Uh-oh. We might have an address for x[n-100000]. This needs
1049 special handling to avoid creating an indexed memory address
1050 with x-100000 as the base.
1052 If the constant part is small enough, then it's still safe because
1053 there is a guard page at the beginning and end of the data segment.
1055 Scaled references are common enough that we want to try and rearrange the
1056 terms so that we can use indexing for these addresses too. Only
1057 do the optimization for floatint point modes. */
1059 if (GET_CODE (x) == PLUS
1060 && symbolic_expression_p (XEXP (x, 1)))
1062 /* Ugly. We modify things here so that the address offset specified
1063 by the index expression is computed first, then added to x to form
1064 the entire address. */
1066 rtx regx1, regx2, regy1, regy2, y;
1068 /* Strip off any CONST. */
1070 if (GET_CODE (y) == CONST)
1073 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1075 /* See if this looks like
1076 (plus (mult (reg) (shadd_const))
1077 (const (plus (symbol_ref) (const_int))))
1079 Where const_int is small. In that case the const
1080 expression is a valid pointer for indexing.
1082 If const_int is big, but can be divided evenly by shadd_const
1083 and added to (reg). This allows more scaled indexed addresses. */
1084 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1085 && GET_CODE (XEXP (x, 0)) == MULT
1086 && GET_CODE (XEXP (y, 1)) == CONST_INT
1087 && INTVAL (XEXP (y, 1)) >= -4096
1088 && INTVAL (XEXP (y, 1)) <= 4095
1089 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1090 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1092 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1096 if (GET_CODE (reg1) != REG)
1097 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1099 reg2 = XEXP (XEXP (x, 0), 0);
1100 if (GET_CODE (reg2) != REG)
1101 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1103 return force_reg (Pmode,
1104 gen_rtx_PLUS (Pmode,
1105 gen_rtx_MULT (Pmode,
1110 else if ((mode == DFmode || mode == SFmode)
1111 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1112 && GET_CODE (XEXP (x, 0)) == MULT
1113 && GET_CODE (XEXP (y, 1)) == CONST_INT
1114 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1115 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1116 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1119 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1120 / INTVAL (XEXP (XEXP (x, 0), 1))));
1121 regx2 = XEXP (XEXP (x, 0), 0);
1122 if (GET_CODE (regx2) != REG)
1123 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1124 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1128 gen_rtx_PLUS (Pmode,
1129 gen_rtx_MULT (Pmode, regx2,
1130 XEXP (XEXP (x, 0), 1)),
1131 force_reg (Pmode, XEXP (y, 0))));
1133 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1134 && INTVAL (XEXP (y, 1)) >= -4096
1135 && INTVAL (XEXP (y, 1)) <= 4095)
1137 /* This is safe because of the guard page at the
1138 beginning and end of the data space. Just
1139 return the original address. */
1144 /* Doesn't look like one we can optimize. */
1145 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1146 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1147 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1148 regx1 = force_reg (Pmode,
1149 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1151 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1159 /* For the HPPA, REG and REG+CONST is cost 0
1160 and addresses involving symbolic constants are cost 2.
1162 PIC addresses are very expensive.
1164 It is no coincidence that this has the same structure
1165 as GO_IF_LEGITIMATE_ADDRESS. */
1168 hppa_address_cost (rtx X)
1170 switch (GET_CODE (X))
1183 /* Compute a (partial) cost for rtx X. Return true if the complete
1184 cost has been computed, and false if subexpressions should be
1185 scanned. In either case, *TOTAL contains the cost result. */
1188 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1193 if (INTVAL (x) == 0)
1195 else if (INT_14_BITS (x))
1212 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1213 && outer_code != SET)
1220 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1221 *total = COSTS_N_INSNS (3);
1222 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1223 *total = COSTS_N_INSNS (8);
1225 *total = COSTS_N_INSNS (20);
1229 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1231 *total = COSTS_N_INSNS (14);
1239 *total = COSTS_N_INSNS (60);
1242 case PLUS: /* this includes shNadd insns */
1244 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1245 *total = COSTS_N_INSNS (3);
1247 *total = COSTS_N_INSNS (1);
1253 *total = COSTS_N_INSNS (1);
1261 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1262 new rtx with the correct mode. */
1264 force_mode (enum machine_mode mode, rtx orig)
1266 if (mode == GET_MODE (orig))
1269 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1271 return gen_rtx_REG (mode, REGNO (orig));
1274 /* Return 1 if *X is a thread-local symbol. */
1277 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1279 return PA_SYMBOL_REF_TLS_P (*x);
1282 /* Return 1 if X contains a thread-local symbol. */
1285 pa_tls_referenced_p (rtx x)
1287 if (!TARGET_HAVE_TLS)
1290 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1293 /* Emit insns to move operands[1] into operands[0].
1295 Return 1 if we have written out everything that needs to be done to
1296 do the move. Otherwise, return 0 and the caller will emit the move
1299 Note SCRATCH_REG may not be in the proper mode depending on how it
1300 will be used. This routine is responsible for creating a new copy
1301 of SCRATCH_REG in the proper mode. */
1304 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1306 register rtx operand0 = operands[0];
1307 register rtx operand1 = operands[1];
1310 /* We can only handle indexed addresses in the destination operand
1311 of floating point stores. Thus, we need to break out indexed
1312 addresses from the destination operand. */
1313 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1315 /* This is only safe up to the beginning of life analysis. */
1316 gcc_assert (!no_new_pseudos);
1318 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1319 operand0 = replace_equiv_address (operand0, tem);
1322 /* On targets with non-equivalent space registers, break out unscaled
1323 indexed addresses from the source operand before the final CSE.
1324 We have to do this because the REG_POINTER flag is not correctly
1325 carried through various optimization passes and CSE may substitute
1326 a pseudo without the pointer set for one with the pointer set. As
1327 a result, we loose various opportunities to create insns with
1328 unscaled indexed addresses. */
1329 if (!TARGET_NO_SPACE_REGS
1330 && !cse_not_expected
1331 && GET_CODE (operand1) == MEM
1332 && GET_CODE (XEXP (operand1, 0)) == PLUS
1333 && REG_P (XEXP (XEXP (operand1, 0), 0))
1334 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1336 = replace_equiv_address (operand1,
1337 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1340 && reload_in_progress && GET_CODE (operand0) == REG
1341 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1342 operand0 = reg_equiv_mem[REGNO (operand0)];
1343 else if (scratch_reg
1344 && reload_in_progress && GET_CODE (operand0) == SUBREG
1345 && GET_CODE (SUBREG_REG (operand0)) == REG
1346 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1348 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1349 the code which tracks sets/uses for delete_output_reload. */
1350 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1351 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1352 SUBREG_BYTE (operand0));
1353 operand0 = alter_subreg (&temp);
1357 && reload_in_progress && GET_CODE (operand1) == REG
1358 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1359 operand1 = reg_equiv_mem[REGNO (operand1)];
1360 else if (scratch_reg
1361 && reload_in_progress && GET_CODE (operand1) == SUBREG
1362 && GET_CODE (SUBREG_REG (operand1)) == REG
1363 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1365 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1366 the code which tracks sets/uses for delete_output_reload. */
1367 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1368 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1369 SUBREG_BYTE (operand1));
1370 operand1 = alter_subreg (&temp);
1373 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1374 && ((tem = find_replacement (&XEXP (operand0, 0)))
1375 != XEXP (operand0, 0)))
1376 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1378 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1379 && ((tem = find_replacement (&XEXP (operand1, 0)))
1380 != XEXP (operand1, 0)))
1381 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1383 /* Handle secondary reloads for loads/stores of FP registers from
1384 REG+D addresses where D does not fit in 5 or 14 bits, including
1385 (subreg (mem (addr))) cases. */
1387 && fp_reg_operand (operand0, mode)
1388 && ((GET_CODE (operand1) == MEM
1389 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1390 XEXP (operand1, 0)))
1391 || ((GET_CODE (operand1) == SUBREG
1392 && GET_CODE (XEXP (operand1, 0)) == MEM
1393 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1395 XEXP (XEXP (operand1, 0), 0))))))
1397 if (GET_CODE (operand1) == SUBREG)
1398 operand1 = XEXP (operand1, 0);
1400 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1401 it in WORD_MODE regardless of what mode it was originally given
1403 scratch_reg = force_mode (word_mode, scratch_reg);
1405 /* D might not fit in 14 bits either; for such cases load D into
1407 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1409 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1410 emit_move_insn (scratch_reg,
1411 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1413 XEXP (XEXP (operand1, 0), 0),
1417 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1418 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1419 gen_rtx_MEM (mode, scratch_reg)));
1422 else if (scratch_reg
1423 && fp_reg_operand (operand1, mode)
1424 && ((GET_CODE (operand0) == MEM
1425 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1427 XEXP (operand0, 0)))
1428 || ((GET_CODE (operand0) == SUBREG)
1429 && GET_CODE (XEXP (operand0, 0)) == MEM
1430 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1432 XEXP (XEXP (operand0, 0), 0)))))
1434 if (GET_CODE (operand0) == SUBREG)
1435 operand0 = XEXP (operand0, 0);
1437 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1438 it in WORD_MODE regardless of what mode it was originally given
1440 scratch_reg = force_mode (word_mode, scratch_reg);
1442 /* D might not fit in 14 bits either; for such cases load D into
1444 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1446 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1447 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1450 XEXP (XEXP (operand0, 0),
1455 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1456 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1460 /* Handle secondary reloads for loads of FP registers from constant
1461 expressions by forcing the constant into memory.
1463 Use scratch_reg to hold the address of the memory location.
1465 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1466 NO_REGS when presented with a const_int and a register class
1467 containing only FP registers. Doing so unfortunately creates
1468 more problems than it solves. Fix this for 2.5. */
1469 else if (scratch_reg
1470 && CONSTANT_P (operand1)
1471 && fp_reg_operand (operand0, mode))
1475 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1476 it in WORD_MODE regardless of what mode it was originally given
1478 scratch_reg = force_mode (word_mode, scratch_reg);
1480 /* Force the constant into memory and put the address of the
1481 memory location into scratch_reg. */
1482 xoperands[0] = scratch_reg;
1483 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1484 emit_move_sequence (xoperands, Pmode, 0);
1486 /* Now load the destination register. */
1487 emit_insn (gen_rtx_SET (mode, operand0,
1488 gen_rtx_MEM (mode, scratch_reg)));
1491 /* Handle secondary reloads for SAR. These occur when trying to load
1492 the SAR from memory, FP register, or with a constant. */
1493 else if (scratch_reg
1494 && GET_CODE (operand0) == REG
1495 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1496 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1497 && (GET_CODE (operand1) == MEM
1498 || GET_CODE (operand1) == CONST_INT
1499 || (GET_CODE (operand1) == REG
1500 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1502 /* D might not fit in 14 bits either; for such cases load D into
1504 if (GET_CODE (operand1) == MEM
1505 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1507 /* We are reloading the address into the scratch register, so we
1508 want to make sure the scratch register is a full register. */
1509 scratch_reg = force_mode (word_mode, scratch_reg);
1511 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1512 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1515 XEXP (XEXP (operand1, 0),
1519 /* Now we are going to load the scratch register from memory,
1520 we want to load it in the same width as the original MEM,
1521 which must be the same as the width of the ultimate destination,
1523 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1525 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1530 /* We want to load the scratch register using the same mode as
1531 the ultimate destination. */
1532 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1534 emit_move_insn (scratch_reg, operand1);
1537 /* And emit the insn to set the ultimate destination. We know that
1538 the scratch register has the same mode as the destination at this
1540 emit_move_insn (operand0, scratch_reg);
1543 /* Handle the most common case: storing into a register. */
1544 else if (register_operand (operand0, mode))
1546 if (register_operand (operand1, mode)
1547 || (GET_CODE (operand1) == CONST_INT
1548 && cint_ok_for_move (INTVAL (operand1)))
1549 || (operand1 == CONST0_RTX (mode))
1550 || (GET_CODE (operand1) == HIGH
1551 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1552 /* Only `general_operands' can come here, so MEM is ok. */
1553 || GET_CODE (operand1) == MEM)
1555 /* Various sets are created during RTL generation which don't
1556 have the REG_POINTER flag correctly set. After the CSE pass,
1557 instruction recognition can fail if we don't consistently
1558 set this flag when performing register copies. This should
1559 also improve the opportunities for creating insns that use
1560 unscaled indexing. */
1561 if (REG_P (operand0) && REG_P (operand1))
1563 if (REG_POINTER (operand1)
1564 && !REG_POINTER (operand0)
1565 && !HARD_REGISTER_P (operand0))
1566 copy_reg_pointer (operand0, operand1);
1567 else if (REG_POINTER (operand0)
1568 && !REG_POINTER (operand1)
1569 && !HARD_REGISTER_P (operand1))
1570 copy_reg_pointer (operand1, operand0);
1573 /* When MEMs are broken out, the REG_POINTER flag doesn't
1574 get set. In some cases, we can set the REG_POINTER flag
1575 from the declaration for the MEM. */
1576 if (REG_P (operand0)
1577 && GET_CODE (operand1) == MEM
1578 && !REG_POINTER (operand0))
1580 tree decl = MEM_EXPR (operand1);
1582 /* Set the register pointer flag and register alignment
1583 if the declaration for this memory reference is a
1584 pointer type. Fortran indirect argument references
1587 && !(flag_argument_noalias > 1
1588 && TREE_CODE (decl) == INDIRECT_REF
1589 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1593 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1595 if (TREE_CODE (decl) == COMPONENT_REF)
1596 decl = TREE_OPERAND (decl, 1);
1598 type = TREE_TYPE (decl);
1599 if (TREE_CODE (type) == ARRAY_TYPE)
1600 type = get_inner_array_type (type);
1602 if (POINTER_TYPE_P (type))
1606 type = TREE_TYPE (type);
1607 /* Using TYPE_ALIGN_OK is rather conservative as
1608 only the ada frontend actually sets it. */
1609 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1611 mark_reg_pointer (operand0, align);
1616 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1620 else if (GET_CODE (operand0) == MEM)
1622 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1623 && !(reload_in_progress || reload_completed))
1625 rtx temp = gen_reg_rtx (DFmode);
1627 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1628 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1631 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1633 /* Run this case quickly. */
1634 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1637 if (! (reload_in_progress || reload_completed))
1639 operands[0] = validize_mem (operand0);
1640 operands[1] = operand1 = force_reg (mode, operand1);
1644 /* Simplify the source if we need to.
1645 Note we do have to handle function labels here, even though we do
1646 not consider them legitimate constants. Loop optimizations can
1647 call the emit_move_xxx with one as a source. */
1648 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1649 || function_label_operand (operand1, mode)
1650 || (GET_CODE (operand1) == HIGH
1651 && symbolic_operand (XEXP (operand1, 0), mode)))
1655 if (GET_CODE (operand1) == HIGH)
1658 operand1 = XEXP (operand1, 0);
1660 if (symbolic_operand (operand1, mode))
1662 /* Argh. The assembler and linker can't handle arithmetic
1665 So we force the plabel into memory, load operand0 from
1666 the memory location, then add in the constant part. */
1667 if ((GET_CODE (operand1) == CONST
1668 && GET_CODE (XEXP (operand1, 0)) == PLUS
1669 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1670 || function_label_operand (operand1, mode))
1672 rtx temp, const_part;
1674 /* Figure out what (if any) scratch register to use. */
1675 if (reload_in_progress || reload_completed)
1677 scratch_reg = scratch_reg ? scratch_reg : operand0;
1678 /* SCRATCH_REG will hold an address and maybe the actual
1679 data. We want it in WORD_MODE regardless of what mode it
1680 was originally given to us. */
1681 scratch_reg = force_mode (word_mode, scratch_reg);
1684 scratch_reg = gen_reg_rtx (Pmode);
1686 if (GET_CODE (operand1) == CONST)
1688 /* Save away the constant part of the expression. */
1689 const_part = XEXP (XEXP (operand1, 0), 1);
1690 gcc_assert (GET_CODE (const_part) == CONST_INT);
1692 /* Force the function label into memory. */
1693 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1697 /* No constant part. */
1698 const_part = NULL_RTX;
1700 /* Force the function label into memory. */
1701 temp = force_const_mem (mode, operand1);
1705 /* Get the address of the memory location. PIC-ify it if
1707 temp = XEXP (temp, 0);
1709 temp = legitimize_pic_address (temp, mode, scratch_reg);
1711 /* Put the address of the memory location into our destination
1714 emit_move_sequence (operands, mode, scratch_reg);
1716 /* Now load from the memory location into our destination
1718 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1719 emit_move_sequence (operands, mode, scratch_reg);
1721 /* And add back in the constant part. */
1722 if (const_part != NULL_RTX)
1723 expand_inc (operand0, const_part);
1732 if (reload_in_progress || reload_completed)
1734 temp = scratch_reg ? scratch_reg : operand0;
1735 /* TEMP will hold an address and maybe the actual
1736 data. We want it in WORD_MODE regardless of what mode it
1737 was originally given to us. */
1738 temp = force_mode (word_mode, temp);
1741 temp = gen_reg_rtx (Pmode);
1743 /* (const (plus (symbol) (const_int))) must be forced to
1744 memory during/after reload if the const_int will not fit
1746 if (GET_CODE (operand1) == CONST
1747 && GET_CODE (XEXP (operand1, 0)) == PLUS
1748 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1749 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1750 && (reload_completed || reload_in_progress)
1753 operands[1] = force_const_mem (mode, operand1);
1754 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1756 operands[1] = gen_rtx_MEM (mode, operands[1]);
1757 emit_move_sequence (operands, mode, temp);
1761 operands[1] = legitimize_pic_address (operand1, mode, temp);
1762 if (REG_P (operand0) && REG_P (operands[1]))
1763 copy_reg_pointer (operand0, operands[1]);
1764 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1767 /* On the HPPA, references to data space are supposed to use dp,
1768 register 27, but showing it in the RTL inhibits various cse
1769 and loop optimizations. */
1774 if (reload_in_progress || reload_completed)
1776 temp = scratch_reg ? scratch_reg : operand0;
1777 /* TEMP will hold an address and maybe the actual
1778 data. We want it in WORD_MODE regardless of what mode it
1779 was originally given to us. */
1780 temp = force_mode (word_mode, temp);
1783 temp = gen_reg_rtx (mode);
1785 /* Loading a SYMBOL_REF into a register makes that register
1786 safe to be used as the base in an indexed address.
1788 Don't mark hard registers though. That loses. */
1789 if (GET_CODE (operand0) == REG
1790 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1791 mark_reg_pointer (operand0, BITS_PER_UNIT);
1792 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1793 mark_reg_pointer (temp, BITS_PER_UNIT);
1796 set = gen_rtx_SET (mode, operand0, temp);
1798 set = gen_rtx_SET (VOIDmode,
1800 gen_rtx_LO_SUM (mode, temp, operand1));
1802 emit_insn (gen_rtx_SET (VOIDmode,
1804 gen_rtx_HIGH (mode, operand1)));
1810 else if (pa_tls_referenced_p (operand1))
1815 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
1817 addend = XEXP (XEXP (tmp, 0), 1);
1818 tmp = XEXP (XEXP (tmp, 0), 0);
1821 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
1822 tmp = legitimize_tls_address (tmp);
1825 tmp = gen_rtx_PLUS (mode, tmp, addend);
1826 tmp = force_operand (tmp, operands[0]);
1830 else if (GET_CODE (operand1) != CONST_INT
1831 || !cint_ok_for_move (INTVAL (operand1)))
1835 HOST_WIDE_INT value = 0;
1836 HOST_WIDE_INT insv = 0;
1839 if (GET_CODE (operand1) == CONST_INT)
1840 value = INTVAL (operand1);
1843 && GET_CODE (operand1) == CONST_INT
1844 && HOST_BITS_PER_WIDE_INT > 32
1845 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1849 /* Extract the low order 32 bits of the value and sign extend.
1850 If the new value is the same as the original value, we can
1851 can use the original value as-is. If the new value is
1852 different, we use it and insert the most-significant 32-bits
1853 of the original value into the final result. */
1854 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
1855 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1858 #if HOST_BITS_PER_WIDE_INT > 32
1859 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
1863 operand1 = GEN_INT (nval);
1867 if (reload_in_progress || reload_completed)
1868 temp = scratch_reg ? scratch_reg : operand0;
1870 temp = gen_reg_rtx (mode);
1872 /* We don't directly split DImode constants on 32-bit targets
1873 because PLUS uses an 11-bit immediate and the insn sequence
1874 generated is not as efficient as the one using HIGH/LO_SUM. */
1875 if (GET_CODE (operand1) == CONST_INT
1876 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1879 /* Directly break constant into high and low parts. This
1880 provides better optimization opportunities because various
1881 passes recognize constants split with PLUS but not LO_SUM.
1882 We use a 14-bit signed low part except when the addition
1883 of 0x4000 to the high part might change the sign of the
1885 HOST_WIDE_INT low = value & 0x3fff;
1886 HOST_WIDE_INT high = value & ~ 0x3fff;
1890 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1898 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1899 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1903 emit_insn (gen_rtx_SET (VOIDmode, temp,
1904 gen_rtx_HIGH (mode, operand1)));
1905 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1908 insn = emit_move_insn (operands[0], operands[1]);
1910 /* Now insert the most significant 32 bits of the value
1911 into the register. When we don't have a second register
1912 available, it could take up to nine instructions to load
1913 a 64-bit integer constant. Prior to reload, we force
1914 constants that would take more than three instructions
1915 to load to the constant pool. During and after reload,
1916 we have to handle all possible values. */
1919 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
1920 register and the value to be inserted is outside the
1921 range that can be loaded with three depdi instructions. */
1922 if (temp != operand0 && (insv >= 16384 || insv < -16384))
1924 operand1 = GEN_INT (insv);
1926 emit_insn (gen_rtx_SET (VOIDmode, temp,
1927 gen_rtx_HIGH (mode, operand1)));
1928 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
1929 emit_insn (gen_insv (operand0, GEN_INT (32),
1934 int len = 5, pos = 27;
1936 /* Insert the bits using the depdi instruction. */
1939 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
1940 HOST_WIDE_INT sign = v5 < 0;
1942 /* Left extend the insertion. */
1943 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
1944 while (pos > 0 && (insv & 1) == sign)
1946 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
1951 emit_insn (gen_insv (operand0, GEN_INT (len),
1952 GEN_INT (pos), GEN_INT (v5)));
1954 len = pos > 0 && pos < 5 ? pos : 5;
1961 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
1966 /* Now have insn-emit do whatever it normally does. */
1970 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1971 it will need a link/runtime reloc). */
1974 reloc_needed (tree exp)
1978 switch (TREE_CODE (exp))
1985 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1986 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1991 case NON_LVALUE_EXPR:
1992 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1998 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1999 if (TREE_VALUE (link) != 0)
2000 reloc |= reloc_needed (TREE_VALUE (link));
2013 /* Does operand (which is a symbolic_operand) live in text space?
2014 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2018 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2020 if (GET_CODE (operand) == CONST)
2021 operand = XEXP (XEXP (operand, 0), 0);
2024 if (GET_CODE (operand) == SYMBOL_REF)
2025 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2029 if (GET_CODE (operand) == SYMBOL_REF)
2030 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2036 /* Return the best assembler insn template
2037 for moving operands[1] into operands[0] as a fullword. */
2039 singlemove_string (rtx *operands)
2041 HOST_WIDE_INT intval;
2043 if (GET_CODE (operands[0]) == MEM)
2044 return "stw %r1,%0";
2045 if (GET_CODE (operands[1]) == MEM)
2047 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2052 gcc_assert (GET_MODE (operands[1]) == SFmode);
2054 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2056 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2057 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2059 operands[1] = GEN_INT (i);
2060 /* Fall through to CONST_INT case. */
2062 if (GET_CODE (operands[1]) == CONST_INT)
2064 intval = INTVAL (operands[1]);
2066 if (VAL_14_BITS_P (intval))
2068 else if ((intval & 0x7ff) == 0)
2069 return "ldil L'%1,%0";
2070 else if (zdepi_cint_p (intval))
2071 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2073 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2075 return "copy %1,%0";
2079 /* Compute position (in OP[1]) and width (in OP[2])
2080 useful for copying IMM to a register using the zdepi
2081 instructions. Store the immediate value to insert in OP[0]. */
2083 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2087 /* Find the least significant set bit in IMM. */
2088 for (lsb = 0; lsb < 32; lsb++)
2095 /* Choose variants based on *sign* of the 5-bit field. */
2096 if ((imm & 0x10) == 0)
2097 len = (lsb <= 28) ? 4 : 32 - lsb;
2100 /* Find the width of the bitstring in IMM. */
2101 for (len = 5; len < 32; len++)
2103 if ((imm & (1 << len)) == 0)
2107 /* Sign extend IMM as a 5-bit value. */
2108 imm = (imm & 0xf) - 0x10;
2116 /* Compute position (in OP[1]) and width (in OP[2])
2117 useful for copying IMM to a register using the depdi,z
2118 instructions. Store the immediate value to insert in OP[0]. */
2120 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2122 HOST_WIDE_INT lsb, len;
2124 /* Find the least significant set bit in IMM. */
2125 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2132 /* Choose variants based on *sign* of the 5-bit field. */
2133 if ((imm & 0x10) == 0)
2134 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2135 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2138 /* Find the width of the bitstring in IMM. */
2139 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2141 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2145 /* Sign extend IMM as a 5-bit value. */
2146 imm = (imm & 0xf) - 0x10;
2154 /* Output assembler code to perform a doubleword move insn
2155 with operands OPERANDS. */
2158 output_move_double (rtx *operands)
2160 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2162 rtx addreg0 = 0, addreg1 = 0;
2164 /* First classify both operands. */
2166 if (REG_P (operands[0]))
2168 else if (offsettable_memref_p (operands[0]))
2170 else if (GET_CODE (operands[0]) == MEM)
2175 if (REG_P (operands[1]))
2177 else if (CONSTANT_P (operands[1]))
2179 else if (offsettable_memref_p (operands[1]))
2181 else if (GET_CODE (operands[1]) == MEM)
2186 /* Check for the cases that the operand constraints are not
2187 supposed to allow to happen. */
2188 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2190 /* Handle auto decrementing and incrementing loads and stores
2191 specifically, since the structure of the function doesn't work
2192 for them without major modification. Do it better when we learn
2193 this port about the general inc/dec addressing of PA.
2194 (This was written by tege. Chide him if it doesn't work.) */
2196 if (optype0 == MEMOP)
2198 /* We have to output the address syntax ourselves, since print_operand
2199 doesn't deal with the addresses we want to use. Fix this later. */
2201 rtx addr = XEXP (operands[0], 0);
2202 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2204 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2206 operands[0] = XEXP (addr, 0);
2207 gcc_assert (GET_CODE (operands[1]) == REG
2208 && GET_CODE (operands[0]) == REG);
2210 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2212 /* No overlap between high target register and address
2213 register. (We do this in a non-obvious way to
2214 save a register file writeback) */
2215 if (GET_CODE (addr) == POST_INC)
2216 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2217 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2219 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2221 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2223 operands[0] = XEXP (addr, 0);
2224 gcc_assert (GET_CODE (operands[1]) == REG
2225 && GET_CODE (operands[0]) == REG);
2227 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2228 /* No overlap between high target register and address
2229 register. (We do this in a non-obvious way to save a
2230 register file writeback) */
2231 if (GET_CODE (addr) == PRE_INC)
2232 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2233 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2236 if (optype1 == MEMOP)
2238 /* We have to output the address syntax ourselves, since print_operand
2239 doesn't deal with the addresses we want to use. Fix this later. */
2241 rtx addr = XEXP (operands[1], 0);
2242 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2244 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2246 operands[1] = XEXP (addr, 0);
2247 gcc_assert (GET_CODE (operands[0]) == REG
2248 && GET_CODE (operands[1]) == REG);
2250 if (!reg_overlap_mentioned_p (high_reg, addr))
2252 /* No overlap between high target register and address
2253 register. (We do this in a non-obvious way to
2254 save a register file writeback) */
2255 if (GET_CODE (addr) == POST_INC)
2256 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2257 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2261 /* This is an undefined situation. We should load into the
2262 address register *and* update that register. Probably
2263 we don't need to handle this at all. */
2264 if (GET_CODE (addr) == POST_INC)
2265 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2266 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2269 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2271 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2273 operands[1] = XEXP (addr, 0);
2274 gcc_assert (GET_CODE (operands[0]) == REG
2275 && GET_CODE (operands[1]) == REG);
2277 if (!reg_overlap_mentioned_p (high_reg, addr))
2279 /* No overlap between high target register and address
2280 register. (We do this in a non-obvious way to
2281 save a register file writeback) */
2282 if (GET_CODE (addr) == PRE_INC)
2283 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2284 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2288 /* This is an undefined situation. We should load into the
2289 address register *and* update that register. Probably
2290 we don't need to handle this at all. */
2291 if (GET_CODE (addr) == PRE_INC)
2292 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2293 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2296 else if (GET_CODE (addr) == PLUS
2297 && GET_CODE (XEXP (addr, 0)) == MULT)
2299 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2301 if (!reg_overlap_mentioned_p (high_reg, addr))
2305 xoperands[0] = high_reg;
2306 xoperands[1] = XEXP (addr, 1);
2307 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2308 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2309 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2311 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2317 xoperands[0] = high_reg;
2318 xoperands[1] = XEXP (addr, 1);
2319 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2320 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2321 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2323 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2328 /* If an operand is an unoffsettable memory ref, find a register
2329 we can increment temporarily to make it refer to the second word. */
2331 if (optype0 == MEMOP)
2332 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2334 if (optype1 == MEMOP)
2335 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2337 /* Ok, we can do one word at a time.
2338 Normally we do the low-numbered word first.
2340 In either case, set up in LATEHALF the operands to use
2341 for the high-numbered word and in some cases alter the
2342 operands in OPERANDS to be suitable for the low-numbered word. */
2344 if (optype0 == REGOP)
2345 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2346 else if (optype0 == OFFSOP)
2347 latehalf[0] = adjust_address (operands[0], SImode, 4);
2349 latehalf[0] = operands[0];
2351 if (optype1 == REGOP)
2352 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2353 else if (optype1 == OFFSOP)
2354 latehalf[1] = adjust_address (operands[1], SImode, 4);
2355 else if (optype1 == CNSTOP)
2356 split_double (operands[1], &operands[1], &latehalf[1]);
2358 latehalf[1] = operands[1];
2360 /* If the first move would clobber the source of the second one,
2361 do them in the other order.
2363 This can happen in two cases:
2365 mem -> register where the first half of the destination register
2366 is the same register used in the memory's address. Reload
2367 can create such insns.
2369 mem in this case will be either register indirect or register
2370 indirect plus a valid offset.
2372 register -> register move where REGNO(dst) == REGNO(src + 1)
2373 someone (Tim/Tege?) claimed this can happen for parameter loads.
2375 Handle mem -> register case first. */
2376 if (optype0 == REGOP
2377 && (optype1 == MEMOP || optype1 == OFFSOP)
2378 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2381 /* Do the late half first. */
2383 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2384 output_asm_insn (singlemove_string (latehalf), latehalf);
2388 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2389 return singlemove_string (operands);
2392 /* Now handle register -> register case. */
2393 if (optype0 == REGOP && optype1 == REGOP
2394 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2396 output_asm_insn (singlemove_string (latehalf), latehalf);
2397 return singlemove_string (operands);
2400 /* Normal case: do the two words, low-numbered first. */
2402 output_asm_insn (singlemove_string (operands), operands);
2404 /* Make any unoffsettable addresses point at high-numbered word. */
2406 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2408 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2411 output_asm_insn (singlemove_string (latehalf), latehalf);
2413 /* Undo the adds we just did. */
2415 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2417 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2423 output_fp_move_double (rtx *operands)
2425 if (FP_REG_P (operands[0]))
2427 if (FP_REG_P (operands[1])
2428 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2429 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2431 output_asm_insn ("fldd%F1 %1,%0", operands);
2433 else if (FP_REG_P (operands[1]))
2435 output_asm_insn ("fstd%F0 %1,%0", operands);
2441 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2443 /* This is a pain. You have to be prepared to deal with an
2444 arbitrary address here including pre/post increment/decrement.
2446 so avoid this in the MD. */
2447 gcc_assert (GET_CODE (operands[0]) == REG);
2449 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2450 xoperands[0] = operands[0];
2451 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2456 /* Return a REG that occurs in ADDR with coefficient 1.
2457 ADDR can be effectively incremented by incrementing REG. */
2460 find_addr_reg (rtx addr)
2462 while (GET_CODE (addr) == PLUS)
2464 if (GET_CODE (XEXP (addr, 0)) == REG)
2465 addr = XEXP (addr, 0);
2466 else if (GET_CODE (XEXP (addr, 1)) == REG)
2467 addr = XEXP (addr, 1);
2468 else if (CONSTANT_P (XEXP (addr, 0)))
2469 addr = XEXP (addr, 1);
2470 else if (CONSTANT_P (XEXP (addr, 1)))
2471 addr = XEXP (addr, 0);
2475 gcc_assert (GET_CODE (addr) == REG);
2479 /* Emit code to perform a block move.
2481 OPERANDS[0] is the destination pointer as a REG, clobbered.
2482 OPERANDS[1] is the source pointer as a REG, clobbered.
2483 OPERANDS[2] is a register for temporary storage.
2484 OPERANDS[3] is a register for temporary storage.
2485 OPERANDS[4] is the size as a CONST_INT
2486 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2487 OPERANDS[6] is another temporary register. */
2490 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2492 int align = INTVAL (operands[5]);
2493 unsigned long n_bytes = INTVAL (operands[4]);
2495 /* We can't move more than a word at a time because the PA
2496 has no longer integer move insns. (Could use fp mem ops?) */
2497 if (align > (TARGET_64BIT ? 8 : 4))
2498 align = (TARGET_64BIT ? 8 : 4);
2500 /* Note that we know each loop below will execute at least twice
2501 (else we would have open-coded the copy). */
2505 /* Pre-adjust the loop counter. */
2506 operands[4] = GEN_INT (n_bytes - 16);
2507 output_asm_insn ("ldi %4,%2", operands);
2510 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2511 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2512 output_asm_insn ("std,ma %3,8(%0)", operands);
2513 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2514 output_asm_insn ("std,ma %6,8(%0)", operands);
2516 /* Handle the residual. There could be up to 7 bytes of
2517 residual to copy! */
2518 if (n_bytes % 16 != 0)
2520 operands[4] = GEN_INT (n_bytes % 8);
2521 if (n_bytes % 16 >= 8)
2522 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2523 if (n_bytes % 8 != 0)
2524 output_asm_insn ("ldd 0(%1),%6", operands);
2525 if (n_bytes % 16 >= 8)
2526 output_asm_insn ("std,ma %3,8(%0)", operands);
2527 if (n_bytes % 8 != 0)
2528 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2533 /* Pre-adjust the loop counter. */
2534 operands[4] = GEN_INT (n_bytes - 8);
2535 output_asm_insn ("ldi %4,%2", operands);
2538 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2539 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2540 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2541 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2542 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2544 /* Handle the residual. There could be up to 7 bytes of
2545 residual to copy! */
2546 if (n_bytes % 8 != 0)
2548 operands[4] = GEN_INT (n_bytes % 4);
2549 if (n_bytes % 8 >= 4)
2550 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2551 if (n_bytes % 4 != 0)
2552 output_asm_insn ("ldw 0(%1),%6", operands);
2553 if (n_bytes % 8 >= 4)
2554 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2555 if (n_bytes % 4 != 0)
2556 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2561 /* Pre-adjust the loop counter. */
2562 operands[4] = GEN_INT (n_bytes - 4);
2563 output_asm_insn ("ldi %4,%2", operands);
2566 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2567 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2568 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2569 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2570 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2572 /* Handle the residual. */
2573 if (n_bytes % 4 != 0)
2575 if (n_bytes % 4 >= 2)
2576 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2577 if (n_bytes % 2 != 0)
2578 output_asm_insn ("ldb 0(%1),%6", operands);
2579 if (n_bytes % 4 >= 2)
2580 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2581 if (n_bytes % 2 != 0)
2582 output_asm_insn ("stb %6,0(%0)", operands);
2587 /* Pre-adjust the loop counter. */
2588 operands[4] = GEN_INT (n_bytes - 2);
2589 output_asm_insn ("ldi %4,%2", operands);
2592 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2593 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2594 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2595 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2596 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2598 /* Handle the residual. */
2599 if (n_bytes % 2 != 0)
2601 output_asm_insn ("ldb 0(%1),%3", operands);
2602 output_asm_insn ("stb %3,0(%0)", operands);
2611 /* Count the number of insns necessary to handle this block move.
2613 Basic structure is the same as emit_block_move, except that we
2614 count insns rather than emit them. */
2617 compute_movmem_length (rtx insn)
2619 rtx pat = PATTERN (insn);
2620 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2621 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2622 unsigned int n_insns = 0;
2624 /* We can't move more than four bytes at a time because the PA
2625 has no longer integer move insns. (Could use fp mem ops?) */
2626 if (align > (TARGET_64BIT ? 8 : 4))
2627 align = (TARGET_64BIT ? 8 : 4);
2629 /* The basic copying loop. */
2633 if (n_bytes % (2 * align) != 0)
2635 if ((n_bytes % (2 * align)) >= align)
2638 if ((n_bytes % align) != 0)
2642 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2646 /* Emit code to perform a block clear.
2648 OPERANDS[0] is the destination pointer as a REG, clobbered.
2649 OPERANDS[1] is a register for temporary storage.
2650 OPERANDS[2] is the size as a CONST_INT
2651 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2654 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2656 int align = INTVAL (operands[3]);
2657 unsigned long n_bytes = INTVAL (operands[2]);
2659 /* We can't clear more than a word at a time because the PA
2660 has no longer integer move insns. */
2661 if (align > (TARGET_64BIT ? 8 : 4))
2662 align = (TARGET_64BIT ? 8 : 4);
2664 /* Note that we know each loop below will execute at least twice
2665 (else we would have open-coded the copy). */
2669 /* Pre-adjust the loop counter. */
2670 operands[2] = GEN_INT (n_bytes - 16);
2671 output_asm_insn ("ldi %2,%1", operands);
2674 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2675 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2676 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2678 /* Handle the residual. There could be up to 7 bytes of
2679 residual to copy! */
2680 if (n_bytes % 16 != 0)
2682 operands[2] = GEN_INT (n_bytes % 8);
2683 if (n_bytes % 16 >= 8)
2684 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2685 if (n_bytes % 8 != 0)
2686 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2691 /* Pre-adjust the loop counter. */
2692 operands[2] = GEN_INT (n_bytes - 8);
2693 output_asm_insn ("ldi %2,%1", operands);
2696 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2697 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2698 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2700 /* Handle the residual. There could be up to 7 bytes of
2701 residual to copy! */
2702 if (n_bytes % 8 != 0)
2704 operands[2] = GEN_INT (n_bytes % 4);
2705 if (n_bytes % 8 >= 4)
2706 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2707 if (n_bytes % 4 != 0)
2708 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2713 /* Pre-adjust the loop counter. */
2714 operands[2] = GEN_INT (n_bytes - 4);
2715 output_asm_insn ("ldi %2,%1", operands);
2718 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2719 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2720 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2722 /* Handle the residual. */
2723 if (n_bytes % 4 != 0)
2725 if (n_bytes % 4 >= 2)
2726 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2727 if (n_bytes % 2 != 0)
2728 output_asm_insn ("stb %%r0,0(%0)", operands);
2733 /* Pre-adjust the loop counter. */
2734 operands[2] = GEN_INT (n_bytes - 2);
2735 output_asm_insn ("ldi %2,%1", operands);
2738 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2739 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2740 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2742 /* Handle the residual. */
2743 if (n_bytes % 2 != 0)
2744 output_asm_insn ("stb %%r0,0(%0)", operands);
2753 /* Count the number of insns necessary to handle this block move.
2755 Basic structure is the same as emit_block_move, except that we
2756 count insns rather than emit them. */
2759 compute_clrmem_length (rtx insn)
2761 rtx pat = PATTERN (insn);
2762 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2763 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2764 unsigned int n_insns = 0;
2766 /* We can't clear more than a word at a time because the PA
2767 has no longer integer move insns. */
2768 if (align > (TARGET_64BIT ? 8 : 4))
2769 align = (TARGET_64BIT ? 8 : 4);
2771 /* The basic loop. */
2775 if (n_bytes % (2 * align) != 0)
2777 if ((n_bytes % (2 * align)) >= align)
2780 if ((n_bytes % align) != 0)
2784 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2790 output_and (rtx *operands)
2792 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2794 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2795 int ls0, ls1, ms0, p, len;
2797 for (ls0 = 0; ls0 < 32; ls0++)
2798 if ((mask & (1 << ls0)) == 0)
2801 for (ls1 = ls0; ls1 < 32; ls1++)
2802 if ((mask & (1 << ls1)) != 0)
2805 for (ms0 = ls1; ms0 < 32; ms0++)
2806 if ((mask & (1 << ms0)) == 0)
2809 gcc_assert (ms0 == 32);
2817 operands[2] = GEN_INT (len);
2818 return "{extru|extrw,u} %1,31,%2,%0";
2822 /* We could use this `depi' for the case above as well, but `depi'
2823 requires one more register file access than an `extru'. */
2828 operands[2] = GEN_INT (p);
2829 operands[3] = GEN_INT (len);
2830 return "{depi|depwi} 0,%2,%3,%0";
2834 return "and %1,%2,%0";
2837 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2838 storing the result in operands[0]. */
2840 output_64bit_and (rtx *operands)
2842 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2844 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2845 int ls0, ls1, ms0, p, len;
2847 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2848 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2851 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2852 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2855 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2856 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2859 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
2861 if (ls1 == HOST_BITS_PER_WIDE_INT)
2867 operands[2] = GEN_INT (len);
2868 return "extrd,u %1,63,%2,%0";
2872 /* We could use this `depi' for the case above as well, but `depi'
2873 requires one more register file access than an `extru'. */
2878 operands[2] = GEN_INT (p);
2879 operands[3] = GEN_INT (len);
2880 return "depdi 0,%2,%3,%0";
2884 return "and %1,%2,%0";
2888 output_ior (rtx *operands)
2890 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2891 int bs0, bs1, p, len;
2893 if (INTVAL (operands[2]) == 0)
2894 return "copy %1,%0";
2896 for (bs0 = 0; bs0 < 32; bs0++)
2897 if ((mask & (1 << bs0)) != 0)
2900 for (bs1 = bs0; bs1 < 32; bs1++)
2901 if ((mask & (1 << bs1)) == 0)
2904 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2909 operands[2] = GEN_INT (p);
2910 operands[3] = GEN_INT (len);
2911 return "{depi|depwi} -1,%2,%3,%0";
2914 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2915 storing the result in operands[0]. */
2917 output_64bit_ior (rtx *operands)
2919 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2920 int bs0, bs1, p, len;
2922 if (INTVAL (operands[2]) == 0)
2923 return "copy %1,%0";
2925 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2926 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2929 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2930 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2933 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
2934 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2939 operands[2] = GEN_INT (p);
2940 operands[3] = GEN_INT (len);
2941 return "depdi -1,%2,%3,%0";
2944 /* Target hook for assembling integer objects. This code handles
2945 aligned SI and DI integers specially since function references
2946 must be preceded by P%. */
2949 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
2951 if (size == UNITS_PER_WORD
2953 && function_label_operand (x, VOIDmode))
2955 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2956 output_addr_const (asm_out_file, x);
2957 fputc ('\n', asm_out_file);
2960 return default_assemble_integer (x, size, aligned_p);
2963 /* Output an ascii string. */
2965 output_ascii (FILE *file, const char *p, int size)
2969 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2971 /* The HP assembler can only take strings of 256 characters at one
2972 time. This is a limitation on input line length, *not* the
2973 length of the string. Sigh. Even worse, it seems that the
2974 restriction is in number of input characters (see \xnn &
2975 \whatever). So we have to do this very carefully. */
2977 fputs ("\t.STRING \"", file);
2980 for (i = 0; i < size; i += 4)
2984 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2986 register unsigned int c = (unsigned char) p[i + io];
2988 if (c == '\"' || c == '\\')
2989 partial_output[co++] = '\\';
2990 if (c >= ' ' && c < 0177)
2991 partial_output[co++] = c;
2995 partial_output[co++] = '\\';
2996 partial_output[co++] = 'x';
2997 hexd = c / 16 - 0 + '0';
2999 hexd -= '9' - 'a' + 1;
3000 partial_output[co++] = hexd;
3001 hexd = c % 16 - 0 + '0';
3003 hexd -= '9' - 'a' + 1;
3004 partial_output[co++] = hexd;
3007 if (chars_output + co > 243)
3009 fputs ("\"\n\t.STRING \"", file);
3012 fwrite (partial_output, 1, (size_t) co, file);
3016 fputs ("\"\n", file);
3019 /* Try to rewrite floating point comparisons & branches to avoid
3020 useless add,tr insns.
3022 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3023 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3024 first attempt to remove useless add,tr insns. It is zero
3025 for the second pass as reorg sometimes leaves bogus REG_DEAD
3028 When CHECK_NOTES is zero we can only eliminate add,tr insns
3029 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3032 remove_useless_addtr_insns (int check_notes)
3035 static int pass = 0;
3037 /* This is fairly cheap, so always run it when optimizing. */
3041 int fbranch_count = 0;
3043 /* Walk all the insns in this function looking for fcmp & fbranch
3044 instructions. Keep track of how many of each we find. */
3045 for (insn = get_insns (); insn; insn = next_insn (insn))
3049 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3050 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3053 tmp = PATTERN (insn);
3055 /* It must be a set. */
3056 if (GET_CODE (tmp) != SET)
3059 /* If the destination is CCFP, then we've found an fcmp insn. */
3060 tmp = SET_DEST (tmp);
3061 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3067 tmp = PATTERN (insn);
3068 /* If this is an fbranch instruction, bump the fbranch counter. */
3069 if (GET_CODE (tmp) == SET
3070 && SET_DEST (tmp) == pc_rtx
3071 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3072 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3073 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3074 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3082 /* Find all floating point compare + branch insns. If possible,
3083 reverse the comparison & the branch to avoid add,tr insns. */
3084 for (insn = get_insns (); insn; insn = next_insn (insn))
3088 /* Ignore anything that isn't an INSN. */
3089 if (GET_CODE (insn) != INSN)
3092 tmp = PATTERN (insn);
3094 /* It must be a set. */
3095 if (GET_CODE (tmp) != SET)
3098 /* The destination must be CCFP, which is register zero. */
3099 tmp = SET_DEST (tmp);
3100 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3103 /* INSN should be a set of CCFP.
3105 See if the result of this insn is used in a reversed FP
3106 conditional branch. If so, reverse our condition and
3107 the branch. Doing so avoids useless add,tr insns. */
3108 next = next_insn (insn);
3111 /* Jumps, calls and labels stop our search. */
3112 if (GET_CODE (next) == JUMP_INSN
3113 || GET_CODE (next) == CALL_INSN
3114 || GET_CODE (next) == CODE_LABEL)
3117 /* As does another fcmp insn. */
3118 if (GET_CODE (next) == INSN
3119 && GET_CODE (PATTERN (next)) == SET
3120 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3121 && REGNO (SET_DEST (PATTERN (next))) == 0)
3124 next = next_insn (next);
3127 /* Is NEXT_INSN a branch? */
3129 && GET_CODE (next) == JUMP_INSN)
3131 rtx pattern = PATTERN (next);
3133 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3134 and CCFP dies, then reverse our conditional and the branch
3135 to avoid the add,tr. */
3136 if (GET_CODE (pattern) == SET
3137 && SET_DEST (pattern) == pc_rtx
3138 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3139 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3140 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3141 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3142 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3143 && (fcmp_count == fbranch_count
3145 && find_regno_note (next, REG_DEAD, 0))))
3147 /* Reverse the branch. */
3148 tmp = XEXP (SET_SRC (pattern), 1);
3149 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3150 XEXP (SET_SRC (pattern), 2) = tmp;
3151 INSN_CODE (next) = -1;
3153 /* Reverse our condition. */
3154 tmp = PATTERN (insn);
3155 PUT_CODE (XEXP (tmp, 1),
3156 (reverse_condition_maybe_unordered
3157 (GET_CODE (XEXP (tmp, 1)))));
3167 /* You may have trouble believing this, but this is the 32 bit HP-PA
3172 Variable arguments (optional; any number may be allocated)
3174 SP-(4*(N+9)) arg word N
3179 Fixed arguments (must be allocated; may remain unused)
3188 SP-32 External Data Pointer (DP)
3190 SP-24 External/stub RP (RP')
3194 SP-8 Calling Stub RP (RP'')
3199 SP-0 Stack Pointer (points to next available address)
3203 /* This function saves registers as follows. Registers marked with ' are
3204 this function's registers (as opposed to the previous function's).
3205 If a frame_pointer isn't needed, r4 is saved as a general register;
3206 the space for the frame pointer is still allocated, though, to keep
3212 SP (FP') Previous FP
3213 SP + 4 Alignment filler (sigh)
3214 SP + 8 Space for locals reserved here.
3218 SP + n All call saved register used.
3222 SP + o All call saved fp registers used.
3226 SP + p (SP') points to next available address.
3230 /* Global variables set by output_function_prologue(). */
3231 /* Size of frame. Need to know this to emit return insns from
3233 static HOST_WIDE_INT actual_fsize, local_fsize;
3234 static int save_fregs;
3236 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3237 Handle case where DISP > 8k by using the add_high_const patterns.
3239 Note in DISP > 8k case, we will leave the high part of the address
3240 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3243 store_reg (int reg, HOST_WIDE_INT disp, int base)
3245 rtx insn, dest, src, basereg;
3247 src = gen_rtx_REG (word_mode, reg);
3248 basereg = gen_rtx_REG (Pmode, base);
3249 if (VAL_14_BITS_P (disp))
3251 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3252 insn = emit_move_insn (dest, src);
3254 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3256 rtx delta = GEN_INT (disp);
3257 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3259 emit_move_insn (tmpreg, delta);
3260 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3261 dest = gen_rtx_MEM (word_mode, tmpreg);
3262 insn = emit_move_insn (dest, src);
3266 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3267 gen_rtx_SET (VOIDmode,
3268 gen_rtx_MEM (word_mode,
3269 gen_rtx_PLUS (word_mode, basereg,
3277 rtx delta = GEN_INT (disp);
3278 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3279 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3281 emit_move_insn (tmpreg, high);
3282 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3283 insn = emit_move_insn (dest, src);
3287 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3288 gen_rtx_SET (VOIDmode,
3289 gen_rtx_MEM (word_mode,
3290 gen_rtx_PLUS (word_mode, basereg,
3298 RTX_FRAME_RELATED_P (insn) = 1;
3301 /* Emit RTL to store REG at the memory location specified by BASE and then
3302 add MOD to BASE. MOD must be <= 8k. */
3305 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3307 rtx insn, basereg, srcreg, delta;
3309 gcc_assert (VAL_14_BITS_P (mod));
3311 basereg = gen_rtx_REG (Pmode, base);
3312 srcreg = gen_rtx_REG (word_mode, reg);
3313 delta = GEN_INT (mod);
3315 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3318 RTX_FRAME_RELATED_P (insn) = 1;
3320 /* RTX_FRAME_RELATED_P must be set on each frame related set
3321 in a parallel with more than one element. Don't set
3322 RTX_FRAME_RELATED_P in the first set if reg is temporary
3323 register 1. The effect of this operation is recorded in
3324 the initial copy. */
3327 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3328 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3332 /* The first element of a PARALLEL is always processed if it is
3333 a SET. Thus, we need an expression list for this case. */
3335 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3336 gen_rtx_SET (VOIDmode, basereg,
3337 gen_rtx_PLUS (word_mode, basereg, delta)),
3343 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3344 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3345 whether to add a frame note or not.
3347 In the DISP > 8k case, we leave the high part of the address in %r1.
3348 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3351 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3355 if (VAL_14_BITS_P (disp))
3357 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3358 plus_constant (gen_rtx_REG (Pmode, base), disp));
3360 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3362 rtx basereg = gen_rtx_REG (Pmode, base);
3363 rtx delta = GEN_INT (disp);
3364 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3366 emit_move_insn (tmpreg, delta);
3367 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3368 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3372 rtx basereg = gen_rtx_REG (Pmode, base);
3373 rtx delta = GEN_INT (disp);
3374 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3376 emit_move_insn (tmpreg,
3377 gen_rtx_PLUS (Pmode, basereg,
3378 gen_rtx_HIGH (Pmode, delta)));
3379 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3380 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3383 if (DO_FRAME_NOTES && note)
3384 RTX_FRAME_RELATED_P (insn) = 1;
3388 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3393 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3394 be consistent with the rounding and size calculation done here.
3395 Change them at the same time. */
3397 /* We do our own stack alignment. First, round the size of the
3398 stack locals up to a word boundary. */
3399 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3401 /* Space for previous frame pointer + filler. If any frame is
3402 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3403 waste some space here for the sake of HP compatibility. The
3404 first slot is only used when the frame pointer is needed. */
3405 if (size || frame_pointer_needed)
3406 size += STARTING_FRAME_OFFSET;
3408 /* If the current function calls __builtin_eh_return, then we need
3409 to allocate stack space for registers that will hold data for
3410 the exception handler. */
3411 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3415 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3417 size += i * UNITS_PER_WORD;
3420 /* Account for space used by the callee general register saves. */
3421 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3422 if (regs_ever_live[i])
3423 size += UNITS_PER_WORD;
3425 /* Account for space used by the callee floating point register saves. */
3426 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3427 if (regs_ever_live[i]
3428 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3432 /* We always save both halves of the FP register, so always
3433 increment the frame size by 8 bytes. */
3437 /* If any of the floating registers are saved, account for the
3438 alignment needed for the floating point register save block. */
3441 size = (size + 7) & ~7;
3446 /* The various ABIs include space for the outgoing parameters in the
3447 size of the current function's stack frame. We don't need to align
3448 for the outgoing arguments as their alignment is set by the final
3449 rounding for the frame as a whole. */
3450 size += current_function_outgoing_args_size;
3452 /* Allocate space for the fixed frame marker. This space must be
3453 allocated for any function that makes calls or allocates
3455 if (!current_function_is_leaf || size)
3456 size += TARGET_64BIT ? 48 : 32;
3458 /* Finally, round to the preferred stack boundary. */
3459 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3460 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3463 /* Generate the assembly code for function entry. FILE is a stdio
3464 stream to output the code to. SIZE is an int: how many units of
3465 temporary storage to allocate.
3467 Refer to the array `regs_ever_live' to determine which registers to
3468 save; `regs_ever_live[I]' is nonzero if register number I is ever
3469 used in the function. This function is responsible for knowing
3470 which registers should not be saved even if used. */
3472 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3473 of memory. If any fpu reg is used in the function, we allocate
3474 such a block here, at the bottom of the frame, just in case it's needed.
3476 If this function is a leaf procedure, then we may choose not
3477 to do a "save" insn. The decision about whether or not
3478 to do this is made in regclass.c. */
3481 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3483 /* The function's label and associated .PROC must never be
3484 separated and must be output *after* any profiling declarations
3485 to avoid changing spaces/subspaces within a procedure. */
3486 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3487 fputs ("\t.PROC\n", file);
3489 /* hppa_expand_prologue does the dirty work now. We just need
3490 to output the assembler directives which denote the start
3492 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3493 if (regs_ever_live[2])
3494 fputs (",CALLS,SAVE_RP", file);
3496 fputs (",NO_CALLS", file);
3498 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3499 at the beginning of the frame and that it is used as the frame
3500 pointer for the frame. We do this because our current frame
3501 layout doesn't conform to that specified in the the HP runtime
3502 documentation and we need a way to indicate to programs such as
3503 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3504 isn't used by HP compilers but is supported by the assembler.
3505 However, SAVE_SP is supposed to indicate that the previous stack
3506 pointer has been saved in the frame marker. */
3507 if (frame_pointer_needed)
3508 fputs (",SAVE_SP", file);
3510 /* Pass on information about the number of callee register saves
3511 performed in the prologue.
3513 The compiler is supposed to pass the highest register number
3514 saved, the assembler then has to adjust that number before
3515 entering it into the unwind descriptor (to account for any
3516 caller saved registers with lower register numbers than the
3517 first callee saved register). */
3519 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3522 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3524 fputs ("\n\t.ENTRY\n", file);
3526 remove_useless_addtr_insns (0);
3530 hppa_expand_prologue (void)
3532 int merge_sp_adjust_with_store = 0;
3533 HOST_WIDE_INT size = get_frame_size ();
3534 HOST_WIDE_INT offset;
3542 /* Compute total size for frame pointer, filler, locals and rounding to
3543 the next word boundary. Similar code appears in compute_frame_size
3544 and must be changed in tandem with this code. */
3545 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3546 if (local_fsize || frame_pointer_needed)
3547 local_fsize += STARTING_FRAME_OFFSET;
3549 actual_fsize = compute_frame_size (size, &save_fregs);
3551 /* Compute a few things we will use often. */
3552 tmpreg = gen_rtx_REG (word_mode, 1);
3554 /* Save RP first. The calling conventions manual states RP will
3555 always be stored into the caller's frame at sp - 20 or sp - 16
3556 depending on which ABI is in use. */
3557 if (regs_ever_live[2] || current_function_calls_eh_return)
3558 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3560 /* Allocate the local frame and set up the frame pointer if needed. */
3561 if (actual_fsize != 0)
3563 if (frame_pointer_needed)
3565 /* Copy the old frame pointer temporarily into %r1. Set up the
3566 new stack pointer, then store away the saved old frame pointer
3567 into the stack at sp and at the same time update the stack
3568 pointer by actual_fsize bytes. Two versions, first
3569 handles small (<8k) frames. The second handles large (>=8k)
3571 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3574 /* We need to record the frame pointer save here since the
3575 new frame pointer is set in the following insn. */
3576 RTX_FRAME_RELATED_P (insn) = 1;
3578 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3579 gen_rtx_SET (VOIDmode,
3580 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3585 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3587 RTX_FRAME_RELATED_P (insn) = 1;
3589 if (VAL_14_BITS_P (actual_fsize))
3590 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3593 /* It is incorrect to store the saved frame pointer at *sp,
3594 then increment sp (writes beyond the current stack boundary).
3596 So instead use stwm to store at *sp and post-increment the
3597 stack pointer as an atomic operation. Then increment sp to
3598 finish allocating the new frame. */
3599 HOST_WIDE_INT adjust1 = 8192 - 64;
3600 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3602 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3603 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3607 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3608 we need to store the previous stack pointer (frame pointer)
3609 into the frame marker on targets that use the HP unwind
3610 library. This allows the HP unwind library to be used to
3611 unwind GCC frames. However, we are not fully compatible
3612 with the HP library because our frame layout differs from
3613 that specified in the HP runtime specification.
3615 We don't want a frame note on this instruction as the frame
3616 marker moves during dynamic stack allocation.
3618 This instruction also serves as a blockage to prevent
3619 register spills from being scheduled before the stack
3620 pointer is raised. This is necessary as we store
3621 registers using the frame pointer as a base register,
3622 and the frame pointer is set before sp is raised. */
3623 if (TARGET_HPUX_UNWIND_LIBRARY)
3625 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3626 GEN_INT (TARGET_64BIT ? -8 : -4));
3628 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3632 emit_insn (gen_blockage ());
3634 /* no frame pointer needed. */
3637 /* In some cases we can perform the first callee register save
3638 and allocating the stack frame at the same time. If so, just
3639 make a note of it and defer allocating the frame until saving
3640 the callee registers. */
3641 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3642 merge_sp_adjust_with_store = 1;
3643 /* Can not optimize. Adjust the stack frame by actual_fsize
3646 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3651 /* Normal register save.
3653 Do not save the frame pointer in the frame_pointer_needed case. It
3654 was done earlier. */
3655 if (frame_pointer_needed)
3657 offset = local_fsize;
3659 /* Saving the EH return data registers in the frame is the simplest
3660 way to get the frame unwind information emitted. We put them
3661 just before the general registers. */
3662 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3664 unsigned int i, regno;
3668 regno = EH_RETURN_DATA_REGNO (i);
3669 if (regno == INVALID_REGNUM)
3672 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3673 offset += UNITS_PER_WORD;
3677 for (i = 18; i >= 4; i--)
3678 if (regs_ever_live[i] && ! call_used_regs[i])
3680 store_reg (i, offset, FRAME_POINTER_REGNUM);
3681 offset += UNITS_PER_WORD;
3684 /* Account for %r3 which is saved in a special place. */
3687 /* No frame pointer needed. */
3690 offset = local_fsize - actual_fsize;
3692 /* Saving the EH return data registers in the frame is the simplest
3693 way to get the frame unwind information emitted. */
3694 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3696 unsigned int i, regno;
3700 regno = EH_RETURN_DATA_REGNO (i);
3701 if (regno == INVALID_REGNUM)
3704 /* If merge_sp_adjust_with_store is nonzero, then we can
3705 optimize the first save. */
3706 if (merge_sp_adjust_with_store)
3708 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3709 merge_sp_adjust_with_store = 0;
3712 store_reg (regno, offset, STACK_POINTER_REGNUM);
3713 offset += UNITS_PER_WORD;
3717 for (i = 18; i >= 3; i--)
3718 if (regs_ever_live[i] && ! call_used_regs[i])
3720 /* If merge_sp_adjust_with_store is nonzero, then we can
3721 optimize the first GR save. */
3722 if (merge_sp_adjust_with_store)
3724 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3725 merge_sp_adjust_with_store = 0;
3728 store_reg (i, offset, STACK_POINTER_REGNUM);
3729 offset += UNITS_PER_WORD;
3733 /* If we wanted to merge the SP adjustment with a GR save, but we never
3734 did any GR saves, then just emit the adjustment here. */
3735 if (merge_sp_adjust_with_store)
3736 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3740 /* The hppa calling conventions say that %r19, the pic offset
3741 register, is saved at sp - 32 (in this function's frame)
3742 when generating PIC code. FIXME: What is the correct thing
3743 to do for functions which make no calls and allocate no
3744 frame? Do we need to allocate a frame, or can we just omit
3745 the save? For now we'll just omit the save.
3747 We don't want a note on this insn as the frame marker can
3748 move if there is a dynamic stack allocation. */
3749 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3751 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3753 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3757 /* Align pointer properly (doubleword boundary). */
3758 offset = (offset + 7) & ~7;
3760 /* Floating point register store. */
3765 /* First get the frame or stack pointer to the start of the FP register
3767 if (frame_pointer_needed)
3769 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3770 base = frame_pointer_rtx;
3774 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3775 base = stack_pointer_rtx;
3778 /* Now actually save the FP registers. */
3779 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3781 if (regs_ever_live[i]
3782 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3784 rtx addr, insn, reg;
3785 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3786 reg = gen_rtx_REG (DFmode, i);
3787 insn = emit_move_insn (addr, reg);
3790 RTX_FRAME_RELATED_P (insn) = 1;
3793 rtx mem = gen_rtx_MEM (DFmode,
3794 plus_constant (base, offset));
3796 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3797 gen_rtx_SET (VOIDmode, mem, reg),
3802 rtx meml = gen_rtx_MEM (SFmode,
3803 plus_constant (base, offset));
3804 rtx memr = gen_rtx_MEM (SFmode,
3805 plus_constant (base, offset + 4));
3806 rtx regl = gen_rtx_REG (SFmode, i);
3807 rtx regr = gen_rtx_REG (SFmode, i + 1);
3808 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3809 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3812 RTX_FRAME_RELATED_P (setl) = 1;
3813 RTX_FRAME_RELATED_P (setr) = 1;
3814 vec = gen_rtvec (2, setl, setr);
3816 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3817 gen_rtx_SEQUENCE (VOIDmode, vec),
3821 offset += GET_MODE_SIZE (DFmode);
3828 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3829 Handle case where DISP > 8k by using the add_high_const patterns. */
3832 load_reg (int reg, HOST_WIDE_INT disp, int base)
3834 rtx dest = gen_rtx_REG (word_mode, reg);
3835 rtx basereg = gen_rtx_REG (Pmode, base);
3838 if (VAL_14_BITS_P (disp))
3839 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3840 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3842 rtx delta = GEN_INT (disp);
3843 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3845 emit_move_insn (tmpreg, delta);
3846 if (TARGET_DISABLE_INDEXING)
3848 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3849 src = gen_rtx_MEM (word_mode, tmpreg);
3852 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3856 rtx delta = GEN_INT (disp);
3857 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3858 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3860 emit_move_insn (tmpreg, high);
3861 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3864 emit_move_insn (dest, src);
3867 /* Update the total code bytes output to the text section. */
3870 update_total_code_bytes (int nbytes)
3872 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3873 && !IN_NAMED_SECTION_P (cfun->decl))
3875 if (INSN_ADDRESSES_SET_P ())
3877 unsigned long old_total = total_code_bytes;
3879 total_code_bytes += nbytes;
3881 /* Be prepared to handle overflows. */
3882 if (old_total > total_code_bytes)
3883 total_code_bytes = -1;
3886 total_code_bytes = -1;
3890 /* This function generates the assembly code for function exit.
3891 Args are as for output_function_prologue ().
3893 The function epilogue should not depend on the current stack
3894 pointer! It should use the frame pointer only. This is mandatory
3895 because of alloca; we also take advantage of it to omit stack
3896 adjustments before returning. */
3899 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3901 rtx insn = get_last_insn ();
3905 /* hppa_expand_epilogue does the dirty work now. We just need
3906 to output the assembler directives which denote the end
3909 To make debuggers happy, emit a nop if the epilogue was completely
3910 eliminated due to a volatile call as the last insn in the
3911 current function. That way the return address (in %r2) will
3912 always point to a valid instruction in the current function. */
3914 /* Get the last real insn. */
3915 if (GET_CODE (insn) == NOTE)
3916 insn = prev_real_insn (insn);
3918 /* If it is a sequence, then look inside. */
3919 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3920 insn = XVECEXP (PATTERN (insn), 0, 0);
3922 /* If insn is a CALL_INSN, then it must be a call to a volatile
3923 function (otherwise there would be epilogue insns). */
3924 if (insn && GET_CODE (insn) == CALL_INSN)
3926 fputs ("\tnop\n", file);
3930 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3932 if (TARGET_SOM && TARGET_GAS)
3934 /* We done with this subspace except possibly for some additional
3935 debug information. Forget that we are in this subspace to ensure
3936 that the next function is output in its own subspace. */
3940 if (INSN_ADDRESSES_SET_P ())
3942 insn = get_last_nonnote_insn ();
3943 last_address += INSN_ADDRESSES (INSN_UID (insn));
3945 last_address += insn_default_length (insn);
3946 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
3947 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
3950 /* Finally, update the total number of code bytes output so far. */
3951 update_total_code_bytes (last_address);
3955 hppa_expand_epilogue (void)
3958 HOST_WIDE_INT offset;
3959 HOST_WIDE_INT ret_off = 0;
3961 int merge_sp_adjust_with_load = 0;
3963 /* We will use this often. */
3964 tmpreg = gen_rtx_REG (word_mode, 1);
3966 /* Try to restore RP early to avoid load/use interlocks when
3967 RP gets used in the return (bv) instruction. This appears to still
3968 be necessary even when we schedule the prologue and epilogue. */
3969 if (regs_ever_live [2] || current_function_calls_eh_return)
3971 ret_off = TARGET_64BIT ? -16 : -20;
3972 if (frame_pointer_needed)
3974 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3979 /* No frame pointer, and stack is smaller than 8k. */
3980 if (VAL_14_BITS_P (ret_off - actual_fsize))
3982 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3988 /* General register restores. */
3989 if (frame_pointer_needed)
3991 offset = local_fsize;
3993 /* If the current function calls __builtin_eh_return, then we need
3994 to restore the saved EH data registers. */
3995 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3997 unsigned int i, regno;
4001 regno = EH_RETURN_DATA_REGNO (i);
4002 if (regno == INVALID_REGNUM)
4005 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4006 offset += UNITS_PER_WORD;
4010 for (i = 18; i >= 4; i--)
4011 if (regs_ever_live[i] && ! call_used_regs[i])
4013 load_reg (i, offset, FRAME_POINTER_REGNUM);
4014 offset += UNITS_PER_WORD;
4019 offset = local_fsize - actual_fsize;
4021 /* If the current function calls __builtin_eh_return, then we need
4022 to restore the saved EH data registers. */
4023 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4025 unsigned int i, regno;
4029 regno = EH_RETURN_DATA_REGNO (i);
4030 if (regno == INVALID_REGNUM)
4033 /* Only for the first load.
4034 merge_sp_adjust_with_load holds the register load
4035 with which we will merge the sp adjustment. */
4036 if (merge_sp_adjust_with_load == 0
4038 && VAL_14_BITS_P (-actual_fsize))
4039 merge_sp_adjust_with_load = regno;
4041 load_reg (regno, offset, STACK_POINTER_REGNUM);
4042 offset += UNITS_PER_WORD;
4046 for (i = 18; i >= 3; i--)
4048 if (regs_ever_live[i] && ! call_used_regs[i])
4050 /* Only for the first load.
4051 merge_sp_adjust_with_load holds the register load
4052 with which we will merge the sp adjustment. */
4053 if (merge_sp_adjust_with_load == 0
4055 && VAL_14_BITS_P (-actual_fsize))
4056 merge_sp_adjust_with_load = i;
4058 load_reg (i, offset, STACK_POINTER_REGNUM);
4059 offset += UNITS_PER_WORD;
4064 /* Align pointer properly (doubleword boundary). */
4065 offset = (offset + 7) & ~7;
4067 /* FP register restores. */
4070 /* Adjust the register to index off of. */
4071 if (frame_pointer_needed)
4072 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4074 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4076 /* Actually do the restores now. */
4077 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4078 if (regs_ever_live[i]
4079 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4081 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4082 rtx dest = gen_rtx_REG (DFmode, i);
4083 emit_move_insn (dest, src);
4087 /* Emit a blockage insn here to keep these insns from being moved to
4088 an earlier spot in the epilogue, or into the main instruction stream.
4090 This is necessary as we must not cut the stack back before all the
4091 restores are finished. */
4092 emit_insn (gen_blockage ());
4094 /* Reset stack pointer (and possibly frame pointer). The stack
4095 pointer is initially set to fp + 64 to avoid a race condition. */
4096 if (frame_pointer_needed)
4098 rtx delta = GEN_INT (-64);
4100 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4101 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4103 /* If we were deferring a callee register restore, do it now. */
4104 else if (merge_sp_adjust_with_load)
4106 rtx delta = GEN_INT (-actual_fsize);
4107 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4109 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4111 else if (actual_fsize != 0)
4112 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4115 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4116 frame greater than 8k), do so now. */
4118 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4120 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4122 rtx sa = EH_RETURN_STACKADJ_RTX;
4124 emit_insn (gen_blockage ());
4125 emit_insn (TARGET_64BIT
4126 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4127 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4132 hppa_pic_save_rtx (void)
4134 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4138 hppa_profile_hook (int label_no)
4140 /* We use SImode for the address of the function in both 32 and
4141 64-bit code to avoid having to provide DImode versions of the
4142 lcla2 and load_offset_label_address insn patterns. */
4143 rtx reg = gen_reg_rtx (SImode);
4144 rtx label_rtx = gen_label_rtx ();
4145 rtx begin_label_rtx, call_insn;
4146 char begin_label_name[16];
4148 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4150 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4153 emit_move_insn (arg_pointer_rtx,
4154 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4157 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4159 /* The address of the function is loaded into %r25 with a instruction-
4160 relative sequence that avoids the use of relocations. The sequence
4161 is split so that the load_offset_label_address instruction can
4162 occupy the delay slot of the call to _mcount. */
4164 emit_insn (gen_lcla2 (reg, label_rtx));
4166 emit_insn (gen_lcla1 (reg, label_rtx));
4168 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4169 reg, begin_label_rtx, label_rtx));
4171 #ifndef NO_PROFILE_COUNTERS
4173 rtx count_label_rtx, addr, r24;
4174 char count_label_name[16];
4176 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4177 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4179 addr = force_reg (Pmode, count_label_rtx);
4180 r24 = gen_rtx_REG (Pmode, 24);
4181 emit_move_insn (r24, addr);
4184 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4185 gen_rtx_SYMBOL_REF (Pmode,
4187 GEN_INT (TARGET_64BIT ? 24 : 12)));
4189 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4194 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4195 gen_rtx_SYMBOL_REF (Pmode,
4197 GEN_INT (TARGET_64BIT ? 16 : 8)));
4201 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4202 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4204 /* Indicate the _mcount call cannot throw, nor will it execute a
4206 REG_NOTES (call_insn)
4207 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4210 /* Fetch the return address for the frame COUNT steps up from
4211 the current frame, after the prologue. FRAMEADDR is the
4212 frame pointer of the COUNT frame.
4214 We want to ignore any export stub remnants here. To handle this,
4215 we examine the code at the return address, and if it is an export
4216 stub, we return a memory rtx for the stub return address stored
4219 The value returned is used in two different ways:
4221 1. To find a function's caller.
4223 2. To change the return address for a function.
4225 This function handles most instances of case 1; however, it will
4226 fail if there are two levels of stubs to execute on the return
4227 path. The only way I believe that can happen is if the return value
4228 needs a parameter relocation, which never happens for C code.
4230 This function handles most instances of case 2; however, it will
4231 fail if we did not originally have stub code on the return path
4232 but will need stub code on the new return path. This can happen if
4233 the caller & callee are both in the main program, but the new
4234 return location is in a shared library. */
4237 return_addr_rtx (int count, rtx frameaddr)
4247 rp = get_hard_reg_initial_val (Pmode, 2);
4249 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4252 saved_rp = gen_reg_rtx (Pmode);
4253 emit_move_insn (saved_rp, rp);
4255 /* Get pointer to the instruction stream. We have to mask out the
4256 privilege level from the two low order bits of the return address
4257 pointer here so that ins will point to the start of the first
4258 instruction that would have been executed if we returned. */
4259 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4260 label = gen_label_rtx ();
4262 /* Check the instruction stream at the normal return address for the
4265 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4266 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4267 0x00011820 | stub+16: mtsp r1,sr0
4268 0xe0400002 | stub+20: be,n 0(sr0,rp)
4270 If it is an export stub, than our return address is really in
4273 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4274 NULL_RTX, SImode, 1);
4275 emit_jump_insn (gen_bne (label));
4277 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4278 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4279 emit_jump_insn (gen_bne (label));
4281 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4282 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4283 emit_jump_insn (gen_bne (label));
4285 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4286 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4288 /* If there is no export stub then just use the value saved from
4289 the return pointer register. */
4291 emit_jump_insn (gen_bne (label));
4293 /* Here we know that our return address points to an export
4294 stub. We don't want to return the address of the export stub,
4295 but rather the return address of the export stub. That return
4296 address is stored at -24[frameaddr]. */
4298 emit_move_insn (saved_rp,
4300 memory_address (Pmode,
4301 plus_constant (frameaddr,
4308 /* This is only valid once reload has completed because it depends on
4309 knowing exactly how much (if any) frame there is and...
4311 It's only valid if there is no frame marker to de-allocate and...
4313 It's only valid if %r2 hasn't been saved into the caller's frame
4314 (we're not profiling and %r2 isn't live anywhere). */
4316 hppa_can_use_return_insn_p (void)
4318 return (reload_completed
4319 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4320 && ! regs_ever_live[2]
4321 && ! frame_pointer_needed);
4325 emit_bcond_fp (enum rtx_code code, rtx operand0)
4327 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4328 gen_rtx_IF_THEN_ELSE (VOIDmode,
4329 gen_rtx_fmt_ee (code,
4331 gen_rtx_REG (CCFPmode, 0),
4333 gen_rtx_LABEL_REF (VOIDmode, operand0),
4339 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4341 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4342 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4345 /* Adjust the cost of a scheduling dependency. Return the new cost of
4346 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4349 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4351 enum attr_type attr_type;
4353 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4354 true dependencies as they are described with bypasses now. */
4355 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4358 if (! recog_memoized (insn))
4361 attr_type = get_attr_type (insn);
4363 switch (REG_NOTE_KIND (link))
4366 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4369 if (attr_type == TYPE_FPLOAD)
4371 rtx pat = PATTERN (insn);
4372 rtx dep_pat = PATTERN (dep_insn);
4373 if (GET_CODE (pat) == PARALLEL)
4375 /* This happens for the fldXs,mb patterns. */
4376 pat = XVECEXP (pat, 0, 0);
4378 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4379 /* If this happens, we have to extend this to schedule
4380 optimally. Return 0 for now. */
4383 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4385 if (! recog_memoized (dep_insn))
4387 switch (get_attr_type (dep_insn))
4394 case TYPE_FPSQRTSGL:
4395 case TYPE_FPSQRTDBL:
4396 /* A fpload can't be issued until one cycle before a
4397 preceding arithmetic operation has finished if
4398 the target of the fpload is any of the sources
4399 (or destination) of the arithmetic operation. */
4400 return insn_default_latency (dep_insn) - 1;
4407 else if (attr_type == TYPE_FPALU)
4409 rtx pat = PATTERN (insn);
4410 rtx dep_pat = PATTERN (dep_insn);
4411 if (GET_CODE (pat) == PARALLEL)
4413 /* This happens for the fldXs,mb patterns. */
4414 pat = XVECEXP (pat, 0, 0);
4416 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4417 /* If this happens, we have to extend this to schedule
4418 optimally. Return 0 for now. */
4421 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4423 if (! recog_memoized (dep_insn))
4425 switch (get_attr_type (dep_insn))
4429 case TYPE_FPSQRTSGL:
4430 case TYPE_FPSQRTDBL:
4431 /* An ALU flop can't be issued until two cycles before a
4432 preceding divide or sqrt operation has finished if
4433 the target of the ALU flop is any of the sources
4434 (or destination) of the divide or sqrt operation. */
4435 return insn_default_latency (dep_insn) - 2;
4443 /* For other anti dependencies, the cost is 0. */
4446 case REG_DEP_OUTPUT:
4447 /* Output dependency; DEP_INSN writes a register that INSN writes some
4449 if (attr_type == TYPE_FPLOAD)
4451 rtx pat = PATTERN (insn);
4452 rtx dep_pat = PATTERN (dep_insn);
4453 if (GET_CODE (pat) == PARALLEL)
4455 /* This happens for the fldXs,mb patterns. */
4456 pat = XVECEXP (pat, 0, 0);
4458 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4459 /* If this happens, we have to extend this to schedule
4460 optimally. Return 0 for now. */
4463 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4465 if (! recog_memoized (dep_insn))
4467 switch (get_attr_type (dep_insn))
4474 case TYPE_FPSQRTSGL:
4475 case TYPE_FPSQRTDBL:
4476 /* A fpload can't be issued until one cycle before a
4477 preceding arithmetic operation has finished if
4478 the target of the fpload is the destination of the
4479 arithmetic operation.
4481 Exception: For PA7100LC, PA7200 and PA7300, the cost
4482 is 3 cycles, unless they bundle together. We also
4483 pay the penalty if the second insn is a fpload. */
4484 return insn_default_latency (dep_insn) - 1;
4491 else if (attr_type == TYPE_FPALU)
4493 rtx pat = PATTERN (insn);
4494 rtx dep_pat = PATTERN (dep_insn);
4495 if (GET_CODE (pat) == PARALLEL)
4497 /* This happens for the fldXs,mb patterns. */
4498 pat = XVECEXP (pat, 0, 0);
4500 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4501 /* If this happens, we have to extend this to schedule
4502 optimally. Return 0 for now. */
4505 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4507 if (! recog_memoized (dep_insn))
4509 switch (get_attr_type (dep_insn))
4513 case TYPE_FPSQRTSGL:
4514 case TYPE_FPSQRTDBL:
4515 /* An ALU flop can't be issued until two cycles before a
4516 preceding divide or sqrt operation has finished if
4517 the target of the ALU flop is also the target of
4518 the divide or sqrt operation. */
4519 return insn_default_latency (dep_insn) - 2;
4527 /* For other output dependencies, the cost is 0. */
4535 /* Adjust scheduling priorities. We use this to try and keep addil
4536 and the next use of %r1 close together. */
4538 pa_adjust_priority (rtx insn, int priority)
4540 rtx set = single_set (insn);
4544 src = SET_SRC (set);
4545 dest = SET_DEST (set);
4546 if (GET_CODE (src) == LO_SUM
4547 && symbolic_operand (XEXP (src, 1), VOIDmode)
4548 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4551 else if (GET_CODE (src) == MEM
4552 && GET_CODE (XEXP (src, 0)) == LO_SUM
4553 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4554 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4557 else if (GET_CODE (dest) == MEM
4558 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4559 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4560 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4566 /* The 700 can only issue a single insn at a time.
4567 The 7XXX processors can issue two insns at a time.
4568 The 8000 can issue 4 insns at a time. */
4570 pa_issue_rate (void)
4574 case PROCESSOR_700: return 1;
4575 case PROCESSOR_7100: return 2;
4576 case PROCESSOR_7100LC: return 2;
4577 case PROCESSOR_7200: return 2;
4578 case PROCESSOR_7300: return 2;
4579 case PROCESSOR_8000: return 4;
4588 /* Return any length adjustment needed by INSN which already has its length
4589 computed as LENGTH. Return zero if no adjustment is necessary.
4591 For the PA: function calls, millicode calls, and backwards short
4592 conditional branches with unfilled delay slots need an adjustment by +1
4593 (to account for the NOP which will be inserted into the instruction stream).
4595 Also compute the length of an inline block move here as it is too
4596 complicated to express as a length attribute in pa.md. */
4598 pa_adjust_insn_length (rtx insn, int length)
4600 rtx pat = PATTERN (insn);
4602 /* Jumps inside switch tables which have unfilled delay slots need
4604 if (GET_CODE (insn) == JUMP_INSN
4605 && GET_CODE (pat) == PARALLEL
4606 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4608 /* Millicode insn with an unfilled delay slot. */
4609 else if (GET_CODE (insn) == INSN
4610 && GET_CODE (pat) != SEQUENCE
4611 && GET_CODE (pat) != USE
4612 && GET_CODE (pat) != CLOBBER
4613 && get_attr_type (insn) == TYPE_MILLI)
4615 /* Block move pattern. */
4616 else if (GET_CODE (insn) == INSN
4617 && GET_CODE (pat) == PARALLEL
4618 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4619 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4620 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4621 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4622 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4623 return compute_movmem_length (insn) - 4;
4624 /* Block clear pattern. */
4625 else if (GET_CODE (insn) == INSN
4626 && GET_CODE (pat) == PARALLEL
4627 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4628 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4629 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4630 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4631 return compute_clrmem_length (insn) - 4;
4632 /* Conditional branch with an unfilled delay slot. */
4633 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4635 /* Adjust a short backwards conditional with an unfilled delay slot. */
4636 if (GET_CODE (pat) == SET
4638 && ! forward_branch_p (insn))
4640 else if (GET_CODE (pat) == PARALLEL
4641 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4644 /* Adjust dbra insn with short backwards conditional branch with
4645 unfilled delay slot -- only for case where counter is in a
4646 general register register. */
4647 else if (GET_CODE (pat) == PARALLEL
4648 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4649 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4650 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4652 && ! forward_branch_p (insn))
4660 /* Print operand X (an rtx) in assembler syntax to file FILE.
4661 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4662 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4665 print_operand (FILE *file, rtx x, int code)
4670 /* Output a 'nop' if there's nothing for the delay slot. */
4671 if (dbr_sequence_length () == 0)
4672 fputs ("\n\tnop", file);
4675 /* Output a nullification completer if there's nothing for the */
4676 /* delay slot or nullification is requested. */
4677 if (dbr_sequence_length () == 0 ||
4679 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4683 /* Print out the second register name of a register pair.
4684 I.e., R (6) => 7. */
4685 fputs (reg_names[REGNO (x) + 1], file);
4688 /* A register or zero. */
4690 || (x == CONST0_RTX (DFmode))
4691 || (x == CONST0_RTX (SFmode)))
4693 fputs ("%r0", file);
4699 /* A register or zero (floating point). */
4701 || (x == CONST0_RTX (DFmode))
4702 || (x == CONST0_RTX (SFmode)))
4704 fputs ("%fr0", file);
4713 xoperands[0] = XEXP (XEXP (x, 0), 0);
4714 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4715 output_global_address (file, xoperands[1], 0);
4716 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4720 case 'C': /* Plain (C)ondition */
4722 switch (GET_CODE (x))
4725 fputs ("=", file); break;
4727 fputs ("<>", file); break;
4729 fputs (">", file); break;
4731 fputs (">=", file); break;
4733 fputs (">>=", file); break;
4735 fputs (">>", file); break;
4737 fputs ("<", file); break;
4739 fputs ("<=", file); break;
4741 fputs ("<<=", file); break;
4743 fputs ("<<", file); break;
4748 case 'N': /* Condition, (N)egated */
4749 switch (GET_CODE (x))
4752 fputs ("<>", file); break;
4754 fputs ("=", file); break;
4756 fputs ("<=", file); break;
4758 fputs ("<", file); break;
4760 fputs ("<<", file); break;
4762 fputs ("<<=", file); break;
4764 fputs (">=", file); break;
4766 fputs (">", file); break;
4768 fputs (">>", file); break;
4770 fputs (">>=", file); break;
4775 /* For floating point comparisons. Note that the output
4776 predicates are the complement of the desired mode. The
4777 conditions for GT, GE, LT, LE and LTGT cause an invalid
4778 operation exception if the result is unordered and this
4779 exception is enabled in the floating-point status register. */
4781 switch (GET_CODE (x))
4784 fputs ("!=", file); break;
4786 fputs ("=", file); break;
4788 fputs ("!>", file); break;
4790 fputs ("!>=", file); break;
4792 fputs ("!<", file); break;
4794 fputs ("!<=", file); break;
4796 fputs ("!<>", file); break;
4798 fputs ("!?<=", file); break;
4800 fputs ("!?<", file); break;
4802 fputs ("!?>=", file); break;
4804 fputs ("!?>", file); break;
4806 fputs ("!?=", file); break;
4808 fputs ("!?", file); break;
4810 fputs ("?", file); break;
4815 case 'S': /* Condition, operands are (S)wapped. */
4816 switch (GET_CODE (x))
4819 fputs ("=", file); break;
4821 fputs ("<>", file); break;
4823 fputs ("<", file); break;
4825 fputs ("<=", file); break;
4827 fputs ("<<=", file); break;
4829 fputs ("<<", file); break;
4831 fputs (">", file); break;
4833 fputs (">=", file); break;
4835 fputs (">>=", file); break;
4837 fputs (">>", file); break;
4842 case 'B': /* Condition, (B)oth swapped and negate. */
4843 switch (GET_CODE (x))
4846 fputs ("<>", file); break;
4848 fputs ("=", file); break;
4850 fputs (">=", file); break;
4852 fputs (">", file); break;
4854 fputs (">>", file); break;
4856 fputs (">>=", file); break;
4858 fputs ("<=", file); break;
4860 fputs ("<", file); break;
4862 fputs ("<<", file); break;
4864 fputs ("<<=", file); break;
4870 gcc_assert (GET_CODE (x) == CONST_INT);
4871 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4874 gcc_assert (GET_CODE (x) == CONST_INT);
4875 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4878 gcc_assert (GET_CODE (x) == CONST_INT);
4879 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4882 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
4883 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4886 gcc_assert (GET_CODE (x) == CONST_INT);
4887 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4890 gcc_assert (GET_CODE (x) == CONST_INT);
4891 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4894 if (GET_CODE (x) == CONST_INT)
4899 switch (GET_CODE (XEXP (x, 0)))
4903 if (ASSEMBLER_DIALECT == 0)
4904 fputs ("s,mb", file);
4906 fputs (",mb", file);
4910 if (ASSEMBLER_DIALECT == 0)
4911 fputs ("s,ma", file);
4913 fputs (",ma", file);
4916 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4917 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
4919 if (ASSEMBLER_DIALECT == 0)
4922 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4923 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4925 if (ASSEMBLER_DIALECT == 0)
4926 fputs ("x,s", file);
4930 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4934 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4940 output_global_address (file, x, 0);
4943 output_global_address (file, x, 1);
4945 case 0: /* Don't do anything special */
4950 compute_zdepwi_operands (INTVAL (x), op);
4951 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4957 compute_zdepdi_operands (INTVAL (x), op);
4958 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4962 /* We can get here from a .vtable_inherit due to our
4963 CONSTANT_ADDRESS_P rejecting perfectly good constant
4969 if (GET_CODE (x) == REG)
4971 fputs (reg_names [REGNO (x)], file);
4972 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4978 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4979 && (REGNO (x) & 1) == 0)
4982 else if (GET_CODE (x) == MEM)
4984 int size = GET_MODE_SIZE (GET_MODE (x));
4985 rtx base = NULL_RTX;
4986 switch (GET_CODE (XEXP (x, 0)))
4990 base = XEXP (XEXP (x, 0), 0);
4991 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4995 base = XEXP (XEXP (x, 0), 0);
4996 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4999 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5000 fprintf (file, "%s(%s)",
5001 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5002 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5003 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5004 fprintf (file, "%s(%s)",
5005 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5006 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5007 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5008 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5010 /* Because the REG_POINTER flag can get lost during reload,
5011 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5012 index and base registers in the combined move patterns. */
5013 rtx base = XEXP (XEXP (x, 0), 1);
5014 rtx index = XEXP (XEXP (x, 0), 0);
5016 fprintf (file, "%s(%s)",
5017 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5020 output_address (XEXP (x, 0));
5023 output_address (XEXP (x, 0));
5028 output_addr_const (file, x);
5031 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5034 output_global_address (FILE *file, rtx x, int round_constant)
5037 /* Imagine (high (const (plus ...))). */
5038 if (GET_CODE (x) == HIGH)
5041 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5042 output_addr_const (file, x);
5043 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5045 output_addr_const (file, x);
5046 fputs ("-$global$", file);
5048 else if (GET_CODE (x) == CONST)
5050 const char *sep = "";
5051 int offset = 0; /* assembler wants -$global$ at end */
5052 rtx base = NULL_RTX;
5054 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5057 base = XEXP (XEXP (x, 0), 0);
5058 output_addr_const (file, base);
5061 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5067 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5070 base = XEXP (XEXP (x, 0), 1);
5071 output_addr_const (file, base);
5074 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5080 /* How bogus. The compiler is apparently responsible for
5081 rounding the constant if it uses an LR field selector.
5083 The linker and/or assembler seem a better place since
5084 they have to do this kind of thing already.
5086 If we fail to do this, HP's optimizing linker may eliminate
5087 an addil, but not update the ldw/stw/ldo instruction that
5088 uses the result of the addil. */
5090 offset = ((offset + 0x1000) & ~0x1fff);
5092 switch (GET_CODE (XEXP (x, 0)))
5105 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5113 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5114 fputs ("-$global$", file);
5116 fprintf (file, "%s%d", sep, offset);
5119 output_addr_const (file, x);
5122 /* Output boilerplate text to appear at the beginning of the file.
5123 There are several possible versions. */
5124 #define aputs(x) fputs(x, asm_out_file)
5126 pa_file_start_level (void)
5129 aputs ("\t.LEVEL 2.0w\n");
5130 else if (TARGET_PA_20)
5131 aputs ("\t.LEVEL 2.0\n");
5132 else if (TARGET_PA_11)
5133 aputs ("\t.LEVEL 1.1\n");
5135 aputs ("\t.LEVEL 1.0\n");
5139 pa_file_start_space (int sortspace)
5141 aputs ("\t.SPACE $PRIVATE$");
5144 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5145 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5146 "\n\t.SPACE $TEXT$");
5149 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5150 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5154 pa_file_start_file (int want_version)
5156 if (write_symbols != NO_DEBUG)
5158 output_file_directive (asm_out_file, main_input_filename);
5160 aputs ("\t.version\t\"01.01\"\n");
5165 pa_file_start_mcount (const char *aswhat)
5168 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5172 pa_elf_file_start (void)
5174 pa_file_start_level ();
5175 pa_file_start_mcount ("ENTRY");
5176 pa_file_start_file (0);
5180 pa_som_file_start (void)
5182 pa_file_start_level ();
5183 pa_file_start_space (0);
5184 aputs ("\t.IMPORT $global$,DATA\n"
5185 "\t.IMPORT $$dyncall,MILLICODE\n");
5186 pa_file_start_mcount ("CODE");
5187 pa_file_start_file (0);
5191 pa_linux_file_start (void)
5193 pa_file_start_file (1);
5194 pa_file_start_level ();
5195 pa_file_start_mcount ("CODE");
5199 pa_hpux64_gas_file_start (void)
5201 pa_file_start_level ();
5202 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5204 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5206 pa_file_start_file (1);
5210 pa_hpux64_hpas_file_start (void)
5212 pa_file_start_level ();
5213 pa_file_start_space (1);
5214 pa_file_start_mcount ("CODE");
5215 pa_file_start_file (0);
5219 static struct deferred_plabel *
5220 get_plabel (rtx symbol)
5222 const char *fname = XSTR (symbol, 0);
5225 /* See if we have already put this function on the list of deferred
5226 plabels. This list is generally small, so a liner search is not
5227 too ugly. If it proves too slow replace it with something faster. */
5228 for (i = 0; i < n_deferred_plabels; i++)
5229 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5232 /* If the deferred plabel list is empty, or this entry was not found
5233 on the list, create a new entry on the list. */
5234 if (deferred_plabels == NULL || i == n_deferred_plabels)
5238 if (deferred_plabels == 0)
5239 deferred_plabels = (struct deferred_plabel *)
5240 ggc_alloc (sizeof (struct deferred_plabel));
5242 deferred_plabels = (struct deferred_plabel *)
5243 ggc_realloc (deferred_plabels,
5244 ((n_deferred_plabels + 1)
5245 * sizeof (struct deferred_plabel)));
5247 i = n_deferred_plabels++;
5248 deferred_plabels[i].internal_label = gen_label_rtx ();
5249 deferred_plabels[i].symbol = symbol;
5251 /* Gross. We have just implicitly taken the address of this
5252 function. Mark it in the same manner as assemble_name. */
5253 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5255 mark_referenced (id);
5258 return &deferred_plabels[i];
5262 output_deferred_plabels (void)
5265 /* If we have deferred plabels, then we need to switch into the data
5266 section and align it to a 4 byte boundary before we output the
5267 deferred plabels. */
5268 if (n_deferred_plabels)
5271 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5274 /* Now output the deferred plabels. */
5275 for (i = 0; i < n_deferred_plabels; i++)
5277 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5278 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5279 assemble_integer (deferred_plabels[i].symbol,
5280 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5284 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5285 /* Initialize optabs to point to HPUX long double emulation routines. */
5287 pa_hpux_init_libfuncs (void)
5289 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5290 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5291 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5292 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5293 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5294 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5295 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5296 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5297 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5299 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5300 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5301 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5302 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5303 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5304 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5305 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5307 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5308 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5309 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5310 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5312 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5313 ? "__U_Qfcnvfxt_quad_to_sgl"
5314 : "_U_Qfcnvfxt_quad_to_sgl");
5315 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5316 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5317 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5319 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5320 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5324 /* HP's millicode routines mean something special to the assembler.
5325 Keep track of which ones we have used. */
5327 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5328 static void import_milli (enum millicodes);
5329 static char imported[(int) end1000];
5330 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5331 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5332 #define MILLI_START 10
5335 import_milli (enum millicodes code)
5337 char str[sizeof (import_string)];
5339 if (!imported[(int) code])
5341 imported[(int) code] = 1;
5342 strcpy (str, import_string);
5343 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5344 output_asm_insn (str, 0);
5348 /* The register constraints have put the operands and return value in
5349 the proper registers. */
5352 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5354 import_milli (mulI);
5355 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5358 /* Emit the rtl for doing a division by a constant. */
5360 /* Do magic division millicodes exist for this value? */
5361 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5363 /* We'll use an array to keep track of the magic millicodes and
5364 whether or not we've used them already. [n][0] is signed, [n][1] is
5367 static int div_milli[16][2];
5370 emit_hpdiv_const (rtx *operands, int unsignedp)
5372 if (GET_CODE (operands[2]) == CONST_INT
5373 && INTVAL (operands[2]) > 0
5374 && INTVAL (operands[2]) < 16
5375 && magic_milli[INTVAL (operands[2])])
5377 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5379 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5383 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5384 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5386 gen_rtx_REG (SImode, 26),
5388 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5389 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5390 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5391 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5392 gen_rtx_CLOBBER (VOIDmode, ret))));
5393 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5400 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5404 /* If the divisor is a constant, try to use one of the special
5406 if (GET_CODE (operands[0]) == CONST_INT)
5408 static char buf[100];
5409 divisor = INTVAL (operands[0]);
5410 if (!div_milli[divisor][unsignedp])
5412 div_milli[divisor][unsignedp] = 1;
5414 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5416 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5420 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5421 INTVAL (operands[0]));
5422 return output_millicode_call (insn,
5423 gen_rtx_SYMBOL_REF (SImode, buf));
5427 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5428 INTVAL (operands[0]));
5429 return output_millicode_call (insn,
5430 gen_rtx_SYMBOL_REF (SImode, buf));
5433 /* Divisor isn't a special constant. */
5438 import_milli (divU);
5439 return output_millicode_call (insn,
5440 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5444 import_milli (divI);
5445 return output_millicode_call (insn,
5446 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5451 /* Output a $$rem millicode to do mod. */
5454 output_mod_insn (int unsignedp, rtx insn)
5458 import_milli (remU);
5459 return output_millicode_call (insn,
5460 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5464 import_milli (remI);
5465 return output_millicode_call (insn,
5466 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5471 output_arg_descriptor (rtx call_insn)
5473 const char *arg_regs[4];
5474 enum machine_mode arg_mode;
5476 int i, output_flag = 0;
5479 /* We neither need nor want argument location descriptors for the
5480 64bit runtime environment or the ELF32 environment. */
5481 if (TARGET_64BIT || TARGET_ELF32)
5484 for (i = 0; i < 4; i++)
5487 /* Specify explicitly that no argument relocations should take place
5488 if using the portable runtime calling conventions. */
5489 if (TARGET_PORTABLE_RUNTIME)
5491 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5496 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5497 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5498 link; link = XEXP (link, 1))
5500 rtx use = XEXP (link, 0);
5502 if (! (GET_CODE (use) == USE
5503 && GET_CODE (XEXP (use, 0)) == REG
5504 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5507 arg_mode = GET_MODE (XEXP (use, 0));
5508 regno = REGNO (XEXP (use, 0));
5509 if (regno >= 23 && regno <= 26)
5511 arg_regs[26 - regno] = "GR";
5512 if (arg_mode == DImode)
5513 arg_regs[25 - regno] = "GR";
5515 else if (regno >= 32 && regno <= 39)
5517 if (arg_mode == SFmode)
5518 arg_regs[(regno - 32) / 2] = "FR";
5521 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5522 arg_regs[(regno - 34) / 2] = "FR";
5523 arg_regs[(regno - 34) / 2 + 1] = "FU";
5525 arg_regs[(regno - 34) / 2] = "FU";
5526 arg_regs[(regno - 34) / 2 + 1] = "FR";
5531 fputs ("\t.CALL ", asm_out_file);
5532 for (i = 0; i < 4; i++)
5537 fputc (',', asm_out_file);
5538 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5541 fputc ('\n', asm_out_file);
5544 /* Return the class of any secondary reload register that is needed to
5545 move IN into a register in class CLASS using mode MODE.
5547 Profiling has showed this routine and its descendants account for
5548 a significant amount of compile time (~7%). So it has been
5549 optimized to reduce redundant computations and eliminate useless
5552 It might be worthwhile to try and make this a leaf function too. */
5555 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5557 int regno, is_symbolic;
5559 /* Trying to load a constant into a FP register during PIC code
5560 generation will require %r1 as a scratch register. */
5562 && GET_MODE_CLASS (mode) == MODE_INT
5563 && FP_REG_CLASS_P (class)
5564 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5567 /* Profiling showed the PA port spends about 1.3% of its compilation
5568 time in true_regnum from calls inside secondary_reload_class. */
5570 if (GET_CODE (in) == REG)
5573 if (regno >= FIRST_PSEUDO_REGISTER)
5574 regno = true_regnum (in);
5576 else if (GET_CODE (in) == SUBREG)
5577 regno = true_regnum (in);
5581 /* If we have something like (mem (mem (...)), we can safely assume the
5582 inner MEM will end up in a general register after reloading, so there's
5583 no need for a secondary reload. */
5584 if (GET_CODE (in) == MEM
5585 && GET_CODE (XEXP (in, 0)) == MEM)
5588 /* Handle out of range displacement for integer mode loads/stores of
5590 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5591 && GET_MODE_CLASS (mode) == MODE_INT
5592 && FP_REG_CLASS_P (class))
5593 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5594 return GENERAL_REGS;
5596 /* A SAR<->FP register copy requires a secondary register (GPR) as
5597 well as secondary memory. */
5598 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5599 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5600 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5601 return GENERAL_REGS;
5603 if (GET_CODE (in) == HIGH)
5606 /* Profiling has showed GCC spends about 2.6% of its compilation
5607 time in symbolic_operand from calls inside secondary_reload_class.
5609 We use an inline copy and only compute its return value once to avoid
5611 switch (GET_CODE (in))
5621 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5622 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5623 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5633 && read_only_operand (in, VOIDmode))
5636 if (class != R1_REGS && is_symbolic)
5642 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5643 by invisible reference. As a GCC extension, we also pass anything
5644 with a zero or variable size by reference.
5646 The 64-bit runtime does not describe passing any types by invisible
5647 reference. The internals of GCC can't currently handle passing
5648 empty structures, and zero or variable length arrays when they are
5649 not passed entirely on the stack or by reference. Thus, as a GCC
5650 extension, we pass these types by reference. The HP compiler doesn't
5651 support these types, so hopefully there shouldn't be any compatibility
5652 issues. This may have to be revisited when HP releases a C99 compiler
5653 or updates the ABI. */
5656 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5657 enum machine_mode mode, tree type,
5658 bool named ATTRIBUTE_UNUSED)
5663 size = int_size_in_bytes (type);
5665 size = GET_MODE_SIZE (mode);
5670 return size <= 0 || size > 8;
5674 function_arg_padding (enum machine_mode mode, tree type)
5677 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5679 /* Return none if justification is not required. */
5681 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5682 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5685 /* The directions set here are ignored when a BLKmode argument larger
5686 than a word is placed in a register. Different code is used for
5687 the stack and registers. This makes it difficult to have a
5688 consistent data representation for both the stack and registers.
5689 For both runtimes, the justification and padding for arguments on
5690 the stack and in registers should be identical. */
5692 /* The 64-bit runtime specifies left justification for aggregates. */
5695 /* The 32-bit runtime architecture specifies right justification.
5696 When the argument is passed on the stack, the argument is padded
5697 with garbage on the left. The HP compiler pads with zeros. */
5701 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5708 /* Do what is necessary for `va_start'. We look at the current function
5709 to determine if stdargs or varargs is used and fill in an initial
5710 va_list. A pointer to this constructor is returned. */
5713 hppa_builtin_saveregs (void)
5716 tree fntype = TREE_TYPE (current_function_decl);
5717 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5718 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5719 != void_type_node)))
5720 ? UNITS_PER_WORD : 0);
5723 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5725 offset = current_function_arg_offset_rtx;
5731 /* Adjust for varargs/stdarg differences. */
5733 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5735 offset = current_function_arg_offset_rtx;
5737 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5738 from the incoming arg pointer and growing to larger addresses. */
5739 for (i = 26, off = -64; i >= 19; i--, off += 8)
5740 emit_move_insn (gen_rtx_MEM (word_mode,
5741 plus_constant (arg_pointer_rtx, off)),
5742 gen_rtx_REG (word_mode, i));
5744 /* The incoming args pointer points just beyond the flushback area;
5745 normally this is not a serious concern. However, when we are doing
5746 varargs/stdargs we want to make the arg pointer point to the start
5747 of the incoming argument area. */
5748 emit_move_insn (virtual_incoming_args_rtx,
5749 plus_constant (arg_pointer_rtx, -64));
5751 /* Now return a pointer to the first anonymous argument. */
5752 return copy_to_reg (expand_binop (Pmode, add_optab,
5753 virtual_incoming_args_rtx,
5754 offset, 0, 0, OPTAB_LIB_WIDEN));
5757 /* Store general registers on the stack. */
5758 dest = gen_rtx_MEM (BLKmode,
5759 plus_constant (current_function_internal_arg_pointer,
5761 set_mem_alias_set (dest, get_varargs_alias_set ());
5762 set_mem_align (dest, BITS_PER_WORD);
5763 move_block_from_reg (23, dest, 4);
5765 /* move_block_from_reg will emit code to store the argument registers
5766 individually as scalar stores.
5768 However, other insns may later load from the same addresses for
5769 a structure load (passing a struct to a varargs routine).
5771 The alias code assumes that such aliasing can never happen, so we
5772 have to keep memory referencing insns from moving up beyond the
5773 last argument register store. So we emit a blockage insn here. */
5774 emit_insn (gen_blockage ());
5776 return copy_to_reg (expand_binop (Pmode, add_optab,
5777 current_function_internal_arg_pointer,
5778 offset, 0, 0, OPTAB_LIB_WIDEN));
5782 hppa_va_start (tree valist, rtx nextarg)
5784 nextarg = expand_builtin_saveregs ();
5785 std_expand_builtin_va_start (valist, nextarg);
5789 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
5793 /* Args grow upward. We can use the generic routines. */
5794 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5796 else /* !TARGET_64BIT */
5798 tree ptr = build_pointer_type (type);
5801 unsigned int size, ofs;
5804 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5808 ptr = build_pointer_type (type);
5810 size = int_size_in_bytes (type);
5811 valist_type = TREE_TYPE (valist);
5813 /* Args grow down. Not handled by generic routines. */
5815 u = fold_convert (valist_type, size_in_bytes (type));
5816 t = build (MINUS_EXPR, valist_type, valist, u);
5818 /* Copied from va-pa.h, but we probably don't need to align to
5819 word size, since we generate and preserve that invariant. */
5820 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
5821 t = build (BIT_AND_EXPR, valist_type, t, u);
5823 t = build (MODIFY_EXPR, valist_type, valist, t);
5825 ofs = (8 - size) % 4;
5828 u = fold_convert (valist_type, size_int (ofs));
5829 t = build (PLUS_EXPR, valist_type, t, u);
5832 t = fold_convert (ptr, t);
5833 t = build_fold_indirect_ref (t);
5836 t = build_fold_indirect_ref (t);
5842 /* True if MODE is valid for the target. By "valid", we mean able to
5843 be manipulated in non-trivial ways. In particular, this means all
5844 the arithmetic is supported.
5846 Currently, TImode is not valid as the HP 64-bit runtime documentation
5847 doesn't document the alignment and calling conventions for this type.
5848 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
5849 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
5852 pa_scalar_mode_supported_p (enum machine_mode mode)
5854 int precision = GET_MODE_PRECISION (mode);
5856 switch (GET_MODE_CLASS (mode))
5858 case MODE_PARTIAL_INT:
5860 if (precision == CHAR_TYPE_SIZE)
5862 if (precision == SHORT_TYPE_SIZE)
5864 if (precision == INT_TYPE_SIZE)
5866 if (precision == LONG_TYPE_SIZE)
5868 if (precision == LONG_LONG_TYPE_SIZE)
5873 if (precision == FLOAT_TYPE_SIZE)
5875 if (precision == DOUBLE_TYPE_SIZE)
5877 if (precision == LONG_DOUBLE_TYPE_SIZE)
5886 /* This routine handles all the normal conditional branch sequences we
5887 might need to generate. It handles compare immediate vs compare
5888 register, nullification of delay slots, varying length branches,
5889 negated branches, and all combinations of the above. It returns the
5890 output appropriate to emit the branch corresponding to all given
5894 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
5896 static char buf[100];
5900 /* A conditional branch to the following instruction (e.g. the delay slot)
5901 is asking for a disaster. This can happen when not optimizing and
5902 when jump optimization fails.
5904 While it is usually safe to emit nothing, this can fail if the
5905 preceding instruction is a nullified branch with an empty delay
5906 slot and the same branch target as this branch. We could check
5907 for this but jump optimization should eliminate nop jumps. It
5908 is always safe to emit a nop. */
5909 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5912 /* The doubleword form of the cmpib instruction doesn't have the LEU
5913 and GTU conditions while the cmpb instruction does. Since we accept
5914 zero for cmpb, we must ensure that we use cmpb for the comparison. */
5915 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
5916 operands[2] = gen_rtx_REG (DImode, 0);
5918 /* If this is a long branch with its delay slot unfilled, set `nullify'
5919 as it can nullify the delay slot and save a nop. */
5920 if (length == 8 && dbr_sequence_length () == 0)
5923 /* If this is a short forward conditional branch which did not get
5924 its delay slot filled, the delay slot can still be nullified. */
5925 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5926 nullify = forward_branch_p (insn);
5928 /* A forward branch over a single nullified insn can be done with a
5929 comclr instruction. This avoids a single cycle penalty due to
5930 mis-predicted branch if we fall through (branch not taken). */
5932 && next_real_insn (insn) != 0
5933 && get_attr_length (next_real_insn (insn)) == 4
5934 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5940 /* All short conditional branches except backwards with an unfilled
5944 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5946 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5947 if (GET_MODE (operands[1]) == DImode)
5950 strcat (buf, "%B3");
5952 strcat (buf, "%S3");
5954 strcat (buf, " %2,%r1,%%r0");
5956 strcat (buf, ",n %2,%r1,%0");
5958 strcat (buf, " %2,%r1,%0");
5961 /* All long conditionals. Note a short backward branch with an
5962 unfilled delay slot is treated just like a long backward branch
5963 with an unfilled delay slot. */
5965 /* Handle weird backwards branch with a filled delay slot
5966 with is nullified. */
5967 if (dbr_sequence_length () != 0
5968 && ! forward_branch_p (insn)
5971 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5972 if (GET_MODE (operands[1]) == DImode)
5975 strcat (buf, "%S3");
5977 strcat (buf, "%B3");
5978 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5980 /* Handle short backwards branch with an unfilled delay slot.
5981 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5982 taken and untaken branches. */
5983 else if (dbr_sequence_length () == 0
5984 && ! forward_branch_p (insn)
5985 && INSN_ADDRESSES_SET_P ()
5986 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5987 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5989 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5990 if (GET_MODE (operands[1]) == DImode)
5993 strcat (buf, "%B3 %2,%r1,%0%#");
5995 strcat (buf, "%S3 %2,%r1,%0%#");
5999 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6000 if (GET_MODE (operands[1]) == DImode)
6003 strcat (buf, "%S3");
6005 strcat (buf, "%B3");
6007 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6009 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6015 xoperands[0] = operands[0];
6016 xoperands[1] = operands[1];
6017 xoperands[2] = operands[2];
6018 xoperands[3] = operands[3];
6020 /* The reversed conditional branch must branch over one additional
6021 instruction if the delay slot is filled. If the delay slot
6022 is empty, the instruction after the reversed condition branch
6023 must be nullified. */
6024 nullify = dbr_sequence_length () == 0;
6025 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6027 /* Create a reversed conditional branch which branches around
6028 the following insns. */
6029 if (GET_MODE (operands[1]) != DImode)
6035 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6038 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6044 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6047 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6056 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6059 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6065 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6068 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6072 output_asm_insn (buf, xoperands);
6073 return output_lbranch (operands[0], insn);
6081 /* This routine handles long unconditional branches that exceed the
6082 maximum range of a simple branch instruction. */
6085 output_lbranch (rtx dest, rtx insn)
6089 xoperands[0] = dest;
6091 /* First, free up the delay slot. */
6092 if (dbr_sequence_length () != 0)
6094 /* We can't handle a jump in the delay slot. */
6095 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6097 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6100 /* Now delete the delay insn. */
6101 PUT_CODE (NEXT_INSN (insn), NOTE);
6102 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6103 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6106 /* Output an insn to save %r1. The runtime documentation doesn't
6107 specify whether the "Clean Up" slot in the callers frame can
6108 be clobbered by the callee. It isn't copied by HP's builtin
6109 alloca, so this suggests that it can be clobbered if necessary.
6110 The "Static Link" location is copied by HP builtin alloca, so
6111 we avoid using it. Using the cleanup slot might be a problem
6112 if we have to interoperate with languages that pass cleanup
6113 information. However, it should be possible to handle these
6114 situations with GCC's asm feature.
6116 The "Current RP" slot is reserved for the called procedure, so
6117 we try to use it when we don't have a frame of our own. It's
6118 rather unlikely that we won't have a frame when we need to emit
6121 Really the way to go long term is a register scavenger; goto
6122 the target of the jump and find a register which we can use
6123 as a scratch to hold the value in %r1. Then, we wouldn't have
6124 to free up the delay slot or clobber a slot that may be needed
6125 for other purposes. */
6128 if (actual_fsize == 0 && !regs_ever_live[2])
6129 /* Use the return pointer slot in the frame marker. */
6130 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6132 /* Use the slot at -40 in the frame marker since HP builtin
6133 alloca doesn't copy it. */
6134 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6138 if (actual_fsize == 0 && !regs_ever_live[2])
6139 /* Use the return pointer slot in the frame marker. */
6140 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6142 /* Use the "Clean Up" slot in the frame marker. In GCC,
6143 the only other use of this location is for copying a
6144 floating point double argument from a floating-point
6145 register to two general registers. The copy is done
6146 as an "atomic" operation when outputting a call, so it
6147 won't interfere with our using the location here. */
6148 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6151 if (TARGET_PORTABLE_RUNTIME)
6153 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6154 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6155 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6159 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6160 if (TARGET_SOM || !TARGET_GAS)
6162 xoperands[1] = gen_label_rtx ();
6163 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6164 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6165 CODE_LABEL_NUMBER (xoperands[1]));
6166 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6170 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6171 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6173 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6176 /* Now output a very long branch to the original target. */
6177 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6179 /* Now restore the value of %r1 in the delay slot. */
6182 if (actual_fsize == 0 && !regs_ever_live[2])
6183 return "ldd -16(%%r30),%%r1";
6185 return "ldd -40(%%r30),%%r1";
6189 if (actual_fsize == 0 && !regs_ever_live[2])
6190 return "ldw -20(%%r30),%%r1";
6192 return "ldw -12(%%r30),%%r1";
6196 /* This routine handles all the branch-on-bit conditional branch sequences we
6197 might need to generate. It handles nullification of delay slots,
6198 varying length branches, negated branches and all combinations of the
6199 above. it returns the appropriate output template to emit the branch. */
6202 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6203 int negated, rtx insn, int which)
6205 static char buf[100];
6208 /* A conditional branch to the following instruction (e.g. the delay slot) is
6209 asking for a disaster. I do not think this can happen as this pattern
6210 is only used when optimizing; jump optimization should eliminate the
6211 jump. But be prepared just in case. */
6213 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6216 /* If this is a long branch with its delay slot unfilled, set `nullify'
6217 as it can nullify the delay slot and save a nop. */
6218 if (length == 8 && dbr_sequence_length () == 0)
6221 /* If this is a short forward conditional branch which did not get
6222 its delay slot filled, the delay slot can still be nullified. */
6223 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6224 nullify = forward_branch_p (insn);
6226 /* A forward branch over a single nullified insn can be done with a
6227 extrs instruction. This avoids a single cycle penalty due to
6228 mis-predicted branch if we fall through (branch not taken). */
6231 && next_real_insn (insn) != 0
6232 && get_attr_length (next_real_insn (insn)) == 4
6233 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6240 /* All short conditional branches except backwards with an unfilled
6244 strcpy (buf, "{extrs,|extrw,s,}");
6246 strcpy (buf, "bb,");
6247 if (useskip && GET_MODE (operands[0]) == DImode)
6248 strcpy (buf, "extrd,s,*");
6249 else if (GET_MODE (operands[0]) == DImode)
6250 strcpy (buf, "bb,*");
6251 if ((which == 0 && negated)
6252 || (which == 1 && ! negated))
6257 strcat (buf, " %0,%1,1,%%r0");
6258 else if (nullify && negated)
6259 strcat (buf, ",n %0,%1,%3");
6260 else if (nullify && ! negated)
6261 strcat (buf, ",n %0,%1,%2");
6262 else if (! nullify && negated)
6263 strcat (buf, "%0,%1,%3");
6264 else if (! nullify && ! negated)
6265 strcat (buf, " %0,%1,%2");
6268 /* All long conditionals. Note a short backward branch with an
6269 unfilled delay slot is treated just like a long backward branch
6270 with an unfilled delay slot. */
6272 /* Handle weird backwards branch with a filled delay slot
6273 with is nullified. */
6274 if (dbr_sequence_length () != 0
6275 && ! forward_branch_p (insn)
6278 strcpy (buf, "bb,");
6279 if (GET_MODE (operands[0]) == DImode)
6281 if ((which == 0 && negated)
6282 || (which == 1 && ! negated))
6287 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6289 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6291 /* Handle short backwards branch with an unfilled delay slot.
6292 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6293 taken and untaken branches. */
6294 else if (dbr_sequence_length () == 0
6295 && ! forward_branch_p (insn)
6296 && INSN_ADDRESSES_SET_P ()
6297 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6298 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6300 strcpy (buf, "bb,");
6301 if (GET_MODE (operands[0]) == DImode)
6303 if ((which == 0 && negated)
6304 || (which == 1 && ! negated))
6309 strcat (buf, " %0,%1,%3%#");
6311 strcat (buf, " %0,%1,%2%#");
6315 strcpy (buf, "{extrs,|extrw,s,}");
6316 if (GET_MODE (operands[0]) == DImode)
6317 strcpy (buf, "extrd,s,*");
6318 if ((which == 0 && negated)
6319 || (which == 1 && ! negated))
6323 if (nullify && negated)
6324 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6325 else if (nullify && ! negated)
6326 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6328 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6330 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6340 /* This routine handles all the branch-on-variable-bit conditional branch
6341 sequences we might need to generate. It handles nullification of delay
6342 slots, varying length branches, negated branches and all combinations
6343 of the above. it returns the appropriate output template to emit the
6347 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6348 int negated, rtx insn, int which)
6350 static char buf[100];
6353 /* A conditional branch to the following instruction (e.g. the delay slot) is
6354 asking for a disaster. I do not think this can happen as this pattern
6355 is only used when optimizing; jump optimization should eliminate the
6356 jump. But be prepared just in case. */
6358 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6361 /* If this is a long branch with its delay slot unfilled, set `nullify'
6362 as it can nullify the delay slot and save a nop. */
6363 if (length == 8 && dbr_sequence_length () == 0)
6366 /* If this is a short forward conditional branch which did not get
6367 its delay slot filled, the delay slot can still be nullified. */
6368 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6369 nullify = forward_branch_p (insn);
6371 /* A forward branch over a single nullified insn can be done with a
6372 extrs instruction. This avoids a single cycle penalty due to
6373 mis-predicted branch if we fall through (branch not taken). */
6376 && next_real_insn (insn) != 0
6377 && get_attr_length (next_real_insn (insn)) == 4
6378 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6385 /* All short conditional branches except backwards with an unfilled
6389 strcpy (buf, "{vextrs,|extrw,s,}");
6391 strcpy (buf, "{bvb,|bb,}");
6392 if (useskip && GET_MODE (operands[0]) == DImode)
6393 strcpy (buf, "extrd,s,*");
6394 else if (GET_MODE (operands[0]) == DImode)
6395 strcpy (buf, "bb,*");
6396 if ((which == 0 && negated)
6397 || (which == 1 && ! negated))
6402 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6403 else if (nullify && negated)
6404 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6405 else if (nullify && ! negated)
6406 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6407 else if (! nullify && negated)
6408 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6409 else if (! nullify && ! negated)
6410 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6413 /* All long conditionals. Note a short backward branch with an
6414 unfilled delay slot is treated just like a long backward branch
6415 with an unfilled delay slot. */
6417 /* Handle weird backwards branch with a filled delay slot
6418 with is nullified. */
6419 if (dbr_sequence_length () != 0
6420 && ! forward_branch_p (insn)
6423 strcpy (buf, "{bvb,|bb,}");
6424 if (GET_MODE (operands[0]) == DImode)
6426 if ((which == 0 && negated)
6427 || (which == 1 && ! negated))
6432 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6434 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6436 /* Handle short backwards branch with an unfilled delay slot.
6437 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6438 taken and untaken branches. */
6439 else if (dbr_sequence_length () == 0
6440 && ! forward_branch_p (insn)
6441 && INSN_ADDRESSES_SET_P ()
6442 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6443 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6445 strcpy (buf, "{bvb,|bb,}");
6446 if (GET_MODE (operands[0]) == DImode)
6448 if ((which == 0 && negated)
6449 || (which == 1 && ! negated))
6454 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6456 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6460 strcpy (buf, "{vextrs,|extrw,s,}");
6461 if (GET_MODE (operands[0]) == DImode)
6462 strcpy (buf, "extrd,s,*");
6463 if ((which == 0 && negated)
6464 || (which == 1 && ! negated))
6468 if (nullify && negated)
6469 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6470 else if (nullify && ! negated)
6471 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6473 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6475 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6485 /* Return the output template for emitting a dbra type insn.
6487 Note it may perform some output operations on its own before
6488 returning the final output string. */
6490 output_dbra (rtx *operands, rtx insn, int which_alternative)
6493 /* A conditional branch to the following instruction (e.g. the delay slot) is
6494 asking for a disaster. Be prepared! */
6496 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6498 if (which_alternative == 0)
6499 return "ldo %1(%0),%0";
6500 else if (which_alternative == 1)
6502 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6503 output_asm_insn ("ldw -16(%%r30),%4", operands);
6504 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6505 return "{fldws|fldw} -16(%%r30),%0";
6509 output_asm_insn ("ldw %0,%4", operands);
6510 return "ldo %1(%4),%4\n\tstw %4,%0";
6514 if (which_alternative == 0)
6516 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6517 int length = get_attr_length (insn);
6519 /* If this is a long branch with its delay slot unfilled, set `nullify'
6520 as it can nullify the delay slot and save a nop. */
6521 if (length == 8 && dbr_sequence_length () == 0)
6524 /* If this is a short forward conditional branch which did not get
6525 its delay slot filled, the delay slot can still be nullified. */
6526 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6527 nullify = forward_branch_p (insn);
6533 return "addib,%C2,n %1,%0,%3";
6535 return "addib,%C2 %1,%0,%3";
6538 /* Handle weird backwards branch with a fulled delay slot
6539 which is nullified. */
6540 if (dbr_sequence_length () != 0
6541 && ! forward_branch_p (insn)
6543 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6544 /* Handle short backwards branch with an unfilled delay slot.
6545 Using a addb;nop rather than addi;bl saves 1 cycle for both
6546 taken and untaken branches. */
6547 else if (dbr_sequence_length () == 0
6548 && ! forward_branch_p (insn)
6549 && INSN_ADDRESSES_SET_P ()
6550 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6551 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6552 return "addib,%C2 %1,%0,%3%#";
6554 /* Handle normal cases. */
6556 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6558 return "addi,%N2 %1,%0,%0\n\tb %3";
6565 /* Deal with gross reload from FP register case. */
6566 else if (which_alternative == 1)
6568 /* Move loop counter from FP register to MEM then into a GR,
6569 increment the GR, store the GR into MEM, and finally reload
6570 the FP register from MEM from within the branch's delay slot. */
6571 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6573 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6574 if (get_attr_length (insn) == 24)
6575 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6577 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6579 /* Deal with gross reload from memory case. */
6582 /* Reload loop counter from memory, the store back to memory
6583 happens in the branch's delay slot. */
6584 output_asm_insn ("ldw %0,%4", operands);
6585 if (get_attr_length (insn) == 12)
6586 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6588 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6592 /* Return the output template for emitting a dbra type insn.
6594 Note it may perform some output operations on its own before
6595 returning the final output string. */
6597 output_movb (rtx *operands, rtx insn, int which_alternative,
6598 int reverse_comparison)
6601 /* A conditional branch to the following instruction (e.g. the delay slot) is
6602 asking for a disaster. Be prepared! */
6604 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6606 if (which_alternative == 0)
6607 return "copy %1,%0";
6608 else if (which_alternative == 1)
6610 output_asm_insn ("stw %1,-16(%%r30)", operands);
6611 return "{fldws|fldw} -16(%%r30),%0";
6613 else if (which_alternative == 2)
6619 /* Support the second variant. */
6620 if (reverse_comparison)
6621 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6623 if (which_alternative == 0)
6625 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6626 int length = get_attr_length (insn);
6628 /* If this is a long branch with its delay slot unfilled, set `nullify'
6629 as it can nullify the delay slot and save a nop. */
6630 if (length == 8 && dbr_sequence_length () == 0)
6633 /* If this is a short forward conditional branch which did not get
6634 its delay slot filled, the delay slot can still be nullified. */
6635 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6636 nullify = forward_branch_p (insn);
6642 return "movb,%C2,n %1,%0,%3";
6644 return "movb,%C2 %1,%0,%3";
6647 /* Handle weird backwards branch with a filled delay slot
6648 which is nullified. */
6649 if (dbr_sequence_length () != 0
6650 && ! forward_branch_p (insn)
6652 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6654 /* Handle short backwards branch with an unfilled delay slot.
6655 Using a movb;nop rather than or;bl saves 1 cycle for both
6656 taken and untaken branches. */
6657 else if (dbr_sequence_length () == 0
6658 && ! forward_branch_p (insn)
6659 && INSN_ADDRESSES_SET_P ()
6660 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6661 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6662 return "movb,%C2 %1,%0,%3%#";
6663 /* Handle normal cases. */
6665 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6667 return "or,%N2 %1,%%r0,%0\n\tb %3";
6673 /* Deal with gross reload from FP register case. */
6674 else if (which_alternative == 1)
6676 /* Move loop counter from FP register to MEM then into a GR,
6677 increment the GR, store the GR into MEM, and finally reload
6678 the FP register from MEM from within the branch's delay slot. */
6679 output_asm_insn ("stw %1,-16(%%r30)", operands);
6680 if (get_attr_length (insn) == 12)
6681 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6683 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6685 /* Deal with gross reload from memory case. */
6686 else if (which_alternative == 2)
6688 /* Reload loop counter from memory, the store back to memory
6689 happens in the branch's delay slot. */
6690 if (get_attr_length (insn) == 8)
6691 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6693 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6695 /* Handle SAR as a destination. */
6698 if (get_attr_length (insn) == 8)
6699 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6701 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
6705 /* Copy any FP arguments in INSN into integer registers. */
6707 copy_fp_args (rtx insn)
6712 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6714 int arg_mode, regno;
6715 rtx use = XEXP (link, 0);
6717 if (! (GET_CODE (use) == USE
6718 && GET_CODE (XEXP (use, 0)) == REG
6719 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6722 arg_mode = GET_MODE (XEXP (use, 0));
6723 regno = REGNO (XEXP (use, 0));
6725 /* Is it a floating point register? */
6726 if (regno >= 32 && regno <= 39)
6728 /* Copy the FP register into an integer register via memory. */
6729 if (arg_mode == SFmode)
6731 xoperands[0] = XEXP (use, 0);
6732 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6733 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6734 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6738 xoperands[0] = XEXP (use, 0);
6739 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6740 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6741 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6742 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6748 /* Compute length of the FP argument copy sequence for INSN. */
6750 length_fp_args (rtx insn)
6755 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6757 int arg_mode, regno;
6758 rtx use = XEXP (link, 0);
6760 if (! (GET_CODE (use) == USE
6761 && GET_CODE (XEXP (use, 0)) == REG
6762 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6765 arg_mode = GET_MODE (XEXP (use, 0));
6766 regno = REGNO (XEXP (use, 0));
6768 /* Is it a floating point register? */
6769 if (regno >= 32 && regno <= 39)
6771 if (arg_mode == SFmode)
6781 /* Return the attribute length for the millicode call instruction INSN.
6782 The length must match the code generated by output_millicode_call.
6783 We include the delay slot in the returned length as it is better to
6784 over estimate the length than to under estimate it. */
6787 attr_length_millicode_call (rtx insn)
6789 unsigned long distance = -1;
6790 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
6792 if (INSN_ADDRESSES_SET_P ())
6794 distance = (total + insn_current_reference_address (insn));
6795 if (distance < total)
6801 if (!TARGET_LONG_CALLS && distance < 7600000)
6806 else if (TARGET_PORTABLE_RUNTIME)
6810 if (!TARGET_LONG_CALLS && distance < 240000)
6813 if (TARGET_LONG_ABS_CALL && !flag_pic)
6820 /* INSN is a function call. It may have an unconditional jump
6823 CALL_DEST is the routine we are calling. */
6826 output_millicode_call (rtx insn, rtx call_dest)
6828 int attr_length = get_attr_length (insn);
6829 int seq_length = dbr_sequence_length ();
6834 xoperands[0] = call_dest;
6835 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6837 /* Handle the common case where we are sure that the branch will
6838 reach the beginning of the $CODE$ subspace. The within reach
6839 form of the $$sh_func_adrs call has a length of 28. Because
6840 it has an attribute type of multi, it never has a nonzero
6841 sequence length. The length of the $$sh_func_adrs is the same
6842 as certain out of reach PIC calls to other routines. */
6843 if (!TARGET_LONG_CALLS
6844 && ((seq_length == 0
6845 && (attr_length == 12
6846 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6847 || (seq_length != 0 && attr_length == 8)))
6849 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6855 /* It might seem that one insn could be saved by accessing
6856 the millicode function using the linkage table. However,
6857 this doesn't work in shared libraries and other dynamically
6858 loaded objects. Using a pc-relative sequence also avoids
6859 problems related to the implicit use of the gp register. */
6860 output_asm_insn ("b,l .+8,%%r1", xoperands);
6864 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6865 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6869 xoperands[1] = gen_label_rtx ();
6870 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6871 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6872 CODE_LABEL_NUMBER (xoperands[1]));
6873 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6876 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6878 else if (TARGET_PORTABLE_RUNTIME)
6880 /* Pure portable runtime doesn't allow be/ble; we also don't
6881 have PIC support in the assembler/linker, so this sequence
6884 /* Get the address of our target into %r1. */
6885 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6886 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6888 /* Get our return address into %r31. */
6889 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
6890 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
6892 /* Jump to our target address in %r1. */
6893 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6897 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6899 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
6901 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6905 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6906 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
6908 if (TARGET_SOM || !TARGET_GAS)
6910 /* The HP assembler can generate relocations for the
6911 difference of two symbols. GAS can do this for a
6912 millicode symbol but not an arbitrary external
6913 symbol when generating SOM output. */
6914 xoperands[1] = gen_label_rtx ();
6915 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6916 CODE_LABEL_NUMBER (xoperands[1]));
6917 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6918 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6922 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
6923 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
6927 /* Jump to our target address in %r1. */
6928 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6932 if (seq_length == 0)
6933 output_asm_insn ("nop", xoperands);
6935 /* We are done if there isn't a jump in the delay slot. */
6936 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6939 /* This call has an unconditional jump in its delay slot. */
6940 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6942 /* See if the return address can be adjusted. Use the containing
6943 sequence insn's address. */
6944 if (INSN_ADDRESSES_SET_P ())
6946 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6947 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6948 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6950 if (VAL_14_BITS_P (distance))
6952 xoperands[1] = gen_label_rtx ();
6953 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
6954 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6955 CODE_LABEL_NUMBER (xoperands[1]));
6958 /* ??? This branch may not reach its target. */
6959 output_asm_insn ("nop\n\tb,n %0", xoperands);
6962 /* ??? This branch may not reach its target. */
6963 output_asm_insn ("nop\n\tb,n %0", xoperands);
6965 /* Delete the jump. */
6966 PUT_CODE (NEXT_INSN (insn), NOTE);
6967 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6968 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6973 /* Return the attribute length of the call instruction INSN. The SIBCALL
6974 flag indicates whether INSN is a regular call or a sibling call. The
6975 length returned must be longer than the code actually generated by
6976 output_call. Since branch shortening is done before delay branch
6977 sequencing, there is no way to determine whether or not the delay
6978 slot will be filled during branch shortening. Even when the delay
6979 slot is filled, we may have to add a nop if the delay slot contains
6980 a branch that can't reach its target. Thus, we always have to include
6981 the delay slot in the length estimate. This used to be done in
6982 pa_adjust_insn_length but we do it here now as some sequences always
6983 fill the delay slot and we can save four bytes in the estimate for
6987 attr_length_call (rtx insn, int sibcall)
6993 rtx pat = PATTERN (insn);
6994 unsigned long distance = -1;
6996 if (INSN_ADDRESSES_SET_P ())
6998 unsigned long total;
7000 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7001 distance = (total + insn_current_reference_address (insn));
7002 if (distance < total)
7006 /* Determine if this is a local call. */
7007 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7008 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7010 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7012 call_decl = SYMBOL_REF_DECL (call_dest);
7013 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7015 /* pc-relative branch. */
7016 if (!TARGET_LONG_CALLS
7017 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7018 || distance < 240000))
7021 /* 64-bit plabel sequence. */
7022 else if (TARGET_64BIT && !local_call)
7023 length += sibcall ? 28 : 24;
7025 /* non-pic long absolute branch sequence. */
7026 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7029 /* long pc-relative branch sequence. */
7030 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7031 || (TARGET_64BIT && !TARGET_GAS)
7032 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7036 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7040 /* 32-bit plabel sequence. */
7046 length += length_fp_args (insn);
7056 if (!TARGET_NO_SPACE_REGS)
7064 /* INSN is a function call. It may have an unconditional jump
7067 CALL_DEST is the routine we are calling. */
7070 output_call (rtx insn, rtx call_dest, int sibcall)
7072 int delay_insn_deleted = 0;
7073 int delay_slot_filled = 0;
7074 int seq_length = dbr_sequence_length ();
7075 tree call_decl = SYMBOL_REF_DECL (call_dest);
7076 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7079 xoperands[0] = call_dest;
7081 /* Handle the common case where we're sure that the branch will reach
7082 the beginning of the "$CODE$" subspace. This is the beginning of
7083 the current function if we are in a named section. */
7084 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7086 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7087 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7091 if (TARGET_64BIT && !local_call)
7093 /* ??? As far as I can tell, the HP linker doesn't support the
7094 long pc-relative sequence described in the 64-bit runtime
7095 architecture. So, we use a slightly longer indirect call. */
7096 struct deferred_plabel *p = get_plabel (call_dest);
7098 xoperands[0] = p->internal_label;
7099 xoperands[1] = gen_label_rtx ();
7101 /* If this isn't a sibcall, we put the load of %r27 into the
7102 delay slot. We can't do this in a sibcall as we don't
7103 have a second call-clobbered scratch register available. */
7105 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7108 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7111 /* Now delete the delay insn. */
7112 PUT_CODE (NEXT_INSN (insn), NOTE);
7113 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7114 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7115 delay_insn_deleted = 1;
7118 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7119 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7120 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7124 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7125 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7126 output_asm_insn ("bve (%%r1)", xoperands);
7130 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7131 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7132 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7133 delay_slot_filled = 1;
7138 int indirect_call = 0;
7140 /* Emit a long call. There are several different sequences
7141 of increasing length and complexity. In most cases,
7142 they don't allow an instruction in the delay slot. */
7143 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7144 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7145 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7150 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7152 && (!TARGET_PA_20 || indirect_call))
7154 /* A non-jump insn in the delay slot. By definition we can
7155 emit this insn before the call (and in fact before argument
7157 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7160 /* Now delete the delay insn. */
7161 PUT_CODE (NEXT_INSN (insn), NOTE);
7162 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7163 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7164 delay_insn_deleted = 1;
7167 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7169 /* This is the best sequence for making long calls in
7170 non-pic code. Unfortunately, GNU ld doesn't provide
7171 the stub needed for external calls, and GAS's support
7172 for this with the SOM linker is buggy. It is safe
7173 to use this for local calls. */
7174 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7176 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7180 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7183 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7185 output_asm_insn ("copy %%r31,%%r2", xoperands);
7186 delay_slot_filled = 1;
7191 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7192 || (TARGET_64BIT && !TARGET_GAS))
7194 /* The HP assembler and linker can handle relocations
7195 for the difference of two symbols. GAS and the HP
7196 linker can't do this when one of the symbols is
7198 xoperands[1] = gen_label_rtx ();
7199 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7200 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7201 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7202 CODE_LABEL_NUMBER (xoperands[1]));
7203 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7205 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7207 /* GAS currently can't generate the relocations that
7208 are needed for the SOM linker under HP-UX using this
7209 sequence. The GNU linker doesn't generate the stubs
7210 that are needed for external calls on TARGET_ELF32
7211 with this sequence. For now, we have to use a
7212 longer plabel sequence when using GAS. */
7213 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7214 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7216 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7221 /* Emit a long plabel-based call sequence. This is
7222 essentially an inline implementation of $$dyncall.
7223 We don't actually try to call $$dyncall as this is
7224 as difficult as calling the function itself. */
7225 struct deferred_plabel *p = get_plabel (call_dest);
7227 xoperands[0] = p->internal_label;
7228 xoperands[1] = gen_label_rtx ();
7230 /* Since the call is indirect, FP arguments in registers
7231 need to be copied to the general registers. Then, the
7232 argument relocation stub will copy them back. */
7234 copy_fp_args (insn);
7238 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7239 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7240 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7244 output_asm_insn ("addil LR'%0-$global$,%%r27",
7246 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7250 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7251 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7252 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7253 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7255 if (!sibcall && !TARGET_PA_20)
7257 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7258 if (TARGET_NO_SPACE_REGS)
7259 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7261 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7268 output_asm_insn ("bve (%%r1)", xoperands);
7273 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7274 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7275 delay_slot_filled = 1;
7278 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7283 if (!TARGET_NO_SPACE_REGS)
7284 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7289 if (TARGET_NO_SPACE_REGS)
7290 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7292 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7296 if (TARGET_NO_SPACE_REGS)
7297 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7299 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7302 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7304 output_asm_insn ("copy %%r31,%%r2", xoperands);
7305 delay_slot_filled = 1;
7312 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7313 output_asm_insn ("nop", xoperands);
7315 /* We are done if there isn't a jump in the delay slot. */
7317 || delay_insn_deleted
7318 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7321 /* A sibcall should never have a branch in the delay slot. */
7322 gcc_assert (!sibcall);
7324 /* This call has an unconditional jump in its delay slot. */
7325 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7327 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7329 /* See if the return address can be adjusted. Use the containing
7330 sequence insn's address. */
7331 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7332 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7333 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7335 if (VAL_14_BITS_P (distance))
7337 xoperands[1] = gen_label_rtx ();
7338 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7339 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7340 CODE_LABEL_NUMBER (xoperands[1]));
7343 output_asm_insn ("nop\n\tb,n %0", xoperands);
7346 output_asm_insn ("b,n %0", xoperands);
7348 /* Delete the jump. */
7349 PUT_CODE (NEXT_INSN (insn), NOTE);
7350 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7351 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7356 /* Return the attribute length of the indirect call instruction INSN.
7357 The length must match the code generated by output_indirect call.
7358 The returned length includes the delay slot. Currently, the delay
7359 slot of an indirect call sequence is not exposed and it is used by
7360 the sequence itself. */
7363 attr_length_indirect_call (rtx insn)
7365 unsigned long distance = -1;
7366 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7368 if (INSN_ADDRESSES_SET_P ())
7370 distance = (total + insn_current_reference_address (insn));
7371 if (distance < total)
7378 if (TARGET_FAST_INDIRECT_CALLS
7379 || (!TARGET_PORTABLE_RUNTIME
7380 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7386 if (TARGET_PORTABLE_RUNTIME)
7389 /* Out of reach, can use ble. */
7394 output_indirect_call (rtx insn, rtx call_dest)
7400 xoperands[0] = call_dest;
7401 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7402 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7406 /* First the special case for kernels, level 0 systems, etc. */
7407 if (TARGET_FAST_INDIRECT_CALLS)
7408 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7410 /* Now the normal case -- we can reach $$dyncall directly or
7411 we're sure that we can get there via a long-branch stub.
7413 No need to check target flags as the length uniquely identifies
7414 the remaining cases. */
7415 if (attr_length_indirect_call (insn) == 8)
7417 /* The HP linker substitutes a BLE for millicode calls using
7418 the short PIC PCREL form. Thus, we must use %r31 as the
7419 link register when generating PA 1.x code. */
7421 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7423 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7426 /* Long millicode call, but we are not generating PIC or portable runtime
7428 if (attr_length_indirect_call (insn) == 12)
7429 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7431 /* Long millicode call for portable runtime. */
7432 if (attr_length_indirect_call (insn) == 20)
7433 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7435 /* We need a long PIC call to $$dyncall. */
7436 xoperands[0] = NULL_RTX;
7437 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7438 if (TARGET_SOM || !TARGET_GAS)
7440 xoperands[0] = gen_label_rtx ();
7441 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7442 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7443 CODE_LABEL_NUMBER (xoperands[0]));
7444 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7448 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7449 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7452 output_asm_insn ("blr %%r0,%%r2", xoperands);
7453 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7457 /* Return the total length of the save and restore instructions needed for
7458 the data linkage table pointer (i.e., the PIC register) across the call
7459 instruction INSN. No-return calls do not require a save and restore.
7460 In addition, we may be able to avoid the save and restore for calls
7461 within the same translation unit. */
7464 attr_length_save_restore_dltp (rtx insn)
7466 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7472 /* In HPUX 8.0's shared library scheme, special relocations are needed
7473 for function labels if they might be passed to a function
7474 in a shared library (because shared libraries don't live in code
7475 space), and special magic is needed to construct their address. */
7478 hppa_encode_label (rtx sym)
7480 const char *str = XSTR (sym, 0);
7481 int len = strlen (str) + 1;
7484 p = newstr = alloca (len + 1);
7488 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7492 pa_encode_section_info (tree decl, rtx rtl, int first)
7494 default_encode_section_info (decl, rtl, first);
7496 if (first && TEXT_SPACE_P (decl))
7498 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7499 if (TREE_CODE (decl) == FUNCTION_DECL)
7500 hppa_encode_label (XEXP (rtl, 0));
7504 /* This is sort of inverse to pa_encode_section_info. */
7507 pa_strip_name_encoding (const char *str)
7509 str += (*str == '@');
7510 str += (*str == '*');
7515 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7517 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7520 /* Returns 1 if OP is a function label involved in a simple addition
7521 with a constant. Used to keep certain patterns from matching
7522 during instruction combination. */
7524 is_function_label_plus_const (rtx op)
7526 /* Strip off any CONST. */
7527 if (GET_CODE (op) == CONST)
7530 return (GET_CODE (op) == PLUS
7531 && function_label_operand (XEXP (op, 0), Pmode)
7532 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7535 /* Output assembly code for a thunk to FUNCTION. */
7538 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7539 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7542 static unsigned int current_thunk_number;
7543 int val_14 = VAL_14_BITS_P (delta);
7548 xoperands[0] = XEXP (DECL_RTL (function), 0);
7549 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
7550 xoperands[2] = GEN_INT (delta);
7552 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
7553 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7555 /* Output the thunk. We know that the function is in the same
7556 translation unit (i.e., the same space) as the thunk, and that
7557 thunks are output after their method. Thus, we don't need an
7558 external branch to reach the function. With SOM and GAS,
7559 functions and thunks are effectively in different sections.
7560 Thus, we can always use a IA-relative branch and the linker
7561 will add a long branch stub if necessary.
7563 However, we have to be careful when generating PIC code on the
7564 SOM port to ensure that the sequence does not transfer to an
7565 import stub for the target function as this could clobber the
7566 return value saved at SP-24. This would also apply to the
7567 32-bit linux port if the multi-space model is implemented. */
7568 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7569 && !(flag_pic && TREE_PUBLIC (function))
7570 && (TARGET_GAS || last_address < 262132))
7571 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7572 && ((targetm.have_named_sections
7573 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7574 /* The GNU 64-bit linker has rather poor stub management.
7575 So, we use a long branch from thunks that aren't in
7576 the same section as the target function. */
7578 && (DECL_SECTION_NAME (thunk_fndecl)
7579 != DECL_SECTION_NAME (function)))
7580 || ((DECL_SECTION_NAME (thunk_fndecl)
7581 == DECL_SECTION_NAME (function))
7582 && last_address < 262132)))
7583 || (!targetm.have_named_sections && last_address < 262132))))
7586 output_asm_insn ("addil L'%2,%%r26", xoperands);
7588 output_asm_insn ("b %0", xoperands);
7592 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7597 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7601 else if (TARGET_64BIT)
7603 /* We only have one call-clobbered scratch register, so we can't
7604 make use of the delay slot if delta doesn't fit in 14 bits. */
7607 output_asm_insn ("addil L'%2,%%r26", xoperands);
7608 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7611 output_asm_insn ("b,l .+8,%%r1", xoperands);
7615 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7616 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7620 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
7621 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
7626 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7627 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7632 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
7636 else if (TARGET_PORTABLE_RUNTIME)
7638 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7639 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
7642 output_asm_insn ("addil L'%2,%%r26", xoperands);
7644 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7648 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7653 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7657 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7659 /* The function is accessible from outside this module. The only
7660 way to avoid an import stub between the thunk and function is to
7661 call the function directly with an indirect sequence similar to
7662 that used by $$dyncall. This is possible because $$dyncall acts
7663 as the import stub in an indirect call. */
7664 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7665 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
7666 output_asm_insn ("addil LT'%3,%%r19", xoperands);
7667 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
7668 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7669 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
7670 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
7671 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
7672 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7676 output_asm_insn ("addil L'%2,%%r26", xoperands);
7682 output_asm_insn ("bve (%%r22)", xoperands);
7685 else if (TARGET_NO_SPACE_REGS)
7687 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
7692 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
7693 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
7694 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
7699 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7701 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7705 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7707 if (TARGET_SOM || !TARGET_GAS)
7709 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
7710 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
7714 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7715 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
7719 output_asm_insn ("addil L'%2,%%r26", xoperands);
7721 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7725 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7730 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7737 output_asm_insn ("addil L'%2,%%r26", xoperands);
7739 output_asm_insn ("ldil L'%0,%%r22", xoperands);
7740 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
7744 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7749 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7754 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7756 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7759 output_asm_insn (".align 4", xoperands);
7760 ASM_OUTPUT_LABEL (file, label);
7761 output_asm_insn (".word P'%0", xoperands);
7763 else if (TARGET_SOM && TARGET_GAS)
7766 current_thunk_number++;
7767 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
7768 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
7769 last_address += nbytes;
7770 update_total_code_bytes (nbytes);
7773 /* Only direct calls to static functions are allowed to be sibling (tail)
7776 This restriction is necessary because some linker generated stubs will
7777 store return pointers into rp' in some cases which might clobber a
7778 live value already in rp'.
7780 In a sibcall the current function and the target function share stack
7781 space. Thus if the path to the current function and the path to the
7782 target function save a value in rp', they save the value into the
7783 same stack slot, which has undesirable consequences.
7785 Because of the deferred binding nature of shared libraries any function
7786 with external scope could be in a different load module and thus require
7787 rp' to be saved when calling that function. So sibcall optimizations
7788 can only be safe for static function.
7790 Note that GCC never needs return value relocations, so we don't have to
7791 worry about static calls with return value relocations (which require
7794 It is safe to perform a sibcall optimization when the target function
7795 will never return. */
7797 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7799 if (TARGET_PORTABLE_RUNTIME)
7802 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7803 single subspace mode and the call is not indirect. As far as I know,
7804 there is no operating system support for the multiple subspace mode.
7805 It might be possible to support indirect calls if we didn't use
7806 $$dyncall (see the indirect sequence generated in output_call). */
7808 return (decl != NULL_TREE);
7810 /* Sibcalls are not ok because the arg pointer register is not a fixed
7811 register. This prevents the sibcall optimization from occurring. In
7812 addition, there are problems with stub placement using GNU ld. This
7813 is because a normal sibcall branch uses a 17-bit relocation while
7814 a regular call branch uses a 22-bit relocation. As a result, more
7815 care needs to be taken in the placement of long-branch stubs. */
7819 /* Sibcalls are only ok within a translation unit. */
7820 return (decl && !TREE_PUBLIC (decl));
7823 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7824 use in fmpyadd instructions. */
7826 fmpyaddoperands (rtx *operands)
7828 enum machine_mode mode = GET_MODE (operands[0]);
7830 /* Must be a floating point mode. */
7831 if (mode != SFmode && mode != DFmode)
7834 /* All modes must be the same. */
7835 if (! (mode == GET_MODE (operands[1])
7836 && mode == GET_MODE (operands[2])
7837 && mode == GET_MODE (operands[3])
7838 && mode == GET_MODE (operands[4])
7839 && mode == GET_MODE (operands[5])))
7842 /* All operands must be registers. */
7843 if (! (GET_CODE (operands[1]) == REG
7844 && GET_CODE (operands[2]) == REG
7845 && GET_CODE (operands[3]) == REG
7846 && GET_CODE (operands[4]) == REG
7847 && GET_CODE (operands[5]) == REG))
7850 /* Only 2 real operands to the addition. One of the input operands must
7851 be the same as the output operand. */
7852 if (! rtx_equal_p (operands[3], operands[4])
7853 && ! rtx_equal_p (operands[3], operands[5]))
7856 /* Inout operand of add cannot conflict with any operands from multiply. */
7857 if (rtx_equal_p (operands[3], operands[0])
7858 || rtx_equal_p (operands[3], operands[1])
7859 || rtx_equal_p (operands[3], operands[2]))
7862 /* multiply cannot feed into addition operands. */
7863 if (rtx_equal_p (operands[4], operands[0])
7864 || rtx_equal_p (operands[5], operands[0]))
7867 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7869 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7870 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7871 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7872 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7873 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7874 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7877 /* Passed. Operands are suitable for fmpyadd. */
7881 #if !defined(USE_COLLECT2)
7883 pa_asm_out_constructor (rtx symbol, int priority)
7885 if (!function_label_operand (symbol, VOIDmode))
7886 hppa_encode_label (symbol);
7888 #ifdef CTORS_SECTION_ASM_OP
7889 default_ctor_section_asm_out_constructor (symbol, priority);
7891 # ifdef TARGET_ASM_NAMED_SECTION
7892 default_named_section_asm_out_constructor (symbol, priority);
7894 default_stabs_asm_out_constructor (symbol, priority);
7900 pa_asm_out_destructor (rtx symbol, int priority)
7902 if (!function_label_operand (symbol, VOIDmode))
7903 hppa_encode_label (symbol);
7905 #ifdef DTORS_SECTION_ASM_OP
7906 default_dtor_section_asm_out_destructor (symbol, priority);
7908 # ifdef TARGET_ASM_NAMED_SECTION
7909 default_named_section_asm_out_destructor (symbol, priority);
7911 default_stabs_asm_out_destructor (symbol, priority);
7917 /* This function places uninitialized global data in the bss section.
7918 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
7919 function on the SOM port to prevent uninitialized global data from
7920 being placed in the data section. */
7923 pa_asm_output_aligned_bss (FILE *stream,
7925 unsigned HOST_WIDE_INT size,
7929 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7931 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7932 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7935 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7936 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7939 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7940 ASM_OUTPUT_LABEL (stream, name);
7941 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
7944 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
7945 that doesn't allow the alignment of global common storage to be directly
7946 specified. The SOM linker aligns common storage based on the rounded
7947 value of the NUM_BYTES parameter in the .comm directive. It's not
7948 possible to use the .align directive as it doesn't affect the alignment
7949 of the label associated with a .comm directive. */
7952 pa_asm_output_aligned_common (FILE *stream,
7954 unsigned HOST_WIDE_INT size,
7957 unsigned int max_common_align;
7959 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
7960 if (align > max_common_align)
7962 warning (0, "alignment (%u) for %s exceeds maximum alignment "
7963 "for global common data. Using %u",
7964 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
7965 align = max_common_align;
7970 assemble_name (stream, name);
7971 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
7972 MAX (size, align / BITS_PER_UNIT));
7975 /* We can't use .comm for local common storage as the SOM linker effectively
7976 treats the symbol as universal and uses the same storage for local symbols
7977 with the same name in different object files. The .block directive
7978 reserves an uninitialized block of storage. However, it's not common
7979 storage. Fortunately, GCC never requests common storage with the same
7980 name in any given translation unit. */
7983 pa_asm_output_aligned_local (FILE *stream,
7985 unsigned HOST_WIDE_INT size,
7989 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7992 fprintf (stream, "%s", LOCAL_ASM_OP);
7993 assemble_name (stream, name);
7994 fprintf (stream, "\n");
7997 ASM_OUTPUT_LABEL (stream, name);
7998 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8001 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8002 use in fmpysub instructions. */
8004 fmpysuboperands (rtx *operands)
8006 enum machine_mode mode = GET_MODE (operands[0]);
8008 /* Must be a floating point mode. */
8009 if (mode != SFmode && mode != DFmode)
8012 /* All modes must be the same. */
8013 if (! (mode == GET_MODE (operands[1])
8014 && mode == GET_MODE (operands[2])
8015 && mode == GET_MODE (operands[3])
8016 && mode == GET_MODE (operands[4])
8017 && mode == GET_MODE (operands[5])))
8020 /* All operands must be registers. */
8021 if (! (GET_CODE (operands[1]) == REG
8022 && GET_CODE (operands[2]) == REG
8023 && GET_CODE (operands[3]) == REG
8024 && GET_CODE (operands[4]) == REG
8025 && GET_CODE (operands[5]) == REG))
8028 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8029 operation, so operands[4] must be the same as operand[3]. */
8030 if (! rtx_equal_p (operands[3], operands[4]))
8033 /* multiply cannot feed into subtraction. */
8034 if (rtx_equal_p (operands[5], operands[0]))
8037 /* Inout operand of sub cannot conflict with any operands from multiply. */
8038 if (rtx_equal_p (operands[3], operands[0])
8039 || rtx_equal_p (operands[3], operands[1])
8040 || rtx_equal_p (operands[3], operands[2]))
8043 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8045 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8046 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8047 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8048 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8049 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8050 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8053 /* Passed. Operands are suitable for fmpysub. */
8057 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8058 constants for shadd instructions. */
8060 shadd_constant_p (int val)
8062 if (val == 2 || val == 4 || val == 8)
8068 /* Return 1 if OP is valid as a base or index register in a
8072 borx_reg_operand (rtx op, enum machine_mode mode)
8074 if (GET_CODE (op) != REG)
8077 /* We must reject virtual registers as the only expressions that
8078 can be instantiated are REG and REG+CONST. */
8079 if (op == virtual_incoming_args_rtx
8080 || op == virtual_stack_vars_rtx
8081 || op == virtual_stack_dynamic_rtx
8082 || op == virtual_outgoing_args_rtx
8083 || op == virtual_cfa_rtx)
8086 /* While it's always safe to index off the frame pointer, it's not
8087 profitable to do so when the frame pointer is being eliminated. */
8088 if (!reload_completed
8089 && flag_omit_frame_pointer
8090 && !current_function_calls_alloca
8091 && op == frame_pointer_rtx)
8094 return register_operand (op, mode);
8097 /* Return 1 if this operand is anything other than a hard register. */
8100 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8102 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8105 /* Return 1 if INSN branches forward. Should be using insn_addresses
8106 to avoid walking through all the insns... */
8108 forward_branch_p (rtx insn)
8110 rtx label = JUMP_LABEL (insn);
8117 insn = NEXT_INSN (insn);
8120 return (insn == label);
8123 /* Return 1 if OP is an equality comparison, else return 0. */
8125 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8127 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8130 /* Return 1 if INSN is in the delay slot of a call instruction. */
8132 jump_in_call_delay (rtx insn)
8135 if (GET_CODE (insn) != JUMP_INSN)
8138 if (PREV_INSN (insn)
8139 && PREV_INSN (PREV_INSN (insn))
8140 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8142 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8144 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8145 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8152 /* Output an unconditional move and branch insn. */
8155 output_parallel_movb (rtx *operands, int length)
8157 /* These are the cases in which we win. */
8159 return "mov%I1b,tr %1,%0,%2";
8161 /* None of these cases wins, but they don't lose either. */
8162 if (dbr_sequence_length () == 0)
8164 /* Nothing in the delay slot, fake it by putting the combined
8165 insn (the copy or add) in the delay slot of a bl. */
8166 if (GET_CODE (operands[1]) == CONST_INT)
8167 return "b %2\n\tldi %1,%0";
8169 return "b %2\n\tcopy %1,%0";
8173 /* Something in the delay slot, but we've got a long branch. */
8174 if (GET_CODE (operands[1]) == CONST_INT)
8175 return "ldi %1,%0\n\tb %2";
8177 return "copy %1,%0\n\tb %2";
8181 /* Output an unconditional add and branch insn. */
8184 output_parallel_addb (rtx *operands, int length)
8186 /* To make life easy we want operand0 to be the shared input/output
8187 operand and operand1 to be the readonly operand. */
8188 if (operands[0] == operands[1])
8189 operands[1] = operands[2];
8191 /* These are the cases in which we win. */
8193 return "add%I1b,tr %1,%0,%3";
8195 /* None of these cases win, but they don't lose either. */
8196 if (dbr_sequence_length () == 0)
8198 /* Nothing in the delay slot, fake it by putting the combined
8199 insn (the copy or add) in the delay slot of a bl. */
8200 return "b %3\n\tadd%I1 %1,%0,%0";
8204 /* Something in the delay slot, but we've got a long branch. */
8205 return "add%I1 %1,%0,%0\n\tb %3";
8209 /* Return nonzero if INSN (a jump insn) immediately follows a call
8210 to a named function. This is used to avoid filling the delay slot
8211 of the jump since it can usually be eliminated by modifying RP in
8212 the delay slot of the call. */
8215 following_call (rtx insn)
8217 if (! TARGET_JUMP_IN_DELAY)
8220 /* Find the previous real insn, skipping NOTEs. */
8221 insn = PREV_INSN (insn);
8222 while (insn && GET_CODE (insn) == NOTE)
8223 insn = PREV_INSN (insn);
8225 /* Check for CALL_INSNs and millicode calls. */
8227 && ((GET_CODE (insn) == CALL_INSN
8228 && get_attr_type (insn) != TYPE_DYNCALL)
8229 || (GET_CODE (insn) == INSN
8230 && GET_CODE (PATTERN (insn)) != SEQUENCE
8231 && GET_CODE (PATTERN (insn)) != USE
8232 && GET_CODE (PATTERN (insn)) != CLOBBER
8233 && get_attr_type (insn) == TYPE_MILLI)))
8239 /* We use this hook to perform a PA specific optimization which is difficult
8240 to do in earlier passes.
8242 We want the delay slots of branches within jump tables to be filled.
8243 None of the compiler passes at the moment even has the notion that a
8244 PA jump table doesn't contain addresses, but instead contains actual
8247 Because we actually jump into the table, the addresses of each entry
8248 must stay constant in relation to the beginning of the table (which
8249 itself must stay constant relative to the instruction to jump into
8250 it). I don't believe we can guarantee earlier passes of the compiler
8251 will adhere to those rules.
8253 So, late in the compilation process we find all the jump tables, and
8254 expand them into real code -- e.g. each entry in the jump table vector
8255 will get an appropriate label followed by a jump to the final target.
8257 Reorg and the final jump pass can then optimize these branches and
8258 fill their delay slots. We end up with smaller, more efficient code.
8260 The jump instructions within the table are special; we must be able
8261 to identify them during assembly output (if the jumps don't get filled
8262 we need to emit a nop rather than nullifying the delay slot)). We
8263 identify jumps in switch tables by using insns with the attribute
8264 type TYPE_BTABLE_BRANCH.
8266 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8267 insns. This serves two purposes, first it prevents jump.c from
8268 noticing that the last N entries in the table jump to the instruction
8269 immediately after the table and deleting the jumps. Second, those
8270 insns mark where we should emit .begin_brtab and .end_brtab directives
8271 when using GAS (allows for better link time optimizations). */
8278 remove_useless_addtr_insns (1);
8280 if (pa_cpu < PROCESSOR_8000)
8281 pa_combine_instructions ();
8284 /* This is fairly cheap, so always run it if optimizing. */
8285 if (optimize > 0 && !TARGET_BIG_SWITCH)
8287 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8288 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8290 rtx pattern, tmp, location, label;
8291 unsigned int length, i;
8293 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8294 if (GET_CODE (insn) != JUMP_INSN
8295 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8296 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8299 /* Emit marker for the beginning of the branch table. */
8300 emit_insn_before (gen_begin_brtab (), insn);
8302 pattern = PATTERN (insn);
8303 location = PREV_INSN (insn);
8304 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8306 for (i = 0; i < length; i++)
8308 /* Emit a label before each jump to keep jump.c from
8309 removing this code. */
8310 tmp = gen_label_rtx ();
8311 LABEL_NUSES (tmp) = 1;
8312 emit_label_after (tmp, location);
8313 location = NEXT_INSN (location);
8315 if (GET_CODE (pattern) == ADDR_VEC)
8316 label = XEXP (XVECEXP (pattern, 0, i), 0);
8318 label = XEXP (XVECEXP (pattern, 1, i), 0);
8320 tmp = gen_short_jump (label);
8322 /* Emit the jump itself. */
8323 tmp = emit_jump_insn_after (tmp, location);
8324 JUMP_LABEL (tmp) = label;
8325 LABEL_NUSES (label)++;
8326 location = NEXT_INSN (location);
8328 /* Emit a BARRIER after the jump. */
8329 emit_barrier_after (location);
8330 location = NEXT_INSN (location);
8333 /* Emit marker for the end of the branch table. */
8334 emit_insn_before (gen_end_brtab (), location);
8335 location = NEXT_INSN (location);
8336 emit_barrier_after (location);
8338 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8344 /* Still need brtab marker insns. FIXME: the presence of these
8345 markers disables output of the branch table to readonly memory,
8346 and any alignment directives that might be needed. Possibly,
8347 the begin_brtab insn should be output before the label for the
8348 table. This doesn't matter at the moment since the tables are
8349 always output in the text section. */
8350 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8352 /* Find an ADDR_VEC insn. */
8353 if (GET_CODE (insn) != JUMP_INSN
8354 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8355 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8358 /* Now generate markers for the beginning and end of the
8360 emit_insn_before (gen_begin_brtab (), insn);
8361 emit_insn_after (gen_end_brtab (), insn);
8366 /* The PA has a number of odd instructions which can perform multiple
8367 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8368 it may be profitable to combine two instructions into one instruction
8369 with two outputs. It's not profitable PA2.0 machines because the
8370 two outputs would take two slots in the reorder buffers.
8372 This routine finds instructions which can be combined and combines
8373 them. We only support some of the potential combinations, and we
8374 only try common ways to find suitable instructions.
8376 * addb can add two registers or a register and a small integer
8377 and jump to a nearby (+-8k) location. Normally the jump to the
8378 nearby location is conditional on the result of the add, but by
8379 using the "true" condition we can make the jump unconditional.
8380 Thus addb can perform two independent operations in one insn.
8382 * movb is similar to addb in that it can perform a reg->reg
8383 or small immediate->reg copy and jump to a nearby (+-8k location).
8385 * fmpyadd and fmpysub can perform a FP multiply and either an
8386 FP add or FP sub if the operands of the multiply and add/sub are
8387 independent (there are other minor restrictions). Note both
8388 the fmpy and fadd/fsub can in theory move to better spots according
8389 to data dependencies, but for now we require the fmpy stay at a
8392 * Many of the memory operations can perform pre & post updates
8393 of index registers. GCC's pre/post increment/decrement addressing
8394 is far too simple to take advantage of all the possibilities. This
8395 pass may not be suitable since those insns may not be independent.
8397 * comclr can compare two ints or an int and a register, nullify
8398 the following instruction and zero some other register. This
8399 is more difficult to use as it's harder to find an insn which
8400 will generate a comclr than finding something like an unconditional
8401 branch. (conditional moves & long branches create comclr insns).
8403 * Most arithmetic operations can conditionally skip the next
8404 instruction. They can be viewed as "perform this operation
8405 and conditionally jump to this nearby location" (where nearby
8406 is an insns away). These are difficult to use due to the
8407 branch length restrictions. */
8410 pa_combine_instructions (void)
8414 /* This can get expensive since the basic algorithm is on the
8415 order of O(n^2) (or worse). Only do it for -O2 or higher
8416 levels of optimization. */
8420 /* Walk down the list of insns looking for "anchor" insns which
8421 may be combined with "floating" insns. As the name implies,
8422 "anchor" instructions don't move, while "floating" insns may
8424 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8425 new = make_insn_raw (new);
8427 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8429 enum attr_pa_combine_type anchor_attr;
8430 enum attr_pa_combine_type floater_attr;
8432 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8433 Also ignore any special USE insns. */
8434 if ((GET_CODE (anchor) != INSN
8435 && GET_CODE (anchor) != JUMP_INSN
8436 && GET_CODE (anchor) != CALL_INSN)
8437 || GET_CODE (PATTERN (anchor)) == USE
8438 || GET_CODE (PATTERN (anchor)) == CLOBBER
8439 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8440 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8443 anchor_attr = get_attr_pa_combine_type (anchor);
8444 /* See if anchor is an insn suitable for combination. */
8445 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8446 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8447 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8448 && ! forward_branch_p (anchor)))
8452 for (floater = PREV_INSN (anchor);
8454 floater = PREV_INSN (floater))
8456 if (GET_CODE (floater) == NOTE
8457 || (GET_CODE (floater) == INSN
8458 && (GET_CODE (PATTERN (floater)) == USE
8459 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8462 /* Anything except a regular INSN will stop our search. */
8463 if (GET_CODE (floater) != INSN
8464 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8465 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8471 /* See if FLOATER is suitable for combination with the
8473 floater_attr = get_attr_pa_combine_type (floater);
8474 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8475 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8476 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8477 && floater_attr == PA_COMBINE_TYPE_FMPY))
8479 /* If ANCHOR and FLOATER can be combined, then we're
8480 done with this pass. */
8481 if (pa_can_combine_p (new, anchor, floater, 0,
8482 SET_DEST (PATTERN (floater)),
8483 XEXP (SET_SRC (PATTERN (floater)), 0),
8484 XEXP (SET_SRC (PATTERN (floater)), 1)))
8488 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8489 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8491 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8493 if (pa_can_combine_p (new, anchor, floater, 0,
8494 SET_DEST (PATTERN (floater)),
8495 XEXP (SET_SRC (PATTERN (floater)), 0),
8496 XEXP (SET_SRC (PATTERN (floater)), 1)))
8501 if (pa_can_combine_p (new, anchor, floater, 0,
8502 SET_DEST (PATTERN (floater)),
8503 SET_SRC (PATTERN (floater)),
8504 SET_SRC (PATTERN (floater))))
8510 /* If we didn't find anything on the backwards scan try forwards. */
8512 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8513 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8515 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8517 if (GET_CODE (floater) == NOTE
8518 || (GET_CODE (floater) == INSN
8519 && (GET_CODE (PATTERN (floater)) == USE
8520 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8524 /* Anything except a regular INSN will stop our search. */
8525 if (GET_CODE (floater) != INSN
8526 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8527 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8533 /* See if FLOATER is suitable for combination with the
8535 floater_attr = get_attr_pa_combine_type (floater);
8536 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8537 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8538 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8539 && floater_attr == PA_COMBINE_TYPE_FMPY))
8541 /* If ANCHOR and FLOATER can be combined, then we're
8542 done with this pass. */
8543 if (pa_can_combine_p (new, anchor, floater, 1,
8544 SET_DEST (PATTERN (floater)),
8545 XEXP (SET_SRC (PATTERN (floater)),
8547 XEXP (SET_SRC (PATTERN (floater)),
8554 /* FLOATER will be nonzero if we found a suitable floating
8555 insn for combination with ANCHOR. */
8557 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8558 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8560 /* Emit the new instruction and delete the old anchor. */
8561 emit_insn_before (gen_rtx_PARALLEL
8563 gen_rtvec (2, PATTERN (anchor),
8564 PATTERN (floater))),
8567 PUT_CODE (anchor, NOTE);
8568 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8569 NOTE_SOURCE_FILE (anchor) = 0;
8571 /* Emit a special USE insn for FLOATER, then delete
8572 the floating insn. */
8573 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8574 delete_insn (floater);
8579 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8582 /* Emit the new_jump instruction and delete the old anchor. */
8584 = emit_jump_insn_before (gen_rtx_PARALLEL
8586 gen_rtvec (2, PATTERN (anchor),
8587 PATTERN (floater))),
8590 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8591 PUT_CODE (anchor, NOTE);
8592 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8593 NOTE_SOURCE_FILE (anchor) = 0;
8595 /* Emit a special USE insn for FLOATER, then delete
8596 the floating insn. */
8597 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8598 delete_insn (floater);
8606 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8609 int insn_code_number;
8612 /* Create a PARALLEL with the patterns of ANCHOR and
8613 FLOATER, try to recognize it, then test constraints
8614 for the resulting pattern.
8616 If the pattern doesn't match or the constraints
8617 aren't met keep searching for a suitable floater
8619 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8620 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8621 INSN_CODE (new) = -1;
8622 insn_code_number = recog_memoized (new);
8623 if (insn_code_number < 0
8624 || (extract_insn (new), ! constrain_operands (1)))
8638 /* There's up to three operands to consider. One
8639 output and two inputs.
8641 The output must not be used between FLOATER & ANCHOR
8642 exclusive. The inputs must not be set between
8643 FLOATER and ANCHOR exclusive. */
8645 if (reg_used_between_p (dest, start, end))
8648 if (reg_set_between_p (src1, start, end))
8651 if (reg_set_between_p (src2, start, end))
8654 /* If we get here, then everything is good. */
8658 /* Return nonzero if references for INSN are delayed.
8660 Millicode insns are actually function calls with some special
8661 constraints on arguments and register usage.
8663 Millicode calls always expect their arguments in the integer argument
8664 registers, and always return their result in %r29 (ret1). They
8665 are expected to clobber their arguments, %r1, %r29, and the return
8666 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8668 This function tells reorg that the references to arguments and
8669 millicode calls do not appear to happen until after the millicode call.
8670 This allows reorg to put insns which set the argument registers into the
8671 delay slot of the millicode call -- thus they act more like traditional
8674 Note we cannot consider side effects of the insn to be delayed because
8675 the branch and link insn will clobber the return pointer. If we happened
8676 to use the return pointer in the delay slot of the call, then we lose.
8678 get_attr_type will try to recognize the given insn, so make sure to
8679 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8682 insn_refs_are_delayed (rtx insn)
8684 return ((GET_CODE (insn) == INSN
8685 && GET_CODE (PATTERN (insn)) != SEQUENCE
8686 && GET_CODE (PATTERN (insn)) != USE
8687 && GET_CODE (PATTERN (insn)) != CLOBBER
8688 && get_attr_type (insn) == TYPE_MILLI));
8691 /* On the HP-PA the value is found in register(s) 28(-29), unless
8692 the mode is SF or DF. Then the value is returned in fr4 (32).
8694 This must perform the same promotions as PROMOTE_MODE, else
8695 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8697 Small structures must be returned in a PARALLEL on PA64 in order
8698 to match the HP Compiler ABI. */
8701 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8703 enum machine_mode valmode;
8705 if (AGGREGATE_TYPE_P (valtype))
8709 /* Aggregates with a size less than or equal to 128 bits are
8710 returned in GR 28(-29). They are left justified. The pad
8711 bits are undefined. Larger aggregates are returned in
8715 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8717 for (i = 0; i < ub; i++)
8719 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8720 gen_rtx_REG (DImode, 28 + i),
8725 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8727 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
8729 /* Aggregates 5 to 8 bytes in size are returned in general
8730 registers r28-r29 in the same manner as other non
8731 floating-point objects. The data is right-justified and
8732 zero-extended to 64 bits. This is opposite to the normal
8733 justification used on big endian targets and requires
8734 special treatment. */
8735 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8736 gen_rtx_REG (DImode, 28), const0_rtx);
8737 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
8741 if ((INTEGRAL_TYPE_P (valtype)
8742 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8743 || POINTER_TYPE_P (valtype))
8744 valmode = word_mode;
8746 valmode = TYPE_MODE (valtype);
8748 if (TREE_CODE (valtype) == REAL_TYPE
8749 && !AGGREGATE_TYPE_P (valtype)
8750 && TYPE_MODE (valtype) != TFmode
8751 && !TARGET_SOFT_FLOAT)
8752 return gen_rtx_REG (valmode, 32);
8754 return gen_rtx_REG (valmode, 28);
8757 /* Return the location of a parameter that is passed in a register or NULL
8758 if the parameter has any component that is passed in memory.
8760 This is new code and will be pushed to into the net sources after
8763 ??? We might want to restructure this so that it looks more like other
8766 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8767 int named ATTRIBUTE_UNUSED)
8769 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8776 if (mode == VOIDmode)
8779 arg_size = FUNCTION_ARG_SIZE (mode, type);
8781 /* If this arg would be passed partially or totally on the stack, then
8782 this routine should return zero. pa_arg_partial_bytes will
8783 handle arguments which are split between regs and stack slots if
8784 the ABI mandates split arguments. */
8787 /* The 32-bit ABI does not split arguments. */
8788 if (cum->words + arg_size > max_arg_words)
8794 alignment = cum->words & 1;
8795 if (cum->words + alignment >= max_arg_words)
8799 /* The 32bit ABIs and the 64bit ABIs are rather different,
8800 particularly in their handling of FP registers. We might
8801 be able to cleverly share code between them, but I'm not
8802 going to bother in the hope that splitting them up results
8803 in code that is more easily understood. */
8807 /* Advance the base registers to their current locations.
8809 Remember, gprs grow towards smaller register numbers while
8810 fprs grow to higher register numbers. Also remember that
8811 although FP regs are 32-bit addressable, we pretend that
8812 the registers are 64-bits wide. */
8813 gpr_reg_base = 26 - cum->words;
8814 fpr_reg_base = 32 + cum->words;
8816 /* Arguments wider than one word and small aggregates need special
8820 || (type && AGGREGATE_TYPE_P (type)))
8822 /* Double-extended precision (80-bit), quad-precision (128-bit)
8823 and aggregates including complex numbers are aligned on
8824 128-bit boundaries. The first eight 64-bit argument slots
8825 are associated one-to-one, with general registers r26
8826 through r19, and also with floating-point registers fr4
8827 through fr11. Arguments larger than one word are always
8828 passed in general registers.
8830 Using a PARALLEL with a word mode register results in left
8831 justified data on a big-endian target. */
8834 int i, offset = 0, ub = arg_size;
8836 /* Align the base register. */
8837 gpr_reg_base -= alignment;
8839 ub = MIN (ub, max_arg_words - cum->words - alignment);
8840 for (i = 0; i < ub; i++)
8842 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8843 gen_rtx_REG (DImode, gpr_reg_base),
8849 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8854 /* If the argument is larger than a word, then we know precisely
8855 which registers we must use. */
8869 /* Structures 5 to 8 bytes in size are passed in the general
8870 registers in the same manner as other non floating-point
8871 objects. The data is right-justified and zero-extended
8872 to 64 bits. This is opposite to the normal justification
8873 used on big endian targets and requires special treatment.
8874 We now define BLOCK_REG_PADDING to pad these objects. */
8875 if (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
8877 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8878 gen_rtx_REG (DImode, gpr_reg_base),
8880 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
8885 /* We have a single word (32 bits). A simple computation
8886 will get us the register #s we need. */
8887 gpr_reg_base = 26 - cum->words;
8888 fpr_reg_base = 32 + 2 * cum->words;
8892 /* Determine if the argument needs to be passed in both general and
8893 floating point registers. */
8894 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8895 /* If we are doing soft-float with portable runtime, then there
8896 is no need to worry about FP regs. */
8897 && !TARGET_SOFT_FLOAT
8898 /* The parameter must be some kind of float, else we can just
8899 pass it in integer registers. */
8900 && FLOAT_MODE_P (mode)
8901 /* The target function must not have a prototype. */
8902 && cum->nargs_prototype <= 0
8903 /* libcalls do not need to pass items in both FP and general
8905 && type != NULL_TREE
8906 /* All this hair applies to "outgoing" args only. This includes
8907 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8909 /* Also pass outgoing floating arguments in both registers in indirect
8910 calls with the 32 bit ABI and the HP assembler since there is no
8911 way to the specify argument locations in static functions. */
8916 && FLOAT_MODE_P (mode)))
8922 gen_rtx_EXPR_LIST (VOIDmode,
8923 gen_rtx_REG (mode, fpr_reg_base),
8925 gen_rtx_EXPR_LIST (VOIDmode,
8926 gen_rtx_REG (mode, gpr_reg_base),
8931 /* See if we should pass this parameter in a general register. */
8932 if (TARGET_SOFT_FLOAT
8933 /* Indirect calls in the normal 32bit ABI require all arguments
8934 to be passed in general registers. */
8935 || (!TARGET_PORTABLE_RUNTIME
8939 /* If the parameter is not a floating point parameter, then
8940 it belongs in GPRs. */
8941 || !FLOAT_MODE_P (mode)
8942 /* Structure with single SFmode field belongs in GPR. */
8943 || (type && AGGREGATE_TYPE_P (type)))
8944 retval = gen_rtx_REG (mode, gpr_reg_base);
8946 retval = gen_rtx_REG (mode, fpr_reg_base);
8952 /* If this arg would be passed totally in registers or totally on the stack,
8953 then this routine should return zero. */
8956 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8957 tree type, bool named ATTRIBUTE_UNUSED)
8959 unsigned int max_arg_words = 8;
8960 unsigned int offset = 0;
8965 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
8968 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
8969 /* Arg fits fully into registers. */
8971 else if (cum->words + offset >= max_arg_words)
8972 /* Arg fully on the stack. */
8976 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
8980 /* Return a string to output before text in the current function.
8982 This function is only used with SOM. Because we don't support
8983 named subspaces, we can only create a new subspace or switch back
8984 to the default text subspace. */
8986 som_text_section_asm_op (void)
8993 if (cfun && !cfun->machine->in_nsubspa)
8995 /* We only want to emit a .nsubspa directive once at the
8996 start of the function. */
8997 cfun->machine->in_nsubspa = 1;
8999 /* Create a new subspace for the text. This provides
9000 better stub placement and one-only functions. */
9002 && DECL_ONE_ONLY (cfun->decl)
9003 && !DECL_WEAK (cfun->decl))
9005 "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT";
9007 return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$";
9011 /* There isn't a current function or the body of the current
9012 function has been completed. So, we are changing to the
9013 text section to output debugging information. Do this in
9014 the default text section. We need to forget that we are
9015 in the text section so that the function text_section in
9016 varasm.c will call us the next time around. */
9021 return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$";
9024 /* On hpux10, the linker will give an error if we have a reference
9025 in the read-only data section to a symbol defined in a shared
9026 library. Therefore, expressions that might require a reloc can
9027 not be placed in the read-only data section. */
9030 pa_select_section (tree exp, int reloc,
9031 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9033 if (TREE_CODE (exp) == VAR_DECL
9034 && TREE_READONLY (exp)
9035 && !TREE_THIS_VOLATILE (exp)
9036 && DECL_INITIAL (exp)
9037 && (DECL_INITIAL (exp) == error_mark_node
9038 || TREE_CONSTANT (DECL_INITIAL (exp)))
9042 && DECL_ONE_ONLY (exp)
9043 && !DECL_WEAK (exp))
9044 som_one_only_readonly_data_section ();
9046 readonly_data_section ();
9048 else if (CONSTANT_CLASS_P (exp) && !reloc)
9049 readonly_data_section ();
9051 && TREE_CODE (exp) == VAR_DECL
9052 && DECL_ONE_ONLY (exp)
9053 && !DECL_WEAK (exp))
9054 som_one_only_data_section ();
9060 pa_globalize_label (FILE *stream, const char *name)
9062 /* We only handle DATA objects here, functions are globalized in
9063 ASM_DECLARE_FUNCTION_NAME. */
9064 if (! FUNCTION_NAME_P (name))
9066 fputs ("\t.EXPORT ", stream);
9067 assemble_name (stream, name);
9068 fputs (",DATA\n", stream);
9072 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9075 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9076 int incoming ATTRIBUTE_UNUSED)
9078 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9081 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9084 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9086 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9087 PA64 ABI says that objects larger than 128 bits are returned in memory.
9088 Note, int_size_in_bytes can return -1 if the size of the object is
9089 variable or larger than the maximum value that can be expressed as
9090 a HOST_WIDE_INT. It can also return zero for an empty type. The
9091 simplest way to handle variable and empty types is to pass them in
9092 memory. This avoids problems in defining the boundaries of argument
9093 slots, allocating registers, etc. */
9094 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9095 || int_size_in_bytes (type) <= 0);
9098 /* Structure to hold declaration and name of external symbols that are
9099 emitted by GCC. We generate a vector of these symbols and output them
9100 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9101 This avoids putting out names that are never really used. */
9103 typedef struct extern_symbol GTY(())
9109 /* Define gc'd vector type for extern_symbol. */
9110 DEF_VEC_O(extern_symbol);
9111 DEF_VEC_ALLOC_O(extern_symbol,gc);
9113 /* Vector of extern_symbol pointers. */
9114 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9116 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9117 /* Mark DECL (name NAME) as an external reference (assembler output
9118 file FILE). This saves the names to output at the end of the file
9119 if actually referenced. */
9122 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9124 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9126 gcc_assert (file == asm_out_file);
9131 /* Output text required at the end of an assembler file.
9132 This includes deferred plabels and .import directives for
9133 all external symbols that were actually referenced. */
9136 pa_hpux_file_end (void)
9141 output_deferred_plabels ();
9143 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9145 tree decl = p->decl;
9147 if (!TREE_ASM_WRITTEN (decl)
9148 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9149 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9152 VEC_free (extern_symbol, gc, extern_symbols);