1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static int hppa_address_cost (rtx);
88 static bool hppa_rtx_costs (rtx, int, int, int *);
89 static inline rtx force_mode (enum machine_mode, rtx);
90 static void pa_reorg (void);
91 static void pa_combine_instructions (void);
92 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
93 static int forward_branch_p (rtx);
94 static int shadd_constant_p (int);
95 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
96 static int compute_movmem_length (rtx);
97 static int compute_clrmem_length (rtx);
98 static bool pa_assemble_integer (rtx, unsigned int, int);
99 static void remove_useless_addtr_insns (int);
100 static void store_reg (int, HOST_WIDE_INT, int);
101 static void store_reg_modify (int, int, HOST_WIDE_INT);
102 static void load_reg (int, HOST_WIDE_INT, int);
103 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
104 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
105 static void update_total_code_bytes (int);
106 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
107 static int pa_adjust_cost (rtx, rtx, rtx, int);
108 static int pa_adjust_priority (rtx, int);
109 static int pa_issue_rate (void);
110 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
112 static void pa_encode_section_info (tree, rtx, int);
113 static const char *pa_strip_name_encoding (const char *);
114 static bool pa_function_ok_for_sibcall (tree, tree);
115 static void pa_globalize_label (FILE *, const char *)
117 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
118 HOST_WIDE_INT, tree);
119 #if !defined(USE_COLLECT2)
120 static void pa_asm_out_constructor (rtx, int);
121 static void pa_asm_out_destructor (rtx, int);
123 static void pa_init_builtins (void);
124 static rtx hppa_builtin_saveregs (void);
125 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
126 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
127 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
128 static struct deferred_plabel *get_plabel (const char *)
130 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
134 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
135 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
139 static void output_deferred_plabels (void);
140 #ifdef HPUX_LONG_DOUBLE_LIBRARY
141 static void pa_hpux_init_libfuncs (void);
143 static rtx pa_struct_value_rtx (tree, int);
144 static bool pa_pass_by_reference (CUMULATIVE_ARGS *ca, enum machine_mode,
146 static struct machine_function * pa_init_machine_status (void);
149 /* Save the operands last given to a compare for use when we
150 generate a scc or bcc insn. */
151 rtx hppa_compare_op0, hppa_compare_op1;
152 enum cmp_type hppa_branch_type;
154 /* Which architecture we are generating code for. */
155 enum architecture_type pa_arch;
157 /* String to hold which architecture we are generating code for. */
158 const char *pa_arch_string;
160 /* String used with the -mfixed-range= option. */
161 const char *pa_fixed_range_string;
163 /* Which cpu we are scheduling for. */
164 enum processor_type pa_cpu;
166 /* String to hold which cpu we are scheduling for. */
167 const char *pa_cpu_string;
169 /* String used with the -munix= option. */
170 const char *pa_unix_string;
172 /* The UNIX standard to use for predefines and linking. */
175 /* Counts for the number of callee-saved general and floating point
176 registers which were saved by the current function's prologue. */
177 static int gr_saved, fr_saved;
179 static rtx find_addr_reg (rtx);
181 /* Keep track of the number of bytes we have output in the CODE subspace
182 during this compilation so we'll know when to emit inline long-calls. */
183 unsigned long total_code_bytes;
185 /* The last address of the previous function plus the number of bytes in
186 associated thunks that have been output. This is used to determine if
187 a thunk can use an IA-relative branch to reach its target function. */
188 static int last_address;
190 /* Variables to handle plabels that we discover are necessary at assembly
191 output time. They are output after the current function. */
192 struct deferred_plabel GTY(())
197 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
199 static size_t n_deferred_plabels = 0;
202 /* Initialize the GCC target structure. */
204 #undef TARGET_ASM_ALIGNED_HI_OP
205 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
206 #undef TARGET_ASM_ALIGNED_SI_OP
207 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
208 #undef TARGET_ASM_ALIGNED_DI_OP
209 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
210 #undef TARGET_ASM_UNALIGNED_HI_OP
211 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
212 #undef TARGET_ASM_UNALIGNED_SI_OP
213 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
214 #undef TARGET_ASM_UNALIGNED_DI_OP
215 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
216 #undef TARGET_ASM_INTEGER
217 #define TARGET_ASM_INTEGER pa_assemble_integer
219 #undef TARGET_ASM_FUNCTION_PROLOGUE
220 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
221 #undef TARGET_ASM_FUNCTION_EPILOGUE
222 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
224 #undef TARGET_SCHED_ADJUST_COST
225 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
226 #undef TARGET_SCHED_ADJUST_PRIORITY
227 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
228 #undef TARGET_SCHED_ISSUE_RATE
229 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
231 #undef TARGET_ENCODE_SECTION_INFO
232 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
233 #undef TARGET_STRIP_NAME_ENCODING
234 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
236 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
237 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
239 #undef TARGET_ASM_OUTPUT_MI_THUNK
240 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
241 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
242 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
244 #undef TARGET_ASM_FILE_END
245 #define TARGET_ASM_FILE_END output_deferred_plabels
247 #if !defined(USE_COLLECT2)
248 #undef TARGET_ASM_CONSTRUCTOR
249 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
250 #undef TARGET_ASM_DESTRUCTOR
251 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
254 #undef TARGET_INIT_BUILTINS
255 #define TARGET_INIT_BUILTINS pa_init_builtins
257 #undef TARGET_RTX_COSTS
258 #define TARGET_RTX_COSTS hppa_rtx_costs
259 #undef TARGET_ADDRESS_COST
260 #define TARGET_ADDRESS_COST hppa_address_cost
262 #undef TARGET_MACHINE_DEPENDENT_REORG
263 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
265 #ifdef HPUX_LONG_DOUBLE_LIBRARY
266 #undef TARGET_INIT_LIBFUNCS
267 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
270 #undef TARGET_PROMOTE_FUNCTION_RETURN
271 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
272 #undef TARGET_PROMOTE_PROTOTYPES
273 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
275 #undef TARGET_STRUCT_VALUE_RTX
276 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
277 #undef TARGET_RETURN_IN_MEMORY
278 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
279 #undef TARGET_MUST_PASS_IN_STACK
280 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
281 #undef TARGET_PASS_BY_REFERENCE
282 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
283 #undef TARGET_CALLEE_COPIES
284 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
286 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
287 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
288 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
289 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
291 struct gcc_target targetm = TARGET_INITIALIZER;
293 /* Parse the -mfixed-range= option string. */
296 fix_range (const char *const_str)
299 char *str, *dash, *comma;
301 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
302 REG2 are either register names or register numbers. The effect
303 of this option is to mark the registers in the range from REG1 to
304 REG2 as ``fixed'' so they won't be used by the compiler. This is
305 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
307 i = strlen (const_str);
308 str = (char *) alloca (i + 1);
309 memcpy (str, const_str, i + 1);
313 dash = strchr (str, '-');
316 warning ("value of -mfixed-range must have form REG1-REG2");
321 comma = strchr (dash + 1, ',');
325 first = decode_reg_name (str);
328 warning ("unknown register name: %s", str);
332 last = decode_reg_name (dash + 1);
335 warning ("unknown register name: %s", dash + 1);
343 warning ("%s-%s is an empty range", str, dash + 1);
347 for (i = first; i <= last; ++i)
348 fixed_regs[i] = call_used_regs[i] = 1;
357 /* Check if all floating point registers have been fixed. */
358 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
363 target_flags |= MASK_DISABLE_FPREGS;
367 override_options (void)
369 if (pa_cpu_string == NULL)
370 pa_cpu_string = TARGET_SCHED_DEFAULT;
372 if (! strcmp (pa_cpu_string, "8000"))
374 pa_cpu_string = "8000";
375 pa_cpu = PROCESSOR_8000;
377 else if (! strcmp (pa_cpu_string, "7100"))
379 pa_cpu_string = "7100";
380 pa_cpu = PROCESSOR_7100;
382 else if (! strcmp (pa_cpu_string, "700"))
384 pa_cpu_string = "700";
385 pa_cpu = PROCESSOR_700;
387 else if (! strcmp (pa_cpu_string, "7100LC"))
389 pa_cpu_string = "7100LC";
390 pa_cpu = PROCESSOR_7100LC;
392 else if (! strcmp (pa_cpu_string, "7200"))
394 pa_cpu_string = "7200";
395 pa_cpu = PROCESSOR_7200;
397 else if (! strcmp (pa_cpu_string, "7300"))
399 pa_cpu_string = "7300";
400 pa_cpu = PROCESSOR_7300;
404 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
407 /* Set the instruction architecture. */
408 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
410 pa_arch_string = "1.0";
411 pa_arch = ARCHITECTURE_10;
412 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
414 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
416 pa_arch_string = "1.1";
417 pa_arch = ARCHITECTURE_11;
418 target_flags &= ~MASK_PA_20;
419 target_flags |= MASK_PA_11;
421 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
423 pa_arch_string = "2.0";
424 pa_arch = ARCHITECTURE_20;
425 target_flags |= MASK_PA_11 | MASK_PA_20;
427 else if (pa_arch_string)
429 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
434 /* Set the default UNIX standard for HP-UX. This affects the
435 predefines and startfiles used for the target. */
436 if (pa_unix_string == NULL)
438 = TARGET_HPUX_11_11 ? "98" : (TARGET_HPUX_10_10 ? "95" : "93");
440 if (!strcmp (pa_unix_string, "93"))
442 else if (!strcmp (pa_unix_string, "95"))
444 else if (TARGET_HPUX_11_11)
446 if (!strcmp (pa_unix_string, "98"))
449 warning ("unknown -munix= option (%s).\n"
450 "Valid options are 93, 95 and 98.\n",
453 else if (TARGET_HPUX_10_10)
454 warning ("unknown -munix= option (%s)."
455 "\nValid options are 93 and 95.\n",
458 warning ("unknown -munix= option (%s).\nValid option is 93.\n",
462 if (pa_fixed_range_string)
463 fix_range (pa_fixed_range_string);
465 /* Unconditional branches in the delay slot are not compatible with dwarf2
466 call frame information. There is no benefit in using this optimization
467 on PA8000 and later processors. */
468 if (pa_cpu >= PROCESSOR_8000
469 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
470 || flag_unwind_tables)
471 target_flags &= ~MASK_JUMP_IN_DELAY;
473 if (flag_pic && TARGET_PORTABLE_RUNTIME)
475 warning ("PIC code generation is not supported in the portable runtime model\n");
478 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
480 warning ("PIC code generation is not compatible with fast indirect calls\n");
483 if (! TARGET_GAS && write_symbols != NO_DEBUG)
485 warning ("-g is only supported when using GAS on this processor,");
486 warning ("-g option disabled");
487 write_symbols = NO_DEBUG;
490 /* We only support the "big PIC" model now. And we always generate PIC
491 code when in 64bit mode. */
492 if (flag_pic == 1 || TARGET_64BIT)
495 /* We can't guarantee that .dword is available for 32-bit targets. */
496 if (UNITS_PER_WORD == 4)
497 targetm.asm_out.aligned_op.di = NULL;
499 /* The unaligned ops are only available when using GAS. */
502 targetm.asm_out.unaligned_op.hi = NULL;
503 targetm.asm_out.unaligned_op.si = NULL;
504 targetm.asm_out.unaligned_op.di = NULL;
507 init_machine_status = pa_init_machine_status;
511 pa_init_builtins (void)
513 #ifdef DONT_HAVE_FPUTC_UNLOCKED
514 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
515 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
519 /* Function to init struct machine_function.
520 This will be called, via a pointer variable,
521 from push_function_context. */
523 static struct machine_function *
524 pa_init_machine_status (void)
526 return ggc_alloc_cleared (sizeof (machine_function));
529 /* If FROM is a probable pointer register, mark TO as a probable
530 pointer register with the same pointer alignment as FROM. */
533 copy_reg_pointer (rtx to, rtx from)
535 if (REG_POINTER (from))
536 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
539 /* Return nonzero only if OP is a register of mode MODE,
542 reg_or_0_operand (rtx op, enum machine_mode mode)
544 return (op == CONST0_RTX (mode) || register_operand (op, mode));
547 /* Return nonzero if OP is suitable for use in a call to a named
550 For 2.5 try to eliminate either call_operand_address or
551 function_label_operand, they perform very similar functions. */
553 call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
555 return (GET_MODE (op) == word_mode
556 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
559 /* Return 1 if X contains a symbolic expression. We know these
560 expressions will have one of a few well defined forms, so
561 we need only check those forms. */
563 symbolic_expression_p (rtx x)
566 /* Strip off any HIGH. */
567 if (GET_CODE (x) == HIGH)
570 return (symbolic_operand (x, VOIDmode));
574 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
576 switch (GET_CODE (op))
583 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
584 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
585 && GET_CODE (XEXP (op, 1)) == CONST_INT);
591 /* Return truth value of statement that OP is a symbolic memory
592 operand of mode MODE. */
595 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
597 if (GET_CODE (op) == SUBREG)
598 op = SUBREG_REG (op);
599 if (GET_CODE (op) != MEM)
602 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
603 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
606 /* Return 1 if the operand is either a register, zero, or a memory operand
607 that is not symbolic. */
610 reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode)
612 if (register_operand (op, mode))
615 if (op == CONST0_RTX (mode))
618 if (GET_CODE (op) == SUBREG)
619 op = SUBREG_REG (op);
621 if (GET_CODE (op) != MEM)
624 /* Until problems with management of the REG_POINTER flag are resolved,
625 we need to delay creating move insns with unscaled indexed addresses
626 until CSE is not expected. */
627 if (!TARGET_NO_SPACE_REGS
629 && GET_CODE (XEXP (op, 0)) == PLUS
630 && REG_P (XEXP (XEXP (op, 0), 0))
631 && REG_P (XEXP (XEXP (op, 0), 1)))
634 return (!symbolic_memory_operand (op, mode)
635 && memory_address_p (mode, XEXP (op, 0)));
638 /* Return 1 if the operand is a register operand or a non-symbolic memory
639 operand after reload. This predicate is used for branch patterns that
640 internally handle register reloading. We need to accept non-symbolic
641 memory operands after reload to ensure that the pattern is still valid
642 if reload didn't find a hard register for the operand. */
645 reg_before_reload_operand (rtx op, enum machine_mode mode)
647 /* Don't accept a SUBREG since it will need a reload. */
648 if (GET_CODE (op) == SUBREG)
651 if (register_operand (op, mode))
655 && memory_operand (op, mode)
656 && !symbolic_memory_operand (op, mode))
662 /* Accept any constant that can be moved in one instruction into a
665 cint_ok_for_move (HOST_WIDE_INT intval)
667 /* OK if ldo, ldil, or zdepi, can be used. */
668 return (CONST_OK_FOR_LETTER_P (intval, 'J')
669 || CONST_OK_FOR_LETTER_P (intval, 'N')
670 || CONST_OK_FOR_LETTER_P (intval, 'K'));
673 /* Return 1 iff OP is an indexed memory operand. */
675 indexed_memory_operand (rtx op, enum machine_mode mode)
677 if (GET_MODE (op) != mode)
680 /* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
681 if (reload_completed && GET_CODE (op) == SUBREG)
682 op = SUBREG_REG (op);
684 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
689 return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op));
692 /* Accept anything that can be used as a destination operand for a
693 move instruction. We don't accept indexed memory operands since
694 they are supported only for floating point stores. */
696 move_dest_operand (rtx op, enum machine_mode mode)
698 if (register_operand (op, mode))
701 if (GET_MODE (op) != mode)
704 if (GET_CODE (op) == SUBREG)
705 op = SUBREG_REG (op);
707 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
712 return (memory_address_p (mode, op)
713 && !IS_INDEX_ADDR_P (op)
714 && !IS_LO_SUM_DLT_ADDR_P (op));
717 /* Accept anything that can be used as a source operand for a move
720 move_src_operand (rtx op, enum machine_mode mode)
722 if (register_operand (op, mode))
725 if (GET_CODE (op) == CONST_INT)
726 return cint_ok_for_move (INTVAL (op));
728 if (GET_MODE (op) != mode)
731 if (GET_CODE (op) == SUBREG)
732 op = SUBREG_REG (op);
734 if (GET_CODE (op) != MEM)
737 /* Until problems with management of the REG_POINTER flag are resolved,
738 we need to delay creating move insns with unscaled indexed addresses
739 until CSE is not expected. */
740 if (!TARGET_NO_SPACE_REGS
742 && GET_CODE (XEXP (op, 0)) == PLUS
743 && REG_P (XEXP (XEXP (op, 0), 0))
744 && REG_P (XEXP (XEXP (op, 0), 1)))
747 return memory_address_p (mode, XEXP (op, 0));
750 /* Accept anything that can be used as the source operand for a prefetch
753 prefetch_operand (rtx op, enum machine_mode mode)
755 if (GET_CODE (op) != MEM)
758 /* Until problems with management of the REG_POINTER flag are resolved,
759 we need to delay creating prefetch insns with unscaled indexed addresses
760 until CSE is not expected. */
761 if (!TARGET_NO_SPACE_REGS
763 && GET_CODE (XEXP (op, 0)) == PLUS
764 && REG_P (XEXP (XEXP (op, 0), 0))
765 && REG_P (XEXP (XEXP (op, 0), 1)))
768 return memory_address_p (mode, XEXP (op, 0));
771 /* Accept REG and any CONST_INT that can be moved in one instruction into a
774 reg_or_cint_move_operand (rtx op, enum machine_mode mode)
776 if (register_operand (op, mode))
779 return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op)));
783 pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
788 switch (GET_CODE (op))
794 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
795 && GET_CODE (XEXP (op, 1)) == CONST_INT);
802 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
804 return reg_renumber && FP_REG_P (op);
809 /* Return truth value of whether OP can be used as an operand in a
810 three operand arithmetic insn that accepts registers of mode MODE
811 or 14-bit signed integers. */
813 arith_operand (rtx op, enum machine_mode mode)
815 return (register_operand (op, mode)
816 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
819 /* Return truth value of whether OP can be used as an operand in a
820 three operand arithmetic insn that accepts registers of mode MODE
821 or 11-bit signed integers. */
823 arith11_operand (rtx op, enum machine_mode mode)
825 return (register_operand (op, mode)
826 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
829 /* Return truth value of whether OP can be used as an operand in a
832 adddi3_operand (rtx op, enum machine_mode mode)
834 return (register_operand (op, mode)
835 || (GET_CODE (op) == CONST_INT
836 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
839 /* A constant integer suitable for use in a PRE_MODIFY memory
842 pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
844 return (GET_CODE (op) == CONST_INT
845 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
848 /* A constant integer suitable for use in a POST_MODIFY memory
851 post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
853 return (GET_CODE (op) == CONST_INT
854 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
858 arith_double_operand (rtx op, enum machine_mode mode)
860 return (register_operand (op, mode)
861 || (GET_CODE (op) == CONST_DOUBLE
862 && GET_MODE (op) == mode
863 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
864 && ((CONST_DOUBLE_HIGH (op) >= 0)
865 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
868 /* Return truth value of whether OP is an integer which fits the
869 range constraining immediate operands in three-address insns, or
870 is an integer register. */
873 ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
875 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
876 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
879 /* Return nonzero if OP is an integer register, else return zero. */
881 ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
883 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
886 /* Return truth value of whether OP is an integer which fits the
887 range constraining immediate operands in three-address insns. */
890 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
892 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
896 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
898 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
902 int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
904 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
908 uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
910 #if HOST_BITS_PER_WIDE_INT > 32
911 /* All allowed constants will fit a CONST_INT. */
912 return (GET_CODE (op) == CONST_INT
913 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
915 return (GET_CODE (op) == CONST_INT
916 || (GET_CODE (op) == CONST_DOUBLE
917 && CONST_DOUBLE_HIGH (op) == 0));
922 arith5_operand (rtx op, enum machine_mode mode)
924 return register_operand (op, mode) || int5_operand (op, mode);
927 /* True iff zdepi can be used to generate this CONST_INT.
928 zdepi first sign extends a 5 bit signed number to a given field
929 length, then places this field anywhere in a zero. */
931 zdepi_cint_p (unsigned HOST_WIDE_INT x)
933 unsigned HOST_WIDE_INT lsb_mask, t;
935 /* This might not be obvious, but it's at least fast.
936 This function is critical; we don't have the time loops would take. */
938 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
939 /* Return true iff t is a power of two. */
940 return ((t & (t - 1)) == 0);
943 /* True iff depi or extru can be used to compute (reg & mask).
944 Accept bit pattern like these:
949 and_mask_p (unsigned HOST_WIDE_INT mask)
952 mask += mask & -mask;
953 return (mask & (mask - 1)) == 0;
956 /* True iff depi or extru can be used to compute (reg & OP). */
958 and_operand (rtx op, enum machine_mode mode)
960 return (register_operand (op, mode)
961 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
964 /* True iff depi can be used to compute (reg | MASK). */
966 ior_mask_p (unsigned HOST_WIDE_INT mask)
968 mask += mask & -mask;
969 return (mask & (mask - 1)) == 0;
972 /* True iff depi can be used to compute (reg | OP). */
974 ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
976 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
980 lhs_lshift_operand (rtx op, enum machine_mode mode)
982 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
985 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
986 Such values can be the left hand side x in (x << r), using the zvdepi
989 lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
991 unsigned HOST_WIDE_INT x;
992 if (GET_CODE (op) != CONST_INT)
994 x = INTVAL (op) >> 4;
995 return (x & (x + 1)) == 0;
999 arith32_operand (rtx op, enum machine_mode mode)
1001 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
1005 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1007 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
1010 /* Legitimize PIC addresses. If the address is already
1011 position-independent, we return ORIG. Newly generated
1012 position-independent addresses go to REG. If we need more
1013 than one register, we lose. */
1016 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
1020 /* Labels need special handling. */
1021 if (pic_label_operand (orig, mode))
1023 /* We do not want to go through the movXX expanders here since that
1024 would create recursion.
1026 Nor do we really want to call a generator for a named pattern
1027 since that requires multiple patterns if we want to support
1028 multiple word sizes.
1030 So instead we just emit the raw set, which avoids the movXX
1031 expanders completely. */
1032 mark_reg_pointer (reg, BITS_PER_UNIT);
1033 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
1034 current_function_uses_pic_offset_table = 1;
1037 if (GET_CODE (orig) == SYMBOL_REF)
1044 /* Before reload, allocate a temporary register for the intermediate
1045 result. This allows the sequence to be deleted when the final
1046 result is unused and the insns are trivially dead. */
1047 tmp_reg = ((reload_in_progress || reload_completed)
1048 ? reg : gen_reg_rtx (Pmode));
1050 emit_move_insn (tmp_reg,
1051 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
1052 gen_rtx_HIGH (word_mode, orig)));
1054 = gen_const_mem (Pmode,
1055 gen_rtx_LO_SUM (Pmode, tmp_reg,
1056 gen_rtx_UNSPEC (Pmode,
1057 gen_rtvec (1, orig),
1058 UNSPEC_DLTIND14R)));
1060 current_function_uses_pic_offset_table = 1;
1061 mark_reg_pointer (reg, BITS_PER_UNIT);
1062 insn = emit_move_insn (reg, pic_ref);
1064 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
1065 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
1069 else if (GET_CODE (orig) == CONST)
1073 if (GET_CODE (XEXP (orig, 0)) == PLUS
1074 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1080 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1082 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1083 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1084 base == reg ? 0 : reg);
1089 if (GET_CODE (orig) == CONST_INT)
1091 if (INT_14_BITS (orig))
1092 return plus_constant (base, INTVAL (orig));
1093 orig = force_reg (Pmode, orig);
1095 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
1096 /* Likewise, should we set special REG_NOTEs here? */
1102 /* Try machine-dependent ways of modifying an illegitimate address
1103 to be legitimate. If we find one, return the new, valid address.
1104 This macro is used in only one place: `memory_address' in explow.c.
1106 OLDX is the address as it was before break_out_memory_refs was called.
1107 In some cases it is useful to look at this to decide what needs to be done.
1109 MODE and WIN are passed so that this macro can use
1110 GO_IF_LEGITIMATE_ADDRESS.
1112 It is always safe for this macro to do nothing. It exists to recognize
1113 opportunities to optimize the output.
1115 For the PA, transform:
1117 memory(X + <large int>)
1121 if (<large int> & mask) >= 16
1122 Y = (<large int> & ~mask) + mask + 1 Round up.
1124 Y = (<large int> & ~mask) Round down.
1126 memory (Z + (<large int> - Y));
1128 This is for CSE to find several similar references, and only use one Z.
1130 X can either be a SYMBOL_REF or REG, but because combine cannot
1131 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
1132 D will not fit in 14 bits.
1134 MODE_FLOAT references allow displacements which fit in 5 bits, so use
1137 MODE_INT references allow displacements which fit in 14 bits, so use
1140 This relies on the fact that most mode MODE_FLOAT references will use FP
1141 registers and most mode MODE_INT references will use integer registers.
1142 (In the rare case of an FP register used in an integer MODE, we depend
1143 on secondary reloads to clean things up.)
1146 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1147 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1148 addressing modes to be used).
1150 Put X and Z into registers. Then put the entire expression into
1154 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1155 enum machine_mode mode)
1159 /* We need to canonicalize the order of operands in unscaled indexed
1160 addresses since the code that checks if an address is valid doesn't
1161 always try both orders. */
1162 if (!TARGET_NO_SPACE_REGS
1163 && GET_CODE (x) == PLUS
1164 && GET_MODE (x) == Pmode
1165 && REG_P (XEXP (x, 0))
1166 && REG_P (XEXP (x, 1))
1167 && REG_POINTER (XEXP (x, 0))
1168 && !REG_POINTER (XEXP (x, 1)))
1169 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1172 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1174 /* Strip off CONST. */
1175 if (GET_CODE (x) == CONST)
1178 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1179 That should always be safe. */
1180 if (GET_CODE (x) == PLUS
1181 && GET_CODE (XEXP (x, 0)) == REG
1182 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1184 rtx reg = force_reg (Pmode, XEXP (x, 1));
1185 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1188 /* Note we must reject symbols which represent function addresses
1189 since the assembler/linker can't handle arithmetic on plabels. */
1190 if (GET_CODE (x) == PLUS
1191 && GET_CODE (XEXP (x, 1)) == CONST_INT
1192 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1193 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1194 || GET_CODE (XEXP (x, 0)) == REG))
1196 rtx int_part, ptr_reg;
1198 int offset = INTVAL (XEXP (x, 1));
1201 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1202 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1204 /* Choose which way to round the offset. Round up if we
1205 are >= halfway to the next boundary. */
1206 if ((offset & mask) >= ((mask + 1) / 2))
1207 newoffset = (offset & ~ mask) + mask + 1;
1209 newoffset = (offset & ~ mask);
1211 /* If the newoffset will not fit in 14 bits (ldo), then
1212 handling this would take 4 or 5 instructions (2 to load
1213 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1214 add the new offset and the SYMBOL_REF.) Combine can
1215 not handle 4->2 or 5->2 combinations, so do not create
1217 if (! VAL_14_BITS_P (newoffset)
1218 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1220 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1223 gen_rtx_HIGH (Pmode, const_part));
1226 gen_rtx_LO_SUM (Pmode,
1227 tmp_reg, const_part));
1231 if (! VAL_14_BITS_P (newoffset))
1232 int_part = force_reg (Pmode, GEN_INT (newoffset));
1234 int_part = GEN_INT (newoffset);
1236 ptr_reg = force_reg (Pmode,
1237 gen_rtx_PLUS (Pmode,
1238 force_reg (Pmode, XEXP (x, 0)),
1241 return plus_constant (ptr_reg, offset - newoffset);
1244 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1246 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1247 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1248 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1249 && (OBJECT_P (XEXP (x, 1))
1250 || GET_CODE (XEXP (x, 1)) == SUBREG)
1251 && GET_CODE (XEXP (x, 1)) != CONST)
1253 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1257 if (GET_CODE (reg1) != REG)
1258 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1260 reg2 = XEXP (XEXP (x, 0), 0);
1261 if (GET_CODE (reg2) != REG)
1262 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1264 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1265 gen_rtx_MULT (Pmode,
1271 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1273 Only do so for floating point modes since this is more speculative
1274 and we lose if it's an integer store. */
1275 if (GET_CODE (x) == PLUS
1276 && GET_CODE (XEXP (x, 0)) == PLUS
1277 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1278 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1279 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1280 && (mode == SFmode || mode == DFmode))
1283 /* First, try and figure out what to use as a base register. */
1284 rtx reg1, reg2, base, idx, orig_base;
1286 reg1 = XEXP (XEXP (x, 0), 1);
1291 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1292 then emit_move_sequence will turn on REG_POINTER so we'll know
1293 it's a base register below. */
1294 if (GET_CODE (reg1) != REG)
1295 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1297 if (GET_CODE (reg2) != REG)
1298 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1300 /* Figure out what the base and index are. */
1302 if (GET_CODE (reg1) == REG
1303 && REG_POINTER (reg1))
1306 orig_base = XEXP (XEXP (x, 0), 1);
1307 idx = gen_rtx_PLUS (Pmode,
1308 gen_rtx_MULT (Pmode,
1309 XEXP (XEXP (XEXP (x, 0), 0), 0),
1310 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1313 else if (GET_CODE (reg2) == REG
1314 && REG_POINTER (reg2))
1317 orig_base = XEXP (x, 1);
1324 /* If the index adds a large constant, try to scale the
1325 constant so that it can be loaded with only one insn. */
1326 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1327 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1328 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1329 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1331 /* Divide the CONST_INT by the scale factor, then add it to A. */
1332 int val = INTVAL (XEXP (idx, 1));
1334 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1335 reg1 = XEXP (XEXP (idx, 0), 0);
1336 if (GET_CODE (reg1) != REG)
1337 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1339 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1341 /* We can now generate a simple scaled indexed address. */
1344 (Pmode, gen_rtx_PLUS (Pmode,
1345 gen_rtx_MULT (Pmode, reg1,
1346 XEXP (XEXP (idx, 0), 1)),
1350 /* If B + C is still a valid base register, then add them. */
1351 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1352 && INTVAL (XEXP (idx, 1)) <= 4096
1353 && INTVAL (XEXP (idx, 1)) >= -4096)
1355 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1358 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1360 reg2 = XEXP (XEXP (idx, 0), 0);
1361 if (GET_CODE (reg2) != CONST_INT)
1362 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1364 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1365 gen_rtx_MULT (Pmode,
1371 /* Get the index into a register, then add the base + index and
1372 return a register holding the result. */
1374 /* First get A into a register. */
1375 reg1 = XEXP (XEXP (idx, 0), 0);
1376 if (GET_CODE (reg1) != REG)
1377 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1379 /* And get B into a register. */
1380 reg2 = XEXP (idx, 1);
1381 if (GET_CODE (reg2) != REG)
1382 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1384 reg1 = force_reg (Pmode,
1385 gen_rtx_PLUS (Pmode,
1386 gen_rtx_MULT (Pmode, reg1,
1387 XEXP (XEXP (idx, 0), 1)),
1390 /* Add the result to our base register and return. */
1391 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1395 /* Uh-oh. We might have an address for x[n-100000]. This needs
1396 special handling to avoid creating an indexed memory address
1397 with x-100000 as the base.
1399 If the constant part is small enough, then it's still safe because
1400 there is a guard page at the beginning and end of the data segment.
1402 Scaled references are common enough that we want to try and rearrange the
1403 terms so that we can use indexing for these addresses too. Only
1404 do the optimization for floatint point modes. */
1406 if (GET_CODE (x) == PLUS
1407 && symbolic_expression_p (XEXP (x, 1)))
1409 /* Ugly. We modify things here so that the address offset specified
1410 by the index expression is computed first, then added to x to form
1411 the entire address. */
1413 rtx regx1, regx2, regy1, regy2, y;
1415 /* Strip off any CONST. */
1417 if (GET_CODE (y) == CONST)
1420 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1422 /* See if this looks like
1423 (plus (mult (reg) (shadd_const))
1424 (const (plus (symbol_ref) (const_int))))
1426 Where const_int is small. In that case the const
1427 expression is a valid pointer for indexing.
1429 If const_int is big, but can be divided evenly by shadd_const
1430 and added to (reg). This allows more scaled indexed addresses. */
1431 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1432 && GET_CODE (XEXP (x, 0)) == MULT
1433 && GET_CODE (XEXP (y, 1)) == CONST_INT
1434 && INTVAL (XEXP (y, 1)) >= -4096
1435 && INTVAL (XEXP (y, 1)) <= 4095
1436 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1437 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1439 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1443 if (GET_CODE (reg1) != REG)
1444 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1446 reg2 = XEXP (XEXP (x, 0), 0);
1447 if (GET_CODE (reg2) != REG)
1448 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1450 return force_reg (Pmode,
1451 gen_rtx_PLUS (Pmode,
1452 gen_rtx_MULT (Pmode,
1457 else if ((mode == DFmode || mode == SFmode)
1458 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1459 && GET_CODE (XEXP (x, 0)) == MULT
1460 && GET_CODE (XEXP (y, 1)) == CONST_INT
1461 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1462 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1463 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1466 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1467 / INTVAL (XEXP (XEXP (x, 0), 1))));
1468 regx2 = XEXP (XEXP (x, 0), 0);
1469 if (GET_CODE (regx2) != REG)
1470 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1471 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1475 gen_rtx_PLUS (Pmode,
1476 gen_rtx_MULT (Pmode, regx2,
1477 XEXP (XEXP (x, 0), 1)),
1478 force_reg (Pmode, XEXP (y, 0))));
1480 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1481 && INTVAL (XEXP (y, 1)) >= -4096
1482 && INTVAL (XEXP (y, 1)) <= 4095)
1484 /* This is safe because of the guard page at the
1485 beginning and end of the data space. Just
1486 return the original address. */
1491 /* Doesn't look like one we can optimize. */
1492 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1493 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1494 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1495 regx1 = force_reg (Pmode,
1496 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1498 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1506 /* For the HPPA, REG and REG+CONST is cost 0
1507 and addresses involving symbolic constants are cost 2.
1509 PIC addresses are very expensive.
1511 It is no coincidence that this has the same structure
1512 as GO_IF_LEGITIMATE_ADDRESS. */
1515 hppa_address_cost (rtx X)
1517 switch (GET_CODE (X))
1530 /* Compute a (partial) cost for rtx X. Return true if the complete
1531 cost has been computed, and false if subexpressions should be
1532 scanned. In either case, *TOTAL contains the cost result. */
1535 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1540 if (INTVAL (x) == 0)
1542 else if (INT_14_BITS (x))
1559 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1560 && outer_code != SET)
1567 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1568 *total = COSTS_N_INSNS (3);
1569 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1570 *total = COSTS_N_INSNS (8);
1572 *total = COSTS_N_INSNS (20);
1576 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1578 *total = COSTS_N_INSNS (14);
1586 *total = COSTS_N_INSNS (60);
1589 case PLUS: /* this includes shNadd insns */
1591 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1592 *total = COSTS_N_INSNS (3);
1594 *total = COSTS_N_INSNS (1);
1600 *total = COSTS_N_INSNS (1);
1608 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1609 new rtx with the correct mode. */
1611 force_mode (enum machine_mode mode, rtx orig)
1613 if (mode == GET_MODE (orig))
1616 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1619 return gen_rtx_REG (mode, REGNO (orig));
1622 /* Emit insns to move operands[1] into operands[0].
1624 Return 1 if we have written out everything that needs to be done to
1625 do the move. Otherwise, return 0 and the caller will emit the move
1628 Note SCRATCH_REG may not be in the proper mode depending on how it
1629 will be used. This routine is responsible for creating a new copy
1630 of SCRATCH_REG in the proper mode. */
1633 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1635 register rtx operand0 = operands[0];
1636 register rtx operand1 = operands[1];
1639 /* We can only handle indexed addresses in the destination operand
1640 of floating point stores. Thus, we need to break out indexed
1641 addresses from the destination operand. */
1642 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1644 /* This is only safe up to the beginning of life analysis. */
1648 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1649 operand0 = replace_equiv_address (operand0, tem);
1652 /* On targets with non-equivalent space registers, break out unscaled
1653 indexed addresses from the source operand before the final CSE.
1654 We have to do this because the REG_POINTER flag is not correctly
1655 carried through various optimization passes and CSE may substitute
1656 a pseudo without the pointer set for one with the pointer set. As
1657 a result, we loose various opportunities to create insns with
1658 unscaled indexed addresses. */
1659 if (!TARGET_NO_SPACE_REGS
1660 && !cse_not_expected
1661 && GET_CODE (operand1) == MEM
1662 && GET_CODE (XEXP (operand1, 0)) == PLUS
1663 && REG_P (XEXP (XEXP (operand1, 0), 0))
1664 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1666 = replace_equiv_address (operand1,
1667 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1670 && reload_in_progress && GET_CODE (operand0) == REG
1671 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1672 operand0 = reg_equiv_mem[REGNO (operand0)];
1673 else if (scratch_reg
1674 && reload_in_progress && GET_CODE (operand0) == SUBREG
1675 && GET_CODE (SUBREG_REG (operand0)) == REG
1676 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1678 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1679 the code which tracks sets/uses for delete_output_reload. */
1680 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1681 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1682 SUBREG_BYTE (operand0));
1683 operand0 = alter_subreg (&temp);
1687 && reload_in_progress && GET_CODE (operand1) == REG
1688 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1689 operand1 = reg_equiv_mem[REGNO (operand1)];
1690 else if (scratch_reg
1691 && reload_in_progress && GET_CODE (operand1) == SUBREG
1692 && GET_CODE (SUBREG_REG (operand1)) == REG
1693 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1695 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1696 the code which tracks sets/uses for delete_output_reload. */
1697 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1698 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1699 SUBREG_BYTE (operand1));
1700 operand1 = alter_subreg (&temp);
1703 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1704 && ((tem = find_replacement (&XEXP (operand0, 0)))
1705 != XEXP (operand0, 0)))
1706 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1708 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1709 && ((tem = find_replacement (&XEXP (operand1, 0)))
1710 != XEXP (operand1, 0)))
1711 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1713 /* Handle secondary reloads for loads/stores of FP registers from
1714 REG+D addresses where D does not fit in 5 or 14 bits, including
1715 (subreg (mem (addr))) cases. */
1717 && fp_reg_operand (operand0, mode)
1718 && ((GET_CODE (operand1) == MEM
1719 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1720 XEXP (operand1, 0)))
1721 || ((GET_CODE (operand1) == SUBREG
1722 && GET_CODE (XEXP (operand1, 0)) == MEM
1723 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1725 XEXP (XEXP (operand1, 0), 0))))))
1727 if (GET_CODE (operand1) == SUBREG)
1728 operand1 = XEXP (operand1, 0);
1730 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1731 it in WORD_MODE regardless of what mode it was originally given
1733 scratch_reg = force_mode (word_mode, scratch_reg);
1735 /* D might not fit in 14 bits either; for such cases load D into
1737 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1739 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1740 emit_move_insn (scratch_reg,
1741 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1743 XEXP (XEXP (operand1, 0), 0),
1747 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1748 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1749 gen_rtx_MEM (mode, scratch_reg)));
1752 else if (scratch_reg
1753 && fp_reg_operand (operand1, mode)
1754 && ((GET_CODE (operand0) == MEM
1755 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1757 XEXP (operand0, 0)))
1758 || ((GET_CODE (operand0) == SUBREG)
1759 && GET_CODE (XEXP (operand0, 0)) == MEM
1760 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1762 XEXP (XEXP (operand0, 0), 0)))))
1764 if (GET_CODE (operand0) == SUBREG)
1765 operand0 = XEXP (operand0, 0);
1767 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1768 it in WORD_MODE regardless of what mode it was originally given
1770 scratch_reg = force_mode (word_mode, scratch_reg);
1772 /* D might not fit in 14 bits either; for such cases load D into
1774 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1776 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1777 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1780 XEXP (XEXP (operand0, 0),
1785 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1786 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1790 /* Handle secondary reloads for loads of FP registers from constant
1791 expressions by forcing the constant into memory.
1793 Use scratch_reg to hold the address of the memory location.
1795 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1796 NO_REGS when presented with a const_int and a register class
1797 containing only FP registers. Doing so unfortunately creates
1798 more problems than it solves. Fix this for 2.5. */
1799 else if (scratch_reg
1800 && CONSTANT_P (operand1)
1801 && fp_reg_operand (operand0, mode))
1805 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1806 it in WORD_MODE regardless of what mode it was originally given
1808 scratch_reg = force_mode (word_mode, scratch_reg);
1810 /* Force the constant into memory and put the address of the
1811 memory location into scratch_reg. */
1812 xoperands[0] = scratch_reg;
1813 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1814 emit_move_sequence (xoperands, Pmode, 0);
1816 /* Now load the destination register. */
1817 emit_insn (gen_rtx_SET (mode, operand0,
1818 gen_rtx_MEM (mode, scratch_reg)));
1821 /* Handle secondary reloads for SAR. These occur when trying to load
1822 the SAR from memory, FP register, or with a constant. */
1823 else if (scratch_reg
1824 && GET_CODE (operand0) == REG
1825 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1826 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1827 && (GET_CODE (operand1) == MEM
1828 || GET_CODE (operand1) == CONST_INT
1829 || (GET_CODE (operand1) == REG
1830 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1832 /* D might not fit in 14 bits either; for such cases load D into
1834 if (GET_CODE (operand1) == MEM
1835 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1837 /* We are reloading the address into the scratch register, so we
1838 want to make sure the scratch register is a full register. */
1839 scratch_reg = force_mode (word_mode, scratch_reg);
1841 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1842 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1845 XEXP (XEXP (operand1, 0),
1849 /* Now we are going to load the scratch register from memory,
1850 we want to load it in the same width as the original MEM,
1851 which must be the same as the width of the ultimate destination,
1853 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1855 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1860 /* We want to load the scratch register using the same mode as
1861 the ultimate destination. */
1862 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1864 emit_move_insn (scratch_reg, operand1);
1867 /* And emit the insn to set the ultimate destination. We know that
1868 the scratch register has the same mode as the destination at this
1870 emit_move_insn (operand0, scratch_reg);
1873 /* Handle the most common case: storing into a register. */
1874 else if (register_operand (operand0, mode))
1876 if (register_operand (operand1, mode)
1877 || (GET_CODE (operand1) == CONST_INT
1878 && cint_ok_for_move (INTVAL (operand1)))
1879 || (operand1 == CONST0_RTX (mode))
1880 || (GET_CODE (operand1) == HIGH
1881 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1882 /* Only `general_operands' can come here, so MEM is ok. */
1883 || GET_CODE (operand1) == MEM)
1885 /* Various sets are created during RTL generation which don't
1886 have the REG_POINTER flag correctly set. After the CSE pass,
1887 instruction recognition can fail if we don't consistently
1888 set this flag when performing register copies. This should
1889 also improve the opportunities for creating insns that use
1890 unscaled indexing. */
1891 if (REG_P (operand0) && REG_P (operand1))
1893 if (REG_POINTER (operand1)
1894 && !REG_POINTER (operand0)
1895 && !HARD_REGISTER_P (operand0))
1896 copy_reg_pointer (operand0, operand1);
1897 else if (REG_POINTER (operand0)
1898 && !REG_POINTER (operand1)
1899 && !HARD_REGISTER_P (operand1))
1900 copy_reg_pointer (operand1, operand0);
1903 /* When MEMs are broken out, the REG_POINTER flag doesn't
1904 get set. In some cases, we can set the REG_POINTER flag
1905 from the declaration for the MEM. */
1906 if (REG_P (operand0)
1907 && GET_CODE (operand1) == MEM
1908 && !REG_POINTER (operand0))
1910 tree decl = MEM_EXPR (operand1);
1912 /* Set the register pointer flag and register alignment
1913 if the declaration for this memory reference is a
1914 pointer type. Fortran indirect argument references
1917 && !(flag_argument_noalias > 1
1918 && TREE_CODE (decl) == INDIRECT_REF
1919 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1923 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1925 if (TREE_CODE (decl) == COMPONENT_REF)
1926 decl = TREE_OPERAND (decl, 1);
1928 type = TREE_TYPE (decl);
1929 if (TREE_CODE (type) == ARRAY_TYPE)
1930 type = get_inner_array_type (type);
1932 if (POINTER_TYPE_P (type))
1936 type = TREE_TYPE (type);
1937 /* Using TYPE_ALIGN_OK is rather conservative as
1938 only the ada frontend actually sets it. */
1939 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1941 mark_reg_pointer (operand0, align);
1946 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1950 else if (GET_CODE (operand0) == MEM)
1952 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1953 && !(reload_in_progress || reload_completed))
1955 rtx temp = gen_reg_rtx (DFmode);
1957 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1958 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1961 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1963 /* Run this case quickly. */
1964 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1967 if (! (reload_in_progress || reload_completed))
1969 operands[0] = validize_mem (operand0);
1970 operands[1] = operand1 = force_reg (mode, operand1);
1974 /* Simplify the source if we need to.
1975 Note we do have to handle function labels here, even though we do
1976 not consider them legitimate constants. Loop optimizations can
1977 call the emit_move_xxx with one as a source. */
1978 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1979 || function_label_operand (operand1, mode)
1980 || (GET_CODE (operand1) == HIGH
1981 && symbolic_operand (XEXP (operand1, 0), mode)))
1985 if (GET_CODE (operand1) == HIGH)
1988 operand1 = XEXP (operand1, 0);
1990 if (symbolic_operand (operand1, mode))
1992 /* Argh. The assembler and linker can't handle arithmetic
1995 So we force the plabel into memory, load operand0 from
1996 the memory location, then add in the constant part. */
1997 if ((GET_CODE (operand1) == CONST
1998 && GET_CODE (XEXP (operand1, 0)) == PLUS
1999 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
2000 || function_label_operand (operand1, mode))
2002 rtx temp, const_part;
2004 /* Figure out what (if any) scratch register to use. */
2005 if (reload_in_progress || reload_completed)
2007 scratch_reg = scratch_reg ? scratch_reg : operand0;
2008 /* SCRATCH_REG will hold an address and maybe the actual
2009 data. We want it in WORD_MODE regardless of what mode it
2010 was originally given to us. */
2011 scratch_reg = force_mode (word_mode, scratch_reg);
2014 scratch_reg = gen_reg_rtx (Pmode);
2016 if (GET_CODE (operand1) == CONST)
2018 /* Save away the constant part of the expression. */
2019 const_part = XEXP (XEXP (operand1, 0), 1);
2020 if (GET_CODE (const_part) != CONST_INT)
2023 /* Force the function label into memory. */
2024 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
2028 /* No constant part. */
2029 const_part = NULL_RTX;
2031 /* Force the function label into memory. */
2032 temp = force_const_mem (mode, operand1);
2036 /* Get the address of the memory location. PIC-ify it if
2038 temp = XEXP (temp, 0);
2040 temp = legitimize_pic_address (temp, mode, scratch_reg);
2042 /* Put the address of the memory location into our destination
2045 emit_move_sequence (operands, mode, scratch_reg);
2047 /* Now load from the memory location into our destination
2049 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
2050 emit_move_sequence (operands, mode, scratch_reg);
2052 /* And add back in the constant part. */
2053 if (const_part != NULL_RTX)
2054 expand_inc (operand0, const_part);
2063 if (reload_in_progress || reload_completed)
2065 temp = scratch_reg ? scratch_reg : operand0;
2066 /* TEMP will hold an address and maybe the actual
2067 data. We want it in WORD_MODE regardless of what mode it
2068 was originally given to us. */
2069 temp = force_mode (word_mode, temp);
2072 temp = gen_reg_rtx (Pmode);
2074 /* (const (plus (symbol) (const_int))) must be forced to
2075 memory during/after reload if the const_int will not fit
2077 if (GET_CODE (operand1) == CONST
2078 && GET_CODE (XEXP (operand1, 0)) == PLUS
2079 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
2080 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
2081 && (reload_completed || reload_in_progress)
2084 operands[1] = force_const_mem (mode, operand1);
2085 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
2087 operands[1] = gen_rtx_MEM (mode, operands[1]);
2088 emit_move_sequence (operands, mode, temp);
2092 operands[1] = legitimize_pic_address (operand1, mode, temp);
2093 if (REG_P (operand0) && REG_P (operands[1]))
2094 copy_reg_pointer (operand0, operands[1]);
2095 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
2098 /* On the HPPA, references to data space are supposed to use dp,
2099 register 27, but showing it in the RTL inhibits various cse
2100 and loop optimizations. */
2105 if (reload_in_progress || reload_completed)
2107 temp = scratch_reg ? scratch_reg : operand0;
2108 /* TEMP will hold an address and maybe the actual
2109 data. We want it in WORD_MODE regardless of what mode it
2110 was originally given to us. */
2111 temp = force_mode (word_mode, temp);
2114 temp = gen_reg_rtx (mode);
2116 /* Loading a SYMBOL_REF into a register makes that register
2117 safe to be used as the base in an indexed address.
2119 Don't mark hard registers though. That loses. */
2120 if (GET_CODE (operand0) == REG
2121 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2122 mark_reg_pointer (operand0, BITS_PER_UNIT);
2123 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
2124 mark_reg_pointer (temp, BITS_PER_UNIT);
2127 set = gen_rtx_SET (mode, operand0, temp);
2129 set = gen_rtx_SET (VOIDmode,
2131 gen_rtx_LO_SUM (mode, temp, operand1));
2133 emit_insn (gen_rtx_SET (VOIDmode,
2135 gen_rtx_HIGH (mode, operand1)));
2141 else if (GET_CODE (operand1) != CONST_INT
2142 || !cint_ok_for_move (INTVAL (operand1)))
2146 HOST_WIDE_INT value = 0;
2147 HOST_WIDE_INT insv = 0;
2150 if (GET_CODE (operand1) == CONST_INT)
2151 value = INTVAL (operand1);
2154 && GET_CODE (operand1) == CONST_INT
2155 && HOST_BITS_PER_WIDE_INT > 32
2156 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2160 /* Extract the low order 32 bits of the value and sign extend.
2161 If the new value is the same as the original value, we can
2162 can use the original value as-is. If the new value is
2163 different, we use it and insert the most-significant 32-bits
2164 of the original value into the final result. */
2165 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2166 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2169 #if HOST_BITS_PER_WIDE_INT > 32
2170 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2174 operand1 = GEN_INT (nval);
2178 if (reload_in_progress || reload_completed)
2179 temp = scratch_reg ? scratch_reg : operand0;
2181 temp = gen_reg_rtx (mode);
2183 /* We don't directly split DImode constants on 32-bit targets
2184 because PLUS uses an 11-bit immediate and the insn sequence
2185 generated is not as efficient as the one using HIGH/LO_SUM. */
2186 if (GET_CODE (operand1) == CONST_INT
2187 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2190 /* Directly break constant into high and low parts. This
2191 provides better optimization opportunities because various
2192 passes recognize constants split with PLUS but not LO_SUM.
2193 We use a 14-bit signed low part except when the addition
2194 of 0x4000 to the high part might change the sign of the
2196 HOST_WIDE_INT low = value & 0x3fff;
2197 HOST_WIDE_INT high = value & ~ 0x3fff;
2201 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2209 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2210 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2214 emit_insn (gen_rtx_SET (VOIDmode, temp,
2215 gen_rtx_HIGH (mode, operand1)));
2216 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2219 insn = emit_move_insn (operands[0], operands[1]);
2221 /* Now insert the most significant 32 bits of the value
2222 into the register. When we don't have a second register
2223 available, it could take up to nine instructions to load
2224 a 64-bit integer constant. Prior to reload, we force
2225 constants that would take more than three instructions
2226 to load to the constant pool. During and after reload,
2227 we have to handle all possible values. */
2230 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2231 register and the value to be inserted is outside the
2232 range that can be loaded with three depdi instructions. */
2233 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2235 operand1 = GEN_INT (insv);
2237 emit_insn (gen_rtx_SET (VOIDmode, temp,
2238 gen_rtx_HIGH (mode, operand1)));
2239 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2240 emit_insn (gen_insv (operand0, GEN_INT (32),
2245 int len = 5, pos = 27;
2247 /* Insert the bits using the depdi instruction. */
2250 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2251 HOST_WIDE_INT sign = v5 < 0;
2253 /* Left extend the insertion. */
2254 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2255 while (pos > 0 && (insv & 1) == sign)
2257 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2262 emit_insn (gen_insv (operand0, GEN_INT (len),
2263 GEN_INT (pos), GEN_INT (v5)));
2265 len = pos > 0 && pos < 5 ? pos : 5;
2272 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
2277 /* Now have insn-emit do whatever it normally does. */
2281 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2282 it will need a link/runtime reloc). */
2285 reloc_needed (tree exp)
2289 switch (TREE_CODE (exp))
2296 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2297 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2302 case NON_LVALUE_EXPR:
2303 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2309 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
2310 if (TREE_VALUE (link) != 0)
2311 reloc |= reloc_needed (TREE_VALUE (link));
2324 /* Does operand (which is a symbolic_operand) live in text space?
2325 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2329 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2331 if (GET_CODE (operand) == CONST)
2332 operand = XEXP (XEXP (operand, 0), 0);
2335 if (GET_CODE (operand) == SYMBOL_REF)
2336 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2340 if (GET_CODE (operand) == SYMBOL_REF)
2341 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2347 /* Return the best assembler insn template
2348 for moving operands[1] into operands[0] as a fullword. */
2350 singlemove_string (rtx *operands)
2352 HOST_WIDE_INT intval;
2354 if (GET_CODE (operands[0]) == MEM)
2355 return "stw %r1,%0";
2356 if (GET_CODE (operands[1]) == MEM)
2358 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2363 if (GET_MODE (operands[1]) != SFmode)
2366 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2368 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2369 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2371 operands[1] = GEN_INT (i);
2372 /* Fall through to CONST_INT case. */
2374 if (GET_CODE (operands[1]) == CONST_INT)
2376 intval = INTVAL (operands[1]);
2378 if (VAL_14_BITS_P (intval))
2380 else if ((intval & 0x7ff) == 0)
2381 return "ldil L'%1,%0";
2382 else if (zdepi_cint_p (intval))
2383 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2385 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2387 return "copy %1,%0";
2391 /* Compute position (in OP[1]) and width (in OP[2])
2392 useful for copying IMM to a register using the zdepi
2393 instructions. Store the immediate value to insert in OP[0]. */
2395 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2399 /* Find the least significant set bit in IMM. */
2400 for (lsb = 0; lsb < 32; lsb++)
2407 /* Choose variants based on *sign* of the 5-bit field. */
2408 if ((imm & 0x10) == 0)
2409 len = (lsb <= 28) ? 4 : 32 - lsb;
2412 /* Find the width of the bitstring in IMM. */
2413 for (len = 5; len < 32; len++)
2415 if ((imm & (1 << len)) == 0)
2419 /* Sign extend IMM as a 5-bit value. */
2420 imm = (imm & 0xf) - 0x10;
2428 /* Compute position (in OP[1]) and width (in OP[2])
2429 useful for copying IMM to a register using the depdi,z
2430 instructions. Store the immediate value to insert in OP[0]. */
2432 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2434 HOST_WIDE_INT lsb, len;
2436 /* Find the least significant set bit in IMM. */
2437 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2444 /* Choose variants based on *sign* of the 5-bit field. */
2445 if ((imm & 0x10) == 0)
2446 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2447 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2450 /* Find the width of the bitstring in IMM. */
2451 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2453 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2457 /* Sign extend IMM as a 5-bit value. */
2458 imm = (imm & 0xf) - 0x10;
2466 /* Output assembler code to perform a doubleword move insn
2467 with operands OPERANDS. */
2470 output_move_double (rtx *operands)
2472 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2474 rtx addreg0 = 0, addreg1 = 0;
2476 /* First classify both operands. */
2478 if (REG_P (operands[0]))
2480 else if (offsettable_memref_p (operands[0]))
2482 else if (GET_CODE (operands[0]) == MEM)
2487 if (REG_P (operands[1]))
2489 else if (CONSTANT_P (operands[1]))
2491 else if (offsettable_memref_p (operands[1]))
2493 else if (GET_CODE (operands[1]) == MEM)
2498 /* Check for the cases that the operand constraints are not
2499 supposed to allow to happen. Abort if we get one,
2500 because generating code for these cases is painful. */
2502 if (optype0 != REGOP && optype1 != REGOP)
2505 /* Handle auto decrementing and incrementing loads and stores
2506 specifically, since the structure of the function doesn't work
2507 for them without major modification. Do it better when we learn
2508 this port about the general inc/dec addressing of PA.
2509 (This was written by tege. Chide him if it doesn't work.) */
2511 if (optype0 == MEMOP)
2513 /* We have to output the address syntax ourselves, since print_operand
2514 doesn't deal with the addresses we want to use. Fix this later. */
2516 rtx addr = XEXP (operands[0], 0);
2517 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2519 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2521 operands[0] = XEXP (addr, 0);
2522 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2525 if (!reg_overlap_mentioned_p (high_reg, addr))
2527 /* No overlap between high target register and address
2528 register. (We do this in a non-obvious way to
2529 save a register file writeback) */
2530 if (GET_CODE (addr) == POST_INC)
2531 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2532 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2537 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2539 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2541 operands[0] = XEXP (addr, 0);
2542 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2545 if (!reg_overlap_mentioned_p (high_reg, addr))
2547 /* No overlap between high target register and address
2548 register. (We do this in a non-obvious way to
2549 save a register file writeback) */
2550 if (GET_CODE (addr) == PRE_INC)
2551 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2552 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2558 if (optype1 == MEMOP)
2560 /* We have to output the address syntax ourselves, since print_operand
2561 doesn't deal with the addresses we want to use. Fix this later. */
2563 rtx addr = XEXP (operands[1], 0);
2564 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2566 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2568 operands[1] = XEXP (addr, 0);
2569 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2572 if (!reg_overlap_mentioned_p (high_reg, addr))
2574 /* No overlap between high target register and address
2575 register. (We do this in a non-obvious way to
2576 save a register file writeback) */
2577 if (GET_CODE (addr) == POST_INC)
2578 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2579 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2583 /* This is an undefined situation. We should load into the
2584 address register *and* update that register. Probably
2585 we don't need to handle this at all. */
2586 if (GET_CODE (addr) == POST_INC)
2587 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2588 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2591 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2593 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2595 operands[1] = XEXP (addr, 0);
2596 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2599 if (!reg_overlap_mentioned_p (high_reg, addr))
2601 /* No overlap between high target register and address
2602 register. (We do this in a non-obvious way to
2603 save a register file writeback) */
2604 if (GET_CODE (addr) == PRE_INC)
2605 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2606 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2610 /* This is an undefined situation. We should load into the
2611 address register *and* update that register. Probably
2612 we don't need to handle this at all. */
2613 if (GET_CODE (addr) == PRE_INC)
2614 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2615 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2618 else if (GET_CODE (addr) == PLUS
2619 && GET_CODE (XEXP (addr, 0)) == MULT)
2621 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2623 if (!reg_overlap_mentioned_p (high_reg, addr))
2627 xoperands[0] = high_reg;
2628 xoperands[1] = XEXP (addr, 1);
2629 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2630 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2631 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2633 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2639 xoperands[0] = high_reg;
2640 xoperands[1] = XEXP (addr, 1);
2641 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2642 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2643 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2645 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2650 /* If an operand is an unoffsettable memory ref, find a register
2651 we can increment temporarily to make it refer to the second word. */
2653 if (optype0 == MEMOP)
2654 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2656 if (optype1 == MEMOP)
2657 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2659 /* Ok, we can do one word at a time.
2660 Normally we do the low-numbered word first.
2662 In either case, set up in LATEHALF the operands to use
2663 for the high-numbered word and in some cases alter the
2664 operands in OPERANDS to be suitable for the low-numbered word. */
2666 if (optype0 == REGOP)
2667 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2668 else if (optype0 == OFFSOP)
2669 latehalf[0] = adjust_address (operands[0], SImode, 4);
2671 latehalf[0] = operands[0];
2673 if (optype1 == REGOP)
2674 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2675 else if (optype1 == OFFSOP)
2676 latehalf[1] = adjust_address (operands[1], SImode, 4);
2677 else if (optype1 == CNSTOP)
2678 split_double (operands[1], &operands[1], &latehalf[1]);
2680 latehalf[1] = operands[1];
2682 /* If the first move would clobber the source of the second one,
2683 do them in the other order.
2685 This can happen in two cases:
2687 mem -> register where the first half of the destination register
2688 is the same register used in the memory's address. Reload
2689 can create such insns.
2691 mem in this case will be either register indirect or register
2692 indirect plus a valid offset.
2694 register -> register move where REGNO(dst) == REGNO(src + 1)
2695 someone (Tim/Tege?) claimed this can happen for parameter loads.
2697 Handle mem -> register case first. */
2698 if (optype0 == REGOP
2699 && (optype1 == MEMOP || optype1 == OFFSOP)
2700 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2703 /* Do the late half first. */
2705 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2706 output_asm_insn (singlemove_string (latehalf), latehalf);
2710 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2711 return singlemove_string (operands);
2714 /* Now handle register -> register case. */
2715 if (optype0 == REGOP && optype1 == REGOP
2716 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2718 output_asm_insn (singlemove_string (latehalf), latehalf);
2719 return singlemove_string (operands);
2722 /* Normal case: do the two words, low-numbered first. */
2724 output_asm_insn (singlemove_string (operands), operands);
2726 /* Make any unoffsettable addresses point at high-numbered word. */
2728 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2730 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2733 output_asm_insn (singlemove_string (latehalf), latehalf);
2735 /* Undo the adds we just did. */
2737 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2739 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2745 output_fp_move_double (rtx *operands)
2747 if (FP_REG_P (operands[0]))
2749 if (FP_REG_P (operands[1])
2750 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2751 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2753 output_asm_insn ("fldd%F1 %1,%0", operands);
2755 else if (FP_REG_P (operands[1]))
2757 output_asm_insn ("fstd%F0 %1,%0", operands);
2759 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2761 if (GET_CODE (operands[0]) == REG)
2764 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2765 xoperands[0] = operands[0];
2766 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2768 /* This is a pain. You have to be prepared to deal with an
2769 arbitrary address here including pre/post increment/decrement.
2771 so avoid this in the MD. */
2779 /* Return a REG that occurs in ADDR with coefficient 1.
2780 ADDR can be effectively incremented by incrementing REG. */
2783 find_addr_reg (rtx addr)
2785 while (GET_CODE (addr) == PLUS)
2787 if (GET_CODE (XEXP (addr, 0)) == REG)
2788 addr = XEXP (addr, 0);
2789 else if (GET_CODE (XEXP (addr, 1)) == REG)
2790 addr = XEXP (addr, 1);
2791 else if (CONSTANT_P (XEXP (addr, 0)))
2792 addr = XEXP (addr, 1);
2793 else if (CONSTANT_P (XEXP (addr, 1)))
2794 addr = XEXP (addr, 0);
2798 if (GET_CODE (addr) == REG)
2803 /* Emit code to perform a block move.
2805 OPERANDS[0] is the destination pointer as a REG, clobbered.
2806 OPERANDS[1] is the source pointer as a REG, clobbered.
2807 OPERANDS[2] is a register for temporary storage.
2808 OPERANDS[3] is a register for temporary storage.
2809 OPERANDS[4] is the size as a CONST_INT
2810 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2811 OPERANDS[6] is another temporary register. */
2814 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2816 int align = INTVAL (operands[5]);
2817 unsigned long n_bytes = INTVAL (operands[4]);
2819 /* We can't move more than a word at a time because the PA
2820 has no longer integer move insns. (Could use fp mem ops?) */
2821 if (align > (TARGET_64BIT ? 8 : 4))
2822 align = (TARGET_64BIT ? 8 : 4);
2824 /* Note that we know each loop below will execute at least twice
2825 (else we would have open-coded the copy). */
2829 /* Pre-adjust the loop counter. */
2830 operands[4] = GEN_INT (n_bytes - 16);
2831 output_asm_insn ("ldi %4,%2", operands);
2834 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2835 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2836 output_asm_insn ("std,ma %3,8(%0)", operands);
2837 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2838 output_asm_insn ("std,ma %6,8(%0)", operands);
2840 /* Handle the residual. There could be up to 7 bytes of
2841 residual to copy! */
2842 if (n_bytes % 16 != 0)
2844 operands[4] = GEN_INT (n_bytes % 8);
2845 if (n_bytes % 16 >= 8)
2846 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2847 if (n_bytes % 8 != 0)
2848 output_asm_insn ("ldd 0(%1),%6", operands);
2849 if (n_bytes % 16 >= 8)
2850 output_asm_insn ("std,ma %3,8(%0)", operands);
2851 if (n_bytes % 8 != 0)
2852 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2857 /* Pre-adjust the loop counter. */
2858 operands[4] = GEN_INT (n_bytes - 8);
2859 output_asm_insn ("ldi %4,%2", operands);
2862 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2863 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2864 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2865 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2866 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2868 /* Handle the residual. There could be up to 7 bytes of
2869 residual to copy! */
2870 if (n_bytes % 8 != 0)
2872 operands[4] = GEN_INT (n_bytes % 4);
2873 if (n_bytes % 8 >= 4)
2874 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2875 if (n_bytes % 4 != 0)
2876 output_asm_insn ("ldw 0(%1),%6", operands);
2877 if (n_bytes % 8 >= 4)
2878 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2879 if (n_bytes % 4 != 0)
2880 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2885 /* Pre-adjust the loop counter. */
2886 operands[4] = GEN_INT (n_bytes - 4);
2887 output_asm_insn ("ldi %4,%2", operands);
2890 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2891 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2892 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2893 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2894 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2896 /* Handle the residual. */
2897 if (n_bytes % 4 != 0)
2899 if (n_bytes % 4 >= 2)
2900 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2901 if (n_bytes % 2 != 0)
2902 output_asm_insn ("ldb 0(%1),%6", operands);
2903 if (n_bytes % 4 >= 2)
2904 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2905 if (n_bytes % 2 != 0)
2906 output_asm_insn ("stb %6,0(%0)", operands);
2911 /* Pre-adjust the loop counter. */
2912 operands[4] = GEN_INT (n_bytes - 2);
2913 output_asm_insn ("ldi %4,%2", operands);
2916 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2917 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2918 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2919 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2920 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2922 /* Handle the residual. */
2923 if (n_bytes % 2 != 0)
2925 output_asm_insn ("ldb 0(%1),%3", operands);
2926 output_asm_insn ("stb %3,0(%0)", operands);
2935 /* Count the number of insns necessary to handle this block move.
2937 Basic structure is the same as emit_block_move, except that we
2938 count insns rather than emit them. */
2941 compute_movmem_length (rtx insn)
2943 rtx pat = PATTERN (insn);
2944 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2945 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2946 unsigned int n_insns = 0;
2948 /* We can't move more than four bytes at a time because the PA
2949 has no longer integer move insns. (Could use fp mem ops?) */
2950 if (align > (TARGET_64BIT ? 8 : 4))
2951 align = (TARGET_64BIT ? 8 : 4);
2953 /* The basic copying loop. */
2957 if (n_bytes % (2 * align) != 0)
2959 if ((n_bytes % (2 * align)) >= align)
2962 if ((n_bytes % align) != 0)
2966 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2970 /* Emit code to perform a block clear.
2972 OPERANDS[0] is the destination pointer as a REG, clobbered.
2973 OPERANDS[1] is a register for temporary storage.
2974 OPERANDS[2] is the size as a CONST_INT
2975 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2978 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2980 int align = INTVAL (operands[3]);
2981 unsigned long n_bytes = INTVAL (operands[2]);
2983 /* We can't clear more than a word at a time because the PA
2984 has no longer integer move insns. */
2985 if (align > (TARGET_64BIT ? 8 : 4))
2986 align = (TARGET_64BIT ? 8 : 4);
2988 /* Note that we know each loop below will execute at least twice
2989 (else we would have open-coded the copy). */
2993 /* Pre-adjust the loop counter. */
2994 operands[2] = GEN_INT (n_bytes - 16);
2995 output_asm_insn ("ldi %2,%1", operands);
2998 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2999 output_asm_insn ("addib,>= -16,%1,.-4", operands);
3000 output_asm_insn ("std,ma %%r0,8(%0)", operands);
3002 /* Handle the residual. There could be up to 7 bytes of
3003 residual to copy! */
3004 if (n_bytes % 16 != 0)
3006 operands[2] = GEN_INT (n_bytes % 8);
3007 if (n_bytes % 16 >= 8)
3008 output_asm_insn ("std,ma %%r0,8(%0)", operands);
3009 if (n_bytes % 8 != 0)
3010 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
3015 /* Pre-adjust the loop counter. */
3016 operands[2] = GEN_INT (n_bytes - 8);
3017 output_asm_insn ("ldi %2,%1", operands);
3020 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3021 output_asm_insn ("addib,>= -8,%1,.-4", operands);
3022 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3024 /* Handle the residual. There could be up to 7 bytes of
3025 residual to copy! */
3026 if (n_bytes % 8 != 0)
3028 operands[2] = GEN_INT (n_bytes % 4);
3029 if (n_bytes % 8 >= 4)
3030 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3031 if (n_bytes % 4 != 0)
3032 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
3037 /* Pre-adjust the loop counter. */
3038 operands[2] = GEN_INT (n_bytes - 4);
3039 output_asm_insn ("ldi %2,%1", operands);
3042 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3043 output_asm_insn ("addib,>= -4,%1,.-4", operands);
3044 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3046 /* Handle the residual. */
3047 if (n_bytes % 4 != 0)
3049 if (n_bytes % 4 >= 2)
3050 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3051 if (n_bytes % 2 != 0)
3052 output_asm_insn ("stb %%r0,0(%0)", operands);
3057 /* Pre-adjust the loop counter. */
3058 operands[2] = GEN_INT (n_bytes - 2);
3059 output_asm_insn ("ldi %2,%1", operands);
3062 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3063 output_asm_insn ("addib,>= -2,%1,.-4", operands);
3064 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3066 /* Handle the residual. */
3067 if (n_bytes % 2 != 0)
3068 output_asm_insn ("stb %%r0,0(%0)", operands);
3077 /* Count the number of insns necessary to handle this block move.
3079 Basic structure is the same as emit_block_move, except that we
3080 count insns rather than emit them. */
3083 compute_clrmem_length (rtx insn)
3085 rtx pat = PATTERN (insn);
3086 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
3087 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
3088 unsigned int n_insns = 0;
3090 /* We can't clear more than a word at a time because the PA
3091 has no longer integer move insns. */
3092 if (align > (TARGET_64BIT ? 8 : 4))
3093 align = (TARGET_64BIT ? 8 : 4);
3095 /* The basic loop. */
3099 if (n_bytes % (2 * align) != 0)
3101 if ((n_bytes % (2 * align)) >= align)
3104 if ((n_bytes % align) != 0)
3108 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3114 output_and (rtx *operands)
3116 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3118 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3119 int ls0, ls1, ms0, p, len;
3121 for (ls0 = 0; ls0 < 32; ls0++)
3122 if ((mask & (1 << ls0)) == 0)
3125 for (ls1 = ls0; ls1 < 32; ls1++)
3126 if ((mask & (1 << ls1)) != 0)
3129 for (ms0 = ls1; ms0 < 32; ms0++)
3130 if ((mask & (1 << ms0)) == 0)
3143 operands[2] = GEN_INT (len);
3144 return "{extru|extrw,u} %1,31,%2,%0";
3148 /* We could use this `depi' for the case above as well, but `depi'
3149 requires one more register file access than an `extru'. */
3154 operands[2] = GEN_INT (p);
3155 operands[3] = GEN_INT (len);
3156 return "{depi|depwi} 0,%2,%3,%0";
3160 return "and %1,%2,%0";
3163 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3164 storing the result in operands[0]. */
3166 output_64bit_and (rtx *operands)
3168 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3170 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3171 int ls0, ls1, ms0, p, len;
3173 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3174 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3177 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3178 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3181 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3182 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3185 if (ms0 != HOST_BITS_PER_WIDE_INT)
3188 if (ls1 == HOST_BITS_PER_WIDE_INT)
3195 operands[2] = GEN_INT (len);
3196 return "extrd,u %1,63,%2,%0";
3200 /* We could use this `depi' for the case above as well, but `depi'
3201 requires one more register file access than an `extru'. */
3206 operands[2] = GEN_INT (p);
3207 operands[3] = GEN_INT (len);
3208 return "depdi 0,%2,%3,%0";
3212 return "and %1,%2,%0";
3216 output_ior (rtx *operands)
3218 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3219 int bs0, bs1, p, len;
3221 if (INTVAL (operands[2]) == 0)
3222 return "copy %1,%0";
3224 for (bs0 = 0; bs0 < 32; bs0++)
3225 if ((mask & (1 << bs0)) != 0)
3228 for (bs1 = bs0; bs1 < 32; bs1++)
3229 if ((mask & (1 << bs1)) == 0)
3232 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3238 operands[2] = GEN_INT (p);
3239 operands[3] = GEN_INT (len);
3240 return "{depi|depwi} -1,%2,%3,%0";
3243 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3244 storing the result in operands[0]. */
3246 output_64bit_ior (rtx *operands)
3248 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3249 int bs0, bs1, p, len;
3251 if (INTVAL (operands[2]) == 0)
3252 return "copy %1,%0";
3254 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3255 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3258 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3259 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3262 if (bs1 != HOST_BITS_PER_WIDE_INT
3263 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3269 operands[2] = GEN_INT (p);
3270 operands[3] = GEN_INT (len);
3271 return "depdi -1,%2,%3,%0";
3274 /* Target hook for assembling integer objects. This code handles
3275 aligned SI and DI integers specially, since function references must
3276 be preceded by P%. */
3279 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3281 if (size == UNITS_PER_WORD && aligned_p
3282 && function_label_operand (x, VOIDmode))
3284 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3285 output_addr_const (asm_out_file, x);
3286 fputc ('\n', asm_out_file);
3289 return default_assemble_integer (x, size, aligned_p);
3292 /* Output an ascii string. */
3294 output_ascii (FILE *file, const char *p, int size)
3298 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3300 /* The HP assembler can only take strings of 256 characters at one
3301 time. This is a limitation on input line length, *not* the
3302 length of the string. Sigh. Even worse, it seems that the
3303 restriction is in number of input characters (see \xnn &
3304 \whatever). So we have to do this very carefully. */
3306 fputs ("\t.STRING \"", file);
3309 for (i = 0; i < size; i += 4)
3313 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3315 register unsigned int c = (unsigned char) p[i + io];
3317 if (c == '\"' || c == '\\')
3318 partial_output[co++] = '\\';
3319 if (c >= ' ' && c < 0177)
3320 partial_output[co++] = c;
3324 partial_output[co++] = '\\';
3325 partial_output[co++] = 'x';
3326 hexd = c / 16 - 0 + '0';
3328 hexd -= '9' - 'a' + 1;
3329 partial_output[co++] = hexd;
3330 hexd = c % 16 - 0 + '0';
3332 hexd -= '9' - 'a' + 1;
3333 partial_output[co++] = hexd;
3336 if (chars_output + co > 243)
3338 fputs ("\"\n\t.STRING \"", file);
3341 fwrite (partial_output, 1, (size_t) co, file);
3345 fputs ("\"\n", file);
3348 /* Try to rewrite floating point comparisons & branches to avoid
3349 useless add,tr insns.
3351 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3352 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3353 first attempt to remove useless add,tr insns. It is zero
3354 for the second pass as reorg sometimes leaves bogus REG_DEAD
3357 When CHECK_NOTES is zero we can only eliminate add,tr insns
3358 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3361 remove_useless_addtr_insns (int check_notes)
3364 static int pass = 0;
3366 /* This is fairly cheap, so always run it when optimizing. */
3370 int fbranch_count = 0;
3372 /* Walk all the insns in this function looking for fcmp & fbranch
3373 instructions. Keep track of how many of each we find. */
3374 for (insn = get_insns (); insn; insn = next_insn (insn))
3378 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3379 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3382 tmp = PATTERN (insn);
3384 /* It must be a set. */
3385 if (GET_CODE (tmp) != SET)
3388 /* If the destination is CCFP, then we've found an fcmp insn. */
3389 tmp = SET_DEST (tmp);
3390 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3396 tmp = PATTERN (insn);
3397 /* If this is an fbranch instruction, bump the fbranch counter. */
3398 if (GET_CODE (tmp) == SET
3399 && SET_DEST (tmp) == pc_rtx
3400 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3401 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3402 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3403 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3411 /* Find all floating point compare + branch insns. If possible,
3412 reverse the comparison & the branch to avoid add,tr insns. */
3413 for (insn = get_insns (); insn; insn = next_insn (insn))
3417 /* Ignore anything that isn't an INSN. */
3418 if (GET_CODE (insn) != INSN)
3421 tmp = PATTERN (insn);
3423 /* It must be a set. */
3424 if (GET_CODE (tmp) != SET)
3427 /* The destination must be CCFP, which is register zero. */
3428 tmp = SET_DEST (tmp);
3429 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3432 /* INSN should be a set of CCFP.
3434 See if the result of this insn is used in a reversed FP
3435 conditional branch. If so, reverse our condition and
3436 the branch. Doing so avoids useless add,tr insns. */
3437 next = next_insn (insn);
3440 /* Jumps, calls and labels stop our search. */
3441 if (GET_CODE (next) == JUMP_INSN
3442 || GET_CODE (next) == CALL_INSN
3443 || GET_CODE (next) == CODE_LABEL)
3446 /* As does another fcmp insn. */
3447 if (GET_CODE (next) == INSN
3448 && GET_CODE (PATTERN (next)) == SET
3449 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3450 && REGNO (SET_DEST (PATTERN (next))) == 0)
3453 next = next_insn (next);
3456 /* Is NEXT_INSN a branch? */
3458 && GET_CODE (next) == JUMP_INSN)
3460 rtx pattern = PATTERN (next);
3462 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3463 and CCFP dies, then reverse our conditional and the branch
3464 to avoid the add,tr. */
3465 if (GET_CODE (pattern) == SET
3466 && SET_DEST (pattern) == pc_rtx
3467 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3468 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3469 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3470 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3471 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3472 && (fcmp_count == fbranch_count
3474 && find_regno_note (next, REG_DEAD, 0))))
3476 /* Reverse the branch. */
3477 tmp = XEXP (SET_SRC (pattern), 1);
3478 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3479 XEXP (SET_SRC (pattern), 2) = tmp;
3480 INSN_CODE (next) = -1;
3482 /* Reverse our condition. */
3483 tmp = PATTERN (insn);
3484 PUT_CODE (XEXP (tmp, 1),
3485 (reverse_condition_maybe_unordered
3486 (GET_CODE (XEXP (tmp, 1)))));
3496 /* You may have trouble believing this, but this is the 32 bit HP-PA
3501 Variable arguments (optional; any number may be allocated)
3503 SP-(4*(N+9)) arg word N
3508 Fixed arguments (must be allocated; may remain unused)
3517 SP-32 External Data Pointer (DP)
3519 SP-24 External/stub RP (RP')
3523 SP-8 Calling Stub RP (RP'')
3528 SP-0 Stack Pointer (points to next available address)
3532 /* This function saves registers as follows. Registers marked with ' are
3533 this function's registers (as opposed to the previous function's).
3534 If a frame_pointer isn't needed, r4 is saved as a general register;
3535 the space for the frame pointer is still allocated, though, to keep
3541 SP (FP') Previous FP
3542 SP + 4 Alignment filler (sigh)
3543 SP + 8 Space for locals reserved here.
3547 SP + n All call saved register used.
3551 SP + o All call saved fp registers used.
3555 SP + p (SP') points to next available address.
3559 /* Global variables set by output_function_prologue(). */
3560 /* Size of frame. Need to know this to emit return insns from
3562 static HOST_WIDE_INT actual_fsize, local_fsize;
3563 static int save_fregs;
3565 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3566 Handle case where DISP > 8k by using the add_high_const patterns.
3568 Note in DISP > 8k case, we will leave the high part of the address
3569 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3572 store_reg (int reg, HOST_WIDE_INT disp, int base)
3574 rtx insn, dest, src, basereg;
3576 src = gen_rtx_REG (word_mode, reg);
3577 basereg = gen_rtx_REG (Pmode, base);
3578 if (VAL_14_BITS_P (disp))
3580 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3581 insn = emit_move_insn (dest, src);
3583 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3585 rtx delta = GEN_INT (disp);
3586 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3588 emit_move_insn (tmpreg, delta);
3589 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3590 dest = gen_rtx_MEM (word_mode, tmpreg);
3591 insn = emit_move_insn (dest, src);
3595 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3596 gen_rtx_SET (VOIDmode,
3597 gen_rtx_MEM (word_mode,
3598 gen_rtx_PLUS (word_mode, basereg,
3606 rtx delta = GEN_INT (disp);
3607 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3608 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3610 emit_move_insn (tmpreg, high);
3611 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3612 insn = emit_move_insn (dest, src);
3616 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3617 gen_rtx_SET (VOIDmode,
3618 gen_rtx_MEM (word_mode,
3619 gen_rtx_PLUS (word_mode, basereg,
3627 RTX_FRAME_RELATED_P (insn) = 1;
3630 /* Emit RTL to store REG at the memory location specified by BASE and then
3631 add MOD to BASE. MOD must be <= 8k. */
3634 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3636 rtx insn, basereg, srcreg, delta;
3638 if (!VAL_14_BITS_P (mod))
3641 basereg = gen_rtx_REG (Pmode, base);
3642 srcreg = gen_rtx_REG (word_mode, reg);
3643 delta = GEN_INT (mod);
3645 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3648 RTX_FRAME_RELATED_P (insn) = 1;
3650 /* RTX_FRAME_RELATED_P must be set on each frame related set
3651 in a parallel with more than one element. Don't set
3652 RTX_FRAME_RELATED_P in the first set if reg is temporary
3653 register 1. The effect of this operation is recorded in
3654 the initial copy. */
3657 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3658 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3662 /* The first element of a PARALLEL is always processed if it is
3663 a SET. Thus, we need an expression list for this case. */
3665 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3666 gen_rtx_SET (VOIDmode, basereg,
3667 gen_rtx_PLUS (word_mode, basereg, delta)),
3673 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3674 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3675 whether to add a frame note or not.
3677 In the DISP > 8k case, we leave the high part of the address in %r1.
3678 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3681 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3685 if (VAL_14_BITS_P (disp))
3687 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3688 plus_constant (gen_rtx_REG (Pmode, base), disp));
3690 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3692 rtx basereg = gen_rtx_REG (Pmode, base);
3693 rtx delta = GEN_INT (disp);
3694 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3696 emit_move_insn (tmpreg, delta);
3697 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3698 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3702 rtx basereg = gen_rtx_REG (Pmode, base);
3703 rtx delta = GEN_INT (disp);
3704 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3706 emit_move_insn (tmpreg,
3707 gen_rtx_PLUS (Pmode, basereg,
3708 gen_rtx_HIGH (Pmode, delta)));
3709 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3710 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3713 if (DO_FRAME_NOTES && note)
3714 RTX_FRAME_RELATED_P (insn) = 1;
3718 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3723 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3724 be consistent with the rounding and size calculation done here.
3725 Change them at the same time. */
3727 /* We do our own stack alignment. First, round the size of the
3728 stack locals up to a word boundary. */
3729 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3731 /* Space for previous frame pointer + filler. If any frame is
3732 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3733 waste some space here for the sake of HP compatibility. The
3734 first slot is only used when the frame pointer is needed. */
3735 if (size || frame_pointer_needed)
3736 size += STARTING_FRAME_OFFSET;
3738 /* If the current function calls __builtin_eh_return, then we need
3739 to allocate stack space for registers that will hold data for
3740 the exception handler. */
3741 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3745 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3747 size += i * UNITS_PER_WORD;
3750 /* Account for space used by the callee general register saves. */
3751 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3752 if (regs_ever_live[i])
3753 size += UNITS_PER_WORD;
3755 /* Account for space used by the callee floating point register saves. */
3756 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3757 if (regs_ever_live[i]
3758 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3762 /* We always save both halves of the FP register, so always
3763 increment the frame size by 8 bytes. */
3767 /* If any of the floating registers are saved, account for the
3768 alignment needed for the floating point register save block. */
3771 size = (size + 7) & ~7;
3776 /* The various ABIs include space for the outgoing parameters in the
3777 size of the current function's stack frame. We don't need to align
3778 for the outgoing arguments as their alignment is set by the final
3779 rounding for the frame as a whole. */
3780 size += current_function_outgoing_args_size;
3782 /* Allocate space for the fixed frame marker. This space must be
3783 allocated for any function that makes calls or allocates
3785 if (!current_function_is_leaf || size)
3786 size += TARGET_64BIT ? 48 : 32;
3788 /* Finally, round to the preferred stack boundary. */
3789 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3790 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3793 /* Generate the assembly code for function entry. FILE is a stdio
3794 stream to output the code to. SIZE is an int: how many units of
3795 temporary storage to allocate.
3797 Refer to the array `regs_ever_live' to determine which registers to
3798 save; `regs_ever_live[I]' is nonzero if register number I is ever
3799 used in the function. This function is responsible for knowing
3800 which registers should not be saved even if used. */
3802 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3803 of memory. If any fpu reg is used in the function, we allocate
3804 such a block here, at the bottom of the frame, just in case it's needed.
3806 If this function is a leaf procedure, then we may choose not
3807 to do a "save" insn. The decision about whether or not
3808 to do this is made in regclass.c. */
3811 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3813 /* The function's label and associated .PROC must never be
3814 separated and must be output *after* any profiling declarations
3815 to avoid changing spaces/subspaces within a procedure. */
3816 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3817 fputs ("\t.PROC\n", file);
3819 /* hppa_expand_prologue does the dirty work now. We just need
3820 to output the assembler directives which denote the start
3822 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3823 if (regs_ever_live[2])
3824 fputs (",CALLS,SAVE_RP", file);
3826 fputs (",NO_CALLS", file);
3828 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3829 at the beginning of the frame and that it is used as the frame
3830 pointer for the frame. We do this because our current frame
3831 layout doesn't conform to that specified in the the HP runtime
3832 documentation and we need a way to indicate to programs such as
3833 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3834 isn't used by HP compilers but is supported by the assembler.
3835 However, SAVE_SP is supposed to indicate that the previous stack
3836 pointer has been saved in the frame marker. */
3837 if (frame_pointer_needed)
3838 fputs (",SAVE_SP", file);
3840 /* Pass on information about the number of callee register saves
3841 performed in the prologue.
3843 The compiler is supposed to pass the highest register number
3844 saved, the assembler then has to adjust that number before
3845 entering it into the unwind descriptor (to account for any
3846 caller saved registers with lower register numbers than the
3847 first callee saved register). */
3849 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3852 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3854 fputs ("\n\t.ENTRY\n", file);
3856 remove_useless_addtr_insns (0);
3860 hppa_expand_prologue (void)
3862 int merge_sp_adjust_with_store = 0;
3863 HOST_WIDE_INT size = get_frame_size ();
3864 HOST_WIDE_INT offset;
3872 /* Compute total size for frame pointer, filler, locals and rounding to
3873 the next word boundary. Similar code appears in compute_frame_size
3874 and must be changed in tandem with this code. */
3875 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3876 if (local_fsize || frame_pointer_needed)
3877 local_fsize += STARTING_FRAME_OFFSET;
3879 actual_fsize = compute_frame_size (size, &save_fregs);
3881 /* Compute a few things we will use often. */
3882 tmpreg = gen_rtx_REG (word_mode, 1);
3884 /* Save RP first. The calling conventions manual states RP will
3885 always be stored into the caller's frame at sp - 20 or sp - 16
3886 depending on which ABI is in use. */
3887 if (regs_ever_live[2] || current_function_calls_eh_return)
3888 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3890 /* Allocate the local frame and set up the frame pointer if needed. */
3891 if (actual_fsize != 0)
3893 if (frame_pointer_needed)
3895 /* Copy the old frame pointer temporarily into %r1. Set up the
3896 new stack pointer, then store away the saved old frame pointer
3897 into the stack at sp and at the same time update the stack
3898 pointer by actual_fsize bytes. Two versions, first
3899 handles small (<8k) frames. The second handles large (>=8k)
3901 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3904 /* We need to record the frame pointer save here since the
3905 new frame pointer is set in the following insn. */
3906 RTX_FRAME_RELATED_P (insn) = 1;
3908 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3909 gen_rtx_SET (VOIDmode,
3910 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3915 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3917 RTX_FRAME_RELATED_P (insn) = 1;
3919 if (VAL_14_BITS_P (actual_fsize))
3920 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3923 /* It is incorrect to store the saved frame pointer at *sp,
3924 then increment sp (writes beyond the current stack boundary).
3926 So instead use stwm to store at *sp and post-increment the
3927 stack pointer as an atomic operation. Then increment sp to
3928 finish allocating the new frame. */
3929 HOST_WIDE_INT adjust1 = 8192 - 64;
3930 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3932 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3933 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3937 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3938 we need to store the previous stack pointer (frame pointer)
3939 into the frame marker on targets that use the HP unwind
3940 library. This allows the HP unwind library to be used to
3941 unwind GCC frames. However, we are not fully compatible
3942 with the HP library because our frame layout differs from
3943 that specified in the HP runtime specification.
3945 We don't want a frame note on this instruction as the frame
3946 marker moves during dynamic stack allocation.
3948 This instruction also serves as a blockage to prevent
3949 register spills from being scheduled before the stack
3950 pointer is raised. This is necessary as we store
3951 registers using the frame pointer as a base register,
3952 and the frame pointer is set before sp is raised. */
3953 if (TARGET_HPUX_UNWIND_LIBRARY)
3955 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3956 GEN_INT (TARGET_64BIT ? -8 : -4));
3958 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3962 emit_insn (gen_blockage ());
3964 /* no frame pointer needed. */
3967 /* In some cases we can perform the first callee register save
3968 and allocating the stack frame at the same time. If so, just
3969 make a note of it and defer allocating the frame until saving
3970 the callee registers. */
3971 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3972 merge_sp_adjust_with_store = 1;
3973 /* Can not optimize. Adjust the stack frame by actual_fsize
3976 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3981 /* Normal register save.
3983 Do not save the frame pointer in the frame_pointer_needed case. It
3984 was done earlier. */
3985 if (frame_pointer_needed)
3987 offset = local_fsize;
3989 /* Saving the EH return data registers in the frame is the simplest
3990 way to get the frame unwind information emitted. We put them
3991 just before the general registers. */
3992 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3994 unsigned int i, regno;
3998 regno = EH_RETURN_DATA_REGNO (i);
3999 if (regno == INVALID_REGNUM)
4002 store_reg (regno, offset, FRAME_POINTER_REGNUM);
4003 offset += UNITS_PER_WORD;
4007 for (i = 18; i >= 4; i--)
4008 if (regs_ever_live[i] && ! call_used_regs[i])
4010 store_reg (i, offset, FRAME_POINTER_REGNUM);
4011 offset += UNITS_PER_WORD;
4014 /* Account for %r3 which is saved in a special place. */
4017 /* No frame pointer needed. */
4020 offset = local_fsize - actual_fsize;
4022 /* Saving the EH return data registers in the frame is the simplest
4023 way to get the frame unwind information emitted. */
4024 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4026 unsigned int i, regno;
4030 regno = EH_RETURN_DATA_REGNO (i);
4031 if (regno == INVALID_REGNUM)
4034 /* If merge_sp_adjust_with_store is nonzero, then we can
4035 optimize the first save. */
4036 if (merge_sp_adjust_with_store)
4038 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
4039 merge_sp_adjust_with_store = 0;
4042 store_reg (regno, offset, STACK_POINTER_REGNUM);
4043 offset += UNITS_PER_WORD;
4047 for (i = 18; i >= 3; i--)
4048 if (regs_ever_live[i] && ! call_used_regs[i])
4050 /* If merge_sp_adjust_with_store is nonzero, then we can
4051 optimize the first GR save. */
4052 if (merge_sp_adjust_with_store)
4054 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
4055 merge_sp_adjust_with_store = 0;
4058 store_reg (i, offset, STACK_POINTER_REGNUM);
4059 offset += UNITS_PER_WORD;
4063 /* If we wanted to merge the SP adjustment with a GR save, but we never
4064 did any GR saves, then just emit the adjustment here. */
4065 if (merge_sp_adjust_with_store)
4066 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4070 /* The hppa calling conventions say that %r19, the pic offset
4071 register, is saved at sp - 32 (in this function's frame)
4072 when generating PIC code. FIXME: What is the correct thing
4073 to do for functions which make no calls and allocate no
4074 frame? Do we need to allocate a frame, or can we just omit
4075 the save? For now we'll just omit the save.
4077 We don't want a note on this insn as the frame marker can
4078 move if there is a dynamic stack allocation. */
4079 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
4081 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
4083 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
4087 /* Align pointer properly (doubleword boundary). */
4088 offset = (offset + 7) & ~7;
4090 /* Floating point register store. */
4095 /* First get the frame or stack pointer to the start of the FP register
4097 if (frame_pointer_needed)
4099 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4100 base = frame_pointer_rtx;
4104 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4105 base = stack_pointer_rtx;
4108 /* Now actually save the FP registers. */
4109 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4111 if (regs_ever_live[i]
4112 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4114 rtx addr, insn, reg;
4115 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4116 reg = gen_rtx_REG (DFmode, i);
4117 insn = emit_move_insn (addr, reg);
4120 RTX_FRAME_RELATED_P (insn) = 1;
4123 rtx mem = gen_rtx_MEM (DFmode,
4124 plus_constant (base, offset));
4126 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4127 gen_rtx_SET (VOIDmode, mem, reg),
4132 rtx meml = gen_rtx_MEM (SFmode,
4133 plus_constant (base, offset));
4134 rtx memr = gen_rtx_MEM (SFmode,
4135 plus_constant (base, offset + 4));
4136 rtx regl = gen_rtx_REG (SFmode, i);
4137 rtx regr = gen_rtx_REG (SFmode, i + 1);
4138 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4139 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4142 RTX_FRAME_RELATED_P (setl) = 1;
4143 RTX_FRAME_RELATED_P (setr) = 1;
4144 vec = gen_rtvec (2, setl, setr);
4146 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4147 gen_rtx_SEQUENCE (VOIDmode, vec),
4151 offset += GET_MODE_SIZE (DFmode);
4158 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4159 Handle case where DISP > 8k by using the add_high_const patterns. */
4162 load_reg (int reg, HOST_WIDE_INT disp, int base)
4164 rtx dest = gen_rtx_REG (word_mode, reg);
4165 rtx basereg = gen_rtx_REG (Pmode, base);
4168 if (VAL_14_BITS_P (disp))
4169 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4170 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4172 rtx delta = GEN_INT (disp);
4173 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4175 emit_move_insn (tmpreg, delta);
4176 if (TARGET_DISABLE_INDEXING)
4178 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4179 src = gen_rtx_MEM (word_mode, tmpreg);
4182 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4186 rtx delta = GEN_INT (disp);
4187 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4188 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4190 emit_move_insn (tmpreg, high);
4191 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4194 emit_move_insn (dest, src);
4197 /* Update the total code bytes output to the text section. */
4200 update_total_code_bytes (int nbytes)
4202 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4203 && !IN_NAMED_SECTION_P (cfun->decl))
4205 if (INSN_ADDRESSES_SET_P ())
4207 unsigned long old_total = total_code_bytes;
4209 total_code_bytes += nbytes;
4211 /* Be prepared to handle overflows. */
4212 if (old_total > total_code_bytes)
4213 total_code_bytes = -1;
4216 total_code_bytes = -1;
4220 /* This function generates the assembly code for function exit.
4221 Args are as for output_function_prologue ().
4223 The function epilogue should not depend on the current stack
4224 pointer! It should use the frame pointer only. This is mandatory
4225 because of alloca; we also take advantage of it to omit stack
4226 adjustments before returning. */
4229 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4231 rtx insn = get_last_insn ();
4235 /* hppa_expand_epilogue does the dirty work now. We just need
4236 to output the assembler directives which denote the end
4239 To make debuggers happy, emit a nop if the epilogue was completely
4240 eliminated due to a volatile call as the last insn in the
4241 current function. That way the return address (in %r2) will
4242 always point to a valid instruction in the current function. */
4244 /* Get the last real insn. */
4245 if (GET_CODE (insn) == NOTE)
4246 insn = prev_real_insn (insn);
4248 /* If it is a sequence, then look inside. */
4249 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4250 insn = XVECEXP (PATTERN (insn), 0, 0);
4252 /* If insn is a CALL_INSN, then it must be a call to a volatile
4253 function (otherwise there would be epilogue insns). */
4254 if (insn && GET_CODE (insn) == CALL_INSN)
4256 fputs ("\tnop\n", file);
4260 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4262 if (TARGET_SOM && TARGET_GAS)
4264 /* We done with this subspace except possibly for some additional
4265 debug information. Forget that we are in this subspace to ensure
4266 that the next function is output in its own subspace. */
4270 if (INSN_ADDRESSES_SET_P ())
4272 insn = get_last_nonnote_insn ();
4273 last_address += INSN_ADDRESSES (INSN_UID (insn));
4275 last_address += insn_default_length (insn);
4276 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4277 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4280 /* Finally, update the total number of code bytes output so far. */
4281 update_total_code_bytes (last_address);
4285 hppa_expand_epilogue (void)
4288 HOST_WIDE_INT offset;
4289 HOST_WIDE_INT ret_off = 0;
4291 int merge_sp_adjust_with_load = 0;
4293 /* We will use this often. */
4294 tmpreg = gen_rtx_REG (word_mode, 1);
4296 /* Try to restore RP early to avoid load/use interlocks when
4297 RP gets used in the return (bv) instruction. This appears to still
4298 be necessary even when we schedule the prologue and epilogue. */
4299 if (regs_ever_live [2] || current_function_calls_eh_return)
4301 ret_off = TARGET_64BIT ? -16 : -20;
4302 if (frame_pointer_needed)
4304 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4309 /* No frame pointer, and stack is smaller than 8k. */
4310 if (VAL_14_BITS_P (ret_off - actual_fsize))
4312 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4318 /* General register restores. */
4319 if (frame_pointer_needed)
4321 offset = local_fsize;
4323 /* If the current function calls __builtin_eh_return, then we need
4324 to restore the saved EH data registers. */
4325 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4327 unsigned int i, regno;
4331 regno = EH_RETURN_DATA_REGNO (i);
4332 if (regno == INVALID_REGNUM)
4335 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4336 offset += UNITS_PER_WORD;
4340 for (i = 18; i >= 4; i--)
4341 if (regs_ever_live[i] && ! call_used_regs[i])
4343 load_reg (i, offset, FRAME_POINTER_REGNUM);
4344 offset += UNITS_PER_WORD;
4349 offset = local_fsize - actual_fsize;
4351 /* If the current function calls __builtin_eh_return, then we need
4352 to restore the saved EH data registers. */
4353 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4355 unsigned int i, regno;
4359 regno = EH_RETURN_DATA_REGNO (i);
4360 if (regno == INVALID_REGNUM)
4363 /* Only for the first load.
4364 merge_sp_adjust_with_load holds the register load
4365 with which we will merge the sp adjustment. */
4366 if (merge_sp_adjust_with_load == 0
4368 && VAL_14_BITS_P (-actual_fsize))
4369 merge_sp_adjust_with_load = regno;
4371 load_reg (regno, offset, STACK_POINTER_REGNUM);
4372 offset += UNITS_PER_WORD;
4376 for (i = 18; i >= 3; i--)
4378 if (regs_ever_live[i] && ! call_used_regs[i])
4380 /* Only for the first load.
4381 merge_sp_adjust_with_load holds the register load
4382 with which we will merge the sp adjustment. */
4383 if (merge_sp_adjust_with_load == 0
4385 && VAL_14_BITS_P (-actual_fsize))
4386 merge_sp_adjust_with_load = i;
4388 load_reg (i, offset, STACK_POINTER_REGNUM);
4389 offset += UNITS_PER_WORD;
4394 /* Align pointer properly (doubleword boundary). */
4395 offset = (offset + 7) & ~7;
4397 /* FP register restores. */
4400 /* Adjust the register to index off of. */
4401 if (frame_pointer_needed)
4402 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4404 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4406 /* Actually do the restores now. */
4407 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4408 if (regs_ever_live[i]
4409 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4411 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4412 rtx dest = gen_rtx_REG (DFmode, i);
4413 emit_move_insn (dest, src);
4417 /* Emit a blockage insn here to keep these insns from being moved to
4418 an earlier spot in the epilogue, or into the main instruction stream.
4420 This is necessary as we must not cut the stack back before all the
4421 restores are finished. */
4422 emit_insn (gen_blockage ());
4424 /* Reset stack pointer (and possibly frame pointer). The stack
4425 pointer is initially set to fp + 64 to avoid a race condition. */
4426 if (frame_pointer_needed)
4428 rtx delta = GEN_INT (-64);
4430 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4431 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4433 /* If we were deferring a callee register restore, do it now. */
4434 else if (merge_sp_adjust_with_load)
4436 rtx delta = GEN_INT (-actual_fsize);
4437 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4439 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4441 else if (actual_fsize != 0)
4442 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4445 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4446 frame greater than 8k), do so now. */
4448 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4450 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4452 rtx sa = EH_RETURN_STACKADJ_RTX;
4454 emit_insn (gen_blockage ());
4455 emit_insn (TARGET_64BIT
4456 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4457 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4462 hppa_pic_save_rtx (void)
4464 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4468 hppa_profile_hook (int label_no)
4470 /* We use SImode for the address of the function in both 32 and
4471 64-bit code to avoid having to provide DImode versions of the
4472 lcla2 and load_offset_label_address insn patterns. */
4473 rtx reg = gen_reg_rtx (SImode);
4474 rtx label_rtx = gen_label_rtx ();
4475 rtx begin_label_rtx, call_insn;
4476 char begin_label_name[16];
4478 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4480 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4483 emit_move_insn (arg_pointer_rtx,
4484 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4487 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4489 /* The address of the function is loaded into %r25 with a instruction-
4490 relative sequence that avoids the use of relocations. The sequence
4491 is split so that the load_offset_label_address instruction can
4492 occupy the delay slot of the call to _mcount. */
4494 emit_insn (gen_lcla2 (reg, label_rtx));
4496 emit_insn (gen_lcla1 (reg, label_rtx));
4498 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4499 reg, begin_label_rtx, label_rtx));
4501 #ifndef NO_PROFILE_COUNTERS
4503 rtx count_label_rtx, addr, r24;
4504 char count_label_name[16];
4506 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4507 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4509 addr = force_reg (Pmode, count_label_rtx);
4510 r24 = gen_rtx_REG (Pmode, 24);
4511 emit_move_insn (r24, addr);
4514 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4515 gen_rtx_SYMBOL_REF (Pmode,
4517 GEN_INT (TARGET_64BIT ? 24 : 12)));
4519 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4524 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4525 gen_rtx_SYMBOL_REF (Pmode,
4527 GEN_INT (TARGET_64BIT ? 16 : 8)));
4531 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4532 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4534 /* Indicate the _mcount call cannot throw, nor will it execute a
4536 REG_NOTES (call_insn)
4537 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4540 /* Fetch the return address for the frame COUNT steps up from
4541 the current frame, after the prologue. FRAMEADDR is the
4542 frame pointer of the COUNT frame.
4544 We want to ignore any export stub remnants here. To handle this,
4545 we examine the code at the return address, and if it is an export
4546 stub, we return a memory rtx for the stub return address stored
4549 The value returned is used in two different ways:
4551 1. To find a function's caller.
4553 2. To change the return address for a function.
4555 This function handles most instances of case 1; however, it will
4556 fail if there are two levels of stubs to execute on the return
4557 path. The only way I believe that can happen is if the return value
4558 needs a parameter relocation, which never happens for C code.
4560 This function handles most instances of case 2; however, it will
4561 fail if we did not originally have stub code on the return path
4562 but will need stub code on the new return path. This can happen if
4563 the caller & callee are both in the main program, but the new
4564 return location is in a shared library. */
4567 return_addr_rtx (int count, rtx frameaddr)
4577 rp = get_hard_reg_initial_val (Pmode, 2);
4579 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4582 saved_rp = gen_reg_rtx (Pmode);
4583 emit_move_insn (saved_rp, rp);
4585 /* Get pointer to the instruction stream. We have to mask out the
4586 privilege level from the two low order bits of the return address
4587 pointer here so that ins will point to the start of the first
4588 instruction that would have been executed if we returned. */
4589 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4590 label = gen_label_rtx ();
4592 /* Check the instruction stream at the normal return address for the
4595 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4596 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4597 0x00011820 | stub+16: mtsp r1,sr0
4598 0xe0400002 | stub+20: be,n 0(sr0,rp)
4600 If it is an export stub, than our return address is really in
4603 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4604 NULL_RTX, SImode, 1);
4605 emit_jump_insn (gen_bne (label));
4607 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4608 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4609 emit_jump_insn (gen_bne (label));
4611 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4612 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4613 emit_jump_insn (gen_bne (label));
4615 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4616 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4618 /* If there is no export stub then just use the value saved from
4619 the return pointer register. */
4621 emit_jump_insn (gen_bne (label));
4623 /* Here we know that our return address points to an export
4624 stub. We don't want to return the address of the export stub,
4625 but rather the return address of the export stub. That return
4626 address is stored at -24[frameaddr]. */
4628 emit_move_insn (saved_rp,
4630 memory_address (Pmode,
4631 plus_constant (frameaddr,
4638 /* This is only valid once reload has completed because it depends on
4639 knowing exactly how much (if any) frame there is and...
4641 It's only valid if there is no frame marker to de-allocate and...
4643 It's only valid if %r2 hasn't been saved into the caller's frame
4644 (we're not profiling and %r2 isn't live anywhere). */
4646 hppa_can_use_return_insn_p (void)
4648 return (reload_completed
4649 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4650 && ! regs_ever_live[2]
4651 && ! frame_pointer_needed);
4655 emit_bcond_fp (enum rtx_code code, rtx operand0)
4657 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4658 gen_rtx_IF_THEN_ELSE (VOIDmode,
4659 gen_rtx_fmt_ee (code,
4661 gen_rtx_REG (CCFPmode, 0),
4663 gen_rtx_LABEL_REF (VOIDmode, operand0),
4669 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4671 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4672 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4675 /* Adjust the cost of a scheduling dependency. Return the new cost of
4676 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4679 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4681 enum attr_type attr_type;
4683 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4684 true dependencies as they are described with bypasses now. */
4685 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4688 if (! recog_memoized (insn))
4691 attr_type = get_attr_type (insn);
4693 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4695 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4698 if (attr_type == TYPE_FPLOAD)
4700 rtx pat = PATTERN (insn);
4701 rtx dep_pat = PATTERN (dep_insn);
4702 if (GET_CODE (pat) == PARALLEL)
4704 /* This happens for the fldXs,mb patterns. */
4705 pat = XVECEXP (pat, 0, 0);
4707 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4708 /* If this happens, we have to extend this to schedule
4709 optimally. Return 0 for now. */
4712 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4714 if (! recog_memoized (dep_insn))
4716 switch (get_attr_type (dep_insn))
4723 case TYPE_FPSQRTSGL:
4724 case TYPE_FPSQRTDBL:
4725 /* A fpload can't be issued until one cycle before a
4726 preceding arithmetic operation has finished if
4727 the target of the fpload is any of the sources
4728 (or destination) of the arithmetic operation. */
4729 return insn_default_latency (dep_insn) - 1;
4736 else if (attr_type == TYPE_FPALU)
4738 rtx pat = PATTERN (insn);
4739 rtx dep_pat = PATTERN (dep_insn);
4740 if (GET_CODE (pat) == PARALLEL)
4742 /* This happens for the fldXs,mb patterns. */
4743 pat = XVECEXP (pat, 0, 0);
4745 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4746 /* If this happens, we have to extend this to schedule
4747 optimally. Return 0 for now. */
4750 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4752 if (! recog_memoized (dep_insn))
4754 switch (get_attr_type (dep_insn))
4758 case TYPE_FPSQRTSGL:
4759 case TYPE_FPSQRTDBL:
4760 /* An ALU flop can't be issued until two cycles before a
4761 preceding divide or sqrt operation has finished if
4762 the target of the ALU flop is any of the sources
4763 (or destination) of the divide or sqrt operation. */
4764 return insn_default_latency (dep_insn) - 2;
4772 /* For other anti dependencies, the cost is 0. */
4775 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4777 /* Output dependency; DEP_INSN writes a register that INSN writes some
4779 if (attr_type == TYPE_FPLOAD)
4781 rtx pat = PATTERN (insn);
4782 rtx dep_pat = PATTERN (dep_insn);
4783 if (GET_CODE (pat) == PARALLEL)
4785 /* This happens for the fldXs,mb patterns. */
4786 pat = XVECEXP (pat, 0, 0);
4788 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4789 /* If this happens, we have to extend this to schedule
4790 optimally. Return 0 for now. */
4793 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4795 if (! recog_memoized (dep_insn))
4797 switch (get_attr_type (dep_insn))
4804 case TYPE_FPSQRTSGL:
4805 case TYPE_FPSQRTDBL:
4806 /* A fpload can't be issued until one cycle before a
4807 preceding arithmetic operation has finished if
4808 the target of the fpload is the destination of the
4809 arithmetic operation.
4811 Exception: For PA7100LC, PA7200 and PA7300, the cost
4812 is 3 cycles, unless they bundle together. We also
4813 pay the penalty if the second insn is a fpload. */
4814 return insn_default_latency (dep_insn) - 1;
4821 else if (attr_type == TYPE_FPALU)
4823 rtx pat = PATTERN (insn);
4824 rtx dep_pat = PATTERN (dep_insn);
4825 if (GET_CODE (pat) == PARALLEL)
4827 /* This happens for the fldXs,mb patterns. */
4828 pat = XVECEXP (pat, 0, 0);
4830 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4831 /* If this happens, we have to extend this to schedule
4832 optimally. Return 0 for now. */
4835 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4837 if (! recog_memoized (dep_insn))
4839 switch (get_attr_type (dep_insn))
4843 case TYPE_FPSQRTSGL:
4844 case TYPE_FPSQRTDBL:
4845 /* An ALU flop can't be issued until two cycles before a
4846 preceding divide or sqrt operation has finished if
4847 the target of the ALU flop is also the target of
4848 the divide or sqrt operation. */
4849 return insn_default_latency (dep_insn) - 2;
4857 /* For other output dependencies, the cost is 0. */
4864 /* Adjust scheduling priorities. We use this to try and keep addil
4865 and the next use of %r1 close together. */
4867 pa_adjust_priority (rtx insn, int priority)
4869 rtx set = single_set (insn);
4873 src = SET_SRC (set);
4874 dest = SET_DEST (set);
4875 if (GET_CODE (src) == LO_SUM
4876 && symbolic_operand (XEXP (src, 1), VOIDmode)
4877 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4880 else if (GET_CODE (src) == MEM
4881 && GET_CODE (XEXP (src, 0)) == LO_SUM
4882 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4883 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4886 else if (GET_CODE (dest) == MEM
4887 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4888 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4889 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4895 /* The 700 can only issue a single insn at a time.
4896 The 7XXX processors can issue two insns at a time.
4897 The 8000 can issue 4 insns at a time. */
4899 pa_issue_rate (void)
4903 case PROCESSOR_700: return 1;
4904 case PROCESSOR_7100: return 2;
4905 case PROCESSOR_7100LC: return 2;
4906 case PROCESSOR_7200: return 2;
4907 case PROCESSOR_7300: return 2;
4908 case PROCESSOR_8000: return 4;
4917 /* Return any length adjustment needed by INSN which already has its length
4918 computed as LENGTH. Return zero if no adjustment is necessary.
4920 For the PA: function calls, millicode calls, and backwards short
4921 conditional branches with unfilled delay slots need an adjustment by +1
4922 (to account for the NOP which will be inserted into the instruction stream).
4924 Also compute the length of an inline block move here as it is too
4925 complicated to express as a length attribute in pa.md. */
4927 pa_adjust_insn_length (rtx insn, int length)
4929 rtx pat = PATTERN (insn);
4931 /* Jumps inside switch tables which have unfilled delay slots need
4933 if (GET_CODE (insn) == JUMP_INSN
4934 && GET_CODE (pat) == PARALLEL
4935 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4937 /* Millicode insn with an unfilled delay slot. */
4938 else if (GET_CODE (insn) == INSN
4939 && GET_CODE (pat) != SEQUENCE
4940 && GET_CODE (pat) != USE
4941 && GET_CODE (pat) != CLOBBER
4942 && get_attr_type (insn) == TYPE_MILLI)
4944 /* Block move pattern. */
4945 else if (GET_CODE (insn) == INSN
4946 && GET_CODE (pat) == PARALLEL
4947 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4948 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4949 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4950 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4951 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4952 return compute_movmem_length (insn) - 4;
4953 /* Block clear pattern. */
4954 else if (GET_CODE (insn) == INSN
4955 && GET_CODE (pat) == PARALLEL
4956 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4957 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4958 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4959 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4960 return compute_clrmem_length (insn) - 4;
4961 /* Conditional branch with an unfilled delay slot. */
4962 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4964 /* Adjust a short backwards conditional with an unfilled delay slot. */
4965 if (GET_CODE (pat) == SET
4967 && ! forward_branch_p (insn))
4969 else if (GET_CODE (pat) == PARALLEL
4970 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4973 /* Adjust dbra insn with short backwards conditional branch with
4974 unfilled delay slot -- only for case where counter is in a
4975 general register register. */
4976 else if (GET_CODE (pat) == PARALLEL
4977 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4978 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4979 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4981 && ! forward_branch_p (insn))
4989 /* Print operand X (an rtx) in assembler syntax to file FILE.
4990 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4991 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4994 print_operand (FILE *file, rtx x, int code)
4999 /* Output a 'nop' if there's nothing for the delay slot. */
5000 if (dbr_sequence_length () == 0)
5001 fputs ("\n\tnop", file);
5004 /* Output a nullification completer if there's nothing for the */
5005 /* delay slot or nullification is requested. */
5006 if (dbr_sequence_length () == 0 ||
5008 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
5012 /* Print out the second register name of a register pair.
5013 I.e., R (6) => 7. */
5014 fputs (reg_names[REGNO (x) + 1], file);
5017 /* A register or zero. */
5019 || (x == CONST0_RTX (DFmode))
5020 || (x == CONST0_RTX (SFmode)))
5022 fputs ("%r0", file);
5028 /* A register or zero (floating point). */
5030 || (x == CONST0_RTX (DFmode))
5031 || (x == CONST0_RTX (SFmode)))
5033 fputs ("%fr0", file);
5042 xoperands[0] = XEXP (XEXP (x, 0), 0);
5043 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
5044 output_global_address (file, xoperands[1], 0);
5045 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
5049 case 'C': /* Plain (C)ondition */
5051 switch (GET_CODE (x))
5054 fputs ("=", file); break;
5056 fputs ("<>", file); break;
5058 fputs (">", file); break;
5060 fputs (">=", file); break;
5062 fputs (">>=", file); break;
5064 fputs (">>", file); break;
5066 fputs ("<", file); break;
5068 fputs ("<=", file); break;
5070 fputs ("<<=", file); break;
5072 fputs ("<<", file); break;
5077 case 'N': /* Condition, (N)egated */
5078 switch (GET_CODE (x))
5081 fputs ("<>", file); break;
5083 fputs ("=", file); break;
5085 fputs ("<=", file); break;
5087 fputs ("<", file); break;
5089 fputs ("<<", file); break;
5091 fputs ("<<=", file); break;
5093 fputs (">=", file); break;
5095 fputs (">", file); break;
5097 fputs (">>", file); break;
5099 fputs (">>=", file); break;
5104 /* For floating point comparisons. Note that the output
5105 predicates are the complement of the desired mode. The
5106 conditions for GT, GE, LT, LE and LTGT cause an invalid
5107 operation exception if the result is unordered and this
5108 exception is enabled in the floating-point status register. */
5110 switch (GET_CODE (x))
5113 fputs ("!=", file); break;
5115 fputs ("=", file); break;
5117 fputs ("!>", file); break;
5119 fputs ("!>=", file); break;
5121 fputs ("!<", file); break;
5123 fputs ("!<=", file); break;
5125 fputs ("!<>", file); break;
5127 fputs ("!?<=", file); break;
5129 fputs ("!?<", file); break;
5131 fputs ("!?>=", file); break;
5133 fputs ("!?>", file); break;
5135 fputs ("!?=", file); break;
5137 fputs ("!?", file); break;
5139 fputs ("?", file); break;
5144 case 'S': /* Condition, operands are (S)wapped. */
5145 switch (GET_CODE (x))
5148 fputs ("=", file); break;
5150 fputs ("<>", file); break;
5152 fputs ("<", file); break;
5154 fputs ("<=", file); break;
5156 fputs ("<<=", file); break;
5158 fputs ("<<", file); break;
5160 fputs (">", file); break;
5162 fputs (">=", file); break;
5164 fputs (">>=", file); break;
5166 fputs (">>", file); break;
5171 case 'B': /* Condition, (B)oth swapped and negate. */
5172 switch (GET_CODE (x))
5175 fputs ("<>", file); break;
5177 fputs ("=", file); break;
5179 fputs (">=", file); break;
5181 fputs (">", file); break;
5183 fputs (">>", file); break;
5185 fputs (">>=", file); break;
5187 fputs ("<=", file); break;
5189 fputs ("<", file); break;
5191 fputs ("<<", file); break;
5193 fputs ("<<=", file); break;
5199 if (GET_CODE (x) == CONST_INT)
5201 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5206 if (GET_CODE (x) == CONST_INT)
5208 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5213 if (GET_CODE (x) == CONST_INT)
5215 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5220 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
5222 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5227 if (GET_CODE (x) == CONST_INT)
5229 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5234 if (GET_CODE (x) == CONST_INT)
5236 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5241 if (GET_CODE (x) == CONST_INT)
5246 switch (GET_CODE (XEXP (x, 0)))
5250 if (ASSEMBLER_DIALECT == 0)
5251 fputs ("s,mb", file);
5253 fputs (",mb", file);
5257 if (ASSEMBLER_DIALECT == 0)
5258 fputs ("s,ma", file);
5260 fputs (",ma", file);
5263 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5264 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5266 if (ASSEMBLER_DIALECT == 0)
5269 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5270 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5272 if (ASSEMBLER_DIALECT == 0)
5273 fputs ("x,s", file);
5277 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5281 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5287 output_global_address (file, x, 0);
5290 output_global_address (file, x, 1);
5292 case 0: /* Don't do anything special */
5297 compute_zdepwi_operands (INTVAL (x), op);
5298 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5304 compute_zdepdi_operands (INTVAL (x), op);
5305 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5309 /* We can get here from a .vtable_inherit due to our
5310 CONSTANT_ADDRESS_P rejecting perfectly good constant
5316 if (GET_CODE (x) == REG)
5318 fputs (reg_names [REGNO (x)], file);
5319 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5325 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5326 && (REGNO (x) & 1) == 0)
5329 else if (GET_CODE (x) == MEM)
5331 int size = GET_MODE_SIZE (GET_MODE (x));
5332 rtx base = NULL_RTX;
5333 switch (GET_CODE (XEXP (x, 0)))
5337 base = XEXP (XEXP (x, 0), 0);
5338 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5342 base = XEXP (XEXP (x, 0), 0);
5343 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5346 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5347 fprintf (file, "%s(%s)",
5348 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5349 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5350 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5351 fprintf (file, "%s(%s)",
5352 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5353 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5354 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5355 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5357 /* Because the REG_POINTER flag can get lost during reload,
5358 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5359 index and base registers in the combined move patterns. */
5360 rtx base = XEXP (XEXP (x, 0), 1);
5361 rtx index = XEXP (XEXP (x, 0), 0);
5363 fprintf (file, "%s(%s)",
5364 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5367 output_address (XEXP (x, 0));
5370 output_address (XEXP (x, 0));
5375 output_addr_const (file, x);
5378 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5381 output_global_address (FILE *file, rtx x, int round_constant)
5384 /* Imagine (high (const (plus ...))). */
5385 if (GET_CODE (x) == HIGH)
5388 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5389 assemble_name (file, XSTR (x, 0));
5390 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5392 assemble_name (file, XSTR (x, 0));
5393 fputs ("-$global$", file);
5395 else if (GET_CODE (x) == CONST)
5397 const char *sep = "";
5398 int offset = 0; /* assembler wants -$global$ at end */
5399 rtx base = NULL_RTX;
5401 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
5403 base = XEXP (XEXP (x, 0), 0);
5404 output_addr_const (file, base);
5406 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
5407 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5410 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
5412 base = XEXP (XEXP (x, 0), 1);
5413 output_addr_const (file, base);
5415 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
5416 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5419 /* How bogus. The compiler is apparently responsible for
5420 rounding the constant if it uses an LR field selector.
5422 The linker and/or assembler seem a better place since
5423 they have to do this kind of thing already.
5425 If we fail to do this, HP's optimizing linker may eliminate
5426 an addil, but not update the ldw/stw/ldo instruction that
5427 uses the result of the addil. */
5429 offset = ((offset + 0x1000) & ~0x1fff);
5431 if (GET_CODE (XEXP (x, 0)) == PLUS)
5441 else if (GET_CODE (XEXP (x, 0)) == MINUS
5442 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5446 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5447 fputs ("-$global$", file);
5449 fprintf (file, "%s%d", sep, offset);
5452 output_addr_const (file, x);
5455 /* Output boilerplate text to appear at the beginning of the file.
5456 There are several possible versions. */
5457 #define aputs(x) fputs(x, asm_out_file)
5459 pa_file_start_level (void)
5462 aputs ("\t.LEVEL 2.0w\n");
5463 else if (TARGET_PA_20)
5464 aputs ("\t.LEVEL 2.0\n");
5465 else if (TARGET_PA_11)
5466 aputs ("\t.LEVEL 1.1\n");
5468 aputs ("\t.LEVEL 1.0\n");
5472 pa_file_start_space (int sortspace)
5474 aputs ("\t.SPACE $PRIVATE$");
5477 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5478 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5479 "\n\t.SPACE $TEXT$");
5482 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5483 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5487 pa_file_start_file (int want_version)
5489 if (write_symbols != NO_DEBUG)
5491 output_file_directive (asm_out_file, main_input_filename);
5493 aputs ("\t.version\t\"01.01\"\n");
5498 pa_file_start_mcount (const char *aswhat)
5501 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5505 pa_elf_file_start (void)
5507 pa_file_start_level ();
5508 pa_file_start_mcount ("ENTRY");
5509 pa_file_start_file (0);
5513 pa_som_file_start (void)
5515 pa_file_start_level ();
5516 pa_file_start_space (0);
5517 aputs ("\t.IMPORT $global$,DATA\n"
5518 "\t.IMPORT $$dyncall,MILLICODE\n");
5519 pa_file_start_mcount ("CODE");
5520 pa_file_start_file (0);
5524 pa_linux_file_start (void)
5526 pa_file_start_file (1);
5527 pa_file_start_level ();
5528 pa_file_start_mcount ("CODE");
5532 pa_hpux64_gas_file_start (void)
5534 pa_file_start_level ();
5535 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5537 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5539 pa_file_start_file (1);
5543 pa_hpux64_hpas_file_start (void)
5545 pa_file_start_level ();
5546 pa_file_start_space (1);
5547 pa_file_start_mcount ("CODE");
5548 pa_file_start_file (0);
5552 static struct deferred_plabel *
5553 get_plabel (const char *fname)
5557 /* See if we have already put this function on the list of deferred
5558 plabels. This list is generally small, so a liner search is not
5559 too ugly. If it proves too slow replace it with something faster. */
5560 for (i = 0; i < n_deferred_plabels; i++)
5561 if (strcmp (fname, deferred_plabels[i].name) == 0)
5564 /* If the deferred plabel list is empty, or this entry was not found
5565 on the list, create a new entry on the list. */
5566 if (deferred_plabels == NULL || i == n_deferred_plabels)
5568 const char *real_name;
5570 if (deferred_plabels == 0)
5571 deferred_plabels = (struct deferred_plabel *)
5572 ggc_alloc (sizeof (struct deferred_plabel));
5574 deferred_plabels = (struct deferred_plabel *)
5575 ggc_realloc (deferred_plabels,
5576 ((n_deferred_plabels + 1)
5577 * sizeof (struct deferred_plabel)));
5579 i = n_deferred_plabels++;
5580 deferred_plabels[i].internal_label = gen_label_rtx ();
5581 deferred_plabels[i].name = ggc_strdup (fname);
5583 /* Gross. We have just implicitly taken the address of this function,
5585 real_name = (*targetm.strip_name_encoding) (fname);
5586 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5589 return &deferred_plabels[i];
5593 output_deferred_plabels (void)
5596 /* If we have deferred plabels, then we need to switch into the data
5597 section and align it to a 4 byte boundary before we output the
5598 deferred plabels. */
5599 if (n_deferred_plabels)
5602 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5605 /* Now output the deferred plabels. */
5606 for (i = 0; i < n_deferred_plabels; i++)
5608 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5609 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5610 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
5611 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5615 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5616 /* Initialize optabs to point to HPUX long double emulation routines. */
5618 pa_hpux_init_libfuncs (void)
5620 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5621 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5622 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5623 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5624 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5625 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5626 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5627 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5628 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5630 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5631 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5632 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5633 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5634 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5635 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5636 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5638 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5639 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5640 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5641 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5643 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5644 ? "__U_Qfcnvfxt_quad_to_sgl"
5645 : "_U_Qfcnvfxt_quad_to_sgl");
5646 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5647 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5648 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5650 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5651 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5655 /* HP's millicode routines mean something special to the assembler.
5656 Keep track of which ones we have used. */
5658 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5659 static void import_milli (enum millicodes);
5660 static char imported[(int) end1000];
5661 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5662 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5663 #define MILLI_START 10
5666 import_milli (enum millicodes code)
5668 char str[sizeof (import_string)];
5670 if (!imported[(int) code])
5672 imported[(int) code] = 1;
5673 strcpy (str, import_string);
5674 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5675 output_asm_insn (str, 0);
5679 /* The register constraints have put the operands and return value in
5680 the proper registers. */
5683 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5685 import_milli (mulI);
5686 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5689 /* Emit the rtl for doing a division by a constant. */
5691 /* Do magic division millicodes exist for this value? */
5692 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5695 /* We'll use an array to keep track of the magic millicodes and
5696 whether or not we've used them already. [n][0] is signed, [n][1] is
5699 static int div_milli[16][2];
5702 div_operand (rtx op, enum machine_mode mode)
5704 return (mode == SImode
5705 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5706 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5707 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5711 emit_hpdiv_const (rtx *operands, int unsignedp)
5713 if (GET_CODE (operands[2]) == CONST_INT
5714 && INTVAL (operands[2]) > 0
5715 && INTVAL (operands[2]) < 16
5716 && magic_milli[INTVAL (operands[2])])
5718 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5720 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5724 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5725 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5727 gen_rtx_REG (SImode, 26),
5729 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5730 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5731 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5732 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5733 gen_rtx_CLOBBER (VOIDmode, ret))));
5734 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5741 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5745 /* If the divisor is a constant, try to use one of the special
5747 if (GET_CODE (operands[0]) == CONST_INT)
5749 static char buf[100];
5750 divisor = INTVAL (operands[0]);
5751 if (!div_milli[divisor][unsignedp])
5753 div_milli[divisor][unsignedp] = 1;
5755 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5757 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5761 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5762 INTVAL (operands[0]));
5763 return output_millicode_call (insn,
5764 gen_rtx_SYMBOL_REF (SImode, buf));
5768 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5769 INTVAL (operands[0]));
5770 return output_millicode_call (insn,
5771 gen_rtx_SYMBOL_REF (SImode, buf));
5774 /* Divisor isn't a special constant. */
5779 import_milli (divU);
5780 return output_millicode_call (insn,
5781 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5785 import_milli (divI);
5786 return output_millicode_call (insn,
5787 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5792 /* Output a $$rem millicode to do mod. */
5795 output_mod_insn (int unsignedp, rtx insn)
5799 import_milli (remU);
5800 return output_millicode_call (insn,
5801 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5805 import_milli (remI);
5806 return output_millicode_call (insn,
5807 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5812 output_arg_descriptor (rtx call_insn)
5814 const char *arg_regs[4];
5815 enum machine_mode arg_mode;
5817 int i, output_flag = 0;
5820 /* We neither need nor want argument location descriptors for the
5821 64bit runtime environment or the ELF32 environment. */
5822 if (TARGET_64BIT || TARGET_ELF32)
5825 for (i = 0; i < 4; i++)
5828 /* Specify explicitly that no argument relocations should take place
5829 if using the portable runtime calling conventions. */
5830 if (TARGET_PORTABLE_RUNTIME)
5832 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5837 if (GET_CODE (call_insn) != CALL_INSN)
5839 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5841 rtx use = XEXP (link, 0);
5843 if (! (GET_CODE (use) == USE
5844 && GET_CODE (XEXP (use, 0)) == REG
5845 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5848 arg_mode = GET_MODE (XEXP (use, 0));
5849 regno = REGNO (XEXP (use, 0));
5850 if (regno >= 23 && regno <= 26)
5852 arg_regs[26 - regno] = "GR";
5853 if (arg_mode == DImode)
5854 arg_regs[25 - regno] = "GR";
5856 else if (regno >= 32 && regno <= 39)
5858 if (arg_mode == SFmode)
5859 arg_regs[(regno - 32) / 2] = "FR";
5862 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5863 arg_regs[(regno - 34) / 2] = "FR";
5864 arg_regs[(regno - 34) / 2 + 1] = "FU";
5866 arg_regs[(regno - 34) / 2] = "FU";
5867 arg_regs[(regno - 34) / 2 + 1] = "FR";
5872 fputs ("\t.CALL ", asm_out_file);
5873 for (i = 0; i < 4; i++)
5878 fputc (',', asm_out_file);
5879 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5882 fputc ('\n', asm_out_file);
5885 /* Return the class of any secondary reload register that is needed to
5886 move IN into a register in class CLASS using mode MODE.
5888 Profiling has showed this routine and its descendants account for
5889 a significant amount of compile time (~7%). So it has been
5890 optimized to reduce redundant computations and eliminate useless
5893 It might be worthwhile to try and make this a leaf function too. */
5896 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5898 int regno, is_symbolic;
5900 /* Trying to load a constant into a FP register during PIC code
5901 generation will require %r1 as a scratch register. */
5903 && GET_MODE_CLASS (mode) == MODE_INT
5904 && FP_REG_CLASS_P (class)
5905 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5908 /* Profiling showed the PA port spends about 1.3% of its compilation
5909 time in true_regnum from calls inside secondary_reload_class. */
5911 if (GET_CODE (in) == REG)
5914 if (regno >= FIRST_PSEUDO_REGISTER)
5915 regno = true_regnum (in);
5917 else if (GET_CODE (in) == SUBREG)
5918 regno = true_regnum (in);
5922 /* If we have something like (mem (mem (...)), we can safely assume the
5923 inner MEM will end up in a general register after reloading, so there's
5924 no need for a secondary reload. */
5925 if (GET_CODE (in) == MEM
5926 && GET_CODE (XEXP (in, 0)) == MEM)
5929 /* Handle out of range displacement for integer mode loads/stores of
5931 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5932 && GET_MODE_CLASS (mode) == MODE_INT
5933 && FP_REG_CLASS_P (class))
5934 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5935 return GENERAL_REGS;
5937 /* A SAR<->FP register copy requires a secondary register (GPR) as
5938 well as secondary memory. */
5939 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5940 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5941 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5942 return GENERAL_REGS;
5944 if (GET_CODE (in) == HIGH)
5947 /* Profiling has showed GCC spends about 2.6% of its compilation
5948 time in symbolic_operand from calls inside secondary_reload_class.
5950 We use an inline copy and only compute its return value once to avoid
5952 switch (GET_CODE (in))
5962 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5963 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5964 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5974 && read_only_operand (in, VOIDmode))
5977 if (class != R1_REGS && is_symbolic)
5983 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5984 by invisible reference. As a GCC extension, we also pass anything
5985 with a zero or variable size by reference.
5987 The 64-bit runtime does not describe passing any types by invisible
5988 reference. The internals of GCC can't currently handle passing
5989 empty structures, and zero or variable length arrays when they are
5990 not passed entirely on the stack or by reference. Thus, as a GCC
5991 extension, we pass these types by reference. The HP compiler doesn't
5992 support these types, so hopefully there shouldn't be any compatibility
5993 issues. This may have to be revisited when HP releases a C99 compiler
5994 or updates the ABI. */
5997 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5998 enum machine_mode mode, tree type,
5999 bool named ATTRIBUTE_UNUSED)
6004 size = int_size_in_bytes (type);
6006 size = GET_MODE_SIZE (mode);
6011 return size <= 0 || size > 8;
6015 function_arg_padding (enum machine_mode mode, tree type)
6018 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
6020 /* Return none if justification is not required. */
6022 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
6023 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
6026 /* The directions set here are ignored when a BLKmode argument larger
6027 than a word is placed in a register. Different code is used for
6028 the stack and registers. This makes it difficult to have a
6029 consistent data representation for both the stack and registers.
6030 For both runtimes, the justification and padding for arguments on
6031 the stack and in registers should be identical. */
6033 /* The 64-bit runtime specifies left justification for aggregates. */
6036 /* The 32-bit runtime architecture specifies right justification.
6037 When the argument is passed on the stack, the argument is padded
6038 with garbage on the left. The HP compiler pads with zeros. */
6042 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
6049 /* Do what is necessary for `va_start'. We look at the current function
6050 to determine if stdargs or varargs is used and fill in an initial
6051 va_list. A pointer to this constructor is returned. */
6054 hppa_builtin_saveregs (void)
6057 tree fntype = TREE_TYPE (current_function_decl);
6058 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
6059 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
6060 != void_type_node)))
6061 ? UNITS_PER_WORD : 0);
6064 offset = plus_constant (current_function_arg_offset_rtx, argadj);
6066 offset = current_function_arg_offset_rtx;
6072 /* Adjust for varargs/stdarg differences. */
6074 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
6076 offset = current_function_arg_offset_rtx;
6078 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6079 from the incoming arg pointer and growing to larger addresses. */
6080 for (i = 26, off = -64; i >= 19; i--, off += 8)
6081 emit_move_insn (gen_rtx_MEM (word_mode,
6082 plus_constant (arg_pointer_rtx, off)),
6083 gen_rtx_REG (word_mode, i));
6085 /* The incoming args pointer points just beyond the flushback area;
6086 normally this is not a serious concern. However, when we are doing
6087 varargs/stdargs we want to make the arg pointer point to the start
6088 of the incoming argument area. */
6089 emit_move_insn (virtual_incoming_args_rtx,
6090 plus_constant (arg_pointer_rtx, -64));
6092 /* Now return a pointer to the first anonymous argument. */
6093 return copy_to_reg (expand_binop (Pmode, add_optab,
6094 virtual_incoming_args_rtx,
6095 offset, 0, 0, OPTAB_LIB_WIDEN));
6098 /* Store general registers on the stack. */
6099 dest = gen_rtx_MEM (BLKmode,
6100 plus_constant (current_function_internal_arg_pointer,
6102 set_mem_alias_set (dest, get_varargs_alias_set ());
6103 set_mem_align (dest, BITS_PER_WORD);
6104 move_block_from_reg (23, dest, 4);
6106 /* move_block_from_reg will emit code to store the argument registers
6107 individually as scalar stores.
6109 However, other insns may later load from the same addresses for
6110 a structure load (passing a struct to a varargs routine).
6112 The alias code assumes that such aliasing can never happen, so we
6113 have to keep memory referencing insns from moving up beyond the
6114 last argument register store. So we emit a blockage insn here. */
6115 emit_insn (gen_blockage ());
6117 return copy_to_reg (expand_binop (Pmode, add_optab,
6118 current_function_internal_arg_pointer,
6119 offset, 0, 0, OPTAB_LIB_WIDEN));
6123 hppa_va_start (tree valist, rtx nextarg)
6125 nextarg = expand_builtin_saveregs ();
6126 std_expand_builtin_va_start (valist, nextarg);
6130 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
6134 /* Args grow upward. We can use the generic routines. */
6135 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6137 else /* !TARGET_64BIT */
6139 tree ptr = build_pointer_type (type);
6142 unsigned int size, ofs;
6145 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6149 ptr = build_pointer_type (type);
6151 size = int_size_in_bytes (type);
6152 valist_type = TREE_TYPE (valist);
6154 /* Args grow down. Not handled by generic routines. */
6156 u = fold_convert (valist_type, size_in_bytes (type));
6157 t = build (MINUS_EXPR, valist_type, valist, u);
6159 /* Copied from va-pa.h, but we probably don't need to align to
6160 word size, since we generate and preserve that invariant. */
6161 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
6162 t = build (BIT_AND_EXPR, valist_type, t, u);
6164 t = build (MODIFY_EXPR, valist_type, valist, t);
6166 ofs = (8 - size) % 4;
6169 u = fold_convert (valist_type, size_int (ofs));
6170 t = build (PLUS_EXPR, valist_type, t, u);
6173 t = fold_convert (ptr, t);
6174 t = build_fold_indirect_ref (t);
6177 t = build_fold_indirect_ref (t);
6183 /* This routine handles all the normal conditional branch sequences we
6184 might need to generate. It handles compare immediate vs compare
6185 register, nullification of delay slots, varying length branches,
6186 negated branches, and all combinations of the above. It returns the
6187 output appropriate to emit the branch corresponding to all given
6191 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
6193 static char buf[100];
6197 /* A conditional branch to the following instruction (e.g. the delay slot)
6198 is asking for a disaster. This can happen when not optimizing and
6199 when jump optimization fails.
6201 While it is usually safe to emit nothing, this can fail if the
6202 preceding instruction is a nullified branch with an empty delay
6203 slot and the same branch target as this branch. We could check
6204 for this but jump optimization should eliminate nop jumps. It
6205 is always safe to emit a nop. */
6206 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6209 /* The doubleword form of the cmpib instruction doesn't have the LEU
6210 and GTU conditions while the cmpb instruction does. Since we accept
6211 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6212 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6213 operands[2] = gen_rtx_REG (DImode, 0);
6215 /* If this is a long branch with its delay slot unfilled, set `nullify'
6216 as it can nullify the delay slot and save a nop. */
6217 if (length == 8 && dbr_sequence_length () == 0)
6220 /* If this is a short forward conditional branch which did not get
6221 its delay slot filled, the delay slot can still be nullified. */
6222 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6223 nullify = forward_branch_p (insn);
6225 /* A forward branch over a single nullified insn can be done with a
6226 comclr instruction. This avoids a single cycle penalty due to
6227 mis-predicted branch if we fall through (branch not taken). */
6229 && next_real_insn (insn) != 0
6230 && get_attr_length (next_real_insn (insn)) == 4
6231 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6237 /* All short conditional branches except backwards with an unfilled
6241 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6243 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6244 if (GET_MODE (operands[1]) == DImode)
6247 strcat (buf, "%B3");
6249 strcat (buf, "%S3");
6251 strcat (buf, " %2,%r1,%%r0");
6253 strcat (buf, ",n %2,%r1,%0");
6255 strcat (buf, " %2,%r1,%0");
6258 /* All long conditionals. Note a short backward branch with an
6259 unfilled delay slot is treated just like a long backward branch
6260 with an unfilled delay slot. */
6262 /* Handle weird backwards branch with a filled delay slot
6263 with is nullified. */
6264 if (dbr_sequence_length () != 0
6265 && ! forward_branch_p (insn)
6268 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6269 if (GET_MODE (operands[1]) == DImode)
6272 strcat (buf, "%S3");
6274 strcat (buf, "%B3");
6275 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6277 /* Handle short backwards branch with an unfilled delay slot.
6278 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6279 taken and untaken branches. */
6280 else if (dbr_sequence_length () == 0
6281 && ! forward_branch_p (insn)
6282 && INSN_ADDRESSES_SET_P ()
6283 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6284 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6286 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6287 if (GET_MODE (operands[1]) == DImode)
6290 strcat (buf, "%B3 %2,%r1,%0%#");
6292 strcat (buf, "%S3 %2,%r1,%0%#");
6296 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6297 if (GET_MODE (operands[1]) == DImode)
6300 strcat (buf, "%S3");
6302 strcat (buf, "%B3");
6304 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6306 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6312 xoperands[0] = operands[0];
6313 xoperands[1] = operands[1];
6314 xoperands[2] = operands[2];
6315 xoperands[3] = operands[3];
6317 /* The reversed conditional branch must branch over one additional
6318 instruction if the delay slot is filled. If the delay slot
6319 is empty, the instruction after the reversed condition branch
6320 must be nullified. */
6321 nullify = dbr_sequence_length () == 0;
6322 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6324 /* Create a reversed conditional branch which branches around
6325 the following insns. */
6326 if (GET_MODE (operands[1]) != DImode)
6332 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6335 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6341 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6344 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6353 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6356 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6362 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6365 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6369 output_asm_insn (buf, xoperands);
6370 return output_lbranch (operands[0], insn);
6378 /* This routine handles long unconditional branches that exceed the
6379 maximum range of a simple branch instruction. */
6382 output_lbranch (rtx dest, rtx insn)
6386 xoperands[0] = dest;
6388 /* First, free up the delay slot. */
6389 if (dbr_sequence_length () != 0)
6391 /* We can't handle a jump in the delay slot. */
6392 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
6395 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6396 optimize, 0, 0, NULL);
6398 /* Now delete the delay insn. */
6399 PUT_CODE (NEXT_INSN (insn), NOTE);
6400 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6401 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6404 /* Output an insn to save %r1. The runtime documentation doesn't
6405 specify whether the "Clean Up" slot in the callers frame can
6406 be clobbered by the callee. It isn't copied by HP's builtin
6407 alloca, so this suggests that it can be clobbered if necessary.
6408 The "Static Link" location is copied by HP builtin alloca, so
6409 we avoid using it. Using the cleanup slot might be a problem
6410 if we have to interoperate with languages that pass cleanup
6411 information. However, it should be possible to handle these
6412 situations with GCC's asm feature.
6414 The "Current RP" slot is reserved for the called procedure, so
6415 we try to use it when we don't have a frame of our own. It's
6416 rather unlikely that we won't have a frame when we need to emit
6419 Really the way to go long term is a register scavenger; goto
6420 the target of the jump and find a register which we can use
6421 as a scratch to hold the value in %r1. Then, we wouldn't have
6422 to free up the delay slot or clobber a slot that may be needed
6423 for other purposes. */
6426 if (actual_fsize == 0 && !regs_ever_live[2])
6427 /* Use the return pointer slot in the frame marker. */
6428 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6430 /* Use the slot at -40 in the frame marker since HP builtin
6431 alloca doesn't copy it. */
6432 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6436 if (actual_fsize == 0 && !regs_ever_live[2])
6437 /* Use the return pointer slot in the frame marker. */
6438 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6440 /* Use the "Clean Up" slot in the frame marker. In GCC,
6441 the only other use of this location is for copying a
6442 floating point double argument from a floating-point
6443 register to two general registers. The copy is done
6444 as an "atomic" operation when outputting a call, so it
6445 won't interfere with our using the location here. */
6446 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6449 if (TARGET_PORTABLE_RUNTIME)
6451 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6452 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6453 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6457 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6458 if (TARGET_SOM || !TARGET_GAS)
6460 xoperands[1] = gen_label_rtx ();
6461 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6462 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6463 CODE_LABEL_NUMBER (xoperands[1]));
6464 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6468 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6469 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6471 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6474 /* Now output a very long branch to the original target. */
6475 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6477 /* Now restore the value of %r1 in the delay slot. */
6480 if (actual_fsize == 0 && !regs_ever_live[2])
6481 return "ldd -16(%%r30),%%r1";
6483 return "ldd -40(%%r30),%%r1";
6487 if (actual_fsize == 0 && !regs_ever_live[2])
6488 return "ldw -20(%%r30),%%r1";
6490 return "ldw -12(%%r30),%%r1";
6494 /* This routine handles all the branch-on-bit conditional branch sequences we
6495 might need to generate. It handles nullification of delay slots,
6496 varying length branches, negated branches and all combinations of the
6497 above. it returns the appropriate output template to emit the branch. */
6500 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6501 int negated, rtx insn, int which)
6503 static char buf[100];
6506 /* A conditional branch to the following instruction (e.g. the delay slot) is
6507 asking for a disaster. I do not think this can happen as this pattern
6508 is only used when optimizing; jump optimization should eliminate the
6509 jump. But be prepared just in case. */
6511 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6514 /* If this is a long branch with its delay slot unfilled, set `nullify'
6515 as it can nullify the delay slot and save a nop. */
6516 if (length == 8 && dbr_sequence_length () == 0)
6519 /* If this is a short forward conditional branch which did not get
6520 its delay slot filled, the delay slot can still be nullified. */
6521 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6522 nullify = forward_branch_p (insn);
6524 /* A forward branch over a single nullified insn can be done with a
6525 extrs instruction. This avoids a single cycle penalty due to
6526 mis-predicted branch if we fall through (branch not taken). */
6529 && next_real_insn (insn) != 0
6530 && get_attr_length (next_real_insn (insn)) == 4
6531 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6538 /* All short conditional branches except backwards with an unfilled
6542 strcpy (buf, "{extrs,|extrw,s,}");
6544 strcpy (buf, "bb,");
6545 if (useskip && GET_MODE (operands[0]) == DImode)
6546 strcpy (buf, "extrd,s,*");
6547 else if (GET_MODE (operands[0]) == DImode)
6548 strcpy (buf, "bb,*");
6549 if ((which == 0 && negated)
6550 || (which == 1 && ! negated))
6555 strcat (buf, " %0,%1,1,%%r0");
6556 else if (nullify && negated)
6557 strcat (buf, ",n %0,%1,%3");
6558 else if (nullify && ! negated)
6559 strcat (buf, ",n %0,%1,%2");
6560 else if (! nullify && negated)
6561 strcat (buf, "%0,%1,%3");
6562 else if (! nullify && ! negated)
6563 strcat (buf, " %0,%1,%2");
6566 /* All long conditionals. Note a short backward branch with an
6567 unfilled delay slot is treated just like a long backward branch
6568 with an unfilled delay slot. */
6570 /* Handle weird backwards branch with a filled delay slot
6571 with is nullified. */
6572 if (dbr_sequence_length () != 0
6573 && ! forward_branch_p (insn)
6576 strcpy (buf, "bb,");
6577 if (GET_MODE (operands[0]) == DImode)
6579 if ((which == 0 && negated)
6580 || (which == 1 && ! negated))
6585 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6587 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6589 /* Handle short backwards branch with an unfilled delay slot.
6590 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6591 taken and untaken branches. */
6592 else if (dbr_sequence_length () == 0
6593 && ! forward_branch_p (insn)
6594 && INSN_ADDRESSES_SET_P ()
6595 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6596 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6598 strcpy (buf, "bb,");
6599 if (GET_MODE (operands[0]) == DImode)
6601 if ((which == 0 && negated)
6602 || (which == 1 && ! negated))
6607 strcat (buf, " %0,%1,%3%#");
6609 strcat (buf, " %0,%1,%2%#");
6613 strcpy (buf, "{extrs,|extrw,s,}");
6614 if (GET_MODE (operands[0]) == DImode)
6615 strcpy (buf, "extrd,s,*");
6616 if ((which == 0 && negated)
6617 || (which == 1 && ! negated))
6621 if (nullify && negated)
6622 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6623 else if (nullify && ! negated)
6624 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6626 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6628 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6638 /* This routine handles all the branch-on-variable-bit conditional branch
6639 sequences we might need to generate. It handles nullification of delay
6640 slots, varying length branches, negated branches and all combinations
6641 of the above. it returns the appropriate output template to emit the
6645 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6646 int negated, rtx insn, int which)
6648 static char buf[100];
6651 /* A conditional branch to the following instruction (e.g. the delay slot) is
6652 asking for a disaster. I do not think this can happen as this pattern
6653 is only used when optimizing; jump optimization should eliminate the
6654 jump. But be prepared just in case. */
6656 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6659 /* If this is a long branch with its delay slot unfilled, set `nullify'
6660 as it can nullify the delay slot and save a nop. */
6661 if (length == 8 && dbr_sequence_length () == 0)
6664 /* If this is a short forward conditional branch which did not get
6665 its delay slot filled, the delay slot can still be nullified. */
6666 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6667 nullify = forward_branch_p (insn);
6669 /* A forward branch over a single nullified insn can be done with a
6670 extrs instruction. This avoids a single cycle penalty due to
6671 mis-predicted branch if we fall through (branch not taken). */
6674 && next_real_insn (insn) != 0
6675 && get_attr_length (next_real_insn (insn)) == 4
6676 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6683 /* All short conditional branches except backwards with an unfilled
6687 strcpy (buf, "{vextrs,|extrw,s,}");
6689 strcpy (buf, "{bvb,|bb,}");
6690 if (useskip && GET_MODE (operands[0]) == DImode)
6691 strcpy (buf, "extrd,s,*");
6692 else if (GET_MODE (operands[0]) == DImode)
6693 strcpy (buf, "bb,*");
6694 if ((which == 0 && negated)
6695 || (which == 1 && ! negated))
6700 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6701 else if (nullify && negated)
6702 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6703 else if (nullify && ! negated)
6704 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6705 else if (! nullify && negated)
6706 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6707 else if (! nullify && ! negated)
6708 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6711 /* All long conditionals. Note a short backward branch with an
6712 unfilled delay slot is treated just like a long backward branch
6713 with an unfilled delay slot. */
6715 /* Handle weird backwards branch with a filled delay slot
6716 with is nullified. */
6717 if (dbr_sequence_length () != 0
6718 && ! forward_branch_p (insn)
6721 strcpy (buf, "{bvb,|bb,}");
6722 if (GET_MODE (operands[0]) == DImode)
6724 if ((which == 0 && negated)
6725 || (which == 1 && ! negated))
6730 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6732 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6734 /* Handle short backwards branch with an unfilled delay slot.
6735 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6736 taken and untaken branches. */
6737 else if (dbr_sequence_length () == 0
6738 && ! forward_branch_p (insn)
6739 && INSN_ADDRESSES_SET_P ()
6740 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6741 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6743 strcpy (buf, "{bvb,|bb,}");
6744 if (GET_MODE (operands[0]) == DImode)
6746 if ((which == 0 && negated)
6747 || (which == 1 && ! negated))
6752 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6754 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6758 strcpy (buf, "{vextrs,|extrw,s,}");
6759 if (GET_MODE (operands[0]) == DImode)
6760 strcpy (buf, "extrd,s,*");
6761 if ((which == 0 && negated)
6762 || (which == 1 && ! negated))
6766 if (nullify && negated)
6767 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6768 else if (nullify && ! negated)
6769 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6771 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6773 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6783 /* Return the output template for emitting a dbra type insn.
6785 Note it may perform some output operations on its own before
6786 returning the final output string. */
6788 output_dbra (rtx *operands, rtx insn, int which_alternative)
6791 /* A conditional branch to the following instruction (e.g. the delay slot) is
6792 asking for a disaster. Be prepared! */
6794 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6796 if (which_alternative == 0)
6797 return "ldo %1(%0),%0";
6798 else if (which_alternative == 1)
6800 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6801 output_asm_insn ("ldw -16(%%r30),%4", operands);
6802 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6803 return "{fldws|fldw} -16(%%r30),%0";
6807 output_asm_insn ("ldw %0,%4", operands);
6808 return "ldo %1(%4),%4\n\tstw %4,%0";
6812 if (which_alternative == 0)
6814 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6815 int length = get_attr_length (insn);
6817 /* If this is a long branch with its delay slot unfilled, set `nullify'
6818 as it can nullify the delay slot and save a nop. */
6819 if (length == 8 && dbr_sequence_length () == 0)
6822 /* If this is a short forward conditional branch which did not get
6823 its delay slot filled, the delay slot can still be nullified. */
6824 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6825 nullify = forward_branch_p (insn);
6827 /* Handle short versions first. */
6828 if (length == 4 && nullify)
6829 return "addib,%C2,n %1,%0,%3";
6830 else if (length == 4 && ! nullify)
6831 return "addib,%C2 %1,%0,%3";
6832 else if (length == 8)
6834 /* Handle weird backwards branch with a fulled delay slot
6835 which is nullified. */
6836 if (dbr_sequence_length () != 0
6837 && ! forward_branch_p (insn)
6839 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6840 /* Handle short backwards branch with an unfilled delay slot.
6841 Using a addb;nop rather than addi;bl saves 1 cycle for both
6842 taken and untaken branches. */
6843 else if (dbr_sequence_length () == 0
6844 && ! forward_branch_p (insn)
6845 && INSN_ADDRESSES_SET_P ()
6846 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6847 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6848 return "addib,%C2 %1,%0,%3%#";
6850 /* Handle normal cases. */
6852 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6854 return "addi,%N2 %1,%0,%0\n\tb %3";
6859 /* Deal with gross reload from FP register case. */
6860 else if (which_alternative == 1)
6862 /* Move loop counter from FP register to MEM then into a GR,
6863 increment the GR, store the GR into MEM, and finally reload
6864 the FP register from MEM from within the branch's delay slot. */
6865 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6867 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6868 if (get_attr_length (insn) == 24)
6869 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6871 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6873 /* Deal with gross reload from memory case. */
6876 /* Reload loop counter from memory, the store back to memory
6877 happens in the branch's delay slot. */
6878 output_asm_insn ("ldw %0,%4", operands);
6879 if (get_attr_length (insn) == 12)
6880 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6882 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6886 /* Return the output template for emitting a dbra type insn.
6888 Note it may perform some output operations on its own before
6889 returning the final output string. */
6891 output_movb (rtx *operands, rtx insn, int which_alternative,
6892 int reverse_comparison)
6895 /* A conditional branch to the following instruction (e.g. the delay slot) is
6896 asking for a disaster. Be prepared! */
6898 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6900 if (which_alternative == 0)
6901 return "copy %1,%0";
6902 else if (which_alternative == 1)
6904 output_asm_insn ("stw %1,-16(%%r30)", operands);
6905 return "{fldws|fldw} -16(%%r30),%0";
6907 else if (which_alternative == 2)
6913 /* Support the second variant. */
6914 if (reverse_comparison)
6915 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6917 if (which_alternative == 0)
6919 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6920 int length = get_attr_length (insn);
6922 /* If this is a long branch with its delay slot unfilled, set `nullify'
6923 as it can nullify the delay slot and save a nop. */
6924 if (length == 8 && dbr_sequence_length () == 0)
6927 /* If this is a short forward conditional branch which did not get
6928 its delay slot filled, the delay slot can still be nullified. */
6929 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6930 nullify = forward_branch_p (insn);
6932 /* Handle short versions first. */
6933 if (length == 4 && nullify)
6934 return "movb,%C2,n %1,%0,%3";
6935 else if (length == 4 && ! nullify)
6936 return "movb,%C2 %1,%0,%3";
6937 else if (length == 8)
6939 /* Handle weird backwards branch with a filled delay slot
6940 which is nullified. */
6941 if (dbr_sequence_length () != 0
6942 && ! forward_branch_p (insn)
6944 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6946 /* Handle short backwards branch with an unfilled delay slot.
6947 Using a movb;nop rather than or;bl saves 1 cycle for both
6948 taken and untaken branches. */
6949 else if (dbr_sequence_length () == 0
6950 && ! forward_branch_p (insn)
6951 && INSN_ADDRESSES_SET_P ()
6952 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6953 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6954 return "movb,%C2 %1,%0,%3%#";
6955 /* Handle normal cases. */
6957 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6959 return "or,%N2 %1,%%r0,%0\n\tb %3";
6964 /* Deal with gross reload from FP register case. */
6965 else if (which_alternative == 1)
6967 /* Move loop counter from FP register to MEM then into a GR,
6968 increment the GR, store the GR into MEM, and finally reload
6969 the FP register from MEM from within the branch's delay slot. */
6970 output_asm_insn ("stw %1,-16(%%r30)", operands);
6971 if (get_attr_length (insn) == 12)
6972 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6974 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6976 /* Deal with gross reload from memory case. */
6977 else if (which_alternative == 2)
6979 /* Reload loop counter from memory, the store back to memory
6980 happens in the branch's delay slot. */
6981 if (get_attr_length (insn) == 8)
6982 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6984 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6986 /* Handle SAR as a destination. */
6989 if (get_attr_length (insn) == 8)
6990 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6992 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
6996 /* Copy any FP arguments in INSN into integer registers. */
6998 copy_fp_args (rtx insn)
7003 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7005 int arg_mode, regno;
7006 rtx use = XEXP (link, 0);
7008 if (! (GET_CODE (use) == USE
7009 && GET_CODE (XEXP (use, 0)) == REG
7010 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7013 arg_mode = GET_MODE (XEXP (use, 0));
7014 regno = REGNO (XEXP (use, 0));
7016 /* Is it a floating point register? */
7017 if (regno >= 32 && regno <= 39)
7019 /* Copy the FP register into an integer register via memory. */
7020 if (arg_mode == SFmode)
7022 xoperands[0] = XEXP (use, 0);
7023 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
7024 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
7025 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7029 xoperands[0] = XEXP (use, 0);
7030 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
7031 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
7032 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
7033 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7039 /* Compute length of the FP argument copy sequence for INSN. */
7041 length_fp_args (rtx insn)
7046 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7048 int arg_mode, regno;
7049 rtx use = XEXP (link, 0);
7051 if (! (GET_CODE (use) == USE
7052 && GET_CODE (XEXP (use, 0)) == REG
7053 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7056 arg_mode = GET_MODE (XEXP (use, 0));
7057 regno = REGNO (XEXP (use, 0));
7059 /* Is it a floating point register? */
7060 if (regno >= 32 && regno <= 39)
7062 if (arg_mode == SFmode)
7072 /* Return the attribute length for the millicode call instruction INSN.
7073 The length must match the code generated by output_millicode_call.
7074 We include the delay slot in the returned length as it is better to
7075 over estimate the length than to under estimate it. */
7078 attr_length_millicode_call (rtx insn)
7080 unsigned long distance = -1;
7081 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7083 if (INSN_ADDRESSES_SET_P ())
7085 distance = (total + insn_current_reference_address (insn));
7086 if (distance < total)
7092 if (!TARGET_LONG_CALLS && distance < 7600000)
7097 else if (TARGET_PORTABLE_RUNTIME)
7101 if (!TARGET_LONG_CALLS && distance < 240000)
7104 if (TARGET_LONG_ABS_CALL && !flag_pic)
7111 /* INSN is a function call. It may have an unconditional jump
7114 CALL_DEST is the routine we are calling. */
7117 output_millicode_call (rtx insn, rtx call_dest)
7119 int attr_length = get_attr_length (insn);
7120 int seq_length = dbr_sequence_length ();
7125 xoperands[0] = call_dest;
7126 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7128 /* Handle the common case where we are sure that the branch will
7129 reach the beginning of the $CODE$ subspace. The within reach
7130 form of the $$sh_func_adrs call has a length of 28. Because
7131 it has an attribute type of multi, it never has a nonzero
7132 sequence length. The length of the $$sh_func_adrs is the same
7133 as certain out of reach PIC calls to other routines. */
7134 if (!TARGET_LONG_CALLS
7135 && ((seq_length == 0
7136 && (attr_length == 12
7137 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7138 || (seq_length != 0 && attr_length == 8)))
7140 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7146 /* It might seem that one insn could be saved by accessing
7147 the millicode function using the linkage table. However,
7148 this doesn't work in shared libraries and other dynamically
7149 loaded objects. Using a pc-relative sequence also avoids
7150 problems related to the implicit use of the gp register. */
7151 output_asm_insn ("b,l .+8,%%r1", xoperands);
7155 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7156 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7160 xoperands[1] = gen_label_rtx ();
7161 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7162 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7163 CODE_LABEL_NUMBER (xoperands[1]));
7164 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7167 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7169 else if (TARGET_PORTABLE_RUNTIME)
7171 /* Pure portable runtime doesn't allow be/ble; we also don't
7172 have PIC support in the assembler/linker, so this sequence
7175 /* Get the address of our target into %r1. */
7176 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7177 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7179 /* Get our return address into %r31. */
7180 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7181 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7183 /* Jump to our target address in %r1. */
7184 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7188 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7190 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7192 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7196 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7197 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7199 if (TARGET_SOM || !TARGET_GAS)
7201 /* The HP assembler can generate relocations for the
7202 difference of two symbols. GAS can do this for a
7203 millicode symbol but not an arbitrary external
7204 symbol when generating SOM output. */
7205 xoperands[1] = gen_label_rtx ();
7206 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7207 CODE_LABEL_NUMBER (xoperands[1]));
7208 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7209 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7213 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7214 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7218 /* Jump to our target address in %r1. */
7219 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7223 if (seq_length == 0)
7224 output_asm_insn ("nop", xoperands);
7226 /* We are done if there isn't a jump in the delay slot. */
7227 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7230 /* This call has an unconditional jump in its delay slot. */
7231 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7233 /* See if the return address can be adjusted. Use the containing
7234 sequence insn's address. */
7235 if (INSN_ADDRESSES_SET_P ())
7237 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7238 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7239 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7241 if (VAL_14_BITS_P (distance))
7243 xoperands[1] = gen_label_rtx ();
7244 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7245 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7246 CODE_LABEL_NUMBER (xoperands[1]));
7249 /* ??? This branch may not reach its target. */
7250 output_asm_insn ("nop\n\tb,n %0", xoperands);
7253 /* ??? This branch may not reach its target. */
7254 output_asm_insn ("nop\n\tb,n %0", xoperands);
7256 /* Delete the jump. */
7257 PUT_CODE (NEXT_INSN (insn), NOTE);
7258 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7259 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7264 /* Return the attribute length of the call instruction INSN. The SIBCALL
7265 flag indicates whether INSN is a regular call or a sibling call. The
7266 length returned must be longer than the code actually generated by
7267 output_call. Since branch shortening is done before delay branch
7268 sequencing, there is no way to determine whether or not the delay
7269 slot will be filled during branch shortening. Even when the delay
7270 slot is filled, we may have to add a nop if the delay slot contains
7271 a branch that can't reach its target. Thus, we always have to include
7272 the delay slot in the length estimate. This used to be done in
7273 pa_adjust_insn_length but we do it here now as some sequences always
7274 fill the delay slot and we can save four bytes in the estimate for
7278 attr_length_call (rtx insn, int sibcall)
7284 rtx pat = PATTERN (insn);
7285 unsigned long distance = -1;
7287 if (INSN_ADDRESSES_SET_P ())
7289 unsigned long total;
7291 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7292 distance = (total + insn_current_reference_address (insn));
7293 if (distance < total)
7297 /* Determine if this is a local call. */
7298 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7299 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7301 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7303 call_decl = SYMBOL_REF_DECL (call_dest);
7304 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7306 /* pc-relative branch. */
7307 if (!TARGET_LONG_CALLS
7308 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7309 || distance < 240000))
7312 /* 64-bit plabel sequence. */
7313 else if (TARGET_64BIT && !local_call)
7314 length += sibcall ? 28 : 24;
7316 /* non-pic long absolute branch sequence. */
7317 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7320 /* long pc-relative branch sequence. */
7321 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7322 || (TARGET_64BIT && !TARGET_GAS)
7323 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7327 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7331 /* 32-bit plabel sequence. */
7337 length += length_fp_args (insn);
7347 if (!TARGET_NO_SPACE_REGS)
7355 /* INSN is a function call. It may have an unconditional jump
7358 CALL_DEST is the routine we are calling. */
7361 output_call (rtx insn, rtx call_dest, int sibcall)
7363 int delay_insn_deleted = 0;
7364 int delay_slot_filled = 0;
7365 int seq_length = dbr_sequence_length ();
7366 tree call_decl = SYMBOL_REF_DECL (call_dest);
7367 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7370 xoperands[0] = call_dest;
7372 /* Handle the common case where we're sure that the branch will reach
7373 the beginning of the "$CODE$" subspace. This is the beginning of
7374 the current function if we are in a named section. */
7375 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7377 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7378 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7382 if (TARGET_64BIT && !local_call)
7384 /* ??? As far as I can tell, the HP linker doesn't support the
7385 long pc-relative sequence described in the 64-bit runtime
7386 architecture. So, we use a slightly longer indirect call. */
7387 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7389 xoperands[0] = p->internal_label;
7390 xoperands[1] = gen_label_rtx ();
7392 /* If this isn't a sibcall, we put the load of %r27 into the
7393 delay slot. We can't do this in a sibcall as we don't
7394 have a second call-clobbered scratch register available. */
7396 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7399 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7400 optimize, 0, 0, NULL);
7402 /* Now delete the delay insn. */
7403 PUT_CODE (NEXT_INSN (insn), NOTE);
7404 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7405 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7406 delay_insn_deleted = 1;
7409 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7410 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7411 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7415 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7416 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7417 output_asm_insn ("bve (%%r1)", xoperands);
7421 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7422 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7423 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7424 delay_slot_filled = 1;
7429 int indirect_call = 0;
7431 /* Emit a long call. There are several different sequences
7432 of increasing length and complexity. In most cases,
7433 they don't allow an instruction in the delay slot. */
7434 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7435 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7436 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7441 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7443 && (!TARGET_PA_20 || indirect_call))
7445 /* A non-jump insn in the delay slot. By definition we can
7446 emit this insn before the call (and in fact before argument
7448 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0,
7451 /* Now delete the delay insn. */
7452 PUT_CODE (NEXT_INSN (insn), NOTE);
7453 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7454 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7455 delay_insn_deleted = 1;
7458 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7460 /* This is the best sequence for making long calls in
7461 non-pic code. Unfortunately, GNU ld doesn't provide
7462 the stub needed for external calls, and GAS's support
7463 for this with the SOM linker is buggy. It is safe
7464 to use this for local calls. */
7465 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7467 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7471 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7474 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7476 output_asm_insn ("copy %%r31,%%r2", xoperands);
7477 delay_slot_filled = 1;
7482 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7483 || (TARGET_64BIT && !TARGET_GAS))
7485 /* The HP assembler and linker can handle relocations
7486 for the difference of two symbols. GAS and the HP
7487 linker can't do this when one of the symbols is
7489 xoperands[1] = gen_label_rtx ();
7490 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7491 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7492 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7493 CODE_LABEL_NUMBER (xoperands[1]));
7494 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7496 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7498 /* GAS currently can't generate the relocations that
7499 are needed for the SOM linker under HP-UX using this
7500 sequence. The GNU linker doesn't generate the stubs
7501 that are needed for external calls on TARGET_ELF32
7502 with this sequence. For now, we have to use a
7503 longer plabel sequence when using GAS. */
7504 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7505 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7507 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7512 /* Emit a long plabel-based call sequence. This is
7513 essentially an inline implementation of $$dyncall.
7514 We don't actually try to call $$dyncall as this is
7515 as difficult as calling the function itself. */
7516 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7518 xoperands[0] = p->internal_label;
7519 xoperands[1] = gen_label_rtx ();
7521 /* Since the call is indirect, FP arguments in registers
7522 need to be copied to the general registers. Then, the
7523 argument relocation stub will copy them back. */
7525 copy_fp_args (insn);
7529 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7530 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7531 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7535 output_asm_insn ("addil LR'%0-$global$,%%r27",
7537 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7541 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7542 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7543 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7544 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7546 if (!sibcall && !TARGET_PA_20)
7548 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7549 if (TARGET_NO_SPACE_REGS)
7550 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7552 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7559 output_asm_insn ("bve (%%r1)", xoperands);
7564 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7565 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7566 delay_slot_filled = 1;
7569 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7574 if (!TARGET_NO_SPACE_REGS)
7575 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7580 if (TARGET_NO_SPACE_REGS)
7581 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7583 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7587 if (TARGET_NO_SPACE_REGS)
7588 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7590 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7593 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7595 output_asm_insn ("copy %%r31,%%r2", xoperands);
7596 delay_slot_filled = 1;
7603 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7604 output_asm_insn ("nop", xoperands);
7606 /* We are done if there isn't a jump in the delay slot. */
7608 || delay_insn_deleted
7609 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7612 /* A sibcall should never have a branch in the delay slot. */
7616 /* This call has an unconditional jump in its delay slot. */
7617 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7619 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7621 /* See if the return address can be adjusted. Use the containing
7622 sequence insn's address. */
7623 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7624 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7625 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7627 if (VAL_14_BITS_P (distance))
7629 xoperands[1] = gen_label_rtx ();
7630 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7631 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7632 CODE_LABEL_NUMBER (xoperands[1]));
7635 output_asm_insn ("nop\n\tb,n %0", xoperands);
7638 output_asm_insn ("b,n %0", xoperands);
7640 /* Delete the jump. */
7641 PUT_CODE (NEXT_INSN (insn), NOTE);
7642 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7643 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7648 /* Return the attribute length of the indirect call instruction INSN.
7649 The length must match the code generated by output_indirect call.
7650 The returned length includes the delay slot. Currently, the delay
7651 slot of an indirect call sequence is not exposed and it is used by
7652 the sequence itself. */
7655 attr_length_indirect_call (rtx insn)
7657 unsigned long distance = -1;
7658 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7660 if (INSN_ADDRESSES_SET_P ())
7662 distance = (total + insn_current_reference_address (insn));
7663 if (distance < total)
7670 if (TARGET_FAST_INDIRECT_CALLS
7671 || (!TARGET_PORTABLE_RUNTIME
7672 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7678 if (TARGET_PORTABLE_RUNTIME)
7681 /* Out of reach, can use ble. */
7686 output_indirect_call (rtx insn, rtx call_dest)
7692 xoperands[0] = call_dest;
7693 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7694 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7698 /* First the special case for kernels, level 0 systems, etc. */
7699 if (TARGET_FAST_INDIRECT_CALLS)
7700 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7702 /* Now the normal case -- we can reach $$dyncall directly or
7703 we're sure that we can get there via a long-branch stub.
7705 No need to check target flags as the length uniquely identifies
7706 the remaining cases. */
7707 if (attr_length_indirect_call (insn) == 8)
7709 /* The HP linker substitutes a BLE for millicode calls using
7710 the short PIC PCREL form. Thus, we must use %r31 as the
7711 link register when generating PA 1.x code. */
7713 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7715 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7718 /* Long millicode call, but we are not generating PIC or portable runtime
7720 if (attr_length_indirect_call (insn) == 12)
7721 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7723 /* Long millicode call for portable runtime. */
7724 if (attr_length_indirect_call (insn) == 20)
7725 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7727 /* We need a long PIC call to $$dyncall. */
7728 xoperands[0] = NULL_RTX;
7729 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7730 if (TARGET_SOM || !TARGET_GAS)
7732 xoperands[0] = gen_label_rtx ();
7733 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7734 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7735 CODE_LABEL_NUMBER (xoperands[0]));
7736 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7740 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7741 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7744 output_asm_insn ("blr %%r0,%%r2", xoperands);
7745 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7749 /* Return the total length of the save and restore instructions needed for
7750 the data linkage table pointer (i.e., the PIC register) across the call
7751 instruction INSN. No-return calls do not require a save and restore.
7752 In addition, we may be able to avoid the save and restore for calls
7753 within the same translation unit. */
7756 attr_length_save_restore_dltp (rtx insn)
7758 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7764 /* In HPUX 8.0's shared library scheme, special relocations are needed
7765 for function labels if they might be passed to a function
7766 in a shared library (because shared libraries don't live in code
7767 space), and special magic is needed to construct their address. */
7770 hppa_encode_label (rtx sym)
7772 const char *str = XSTR (sym, 0);
7773 int len = strlen (str) + 1;
7776 p = newstr = alloca (len + 1);
7780 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7784 pa_encode_section_info (tree decl, rtx rtl, int first)
7786 if (first && TEXT_SPACE_P (decl))
7788 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7789 if (TREE_CODE (decl) == FUNCTION_DECL)
7790 hppa_encode_label (XEXP (rtl, 0));
7794 /* This is sort of inverse to pa_encode_section_info. */
7797 pa_strip_name_encoding (const char *str)
7799 str += (*str == '@');
7800 str += (*str == '*');
7805 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7807 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7810 /* Returns 1 if OP is a function label involved in a simple addition
7811 with a constant. Used to keep certain patterns from matching
7812 during instruction combination. */
7814 is_function_label_plus_const (rtx op)
7816 /* Strip off any CONST. */
7817 if (GET_CODE (op) == CONST)
7820 return (GET_CODE (op) == PLUS
7821 && function_label_operand (XEXP (op, 0), Pmode)
7822 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7825 /* Output assembly code for a thunk to FUNCTION. */
7828 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7829 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7832 const char *fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
7833 const char *tname = XSTR (XEXP (DECL_RTL (thunk_fndecl), 0), 0);
7834 int val_14 = VAL_14_BITS_P (delta);
7836 static unsigned int current_thunk_number;
7839 ASM_OUTPUT_LABEL (file, tname);
7840 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7842 fname = (*targetm.strip_name_encoding) (fname);
7843 tname = (*targetm.strip_name_encoding) (tname);
7845 /* Output the thunk. We know that the function is in the same
7846 translation unit (i.e., the same space) as the thunk, and that
7847 thunks are output after their method. Thus, we don't need an
7848 external branch to reach the function. With SOM and GAS,
7849 functions and thunks are effectively in different sections.
7850 Thus, we can always use a IA-relative branch and the linker
7851 will add a long branch stub if necessary.
7853 However, we have to be careful when generating PIC code on the
7854 SOM port to ensure that the sequence does not transfer to an
7855 import stub for the target function as this could clobber the
7856 return value saved at SP-24. This would also apply to the
7857 32-bit linux port if the multi-space model is implemented. */
7858 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7859 && !(flag_pic && TREE_PUBLIC (function))
7860 && (TARGET_GAS || last_address < 262132))
7861 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7862 && ((targetm.have_named_sections
7863 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7864 /* The GNU 64-bit linker has rather poor stub management.
7865 So, we use a long branch from thunks that aren't in
7866 the same section as the target function. */
7868 && (DECL_SECTION_NAME (thunk_fndecl)
7869 != DECL_SECTION_NAME (function)))
7870 || ((DECL_SECTION_NAME (thunk_fndecl)
7871 == DECL_SECTION_NAME (function))
7872 && last_address < 262132)))
7873 || (!targetm.have_named_sections && last_address < 262132))))
7877 fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC
7878 "(%%r26),%%r26\n", fname, delta);
7883 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7885 fprintf (file, "\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7886 "(%%r1),%%r26\n", fname, delta);
7890 else if (TARGET_64BIT)
7892 /* We only have one call-clobbered scratch register, so we can't
7893 make use of the delay slot if delta doesn't fit in 14 bits. */
7895 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7896 ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7897 "(%%r1),%%r26\n", delta, delta);
7899 fprintf (file, "\tb,l .+8,%%r1\n");
7903 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7904 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r1\n", fname);
7908 int off = val_14 ? 8 : 16;
7909 fprintf (file, "\taddil L'%s-%s-%d,%%r1\n", fname, tname, off);
7910 fprintf (file, "\tldo R'%s-%s-%d(%%r1),%%r1\n", fname, tname, off);
7915 fprintf (file, "\tbv %%r0(%%r1)\n\tldo ");
7916 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7921 fprintf (file, "\tbv,n %%r0(%%r1)\n");
7925 else if (TARGET_PORTABLE_RUNTIME)
7927 fprintf (file, "\tldil L'%s,%%r1\n", fname);
7928 fprintf (file, "\tldo R'%s(%%r1),%%r22\n", fname);
7932 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7933 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7938 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7940 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7941 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7945 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7947 /* The function is accessible from outside this module. The only
7948 way to avoid an import stub between the thunk and function is to
7949 call the function directly with an indirect sequence similar to
7950 that used by $$dyncall. This is possible because $$dyncall acts
7951 as the import stub in an indirect call. */
7954 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7955 lab = (*targetm.strip_name_encoding) (label);
7957 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7958 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7959 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7960 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7961 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7962 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7963 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7966 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7972 fprintf (file, "\tbve (%%r22)\n\tldo ");
7977 if (TARGET_NO_SPACE_REGS)
7979 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
7984 fprintf (file, "\tldsid (%%sr0,%%r22),%%r21\n");
7985 fprintf (file, "\tmtsp %%r21,%%sr0\n");
7986 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
7992 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7994 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7999 fprintf (file, "\tb,l .+8,%%r1\n");
8001 fprintf (file, "\tbl .+8,%%r1\n");
8003 if (TARGET_SOM || !TARGET_GAS)
8005 fprintf (file, "\taddil L'%s-%s-8,%%r1\n", fname, tname);
8006 fprintf (file, "\tldo R'%s-%s-8(%%r1),%%r22\n", fname, tname);
8010 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
8011 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r22\n", fname);
8016 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
8017 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
8022 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
8024 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
8025 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
8032 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC ",%%r26\n", delta);
8034 fprintf (file, "\tldil L'%s,%%r22\n", fname);
8035 fprintf (file, "\tbe R'%s(%%sr4,%%r22)\n\tldo ", fname);
8039 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
8044 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
8049 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8051 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8054 fprintf (file, "\t.align 4\n");
8055 ASM_OUTPUT_LABEL (file, label);
8056 fprintf (file, "\t.word P'%s\n", fname);
8058 else if (TARGET_SOM && TARGET_GAS)
8061 current_thunk_number++;
8062 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8063 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8064 last_address += nbytes;
8065 update_total_code_bytes (nbytes);
8068 /* Only direct calls to static functions are allowed to be sibling (tail)
8071 This restriction is necessary because some linker generated stubs will
8072 store return pointers into rp' in some cases which might clobber a
8073 live value already in rp'.
8075 In a sibcall the current function and the target function share stack
8076 space. Thus if the path to the current function and the path to the
8077 target function save a value in rp', they save the value into the
8078 same stack slot, which has undesirable consequences.
8080 Because of the deferred binding nature of shared libraries any function
8081 with external scope could be in a different load module and thus require
8082 rp' to be saved when calling that function. So sibcall optimizations
8083 can only be safe for static function.
8085 Note that GCC never needs return value relocations, so we don't have to
8086 worry about static calls with return value relocations (which require
8089 It is safe to perform a sibcall optimization when the target function
8090 will never return. */
8092 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8094 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8095 single subspace mode and the call is not indirect. As far as I know,
8096 there is no operating system support for the multiple subspace mode.
8097 It might be possible to support indirect calls if we didn't use
8098 $$dyncall (see the indirect sequence generated in output_call). */
8100 return (decl != NULL_TREE);
8102 /* Sibcalls are not ok because the arg pointer register is not a fixed
8103 register. This prevents the sibcall optimization from occurring. In
8104 addition, there are problems with stub placement using GNU ld. This
8105 is because a normal sibcall branch uses a 17-bit relocation while
8106 a regular call branch uses a 22-bit relocation. As a result, more
8107 care needs to be taken in the placement of long-branch stubs. */
8112 && !TARGET_PORTABLE_RUNTIME
8113 && !TREE_PUBLIC (decl));
8116 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8117 use in fmpyadd instructions. */
8119 fmpyaddoperands (rtx *operands)
8121 enum machine_mode mode = GET_MODE (operands[0]);
8123 /* Must be a floating point mode. */
8124 if (mode != SFmode && mode != DFmode)
8127 /* All modes must be the same. */
8128 if (! (mode == GET_MODE (operands[1])
8129 && mode == GET_MODE (operands[2])
8130 && mode == GET_MODE (operands[3])
8131 && mode == GET_MODE (operands[4])
8132 && mode == GET_MODE (operands[5])))
8135 /* All operands must be registers. */
8136 if (! (GET_CODE (operands[1]) == REG
8137 && GET_CODE (operands[2]) == REG
8138 && GET_CODE (operands[3]) == REG
8139 && GET_CODE (operands[4]) == REG
8140 && GET_CODE (operands[5]) == REG))
8143 /* Only 2 real operands to the addition. One of the input operands must
8144 be the same as the output operand. */
8145 if (! rtx_equal_p (operands[3], operands[4])
8146 && ! rtx_equal_p (operands[3], operands[5]))
8149 /* Inout operand of add cannot conflict with any operands from multiply. */
8150 if (rtx_equal_p (operands[3], operands[0])
8151 || rtx_equal_p (operands[3], operands[1])
8152 || rtx_equal_p (operands[3], operands[2]))
8155 /* multiply cannot feed into addition operands. */
8156 if (rtx_equal_p (operands[4], operands[0])
8157 || rtx_equal_p (operands[5], operands[0]))
8160 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8162 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8163 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8164 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8165 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8166 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8167 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8170 /* Passed. Operands are suitable for fmpyadd. */
8174 #if !defined(USE_COLLECT2)
8176 pa_asm_out_constructor (rtx symbol, int priority)
8178 if (!function_label_operand (symbol, VOIDmode))
8179 hppa_encode_label (symbol);
8181 #ifdef CTORS_SECTION_ASM_OP
8182 default_ctor_section_asm_out_constructor (symbol, priority);
8184 # ifdef TARGET_ASM_NAMED_SECTION
8185 default_named_section_asm_out_constructor (symbol, priority);
8187 default_stabs_asm_out_constructor (symbol, priority);
8193 pa_asm_out_destructor (rtx symbol, int priority)
8195 if (!function_label_operand (symbol, VOIDmode))
8196 hppa_encode_label (symbol);
8198 #ifdef DTORS_SECTION_ASM_OP
8199 default_dtor_section_asm_out_destructor (symbol, priority);
8201 # ifdef TARGET_ASM_NAMED_SECTION
8202 default_named_section_asm_out_destructor (symbol, priority);
8204 default_stabs_asm_out_destructor (symbol, priority);
8210 /* This function places uninitialized global data in the bss section.
8211 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8212 function on the SOM port to prevent uninitialized global data from
8213 being placed in the data section. */
8216 pa_asm_output_aligned_bss (FILE *stream,
8218 unsigned HOST_WIDE_INT size,
8222 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8224 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8225 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8228 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8229 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8232 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8233 ASM_OUTPUT_LABEL (stream, name);
8234 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8237 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8238 that doesn't allow the alignment of global common storage to be directly
8239 specified. The SOM linker aligns common storage based on the rounded
8240 value of the NUM_BYTES parameter in the .comm directive. It's not
8241 possible to use the .align directive as it doesn't affect the alignment
8242 of the label associated with a .comm directive. */
8245 pa_asm_output_aligned_common (FILE *stream,
8247 unsigned HOST_WIDE_INT size,
8252 assemble_name (stream, name);
8253 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8254 MAX (size, align / BITS_PER_UNIT));
8257 /* We can't use .comm for local common storage as the SOM linker effectively
8258 treats the symbol as universal and uses the same storage for local symbols
8259 with the same name in different object files. The .block directive
8260 reserves an uninitialized block of storage. However, it's not common
8261 storage. Fortunately, GCC never requests common storage with the same
8262 name in any given translation unit. */
8265 pa_asm_output_aligned_local (FILE *stream,
8267 unsigned HOST_WIDE_INT size,
8271 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8274 fprintf (stream, "%s", LOCAL_ASM_OP);
8275 assemble_name (stream, name);
8276 fprintf (stream, "\n");
8279 ASM_OUTPUT_LABEL (stream, name);
8280 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8283 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8284 use in fmpysub instructions. */
8286 fmpysuboperands (rtx *operands)
8288 enum machine_mode mode = GET_MODE (operands[0]);
8290 /* Must be a floating point mode. */
8291 if (mode != SFmode && mode != DFmode)
8294 /* All modes must be the same. */
8295 if (! (mode == GET_MODE (operands[1])
8296 && mode == GET_MODE (operands[2])
8297 && mode == GET_MODE (operands[3])
8298 && mode == GET_MODE (operands[4])
8299 && mode == GET_MODE (operands[5])))
8302 /* All operands must be registers. */
8303 if (! (GET_CODE (operands[1]) == REG
8304 && GET_CODE (operands[2]) == REG
8305 && GET_CODE (operands[3]) == REG
8306 && GET_CODE (operands[4]) == REG
8307 && GET_CODE (operands[5]) == REG))
8310 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8311 operation, so operands[4] must be the same as operand[3]. */
8312 if (! rtx_equal_p (operands[3], operands[4]))
8315 /* multiply cannot feed into subtraction. */
8316 if (rtx_equal_p (operands[5], operands[0]))
8319 /* Inout operand of sub cannot conflict with any operands from multiply. */
8320 if (rtx_equal_p (operands[3], operands[0])
8321 || rtx_equal_p (operands[3], operands[1])
8322 || rtx_equal_p (operands[3], operands[2]))
8325 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8327 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8328 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8329 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8330 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8331 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8332 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8335 /* Passed. Operands are suitable for fmpysub. */
8340 plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8342 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
8343 || GET_CODE (op) == IOR);
8346 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8347 constants for shadd instructions. */
8349 shadd_constant_p (int val)
8351 if (val == 2 || val == 4 || val == 8)
8357 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
8358 the valid constant for shadd instructions. */
8360 shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8362 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
8365 /* Return 1 if OP is valid as a base or index register in a
8369 borx_reg_operand (rtx op, enum machine_mode mode)
8371 if (GET_CODE (op) != REG)
8374 /* We must reject virtual registers as the only expressions that
8375 can be instantiated are REG and REG+CONST. */
8376 if (op == virtual_incoming_args_rtx
8377 || op == virtual_stack_vars_rtx
8378 || op == virtual_stack_dynamic_rtx
8379 || op == virtual_outgoing_args_rtx
8380 || op == virtual_cfa_rtx)
8383 /* While it's always safe to index off the frame pointer, it's not
8384 profitable to do so when the frame pointer is being eliminated. */
8385 if (!reload_completed
8386 && flag_omit_frame_pointer
8387 && !current_function_calls_alloca
8388 && op == frame_pointer_rtx)
8391 return register_operand (op, mode);
8394 /* Return 1 if this operand is anything other than a hard register. */
8397 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8399 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8402 /* Return 1 if INSN branches forward. Should be using insn_addresses
8403 to avoid walking through all the insns... */
8405 forward_branch_p (rtx insn)
8407 rtx label = JUMP_LABEL (insn);
8414 insn = NEXT_INSN (insn);
8417 return (insn == label);
8420 /* Return 1 if OP is an equality comparison, else return 0. */
8422 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8424 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8427 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
8429 movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8431 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
8432 || GET_CODE (op) == LT || GET_CODE (op) == GE);
8435 /* Return 1 if INSN is in the delay slot of a call instruction. */
8437 jump_in_call_delay (rtx insn)
8440 if (GET_CODE (insn) != JUMP_INSN)
8443 if (PREV_INSN (insn)
8444 && PREV_INSN (PREV_INSN (insn))
8445 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8447 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8449 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8450 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8457 /* Output an unconditional move and branch insn. */
8460 output_parallel_movb (rtx *operands, int length)
8462 /* These are the cases in which we win. */
8464 return "mov%I1b,tr %1,%0,%2";
8466 /* None of these cases wins, but they don't lose either. */
8467 if (dbr_sequence_length () == 0)
8469 /* Nothing in the delay slot, fake it by putting the combined
8470 insn (the copy or add) in the delay slot of a bl. */
8471 if (GET_CODE (operands[1]) == CONST_INT)
8472 return "b %2\n\tldi %1,%0";
8474 return "b %2\n\tcopy %1,%0";
8478 /* Something in the delay slot, but we've got a long branch. */
8479 if (GET_CODE (operands[1]) == CONST_INT)
8480 return "ldi %1,%0\n\tb %2";
8482 return "copy %1,%0\n\tb %2";
8486 /* Output an unconditional add and branch insn. */
8489 output_parallel_addb (rtx *operands, int length)
8491 /* To make life easy we want operand0 to be the shared input/output
8492 operand and operand1 to be the readonly operand. */
8493 if (operands[0] == operands[1])
8494 operands[1] = operands[2];
8496 /* These are the cases in which we win. */
8498 return "add%I1b,tr %1,%0,%3";
8500 /* None of these cases win, but they don't lose either. */
8501 if (dbr_sequence_length () == 0)
8503 /* Nothing in the delay slot, fake it by putting the combined
8504 insn (the copy or add) in the delay slot of a bl. */
8505 return "b %3\n\tadd%I1 %1,%0,%0";
8509 /* Something in the delay slot, but we've got a long branch. */
8510 return "add%I1 %1,%0,%0\n\tb %3";
8514 /* Return nonzero if INSN (a jump insn) immediately follows a call
8515 to a named function. This is used to avoid filling the delay slot
8516 of the jump since it can usually be eliminated by modifying RP in
8517 the delay slot of the call. */
8520 following_call (rtx insn)
8522 if (! TARGET_JUMP_IN_DELAY)
8525 /* Find the previous real insn, skipping NOTEs. */
8526 insn = PREV_INSN (insn);
8527 while (insn && GET_CODE (insn) == NOTE)
8528 insn = PREV_INSN (insn);
8530 /* Check for CALL_INSNs and millicode calls. */
8532 && ((GET_CODE (insn) == CALL_INSN
8533 && get_attr_type (insn) != TYPE_DYNCALL)
8534 || (GET_CODE (insn) == INSN
8535 && GET_CODE (PATTERN (insn)) != SEQUENCE
8536 && GET_CODE (PATTERN (insn)) != USE
8537 && GET_CODE (PATTERN (insn)) != CLOBBER
8538 && get_attr_type (insn) == TYPE_MILLI)))
8544 /* We use this hook to perform a PA specific optimization which is difficult
8545 to do in earlier passes.
8547 We want the delay slots of branches within jump tables to be filled.
8548 None of the compiler passes at the moment even has the notion that a
8549 PA jump table doesn't contain addresses, but instead contains actual
8552 Because we actually jump into the table, the addresses of each entry
8553 must stay constant in relation to the beginning of the table (which
8554 itself must stay constant relative to the instruction to jump into
8555 it). I don't believe we can guarantee earlier passes of the compiler
8556 will adhere to those rules.
8558 So, late in the compilation process we find all the jump tables, and
8559 expand them into real code -- e.g. each entry in the jump table vector
8560 will get an appropriate label followed by a jump to the final target.
8562 Reorg and the final jump pass can then optimize these branches and
8563 fill their delay slots. We end up with smaller, more efficient code.
8565 The jump instructions within the table are special; we must be able
8566 to identify them during assembly output (if the jumps don't get filled
8567 we need to emit a nop rather than nullifying the delay slot)). We
8568 identify jumps in switch tables by using insns with the attribute
8569 type TYPE_BTABLE_BRANCH.
8571 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8572 insns. This serves two purposes, first it prevents jump.c from
8573 noticing that the last N entries in the table jump to the instruction
8574 immediately after the table and deleting the jumps. Second, those
8575 insns mark where we should emit .begin_brtab and .end_brtab directives
8576 when using GAS (allows for better link time optimizations). */
8583 remove_useless_addtr_insns (1);
8585 if (pa_cpu < PROCESSOR_8000)
8586 pa_combine_instructions ();
8589 /* This is fairly cheap, so always run it if optimizing. */
8590 if (optimize > 0 && !TARGET_BIG_SWITCH)
8592 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8593 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8595 rtx pattern, tmp, location, label;
8596 unsigned int length, i;
8598 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8599 if (GET_CODE (insn) != JUMP_INSN
8600 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8601 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8604 /* Emit marker for the beginning of the branch table. */
8605 emit_insn_before (gen_begin_brtab (), insn);
8607 pattern = PATTERN (insn);
8608 location = PREV_INSN (insn);
8609 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8611 for (i = 0; i < length; i++)
8613 /* Emit a label before each jump to keep jump.c from
8614 removing this code. */
8615 tmp = gen_label_rtx ();
8616 LABEL_NUSES (tmp) = 1;
8617 emit_label_after (tmp, location);
8618 location = NEXT_INSN (location);
8620 if (GET_CODE (pattern) == ADDR_VEC)
8621 label = XEXP (XVECEXP (pattern, 0, i), 0);
8623 label = XEXP (XVECEXP (pattern, 1, i), 0);
8625 tmp = gen_short_jump (label);
8627 /* Emit the jump itself. */
8628 tmp = emit_jump_insn_after (tmp, location);
8629 JUMP_LABEL (tmp) = label;
8630 LABEL_NUSES (label)++;
8631 location = NEXT_INSN (location);
8633 /* Emit a BARRIER after the jump. */
8634 emit_barrier_after (location);
8635 location = NEXT_INSN (location);
8638 /* Emit marker for the end of the branch table. */
8639 emit_insn_before (gen_end_brtab (), location);
8640 location = NEXT_INSN (location);
8641 emit_barrier_after (location);
8643 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8649 /* Still need brtab marker insns. FIXME: the presence of these
8650 markers disables output of the branch table to readonly memory,
8651 and any alignment directives that might be needed. Possibly,
8652 the begin_brtab insn should be output before the label for the
8653 table. This doesn't matter at the moment since the tables are
8654 always output in the text section. */
8655 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8657 /* Find an ADDR_VEC insn. */
8658 if (GET_CODE (insn) != JUMP_INSN
8659 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8660 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8663 /* Now generate markers for the beginning and end of the
8665 emit_insn_before (gen_begin_brtab (), insn);
8666 emit_insn_after (gen_end_brtab (), insn);
8671 /* The PA has a number of odd instructions which can perform multiple
8672 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8673 it may be profitable to combine two instructions into one instruction
8674 with two outputs. It's not profitable PA2.0 machines because the
8675 two outputs would take two slots in the reorder buffers.
8677 This routine finds instructions which can be combined and combines
8678 them. We only support some of the potential combinations, and we
8679 only try common ways to find suitable instructions.
8681 * addb can add two registers or a register and a small integer
8682 and jump to a nearby (+-8k) location. Normally the jump to the
8683 nearby location is conditional on the result of the add, but by
8684 using the "true" condition we can make the jump unconditional.
8685 Thus addb can perform two independent operations in one insn.
8687 * movb is similar to addb in that it can perform a reg->reg
8688 or small immediate->reg copy and jump to a nearby (+-8k location).
8690 * fmpyadd and fmpysub can perform a FP multiply and either an
8691 FP add or FP sub if the operands of the multiply and add/sub are
8692 independent (there are other minor restrictions). Note both
8693 the fmpy and fadd/fsub can in theory move to better spots according
8694 to data dependencies, but for now we require the fmpy stay at a
8697 * Many of the memory operations can perform pre & post updates
8698 of index registers. GCC's pre/post increment/decrement addressing
8699 is far too simple to take advantage of all the possibilities. This
8700 pass may not be suitable since those insns may not be independent.
8702 * comclr can compare two ints or an int and a register, nullify
8703 the following instruction and zero some other register. This
8704 is more difficult to use as it's harder to find an insn which
8705 will generate a comclr than finding something like an unconditional
8706 branch. (conditional moves & long branches create comclr insns).
8708 * Most arithmetic operations can conditionally skip the next
8709 instruction. They can be viewed as "perform this operation
8710 and conditionally jump to this nearby location" (where nearby
8711 is an insns away). These are difficult to use due to the
8712 branch length restrictions. */
8715 pa_combine_instructions (void)
8719 /* This can get expensive since the basic algorithm is on the
8720 order of O(n^2) (or worse). Only do it for -O2 or higher
8721 levels of optimization. */
8725 /* Walk down the list of insns looking for "anchor" insns which
8726 may be combined with "floating" insns. As the name implies,
8727 "anchor" instructions don't move, while "floating" insns may
8729 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8730 new = make_insn_raw (new);
8732 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8734 enum attr_pa_combine_type anchor_attr;
8735 enum attr_pa_combine_type floater_attr;
8737 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8738 Also ignore any special USE insns. */
8739 if ((GET_CODE (anchor) != INSN
8740 && GET_CODE (anchor) != JUMP_INSN
8741 && GET_CODE (anchor) != CALL_INSN)
8742 || GET_CODE (PATTERN (anchor)) == USE
8743 || GET_CODE (PATTERN (anchor)) == CLOBBER
8744 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8745 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8748 anchor_attr = get_attr_pa_combine_type (anchor);
8749 /* See if anchor is an insn suitable for combination. */
8750 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8751 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8752 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8753 && ! forward_branch_p (anchor)))
8757 for (floater = PREV_INSN (anchor);
8759 floater = PREV_INSN (floater))
8761 if (GET_CODE (floater) == NOTE
8762 || (GET_CODE (floater) == INSN
8763 && (GET_CODE (PATTERN (floater)) == USE
8764 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8767 /* Anything except a regular INSN will stop our search. */
8768 if (GET_CODE (floater) != INSN
8769 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8770 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8776 /* See if FLOATER is suitable for combination with the
8778 floater_attr = get_attr_pa_combine_type (floater);
8779 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8780 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8781 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8782 && floater_attr == PA_COMBINE_TYPE_FMPY))
8784 /* If ANCHOR and FLOATER can be combined, then we're
8785 done with this pass. */
8786 if (pa_can_combine_p (new, anchor, floater, 0,
8787 SET_DEST (PATTERN (floater)),
8788 XEXP (SET_SRC (PATTERN (floater)), 0),
8789 XEXP (SET_SRC (PATTERN (floater)), 1)))
8793 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8794 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8796 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8798 if (pa_can_combine_p (new, anchor, floater, 0,
8799 SET_DEST (PATTERN (floater)),
8800 XEXP (SET_SRC (PATTERN (floater)), 0),
8801 XEXP (SET_SRC (PATTERN (floater)), 1)))
8806 if (pa_can_combine_p (new, anchor, floater, 0,
8807 SET_DEST (PATTERN (floater)),
8808 SET_SRC (PATTERN (floater)),
8809 SET_SRC (PATTERN (floater))))
8815 /* If we didn't find anything on the backwards scan try forwards. */
8817 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8818 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8820 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8822 if (GET_CODE (floater) == NOTE
8823 || (GET_CODE (floater) == INSN
8824 && (GET_CODE (PATTERN (floater)) == USE
8825 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8829 /* Anything except a regular INSN will stop our search. */
8830 if (GET_CODE (floater) != INSN
8831 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8832 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8838 /* See if FLOATER is suitable for combination with the
8840 floater_attr = get_attr_pa_combine_type (floater);
8841 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8842 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8843 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8844 && floater_attr == PA_COMBINE_TYPE_FMPY))
8846 /* If ANCHOR and FLOATER can be combined, then we're
8847 done with this pass. */
8848 if (pa_can_combine_p (new, anchor, floater, 1,
8849 SET_DEST (PATTERN (floater)),
8850 XEXP (SET_SRC (PATTERN (floater)),
8852 XEXP (SET_SRC (PATTERN (floater)),
8859 /* FLOATER will be nonzero if we found a suitable floating
8860 insn for combination with ANCHOR. */
8862 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8863 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8865 /* Emit the new instruction and delete the old anchor. */
8866 emit_insn_before (gen_rtx_PARALLEL
8868 gen_rtvec (2, PATTERN (anchor),
8869 PATTERN (floater))),
8872 PUT_CODE (anchor, NOTE);
8873 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8874 NOTE_SOURCE_FILE (anchor) = 0;
8876 /* Emit a special USE insn for FLOATER, then delete
8877 the floating insn. */
8878 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8879 delete_insn (floater);
8884 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8887 /* Emit the new_jump instruction and delete the old anchor. */
8889 = emit_jump_insn_before (gen_rtx_PARALLEL
8891 gen_rtvec (2, PATTERN (anchor),
8892 PATTERN (floater))),
8895 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8896 PUT_CODE (anchor, NOTE);
8897 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8898 NOTE_SOURCE_FILE (anchor) = 0;
8900 /* Emit a special USE insn for FLOATER, then delete
8901 the floating insn. */
8902 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8903 delete_insn (floater);
8911 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8914 int insn_code_number;
8917 /* Create a PARALLEL with the patterns of ANCHOR and
8918 FLOATER, try to recognize it, then test constraints
8919 for the resulting pattern.
8921 If the pattern doesn't match or the constraints
8922 aren't met keep searching for a suitable floater
8924 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8925 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8926 INSN_CODE (new) = -1;
8927 insn_code_number = recog_memoized (new);
8928 if (insn_code_number < 0
8929 || (extract_insn (new), ! constrain_operands (1)))
8943 /* There's up to three operands to consider. One
8944 output and two inputs.
8946 The output must not be used between FLOATER & ANCHOR
8947 exclusive. The inputs must not be set between
8948 FLOATER and ANCHOR exclusive. */
8950 if (reg_used_between_p (dest, start, end))
8953 if (reg_set_between_p (src1, start, end))
8956 if (reg_set_between_p (src2, start, end))
8959 /* If we get here, then everything is good. */
8963 /* Return nonzero if references for INSN are delayed.
8965 Millicode insns are actually function calls with some special
8966 constraints on arguments and register usage.
8968 Millicode calls always expect their arguments in the integer argument
8969 registers, and always return their result in %r29 (ret1). They
8970 are expected to clobber their arguments, %r1, %r29, and the return
8971 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8973 This function tells reorg that the references to arguments and
8974 millicode calls do not appear to happen until after the millicode call.
8975 This allows reorg to put insns which set the argument registers into the
8976 delay slot of the millicode call -- thus they act more like traditional
8979 Note we cannot consider side effects of the insn to be delayed because
8980 the branch and link insn will clobber the return pointer. If we happened
8981 to use the return pointer in the delay slot of the call, then we lose.
8983 get_attr_type will try to recognize the given insn, so make sure to
8984 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8987 insn_refs_are_delayed (rtx insn)
8989 return ((GET_CODE (insn) == INSN
8990 && GET_CODE (PATTERN (insn)) != SEQUENCE
8991 && GET_CODE (PATTERN (insn)) != USE
8992 && GET_CODE (PATTERN (insn)) != CLOBBER
8993 && get_attr_type (insn) == TYPE_MILLI));
8996 /* On the HP-PA the value is found in register(s) 28(-29), unless
8997 the mode is SF or DF. Then the value is returned in fr4 (32).
8999 This must perform the same promotions as PROMOTE_MODE, else
9000 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
9002 Small structures must be returned in a PARALLEL on PA64 in order
9003 to match the HP Compiler ABI. */
9006 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
9008 enum machine_mode valmode;
9010 /* Aggregates with a size less than or equal to 128 bits are returned
9011 in GR 28(-29). They are left justified. The pad bits are undefined.
9012 Larger aggregates are returned in memory. */
9013 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
9017 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9019 for (i = 0; i < ub; i++)
9021 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9022 gen_rtx_REG (DImode, 28 + i),
9027 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9030 if ((INTEGRAL_TYPE_P (valtype)
9031 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
9032 || POINTER_TYPE_P (valtype))
9033 valmode = word_mode;
9035 valmode = TYPE_MODE (valtype);
9037 if (TREE_CODE (valtype) == REAL_TYPE
9038 && TYPE_MODE (valtype) != TFmode
9039 && !TARGET_SOFT_FLOAT)
9040 return gen_rtx_REG (valmode, 32);
9042 return gen_rtx_REG (valmode, 28);
9045 /* Return the location of a parameter that is passed in a register or NULL
9046 if the parameter has any component that is passed in memory.
9048 This is new code and will be pushed to into the net sources after
9051 ??? We might want to restructure this so that it looks more like other
9054 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
9055 int named ATTRIBUTE_UNUSED)
9057 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9064 if (mode == VOIDmode)
9067 arg_size = FUNCTION_ARG_SIZE (mode, type);
9069 /* If this arg would be passed partially or totally on the stack, then
9070 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
9071 handle arguments which are split between regs and stack slots if
9072 the ABI mandates split arguments. */
9075 /* The 32-bit ABI does not split arguments. */
9076 if (cum->words + arg_size > max_arg_words)
9082 alignment = cum->words & 1;
9083 if (cum->words + alignment >= max_arg_words)
9087 /* The 32bit ABIs and the 64bit ABIs are rather different,
9088 particularly in their handling of FP registers. We might
9089 be able to cleverly share code between them, but I'm not
9090 going to bother in the hope that splitting them up results
9091 in code that is more easily understood. */
9095 /* Advance the base registers to their current locations.
9097 Remember, gprs grow towards smaller register numbers while
9098 fprs grow to higher register numbers. Also remember that
9099 although FP regs are 32-bit addressable, we pretend that
9100 the registers are 64-bits wide. */
9101 gpr_reg_base = 26 - cum->words;
9102 fpr_reg_base = 32 + cum->words;
9104 /* Arguments wider than one word and small aggregates need special
9108 || (type && AGGREGATE_TYPE_P (type)))
9110 /* Double-extended precision (80-bit), quad-precision (128-bit)
9111 and aggregates including complex numbers are aligned on
9112 128-bit boundaries. The first eight 64-bit argument slots
9113 are associated one-to-one, with general registers r26
9114 through r19, and also with floating-point registers fr4
9115 through fr11. Arguments larger than one word are always
9116 passed in general registers.
9118 Using a PARALLEL with a word mode register results in left
9119 justified data on a big-endian target. */
9122 int i, offset = 0, ub = arg_size;
9124 /* Align the base register. */
9125 gpr_reg_base -= alignment;
9127 ub = MIN (ub, max_arg_words - cum->words - alignment);
9128 for (i = 0; i < ub; i++)
9130 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9131 gen_rtx_REG (DImode, gpr_reg_base),
9137 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9142 /* If the argument is larger than a word, then we know precisely
9143 which registers we must use. */
9157 /* Structures 5 to 8 bytes in size are passed in the general
9158 registers in the same manner as other non floating-point
9159 objects. The data is right-justified and zero-extended
9160 to 64 bits. This is opposite to the normal justification
9161 used on big endian targets and requires special treatment.
9162 We now define BLOCK_REG_PADDING to pad these objects. */
9163 if (mode == BLKmode)
9165 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9166 gen_rtx_REG (DImode, gpr_reg_base),
9168 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
9173 /* We have a single word (32 bits). A simple computation
9174 will get us the register #s we need. */
9175 gpr_reg_base = 26 - cum->words;
9176 fpr_reg_base = 32 + 2 * cum->words;
9180 /* Determine if the argument needs to be passed in both general and
9181 floating point registers. */
9182 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9183 /* If we are doing soft-float with portable runtime, then there
9184 is no need to worry about FP regs. */
9185 && !TARGET_SOFT_FLOAT
9186 /* The parameter must be some kind of float, else we can just
9187 pass it in integer registers. */
9188 && FLOAT_MODE_P (mode)
9189 /* The target function must not have a prototype. */
9190 && cum->nargs_prototype <= 0
9191 /* libcalls do not need to pass items in both FP and general
9193 && type != NULL_TREE
9194 /* All this hair applies to "outgoing" args only. This includes
9195 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9197 /* Also pass outgoing floating arguments in both registers in indirect
9198 calls with the 32 bit ABI and the HP assembler since there is no
9199 way to the specify argument locations in static functions. */
9204 && FLOAT_MODE_P (mode)))
9210 gen_rtx_EXPR_LIST (VOIDmode,
9211 gen_rtx_REG (mode, fpr_reg_base),
9213 gen_rtx_EXPR_LIST (VOIDmode,
9214 gen_rtx_REG (mode, gpr_reg_base),
9219 /* See if we should pass this parameter in a general register. */
9220 if (TARGET_SOFT_FLOAT
9221 /* Indirect calls in the normal 32bit ABI require all arguments
9222 to be passed in general registers. */
9223 || (!TARGET_PORTABLE_RUNTIME
9227 /* If the parameter is not a floating point parameter, then
9228 it belongs in GPRs. */
9229 || !FLOAT_MODE_P (mode))
9230 retval = gen_rtx_REG (mode, gpr_reg_base);
9232 retval = gen_rtx_REG (mode, fpr_reg_base);
9238 /* If this arg would be passed totally in registers or totally on the stack,
9239 then this routine should return zero. It is currently called only for
9240 the 64-bit target. */
9242 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9243 tree type, int named ATTRIBUTE_UNUSED)
9245 unsigned int max_arg_words = 8;
9246 unsigned int offset = 0;
9248 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9251 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9252 /* Arg fits fully into registers. */
9254 else if (cum->words + offset >= max_arg_words)
9255 /* Arg fully on the stack. */
9259 return max_arg_words - cum->words - offset;
9263 /* Return 1 if this is a comparison operator. This allows the use of
9264 MATCH_OPERATOR to recognize all the branch insns. */
9267 cmpib_comparison_operator (rtx op, enum machine_mode mode)
9269 return ((mode == VOIDmode || GET_MODE (op) == mode)
9270 && (GET_CODE (op) == EQ
9271 || GET_CODE (op) == NE
9272 || GET_CODE (op) == GT
9273 || GET_CODE (op) == GTU
9274 || GET_CODE (op) == GE
9275 || GET_CODE (op) == LT
9276 || GET_CODE (op) == LE
9277 || GET_CODE (op) == LEU));
9280 /* Return a string to output before text in the current function.
9282 This function is only used with SOM. Because we don't support
9283 named subspaces, we can only create a new subspace or switch back
9284 to the default text subspace. */
9286 som_text_section_asm_op (void)
9293 if (cfun && !cfun->machine->in_nsubspa)
9295 /* We only want to emit a .nsubspa directive once at the
9296 start of the function. */
9297 cfun->machine->in_nsubspa = 1;
9299 /* Create a new subspace for the text. This provides
9300 better stub placement and one-only functions. */
9302 && DECL_ONE_ONLY (cfun->decl)
9303 && !DECL_WEAK (cfun->decl))
9305 "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT";
9307 return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$";
9311 /* There isn't a current function or the body of the current
9312 function has been completed. So, we are changing to the
9313 text section to output debugging information. Do this in
9314 the default text section. We need to forget that we are
9315 in the text section so that the function text_section in
9316 varasm.c will call us the next time around. */
9321 return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$";
9324 /* On hpux10, the linker will give an error if we have a reference
9325 in the read-only data section to a symbol defined in a shared
9326 library. Therefore, expressions that might require a reloc can
9327 not be placed in the read-only data section. */
9330 pa_select_section (tree exp, int reloc,
9331 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9333 if (TREE_CODE (exp) == VAR_DECL
9334 && TREE_READONLY (exp)
9335 && !TREE_THIS_VOLATILE (exp)
9336 && DECL_INITIAL (exp)
9337 && (DECL_INITIAL (exp) == error_mark_node
9338 || TREE_CONSTANT (DECL_INITIAL (exp)))
9342 && DECL_ONE_ONLY (exp)
9343 && !DECL_WEAK (exp))
9344 som_one_only_readonly_data_section ();
9346 readonly_data_section ();
9348 else if (CONSTANT_CLASS_P (exp) && !reloc)
9349 readonly_data_section ();
9351 && TREE_CODE (exp) == VAR_DECL
9352 && DECL_ONE_ONLY (exp)
9354 && DECL_INITIAL (exp))
9355 som_one_only_data_section ();
9361 pa_globalize_label (FILE *stream, const char *name)
9363 /* We only handle DATA objects here, functions are globalized in
9364 ASM_DECLARE_FUNCTION_NAME. */
9365 if (! FUNCTION_NAME_P (name))
9367 fputs ("\t.EXPORT ", stream);
9368 assemble_name (stream, name);
9369 fputs (",DATA\n", stream);
9373 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9376 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9377 int incoming ATTRIBUTE_UNUSED)
9379 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9382 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9385 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9387 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9388 PA64 ABI says that objects larger than 128 bits are returned in memory.
9389 Note, int_size_in_bytes can return -1 if the size of the object is
9390 variable or larger than the maximum value that can be expressed as
9391 a HOST_WIDE_INT. It can also return zero for an empty type. The
9392 simplest way to handle variable and empty types is to pass them in
9393 memory. This avoids problems in defining the boundaries of argument
9394 slots, allocating registers, etc. */
9395 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9396 || int_size_in_bytes (type) <= 0);