1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "hard-reg-set.h"
27 #include "insn-config.h"
28 #include "conditions.h"
29 #include "insn-flags.h"
31 #include "insn-attr.h"
38 /* Save the operands last given to a compare for use when we
39 generate a scc or bcc insn. */
41 rtx hppa_compare_op0, hppa_compare_op1;
42 enum cmp_type hppa_branch_type;
44 rtx hppa_save_pic_table_rtx;
46 /* Set by the FUNCTION_PROFILER macro. */
47 int hp_profile_labelno;
49 static rtx find_addr_reg ();
51 /* Return non-zero only if OP is a register of mode MODE,
54 reg_or_0_operand (op, mode)
56 enum machine_mode mode;
58 return (op == CONST0_RTX (mode) || register_operand (op, mode));
61 /* Return non-zero if OP is suitable for use in a call to a named
64 (???) For 2.5 try to eliminate either call_operand_address or
65 function_label_operand, they perform very similar functions. */
67 call_operand_address (op, mode)
69 enum machine_mode mode;
71 return (CONSTANT_P (op) && ! TARGET_LONG_CALLS);
74 /* Return 1 if X contains a symbolic expression. We know these
75 expressions will have one of a few well defined forms, so
76 we need only check those forms. */
78 symbolic_expression_p (x)
82 /* Strip off any HIGH. */
83 if (GET_CODE (x) == HIGH)
86 return (symbolic_operand (x, VOIDmode));
90 symbolic_operand (op, mode)
92 enum machine_mode mode;
94 switch (GET_CODE (op))
101 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
102 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
103 && GET_CODE (XEXP (op, 1)) == CONST_INT);
109 /* Return truth value of statement that OP is a symbolic memory
110 operand of mode MODE. */
113 symbolic_memory_operand (op, mode)
115 enum machine_mode mode;
117 if (GET_CODE (op) == SUBREG)
118 op = SUBREG_REG (op);
119 if (GET_CODE (op) != MEM)
122 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
123 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
126 /* Return 1 if the operand is either a register or a memory operand that is
130 reg_or_nonsymb_mem_operand (op, mode)
132 enum machine_mode mode;
134 if (register_operand (op, mode))
137 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
143 /* Return 1 if the operand is either a register, zero, or a memory operand
144 that is not symbolic. */
147 reg_or_0_or_nonsymb_mem_operand (op, mode)
149 enum machine_mode mode;
151 if (register_operand (op, mode))
154 if (op == CONST0_RTX (mode))
157 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
163 /* Accept any constant that can be moved in one instructions into a
166 cint_ok_for_move (intval)
169 /* OK if ldo, ldil, or zdepi, can be used. */
170 return (VAL_14_BITS_P (intval) || (intval & 0x7ff) == 0
171 || zdepi_cint_p (intval));
174 /* Accept anything that can be moved in one instruction into a general
177 move_operand (op, mode)
179 enum machine_mode mode;
181 if (register_operand (op, mode))
184 if (GET_CODE (op) == CONST_INT)
185 return cint_ok_for_move (INTVAL (op));
187 if (GET_MODE (op) != mode)
189 if (GET_CODE (op) == SUBREG)
190 op = SUBREG_REG (op);
191 if (GET_CODE (op) != MEM)
195 if (GET_CODE (op) == LO_SUM)
196 return (register_operand (XEXP (op, 0), Pmode)
197 && CONSTANT_P (XEXP (op, 1)));
198 return memory_address_p (mode, op);
201 /* Accept REG and any CONST_INT that can be moved in one instruction into a
204 reg_or_cint_move_operand (op, mode)
206 enum machine_mode mode;
208 if (register_operand (op, mode))
211 if (GET_CODE (op) == CONST_INT)
212 return cint_ok_for_move (INTVAL (op));
218 pic_operand (op, mode)
220 enum machine_mode mode;
222 return flag_pic && GET_CODE (op) == LABEL_REF;
226 fp_reg_operand (op, mode)
228 enum machine_mode mode;
230 return reg_renumber && FP_REG_P (op);
234 extern int current_function_uses_pic_offset_table;
235 extern rtx force_reg (), validize_mem ();
237 /* The rtx for the global offset table which is a special form
238 that *is* a position independent symbolic constant. */
241 /* Ensure that we are not using patterns that are not OK with PIC. */
247 extern rtx recog_operand[];
251 if (GET_CODE (recog_operand[i]) == SYMBOL_REF
252 || (GET_CODE (recog_operand[i]) == CONST
253 && ! rtx_equal_p (pic_pc_rtx, recog_operand[i])))
261 /* Return truth value of whether OP can be used as an operand in a
262 three operand arithmetic insn that accepts registers of mode MODE
263 or 14-bit signed integers. */
265 arith_operand (op, mode)
267 enum machine_mode mode;
269 return (register_operand (op, mode)
270 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
273 /* Return truth value of whether OP can be used as an operand in a
274 three operand arithmetic insn that accepts registers of mode MODE
275 or 11-bit signed integers. */
277 arith11_operand (op, mode)
279 enum machine_mode mode;
281 return (register_operand (op, mode)
282 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
285 /* A constant integer suitable for use in a PRE_MODIFY memory
288 pre_cint_operand (op, mode)
290 enum machine_mode mode;
292 return (GET_CODE (op) == CONST_INT
293 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
296 /* A constant integer suitable for use in a POST_MODIFY memory
299 post_cint_operand (op, mode)
301 enum machine_mode mode;
303 return (GET_CODE (op) == CONST_INT
304 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
308 arith_double_operand (op, mode)
310 enum machine_mode mode;
312 return (register_operand (op, mode)
313 || (GET_CODE (op) == CONST_DOUBLE
314 && GET_MODE (op) == mode
315 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
316 && (CONST_DOUBLE_HIGH (op) >= 0
317 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
320 /* Return truth value of whether OP is a integer which fits the
321 range constraining immediate operands in three-address insns. */
324 int5_operand (op, mode)
326 enum machine_mode mode;
328 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
332 uint5_operand (op, mode)
334 enum machine_mode mode;
336 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
341 int11_operand (op, mode)
343 enum machine_mode mode;
345 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
349 arith5_operand (op, mode)
351 enum machine_mode mode;
353 return register_operand (op, mode) || int5_operand (op, mode);
356 /* True iff zdepi can be used to generate this CONST_INT. */
361 unsigned lsb_mask, t;
363 /* This might not be obvious, but it's at least fast.
364 This function is critcal; we don't have the time loops would take. */
366 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
367 /* Return true iff t is a power of two. */
368 return ((t & (t - 1)) == 0);
371 /* True iff depi or extru can be used to compute (reg & mask). */
377 mask += mask & -mask;
378 return (mask & (mask - 1)) == 0;
381 /* True iff depi or extru can be used to compute (reg & OP). */
383 and_operand (op, mode)
385 enum machine_mode mode;
387 return (register_operand (op, mode)
388 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
391 /* True iff depi can be used to compute (reg | MASK). */
396 mask += mask & -mask;
397 return (mask & (mask - 1)) == 0;
400 /* True iff depi can be used to compute (reg | OP). */
402 ior_operand (op, mode)
404 enum machine_mode mode;
406 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
410 lhs_lshift_operand (op, mode)
412 enum machine_mode mode;
414 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
417 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
418 Such values can be the left hand side x in (x << r), using the zvdepi
421 lhs_lshift_cint_operand (op, mode)
423 enum machine_mode mode;
426 if (GET_CODE (op) != CONST_INT)
428 x = INTVAL (op) >> 4;
429 return (x & (x + 1)) == 0;
433 arith32_operand (op, mode)
435 enum machine_mode mode;
437 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
441 pc_or_label_operand (op, mode)
443 enum machine_mode mode;
445 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
448 /* Legitimize PIC addresses. If the address is already
449 position-independent, we return ORIG. Newly generated
450 position-independent addresses go to REG. If we need more
451 than one register, we lose. */
454 legitimize_pic_address (orig, mode, reg)
456 enum machine_mode mode;
460 if (GET_CODE (orig) == SYMBOL_REF)
467 emit_insn (gen_rtx (SET, VOIDmode, reg,
468 gen_rtx (HIGH, Pmode, orig)));
469 emit_insn (gen_rtx (SET, VOIDmode, reg,
470 gen_rtx (LO_SUM, Pmode, reg, orig)));
473 pic_ref = gen_rtx (MEM, Pmode,
474 gen_rtx (PLUS, Pmode,
475 pic_offset_table_rtx, orig));
476 current_function_uses_pic_offset_table = 1;
477 RTX_UNCHANGING_P (pic_ref) = 1;
478 emit_move_insn (reg, pic_ref);
481 else if (GET_CODE (orig) == CONST)
485 if (GET_CODE (XEXP (orig, 0)) == PLUS
486 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
492 if (GET_CODE (XEXP (orig, 0)) == PLUS)
494 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
495 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
496 base == reg ? 0 : reg);
499 if (GET_CODE (orig) == CONST_INT)
501 if (INT_14_BITS (orig))
502 return plus_constant_for_output (base, INTVAL (orig));
503 orig = force_reg (Pmode, orig);
505 pic_ref = gen_rtx (PLUS, Pmode, base, orig);
506 /* Likewise, should we set special REG_NOTEs here? */
511 /* Set up PIC-specific rtl. This should not cause any insns
519 /* Emit special PIC prologues and epilogues. */
524 if (hppa_save_pic_table_rtx)
526 emit_insn_after (gen_rtx (SET, VOIDmode,
527 hppa_save_pic_table_rtx,
528 gen_rtx (REG, Pmode, 19)),
530 /* Need to emit this whether or not we obey regdecls,
531 since setjmp/longjmp can cause life info to screw up. */
532 hppa_save_pic_table_rtx = 0;
534 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
538 /* Try machine-dependent ways of modifying an illegitimate address
539 to be legitimate. If we find one, return the new, valid address.
540 This macro is used in only one place: `memory_address' in explow.c.
542 OLDX is the address as it was before break_out_memory_refs was called.
543 In some cases it is useful to look at this to decide what needs to be done.
545 MODE and WIN are passed so that this macro can use
546 GO_IF_LEGITIMATE_ADDRESS.
548 It is always safe for this macro to do nothing. It exists to recognize
549 opportunities to optimize the output.
551 For the PA, transform:
553 memory(X + <large int>)
557 if (<large int> & mask) >= 16
558 Y = (<large int> & ~mask) + mask + 1 Round up.
560 Y = (<large int> & ~mask) Round down.
562 memory (Z + (<large int> - Y));
564 This is for CSE to find several similar references, and only use one Z.
566 X can either be a SYMBOL_REF or REG, but because combine can not
567 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
568 D will not fit in 14 bits.
570 MODE_FLOAT references allow displacements which fit in 5 bits, so use
573 MODE_INT references allow displacements which fit in 14 bits, so use
576 This relies on the fact that most mode MODE_FLOAT references will use FP
577 registers and most mode MODE_INT references will use integer registers.
578 (In the rare case of an FP register used in an integer MODE, we depend
579 on secondary reloads to clean things up.)
582 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
583 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
584 adressing modes to be used).
586 Put X and Z into registers. Then put the entire expression into
590 hppa_legitimize_address (x, oldx, mode)
592 enum machine_mode mode;
597 /* Strip off CONST. */
598 if (GET_CODE (x) == CONST)
601 if (GET_CODE (x) == PLUS
602 && GET_CODE (XEXP (x, 1)) == CONST_INT
603 && (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
604 || GET_CODE (XEXP (x, 0)) == REG))
606 rtx int_part, ptr_reg;
608 int offset = INTVAL (XEXP (x, 1));
609 int mask = GET_MODE_CLASS (mode) == MODE_FLOAT ? 0x1f : 0x3fff;
611 /* Choose which way to round the offset. Round up if we
612 are >= halfway to the next boundary. */
613 if ((offset & mask) >= ((mask + 1) / 2))
614 newoffset = (offset & ~ mask) + mask + 1;
616 newoffset = (offset & ~ mask);
618 /* If the newoffset will not fit in 14 bits (ldo), then
619 handling this would take 4 or 5 instructions (2 to load
620 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
621 add the new offset and the SYMBOL_REF.) Combine can
622 not handle 4->2 or 5->2 combinations, so do not create
624 if (! VAL_14_BITS_P (newoffset)
625 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
627 rtx const_part = gen_rtx (CONST, VOIDmode,
628 gen_rtx (PLUS, Pmode,
630 GEN_INT (newoffset)));
633 gen_rtx (HIGH, Pmode, const_part));
636 gen_rtx (LO_SUM, Pmode,
637 tmp_reg, const_part));
641 if (! VAL_14_BITS_P (newoffset))
642 int_part = force_reg (Pmode, GEN_INT (newoffset));
644 int_part = GEN_INT (newoffset);
646 ptr_reg = force_reg (Pmode,
647 gen_rtx (PLUS, Pmode,
648 force_reg (Pmode, XEXP (x, 0)),
651 return plus_constant (ptr_reg, offset - newoffset);
653 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
654 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
655 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
657 int val = INTVAL (XEXP (XEXP (x, 0), 1));
659 reg1 = force_reg (Pmode, force_operand (XEXP (x, 1), 0));
660 reg2 = force_reg (Pmode,
661 force_operand (XEXP (XEXP (x, 0), 0), 0));
662 return force_reg (Pmode,
663 gen_rtx (PLUS, Pmode,
664 gen_rtx (MULT, Pmode, reg2,
669 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
674 /* For the HPPA, REG and REG+CONST is cost 0
675 and addresses involving symbolic constants are cost 2.
677 PIC addresses are very expensive.
679 It is no coincidence that this has the same structure
680 as GO_IF_LEGITIMATE_ADDRESS. */
682 hppa_address_cost (X)
685 if (GET_CODE (X) == PLUS)
687 else if (GET_CODE (X) == LO_SUM)
689 else if (GET_CODE (X) == HIGH)
694 /* Emit insns to move operands[1] into operands[0].
696 Return 1 if we have written out everything that needs to be done to
697 do the move. Otherwise, return 0 and the caller will emit the move
701 emit_move_sequence (operands, mode, scratch_reg)
703 enum machine_mode mode;
706 register rtx operand0 = operands[0];
707 register rtx operand1 = operands[1];
709 /* Handle secondary reloads for loads/stores of FP registers from
710 REG+D addresses where D does not fit in 5 bits. */
711 if (fp_reg_operand (operand0, mode)
712 && GET_CODE (operand1) == MEM
713 /* Using DFmode forces only short displacements be be
714 recognized as valid in reg+d addressing modes. */
715 && ! memory_address_p (DFmode, XEXP (operand1, 0))
718 emit_move_insn (scratch_reg, XEXP (operand1 , 0));
719 emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (MEM, mode,
723 else if (fp_reg_operand (operand1, mode)
724 && GET_CODE (operand0) == MEM
725 /* Using DFmode forces only short displacements be be
726 recognized as valid in reg+d addressing modes. */
727 && ! memory_address_p (DFmode, XEXP (operand0, 0))
730 emit_move_insn (scratch_reg, XEXP (operand0 , 0));
731 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (MEM, mode, scratch_reg),
735 /* Handle secondary reloads for loads of FP registers from constant
736 expressions by forcing the constant into memory.
738 use scratch_reg to hold the address of the memory location.
740 ??? The proper fix is to change PREFERRED_RELOAD_CLASS to return
741 NO_REGS when presented with a const_int and an register class
742 containing only FP registers. Doing so unfortunately creates
743 more problems than it solves. Fix this for 2.5. */
744 else if (fp_reg_operand (operand0, mode)
745 && CONSTANT_P (operand1)
750 /* Force the constant into memory and put the address of the
751 memory location into scratch_reg. */
752 xoperands[0] = scratch_reg;
753 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
754 emit_move_sequence (xoperands, mode, 0);
756 /* Now load the destination register. */
757 emit_insn (gen_rtx (SET, mode, operand0,
758 gen_rtx (MEM, mode, scratch_reg)));
761 /* Handle secondary reloads for SAR. These occur when trying to load
762 the SAR from memory or from a FP register. */
763 else if (GET_CODE (operand0) == REG
764 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
765 && (GET_CODE (operand1) == MEM
766 || (GET_CODE (operand1) == REG
767 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
770 emit_move_insn (scratch_reg, operand1);
771 emit_move_insn (operand0, scratch_reg);
774 /* Handle most common case: storing into a register. */
775 else if (register_operand (operand0, mode))
777 if (register_operand (operand1, mode)
778 || (GET_CODE (operand1) == CONST_INT && INT_14_BITS (operand1))
779 || (operand1 == CONST0_RTX (mode))
780 || (GET_CODE (operand1) == HIGH
781 && !symbolic_operand (XEXP (operand1, 0)))
782 /* Only `general_operands' can come here, so MEM is ok. */
783 || GET_CODE (operand1) == MEM)
785 /* Run this case quickly. */
786 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
790 else if (GET_CODE (operand0) == MEM)
792 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
794 /* Run this case quickly. */
795 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
798 if (! reload_in_progress)
800 operands[0] = validize_mem (operand0);
801 operands[1] = operand1 = force_reg (mode, operand1);
805 /* Simplify the source if we need to. */
806 if (GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)
807 || (GET_CODE (operand1) == HIGH
808 && symbolic_operand (XEXP (operand1, 0), mode)
813 if (GET_CODE (operand1) == HIGH)
816 operand1 = XEXP (operand1, 0);
818 if (symbolic_operand (operand1, mode))
822 rtx temp = reload_in_progress ? operand0 : gen_reg_rtx (Pmode);
823 operands[1] = legitimize_pic_address (operand1, mode, temp);
824 emit_insn (gen_rtx (SET, VOIDmode, operand0, operands[1]));
826 /* On the HPPA, references to data space are supposed to */
827 /* use dp, register 27, but showing it in the RTL inhibits various
828 cse and loop optimizations. */
833 if (reload_in_progress)
834 temp = scratch_reg ? scratch_reg : operand0;
836 temp = gen_reg_rtx (mode);
839 set = gen_rtx (SET, mode, operand0, temp);
841 set = gen_rtx (SET, VOIDmode,
843 gen_rtx (LO_SUM, mode, temp, operand1));
845 emit_insn (gen_rtx (SET, VOIDmode,
847 gen_rtx (HIGH, mode, operand1)));
848 if (function_label_operand (operand1, mode))
850 rtx temp = reload_in_progress ? scratch_reg
851 : gen_reg_rtx (mode);
854 emit_insn (gen_rtx (PARALLEL, VOIDmode,
857 gen_rtx (CLOBBER, VOIDmode,
866 else if (GET_CODE (operand1) != CONST_INT
867 || (! INT_14_BITS (operand1)
868 && ! ((INTVAL (operand1) & 0x7ff) == 0)
869 && ! zdepi_cint_p (INTVAL (operand1))))
871 rtx temp = reload_in_progress ? operand0 : gen_reg_rtx (mode);
872 emit_insn (gen_rtx (SET, VOIDmode, temp,
873 gen_rtx (HIGH, mode, operand1)));
874 operands[1] = gen_rtx (LO_SUM, mode, temp, operand1);
877 /* Now have insn-emit do whatever it normally does. */
881 /* Does operand (which is a symbolic_operand) live in text space? If
882 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
885 read_only_operand (operand)
888 if (GET_CODE (operand) == CONST)
889 operand = XEXP (XEXP (operand, 0), 0);
890 if (GET_CODE (operand) == SYMBOL_REF)
891 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
896 /* Return the best assembler insn template
897 for moving operands[1] into operands[0] as a fullword. */
899 singlemove_string (operands)
902 if (GET_CODE (operands[0]) == MEM)
904 else if (GET_CODE (operands[1]) == MEM)
906 else if (GET_CODE (operands[1]) == CONST_DOUBLE
907 && GET_MODE (operands[1]) == SFmode)
910 union real_extract u;
911 union float_extract { float f; int i; } v;
913 bcopy (&CONST_DOUBLE_LOW (operands[1]), &u, sizeof u);
914 v.f = REAL_VALUE_TRUNCATE (SFmode, u.d);
917 operands[1] = gen_rtx (CONST_INT, VOIDmode, i);
919 /* See if we can handle this constant in a single instruction. */
920 if (cint_ok_for_move (INTVAL (operands[1])))
922 int intval = INTVAL (operands[1]);
926 else if (VAL_14_BITS_P (intval))
928 else if ((intval & 0x7ff) == 0)
929 return "ldil L'%1,%0";
930 else if (zdepi_cint_p (intval))
931 return "zdepi %Z1,%0";
934 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
937 else if (GET_CODE (operands[1]) == CONST_INT)
939 /* See if we can handle this in a single instruction. */
940 if (cint_ok_for_move (INTVAL (operands[1])))
942 int intval = INTVAL (operands[1]);
946 else if (VAL_14_BITS_P (intval))
948 else if ((intval & 0x7ff) == 0)
949 return "ldil L'%1,%0";
950 else if (zdepi_cint_p (intval))
951 return "zdepi %Z1,%0";
954 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
960 /* Compute position (in OP[1]) and width (in OP[2])
961 useful for copying IMM to a register using the zdepi
962 instructions. Store the immediate value to insert in OP[0]. */
964 compute_zdepi_operands (imm, op)
970 /* Find the least significant set bit in IMM. */
971 for (lsb = 0; lsb < 32; lsb++)
978 /* Choose variants based on *sign* of the 5-bit field. */
979 if ((imm & 0x10) == 0)
980 len = (lsb <= 28) ? 4 : 32 - lsb;
983 /* Find the width of the bitstring in IMM. */
984 for (len = 5; len < 32; len++)
986 if ((imm & (1 << len)) == 0)
990 /* Sign extend IMM as a 5-bit value. */
991 imm = (imm & 0xf) - 0x10;
999 /* Output assembler code to perform a doubleword move insn
1000 with operands OPERANDS. */
1003 output_move_double (operands)
1006 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1008 rtx addreg0 = 0, addreg1 = 0;
1010 /* First classify both operands. */
1012 if (REG_P (operands[0]))
1014 else if (offsettable_memref_p (operands[0]))
1016 else if (GET_CODE (operands[0]) == MEM)
1021 if (REG_P (operands[1]))
1023 else if (CONSTANT_P (operands[1]))
1025 else if (offsettable_memref_p (operands[1]))
1027 else if (GET_CODE (operands[1]) == MEM)
1032 /* Check for the cases that the operand constraints are not
1033 supposed to allow to happen. Abort if we get one,
1034 because generating code for these cases is painful. */
1036 if (optype0 != REGOP && optype1 != REGOP)
1039 /* Handle auto decrementing and incrementing loads and stores
1040 specifically, since the structure of the function doesn't work
1041 for them without major modification. Do it better when we learn
1042 this port about the general inc/dec addressing of PA.
1043 (This was written by tege. Chide him if it doesn't work.) */
1045 if (optype0 == MEMOP)
1047 /* We have to output the address syntax ourselves, since print_operand
1048 doesn't deal with the addresses we want to use. Fix this later. */
1050 rtx addr = XEXP (operands[0], 0);
1051 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1053 rtx high_reg = gen_rtx (SUBREG, SImode, operands[1], 0);
1055 operands[0] = XEXP (addr, 0);
1056 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1059 if (!reg_overlap_mentioned_p (high_reg, addr))
1061 /* No overlap between high target register and address
1062 register. (We do this in a non-obvious way to
1063 save a register file writeback) */
1064 if (GET_CODE (addr) == POST_INC)
1065 return "stws,ma %1,8(0,%0)\n\tstw %R1,-4(0,%0)";
1066 return "stws,ma %1,-8(0,%0)\n\tstw %R1,12(0,%0)";
1071 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1073 rtx high_reg = gen_rtx (SUBREG, SImode, operands[1], 0);
1075 operands[0] = XEXP (addr, 0);
1076 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1079 if (!reg_overlap_mentioned_p (high_reg, addr))
1081 /* No overlap between high target register and address
1082 register. (We do this in a non-obvious way to
1083 save a register file writeback) */
1084 if (GET_CODE (addr) == PRE_INC)
1085 return "stws,mb %1,8(0,%0)\n\tstw %R1,4(0,%0)";
1086 return "stws,mb %1,-8(0,%0)\n\tstw %R1,4(0,%0)";
1092 if (optype1 == MEMOP)
1094 /* We have to output the address syntax ourselves, since print_operand
1095 doesn't deal with the addresses we want to use. Fix this later. */
1097 rtx addr = XEXP (operands[1], 0);
1098 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1100 rtx high_reg = gen_rtx (SUBREG, SImode, operands[0], 0);
1102 operands[1] = XEXP (addr, 0);
1103 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1106 if (!reg_overlap_mentioned_p (high_reg, addr))
1108 /* No overlap between high target register and address
1109 register. (We do this in a non-obvious way to
1110 save a register file writeback) */
1111 if (GET_CODE (addr) == POST_INC)
1112 return "ldws,ma 8(0,%1),%0\n\tldw -4(0,%1),%R0";
1113 return "ldws,ma -8(0,%1),%0\n\tldw 12(0,%1),%R0";
1117 /* This is an undefined situation. We should load into the
1118 address register *and* update that register. Probably
1119 we don't need to handle this at all. */
1120 if (GET_CODE (addr) == POST_INC)
1121 return "ldw 4(0,%1),%R0\n\tldws,ma 8(0,%1),%0";
1122 return "ldw 4(0,%1),%R0\n\tldws,ma -8(0,%1),%0";
1125 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1127 rtx high_reg = gen_rtx (SUBREG, SImode, operands[0], 0);
1129 operands[1] = XEXP (addr, 0);
1130 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1133 if (!reg_overlap_mentioned_p (high_reg, addr))
1135 /* No overlap between high target register and address
1136 register. (We do this in a non-obvious way to
1137 save a register file writeback) */
1138 if (GET_CODE (addr) == PRE_INC)
1139 return "ldws,mb 8(0,%1),%0\n\tldw 4(0,%1),%R0";
1140 return "ldws,mb -8(0,%1),%0\n\tldw 4(0,%1),%R0";
1144 /* This is an undefined situation. We should load into the
1145 address register *and* update that register. Probably
1146 we don't need to handle this at all. */
1147 if (GET_CODE (addr) == PRE_INC)
1148 return "ldw 12(0,%1),%R0\n\tldws,mb 8(0,%1),%0";
1149 return "ldw -4(0,%1),%R0\n\tldws,mb -8(0,%1),%0";
1154 /* If an operand is an unoffsettable memory ref, find a register
1155 we can increment temporarily to make it refer to the second word. */
1157 if (optype0 == MEMOP)
1158 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1160 if (optype1 == MEMOP)
1161 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1163 /* Ok, we can do one word at a time.
1164 Normally we do the low-numbered word first.
1166 In either case, set up in LATEHALF the operands to use
1167 for the high-numbered word and in some cases alter the
1168 operands in OPERANDS to be suitable for the low-numbered word. */
1170 if (optype0 == REGOP)
1171 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1172 else if (optype0 == OFFSOP)
1173 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1175 latehalf[0] = operands[0];
1177 if (optype1 == REGOP)
1178 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1179 else if (optype1 == OFFSOP)
1180 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1181 else if (optype1 == CNSTOP)
1182 split_double (operands[1], &operands[1], &latehalf[1]);
1184 latehalf[1] = operands[1];
1186 /* If the first move would clobber the source of the second one,
1187 do them in the other order.
1189 RMS says "This happens only for registers;
1190 such overlap can't happen in memory unless the user explicitly
1191 sets it up, and that is an undefined circumstance."
1193 but it happens on the HP-PA when loading parameter registers,
1194 so I am going to define that circumstance, and make it work
1197 if (optype0 == REGOP && (optype1 == MEMOP || optype1 == OFFSOP)
1198 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
1200 /* XXX THIS PROBABLY DOESN'T WORK. */
1201 /* Do the late half first. */
1203 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1204 output_asm_insn (singlemove_string (latehalf), latehalf);
1206 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1208 return singlemove_string (operands);
1211 if (optype0 == REGOP && optype1 == REGOP
1212 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1214 output_asm_insn (singlemove_string (latehalf), latehalf);
1215 return singlemove_string (operands);
1218 /* Normal case: do the two words, low-numbered first. */
1220 output_asm_insn (singlemove_string (operands), operands);
1222 /* Make any unoffsettable addresses point at high-numbered word. */
1224 output_asm_insn ("ldo 4(%0),%0", &addreg0);
1226 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1229 output_asm_insn (singlemove_string (latehalf), latehalf);
1231 /* Undo the adds we just did. */
1233 output_asm_insn ("ldo -4(%0),%0", &addreg0);
1235 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1241 output_fp_move_double (operands)
1244 if (FP_REG_P (operands[0]))
1246 if (FP_REG_P (operands[1])
1247 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1248 output_asm_insn ("fcpy,dbl %r1,%0", operands);
1250 output_asm_insn ("fldds%F1 %1,%0", operands);
1252 else if (FP_REG_P (operands[1]))
1254 output_asm_insn ("fstds%F0 %1,%0", operands);
1256 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1258 if (GET_CODE (operands[0]) == REG)
1261 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1262 xoperands[0] = operands[0];
1263 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
1265 /* This is a pain. You have to be prepared to deal with an
1266 arbritary address here including pre/post increment/decrement.
1268 so avoid this in the MD. */
1276 /* Return a REG that occurs in ADDR with coefficient 1.
1277 ADDR can be effectively incremented by incrementing REG. */
1280 find_addr_reg (addr)
1283 while (GET_CODE (addr) == PLUS)
1285 if (GET_CODE (XEXP (addr, 0)) == REG)
1286 addr = XEXP (addr, 0);
1287 else if (GET_CODE (XEXP (addr, 1)) == REG)
1288 addr = XEXP (addr, 1);
1289 else if (CONSTANT_P (XEXP (addr, 0)))
1290 addr = XEXP (addr, 1);
1291 else if (CONSTANT_P (XEXP (addr, 1)))
1292 addr = XEXP (addr, 0);
1296 if (GET_CODE (addr) == REG)
1301 /* Emit code to perform a block move.
1303 Restriction: If the length argument is non-constant, alignment
1306 OPERANDS[0] is the destination pointer as a REG, clobbered.
1307 OPERANDS[1] is the source pointer as a REG, clobbered.
1309 OPERANDS[2] is a register for temporary storage.
1310 OPERANDS[4] is the size as a CONST_INT
1312 OPERANDS[2] is a REG which will contain the size, clobbered.
1313 OPERANDS[3] is a register for temporary storage.
1314 OPERANDS[5] is the alignment safe to use, as a CONST_INT. */
1317 output_block_move (operands, size_is_constant)
1319 int size_is_constant;
1321 int align = INTVAL (operands[5]);
1322 unsigned long n_bytes;
1324 /* We can't move more than four bytes at a time because the PA
1325 has no longer integer move insns. (Could use fp mem ops?) */
1329 if (size_is_constant)
1331 unsigned long n_items;
1332 unsigned long offset;
1335 n_bytes = INTVAL (operands[4]);
1341 /* Don't unroll too large blocks. */
1343 goto copy_with_loop;
1345 /* Read and store using two registers, and hide latency
1346 by deferring the stores until three instructions after
1347 the corresponding load. The last load insn will read
1348 the entire word were the last bytes are, possibly past
1349 the end of the source block, but since loads are aligned,
1350 this is harmless. */
1352 output_asm_insn ("ldws,ma 4(0,%1),%2", operands);
1354 for (offset = 4; offset < n_bytes; offset += 4)
1356 output_asm_insn ("ldws,ma 4(0,%1),%3", operands);
1357 output_asm_insn ("stws,ma %2,4(0,%0)", operands);
1360 operands[2] = operands[3];
1363 if (n_bytes % 4 == 0)
1364 /* Store the last word. */
1365 output_asm_insn ("stw %2,0(0,%0)", operands);
1368 /* Store the last, partial word. */
1369 operands[4] = gen_rtx (CONST_INT, VOIDmode, n_bytes % 4);
1370 output_asm_insn ("stbys,e %2,%4(0,%0)", operands);
1375 if (align >= 2 && n_bytes >= 2)
1377 output_asm_insn ("ldhs,ma 2(0,%1),%2", operands);
1379 for (offset = 2; offset + 2 <= n_bytes; offset += 2)
1381 output_asm_insn ("ldhs,ma 2(0,%1),%3", operands);
1382 output_asm_insn ("sths,ma %2,2(0,%0)", operands);
1385 operands[2] = operands[3];
1388 if (n_bytes % 2 != 0)
1389 output_asm_insn ("ldb 0(0,%1),%3", operands);
1391 output_asm_insn ("sths,ma %2,2(0,%0)", operands);
1393 if (n_bytes % 2 != 0)
1394 output_asm_insn ("stb %3,0(0,%0)", operands);
1399 output_asm_insn ("ldbs,ma 1(0,%1),%2", operands);
1401 for (offset = 1; offset + 1 <= n_bytes; offset += 1)
1403 output_asm_insn ("ldbs,ma 1(0,%1),%3", operands);
1404 output_asm_insn ("stbs,ma %2,1(0,%0)", operands);
1407 operands[2] = operands[3];
1410 output_asm_insn ("stb %2,0(0,%0)", operands);
1420 if (size_is_constant)
1422 /* Size is compile-time determined, and also not
1423 very small (such small cases are handled above). */
1424 operands[4] = gen_rtx (CONST_INT, VOIDmode, n_bytes - 4);
1425 output_asm_insn ("ldo %4(0),%2", operands);
1429 /* Decrement counter by 4, and if it becomes negative, jump past the
1430 word copying loop. */
1431 output_asm_insn ("addib,<,n -4,%2,.+16", operands);
1434 /* Copying loop. Note that the first load is in the annulled delay slot
1435 of addib. Is it OK on PA to have a load in a delay slot, i.e. is a
1436 possible page fault stopped in time? */
1437 output_asm_insn ("ldws,ma 4(0,%1),%3", operands);
1438 output_asm_insn ("addib,>= -4,%2,.-4", operands);
1439 output_asm_insn ("stws,ma %3,4(0,%0)", operands);
1441 /* The counter is negative, >= -4. The remaining number of bytes are
1442 determined by the two least significant bits. */
1444 if (size_is_constant)
1446 if (n_bytes % 4 != 0)
1448 /* Read the entire word of the source block tail. */
1449 output_asm_insn ("ldw 0(0,%1),%3", operands);
1450 operands[4] = gen_rtx (CONST_INT, VOIDmode, n_bytes % 4);
1451 output_asm_insn ("stbys,e %3,%4(0,%0)", operands);
1456 /* Add 4 to counter. If it becomes zero, we're done. */
1457 output_asm_insn ("addib,=,n 4,%2,.+16", operands);
1459 /* Read the entire word of the source block tail. (Also this
1460 load is in an annulled delay slot.) */
1461 output_asm_insn ("ldw 0(0,%1),%3", operands);
1463 /* Make %0 point at the first byte after the destination block. */
1464 output_asm_insn ("add %2,%0,%0", operands);
1465 /* Store the leftmost bytes, up to, but not including, the address
1467 output_asm_insn ("stbys,e %3,0(0,%0)", operands);
1472 /* Count the number of insns necessary to handle this block move.
1474 Basic structure is the same as emit_block_move, except that we
1475 count insns rather than emit them. */
1478 compute_movstrsi_length (insn)
1481 rtx pat = PATTERN (insn);
1482 int size_is_constant;
1483 int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
1484 unsigned long n_bytes;
1487 if (GET_CODE (XEXP (XVECEXP (pat, 0, 5), 0)) == CONST_INT)
1489 size_is_constant = 1;
1490 n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
1494 size_is_constant = 0;
1498 /* We can't move more than four bytes at a time because the PA
1499 has no longer integer move insns. (Could use fp mem ops?) */
1503 if (size_is_constant)
1505 unsigned long n_items;
1506 unsigned long offset;
1514 /* Don't unroll too large blocks. */
1516 goto copy_with_loop;
1521 /* Count the unrolled insns. */
1522 for (offset = 4; offset < n_bytes; offset += 4)
1525 /* Count last store or partial store. */
1530 if (align >= 2 && n_bytes >= 2)
1535 /* Unrolled loop. */
1536 for (offset = 2; offset + 2 <= n_bytes; offset += 2)
1539 /* ??? odd load/store */
1540 if (n_bytes % 2 != 0)
1543 /* ??? final store from loop. */
1552 /* The unrolled loop. */
1553 for (offset = 1; offset + 1 <= n_bytes; offset += 1)
1567 /* setup for constant and non-constant case. */
1570 /* The copying loop. */
1573 /* The counter is negative, >= -4. The remaining number of bytes are
1574 determined by the two least significant bits. */
1576 if (size_is_constant)
1578 if (n_bytes % 4 != 0)
1588 output_and (operands)
1591 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
1593 unsigned mask = INTVAL (operands[2]);
1594 int ls0, ls1, ms0, p, len;
1596 for (ls0 = 0; ls0 < 32; ls0++)
1597 if ((mask & (1 << ls0)) == 0)
1600 for (ls1 = ls0; ls1 < 32; ls1++)
1601 if ((mask & (1 << ls1)) != 0)
1604 for (ms0 = ls1; ms0 < 32; ms0++)
1605 if ((mask & (1 << ms0)) == 0)
1618 operands[2] = gen_rtx (CONST_INT, VOIDmode, len);
1619 return "extru %1,31,%2,%0";
1623 /* We could use this `depi' for the case above as well, but `depi'
1624 requires one more register file access than an `extru'. */
1629 operands[2] = gen_rtx (CONST_INT, VOIDmode, p);
1630 operands[3] = gen_rtx (CONST_INT, VOIDmode, len);
1631 return "depi 0,%2,%3,%0";
1635 return "and %1,%2,%0";
1639 output_ior (operands)
1642 unsigned mask = INTVAL (operands[2]);
1643 int bs0, bs1, bs2, p, len;
1645 if (INTVAL (operands[2]) == 0)
1646 return "copy %1,%0";
1648 for (bs0 = 0; bs0 < 32; bs0++)
1649 if ((mask & (1 << bs0)) != 0)
1652 for (bs1 = bs0; bs1 < 32; bs1++)
1653 if ((mask & (1 << bs1)) == 0)
1656 if (bs1 != 32 && ((unsigned) 1 << bs1) <= mask)
1662 operands[2] = gen_rtx (CONST_INT, VOIDmode, p);
1663 operands[3] = gen_rtx (CONST_INT, VOIDmode, len);
1664 return "depi -1,%2,%3,%0";
1667 /* Output an ascii string. */
1668 output_ascii (file, p, size)
1675 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
1677 /* The HP assembler can only take strings of 256 characters at one
1678 time. This is a limitation on input line length, *not* the
1679 length of the string. Sigh. Even worse, it seems that the
1680 restriction is in number of input characters (see \xnn &
1681 \whatever). So we have to do this very carefully. */
1683 fprintf (file, "\t.STRING \"");
1686 for (i = 0; i < size; i += 4)
1690 for (io = 0, co = 0; io < MIN (4, size - i); io++)
1692 register unsigned int c = p[i + io];
1694 if (c == '\"' || c == '\\')
1695 partial_output[co++] = '\\';
1696 if (c >= ' ' && c < 0177)
1697 partial_output[co++] = c;
1701 partial_output[co++] = '\\';
1702 partial_output[co++] = 'x';
1703 hexd = c / 16 - 0 + '0';
1705 hexd -= '9' - 'a' + 1;
1706 partial_output[co++] = hexd;
1707 hexd = c % 16 - 0 + '0';
1709 hexd -= '9' - 'a' + 1;
1710 partial_output[co++] = hexd;
1713 if (chars_output + co > 243)
1715 fprintf (file, "\"\n\t.STRING \"");
1718 fwrite (partial_output, 1, co, file);
1722 fprintf (file, "\"\n");
1725 /* You may have trouble believing this, but this is the HP-PA stack
1730 Variable arguments (optional; any number may be allocated)
1732 SP-(4*(N+9)) arg word N
1737 Fixed arguments (must be allocated; may remain unused)
1746 SP-32 External Data Pointer (DP)
1748 SP-24 External/stub RP (RP')
1752 SP-8 Calling Stub RP (RP'')
1757 SP-0 Stack Pointer (points to next available address)
1761 /* This function saves registers as follows. Registers marked with ' are
1762 this function's registers (as opposed to the previous function's).
1763 If a frame_pointer isn't needed, r4 is saved as a general register;
1764 the space for the frame pointer is still allocated, though, to keep
1770 SP (FP') Previous FP
1771 SP + 4 Alignment filler (sigh)
1772 SP + 8 Space for locals reserved here.
1776 SP + n All call saved register used.
1780 SP + o All call saved fp registers used.
1784 SP + p (SP') points to next available address.
1788 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
1789 Handle case where DISP > 8k by using the add_high_const pattern.
1791 Note in DISP > 8k case, we will leave the high part of the address
1792 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
1794 store_reg (reg, disp, base)
1795 int reg, disp, base;
1797 if (VAL_14_BITS_P (disp))
1799 emit_move_insn (gen_rtx (MEM, SImode,
1800 gen_rtx (PLUS, SImode,
1801 gen_rtx (REG, SImode, base),
1803 gen_rtx (REG, SImode, reg));
1807 emit_insn (gen_add_high_const (gen_rtx (REG, SImode, 1),
1808 gen_rtx (REG, SImode, base),
1810 emit_move_insn (gen_rtx (MEM, SImode,
1811 gen_rtx (LO_SUM, SImode,
1812 gen_rtx (REG, SImode, 1),
1814 gen_rtx (REG, SImode, reg));
1818 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
1819 Handle case where DISP > 8k by using the add_high_const pattern.
1821 Note in DISP > 8k case, we will leave the high part of the address
1822 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
1824 load_reg (reg, disp, base)
1825 int reg, disp, base;
1827 if (VAL_14_BITS_P (disp))
1829 emit_move_insn (gen_rtx (REG, SImode, reg),
1830 gen_rtx (MEM, SImode,
1831 gen_rtx (PLUS, SImode,
1832 gen_rtx (REG, SImode, base),
1838 emit_insn (gen_add_high_const (gen_rtx (REG, SImode, 1),
1839 gen_rtx (REG, SImode, base),
1841 emit_move_insn (gen_rtx (REG, SImode, reg),
1842 gen_rtx (MEM, SImode,
1843 gen_rtx (LO_SUM, SImode,
1844 gen_rtx (REG, SImode, 1),
1849 /* Emit RTL to set REG to the value specified by BASE+DISP.
1850 Handle case where DISP > 8k by using the add_high_const pattern.
1852 Note in DISP > 8k case, we will leave the high part of the address
1853 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
1855 set_reg_plus_d(reg, base, disp)
1856 int reg, base, disp;
1858 if (VAL_14_BITS_P (disp))
1860 emit_move_insn (gen_rtx (REG, SImode, reg),
1861 gen_rtx (PLUS, SImode,
1862 gen_rtx (REG, SImode, base),
1868 emit_insn (gen_add_high_const (gen_rtx (REG, SImode, 1),
1869 gen_rtx (REG, SImode, base),
1871 emit_move_insn (gen_rtx (REG, SImode, reg),
1872 gen_rtx (LO_SUM, SImode,
1873 gen_rtx (REG, SImode, 1),
1878 /* Global variables set by FUNCTION_PROLOGUE. */
1879 /* Size of frame. Need to know this to emit return insns from
1881 static int actual_fsize;
1882 static int local_fsize, save_fregs;
1885 compute_frame_size (size, fregs_live)
1889 extern int current_function_outgoing_args_size;
1892 /* 8 is space for frame pointer + filler. If any frame is allocated
1893 we need to add this in because of STARTING_FRAME_OFFSET. */
1894 fsize = size + (size || frame_pointer_needed ? 8 : 0);
1896 /* fp is stored in a special place. */
1897 if (frame_pointer_needed)
1899 for (i = 18; i >= 5; i--)
1900 if (regs_ever_live[i])
1903 if (regs_ever_live[3])
1908 for (i = 18; i >= 3; i--)
1909 if (regs_ever_live[i])
1912 fsize = (fsize + 7) & ~7;
1916 for (i = 43; i >= 40; i--)
1917 if (regs_ever_live[i])
1926 for (i = 78; i >= 60; i -= 2)
1927 if (regs_ever_live[i] || regs_ever_live[i + 1])
1934 fsize += current_function_outgoing_args_size;
1935 if (! leaf_function_p () || fsize)
1937 return TARGET_SNAKE ? (fsize + 63 & ~63) : fsize;
1940 rtx hp_profile_label_rtx;
1941 static char hp_profile_label_name[8];
1943 output_function_prologue (file, size)
1948 /* hppa_expand_prologue does the dirty work now. We just need
1949 to output the assembler directives which denote the start
1951 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=%d", actual_fsize);
1952 if (regs_ever_live[2] || profile_flag)
1953 fprintf (file, ",CALLS,SAVE_RP");
1955 fprintf (file, ",NO_CALLS");
1957 if (frame_pointer_needed)
1958 fprintf (file, ",SAVE_SP");
1960 fprintf (file, "\n\t.ENTRY\n");
1962 /* Horrid hack. emit_function_prologue will modify this RTL in
1963 place to get the expected results. */
1965 sprintf(hp_profile_label_name, "LP$%04d", hp_profile_labelno);
1968 hppa_expand_prologue()
1971 extern char call_used_regs[];
1972 int size = get_frame_size ();
1973 int merge_sp_adjust_with_store = 0;
1975 rtx tmpreg, size_rtx;
1979 local_fsize = size + (size || frame_pointer_needed ? 8 : 0);
1980 actual_fsize = compute_frame_size (size, &save_fregs);
1982 /* Compute a few things we will use often. */
1983 tmpreg = gen_rtx (REG, SImode, 1);
1984 size_rtx = GEN_INT (actual_fsize);
1986 /* Save RP first. The calling conventions manual states RP will
1987 always be stored into the caller's frame at sp-20. */
1988 if (regs_ever_live[2] || profile_flag)
1989 store_reg (2, -20, STACK_POINTER_REGNUM);
1991 /* Allocate the local frame and set up the frame pointer if needed. */
1993 if (frame_pointer_needed)
1995 /* Copy the old frame pointer temporarily into %r1. Set up the
1996 new stack pointer, then store away the saved old frame pointer
1997 into the stack at sp+actual_fsize and at the same time update
1998 the stack pointer by actual_fsize bytes. Two versions, first
1999 handles small (<8k) frames. The second handles large (>8k)
2001 emit_move_insn (tmpreg, frame_pointer_rtx);
2002 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2003 if (VAL_14_BITS_P (actual_fsize))
2004 emit_insn (gen_post_stwm (stack_pointer_rtx,
2009 store_reg (1, 0, FRAME_POINTER_REGNUM);
2010 set_reg_plus_d (STACK_POINTER_REGNUM,
2011 STACK_POINTER_REGNUM,
2015 /* no frame pointer needed. */
2018 /* In some cases we can perform the first callee register save
2019 and allocating the stack frame at the same time. If so, just
2020 make a note of it and defer allocating the frame until saving
2021 the callee registers. */
2022 if (VAL_14_BITS_P (-actual_fsize)
2026 merge_sp_adjust_with_store = 1;
2027 /* Can not optimize. Adjust the stack frame by actual_fsize bytes. */
2028 else if (actual_fsize != 0)
2029 set_reg_plus_d (STACK_POINTER_REGNUM,
2030 STACK_POINTER_REGNUM,
2033 /* The hppa calling conventions say that that %r19, the pic offset
2034 register, is saved at sp - 32 (in this function's frame) when
2035 generating PIC code. */
2037 store_reg (19, -32, STACK_POINTER_REGNUM);
2041 Instead of taking one argument, the counter label, as most normal
2042 mcounts do, _mcount appears to behave differently on the HPPA. It
2043 takes the return address of the caller, the address of this routine,
2044 and the address of the label. Also, it isn't magic, so
2045 argument registre hsave to be preserved. */
2048 int pc_offset, i, arg_offset, basereg, offsetadj;
2050 pc_offset = 4 + (frame_pointer_needed
2051 ? (VAL_14_BITS_P (actual_fsize) ? 12 : 20)
2052 : (VAL_14_BITS_P (actual_fsize) ? 4 : 8));
2054 /* When the function has a frame pointer, use it as the base
2055 register for saving/restore registers. Else use the stack
2056 pointer. Adjust the offset according to the frame size if
2057 this function does not have a frame pointer. */
2059 basereg = frame_pointer_needed ? FRAME_POINTER_REGNUM
2060 : STACK_POINTER_REGNUM;
2061 offsetadj = frame_pointer_needed ? 0 : actual_fsize;
2063 /* Horrid hack. emit_function_prologue will modify this RTL in
2064 place to get the expected results. sprintf here is just to
2065 put something in the name. */
2066 sprintf(hp_profile_label_name, "LP$%04d", -1);
2067 hp_profile_label_rtx = gen_rtx (SYMBOL_REF, SImode,
2068 hp_profile_label_name);
2069 if (current_function_returns_struct)
2070 store_reg (STRUCT_VALUE_REGNUM, - 12 - offsetadj, basereg);
2072 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2073 if (regs_ever_live [i])
2075 store_reg (i, arg_offset, basereg);
2076 /* Deal with arg_offset not fitting in 14 bits. */
2077 pc_offset += VAL_14_BITS_P (arg_offset) ? 4 : 8;
2080 emit_move_insn (gen_rtx (REG, SImode, 26), gen_rtx (REG, SImode, 2));
2081 emit_move_insn (tmpreg, gen_rtx (HIGH, SImode, hp_profile_label_rtx));
2082 emit_move_insn (gen_rtx (REG, SImode, 24),
2083 gen_rtx (LO_SUM, SImode, tmpreg, hp_profile_label_rtx));
2084 /* %r25 is set from within the output pattern. */
2085 emit_insn (gen_call_profiler (GEN_INT (- pc_offset - 20)));
2087 /* Restore argument registers. */
2088 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2089 if (regs_ever_live [i])
2090 load_reg (i, arg_offset, basereg);
2092 if (current_function_returns_struct)
2093 load_reg (STRUCT_VALUE_REGNUM, -12 - offsetadj, basereg);
2097 /* Normal register save.
2099 Do not save the frame pointer in the frame_pointer_needed case. It
2100 was done earlier. */
2101 if (frame_pointer_needed)
2103 for (i = 18, offset = local_fsize; i >= 3; i--)
2104 if (regs_ever_live[i] && ! call_used_regs[i]
2105 && i != FRAME_POINTER_REGNUM)
2107 store_reg (i, offset, FRAME_POINTER_REGNUM);
2111 /* No frame pointer needed. */
2114 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
2115 if (regs_ever_live[i] && ! call_used_regs[i])
2117 /* If merge_sp_adjust_with_store is nonzero, then we can
2118 optimize the first GR save. */
2119 if (merge_sp_adjust_with_store)
2121 merge_sp_adjust_with_store = 0;
2122 emit_insn (gen_post_stwm (stack_pointer_rtx,
2125 gen_rtx (REG, SImode, i)));
2128 store_reg (i, offset, STACK_POINTER_REGNUM);
2132 /* If we wanted to merge the SP adjustment with a GR save, but we never
2133 did any GR saves, then just emit the adjustment here. */
2134 if (merge_sp_adjust_with_store)
2135 set_reg_plus_d (STACK_POINTER_REGNUM,
2136 STACK_POINTER_REGNUM,
2140 /* Align pointer properly (doubleword boundary). */
2141 offset = (offset + 7) & ~7;
2143 /* Floating point register store. */
2147 /* First get the frame or stack pointer to the start of the FP register
2149 if (frame_pointer_needed)
2150 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
2152 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
2154 /* Now actually save the FP registers. */
2157 for (i = 43; i >= 40; i--)
2159 if (regs_ever_live[i])
2160 emit_move_insn (gen_rtx (MEM, DFmode,
2161 gen_rtx (POST_INC, DFmode, tmpreg)),
2162 gen_rtx (REG, DFmode, i));
2167 for (i = 78; i >= 60; i -= 2)
2168 if (regs_ever_live[i] || regs_ever_live[i + 1])
2170 emit_move_insn (gen_rtx (MEM, DFmode,
2171 gen_rtx (POST_INC, DFmode, tmpreg)),
2172 gen_rtx (REG, DFmode, i));
2180 output_function_epilogue (file, size)
2185 rtx insn = get_last_insn ();
2187 /* hppa_expand_epilogue does the dirty work now. We just need
2188 to output the assembler directives which denote the end
2191 To make debuggers happy, emit a nop if the epilogue was completely
2192 eliminated due to a volatile call as the last insn in the
2193 current function. That way the return address (in %r2) will
2194 always point to a valid instruction in the current function. */
2196 /* Get the last real insn. */
2197 if (GET_CODE (insn) == NOTE)
2198 insn = prev_real_insn (insn);
2200 /* If it is a sequence, then look inside. */
2201 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
2202 insn = XVECEXP (PATTERN (insn), 0, 0);
2204 /* If insn is a CALL_INSN, then it must be a call to a volatile
2205 function (otherwise there would be epilogue insns). */
2206 if (insn && GET_CODE (insn) == CALL_INSN)
2207 fprintf (file, "\tnop\n");
2209 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
2213 hppa_expand_epilogue ()
2217 int merge_sp_adjust_with_load = 0;
2219 /* We will use this often. */
2220 tmpreg = gen_rtx (REG, SImode, 1);
2222 /* Try to restore RP early to avoid load/use interlocks when
2223 RP gets used in the return (bv) instruction. This appears to still
2224 be necessary even when we schedule the prologue and epilogue. */
2225 if (frame_pointer_needed
2226 && (regs_ever_live [2] || profile_flag))
2227 load_reg (2, -20, FRAME_POINTER_REGNUM);
2229 /* No frame pointer, and stack is smaller than 8k. */
2230 else if (! frame_pointer_needed
2231 && VAL_14_BITS_P (actual_fsize + 20)
2232 && (regs_ever_live[2] || profile_flag))
2233 load_reg (2, - (actual_fsize + 20), STACK_POINTER_REGNUM);
2235 /* General register restores. */
2236 if (frame_pointer_needed)
2238 for (i = 18, offset = local_fsize; i >= 3; i--)
2239 if (regs_ever_live[i] && ! call_used_regs[i]
2240 && i != FRAME_POINTER_REGNUM)
2242 load_reg (i, offset, FRAME_POINTER_REGNUM);
2248 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
2249 if (regs_ever_live[i] && ! call_used_regs[i])
2251 /* Only for the first load.
2252 merge_sp_adjust_with_load holds the register load
2253 with which we will merge the sp adjustment. */
2254 if (VAL_14_BITS_P (actual_fsize + 20)
2256 && ! merge_sp_adjust_with_load)
2257 merge_sp_adjust_with_load = i;
2259 load_reg (i, offset, STACK_POINTER_REGNUM);
2264 /* Align pointer properly (doubleword boundary). */
2265 offset = (offset + 7) & ~7;
2267 /* FP register restores. */
2270 /* Adjust the register to index off of. */
2271 if (frame_pointer_needed)
2272 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
2274 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
2276 /* Actually do the restores now. */
2279 for (i = 43; i >= 40; i--)
2280 if (regs_ever_live[i])
2281 emit_move_insn (gen_rtx (REG, DFmode, i),
2282 gen_rtx (MEM, DFmode,
2283 gen_rtx (POST_INC, DFmode, tmpreg)));
2288 for (i = 78; i >= 60; i -= 2)
2289 if (regs_ever_live[i] || regs_ever_live[i + 1])
2290 emit_move_insn (gen_rtx (REG, DFmode, i),
2291 gen_rtx (MEM, DFmode,
2292 gen_rtx (POST_INC, DFmode, tmpreg)));
2296 /* No frame pointer, but we have a stack greater than 8k. We restore
2297 %r2 very late in this case. (All other cases are restored as early
2299 if (! frame_pointer_needed
2300 && ! VAL_14_BITS_P (actual_fsize + 20)
2301 && (regs_ever_live[2] || profile_flag))
2303 set_reg_plus_d (STACK_POINTER_REGNUM,
2304 STACK_POINTER_REGNUM,
2306 /* Uses value left over in %r1 by set_reg_plus_d. */
2307 load_reg (2, - (actual_fsize + 20 + ((- actual_fsize) & ~0x7ff)), 1);
2310 /* Reset stack pointer (and possibly frame pointer). The stack */
2311 /* pointer is initially set to fp + 64 to avoid a race condition.
2312 ??? What race condition?!? */
2313 else if (frame_pointer_needed)
2315 /* Emit a blockage insn here to keep these insns from being moved
2316 to the beginning of the prologue or into the main instruction
2317 stream, doing so avoids some very obscure problems. */
2318 emit_insn (gen_blockage ());
2319 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64);
2320 emit_insn (gen_pre_ldwm (stack_pointer_rtx, stack_pointer_rtx,
2321 GEN_INT (-64), frame_pointer_rtx));
2323 /* If we were deferring a callee register restore, do it now. */
2324 else if (! frame_pointer_needed && merge_sp_adjust_with_load)
2325 emit_insn (gen_pre_ldwm (stack_pointer_rtx,
2327 GEN_INT (- actual_fsize),
2328 gen_rtx (REG, SImode,
2329 merge_sp_adjust_with_load)));
2330 else if (actual_fsize != 0)
2331 set_reg_plus_d (STACK_POINTER_REGNUM,
2332 STACK_POINTER_REGNUM,
2336 /* This is only valid once reload has completed because it depends on
2337 knowing exactly how much (if any) frame there is and...
2339 It's only valid if there is no frame marker to de-allocate and...
2341 It's only valid if %r2 hasn't been saved into the caller's frame
2342 (we're not profiling and %r2 isn't live anywhere). */
2344 hppa_can_use_return_insn_p ()
2346 return (reload_completed
2347 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
2349 && ! regs_ever_live[2]
2350 && ! frame_pointer_needed);
2354 emit_bcond_fp (code, operand0)
2358 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
2359 gen_rtx (IF_THEN_ELSE, VOIDmode,
2360 gen_rtx (code, VOIDmode,
2361 gen_rtx (REG, CCFPmode, 0),
2363 gen_rtx (LABEL_REF, VOIDmode, operand0),
2369 gen_cmp_fp (code, operand0, operand1)
2371 rtx operand0, operand1;
2373 return gen_rtx (SET, VOIDmode, gen_rtx (REG, CCFPmode, 0),
2374 gen_rtx (code, CCFPmode, operand0, operand1));
2377 /* Adjust the cost of a scheduling dependency. Return the new cost of
2378 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
2381 pa_adjust_cost (insn, link, dep_insn, cost)
2387 if (! recog_memoized (insn))
2390 if (REG_NOTE_KIND (link) == 0)
2392 /* Data dependency; DEP_INSN writes a register that INSN reads some
2395 if (get_attr_type (insn) == TYPE_FPSTORE)
2397 rtx pat = PATTERN (insn);
2398 rtx dep_pat = PATTERN (dep_insn);
2399 if (GET_CODE (pat) == PARALLEL)
2401 /* This happens for the fstXs,mb patterns. */
2402 pat = XVECEXP (pat, 0, 0);
2404 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
2405 /* If this happens, we have to extend this to schedule
2406 optimally. Return 0 for now. */
2409 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
2411 if (! recog_memoized (dep_insn))
2413 /* DEP_INSN is writing its result to the register
2414 being stored in the fpstore INSN. */
2415 switch (get_attr_type (dep_insn))
2418 /* This cost 3 cycles, not 2 as the md says. */
2425 case TYPE_FPSQRTSGL:
2426 case TYPE_FPSQRTDBL:
2427 /* In these important cases, we save one cycle compared to
2428 when flop instruction feed each other. */
2437 /* For other data dependencies, the default cost specified in the
2441 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
2443 /* Anti dependency; DEP_INSN reads a register that INSN writes some
2446 if (get_attr_type (insn) == TYPE_FPLOAD)
2448 rtx pat = PATTERN (insn);
2449 rtx dep_pat = PATTERN (dep_insn);
2450 if (GET_CODE (pat) == PARALLEL)
2452 /* This happens for the fldXs,mb patterns. */
2453 pat = XVECEXP (pat, 0, 0);
2455 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
2456 /* If this happens, we have to extend this to schedule
2457 optimally. Return 0 for now. */
2460 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
2462 if (! recog_memoized (dep_insn))
2464 switch (get_attr_type (dep_insn))
2470 case TYPE_FPSQRTSGL:
2471 case TYPE_FPSQRTDBL:
2472 /* A fpload can't be issued until one cycle before a
2473 preceeding arithmetic operation has finished, if
2474 the target of the fpload is any of the sources
2475 (or destination) of the arithmetic operation. */
2484 /* For other anti dependencies, the cost is 0. */
2488 /* For output dependencies, the cost is often one too high. */
2492 /* Return any length adjustment needed by INSN which already has its length
2493 computed as LENGTH. Return zero if no adjustment is necessary.
2495 For the PA: function calls, millicode calls, and backwards short
2496 conditional branches with unfilled delay slots need an adjustment by +1
2497 (to account for the NOP which will be inserted into the instruction stream).
2499 Also compute the length of an inline block move here as it is too
2500 complicated to express as a length attribute in pa.md. */
2502 pa_adjust_insn_length (insn, length)
2506 rtx pat = PATTERN (insn);
2508 /* Call insns which are *not* indirect and have unfilled delay slots. */
2509 if (GET_CODE (insn) == CALL_INSN)
2512 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
2513 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
2515 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
2516 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
2522 /* Millicode insn with an unfilled delay slot. */
2523 else if (GET_CODE (insn) == INSN
2524 && GET_CODE (pat) != SEQUENCE
2525 && GET_CODE (pat) != USE
2526 && GET_CODE (pat) != CLOBBER
2527 && get_attr_type (insn) == TYPE_MILLI)
2529 /* Block move pattern. */
2530 else if (GET_CODE (insn) == INSN
2531 && GET_CODE (pat) == PARALLEL
2532 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
2533 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
2534 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
2535 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
2536 return compute_movstrsi_length (insn) - 1;
2537 /* Conditional branch with an unfilled delay slot. */
2538 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
2540 /* Adjust a short backwards conditional with an unfilled delay slot. */
2541 if (GET_CODE (pat) == SET
2543 && ! forward_branch_p (insn))
2545 /* Adjust dbra insn with short backwards conditional branch with
2546 unfilled delay slot -- only for case where counter is in a register. */
2547 else if (GET_CODE (pat) == PARALLEL
2548 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
2549 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
2551 && ! forward_branch_p (insn))
2560 /* Print operand X (an rtx) in assembler syntax to file FILE.
2561 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2562 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2565 print_operand (file, x, code)
2573 /* Output a 'nop' if there's nothing for the delay slot. */
2574 if (dbr_sequence_length () == 0)
2575 fputs ("\n\tnop", file);
2578 /* Output an nullification completer if there's nothing for the */
2579 /* delay slot or nullification is requested. */
2580 if (dbr_sequence_length () == 0 ||
2582 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
2586 /* Print out the second register name of a register pair.
2587 I.e., R (6) => 7. */
2588 fputs (reg_names[REGNO (x)+1], file);
2591 /* A register or zero. */
2593 || (x == CONST0_RTX (DFmode))
2594 || (x == CONST0_RTX (SFmode)))
2601 case 'C': /* Plain (C)ondition */
2603 switch (GET_CODE (x))
2606 fprintf (file, "="); break;
2608 fprintf (file, "<>"); break;
2610 fprintf (file, ">"); break;
2612 fprintf (file, ">="); break;
2614 fprintf (file, ">>="); break;
2616 fprintf (file, ">>"); break;
2618 fprintf (file, "<"); break;
2620 fprintf (file, "<="); break;
2622 fprintf (file, "<<="); break;
2624 fprintf (file, "<<"); break;
2626 printf ("Can't grok '%c' operator:\n", code);
2631 case 'N': /* Condition, (N)egated */
2632 switch (GET_CODE (x))
2635 fprintf (file, "<>"); break;
2637 fprintf (file, "="); break;
2639 fprintf (file, "<="); break;
2641 fprintf (file, "<"); break;
2643 fprintf (file, "<<"); break;
2645 fprintf (file, "<<="); break;
2647 fprintf (file, ">="); break;
2649 fprintf (file, ">"); break;
2651 fprintf (file, ">>"); break;
2653 fprintf (file, ">>="); break;
2655 printf ("Can't grok '%c' operator:\n", code);
2660 /* For floating point comparisons. Need special conditions to deal
2661 with NaNs properly. */
2663 switch (GET_CODE (x))
2666 fprintf (file, "!="); break;
2668 fprintf (file, "="); break;
2670 fprintf (file, "!>"); break;
2672 fprintf (file, "!>="); break;
2674 fprintf (file, "!<"); break;
2676 fprintf (file, "!<="); break;
2678 printf ("Can't grok '%c' operator:\n", code);
2683 case 'S': /* Condition, operands are (S)wapped. */
2684 switch (GET_CODE (x))
2687 fprintf (file, "="); break;
2689 fprintf (file, "<>"); break;
2691 fprintf (file, "<"); break;
2693 fprintf (file, "<="); break;
2695 fprintf (file, "<<="); break;
2697 fprintf (file, "<<"); break;
2699 fprintf (file, ">"); break;
2701 fprintf (file, ">="); break;
2703 fprintf (file, ">>="); break;
2705 fprintf (file, ">>"); break;
2707 printf ("Can't grok '%c' operator:\n", code);
2712 case 'B': /* Condition, (B)oth swapped and negate. */
2713 switch (GET_CODE (x))
2716 fprintf (file, "<>"); break;
2718 fprintf (file, "="); break;
2720 fprintf (file, ">="); break;
2722 fprintf (file, ">"); break;
2724 fprintf (file, ">>"); break;
2726 fprintf (file, ">>="); break;
2728 fprintf (file, "<="); break;
2730 fprintf (file, "<"); break;
2732 fprintf (file, "<<"); break;
2734 fprintf (file, "<<="); break;
2736 printf ("Can't grok '%c' operator:\n", code);
2742 if (GET_CODE (x) == CONST_INT)
2744 fprintf (file, "%d", ~INTVAL (x));
2749 if (GET_CODE (x) == CONST_INT)
2751 fprintf (file, "%d", 32 - (INTVAL (x) & 31));
2756 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
2758 fprintf (file, "%d", exact_log2 (INTVAL (x)));
2763 if (GET_CODE (x) == CONST_INT)
2765 fprintf (file, "%d", 31 - (INTVAL (x) & 31));
2770 if (GET_CODE (x) == CONST_INT)
2774 switch (GET_CODE (XEXP (x, 0)))
2778 fprintf (file, "s,mb");
2782 fprintf (file, "s,ma");
2789 switch (GET_CODE (XEXP (x, 0)))
2793 fprintf (file, ",mb");
2797 fprintf (file, ",ma");
2804 output_global_address (file, x);
2806 case 0: /* Don't do anything special */
2811 compute_zdepi_operands (INTVAL (x), op);
2812 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
2818 if (GET_CODE (x) == REG)
2819 fprintf (file, "%s", reg_names [REGNO (x)]);
2820 else if (GET_CODE (x) == MEM)
2822 int size = GET_MODE_SIZE (GET_MODE (x));
2823 rtx base = XEXP (XEXP (x, 0), 0);
2824 switch (GET_CODE (XEXP (x, 0)))
2828 fprintf (file, "-%d(0,%s)", size, reg_names [REGNO (base)]);
2832 fprintf (file, "%d(0,%s)", size, reg_names [REGNO (base)]);
2835 output_address (XEXP (x, 0));
2839 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
2841 union { double d; int i[2]; } u;
2842 union { float f; int i; } u1;
2843 u.i[0] = XINT (x, 0); u.i[1] = XINT (x, 1);
2846 fprintf (file, "0r%.9g", u1.f);
2848 fprintf (file, "0x%x", u1.i);
2850 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != DImode)
2852 union { double d; int i[2]; } u;
2853 u.i[0] = XINT (x, 0); u.i[1] = XINT (x, 1);
2854 fprintf (file, "0r%.20g", u.d);
2857 output_addr_const (file, x);
2860 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
2863 output_global_address (file, x)
2868 /* Imagine (high (const (plus ...))). */
2869 if (GET_CODE (x) == HIGH)
2872 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x))
2873 assemble_name (file, XSTR (x, 0));
2874 else if (GET_CODE (x) == SYMBOL_REF)
2876 assemble_name (file, XSTR (x, 0));
2877 fprintf (file, "-$global$");
2879 else if (GET_CODE (x) == CONST)
2882 int offset = 0; /* assembler wants -$global$ at end */
2885 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
2887 base = XEXP (XEXP (x, 0), 0);
2888 output_addr_const (file, base);
2890 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
2891 offset = INTVAL (XEXP (XEXP (x, 0), 0));
2894 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
2896 base = XEXP (XEXP (x, 0), 1);
2897 output_addr_const (file, base);
2899 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2900 offset = INTVAL (XEXP (XEXP (x, 0),1));
2903 if (GET_CODE (XEXP (x, 0)) == PLUS)
2913 else if (GET_CODE (XEXP (x, 0)) == MINUS
2914 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
2918 if (!read_only_operand (base))
2919 fprintf (file, "-$global$");
2920 fprintf (file, "%s", sep);
2921 if (offset) fprintf (file,"%d", offset);
2924 output_addr_const (file, x);
2927 /* HP's millicode routines mean something special to the assembler.
2928 Keep track of which ones we have used. */
2930 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
2931 static char imported[(int)end1000];
2932 static char *milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
2933 static char import_string[] = ".IMPORT $$....,MILLICODE";
2934 #define MILLI_START 10
2938 enum millicodes code;
2940 char str[sizeof (import_string)];
2942 if (!imported[(int)code])
2944 imported[(int)code] = 1;
2945 strcpy (str, import_string);
2946 strncpy (str + MILLI_START, milli_names[(int)code], 4);
2947 output_asm_insn (str, 0);
2951 /* The register constraints have put the operands and return value in
2952 the proper registers. */
2955 output_mul_insn (unsignedp)
2960 import_milli (mulU);
2961 return "bl $$mulU,31%#";
2965 import_milli (mulI);
2966 return "bl $$mulI,31%#";
2970 /* If operands isn't NULL, then it's a CONST_INT with which we can do
2974 /* Emit the rtl for doing a division by a constant. */
2976 /* Do magic division millicodes exist for this value? */
2978 static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
2981 /* We'll use an array to keep track of the magic millicodes and
2982 whether or not we've used them already. [n][0] is signed, [n][1] is
2985 static int div_milli[16][2];
2988 div_operand (op, mode)
2990 enum machine_mode mode;
2992 return (mode == SImode
2993 && ((GET_CODE (op) == REG && REGNO (op) == 25)
2994 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
2995 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
2999 emit_hpdiv_const (operands, unsignedp)
3003 if (GET_CODE (operands[2]) == CONST_INT
3004 && INTVAL (operands[2]) > 0
3005 && INTVAL (operands[2]) < 16
3006 && magic_milli[INTVAL (operands[2])])
3008 emit_move_insn ( gen_rtx (REG, SImode, 26), operands[1]);
3011 (PARALLEL, VOIDmode,
3012 gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
3013 gen_rtx (unsignedp ? UDIV : DIV, SImode,
3014 gen_rtx (REG, SImode, 26),
3016 gen_rtx (CLOBBER, VOIDmode, operands[3]),
3017 gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
3018 gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
3019 gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
3020 emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
3027 output_div_insn (operands, unsignedp)
3033 /* If the divisor is a constant, try to use one of the special
3035 if (GET_CODE (operands[0]) == CONST_INT)
3037 divisor = INTVAL (operands[0]);
3038 if (!div_milli[divisor][unsignedp])
3041 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
3043 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
3044 div_milli[divisor][unsignedp] = 1;
3047 return "bl $$divU_%0,31%#";
3048 return "bl $$divI_%0,31%#";
3050 /* Divisor isn't a special constant. */
3055 import_milli (divU);
3056 return "bl $$divU,31%#";
3060 import_milli (divI);
3061 return "bl $$divI,31%#";
3066 /* Output a $$rem millicode to do mod. */
3069 output_mod_insn (unsignedp)
3074 import_milli (remU);
3075 return "bl $$remU,31%#";
3079 import_milli (remI);
3080 return "bl $$remI,31%#";
3085 output_arg_descriptor (insn)
3089 enum machine_mode arg_mode;
3091 int i, output_flag = 0;
3094 for (i = 0; i < 4; i++)
3097 for (prev_insn = PREV_INSN (insn); GET_CODE (prev_insn) == INSN;
3098 prev_insn = PREV_INSN (prev_insn))
3100 if (!(GET_CODE (PATTERN (prev_insn)) == USE &&
3101 GET_CODE (XEXP (PATTERN (prev_insn), 0)) == REG &&
3102 FUNCTION_ARG_REGNO_P (REGNO (XEXP (PATTERN (prev_insn), 0)))))
3104 arg_mode = GET_MODE (XEXP (PATTERN (prev_insn), 0));
3105 regno = REGNO (XEXP (PATTERN (prev_insn), 0));
3106 if (regno >= 23 && regno <= 26)
3108 arg_regs[26 - regno] = "GR";
3109 if (arg_mode == DImode)
3110 arg_regs[25 - regno] = "GR";
3112 else if (!TARGET_SNAKE) /* fp args */
3114 if (arg_mode == SFmode)
3115 arg_regs[regno - 32] = "FR";
3118 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
3119 arg_regs[regno - 33] = "FR";
3120 arg_regs[regno - 32] = "FU";
3122 arg_regs[regno - 33] = "FU";
3123 arg_regs[regno - 32] = "FR";
3129 if (arg_mode == SFmode)
3130 arg_regs[(regno - 44) / 2] = "FR";
3133 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
3134 arg_regs[(regno - 46) / 2] = "FR";
3135 arg_regs[(regno - 46) / 2 + 1] = "FU";
3137 arg_regs[(regno - 46) / 2] = "FU";
3138 arg_regs[(regno - 46) / 2 + 1] = "FR";
3143 fputs ("\t.CALL ", asm_out_file);
3144 for (i = 0; i < 4; i++)
3149 fputc (',', asm_out_file);
3150 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
3153 fputc ('\n', asm_out_file);
3156 /* Memory loads/stores to/from the shift need to go through
3157 the general registers. */
3160 secondary_reload_class (class, mode, in)
3161 enum reg_class class;
3162 enum machine_mode mode;
3165 int regno = true_regnum (in);
3167 if (function_label_operand (in, mode)
3168 || ((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
3169 && GET_MODE_CLASS (mode) == MODE_INT
3170 && FP_REG_CLASS_P (class))
3171 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
3172 return GENERAL_REGS;
3174 if (GET_CODE (in) == HIGH)
3177 if (TARGET_KERNEL && class != R1_REGS && symbolic_operand (in, VOIDmode))
3184 function_arg_padding (mode, type)
3185 enum machine_mode mode;
3190 if (mode == BLKmode)
3192 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
3193 size = int_size_in_bytes (type) * BITS_PER_UNIT;
3195 return upward; /* Don't know if this is right, but */
3196 /* same as old definition. */
3199 size = GET_MODE_BITSIZE (mode);
3200 if (size < PARM_BOUNDARY)
3202 else if (size % PARM_BOUNDARY)
3209 /* Do what is necessary for `va_start'. The argument is ignored;
3210 We look at the current function to determine if stdargs or varargs
3211 is used and fill in an initial va_list. A pointer to this constructor
3215 hppa_builtin_saveregs (arglist)
3218 rtx block, float_addr, offset, float_mem;
3219 tree fntype = TREE_TYPE (current_function_decl);
3220 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
3221 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3222 != void_type_node)))
3223 ? UNITS_PER_WORD : 0);
3226 offset = plus_constant (current_function_arg_offset_rtx, argadj);
3228 offset = current_function_arg_offset_rtx;
3230 /* Store general registers on the stack. */
3231 move_block_from_reg (23,
3232 gen_rtx (MEM, BLKmode,
3234 (current_function_internal_arg_pointer, -16)),
3236 return copy_to_reg (expand_binop (Pmode, add_optab,
3237 current_function_internal_arg_pointer,
3238 offset, 0, 0, OPTAB_LIB_WIDEN));
3241 /* This routine handles all the normal conditional branch sequences we
3242 might need to generate. It handles compare immediate vs compare
3243 register, nullification of delay slots, varying length branches,
3244 negated branches, and all combinations of the above. It returns the
3245 output appropriate to emit the branch corresponding to all given
3249 output_cbranch (operands, nullify, length, negated, insn)
3251 int nullify, length, negated;
3254 static char buf[100];
3257 /* If this is a long branch with its delay slot unfilled, set `nullify'
3258 as it can nullify the delay slot and save a nop. */
3259 if (length == 2 && dbr_sequence_length () == 0)
3262 /* If this is a short forward conditional branch which did not get
3263 its delay slot filled, the delay slot can still be nullified. */
3264 if (! nullify && length == 1 && dbr_sequence_length () == 0)
3265 nullify = forward_branch_p (insn);
3267 /* A forward branch over a single nullified insn can be done with a
3268 comclr instruction. This avoids a single cycle penalty due to
3269 mis-predicted branch if we fall through (branch not taken). */
3271 && next_real_insn (insn) != 0
3272 && get_attr_length (next_real_insn (insn)) == 1
3273 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
3279 /* All short conditional branches except backwards with an unfilled
3283 strcpy (buf, "com%I2clr,");
3285 strcpy (buf, "com%I2b,");
3287 strcat (buf, "%B3");
3289 strcat (buf, "%S3");
3291 strcat (buf, " %2,%1,0");
3293 strcat (buf, ",n %2,%1,%0");
3295 strcat (buf, " %2,%1,%0");
3298 /* All long conditionals. Note an short backward branch with an
3299 unfilled delay slot is treated just like a long backward branch
3300 with an unfilled delay slot. */
3302 /* Handle weird backwards branch with a filled delay slot
3303 with is nullified. */
3304 if (dbr_sequence_length () != 0
3305 && ! forward_branch_p (insn)
3308 strcpy (buf, "com%I2b,");
3310 strcat (buf, "%S3");
3312 strcat (buf, "%B3");
3313 strcat (buf, ",n %2,%1,.+12\n\tbl %0,0");
3317 strcpy (buf, "com%I2clr,");
3319 strcat (buf, "%S3");
3321 strcat (buf, "%B3");
3323 strcat (buf, " %2,%1,0\n\tbl,n %0,0");
3325 strcat (buf, " %2,%1,0\n\tbl %0,0");
3335 /* This routine handles all the branch-on-bit conditional branch sequences we
3336 might need to generate. It handles nullification of delay slots,
3337 varying length branches, negated branches and all combinations of the
3338 above. it returns the appropriate output template to emit the branch. */
3341 output_bb (operands, nullify, length, negated, insn, which)
3343 int nullify, length, negated;
3347 static char buf[100];
3350 /* If this is a long branch with its delay slot unfilled, set `nullify'
3351 as it can nullify the delay slot and save a nop. */
3352 if (length == 2 && dbr_sequence_length () == 0)
3355 /* If this is a short forward conditional branch which did not get
3356 its delay slot filled, the delay slot can still be nullified. */
3357 if (! nullify && length == 1 && dbr_sequence_length () == 0)
3358 nullify = forward_branch_p (insn);
3360 /* A forward branch over a single nullified insn can be done with a
3361 extrs instruction. This avoids a single cycle penalty due to
3362 mis-predicted branch if we fall through (branch not taken). */
3365 && next_real_insn (insn) != 0
3366 && get_attr_length (next_real_insn (insn)) == 1
3367 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
3374 /* All short conditional branches except backwards with an unfilled
3378 strcpy (buf, "extrs,");
3380 strcpy (buf, "bb,");
3381 if ((which == 0 && negated)
3382 || (which == 1 && ! negated))
3387 strcat (buf, " %0,%1,1,0");
3388 else if (nullify && negated)
3389 strcat (buf, ",n %0,%1,%3");
3390 else if (nullify && ! negated)
3391 strcat (buf, ",n %0,%1,%2");
3392 else if (! nullify && negated)
3393 strcat (buf, "%0,%1,%3");
3394 else if (! nullify && ! negated)
3395 strcat (buf, " %0,%1,%2");
3398 /* All long conditionals. Note an short backward branch with an
3399 unfilled delay slot is treated just like a long backward branch
3400 with an unfilled delay slot. */
3402 /* Handle weird backwards branch with a filled delay slot
3403 with is nullified. */
3404 if (dbr_sequence_length () != 0
3405 && ! forward_branch_p (insn)
3408 strcpy (buf, "bb,");
3409 if ((which == 0 && negated)
3410 || (which == 1 && ! negated))
3415 strcat (buf, " %0,%1,.+12\n\tbl %3,0");
3417 strcat (buf, " %0,%1,.+12\n\tbl %2,0");
3421 strcpy (buf, "extrs,");
3422 if ((which == 0 && negated)
3423 || (which == 1 && ! negated))
3427 if (nullify && negated)
3428 strcat (buf, " %0,%1,1,0\n\tbl,n %3,0");
3429 else if (nullify && ! negated)
3430 strcat (buf, " %0,%1,1,0\n\tbl,n %2,0");
3432 strcat (buf, " %0,%1,1,0\n\tbl %3,0");
3434 strcat (buf, " %0,%1,1,0\n\tbl %2,0");
3444 extern struct obstack *saveable_obstack;
3446 /* In HPUX 8.0's shared library scheme, special relocations are needed
3447 for function labels if they might be passed to a function
3448 in a shared library (because shared libraries don't live in code
3449 space), and special magic is needed to construct their address. */
3452 hppa_encode_label (sym)
3455 char *str = XSTR (sym, 0);
3456 int len = strlen (str);
3457 char *newstr = obstack_alloc (saveable_obstack, len + 2) ;
3461 strcpy (newstr + 1, str);
3463 XSTR (sym,0) = newstr;
3467 function_label_operand (op, mode)
3469 enum machine_mode mode;
3471 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
3474 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
3475 use in fmpyadd instructions. */
3477 fmpyaddoperands(operands)
3480 enum machine_mode mode = GET_MODE (operands[0]);
3482 /* All modes must be the same. */
3483 if (! (mode == GET_MODE (operands[1])
3484 && mode == GET_MODE (operands[2])
3485 && mode == GET_MODE (operands[3])
3486 && mode == GET_MODE (operands[4])
3487 && mode == GET_MODE (operands[5])))
3490 /* Both DFmode and SFmode should work. But using SFmode makes the
3491 assembler complain. Just turn it off for now. */
3495 /* Only 2 real operands to the addition. One of the input operands must
3496 be the same as the output operand. */
3497 if (! rtx_equal_p (operands[3], operands[4])
3498 && ! rtx_equal_p (operands[3], operands[5]))
3501 /* Inout operand of add can not conflict with any operands from multiply. */
3502 if (rtx_equal_p (operands[3], operands[0])
3503 || rtx_equal_p (operands[3], operands[1])
3504 || rtx_equal_p (operands[3], operands[2]))
3507 /* multiply can not feed into addition operands. */
3508 if (rtx_equal_p (operands[4], operands[0])
3509 || rtx_equal_p (operands[5], operands[0]))
3512 /* Passed. Operands are suitable for fmpyadd. */
3516 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
3517 use in fmpysub instructions. */
3519 fmpysuboperands(operands)
3522 enum machine_mode mode = GET_MODE (operands[0]);
3524 /* All modes must be the same. */
3525 if (! (mode == GET_MODE (operands[1])
3526 && mode == GET_MODE (operands[2])
3527 && mode == GET_MODE (operands[3])
3528 && mode == GET_MODE (operands[4])
3529 && mode == GET_MODE (operands[5])))
3532 /* Both DFmode and SFmode should work. But using SFmode makes the
3533 assembler complain. Just turn it off for now. */
3537 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
3538 operation, so operands[4] must be the same as operand[3]. */
3539 if (! rtx_equal_p (operands[3], operands[4]))
3542 /* multiply can not feed into subtraction. */
3543 if (rtx_equal_p (operands[5], operands[0]))
3546 /* Inout operand of sub can not conflict with any operands from multiply. */
3547 if (rtx_equal_p (operands[3], operands[0])
3548 || rtx_equal_p (operands[3], operands[1])
3549 || rtx_equal_p (operands[3], operands[2]))
3552 /* Passed. Operands are suitable for fmpysub. */
3557 plus_xor_ior_operator (op, mode)
3559 enum machine_mode mode;
3561 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
3562 || GET_CODE (op) == IOR);
3565 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
3566 constants for shadd instructions. */
3568 shadd_constant_p (val)
3571 if (val == 2 || val == 4 || val == 8)
3577 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
3578 the valid constant for shadd instructions. */
3580 shadd_operand (op, mode)
3582 enum machine_mode mode;
3584 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
3587 /* Return 1 if INSN branches forward. Should be using insn_addresses
3588 to avoid walking through all the insns... */
3590 forward_branch_p (insn)
3593 rtx label = JUMP_LABEL (insn);
3600 insn = NEXT_INSN (insn);
3603 return (insn == label);