1 ;; GCC machine description for MMIX
2 ;; Copyright (C) 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 ;; Contributed by Hans-Peter Nilsson (hp@bitrange.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See file "rtl.def" for documentation on define_insn, match_*, et al.
27 ;; Uses of UNSPEC in this file:
30 ;; 0 sync_icache (sync icache before trampoline jump)
31 ;; 1 nonlocal_goto_receiver
34 ;; The order of insns is as in Node: Standard Names, with smaller modes
35 ;; before bigger modes.
40 (MMIX_fp_rO_OFFSET -24)]
43 ;; FIXME: Can we remove the reg-to-reg for smaller modes? Shouldn't they
46 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r ,r,x ,r,r,m,??r")
47 (match_operand:QI 1 "general_operand" "r,LS,K,rI,x,m,r,n"))]
60 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r ,r ,x,r,r,m,??r")
61 (match_operand:HI 1 "general_operand" "r,LS,K,r,x,m,r,n"))]
73 ;; gcc.c-torture/compile/920428-2.c fails if there's no "n".
75 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r ,r,x,r,r,m,??r")
76 (match_operand:SI 1 "general_operand" "r,LS,K,r,x,m,r,n"))]
88 ;; We assume all "s" are addresses. Does that hold?
90 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r ,r,x,r,m,r,m,r,r,??r")
91 (match_operand:DI 1 "general_operand" "r,LS,K,r,x,I,m,r,R,s,n"))]
106 ;; Note that we move around the float as a collection of bits; no
107 ;; conversion to double.
109 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,x,r,r,m,??r")
110 (match_operand:SF 1 "general_operand" "r,G,r,x,m,r,F"))]
122 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,x,r,r,m,??r")
123 (match_operand:DF 1 "general_operand" "r,G,r,x,m,r,F"))]
134 ;; We need to be able to move around the values used as condition codes.
135 ;; First spotted as reported in
136 ;; <URL:http://gcc.gnu.org/ml/gcc-bugs/2003-03/msg00008.html> due to
137 ;; changes in loop optimization. The file machmode.def says they're of
138 ;; size 4 QI. Valid bit-patterns correspond to integers -1, 0 and 1, so
139 ;; we treat them as signed entities; see mmix-modes.def. The following
140 ;; expanders should cover all MODE_CC modes, and expand for this pattern.
141 (define_insn "*movcc_expanded"
142 [(set (match_operand 0 "nonimmediate_operand" "=r,x,r,r,m")
143 (match_operand 1 "nonimmediate_operand" "r,r,x,m,r"))]
144 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_CC
145 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_CC"
153 (define_expand "movcc"
154 [(set (match_operand:CC 0 "nonimmediate_operand" "")
155 (match_operand:CC 1 "nonimmediate_operand" ""))]
159 (define_expand "movcc_uns"
160 [(set (match_operand:CC_UNS 0 "nonimmediate_operand" "")
161 (match_operand:CC_UNS 1 "nonimmediate_operand" ""))]
165 (define_expand "movcc_fp"
166 [(set (match_operand:CC_FP 0 "nonimmediate_operand" "")
167 (match_operand:CC_FP 1 "nonimmediate_operand" ""))]
171 (define_expand "movcc_fpeq"
172 [(set (match_operand:CC_FPEQ 0 "nonimmediate_operand" "")
173 (match_operand:CC_FPEQ 1 "nonimmediate_operand" ""))]
177 (define_expand "movcc_fun"
178 [(set (match_operand:CC_FUN 0 "nonimmediate_operand" "")
179 (match_operand:CC_FUN 1 "nonimmediate_operand" ""))]
183 (define_insn "adddi3"
184 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
186 (match_operand:DI 1 "register_operand" "%r,r,0")
187 (match_operand:DI 2 "mmix_reg_or_constant_operand" "rI,K,LS")))]
194 (define_insn "adddf3"
195 [(set (match_operand:DF 0 "register_operand" "=r")
196 (plus:DF (match_operand:DF 1 "register_operand" "%r")
197 (match_operand:DF 2 "register_operand" "r")))]
201 ;; Insn canonicalization *should* have removed the need for an integer
203 (define_insn "subdi3"
204 [(set (match_operand:DI 0 "register_operand" "=r,r")
205 (minus:DI (match_operand:DI 1 "mmix_reg_or_8bit_operand" "r,I")
206 (match_operand:DI 2 "register_operand" "r,r")))]
212 (define_insn "subdf3"
213 [(set (match_operand:DF 0 "register_operand" "=r")
214 (minus:DF (match_operand:DF 1 "register_operand" "r")
215 (match_operand:DF 2 "register_operand" "r")))]
219 ;; FIXME: Should we define_expand and match 2, 4, 8 (etc) with shift (or
220 ;; %{something}2ADDU %0,%1,0)? Hopefully GCC should still handle it, so
221 ;; we don't have to taint the machine description. If results are bad
222 ;; enough, we may have to do it anyway.
223 (define_insn "muldi3"
224 [(set (match_operand:DI 0 "register_operand" "=r,r")
225 (mult:DI (match_operand:DI 1 "register_operand" "%r,r")
226 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "O,rI")))
227 (clobber (match_scratch:DI 3 "=X,z"))]
233 (define_insn "muldf3"
234 [(set (match_operand:DF 0 "register_operand" "=r")
235 (mult:DF (match_operand:DF 1 "register_operand" "r")
236 (match_operand:DF 2 "register_operand" "r")))]
240 (define_insn "divdf3"
241 [(set (match_operand:DF 0 "register_operand" "=r")
242 (div:DF (match_operand:DF 1 "register_operand" "r")
243 (match_operand:DF 2 "register_operand" "r")))]
247 ;; FIXME: Is "frem" doing the right operation for moddf3?
248 (define_insn "moddf3"
249 [(set (match_operand:DF 0 "register_operand" "=r")
250 (mod:DF (match_operand:DF 1 "register_operand" "r")
251 (match_operand:DF 2 "register_operand" "r")))]
255 ;; FIXME: Should we define_expand for smin, smax, umin, umax using a
256 ;; nifty conditional sequence?
258 ;; FIXME: The cuter andn combinations don't get here, presumably because
259 ;; they ended up in the constant pool. Check: still?
260 (define_insn "anddi3"
261 [(set (match_operand:DI 0 "register_operand" "=r,r")
263 (match_operand:DI 1 "register_operand" "%r,0")
264 (match_operand:DI 2 "mmix_reg_or_constant_operand" "rI,NT")))]
270 (define_insn "iordi3"
271 [(set (match_operand:DI 0 "register_operand" "=r,r")
272 (ior:DI (match_operand:DI 1 "register_operand" "%r,0")
273 (match_operand:DI 2 "mmix_reg_or_constant_operand" "rH,LS")))]
279 (define_insn "xordi3"
280 [(set (match_operand:DI 0 "register_operand" "=r")
281 (xor:DI (match_operand:DI 1 "register_operand" "%r")
282 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
286 ;; FIXME: When TImode works for other reasons (like cross-compiling from
287 ;; a 32-bit host), add back umulditi3 and umuldi3_highpart here.
289 ;; FIXME: Check what's really reasonable for the mod part.
291 ;; One day we might persuade GCC to expand divisions with constants the
292 ;; way MMIX does; giving the remainder the sign of the divisor. But even
293 ;; then, it might be good to have an option to divide the way "everybody
294 ;; else" does. Perhaps then, this option can be on by default. However,
295 ;; it's not likely to happen because major (C, C++, Fortran) language
296 ;; standards in effect at 2002-04-29 reportedly demand that the sign of
297 ;; the remainder must follow the sign of the dividend.
299 (define_insn "divmoddi4"
300 [(set (match_operand:DI 0 "register_operand" "=r")
301 (div:DI (match_operand:DI 1 "register_operand" "r")
302 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))
303 (set (match_operand:DI 3 "register_operand" "=y")
304 (mod:DI (match_dup 1) (match_dup 2)))]
305 ;; Do the library stuff later.
306 "TARGET_KNUTH_DIVISION"
309 (define_insn "udivmoddi4"
310 [(set (match_operand:DI 0 "register_operand" "=r")
311 (udiv:DI (match_operand:DI 1 "register_operand" "r")
312 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))
313 (set (match_operand:DI 3 "register_operand" "=y")
314 (umod:DI (match_dup 1) (match_dup 2)))]
318 (define_expand "divdi3"
320 [(set (match_operand:DI 0 "register_operand" "=&r")
321 (div:DI (match_operand:DI 1 "register_operand" "r")
322 (match_operand:DI 2 "register_operand" "r")))
323 (clobber (scratch:DI))
324 (clobber (scratch:DI))
325 (clobber (reg:DI MMIX_rR_REGNUM))])]
326 "! TARGET_KNUTH_DIVISION"
329 ;; The %2-is-%1-case is there just to make sure things don't fail. Could
330 ;; presumably happen with optimizations off; no evidence.
331 (define_insn "*divdi3_nonknuth"
332 [(set (match_operand:DI 0 "register_operand" "=&r,r")
333 (div:DI (match_operand:DI 1 "register_operand" "r,r")
334 (match_operand:DI 2 "register_operand" "1,r")))
335 (clobber (match_scratch:DI 3 "=1,1"))
336 (clobber (match_scratch:DI 4 "=2,2"))
337 (clobber (reg:DI MMIX_rR_REGNUM))]
338 "! TARGET_KNUTH_DIVISION"
341 XOR $255,%1,%2\;NEGU %0,0,%2\;CSN %2,%2,%0\;NEGU %0,0,%1\;CSN %1,%1,%0\;\
342 DIVU %0,%1,%2\;NEGU %1,0,%0\;CSN %0,$255,%1")
344 (define_expand "moddi3"
346 [(set (match_operand:DI 0 "register_operand" "=&r")
347 (mod:DI (match_operand:DI 1 "register_operand" "r")
348 (match_operand:DI 2 "register_operand" "r")))
349 (clobber (scratch:DI))
350 (clobber (scratch:DI))
351 (clobber (reg:DI MMIX_rR_REGNUM))])]
352 "! TARGET_KNUTH_DIVISION"
355 ;; The %2-is-%1-case is there just to make sure things don't fail. Could
356 ;; presumably happen with optimizations off; no evidence.
357 (define_insn "*moddi3_nonknuth"
358 [(set (match_operand:DI 0 "register_operand" "=&r,r")
359 (mod:DI (match_operand:DI 1 "register_operand" "r,r")
360 (match_operand:DI 2 "register_operand" "1,r")))
361 (clobber (match_scratch:DI 3 "=1,1"))
362 (clobber (match_scratch:DI 4 "=2,2"))
363 (clobber (reg:DI MMIX_rR_REGNUM))]
364 "! TARGET_KNUTH_DIVISION"
367 NEGU %0,0,%2\;CSN %2,%2,%0\;NEGU $255,0,%1\;CSN %1,%1,$255\;\
368 DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
370 (define_insn "ashldi3"
371 [(set (match_operand:DI 0 "register_operand" "=r")
373 (match_operand:DI 1 "register_operand" "r")
374 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
378 (define_insn "ashrdi3"
379 [(set (match_operand:DI 0 "register_operand" "=r")
381 (match_operand:DI 1 "register_operand" "r")
382 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
386 (define_insn "lshrdi3"
387 [(set (match_operand:DI 0 "register_operand" "=r")
389 (match_operand:DI 1 "register_operand" "r")
390 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
394 (define_insn "negdi2"
395 [(set (match_operand:DI 0 "register_operand" "=r")
396 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
400 (define_expand "negdf2"
401 [(parallel [(set (match_operand:DF 0 "register_operand" "=r")
402 (neg:DF (match_operand:DF 1 "register_operand" "r")))
403 (use (match_dup 2))])]
406 /* Emit bit-flipping sequence to be IEEE-safe wrt. -+0. */
407 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
410 (define_insn "*expanded_negdf2"
411 [(set (match_operand:DF 0 "register_operand" "=r")
412 (neg:DF (match_operand:DF 1 "register_operand" "r")))
413 (use (match_operand:DI 2 "register_operand" "r"))]
417 ;; FIXME: define_expand for absdi2?
419 (define_insn "absdf2"
420 [(set (match_operand:DF 0 "register_operand" "=r")
421 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
425 (define_insn "sqrtdf2"
426 [(set (match_operand:DF 0 "register_operand" "=r")
427 (sqrt:DF (match_operand:DF 1 "register_operand" "r")))]
431 ;; FIXME: define_expand for ffssi2? (not ffsdi2 since int is SImode).
433 (define_insn "one_cmpldi2"
434 [(set (match_operand:DI 0 "register_operand" "=r")
435 (not:DI (match_operand:DI 1 "register_operand" "r")))]
439 ;; Since we don't have cc0, we do what is recommended in the manual;
440 ;; store away the operands for use in the branch, scc or movcc insn.
441 (define_expand "cmpdi"
442 [(match_operand:DI 0 "register_operand" "")
443 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "")]
447 mmix_compare_op0 = operands[0];
448 mmix_compare_op1 = operands[1];
452 (define_expand "cmpdf"
453 [(match_operand:DF 0 "register_operand" "")
454 (match_operand:DF 1 "register_operand" "")]
458 mmix_compare_op0 = operands[0];
459 mmix_compare_op1 = operands[1];
463 ;; When the user-patterns expand, the resulting insns will match the
466 ;; We can fold the signed-compare where the register value is
467 ;; already equal to (compare:CCTYPE (reg) (const_int 0)).
468 ;; We can't do that at all for floating-point, due to NaN, +0.0
469 ;; and -0.0, and we can only do it for the non/zero test of
470 ;; unsigned, so that has to be done another way.
471 ;; FIXME: Perhaps a peep2 changing CCcode to a new code, that
473 (define_insn "*cmpcc_folded"
474 [(set (match_operand:CC 0 "register_operand" "=r")
476 (match_operand:DI 1 "register_operand" "r")
478 ;; FIXME: Can we test equivalence any other way?
479 ;; FIXME: Can we fold any other way?
480 "REGNO (operands[1]) == REGNO (operands[0])"
481 "%% folded: cmp %0,%1,0")
483 (define_insn "*cmpcc"
484 [(set (match_operand:CC 0 "register_operand" "=r")
486 (match_operand:DI 1 "register_operand" "r")
487 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
492 [(set (match_operand:CC_UNS 0 "register_operand" "=r")
494 (match_operand:DI 1 "register_operand" "r")
495 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
500 [(set (match_operand:CC_FP 0 "register_operand" "=r")
502 (match_operand:DF 1 "register_operand" "r")
503 (match_operand:DF 2 "register_operand" "r")))]
507 ;; FIXME: for -mieee, add fsub %0,%1,%1\;fsub %0,%2,%2 before to
508 ;; make signalling compliant.
510 [(set (match_operand:CC_FPEQ 0 "register_operand" "=r")
512 (match_operand:DF 1 "register_operand" "r")
513 (match_operand:DF 2 "register_operand" "r")))]
518 [(set (match_operand:CC_FUN 0 "register_operand" "=r")
520 (match_operand:DF 1 "register_operand" "r")
521 (match_operand:DF 2 "register_operand" "r")))]
525 ;; In order to get correct rounding, we have to use SFLOT and SFLOTU for
526 ;; conversion. They do not convert to SFmode; they convert to DFmode,
527 ;; with rounding as of SFmode. They are not usable as is, but we pretend
528 ;; we have a single instruction but emit two.
530 ;; Note that this will (somewhat unexpectedly) create an inexact
531 ;; exception if rounding is necessary - has to be masked off in crt0?
532 (define_expand "floatdisf2"
533 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "=rm")
535 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
536 ;; Let's use a DI scratch, since SF don't generally get into
537 ;; registers. Dunno what's best; it's really a DF, but that
538 ;; doesn't logically follow from operands in the pattern.
539 (clobber (match_scratch:DI 2 "=&r"))])]
543 if (GET_CODE (operands[0]) != MEM)
547 /* FIXME: This stack-slot remains even at -O3. There must be a
550 = validize_mem (assign_stack_temp (SFmode,
551 GET_MODE_SIZE (SFmode), 0));
552 emit_insn (gen_floatdisf2 (stack_slot, operands[1]));
553 emit_move_insn (operands[0], stack_slot);
558 (define_insn "*floatdisf2_real"
559 [(set (match_operand:SF 0 "memory_operand" "=m")
561 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
562 (clobber (match_scratch:DI 2 "=&r"))]
564 "SFLOT %2,%1\;STSF %2,%0")
566 (define_expand "floatunsdisf2"
567 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "=rm")
569 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
570 ;; Let's use a DI scratch, since SF don't generally get into
571 ;; registers. Dunno what's best; it's really a DF, but that
572 ;; doesn't logically follow from operands in the pattern.
573 (clobber (scratch:DI))])]
577 if (GET_CODE (operands[0]) != MEM)
581 /* FIXME: This stack-slot remains even at -O3. Must be a better
584 = validize_mem (assign_stack_temp (SFmode,
585 GET_MODE_SIZE (SFmode), 0));
586 emit_insn (gen_floatunsdisf2 (stack_slot, operands[1]));
587 emit_move_insn (operands[0], stack_slot);
592 (define_insn "*floatunsdisf2_real"
593 [(set (match_operand:SF 0 "memory_operand" "=m")
595 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
596 (clobber (match_scratch:DI 2 "=&r"))]
598 "SFLOTU %2,%1\;STSF %2,%0")
600 ;; Note that this will (somewhat unexpectedly) create an inexact
601 ;; exception if rounding is necessary - has to be masked off in crt0?
602 (define_insn "floatdidf2"
603 [(set (match_operand:DF 0 "register_operand" "=r")
605 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))]
609 (define_insn "floatunsdidf2"
610 [(set (match_operand:DF 0 "register_operand" "=r")
612 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))]
616 (define_insn "ftruncdf2"
617 [(set (match_operand:DF 0 "register_operand" "=r")
618 (fix:DF (match_operand:DF 1 "register_operand" "r")))]
623 ;; Note that this will (somewhat unexpectedly) create an inexact
624 ;; exception if rounding is necessary - has to be masked off in crt0?
625 (define_insn "fix_truncdfdi2"
626 [(set (match_operand:DI 0 "register_operand" "=r")
627 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "r"))))]
632 (define_insn "fixuns_truncdfdi2"
633 [(set (match_operand:DI 0 "register_operand" "=r")
635 (fix:DF (match_operand:DF 1 "register_operand" "r"))))]
640 ;; It doesn't seem like it's possible to have memory_operand as a
641 ;; predicate here (testcase: libgcc2 floathisf). FIXME: Shouldn't it be
642 ;; possible to do that? Bug in GCC? Anyway, this used to be a simple
643 ;; pattern with a memory_operand predicate, but was split up with a
644 ;; define_expand with the old pattern as "anonymous".
645 ;; FIXME: Perhaps with SECONDARY_MEMORY_NEEDED?
646 (define_expand "truncdfsf2"
647 [(set (match_operand:SF 0 "memory_operand" "")
648 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
652 if (GET_CODE (operands[0]) != MEM)
654 /* FIXME: There should be a way to say: 'put this in operands[0]
655 but *after* the expanded insn'. */
658 /* There is no sane destination but a register here, if it wasn't
659 already MEM. (It's too hard to get fatal_insn to work here.) */
660 if (! REG_P (operands[0]))
661 internal_error (\"MMIX Internal: Bad truncdfsf2 expansion\");
663 /* FIXME: This stack-slot remains even at -O3. Must be a better
666 = validize_mem (assign_stack_temp (SFmode,
667 GET_MODE_SIZE (SFmode), 0));
668 emit_insn (gen_truncdfsf2 (stack_slot, operands[1]));
669 emit_move_insn (operands[0], stack_slot);
674 (define_insn "*truncdfsf2_real"
675 [(set (match_operand:SF 0 "memory_operand" "=m")
676 (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
680 ;; Same comment as for truncdfsf2.
681 (define_expand "extendsfdf2"
682 [(set (match_operand:DF 0 "register_operand" "=r")
683 (float_extend:DF (match_operand:SF 1 "memory_operand" "m")))]
687 if (GET_CODE (operands[1]) != MEM)
691 /* There is no sane destination but a register here, if it wasn't
692 already MEM. (It's too hard to get fatal_insn to work here.) */
693 if (! REG_P (operands[0]))
694 internal_error (\"MMIX Internal: Bad extendsfdf2 expansion\");
696 /* FIXME: This stack-slot remains even at -O3. There must be a
699 = validize_mem (assign_stack_temp (SFmode,
700 GET_MODE_SIZE (SFmode), 0));
701 emit_move_insn (stack_slot, operands[1]);
702 emit_insn (gen_extendsfdf2 (operands[0], stack_slot));
707 (define_insn "*extendsfdf2_real"
708 [(set (match_operand:DF 0 "register_operand" "=r")
709 (float_extend:DF (match_operand:SF 1 "memory_operand" "m")))]
713 ;; Neither sign-extend nor zero-extend are necessary; gcc knows how to
714 ;; synthesize using shifts or and, except with a memory source and not
715 ;; completely optimal. FIXME: Actually, other bugs surface when those
716 ;; patterns are defined; fix later.
718 ;; There are no sane values with the bit-patterns of (int) 0..255 except
719 ;; 0 to use in movdfcc.
721 (define_expand "movdfcc"
722 [(set (match_operand:DF 0 "register_operand" "")
724 (match_operand 1 "comparison_operator" "")
725 (match_operand:DF 2 "mmix_reg_or_0_operand" "")
726 (match_operand:DF 3 "mmix_reg_or_0_operand" "")))]
730 enum rtx_code code = GET_CODE (operands[1]);
731 rtx cc_reg = mmix_gen_compare_reg (code, mmix_compare_op0,
733 if (cc_reg == NULL_RTX)
735 operands[1] = gen_rtx (code, VOIDmode, cc_reg, const0_rtx);
738 (define_expand "movdicc"
739 [(set (match_operand:DI 0 "register_operand" "")
741 (match_operand 1 "comparison_operator" "")
742 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "")
743 (match_operand:DI 3 "mmix_reg_or_8bit_operand" "")))]
747 enum rtx_code code = GET_CODE (operands[1]);
748 rtx cc_reg = mmix_gen_compare_reg (code, mmix_compare_op0,
750 if (cc_reg == NULL_RTX)
752 operands[1] = gen_rtx (code, VOIDmode, cc_reg, const0_rtx);
755 ;; FIXME: Is this the right way to do "folding" of CCmode -> DImode?
756 (define_insn "*movdicc_real_foldable"
757 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
759 (match_operator 2 "mmix_foldable_comparison_operator"
760 [(match_operand 3 "register_operand" "r,r,r,r")
762 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI,0 ,rI,GM")
763 (match_operand:DI 4 "mmix_reg_or_8bit_operand" "0 ,rI,GM,rI")))]
771 (define_insn "*movdicc_real"
773 (match_operand:DI 0 "register_operand" "=r ,r ,r ,r")
776 2 "mmix_comparison_operator"
777 [(match_operand 3 "mmix_reg_cc_operand" "r ,r ,r ,r")
779 (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI,0 ,rI,GM")
780 (match_operand:DI 4 "mmix_reg_or_8bit_operand" "0 ,rI,GM,rI")))]
788 (define_insn "*movdfcc_real_foldable"
790 (match_operand:DF 0 "register_operand" "=r ,r ,r ,r")
793 2 "mmix_foldable_comparison_operator"
794 [(match_operand 3 "register_operand" "r ,r ,r ,r")
796 (match_operand:DF 1 "mmix_reg_or_0_operand" "rGM,0 ,rGM,GM")
797 (match_operand:DF 4 "mmix_reg_or_0_operand" "0 ,rGM,GM ,rGM")))]
805 (define_insn "*movdfcc_real"
807 (match_operand:DF 0 "register_operand" "=r ,r ,r ,r")
810 2 "mmix_comparison_operator"
811 [(match_operand 3 "mmix_reg_cc_operand" "r ,r ,r ,r")
813 (match_operand:DF 1 "mmix_reg_or_0_operand" "rGM,0 ,rGM,GM")
814 (match_operand:DF 4 "mmix_reg_or_0_operand" "0 ,rGM,GM ,rGM")))]
822 ;; FIXME: scc patterns will probably help, I just skip them
823 ;; right now. Revisit.
827 (if_then_else (eq (match_dup 1) (const_int 0))
828 (label_ref (match_operand 0 "" ""))
834 = mmix_gen_compare_reg (EQ, mmix_compare_op0, mmix_compare_op1);
839 (if_then_else (ne (match_dup 1) (const_int 0))
840 (label_ref (match_operand 0 "" ""))
846 = mmix_gen_compare_reg (NE, mmix_compare_op0, mmix_compare_op1);
851 (if_then_else (gt (match_dup 1) (const_int 0))
852 (label_ref (match_operand 0 "" ""))
858 = mmix_gen_compare_reg (GT, mmix_compare_op0, mmix_compare_op1);
863 (if_then_else (le (match_dup 1) (const_int 0))
864 (label_ref (match_operand 0 "" ""))
870 = mmix_gen_compare_reg (LE, mmix_compare_op0, mmix_compare_op1);
872 /* The head comment of optabs.c:can_compare_p says we're required to
873 implement this, so we have to clean up the mess here. */
874 if (operands[1] == NULL_RTX)
876 /* FIXME: Watch out for sharing/unsharing of rtx:es. */
877 emit_jump_insn ((*bcc_gen_fctn[(int) LT]) (operands[0]));
878 emit_jump_insn ((*bcc_gen_fctn[(int) EQ]) (operands[0]));
885 (if_then_else (ge (match_dup 1) (const_int 0))
886 (label_ref (match_operand 0 "" ""))
892 = mmix_gen_compare_reg (GE, mmix_compare_op0, mmix_compare_op1);
894 /* The head comment of optabs.c:can_compare_p says we're required to
895 implement this, so we have to clean up the mess here. */
896 if (operands[1] == NULL_RTX)
898 /* FIXME: Watch out for sharing/unsharing of rtx:es. */
899 emit_jump_insn ((*bcc_gen_fctn[(int) GT]) (operands[0]));
900 emit_jump_insn ((*bcc_gen_fctn[(int) EQ]) (operands[0]));
907 (if_then_else (lt (match_dup 1) (const_int 0))
908 (label_ref (match_operand 0 "" ""))
914 = mmix_gen_compare_reg (LT, mmix_compare_op0, mmix_compare_op1);
917 (define_expand "bgtu"
919 (if_then_else (gtu (match_dup 1) (const_int 0))
920 (label_ref (match_operand 0 "" ""))
926 = mmix_gen_compare_reg (GTU, mmix_compare_op0, mmix_compare_op1);
929 (define_expand "bleu"
931 (if_then_else (leu (match_dup 1) (const_int 0))
932 (label_ref (match_operand 0 "" ""))
938 = mmix_gen_compare_reg (LEU, mmix_compare_op0, mmix_compare_op1);
941 (define_expand "bgeu"
943 (if_then_else (geu (match_dup 1) (const_int 0))
944 (label_ref (match_operand 0 "" ""))
950 = mmix_gen_compare_reg (GEU, mmix_compare_op0, mmix_compare_op1);
953 (define_expand "bltu"
955 (if_then_else (ltu (match_dup 1) (const_int 0))
956 (label_ref (match_operand 0 "" ""))
962 = mmix_gen_compare_reg (LTU, mmix_compare_op0, mmix_compare_op1);
965 (define_expand "bunordered"
967 (if_then_else (unordered (match_dup 1) (const_int 0))
968 (label_ref (match_operand 0 "" ""))
974 = mmix_gen_compare_reg (UNORDERED, mmix_compare_op0, mmix_compare_op1);
976 if (operands[1] == NULL_RTX)
980 (define_expand "bordered"
982 (if_then_else (ordered (match_dup 1) (const_int 0))
983 (label_ref (match_operand 0 "" ""))
989 = mmix_gen_compare_reg (ORDERED, mmix_compare_op0, mmix_compare_op1);
992 ;; FIXME: we can emit an unordered-or-*not*-equal compare in one insn, but
993 ;; there's no RTL code for it. Maybe revisit in future.
995 ;; FIXME: Odd/Even matchers?
996 (define_insn "*bCC_foldable"
999 (match_operator 1 "mmix_foldable_comparison_operator"
1000 [(match_operand 2 "register_operand" "r")
1002 (label_ref (match_operand 0 "" ""))
1010 (match_operator 1 "mmix_comparison_operator"
1011 [(match_operand 2 "mmix_reg_cc_operand" "r")
1013 (label_ref (match_operand 0 "" ""))
1018 (define_insn "*bCC_inverted_foldable"
1021 (match_operator 1 "mmix_foldable_comparison_operator"
1022 [(match_operand 2 "register_operand" "r")
1025 (label_ref (match_operand 0 "" ""))))]
1026 ;; REVERSIBLE_CC_MODE is checked by mmix_foldable_comparison_operator.
1030 (define_insn "*bCC_inverted"
1033 (match_operator 1 "mmix_comparison_operator"
1034 [(match_operand 2 "mmix_reg_cc_operand" "r")
1037 (label_ref (match_operand 0 "" ""))))]
1038 "REVERSIBLE_CC_MODE (GET_MODE (operands[2]))"
1041 (define_expand "call"
1042 [(parallel [(call (match_operand:QI 0 "memory_operand" "")
1043 (match_operand 1 "general_operand" ""))
1044 (use (match_operand 2 "general_operand" ""))
1045 (clobber (match_dup 4))])
1046 (set (match_dup 4) (match_dup 3))]
1050 /* Since the epilogue 'uses' the return address, and it is clobbered
1051 in the call, and we set it back after every call (all but one setting
1052 will be optimized away), integrity is maintained. */
1054 = mmix_get_hard_reg_initial_val (Pmode,
1055 MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
1057 /* FIXME: There's a bug in gcc which causes NULL to be passed as
1058 operand[2] when we get out of registers, which later confuses gcc.
1059 Work around it by replacing it with const_int 0. Possibly documentation
1061 if (operands[2] == NULL_RTX)
1062 operands[2] = const0_rtx;
1064 operands[4] = gen_rtx_REG (DImode, MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
1067 (define_expand "call_value"
1068 [(parallel [(set (match_operand 0 "" "")
1069 (call (match_operand:QI 1 "memory_operand" "")
1070 (match_operand 2 "general_operand" "")))
1071 (use (match_operand 3 "general_operand" ""))
1072 (clobber (match_dup 5))])
1073 (set (match_dup 5) (match_dup 4))]
1077 /* Since the epilogue 'uses' the return address, and it is clobbered
1078 in the call, and we set it back after every call (all but one setting
1079 will be optimized away), integrity is maintained. */
1081 = mmix_get_hard_reg_initial_val (Pmode,
1082 MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
1084 /* FIXME: See 'call'. */
1085 if (operands[3] == NULL_RTX)
1086 operands[3] = const0_rtx;
1088 /* FIXME: Documentation bug: operands[3] (operands[2] for 'call') is the
1089 *next* argument register, not the number of arguments in registers.
1090 (There used to be code here where that mattered.) */
1092 operands[5] = gen_rtx_REG (DImode, MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
1095 ;; Don't use 'p' here. A 'p' must stand first in constraints, or reload
1096 ;; messes up, not registering the address for reload. Several C++
1097 ;; test-cases, including g++.brendan/crash40.C. FIXME: This is arguably a
1098 ;; bug in gcc. Note line ~2612 in reload.c, that does things on the
1099 ;; condition <<else if (constraints[i][0] == 'p')>> and the comment on
1102 ;; /* All necessary reloads for an address_operand
1103 ;; were handled in find_reloads_address. */>>
1104 ;; Sorry, I have not dug deeper. If symbolic addresses are used
1105 ;; rarely compared to addresses in registers, disparaging the
1106 ;; first ("p") alternative by adding ? in the first operand
1107 ;; might do the trick. We define 'U' as a synonym to 'p', but without the
1108 ;; caveats (and very small advantages) of 'p'.
1109 (define_insn "*call_real"
1111 (match_operand:DI 0 "mmix_symbolic_or_address_operand" "s,rU"))
1112 (match_operand 1 "" ""))
1113 (use (match_operand 2 "" ""))
1114 (clobber (reg:DI MMIX_rJ_REGNUM))]
1120 (define_insn "*call_value_real"
1121 [(set (match_operand 0 "register_operand" "=r,r")
1123 (match_operand:DI 1 "mmix_symbolic_or_address_operand" "s,rU"))
1124 (match_operand 2 "" "")))
1125 (use (match_operand 3 "" ""))
1126 (clobber (reg:DI MMIX_rJ_REGNUM))]
1132 ;; I hope untyped_call and untyped_return are not needed for MMIX.
1133 ;; Users of Objective-C will notice.
1136 (define_expand "return"
1138 "mmix_use_simple_return ()"
1141 ; Generated by the epilogue expander.
1142 (define_insn "*expanded_return"
1147 (define_expand "prologue"
1150 "mmix_expand_prologue (); DONE;")
1152 ; Note that the (return) from the expander itself is always the last insn
1154 (define_expand "epilogue"
1157 "mmix_expand_epilogue ();")
1165 [(set (pc) (label_ref (match_operand 0 "" "")))]
1169 (define_insn "indirect_jump"
1170 [(set (pc) (match_operand 0 "address_operand" "p"))]
1174 ;; FIXME: This is just a jump, and should be expanded to one.
1175 (define_insn "tablejump"
1176 [(set (pc) (match_operand:DI 0 "address_operand" "p"))
1177 (use (label_ref (match_operand 1 "" "")))]
1181 ;; The only peculiar thing is that the register stack has to be unwound at
1182 ;; nonlocal_goto_receiver. At each function that has a nonlocal label, we
1183 ;; save at function entry the location of the "alpha" register stack
1184 ;; pointer, rO, in a stack slot known to that function (right below where
1185 ;; the frame-pointer would be located).
1186 ;; In the nonlocal goto receiver, we unwind the register stack by a series
1187 ;; of "pop 0,0" until rO equals the saved value. (If it goes lower, we
1188 ;; should call abort.)
1189 (define_expand "nonlocal_goto_receiver"
1190 [(parallel [(unspec_volatile [(const_int 0)] 1)
1191 (clobber (scratch:DI))
1192 (clobber (reg:DI MMIX_rJ_REGNUM))])
1193 (set (reg:DI MMIX_rJ_REGNUM) (match_dup 0))]
1198 = mmix_get_hard_reg_initial_val (Pmode,
1199 MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
1201 /* Mark this function as containing a landing-pad. */
1202 cfun->machine->has_landing_pad = 1;
1205 ;; GCC can insist on using saved registers to keep the slot address in
1206 ;; "across" the exception, or (perhaps) to use saved registers in the
1207 ;; address and re-use them after the register stack unwind, so it's best
1208 ;; to form the address ourselves.
1209 (define_insn "*nonlocal_goto_receiver_expanded"
1210 [(unspec_volatile [(const_int 0)] 1)
1211 (clobber (match_scratch:DI 0 "=&r"))
1212 (clobber (reg:DI MMIX_rJ_REGNUM))]
1215 rtx temp_reg = operands[0];
1217 HOST_WIDEST_INT offs;
1218 const char *my_template
1219 = "GETA $255,0f\;PUT rJ,$255\;LDOU $255,%a0\n\
1220 0:\;GET %1,rO\;CMPU %1,%1,$255\;BNP %1,1f\;POP 0,0\n1:";
1222 my_operands[1] = temp_reg;
1224 /* If we have a frame-pointer (hence unknown stack-pointer offset),
1225 just use the frame-pointer and the known offset. */
1226 if (frame_pointer_needed)
1228 my_operands[0] = GEN_INT (-MMIX_fp_rO_OFFSET);
1230 output_asm_insn ("NEGU %1,0,%0", my_operands);
1231 my_operands[0] = gen_rtx_PLUS (Pmode, frame_pointer_rtx, temp_reg);
1235 /* We know the fp-based offset, so "eliminate" it to be sp-based. */
1237 = (mmix_initial_elimination_offset (MMIX_FRAME_POINTER_REGNUM,
1238 MMIX_STACK_POINTER_REGNUM)
1239 + MMIX_fp_rO_OFFSET);
1241 if (offs >= 0 && offs <= 255)
1243 = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offs));
1246 mmix_output_register_setting (asm_out_file, REGNO (temp_reg),
1248 my_operands[0] = gen_rtx_PLUS (Pmode, stack_pointer_rtx, temp_reg);
1252 output_asm_insn (my_template, my_operands);
1256 (define_insn "*Naddu"
1257 [(set (match_operand:DI 0 "register_operand" "=r")
1258 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "r")
1259 (match_operand:DI 2 "const_int_operand" "n"))
1260 (match_operand:DI 3 "mmix_reg_or_8bit_operand" "rI")))]
1261 "GET_CODE (operands[2]) == CONST_INT
1262 && (INTVAL (operands[2]) == 2
1263 || INTVAL (operands[2]) == 4
1264 || INTVAL (operands[2]) == 8
1265 || INTVAL (operands[2]) == 16)"
1268 (define_insn "*andn"
1269 [(set (match_operand:DI 0 "register_operand" "=r")
1271 (not:DI (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI"))
1272 (match_operand:DI 2 "register_operand" "r")))]
1276 (define_insn "*nand"
1277 [(set (match_operand:DI 0 "register_operand" "=r")
1279 (not:DI (match_operand:DI 1 "register_operand" "%r"))
1280 (not:DI (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI"))))]
1285 [(set (match_operand:DI 0 "register_operand" "=r")
1287 (not:DI (match_operand:DI 1 "register_operand" "%r"))
1288 (not:DI (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI"))))]
1292 (define_insn "*nxor"
1293 [(set (match_operand:DI 0 "register_operand" "=r")
1295 (xor:DI (match_operand:DI 1 "register_operand" "%r")
1296 (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI"))))]
1300 (define_insn "sync_icache"
1301 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")
1302 (match_operand:DI 1 "const_int_operand" "I")] 0)]
1308 ;; indent-tabs-mode: t