1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
5 ;; Changes by Michael Meissner, meissner@osf.org
6 ;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 ;; Brendan Eich, brendan@microunity.com.
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 2, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING. If not, write to
23 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 ;; Boston, MA 02110-1301, USA.
27 [(UNSPEC_LOAD_DF_LOW 0)
28 (UNSPEC_LOAD_DF_HIGH 1)
29 (UNSPEC_STORE_DF_HIGH 2)
33 (UNSPEC_EH_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
51 (UNSPEC_ADDRESS_FIRST 100)
55 ;; For MIPS Paired-Singled Floating Point Instructions.
57 (UNSPEC_MOVE_TF_PS 200)
60 ;; MIPS64/MIPS32R2 alnv.ps
63 ;; MIPS-3D instructions
67 (UNSPEC_CVT_PW_PS 205)
68 (UNSPEC_CVT_PS_PW 206)
75 (UNSPEC_SINGLE_CC 212)
77 ;; MIPS DSP ASE Revision 0.98 3/24/2005
85 (UNSPEC_RADDU_W_QB 307)
87 (UNSPEC_PRECRQ_QB_PH 309)
88 (UNSPEC_PRECRQ_PH_W 310)
89 (UNSPEC_PRECRQ_RS_PH_W 311)
90 (UNSPEC_PRECRQU_S_QB_PH 312)
91 (UNSPEC_PRECEQ_W_PHL 313)
92 (UNSPEC_PRECEQ_W_PHR 314)
93 (UNSPEC_PRECEQU_PH_QBL 315)
94 (UNSPEC_PRECEQU_PH_QBR 316)
95 (UNSPEC_PRECEQU_PH_QBLA 317)
96 (UNSPEC_PRECEQU_PH_QBRA 318)
97 (UNSPEC_PRECEU_PH_QBL 319)
98 (UNSPEC_PRECEU_PH_QBR 320)
99 (UNSPEC_PRECEU_PH_QBLA 321)
100 (UNSPEC_PRECEU_PH_QBRA 322)
106 (UNSPEC_MULEU_S_PH_QBL 328)
107 (UNSPEC_MULEU_S_PH_QBR 329)
108 (UNSPEC_MULQ_RS_PH 330)
109 (UNSPEC_MULEQ_S_W_PHL 331)
110 (UNSPEC_MULEQ_S_W_PHR 332)
111 (UNSPEC_DPAU_H_QBL 333)
112 (UNSPEC_DPAU_H_QBR 334)
113 (UNSPEC_DPSU_H_QBL 335)
114 (UNSPEC_DPSU_H_QBR 336)
115 (UNSPEC_DPAQ_S_W_PH 337)
116 (UNSPEC_DPSQ_S_W_PH 338)
117 (UNSPEC_MULSAQ_S_W_PH 339)
118 (UNSPEC_DPAQ_SA_L_W 340)
119 (UNSPEC_DPSQ_SA_L_W 341)
120 (UNSPEC_MAQ_S_W_PHL 342)
121 (UNSPEC_MAQ_S_W_PHR 343)
122 (UNSPEC_MAQ_SA_W_PHL 344)
123 (UNSPEC_MAQ_SA_W_PHR 345)
131 (UNSPEC_CMPGU_EQ_QB 353)
132 (UNSPEC_CMPGU_LT_QB 354)
133 (UNSPEC_CMPGU_LE_QB 355)
135 (UNSPEC_PACKRL_PH 357)
137 (UNSPEC_EXTR_R_W 359)
138 (UNSPEC_EXTR_RS_W 360)
139 (UNSPEC_EXTR_S_H 361)
149 (include "predicates.md")
150 (include "constraints.md")
152 ;; ....................
156 ;; ....................
158 (define_attr "got" "unset,xgot_high,load"
159 (const_string "unset"))
161 ;; For jal instructions, this attribute is DIRECT when the target address
162 ;; is symbolic and INDIRECT when it is a register.
163 (define_attr "jal" "unset,direct,indirect"
164 (const_string "unset"))
166 ;; This attribute is YES if the instruction is a jal macro (not a
167 ;; real jal instruction).
169 ;; jal is always a macro in SVR4 PIC since it includes an instruction to
170 ;; restore $gp. Direct jals are also macros in NewABI PIC since they
171 ;; load the target address into $25.
172 (define_attr "jal_macro" "no,yes"
173 (cond [(eq_attr "jal" "direct")
174 (symbol_ref "TARGET_ABICALLS != 0")
175 (eq_attr "jal" "indirect")
176 (symbol_ref "(TARGET_ABICALLS && !TARGET_NEWABI) != 0")]
177 (const_string "no")))
179 ;; Classification of each insn.
180 ;; branch conditional branch
181 ;; jump unconditional jump
182 ;; call unconditional call
183 ;; load load instruction(s)
184 ;; fpload floating point load
185 ;; fpidxload floating point indexed load
186 ;; store store instruction(s)
187 ;; fpstore floating point store
188 ;; fpidxstore floating point indexed store
189 ;; prefetch memory prefetch (register + offset)
190 ;; prefetchx memory indexed prefetch (register + register)
191 ;; condmove conditional moves
192 ;; xfer transfer to/from coprocessor
193 ;; mthilo transfer to hi/lo registers
194 ;; mfhilo transfer from hi/lo registers
195 ;; const load constant
196 ;; arith integer arithmetic and logical instructions
197 ;; shift integer shift instructions
198 ;; slt set less than instructions
199 ;; clz the clz and clo instructions
200 ;; trap trap if instructions
201 ;; imul integer multiply 2 operands
202 ;; imul3 integer multiply 3 operands
203 ;; imadd integer multiply-add
204 ;; idiv integer divide
205 ;; fmove floating point register move
206 ;; fadd floating point add/subtract
207 ;; fmul floating point multiply
208 ;; fmadd floating point multiply-add
209 ;; fdiv floating point divide
210 ;; frdiv floating point reciprocal divide
211 ;; frdiv1 floating point reciprocal divide step 1
212 ;; frdiv2 floating point reciprocal divide step 2
213 ;; fabs floating point absolute value
214 ;; fneg floating point negation
215 ;; fcmp floating point compare
216 ;; fcvt floating point convert
217 ;; fsqrt floating point square root
218 ;; frsqrt floating point reciprocal square root
219 ;; frsqrt1 floating point reciprocal square root step1
220 ;; frsqrt2 floating point reciprocal square root step2
221 ;; multi multiword sequence (or user asm statements)
224 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
225 (cond [(eq_attr "jal" "!unset") (const_string "call")
226 (eq_attr "got" "load") (const_string "load")]
227 (const_string "unknown")))
229 ;; Main data type used by the insn
230 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
231 (const_string "unknown"))
233 ;; Mode for conversion types (fcvt)
234 ;; I2S integer to float single (SI/DI to SF)
235 ;; I2D integer to float double (SI/DI to DF)
236 ;; S2I float to integer (SF to SI/DI)
237 ;; D2I float to integer (DF to SI/DI)
238 ;; D2S double to float single
239 ;; S2D float single to double
241 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
242 (const_string "unknown"))
244 ;; Is this an extended instruction in mips16 mode?
245 (define_attr "extended_mips16" "no,yes"
248 ;; Length of instruction in bytes.
249 (define_attr "length" ""
250 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
251 ;; If a branch is outside this range, we have a choice of two
252 ;; sequences. For PIC, an out-of-range branch like:
257 ;; becomes the equivalent of:
266 ;; where the load address can be up to three instructions long
269 ;; The non-PIC case is similar except that we use a direct
270 ;; jump instead of an la/jr pair. Since the target of this
271 ;; jump is an absolute 28-bit bit address (the other bits
272 ;; coming from the address of the delay slot) this form cannot
273 ;; cross a 256MB boundary. We could provide the option of
274 ;; using la/jr in this case too, but we do not do so at
277 ;; Note that this value does not account for the delay slot
278 ;; instruction, whose length is added separately. If the RTL
279 ;; pattern has no explicit delay slot, mips_adjust_insn_length
280 ;; will add the length of the implicit nop. The values for
281 ;; forward and backward branches will be different as well.
282 (eq_attr "type" "branch")
283 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
284 (le (minus (pc) (match_dup 1)) (const_int 131068)))
286 (ne (symbol_ref "flag_pic") (const_int 0))
290 (eq_attr "got" "load")
292 (eq_attr "got" "xgot_high")
295 (eq_attr "type" "const")
296 (symbol_ref "mips_const_insns (operands[1]) * 4")
297 (eq_attr "type" "load,fpload")
298 (symbol_ref "mips_fetch_insns (operands[1]) * 4")
299 (eq_attr "type" "store,fpstore")
300 (symbol_ref "mips_fetch_insns (operands[0]) * 4")
302 ;; In the worst case, a call macro will take 8 instructions:
304 ;; lui $25,%call_hi(FOO)
306 ;; lw $25,%call_lo(FOO)($25)
312 (eq_attr "jal_macro" "yes")
315 (and (eq_attr "extended_mips16" "yes")
316 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
319 ;; Various VR4120 errata require a nop to be inserted after a macc
320 ;; instruction. The assembler does this for us, so account for
321 ;; the worst-case length here.
322 (and (eq_attr "type" "imadd")
323 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
326 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
327 ;; the result of the second one is missed. The assembler should work
328 ;; around this by inserting a nop after the first dmult.
329 (and (eq_attr "type" "imul,imul3")
330 (and (eq_attr "mode" "DI")
331 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
334 (eq_attr "type" "idiv")
335 (symbol_ref "mips_idiv_insns () * 4")
338 ;; Attribute describing the processor. This attribute must match exactly
339 ;; with the processor_type enumeration in mips.h.
341 "r3000,4kc,4kp,5kc,5kf,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
342 (const (symbol_ref "mips_tune")))
344 ;; The type of hardware hazard associated with this instruction.
345 ;; DELAY means that the next instruction cannot read the result
346 ;; of this one. HILO means that the next two instructions cannot
347 ;; write to HI or LO.
348 (define_attr "hazard" "none,delay,hilo"
349 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
350 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
351 (const_string "delay")
353 (and (eq_attr "type" "xfer")
354 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
355 (const_string "delay")
357 (and (eq_attr "type" "fcmp")
358 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
359 (const_string "delay")
361 ;; The r4000 multiplication patterns include an mflo instruction.
362 (and (eq_attr "type" "imul")
363 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
364 (const_string "hilo")
366 (and (eq_attr "type" "mfhilo")
367 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
368 (const_string "hilo")]
369 (const_string "none")))
371 ;; Is it a single instruction?
372 (define_attr "single_insn" "no,yes"
373 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
375 ;; Can the instruction be put into a delay slot?
376 (define_attr "can_delay" "no,yes"
377 (if_then_else (and (eq_attr "type" "!branch,call,jump")
378 (and (eq_attr "hazard" "none")
379 (eq_attr "single_insn" "yes")))
381 (const_string "no")))
383 ;; Attribute defining whether or not we can use the branch-likely instructions
384 (define_attr "branch_likely" "no,yes"
386 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
388 (const_string "no"))))
390 ;; True if an instruction might assign to hi or lo when reloaded.
391 ;; This is used by the TUNE_MACC_CHAINS code.
392 (define_attr "may_clobber_hilo" "no,yes"
393 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
395 (const_string "no")))
397 ;; Describe a user's asm statement.
398 (define_asm_attributes
399 [(set_attr "type" "multi")
400 (set_attr "can_delay" "no")])
402 ;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
403 ;; from the same template.
404 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
406 ;; This mode macro allows :P to be used for patterns that operate on
407 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
408 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
410 ;; This mode macro allows :MOVECC to be used anywhere that a
411 ;; conditional-move-type condition is needed.
412 (define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
414 ;; This mode macro allows the QI and HI extension patterns to be defined from
415 ;; the same template.
416 (define_mode_macro SHORT [QI HI])
418 ;; This mode macro allows :ANYF to be used wherever a scalar or vector
419 ;; floating-point mode is allowed.
420 (define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
421 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
422 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
424 ;; Like ANYF, but only applies to scalar modes.
425 (define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
426 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
428 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
429 ;; 32-bit version and "dsubu" in the 64-bit version.
430 (define_mode_attr d [(SI "") (DI "d")])
432 ;; This attribute gives the length suffix for a sign- or zero-extension
434 (define_mode_attr size [(QI "b") (HI "h")])
436 ;; This attributes gives the mode mask of a SHORT.
437 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
439 ;; Mode attributes for GPR loads and stores.
440 (define_mode_attr load [(SI "lw") (DI "ld")])
441 (define_mode_attr store [(SI "sw") (DI "sd")])
443 ;; Similarly for MIPS IV indexed FPR loads and stores.
444 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
445 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
447 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
448 ;; are different. Some forms of unextended addiu have an 8-bit immediate
449 ;; field but the equivalent daddiu has only a 5-bit field.
450 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
452 ;; This attribute gives the best constraint to use for registers of
454 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
456 ;; This attribute gives the format suffix for floating-point operations.
457 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
459 ;; This attribute gives the upper-case mode name for one unit of a
460 ;; floating-point mode.
461 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
463 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
465 ;; In certain cases, div.s and div.ps may have a rounding error
466 ;; and/or wrong inexact flag.
468 ;; Therefore, we only allow div.s if not working around SB-1 rev2
469 ;; errata or if a slight loss of precision is OK.
470 (define_mode_attr divide_condition
471 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
472 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
474 ; This attribute gives the condition for which sqrt instructions exist.
475 (define_mode_attr sqrt_condition
476 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
478 ; This attribute gives the condition for which recip and rsqrt instructions
480 (define_mode_attr recip_condition
481 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
483 ;; This code macro allows all branch instructions to be generated from
484 ;; a single define_expand template.
485 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
486 eq ne gt ge lt le gtu geu ltu leu])
488 ;; This code macro allows signed and unsigned widening multiplications
489 ;; to use the same template.
490 (define_code_macro any_extend [sign_extend zero_extend])
492 ;; This code macro allows the three shift instructions to be generated
493 ;; from the same template.
494 (define_code_macro any_shift [ashift ashiftrt lshiftrt])
496 ;; This code macro allows all native floating-point comparisons to be
497 ;; generated from the same template.
498 (define_code_macro fcond [unordered uneq unlt unle eq lt le])
500 ;; This code macro is used for comparisons that can be implemented
501 ;; by swapping the operands.
502 (define_code_macro swapped_fcond [ge gt unge ungt])
504 ;; <u> expands to an empty string when doing a signed operation and
505 ;; "u" when doing an unsigned operation.
506 (define_code_attr u [(sign_extend "") (zero_extend "u")])
508 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
509 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
511 ;; <optab> expands to the name of the optab for a particular code.
512 (define_code_attr optab [(ashift "ashl")
516 ;; <insn> expands to the name of the insn that implements a particular code.
517 (define_code_attr insn [(ashift "sll")
521 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
522 (define_code_attr fcond [(unordered "un")
530 ;; Similar, but for swapped conditions.
531 (define_code_attr swapped_fcond [(ge "le")
536 ;; .........................
538 ;; Branch, call and jump delay slots
540 ;; .........................
542 (define_delay (and (eq_attr "type" "branch")
543 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
544 [(eq_attr "can_delay" "yes")
546 (and (eq_attr "branch_likely" "yes")
547 (eq_attr "can_delay" "yes"))])
549 (define_delay (eq_attr "type" "jump")
550 [(eq_attr "can_delay" "yes")
554 (define_delay (and (eq_attr "type" "call")
555 (eq_attr "jal_macro" "no"))
556 [(eq_attr "can_delay" "yes")
560 ;; Pipeline descriptions.
562 ;; generic.md provides a fallback for processors without a specific
563 ;; pipeline description. It is derived from the old define_function_unit
564 ;; version and uses the "alu" and "imuldiv" units declared below.
566 ;; Some of the processor-specific files are also derived from old
567 ;; define_function_unit descriptions and simply override the parts of
568 ;; generic.md that don't apply. The other processor-specific files
569 ;; are self-contained.
570 (define_automaton "alu,imuldiv")
572 (define_cpu_unit "alu" "alu")
573 (define_cpu_unit "imuldiv" "imuldiv")
592 (include "generic.md")
595 ;; ....................
599 ;; ....................
603 [(trap_if (const_int 1) (const_int 0))]
606 if (ISA_HAS_COND_TRAP)
608 else if (TARGET_MIPS16)
613 [(set_attr "type" "trap")])
615 (define_expand "conditional_trap"
616 [(trap_if (match_operator 0 "comparison_operator"
617 [(match_dup 2) (match_dup 3)])
618 (match_operand 1 "const_int_operand"))]
621 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
622 && operands[1] == const0_rtx)
624 mips_gen_conditional_trap (operands);
631 (define_insn "*conditional_trap<mode>"
632 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
633 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
634 (match_operand:GPR 2 "arith_operand" "dI")])
638 [(set_attr "type" "trap")])
641 ;; ....................
645 ;; ....................
648 (define_insn "add<mode>3"
649 [(set (match_operand:ANYF 0 "register_operand" "=f")
650 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
651 (match_operand:ANYF 2 "register_operand" "f")))]
653 "add.<fmt>\t%0,%1,%2"
654 [(set_attr "type" "fadd")
655 (set_attr "mode" "<UNITMODE>")])
657 (define_expand "add<mode>3"
658 [(set (match_operand:GPR 0 "register_operand")
659 (plus:GPR (match_operand:GPR 1 "register_operand")
660 (match_operand:GPR 2 "arith_operand")))]
663 (define_insn "*add<mode>3"
664 [(set (match_operand:GPR 0 "register_operand" "=d,d")
665 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
666 (match_operand:GPR 2 "arith_operand" "d,Q")))]
671 [(set_attr "type" "arith")
672 (set_attr "mode" "<MODE>")])
674 ;; We need to recognize MIPS16 stack pointer additions explicitly, since
675 ;; we don't have a constraint for $sp. These insns will be generated by
676 ;; the save_restore_insns functions.
678 (define_insn "*add<mode>3_sp1"
680 (plus:GPR (reg:GPR 29)
681 (match_operand:GPR 0 "const_arith_operand" "")))]
684 [(set_attr "type" "arith")
685 (set_attr "mode" "<MODE>")
686 (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8")
690 (define_insn "*add<mode>3_sp2"
691 [(set (match_operand:GPR 0 "register_operand" "=d")
692 (plus:GPR (reg:GPR 29)
693 (match_operand:GPR 1 "const_arith_operand" "")))]
696 [(set_attr "type" "arith")
697 (set_attr "mode" "<MODE>")
698 (set (attr "length") (if_then_else (match_operand 1 "m16_uimm<si8_di5>_4")
702 (define_insn "*add<mode>3_mips16"
703 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
704 (plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d")
705 (match_operand:GPR 2 "arith_operand" "Q,O,d")))]
711 [(set_attr "type" "arith")
712 (set_attr "mode" "<MODE>")
713 (set_attr_alternative "length"
714 [(if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
717 (if_then_else (match_operand 2 "m16_simm4_1")
723 ;; On the mips16, we can sometimes split an add of a constant which is
724 ;; a 4 byte instruction into two adds which are both 2 byte
725 ;; instructions. There are two cases: one where we are adding a
726 ;; constant plus a register to another register, and one where we are
727 ;; simply adding a constant to a register.
730 [(set (match_operand:SI 0 "register_operand")
731 (plus:SI (match_dup 0)
732 (match_operand:SI 1 "const_int_operand")))]
733 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
734 && REG_P (operands[0])
735 && M16_REG_P (REGNO (operands[0]))
736 && GET_CODE (operands[1]) == CONST_INT
737 && ((INTVAL (operands[1]) > 0x7f
738 && INTVAL (operands[1]) <= 0x7f + 0x7f)
739 || (INTVAL (operands[1]) < - 0x80
740 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
741 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
742 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
744 HOST_WIDE_INT val = INTVAL (operands[1]);
748 operands[1] = GEN_INT (0x7f);
749 operands[2] = GEN_INT (val - 0x7f);
753 operands[1] = GEN_INT (- 0x80);
754 operands[2] = GEN_INT (val + 0x80);
759 [(set (match_operand:SI 0 "register_operand")
760 (plus:SI (match_operand:SI 1 "register_operand")
761 (match_operand:SI 2 "const_int_operand")))]
762 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
763 && REG_P (operands[0])
764 && M16_REG_P (REGNO (operands[0]))
765 && REG_P (operands[1])
766 && M16_REG_P (REGNO (operands[1]))
767 && REGNO (operands[0]) != REGNO (operands[1])
768 && GET_CODE (operands[2]) == CONST_INT
769 && ((INTVAL (operands[2]) > 0x7
770 && INTVAL (operands[2]) <= 0x7 + 0x7f)
771 || (INTVAL (operands[2]) < - 0x8
772 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
773 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
774 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
776 HOST_WIDE_INT val = INTVAL (operands[2]);
780 operands[2] = GEN_INT (0x7);
781 operands[3] = GEN_INT (val - 0x7);
785 operands[2] = GEN_INT (- 0x8);
786 operands[3] = GEN_INT (val + 0x8);
791 [(set (match_operand:DI 0 "register_operand")
792 (plus:DI (match_dup 0)
793 (match_operand:DI 1 "const_int_operand")))]
794 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
795 && REG_P (operands[0])
796 && M16_REG_P (REGNO (operands[0]))
797 && GET_CODE (operands[1]) == CONST_INT
798 && ((INTVAL (operands[1]) > 0xf
799 && INTVAL (operands[1]) <= 0xf + 0xf)
800 || (INTVAL (operands[1]) < - 0x10
801 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
802 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
803 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
805 HOST_WIDE_INT val = INTVAL (operands[1]);
809 operands[1] = GEN_INT (0xf);
810 operands[2] = GEN_INT (val - 0xf);
814 operands[1] = GEN_INT (- 0x10);
815 operands[2] = GEN_INT (val + 0x10);
820 [(set (match_operand:DI 0 "register_operand")
821 (plus:DI (match_operand:DI 1 "register_operand")
822 (match_operand:DI 2 "const_int_operand")))]
823 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
824 && REG_P (operands[0])
825 && M16_REG_P (REGNO (operands[0]))
826 && REG_P (operands[1])
827 && M16_REG_P (REGNO (operands[1]))
828 && REGNO (operands[0]) != REGNO (operands[1])
829 && GET_CODE (operands[2]) == CONST_INT
830 && ((INTVAL (operands[2]) > 0x7
831 && INTVAL (operands[2]) <= 0x7 + 0xf)
832 || (INTVAL (operands[2]) < - 0x8
833 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
834 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
835 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
837 HOST_WIDE_INT val = INTVAL (operands[2]);
841 operands[2] = GEN_INT (0x7);
842 operands[3] = GEN_INT (val - 0x7);
846 operands[2] = GEN_INT (- 0x8);
847 operands[3] = GEN_INT (val + 0x8);
851 (define_insn "*addsi3_extended"
852 [(set (match_operand:DI 0 "register_operand" "=d,d")
854 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
855 (match_operand:SI 2 "arith_operand" "d,Q"))))]
856 "TARGET_64BIT && !TARGET_MIPS16"
860 [(set_attr "type" "arith")
861 (set_attr "mode" "SI")])
863 ;; Split this insn so that the addiu splitters can have a crack at it.
864 ;; Use a conservative length estimate until the split.
865 (define_insn_and_split "*addsi3_extended_mips16"
866 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
868 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
869 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
870 "TARGET_64BIT && TARGET_MIPS16"
872 "&& reload_completed"
873 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
874 { operands[3] = gen_lowpart (SImode, operands[0]); }
875 [(set_attr "type" "arith")
876 (set_attr "mode" "SI")
877 (set_attr "extended_mips16" "yes")])
880 ;; ....................
884 ;; ....................
887 (define_insn "sub<mode>3"
888 [(set (match_operand:ANYF 0 "register_operand" "=f")
889 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
890 (match_operand:ANYF 2 "register_operand" "f")))]
892 "sub.<fmt>\t%0,%1,%2"
893 [(set_attr "type" "fadd")
894 (set_attr "mode" "<UNITMODE>")])
896 (define_insn "sub<mode>3"
897 [(set (match_operand:GPR 0 "register_operand" "=d")
898 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
899 (match_operand:GPR 2 "register_operand" "d")))]
902 [(set_attr "type" "arith")
903 (set_attr "mode" "<MODE>")])
905 (define_insn "*subsi3_extended"
906 [(set (match_operand:DI 0 "register_operand" "=d")
908 (minus:SI (match_operand:SI 1 "register_operand" "d")
909 (match_operand:SI 2 "register_operand" "d"))))]
912 [(set_attr "type" "arith")
913 (set_attr "mode" "DI")])
916 ;; ....................
920 ;; ....................
923 (define_expand "mul<mode>3"
924 [(set (match_operand:SCALARF 0 "register_operand")
925 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
926 (match_operand:SCALARF 2 "register_operand")))]
930 (define_insn "*mul<mode>3"
931 [(set (match_operand:SCALARF 0 "register_operand" "=f")
932 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
933 (match_operand:SCALARF 2 "register_operand" "f")))]
934 "!TARGET_4300_MUL_FIX"
935 "mul.<fmt>\t%0,%1,%2"
936 [(set_attr "type" "fmul")
937 (set_attr "mode" "<MODE>")])
939 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
940 ;; operands may corrupt immediately following multiplies. This is a
941 ;; simple fix to insert NOPs.
943 (define_insn "*mul<mode>3_r4300"
944 [(set (match_operand:SCALARF 0 "register_operand" "=f")
945 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
946 (match_operand:SCALARF 2 "register_operand" "f")))]
947 "TARGET_4300_MUL_FIX"
948 "mul.<fmt>\t%0,%1,%2\;nop"
949 [(set_attr "type" "fmul")
950 (set_attr "mode" "<MODE>")
951 (set_attr "length" "8")])
953 (define_insn "mulv2sf3"
954 [(set (match_operand:V2SF 0 "register_operand" "=f")
955 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
956 (match_operand:V2SF 2 "register_operand" "f")))]
957 "TARGET_PAIRED_SINGLE_FLOAT"
959 [(set_attr "type" "fmul")
960 (set_attr "mode" "SF")])
962 ;; The original R4000 has a cpu bug. If a double-word or a variable
963 ;; shift executes while an integer multiplication is in progress, the
964 ;; shift may give an incorrect result. Avoid this by keeping the mflo
965 ;; with the mult on the R4000.
967 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
968 ;; (also valid for MIPS R4000MC processors):
970 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
971 ;; this errata description.
972 ;; The following code sequence causes the R4000 to incorrectly
973 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
974 ;; instruction. If the dsra32 instruction is executed during an
975 ;; integer multiply, the dsra32 will only shift by the amount in
976 ;; specified in the instruction rather than the amount plus 32
978 ;; instruction 1: mult rs,rt integer multiply
979 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
980 ;; right arithmetic + 32
981 ;; Workaround: A dsra32 instruction placed after an integer
982 ;; multiply should not be one of the 11 instructions after the
983 ;; multiply instruction."
987 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
988 ;; the following description.
989 ;; All extended shifts (shift by n+32) and variable shifts (32 and
990 ;; 64-bit versions) may produce incorrect results under the
991 ;; following conditions:
992 ;; 1) An integer multiply is currently executing
993 ;; 2) These types of shift instructions are executed immediately
994 ;; following an integer divide instruction.
996 ;; 1) Make sure no integer multiply is running wihen these
997 ;; instruction are executed. If this cannot be predicted at
998 ;; compile time, then insert a "mfhi" to R0 instruction
999 ;; immediately after the integer multiply instruction. This
1000 ;; will cause the integer multiply to complete before the shift
1002 ;; 2) Separate integer divide and these two classes of shift
1003 ;; instructions by another instruction or a noop."
1005 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1008 (define_expand "mul<mode>3"
1009 [(set (match_operand:GPR 0 "register_operand")
1010 (mult:GPR (match_operand:GPR 1 "register_operand")
1011 (match_operand:GPR 2 "register_operand")))]
1014 if (GENERATE_MULT3_<MODE>)
1015 emit_insn (gen_mul<mode>3_mult3 (operands[0], operands[1], operands[2]));
1016 else if (!TARGET_FIX_R4000)
1017 emit_insn (gen_mul<mode>3_internal (operands[0], operands[1],
1020 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1024 (define_insn "mulsi3_mult3"
1025 [(set (match_operand:SI 0 "register_operand" "=d,l")
1026 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1027 (match_operand:SI 2 "register_operand" "d,d")))
1028 (clobber (match_scratch:SI 3 "=h,h"))
1029 (clobber (match_scratch:SI 4 "=l,X"))]
1032 if (which_alternative == 1)
1033 return "mult\t%1,%2";
1042 return "mul\t%0,%1,%2";
1043 return "mult\t%0,%1,%2";
1045 [(set_attr "type" "imul3,imul")
1046 (set_attr "mode" "SI")])
1048 (define_insn "muldi3_mult3"
1049 [(set (match_operand:DI 0 "register_operand" "=d")
1050 (mult:DI (match_operand:DI 1 "register_operand" "d")
1051 (match_operand:DI 2 "register_operand" "d")))
1052 (clobber (match_scratch:DI 3 "=h"))
1053 (clobber (match_scratch:DI 4 "=l"))]
1054 "TARGET_64BIT && GENERATE_MULT3_DI"
1056 [(set_attr "type" "imul3")
1057 (set_attr "mode" "DI")])
1059 ;; If a register gets allocated to LO, and we spill to memory, the reload
1060 ;; will include a move from LO to a GPR. Merge it into the multiplication
1061 ;; if it can set the GPR directly.
1064 ;; Operand 1: GPR (1st multiplication operand)
1065 ;; Operand 2: GPR (2nd multiplication operand)
1067 ;; Operand 4: GPR (destination)
1070 [(set (match_operand:SI 0 "register_operand")
1071 (mult:SI (match_operand:SI 1 "register_operand")
1072 (match_operand:SI 2 "register_operand")))
1073 (clobber (match_operand:SI 3 "register_operand"))
1074 (clobber (scratch:SI))])
1075 (set (match_operand:SI 4 "register_operand")
1076 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1077 "GENERATE_MULT3_SI && peep2_reg_dead_p (2, operands[0])"
1080 (mult:SI (match_dup 1)
1082 (clobber (match_dup 3))
1083 (clobber (match_dup 0))])])
1085 (define_insn "mul<mode>3_internal"
1086 [(set (match_operand:GPR 0 "register_operand" "=l")
1087 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1088 (match_operand:GPR 2 "register_operand" "d")))
1089 (clobber (match_scratch:GPR 3 "=h"))]
1092 [(set_attr "type" "imul")
1093 (set_attr "mode" "<MODE>")])
1095 (define_insn "mul<mode>3_r4000"
1096 [(set (match_operand:GPR 0 "register_operand" "=d")
1097 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1098 (match_operand:GPR 2 "register_operand" "d")))
1099 (clobber (match_scratch:GPR 3 "=h"))
1100 (clobber (match_scratch:GPR 4 "=l"))]
1102 "<d>mult\t%1,%2\;mflo\t%0"
1103 [(set_attr "type" "imul")
1104 (set_attr "mode" "<MODE>")
1105 (set_attr "length" "8")])
1107 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1108 ;; of "mult; mflo". They have the same latency, but the first form gives
1109 ;; us an extra cycle to compute the operands.
1112 ;; Operand 1: GPR (1st multiplication operand)
1113 ;; Operand 2: GPR (2nd multiplication operand)
1115 ;; Operand 4: GPR (destination)
1118 [(set (match_operand:SI 0 "register_operand")
1119 (mult:SI (match_operand:SI 1 "register_operand")
1120 (match_operand:SI 2 "register_operand")))
1121 (clobber (match_operand:SI 3 "register_operand"))])
1122 (set (match_operand:SI 4 "register_operand")
1123 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1124 "ISA_HAS_MACC && !GENERATE_MULT3_SI"
1129 (plus:SI (mult:SI (match_dup 1)
1133 (plus:SI (mult:SI (match_dup 1)
1136 (clobber (match_dup 3))])])
1138 ;; Multiply-accumulate patterns
1140 ;; For processors that can copy the output to a general register:
1142 ;; The all-d alternative is needed because the combiner will find this
1143 ;; pattern and then register alloc/reload will move registers around to
1144 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1146 ;; The last alternative should be made slightly less desirable, but adding
1147 ;; "?" to the constraint is too strong, and causes values to be loaded into
1148 ;; LO even when that's more costly. For now, using "*d" mostly does the
1150 (define_insn "*mul_acc_si"
1151 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1152 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1153 (match_operand:SI 2 "register_operand" "d,d,d"))
1154 (match_operand:SI 3 "register_operand" "0,l,*d")))
1155 (clobber (match_scratch:SI 4 "=h,h,h"))
1156 (clobber (match_scratch:SI 5 "=X,3,l"))
1157 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1159 || ISA_HAS_MADD_MSUB)
1162 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1163 if (which_alternative == 2)
1165 if (ISA_HAS_MADD_MSUB && which_alternative != 0)
1167 return madd[which_alternative];
1169 [(set_attr "type" "imadd,imadd,multi")
1170 (set_attr "mode" "SI")
1171 (set_attr "length" "4,4,8")])
1173 ;; Split the above insn if we failed to get LO allocated.
1175 [(set (match_operand:SI 0 "register_operand")
1176 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1177 (match_operand:SI 2 "register_operand"))
1178 (match_operand:SI 3 "register_operand")))
1179 (clobber (match_scratch:SI 4))
1180 (clobber (match_scratch:SI 5))
1181 (clobber (match_scratch:SI 6))]
1182 "reload_completed && !TARGET_DEBUG_D_MODE
1183 && GP_REG_P (true_regnum (operands[0]))
1184 && GP_REG_P (true_regnum (operands[3]))"
1185 [(parallel [(set (match_dup 6)
1186 (mult:SI (match_dup 1) (match_dup 2)))
1187 (clobber (match_dup 4))
1188 (clobber (match_dup 5))])
1189 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1192 ;; Splitter to copy result of MADD to a general register
1194 [(set (match_operand:SI 0 "register_operand")
1195 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1196 (match_operand:SI 2 "register_operand"))
1197 (match_operand:SI 3 "register_operand")))
1198 (clobber (match_scratch:SI 4))
1199 (clobber (match_scratch:SI 5))
1200 (clobber (match_scratch:SI 6))]
1201 "reload_completed && !TARGET_DEBUG_D_MODE
1202 && GP_REG_P (true_regnum (operands[0]))
1203 && true_regnum (operands[3]) == LO_REGNUM"
1204 [(parallel [(set (match_dup 3)
1205 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1207 (clobber (match_dup 4))
1208 (clobber (match_dup 5))
1209 (clobber (match_dup 6))])
1210 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1213 (define_insn "*macc"
1214 [(set (match_operand:SI 0 "register_operand" "=l,d")
1215 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1216 (match_operand:SI 2 "register_operand" "d,d"))
1217 (match_operand:SI 3 "register_operand" "0,l")))
1218 (clobber (match_scratch:SI 4 "=h,h"))
1219 (clobber (match_scratch:SI 5 "=X,3"))]
1222 if (which_alternative == 1)
1223 return "macc\t%0,%1,%2";
1224 else if (TARGET_MIPS5500)
1225 return "madd\t%1,%2";
1227 /* The VR4130 assumes that there is a two-cycle latency between a macc
1228 that "writes" to $0 and an instruction that reads from it. We avoid
1229 this by assigning to $1 instead. */
1230 return "%[macc\t%@,%1,%2%]";
1232 [(set_attr "type" "imadd")
1233 (set_attr "mode" "SI")])
1235 (define_insn "*msac"
1236 [(set (match_operand:SI 0 "register_operand" "=l,d")
1237 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1238 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1239 (match_operand:SI 3 "register_operand" "d,d"))))
1240 (clobber (match_scratch:SI 4 "=h,h"))
1241 (clobber (match_scratch:SI 5 "=X,1"))]
1244 if (which_alternative == 1)
1245 return "msac\t%0,%2,%3";
1246 else if (TARGET_MIPS5500)
1247 return "msub\t%2,%3";
1249 return "msac\t$0,%2,%3";
1251 [(set_attr "type" "imadd")
1252 (set_attr "mode" "SI")])
1254 ;; An msac-like instruction implemented using negation and a macc.
1255 (define_insn_and_split "*msac_using_macc"
1256 [(set (match_operand:SI 0 "register_operand" "=l,d")
1257 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1258 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1259 (match_operand:SI 3 "register_operand" "d,d"))))
1260 (clobber (match_scratch:SI 4 "=h,h"))
1261 (clobber (match_scratch:SI 5 "=X,1"))
1262 (clobber (match_scratch:SI 6 "=d,d"))]
1263 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1265 "&& reload_completed"
1267 (neg:SI (match_dup 3)))
1270 (plus:SI (mult:SI (match_dup 2)
1273 (clobber (match_dup 4))
1274 (clobber (match_dup 5))])]
1276 [(set_attr "type" "imadd")
1277 (set_attr "length" "8")])
1279 ;; Patterns generated by the define_peephole2 below.
1281 (define_insn "*macc2"
1282 [(set (match_operand:SI 0 "register_operand" "=l")
1283 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1284 (match_operand:SI 2 "register_operand" "d"))
1286 (set (match_operand:SI 3 "register_operand" "=d")
1287 (plus:SI (mult:SI (match_dup 1)
1290 (clobber (match_scratch:SI 4 "=h"))]
1291 "ISA_HAS_MACC && reload_completed"
1293 [(set_attr "type" "imadd")
1294 (set_attr "mode" "SI")])
1296 (define_insn "*msac2"
1297 [(set (match_operand:SI 0 "register_operand" "=l")
1298 (minus:SI (match_dup 0)
1299 (mult:SI (match_operand:SI 1 "register_operand" "d")
1300 (match_operand:SI 2 "register_operand" "d"))))
1301 (set (match_operand:SI 3 "register_operand" "=d")
1302 (minus:SI (match_dup 0)
1303 (mult:SI (match_dup 1)
1305 (clobber (match_scratch:SI 4 "=h"))]
1306 "ISA_HAS_MSAC && reload_completed"
1308 [(set_attr "type" "imadd")
1309 (set_attr "mode" "SI")])
1311 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1315 ;; Operand 1: macc/msac
1317 ;; Operand 3: GPR (destination)
1320 [(set (match_operand:SI 0 "register_operand")
1321 (match_operand:SI 1 "macc_msac_operand"))
1322 (clobber (match_operand:SI 2 "register_operand"))
1323 (clobber (scratch:SI))])
1324 (set (match_operand:SI 3 "register_operand")
1325 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1327 [(parallel [(set (match_dup 0)
1331 (clobber (match_dup 2))])]
1334 ;; When we have a three-address multiplication instruction, it should
1335 ;; be faster to do a separate multiply and add, rather than moving
1336 ;; something into LO in order to use a macc instruction.
1338 ;; This peephole needs a scratch register to cater for the case when one
1339 ;; of the multiplication operands is the same as the destination.
1341 ;; Operand 0: GPR (scratch)
1343 ;; Operand 2: GPR (addend)
1344 ;; Operand 3: GPR (destination)
1345 ;; Operand 4: macc/msac
1347 ;; Operand 6: new multiplication
1348 ;; Operand 7: new addition/subtraction
1350 [(match_scratch:SI 0 "d")
1351 (set (match_operand:SI 1 "register_operand")
1352 (match_operand:SI 2 "register_operand"))
1355 [(set (match_operand:SI 3 "register_operand")
1356 (match_operand:SI 4 "macc_msac_operand"))
1357 (clobber (match_operand:SI 5 "register_operand"))
1358 (clobber (match_dup 1))])]
1360 && true_regnum (operands[1]) == LO_REGNUM
1361 && peep2_reg_dead_p (2, operands[1])
1362 && GP_REG_P (true_regnum (operands[3]))"
1363 [(parallel [(set (match_dup 0)
1365 (clobber (match_dup 5))
1366 (clobber (match_dup 1))])
1370 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1371 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1372 operands[2], operands[0]);
1375 ;; Same as above, except LO is the initial target of the macc.
1377 ;; Operand 0: GPR (scratch)
1379 ;; Operand 2: GPR (addend)
1380 ;; Operand 3: macc/msac
1382 ;; Operand 5: GPR (destination)
1383 ;; Operand 6: new multiplication
1384 ;; Operand 7: new addition/subtraction
1386 [(match_scratch:SI 0 "d")
1387 (set (match_operand:SI 1 "register_operand")
1388 (match_operand:SI 2 "register_operand"))
1392 (match_operand:SI 3 "macc_msac_operand"))
1393 (clobber (match_operand:SI 4 "register_operand"))
1394 (clobber (scratch:SI))])
1396 (set (match_operand:SI 5 "register_operand")
1397 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1398 "GENERATE_MULT3_SI && peep2_reg_dead_p (3, operands[1])"
1399 [(parallel [(set (match_dup 0)
1401 (clobber (match_dup 4))
1402 (clobber (match_dup 1))])
1406 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1407 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1408 operands[2], operands[0]);
1411 (define_insn "*mul_sub_si"
1412 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1413 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1414 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1415 (match_operand:SI 3 "register_operand" "d,d,d"))))
1416 (clobber (match_scratch:SI 4 "=h,h,h"))
1417 (clobber (match_scratch:SI 5 "=X,1,l"))
1418 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1424 [(set_attr "type" "imadd,multi,multi")
1425 (set_attr "mode" "SI")
1426 (set_attr "length" "4,8,8")])
1428 ;; Split the above insn if we failed to get LO allocated.
1430 [(set (match_operand:SI 0 "register_operand")
1431 (minus:SI (match_operand:SI 1 "register_operand")
1432 (mult:SI (match_operand:SI 2 "register_operand")
1433 (match_operand:SI 3 "register_operand"))))
1434 (clobber (match_scratch:SI 4))
1435 (clobber (match_scratch:SI 5))
1436 (clobber (match_scratch:SI 6))]
1437 "reload_completed && !TARGET_DEBUG_D_MODE
1438 && GP_REG_P (true_regnum (operands[0]))
1439 && GP_REG_P (true_regnum (operands[1]))"
1440 [(parallel [(set (match_dup 6)
1441 (mult:SI (match_dup 2) (match_dup 3)))
1442 (clobber (match_dup 4))
1443 (clobber (match_dup 5))])
1444 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1447 ;; Splitter to copy result of MSUB to a general register
1449 [(set (match_operand:SI 0 "register_operand")
1450 (minus:SI (match_operand:SI 1 "register_operand")
1451 (mult:SI (match_operand:SI 2 "register_operand")
1452 (match_operand:SI 3 "register_operand"))))
1453 (clobber (match_scratch:SI 4))
1454 (clobber (match_scratch:SI 5))
1455 (clobber (match_scratch:SI 6))]
1456 "reload_completed && !TARGET_DEBUG_D_MODE
1457 && GP_REG_P (true_regnum (operands[0]))
1458 && true_regnum (operands[1]) == LO_REGNUM"
1459 [(parallel [(set (match_dup 1)
1460 (minus:SI (match_dup 1)
1461 (mult:SI (match_dup 2) (match_dup 3))))
1462 (clobber (match_dup 4))
1463 (clobber (match_dup 5))
1464 (clobber (match_dup 6))])
1465 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1468 (define_insn "*muls"
1469 [(set (match_operand:SI 0 "register_operand" "=l,d")
1470 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1471 (match_operand:SI 2 "register_operand" "d,d"))))
1472 (clobber (match_scratch:SI 3 "=h,h"))
1473 (clobber (match_scratch:SI 4 "=X,l"))]
1478 [(set_attr "type" "imul,imul3")
1479 (set_attr "mode" "SI")])
1481 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1483 (define_expand "<u>mulsidi3"
1485 [(set (match_operand:DI 0 "register_operand")
1486 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1487 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1488 (clobber (scratch:DI))
1489 (clobber (scratch:DI))
1490 (clobber (scratch:DI))])]
1491 "!TARGET_64BIT || !TARGET_FIX_R4000"
1495 if (!TARGET_FIX_R4000)
1496 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1499 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1505 (define_insn "<u>mulsidi3_32bit_internal"
1506 [(set (match_operand:DI 0 "register_operand" "=x")
1507 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1508 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1509 "!TARGET_64BIT && !TARGET_FIX_R4000"
1511 [(set_attr "type" "imul")
1512 (set_attr "mode" "SI")])
1514 (define_insn "<u>mulsidi3_32bit_r4000"
1515 [(set (match_operand:DI 0 "register_operand" "=d")
1516 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1517 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1518 (clobber (match_scratch:DI 3 "=x"))]
1519 "!TARGET_64BIT && TARGET_FIX_R4000"
1520 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1521 [(set_attr "type" "imul")
1522 (set_attr "mode" "SI")
1523 (set_attr "length" "12")])
1525 (define_insn_and_split "*<u>mulsidi3_64bit"
1526 [(set (match_operand:DI 0 "register_operand" "=d")
1527 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1528 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1529 (clobber (match_scratch:DI 3 "=l"))
1530 (clobber (match_scratch:DI 4 "=h"))
1531 (clobber (match_scratch:DI 5 "=d"))]
1532 "TARGET_64BIT && !TARGET_FIX_R4000"
1534 "&& reload_completed"
1538 (mult:SI (match_dup 1)
1542 (mult:DI (any_extend:DI (match_dup 1))
1543 (any_extend:DI (match_dup 2)))
1546 ;; OP5 <- LO, OP0 <- HI
1547 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1548 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1552 (ashift:DI (match_dup 5)
1555 (lshiftrt:DI (match_dup 5)
1558 ;; Shift OP0 into place.
1560 (ashift:DI (match_dup 0)
1563 ;; OR the two halves together
1565 (ior:DI (match_dup 0)
1568 [(set_attr "type" "imul")
1569 (set_attr "mode" "SI")
1570 (set_attr "length" "24")])
1572 (define_insn "*<u>mulsidi3_64bit_parts"
1573 [(set (match_operand:DI 0 "register_operand" "=l")
1575 (mult:SI (match_operand:SI 2 "register_operand" "d")
1576 (match_operand:SI 3 "register_operand" "d"))))
1577 (set (match_operand:DI 1 "register_operand" "=h")
1579 (mult:DI (any_extend:DI (match_dup 2))
1580 (any_extend:DI (match_dup 3)))
1582 "TARGET_64BIT && !TARGET_FIX_R4000"
1584 [(set_attr "type" "imul")
1585 (set_attr "mode" "SI")])
1587 ;; Widening multiply with negation.
1588 (define_insn "*muls<u>_di"
1589 [(set (match_operand:DI 0 "register_operand" "=x")
1592 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1593 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1594 "!TARGET_64BIT && ISA_HAS_MULS"
1596 [(set_attr "type" "imul")
1597 (set_attr "mode" "SI")])
1599 (define_insn "*msac<u>_di"
1600 [(set (match_operand:DI 0 "register_operand" "=x")
1602 (match_operand:DI 3 "register_operand" "0")
1604 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1605 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1606 "!TARGET_64BIT && ISA_HAS_MSAC"
1608 if (TARGET_MIPS5500)
1609 return "msub<u>\t%1,%2";
1611 return "msac<u>\t$0,%1,%2";
1613 [(set_attr "type" "imadd")
1614 (set_attr "mode" "SI")])
1616 ;; _highpart patterns
1618 (define_expand "<su>mulsi3_highpart"
1619 [(set (match_operand:SI 0 "register_operand")
1622 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1623 (any_extend:DI (match_operand:SI 2 "register_operand")))
1625 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1628 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1632 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1637 (define_insn "<su>mulsi3_highpart_internal"
1638 [(set (match_operand:SI 0 "register_operand" "=h")
1641 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1642 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1644 (clobber (match_scratch:SI 3 "=l"))]
1645 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1647 [(set_attr "type" "imul")
1648 (set_attr "mode" "SI")])
1650 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1651 [(set (match_operand:SI 0 "register_operand" "=h,d")
1655 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1656 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1658 (clobber (match_scratch:SI 3 "=l,l"))
1659 (clobber (match_scratch:SI 4 "=X,h"))]
1664 [(set_attr "type" "imul,imul3")
1665 (set_attr "mode" "SI")])
1667 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1668 [(set (match_operand:SI 0 "register_operand" "=h,d")
1673 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1674 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1676 (clobber (match_scratch:SI 3 "=l,l"))
1677 (clobber (match_scratch:SI 4 "=X,h"))]
1681 mulshi<u>\t%0,%1,%2"
1682 [(set_attr "type" "imul,imul3")
1683 (set_attr "mode" "SI")])
1685 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1686 ;; errata MD(0), which says that dmultu does not always produce the
1688 (define_insn "<su>muldi3_highpart"
1689 [(set (match_operand:DI 0 "register_operand" "=h")
1693 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1694 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1696 (clobber (match_scratch:DI 3 "=l"))]
1697 "TARGET_64BIT && !TARGET_FIX_R4000
1698 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1700 [(set_attr "type" "imul")
1701 (set_attr "mode" "DI")])
1703 ;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
1704 ;; instruction. The HI/LO registers are used as a 64 bit accumulator.
1706 (define_insn "madsi"
1707 [(set (match_operand:SI 0 "register_operand" "+l")
1708 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1709 (match_operand:SI 2 "register_operand" "d"))
1711 (clobber (match_scratch:SI 3 "=h"))]
1714 [(set_attr "type" "imadd")
1715 (set_attr "mode" "SI")])
1717 (define_insn "*<su>mul_acc_di"
1718 [(set (match_operand:DI 0 "register_operand" "=x")
1720 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1721 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1722 (match_operand:DI 3 "register_operand" "0")))]
1723 "(TARGET_MAD || ISA_HAS_MACC)
1727 return "mad<u>\t%1,%2";
1728 else if (TARGET_MIPS5500)
1729 return "madd<u>\t%1,%2";
1731 /* See comment in *macc. */
1732 return "%[macc<u>\t%@,%1,%2%]";
1734 [(set_attr "type" "imadd")
1735 (set_attr "mode" "SI")])
1737 ;; Floating point multiply accumulate instructions.
1739 (define_insn "*madd<mode>"
1740 [(set (match_operand:ANYF 0 "register_operand" "=f")
1741 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1742 (match_operand:ANYF 2 "register_operand" "f"))
1743 (match_operand:ANYF 3 "register_operand" "f")))]
1744 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1745 "madd.<fmt>\t%0,%3,%1,%2"
1746 [(set_attr "type" "fmadd")
1747 (set_attr "mode" "<UNITMODE>")])
1749 (define_insn "*msub<mode>"
1750 [(set (match_operand:ANYF 0 "register_operand" "=f")
1751 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1752 (match_operand:ANYF 2 "register_operand" "f"))
1753 (match_operand:ANYF 3 "register_operand" "f")))]
1754 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1755 "msub.<fmt>\t%0,%3,%1,%2"
1756 [(set_attr "type" "fmadd")
1757 (set_attr "mode" "<UNITMODE>")])
1759 (define_insn "*nmadd<mode>"
1760 [(set (match_operand:ANYF 0 "register_operand" "=f")
1761 (neg:ANYF (plus:ANYF
1762 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1763 (match_operand:ANYF 2 "register_operand" "f"))
1764 (match_operand:ANYF 3 "register_operand" "f"))))]
1765 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1766 && HONOR_SIGNED_ZEROS (<MODE>mode)"
1767 "nmadd.<fmt>\t%0,%3,%1,%2"
1768 [(set_attr "type" "fmadd")
1769 (set_attr "mode" "<UNITMODE>")])
1771 (define_insn "*nmadd<mode>_fastmath"
1772 [(set (match_operand:ANYF 0 "register_operand" "=f")
1774 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1775 (match_operand:ANYF 2 "register_operand" "f"))
1776 (match_operand:ANYF 3 "register_operand" "f")))]
1777 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1778 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
1779 "nmadd.<fmt>\t%0,%3,%1,%2"
1780 [(set_attr "type" "fmadd")
1781 (set_attr "mode" "<UNITMODE>")])
1783 (define_insn "*nmsub<mode>"
1784 [(set (match_operand:ANYF 0 "register_operand" "=f")
1785 (neg:ANYF (minus:ANYF
1786 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1787 (match_operand:ANYF 3 "register_operand" "f"))
1788 (match_operand:ANYF 1 "register_operand" "f"))))]
1789 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1790 && HONOR_SIGNED_ZEROS (<MODE>mode)"
1791 "nmsub.<fmt>\t%0,%1,%2,%3"
1792 [(set_attr "type" "fmadd")
1793 (set_attr "mode" "<UNITMODE>")])
1795 (define_insn "*nmsub<mode>_fastmath"
1796 [(set (match_operand:ANYF 0 "register_operand" "=f")
1798 (match_operand:ANYF 1 "register_operand" "f")
1799 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1800 (match_operand:ANYF 3 "register_operand" "f"))))]
1801 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1802 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
1803 "nmsub.<fmt>\t%0,%1,%2,%3"
1804 [(set_attr "type" "fmadd")
1805 (set_attr "mode" "<UNITMODE>")])
1808 ;; ....................
1810 ;; DIVISION and REMAINDER
1812 ;; ....................
1815 (define_expand "div<mode>3"
1816 [(set (match_operand:ANYF 0 "register_operand")
1817 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1818 (match_operand:ANYF 2 "register_operand")))]
1819 "<divide_condition>"
1821 if (const_1_operand (operands[1], <MODE>mode))
1822 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1823 operands[1] = force_reg (<MODE>mode, operands[1]);
1826 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1828 ;; If an mfc1 or dmfc1 happens to access the floating point register
1829 ;; file at the same time a long latency operation (div, sqrt, recip,
1830 ;; sqrt) iterates an intermediate result back through the floating
1831 ;; point register file bypass, then instead returning the correct
1832 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1833 ;; result of the long latency operation.
1835 ;; The workaround is to insert an unconditional 'mov' from/to the
1836 ;; long latency op destination register.
1838 (define_insn "*div<mode>3"
1839 [(set (match_operand:ANYF 0 "register_operand" "=f")
1840 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1841 (match_operand:ANYF 2 "register_operand" "f")))]
1842 "<divide_condition>"
1845 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1847 return "div.<fmt>\t%0,%1,%2";
1849 [(set_attr "type" "fdiv")
1850 (set_attr "mode" "<UNITMODE>")
1851 (set (attr "length")
1852 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1856 (define_insn "*recip<mode>3"
1857 [(set (match_operand:ANYF 0 "register_operand" "=f")
1858 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1859 (match_operand:ANYF 2 "register_operand" "f")))]
1860 "<recip_condition> && flag_unsafe_math_optimizations"
1863 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1865 return "recip.<fmt>\t%0,%2";
1867 [(set_attr "type" "frdiv")
1868 (set_attr "mode" "<UNITMODE>")
1869 (set (attr "length")
1870 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1874 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1875 ;; with negative operands. We use special libgcc functions instead.
1876 (define_insn "divmod<mode>4"
1877 [(set (match_operand:GPR 0 "register_operand" "=l")
1878 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1879 (match_operand:GPR 2 "register_operand" "d")))
1880 (set (match_operand:GPR 3 "register_operand" "=h")
1881 (mod:GPR (match_dup 1)
1883 "!TARGET_FIX_VR4120"
1884 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1885 [(set_attr "type" "idiv")
1886 (set_attr "mode" "<MODE>")])
1888 (define_insn "udivmod<mode>4"
1889 [(set (match_operand:GPR 0 "register_operand" "=l")
1890 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
1891 (match_operand:GPR 2 "register_operand" "d")))
1892 (set (match_operand:GPR 3 "register_operand" "=h")
1893 (umod:GPR (match_dup 1)
1896 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
1897 [(set_attr "type" "idiv")
1898 (set_attr "mode" "<MODE>")])
1901 ;; ....................
1905 ;; ....................
1907 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
1908 ;; "*div[sd]f3" comment for details).
1910 (define_insn "sqrt<mode>2"
1911 [(set (match_operand:ANYF 0 "register_operand" "=f")
1912 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1916 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
1918 return "sqrt.<fmt>\t%0,%1";
1920 [(set_attr "type" "fsqrt")
1921 (set_attr "mode" "<UNITMODE>")
1922 (set (attr "length")
1923 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1927 (define_insn "*rsqrt<mode>a"
1928 [(set (match_operand:ANYF 0 "register_operand" "=f")
1929 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1930 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
1931 "<recip_condition> && flag_unsafe_math_optimizations"
1934 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1936 return "rsqrt.<fmt>\t%0,%2";
1938 [(set_attr "type" "frsqrt")
1939 (set_attr "mode" "<UNITMODE>")
1940 (set (attr "length")
1941 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1945 (define_insn "*rsqrt<mode>b"
1946 [(set (match_operand:ANYF 0 "register_operand" "=f")
1947 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1948 (match_operand:ANYF 2 "register_operand" "f"))))]
1949 "<recip_condition> && flag_unsafe_math_optimizations"
1952 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1954 return "rsqrt.<fmt>\t%0,%2";
1956 [(set_attr "type" "frsqrt")
1957 (set_attr "mode" "<UNITMODE>")
1958 (set (attr "length")
1959 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1964 ;; ....................
1968 ;; ....................
1970 ;; Do not use the integer abs macro instruction, since that signals an
1971 ;; exception on -2147483648 (sigh).
1973 (define_insn "abs<mode>2"
1974 [(set (match_operand:ANYF 0 "register_operand" "=f")
1975 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1978 [(set_attr "type" "fabs")
1979 (set_attr "mode" "<UNITMODE>")])
1982 ;; ...................
1984 ;; Count leading zeroes.
1986 ;; ...................
1989 (define_insn "clz<mode>2"
1990 [(set (match_operand:GPR 0 "register_operand" "=d")
1991 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
1994 [(set_attr "type" "clz")
1995 (set_attr "mode" "<MODE>")])
1998 ;; ....................
2000 ;; NEGATION and ONE'S COMPLEMENT
2002 ;; ....................
2004 (define_insn "negsi2"
2005 [(set (match_operand:SI 0 "register_operand" "=d")
2006 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2010 return "neg\t%0,%1";
2012 return "subu\t%0,%.,%1";
2014 [(set_attr "type" "arith")
2015 (set_attr "mode" "SI")])
2017 (define_insn "negdi2"
2018 [(set (match_operand:DI 0 "register_operand" "=d")
2019 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2020 "TARGET_64BIT && !TARGET_MIPS16"
2022 [(set_attr "type" "arith")
2023 (set_attr "mode" "DI")])
2025 (define_insn "neg<mode>2"
2026 [(set (match_operand:ANYF 0 "register_operand" "=f")
2027 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2030 [(set_attr "type" "fneg")
2031 (set_attr "mode" "<UNITMODE>")])
2033 (define_insn "one_cmpl<mode>2"
2034 [(set (match_operand:GPR 0 "register_operand" "=d")
2035 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2039 return "not\t%0,%1";
2041 return "nor\t%0,%.,%1";
2043 [(set_attr "type" "arith")
2044 (set_attr "mode" "<MODE>")])
2047 ;; ....................
2051 ;; ....................
2054 ;; Many of these instructions use trivial define_expands, because we
2055 ;; want to use a different set of constraints when TARGET_MIPS16.
2057 (define_expand "and<mode>3"
2058 [(set (match_operand:GPR 0 "register_operand")
2059 (and:GPR (match_operand:GPR 1 "register_operand")
2060 (match_operand:GPR 2 "uns_arith_operand")))]
2064 operands[2] = force_reg (<MODE>mode, operands[2]);
2067 (define_insn "*and<mode>3"
2068 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2069 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2070 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2075 [(set_attr "type" "arith")
2076 (set_attr "mode" "<MODE>")])
2078 (define_insn "*and<mode>3_mips16"
2079 [(set (match_operand:GPR 0 "register_operand" "=d")
2080 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2081 (match_operand:GPR 2 "register_operand" "d")))]
2084 [(set_attr "type" "arith")
2085 (set_attr "mode" "<MODE>")])
2087 (define_expand "ior<mode>3"
2088 [(set (match_operand:GPR 0 "register_operand")
2089 (ior:GPR (match_operand:GPR 1 "register_operand")
2090 (match_operand:GPR 2 "uns_arith_operand")))]
2094 operands[2] = force_reg (<MODE>mode, operands[2]);
2097 (define_insn "*ior<mode>3"
2098 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2099 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2100 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2105 [(set_attr "type" "arith")
2106 (set_attr "mode" "<MODE>")])
2108 (define_insn "*ior<mode>3_mips16"
2109 [(set (match_operand:GPR 0 "register_operand" "=d")
2110 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2111 (match_operand:GPR 2 "register_operand" "d")))]
2114 [(set_attr "type" "arith")
2115 (set_attr "mode" "<MODE>")])
2117 (define_expand "xor<mode>3"
2118 [(set (match_operand:GPR 0 "register_operand")
2119 (xor:GPR (match_operand:GPR 1 "register_operand")
2120 (match_operand:GPR 2 "uns_arith_operand")))]
2125 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2126 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2127 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2132 [(set_attr "type" "arith")
2133 (set_attr "mode" "<MODE>")])
2136 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2137 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2138 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2144 [(set_attr "type" "arith")
2145 (set_attr "mode" "<MODE>")
2146 (set_attr_alternative "length"
2148 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2153 (define_insn "*nor<mode>3"
2154 [(set (match_operand:GPR 0 "register_operand" "=d")
2155 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2156 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2159 [(set_attr "type" "arith")
2160 (set_attr "mode" "<MODE>")])
2163 ;; ....................
2167 ;; ....................
2171 (define_insn "truncdfsf2"
2172 [(set (match_operand:SF 0 "register_operand" "=f")
2173 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2174 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2176 [(set_attr "type" "fcvt")
2177 (set_attr "cnv_mode" "D2S")
2178 (set_attr "mode" "SF")])
2180 ;; Integer truncation patterns. Truncating SImode values to smaller
2181 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2182 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2183 ;; need to make sure that the lower 32 bits are properly sign-extended
2184 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2185 ;; smaller than SImode is equivalent to two separate truncations:
2188 ;; DI ---> HI == DI ---> SI ---> HI
2189 ;; DI ---> QI == DI ---> SI ---> QI
2191 ;; Step A needs a real instruction but step B does not.
2193 (define_insn "truncdisi2"
2194 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2195 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2200 [(set_attr "type" "shift,store")
2201 (set_attr "mode" "SI")
2202 (set_attr "extended_mips16" "yes,*")])
2204 (define_insn "truncdihi2"
2205 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2206 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2211 [(set_attr "type" "shift,store")
2212 (set_attr "mode" "SI")
2213 (set_attr "extended_mips16" "yes,*")])
2215 (define_insn "truncdiqi2"
2216 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2217 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2222 [(set_attr "type" "shift,store")
2223 (set_attr "mode" "SI")
2224 (set_attr "extended_mips16" "yes,*")])
2226 ;; Combiner patterns to optimize shift/truncate combinations.
2229 [(set (match_operand:SI 0 "register_operand" "=d")
2231 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2232 (match_operand:DI 2 "const_arith_operand" ""))))]
2233 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2235 [(set_attr "type" "shift")
2236 (set_attr "mode" "SI")])
2239 [(set (match_operand:SI 0 "register_operand" "=d")
2240 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2242 "TARGET_64BIT && !TARGET_MIPS16"
2244 [(set_attr "type" "shift")
2245 (set_attr "mode" "SI")])
2248 ;; Combiner patterns for truncate/sign_extend combinations. They use
2249 ;; the shift/truncate patterns above.
2251 (define_insn_and_split ""
2252 [(set (match_operand:SI 0 "register_operand" "=d")
2254 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2255 "TARGET_64BIT && !TARGET_MIPS16"
2257 "&& reload_completed"
2259 (ashift:DI (match_dup 1)
2262 (truncate:SI (ashiftrt:DI (match_dup 2)
2264 { operands[2] = gen_lowpart (DImode, operands[0]); })
2266 (define_insn_and_split ""
2267 [(set (match_operand:SI 0 "register_operand" "=d")
2269 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2270 "TARGET_64BIT && !TARGET_MIPS16"
2272 "&& reload_completed"
2274 (ashift:DI (match_dup 1)
2277 (truncate:SI (ashiftrt:DI (match_dup 2)
2279 { operands[2] = gen_lowpart (DImode, operands[0]); })
2282 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2285 [(set (match_operand:SI 0 "register_operand" "=d")
2286 (zero_extend:SI (truncate:HI
2287 (match_operand:DI 1 "register_operand" "d"))))]
2288 "TARGET_64BIT && !TARGET_MIPS16"
2289 "andi\t%0,%1,0xffff"
2290 [(set_attr "type" "arith")
2291 (set_attr "mode" "SI")])
2294 [(set (match_operand:SI 0 "register_operand" "=d")
2295 (zero_extend:SI (truncate:QI
2296 (match_operand:DI 1 "register_operand" "d"))))]
2297 "TARGET_64BIT && !TARGET_MIPS16"
2299 [(set_attr "type" "arith")
2300 (set_attr "mode" "SI")])
2303 [(set (match_operand:HI 0 "register_operand" "=d")
2304 (zero_extend:HI (truncate:QI
2305 (match_operand:DI 1 "register_operand" "d"))))]
2306 "TARGET_64BIT && !TARGET_MIPS16"
2308 [(set_attr "type" "arith")
2309 (set_attr "mode" "HI")])
2312 ;; ....................
2316 ;; ....................
2320 (define_insn_and_split "zero_extendsidi2"
2321 [(set (match_operand:DI 0 "register_operand" "=d,d")
2322 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2327 "&& reload_completed && REG_P (operands[1])"
2329 (ashift:DI (match_dup 1) (const_int 32)))
2331 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2332 { operands[1] = gen_lowpart (DImode, operands[1]); }
2333 [(set_attr "type" "multi,load")
2334 (set_attr "mode" "DI")
2335 (set_attr "length" "8,*")])
2337 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2338 ;; because of TRULY_NOOP_TRUNCATION.
2340 (define_insn_and_split "*clear_upper32"
2341 [(set (match_operand:DI 0 "register_operand" "=d,d")
2342 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2343 (const_int 4294967295)))]
2346 if (which_alternative == 0)
2349 operands[1] = gen_lowpart (SImode, operands[1]);
2350 return "lwu\t%0,%1";
2352 "&& reload_completed && REG_P (operands[1])"
2354 (ashift:DI (match_dup 1) (const_int 32)))
2356 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2358 [(set_attr "type" "multi,load")
2359 (set_attr "mode" "DI")
2360 (set_attr "length" "8,*")])
2362 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2363 [(set (match_operand:GPR 0 "register_operand")
2364 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2367 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2368 && !memory_operand (operands[1], <SHORT:MODE>mode))
2370 emit_insn (gen_and<GPR:mode>3 (operands[0],
2371 gen_lowpart (<GPR:MODE>mode, operands[1]),
2372 force_reg (<GPR:MODE>mode,
2373 GEN_INT (<SHORT:mask>))));
2378 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2379 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2381 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2384 andi\t%0,%1,<SHORT:mask>
2385 l<SHORT:size>u\t%0,%1"
2386 [(set_attr "type" "arith,load")
2387 (set_attr "mode" "<GPR:MODE>")])
2389 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2390 [(set (match_operand:GPR 0 "register_operand" "=d")
2391 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2393 "ze<SHORT:size>\t%0"
2394 [(set_attr "type" "arith")
2395 (set_attr "mode" "<GPR:MODE>")])
2397 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2398 [(set (match_operand:GPR 0 "register_operand" "=d")
2399 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2401 "l<SHORT:size>u\t%0,%1"
2402 [(set_attr "type" "load")
2403 (set_attr "mode" "<GPR:MODE>")])
2405 (define_expand "zero_extendqihi2"
2406 [(set (match_operand:HI 0 "register_operand")
2407 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2410 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2412 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2418 (define_insn "*zero_extendqihi2"
2419 [(set (match_operand:HI 0 "register_operand" "=d,d")
2420 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2425 [(set_attr "type" "arith,load")
2426 (set_attr "mode" "HI")])
2428 (define_insn "*zero_extendqihi2_mips16"
2429 [(set (match_operand:HI 0 "register_operand" "=d")
2430 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2433 [(set_attr "type" "load")
2434 (set_attr "mode" "HI")])
2437 ;; ....................
2441 ;; ....................
2444 ;; Those for integer source operand are ordered widest source type first.
2446 ;; When TARGET_64BIT, all SImode integer registers should already be in
2447 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2448 ;; therefore get rid of register->register instructions if we constrain
2449 ;; the source to be in the same register as the destination.
2451 ;; The register alternative has type "arith" so that the pre-reload
2452 ;; scheduler will treat it as a move. This reflects what happens if
2453 ;; the register alternative needs a reload.
2454 (define_insn_and_split "extendsidi2"
2455 [(set (match_operand:DI 0 "register_operand" "=d,d")
2456 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2461 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2464 emit_note (NOTE_INSN_DELETED);
2467 [(set_attr "type" "arith,load")
2468 (set_attr "mode" "DI")])
2470 (define_expand "extend<SHORT:mode><GPR:mode>2"
2471 [(set (match_operand:GPR 0 "register_operand")
2472 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2475 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2476 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2477 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2481 l<SHORT:size>\t%0,%1"
2482 [(set_attr "type" "arith,load")
2483 (set_attr "mode" "<GPR:MODE>")])
2485 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2486 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2488 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2489 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2492 l<SHORT:size>\t%0,%1"
2493 "&& reload_completed && REG_P (operands[1])"
2494 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2495 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2497 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2498 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2499 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2501 [(set_attr "type" "arith,load")
2502 (set_attr "mode" "<GPR:MODE>")
2503 (set_attr "length" "8,*")])
2505 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2506 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2508 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2511 se<SHORT:size>\t%0,%1
2512 l<SHORT:size>\t%0,%1"
2513 [(set_attr "type" "arith,load")
2514 (set_attr "mode" "<GPR:MODE>")])
2516 ;; This pattern generates the same code as extendqisi2; split it into
2517 ;; that form after reload.
2518 (define_insn_and_split "extendqihi2"
2519 [(set (match_operand:HI 0 "register_operand" "=d,d")
2520 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2524 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
2525 { operands[0] = gen_lowpart (SImode, operands[0]); }
2526 [(set_attr "type" "arith,load")
2527 (set_attr "mode" "SI")
2528 (set_attr "length" "8,*")])
2530 (define_insn "extendsfdf2"
2531 [(set (match_operand:DF 0 "register_operand" "=f")
2532 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2533 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2535 [(set_attr "type" "fcvt")
2536 (set_attr "cnv_mode" "S2D")
2537 (set_attr "mode" "DF")])
2540 ;; ....................
2544 ;; ....................
2546 (define_expand "fix_truncdfsi2"
2547 [(set (match_operand:SI 0 "register_operand")
2548 (fix:SI (match_operand:DF 1 "register_operand")))]
2549 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2551 if (!ISA_HAS_TRUNC_W)
2553 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2558 (define_insn "fix_truncdfsi2_insn"
2559 [(set (match_operand:SI 0 "register_operand" "=f")
2560 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2561 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2563 [(set_attr "type" "fcvt")
2564 (set_attr "mode" "DF")
2565 (set_attr "cnv_mode" "D2I")
2566 (set_attr "length" "4")])
2568 (define_insn "fix_truncdfsi2_macro"
2569 [(set (match_operand:SI 0 "register_operand" "=f")
2570 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2571 (clobber (match_scratch:DF 2 "=d"))]
2572 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2575 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2577 return "trunc.w.d %0,%1,%2";
2579 [(set_attr "type" "fcvt")
2580 (set_attr "mode" "DF")
2581 (set_attr "cnv_mode" "D2I")
2582 (set_attr "length" "36")])
2584 (define_expand "fix_truncsfsi2"
2585 [(set (match_operand:SI 0 "register_operand")
2586 (fix:SI (match_operand:SF 1 "register_operand")))]
2589 if (!ISA_HAS_TRUNC_W)
2591 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2596 (define_insn "fix_truncsfsi2_insn"
2597 [(set (match_operand:SI 0 "register_operand" "=f")
2598 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2599 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2601 [(set_attr "type" "fcvt")
2602 (set_attr "mode" "SF")
2603 (set_attr "cnv_mode" "S2I")
2604 (set_attr "length" "4")])
2606 (define_insn "fix_truncsfsi2_macro"
2607 [(set (match_operand:SI 0 "register_operand" "=f")
2608 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2609 (clobber (match_scratch:SF 2 "=d"))]
2610 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2613 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2615 return "trunc.w.s %0,%1,%2";
2617 [(set_attr "type" "fcvt")
2618 (set_attr "mode" "SF")
2619 (set_attr "cnv_mode" "S2I")
2620 (set_attr "length" "36")])
2623 (define_insn "fix_truncdfdi2"
2624 [(set (match_operand:DI 0 "register_operand" "=f")
2625 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2626 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2628 [(set_attr "type" "fcvt")
2629 (set_attr "mode" "DF")
2630 (set_attr "cnv_mode" "D2I")
2631 (set_attr "length" "4")])
2634 (define_insn "fix_truncsfdi2"
2635 [(set (match_operand:DI 0 "register_operand" "=f")
2636 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2637 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2639 [(set_attr "type" "fcvt")
2640 (set_attr "mode" "SF")
2641 (set_attr "cnv_mode" "S2I")
2642 (set_attr "length" "4")])
2645 (define_insn "floatsidf2"
2646 [(set (match_operand:DF 0 "register_operand" "=f")
2647 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2648 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2650 [(set_attr "type" "fcvt")
2651 (set_attr "mode" "DF")
2652 (set_attr "cnv_mode" "I2D")
2653 (set_attr "length" "4")])
2656 (define_insn "floatdidf2"
2657 [(set (match_operand:DF 0 "register_operand" "=f")
2658 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2659 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2661 [(set_attr "type" "fcvt")
2662 (set_attr "mode" "DF")
2663 (set_attr "cnv_mode" "I2D")
2664 (set_attr "length" "4")])
2667 (define_insn "floatsisf2"
2668 [(set (match_operand:SF 0 "register_operand" "=f")
2669 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2672 [(set_attr "type" "fcvt")
2673 (set_attr "mode" "SF")
2674 (set_attr "cnv_mode" "I2S")
2675 (set_attr "length" "4")])
2678 (define_insn "floatdisf2"
2679 [(set (match_operand:SF 0 "register_operand" "=f")
2680 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2681 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2683 [(set_attr "type" "fcvt")
2684 (set_attr "mode" "SF")
2685 (set_attr "cnv_mode" "I2S")
2686 (set_attr "length" "4")])
2689 (define_expand "fixuns_truncdfsi2"
2690 [(set (match_operand:SI 0 "register_operand")
2691 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2692 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2694 rtx reg1 = gen_reg_rtx (DFmode);
2695 rtx reg2 = gen_reg_rtx (DFmode);
2696 rtx reg3 = gen_reg_rtx (SImode);
2697 rtx label1 = gen_label_rtx ();
2698 rtx label2 = gen_label_rtx ();
2699 REAL_VALUE_TYPE offset;
2701 real_2expN (&offset, 31);
2703 if (reg1) /* Turn off complaints about unreached code. */
2705 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2706 do_pending_stack_adjust ();
2708 emit_insn (gen_cmpdf (operands[1], reg1));
2709 emit_jump_insn (gen_bge (label1));
2711 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2712 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2713 gen_rtx_LABEL_REF (VOIDmode, label2)));
2716 emit_label (label1);
2717 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2718 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2719 (BITMASK_HIGH, SImode)));
2721 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2722 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2724 emit_label (label2);
2726 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2727 fields, and can't be used for REG_NOTES anyway). */
2728 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2734 (define_expand "fixuns_truncdfdi2"
2735 [(set (match_operand:DI 0 "register_operand")
2736 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2737 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2739 rtx reg1 = gen_reg_rtx (DFmode);
2740 rtx reg2 = gen_reg_rtx (DFmode);
2741 rtx reg3 = gen_reg_rtx (DImode);
2742 rtx label1 = gen_label_rtx ();
2743 rtx label2 = gen_label_rtx ();
2744 REAL_VALUE_TYPE offset;
2746 real_2expN (&offset, 63);
2748 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2749 do_pending_stack_adjust ();
2751 emit_insn (gen_cmpdf (operands[1], reg1));
2752 emit_jump_insn (gen_bge (label1));
2754 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2755 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2756 gen_rtx_LABEL_REF (VOIDmode, label2)));
2759 emit_label (label1);
2760 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2761 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2762 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2764 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2765 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2767 emit_label (label2);
2769 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2770 fields, and can't be used for REG_NOTES anyway). */
2771 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2776 (define_expand "fixuns_truncsfsi2"
2777 [(set (match_operand:SI 0 "register_operand")
2778 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2781 rtx reg1 = gen_reg_rtx (SFmode);
2782 rtx reg2 = gen_reg_rtx (SFmode);
2783 rtx reg3 = gen_reg_rtx (SImode);
2784 rtx label1 = gen_label_rtx ();
2785 rtx label2 = gen_label_rtx ();
2786 REAL_VALUE_TYPE offset;
2788 real_2expN (&offset, 31);
2790 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2791 do_pending_stack_adjust ();
2793 emit_insn (gen_cmpsf (operands[1], reg1));
2794 emit_jump_insn (gen_bge (label1));
2796 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2797 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2798 gen_rtx_LABEL_REF (VOIDmode, label2)));
2801 emit_label (label1);
2802 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2803 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2804 (BITMASK_HIGH, SImode)));
2806 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2807 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2809 emit_label (label2);
2811 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2812 fields, and can't be used for REG_NOTES anyway). */
2813 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2818 (define_expand "fixuns_truncsfdi2"
2819 [(set (match_operand:DI 0 "register_operand")
2820 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2821 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2823 rtx reg1 = gen_reg_rtx (SFmode);
2824 rtx reg2 = gen_reg_rtx (SFmode);
2825 rtx reg3 = gen_reg_rtx (DImode);
2826 rtx label1 = gen_label_rtx ();
2827 rtx label2 = gen_label_rtx ();
2828 REAL_VALUE_TYPE offset;
2830 real_2expN (&offset, 63);
2832 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2833 do_pending_stack_adjust ();
2835 emit_insn (gen_cmpsf (operands[1], reg1));
2836 emit_jump_insn (gen_bge (label1));
2838 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2839 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2840 gen_rtx_LABEL_REF (VOIDmode, label2)));
2843 emit_label (label1);
2844 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2845 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2846 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2848 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2849 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2851 emit_label (label2);
2853 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2854 fields, and can't be used for REG_NOTES anyway). */
2855 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2860 ;; ....................
2864 ;; ....................
2866 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
2868 (define_expand "extv"
2869 [(set (match_operand 0 "register_operand")
2870 (sign_extract (match_operand:QI 1 "memory_operand")
2871 (match_operand 2 "immediate_operand")
2872 (match_operand 3 "immediate_operand")))]
2875 if (mips_expand_unaligned_load (operands[0], operands[1],
2876 INTVAL (operands[2]),
2877 INTVAL (operands[3])))
2883 (define_expand "extzv"
2884 [(set (match_operand 0 "register_operand")
2885 (zero_extract (match_operand 1 "nonimmediate_operand")
2886 (match_operand 2 "immediate_operand")
2887 (match_operand 3 "immediate_operand")))]
2890 if (mips_expand_unaligned_load (operands[0], operands[1],
2891 INTVAL (operands[2]),
2892 INTVAL (operands[3])))
2894 else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
2896 if (GET_MODE (operands[0]) == DImode)
2897 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
2900 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
2908 (define_insn "extzv<mode>"
2909 [(set (match_operand:GPR 0 "register_operand" "=d")
2910 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
2911 (match_operand:SI 2 "immediate_operand" "I")
2912 (match_operand:SI 3 "immediate_operand" "I")))]
2913 "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
2914 "<d>ext\t%0,%1,%3,%2"
2915 [(set_attr "type" "arith")
2916 (set_attr "mode" "<MODE>")])
2919 (define_expand "insv"
2920 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
2921 (match_operand 1 "immediate_operand")
2922 (match_operand 2 "immediate_operand"))
2923 (match_operand 3 "reg_or_0_operand"))]
2926 if (mips_expand_unaligned_store (operands[0], operands[3],
2927 INTVAL (operands[1]),
2928 INTVAL (operands[2])))
2930 else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
2932 if (GET_MODE (operands[0]) == DImode)
2933 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
2936 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
2944 (define_insn "insv<mode>"
2945 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
2946 (match_operand:SI 1 "immediate_operand" "I")
2947 (match_operand:SI 2 "immediate_operand" "I"))
2948 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
2949 "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
2950 "<d>ins\t%0,%z3,%2,%1"
2951 [(set_attr "type" "arith")
2952 (set_attr "mode" "<MODE>")])
2954 ;; Unaligned word moves generated by the bit field patterns.
2956 ;; As far as the rtl is concerned, both the left-part and right-part
2957 ;; instructions can access the whole field. However, the real operand
2958 ;; refers to just the first or the last byte (depending on endianness).
2959 ;; We therefore use two memory operands to each instruction, one to
2960 ;; describe the rtl effect and one to use in the assembly output.
2962 ;; Operands 0 and 1 are the rtl-level target and source respectively.
2963 ;; This allows us to use the standard length calculations for the "load"
2964 ;; and "store" type attributes.
2966 (define_insn "mov_<load>l"
2967 [(set (match_operand:GPR 0 "register_operand" "=d")
2968 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
2969 (match_operand:QI 2 "memory_operand" "m")]
2973 [(set_attr "type" "load")
2974 (set_attr "mode" "<MODE>")])
2976 (define_insn "mov_<load>r"
2977 [(set (match_operand:GPR 0 "register_operand" "=d")
2978 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
2979 (match_operand:QI 2 "memory_operand" "m")
2980 (match_operand:GPR 3 "register_operand" "0")]
2981 UNSPEC_LOAD_RIGHT))]
2984 [(set_attr "type" "load")
2985 (set_attr "mode" "<MODE>")])
2987 (define_insn "mov_<store>l"
2988 [(set (match_operand:BLK 0 "memory_operand" "=m")
2989 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
2990 (match_operand:QI 2 "memory_operand" "m")]
2991 UNSPEC_STORE_LEFT))]
2994 [(set_attr "type" "store")
2995 (set_attr "mode" "<MODE>")])
2997 (define_insn "mov_<store>r"
2998 [(set (match_operand:BLK 0 "memory_operand" "+m")
2999 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3000 (match_operand:QI 2 "memory_operand" "m")
3002 UNSPEC_STORE_RIGHT))]
3005 [(set_attr "type" "store")
3006 (set_attr "mode" "<MODE>")])
3008 ;; An instruction to calculate the high part of a 64-bit SYMBOL_GENERAL.
3009 ;; The required value is:
3011 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3013 ;; which translates to:
3015 ;; lui op0,%highest(op1)
3016 ;; daddiu op0,op0,%higher(op1)
3018 ;; daddiu op0,op0,%hi(op1)
3021 ;; The split is deferred until after flow2 to allow the peephole2 below
3023 (define_insn_and_split "*lea_high64"
3024 [(set (match_operand:DI 0 "register_operand" "=d")
3025 (high:DI (match_operand:DI 1 "general_symbolic_operand" "")))]
3026 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3028 "&& flow2_completed"
3029 [(set (match_dup 0) (high:DI (match_dup 2)))
3030 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3031 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3032 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3033 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3035 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3036 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3038 [(set_attr "length" "20")])
3040 ;; Use a scratch register to reduce the latency of the above pattern
3041 ;; on superscalar machines. The optimized sequence is:
3043 ;; lui op1,%highest(op2)
3045 ;; daddiu op1,op1,%higher(op2)
3047 ;; daddu op1,op1,op0
3049 [(set (match_operand:DI 1 "register_operand")
3050 (high:DI (match_operand:DI 2 "general_symbolic_operand")))
3051 (match_scratch:DI 0 "d")]
3052 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3053 [(set (match_dup 1) (high:DI (match_dup 3)))
3054 (set (match_dup 0) (high:DI (match_dup 4)))
3055 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3056 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3057 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3059 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3060 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3063 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3064 ;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine
3065 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3066 ;; used once. We can then use the sequence:
3068 ;; lui op0,%highest(op1)
3070 ;; daddiu op0,op0,%higher(op1)
3071 ;; daddiu op2,op2,%lo(op1)
3073 ;; daddu op0,op0,op2
3075 ;; which takes 4 cycles on most superscalar targets.
3076 (define_insn_and_split "*lea64"
3077 [(set (match_operand:DI 0 "register_operand" "=d")
3078 (match_operand:DI 1 "general_symbolic_operand" ""))
3079 (clobber (match_scratch:DI 2 "=&d"))]
3080 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3082 "&& reload_completed"
3083 [(set (match_dup 0) (high:DI (match_dup 3)))
3084 (set (match_dup 2) (high:DI (match_dup 4)))
3085 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3086 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3087 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3088 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3090 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3091 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3093 [(set_attr "length" "24")])
3095 ;; Insns to fetch a global symbol from a big GOT.
3097 (define_insn_and_split "*xgot_hi<mode>"
3098 [(set (match_operand:P 0 "register_operand" "=d")
3099 (high:P (match_operand:P 1 "global_got_operand" "")))]
3100 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3102 "&& reload_completed"
3103 [(set (match_dup 0) (high:P (match_dup 2)))
3104 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3106 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
3107 operands[3] = pic_offset_table_rtx;
3109 [(set_attr "got" "xgot_high")
3110 (set_attr "mode" "<MODE>")])
3112 (define_insn_and_split "*xgot_lo<mode>"
3113 [(set (match_operand:P 0 "register_operand" "=d")
3114 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3115 (match_operand:P 2 "global_got_operand" "")))]
3116 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3118 "&& reload_completed"
3120 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3121 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_GLOBAL); }
3122 [(set_attr "got" "load")
3123 (set_attr "mode" "<MODE>")])
3125 ;; Insns to fetch a global symbol from a normal GOT.
3127 (define_insn_and_split "*got_disp<mode>"
3128 [(set (match_operand:P 0 "register_operand" "=d")
3129 (match_operand:P 1 "global_got_operand" ""))]
3130 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3132 "&& reload_completed"
3134 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3136 operands[2] = pic_offset_table_rtx;
3137 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
3139 [(set_attr "got" "load")
3140 (set_attr "mode" "<MODE>")])
3142 ;; Insns for loading the high part of a local symbol.
3144 (define_insn_and_split "*got_page<mode>"
3145 [(set (match_operand:P 0 "register_operand" "=d")
3146 (high:P (match_operand:P 1 "local_got_operand" "")))]
3147 "TARGET_EXPLICIT_RELOCS"
3149 "&& reload_completed"
3151 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3153 operands[2] = pic_offset_table_rtx;
3154 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3156 [(set_attr "got" "load")
3157 (set_attr "mode" "<MODE>")])
3159 ;; Lower-level instructions for loading an address from the GOT.
3160 ;; We could use MEMs, but an unspec gives more optimization
3163 (define_insn "load_got<mode>"
3164 [(set (match_operand:P 0 "register_operand" "=d")
3165 (unspec:P [(match_operand:P 1 "register_operand" "d")
3166 (match_operand:P 2 "immediate_operand" "")]
3169 "<load>\t%0,%R2(%1)"
3170 [(set_attr "type" "load")
3171 (set_attr "mode" "<MODE>")
3172 (set_attr "length" "4")])
3174 ;; Instructions for adding the low 16 bits of an address to a register.
3175 ;; Operand 2 is the address: print_operand works out which relocation
3176 ;; should be applied.
3178 (define_insn "*low<mode>"
3179 [(set (match_operand:P 0 "register_operand" "=d")
3180 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3181 (match_operand:P 2 "immediate_operand" "")))]
3183 "<d>addiu\t%0,%1,%R2"
3184 [(set_attr "type" "arith")
3185 (set_attr "mode" "<MODE>")])
3187 (define_insn "*low<mode>_mips16"
3188 [(set (match_operand:P 0 "register_operand" "=d")
3189 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3190 (match_operand:P 2 "immediate_operand" "")))]
3193 [(set_attr "type" "arith")
3194 (set_attr "mode" "<MODE>")
3195 (set_attr "length" "8")])
3197 ;; Allow combine to split complex const_int load sequences, using operand 2
3198 ;; to store the intermediate results. See move_operand for details.
3200 [(set (match_operand:GPR 0 "register_operand")
3201 (match_operand:GPR 1 "splittable_const_int_operand"))
3202 (clobber (match_operand:GPR 2 "register_operand"))]
3206 mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
3210 ;; Likewise, for symbolic operands.
3212 [(set (match_operand:P 0 "register_operand")
3213 (match_operand:P 1 "splittable_symbolic_operand"))
3214 (clobber (match_operand:P 2 "register_operand"))]
3216 [(set (match_dup 0) (match_dup 1))]
3217 { operands[1] = mips_split_symbol (operands[2], operands[1]); })
3219 ;; 64-bit integer moves
3221 ;; Unlike most other insns, the move insns can't be split with
3222 ;; different predicates, because register spilling and other parts of
3223 ;; the compiler, have memoized the insn number already.
3225 (define_expand "movdi"
3226 [(set (match_operand:DI 0 "")
3227 (match_operand:DI 1 ""))]
3230 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3234 ;; For mips16, we need a special case to handle storing $31 into
3235 ;; memory, since we don't have a constraint to match $31. This
3236 ;; instruction can be generated by save_restore_insns.
3238 (define_insn "*mov<mode>_ra"
3239 [(set (match_operand:GPR 0 "stack_operand" "=m")
3243 [(set_attr "type" "store")
3244 (set_attr "mode" "<MODE>")])
3246 (define_insn "*movdi_32bit"
3247 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3248 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3249 "!TARGET_64BIT && !TARGET_MIPS16
3250 && (register_operand (operands[0], DImode)
3251 || reg_or_0_operand (operands[1], DImode))"
3252 { return mips_output_move (operands[0], operands[1]); }
3253 [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,xfer,load,xfer,store")
3254 (set_attr "mode" "DI")
3255 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3257 (define_insn "*movdi_32bit_mips16"
3258 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3259 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3260 "!TARGET_64BIT && TARGET_MIPS16
3261 && (register_operand (operands[0], DImode)
3262 || register_operand (operands[1], DImode))"
3263 { return mips_output_move (operands[0], operands[1]); }
3264 [(set_attr "type" "arith,arith,arith,arith,arith,load,store,mfhilo")
3265 (set_attr "mode" "DI")
3266 (set_attr "length" "8,8,8,8,12,*,*,8")])
3268 (define_insn "*movdi_64bit"
3269 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3270 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3271 "TARGET_64BIT && !TARGET_MIPS16
3272 && (register_operand (operands[0], DImode)
3273 || reg_or_0_operand (operands[1], DImode))"
3274 { return mips_output_move (operands[0], operands[1]); }
3275 [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,mthilo,xfer,load,xfer,store")
3276 (set_attr "mode" "DI")
3277 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
3279 (define_insn "*movdi_64bit_mips16"
3280 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3281 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3282 "TARGET_64BIT && TARGET_MIPS16
3283 && (register_operand (operands[0], DImode)
3284 || register_operand (operands[1], DImode))"
3285 { return mips_output_move (operands[0], operands[1]); }
3286 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3287 (set_attr "mode" "DI")
3288 (set_attr_alternative "length"
3292 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3295 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3300 (const_string "*")])])
3303 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3304 ;; when the original load is a 4 byte instruction but the add and the
3305 ;; load are 2 2 byte instructions.
3308 [(set (match_operand:DI 0 "register_operand")
3309 (mem:DI (plus:DI (match_dup 0)
3310 (match_operand:DI 1 "const_int_operand"))))]
3311 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3312 && !TARGET_DEBUG_D_MODE
3313 && REG_P (operands[0])
3314 && M16_REG_P (REGNO (operands[0]))
3315 && GET_CODE (operands[1]) == CONST_INT
3316 && ((INTVAL (operands[1]) < 0
3317 && INTVAL (operands[1]) >= -0x10)
3318 || (INTVAL (operands[1]) >= 32 * 8
3319 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3320 || (INTVAL (operands[1]) >= 0
3321 && INTVAL (operands[1]) < 32 * 8
3322 && (INTVAL (operands[1]) & 7) != 0))"
3323 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3324 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3326 HOST_WIDE_INT val = INTVAL (operands[1]);
3329 operands[2] = const0_rtx;
3330 else if (val >= 32 * 8)
3334 operands[1] = GEN_INT (0x8 + off);
3335 operands[2] = GEN_INT (val - off - 0x8);
3341 operands[1] = GEN_INT (off);
3342 operands[2] = GEN_INT (val - off);
3346 ;; 32-bit Integer moves
3348 ;; Unlike most other insns, the move insns can't be split with
3349 ;; different predicates, because register spilling and other parts of
3350 ;; the compiler, have memoized the insn number already.
3352 (define_expand "movsi"
3353 [(set (match_operand:SI 0 "")
3354 (match_operand:SI 1 ""))]
3357 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3361 ;; The difference between these two is whether or not ints are allowed
3362 ;; in FP registers (off by default, use -mdebugh to enable).
3364 (define_insn "*movsi_internal"
3365 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3366 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3368 && (register_operand (operands[0], SImode)
3369 || reg_or_0_operand (operands[1], SImode))"
3370 { return mips_output_move (operands[0], operands[1]); }
3371 [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,mfhilo,xfer,load,xfer,store")
3372 (set_attr "mode" "SI")
3373 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
3375 (define_insn "*movsi_mips16"
3376 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3377 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3379 && (register_operand (operands[0], SImode)
3380 || register_operand (operands[1], SImode))"
3381 { return mips_output_move (operands[0], operands[1]); }
3382 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3383 (set_attr "mode" "SI")
3384 (set_attr_alternative "length"
3388 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3391 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3396 (const_string "*")])])
3398 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3399 ;; when the original load is a 4 byte instruction but the add and the
3400 ;; load are 2 2 byte instructions.
3403 [(set (match_operand:SI 0 "register_operand")
3404 (mem:SI (plus:SI (match_dup 0)
3405 (match_operand:SI 1 "const_int_operand"))))]
3406 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3407 && REG_P (operands[0])
3408 && M16_REG_P (REGNO (operands[0]))
3409 && GET_CODE (operands[1]) == CONST_INT
3410 && ((INTVAL (operands[1]) < 0
3411 && INTVAL (operands[1]) >= -0x80)
3412 || (INTVAL (operands[1]) >= 32 * 4
3413 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3414 || (INTVAL (operands[1]) >= 0
3415 && INTVAL (operands[1]) < 32 * 4
3416 && (INTVAL (operands[1]) & 3) != 0))"
3417 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3418 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3420 HOST_WIDE_INT val = INTVAL (operands[1]);
3423 operands[2] = const0_rtx;
3424 else if (val >= 32 * 4)
3428 operands[1] = GEN_INT (0x7c + off);
3429 operands[2] = GEN_INT (val - off - 0x7c);
3435 operands[1] = GEN_INT (off);
3436 operands[2] = GEN_INT (val - off);
3440 ;; On the mips16, we can split a load of certain constants into a load
3441 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3445 [(set (match_operand:SI 0 "register_operand")
3446 (match_operand:SI 1 "const_int_operand"))]
3447 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3448 && REG_P (operands[0])
3449 && M16_REG_P (REGNO (operands[0]))
3450 && GET_CODE (operands[1]) == CONST_INT
3451 && INTVAL (operands[1]) >= 0x100
3452 && INTVAL (operands[1]) <= 0xff + 0x7f"
3453 [(set (match_dup 0) (match_dup 1))
3454 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3456 int val = INTVAL (operands[1]);
3458 operands[1] = GEN_INT (0xff);
3459 operands[2] = GEN_INT (val - 0xff);
3462 ;; This insn handles moving CCmode values. It's really just a
3463 ;; slightly simplified copy of movsi_internal2, with additional cases
3464 ;; to move a condition register to a general register and to move
3465 ;; between the general registers and the floating point registers.
3467 (define_insn "movcc"
3468 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3469 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3470 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3471 { return mips_output_move (operands[0], operands[1]); }
3472 [(set_attr "type" "xfer,arith,load,store,xfer,xfer,fmove,fpload,fpstore")
3473 (set_attr "mode" "SI")
3474 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3476 ;; Reload condition code registers. reload_incc and reload_outcc
3477 ;; both handle moves from arbitrary operands into condition code
3478 ;; registers. reload_incc handles the more common case in which
3479 ;; a source operand is constrained to be in a condition-code
3480 ;; register, but has not been allocated to one.
3482 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3483 ;; constraints do not include 'z'. reload_outcc handles the case
3484 ;; when such an operand is allocated to a condition-code register.
3486 ;; Note that reloads from a condition code register to some
3487 ;; other location can be done using ordinary moves. Moving
3488 ;; into a GPR takes a single movcc, moving elsewhere takes
3489 ;; two. We can leave these cases to the generic reload code.
3490 (define_expand "reload_incc"
3491 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3492 (match_operand:CC 1 "general_operand" ""))
3493 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3494 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3496 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3500 (define_expand "reload_outcc"
3501 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3502 (match_operand:CC 1 "register_operand" ""))
3503 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3504 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3506 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3510 ;; MIPS4 supports loading and storing a floating point register from
3511 ;; the sum of two general registers. We use two versions for each of
3512 ;; these four instructions: one where the two general registers are
3513 ;; SImode, and one where they are DImode. This is because general
3514 ;; registers will be in SImode when they hold 32 bit values, but,
3515 ;; since the 32 bit values are always sign extended, the [ls][wd]xc1
3516 ;; instructions will still work correctly.
3518 ;; ??? Perhaps it would be better to support these instructions by
3519 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3520 ;; these instructions can only be used to load and store floating
3521 ;; point registers, that would probably cause trouble in reload.
3523 (define_insn "*<ANYF:loadx>_<P:mode>"
3524 [(set (match_operand:ANYF 0 "register_operand" "=f")
3525 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3526 (match_operand:P 2 "register_operand" "d"))))]
3528 "<ANYF:loadx>\t%0,%1(%2)"
3529 [(set_attr "type" "fpidxload")
3530 (set_attr "mode" "<ANYF:UNITMODE>")])
3532 (define_insn "*<ANYF:storex>_<P:mode>"
3533 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3534 (match_operand:P 2 "register_operand" "d")))
3535 (match_operand:ANYF 0 "register_operand" "f"))]
3537 "<ANYF:storex>\t%0,%1(%2)"
3538 [(set_attr "type" "fpidxstore")
3539 (set_attr "mode" "<ANYF:UNITMODE>")])
3541 ;; 16-bit Integer moves
3543 ;; Unlike most other insns, the move insns can't be split with
3544 ;; different predicates, because register spilling and other parts of
3545 ;; the compiler, have memoized the insn number already.
3546 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3548 (define_expand "movhi"
3549 [(set (match_operand:HI 0 "")
3550 (match_operand:HI 1 ""))]
3553 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3557 (define_insn "*movhi_internal"
3558 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3559 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3561 && (register_operand (operands[0], HImode)
3562 || reg_or_0_operand (operands[1], HImode))"
3572 [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
3573 (set_attr "mode" "HI")
3574 (set_attr "length" "4,4,*,*,4,4,4,4")])
3576 (define_insn "*movhi_mips16"
3577 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3578 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3580 && (register_operand (operands[0], HImode)
3581 || register_operand (operands[1], HImode))"
3590 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3591 (set_attr "mode" "HI")
3592 (set_attr_alternative "length"
3596 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3599 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3603 (const_string "*")])])
3606 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3607 ;; when the original load is a 4 byte instruction but the add and the
3608 ;; load are 2 2 byte instructions.
3611 [(set (match_operand:HI 0 "register_operand")
3612 (mem:HI (plus:SI (match_dup 0)
3613 (match_operand:SI 1 "const_int_operand"))))]
3614 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3615 && REG_P (operands[0])
3616 && M16_REG_P (REGNO (operands[0]))
3617 && GET_CODE (operands[1]) == CONST_INT
3618 && ((INTVAL (operands[1]) < 0
3619 && INTVAL (operands[1]) >= -0x80)
3620 || (INTVAL (operands[1]) >= 32 * 2
3621 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3622 || (INTVAL (operands[1]) >= 0
3623 && INTVAL (operands[1]) < 32 * 2
3624 && (INTVAL (operands[1]) & 1) != 0))"
3625 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3626 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3628 HOST_WIDE_INT val = INTVAL (operands[1]);
3631 operands[2] = const0_rtx;
3632 else if (val >= 32 * 2)
3636 operands[1] = GEN_INT (0x7e + off);
3637 operands[2] = GEN_INT (val - off - 0x7e);
3643 operands[1] = GEN_INT (off);
3644 operands[2] = GEN_INT (val - off);
3648 ;; 8-bit Integer moves
3650 ;; Unlike most other insns, the move insns can't be split with
3651 ;; different predicates, because register spilling and other parts of
3652 ;; the compiler, have memoized the insn number already.
3653 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3655 (define_expand "movqi"
3656 [(set (match_operand:QI 0 "")
3657 (match_operand:QI 1 ""))]
3660 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3664 (define_insn "*movqi_internal"
3665 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3666 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3668 && (register_operand (operands[0], QImode)
3669 || reg_or_0_operand (operands[1], QImode))"
3679 [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
3680 (set_attr "mode" "QI")
3681 (set_attr "length" "4,4,*,*,4,4,4,4")])
3683 (define_insn "*movqi_mips16"
3684 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3685 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3687 && (register_operand (operands[0], QImode)
3688 || register_operand (operands[1], QImode))"
3697 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3698 (set_attr "mode" "QI")
3699 (set_attr "length" "4,4,4,4,8,*,*")])
3701 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3702 ;; when the original load is a 4 byte instruction but the add and the
3703 ;; load are 2 2 byte instructions.
3706 [(set (match_operand:QI 0 "register_operand")
3707 (mem:QI (plus:SI (match_dup 0)
3708 (match_operand:SI 1 "const_int_operand"))))]
3709 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3710 && REG_P (operands[0])
3711 && M16_REG_P (REGNO (operands[0]))
3712 && GET_CODE (operands[1]) == CONST_INT
3713 && ((INTVAL (operands[1]) < 0
3714 && INTVAL (operands[1]) >= -0x80)
3715 || (INTVAL (operands[1]) >= 32
3716 && INTVAL (operands[1]) <= 31 + 0x7f))"
3717 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3718 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3720 HOST_WIDE_INT val = INTVAL (operands[1]);
3723 operands[2] = const0_rtx;
3726 operands[1] = GEN_INT (0x7f);
3727 operands[2] = GEN_INT (val - 0x7f);
3731 ;; 32-bit floating point moves
3733 (define_expand "movsf"
3734 [(set (match_operand:SF 0 "")
3735 (match_operand:SF 1 ""))]
3738 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3742 (define_insn "*movsf_hardfloat"
3743 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3744 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3746 && (register_operand (operands[0], SFmode)
3747 || reg_or_0_operand (operands[1], SFmode))"
3748 { return mips_output_move (operands[0], operands[1]); }
3749 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3750 (set_attr "mode" "SF")
3751 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3753 (define_insn "*movsf_softfloat"
3754 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3755 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3756 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3757 && (register_operand (operands[0], SFmode)
3758 || reg_or_0_operand (operands[1], SFmode))"
3759 { return mips_output_move (operands[0], operands[1]); }
3760 [(set_attr "type" "arith,load,store")
3761 (set_attr "mode" "SF")
3762 (set_attr "length" "4,*,*")])
3764 (define_insn "*movsf_mips16"
3765 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3766 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3768 && (register_operand (operands[0], SFmode)
3769 || register_operand (operands[1], SFmode))"
3770 { return mips_output_move (operands[0], operands[1]); }
3771 [(set_attr "type" "arith,arith,arith,load,store")
3772 (set_attr "mode" "SF")
3773 (set_attr "length" "4,4,4,*,*")])
3776 ;; 64-bit floating point moves
3778 (define_expand "movdf"
3779 [(set (match_operand:DF 0 "")
3780 (match_operand:DF 1 ""))]
3783 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3787 (define_insn "*movdf_hardfloat_64bit"
3788 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3789 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3790 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3791 && (register_operand (operands[0], DFmode)
3792 || reg_or_0_operand (operands[1], DFmode))"
3793 { return mips_output_move (operands[0], operands[1]); }
3794 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3795 (set_attr "mode" "DF")
3796 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3798 (define_insn "*movdf_hardfloat_32bit"
3799 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3800 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3801 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
3802 && (register_operand (operands[0], DFmode)
3803 || reg_or_0_operand (operands[1], DFmode))"
3804 { return mips_output_move (operands[0], operands[1]); }
3805 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3806 (set_attr "mode" "DF")
3807 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
3809 (define_insn "*movdf_softfloat"
3810 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
3811 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
3812 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
3813 && (register_operand (operands[0], DFmode)
3814 || reg_or_0_operand (operands[1], DFmode))"
3815 { return mips_output_move (operands[0], operands[1]); }
3816 [(set_attr "type" "arith,load,store,xfer,xfer,fmove")
3817 (set_attr "mode" "DF")
3818 (set_attr "length" "8,*,*,4,4,4")])
3820 (define_insn "*movdf_mips16"
3821 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
3822 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
3824 && (register_operand (operands[0], DFmode)
3825 || register_operand (operands[1], DFmode))"
3826 { return mips_output_move (operands[0], operands[1]); }
3827 [(set_attr "type" "arith,arith,arith,load,store")
3828 (set_attr "mode" "DF")
3829 (set_attr "length" "8,8,8,*,*")])
3832 [(set (match_operand:DI 0 "nonimmediate_operand")
3833 (match_operand:DI 1 "move_operand"))]
3834 "reload_completed && !TARGET_64BIT
3835 && mips_split_64bit_move_p (operands[0], operands[1])"
3838 mips_split_64bit_move (operands[0], operands[1]);
3843 [(set (match_operand:DF 0 "nonimmediate_operand")
3844 (match_operand:DF 1 "move_operand"))]
3845 "reload_completed && !TARGET_64BIT
3846 && mips_split_64bit_move_p (operands[0], operands[1])"
3849 mips_split_64bit_move (operands[0], operands[1]);
3853 ;; When generating mips16 code, split moves of negative constants into
3854 ;; a positive "li" followed by a negation.
3856 [(set (match_operand 0 "register_operand")
3857 (match_operand 1 "const_int_operand"))]
3858 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
3862 (neg:SI (match_dup 2)))]
3864 operands[2] = gen_lowpart (SImode, operands[0]);
3865 operands[3] = GEN_INT (-INTVAL (operands[1]));
3868 ;; 64-bit paired-single floating point moves
3870 (define_expand "movv2sf"
3871 [(set (match_operand:V2SF 0)
3872 (match_operand:V2SF 1))]
3873 "TARGET_PAIRED_SINGLE_FLOAT"
3875 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
3879 (define_insn "movv2sf_hardfloat_64bit"
3880 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3881 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
3882 "TARGET_PAIRED_SINGLE_FLOAT
3884 && (register_operand (operands[0], V2SFmode)
3885 || reg_or_0_operand (operands[1], V2SFmode))"
3886 { return mips_output_move (operands[0], operands[1]); }
3887 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3888 (set_attr "mode" "SF")
3889 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3891 ;; The HI and LO registers are not truly independent. If we move an mthi
3892 ;; instruction before an mflo instruction, it will make the result of the
3893 ;; mflo unpredictable. The same goes for mtlo and mfhi.
3895 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
3896 ;; Operand 1 is the register we want, operand 2 is the other one.
3898 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
3899 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
3900 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
3902 (define_expand "mfhilo_<mode>"
3903 [(set (match_operand:GPR 0 "register_operand")
3904 (unspec:GPR [(match_operand:GPR 1 "register_operand")
3905 (match_operand:GPR 2 "register_operand")]
3908 (define_insn "*mfhilo_<mode>"
3909 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3910 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3911 (match_operand:GPR 2 "register_operand" "l,h")]
3915 [(set_attr "type" "mfhilo")
3916 (set_attr "mode" "<MODE>")])
3918 (define_insn "*mfhilo_<mode>_macc"
3919 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3920 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3921 (match_operand:GPR 2 "register_operand" "l,h")]
3925 if (REGNO (operands[1]) == HI_REGNUM)
3926 return "<d>macchi\t%0,%.,%.";
3928 return "<d>macc\t%0,%.,%.";
3930 [(set_attr "type" "mfhilo")
3931 (set_attr "mode" "<MODE>")])
3933 ;; Patterns for loading or storing part of a paired floating point
3934 ;; register. We need them because odd-numbered floating-point registers
3935 ;; are not fully independent: see mips_split_64bit_move.
3937 ;; Load the low word of operand 0 with operand 1.
3938 (define_insn "load_df_low"
3939 [(set (match_operand:DF 0 "register_operand" "=f,f")
3940 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
3941 UNSPEC_LOAD_DF_LOW))]
3942 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3944 operands[0] = mips_subword (operands[0], 0);
3945 return mips_output_move (operands[0], operands[1]);
3947 [(set_attr "type" "xfer,fpload")
3948 (set_attr "mode" "SF")])
3950 ;; Load the high word of operand 0 from operand 1, preserving the value
3952 (define_insn "load_df_high"
3953 [(set (match_operand:DF 0 "register_operand" "=f,f")
3954 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
3955 (match_operand:DF 2 "register_operand" "0,0")]
3956 UNSPEC_LOAD_DF_HIGH))]
3957 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3959 operands[0] = mips_subword (operands[0], 1);
3960 return mips_output_move (operands[0], operands[1]);
3962 [(set_attr "type" "xfer,fpload")
3963 (set_attr "mode" "SF")])
3965 ;; Store the high word of operand 1 in operand 0. The corresponding
3966 ;; low-word move is done in the normal way.
3967 (define_insn "store_df_high"
3968 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
3969 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
3970 UNSPEC_STORE_DF_HIGH))]
3971 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3973 operands[1] = mips_subword (operands[1], 1);
3974 return mips_output_move (operands[0], operands[1]);
3976 [(set_attr "type" "xfer,fpstore")
3977 (set_attr "mode" "SF")])
3979 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
3980 ;; of _gp from the start of this function. Operand 1 is the incoming
3981 ;; function address.
3982 (define_insn_and_split "loadgp"
3983 [(unspec_volatile [(match_operand 0 "" "")
3984 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
3985 "TARGET_ABICALLS && TARGET_NEWABI"
3988 [(set (match_dup 2) (match_dup 3))
3989 (set (match_dup 2) (match_dup 4))
3990 (set (match_dup 2) (match_dup 5))]
3992 operands[2] = pic_offset_table_rtx;
3993 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
3994 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
3995 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
3997 [(set_attr "length" "12")])
3999 ;; The use of gp is hidden when not using explicit relocations.
4000 ;; This blockage instruction prevents the gp load from being
4001 ;; scheduled after an implicit use of gp. It also prevents
4002 ;; the load from being deleted as dead.
4003 (define_insn "loadgp_blockage"
4004 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
4007 [(set_attr "type" "unknown")
4008 (set_attr "mode" "none")
4009 (set_attr "length" "0")])
4011 ;; Emit a .cprestore directive, which normally expands to a single store
4012 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4013 ;; code so that jals inside inline asms will work correctly.
4014 (define_insn "cprestore"
4015 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")]
4019 if (set_nomacro && which_alternative == 1)
4020 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4022 return ".cprestore\t%0";
4024 [(set_attr "type" "store")
4025 (set_attr "length" "4,12")])
4027 ;; Block moves, see mips.c for more details.
4028 ;; Argument 0 is the destination
4029 ;; Argument 1 is the source
4030 ;; Argument 2 is the length
4031 ;; Argument 3 is the alignment
4033 (define_expand "movmemsi"
4034 [(parallel [(set (match_operand:BLK 0 "general_operand")
4035 (match_operand:BLK 1 "general_operand"))
4036 (use (match_operand:SI 2 ""))
4037 (use (match_operand:SI 3 "const_int_operand"))])]
4038 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4040 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4047 ;; ....................
4051 ;; ....................
4053 (define_expand "<optab><mode>3"
4054 [(set (match_operand:GPR 0 "register_operand")
4055 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4056 (match_operand:SI 2 "arith_operand")))]
4059 /* On the mips16, a shift of more than 8 is a four byte instruction,
4060 so, for a shift between 8 and 16, it is just as fast to do two
4061 shifts of 8 or less. If there is a lot of shifting going on, we
4062 may win in CSE. Otherwise combine will put the shifts back
4063 together again. This can be called by function_arg, so we must
4064 be careful not to allocate a new register if we've reached the
4068 && GET_CODE (operands[2]) == CONST_INT
4069 && INTVAL (operands[2]) > 8
4070 && INTVAL (operands[2]) <= 16
4071 && !reload_in_progress
4072 && !reload_completed)
4074 rtx temp = gen_reg_rtx (<MODE>mode);
4076 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4077 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4078 GEN_INT (INTVAL (operands[2]) - 8)));
4083 (define_insn "*<optab><mode>3"
4084 [(set (match_operand:GPR 0 "register_operand" "=d")
4085 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4086 (match_operand:SI 2 "arith_operand" "dI")))]
4089 if (GET_CODE (operands[2]) == CONST_INT)
4090 operands[2] = GEN_INT (INTVAL (operands[2])
4091 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4093 return "<d><insn>\t%0,%1,%2";
4095 [(set_attr "type" "shift")
4096 (set_attr "mode" "<MODE>")])
4098 (define_insn "*<optab>si3_extend"
4099 [(set (match_operand:DI 0 "register_operand" "=d")
4101 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4102 (match_operand:SI 2 "arith_operand" "dI"))))]
4103 "TARGET_64BIT && !TARGET_MIPS16"
4105 if (GET_CODE (operands[2]) == CONST_INT)
4106 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4108 return "<insn>\t%0,%1,%2";
4110 [(set_attr "type" "shift")
4111 (set_attr "mode" "SI")])
4113 (define_insn "*<optab>si3_mips16"
4114 [(set (match_operand:SI 0 "register_operand" "=d,d")
4115 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4116 (match_operand:SI 2 "arith_operand" "d,I")))]
4119 if (which_alternative == 0)
4120 return "<insn>\t%0,%2";
4122 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4123 return "<insn>\t%0,%1,%2";
4125 [(set_attr "type" "shift")
4126 (set_attr "mode" "SI")
4127 (set_attr_alternative "length"
4129 (if_then_else (match_operand 2 "m16_uimm3_b")
4133 ;; We need separate DImode MIPS16 patterns because of the irregularity
4135 (define_insn "*ashldi3_mips16"
4136 [(set (match_operand:DI 0 "register_operand" "=d,d")
4137 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4138 (match_operand:SI 2 "arith_operand" "d,I")))]
4139 "TARGET_64BIT && TARGET_MIPS16"
4141 if (which_alternative == 0)
4142 return "dsll\t%0,%2";
4144 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4145 return "dsll\t%0,%1,%2";
4147 [(set_attr "type" "shift")
4148 (set_attr "mode" "DI")
4149 (set_attr_alternative "length"
4151 (if_then_else (match_operand 2 "m16_uimm3_b")
4155 (define_insn "*ashrdi3_mips16"
4156 [(set (match_operand:DI 0 "register_operand" "=d,d")
4157 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4158 (match_operand:SI 2 "arith_operand" "d,I")))]
4159 "TARGET_64BIT && TARGET_MIPS16"
4161 if (GET_CODE (operands[2]) == CONST_INT)
4162 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4164 return "dsra\t%0,%2";
4166 [(set_attr "type" "shift")
4167 (set_attr "mode" "DI")
4168 (set_attr_alternative "length"
4170 (if_then_else (match_operand 2 "m16_uimm3_b")
4174 (define_insn "*lshrdi3_mips16"
4175 [(set (match_operand:DI 0 "register_operand" "=d,d")
4176 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4177 (match_operand:SI 2 "arith_operand" "d,I")))]
4178 "TARGET_64BIT && TARGET_MIPS16"
4180 if (GET_CODE (operands[2]) == CONST_INT)
4181 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4183 return "dsrl\t%0,%2";
4185 [(set_attr "type" "shift")
4186 (set_attr "mode" "DI")
4187 (set_attr_alternative "length"
4189 (if_then_else (match_operand 2 "m16_uimm3_b")
4193 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4196 [(set (match_operand:GPR 0 "register_operand")
4197 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4198 (match_operand:GPR 2 "const_int_operand")))]
4199 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4200 && GET_CODE (operands[2]) == CONST_INT
4201 && INTVAL (operands[2]) > 8
4202 && INTVAL (operands[2]) <= 16"
4203 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4204 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4205 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4207 ;; If we load a byte on the mips16 as a bitfield, the resulting
4208 ;; sequence of instructions is too complicated for combine, because it
4209 ;; involves four instructions: a load, a shift, a constant load into a
4210 ;; register, and an and (the key problem here is that the mips16 does
4211 ;; not have and immediate). We recognize a shift of a load in order
4212 ;; to make it simple enough for combine to understand.
4214 ;; The length here is the worst case: the length of the split version
4215 ;; will be more accurate.
4216 (define_insn_and_split ""
4217 [(set (match_operand:SI 0 "register_operand" "=d")
4218 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4219 (match_operand:SI 2 "immediate_operand" "I")))]
4223 [(set (match_dup 0) (match_dup 1))
4224 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4226 [(set_attr "type" "load")
4227 (set_attr "mode" "SI")
4228 (set_attr "length" "16")])
4230 (define_insn "rotr<mode>3"
4231 [(set (match_operand:GPR 0 "register_operand" "=d")
4232 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4233 (match_operand:SI 2 "arith_operand" "dI")))]
4234 "ISA_HAS_ROTR_<MODE>"
4236 if (GET_CODE (operands[2]) == CONST_INT)
4237 gcc_assert (INTVAL (operands[2]) >= 0
4238 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4240 return "<d>ror\t%0,%1,%2";
4242 [(set_attr "type" "shift")
4243 (set_attr "mode" "<MODE>")])
4246 ;; ....................
4250 ;; ....................
4252 ;; Flow here is rather complex:
4254 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4255 ;; into cmp_operands[] but generates no RTL.
4257 ;; 2) The appropriate branch define_expand is called, which then
4258 ;; creates the appropriate RTL for the comparison and branch.
4259 ;; Different CC modes are used, based on what type of branch is
4260 ;; done, so that we can constrain things appropriately. There
4261 ;; are assumptions in the rest of GCC that break if we fold the
4262 ;; operands into the branches for integer operations, and use cc0
4263 ;; for floating point, so we use the fp status register instead.
4264 ;; If needed, an appropriate temporary is created to hold the
4265 ;; of the integer compare.
4267 (define_expand "cmp<mode>"
4269 (compare:CC (match_operand:GPR 0 "register_operand")
4270 (match_operand:GPR 1 "nonmemory_operand")))]
4273 cmp_operands[0] = operands[0];
4274 cmp_operands[1] = operands[1];
4278 (define_expand "cmp<mode>"
4280 (compare:CC (match_operand:SCALARF 0 "register_operand")
4281 (match_operand:SCALARF 1 "register_operand")))]
4284 cmp_operands[0] = operands[0];
4285 cmp_operands[1] = operands[1];
4290 ;; ....................
4292 ;; CONDITIONAL BRANCHES
4294 ;; ....................
4296 ;; Conditional branches on floating-point equality tests.
4298 (define_insn "*branch_fp"
4301 (match_operator 0 "equality_operator"
4302 [(match_operand:CC 2 "register_operand" "z")
4304 (label_ref (match_operand 1 "" ""))
4308 return mips_output_conditional_branch (insn, operands,
4309 MIPS_BRANCH ("b%F0", "%Z2%1"),
4310 MIPS_BRANCH ("b%W0", "%Z2%1"));
4312 [(set_attr "type" "branch")
4313 (set_attr "mode" "none")])
4315 (define_insn "*branch_fp_inverted"
4318 (match_operator 0 "equality_operator"
4319 [(match_operand:CC 2 "register_operand" "z")
4322 (label_ref (match_operand 1 "" ""))))]
4325 return mips_output_conditional_branch (insn, operands,
4326 MIPS_BRANCH ("b%W0", "%Z2%1"),
4327 MIPS_BRANCH ("b%F0", "%Z2%1"));
4329 [(set_attr "type" "branch")
4330 (set_attr "mode" "none")])
4332 ;; Conditional branches on ordered comparisons with zero.
4334 (define_insn "*branch_order<mode>"
4337 (match_operator 0 "order_operator"
4338 [(match_operand:GPR 2 "register_operand" "d")
4340 (label_ref (match_operand 1 "" ""))
4343 { return mips_output_order_conditional_branch (insn, operands, false); }
4344 [(set_attr "type" "branch")
4345 (set_attr "mode" "none")])
4347 (define_insn "*branch_order<mode>_inverted"
4350 (match_operator 0 "order_operator"
4351 [(match_operand:GPR 2 "register_operand" "d")
4354 (label_ref (match_operand 1 "" ""))))]
4356 { return mips_output_order_conditional_branch (insn, operands, true); }
4357 [(set_attr "type" "branch")
4358 (set_attr "mode" "none")])
4360 ;; Conditional branch on equality comparison.
4362 (define_insn "*branch_equality<mode>"
4365 (match_operator 0 "equality_operator"
4366 [(match_operand:GPR 2 "register_operand" "d")
4367 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4368 (label_ref (match_operand 1 "" ""))
4372 return mips_output_conditional_branch (insn, operands,
4373 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
4374 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
4376 [(set_attr "type" "branch")
4377 (set_attr "mode" "none")])
4379 (define_insn "*branch_equality<mode>_inverted"
4382 (match_operator 0 "equality_operator"
4383 [(match_operand:GPR 2 "register_operand" "d")
4384 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4386 (label_ref (match_operand 1 "" ""))))]
4389 return mips_output_conditional_branch (insn, operands,
4390 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
4391 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
4393 [(set_attr "type" "branch")
4394 (set_attr "mode" "none")])
4398 (define_insn "*branch_equality<mode>_mips16"
4401 (match_operator 0 "equality_operator"
4402 [(match_operand:GPR 1 "register_operand" "d,t")
4404 (match_operand 2 "pc_or_label_operand" "")
4405 (match_operand 3 "pc_or_label_operand" "")))]
4408 if (operands[2] != pc_rtx)
4410 if (which_alternative == 0)
4411 return "b%C0z\t%1,%2";
4413 return "bt%C0z\t%2";
4417 if (which_alternative == 0)
4418 return "b%N0z\t%1,%3";
4420 return "bt%N0z\t%3";
4423 [(set_attr "type" "branch")
4424 (set_attr "mode" "none")
4425 (set_attr "length" "8")])
4427 (define_expand "b<code>"
4429 (if_then_else (any_cond:CC (cc0)
4431 (label_ref (match_operand 0 ""))
4435 gen_conditional_branch (operands, <CODE>);
4439 ;; Used to implement built-in functions.
4440 (define_expand "condjump"
4442 (if_then_else (match_operand 0)
4443 (label_ref (match_operand 1))
4447 ;; ....................
4449 ;; SETTING A REGISTER FROM A COMPARISON
4451 ;; ....................
4453 (define_expand "seq"
4454 [(set (match_operand:SI 0 "register_operand")
4455 (eq:SI (match_dup 1)
4458 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
4460 (define_insn "*seq_<mode>"
4461 [(set (match_operand:GPR 0 "register_operand" "=d")
4462 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4466 [(set_attr "type" "slt")
4467 (set_attr "mode" "<MODE>")])
4469 (define_insn "*seq_<mode>_mips16"
4470 [(set (match_operand:GPR 0 "register_operand" "=t")
4471 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4475 [(set_attr "type" "slt")
4476 (set_attr "mode" "<MODE>")])
4478 ;; "sne" uses sltu instructions in which the first operand is $0.
4479 ;; This isn't possible in mips16 code.
4481 (define_expand "sne"
4482 [(set (match_operand:SI 0 "register_operand")
4483 (ne:SI (match_dup 1)
4486 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
4488 (define_insn "*sne_<mode>"
4489 [(set (match_operand:GPR 0 "register_operand" "=d")
4490 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
4494 [(set_attr "type" "slt")
4495 (set_attr "mode" "<MODE>")])
4497 (define_expand "sgt"
4498 [(set (match_operand:SI 0 "register_operand")
4499 (gt:SI (match_dup 1)
4502 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
4504 (define_insn "*sgt_<mode>"
4505 [(set (match_operand:GPR 0 "register_operand" "=d")
4506 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4507 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4510 [(set_attr "type" "slt")
4511 (set_attr "mode" "<MODE>")])
4513 (define_insn "*sgt_<mode>_mips16"
4514 [(set (match_operand:GPR 0 "register_operand" "=t")
4515 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4516 (match_operand:GPR 2 "register_operand" "d")))]
4519 [(set_attr "type" "slt")
4520 (set_attr "mode" "<MODE>")])
4522 (define_expand "sge"
4523 [(set (match_operand:SI 0 "register_operand")
4524 (ge:SI (match_dup 1)
4527 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
4529 (define_insn "*sge_<mode>"
4530 [(set (match_operand:GPR 0 "register_operand" "=d")
4531 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
4535 [(set_attr "type" "slt")
4536 (set_attr "mode" "<MODE>")])
4538 (define_expand "slt"
4539 [(set (match_operand:SI 0 "register_operand")
4540 (lt:SI (match_dup 1)
4543 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
4545 (define_insn "*slt_<mode>"
4546 [(set (match_operand:GPR 0 "register_operand" "=d")
4547 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
4548 (match_operand:GPR 2 "arith_operand" "dI")))]
4551 [(set_attr "type" "slt")
4552 (set_attr "mode" "<MODE>")])
4554 (define_insn "*slt_<mode>_mips16"
4555 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4556 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
4557 (match_operand:GPR 2 "arith_operand" "d,I")))]
4560 [(set_attr "type" "slt")
4561 (set_attr "mode" "<MODE>")
4562 (set_attr_alternative "length"
4564 (if_then_else (match_operand 2 "m16_uimm8_1")
4568 (define_expand "sle"
4569 [(set (match_operand:SI 0 "register_operand")
4570 (le:SI (match_dup 1)
4573 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
4575 (define_insn "*sle_<mode>"
4576 [(set (match_operand:GPR 0 "register_operand" "=d")
4577 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4578 (match_operand:GPR 2 "sle_operand" "")))]
4581 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4582 return "slt\t%0,%1,%2";
4584 [(set_attr "type" "slt")
4585 (set_attr "mode" "<MODE>")])
4587 (define_insn "*sle_<mode>_mips16"
4588 [(set (match_operand:GPR 0 "register_operand" "=t")
4589 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4590 (match_operand:GPR 2 "sle_operand" "")))]
4593 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4594 return "slt\t%1,%2";
4596 [(set_attr "type" "slt")
4597 (set_attr "mode" "<MODE>")
4598 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4602 (define_expand "sgtu"
4603 [(set (match_operand:SI 0 "register_operand")
4604 (gtu:SI (match_dup 1)
4607 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
4609 (define_insn "*sgtu_<mode>"
4610 [(set (match_operand:GPR 0 "register_operand" "=d")
4611 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4612 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4615 [(set_attr "type" "slt")
4616 (set_attr "mode" "<MODE>")])
4618 (define_insn "*sgtu_<mode>_mips16"
4619 [(set (match_operand:GPR 0 "register_operand" "=t")
4620 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4621 (match_operand:GPR 2 "register_operand" "d")))]
4624 [(set_attr "type" "slt")
4625 (set_attr "mode" "<MODE>")])
4627 (define_expand "sgeu"
4628 [(set (match_operand:SI 0 "register_operand")
4629 (geu:SI (match_dup 1)
4632 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
4634 (define_insn "*sge_<mode>"
4635 [(set (match_operand:GPR 0 "register_operand" "=d")
4636 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
4640 [(set_attr "type" "slt")
4641 (set_attr "mode" "<MODE>")])
4643 (define_expand "sltu"
4644 [(set (match_operand:SI 0 "register_operand")
4645 (ltu:SI (match_dup 1)
4648 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
4650 (define_insn "*sltu_<mode>"
4651 [(set (match_operand:GPR 0 "register_operand" "=d")
4652 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
4653 (match_operand:GPR 2 "arith_operand" "dI")))]
4656 [(set_attr "type" "slt")
4657 (set_attr "mode" "<MODE>")])
4659 (define_insn "*sltu_<mode>_mips16"
4660 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4661 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
4662 (match_operand:GPR 2 "arith_operand" "d,I")))]
4665 [(set_attr "type" "slt")
4666 (set_attr "mode" "<MODE>")
4667 (set_attr_alternative "length"
4669 (if_then_else (match_operand 2 "m16_uimm8_1")
4673 (define_expand "sleu"
4674 [(set (match_operand:SI 0 "register_operand")
4675 (leu:SI (match_dup 1)
4678 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
4680 (define_insn "*sleu_<mode>"
4681 [(set (match_operand:GPR 0 "register_operand" "=d")
4682 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4683 (match_operand:GPR 2 "sleu_operand" "")))]
4686 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4687 return "sltu\t%0,%1,%2";
4689 [(set_attr "type" "slt")
4690 (set_attr "mode" "<MODE>")])
4692 (define_insn "*sleu_<mode>_mips16"
4693 [(set (match_operand:GPR 0 "register_operand" "=t")
4694 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4695 (match_operand:GPR 2 "sleu_operand" "")))]
4698 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4699 return "sltu\t%1,%2";
4701 [(set_attr "type" "slt")
4702 (set_attr "mode" "<MODE>")
4703 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4708 ;; ....................
4710 ;; FLOATING POINT COMPARISONS
4712 ;; ....................
4714 (define_insn "s<code>_<mode>"
4715 [(set (match_operand:CC 0 "register_operand" "=z")
4716 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4717 (match_operand:SCALARF 2 "register_operand" "f")))]
4719 "c.<fcond>.<fmt>\t%Z0%1,%2"
4720 [(set_attr "type" "fcmp")
4721 (set_attr "mode" "FPSW")])
4723 (define_insn "s<code>_<mode>"
4724 [(set (match_operand:CC 0 "register_operand" "=z")
4725 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4726 (match_operand:SCALARF 2 "register_operand" "f")))]
4728 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
4729 [(set_attr "type" "fcmp")
4730 (set_attr "mode" "FPSW")])
4733 ;; ....................
4735 ;; UNCONDITIONAL BRANCHES
4737 ;; ....................
4739 ;; Unconditional branches.
4743 (label_ref (match_operand 0 "" "")))]
4748 if (get_attr_length (insn) <= 8)
4749 return "%*b\t%l0%/";
4752 output_asm_insn (mips_output_load_label (), operands);
4753 return "%*jr\t%@%/%]";
4757 return "%*j\t%l0%/";
4759 [(set_attr "type" "jump")
4760 (set_attr "mode" "none")
4761 (set (attr "length")
4762 ;; We can't use `j' when emitting PIC. Emit a branch if it's
4763 ;; in range, otherwise load the address of the branch target into
4764 ;; $at and then jump to it.
4766 (ior (eq (symbol_ref "flag_pic") (const_int 0))
4767 (lt (abs (minus (match_dup 0)
4768 (plus (pc) (const_int 4))))
4769 (const_int 131072)))
4770 (const_int 4) (const_int 16)))])
4772 ;; We need a different insn for the mips16, because a mips16 branch
4773 ;; does not have a delay slot.
4777 (label_ref (match_operand 0 "" "")))]
4780 [(set_attr "type" "branch")
4781 (set_attr "mode" "none")
4782 (set_attr "length" "8")])
4784 (define_expand "indirect_jump"
4785 [(set (pc) (match_operand 0 "register_operand"))]
4788 operands[0] = force_reg (Pmode, operands[0]);
4789 if (Pmode == SImode)
4790 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
4792 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
4796 (define_insn "indirect_jump<mode>"
4797 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
4800 [(set_attr "type" "jump")
4801 (set_attr "mode" "none")])
4803 (define_expand "tablejump"
4805 (match_operand 0 "register_operand"))
4806 (use (label_ref (match_operand 1 "")))]
4810 operands[0] = expand_binop (Pmode, add_optab,
4811 convert_to_mode (Pmode, operands[0], false),
4812 gen_rtx_LABEL_REF (Pmode, operands[1]),
4814 else if (TARGET_GPWORD)
4815 operands[0] = expand_binop (Pmode, add_optab, operands[0],
4816 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
4818 if (Pmode == SImode)
4819 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
4821 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
4825 (define_insn "tablejump<mode>"
4827 (match_operand:P 0 "register_operand" "d"))
4828 (use (label_ref (match_operand 1 "" "")))]
4831 [(set_attr "type" "jump")
4832 (set_attr "mode" "none")])
4834 ;; For TARGET_ABICALLS, we save the gp in the jmp_buf as well.
4835 ;; While it is possible to either pull it off the stack (in the
4836 ;; o32 case) or recalculate it given t9 and our target label,
4837 ;; it takes 3 or 4 insns to do so.
4839 (define_expand "builtin_setjmp_setup"
4840 [(use (match_operand 0 "register_operand"))]
4845 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
4846 emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
4850 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
4851 ;; that older code did recalculate the gp from $25. Continue to jump through
4852 ;; $25 for compatibility (we lose nothing by doing so).
4854 (define_expand "builtin_longjmp"
4855 [(use (match_operand 0 "register_operand"))]
4858 /* The elements of the buffer are, in order: */
4859 int W = GET_MODE_SIZE (Pmode);
4860 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
4861 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
4862 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
4863 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
4864 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
4865 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
4866 The target is bound to be using $28 as the global pointer
4867 but the current function might not be. */
4868 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
4870 /* This bit is similar to expand_builtin_longjmp except that it
4871 restores $gp as well. */
4872 emit_move_insn (hard_frame_pointer_rtx, fp);
4873 emit_move_insn (pv, lab);
4874 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
4875 emit_move_insn (gp, gpv);
4876 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
4877 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4878 emit_insn (gen_rtx_USE (VOIDmode, gp));
4879 emit_indirect_jump (pv);
4884 ;; ....................
4886 ;; Function prologue/epilogue
4888 ;; ....................
4891 (define_expand "prologue"
4895 mips_expand_prologue ();
4899 ;; Block any insns from being moved before this point, since the
4900 ;; profiling call to mcount can use various registers that aren't
4901 ;; saved or used to pass arguments.
4903 (define_insn "blockage"
4904 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
4907 [(set_attr "type" "unknown")
4908 (set_attr "mode" "none")
4909 (set_attr "length" "0")])
4911 (define_expand "epilogue"
4915 mips_expand_epilogue (false);
4919 (define_expand "sibcall_epilogue"
4923 mips_expand_epilogue (true);
4927 ;; Trivial return. Make it look like a normal return insn as that
4928 ;; allows jump optimizations to work better.
4930 (define_insn "return"
4932 "mips_can_use_return_insn ()"
4934 [(set_attr "type" "jump")
4935 (set_attr "mode" "none")])
4939 (define_insn "return_internal"
4941 (use (match_operand 0 "pmode_register_operand" ""))]
4944 [(set_attr "type" "jump")
4945 (set_attr "mode" "none")])
4947 ;; This is used in compiling the unwind routines.
4948 (define_expand "eh_return"
4949 [(use (match_operand 0 "general_operand"))]
4952 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
4954 if (GET_MODE (operands[0]) != gpr_mode)
4955 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
4957 emit_insn (gen_eh_set_lr_di (operands[0]));
4959 emit_insn (gen_eh_set_lr_si (operands[0]));
4964 ;; Clobber the return address on the stack. We can't expand this
4965 ;; until we know where it will be put in the stack frame.
4967 (define_insn "eh_set_lr_si"
4968 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
4969 (clobber (match_scratch:SI 1 "=&d"))]
4973 (define_insn "eh_set_lr_di"
4974 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
4975 (clobber (match_scratch:DI 1 "=&d"))]
4980 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
4981 (clobber (match_scratch 1))]
4982 "reload_completed && !TARGET_DEBUG_D_MODE"
4985 mips_set_return_address (operands[0], operands[1]);
4989 (define_insn_and_split "exception_receiver"
4991 (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
4992 "TARGET_ABICALLS && TARGET_OLDABI"
4994 "&& reload_completed"
5000 [(set_attr "type" "load")
5001 (set_attr "length" "12")])
5004 ;; ....................
5008 ;; ....................
5010 ;; Instructions to load a call address from the GOT. The address might
5011 ;; point to a function or to a lazy binding stub. In the latter case,
5012 ;; the stub will use the dynamic linker to resolve the function, which
5013 ;; in turn will change the GOT entry to point to the function's real
5016 ;; This means that every call, even pure and constant ones, can
5017 ;; potentially modify the GOT entry. And once a stub has been called,
5018 ;; we must not call it again.
5020 ;; We represent this restriction using an imaginary fixed register that
5021 ;; acts like a GOT version number. By making the register call-clobbered,
5022 ;; we tell the target-independent code that the address could be changed
5023 ;; by any call insn.
5024 (define_insn "load_call<mode>"
5025 [(set (match_operand:P 0 "register_operand" "=c")
5026 (unspec:P [(match_operand:P 1 "register_operand" "r")
5027 (match_operand:P 2 "immediate_operand" "")
5028 (reg:P FAKE_CALL_REGNO)]
5031 "<load>\t%0,%R2(%1)"
5032 [(set_attr "type" "load")
5033 (set_attr "mode" "<MODE>")
5034 (set_attr "length" "4")])
5036 ;; Sibling calls. All these patterns use jump instructions.
5038 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5039 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5040 ;; is defined in terms of call_insn_operand, the same is true of the
5043 ;; When we use an indirect jump, we need a register that will be
5044 ;; preserved by the epilogue. Since TARGET_ABICALLS forces us to
5045 ;; use $25 for this purpose -- and $25 is never clobbered by the
5046 ;; epilogue -- we might as well use it for !TARGET_ABICALLS as well.
5048 (define_expand "sibcall"
5049 [(parallel [(call (match_operand 0 "")
5050 (match_operand 1 ""))
5051 (use (match_operand 2 "")) ;; next_arg_reg
5052 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5055 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5059 (define_insn "sibcall_internal"
5060 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5061 (match_operand 1 "" ""))]
5062 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5066 [(set_attr "type" "call")])
5068 (define_expand "sibcall_value"
5069 [(parallel [(set (match_operand 0 "")
5070 (call (match_operand 1 "")
5071 (match_operand 2 "")))
5072 (use (match_operand 3 ""))])] ;; next_arg_reg
5075 mips_expand_call (operands[0], XEXP (operands[1], 0),
5076 operands[2], operands[3], true);
5080 (define_insn "sibcall_value_internal"
5081 [(set (match_operand 0 "register_operand" "=df,df")
5082 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5083 (match_operand 2 "" "")))]
5084 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5088 [(set_attr "type" "call")])
5090 (define_insn "sibcall_value_multiple_internal"
5091 [(set (match_operand 0 "register_operand" "=df,df")
5092 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5093 (match_operand 2 "" "")))
5094 (set (match_operand 3 "register_operand" "=df,df")
5095 (call (mem:SI (match_dup 1))
5097 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5101 [(set_attr "type" "call")])
5103 (define_expand "call"
5104 [(parallel [(call (match_operand 0 "")
5105 (match_operand 1 ""))
5106 (use (match_operand 2 "")) ;; next_arg_reg
5107 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5110 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5114 ;; This instruction directly corresponds to an assembly-language "jal".
5115 ;; There are four cases:
5118 ;; Both symbolic and register destinations are OK. The pattern
5119 ;; always expands to a single mips instruction.
5121 ;; - -mabicalls/-mno-explicit-relocs:
5122 ;; Again, both symbolic and register destinations are OK.
5123 ;; The call is treated as a multi-instruction black box.
5125 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5126 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5129 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5130 ;; Only "jal $25" is allowed. The call is actually two instructions:
5131 ;; "jalr $25" followed by an insn to reload $gp.
5133 ;; In the last case, we can generate the individual instructions with
5134 ;; a define_split. There are several things to be wary of:
5136 ;; - We can't expose the load of $gp before reload. If we did,
5137 ;; it might get removed as dead, but reload can introduce new
5138 ;; uses of $gp by rematerializing constants.
5140 ;; - We shouldn't restore $gp after calls that never return.
5141 ;; It isn't valid to insert instructions between a noreturn
5142 ;; call and the following barrier.
5144 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5145 ;; instruction preserves $gp and so have no effect on its liveness.
5146 ;; But once we generate the separate insns, it becomes obvious that
5147 ;; $gp is not live on entry to the call.
5149 ;; ??? The operands[2] = insn check is a hack to make the original insn
5150 ;; available to the splitter.
5151 (define_insn_and_split "call_internal"
5152 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5153 (match_operand 1 "" ""))
5154 (clobber (reg:SI 31))]
5156 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%0%/"; }
5157 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5160 emit_call_insn (gen_call_split (operands[0], operands[1]));
5161 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5165 [(set_attr "jal" "indirect,direct")
5166 (set_attr "extended_mips16" "no,yes")])
5168 (define_insn "call_split"
5169 [(call (mem:SI (match_operand 0 "call_insn_operand" "c"))
5170 (match_operand 1 "" ""))
5171 (clobber (reg:SI 31))
5172 (clobber (reg:SI 28))]
5173 "TARGET_SPLIT_CALLS"
5175 [(set_attr "type" "call")])
5177 (define_expand "call_value"
5178 [(parallel [(set (match_operand 0 "")
5179 (call (match_operand 1 "")
5180 (match_operand 2 "")))
5181 (use (match_operand 3 ""))])] ;; next_arg_reg
5184 mips_expand_call (operands[0], XEXP (operands[1], 0),
5185 operands[2], operands[3], false);
5189 ;; See comment for call_internal.
5190 (define_insn_and_split "call_value_internal"
5191 [(set (match_operand 0 "register_operand" "=df,df")
5192 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5193 (match_operand 2 "" "")))
5194 (clobber (reg:SI 31))]
5196 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
5197 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5200 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5202 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5206 [(set_attr "jal" "indirect,direct")
5207 (set_attr "extended_mips16" "no,yes")])
5209 (define_insn "call_value_split"
5210 [(set (match_operand 0 "register_operand" "=df")
5211 (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
5212 (match_operand 2 "" "")))
5213 (clobber (reg:SI 31))
5214 (clobber (reg:SI 28))]
5215 "TARGET_SPLIT_CALLS"
5217 [(set_attr "type" "call")])
5219 ;; See comment for call_internal.
5220 (define_insn_and_split "call_value_multiple_internal"
5221 [(set (match_operand 0 "register_operand" "=df,df")
5222 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5223 (match_operand 2 "" "")))
5224 (set (match_operand 3 "register_operand" "=df,df")
5225 (call (mem:SI (match_dup 1))
5227 (clobber (reg:SI 31))]
5229 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
5230 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5233 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5234 operands[2], operands[3]));
5235 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5239 [(set_attr "jal" "indirect,direct")
5240 (set_attr "extended_mips16" "no,yes")])
5242 (define_insn "call_value_multiple_split"
5243 [(set (match_operand 0 "register_operand" "=df")
5244 (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
5245 (match_operand 2 "" "")))
5246 (set (match_operand 3 "register_operand" "=df")
5247 (call (mem:SI (match_dup 1))
5249 (clobber (reg:SI 31))
5250 (clobber (reg:SI 28))]
5251 "TARGET_SPLIT_CALLS"
5253 [(set_attr "type" "call")])
5255 ;; Call subroutine returning any type.
5257 (define_expand "untyped_call"
5258 [(parallel [(call (match_operand 0 "")
5260 (match_operand 1 "")
5261 (match_operand 2 "")])]
5266 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5268 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5270 rtx set = XVECEXP (operands[2], 0, i);
5271 emit_move_insn (SET_DEST (set), SET_SRC (set));
5274 emit_insn (gen_blockage ());
5279 ;; ....................
5283 ;; ....................
5287 (define_insn "prefetch"
5288 [(prefetch (match_operand:QI 0 "address_operand" "p")
5289 (match_operand 1 "const_int_operand" "n")
5290 (match_operand 2 "const_int_operand" "n"))]
5291 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5293 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5294 return "pref\t%1,%a0";
5296 [(set_attr "type" "prefetch")])
5298 (define_insn "*prefetch_indexed_<mode>"
5299 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5300 (match_operand:P 1 "register_operand" "d"))
5301 (match_operand 2 "const_int_operand" "n")
5302 (match_operand 3 "const_int_operand" "n"))]
5303 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5305 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5306 return "prefx\t%2,%1(%0)";
5308 [(set_attr "type" "prefetchx")])
5314 [(set_attr "type" "nop")
5315 (set_attr "mode" "none")])
5317 ;; Like nop, but commented out when outside a .set noreorder block.
5318 (define_insn "hazard_nop"
5327 [(set_attr "type" "nop")])
5329 ;; MIPS4 Conditional move instructions.
5331 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5332 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5334 (match_operator:MOVECC 4 "equality_operator"
5335 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5337 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5338 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5343 [(set_attr "type" "condmove")
5344 (set_attr "mode" "<GPR:MODE>")])
5346 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5347 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5348 (if_then_else:SCALARF
5349 (match_operator:MOVECC 4 "equality_operator"
5350 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5352 (match_operand:SCALARF 2 "register_operand" "f,0")
5353 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5356 mov%T4.<fmt>\t%0,%2,%1
5357 mov%t4.<fmt>\t%0,%3,%1"
5358 [(set_attr "type" "condmove")
5359 (set_attr "mode" "<SCALARF:MODE>")])
5361 ;; These are the main define_expand's used to make conditional moves.
5363 (define_expand "mov<mode>cc"
5364 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5365 (set (match_operand:GPR 0 "register_operand")
5366 (if_then_else:GPR (match_dup 5)
5367 (match_operand:GPR 2 "reg_or_0_operand")
5368 (match_operand:GPR 3 "reg_or_0_operand")))]
5371 gen_conditional_move (operands);
5375 (define_expand "mov<mode>cc"
5376 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5377 (set (match_operand:SCALARF 0 "register_operand")
5378 (if_then_else:SCALARF (match_dup 5)
5379 (match_operand:SCALARF 2 "register_operand")
5380 (match_operand:SCALARF 3 "register_operand")))]
5383 gen_conditional_move (operands);
5388 ;; ....................
5390 ;; mips16 inline constant tables
5392 ;; ....................
5395 (define_insn "consttable_int"
5396 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
5397 (match_operand 1 "const_int_operand" "")]
5398 UNSPEC_CONSTTABLE_INT)]
5401 assemble_integer (operands[0], INTVAL (operands[1]),
5402 BITS_PER_UNIT * INTVAL (operands[1]), 1);
5405 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
5407 (define_insn "consttable_float"
5408 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
5409 UNSPEC_CONSTTABLE_FLOAT)]
5414 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
5415 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
5416 assemble_real (d, GET_MODE (operands[0]),
5417 GET_MODE_BITSIZE (GET_MODE (operands[0])));
5420 [(set (attr "length")
5421 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
5423 (define_insn "align"
5424 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
5427 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
5430 [(match_operand 0 "small_data_pattern")]
5433 { operands[0] = mips_rewrite_small_data (operands[0]); })
5435 ; Thread-Local Storage
5437 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
5438 ; MIPS architecture defines this register, and no current
5439 ; implementation provides it; instead, any OS which supports TLS is
5440 ; expected to trap and emulate this instruction. rdhwr is part of the
5441 ; MIPS 32r2 specification, but we use it on any architecture because
5442 ; we expect it to be emulated. Use .set to force the assembler to
5445 (define_insn "tls_get_tp_<mode>"
5446 [(set (match_operand:P 0 "register_operand" "=v")
5447 (unspec:P [(const_int 0)]
5448 UNSPEC_TLS_GET_TP))]
5449 "HAVE_AS_TLS && !TARGET_MIPS16"
5450 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
5451 [(set_attr "type" "unknown")
5452 (set_attr "mode" "<MODE>")])
5454 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
5456 (include "mips-ps-3d.md")
5458 ; The MIPS DSP Instructions.
5460 (include "mips-dsp.md")