1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
5 ;; Changes by Michael Meissner, meissner@osf.org
6 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 ;; Brendan Eich, brendan@microunity.com.
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 2, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING. If not, write to
23 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 ;; Boston, MA 02110-1301, USA.
27 [(UNSPEC_LOAD_DF_LOW 0)
28 (UNSPEC_LOAD_DF_HIGH 1)
29 (UNSPEC_STORE_DF_HIGH 2)
33 (UNSPEC_EH_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
53 (UNSPEC_ADDRESS_FIRST 100)
57 ;; For MIPS Paired-Singled Floating Point Instructions.
59 (UNSPEC_MOVE_TF_PS 200)
62 ;; MIPS64/MIPS32R2 alnv.ps
65 ;; MIPS-3D instructions
69 (UNSPEC_CVT_PW_PS 205)
70 (UNSPEC_CVT_PS_PW 206)
78 (UNSPEC_SINGLE_CC 213)
81 ;; MIPS DSP ASE Revision 0.98 3/24/2005
89 (UNSPEC_RADDU_W_QB 307)
91 (UNSPEC_PRECRQ_QB_PH 309)
92 (UNSPEC_PRECRQ_PH_W 310)
93 (UNSPEC_PRECRQ_RS_PH_W 311)
94 (UNSPEC_PRECRQU_S_QB_PH 312)
95 (UNSPEC_PRECEQ_W_PHL 313)
96 (UNSPEC_PRECEQ_W_PHR 314)
97 (UNSPEC_PRECEQU_PH_QBL 315)
98 (UNSPEC_PRECEQU_PH_QBR 316)
99 (UNSPEC_PRECEQU_PH_QBLA 317)
100 (UNSPEC_PRECEQU_PH_QBRA 318)
101 (UNSPEC_PRECEU_PH_QBL 319)
102 (UNSPEC_PRECEU_PH_QBR 320)
103 (UNSPEC_PRECEU_PH_QBLA 321)
104 (UNSPEC_PRECEU_PH_QBRA 322)
110 (UNSPEC_MULEU_S_PH_QBL 328)
111 (UNSPEC_MULEU_S_PH_QBR 329)
112 (UNSPEC_MULQ_RS_PH 330)
113 (UNSPEC_MULEQ_S_W_PHL 331)
114 (UNSPEC_MULEQ_S_W_PHR 332)
115 (UNSPEC_DPAU_H_QBL 333)
116 (UNSPEC_DPAU_H_QBR 334)
117 (UNSPEC_DPSU_H_QBL 335)
118 (UNSPEC_DPSU_H_QBR 336)
119 (UNSPEC_DPAQ_S_W_PH 337)
120 (UNSPEC_DPSQ_S_W_PH 338)
121 (UNSPEC_MULSAQ_S_W_PH 339)
122 (UNSPEC_DPAQ_SA_L_W 340)
123 (UNSPEC_DPSQ_SA_L_W 341)
124 (UNSPEC_MAQ_S_W_PHL 342)
125 (UNSPEC_MAQ_S_W_PHR 343)
126 (UNSPEC_MAQ_SA_W_PHL 344)
127 (UNSPEC_MAQ_SA_W_PHR 345)
135 (UNSPEC_CMPGU_EQ_QB 353)
136 (UNSPEC_CMPGU_LT_QB 354)
137 (UNSPEC_CMPGU_LE_QB 355)
139 (UNSPEC_PACKRL_PH 357)
141 (UNSPEC_EXTR_R_W 359)
142 (UNSPEC_EXTR_RS_W 360)
143 (UNSPEC_EXTR_S_H 361)
151 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
152 (UNSPEC_ABSQ_S_QB 400)
154 (UNSPEC_ADDU_S_PH 402)
155 (UNSPEC_ADDUH_QB 403)
156 (UNSPEC_ADDUH_R_QB 404)
159 (UNSPEC_CMPGDU_EQ_QB 407)
160 (UNSPEC_CMPGDU_LT_QB 408)
161 (UNSPEC_CMPGDU_LE_QB 409)
162 (UNSPEC_DPA_W_PH 410)
163 (UNSPEC_DPS_W_PH 411)
169 (UNSPEC_MUL_S_PH 417)
170 (UNSPEC_MULQ_RS_W 418)
171 (UNSPEC_MULQ_S_PH 419)
172 (UNSPEC_MULQ_S_W 420)
173 (UNSPEC_MULSA_W_PH 421)
176 (UNSPEC_PRECR_QB_PH 424)
177 (UNSPEC_PRECR_SRA_PH_W 425)
178 (UNSPEC_PRECR_SRA_R_PH_W 426)
181 (UNSPEC_SHRA_R_QB 429)
184 (UNSPEC_SUBU_S_PH 432)
185 (UNSPEC_SUBUH_QB 433)
186 (UNSPEC_SUBUH_R_QB 434)
187 (UNSPEC_ADDQH_PH 435)
188 (UNSPEC_ADDQH_R_PH 436)
190 (UNSPEC_ADDQH_R_W 438)
191 (UNSPEC_SUBQH_PH 439)
192 (UNSPEC_SUBQH_R_PH 440)
194 (UNSPEC_SUBQH_R_W 442)
195 (UNSPEC_DPAX_W_PH 443)
196 (UNSPEC_DPSX_W_PH 444)
197 (UNSPEC_DPAQX_S_W_PH 445)
198 (UNSPEC_DPAQX_SA_W_PH 446)
199 (UNSPEC_DPSQX_S_W_PH 447)
200 (UNSPEC_DPSQX_SA_W_PH 448)
204 (include "predicates.md")
205 (include "constraints.md")
207 ;; ....................
211 ;; ....................
213 (define_attr "got" "unset,xgot_high,load"
214 (const_string "unset"))
216 ;; For jal instructions, this attribute is DIRECT when the target address
217 ;; is symbolic and INDIRECT when it is a register.
218 (define_attr "jal" "unset,direct,indirect"
219 (const_string "unset"))
221 ;; This attribute is YES if the instruction is a jal macro (not a
222 ;; real jal instruction).
224 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
225 ;; an instruction to restore $gp. Direct jals are also macros for
226 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
227 ;; the target address into a register.
228 (define_attr "jal_macro" "no,yes"
229 (cond [(eq_attr "jal" "direct")
230 (symbol_ref "TARGET_CALL_CLOBBERED_GP
231 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
232 (eq_attr "jal" "indirect")
233 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
234 (const_string "no")))
236 ;; Classification of each insn.
237 ;; branch conditional branch
238 ;; jump unconditional jump
239 ;; call unconditional call
240 ;; load load instruction(s)
241 ;; fpload floating point load
242 ;; fpidxload floating point indexed load
243 ;; store store instruction(s)
244 ;; fpstore floating point store
245 ;; fpidxstore floating point indexed store
246 ;; prefetch memory prefetch (register + offset)
247 ;; prefetchx memory indexed prefetch (register + register)
248 ;; condmove conditional moves
249 ;; mfc transfer from coprocessor
250 ;; mtc transfer to coprocessor
251 ;; mthilo transfer to hi/lo registers
252 ;; mfhilo transfer from hi/lo registers
253 ;; const load constant
254 ;; arith integer arithmetic and logical instructions
255 ;; shift integer shift instructions
256 ;; slt set less than instructions
257 ;; clz the clz and clo instructions
258 ;; trap trap if instructions
259 ;; imul integer multiply 2 operands
260 ;; imul3 integer multiply 3 operands
261 ;; imadd integer multiply-add
262 ;; idiv integer divide
263 ;; fmove floating point register move
264 ;; fadd floating point add/subtract
265 ;; fmul floating point multiply
266 ;; fmadd floating point multiply-add
267 ;; fdiv floating point divide
268 ;; frdiv floating point reciprocal divide
269 ;; frdiv1 floating point reciprocal divide step 1
270 ;; frdiv2 floating point reciprocal divide step 2
271 ;; fabs floating point absolute value
272 ;; fneg floating point negation
273 ;; fcmp floating point compare
274 ;; fcvt floating point convert
275 ;; fsqrt floating point square root
276 ;; frsqrt floating point reciprocal square root
277 ;; frsqrt1 floating point reciprocal square root step1
278 ;; frsqrt2 floating point reciprocal square root step2
279 ;; multi multiword sequence (or user asm statements)
282 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
283 (cond [(eq_attr "jal" "!unset") (const_string "call")
284 (eq_attr "got" "load") (const_string "load")]
285 (const_string "unknown")))
287 ;; Main data type used by the insn
288 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
289 (const_string "unknown"))
291 ;; Mode for conversion types (fcvt)
292 ;; I2S integer to float single (SI/DI to SF)
293 ;; I2D integer to float double (SI/DI to DF)
294 ;; S2I float to integer (SF to SI/DI)
295 ;; D2I float to integer (DF to SI/DI)
296 ;; D2S double to float single
297 ;; S2D float single to double
299 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
300 (const_string "unknown"))
302 ;; Is this an extended instruction in mips16 mode?
303 (define_attr "extended_mips16" "no,yes"
306 ;; Length of instruction in bytes.
307 (define_attr "length" ""
308 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
309 ;; If a branch is outside this range, we have a choice of two
310 ;; sequences. For PIC, an out-of-range branch like:
315 ;; becomes the equivalent of:
324 ;; where the load address can be up to three instructions long
327 ;; The non-PIC case is similar except that we use a direct
328 ;; jump instead of an la/jr pair. Since the target of this
329 ;; jump is an absolute 28-bit bit address (the other bits
330 ;; coming from the address of the delay slot) this form cannot
331 ;; cross a 256MB boundary. We could provide the option of
332 ;; using la/jr in this case too, but we do not do so at
335 ;; Note that this value does not account for the delay slot
336 ;; instruction, whose length is added separately. If the RTL
337 ;; pattern has no explicit delay slot, mips_adjust_insn_length
338 ;; will add the length of the implicit nop. The values for
339 ;; forward and backward branches will be different as well.
340 (eq_attr "type" "branch")
341 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
342 (le (minus (pc) (match_dup 1)) (const_int 131068)))
344 (ne (symbol_ref "flag_pic") (const_int 0))
348 (eq_attr "got" "load")
350 (eq_attr "got" "xgot_high")
353 (eq_attr "type" "const")
354 (symbol_ref "mips_const_insns (operands[1]) * 4")
355 (eq_attr "type" "load,fpload")
356 (symbol_ref "mips_fetch_insns (operands[1]) * 4")
357 (eq_attr "type" "store,fpstore")
358 (symbol_ref "mips_fetch_insns (operands[0]) * 4")
360 ;; In the worst case, a call macro will take 8 instructions:
362 ;; lui $25,%call_hi(FOO)
364 ;; lw $25,%call_lo(FOO)($25)
370 (eq_attr "jal_macro" "yes")
373 (and (eq_attr "extended_mips16" "yes")
374 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
377 ;; Various VR4120 errata require a nop to be inserted after a macc
378 ;; instruction. The assembler does this for us, so account for
379 ;; the worst-case length here.
380 (and (eq_attr "type" "imadd")
381 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
384 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
385 ;; the result of the second one is missed. The assembler should work
386 ;; around this by inserting a nop after the first dmult.
387 (and (eq_attr "type" "imul,imul3")
388 (and (eq_attr "mode" "DI")
389 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
392 (eq_attr "type" "idiv")
393 (symbol_ref "mips_idiv_insns () * 4")
396 ;; Attribute describing the processor. This attribute must match exactly
397 ;; with the processor_type enumeration in mips.h.
399 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf,24kx,74kc,74kf,74kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
400 (const (symbol_ref "mips_tune")))
402 ;; The type of hardware hazard associated with this instruction.
403 ;; DELAY means that the next instruction cannot read the result
404 ;; of this one. HILO means that the next two instructions cannot
405 ;; write to HI or LO.
406 (define_attr "hazard" "none,delay,hilo"
407 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
408 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
409 (const_string "delay")
411 (and (eq_attr "type" "mfc,mtc")
412 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
413 (const_string "delay")
415 (and (eq_attr "type" "fcmp")
416 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
417 (const_string "delay")
419 ;; The r4000 multiplication patterns include an mflo instruction.
420 (and (eq_attr "type" "imul")
421 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
422 (const_string "hilo")
424 (and (eq_attr "type" "mfhilo")
425 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
426 (const_string "hilo")]
427 (const_string "none")))
429 ;; Is it a single instruction?
430 (define_attr "single_insn" "no,yes"
431 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
433 ;; Can the instruction be put into a delay slot?
434 (define_attr "can_delay" "no,yes"
435 (if_then_else (and (eq_attr "type" "!branch,call,jump")
436 (and (eq_attr "hazard" "none")
437 (eq_attr "single_insn" "yes")))
439 (const_string "no")))
441 ;; Attribute defining whether or not we can use the branch-likely instructions
442 (define_attr "branch_likely" "no,yes"
444 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
446 (const_string "no"))))
448 ;; True if an instruction might assign to hi or lo when reloaded.
449 ;; This is used by the TUNE_MACC_CHAINS code.
450 (define_attr "may_clobber_hilo" "no,yes"
451 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
453 (const_string "no")))
455 ;; Describe a user's asm statement.
456 (define_asm_attributes
457 [(set_attr "type" "multi")
458 (set_attr "can_delay" "no")])
460 ;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
461 ;; from the same template.
462 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
464 ;; This mode macro allows :P to be used for patterns that operate on
465 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
466 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
468 ;; This mode macro allows :MOVECC to be used anywhere that a
469 ;; conditional-move-type condition is needed.
470 (define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
472 ;; This mode macro allows the QI and HI extension patterns to be defined from
473 ;; the same template.
474 (define_mode_macro SHORT [QI HI])
476 ;; This mode macro allows :ANYF to be used wherever a scalar or vector
477 ;; floating-point mode is allowed.
478 (define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
479 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
480 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
482 ;; Like ANYF, but only applies to scalar modes.
483 (define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
484 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
486 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
487 ;; 32-bit version and "dsubu" in the 64-bit version.
488 (define_mode_attr d [(SI "") (DI "d")])
490 ;; This attribute gives the length suffix for a sign- or zero-extension
492 (define_mode_attr size [(QI "b") (HI "h")])
494 ;; This attributes gives the mode mask of a SHORT.
495 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
497 ;; Mode attributes for GPR loads and stores.
498 (define_mode_attr load [(SI "lw") (DI "ld")])
499 (define_mode_attr store [(SI "sw") (DI "sd")])
501 ;; Similarly for MIPS IV indexed FPR loads and stores.
502 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
503 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
505 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
506 ;; are different. Some forms of unextended addiu have an 8-bit immediate
507 ;; field but the equivalent daddiu has only a 5-bit field.
508 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
510 ;; This attribute gives the best constraint to use for registers of
512 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
514 ;; This attribute gives the format suffix for floating-point operations.
515 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
517 ;; This attribute gives the upper-case mode name for one unit of a
518 ;; floating-point mode.
519 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
521 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
523 ;; In certain cases, div.s and div.ps may have a rounding error
524 ;; and/or wrong inexact flag.
526 ;; Therefore, we only allow div.s if not working around SB-1 rev2
527 ;; errata or if a slight loss of precision is OK.
528 (define_mode_attr divide_condition
529 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
530 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
532 ; This attribute gives the condition for which sqrt instructions exist.
533 (define_mode_attr sqrt_condition
534 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
536 ; This attribute gives the condition for which recip and rsqrt instructions
538 (define_mode_attr recip_condition
539 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
541 ;; This code macro allows all branch instructions to be generated from
542 ;; a single define_expand template.
543 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
544 eq ne gt ge lt le gtu geu ltu leu])
546 ;; This code macro allows signed and unsigned widening multiplications
547 ;; to use the same template.
548 (define_code_macro any_extend [sign_extend zero_extend])
550 ;; This code macro allows the three shift instructions to be generated
551 ;; from the same template.
552 (define_code_macro any_shift [ashift ashiftrt lshiftrt])
554 ;; This code macro allows all native floating-point comparisons to be
555 ;; generated from the same template.
556 (define_code_macro fcond [unordered uneq unlt unle eq lt le])
558 ;; This code macro is used for comparisons that can be implemented
559 ;; by swapping the operands.
560 (define_code_macro swapped_fcond [ge gt unge ungt])
562 ;; <u> expands to an empty string when doing a signed operation and
563 ;; "u" when doing an unsigned operation.
564 (define_code_attr u [(sign_extend "") (zero_extend "u")])
566 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
567 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
569 ;; <optab> expands to the name of the optab for a particular code.
570 (define_code_attr optab [(ashift "ashl")
574 ;; <insn> expands to the name of the insn that implements a particular code.
575 (define_code_attr insn [(ashift "sll")
579 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
580 (define_code_attr fcond [(unordered "un")
588 ;; Similar, but for swapped conditions.
589 (define_code_attr swapped_fcond [(ge "le")
594 ;; .........................
596 ;; Branch, call and jump delay slots
598 ;; .........................
600 (define_delay (and (eq_attr "type" "branch")
601 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
602 [(eq_attr "can_delay" "yes")
604 (and (eq_attr "branch_likely" "yes")
605 (eq_attr "can_delay" "yes"))])
607 (define_delay (eq_attr "type" "jump")
608 [(eq_attr "can_delay" "yes")
612 (define_delay (and (eq_attr "type" "call")
613 (eq_attr "jal_macro" "no"))
614 [(eq_attr "can_delay" "yes")
618 ;; Pipeline descriptions.
620 ;; generic.md provides a fallback for processors without a specific
621 ;; pipeline description. It is derived from the old define_function_unit
622 ;; version and uses the "alu" and "imuldiv" units declared below.
624 ;; Some of the processor-specific files are also derived from old
625 ;; define_function_unit descriptions and simply override the parts of
626 ;; generic.md that don't apply. The other processor-specific files
627 ;; are self-contained.
628 (define_automaton "alu,imuldiv")
630 (define_cpu_unit "alu" "alu")
631 (define_cpu_unit "imuldiv" "imuldiv")
651 (include "generic.md")
654 ;; ....................
658 ;; ....................
662 [(trap_if (const_int 1) (const_int 0))]
665 if (ISA_HAS_COND_TRAP)
667 else if (TARGET_MIPS16)
672 [(set_attr "type" "trap")])
674 (define_expand "conditional_trap"
675 [(trap_if (match_operator 0 "comparison_operator"
676 [(match_dup 2) (match_dup 3)])
677 (match_operand 1 "const_int_operand"))]
680 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
681 && operands[1] == const0_rtx)
683 mips_gen_conditional_trap (operands);
690 (define_insn "*conditional_trap<mode>"
691 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
692 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
693 (match_operand:GPR 2 "arith_operand" "dI")])
697 [(set_attr "type" "trap")])
700 ;; ....................
704 ;; ....................
707 (define_insn "add<mode>3"
708 [(set (match_operand:ANYF 0 "register_operand" "=f")
709 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
710 (match_operand:ANYF 2 "register_operand" "f")))]
712 "add.<fmt>\t%0,%1,%2"
713 [(set_attr "type" "fadd")
714 (set_attr "mode" "<UNITMODE>")])
716 (define_expand "add<mode>3"
717 [(set (match_operand:GPR 0 "register_operand")
718 (plus:GPR (match_operand:GPR 1 "register_operand")
719 (match_operand:GPR 2 "arith_operand")))]
722 (define_insn "*add<mode>3"
723 [(set (match_operand:GPR 0 "register_operand" "=d,d")
724 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
725 (match_operand:GPR 2 "arith_operand" "d,Q")))]
730 [(set_attr "type" "arith")
731 (set_attr "mode" "<MODE>")])
733 ;; We need to recognize MIPS16 stack pointer additions explicitly, since
734 ;; we don't have a constraint for $sp. These insns will be generated by
735 ;; the save_restore_insns functions.
737 (define_insn "*add<mode>3_sp1"
739 (plus:GPR (reg:GPR 29)
740 (match_operand:GPR 0 "const_arith_operand" "")))]
743 [(set_attr "type" "arith")
744 (set_attr "mode" "<MODE>")
745 (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8")
749 (define_insn "*add<mode>3_sp2"
750 [(set (match_operand:GPR 0 "register_operand" "=d")
751 (plus:GPR (reg:GPR 29)
752 (match_operand:GPR 1 "const_arith_operand" "")))]
755 [(set_attr "type" "arith")
756 (set_attr "mode" "<MODE>")
757 (set (attr "length") (if_then_else (match_operand 1 "m16_uimm<si8_di5>_4")
761 (define_insn "*add<mode>3_mips16"
762 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
763 (plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d")
764 (match_operand:GPR 2 "arith_operand" "Q,O,d")))]
770 [(set_attr "type" "arith")
771 (set_attr "mode" "<MODE>")
772 (set_attr_alternative "length"
773 [(if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
776 (if_then_else (match_operand 2 "m16_simm4_1")
782 ;; On the mips16, we can sometimes split an add of a constant which is
783 ;; a 4 byte instruction into two adds which are both 2 byte
784 ;; instructions. There are two cases: one where we are adding a
785 ;; constant plus a register to another register, and one where we are
786 ;; simply adding a constant to a register.
789 [(set (match_operand:SI 0 "register_operand")
790 (plus:SI (match_dup 0)
791 (match_operand:SI 1 "const_int_operand")))]
792 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
793 && REG_P (operands[0])
794 && M16_REG_P (REGNO (operands[0]))
795 && GET_CODE (operands[1]) == CONST_INT
796 && ((INTVAL (operands[1]) > 0x7f
797 && INTVAL (operands[1]) <= 0x7f + 0x7f)
798 || (INTVAL (operands[1]) < - 0x80
799 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
800 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
801 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
803 HOST_WIDE_INT val = INTVAL (operands[1]);
807 operands[1] = GEN_INT (0x7f);
808 operands[2] = GEN_INT (val - 0x7f);
812 operands[1] = GEN_INT (- 0x80);
813 operands[2] = GEN_INT (val + 0x80);
818 [(set (match_operand:SI 0 "register_operand")
819 (plus:SI (match_operand:SI 1 "register_operand")
820 (match_operand:SI 2 "const_int_operand")))]
821 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
822 && REG_P (operands[0])
823 && M16_REG_P (REGNO (operands[0]))
824 && REG_P (operands[1])
825 && M16_REG_P (REGNO (operands[1]))
826 && REGNO (operands[0]) != REGNO (operands[1])
827 && GET_CODE (operands[2]) == CONST_INT
828 && ((INTVAL (operands[2]) > 0x7
829 && INTVAL (operands[2]) <= 0x7 + 0x7f)
830 || (INTVAL (operands[2]) < - 0x8
831 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
832 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
833 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
835 HOST_WIDE_INT val = INTVAL (operands[2]);
839 operands[2] = GEN_INT (0x7);
840 operands[3] = GEN_INT (val - 0x7);
844 operands[2] = GEN_INT (- 0x8);
845 operands[3] = GEN_INT (val + 0x8);
850 [(set (match_operand:DI 0 "register_operand")
851 (plus:DI (match_dup 0)
852 (match_operand:DI 1 "const_int_operand")))]
853 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
854 && REG_P (operands[0])
855 && M16_REG_P (REGNO (operands[0]))
856 && GET_CODE (operands[1]) == CONST_INT
857 && ((INTVAL (operands[1]) > 0xf
858 && INTVAL (operands[1]) <= 0xf + 0xf)
859 || (INTVAL (operands[1]) < - 0x10
860 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
861 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
862 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
864 HOST_WIDE_INT val = INTVAL (operands[1]);
868 operands[1] = GEN_INT (0xf);
869 operands[2] = GEN_INT (val - 0xf);
873 operands[1] = GEN_INT (- 0x10);
874 operands[2] = GEN_INT (val + 0x10);
879 [(set (match_operand:DI 0 "register_operand")
880 (plus:DI (match_operand:DI 1 "register_operand")
881 (match_operand:DI 2 "const_int_operand")))]
882 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
883 && REG_P (operands[0])
884 && M16_REG_P (REGNO (operands[0]))
885 && REG_P (operands[1])
886 && M16_REG_P (REGNO (operands[1]))
887 && REGNO (operands[0]) != REGNO (operands[1])
888 && GET_CODE (operands[2]) == CONST_INT
889 && ((INTVAL (operands[2]) > 0x7
890 && INTVAL (operands[2]) <= 0x7 + 0xf)
891 || (INTVAL (operands[2]) < - 0x8
892 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
893 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
894 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
896 HOST_WIDE_INT val = INTVAL (operands[2]);
900 operands[2] = GEN_INT (0x7);
901 operands[3] = GEN_INT (val - 0x7);
905 operands[2] = GEN_INT (- 0x8);
906 operands[3] = GEN_INT (val + 0x8);
910 (define_insn "*addsi3_extended"
911 [(set (match_operand:DI 0 "register_operand" "=d,d")
913 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
914 (match_operand:SI 2 "arith_operand" "d,Q"))))]
915 "TARGET_64BIT && !TARGET_MIPS16"
919 [(set_attr "type" "arith")
920 (set_attr "mode" "SI")])
922 ;; Split this insn so that the addiu splitters can have a crack at it.
923 ;; Use a conservative length estimate until the split.
924 (define_insn_and_split "*addsi3_extended_mips16"
925 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
927 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
928 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
929 "TARGET_64BIT && TARGET_MIPS16"
931 "&& reload_completed"
932 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
933 { operands[3] = gen_lowpart (SImode, operands[0]); }
934 [(set_attr "type" "arith")
935 (set_attr "mode" "SI")
936 (set_attr "extended_mips16" "yes")])
939 ;; ....................
943 ;; ....................
946 (define_insn "sub<mode>3"
947 [(set (match_operand:ANYF 0 "register_operand" "=f")
948 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
949 (match_operand:ANYF 2 "register_operand" "f")))]
951 "sub.<fmt>\t%0,%1,%2"
952 [(set_attr "type" "fadd")
953 (set_attr "mode" "<UNITMODE>")])
955 (define_insn "sub<mode>3"
956 [(set (match_operand:GPR 0 "register_operand" "=d")
957 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
958 (match_operand:GPR 2 "register_operand" "d")))]
961 [(set_attr "type" "arith")
962 (set_attr "mode" "<MODE>")])
964 (define_insn "*subsi3_extended"
965 [(set (match_operand:DI 0 "register_operand" "=d")
967 (minus:SI (match_operand:SI 1 "register_operand" "d")
968 (match_operand:SI 2 "register_operand" "d"))))]
971 [(set_attr "type" "arith")
972 (set_attr "mode" "DI")])
975 ;; ....................
979 ;; ....................
982 (define_expand "mul<mode>3"
983 [(set (match_operand:SCALARF 0 "register_operand")
984 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
985 (match_operand:SCALARF 2 "register_operand")))]
989 (define_insn "*mul<mode>3"
990 [(set (match_operand:SCALARF 0 "register_operand" "=f")
991 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
992 (match_operand:SCALARF 2 "register_operand" "f")))]
993 "!TARGET_4300_MUL_FIX"
994 "mul.<fmt>\t%0,%1,%2"
995 [(set_attr "type" "fmul")
996 (set_attr "mode" "<MODE>")])
998 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
999 ;; operands may corrupt immediately following multiplies. This is a
1000 ;; simple fix to insert NOPs.
1002 (define_insn "*mul<mode>3_r4300"
1003 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1004 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1005 (match_operand:SCALARF 2 "register_operand" "f")))]
1006 "TARGET_4300_MUL_FIX"
1007 "mul.<fmt>\t%0,%1,%2\;nop"
1008 [(set_attr "type" "fmul")
1009 (set_attr "mode" "<MODE>")
1010 (set_attr "length" "8")])
1012 (define_insn "mulv2sf3"
1013 [(set (match_operand:V2SF 0 "register_operand" "=f")
1014 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1015 (match_operand:V2SF 2 "register_operand" "f")))]
1016 "TARGET_PAIRED_SINGLE_FLOAT"
1018 [(set_attr "type" "fmul")
1019 (set_attr "mode" "SF")])
1021 ;; The original R4000 has a cpu bug. If a double-word or a variable
1022 ;; shift executes while an integer multiplication is in progress, the
1023 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1024 ;; with the mult on the R4000.
1026 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1027 ;; (also valid for MIPS R4000MC processors):
1029 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1030 ;; this errata description.
1031 ;; The following code sequence causes the R4000 to incorrectly
1032 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1033 ;; instruction. If the dsra32 instruction is executed during an
1034 ;; integer multiply, the dsra32 will only shift by the amount in
1035 ;; specified in the instruction rather than the amount plus 32
1037 ;; instruction 1: mult rs,rt integer multiply
1038 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1039 ;; right arithmetic + 32
1040 ;; Workaround: A dsra32 instruction placed after an integer
1041 ;; multiply should not be one of the 11 instructions after the
1042 ;; multiply instruction."
1046 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1047 ;; the following description.
1048 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1049 ;; 64-bit versions) may produce incorrect results under the
1050 ;; following conditions:
1051 ;; 1) An integer multiply is currently executing
1052 ;; 2) These types of shift instructions are executed immediately
1053 ;; following an integer divide instruction.
1055 ;; 1) Make sure no integer multiply is running wihen these
1056 ;; instruction are executed. If this cannot be predicted at
1057 ;; compile time, then insert a "mfhi" to R0 instruction
1058 ;; immediately after the integer multiply instruction. This
1059 ;; will cause the integer multiply to complete before the shift
1061 ;; 2) Separate integer divide and these two classes of shift
1062 ;; instructions by another instruction or a noop."
1064 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1067 (define_expand "mulsi3"
1068 [(set (match_operand:SI 0 "register_operand")
1069 (mult:SI (match_operand:SI 1 "register_operand")
1070 (match_operand:SI 2 "register_operand")))]
1074 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1075 else if (TARGET_FIX_R4000)
1076 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1078 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1082 (define_expand "muldi3"
1083 [(set (match_operand:DI 0 "register_operand")
1084 (mult:DI (match_operand:DI 1 "register_operand")
1085 (match_operand:DI 2 "register_operand")))]
1088 if (TARGET_FIX_R4000)
1089 emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
1091 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1095 (define_insn "mulsi3_mult3"
1096 [(set (match_operand:SI 0 "register_operand" "=d,l")
1097 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1098 (match_operand:SI 2 "register_operand" "d,d")))
1099 (clobber (match_scratch:SI 3 "=h,h"))
1100 (clobber (match_scratch:SI 4 "=l,X"))]
1103 if (which_alternative == 1)
1104 return "mult\t%1,%2";
1105 if (TARGET_MIPS3900)
1106 return "mult\t%0,%1,%2";
1107 return "mul\t%0,%1,%2";
1109 [(set_attr "type" "imul3,imul")
1110 (set_attr "mode" "SI")])
1112 ;; If a register gets allocated to LO, and we spill to memory, the reload
1113 ;; will include a move from LO to a GPR. Merge it into the multiplication
1114 ;; if it can set the GPR directly.
1117 ;; Operand 1: GPR (1st multiplication operand)
1118 ;; Operand 2: GPR (2nd multiplication operand)
1120 ;; Operand 4: GPR (destination)
1123 [(set (match_operand:SI 0 "register_operand")
1124 (mult:SI (match_operand:SI 1 "register_operand")
1125 (match_operand:SI 2 "register_operand")))
1126 (clobber (match_operand:SI 3 "register_operand"))
1127 (clobber (scratch:SI))])
1128 (set (match_operand:SI 4 "register_operand")
1129 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1130 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1133 (mult:SI (match_dup 1)
1135 (clobber (match_dup 3))
1136 (clobber (match_dup 0))])])
1138 (define_insn "mul<mode>3_internal"
1139 [(set (match_operand:GPR 0 "register_operand" "=l")
1140 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1141 (match_operand:GPR 2 "register_operand" "d")))
1142 (clobber (match_scratch:GPR 3 "=h"))]
1145 [(set_attr "type" "imul")
1146 (set_attr "mode" "<MODE>")])
1148 (define_insn "mul<mode>3_r4000"
1149 [(set (match_operand:GPR 0 "register_operand" "=d")
1150 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1151 (match_operand:GPR 2 "register_operand" "d")))
1152 (clobber (match_scratch:GPR 3 "=h"))
1153 (clobber (match_scratch:GPR 4 "=l"))]
1155 "<d>mult\t%1,%2\;mflo\t%0"
1156 [(set_attr "type" "imul")
1157 (set_attr "mode" "<MODE>")
1158 (set_attr "length" "8")])
1160 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1161 ;; of "mult; mflo". They have the same latency, but the first form gives
1162 ;; us an extra cycle to compute the operands.
1165 ;; Operand 1: GPR (1st multiplication operand)
1166 ;; Operand 2: GPR (2nd multiplication operand)
1168 ;; Operand 4: GPR (destination)
1171 [(set (match_operand:SI 0 "register_operand")
1172 (mult:SI (match_operand:SI 1 "register_operand")
1173 (match_operand:SI 2 "register_operand")))
1174 (clobber (match_operand:SI 3 "register_operand"))])
1175 (set (match_operand:SI 4 "register_operand")
1176 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1177 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1182 (plus:SI (mult:SI (match_dup 1)
1186 (plus:SI (mult:SI (match_dup 1)
1189 (clobber (match_dup 3))])])
1191 ;; Multiply-accumulate patterns
1193 ;; For processors that can copy the output to a general register:
1195 ;; The all-d alternative is needed because the combiner will find this
1196 ;; pattern and then register alloc/reload will move registers around to
1197 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1199 ;; The last alternative should be made slightly less desirable, but adding
1200 ;; "?" to the constraint is too strong, and causes values to be loaded into
1201 ;; LO even when that's more costly. For now, using "*d" mostly does the
1203 (define_insn "*mul_acc_si"
1204 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1205 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1206 (match_operand:SI 2 "register_operand" "d,d,d"))
1207 (match_operand:SI 3 "register_operand" "0,l,*d")))
1208 (clobber (match_scratch:SI 4 "=h,h,h"))
1209 (clobber (match_scratch:SI 5 "=X,3,l"))
1210 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1212 || GENERATE_MADD_MSUB)
1215 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1216 if (which_alternative == 2)
1218 if (GENERATE_MADD_MSUB && which_alternative != 0)
1220 return madd[which_alternative];
1222 [(set_attr "type" "imadd,imadd,multi")
1223 (set_attr "mode" "SI")
1224 (set_attr "length" "4,4,8")])
1226 ;; Split the above insn if we failed to get LO allocated.
1228 [(set (match_operand:SI 0 "register_operand")
1229 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1230 (match_operand:SI 2 "register_operand"))
1231 (match_operand:SI 3 "register_operand")))
1232 (clobber (match_scratch:SI 4))
1233 (clobber (match_scratch:SI 5))
1234 (clobber (match_scratch:SI 6))]
1235 "reload_completed && !TARGET_DEBUG_D_MODE
1236 && GP_REG_P (true_regnum (operands[0]))
1237 && GP_REG_P (true_regnum (operands[3]))"
1238 [(parallel [(set (match_dup 6)
1239 (mult:SI (match_dup 1) (match_dup 2)))
1240 (clobber (match_dup 4))
1241 (clobber (match_dup 5))])
1242 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1245 ;; Splitter to copy result of MADD to a general register
1247 [(set (match_operand:SI 0 "register_operand")
1248 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1249 (match_operand:SI 2 "register_operand"))
1250 (match_operand:SI 3 "register_operand")))
1251 (clobber (match_scratch:SI 4))
1252 (clobber (match_scratch:SI 5))
1253 (clobber (match_scratch:SI 6))]
1254 "reload_completed && !TARGET_DEBUG_D_MODE
1255 && GP_REG_P (true_regnum (operands[0]))
1256 && true_regnum (operands[3]) == LO_REGNUM"
1257 [(parallel [(set (match_dup 3)
1258 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1260 (clobber (match_dup 4))
1261 (clobber (match_dup 5))
1262 (clobber (match_dup 6))])
1263 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1266 (define_insn "*macc"
1267 [(set (match_operand:SI 0 "register_operand" "=l,d")
1268 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1269 (match_operand:SI 2 "register_operand" "d,d"))
1270 (match_operand:SI 3 "register_operand" "0,l")))
1271 (clobber (match_scratch:SI 4 "=h,h"))
1272 (clobber (match_scratch:SI 5 "=X,3"))]
1275 if (which_alternative == 1)
1276 return "macc\t%0,%1,%2";
1277 else if (TARGET_MIPS5500)
1278 return "madd\t%1,%2";
1280 /* The VR4130 assumes that there is a two-cycle latency between a macc
1281 that "writes" to $0 and an instruction that reads from it. We avoid
1282 this by assigning to $1 instead. */
1283 return "%[macc\t%@,%1,%2%]";
1285 [(set_attr "type" "imadd")
1286 (set_attr "mode" "SI")])
1288 (define_insn "*msac"
1289 [(set (match_operand:SI 0 "register_operand" "=l,d")
1290 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1291 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1292 (match_operand:SI 3 "register_operand" "d,d"))))
1293 (clobber (match_scratch:SI 4 "=h,h"))
1294 (clobber (match_scratch:SI 5 "=X,1"))]
1297 if (which_alternative == 1)
1298 return "msac\t%0,%2,%3";
1299 else if (TARGET_MIPS5500)
1300 return "msub\t%2,%3";
1302 return "msac\t$0,%2,%3";
1304 [(set_attr "type" "imadd")
1305 (set_attr "mode" "SI")])
1307 ;; An msac-like instruction implemented using negation and a macc.
1308 (define_insn_and_split "*msac_using_macc"
1309 [(set (match_operand:SI 0 "register_operand" "=l,d")
1310 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1311 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1312 (match_operand:SI 3 "register_operand" "d,d"))))
1313 (clobber (match_scratch:SI 4 "=h,h"))
1314 (clobber (match_scratch:SI 5 "=X,1"))
1315 (clobber (match_scratch:SI 6 "=d,d"))]
1316 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1318 "&& reload_completed"
1320 (neg:SI (match_dup 3)))
1323 (plus:SI (mult:SI (match_dup 2)
1326 (clobber (match_dup 4))
1327 (clobber (match_dup 5))])]
1329 [(set_attr "type" "imadd")
1330 (set_attr "length" "8")])
1332 ;; Patterns generated by the define_peephole2 below.
1334 (define_insn "*macc2"
1335 [(set (match_operand:SI 0 "register_operand" "=l")
1336 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1337 (match_operand:SI 2 "register_operand" "d"))
1339 (set (match_operand:SI 3 "register_operand" "=d")
1340 (plus:SI (mult:SI (match_dup 1)
1343 (clobber (match_scratch:SI 4 "=h"))]
1344 "ISA_HAS_MACC && reload_completed"
1346 [(set_attr "type" "imadd")
1347 (set_attr "mode" "SI")])
1349 (define_insn "*msac2"
1350 [(set (match_operand:SI 0 "register_operand" "=l")
1351 (minus:SI (match_dup 0)
1352 (mult:SI (match_operand:SI 1 "register_operand" "d")
1353 (match_operand:SI 2 "register_operand" "d"))))
1354 (set (match_operand:SI 3 "register_operand" "=d")
1355 (minus:SI (match_dup 0)
1356 (mult:SI (match_dup 1)
1358 (clobber (match_scratch:SI 4 "=h"))]
1359 "ISA_HAS_MSAC && reload_completed"
1361 [(set_attr "type" "imadd")
1362 (set_attr "mode" "SI")])
1364 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1368 ;; Operand 1: macc/msac
1370 ;; Operand 3: GPR (destination)
1373 [(set (match_operand:SI 0 "register_operand")
1374 (match_operand:SI 1 "macc_msac_operand"))
1375 (clobber (match_operand:SI 2 "register_operand"))
1376 (clobber (scratch:SI))])
1377 (set (match_operand:SI 3 "register_operand")
1378 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1380 [(parallel [(set (match_dup 0)
1384 (clobber (match_dup 2))])]
1387 ;; When we have a three-address multiplication instruction, it should
1388 ;; be faster to do a separate multiply and add, rather than moving
1389 ;; something into LO in order to use a macc instruction.
1391 ;; This peephole needs a scratch register to cater for the case when one
1392 ;; of the multiplication operands is the same as the destination.
1394 ;; Operand 0: GPR (scratch)
1396 ;; Operand 2: GPR (addend)
1397 ;; Operand 3: GPR (destination)
1398 ;; Operand 4: macc/msac
1400 ;; Operand 6: new multiplication
1401 ;; Operand 7: new addition/subtraction
1403 [(match_scratch:SI 0 "d")
1404 (set (match_operand:SI 1 "register_operand")
1405 (match_operand:SI 2 "register_operand"))
1408 [(set (match_operand:SI 3 "register_operand")
1409 (match_operand:SI 4 "macc_msac_operand"))
1410 (clobber (match_operand:SI 5 "register_operand"))
1411 (clobber (match_dup 1))])]
1413 && true_regnum (operands[1]) == LO_REGNUM
1414 && peep2_reg_dead_p (2, operands[1])
1415 && GP_REG_P (true_regnum (operands[3]))"
1416 [(parallel [(set (match_dup 0)
1418 (clobber (match_dup 5))
1419 (clobber (match_dup 1))])
1423 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1424 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1425 operands[2], operands[0]);
1428 ;; Same as above, except LO is the initial target of the macc.
1430 ;; Operand 0: GPR (scratch)
1432 ;; Operand 2: GPR (addend)
1433 ;; Operand 3: macc/msac
1435 ;; Operand 5: GPR (destination)
1436 ;; Operand 6: new multiplication
1437 ;; Operand 7: new addition/subtraction
1439 [(match_scratch:SI 0 "d")
1440 (set (match_operand:SI 1 "register_operand")
1441 (match_operand:SI 2 "register_operand"))
1445 (match_operand:SI 3 "macc_msac_operand"))
1446 (clobber (match_operand:SI 4 "register_operand"))
1447 (clobber (scratch:SI))])
1449 (set (match_operand:SI 5 "register_operand")
1450 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1451 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1452 [(parallel [(set (match_dup 0)
1454 (clobber (match_dup 4))
1455 (clobber (match_dup 1))])
1459 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1460 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1461 operands[2], operands[0]);
1464 (define_insn "*mul_sub_si"
1465 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1466 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1467 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1468 (match_operand:SI 3 "register_operand" "d,d,d"))))
1469 (clobber (match_scratch:SI 4 "=h,h,h"))
1470 (clobber (match_scratch:SI 5 "=X,1,l"))
1471 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1472 "GENERATE_MADD_MSUB"
1477 [(set_attr "type" "imadd,multi,multi")
1478 (set_attr "mode" "SI")
1479 (set_attr "length" "4,8,8")])
1481 ;; Split the above insn if we failed to get LO allocated.
1483 [(set (match_operand:SI 0 "register_operand")
1484 (minus:SI (match_operand:SI 1 "register_operand")
1485 (mult:SI (match_operand:SI 2 "register_operand")
1486 (match_operand:SI 3 "register_operand"))))
1487 (clobber (match_scratch:SI 4))
1488 (clobber (match_scratch:SI 5))
1489 (clobber (match_scratch:SI 6))]
1490 "reload_completed && !TARGET_DEBUG_D_MODE
1491 && GP_REG_P (true_regnum (operands[0]))
1492 && GP_REG_P (true_regnum (operands[1]))"
1493 [(parallel [(set (match_dup 6)
1494 (mult:SI (match_dup 2) (match_dup 3)))
1495 (clobber (match_dup 4))
1496 (clobber (match_dup 5))])
1497 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1500 ;; Splitter to copy result of MSUB to a general register
1502 [(set (match_operand:SI 0 "register_operand")
1503 (minus:SI (match_operand:SI 1 "register_operand")
1504 (mult:SI (match_operand:SI 2 "register_operand")
1505 (match_operand:SI 3 "register_operand"))))
1506 (clobber (match_scratch:SI 4))
1507 (clobber (match_scratch:SI 5))
1508 (clobber (match_scratch:SI 6))]
1509 "reload_completed && !TARGET_DEBUG_D_MODE
1510 && GP_REG_P (true_regnum (operands[0]))
1511 && true_regnum (operands[1]) == LO_REGNUM"
1512 [(parallel [(set (match_dup 1)
1513 (minus:SI (match_dup 1)
1514 (mult:SI (match_dup 2) (match_dup 3))))
1515 (clobber (match_dup 4))
1516 (clobber (match_dup 5))
1517 (clobber (match_dup 6))])
1518 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1521 (define_insn "*muls"
1522 [(set (match_operand:SI 0 "register_operand" "=l,d")
1523 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1524 (match_operand:SI 2 "register_operand" "d,d"))))
1525 (clobber (match_scratch:SI 3 "=h,h"))
1526 (clobber (match_scratch:SI 4 "=X,l"))]
1531 [(set_attr "type" "imul,imul3")
1532 (set_attr "mode" "SI")])
1534 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1536 (define_expand "<u>mulsidi3"
1538 [(set (match_operand:DI 0 "register_operand")
1539 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1540 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1541 (clobber (scratch:DI))
1542 (clobber (scratch:DI))
1543 (clobber (scratch:DI))])]
1544 "!TARGET_64BIT || !TARGET_FIX_R4000"
1548 if (!TARGET_FIX_R4000)
1549 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1552 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1558 (define_insn "<u>mulsidi3_32bit_internal"
1559 [(set (match_operand:DI 0 "register_operand" "=x")
1560 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1561 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1562 "!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
1564 [(set_attr "type" "imul")
1565 (set_attr "mode" "SI")])
1567 (define_insn "<u>mulsidi3_32bit_r4000"
1568 [(set (match_operand:DI 0 "register_operand" "=d")
1569 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1570 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1571 (clobber (match_scratch:DI 3 "=x"))]
1572 "!TARGET_64BIT && TARGET_FIX_R4000"
1573 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1574 [(set_attr "type" "imul")
1575 (set_attr "mode" "SI")
1576 (set_attr "length" "12")])
1578 (define_insn_and_split "*<u>mulsidi3_64bit"
1579 [(set (match_operand:DI 0 "register_operand" "=d")
1580 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1581 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1582 (clobber (match_scratch:DI 3 "=l"))
1583 (clobber (match_scratch:DI 4 "=h"))
1584 (clobber (match_scratch:DI 5 "=d"))]
1585 "TARGET_64BIT && !TARGET_FIX_R4000"
1587 "&& reload_completed"
1591 (mult:SI (match_dup 1)
1595 (mult:DI (any_extend:DI (match_dup 1))
1596 (any_extend:DI (match_dup 2)))
1599 ;; OP5 <- LO, OP0 <- HI
1600 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1601 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1605 (ashift:DI (match_dup 5)
1608 (lshiftrt:DI (match_dup 5)
1611 ;; Shift OP0 into place.
1613 (ashift:DI (match_dup 0)
1616 ;; OR the two halves together
1618 (ior:DI (match_dup 0)
1621 [(set_attr "type" "imul")
1622 (set_attr "mode" "SI")
1623 (set_attr "length" "24")])
1625 (define_insn "*<u>mulsidi3_64bit_parts"
1626 [(set (match_operand:DI 0 "register_operand" "=l")
1628 (mult:SI (match_operand:SI 2 "register_operand" "d")
1629 (match_operand:SI 3 "register_operand" "d"))))
1630 (set (match_operand:DI 1 "register_operand" "=h")
1632 (mult:DI (any_extend:DI (match_dup 2))
1633 (any_extend:DI (match_dup 3)))
1635 "TARGET_64BIT && !TARGET_FIX_R4000"
1637 [(set_attr "type" "imul")
1638 (set_attr "mode" "SI")])
1640 ;; Widening multiply with negation.
1641 (define_insn "*muls<u>_di"
1642 [(set (match_operand:DI 0 "register_operand" "=x")
1645 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1646 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1647 "!TARGET_64BIT && ISA_HAS_MULS"
1649 [(set_attr "type" "imul")
1650 (set_attr "mode" "SI")])
1652 (define_insn "<u>msubsidi4"
1653 [(set (match_operand:DI 0 "register_operand" "=ka")
1655 (match_operand:DI 3 "register_operand" "0")
1657 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1658 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1659 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || TARGET_DSPR2)"
1662 return "msub<u>\t%q0,%1,%2";
1663 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1664 return "msub<u>\t%1,%2";
1666 return "msac<u>\t$0,%1,%2";
1668 [(set_attr "type" "imadd")
1669 (set_attr "mode" "SI")])
1671 ;; _highpart patterns
1673 (define_expand "<su>mulsi3_highpart"
1674 [(set (match_operand:SI 0 "register_operand")
1677 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1678 (any_extend:DI (match_operand:SI 2 "register_operand")))
1680 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1683 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1687 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1692 (define_insn "<su>mulsi3_highpart_internal"
1693 [(set (match_operand:SI 0 "register_operand" "=h")
1696 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1697 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1699 (clobber (match_scratch:SI 3 "=l"))]
1700 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1702 [(set_attr "type" "imul")
1703 (set_attr "mode" "SI")])
1705 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1706 [(set (match_operand:SI 0 "register_operand" "=h,d")
1710 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1711 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1713 (clobber (match_scratch:SI 3 "=l,l"))
1714 (clobber (match_scratch:SI 4 "=X,h"))]
1719 [(set_attr "type" "imul,imul3")
1720 (set_attr "mode" "SI")])
1722 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1723 [(set (match_operand:SI 0 "register_operand" "=h,d")
1728 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1729 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1731 (clobber (match_scratch:SI 3 "=l,l"))
1732 (clobber (match_scratch:SI 4 "=X,h"))]
1736 mulshi<u>\t%0,%1,%2"
1737 [(set_attr "type" "imul,imul3")
1738 (set_attr "mode" "SI")])
1740 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1741 ;; errata MD(0), which says that dmultu does not always produce the
1743 (define_insn "<su>muldi3_highpart"
1744 [(set (match_operand:DI 0 "register_operand" "=h")
1748 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1749 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1751 (clobber (match_scratch:DI 3 "=l"))]
1752 "TARGET_64BIT && !TARGET_FIX_R4000
1753 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1755 [(set_attr "type" "imul")
1756 (set_attr "mode" "DI")])
1758 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
1759 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
1761 (define_insn "madsi"
1762 [(set (match_operand:SI 0 "register_operand" "+l")
1763 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1764 (match_operand:SI 2 "register_operand" "d"))
1766 (clobber (match_scratch:SI 3 "=h"))]
1769 [(set_attr "type" "imadd")
1770 (set_attr "mode" "SI")])
1772 (define_insn "<u>maddsidi4"
1773 [(set (match_operand:DI 0 "register_operand" "=ka")
1775 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1776 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1777 (match_operand:DI 3 "register_operand" "0")))]
1778 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || TARGET_DSPR2)
1782 return "mad<u>\t%1,%2";
1783 else if (TARGET_DSPR2)
1784 return "madd<u>\t%q0,%1,%2";
1785 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
1786 return "madd<u>\t%1,%2";
1788 /* See comment in *macc. */
1789 return "%[macc<u>\t%@,%1,%2%]";
1791 [(set_attr "type" "imadd")
1792 (set_attr "mode" "SI")])
1794 ;; Floating point multiply accumulate instructions.
1796 (define_insn "*madd<mode>"
1797 [(set (match_operand:ANYF 0 "register_operand" "=f")
1798 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1799 (match_operand:ANYF 2 "register_operand" "f"))
1800 (match_operand:ANYF 3 "register_operand" "f")))]
1801 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1802 "madd.<fmt>\t%0,%3,%1,%2"
1803 [(set_attr "type" "fmadd")
1804 (set_attr "mode" "<UNITMODE>")])
1806 (define_insn "*msub<mode>"
1807 [(set (match_operand:ANYF 0 "register_operand" "=f")
1808 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1809 (match_operand:ANYF 2 "register_operand" "f"))
1810 (match_operand:ANYF 3 "register_operand" "f")))]
1811 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1812 "msub.<fmt>\t%0,%3,%1,%2"
1813 [(set_attr "type" "fmadd")
1814 (set_attr "mode" "<UNITMODE>")])
1816 (define_insn "*nmadd<mode>"
1817 [(set (match_operand:ANYF 0 "register_operand" "=f")
1818 (neg:ANYF (plus:ANYF
1819 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1820 (match_operand:ANYF 2 "register_operand" "f"))
1821 (match_operand:ANYF 3 "register_operand" "f"))))]
1822 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1823 && HONOR_SIGNED_ZEROS (<MODE>mode)
1824 && !HONOR_NANS (<MODE>mode)"
1825 "nmadd.<fmt>\t%0,%3,%1,%2"
1826 [(set_attr "type" "fmadd")
1827 (set_attr "mode" "<UNITMODE>")])
1829 (define_insn "*nmadd<mode>_fastmath"
1830 [(set (match_operand:ANYF 0 "register_operand" "=f")
1832 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1833 (match_operand:ANYF 2 "register_operand" "f"))
1834 (match_operand:ANYF 3 "register_operand" "f")))]
1835 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1836 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1837 && !HONOR_NANS (<MODE>mode)"
1838 "nmadd.<fmt>\t%0,%3,%1,%2"
1839 [(set_attr "type" "fmadd")
1840 (set_attr "mode" "<UNITMODE>")])
1842 (define_insn "*nmsub<mode>"
1843 [(set (match_operand:ANYF 0 "register_operand" "=f")
1844 (neg:ANYF (minus:ANYF
1845 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1846 (match_operand:ANYF 3 "register_operand" "f"))
1847 (match_operand:ANYF 1 "register_operand" "f"))))]
1848 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1849 && HONOR_SIGNED_ZEROS (<MODE>mode)
1850 && !HONOR_NANS (<MODE>mode)"
1851 "nmsub.<fmt>\t%0,%1,%2,%3"
1852 [(set_attr "type" "fmadd")
1853 (set_attr "mode" "<UNITMODE>")])
1855 (define_insn "*nmsub<mode>_fastmath"
1856 [(set (match_operand:ANYF 0 "register_operand" "=f")
1858 (match_operand:ANYF 1 "register_operand" "f")
1859 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1860 (match_operand:ANYF 3 "register_operand" "f"))))]
1861 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1862 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1863 && !HONOR_NANS (<MODE>mode)"
1864 "nmsub.<fmt>\t%0,%1,%2,%3"
1865 [(set_attr "type" "fmadd")
1866 (set_attr "mode" "<UNITMODE>")])
1869 ;; ....................
1871 ;; DIVISION and REMAINDER
1873 ;; ....................
1876 (define_expand "div<mode>3"
1877 [(set (match_operand:ANYF 0 "register_operand")
1878 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1879 (match_operand:ANYF 2 "register_operand")))]
1880 "<divide_condition>"
1882 if (const_1_operand (operands[1], <MODE>mode))
1883 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1884 operands[1] = force_reg (<MODE>mode, operands[1]);
1887 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1889 ;; If an mfc1 or dmfc1 happens to access the floating point register
1890 ;; file at the same time a long latency operation (div, sqrt, recip,
1891 ;; sqrt) iterates an intermediate result back through the floating
1892 ;; point register file bypass, then instead returning the correct
1893 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1894 ;; result of the long latency operation.
1896 ;; The workaround is to insert an unconditional 'mov' from/to the
1897 ;; long latency op destination register.
1899 (define_insn "*div<mode>3"
1900 [(set (match_operand:ANYF 0 "register_operand" "=f")
1901 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1902 (match_operand:ANYF 2 "register_operand" "f")))]
1903 "<divide_condition>"
1906 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1908 return "div.<fmt>\t%0,%1,%2";
1910 [(set_attr "type" "fdiv")
1911 (set_attr "mode" "<UNITMODE>")
1912 (set (attr "length")
1913 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1917 (define_insn "*recip<mode>3"
1918 [(set (match_operand:ANYF 0 "register_operand" "=f")
1919 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1920 (match_operand:ANYF 2 "register_operand" "f")))]
1921 "<recip_condition> && flag_unsafe_math_optimizations"
1924 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1926 return "recip.<fmt>\t%0,%2";
1928 [(set_attr "type" "frdiv")
1929 (set_attr "mode" "<UNITMODE>")
1930 (set (attr "length")
1931 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1935 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1936 ;; with negative operands. We use special libgcc functions instead.
1937 (define_insn "divmod<mode>4"
1938 [(set (match_operand:GPR 0 "register_operand" "=l")
1939 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1940 (match_operand:GPR 2 "register_operand" "d")))
1941 (set (match_operand:GPR 3 "register_operand" "=h")
1942 (mod:GPR (match_dup 1)
1944 "!TARGET_FIX_VR4120"
1945 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1946 [(set_attr "type" "idiv")
1947 (set_attr "mode" "<MODE>")])
1949 (define_insn "udivmod<mode>4"
1950 [(set (match_operand:GPR 0 "register_operand" "=l")
1951 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
1952 (match_operand:GPR 2 "register_operand" "d")))
1953 (set (match_operand:GPR 3 "register_operand" "=h")
1954 (umod:GPR (match_dup 1)
1957 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
1958 [(set_attr "type" "idiv")
1959 (set_attr "mode" "<MODE>")])
1962 ;; ....................
1966 ;; ....................
1968 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
1969 ;; "*div[sd]f3" comment for details).
1971 (define_insn "sqrt<mode>2"
1972 [(set (match_operand:ANYF 0 "register_operand" "=f")
1973 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1977 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
1979 return "sqrt.<fmt>\t%0,%1";
1981 [(set_attr "type" "fsqrt")
1982 (set_attr "mode" "<UNITMODE>")
1983 (set (attr "length")
1984 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1988 (define_insn "*rsqrt<mode>a"
1989 [(set (match_operand:ANYF 0 "register_operand" "=f")
1990 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1991 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
1992 "<recip_condition> && flag_unsafe_math_optimizations"
1995 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1997 return "rsqrt.<fmt>\t%0,%2";
1999 [(set_attr "type" "frsqrt")
2000 (set_attr "mode" "<UNITMODE>")
2001 (set (attr "length")
2002 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2006 (define_insn "*rsqrt<mode>b"
2007 [(set (match_operand:ANYF 0 "register_operand" "=f")
2008 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2009 (match_operand:ANYF 2 "register_operand" "f"))))]
2010 "<recip_condition> && flag_unsafe_math_optimizations"
2013 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2015 return "rsqrt.<fmt>\t%0,%2";
2017 [(set_attr "type" "frsqrt")
2018 (set_attr "mode" "<UNITMODE>")
2019 (set (attr "length")
2020 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2025 ;; ....................
2029 ;; ....................
2031 ;; Do not use the integer abs macro instruction, since that signals an
2032 ;; exception on -2147483648 (sigh).
2034 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2035 ;; invalid; it does not clear their sign bits. We therefore can't use
2036 ;; abs.fmt if the signs of NaNs matter.
2038 (define_insn "abs<mode>2"
2039 [(set (match_operand:ANYF 0 "register_operand" "=f")
2040 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2041 "!HONOR_NANS (<MODE>mode)"
2043 [(set_attr "type" "fabs")
2044 (set_attr "mode" "<UNITMODE>")])
2047 ;; ...................
2049 ;; Count leading zeroes.
2051 ;; ...................
2054 (define_insn "clz<mode>2"
2055 [(set (match_operand:GPR 0 "register_operand" "=d")
2056 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2059 [(set_attr "type" "clz")
2060 (set_attr "mode" "<MODE>")])
2063 ;; ....................
2065 ;; NEGATION and ONE'S COMPLEMENT
2067 ;; ....................
2069 (define_insn "negsi2"
2070 [(set (match_operand:SI 0 "register_operand" "=d")
2071 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2075 return "neg\t%0,%1";
2077 return "subu\t%0,%.,%1";
2079 [(set_attr "type" "arith")
2080 (set_attr "mode" "SI")])
2082 (define_insn "negdi2"
2083 [(set (match_operand:DI 0 "register_operand" "=d")
2084 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2085 "TARGET_64BIT && !TARGET_MIPS16"
2087 [(set_attr "type" "arith")
2088 (set_attr "mode" "DI")])
2090 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2091 ;; invalid; it does not flip their sign bit. We therefore can't use
2092 ;; neg.fmt if the signs of NaNs matter.
2094 (define_insn "neg<mode>2"
2095 [(set (match_operand:ANYF 0 "register_operand" "=f")
2096 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2097 "!HONOR_NANS (<MODE>mode)"
2099 [(set_attr "type" "fneg")
2100 (set_attr "mode" "<UNITMODE>")])
2102 (define_insn "one_cmpl<mode>2"
2103 [(set (match_operand:GPR 0 "register_operand" "=d")
2104 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2108 return "not\t%0,%1";
2110 return "nor\t%0,%.,%1";
2112 [(set_attr "type" "arith")
2113 (set_attr "mode" "<MODE>")])
2116 ;; ....................
2120 ;; ....................
2123 ;; Many of these instructions use trivial define_expands, because we
2124 ;; want to use a different set of constraints when TARGET_MIPS16.
2126 (define_expand "and<mode>3"
2127 [(set (match_operand:GPR 0 "register_operand")
2128 (and:GPR (match_operand:GPR 1 "register_operand")
2129 (match_operand:GPR 2 "uns_arith_operand")))]
2133 operands[2] = force_reg (<MODE>mode, operands[2]);
2136 (define_insn "*and<mode>3"
2137 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2138 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2139 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2144 [(set_attr "type" "arith")
2145 (set_attr "mode" "<MODE>")])
2147 (define_insn "*and<mode>3_mips16"
2148 [(set (match_operand:GPR 0 "register_operand" "=d")
2149 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2150 (match_operand:GPR 2 "register_operand" "d")))]
2153 [(set_attr "type" "arith")
2154 (set_attr "mode" "<MODE>")])
2156 (define_expand "ior<mode>3"
2157 [(set (match_operand:GPR 0 "register_operand")
2158 (ior:GPR (match_operand:GPR 1 "register_operand")
2159 (match_operand:GPR 2 "uns_arith_operand")))]
2163 operands[2] = force_reg (<MODE>mode, operands[2]);
2166 (define_insn "*ior<mode>3"
2167 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2168 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2169 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2174 [(set_attr "type" "arith")
2175 (set_attr "mode" "<MODE>")])
2177 (define_insn "*ior<mode>3_mips16"
2178 [(set (match_operand:GPR 0 "register_operand" "=d")
2179 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2180 (match_operand:GPR 2 "register_operand" "d")))]
2183 [(set_attr "type" "arith")
2184 (set_attr "mode" "<MODE>")])
2186 (define_expand "xor<mode>3"
2187 [(set (match_operand:GPR 0 "register_operand")
2188 (xor:GPR (match_operand:GPR 1 "register_operand")
2189 (match_operand:GPR 2 "uns_arith_operand")))]
2194 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2195 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2196 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2201 [(set_attr "type" "arith")
2202 (set_attr "mode" "<MODE>")])
2205 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2206 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2207 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2213 [(set_attr "type" "arith")
2214 (set_attr "mode" "<MODE>")
2215 (set_attr_alternative "length"
2217 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2222 (define_insn "*nor<mode>3"
2223 [(set (match_operand:GPR 0 "register_operand" "=d")
2224 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2225 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2228 [(set_attr "type" "arith")
2229 (set_attr "mode" "<MODE>")])
2232 ;; ....................
2236 ;; ....................
2240 (define_insn "truncdfsf2"
2241 [(set (match_operand:SF 0 "register_operand" "=f")
2242 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2243 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2245 [(set_attr "type" "fcvt")
2246 (set_attr "cnv_mode" "D2S")
2247 (set_attr "mode" "SF")])
2249 ;; Integer truncation patterns. Truncating SImode values to smaller
2250 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2251 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2252 ;; need to make sure that the lower 32 bits are properly sign-extended
2253 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2254 ;; smaller than SImode is equivalent to two separate truncations:
2257 ;; DI ---> HI == DI ---> SI ---> HI
2258 ;; DI ---> QI == DI ---> SI ---> QI
2260 ;; Step A needs a real instruction but step B does not.
2262 (define_insn "truncdisi2"
2263 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2264 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2269 [(set_attr "type" "shift,store")
2270 (set_attr "mode" "SI")
2271 (set_attr "extended_mips16" "yes,*")])
2273 (define_insn "truncdihi2"
2274 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2275 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2280 [(set_attr "type" "shift,store")
2281 (set_attr "mode" "SI")
2282 (set_attr "extended_mips16" "yes,*")])
2284 (define_insn "truncdiqi2"
2285 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2286 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2291 [(set_attr "type" "shift,store")
2292 (set_attr "mode" "SI")
2293 (set_attr "extended_mips16" "yes,*")])
2295 ;; Combiner patterns to optimize shift/truncate combinations.
2298 [(set (match_operand:SI 0 "register_operand" "=d")
2300 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2301 (match_operand:DI 2 "const_arith_operand" ""))))]
2302 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2304 [(set_attr "type" "shift")
2305 (set_attr "mode" "SI")])
2308 [(set (match_operand:SI 0 "register_operand" "=d")
2309 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2311 "TARGET_64BIT && !TARGET_MIPS16"
2313 [(set_attr "type" "shift")
2314 (set_attr "mode" "SI")])
2317 ;; Combiner patterns for truncate/sign_extend combinations. They use
2318 ;; the shift/truncate patterns above.
2320 (define_insn_and_split ""
2321 [(set (match_operand:SI 0 "register_operand" "=d")
2323 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2324 "TARGET_64BIT && !TARGET_MIPS16"
2326 "&& reload_completed"
2328 (ashift:DI (match_dup 1)
2331 (truncate:SI (ashiftrt:DI (match_dup 2)
2333 { operands[2] = gen_lowpart (DImode, operands[0]); })
2335 (define_insn_and_split ""
2336 [(set (match_operand:SI 0 "register_operand" "=d")
2338 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2339 "TARGET_64BIT && !TARGET_MIPS16"
2341 "&& reload_completed"
2343 (ashift:DI (match_dup 1)
2346 (truncate:SI (ashiftrt:DI (match_dup 2)
2348 { operands[2] = gen_lowpart (DImode, operands[0]); })
2351 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2354 [(set (match_operand:SI 0 "register_operand" "=d")
2355 (zero_extend:SI (truncate:HI
2356 (match_operand:DI 1 "register_operand" "d"))))]
2357 "TARGET_64BIT && !TARGET_MIPS16"
2358 "andi\t%0,%1,0xffff"
2359 [(set_attr "type" "arith")
2360 (set_attr "mode" "SI")])
2363 [(set (match_operand:SI 0 "register_operand" "=d")
2364 (zero_extend:SI (truncate:QI
2365 (match_operand:DI 1 "register_operand" "d"))))]
2366 "TARGET_64BIT && !TARGET_MIPS16"
2368 [(set_attr "type" "arith")
2369 (set_attr "mode" "SI")])
2372 [(set (match_operand:HI 0 "register_operand" "=d")
2373 (zero_extend:HI (truncate:QI
2374 (match_operand:DI 1 "register_operand" "d"))))]
2375 "TARGET_64BIT && !TARGET_MIPS16"
2377 [(set_attr "type" "arith")
2378 (set_attr "mode" "HI")])
2381 ;; ....................
2385 ;; ....................
2389 (define_insn_and_split "zero_extendsidi2"
2390 [(set (match_operand:DI 0 "register_operand" "=d,d")
2391 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2396 "&& reload_completed && REG_P (operands[1])"
2398 (ashift:DI (match_dup 1) (const_int 32)))
2400 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2401 { operands[1] = gen_lowpart (DImode, operands[1]); }
2402 [(set_attr "type" "multi,load")
2403 (set_attr "mode" "DI")
2404 (set_attr "length" "8,*")])
2406 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2407 ;; because of TRULY_NOOP_TRUNCATION.
2409 (define_insn_and_split "*clear_upper32"
2410 [(set (match_operand:DI 0 "register_operand" "=d,d")
2411 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2412 (const_int 4294967295)))]
2415 if (which_alternative == 0)
2418 operands[1] = gen_lowpart (SImode, operands[1]);
2419 return "lwu\t%0,%1";
2421 "&& reload_completed && REG_P (operands[1])"
2423 (ashift:DI (match_dup 1) (const_int 32)))
2425 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2427 [(set_attr "type" "multi,load")
2428 (set_attr "mode" "DI")
2429 (set_attr "length" "8,*")])
2431 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2432 [(set (match_operand:GPR 0 "register_operand")
2433 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2436 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2437 && !memory_operand (operands[1], <SHORT:MODE>mode))
2439 emit_insn (gen_and<GPR:mode>3 (operands[0],
2440 gen_lowpart (<GPR:MODE>mode, operands[1]),
2441 force_reg (<GPR:MODE>mode,
2442 GEN_INT (<SHORT:mask>))));
2447 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2448 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2450 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2453 andi\t%0,%1,<SHORT:mask>
2454 l<SHORT:size>u\t%0,%1"
2455 [(set_attr "type" "arith,load")
2456 (set_attr "mode" "<GPR:MODE>")])
2458 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2459 [(set (match_operand:GPR 0 "register_operand" "=d")
2460 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2462 "ze<SHORT:size>\t%0"
2463 [(set_attr "type" "arith")
2464 (set_attr "mode" "<GPR:MODE>")])
2466 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2467 [(set (match_operand:GPR 0 "register_operand" "=d")
2468 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2470 "l<SHORT:size>u\t%0,%1"
2471 [(set_attr "type" "load")
2472 (set_attr "mode" "<GPR:MODE>")])
2474 (define_expand "zero_extendqihi2"
2475 [(set (match_operand:HI 0 "register_operand")
2476 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2479 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2481 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2487 (define_insn "*zero_extendqihi2"
2488 [(set (match_operand:HI 0 "register_operand" "=d,d")
2489 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2494 [(set_attr "type" "arith,load")
2495 (set_attr "mode" "HI")])
2497 (define_insn "*zero_extendqihi2_mips16"
2498 [(set (match_operand:HI 0 "register_operand" "=d")
2499 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2502 [(set_attr "type" "load")
2503 (set_attr "mode" "HI")])
2506 ;; ....................
2510 ;; ....................
2513 ;; Those for integer source operand are ordered widest source type first.
2515 ;; When TARGET_64BIT, all SImode integer registers should already be in
2516 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2517 ;; therefore get rid of register->register instructions if we constrain
2518 ;; the source to be in the same register as the destination.
2520 ;; The register alternative has type "arith" so that the pre-reload
2521 ;; scheduler will treat it as a move. This reflects what happens if
2522 ;; the register alternative needs a reload.
2523 (define_insn_and_split "extendsidi2"
2524 [(set (match_operand:DI 0 "register_operand" "=d,d")
2525 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2530 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2533 emit_note (NOTE_INSN_DELETED);
2536 [(set_attr "type" "arith,load")
2537 (set_attr "mode" "DI")])
2539 (define_expand "extend<SHORT:mode><GPR:mode>2"
2540 [(set (match_operand:GPR 0 "register_operand")
2541 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2544 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2545 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2546 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2550 l<SHORT:size>\t%0,%1"
2551 [(set_attr "type" "arith,load")
2552 (set_attr "mode" "<GPR:MODE>")])
2554 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2555 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2557 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2558 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2561 l<SHORT:size>\t%0,%1"
2562 "&& reload_completed && REG_P (operands[1])"
2563 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2564 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2566 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2567 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2568 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2570 [(set_attr "type" "arith,load")
2571 (set_attr "mode" "<GPR:MODE>")
2572 (set_attr "length" "8,*")])
2574 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2575 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2577 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2580 se<SHORT:size>\t%0,%1
2581 l<SHORT:size>\t%0,%1"
2582 [(set_attr "type" "arith,load")
2583 (set_attr "mode" "<GPR:MODE>")])
2585 ;; This pattern generates the same code as extendqisi2; split it into
2586 ;; that form after reload.
2587 (define_insn_and_split "extendqihi2"
2588 [(set (match_operand:HI 0 "register_operand" "=d,d")
2589 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2593 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
2594 { operands[0] = gen_lowpart (SImode, operands[0]); }
2595 [(set_attr "type" "arith,load")
2596 (set_attr "mode" "SI")
2597 (set_attr "length" "8,*")])
2599 (define_insn "extendsfdf2"
2600 [(set (match_operand:DF 0 "register_operand" "=f")
2601 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2602 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2604 [(set_attr "type" "fcvt")
2605 (set_attr "cnv_mode" "S2D")
2606 (set_attr "mode" "DF")])
2609 ;; ....................
2613 ;; ....................
2615 (define_expand "fix_truncdfsi2"
2616 [(set (match_operand:SI 0 "register_operand")
2617 (fix:SI (match_operand:DF 1 "register_operand")))]
2618 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2620 if (!ISA_HAS_TRUNC_W)
2622 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2627 (define_insn "fix_truncdfsi2_insn"
2628 [(set (match_operand:SI 0 "register_operand" "=f")
2629 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2630 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2632 [(set_attr "type" "fcvt")
2633 (set_attr "mode" "DF")
2634 (set_attr "cnv_mode" "D2I")
2635 (set_attr "length" "4")])
2637 (define_insn "fix_truncdfsi2_macro"
2638 [(set (match_operand:SI 0 "register_operand" "=f")
2639 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2640 (clobber (match_scratch:DF 2 "=d"))]
2641 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2644 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2646 return "trunc.w.d %0,%1,%2";
2648 [(set_attr "type" "fcvt")
2649 (set_attr "mode" "DF")
2650 (set_attr "cnv_mode" "D2I")
2651 (set_attr "length" "36")])
2653 (define_expand "fix_truncsfsi2"
2654 [(set (match_operand:SI 0 "register_operand")
2655 (fix:SI (match_operand:SF 1 "register_operand")))]
2658 if (!ISA_HAS_TRUNC_W)
2660 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2665 (define_insn "fix_truncsfsi2_insn"
2666 [(set (match_operand:SI 0 "register_operand" "=f")
2667 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2668 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2670 [(set_attr "type" "fcvt")
2671 (set_attr "mode" "SF")
2672 (set_attr "cnv_mode" "S2I")
2673 (set_attr "length" "4")])
2675 (define_insn "fix_truncsfsi2_macro"
2676 [(set (match_operand:SI 0 "register_operand" "=f")
2677 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2678 (clobber (match_scratch:SF 2 "=d"))]
2679 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2682 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2684 return "trunc.w.s %0,%1,%2";
2686 [(set_attr "type" "fcvt")
2687 (set_attr "mode" "SF")
2688 (set_attr "cnv_mode" "S2I")
2689 (set_attr "length" "36")])
2692 (define_insn "fix_truncdfdi2"
2693 [(set (match_operand:DI 0 "register_operand" "=f")
2694 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2695 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2697 [(set_attr "type" "fcvt")
2698 (set_attr "mode" "DF")
2699 (set_attr "cnv_mode" "D2I")
2700 (set_attr "length" "4")])
2703 (define_insn "fix_truncsfdi2"
2704 [(set (match_operand:DI 0 "register_operand" "=f")
2705 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2706 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2708 [(set_attr "type" "fcvt")
2709 (set_attr "mode" "SF")
2710 (set_attr "cnv_mode" "S2I")
2711 (set_attr "length" "4")])
2714 (define_insn "floatsidf2"
2715 [(set (match_operand:DF 0 "register_operand" "=f")
2716 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2717 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2719 [(set_attr "type" "fcvt")
2720 (set_attr "mode" "DF")
2721 (set_attr "cnv_mode" "I2D")
2722 (set_attr "length" "4")])
2725 (define_insn "floatdidf2"
2726 [(set (match_operand:DF 0 "register_operand" "=f")
2727 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2728 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2730 [(set_attr "type" "fcvt")
2731 (set_attr "mode" "DF")
2732 (set_attr "cnv_mode" "I2D")
2733 (set_attr "length" "4")])
2736 (define_insn "floatsisf2"
2737 [(set (match_operand:SF 0 "register_operand" "=f")
2738 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2741 [(set_attr "type" "fcvt")
2742 (set_attr "mode" "SF")
2743 (set_attr "cnv_mode" "I2S")
2744 (set_attr "length" "4")])
2747 (define_insn "floatdisf2"
2748 [(set (match_operand:SF 0 "register_operand" "=f")
2749 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2750 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2752 [(set_attr "type" "fcvt")
2753 (set_attr "mode" "SF")
2754 (set_attr "cnv_mode" "I2S")
2755 (set_attr "length" "4")])
2758 (define_expand "fixuns_truncdfsi2"
2759 [(set (match_operand:SI 0 "register_operand")
2760 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2761 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2763 rtx reg1 = gen_reg_rtx (DFmode);
2764 rtx reg2 = gen_reg_rtx (DFmode);
2765 rtx reg3 = gen_reg_rtx (SImode);
2766 rtx label1 = gen_label_rtx ();
2767 rtx label2 = gen_label_rtx ();
2768 REAL_VALUE_TYPE offset;
2770 real_2expN (&offset, 31);
2772 if (reg1) /* Turn off complaints about unreached code. */
2774 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2775 do_pending_stack_adjust ();
2777 emit_insn (gen_cmpdf (operands[1], reg1));
2778 emit_jump_insn (gen_bge (label1));
2780 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2781 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2782 gen_rtx_LABEL_REF (VOIDmode, label2)));
2785 emit_label (label1);
2786 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2787 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2788 (BITMASK_HIGH, SImode)));
2790 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2791 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2793 emit_label (label2);
2795 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2796 fields, and can't be used for REG_NOTES anyway). */
2797 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2803 (define_expand "fixuns_truncdfdi2"
2804 [(set (match_operand:DI 0 "register_operand")
2805 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2806 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2808 rtx reg1 = gen_reg_rtx (DFmode);
2809 rtx reg2 = gen_reg_rtx (DFmode);
2810 rtx reg3 = gen_reg_rtx (DImode);
2811 rtx label1 = gen_label_rtx ();
2812 rtx label2 = gen_label_rtx ();
2813 REAL_VALUE_TYPE offset;
2815 real_2expN (&offset, 63);
2817 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2818 do_pending_stack_adjust ();
2820 emit_insn (gen_cmpdf (operands[1], reg1));
2821 emit_jump_insn (gen_bge (label1));
2823 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2824 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2825 gen_rtx_LABEL_REF (VOIDmode, label2)));
2828 emit_label (label1);
2829 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2830 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2831 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2833 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2834 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2836 emit_label (label2);
2838 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2839 fields, and can't be used for REG_NOTES anyway). */
2840 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2845 (define_expand "fixuns_truncsfsi2"
2846 [(set (match_operand:SI 0 "register_operand")
2847 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2850 rtx reg1 = gen_reg_rtx (SFmode);
2851 rtx reg2 = gen_reg_rtx (SFmode);
2852 rtx reg3 = gen_reg_rtx (SImode);
2853 rtx label1 = gen_label_rtx ();
2854 rtx label2 = gen_label_rtx ();
2855 REAL_VALUE_TYPE offset;
2857 real_2expN (&offset, 31);
2859 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2860 do_pending_stack_adjust ();
2862 emit_insn (gen_cmpsf (operands[1], reg1));
2863 emit_jump_insn (gen_bge (label1));
2865 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2866 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2867 gen_rtx_LABEL_REF (VOIDmode, label2)));
2870 emit_label (label1);
2871 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2872 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2873 (BITMASK_HIGH, SImode)));
2875 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2876 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2878 emit_label (label2);
2880 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2881 fields, and can't be used for REG_NOTES anyway). */
2882 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2887 (define_expand "fixuns_truncsfdi2"
2888 [(set (match_operand:DI 0 "register_operand")
2889 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2890 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2892 rtx reg1 = gen_reg_rtx (SFmode);
2893 rtx reg2 = gen_reg_rtx (SFmode);
2894 rtx reg3 = gen_reg_rtx (DImode);
2895 rtx label1 = gen_label_rtx ();
2896 rtx label2 = gen_label_rtx ();
2897 REAL_VALUE_TYPE offset;
2899 real_2expN (&offset, 63);
2901 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2902 do_pending_stack_adjust ();
2904 emit_insn (gen_cmpsf (operands[1], reg1));
2905 emit_jump_insn (gen_bge (label1));
2907 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2908 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2909 gen_rtx_LABEL_REF (VOIDmode, label2)));
2912 emit_label (label1);
2913 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2914 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2915 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2917 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2918 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2920 emit_label (label2);
2922 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2923 fields, and can't be used for REG_NOTES anyway). */
2924 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2929 ;; ....................
2933 ;; ....................
2935 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
2937 (define_expand "extv"
2938 [(set (match_operand 0 "register_operand")
2939 (sign_extract (match_operand:QI 1 "memory_operand")
2940 (match_operand 2 "immediate_operand")
2941 (match_operand 3 "immediate_operand")))]
2944 if (mips_expand_unaligned_load (operands[0], operands[1],
2945 INTVAL (operands[2]),
2946 INTVAL (operands[3])))
2952 (define_expand "extzv"
2953 [(set (match_operand 0 "register_operand")
2954 (zero_extract (match_operand 1 "nonimmediate_operand")
2955 (match_operand 2 "immediate_operand")
2956 (match_operand 3 "immediate_operand")))]
2959 if (mips_expand_unaligned_load (operands[0], operands[1],
2960 INTVAL (operands[2]),
2961 INTVAL (operands[3])))
2963 else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
2965 if (GET_MODE (operands[0]) == DImode)
2966 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
2969 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
2977 (define_insn "extzv<mode>"
2978 [(set (match_operand:GPR 0 "register_operand" "=d")
2979 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
2980 (match_operand:SI 2 "immediate_operand" "I")
2981 (match_operand:SI 3 "immediate_operand" "I")))]
2982 "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
2983 "<d>ext\t%0,%1,%3,%2"
2984 [(set_attr "type" "arith")
2985 (set_attr "mode" "<MODE>")])
2988 (define_expand "insv"
2989 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
2990 (match_operand 1 "immediate_operand")
2991 (match_operand 2 "immediate_operand"))
2992 (match_operand 3 "reg_or_0_operand"))]
2995 if (mips_expand_unaligned_store (operands[0], operands[3],
2996 INTVAL (operands[1]),
2997 INTVAL (operands[2])))
2999 else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
3001 if (GET_MODE (operands[0]) == DImode)
3002 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3005 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3013 (define_insn "insv<mode>"
3014 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3015 (match_operand:SI 1 "immediate_operand" "I")
3016 (match_operand:SI 2 "immediate_operand" "I"))
3017 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3018 "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
3019 "<d>ins\t%0,%z3,%2,%1"
3020 [(set_attr "type" "arith")
3021 (set_attr "mode" "<MODE>")])
3023 ;; Unaligned word moves generated by the bit field patterns.
3025 ;; As far as the rtl is concerned, both the left-part and right-part
3026 ;; instructions can access the whole field. However, the real operand
3027 ;; refers to just the first or the last byte (depending on endianness).
3028 ;; We therefore use two memory operands to each instruction, one to
3029 ;; describe the rtl effect and one to use in the assembly output.
3031 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3032 ;; This allows us to use the standard length calculations for the "load"
3033 ;; and "store" type attributes.
3035 (define_insn "mov_<load>l"
3036 [(set (match_operand:GPR 0 "register_operand" "=d")
3037 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3038 (match_operand:QI 2 "memory_operand" "m")]
3040 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3042 [(set_attr "type" "load")
3043 (set_attr "mode" "<MODE>")])
3045 (define_insn "mov_<load>r"
3046 [(set (match_operand:GPR 0 "register_operand" "=d")
3047 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3048 (match_operand:QI 2 "memory_operand" "m")
3049 (match_operand:GPR 3 "register_operand" "0")]
3050 UNSPEC_LOAD_RIGHT))]
3051 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3053 [(set_attr "type" "load")
3054 (set_attr "mode" "<MODE>")])
3056 (define_insn "mov_<store>l"
3057 [(set (match_operand:BLK 0 "memory_operand" "=m")
3058 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3059 (match_operand:QI 2 "memory_operand" "m")]
3060 UNSPEC_STORE_LEFT))]
3061 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3063 [(set_attr "type" "store")
3064 (set_attr "mode" "<MODE>")])
3066 (define_insn "mov_<store>r"
3067 [(set (match_operand:BLK 0 "memory_operand" "+m")
3068 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3069 (match_operand:QI 2 "memory_operand" "m")
3071 UNSPEC_STORE_RIGHT))]
3072 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3074 [(set_attr "type" "store")
3075 (set_attr "mode" "<MODE>")])
3077 ;; An instruction to calculate the high part of a 64-bit SYMBOL_GENERAL.
3078 ;; The required value is:
3080 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3082 ;; which translates to:
3084 ;; lui op0,%highest(op1)
3085 ;; daddiu op0,op0,%higher(op1)
3087 ;; daddiu op0,op0,%hi(op1)
3090 ;; The split is deferred until after flow2 to allow the peephole2 below
3092 (define_insn_and_split "*lea_high64"
3093 [(set (match_operand:DI 0 "register_operand" "=d")
3094 (high:DI (match_operand:DI 1 "general_symbolic_operand" "")))]
3095 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3097 "&& flow2_completed"
3098 [(set (match_dup 0) (high:DI (match_dup 2)))
3099 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3100 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3101 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3102 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3104 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3105 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3107 [(set_attr "length" "20")])
3109 ;; Use a scratch register to reduce the latency of the above pattern
3110 ;; on superscalar machines. The optimized sequence is:
3112 ;; lui op1,%highest(op2)
3114 ;; daddiu op1,op1,%higher(op2)
3116 ;; daddu op1,op1,op0
3118 [(set (match_operand:DI 1 "register_operand")
3119 (high:DI (match_operand:DI 2 "general_symbolic_operand")))
3120 (match_scratch:DI 0 "d")]
3121 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3122 [(set (match_dup 1) (high:DI (match_dup 3)))
3123 (set (match_dup 0) (high:DI (match_dup 4)))
3124 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3125 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3126 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3128 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3129 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3132 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3133 ;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine
3134 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3135 ;; used once. We can then use the sequence:
3137 ;; lui op0,%highest(op1)
3139 ;; daddiu op0,op0,%higher(op1)
3140 ;; daddiu op2,op2,%lo(op1)
3142 ;; daddu op0,op0,op2
3144 ;; which takes 4 cycles on most superscalar targets.
3145 (define_insn_and_split "*lea64"
3146 [(set (match_operand:DI 0 "register_operand" "=d")
3147 (match_operand:DI 1 "general_symbolic_operand" ""))
3148 (clobber (match_scratch:DI 2 "=&d"))]
3149 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3151 "&& reload_completed"
3152 [(set (match_dup 0) (high:DI (match_dup 3)))
3153 (set (match_dup 2) (high:DI (match_dup 4)))
3154 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3155 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3156 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3157 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3159 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3160 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3162 [(set_attr "length" "24")])
3164 ;; Insns to fetch a symbol from a big GOT.
3166 (define_insn_and_split "*xgot_hi<mode>"
3167 [(set (match_operand:P 0 "register_operand" "=d")
3168 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3169 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3171 "&& reload_completed"
3172 [(set (match_dup 0) (high:P (match_dup 2)))
3173 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3175 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3176 operands[3] = pic_offset_table_rtx;
3178 [(set_attr "got" "xgot_high")
3179 (set_attr "mode" "<MODE>")])
3181 (define_insn_and_split "*xgot_lo<mode>"
3182 [(set (match_operand:P 0 "register_operand" "=d")
3183 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3184 (match_operand:P 2 "got_disp_operand" "")))]
3185 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3187 "&& reload_completed"
3189 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3190 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3191 [(set_attr "got" "load")
3192 (set_attr "mode" "<MODE>")])
3194 ;; Insns to fetch a symbol from a normal GOT.
3196 (define_insn_and_split "*got_disp<mode>"
3197 [(set (match_operand:P 0 "register_operand" "=d")
3198 (match_operand:P 1 "got_disp_operand" ""))]
3199 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3201 "&& reload_completed"
3203 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3205 operands[2] = pic_offset_table_rtx;
3206 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3208 [(set_attr "got" "load")
3209 (set_attr "mode" "<MODE>")])
3211 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3213 (define_insn_and_split "*got_page<mode>"
3214 [(set (match_operand:P 0 "register_operand" "=d")
3215 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3216 "TARGET_EXPLICIT_RELOCS"
3218 "&& reload_completed"
3220 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3222 operands[2] = pic_offset_table_rtx;
3223 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3225 [(set_attr "got" "load")
3226 (set_attr "mode" "<MODE>")])
3228 ;; Lower-level instructions for loading an address from the GOT.
3229 ;; We could use MEMs, but an unspec gives more optimization
3232 (define_insn "load_got<mode>"
3233 [(set (match_operand:P 0 "register_operand" "=d")
3234 (unspec:P [(match_operand:P 1 "register_operand" "d")
3235 (match_operand:P 2 "immediate_operand" "")]
3238 "<load>\t%0,%R2(%1)"
3239 [(set_attr "type" "load")
3240 (set_attr "mode" "<MODE>")
3241 (set_attr "length" "4")])
3243 ;; Instructions for adding the low 16 bits of an address to a register.
3244 ;; Operand 2 is the address: print_operand works out which relocation
3245 ;; should be applied.
3247 (define_insn "*low<mode>"
3248 [(set (match_operand:P 0 "register_operand" "=d")
3249 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3250 (match_operand:P 2 "immediate_operand" "")))]
3252 "<d>addiu\t%0,%1,%R2"
3253 [(set_attr "type" "arith")
3254 (set_attr "mode" "<MODE>")])
3256 (define_insn "*low<mode>_mips16"
3257 [(set (match_operand:P 0 "register_operand" "=d")
3258 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3259 (match_operand:P 2 "immediate_operand" "")))]
3262 [(set_attr "type" "arith")
3263 (set_attr "mode" "<MODE>")
3264 (set_attr "length" "8")])
3266 ;; Allow combine to split complex const_int load sequences, using operand 2
3267 ;; to store the intermediate results. See move_operand for details.
3269 [(set (match_operand:GPR 0 "register_operand")
3270 (match_operand:GPR 1 "splittable_const_int_operand"))
3271 (clobber (match_operand:GPR 2 "register_operand"))]
3275 mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
3279 ;; Likewise, for symbolic operands.
3281 [(set (match_operand:P 0 "register_operand")
3282 (match_operand:P 1 "splittable_symbolic_operand"))
3283 (clobber (match_operand:P 2 "register_operand"))]
3285 [(set (match_dup 0) (match_dup 1))]
3286 { operands[1] = mips_split_symbol (operands[2], operands[1]); })
3288 ;; 64-bit integer moves
3290 ;; Unlike most other insns, the move insns can't be split with
3291 ;; different predicates, because register spilling and other parts of
3292 ;; the compiler, have memoized the insn number already.
3294 (define_expand "movdi"
3295 [(set (match_operand:DI 0 "")
3296 (match_operand:DI 1 ""))]
3299 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3303 ;; For mips16, we need a special case to handle storing $31 into
3304 ;; memory, since we don't have a constraint to match $31. This
3305 ;; instruction can be generated by save_restore_insns.
3307 (define_insn "*mov<mode>_ra"
3308 [(set (match_operand:GPR 0 "stack_operand" "=m")
3312 [(set_attr "type" "store")
3313 (set_attr "mode" "<MODE>")])
3315 (define_insn "*movdi_32bit"
3316 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3317 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3318 "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
3319 && (register_operand (operands[0], DImode)
3320 || reg_or_0_operand (operands[1], DImode))"
3321 { return mips_output_move (operands[0], operands[1]); }
3322 [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,mtc,load,mfc,store")
3323 (set_attr "mode" "DI")
3324 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3326 (define_insn "*movdi_gp32_fp64"
3327 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*f,*d,*m")
3328 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*f,*J*d,*m,*f,*f"))]
3329 "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
3330 && (register_operand (operands[0], DImode)
3331 || reg_or_0_operand (operands[1], DImode))"
3332 { return mips_output_move (operands[0], operands[1]); }
3333 [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
3334 (set_attr "mode" "DI")
3335 (set_attr "length" "8,16,*,*,8,8,4,8,*,8,*")])
3337 (define_insn "*movdi_32bit_mips16"
3338 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3339 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3340 "!TARGET_64BIT && TARGET_MIPS16
3341 && (register_operand (operands[0], DImode)
3342 || register_operand (operands[1], DImode))"
3343 { return mips_output_move (operands[0], operands[1]); }
3344 [(set_attr "type" "arith,arith,arith,arith,arith,load,store,mfhilo")
3345 (set_attr "mode" "DI")
3346 (set_attr "length" "8,8,8,8,12,*,*,8")])
3348 (define_insn "*movdi_64bit"
3349 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3350 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3351 "TARGET_64BIT && !TARGET_MIPS16
3352 && (register_operand (operands[0], DImode)
3353 || reg_or_0_operand (operands[1], DImode))"
3354 { return mips_output_move (operands[0], operands[1]); }
3355 [(set_attr "type" "arith,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
3356 (set_attr "mode" "DI")
3357 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
3359 (define_insn "*movdi_64bit_mips16"
3360 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3361 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3362 "TARGET_64BIT && TARGET_MIPS16
3363 && (register_operand (operands[0], DImode)
3364 || register_operand (operands[1], DImode))"
3365 { return mips_output_move (operands[0], operands[1]); }
3366 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3367 (set_attr "mode" "DI")
3368 (set_attr_alternative "length"
3372 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3375 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3380 (const_string "*")])])
3383 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3384 ;; when the original load is a 4 byte instruction but the add and the
3385 ;; load are 2 2 byte instructions.
3388 [(set (match_operand:DI 0 "register_operand")
3389 (mem:DI (plus:DI (match_dup 0)
3390 (match_operand:DI 1 "const_int_operand"))))]
3391 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3392 && !TARGET_DEBUG_D_MODE
3393 && REG_P (operands[0])
3394 && M16_REG_P (REGNO (operands[0]))
3395 && GET_CODE (operands[1]) == CONST_INT
3396 && ((INTVAL (operands[1]) < 0
3397 && INTVAL (operands[1]) >= -0x10)
3398 || (INTVAL (operands[1]) >= 32 * 8
3399 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3400 || (INTVAL (operands[1]) >= 0
3401 && INTVAL (operands[1]) < 32 * 8
3402 && (INTVAL (operands[1]) & 7) != 0))"
3403 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3404 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3406 HOST_WIDE_INT val = INTVAL (operands[1]);
3409 operands[2] = const0_rtx;
3410 else if (val >= 32 * 8)
3414 operands[1] = GEN_INT (0x8 + off);
3415 operands[2] = GEN_INT (val - off - 0x8);
3421 operands[1] = GEN_INT (off);
3422 operands[2] = GEN_INT (val - off);
3426 ;; 32-bit Integer moves
3428 ;; Unlike most other insns, the move insns can't be split with
3429 ;; different predicates, because register spilling and other parts of
3430 ;; the compiler, have memoized the insn number already.
3432 (define_expand "movsi"
3433 [(set (match_operand:SI 0 "")
3434 (match_operand:SI 1 ""))]
3437 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3441 ;; The difference between these two is whether or not ints are allowed
3442 ;; in FP registers (off by default, use -mdebugh to enable).
3444 (define_insn "*movsi_internal"
3445 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3446 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3448 && (register_operand (operands[0], SImode)
3449 || reg_or_0_operand (operands[1], SImode))"
3450 { return mips_output_move (operands[0], operands[1]); }
3451 [(set_attr "type" "arith,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
3452 (set_attr "mode" "SI")
3453 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
3455 (define_insn "*movsi_mips16"
3456 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3457 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3459 && (register_operand (operands[0], SImode)
3460 || register_operand (operands[1], SImode))"
3461 { return mips_output_move (operands[0], operands[1]); }
3462 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3463 (set_attr "mode" "SI")
3464 (set_attr_alternative "length"
3468 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3471 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3476 (const_string "*")])])
3478 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3479 ;; when the original load is a 4 byte instruction but the add and the
3480 ;; load are 2 2 byte instructions.
3483 [(set (match_operand:SI 0 "register_operand")
3484 (mem:SI (plus:SI (match_dup 0)
3485 (match_operand:SI 1 "const_int_operand"))))]
3486 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3487 && REG_P (operands[0])
3488 && M16_REG_P (REGNO (operands[0]))
3489 && GET_CODE (operands[1]) == CONST_INT
3490 && ((INTVAL (operands[1]) < 0
3491 && INTVAL (operands[1]) >= -0x80)
3492 || (INTVAL (operands[1]) >= 32 * 4
3493 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3494 || (INTVAL (operands[1]) >= 0
3495 && INTVAL (operands[1]) < 32 * 4
3496 && (INTVAL (operands[1]) & 3) != 0))"
3497 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3498 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3500 HOST_WIDE_INT val = INTVAL (operands[1]);
3503 operands[2] = const0_rtx;
3504 else if (val >= 32 * 4)
3508 operands[1] = GEN_INT (0x7c + off);
3509 operands[2] = GEN_INT (val - off - 0x7c);
3515 operands[1] = GEN_INT (off);
3516 operands[2] = GEN_INT (val - off);
3520 ;; On the mips16, we can split a load of certain constants into a load
3521 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3525 [(set (match_operand:SI 0 "register_operand")
3526 (match_operand:SI 1 "const_int_operand"))]
3527 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3528 && REG_P (operands[0])
3529 && M16_REG_P (REGNO (operands[0]))
3530 && GET_CODE (operands[1]) == CONST_INT
3531 && INTVAL (operands[1]) >= 0x100
3532 && INTVAL (operands[1]) <= 0xff + 0x7f"
3533 [(set (match_dup 0) (match_dup 1))
3534 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3536 int val = INTVAL (operands[1]);
3538 operands[1] = GEN_INT (0xff);
3539 operands[2] = GEN_INT (val - 0xff);
3542 ;; This insn handles moving CCmode values. It's really just a
3543 ;; slightly simplified copy of movsi_internal2, with additional cases
3544 ;; to move a condition register to a general register and to move
3545 ;; between the general registers and the floating point registers.
3547 (define_insn "movcc"
3548 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3549 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3550 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3551 { return mips_output_move (operands[0], operands[1]); }
3552 [(set_attr "type" "multi,arith,load,store,mfc,mtc,fmove,fpload,fpstore")
3553 (set_attr "mode" "SI")
3554 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3556 ;; Reload condition code registers. reload_incc and reload_outcc
3557 ;; both handle moves from arbitrary operands into condition code
3558 ;; registers. reload_incc handles the more common case in which
3559 ;; a source operand is constrained to be in a condition-code
3560 ;; register, but has not been allocated to one.
3562 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3563 ;; constraints do not include 'z'. reload_outcc handles the case
3564 ;; when such an operand is allocated to a condition-code register.
3566 ;; Note that reloads from a condition code register to some
3567 ;; other location can be done using ordinary moves. Moving
3568 ;; into a GPR takes a single movcc, moving elsewhere takes
3569 ;; two. We can leave these cases to the generic reload code.
3570 (define_expand "reload_incc"
3571 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3572 (match_operand:CC 1 "general_operand" ""))
3573 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3574 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3576 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3580 (define_expand "reload_outcc"
3581 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3582 (match_operand:CC 1 "register_operand" ""))
3583 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3584 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3586 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3590 ;; MIPS4 supports loading and storing a floating point register from
3591 ;; the sum of two general registers. We use two versions for each of
3592 ;; these four instructions: one where the two general registers are
3593 ;; SImode, and one where they are DImode. This is because general
3594 ;; registers will be in SImode when they hold 32-bit values, but,
3595 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
3596 ;; instructions will still work correctly.
3598 ;; ??? Perhaps it would be better to support these instructions by
3599 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3600 ;; these instructions can only be used to load and store floating
3601 ;; point registers, that would probably cause trouble in reload.
3603 (define_insn "*<ANYF:loadx>_<P:mode>"
3604 [(set (match_operand:ANYF 0 "register_operand" "=f")
3605 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3606 (match_operand:P 2 "register_operand" "d"))))]
3608 "<ANYF:loadx>\t%0,%1(%2)"
3609 [(set_attr "type" "fpidxload")
3610 (set_attr "mode" "<ANYF:UNITMODE>")])
3612 (define_insn "*<ANYF:storex>_<P:mode>"
3613 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3614 (match_operand:P 2 "register_operand" "d")))
3615 (match_operand:ANYF 0 "register_operand" "f"))]
3617 "<ANYF:storex>\t%0,%1(%2)"
3618 [(set_attr "type" "fpidxstore")
3619 (set_attr "mode" "<ANYF:UNITMODE>")])
3621 ;; 16-bit Integer moves
3623 ;; Unlike most other insns, the move insns can't be split with
3624 ;; different predicates, because register spilling and other parts of
3625 ;; the compiler, have memoized the insn number already.
3626 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3628 (define_expand "movhi"
3629 [(set (match_operand:HI 0 "")
3630 (match_operand:HI 1 ""))]
3633 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3637 (define_insn "*movhi_internal"
3638 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3639 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3641 && (register_operand (operands[0], HImode)
3642 || reg_or_0_operand (operands[1], HImode))"
3652 [(set_attr "type" "arith,arith,load,store,mfc,mtc,fmove,mthilo")
3653 (set_attr "mode" "HI")
3654 (set_attr "length" "4,4,*,*,4,4,4,4")])
3656 (define_insn "*movhi_mips16"
3657 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3658 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3660 && (register_operand (operands[0], HImode)
3661 || register_operand (operands[1], HImode))"
3670 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3671 (set_attr "mode" "HI")
3672 (set_attr_alternative "length"
3676 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3679 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3683 (const_string "*")])])
3686 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3687 ;; when the original load is a 4 byte instruction but the add and the
3688 ;; load are 2 2 byte instructions.
3691 [(set (match_operand:HI 0 "register_operand")
3692 (mem:HI (plus:SI (match_dup 0)
3693 (match_operand:SI 1 "const_int_operand"))))]
3694 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3695 && REG_P (operands[0])
3696 && M16_REG_P (REGNO (operands[0]))
3697 && GET_CODE (operands[1]) == CONST_INT
3698 && ((INTVAL (operands[1]) < 0
3699 && INTVAL (operands[1]) >= -0x80)
3700 || (INTVAL (operands[1]) >= 32 * 2
3701 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3702 || (INTVAL (operands[1]) >= 0
3703 && INTVAL (operands[1]) < 32 * 2
3704 && (INTVAL (operands[1]) & 1) != 0))"
3705 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3706 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3708 HOST_WIDE_INT val = INTVAL (operands[1]);
3711 operands[2] = const0_rtx;
3712 else if (val >= 32 * 2)
3716 operands[1] = GEN_INT (0x7e + off);
3717 operands[2] = GEN_INT (val - off - 0x7e);
3723 operands[1] = GEN_INT (off);
3724 operands[2] = GEN_INT (val - off);
3728 ;; 8-bit Integer moves
3730 ;; Unlike most other insns, the move insns can't be split with
3731 ;; different predicates, because register spilling and other parts of
3732 ;; the compiler, have memoized the insn number already.
3733 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3735 (define_expand "movqi"
3736 [(set (match_operand:QI 0 "")
3737 (match_operand:QI 1 ""))]
3740 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3744 (define_insn "*movqi_internal"
3745 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3746 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3748 && (register_operand (operands[0], QImode)
3749 || reg_or_0_operand (operands[1], QImode))"
3759 [(set_attr "type" "arith,arith,load,store,mfc,mtc,fmove,mthilo")
3760 (set_attr "mode" "QI")
3761 (set_attr "length" "4,4,*,*,4,4,4,4")])
3763 (define_insn "*movqi_mips16"
3764 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3765 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3767 && (register_operand (operands[0], QImode)
3768 || register_operand (operands[1], QImode))"
3777 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3778 (set_attr "mode" "QI")
3779 (set_attr "length" "4,4,4,4,8,*,*")])
3781 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3782 ;; when the original load is a 4 byte instruction but the add and the
3783 ;; load are 2 2 byte instructions.
3786 [(set (match_operand:QI 0 "register_operand")
3787 (mem:QI (plus:SI (match_dup 0)
3788 (match_operand:SI 1 "const_int_operand"))))]
3789 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3790 && REG_P (operands[0])
3791 && M16_REG_P (REGNO (operands[0]))
3792 && GET_CODE (operands[1]) == CONST_INT
3793 && ((INTVAL (operands[1]) < 0
3794 && INTVAL (operands[1]) >= -0x80)
3795 || (INTVAL (operands[1]) >= 32
3796 && INTVAL (operands[1]) <= 31 + 0x7f))"
3797 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3798 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3800 HOST_WIDE_INT val = INTVAL (operands[1]);
3803 operands[2] = const0_rtx;
3806 operands[1] = GEN_INT (0x7f);
3807 operands[2] = GEN_INT (val - 0x7f);
3811 ;; 32-bit floating point moves
3813 (define_expand "movsf"
3814 [(set (match_operand:SF 0 "")
3815 (match_operand:SF 1 ""))]
3818 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3822 (define_insn "*movsf_hardfloat"
3823 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3824 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3826 && (register_operand (operands[0], SFmode)
3827 || reg_or_0_operand (operands[1], SFmode))"
3828 { return mips_output_move (operands[0], operands[1]); }
3829 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3830 (set_attr "mode" "SF")
3831 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3833 (define_insn "*movsf_softfloat"
3834 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3835 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3836 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3837 && (register_operand (operands[0], SFmode)
3838 || reg_or_0_operand (operands[1], SFmode))"
3839 { return mips_output_move (operands[0], operands[1]); }
3840 [(set_attr "type" "arith,load,store")
3841 (set_attr "mode" "SF")
3842 (set_attr "length" "4,*,*")])
3844 (define_insn "*movsf_mips16"
3845 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3846 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3848 && (register_operand (operands[0], SFmode)
3849 || register_operand (operands[1], SFmode))"
3850 { return mips_output_move (operands[0], operands[1]); }
3851 [(set_attr "type" "arith,arith,arith,load,store")
3852 (set_attr "mode" "SF")
3853 (set_attr "length" "4,4,4,*,*")])
3856 ;; 64-bit floating point moves
3858 (define_expand "movdf"
3859 [(set (match_operand:DF 0 "")
3860 (match_operand:DF 1 ""))]
3863 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3867 (define_insn "*movdf_hardfloat_64bit"
3868 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3869 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3870 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3871 && (register_operand (operands[0], DFmode)
3872 || reg_or_0_operand (operands[1], DFmode))"
3873 { return mips_output_move (operands[0], operands[1]); }
3874 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3875 (set_attr "mode" "DF")
3876 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3878 ;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
3879 (define_insn "*movdf_hardfloat_32bit"
3880 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3881 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3882 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
3883 && (register_operand (operands[0], DFmode)
3884 || reg_or_0_operand (operands[1], DFmode))"
3885 { return mips_output_move (operands[0], operands[1]); }
3886 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3887 (set_attr "mode" "DF")
3888 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
3890 (define_insn "*movdf_softfloat"
3891 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
3892 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
3893 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
3894 && (register_operand (operands[0], DFmode)
3895 || reg_or_0_operand (operands[1], DFmode))"
3896 { return mips_output_move (operands[0], operands[1]); }
3897 [(set_attr "type" "arith,load,store,mfc,mtc,fmove")
3898 (set_attr "mode" "DF")
3899 (set_attr "length" "8,*,*,4,4,4")])
3901 (define_insn "*movdf_mips16"
3902 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
3903 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
3905 && (register_operand (operands[0], DFmode)
3906 || register_operand (operands[1], DFmode))"
3907 { return mips_output_move (operands[0], operands[1]); }
3908 [(set_attr "type" "arith,arith,arith,load,store")
3909 (set_attr "mode" "DF")
3910 (set_attr "length" "8,8,8,*,*")])
3913 [(set (match_operand:DI 0 "nonimmediate_operand")
3914 (match_operand:DI 1 "move_operand"))]
3915 "reload_completed && !TARGET_64BIT
3916 && mips_split_64bit_move_p (operands[0], operands[1])"
3919 mips_split_64bit_move (operands[0], operands[1]);
3924 [(set (match_operand:DF 0 "nonimmediate_operand")
3925 (match_operand:DF 1 "move_operand"))]
3926 "reload_completed && !TARGET_64BIT
3927 && mips_split_64bit_move_p (operands[0], operands[1])"
3930 mips_split_64bit_move (operands[0], operands[1]);
3934 ;; When generating mips16 code, split moves of negative constants into
3935 ;; a positive "li" followed by a negation.
3937 [(set (match_operand 0 "register_operand")
3938 (match_operand 1 "const_int_operand"))]
3939 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
3943 (neg:SI (match_dup 2)))]
3945 operands[2] = gen_lowpart (SImode, operands[0]);
3946 operands[3] = GEN_INT (-INTVAL (operands[1]));
3949 ;; 64-bit paired-single floating point moves
3951 (define_expand "movv2sf"
3952 [(set (match_operand:V2SF 0)
3953 (match_operand:V2SF 1))]
3954 "TARGET_PAIRED_SINGLE_FLOAT"
3956 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
3960 (define_insn "movv2sf_hardfloat_64bit"
3961 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3962 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
3963 "TARGET_PAIRED_SINGLE_FLOAT
3965 && (register_operand (operands[0], V2SFmode)
3966 || reg_or_0_operand (operands[1], V2SFmode))"
3967 { return mips_output_move (operands[0], operands[1]); }
3968 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3969 (set_attr "mode" "SF")
3970 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3972 ;; The HI and LO registers are not truly independent. If we move an mthi
3973 ;; instruction before an mflo instruction, it will make the result of the
3974 ;; mflo unpredictable. The same goes for mtlo and mfhi.
3976 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
3977 ;; Operand 1 is the register we want, operand 2 is the other one.
3979 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
3980 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
3981 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
3983 (define_expand "mfhilo_<mode>"
3984 [(set (match_operand:GPR 0 "register_operand")
3985 (unspec:GPR [(match_operand:GPR 1 "register_operand")
3986 (match_operand:GPR 2 "register_operand")]
3989 (define_insn "*mfhilo_<mode>"
3990 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3991 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3992 (match_operand:GPR 2 "register_operand" "l,h")]
3996 [(set_attr "type" "mfhilo")
3997 (set_attr "mode" "<MODE>")])
3999 (define_insn "*mfhilo_<mode>_macc"
4000 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4001 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4002 (match_operand:GPR 2 "register_operand" "l,h")]
4006 if (REGNO (operands[1]) == HI_REGNUM)
4007 return "<d>macchi\t%0,%.,%.";
4009 return "<d>macc\t%0,%.,%.";
4011 [(set_attr "type" "mfhilo")
4012 (set_attr "mode" "<MODE>")])
4014 ;; Patterns for loading or storing part of a paired floating point
4015 ;; register. We need them because odd-numbered floating-point registers
4016 ;; are not fully independent: see mips_split_64bit_move.
4018 ;; Load the low word of operand 0 with operand 1.
4019 (define_insn "load_df_low"
4020 [(set (match_operand:DF 0 "register_operand" "=f,f")
4021 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
4022 UNSPEC_LOAD_DF_LOW))]
4023 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4025 operands[0] = mips_subword (operands[0], 0);
4026 return mips_output_move (operands[0], operands[1]);
4028 [(set_attr "type" "mtc,fpload")
4029 (set_attr "mode" "SF")])
4031 ;; Load the high word of operand 0 from operand 1, preserving the value
4033 (define_insn "load_df_high"
4034 [(set (match_operand:DF 0 "register_operand" "=f,f")
4035 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
4036 (match_operand:DF 2 "register_operand" "0,0")]
4037 UNSPEC_LOAD_DF_HIGH))]
4038 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4040 operands[0] = mips_subword (operands[0], 1);
4041 return mips_output_move (operands[0], operands[1]);
4043 [(set_attr "type" "mtc,fpload")
4044 (set_attr "mode" "SF")])
4046 ;; Store the high word of operand 1 in operand 0. The corresponding
4047 ;; low-word move is done in the normal way.
4048 (define_insn "store_df_high"
4049 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
4050 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
4051 UNSPEC_STORE_DF_HIGH))]
4052 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4054 operands[1] = mips_subword (operands[1], 1);
4055 return mips_output_move (operands[0], operands[1]);
4057 [(set_attr "type" "mfc,fpstore")
4058 (set_attr "mode" "SF")])
4060 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4061 ;; value in the low word.
4062 (define_insn "mthc1"
4063 [(set (match_operand:DF 0 "register_operand" "=f")
4064 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ")
4065 (match_operand:DF 2 "register_operand" "0")]
4067 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4069 [(set_attr "type" "mtc")
4070 (set_attr "mode" "SF")])
4072 ;; Move high word of operand 1 to operand 0 using mfhc1. The corresponding
4073 ;; low-word move is done in the normal way.
4074 (define_insn "mfhc1"
4075 [(set (match_operand:SI 0 "register_operand" "=d")
4076 (unspec:SI [(match_operand:DF 1 "register_operand" "f")]
4078 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4080 [(set_attr "type" "mfc")
4081 (set_attr "mode" "SF")])
4083 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4084 (define_expand "load_const_gp"
4085 [(set (match_operand 0 "register_operand" "=d")
4086 (const (unspec [(const_int 0)] UNSPEC_GP)))])
4088 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4089 ;; of _gp from the start of this function. Operand 1 is the incoming
4090 ;; function address.
4091 (define_insn_and_split "loadgp_newabi"
4092 [(unspec_volatile [(match_operand 0 "" "")
4093 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
4094 "mips_current_loadgp_style () == LOADGP_NEWABI"
4097 [(set (match_dup 2) (match_dup 3))
4098 (set (match_dup 2) (match_dup 4))
4099 (set (match_dup 2) (match_dup 5))]
4101 operands[2] = pic_offset_table_rtx;
4102 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
4103 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
4104 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
4106 [(set_attr "length" "12")])
4108 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4109 (define_insn_and_split "loadgp_absolute"
4110 [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
4111 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4116 emit_move_insn (pic_offset_table_rtx, operands[0]);
4119 [(set_attr "length" "8")])
4121 ;; The use of gp is hidden when not using explicit relocations.
4122 ;; This blockage instruction prevents the gp load from being
4123 ;; scheduled after an implicit use of gp. It also prevents
4124 ;; the load from being deleted as dead.
4125 (define_insn "loadgp_blockage"
4126 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
4129 [(set_attr "type" "unknown")
4130 (set_attr "mode" "none")
4131 (set_attr "length" "0")])
4133 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4134 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4135 (define_insn "loadgp_rtp"
4136 [(unspec_volatile [(match_operand 0 "symbol_ref_operand")
4137 (match_operand 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4138 "mips_current_loadgp_style () == LOADGP_RTP"
4140 [(set_attr "length" "12")])
4143 [(unspec_volatile [(match_operand:P 0 "symbol_ref_operand")
4144 (match_operand:P 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4145 "mips_current_loadgp_style () == LOADGP_RTP"
4146 [(set (match_dup 2) (high:P (match_dup 3)))
4147 (set (match_dup 2) (unspec:P [(match_dup 2)
4148 (match_dup 3)] UNSPEC_LOAD_GOT))
4149 (set (match_dup 2) (unspec:P [(match_dup 2)
4150 (match_dup 4)] UNSPEC_LOAD_GOT))]
4152 operands[2] = pic_offset_table_rtx;
4153 operands[3] = mips_unspec_address (operands[0], SYMBOL_GENERAL);
4154 operands[4] = mips_unspec_address (operands[1], SYMBOL_HALF);
4157 ;; Emit a .cprestore directive, which normally expands to a single store
4158 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4159 ;; code so that jals inside inline asms will work correctly.
4160 (define_insn "cprestore"
4161 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")]
4165 if (set_nomacro && which_alternative == 1)
4166 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4168 return ".cprestore\t%0";
4170 [(set_attr "type" "store")
4171 (set_attr "length" "4,12")])
4173 ;; Block moves, see mips.c for more details.
4174 ;; Argument 0 is the destination
4175 ;; Argument 1 is the source
4176 ;; Argument 2 is the length
4177 ;; Argument 3 is the alignment
4179 (define_expand "movmemsi"
4180 [(parallel [(set (match_operand:BLK 0 "general_operand")
4181 (match_operand:BLK 1 "general_operand"))
4182 (use (match_operand:SI 2 ""))
4183 (use (match_operand:SI 3 "const_int_operand"))])]
4184 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4186 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4193 ;; ....................
4197 ;; ....................
4199 (define_expand "<optab><mode>3"
4200 [(set (match_operand:GPR 0 "register_operand")
4201 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4202 (match_operand:SI 2 "arith_operand")))]
4205 /* On the mips16, a shift of more than 8 is a four byte instruction,
4206 so, for a shift between 8 and 16, it is just as fast to do two
4207 shifts of 8 or less. If there is a lot of shifting going on, we
4208 may win in CSE. Otherwise combine will put the shifts back
4209 together again. This can be called by function_arg, so we must
4210 be careful not to allocate a new register if we've reached the
4214 && GET_CODE (operands[2]) == CONST_INT
4215 && INTVAL (operands[2]) > 8
4216 && INTVAL (operands[2]) <= 16
4217 && !reload_in_progress
4218 && !reload_completed)
4220 rtx temp = gen_reg_rtx (<MODE>mode);
4222 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4223 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4224 GEN_INT (INTVAL (operands[2]) - 8)));
4229 (define_insn "*<optab><mode>3"
4230 [(set (match_operand:GPR 0 "register_operand" "=d")
4231 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4232 (match_operand:SI 2 "arith_operand" "dI")))]
4235 if (GET_CODE (operands[2]) == CONST_INT)
4236 operands[2] = GEN_INT (INTVAL (operands[2])
4237 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4239 return "<d><insn>\t%0,%1,%2";
4241 [(set_attr "type" "shift")
4242 (set_attr "mode" "<MODE>")])
4244 (define_insn "*<optab>si3_extend"
4245 [(set (match_operand:DI 0 "register_operand" "=d")
4247 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4248 (match_operand:SI 2 "arith_operand" "dI"))))]
4249 "TARGET_64BIT && !TARGET_MIPS16"
4251 if (GET_CODE (operands[2]) == CONST_INT)
4252 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4254 return "<insn>\t%0,%1,%2";
4256 [(set_attr "type" "shift")
4257 (set_attr "mode" "SI")])
4259 (define_insn "*<optab>si3_mips16"
4260 [(set (match_operand:SI 0 "register_operand" "=d,d")
4261 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4262 (match_operand:SI 2 "arith_operand" "d,I")))]
4265 if (which_alternative == 0)
4266 return "<insn>\t%0,%2";
4268 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4269 return "<insn>\t%0,%1,%2";
4271 [(set_attr "type" "shift")
4272 (set_attr "mode" "SI")
4273 (set_attr_alternative "length"
4275 (if_then_else (match_operand 2 "m16_uimm3_b")
4279 ;; We need separate DImode MIPS16 patterns because of the irregularity
4281 (define_insn "*ashldi3_mips16"
4282 [(set (match_operand:DI 0 "register_operand" "=d,d")
4283 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4284 (match_operand:SI 2 "arith_operand" "d,I")))]
4285 "TARGET_64BIT && TARGET_MIPS16"
4287 if (which_alternative == 0)
4288 return "dsll\t%0,%2";
4290 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4291 return "dsll\t%0,%1,%2";
4293 [(set_attr "type" "shift")
4294 (set_attr "mode" "DI")
4295 (set_attr_alternative "length"
4297 (if_then_else (match_operand 2 "m16_uimm3_b")
4301 (define_insn "*ashrdi3_mips16"
4302 [(set (match_operand:DI 0 "register_operand" "=d,d")
4303 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4304 (match_operand:SI 2 "arith_operand" "d,I")))]
4305 "TARGET_64BIT && TARGET_MIPS16"
4307 if (GET_CODE (operands[2]) == CONST_INT)
4308 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4310 return "dsra\t%0,%2";
4312 [(set_attr "type" "shift")
4313 (set_attr "mode" "DI")
4314 (set_attr_alternative "length"
4316 (if_then_else (match_operand 2 "m16_uimm3_b")
4320 (define_insn "*lshrdi3_mips16"
4321 [(set (match_operand:DI 0 "register_operand" "=d,d")
4322 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4323 (match_operand:SI 2 "arith_operand" "d,I")))]
4324 "TARGET_64BIT && TARGET_MIPS16"
4326 if (GET_CODE (operands[2]) == CONST_INT)
4327 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4329 return "dsrl\t%0,%2";
4331 [(set_attr "type" "shift")
4332 (set_attr "mode" "DI")
4333 (set_attr_alternative "length"
4335 (if_then_else (match_operand 2 "m16_uimm3_b")
4339 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4342 [(set (match_operand:GPR 0 "register_operand")
4343 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4344 (match_operand:GPR 2 "const_int_operand")))]
4345 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4346 && GET_CODE (operands[2]) == CONST_INT
4347 && INTVAL (operands[2]) > 8
4348 && INTVAL (operands[2]) <= 16"
4349 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4350 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4351 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4353 ;; If we load a byte on the mips16 as a bitfield, the resulting
4354 ;; sequence of instructions is too complicated for combine, because it
4355 ;; involves four instructions: a load, a shift, a constant load into a
4356 ;; register, and an and (the key problem here is that the mips16 does
4357 ;; not have and immediate). We recognize a shift of a load in order
4358 ;; to make it simple enough for combine to understand.
4360 ;; The length here is the worst case: the length of the split version
4361 ;; will be more accurate.
4362 (define_insn_and_split ""
4363 [(set (match_operand:SI 0 "register_operand" "=d")
4364 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4365 (match_operand:SI 2 "immediate_operand" "I")))]
4369 [(set (match_dup 0) (match_dup 1))
4370 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4372 [(set_attr "type" "load")
4373 (set_attr "mode" "SI")
4374 (set_attr "length" "16")])
4376 (define_insn "rotr<mode>3"
4377 [(set (match_operand:GPR 0 "register_operand" "=d")
4378 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4379 (match_operand:SI 2 "arith_operand" "dI")))]
4382 if (GET_CODE (operands[2]) == CONST_INT)
4383 gcc_assert (INTVAL (operands[2]) >= 0
4384 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4386 return "<d>ror\t%0,%1,%2";
4388 [(set_attr "type" "shift")
4389 (set_attr "mode" "<MODE>")])
4392 ;; ....................
4396 ;; ....................
4398 ;; Flow here is rather complex:
4400 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4401 ;; into cmp_operands[] but generates no RTL.
4403 ;; 2) The appropriate branch define_expand is called, which then
4404 ;; creates the appropriate RTL for the comparison and branch.
4405 ;; Different CC modes are used, based on what type of branch is
4406 ;; done, so that we can constrain things appropriately. There
4407 ;; are assumptions in the rest of GCC that break if we fold the
4408 ;; operands into the branches for integer operations, and use cc0
4409 ;; for floating point, so we use the fp status register instead.
4410 ;; If needed, an appropriate temporary is created to hold the
4411 ;; of the integer compare.
4413 (define_expand "cmp<mode>"
4415 (compare:CC (match_operand:GPR 0 "register_operand")
4416 (match_operand:GPR 1 "nonmemory_operand")))]
4419 cmp_operands[0] = operands[0];
4420 cmp_operands[1] = operands[1];
4424 (define_expand "cmp<mode>"
4426 (compare:CC (match_operand:SCALARF 0 "register_operand")
4427 (match_operand:SCALARF 1 "register_operand")))]
4430 cmp_operands[0] = operands[0];
4431 cmp_operands[1] = operands[1];
4436 ;; ....................
4438 ;; CONDITIONAL BRANCHES
4440 ;; ....................
4442 ;; Conditional branches on floating-point equality tests.
4444 (define_insn "*branch_fp"
4447 (match_operator 0 "equality_operator"
4448 [(match_operand:CC 2 "register_operand" "z")
4450 (label_ref (match_operand 1 "" ""))
4454 return mips_output_conditional_branch (insn, operands,
4455 MIPS_BRANCH ("b%F0", "%Z2%1"),
4456 MIPS_BRANCH ("b%W0", "%Z2%1"));
4458 [(set_attr "type" "branch")
4459 (set_attr "mode" "none")])
4461 (define_insn "*branch_fp_inverted"
4464 (match_operator 0 "equality_operator"
4465 [(match_operand:CC 2 "register_operand" "z")
4468 (label_ref (match_operand 1 "" ""))))]
4471 return mips_output_conditional_branch (insn, operands,
4472 MIPS_BRANCH ("b%W0", "%Z2%1"),
4473 MIPS_BRANCH ("b%F0", "%Z2%1"));
4475 [(set_attr "type" "branch")
4476 (set_attr "mode" "none")])
4478 ;; Conditional branches on ordered comparisons with zero.
4480 (define_insn "*branch_order<mode>"
4483 (match_operator 0 "order_operator"
4484 [(match_operand:GPR 2 "register_operand" "d")
4486 (label_ref (match_operand 1 "" ""))
4489 { return mips_output_order_conditional_branch (insn, operands, false); }
4490 [(set_attr "type" "branch")
4491 (set_attr "mode" "none")])
4493 (define_insn "*branch_order<mode>_inverted"
4496 (match_operator 0 "order_operator"
4497 [(match_operand:GPR 2 "register_operand" "d")
4500 (label_ref (match_operand 1 "" ""))))]
4502 { return mips_output_order_conditional_branch (insn, operands, true); }
4503 [(set_attr "type" "branch")
4504 (set_attr "mode" "none")])
4506 ;; Conditional branch on equality comparison.
4508 (define_insn "*branch_equality<mode>"
4511 (match_operator 0 "equality_operator"
4512 [(match_operand:GPR 2 "register_operand" "d")
4513 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4514 (label_ref (match_operand 1 "" ""))
4518 return mips_output_conditional_branch (insn, operands,
4519 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
4520 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
4522 [(set_attr "type" "branch")
4523 (set_attr "mode" "none")])
4525 (define_insn "*branch_equality<mode>_inverted"
4528 (match_operator 0 "equality_operator"
4529 [(match_operand:GPR 2 "register_operand" "d")
4530 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4532 (label_ref (match_operand 1 "" ""))))]
4535 return mips_output_conditional_branch (insn, operands,
4536 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
4537 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
4539 [(set_attr "type" "branch")
4540 (set_attr "mode" "none")])
4544 (define_insn "*branch_equality<mode>_mips16"
4547 (match_operator 0 "equality_operator"
4548 [(match_operand:GPR 1 "register_operand" "d,t")
4550 (match_operand 2 "pc_or_label_operand" "")
4551 (match_operand 3 "pc_or_label_operand" "")))]
4554 if (operands[2] != pc_rtx)
4556 if (which_alternative == 0)
4557 return "b%C0z\t%1,%2";
4559 return "bt%C0z\t%2";
4563 if (which_alternative == 0)
4564 return "b%N0z\t%1,%3";
4566 return "bt%N0z\t%3";
4569 [(set_attr "type" "branch")
4570 (set_attr "mode" "none")
4571 (set_attr "length" "8")])
4573 (define_expand "b<code>"
4575 (if_then_else (any_cond:CC (cc0)
4577 (label_ref (match_operand 0 ""))
4581 gen_conditional_branch (operands, <CODE>);
4585 ;; Used to implement built-in functions.
4586 (define_expand "condjump"
4588 (if_then_else (match_operand 0)
4589 (label_ref (match_operand 1))
4593 ;; ....................
4595 ;; SETTING A REGISTER FROM A COMPARISON
4597 ;; ....................
4599 (define_expand "seq"
4600 [(set (match_operand:SI 0 "register_operand")
4601 (eq:SI (match_dup 1)
4604 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
4606 (define_insn "*seq_<mode>"
4607 [(set (match_operand:GPR 0 "register_operand" "=d")
4608 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4612 [(set_attr "type" "slt")
4613 (set_attr "mode" "<MODE>")])
4615 (define_insn "*seq_<mode>_mips16"
4616 [(set (match_operand:GPR 0 "register_operand" "=t")
4617 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4621 [(set_attr "type" "slt")
4622 (set_attr "mode" "<MODE>")])
4624 ;; "sne" uses sltu instructions in which the first operand is $0.
4625 ;; This isn't possible in mips16 code.
4627 (define_expand "sne"
4628 [(set (match_operand:SI 0 "register_operand")
4629 (ne:SI (match_dup 1)
4632 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
4634 (define_insn "*sne_<mode>"
4635 [(set (match_operand:GPR 0 "register_operand" "=d")
4636 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
4640 [(set_attr "type" "slt")
4641 (set_attr "mode" "<MODE>")])
4643 (define_expand "sgt"
4644 [(set (match_operand:SI 0 "register_operand")
4645 (gt:SI (match_dup 1)
4648 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
4650 (define_insn "*sgt_<mode>"
4651 [(set (match_operand:GPR 0 "register_operand" "=d")
4652 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4653 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4656 [(set_attr "type" "slt")
4657 (set_attr "mode" "<MODE>")])
4659 (define_insn "*sgt_<mode>_mips16"
4660 [(set (match_operand:GPR 0 "register_operand" "=t")
4661 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4662 (match_operand:GPR 2 "register_operand" "d")))]
4665 [(set_attr "type" "slt")
4666 (set_attr "mode" "<MODE>")])
4668 (define_expand "sge"
4669 [(set (match_operand:SI 0 "register_operand")
4670 (ge:SI (match_dup 1)
4673 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
4675 (define_insn "*sge_<mode>"
4676 [(set (match_operand:GPR 0 "register_operand" "=d")
4677 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
4681 [(set_attr "type" "slt")
4682 (set_attr "mode" "<MODE>")])
4684 (define_expand "slt"
4685 [(set (match_operand:SI 0 "register_operand")
4686 (lt:SI (match_dup 1)
4689 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
4691 (define_insn "*slt_<mode>"
4692 [(set (match_operand:GPR 0 "register_operand" "=d")
4693 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
4694 (match_operand:GPR 2 "arith_operand" "dI")))]
4697 [(set_attr "type" "slt")
4698 (set_attr "mode" "<MODE>")])
4700 (define_insn "*slt_<mode>_mips16"
4701 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4702 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
4703 (match_operand:GPR 2 "arith_operand" "d,I")))]
4706 [(set_attr "type" "slt")
4707 (set_attr "mode" "<MODE>")
4708 (set_attr_alternative "length"
4710 (if_then_else (match_operand 2 "m16_uimm8_1")
4714 (define_expand "sle"
4715 [(set (match_operand:SI 0 "register_operand")
4716 (le:SI (match_dup 1)
4719 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
4721 (define_insn "*sle_<mode>"
4722 [(set (match_operand:GPR 0 "register_operand" "=d")
4723 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4724 (match_operand:GPR 2 "sle_operand" "")))]
4727 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4728 return "slt\t%0,%1,%2";
4730 [(set_attr "type" "slt")
4731 (set_attr "mode" "<MODE>")])
4733 (define_insn "*sle_<mode>_mips16"
4734 [(set (match_operand:GPR 0 "register_operand" "=t")
4735 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4736 (match_operand:GPR 2 "sle_operand" "")))]
4739 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4740 return "slt\t%1,%2";
4742 [(set_attr "type" "slt")
4743 (set_attr "mode" "<MODE>")
4744 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4748 (define_expand "sgtu"
4749 [(set (match_operand:SI 0 "register_operand")
4750 (gtu:SI (match_dup 1)
4753 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
4755 (define_insn "*sgtu_<mode>"
4756 [(set (match_operand:GPR 0 "register_operand" "=d")
4757 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4758 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4761 [(set_attr "type" "slt")
4762 (set_attr "mode" "<MODE>")])
4764 (define_insn "*sgtu_<mode>_mips16"
4765 [(set (match_operand:GPR 0 "register_operand" "=t")
4766 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4767 (match_operand:GPR 2 "register_operand" "d")))]
4770 [(set_attr "type" "slt")
4771 (set_attr "mode" "<MODE>")])
4773 (define_expand "sgeu"
4774 [(set (match_operand:SI 0 "register_operand")
4775 (geu:SI (match_dup 1)
4778 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
4780 (define_insn "*sge_<mode>"
4781 [(set (match_operand:GPR 0 "register_operand" "=d")
4782 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
4786 [(set_attr "type" "slt")
4787 (set_attr "mode" "<MODE>")])
4789 (define_expand "sltu"
4790 [(set (match_operand:SI 0 "register_operand")
4791 (ltu:SI (match_dup 1)
4794 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
4796 (define_insn "*sltu_<mode>"
4797 [(set (match_operand:GPR 0 "register_operand" "=d")
4798 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
4799 (match_operand:GPR 2 "arith_operand" "dI")))]
4802 [(set_attr "type" "slt")
4803 (set_attr "mode" "<MODE>")])
4805 (define_insn "*sltu_<mode>_mips16"
4806 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4807 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
4808 (match_operand:GPR 2 "arith_operand" "d,I")))]
4811 [(set_attr "type" "slt")
4812 (set_attr "mode" "<MODE>")
4813 (set_attr_alternative "length"
4815 (if_then_else (match_operand 2 "m16_uimm8_1")
4819 (define_expand "sleu"
4820 [(set (match_operand:SI 0 "register_operand")
4821 (leu:SI (match_dup 1)
4824 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
4826 (define_insn "*sleu_<mode>"
4827 [(set (match_operand:GPR 0 "register_operand" "=d")
4828 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4829 (match_operand:GPR 2 "sleu_operand" "")))]
4832 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4833 return "sltu\t%0,%1,%2";
4835 [(set_attr "type" "slt")
4836 (set_attr "mode" "<MODE>")])
4838 (define_insn "*sleu_<mode>_mips16"
4839 [(set (match_operand:GPR 0 "register_operand" "=t")
4840 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4841 (match_operand:GPR 2 "sleu_operand" "")))]
4844 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4845 return "sltu\t%1,%2";
4847 [(set_attr "type" "slt")
4848 (set_attr "mode" "<MODE>")
4849 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4854 ;; ....................
4856 ;; FLOATING POINT COMPARISONS
4858 ;; ....................
4860 (define_insn "s<code>_<mode>"
4861 [(set (match_operand:CC 0 "register_operand" "=z")
4862 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4863 (match_operand:SCALARF 2 "register_operand" "f")))]
4865 "c.<fcond>.<fmt>\t%Z0%1,%2"
4866 [(set_attr "type" "fcmp")
4867 (set_attr "mode" "FPSW")])
4869 (define_insn "s<code>_<mode>"
4870 [(set (match_operand:CC 0 "register_operand" "=z")
4871 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4872 (match_operand:SCALARF 2 "register_operand" "f")))]
4874 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
4875 [(set_attr "type" "fcmp")
4876 (set_attr "mode" "FPSW")])
4879 ;; ....................
4881 ;; UNCONDITIONAL BRANCHES
4883 ;; ....................
4885 ;; Unconditional branches.
4889 (label_ref (match_operand 0 "" "")))]
4894 if (get_attr_length (insn) <= 8)
4895 return "%*b\t%l0%/";
4898 output_asm_insn (mips_output_load_label (), operands);
4899 return "%*jr\t%@%/%]";
4903 return "%*j\t%l0%/";
4905 [(set_attr "type" "jump")
4906 (set_attr "mode" "none")
4907 (set (attr "length")
4908 ;; We can't use `j' when emitting PIC. Emit a branch if it's
4909 ;; in range, otherwise load the address of the branch target into
4910 ;; $at and then jump to it.
4912 (ior (eq (symbol_ref "flag_pic") (const_int 0))
4913 (lt (abs (minus (match_dup 0)
4914 (plus (pc) (const_int 4))))
4915 (const_int 131072)))
4916 (const_int 4) (const_int 16)))])
4918 ;; We need a different insn for the mips16, because a mips16 branch
4919 ;; does not have a delay slot.
4923 (label_ref (match_operand 0 "" "")))]
4926 [(set_attr "type" "branch")
4927 (set_attr "mode" "none")
4928 (set_attr "length" "8")])
4930 (define_expand "indirect_jump"
4931 [(set (pc) (match_operand 0 "register_operand"))]
4934 operands[0] = force_reg (Pmode, operands[0]);
4935 if (Pmode == SImode)
4936 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
4938 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
4942 (define_insn "indirect_jump<mode>"
4943 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
4946 [(set_attr "type" "jump")
4947 (set_attr "mode" "none")])
4949 (define_expand "tablejump"
4951 (match_operand 0 "register_operand"))
4952 (use (label_ref (match_operand 1 "")))]
4956 operands[0] = expand_binop (Pmode, add_optab,
4957 convert_to_mode (Pmode, operands[0], false),
4958 gen_rtx_LABEL_REF (Pmode, operands[1]),
4960 else if (TARGET_GPWORD)
4961 operands[0] = expand_binop (Pmode, add_optab, operands[0],
4962 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
4963 else if (TARGET_RTP_PIC)
4965 /* When generating RTP PIC, we use case table entries that are relative
4966 to the start of the function. Add the function's address to the
4968 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
4969 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
4970 start, 0, 0, OPTAB_WIDEN);
4973 if (Pmode == SImode)
4974 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
4976 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
4980 (define_insn "tablejump<mode>"
4982 (match_operand:P 0 "register_operand" "d"))
4983 (use (label_ref (match_operand 1 "" "")))]
4986 [(set_attr "type" "jump")
4987 (set_attr "mode" "none")])
4989 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
4990 ;; While it is possible to either pull it off the stack (in the
4991 ;; o32 case) or recalculate it given t9 and our target label,
4992 ;; it takes 3 or 4 insns to do so.
4994 (define_expand "builtin_setjmp_setup"
4995 [(use (match_operand 0 "register_operand"))]
5000 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5001 emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5005 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5006 ;; that older code did recalculate the gp from $25. Continue to jump through
5007 ;; $25 for compatibility (we lose nothing by doing so).
5009 (define_expand "builtin_longjmp"
5010 [(use (match_operand 0 "register_operand"))]
5013 /* The elements of the buffer are, in order: */
5014 int W = GET_MODE_SIZE (Pmode);
5015 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5016 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5017 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5018 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5019 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5020 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5021 The target is bound to be using $28 as the global pointer
5022 but the current function might not be. */
5023 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5025 /* This bit is similar to expand_builtin_longjmp except that it
5026 restores $gp as well. */
5027 emit_move_insn (hard_frame_pointer_rtx, fp);
5028 emit_move_insn (pv, lab);
5029 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5030 emit_move_insn (gp, gpv);
5031 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5032 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5033 emit_insn (gen_rtx_USE (VOIDmode, gp));
5034 emit_indirect_jump (pv);
5039 ;; ....................
5041 ;; Function prologue/epilogue
5043 ;; ....................
5046 (define_expand "prologue"
5050 mips_expand_prologue ();
5054 ;; Block any insns from being moved before this point, since the
5055 ;; profiling call to mcount can use various registers that aren't
5056 ;; saved or used to pass arguments.
5058 (define_insn "blockage"
5059 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5062 [(set_attr "type" "unknown")
5063 (set_attr "mode" "none")
5064 (set_attr "length" "0")])
5066 (define_expand "epilogue"
5070 mips_expand_epilogue (false);
5074 (define_expand "sibcall_epilogue"
5078 mips_expand_epilogue (true);
5082 ;; Trivial return. Make it look like a normal return insn as that
5083 ;; allows jump optimizations to work better.
5085 (define_insn "return"
5087 "mips_can_use_return_insn ()"
5089 [(set_attr "type" "jump")
5090 (set_attr "mode" "none")])
5094 (define_insn "return_internal"
5096 (use (match_operand 0 "pmode_register_operand" ""))]
5099 [(set_attr "type" "jump")
5100 (set_attr "mode" "none")])
5102 ;; This is used in compiling the unwind routines.
5103 (define_expand "eh_return"
5104 [(use (match_operand 0 "general_operand"))]
5107 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
5109 if (GET_MODE (operands[0]) != gpr_mode)
5110 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
5112 emit_insn (gen_eh_set_lr_di (operands[0]));
5114 emit_insn (gen_eh_set_lr_si (operands[0]));
5119 ;; Clobber the return address on the stack. We can't expand this
5120 ;; until we know where it will be put in the stack frame.
5122 (define_insn "eh_set_lr_si"
5123 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5124 (clobber (match_scratch:SI 1 "=&d"))]
5128 (define_insn "eh_set_lr_di"
5129 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5130 (clobber (match_scratch:DI 1 "=&d"))]
5135 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5136 (clobber (match_scratch 1))]
5137 "reload_completed && !TARGET_DEBUG_D_MODE"
5140 mips_set_return_address (operands[0], operands[1]);
5144 (define_insn_and_split "exception_receiver"
5146 (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
5147 "TARGET_CALL_CLOBBERED_GP"
5149 "&& reload_completed"
5155 [(set_attr "type" "load")
5156 (set_attr "length" "12")])
5159 ;; ....................
5163 ;; ....................
5165 ;; Instructions to load a call address from the GOT. The address might
5166 ;; point to a function or to a lazy binding stub. In the latter case,
5167 ;; the stub will use the dynamic linker to resolve the function, which
5168 ;; in turn will change the GOT entry to point to the function's real
5171 ;; This means that every call, even pure and constant ones, can
5172 ;; potentially modify the GOT entry. And once a stub has been called,
5173 ;; we must not call it again.
5175 ;; We represent this restriction using an imaginary fixed register that
5176 ;; acts like a GOT version number. By making the register call-clobbered,
5177 ;; we tell the target-independent code that the address could be changed
5178 ;; by any call insn.
5179 (define_insn "load_call<mode>"
5180 [(set (match_operand:P 0 "register_operand" "=d")
5181 (unspec:P [(match_operand:P 1 "register_operand" "r")
5182 (match_operand:P 2 "immediate_operand" "")
5183 (reg:P FAKE_CALL_REGNO)]
5186 "<load>\t%0,%R2(%1)"
5187 [(set_attr "type" "load")
5188 (set_attr "mode" "<MODE>")
5189 (set_attr "length" "4")])
5191 ;; Sibling calls. All these patterns use jump instructions.
5193 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5194 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5195 ;; is defined in terms of call_insn_operand, the same is true of the
5198 ;; When we use an indirect jump, we need a register that will be
5199 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5200 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5201 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5204 (define_expand "sibcall"
5205 [(parallel [(call (match_operand 0 "")
5206 (match_operand 1 ""))
5207 (use (match_operand 2 "")) ;; next_arg_reg
5208 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5211 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5215 (define_insn "sibcall_internal"
5216 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5217 (match_operand 1 "" ""))]
5218 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5219 { return MIPS_CALL ("j", operands, 0); }
5220 [(set_attr "type" "call")])
5222 (define_expand "sibcall_value"
5223 [(parallel [(set (match_operand 0 "")
5224 (call (match_operand 1 "")
5225 (match_operand 2 "")))
5226 (use (match_operand 3 ""))])] ;; next_arg_reg
5229 mips_expand_call (operands[0], XEXP (operands[1], 0),
5230 operands[2], operands[3], true);
5234 (define_insn "sibcall_value_internal"
5235 [(set (match_operand 0 "register_operand" "")
5236 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5237 (match_operand 2 "" "")))]
5238 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5239 { return MIPS_CALL ("j", operands, 1); }
5240 [(set_attr "type" "call")])
5242 (define_insn "sibcall_value_multiple_internal"
5243 [(set (match_operand 0 "register_operand" "")
5244 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5245 (match_operand 2 "" "")))
5246 (set (match_operand 3 "register_operand" "")
5247 (call (mem:SI (match_dup 1))
5249 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5250 { return MIPS_CALL ("j", operands, 1); }
5251 [(set_attr "type" "call")])
5253 (define_expand "call"
5254 [(parallel [(call (match_operand 0 "")
5255 (match_operand 1 ""))
5256 (use (match_operand 2 "")) ;; next_arg_reg
5257 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5260 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5264 ;; This instruction directly corresponds to an assembly-language "jal".
5265 ;; There are four cases:
5268 ;; Both symbolic and register destinations are OK. The pattern
5269 ;; always expands to a single mips instruction.
5271 ;; - -mabicalls/-mno-explicit-relocs:
5272 ;; Again, both symbolic and register destinations are OK.
5273 ;; The call is treated as a multi-instruction black box.
5275 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5276 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5279 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5280 ;; Only "jal $25" is allowed. The call is actually two instructions:
5281 ;; "jalr $25" followed by an insn to reload $gp.
5283 ;; In the last case, we can generate the individual instructions with
5284 ;; a define_split. There are several things to be wary of:
5286 ;; - We can't expose the load of $gp before reload. If we did,
5287 ;; it might get removed as dead, but reload can introduce new
5288 ;; uses of $gp by rematerializing constants.
5290 ;; - We shouldn't restore $gp after calls that never return.
5291 ;; It isn't valid to insert instructions between a noreturn
5292 ;; call and the following barrier.
5294 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5295 ;; instruction preserves $gp and so have no effect on its liveness.
5296 ;; But once we generate the separate insns, it becomes obvious that
5297 ;; $gp is not live on entry to the call.
5299 ;; ??? The operands[2] = insn check is a hack to make the original insn
5300 ;; available to the splitter.
5301 (define_insn_and_split "call_internal"
5302 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5303 (match_operand 1 "" ""))
5304 (clobber (reg:SI 31))]
5306 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5307 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5310 emit_call_insn (gen_call_split (operands[0], operands[1]));
5311 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5315 [(set_attr "jal" "indirect,direct")
5316 (set_attr "extended_mips16" "no,yes")])
5318 (define_insn "call_split"
5319 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5320 (match_operand 1 "" ""))
5321 (clobber (reg:SI 31))
5322 (clobber (reg:SI 28))]
5323 "TARGET_SPLIT_CALLS"
5324 { return MIPS_CALL ("jal", operands, 0); }
5325 [(set_attr "type" "call")])
5327 (define_expand "call_value"
5328 [(parallel [(set (match_operand 0 "")
5329 (call (match_operand 1 "")
5330 (match_operand 2 "")))
5331 (use (match_operand 3 ""))])] ;; next_arg_reg
5334 mips_expand_call (operands[0], XEXP (operands[1], 0),
5335 operands[2], operands[3], false);
5339 ;; See comment for call_internal.
5340 (define_insn_and_split "call_value_internal"
5341 [(set (match_operand 0 "register_operand" "")
5342 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5343 (match_operand 2 "" "")))
5344 (clobber (reg:SI 31))]
5346 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5347 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5350 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5352 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5356 [(set_attr "jal" "indirect,direct")
5357 (set_attr "extended_mips16" "no,yes")])
5359 (define_insn "call_value_split"
5360 [(set (match_operand 0 "register_operand" "")
5361 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5362 (match_operand 2 "" "")))
5363 (clobber (reg:SI 31))
5364 (clobber (reg:SI 28))]
5365 "TARGET_SPLIT_CALLS"
5366 { return MIPS_CALL ("jal", operands, 1); }
5367 [(set_attr "type" "call")])
5369 ;; See comment for call_internal.
5370 (define_insn_and_split "call_value_multiple_internal"
5371 [(set (match_operand 0 "register_operand" "")
5372 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5373 (match_operand 2 "" "")))
5374 (set (match_operand 3 "register_operand" "")
5375 (call (mem:SI (match_dup 1))
5377 (clobber (reg:SI 31))]
5379 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5380 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5383 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5384 operands[2], operands[3]));
5385 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5389 [(set_attr "jal" "indirect,direct")
5390 (set_attr "extended_mips16" "no,yes")])
5392 (define_insn "call_value_multiple_split"
5393 [(set (match_operand 0 "register_operand" "")
5394 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5395 (match_operand 2 "" "")))
5396 (set (match_operand 3 "register_operand" "")
5397 (call (mem:SI (match_dup 1))
5399 (clobber (reg:SI 31))
5400 (clobber (reg:SI 28))]
5401 "TARGET_SPLIT_CALLS"
5402 { return MIPS_CALL ("jal", operands, 1); }
5403 [(set_attr "type" "call")])
5405 ;; Call subroutine returning any type.
5407 (define_expand "untyped_call"
5408 [(parallel [(call (match_operand 0 "")
5410 (match_operand 1 "")
5411 (match_operand 2 "")])]
5416 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5418 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5420 rtx set = XVECEXP (operands[2], 0, i);
5421 emit_move_insn (SET_DEST (set), SET_SRC (set));
5424 emit_insn (gen_blockage ());
5429 ;; ....................
5433 ;; ....................
5437 (define_insn "prefetch"
5438 [(prefetch (match_operand:QI 0 "address_operand" "p")
5439 (match_operand 1 "const_int_operand" "n")
5440 (match_operand 2 "const_int_operand" "n"))]
5441 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5443 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5444 return "pref\t%1,%a0";
5446 [(set_attr "type" "prefetch")])
5448 (define_insn "*prefetch_indexed_<mode>"
5449 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5450 (match_operand:P 1 "register_operand" "d"))
5451 (match_operand 2 "const_int_operand" "n")
5452 (match_operand 3 "const_int_operand" "n"))]
5453 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5455 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5456 return "prefx\t%2,%1(%0)";
5458 [(set_attr "type" "prefetchx")])
5464 [(set_attr "type" "nop")
5465 (set_attr "mode" "none")])
5467 ;; Like nop, but commented out when outside a .set noreorder block.
5468 (define_insn "hazard_nop"
5477 [(set_attr "type" "nop")])
5479 ;; MIPS4 Conditional move instructions.
5481 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5482 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5484 (match_operator:MOVECC 4 "equality_operator"
5485 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5487 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5488 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5493 [(set_attr "type" "condmove")
5494 (set_attr "mode" "<GPR:MODE>")])
5496 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5497 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5498 (if_then_else:SCALARF
5499 (match_operator:MOVECC 4 "equality_operator"
5500 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5502 (match_operand:SCALARF 2 "register_operand" "f,0")
5503 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5506 mov%T4.<fmt>\t%0,%2,%1
5507 mov%t4.<fmt>\t%0,%3,%1"
5508 [(set_attr "type" "condmove")
5509 (set_attr "mode" "<SCALARF:MODE>")])
5511 ;; These are the main define_expand's used to make conditional moves.
5513 (define_expand "mov<mode>cc"
5514 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5515 (set (match_operand:GPR 0 "register_operand")
5516 (if_then_else:GPR (match_dup 5)
5517 (match_operand:GPR 2 "reg_or_0_operand")
5518 (match_operand:GPR 3 "reg_or_0_operand")))]
5521 gen_conditional_move (operands);
5525 (define_expand "mov<mode>cc"
5526 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5527 (set (match_operand:SCALARF 0 "register_operand")
5528 (if_then_else:SCALARF (match_dup 5)
5529 (match_operand:SCALARF 2 "register_operand")
5530 (match_operand:SCALARF 3 "register_operand")))]
5533 gen_conditional_move (operands);
5538 ;; ....................
5540 ;; mips16 inline constant tables
5542 ;; ....................
5545 (define_insn "consttable_int"
5546 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
5547 (match_operand 1 "const_int_operand" "")]
5548 UNSPEC_CONSTTABLE_INT)]
5551 assemble_integer (operands[0], INTVAL (operands[1]),
5552 BITS_PER_UNIT * INTVAL (operands[1]), 1);
5555 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
5557 (define_insn "consttable_float"
5558 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
5559 UNSPEC_CONSTTABLE_FLOAT)]
5564 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
5565 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
5566 assemble_real (d, GET_MODE (operands[0]),
5567 GET_MODE_BITSIZE (GET_MODE (operands[0])));
5570 [(set (attr "length")
5571 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
5573 (define_insn "align"
5574 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
5577 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
5580 [(match_operand 0 "small_data_pattern")]
5583 { operands[0] = mips_rewrite_small_data (operands[0]); })
5585 ; Thread-Local Storage
5587 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
5588 ; MIPS architecture defines this register, and no current
5589 ; implementation provides it; instead, any OS which supports TLS is
5590 ; expected to trap and emulate this instruction. rdhwr is part of the
5591 ; MIPS 32r2 specification, but we use it on any architecture because
5592 ; we expect it to be emulated. Use .set to force the assembler to
5595 (define_insn "tls_get_tp_<mode>"
5596 [(set (match_operand:P 0 "register_operand" "=v")
5597 (unspec:P [(const_int 0)]
5598 UNSPEC_TLS_GET_TP))]
5599 "HAVE_AS_TLS && !TARGET_MIPS16"
5600 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
5601 [(set_attr "type" "unknown")
5602 ; Since rdhwr always generates a trap for now, putting it in a delay
5603 ; slot would make the kernel's emulation of it much slower.
5604 (set_attr "can_delay" "no")
5605 (set_attr "mode" "<MODE>")])
5607 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
5609 (include "mips-ps-3d.md")
5611 ; The MIPS DSP Instructions.
5613 (include "mips-dsp.md")
5615 ; The MIPS DSP REV 2 Instructions.
5617 (include "mips-dspr2.md")