1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
77 /* Recast the cpu class to be the cpu attribute. */
78 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
80 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
81 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
82 to work on a 64 bit machine. */
89 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
90 which is not the same as the above EABI (defined by Cygnus,
91 Greenhills, and Toshiba?). MEABI is not yet complete or published,
92 but at this point it looks like N32 as far as calling conventions go,
93 but allows for either 32 or 64 bit registers.
95 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
96 EABI the legacy EABI. In the end we may end up calling both ABI's
97 EABI but give them different version numbers, but for now I'm going
98 with different names. */
101 /* Whether to emit abicalls code sequences or not. */
103 enum mips_abicalls_type {
108 /* Recast the abicalls class to be the abicalls attribute. */
109 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
111 /* Which type of block move to do (whether or not the last store is
112 split out so it can fill a branch delay slot). */
114 enum block_move_type {
115 BLOCK_MOVE_NORMAL, /* generate complete block move */
116 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
117 BLOCK_MOVE_LAST /* generate just the last store */
120 /* Information about one recognised processor. Defined here for the
121 benefit of TARGET_CPU_CPP_BUILTINS. */
122 struct mips_cpu_info {
123 /* The 'canonical' name of the processor as far as GCC is concerned.
124 It's typically a manufacturer's prefix followed by a numerical
125 designation. It should be lower case. */
128 /* The internal processor number that most closely matches this
129 entry. Several processors can have the same value, if there's no
130 difference between them from GCC's point of view. */
131 enum processor_type cpu;
133 /* The ISA level that the processor implements. */
137 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
138 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
139 extern const char *current_function_file; /* filename current function is in */
140 extern int num_source_filenames; /* current .file # */
141 extern int inside_function; /* != 0 if inside of a function */
142 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
143 extern int file_in_function_warning; /* warning given about .file in func */
144 extern int sdb_label_count; /* block start/end next label # */
145 extern int sdb_begin_function_line; /* Starting Line of current function */
146 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
147 extern int g_switch_value; /* value of the -G xx switch */
148 extern int g_switch_set; /* whether -G xx was passed. */
149 extern int sym_lineno; /* sgi next label # for each stmt */
150 extern int set_noreorder; /* # of nested .set noreorder's */
151 extern int set_nomacro; /* # of nested .set nomacro's */
152 extern int set_noat; /* # of nested .set noat's */
153 extern int set_volatile; /* # of nested .set volatile's */
154 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
155 extern int mips_dbx_regno[]; /* Map register # to debug register # */
156 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
157 extern enum cmp_type branch_type; /* what type of branch to use */
158 extern enum processor_type mips_arch; /* which cpu to codegen for */
159 extern enum processor_type mips_tune; /* which cpu to schedule for */
160 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
161 extern int mips_isa; /* architectural level */
162 extern int mips16; /* whether generating mips16 code */
163 extern int mips16_hard_float; /* mips16 without -msoft-float */
164 extern int mips_entry; /* generate entry/exit for mips16 */
165 extern const char *mips_arch_string; /* for -march=<xxx> */
166 extern const char *mips_tune_string; /* for -mtune=<xxx> */
167 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
168 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
169 extern const char *mips_entry_string; /* for -mentry */
170 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
171 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
172 extern int mips_split_addresses; /* perform high/lo_sum support */
173 extern int dslots_load_total; /* total # load related delay slots */
174 extern int dslots_load_filled; /* # filled load delay slots */
175 extern int dslots_jump_total; /* total # jump related delay slots */
176 extern int dslots_jump_filled; /* # filled jump delay slots */
177 extern int dslots_number_nops; /* # of nops needed by previous insn */
178 extern int num_refs[3]; /* # 1/2/3 word references */
179 extern GTY(()) rtx mips_load_reg; /* register to check for load delay */
180 extern GTY(()) rtx mips_load_reg2; /* 2nd reg to check for load delay */
181 extern GTY(()) rtx mips_load_reg3; /* 3rd reg to check for load delay */
182 extern GTY(()) rtx mips_load_reg4; /* 4th reg to check for load delay */
183 extern int mips_string_length; /* length of strings for mips16 */
184 extern const struct mips_cpu_info mips_cpu_info_table[];
185 extern const struct mips_cpu_info *mips_arch_info;
186 extern const struct mips_cpu_info *mips_tune_info;
188 /* Functions to change what output section we are using. */
189 extern void sdata_section PARAMS ((void));
190 extern void sbss_section PARAMS ((void));
192 /* Macros to silence warnings about numbers being signed in traditional
193 C and unsigned in ISO C when compiled on 32-bit hosts. */
195 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
196 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
197 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
200 /* Run-time compilation parameters selecting different hardware subsets. */
202 /* Macros used in the machine description to test the flags. */
204 /* Bits for real switches */
205 #define MASK_INT64 0x00000001 /* ints are 64 bits */
206 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
207 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
208 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
209 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
210 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
211 #define MASK_STATS 0x00000040 /* print statistics to stderr */
212 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
213 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
214 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
215 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
216 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
217 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
218 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
219 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
220 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
221 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
222 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
223 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
224 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
225 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
226 #define MASK_NO_CHECK_ZERO_DIV \
227 0x00200000 /* divide by zero checking */
228 #define MASK_CHECK_RANGE_DIV \
229 0x00400000 /* divide result range checking */
230 #define MASK_UNINIT_CONST_IN_RODATA \
231 0x00800000 /* Store uninitialized
233 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
234 multiply-add operations. */
235 #define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
238 /* Debug switches, not documented */
239 #define MASK_DEBUG 0 /* unused */
240 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
241 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
242 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
243 #define MASK_DEBUG_D 0 /* don't do define_split's */
244 #define MASK_DEBUG_E 0 /* function_arg debug */
245 #define MASK_DEBUG_F 0 /* ??? */
246 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
247 #define MASK_DEBUG_I 0 /* unused */
249 /* Dummy switches used only in specs */
250 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
252 /* r4000 64 bit sizes */
253 #define TARGET_INT64 (target_flags & MASK_INT64)
254 #define TARGET_LONG64 (target_flags & MASK_LONG64)
255 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
256 #define TARGET_64BIT (target_flags & MASK_64BIT)
258 /* Mips vs. GNU linker */
259 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
261 /* Mips vs. GNU assembler */
262 #define TARGET_GAS (target_flags & MASK_GAS)
263 #define TARGET_MIPS_AS (!TARGET_GAS)
266 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
267 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
268 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
269 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
270 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
271 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
272 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
273 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
274 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
276 /* Reg. Naming in .s ($21 vs. $a0) */
277 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
279 /* Optimize for Sdata/Sbss */
280 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
282 /* print program statistics */
283 #define TARGET_STATS (target_flags & MASK_STATS)
285 /* call memcpy instead of inline code */
286 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
288 /* .abicalls, etc from Pyramid V.4 */
289 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
291 /* software floating point */
292 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
293 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
295 /* always call through a register */
296 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
298 /* generate embedded PIC code;
300 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
302 /* for embedded systems, optimize for
303 reduced RAM space instead of for
305 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
307 /* always store uninitialized const
308 variables in rodata, requires
309 TARGET_EMBEDDED_DATA. */
310 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
312 /* generate big endian code. */
313 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
315 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
316 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
318 #define TARGET_MAD (target_flags & MASK_MAD)
320 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
322 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
324 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
325 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
327 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
329 /* This is true if we must enable the assembly language file switching
332 #define TARGET_FILE_SWITCHING \
333 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
335 /* We must disable the function end stabs when doing the file switching trick,
336 because the Lscope stabs end up in the wrong place, making it impossible
337 to debug the resulting code. */
338 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
340 /* Generate mips16 code */
341 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
343 /* Generic ISA defines. */
344 #define ISA_MIPS1 (mips_isa == 1)
345 #define ISA_MIPS2 (mips_isa == 2)
346 #define ISA_MIPS3 (mips_isa == 3)
347 #define ISA_MIPS4 (mips_isa == 4)
348 #define ISA_MIPS32 (mips_isa == 32)
349 #define ISA_MIPS64 (mips_isa == 64)
351 /* Architecture target defines. */
352 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
353 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
354 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
355 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
356 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
357 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
358 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
360 /* Scheduling target defines. */
361 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
362 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
363 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
364 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
365 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
366 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
368 /* Define preprocessor macros for the -march and -mtune options.
369 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
370 processor. If INFO's canonical name is "foo", define PREFIX to
371 be "foo", and define an additional macro PREFIX_FOO. */
372 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
377 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
378 for (p = macro; *p != 0; p++) \
381 builtin_define (macro); \
382 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
387 /* Target CPU builtins. */
388 #define TARGET_CPU_CPP_BUILTINS() \
391 builtin_assert ("cpu=mips"); \
392 builtin_define ("__mips__"); \
393 builtin_define ("_mips"); \
395 /* We do this here because __mips is defined below \
396 and so we can't use builtin_define_std. */ \
398 builtin_define ("mips"); \
400 /* Treat _R3000 and _R4000 like register-size defines, \
401 which is how they've historically been used. */ \
404 builtin_define ("__mips64"); \
405 builtin_define_std ("R4000"); \
406 builtin_define ("_R4000"); \
410 builtin_define_std ("R3000"); \
411 builtin_define ("_R3000"); \
413 if (TARGET_FLOAT64) \
414 builtin_define ("__mips_fpr=64"); \
416 builtin_define ("__mips_fpr=32"); \
419 builtin_define ("__mips16"); \
421 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
422 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
426 builtin_define ("__mips=1"); \
427 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
429 else if (ISA_MIPS2) \
431 builtin_define ("__mips=2"); \
432 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
434 else if (ISA_MIPS3) \
436 builtin_define ("__mips=3"); \
437 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
439 else if (ISA_MIPS4) \
441 builtin_define ("__mips=4"); \
442 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
444 else if (ISA_MIPS32) \
446 builtin_define ("__mips=32"); \
447 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
449 else if (ISA_MIPS64) \
451 builtin_define ("__mips=64"); \
452 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
455 if (TARGET_HARD_FLOAT) \
456 builtin_define ("__mips_hard_float"); \
457 else if (TARGET_SOFT_FLOAT) \
458 builtin_define ("__mips_soft_float"); \
460 if (TARGET_SINGLE_FLOAT) \
461 builtin_define ("__mips_single_float"); \
463 if (TARGET_BIG_ENDIAN) \
465 builtin_define_std ("MIPSEB"); \
466 builtin_define ("_MIPSEB"); \
470 builtin_define_std ("MIPSEL"); \
471 builtin_define ("_MIPSEL"); \
474 /* Macros dependent on the C dialect. */ \
475 if (preprocessing_asm_p ()) \
477 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
478 builtin_define ("_LANGUAGE_ASSEMBLY"); \
480 else if (c_language == clk_c) \
482 builtin_define_std ("LANGUAGE_C"); \
483 builtin_define ("_LANGUAGE_C"); \
485 else if (c_language == clk_cplusplus) \
487 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
488 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
489 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
493 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
494 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
495 /* Bizzare, but needed at least for Irix. */ \
496 builtin_define_std ("LANGUAGE_C"); \
497 builtin_define ("_LANGUAGE_C"); \
500 if (mips_abi == ABI_EABI) \
501 builtin_define ("__mips_eabi"); \
507 /* Macro to define tables used to set the flags.
508 This is a list in braces of pairs in braces,
509 each pair being { "NAME", VALUE }
510 where VALUE is the bits to set or minus the bits to clear.
511 An empty string NAME is used to identify the default VALUE. */
513 #define TARGET_SWITCHES \
516 N_("No default crt0.o") }, \
517 {"int64", MASK_INT64 | MASK_LONG64, \
518 N_("Use 64-bit int type")}, \
519 {"long64", MASK_LONG64, \
520 N_("Use 64-bit long type")}, \
521 {"long32", -(MASK_LONG64 | MASK_INT64), \
522 N_("Use 32-bit long type")}, \
523 {"split-addresses", MASK_SPLIT_ADDR, \
524 N_("Optimize lui/addiu address loads")}, \
525 {"no-split-addresses", -MASK_SPLIT_ADDR, \
526 N_("Don't optimize lui/addiu address loads")}, \
527 {"mips-as", -MASK_GAS, \
528 N_("Use MIPS as")}, \
531 {"rnames", MASK_NAME_REGS, \
532 N_("Use symbolic register names")}, \
533 {"no-rnames", -MASK_NAME_REGS, \
534 N_("Don't use symbolic register names")}, \
535 {"gpOPT", MASK_GPOPT, \
536 N_("Use GP relative sdata/sbss sections")}, \
537 {"gpopt", MASK_GPOPT, \
538 N_("Use GP relative sdata/sbss sections")}, \
539 {"no-gpOPT", -MASK_GPOPT, \
540 N_("Don't use GP relative sdata/sbss sections")}, \
541 {"no-gpopt", -MASK_GPOPT, \
542 N_("Don't use GP relative sdata/sbss sections")}, \
543 {"stats", MASK_STATS, \
544 N_("Output compiler statistics")}, \
545 {"no-stats", -MASK_STATS, \
546 N_("Don't output compiler statistics")}, \
547 {"memcpy", MASK_MEMCPY, \
548 N_("Don't optimize block moves")}, \
549 {"no-memcpy", -MASK_MEMCPY, \
550 N_("Optimize block moves")}, \
551 {"mips-tfile", MASK_MIPS_TFILE, \
552 N_("Use mips-tfile asm postpass")}, \
553 {"no-mips-tfile", -MASK_MIPS_TFILE, \
554 N_("Don't use mips-tfile asm postpass")}, \
555 {"soft-float", MASK_SOFT_FLOAT, \
556 N_("Use software floating point")}, \
557 {"hard-float", -MASK_SOFT_FLOAT, \
558 N_("Use hardware floating point")}, \
559 {"fp64", MASK_FLOAT64, \
560 N_("Use 64-bit FP registers")}, \
561 {"fp32", -MASK_FLOAT64, \
562 N_("Use 32-bit FP registers")}, \
563 {"gp64", MASK_64BIT, \
564 N_("Use 64-bit general registers")}, \
565 {"gp32", -MASK_64BIT, \
566 N_("Use 32-bit general registers")}, \
567 {"abicalls", MASK_ABICALLS, \
568 N_("Use Irix PIC")}, \
569 {"no-abicalls", -MASK_ABICALLS, \
570 N_("Don't use Irix PIC")}, \
571 {"long-calls", MASK_LONG_CALLS, \
572 N_("Use indirect calls")}, \
573 {"no-long-calls", -MASK_LONG_CALLS, \
574 N_("Don't use indirect calls")}, \
575 {"embedded-pic", MASK_EMBEDDED_PIC, \
576 N_("Use embedded PIC")}, \
577 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
578 N_("Don't use embedded PIC")}, \
579 {"embedded-data", MASK_EMBEDDED_DATA, \
580 N_("Use ROM instead of RAM")}, \
581 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
582 N_("Don't use ROM instead of RAM")}, \
583 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
584 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
585 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
586 N_("Don't put uninitialized constants in ROM")}, \
587 {"eb", MASK_BIG_ENDIAN, \
588 N_("Use big-endian byte order")}, \
589 {"el", -MASK_BIG_ENDIAN, \
590 N_("Use little-endian byte order")}, \
591 {"single-float", MASK_SINGLE_FLOAT, \
592 N_("Use single (32-bit) FP only")}, \
593 {"double-float", -MASK_SINGLE_FLOAT, \
594 N_("Don't use single (32-bit) FP only")}, \
596 N_("Use multiply accumulate")}, \
597 {"no-mad", -MASK_MAD, \
598 N_("Don't use multiply accumulate")}, \
599 {"no-fused-madd", MASK_NO_FUSED_MADD, \
600 N_("Don't generate fused multiply/add instructions")}, \
601 {"fused-madd", -MASK_NO_FUSED_MADD, \
602 N_("Generate fused multiply/add instructions")}, \
603 {"fix4300", MASK_4300_MUL_FIX, \
604 N_("Work around early 4300 hardware bug")}, \
605 {"no-fix4300", -MASK_4300_MUL_FIX, \
606 N_("Don't work around early 4300 hardware bug")}, \
607 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
608 N_("Trap on integer divide by zero")}, \
609 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
610 N_("Don't trap on integer divide by zero")}, \
611 {"check-range-division",MASK_CHECK_RANGE_DIV, \
612 N_("Trap on integer divide overflow")}, \
613 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
614 N_("Don't trap on integer divide overflow")}, \
615 { "branch-likely", MASK_BRANCHLIKELY, \
616 N_("Use Branch Likely instructions, overriding default for arch")}, \
617 { "no-branch-likely", -MASK_BRANCHLIKELY, \
618 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
619 {"debug", MASK_DEBUG, \
621 {"debuga", MASK_DEBUG_A, \
623 {"debugb", MASK_DEBUG_B, \
625 {"debugc", MASK_DEBUG_C, \
627 {"debugd", MASK_DEBUG_D, \
629 {"debuge", MASK_DEBUG_E, \
631 {"debugf", MASK_DEBUG_F, \
633 {"debugg", MASK_DEBUG_G, \
635 {"debugi", MASK_DEBUG_I, \
637 {"", (TARGET_DEFAULT \
638 | TARGET_CPU_DEFAULT \
639 | TARGET_ENDIAN_DEFAULT), \
643 /* Default target_flags if no switches are specified */
645 #ifndef TARGET_DEFAULT
646 #define TARGET_DEFAULT 0
649 #ifndef TARGET_CPU_DEFAULT
650 #define TARGET_CPU_DEFAULT 0
653 #ifndef TARGET_ENDIAN_DEFAULT
654 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
657 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
658 #ifndef MIPS_ISA_DEFAULT
659 #ifndef MIPS_CPU_STRING_DEFAULT
660 #define MIPS_CPU_STRING_DEFAULT "from-abi"
666 /* Make this compile time constant for libgcc2 */
668 #define TARGET_64BIT 1
670 #define TARGET_64BIT 0
672 #endif /* IN_LIBGCC2 */
674 #ifndef MULTILIB_ENDIAN_DEFAULT
675 #if TARGET_ENDIAN_DEFAULT == 0
676 #define MULTILIB_ENDIAN_DEFAULT "EL"
678 #define MULTILIB_ENDIAN_DEFAULT "EB"
682 #ifndef MULTILIB_ISA_DEFAULT
683 # if MIPS_ISA_DEFAULT == 1
684 # define MULTILIB_ISA_DEFAULT "mips1"
686 # if MIPS_ISA_DEFAULT == 2
687 # define MULTILIB_ISA_DEFAULT "mips2"
689 # if MIPS_ISA_DEFAULT == 3
690 # define MULTILIB_ISA_DEFAULT "mips3"
692 # if MIPS_ISA_DEFAULT == 4
693 # define MULTILIB_ISA_DEFAULT "mips4"
695 # if MIPS_ISA_DEFAULT == 32
696 # define MULTILIB_ISA_DEFAULT "mips32"
698 # if MIPS_ISA_DEFAULT == 64
699 # define MULTILIB_ISA_DEFAULT "mips64"
701 # define MULTILIB_ISA_DEFAULT "mips1"
710 #ifndef MULTILIB_DEFAULTS
711 #define MULTILIB_DEFAULTS \
712 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
715 /* We must pass -EL to the linker by default for little endian embedded
716 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
717 linker will default to using big-endian output files. The OUTPUT_FORMAT
718 line must be in the linker script, otherwise -EB/-EL will not work. */
721 #if TARGET_ENDIAN_DEFAULT == 0
722 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
724 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
728 #define TARGET_OPTIONS \
730 SUBTARGET_TARGET_OPTIONS \
731 { "tune=", &mips_tune_string, \
732 N_("Specify CPU for scheduling purposes")}, \
733 { "arch=", &mips_arch_string, \
734 N_("Specify CPU for code generation purposes")}, \
735 { "abi=", &mips_abi_string, \
736 N_("Specify an ABI")}, \
737 { "ips", &mips_isa_string, \
738 N_("Specify a Standard MIPS ISA")}, \
739 { "entry", &mips_entry_string, \
740 N_("Use mips16 entry/exit psuedo ops")}, \
741 { "no-mips16", &mips_no_mips16_string, \
742 N_("Don't use MIPS16 instructions")}, \
743 { "no-flush-func", &mips_cache_flush_func, \
744 N_("Don't call any cache flush functions")}, \
745 { "flush-func=", &mips_cache_flush_func, \
746 N_("Specify cache flush function")}, \
749 /* This is meant to be redefined in the host dependent files. */
750 #define SUBTARGET_TARGET_OPTIONS
752 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
754 /* Generate three-operand multiply instructions for SImode. */
755 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
760 /* Generate three-operand multiply instructions for DImode. */
761 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
764 /* Macros to decide whether certain features are available or not,
765 depending on the instruction set architecture level. */
767 #define HAVE_SQRT_P() (!ISA_MIPS1)
769 /* True if the ABI can only work with 64-bit integer registers. We
770 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
771 otherwise floating-point registers must also be 64-bit. */
772 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
773 || mips_abi == ABI_O64 \
774 || mips_abi == ABI_N32)
776 /* Likewise for 32-bit regs. */
777 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
779 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
780 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
784 /* ISA has branch likely instructions (eg. mips2). */
785 /* Disable branchlikely for tx39 until compare rewrite. They haven't
786 been generated up to this point. */
787 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
789 /* ISA has the conditional move instructions introduced in mips4. */
790 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
795 /* ISA has just the integer condition move instructions (movn,movz) */
796 #define ISA_HAS_INT_CONDMOVE 0
798 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
799 branch on CC, and move (both FP and non-FP) on CC. */
800 #define ISA_HAS_8CC (ISA_MIPS4 \
804 /* This is a catch all for the other new mips4 instructions: indexed load and
805 indexed prefetch instructions, the FP madd and msub instructions,
806 and the FP recip and recip sqrt instructions */
807 #define ISA_HAS_FP4 ((ISA_MIPS4 \
811 /* ISA has conditional trap instructions. */
812 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
815 /* ISA has integer multiply-accumulate instructions, madd and msub. */
816 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
820 /* ISA has floating-point nmadd and nmsub instructions. */
821 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
825 /* ISA has count leading zeroes/ones instruction (not implemented). */
826 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
830 /* ISA has double-word count leading zeroes/ones instruction (not
832 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
835 /* ISA has data prefetch instruction. */
836 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
841 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
842 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
843 also requires TARGET_DOUBLE_FLOAT. */
844 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
846 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
847 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
848 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
849 target_flags, and -mgp64 sets MASK_64BIT.
851 Setting MASK_64BIT in target_flags will cause gcc to assume that
852 registers are 64 bits wide. int, long and void * will be 32 bit;
853 this may be changed with -mint64 or -mlong64.
855 The gen* programs link code that refers to MASK_64BIT. They don't
856 actually use the information in target_flags; they just refer to
859 /* Switch Recognition by gcc.c. Add -G xx support */
861 #undef SWITCH_TAKES_ARG
862 #define SWITCH_TAKES_ARG(CHAR) \
863 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
865 /* Sometimes certain combinations of command options do not make sense
866 on a particular target machine. You can define a macro
867 `OVERRIDE_OPTIONS' to take account of this. This macro, if
868 defined, is executed once just after all the command options have
871 On the MIPS, it is used to handle -G. We also use it to set up all
872 of the tables referenced in the other macros. */
874 #define OVERRIDE_OPTIONS override_options ()
876 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
878 /* Show we can debug even without a frame pointer. */
879 #define CAN_DEBUG_WITHOUT_FP
881 /* Tell collect what flags to pass to nm. */
883 #define NM_FLAGS "-Bn"
887 /* Assembler specs. */
889 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
892 #define MIPS_AS_ASM_SPEC "\
893 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
894 %{pipe: %e-pipe is not supported} \
895 %{K} %(subtarget_mips_as_asm_spec)"
897 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
898 rather than gas. It may be overridden by subtargets. */
900 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
901 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
904 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
907 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
912 #ifndef MIPS_ABI_DEFAULT
913 #define MIPS_ABI_DEFAULT ABI_32
916 /* Use the most portable ABI flag for the ASM specs. */
918 #if MIPS_ABI_DEFAULT == ABI_32
919 #define MULTILIB_ABI_DEFAULT "mabi=32"
920 #define ASM_ABI_DEFAULT_SPEC "-32"
923 #if MIPS_ABI_DEFAULT == ABI_O64
924 #define MULTILIB_ABI_DEFAULT "mabi=o64"
925 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
928 #if MIPS_ABI_DEFAULT == ABI_N32
929 #define MULTILIB_ABI_DEFAULT "mabi=n32"
930 #define ASM_ABI_DEFAULT_SPEC "-n32"
933 #if MIPS_ABI_DEFAULT == ABI_64
934 #define MULTILIB_ABI_DEFAULT "mabi=64"
935 #define ASM_ABI_DEFAULT_SPEC "-64"
938 #if MIPS_ABI_DEFAULT == ABI_EABI
939 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
940 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
943 #if MIPS_ABI_DEFAULT == ABI_MEABI
944 /* Most GAS don't know about MEABI. */
945 #define MULTILIB_ABI_DEFAULT "mabi=meabi"
946 #define ASM_ABI_DEFAULT_SPEC ""
949 /* Only ELF targets can switch the ABI. */
950 #ifndef OBJECT_FORMAT_ELF
951 #undef ASM_ABI_DEFAULT_SPEC
952 #define ASM_ABI_DEFAULT_SPEC ""
955 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
956 GAS_ASM_SPEC as the default, depending upon the value of
959 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
962 #define TARGET_ASM_SPEC "\
963 %{mmips-as: %(mips_as_asm_spec)} \
964 %{!mmips-as: %(gas_asm_spec)}"
968 #define TARGET_ASM_SPEC "\
969 %{!mgas: %(mips_as_asm_spec)} \
970 %{mgas: %(gas_asm_spec)}"
974 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
975 to the assembler. It may be overridden by subtargets. */
976 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
977 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
979 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
982 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
983 the assembler. It may be overridden by subtargets. */
984 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
985 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
986 %{g} %{g0} %{g1} %{g2} %{g3} \
987 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
988 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
989 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
990 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
991 %{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
994 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
995 overridden by subtargets. */
997 #ifndef SUBTARGET_ASM_SPEC
998 #define SUBTARGET_ASM_SPEC ""
1001 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1002 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1003 whether we're using GAS. These options can only be used properly
1004 with GAS, and it is better to get an error from a non-GAS assembler
1005 than to silently generate bad code. */
1009 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
1010 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1011 %(subtarget_asm_optimizing_spec) \
1012 %(subtarget_asm_debugging_spec) \
1014 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1015 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1016 %{mgp32} %{mgp64} %{march=*} \
1017 %(target_asm_spec) \
1018 %(subtarget_asm_spec)"
1020 /* Specify to run a post-processor, mips-tfile after the assembler
1021 has run to stuff the mips debug information into the object file.
1022 This is needed because the $#!%^ MIPS assembler provides no way
1023 of specifying such information in the assembly file. If we are
1024 cross compiling, disable mips-tfile unless the user specifies
1027 #ifndef ASM_FINAL_SPEC
1028 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1030 #define ASM_FINAL_SPEC "\
1031 %{mmips-as: %{!mno-mips-tfile: \
1032 \n mips-tfile %{v*: -v} \
1034 %{!K: %{save-temps: -I %b.o~}} \
1035 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1036 %{.s:%i} %{!.s:%g.s}}}"
1040 #define ASM_FINAL_SPEC "\
1041 %{!mgas: %{!mno-mips-tfile: \
1042 \n mips-tfile %{v*: -v} \
1044 %{!K: %{save-temps: -I %b.o~}} \
1045 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1046 %{.s:%i} %{!.s:%g.s}}}"
1049 #endif /* ASM_FINAL_SPEC */
1051 /* Redefinition of libraries used. Mips doesn't support normal
1052 UNIX style profiling via calling _mcount. It does offer
1053 profiling that samples the PC, so do what we can... */
1056 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1059 /* Extra switches sometimes passed to the linker. */
1060 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1061 will interpret it as a -b option. */
1064 #define LINK_SPEC "\
1066 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
1067 %{bestGnum} %{shared} %{non_shared}"
1068 #endif /* LINK_SPEC defined */
1071 /* Specs for the compiler proper */
1073 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1074 overridden by subtargets. */
1075 #ifndef SUBTARGET_CC1_SPEC
1076 #define SUBTARGET_CC1_SPEC ""
1079 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1080 /* Note, we will need to adjust the following if we ever find a MIPS variant
1081 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1082 that show up in this case. */
1086 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1087 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1089 %(subtarget_cc1_spec)"
1092 /* Preprocessor specs. */
1094 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1095 overridden by subtargets. */
1096 #ifndef SUBTARGET_CPP_SPEC
1097 #define SUBTARGET_CPP_SPEC ""
1100 #define CPP_SPEC "%(subtarget_cpp_spec)"
1102 /* This macro defines names of additional specifications to put in the specs
1103 that can be used in various specifications like CC1_SPEC. Its definition
1104 is an initializer with a subgrouping for each command option.
1106 Each subgrouping contains a string constant, that defines the
1107 specification name, and a string constant that used by the GNU CC driver
1110 Do not define this macro if it does not need to do anything. */
1112 #define EXTRA_SPECS \
1113 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1114 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1115 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1116 { "gas_asm_spec", GAS_ASM_SPEC }, \
1117 { "target_asm_spec", TARGET_ASM_SPEC }, \
1118 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1119 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1120 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1121 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1122 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1123 { "endian_spec", ENDIAN_SPEC }, \
1124 SUBTARGET_EXTRA_SPECS
1126 #ifndef SUBTARGET_EXTRA_SPECS
1127 #define SUBTARGET_EXTRA_SPECS
1130 /* If defined, this macro is an additional prefix to try after
1131 `STANDARD_EXEC_PREFIX'. */
1133 #ifndef MD_EXEC_PREFIX
1134 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1137 #ifndef MD_STARTFILE_PREFIX
1138 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1142 /* Print subsidiary information on the compiler version in use. */
1144 #define MIPS_VERSION "[AL 1.1, MM 40]"
1146 #ifndef MACHINE_TYPE
1147 #define MACHINE_TYPE "BSD Mips"
1150 #ifndef TARGET_VERSION_INTERNAL
1151 #define TARGET_VERSION_INTERNAL(STREAM) \
1152 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1155 #ifndef TARGET_VERSION
1156 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1160 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1161 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1162 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1164 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1165 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1168 /* By default, turn on GDB extensions. */
1169 #define DEFAULT_GDB_EXTENSIONS 1
1171 /* If we are passing smuggling stabs through the MIPS ECOFF object
1172 format, put a comment in front of the .stab<x> operation so
1173 that the MIPS assembler does not choke. The mips-tfile program
1174 will correctly put the stab into the object file. */
1176 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1177 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1178 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1180 /* Local compiler-generated symbols must have a prefix that the assembler
1181 understands. By default, this is $, although some targets (e.g.,
1182 NetBSD-ELF) need to override this. */
1184 #ifndef LOCAL_LABEL_PREFIX
1185 #define LOCAL_LABEL_PREFIX "$"
1188 /* By default on the mips, external symbols do not have an underscore
1189 prepended, but some targets (e.g., NetBSD) require this. */
1191 #ifndef USER_LABEL_PREFIX
1192 #define USER_LABEL_PREFIX ""
1195 /* Forward references to tags are allowed. */
1196 #define SDB_ALLOW_FORWARD_REFERENCES
1198 /* Unknown tags are also allowed. */
1199 #define SDB_ALLOW_UNKNOWN_REFERENCES
1201 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1202 since the length can run past this up to a continuation point. */
1203 #undef DBX_CONTIN_LENGTH
1204 #define DBX_CONTIN_LENGTH 1500
1206 /* How to renumber registers for dbx and gdb. */
1207 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1209 /* The mapping from gcc register number to DWARF 2 CFA column number.
1210 This mapping does not allow for tracking register 0, since SGI's broken
1211 dwarf reader thinks column 0 is used for the frame address, but since
1212 register 0 is fixed this is not a problem. */
1213 #define DWARF_FRAME_REGNUM(REG) \
1214 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1216 /* The DWARF 2 CFA column which tracks the return address. */
1217 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1219 /* Before the prologue, RA lives in r31. */
1220 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1222 /* Describe how we implement __builtin_eh_return. */
1223 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1224 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1226 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1227 The default for this in 64-bit mode is 8, which causes problems with
1228 SFmode register saves. */
1229 #define DWARF_CIE_DATA_ALIGNMENT 4
1231 /* Overrides for the COFF debug format. */
1232 #define PUT_SDB_SCL(a) \
1234 extern FILE *asm_out_text_file; \
1235 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1238 #define PUT_SDB_INT_VAL(a) \
1240 extern FILE *asm_out_text_file; \
1241 fprintf (asm_out_text_file, "\t.val\t"); \
1242 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1243 fprintf (asm_out_text_file, ";"); \
1246 #define PUT_SDB_VAL(a) \
1248 extern FILE *asm_out_text_file; \
1249 fputs ("\t.val\t", asm_out_text_file); \
1250 output_addr_const (asm_out_text_file, (a)); \
1251 fputc (';', asm_out_text_file); \
1254 #define PUT_SDB_DEF(a) \
1256 extern FILE *asm_out_text_file; \
1257 fprintf (asm_out_text_file, "\t%s.def\t", \
1258 (TARGET_GAS) ? "" : "#"); \
1259 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1260 fputc (';', asm_out_text_file); \
1263 #define PUT_SDB_PLAIN_DEF(a) \
1265 extern FILE *asm_out_text_file; \
1266 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1267 (TARGET_GAS) ? "" : "#", (a)); \
1270 #define PUT_SDB_ENDEF \
1272 extern FILE *asm_out_text_file; \
1273 fprintf (asm_out_text_file, "\t.endef\n"); \
1276 #define PUT_SDB_TYPE(a) \
1278 extern FILE *asm_out_text_file; \
1279 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1282 #define PUT_SDB_SIZE(a) \
1284 extern FILE *asm_out_text_file; \
1285 fprintf (asm_out_text_file, "\t.size\t"); \
1286 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1287 fprintf (asm_out_text_file, ";"); \
1290 #define PUT_SDB_DIM(a) \
1292 extern FILE *asm_out_text_file; \
1293 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1296 #ifndef PUT_SDB_START_DIM
1297 #define PUT_SDB_START_DIM \
1299 extern FILE *asm_out_text_file; \
1300 fprintf (asm_out_text_file, "\t.dim\t"); \
1304 #ifndef PUT_SDB_NEXT_DIM
1305 #define PUT_SDB_NEXT_DIM(a) \
1307 extern FILE *asm_out_text_file; \
1308 fprintf (asm_out_text_file, "%d,", a); \
1312 #ifndef PUT_SDB_LAST_DIM
1313 #define PUT_SDB_LAST_DIM(a) \
1315 extern FILE *asm_out_text_file; \
1316 fprintf (asm_out_text_file, "%d;", a); \
1320 #define PUT_SDB_TAG(a) \
1322 extern FILE *asm_out_text_file; \
1323 fprintf (asm_out_text_file, "\t.tag\t"); \
1324 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1325 fputc (';', asm_out_text_file); \
1328 /* For block start and end, we create labels, so that
1329 later we can figure out where the correct offset is.
1330 The normal .ent/.end serve well enough for functions,
1331 so those are just commented out. */
1333 #define PUT_SDB_BLOCK_START(LINE) \
1335 extern FILE *asm_out_text_file; \
1336 fprintf (asm_out_text_file, \
1337 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1338 LOCAL_LABEL_PREFIX, \
1340 (TARGET_GAS) ? "" : "#", \
1341 LOCAL_LABEL_PREFIX, \
1344 sdb_label_count++; \
1347 #define PUT_SDB_BLOCK_END(LINE) \
1349 extern FILE *asm_out_text_file; \
1350 fprintf (asm_out_text_file, \
1351 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1352 LOCAL_LABEL_PREFIX, \
1354 (TARGET_GAS) ? "" : "#", \
1355 LOCAL_LABEL_PREFIX, \
1358 sdb_label_count++; \
1361 #define PUT_SDB_FUNCTION_START(LINE)
1363 #define PUT_SDB_FUNCTION_END(LINE) \
1365 extern FILE *asm_out_text_file; \
1366 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1369 #define PUT_SDB_EPILOGUE_END(NAME)
1371 #define PUT_SDB_SRC_FILE(FILENAME) \
1373 extern FILE *asm_out_text_file; \
1374 output_file_directive (asm_out_text_file, (FILENAME));\
1377 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1378 sprintf ((BUFFER), ".%dfake", (NUMBER));
1380 /* Correct the offset of automatic variables and arguments. Note that
1381 the MIPS debug format wants all automatic variables and arguments
1382 to be in terms of the virtual frame pointer (stack pointer before
1383 any adjustment in the function), while the MIPS 3.0 linker wants
1384 the frame pointer to be the stack pointer after the initial
1387 #define DEBUGGER_AUTO_OFFSET(X) \
1388 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1389 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1390 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1392 /* Tell collect that the object format is ECOFF */
1393 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1394 #define EXTENDED_COFF /* ECOFF, not normal coff */
1396 /* Target machine storage layout */
1398 /* Define this if most significant bit is lowest numbered
1399 in instructions that operate on numbered bit-fields.
1401 #define BITS_BIG_ENDIAN 0
1403 /* Define this if most significant byte of a word is the lowest numbered. */
1404 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1406 /* Define this if most significant word of a multiword number is the lowest. */
1407 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1409 /* Define this to set the endianness to use in libgcc2.c, which can
1410 not depend on target_flags. */
1411 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1412 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1414 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1417 #define MAX_BITS_PER_WORD 64
1419 /* Width of a word, in units (bytes). */
1420 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1421 #define MIN_UNITS_PER_WORD 4
1423 /* For MIPS, width of a floating point register. */
1424 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1426 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1427 the next available register. */
1428 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1430 /* The largest size of value that can be held in floating-point registers. */
1431 #define UNITS_PER_FPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1433 /* The number of bytes in a double. */
1434 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1436 /* A C expression for the size in bits of the type `int' on the
1437 target machine. If you don't define this, the default is one
1439 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1441 /* Tell the preprocessor the maximum size of wchar_t. */
1442 #ifndef MAX_WCHAR_TYPE_SIZE
1443 #ifndef WCHAR_TYPE_SIZE
1444 #define MAX_WCHAR_TYPE_SIZE 64
1448 /* A C expression for the size in bits of the type `short' on the
1449 target machine. If you don't define this, the default is half a
1450 word. (If this would be less than one storage unit, it is
1451 rounded up to one unit.) */
1452 #define SHORT_TYPE_SIZE 16
1454 /* A C expression for the size in bits of the type `long' on the
1455 target machine. If you don't define this, the default is one
1457 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1458 #define MAX_LONG_TYPE_SIZE 64
1460 /* A C expression for the size in bits of the type `long long' on the
1461 target machine. If you don't define this, the default is two
1463 #define LONG_LONG_TYPE_SIZE 64
1465 /* A C expression for the size in bits of the type `float' on the
1466 target machine. If you don't define this, the default is one
1468 #define FLOAT_TYPE_SIZE 32
1470 /* A C expression for the size in bits of the type `double' on the
1471 target machine. If you don't define this, the default is two
1473 #define DOUBLE_TYPE_SIZE 64
1475 /* A C expression for the size in bits of the type `long double' on
1476 the target machine. If you don't define this, the default is two
1478 #define LONG_DOUBLE_TYPE_SIZE 64
1480 /* Width in bits of a pointer.
1481 See also the macro `Pmode' defined below. */
1482 #ifndef POINTER_SIZE
1483 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1486 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1487 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1489 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1490 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1491 || mips_abi == ABI_64 \
1492 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1494 /* Allocation boundary (in *bits*) for the code of a function. */
1495 #define FUNCTION_BOUNDARY 32
1497 /* Alignment of field after `int : 0' in a structure. */
1498 #define EMPTY_FIELD_BOUNDARY 32
1500 /* Every structure's size must be a multiple of this. */
1501 /* 8 is observed right on a DECstation and on riscos 4.02. */
1502 #define STRUCTURE_SIZE_BOUNDARY 8
1504 /* There is no point aligning anything to a rounder boundary than this. */
1505 #define BIGGEST_ALIGNMENT 64
1507 /* Set this nonzero if move instructions will actually fail to work
1508 when given unaligned data. */
1509 #define STRICT_ALIGNMENT 1
1511 /* Define this if you wish to imitate the way many other C compilers
1512 handle alignment of bitfields and the structures that contain
1515 The behavior is that the type written for a bitfield (`int',
1516 `short', or other integer type) imposes an alignment for the
1517 entire structure, as if the structure really did contain an
1518 ordinary field of that type. In addition, the bitfield is placed
1519 within the structure so that it would fit within such a field,
1520 not crossing a boundary for it.
1522 Thus, on most machines, a bitfield whose type is written as `int'
1523 would not cross a four-byte boundary, and would force four-byte
1524 alignment for the whole structure. (The alignment used may not
1525 be four bytes; it is controlled by the other alignment
1528 If the macro is defined, its definition should be a C expression;
1529 a nonzero value for the expression enables this behavior. */
1531 #define PCC_BITFIELD_TYPE_MATTERS 1
1533 /* If defined, a C expression to compute the alignment given to a
1534 constant that is being placed in memory. CONSTANT is the constant
1535 and ALIGN is the alignment that the object would ordinarily have.
1536 The value of this macro is used instead of that alignment to align
1539 If this macro is not defined, then ALIGN is used.
1541 The typical use of this macro is to increase alignment for string
1542 constants to be word aligned so that `strcpy' calls that copy
1543 constants can be done inline. */
1545 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1546 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1547 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1549 /* If defined, a C expression to compute the alignment for a static
1550 variable. TYPE is the data type, and ALIGN is the alignment that
1551 the object would ordinarily have. The value of this macro is used
1552 instead of that alignment to align the object.
1554 If this macro is not defined, then ALIGN is used.
1556 One use of this macro is to increase alignment of medium-size
1557 data to make it all fit in fewer cache lines. Another is to
1558 cause character arrays to be word-aligned so that `strcpy' calls
1559 that copy constants to character arrays can be done inline. */
1561 #undef DATA_ALIGNMENT
1562 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1563 ((((ALIGN) < BITS_PER_WORD) \
1564 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1565 || TREE_CODE (TYPE) == UNION_TYPE \
1566 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1569 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1571 #define PAD_VARARGS_DOWN (TARGET_64BIT \
1572 || mips_abi == ABI_MEABI \
1573 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1575 /* Define this macro if an argument declared as `char' or `short' in a
1576 prototype should actually be passed as an `int'. In addition to
1577 avoiding errors in certain cases of mismatch, it also makes for
1578 better code on certain machines. */
1580 #define PROMOTE_PROTOTYPES 1
1582 /* Define if operations between registers always perform the operation
1583 on the full register even if a narrower mode is specified. */
1584 #define WORD_REGISTER_OPERATIONS
1586 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1587 will either zero-extend or sign-extend. The value of this macro should
1588 be the code that says which one of the two operations is implicitly
1591 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1592 moves. All other referces are zero extended. */
1593 #define LOAD_EXTEND_OP(MODE) \
1594 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1595 ? SIGN_EXTEND : ZERO_EXTEND)
1597 /* Define this macro if it is advisable to hold scalars in registers
1598 in a wider mode than that declared by the program. In such cases,
1599 the value is constrained to be within the bounds of the declared
1600 type, but kept valid in the wider mode. The signedness of the
1601 extension may differ from that of the type.
1603 We promote any value smaller than SImode up to SImode. We don't
1604 want to promote to DImode when in 64 bit mode, because that would
1605 prevent us from using the faster SImode multiply and divide
1608 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1609 if (GET_MODE_CLASS (MODE) == MODE_INT \
1610 && GET_MODE_SIZE (MODE) < 4) \
1613 /* Define this if function arguments should also be promoted using the above
1616 #define PROMOTE_FUNCTION_ARGS
1618 /* Likewise, if the function return value is promoted. */
1620 #define PROMOTE_FUNCTION_RETURN
1622 /* Standard register usage. */
1624 /* Number of actual hardware registers.
1625 The hardware registers are assigned numbers for the compiler
1626 from 0 to just below FIRST_PSEUDO_REGISTER.
1627 All registers that the compiler knows about must be given numbers,
1628 even those that are not normally considered general registers.
1630 On the Mips, we have 32 integer registers, 32 floating point
1631 registers, 8 condition code registers, and the special registers
1632 hi, lo, hilo, and rap. Afetr that we have 32 COP0 registers, 32
1633 COP2 registers, and 32 COp3 registers. (COP1 is the floating-point
1634 processor.) The 8 condition code registers are only used if
1635 mips_isa >= 4. The hilo register is only used in 64 bit mode. It
1636 represents a 64 bit value stored as two 32 bit values in the hi and
1637 lo registers; this is the result of the mult instruction. rap is a
1638 pointer to the stack where the return address reg ($31) was stored.
1639 This is needed for C++ exception handling. */
1641 #define FIRST_PSEUDO_REGISTER 176
1643 /* 1 for registers that have pervasive standard uses
1644 and are not available for the register allocator.
1646 On the MIPS, see conventions, page D-2 */
1648 /* Regarding coprocessor registers: without evidence to the contrary,
1649 it's best to assume that each coprocessor register has a unique
1650 use. This can be overridden, in, e.g., override_options() or
1651 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1652 for a particular target. */
1654 #define FIXED_REGISTERS \
1656 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1657 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1658 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1659 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1660 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
1661 /* COP0 registers */ \
1662 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1663 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1664 /* COP2 registers */ \
1665 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1666 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1667 /* COP3 registers */ \
1668 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1669 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1673 /* 1 for registers not available across function calls.
1674 These must include the FIXED_REGISTERS and also any
1675 registers that can be used without being saved.
1676 The latter must include the registers where values are returned
1677 and the register where structure-value addresses are passed.
1678 Aside from that, you can include as many other registers as you like. */
1680 #define CALL_USED_REGISTERS \
1682 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1683 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1684 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1685 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1686 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1687 /* COP0 registers */ \
1688 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1689 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1690 /* COP2 registers */ \
1691 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1692 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1693 /* COP3 registers */ \
1694 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1695 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1698 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1699 problem which makes CALL_USED_REGISTERS *always* include
1700 all the FIXED_REGISTERS. Until this problem has been
1701 resolved this macro can be used to overcome this situation.
1702 In particular, block_propagate() requires this list
1703 be acurate, or we can remove registers which should be live.
1704 This macro is used in regs_invalidated_by_call. */
1707 #define CALL_REALLY_USED_REGISTERS \
1708 { /* General registers. */ \
1709 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1710 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
1711 /* Floating-point registers. */ \
1712 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1713 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1715 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1716 /* COP0 registers */ \
1717 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1718 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1719 /* COP2 registers */ \
1720 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1721 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1722 /* COP3 registers */ \
1723 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1724 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1727 /* Internal macros to classify a register number as to whether it's a
1728 general purpose register, a floating point register, a
1729 multiply/divide register, or a status register. */
1731 #define GP_REG_FIRST 0
1732 #define GP_REG_LAST 31
1733 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1734 #define GP_DBX_FIRST 0
1736 #define FP_REG_FIRST 32
1737 #define FP_REG_LAST 63
1738 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1739 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1741 #define MD_REG_FIRST 64
1742 #define MD_REG_LAST 66
1743 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1745 #define ST_REG_FIRST 67
1746 #define ST_REG_LAST 74
1747 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1749 #define RAP_REG_NUM 75
1751 #define COP0_REG_FIRST 80
1752 #define COP0_REG_LAST 111
1753 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1755 #define COP2_REG_FIRST 112
1756 #define COP2_REG_LAST 143
1757 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1759 #define COP3_REG_FIRST 144
1760 #define COP3_REG_LAST 175
1761 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1762 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1763 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1765 #define AT_REGNUM (GP_REG_FIRST + 1)
1766 #define HI_REGNUM (MD_REG_FIRST + 0)
1767 #define LO_REGNUM (MD_REG_FIRST + 1)
1768 #define HILO_REGNUM (MD_REG_FIRST + 2)
1770 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1771 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1772 should be used instead. */
1773 #define FPSW_REGNUM ST_REG_FIRST
1775 #define GP_REG_P(REGNO) \
1776 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1777 #define M16_REG_P(REGNO) \
1778 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1779 #define FP_REG_P(REGNO) \
1780 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1781 #define MD_REG_P(REGNO) \
1782 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1783 #define ST_REG_P(REGNO) \
1784 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1785 #define COP0_REG_P(REGNO) \
1786 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1787 #define COP2_REG_P(REGNO) \
1788 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1789 #define COP3_REG_P(REGNO) \
1790 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1791 #define ALL_COP_REG_P(REGNO) \
1792 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1794 /* Return coprocessor number from register number. */
1796 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1797 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1798 : COP3_REG_P (REGNO) ? '3' : '?')
1800 /* Return number of consecutive hard regs needed starting at reg REGNO
1801 to hold something of mode MODE.
1802 This is ordinarily the length in words of a value of mode MODE
1803 but can be less for certain modes in special long registers.
1805 On the MIPS, all general registers are one word long. Except on
1806 the R4000 with the FR bit set, the floating point uses register
1807 pairs, with the second register not being allocable. */
1809 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1811 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1812 MODE. In 32 bit mode, require that DImode and DFmode be in even
1813 registers. For DImode, this makes some of the insns easier to
1814 write, since you don't have to worry about a DImode value in
1815 registers 3 & 4, producing a result in 4 & 5.
1817 To make the code simpler HARD_REGNO_MODE_OK now just references an
1818 array built in override_options. Because machmodes.h is not yet
1819 included before this file is processed, the MODE bound can't be
1822 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1824 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1825 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1827 /* Value is 1 if it is a good idea to tie two pseudo registers
1828 when one has mode MODE1 and one has mode MODE2.
1829 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1830 for any hard reg, then this must be 0 for correct output. */
1831 #define MODES_TIEABLE_P(MODE1, MODE2) \
1832 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1833 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1834 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1835 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1837 /* MIPS pc is not overloaded on a register. */
1838 /* #define PC_REGNUM xx */
1840 /* Register to use for pushing function arguments. */
1841 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1843 /* Offset from the stack pointer to the first available location. Use
1844 the default value zero. */
1845 /* #define STACK_POINTER_OFFSET 0 */
1847 /* Base register for access to local variables of the function. We
1848 pretend that the frame pointer is $1, and then eliminate it to
1849 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1850 a fixed register, and will not be used for anything else. */
1851 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1853 /* Temporary scratch register for use by the assembler. */
1854 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1856 /* $30 is not available on the mips16, so we use $17 as the frame
1858 #define HARD_FRAME_POINTER_REGNUM \
1859 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1861 /* Value should be nonzero if functions must have frame pointers.
1862 Zero means the frame pointer need not be set up (and parms
1863 may be accessed via the stack pointer) in functions that seem suitable.
1864 This is computed in `reload', in reload1.c. */
1865 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1867 /* Base register for access to arguments of the function. */
1868 #define ARG_POINTER_REGNUM GP_REG_FIRST
1870 /* Fake register that holds the address on the stack of the
1871 current function's return address. */
1872 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1874 /* Register in which static-chain is passed to a function. */
1875 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1877 /* If the structure value address is passed in a register, then
1878 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1879 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1881 /* If the structure value address is not passed in a register, define
1882 `STRUCT_VALUE' as an expression returning an RTX for the place
1883 where the address is passed. If it returns 0, the address is
1884 passed as an "invisible" first argument. */
1885 #define STRUCT_VALUE 0
1887 /* Mips registers used in prologue/epilogue code when the stack frame
1888 is larger than 32K bytes. These registers must come from the
1889 scratch register set, and not used for passing and returning
1890 arguments and any other information used in the calling sequence
1891 (such as pic). Must start at 12, since t0/t3 are parameter passing
1892 registers in the 64 bit ABI. */
1894 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1895 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1897 /* Define this macro if it is as good or better to call a constant
1898 function address than to call an address kept in a register. */
1899 #define NO_FUNCTION_CSE 1
1901 /* Define this macro if it is as good or better for a function to
1902 call itself with an explicit address than to call an address
1903 kept in a register. */
1904 #define NO_RECURSIVE_FUNCTION_CSE 1
1906 /* The register number of the register used to address a table of
1907 static data addresses in memory. In some cases this register is
1908 defined by a processor's "application binary interface" (ABI).
1909 When this macro is defined, RTL is generated for this register
1910 once, as with the stack pointer and frame pointer registers. If
1911 this macro is not defined, it is up to the machine-dependent
1912 files to allocate such a register (if necessary). */
1913 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1915 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1917 /* Define the classes of registers for register constraints in the
1918 machine description. Also define ranges of constants.
1920 One of the classes must always be named ALL_REGS and include all hard regs.
1921 If there is more than one class, another class must be named NO_REGS
1922 and contain no registers.
1924 The name GENERAL_REGS must be the name of a class (or an alias for
1925 another name such as ALL_REGS). This is the class of registers
1926 that is allowed by "g" or "r" in a register constraint.
1927 Also, registers outside this class are allocated only when
1928 instructions express preferences for them.
1930 The classes must be numbered in nondecreasing order; that is,
1931 a larger-numbered class must never be contained completely
1932 in a smaller-numbered class.
1934 For any two classes, it is very desirable that there be another
1935 class that represents their union. */
1939 NO_REGS, /* no registers in set */
1940 M16_NA_REGS, /* mips16 regs not used to pass args */
1941 M16_REGS, /* mips16 directly accessible registers */
1942 T_REG, /* mips16 T register ($24) */
1943 M16_T_REGS, /* mips16 registers plus T register */
1944 GR_REGS, /* integer registers */
1945 FP_REGS, /* floating point registers */
1946 HI_REG, /* hi register */
1947 LO_REG, /* lo register */
1948 HILO_REG, /* hilo register pair for 64 bit mode mult */
1949 MD_REGS, /* multiply/divide registers (hi/lo) */
1950 COP0_REGS, /* generic coprocessor classes */
1953 HI_AND_GR_REGS, /* union classes */
1961 ALL_COP_AND_GR_REGS,
1962 ST_REGS, /* status registers (fp status) */
1963 ALL_REGS, /* all registers */
1964 LIM_REG_CLASSES /* max value + 1 */
1967 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1969 #define GENERAL_REGS GR_REGS
1971 /* An initializer containing the names of the register classes as C
1972 string constants. These names are used in writing some of the
1975 #define REG_CLASS_NAMES \
1988 /* coprocessor registers */ \
1994 "HILO_AND_GR_REGS", \
1996 "COP0_AND_GR_REGS", \
1997 "COP2_AND_GR_REGS", \
1998 "COP3_AND_GR_REGS", \
2000 "ALL_COP_AND_GR_REGS", \
2005 /* An initializer containing the contents of the register classes,
2006 as integers which are bit masks. The Nth integer specifies the
2007 contents of class N. The way the integer MASK is interpreted is
2008 that register R is in the class if `MASK & (1 << R)' is 1.
2010 When the machine has more than 32 registers, an integer does not
2011 suffice. Then the integers are replaced by sub-initializers,
2012 braced groupings containing several integers. Each
2013 sub-initializer must be suitable as an initializer for the type
2014 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2016 #define REG_CLASS_CONTENTS \
2018 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2019 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2020 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2021 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2022 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2023 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2024 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2025 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2026 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2027 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* hilo register */ \
2028 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2029 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2030 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2031 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2032 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2033 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2034 { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
2035 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2036 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2037 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2038 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2039 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2040 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2041 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2042 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2046 /* A C expression whose value is a register class containing hard
2047 register REGNO. In general there is more that one such class;
2048 choose a class which is "minimal", meaning that no smaller class
2049 also contains the register. */
2051 extern const enum reg_class mips_regno_to_class[];
2053 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2055 /* A macro whose definition is the name of the class to which a
2056 valid base register must belong. A base register is one used in
2057 an address which is the register value plus a displacement. */
2059 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2061 /* A macro whose definition is the name of the class to which a
2062 valid index register must belong. An index register is one used
2063 in an address where its value is either multiplied by a scale
2064 factor or added to another register (as well as added to a
2067 #define INDEX_REG_CLASS NO_REGS
2069 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2070 registers explicitly used in the rtl to be used as spill registers
2071 but prevents the compiler from extending the lifetime of these
2074 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2076 /* This macro is used later on in the file. */
2077 #define GR_REG_CLASS_P(CLASS) \
2078 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2079 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2081 /* This macro is also used later on in the file. */
2082 #define COP_REG_CLASS_P(CLASS) \
2083 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2085 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2086 is the default value (allocate the registers in numeric order). We
2087 define it just so that we can override it for the mips16 target in
2088 ORDER_REGS_FOR_LOCAL_ALLOC. */
2090 #define REG_ALLOC_ORDER \
2091 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2092 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2093 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2094 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2095 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2096 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2097 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2098 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2099 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2100 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2101 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2104 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2105 to be rearranged based on a particular function. On the mips16, we
2106 want to allocate $24 (T_REG) before other registers for
2107 instructions for which it is possible. */
2109 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2111 /* REGISTER AND CONSTANT CLASSES */
2113 /* Get reg_class from a letter such as appears in the machine
2116 DEFINED REGISTER CLASSES:
2118 'd' General (aka integer) registers
2119 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2120 'y' General registers (in both mips16 and non mips16 mode)
2121 'e' mips16 non argument registers (M16_NA_REGS)
2122 't' mips16 temporary register ($24)
2123 'f' Floating point registers
2126 'x' Multiply/divide registers
2128 'z' FP Status register
2132 'b' All registers */
2134 extern enum reg_class mips_char_to_class[256];
2136 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2138 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2139 string can be used to stand for particular ranges of immediate
2140 operands. This macro defines what the ranges are. C is the
2141 letter, and VALUE is a constant value. Return 1 if VALUE is
2142 in the range specified by C. */
2146 `I' is used for the range of constants an arithmetic insn can
2147 actually contain (16 bits signed integers).
2149 `J' is used for the range which is just zero (ie, $r0).
2151 `K' is used for the range of constants a logical insn can actually
2152 contain (16 bit zero-extended integers).
2154 `L' is used for the range of constants that be loaded with lui
2155 (ie, the bottom 16 bits are zero).
2157 `M' is used for the range of constants that take two words to load
2158 (ie, not matched by `I', `K', and `L').
2160 `N' is used for negative 16 bit constants other than -65536.
2162 `O' is a 15 bit signed integer.
2164 `P' is used for positive 16 bit constants. */
2166 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2167 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2169 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2170 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
2171 : (C) == 'J' ? ((VALUE) == 0) \
2172 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
2173 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2174 && (((VALUE) & ~2147483647) == 0 \
2175 || ((VALUE) & ~2147483647) == ~2147483647)) \
2176 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2177 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2178 && (((VALUE) & 0x0000ffff) != 0 \
2179 || (((VALUE) & ~2147483647) != 0 \
2180 && ((VALUE) & ~2147483647) != ~2147483647))) \
2181 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2182 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2183 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2186 /* Similar, but for floating constants, and defining letters G and H.
2187 Here VALUE is the CONST_DOUBLE rtx itself. */
2191 'G' : Floating point 0 */
2193 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2195 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2197 /* Letters in the range `Q' through `U' may be defined in a
2198 machine-dependent fashion to stand for arbitrary operand types.
2199 The machine description macro `EXTRA_CONSTRAINT' is passed the
2200 operand as its first argument and the constraint letter as its
2203 `Q' is for mips16 GP relative constants
2204 `R' is for memory references which take 1 word for the instruction.
2205 `T' is for memory addresses that can be used to load two words. */
2207 #define EXTRA_CONSTRAINT(OP,CODE) \
2208 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2209 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2210 && mips16_gp_offset_p (OP)) \
2211 : (GET_CODE (OP) != MEM) ? FALSE \
2212 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2215 /* Given an rtx X being reloaded into a reg required to be
2216 in class CLASS, return the class of reg to actually use.
2217 In general this is just CLASS; but on some machines
2218 in some cases it is preferable to use a more restrictive class. */
2220 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2221 ((CLASS) != ALL_REGS \
2222 ? (! TARGET_MIPS16 \
2224 : ((CLASS) != GR_REGS \
2227 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2228 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2229 ? (TARGET_SOFT_FLOAT \
2230 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2232 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2233 || GET_MODE (X) == VOIDmode) \
2234 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2237 /* Certain machines have the property that some registers cannot be
2238 copied to some other registers without using memory. Define this
2239 macro on those machines to be a C expression that is non-zero if
2240 objects of mode MODE in registers of CLASS1 can only be copied to
2241 registers of class CLASS2 by storing a register of CLASS1 into
2242 memory and loading that memory location into a register of CLASS2.
2244 Do not define this macro if its value would always be zero. */
2246 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2247 ((!TARGET_DEBUG_H_MODE \
2248 && GET_MODE_CLASS (MODE) == MODE_INT \
2249 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2250 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2251 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2252 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2253 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2255 /* The HI and LO registers can only be reloaded via the general
2256 registers. Condition code registers can only be loaded to the
2257 general registers, and from the floating point registers. */
2259 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2260 mips_secondary_reload_class (CLASS, MODE, X, 1)
2261 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2262 mips_secondary_reload_class (CLASS, MODE, X, 0)
2264 /* Return the maximum number of consecutive registers
2265 needed to represent mode MODE in a register of class CLASS. */
2267 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2269 /* If defined, gives a class of registers that cannot be used as the
2270 operand of a SUBREG that changes the mode of the object illegally.
2272 In little-endian mode, the hi-lo registers are numbered backwards,
2273 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
2276 Similarly, when using paired floating-point registers, the first
2277 register holds the low word, regardless of endianness. So in big
2278 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
2281 Also, loading a 32-bit value into a 64-bit floating-point register
2282 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
2283 We can't allow 64-bit float registers to change from a 32-bit
2284 mode to a 64-bit mode. */
2286 #define CLASS_CANNOT_CHANGE_MODE \
2287 (TARGET_BIG_ENDIAN ? FP_REGS \
2288 : (TARGET_FLOAT64 ? HI_AND_FP_REGS : HI_REG))
2290 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2292 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2293 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2295 /* Stack layout; function entry, exit and calling. */
2297 /* Define this if pushing a word on the stack
2298 makes the stack pointer a smaller address. */
2299 #define STACK_GROWS_DOWNWARD
2301 /* Define this if the nominal address of the stack frame
2302 is at the high-address end of the local variables;
2303 that is, each additional local variable allocated
2304 goes at a more negative offset in the frame. */
2305 /* #define FRAME_GROWS_DOWNWARD */
2307 /* Offset within stack frame to start allocating local variables at.
2308 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2309 first local allocated. Otherwise, it is the offset to the BEGINNING
2310 of the first local allocated. */
2311 #define STARTING_FRAME_OFFSET \
2312 (current_function_outgoing_args_size \
2313 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2315 /* Offset from the stack pointer register to an item dynamically
2316 allocated on the stack, e.g., by `alloca'.
2318 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2319 length of the outgoing arguments. The default is correct for most
2320 machines. See `function.c' for details.
2322 The MIPS ABI states that functions which dynamically allocate the
2323 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2324 we are trying to create a second frame pointer to the function, so
2325 allocate some stack space to make it happy.
2327 However, the linker currently complains about linking any code that
2328 dynamically allocates stack space, and there seems to be a bug in
2329 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2332 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2333 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2334 ? 4*UNITS_PER_WORD \
2335 : current_function_outgoing_args_size)
2338 /* The return address for the current frame is in r31 if this is a leaf
2339 function. Otherwise, it is on the stack. It is at a variable offset
2340 from sp/fp/ap, so we define a fake hard register rap which is a
2341 poiner to the return address on the stack. This always gets eliminated
2342 during reload to be either the frame pointer or the stack pointer plus
2345 /* ??? This definition fails for leaf functions. There is currently no
2346 general solution for this problem. */
2348 /* ??? There appears to be no way to get the return address of any previous
2349 frame except by disassembling instructions in the prologue/epilogue.
2350 So currently we support only the current frame. */
2352 #define RETURN_ADDR_RTX(count, frame) \
2354 ? (leaf_function_p () \
2355 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
2356 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
2357 RETURN_ADDRESS_POINTER_REGNUM))) \
2360 /* Since the mips16 ISA mode is encoded in the least-significant bit
2361 of the address, mask it off return addresses for purposes of
2362 finding exception handling regions. */
2364 #define MASK_RETURN_ADDR GEN_INT (-2)
2366 /* Similarly, don't use the least-significant bit to tell pointers to
2367 code from vtable index. */
2369 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2371 /* If defined, this macro specifies a table of register pairs used to
2372 eliminate unneeded registers that point into the stack frame. If
2373 it is not defined, the only elimination attempted by the compiler
2374 is to replace references to the frame pointer with references to
2377 The definition of this macro is a list of structure
2378 initializations, each of which specifies an original and
2379 replacement register.
2381 On some machines, the position of the argument pointer is not
2382 known until the compilation is completed. In such a case, a
2383 separate hard register must be used for the argument pointer.
2384 This register can be eliminated by replacing it with either the
2385 frame pointer or the argument pointer, depending on whether or not
2386 the frame pointer has been eliminated.
2388 In this case, you might specify:
2389 #define ELIMINABLE_REGS \
2390 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2391 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2392 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2394 Note that the elimination of the argument pointer with the stack
2395 pointer is specified first since that is the preferred elimination.
2397 The eliminations to $17 are only used on the mips16. See the
2398 definition of HARD_FRAME_POINTER_REGNUM. */
2400 #define ELIMINABLE_REGS \
2401 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2402 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2403 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2404 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2405 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2406 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2407 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2408 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2409 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2411 /* A C expression that returns non-zero if the compiler is allowed to
2412 try to replace register number FROM-REG with register number
2413 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2414 defined, and will usually be the constant 1, since most of the
2415 cases preventing register elimination are things that the compiler
2416 already knows about.
2418 When not in mips16 and mips64, we can always eliminate to the
2419 frame pointer. We can eliminate to the stack pointer unless
2420 a frame pointer is needed. In mips16 mode, we need a frame
2421 pointer for a large frame; otherwise, reload may be unable
2422 to compute the address of a local variable, since there is
2423 no way to add a large constant to the stack pointer
2424 without using a temporary register.
2426 In mips16, for some instructions (eg lwu), we can't eliminate the
2427 frame pointer for the stack pointer. These instructions are
2428 only generated in TARGET_64BIT mode.
2431 #define CAN_ELIMINATE(FROM, TO) \
2432 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
2433 && (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed) \
2434 || (TO) == HARD_FRAME_POINTER_REGNUM)) \
2435 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2436 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2437 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2438 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2439 && (! TARGET_MIPS16 \
2440 || compute_frame_size (get_frame_size ()) < 32768)))))
2442 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2443 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2445 /* If we generate an insn to push BYTES bytes,
2446 this says how many the stack pointer really advances by.
2447 On the VAX, sp@- in a byte insn really pushes a word. */
2449 /* #define PUSH_ROUNDING(BYTES) 0 */
2451 /* If defined, the maximum amount of space required for outgoing
2452 arguments will be computed and placed into the variable
2453 `current_function_outgoing_args_size'. No space will be pushed
2454 onto the stack for each call; instead, the function prologue
2455 should increase the stack frame size by this amount.
2457 It is not proper to define both `PUSH_ROUNDING' and
2458 `ACCUMULATE_OUTGOING_ARGS'. */
2459 #define ACCUMULATE_OUTGOING_ARGS 1
2461 /* Offset from the argument pointer register to the first argument's
2462 address. On some machines it may depend on the data type of the
2465 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2466 the first argument's address.
2468 On the MIPS, we must skip the first argument position if we are
2469 returning a structure or a union, to account for its address being
2470 passed in $4. However, at the current time, this produces a compiler
2471 that can't bootstrap, so comment it out for now. */
2474 #define FIRST_PARM_OFFSET(FNDECL) \
2476 && TREE_TYPE (FNDECL) != 0 \
2477 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2478 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2479 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2483 #define FIRST_PARM_OFFSET(FNDECL) 0
2486 /* When a parameter is passed in a register, stack space is still
2487 allocated for it. For the MIPS, stack space must be allocated, cf
2488 Asm Lang Prog Guide page 7-8.
2490 BEWARE that some space is also allocated for non existing arguments
2491 in register. In case an argument list is of form GF used registers
2492 are a0 (a2,a3), but we should push over a1... */
2494 #define REG_PARM_STACK_SPACE(FNDECL) \
2495 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2496 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2499 /* Define this if it is the responsibility of the caller to
2500 allocate the area reserved for arguments passed in registers.
2501 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2502 of this macro is to determine whether the space is included in
2503 `current_function_outgoing_args_size'. */
2504 #define OUTGOING_REG_PARM_STACK_SPACE
2506 #define STACK_BOUNDARY \
2507 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2510 /* Make sure 4 words are always allocated on the stack. */
2512 #ifndef STACK_ARGS_ADJUST
2513 #define STACK_ARGS_ADJUST(SIZE) \
2515 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2516 SIZE.constant = 4 * UNITS_PER_WORD; \
2521 /* A C expression that should indicate the number of bytes of its
2522 own arguments that a function pops on returning, or 0
2523 if the function pops no arguments and the caller must therefore
2524 pop them all after the function returns.
2526 FUNDECL is the declaration node of the function (as a tree).
2528 FUNTYPE is a C variable whose value is a tree node that
2529 describes the function in question. Normally it is a node of
2530 type `FUNCTION_TYPE' that describes the data type of the function.
2531 From this it is possible to obtain the data types of the value
2532 and arguments (if known).
2534 When a call to a library function is being considered, FUNTYPE
2535 will contain an identifier node for the library function. Thus,
2536 if you need to distinguish among various library functions, you
2537 can do so by their names. Note that "library function" in this
2538 context means a function used to perform arithmetic, whose name
2539 is known specially in the compiler and was not mentioned in the
2540 C code being compiled.
2542 STACK-SIZE is the number of bytes of arguments passed on the
2543 stack. If a variable number of bytes is passed, it is zero, and
2544 argument popping will always be the responsibility of the
2545 calling function. */
2547 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2550 /* Symbolic macros for the registers used to return integer and floating
2553 #define GP_RETURN (GP_REG_FIRST + 2)
2554 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2556 #define MAX_ARGS_IN_REGISTERS \
2557 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2559 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2561 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2563 /* Symbolic macros for the first/last argument registers. */
2565 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2566 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2567 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2568 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2570 /* Define how to find the value returned by a library function
2571 assuming the value has mode MODE. Because we define
2572 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2573 PROMOTE_MODE does. */
2575 #define LIBCALL_VALUE(MODE) \
2576 mips_function_value (NULL_TREE, NULL, (MODE))
2578 /* Define how to find the value returned by a function.
2579 VALTYPE is the data type of the value (as a tree).
2580 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2581 otherwise, FUNC is 0. */
2583 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2584 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2586 /* 1 if N is a possible register number for a function value.
2587 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2588 Currently, R2 and F0 are only implemented here (C has no complex type) */
2590 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2592 /* 1 if N is a possible register number for function argument passing.
2593 We have no FP argument registers when soft-float. When FP registers
2594 are 32 bits, we can't directly reference the odd numbered ones. */
2596 #define FUNCTION_ARG_REGNO_P(N) \
2597 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2598 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2599 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2602 /* A C expression which can inhibit the returning of certain function
2603 values in registers, based on the type of value. A nonzero value says
2604 to return the function value in memory, just as large structures are
2605 always returned. Here TYPE will be a C expression of type
2606 `tree', representing the data type of the value.
2608 Note that values of mode `BLKmode' must be explicitly
2609 handled by this macro. Also, the option `-fpcc-struct-return'
2610 takes effect regardless of this macro. On most systems, it is
2611 possible to leave the macro undefined; this causes a default
2612 definition to be used, whose value is the constant 1 for BLKmode
2613 values, and 0 otherwise.
2615 GCC normally converts 1 byte structures into chars, 2 byte
2616 structs into shorts, and 4 byte structs into ints, and returns
2617 them this way. Defining the following macro overrides this,
2618 to give us MIPS cc compatibility. */
2620 #define RETURN_IN_MEMORY(TYPE) \
2621 mips_return_in_memory (TYPE)
2623 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2624 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2628 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2631 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2633 /* Define a data type for recording info about an argument list
2634 during the scan of that argument list. This data type should
2635 hold all necessary information about the function itself
2636 and about the args processed so far, enough to enable macros
2637 such as FUNCTION_ARG to determine where the next arg should go.
2639 This structure has to cope with two different argument allocation
2640 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2641 first N words go in registers and the rest go on the stack. If I < N,
2642 the Ith word might go in Ith integer argument register or the
2643 Ith floating-point one. In some cases, it has to go in both (see
2644 function_arg). For these ABIs, we only need to remember the number
2645 of words passed so far.
2647 The EABI instead allocates the integer and floating-point arguments
2648 separately. The first N words of FP arguments go in FP registers,
2649 the rest go on the stack. Likewise, the first N words of the other
2650 arguments go in integer registers, and the rest go on the stack. We
2651 need to maintain three counts: the number of integer registers used,
2652 the number of floating-point registers used, and the number of words
2653 passed on the stack.
2655 We could keep separate information for the two ABIs (a word count for
2656 the standard ABIs, and three separate counts for the EABI). But it
2657 seems simpler to view the standard ABIs as forms of EABI that do not
2658 allocate floating-point registers.
2660 So for the standard ABIs, the first N words are allocated to integer
2661 registers, and function_arg decides on an argument-by-argument basis
2662 whether that argument should really go in an integer register, or in
2663 a floating-point one. */
2665 typedef struct mips_args {
2666 /* Always true for varargs functions. Otherwise true if at least
2667 one argument has been passed in an integer register. */
2670 /* The number of arguments seen so far. */
2671 unsigned int arg_number;
2673 /* For EABI, the number of integer registers used so far. For other
2674 ABIs, the number of words passed in registers (whether integer
2675 or floating-point). */
2676 unsigned int num_gprs;
2678 /* For EABI, the number of floating-point registers used so far. */
2679 unsigned int num_fprs;
2681 /* The number of words passed on the stack. */
2682 unsigned int stack_words;
2684 /* On the mips16, we need to keep track of which floating point
2685 arguments were passed in general registers, but would have been
2686 passed in the FP regs if this were a 32 bit function, so that we
2687 can move them to the FP regs if we wind up calling a 32 bit
2688 function. We record this information in fp_code, encoded in base
2689 four. A zero digit means no floating point argument, a one digit
2690 means an SFmode argument, and a two digit means a DFmode argument,
2691 and a three digit is not used. The low order digit is the first
2692 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2693 an SFmode argument. ??? A more sophisticated approach will be
2694 needed if MIPS_ABI != ABI_32. */
2697 /* True if the function has a prototype. */
2700 /* When a structure does not take up a full register, the argument
2701 should sometimes be shifted left so that it occupies the high part
2702 of the register. These two fields describe an array of ashl
2703 patterns for doing this. See function_arg_advance, which creates
2704 the shift patterns, and function_arg, which returns them when given
2705 a VOIDmode argument. */
2706 unsigned int num_adjusts;
2707 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2710 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2711 for a call to a function whose data type is FNTYPE.
2712 For a library call, FNTYPE is 0.
2716 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2717 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2719 /* Update the data in CUM to advance over an argument
2720 of mode MODE and data type TYPE.
2721 (TYPE is null for libcalls where that information may not be available.) */
2723 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2724 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2726 /* Determine where to put an argument to a function.
2727 Value is zero to push the argument on the stack,
2728 or a hard register in which to store the argument.
2730 MODE is the argument's machine mode.
2731 TYPE is the data type of the argument (as a tree).
2732 This is null for libcalls where that information may
2734 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2735 the preceding args and about the function being called.
2736 NAMED is nonzero if this argument is a named parameter
2737 (otherwise it is an extra parameter matching an ellipsis). */
2739 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2740 function_arg( &CUM, MODE, TYPE, NAMED)
2742 /* For an arg passed partly in registers and partly in memory,
2743 this is the number of registers used.
2744 For args passed entirely in registers or entirely in memory, zero. */
2746 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2747 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2749 /* If defined, a C expression that gives the alignment boundary, in
2750 bits, of an argument with the specified mode and type. If it is
2751 not defined, `PARM_BOUNDARY' is used for all arguments. */
2753 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2755 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2757 : TYPE_ALIGN(TYPE)) \
2758 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2760 : GET_MODE_ALIGNMENT(MODE)))
2762 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2763 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2765 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2766 (! BYTES_BIG_ENDIAN \
2768 : (((MODE) == BLKmode \
2769 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2770 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2771 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2772 && (mips_abi == ABI_32 \
2773 || mips_abi == ABI_O64 \
2774 || mips_abi == ABI_EABI \
2775 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2776 ? downward : upward))
2778 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2779 (mips_abi == ABI_EABI && (NAMED) \
2780 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2782 /* Modified version of the macro in expr.h. */
2783 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2785 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2786 || TREE_ADDRESSABLE (TYPE) \
2787 || ((MODE) == BLKmode \
2788 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2789 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2790 && 0 == (int_size_in_bytes (TYPE) \
2791 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2792 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2793 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2795 /* True if using EABI and varargs can be passed in floating-point
2796 registers. Under these conditions, we need a more complex form
2797 of va_list, which tracks GPR, FPR and stack arguments separately. */
2798 #define EABI_FLOAT_VARARGS_P \
2799 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2802 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2804 #define MUST_SAVE_REGISTER(regno) \
2805 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2806 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2807 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2809 /* Treat LOC as a byte offset from the stack pointer and round it up
2810 to the next fully-aligned offset. */
2811 #define MIPS_STACK_ALIGN(LOC) \
2812 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2813 ? ((LOC) + 7) & ~7 \
2814 : ((LOC) + 15) & ~15)
2817 /* Define the `__builtin_va_list' type for the ABI. */
2818 #define BUILD_VA_LIST_TYPE(VALIST) \
2819 (VALIST) = mips_build_va_list ()
2821 /* Implement `va_start' for varargs and stdarg. */
2822 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2823 mips_va_start (valist, nextarg)
2825 /* Implement `va_arg'. */
2826 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2827 mips_va_arg (valist, type)
2829 /* Output assembler code to FILE to increment profiler label # LABELNO
2830 for profiling a function entry. */
2832 #define FUNCTION_PROFILER(FILE, LABELNO) \
2834 if (TARGET_MIPS16) \
2835 sorry ("mips16 function profiling"); \
2836 fprintf (FILE, "\t.set\tnoat\n"); \
2837 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2838 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2840 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2841 TARGET_64BIT ? "dsubu" : "subu", \
2842 reg_names[STACK_POINTER_REGNUM], \
2843 reg_names[STACK_POINTER_REGNUM], \
2844 Pmode == DImode ? 16 : 8); \
2845 fprintf (FILE, "\tjal\t_mcount\n"); \
2846 fprintf (FILE, "\t.set\tat\n"); \
2849 /* Define this macro if the code for function profiling should come
2850 before the function prologue. Normally, the profiling code comes
2853 /* #define PROFILE_BEFORE_PROLOGUE */
2855 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2856 the stack pointer does not matter. The value is tested only in
2857 functions that have frame pointers.
2858 No definition is equivalent to always zero. */
2860 #define EXIT_IGNORE_STACK 1
2863 /* A C statement to output, on the stream FILE, assembler code for a
2864 block of data that contains the constant parts of a trampoline.
2865 This code should not include a label--the label is taken care of
2868 #define TRAMPOLINE_TEMPLATE(STREAM) \
2870 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2871 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2872 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2873 if (Pmode == DImode) \
2875 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2876 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2880 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2881 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2883 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2884 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2885 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2886 if (Pmode == DImode) \
2888 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2889 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2893 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2894 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2898 /* A C expression for the size in bytes of the trampoline, as an
2901 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2903 /* Alignment required for trampolines, in bits. */
2905 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2907 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2908 program and data caches. */
2910 #ifndef CACHE_FLUSH_FUNC
2911 #define CACHE_FLUSH_FUNC "_flush_cache"
2914 /* A C statement to initialize the variable parts of a trampoline.
2915 ADDR is an RTX for the address of the trampoline; FNADDR is an
2916 RTX for the address of the nested function; STATIC_CHAIN is an
2917 RTX for the static chain value that should be passed to the
2918 function when it is called. */
2920 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2923 if (Pmode == DImode) \
2925 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2926 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2930 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2931 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2934 /* Flush both caches. We need to flush the data cache in case \
2935 the system has a write-back cache. */ \
2936 /* ??? Should check the return value for errors. */ \
2937 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2938 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2939 0, VOIDmode, 3, addr, Pmode, \
2940 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2941 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2944 /* Addressing modes, and classification of registers for them. */
2946 /* #define HAVE_POST_INCREMENT 0 */
2947 /* #define HAVE_POST_DECREMENT 0 */
2949 /* #define HAVE_PRE_DECREMENT 0 */
2950 /* #define HAVE_PRE_INCREMENT 0 */
2952 /* These assume that REGNO is a hard or pseudo reg number.
2953 They give nonzero only if REGNO is a hard reg of the suitable class
2954 or a pseudo reg currently allocated to a suitable hard reg.
2955 These definitions are NOT overridden anywhere. */
2957 #define BASE_REG_P(regno, mode) \
2959 ? (M16_REG_P (regno) \
2960 || (regno) == FRAME_POINTER_REGNUM \
2961 || (regno) == ARG_POINTER_REGNUM \
2962 || ((regno) == STACK_POINTER_REGNUM \
2963 && (GET_MODE_SIZE (mode) == 4 \
2964 || GET_MODE_SIZE (mode) == 8))) \
2967 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2968 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2971 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2972 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2974 #define REGNO_OK_FOR_INDEX_P(regno) 0
2975 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2976 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2978 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2979 and check its validity for a certain class.
2980 We have two alternate definitions for each of them.
2981 The usual definition accepts all pseudo regs; the other rejects them all.
2982 The symbol REG_OK_STRICT causes the latter definition to be used.
2984 Most source files want to accept pseudo regs in the hope that
2985 they will get allocated to the class that the insn wants them to be in.
2986 Some source files that are used after register allocation
2987 need to be strict. */
2989 #ifndef REG_OK_STRICT
2990 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2991 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2993 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2994 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2997 #define REG_OK_FOR_INDEX_P(X) 0
3000 /* Maximum number of registers that can appear in a valid memory address. */
3002 #define MAX_REGS_PER_ADDRESS 1
3004 /* A C compound statement with a conditional `goto LABEL;' executed
3005 if X (an RTX) is a legitimate memory address on the target
3006 machine for a memory operand of mode MODE. */
3009 #define GO_PRINTF(x) fprintf(stderr, (x))
3010 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3011 #define GO_DEBUG_RTX(x) debug_rtx(x)
3014 #define GO_PRINTF(x)
3015 #define GO_PRINTF2(x,y)
3016 #define GO_DEBUG_RTX(x)
3019 #ifdef REG_OK_STRICT
3020 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3022 if (mips_legitimate_address_p (MODE, X, 1)) \
3026 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3028 if (mips_legitimate_address_p (MODE, X, 0)) \
3033 /* A C expression that is 1 if the RTX X is a constant which is a
3034 valid address. This is defined to be the same as `CONSTANT_P (X)',
3035 but rejecting CONST_DOUBLE. */
3036 /* When pic, we must reject addresses of the form symbol+large int.
3037 This is because an instruction `sw $4,s+70000' needs to be converted
3038 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
3039 assembler would use $at as a temp to load in the large offset. In this
3040 case $at is already in use. We convert such problem addresses to
3041 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
3042 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them
3043 when !TARGET_GAS. */
3044 /* We should be rejecting everything but const addresses. */
3045 #define CONSTANT_ADDRESS_P(X) \
3046 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
3047 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
3048 || (GET_CODE (X) == CONST \
3049 && ! (flag_pic && pic_address_needs_scratch (X)) \
3051 && (mips_abi != ABI_N32 \
3052 && mips_abi != ABI_64)))
3055 /* Define this, so that when PIC, reload won't try to reload invalid
3056 addresses which require two reload registers. */
3058 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
3060 /* Nonzero if the constant value X is a legitimate general operand.
3061 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3063 At present, GAS doesn't understand li.[sd], so don't allow it
3064 to be generated at present. Also, the MIPS assembler does not
3065 grok li.d Infinity. */
3067 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3068 Note that the Irix 6 assembler problem may already be fixed.
3069 Note also that the GET_CODE (X) == CONST test catches the mips16
3070 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3071 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3072 ABI_64 to work together, we'll need to fix this. */
3073 #define LEGITIMATE_CONSTANT_P(X) \
3074 ((GET_CODE (X) != CONST_DOUBLE \
3075 || mips_const_double_ok (X, GET_MODE (X))) \
3076 && ! (GET_CODE (X) == CONST \
3078 && (mips_abi == ABI_N32 \
3079 || mips_abi == ABI_64)) \
3080 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3082 /* A C compound statement that attempts to replace X with a valid
3083 memory address for an operand of mode MODE. WIN will be a C
3084 statement label elsewhere in the code; the macro definition may
3087 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3089 to avoid further processing if the address has become legitimate.
3091 X will always be the result of a call to `break_out_memory_refs',
3092 and OLDX will be the operand that was given to that function to
3095 The code generated by this macro should not alter the
3096 substructure of X. If it transforms X into a more legitimate
3097 form, it should assign X (which will always be a C variable) a
3100 It is not necessary for this macro to come up with a legitimate
3101 address. The compiler has standard ways of doing so in all
3102 cases. In fact, it is safe for this macro to do nothing. But
3103 often a machine-dependent strategy can generate better code.
3105 For the MIPS, transform:
3107 memory(X + <large int>)
3111 Y = <large int> & ~0x7fff;
3113 memory (Z + (<large int> & 0x7fff));
3115 This is for CSE to find several similar references, and only use one Z.
3117 When PIC, convert addresses of the form memory (symbol+large int) to
3118 memory (reg+large int). */
3121 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3123 register rtx xinsn = (X); \
3125 if (TARGET_DEBUG_B_MODE) \
3127 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3128 GO_DEBUG_RTX (xinsn); \
3131 if (mips_split_addresses && mips_check_split (X, MODE)) \
3133 /* ??? Is this ever executed? */ \
3134 X = gen_rtx_LO_SUM (Pmode, \
3135 copy_to_mode_reg (Pmode, \
3136 gen_rtx (HIGH, Pmode, X)), \
3141 if (GET_CODE (xinsn) == CONST \
3142 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3143 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3145 && (mips_abi == ABI_N32 \
3146 || mips_abi == ABI_64)))) \
3148 rtx ptr_reg = gen_reg_rtx (Pmode); \
3149 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3151 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3153 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3154 if (SMALL_INT (constant)) \
3156 /* Otherwise we fall through so the code below will fix the \
3161 if (GET_CODE (xinsn) == PLUS) \
3163 register rtx xplus0 = XEXP (xinsn, 0); \
3164 register rtx xplus1 = XEXP (xinsn, 1); \
3165 register enum rtx_code code0 = GET_CODE (xplus0); \
3166 register enum rtx_code code1 = GET_CODE (xplus1); \
3168 if (code0 != REG && code1 == REG) \
3170 xplus0 = XEXP (xinsn, 1); \
3171 xplus1 = XEXP (xinsn, 0); \
3172 code0 = GET_CODE (xplus0); \
3173 code1 = GET_CODE (xplus1); \
3176 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3177 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3179 rtx int_reg = gen_reg_rtx (Pmode); \
3180 rtx ptr_reg = gen_reg_rtx (Pmode); \
3182 emit_move_insn (int_reg, \
3183 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3185 emit_insn (gen_rtx_SET (VOIDmode, \
3187 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3189 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3194 if (TARGET_DEBUG_B_MODE) \
3195 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3199 /* A C statement or compound statement with a conditional `goto
3200 LABEL;' executed if memory address X (an RTX) can have different
3201 meanings depending on the machine mode of the memory reference it
3204 Autoincrement and autodecrement addresses typically have
3205 mode-dependent effects because the amount of the increment or
3206 decrement is the size of the operand being addressed. Some
3207 machines have other mode-dependent addresses. Many RISC machines
3208 have no mode-dependent addresses.
3210 You may assume that ADDR is a valid address for the machine. */
3212 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3214 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3215 'the start of the function that this code is output in'. */
3217 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3218 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3219 asm_fprintf ((FILE), "%U%s", \
3220 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3222 asm_fprintf ((FILE), "%U%s", (NAME))
3224 /* The mips16 wants the constant pool to be after the function,
3225 because the PC relative load instructions use unsigned offsets. */
3227 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3229 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3230 mips_string_length = 0;
3233 /* In mips16 mode, put most string constants after the function. */
3234 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3235 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3238 /* Specify the machine mode that this machine uses
3239 for the index in the tablejump instruction.
3240 ??? Using HImode in mips16 mode can cause overflow. However, the
3241 overflow is no more likely than the overflow in a branch
3242 instruction. Large functions can currently break in both ways. */
3243 #define CASE_VECTOR_MODE \
3244 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3246 /* Define as C expression which evaluates to nonzero if the tablejump
3247 instruction expects the table to contain offsets from the address of the
3249 Do not define this if the table should contain absolute addresses. */
3250 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3252 /* Define this as 1 if `char' should by default be signed; else as 0. */
3253 #ifndef DEFAULT_SIGNED_CHAR
3254 #define DEFAULT_SIGNED_CHAR 1
3257 /* Max number of bytes we can move from memory to memory
3258 in one reasonably fast instruction. */
3259 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3260 #define MAX_MOVE_MAX 8
3262 /* Define this macro as a C expression which is nonzero if
3263 accessing less than a word of memory (i.e. a `char' or a
3264 `short') is no faster than accessing a word of memory, i.e., if
3265 such access require more than one instruction or if there is no
3266 difference in cost between byte and (aligned) word loads.
3268 On RISC machines, it tends to generate better code to define
3269 this as 1, since it avoids making a QI or HI mode register. */
3270 #define SLOW_BYTE_ACCESS 1
3272 /* We assume that the store-condition-codes instructions store 0 for false
3273 and some other value for true. This is the value stored for true. */
3275 #define STORE_FLAG_VALUE 1
3277 /* Define this to be nonzero if shift instructions ignore all but the low-order
3279 #define SHIFT_COUNT_TRUNCATED 1
3281 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3282 is done just by pretending it is already truncated. */
3283 /* In 64 bit mode, 32 bit instructions require that register values be properly
3284 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3285 converts a value >32 bits to a value <32 bits. */
3286 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3287 Something needs to be done about this. Perhaps not use any 32 bit
3288 instructions? Perhaps use PROMOTE_MODE? */
3289 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3290 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3292 /* Specify the machine mode that pointers have.
3293 After generation of rtl, the compiler makes no further distinction
3294 between pointers and any other objects of this machine mode.
3296 For MIPS we make pointers are the smaller of longs and gp-registers. */
3299 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3302 /* A function address in a call instruction
3303 is a word address (for indexing purposes)
3304 so give the MEM rtx a words's mode. */
3306 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3309 /* A part of a C `switch' statement that describes the relative
3310 costs of constant RTL expressions. It must contain `case'
3311 labels for expression codes `const_int', `const', `symbol_ref',
3312 `label_ref' and `const_double'. Each case must ultimately reach
3313 a `return' statement to return the relative cost of the use of
3314 that kind of constant value in an expression. The cost may
3315 depend on the precise value of the constant, which is available
3316 for examination in X.
3318 CODE is the expression code--redundant, since it can be obtained
3319 with `GET_CODE (X)'. */
3321 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3323 if (! TARGET_MIPS16) \
3325 /* Always return 0, since we don't have different sized \
3326 instructions, hence different costs according to Richard \
3330 if ((OUTER_CODE) == SET) \
3332 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3334 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3335 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3336 return COSTS_N_INSNS (1); \
3338 return COSTS_N_INSNS (2); \
3340 /* A PLUS could be an address. We don't want to force an address \
3341 to use a register, so accept any signed 16 bit value without \
3343 if ((OUTER_CODE) == PLUS \
3344 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3346 /* A number between 1 and 8 inclusive is efficient for a shift. \
3347 Otherwise, we will need an extended instruction. */ \
3348 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3349 || (OUTER_CODE) == LSHIFTRT) \
3351 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3353 return COSTS_N_INSNS (1); \
3355 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3356 if ((OUTER_CODE) == XOR \
3357 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3359 /* We may be able to use slt or sltu for a comparison with a \
3360 signed 16 bit value. (The boundary conditions aren't quite \
3361 right, but this is just a heuristic anyhow.) */ \
3362 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3363 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3364 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3365 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3366 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3368 /* Equality comparisons with 0 are cheap. */ \
3369 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3370 && INTVAL (X) == 0) \
3373 /* Otherwise, work out the cost to load the value into a \
3375 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3376 return COSTS_N_INSNS (1); \
3377 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3378 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3379 return COSTS_N_INSNS (2); \
3381 return COSTS_N_INSNS (3); \
3384 return COSTS_N_INSNS (2); \
3388 rtx offset = const0_rtx; \
3389 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3391 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3393 /* Treat this like a signed 16 bit CONST_INT. */ \
3394 if ((OUTER_CODE) == PLUS) \
3396 else if ((OUTER_CODE) == SET) \
3397 return COSTS_N_INSNS (1); \
3399 return COSTS_N_INSNS (2); \
3402 if (GET_CODE (symref) == LABEL_REF) \
3403 return COSTS_N_INSNS (2); \
3405 if (GET_CODE (symref) != SYMBOL_REF) \
3406 return COSTS_N_INSNS (4); \
3408 /* let's be paranoid.... */ \
3409 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3410 return COSTS_N_INSNS (2); \
3412 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3416 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3418 case CONST_DOUBLE: \
3421 if (TARGET_MIPS16) \
3422 return COSTS_N_INSNS (4); \
3423 split_double (X, &high, &low); \
3424 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3425 || low == CONST0_RTX (GET_MODE (low))) \
3429 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3430 This can be used, for example, to indicate how costly a multiply
3431 instruction is. In writing this macro, you can use the construct
3432 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3434 This macro is optional; do not define it if the default cost
3435 assumptions are adequate for the target machine.
3437 If -mdebugd is used, change the multiply cost to 2, so multiply by
3438 a constant isn't converted to a series of shifts. This helps
3439 strength reduction, and also makes it easier to identify what the
3440 compiler is doing. */
3442 /* ??? Fix this to be right for the R8000. */
3443 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3446 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3447 if (simple_memory_operand (X, GET_MODE (X))) \
3448 return COSTS_N_INSNS (num_words); \
3450 return COSTS_N_INSNS (2*num_words); \
3454 return COSTS_N_INSNS (6); \
3457 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3462 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3463 return COSTS_N_INSNS (2); \
3470 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3471 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3477 enum machine_mode xmode = GET_MODE (X); \
3478 if (xmode == SFmode || xmode == DFmode) \
3479 return COSTS_N_INSNS (1); \
3481 return COSTS_N_INSNS (4); \
3487 enum machine_mode xmode = GET_MODE (X); \
3488 if (xmode == SFmode || xmode == DFmode) \
3492 return COSTS_N_INSNS (2); \
3493 else if (TUNE_MIPS6000) \
3494 return COSTS_N_INSNS (3); \
3496 return COSTS_N_INSNS (6); \
3499 if (xmode == DImode && !TARGET_64BIT) \
3500 return COSTS_N_INSNS (4); \
3506 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3513 enum machine_mode xmode = GET_MODE (X); \
3514 if (xmode == SFmode) \
3519 return COSTS_N_INSNS (4); \
3520 else if (TUNE_MIPS6000) \
3521 return COSTS_N_INSNS (5); \
3523 return COSTS_N_INSNS (7); \
3526 if (xmode == DFmode) \
3531 return COSTS_N_INSNS (5); \
3532 else if (TUNE_MIPS6000) \
3533 return COSTS_N_INSNS (6); \
3535 return COSTS_N_INSNS (8); \
3538 if (TUNE_MIPS3000) \
3539 return COSTS_N_INSNS (12); \
3540 else if (TUNE_MIPS3900) \
3541 return COSTS_N_INSNS (2); \
3542 else if (TUNE_MIPS6000) \
3543 return COSTS_N_INSNS (17); \
3544 else if (TUNE_MIPS5000) \
3545 return COSTS_N_INSNS (5); \
3547 return COSTS_N_INSNS (10); \
3553 enum machine_mode xmode = GET_MODE (X); \
3554 if (xmode == SFmode) \
3558 return COSTS_N_INSNS (12); \
3559 else if (TUNE_MIPS6000) \
3560 return COSTS_N_INSNS (15); \
3562 return COSTS_N_INSNS (23); \
3565 if (xmode == DFmode) \
3569 return COSTS_N_INSNS (19); \
3570 else if (TUNE_MIPS6000) \
3571 return COSTS_N_INSNS (16); \
3573 return COSTS_N_INSNS (36); \
3576 /* fall through */ \
3582 return COSTS_N_INSNS (35); \
3583 else if (TUNE_MIPS6000) \
3584 return COSTS_N_INSNS (38); \
3585 else if (TUNE_MIPS5000) \
3586 return COSTS_N_INSNS (36); \
3588 return COSTS_N_INSNS (69); \
3591 /* A sign extend from SImode to DImode in 64 bit mode is often \
3592 zero instructions, because the result can often be used \
3593 directly by another instruction; we'll call it one. */ \
3594 if (TARGET_64BIT && GET_MODE (X) == DImode \
3595 && GET_MODE (XEXP (X, 0)) == SImode) \
3596 return COSTS_N_INSNS (1); \
3598 return COSTS_N_INSNS (2); \
3601 if (TARGET_64BIT && GET_MODE (X) == DImode \
3602 && GET_MODE (XEXP (X, 0)) == SImode) \
3603 return COSTS_N_INSNS (2); \
3605 return COSTS_N_INSNS (1);
3607 /* An expression giving the cost of an addressing mode that
3608 contains ADDRESS. If not defined, the cost is computed from the
3609 form of the ADDRESS expression and the `CONST_COSTS' values.
3611 For most CISC machines, the default cost is a good approximation
3612 of the true cost of the addressing mode. However, on RISC
3613 machines, all instructions normally have the same length and
3614 execution time. Hence all addresses will have equal costs.
3616 In cases where more than one form of an address is known, the
3617 form with the lowest cost will be used. If multiple forms have
3618 the same, lowest, cost, the one that is the most complex will be
3621 For example, suppose an address that is equal to the sum of a
3622 register and a constant is used twice in the same basic block.
3623 When this macro is not defined, the address will be computed in
3624 a register and memory references will be indirect through that
3625 register. On machines where the cost of the addressing mode
3626 containing the sum is no higher than that of a simple indirect
3627 reference, this will produce an additional instruction and
3628 possibly require an additional register. Proper specification
3629 of this macro eliminates this overhead for such machines.
3631 Similar use of this macro is made in strength reduction of loops.
3633 ADDRESS need not be valid as an address. In such a case, the
3634 cost is not relevant and can be any value; invalid addresses
3635 need not be assigned a different cost.
3637 On machines where an address involving more than one register is
3638 as cheap as an address computation involving only one register,
3639 defining `ADDRESS_COST' to reflect this can cause two registers
3640 to be live over a region of code where only one would have been
3641 if `ADDRESS_COST' were not defined in that manner. This effect
3642 should be considered in the definition of this macro.
3643 Equivalent costs should probably only be given to addresses with
3644 different numbers of registers on machines with lots of registers.
3646 This macro will normally either not be defined or be defined as
3649 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3651 /* A C expression for the cost of moving data from a register in
3652 class FROM to one in class TO. The classes are expressed using
3653 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3654 the default; other values are interpreted relative to that.
3656 It is not required that the cost always equal 2 when FROM is the
3657 same as TO; on some machines it is expensive to move between
3658 registers if they are not general registers.
3660 If reload sees an insn consisting of a single `set' between two
3661 hard registers, and if `REGISTER_MOVE_COST' applied to their
3662 classes returns a value of 2, reload does not check to ensure
3663 that the constraints of the insn are met. Setting a cost of
3664 other than 2 will allow reload to verify that the constraints are
3665 met. You should do this if the `movM' pattern's constraints do
3666 not allow such copying. */
3668 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3669 mips_register_move_cost (MODE, FROM, TO)
3671 /* ??? Fix this to be right for the R8000. */
3672 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3673 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3674 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3676 /* Define if copies to/from condition code registers should be avoided.
3678 This is needed for the MIPS because reload_outcc is not complete;
3679 it needs to handle cases where the source is a general or another
3680 condition code register. */
3681 #define AVOID_CCMODE_COPIES
3683 /* A C expression for the cost of a branch instruction. A value of
3684 1 is the default; other values are interpreted relative to that. */
3686 /* ??? Fix this to be right for the R8000. */
3687 #define BRANCH_COST \
3689 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3692 /* If defined, modifies the length assigned to instruction INSN as a
3693 function of the context in which it is used. LENGTH is an lvalue
3694 that contains the initially computed length of the insn and should
3695 be updated with the correct length of the insn. */
3696 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3697 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3700 /* Optionally define this if you have added predicates to
3701 `MACHINE.c'. This macro is called within an initializer of an
3702 array of structures. The first field in the structure is the
3703 name of a predicate and the second field is an array of rtl
3704 codes. For each predicate, list all rtl codes that can be in
3705 expressions matched by the predicate. The list should have a
3706 trailing comma. Here is an example of two entries in the list
3707 for a typical RISC machine:
3709 #define PREDICATE_CODES \
3710 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3711 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3713 Defining this macro does not affect the generated code (however,
3714 incorrect definitions that omit an rtl code that may be matched
3715 by the predicate can cause the compiler to malfunction).
3716 Instead, it allows the table built by `genrecog' to be more
3717 compact and efficient, thus speeding up the compiler. The most
3718 important predicates to include in the list specified by this
3719 macro are thoses used in the most insn patterns. */
3721 #define PREDICATE_CODES \
3722 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3723 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3724 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3725 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3726 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3727 {"small_int", { CONST_INT }}, \
3728 {"large_int", { CONST_INT }}, \
3729 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3730 {"const_float_1_operand", { CONST_DOUBLE }}, \
3731 {"simple_memory_operand", { MEM, SUBREG }}, \
3732 {"equality_op", { EQ, NE }}, \
3733 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3735 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3736 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3737 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3738 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3739 SYMBOL_REF, LABEL_REF, SUBREG, \
3741 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3742 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3743 MEM, SIGN_EXTEND }}, \
3744 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3745 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3747 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3749 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3751 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3752 SYMBOL_REF, LABEL_REF, SUBREG, \
3753 REG, SIGN_EXTEND }}, \
3754 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3755 CONST_DOUBLE, CONST }}, \
3756 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3757 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3759 /* A list of predicates that do special things with modes, and so
3760 should not elicit warnings for VOIDmode match_operand. */
3762 #define SPECIAL_MODE_PREDICATES \
3763 "pc_or_label_operand",
3766 /* If defined, a C statement to be executed just prior to the
3767 output of assembler code for INSN, to modify the extracted
3768 operands so they will be output differently.
3770 Here the argument OPVEC is the vector containing the operands
3771 extracted from INSN, and NOPERANDS is the number of elements of
3772 the vector which contain meaningful data for this insn. The
3773 contents of this vector are what will be used to convert the
3774 insn template into assembler code, so you can change the
3775 assembler output by changing the contents of the vector.
3777 We use it to check if the current insn needs a nop in front of it
3778 because of load delays, and also to update the delay slot
3781 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3782 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3785 /* Control the assembler format that we output. */
3787 /* Output at beginning of assembler file.
3788 If we are optimizing to use the global pointer, create a temporary
3789 file to hold all of the text stuff, and write it out to the end.
3790 This is needed because the MIPS assembler is evidently one pass,
3791 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3792 declaration when the code is processed, it generates a two
3793 instruction sequence. */
3795 #undef ASM_FILE_START
3796 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3798 /* Output to assembler file text saying following lines
3799 may contain character constants, extra white space, comments, etc. */
3802 #define ASM_APP_ON " #APP\n"
3805 /* Output to assembler file text saying following lines
3806 no longer contain unusual constructs. */
3809 #define ASM_APP_OFF " #NO_APP\n"
3812 /* How to refer to registers in assembler output.
3813 This sequence is indexed by compiler's hard-register-number (see above).
3815 In order to support the two different conventions for register names,
3816 we use the name of a table set up in mips.c, which is overwritten
3817 if -mrnames is used. */
3819 #define REGISTER_NAMES \
3821 &mips_reg_names[ 0][0], \
3822 &mips_reg_names[ 1][0], \
3823 &mips_reg_names[ 2][0], \
3824 &mips_reg_names[ 3][0], \
3825 &mips_reg_names[ 4][0], \
3826 &mips_reg_names[ 5][0], \
3827 &mips_reg_names[ 6][0], \
3828 &mips_reg_names[ 7][0], \
3829 &mips_reg_names[ 8][0], \
3830 &mips_reg_names[ 9][0], \
3831 &mips_reg_names[10][0], \
3832 &mips_reg_names[11][0], \
3833 &mips_reg_names[12][0], \
3834 &mips_reg_names[13][0], \
3835 &mips_reg_names[14][0], \
3836 &mips_reg_names[15][0], \
3837 &mips_reg_names[16][0], \
3838 &mips_reg_names[17][0], \
3839 &mips_reg_names[18][0], \
3840 &mips_reg_names[19][0], \
3841 &mips_reg_names[20][0], \
3842 &mips_reg_names[21][0], \
3843 &mips_reg_names[22][0], \
3844 &mips_reg_names[23][0], \
3845 &mips_reg_names[24][0], \
3846 &mips_reg_names[25][0], \
3847 &mips_reg_names[26][0], \
3848 &mips_reg_names[27][0], \
3849 &mips_reg_names[28][0], \
3850 &mips_reg_names[29][0], \
3851 &mips_reg_names[30][0], \
3852 &mips_reg_names[31][0], \
3853 &mips_reg_names[32][0], \
3854 &mips_reg_names[33][0], \
3855 &mips_reg_names[34][0], \
3856 &mips_reg_names[35][0], \
3857 &mips_reg_names[36][0], \
3858 &mips_reg_names[37][0], \
3859 &mips_reg_names[38][0], \
3860 &mips_reg_names[39][0], \
3861 &mips_reg_names[40][0], \
3862 &mips_reg_names[41][0], \
3863 &mips_reg_names[42][0], \
3864 &mips_reg_names[43][0], \
3865 &mips_reg_names[44][0], \
3866 &mips_reg_names[45][0], \
3867 &mips_reg_names[46][0], \
3868 &mips_reg_names[47][0], \
3869 &mips_reg_names[48][0], \
3870 &mips_reg_names[49][0], \
3871 &mips_reg_names[50][0], \
3872 &mips_reg_names[51][0], \
3873 &mips_reg_names[52][0], \
3874 &mips_reg_names[53][0], \
3875 &mips_reg_names[54][0], \
3876 &mips_reg_names[55][0], \
3877 &mips_reg_names[56][0], \
3878 &mips_reg_names[57][0], \
3879 &mips_reg_names[58][0], \
3880 &mips_reg_names[59][0], \
3881 &mips_reg_names[60][0], \
3882 &mips_reg_names[61][0], \
3883 &mips_reg_names[62][0], \
3884 &mips_reg_names[63][0], \
3885 &mips_reg_names[64][0], \
3886 &mips_reg_names[65][0], \
3887 &mips_reg_names[66][0], \
3888 &mips_reg_names[67][0], \
3889 &mips_reg_names[68][0], \
3890 &mips_reg_names[69][0], \
3891 &mips_reg_names[70][0], \
3892 &mips_reg_names[71][0], \
3893 &mips_reg_names[72][0], \
3894 &mips_reg_names[73][0], \
3895 &mips_reg_names[74][0], \
3896 &mips_reg_names[75][0], \
3897 &mips_reg_names[76][0], \
3898 &mips_reg_names[77][0], \
3899 &mips_reg_names[78][0], \
3900 &mips_reg_names[79][0], \
3901 &mips_reg_names[80][0], \
3902 &mips_reg_names[81][0], \
3903 &mips_reg_names[82][0], \
3904 &mips_reg_names[83][0], \
3905 &mips_reg_names[84][0], \
3906 &mips_reg_names[85][0], \
3907 &mips_reg_names[86][0], \
3908 &mips_reg_names[87][0], \
3909 &mips_reg_names[88][0], \
3910 &mips_reg_names[89][0], \
3911 &mips_reg_names[90][0], \
3912 &mips_reg_names[91][0], \
3913 &mips_reg_names[92][0], \
3914 &mips_reg_names[93][0], \
3915 &mips_reg_names[94][0], \
3916 &mips_reg_names[95][0], \
3917 &mips_reg_names[96][0], \
3918 &mips_reg_names[97][0], \
3919 &mips_reg_names[98][0], \
3920 &mips_reg_names[99][0], \
3921 &mips_reg_names[100][0], \
3922 &mips_reg_names[101][0], \
3923 &mips_reg_names[102][0], \
3924 &mips_reg_names[103][0], \
3925 &mips_reg_names[104][0], \
3926 &mips_reg_names[105][0], \
3927 &mips_reg_names[106][0], \
3928 &mips_reg_names[107][0], \
3929 &mips_reg_names[108][0], \
3930 &mips_reg_names[109][0], \
3931 &mips_reg_names[110][0], \
3932 &mips_reg_names[111][0], \
3933 &mips_reg_names[112][0], \
3934 &mips_reg_names[113][0], \
3935 &mips_reg_names[114][0], \
3936 &mips_reg_names[115][0], \
3937 &mips_reg_names[116][0], \
3938 &mips_reg_names[117][0], \
3939 &mips_reg_names[118][0], \
3940 &mips_reg_names[119][0], \
3941 &mips_reg_names[120][0], \
3942 &mips_reg_names[121][0], \
3943 &mips_reg_names[122][0], \
3944 &mips_reg_names[123][0], \
3945 &mips_reg_names[124][0], \
3946 &mips_reg_names[125][0], \
3947 &mips_reg_names[126][0], \
3948 &mips_reg_names[127][0], \
3949 &mips_reg_names[128][0], \
3950 &mips_reg_names[129][0], \
3951 &mips_reg_names[130][0], \
3952 &mips_reg_names[131][0], \
3953 &mips_reg_names[132][0], \
3954 &mips_reg_names[133][0], \
3955 &mips_reg_names[134][0], \
3956 &mips_reg_names[135][0], \
3957 &mips_reg_names[136][0], \
3958 &mips_reg_names[137][0], \
3959 &mips_reg_names[138][0], \
3960 &mips_reg_names[139][0], \
3961 &mips_reg_names[140][0], \
3962 &mips_reg_names[141][0], \
3963 &mips_reg_names[142][0], \
3964 &mips_reg_names[143][0], \
3965 &mips_reg_names[144][0], \
3966 &mips_reg_names[145][0], \
3967 &mips_reg_names[146][0], \
3968 &mips_reg_names[147][0], \
3969 &mips_reg_names[148][0], \
3970 &mips_reg_names[149][0], \
3971 &mips_reg_names[150][0], \
3972 &mips_reg_names[151][0], \
3973 &mips_reg_names[152][0], \
3974 &mips_reg_names[153][0], \
3975 &mips_reg_names[154][0], \
3976 &mips_reg_names[155][0], \
3977 &mips_reg_names[156][0], \
3978 &mips_reg_names[157][0], \
3979 &mips_reg_names[158][0], \
3980 &mips_reg_names[159][0], \
3981 &mips_reg_names[160][0], \
3982 &mips_reg_names[161][0], \
3983 &mips_reg_names[162][0], \
3984 &mips_reg_names[163][0], \
3985 &mips_reg_names[164][0], \
3986 &mips_reg_names[165][0], \
3987 &mips_reg_names[166][0], \
3988 &mips_reg_names[167][0], \
3989 &mips_reg_names[168][0], \
3990 &mips_reg_names[169][0], \
3991 &mips_reg_names[170][0], \
3992 &mips_reg_names[171][0], \
3993 &mips_reg_names[172][0], \
3994 &mips_reg_names[173][0], \
3995 &mips_reg_names[174][0], \
3996 &mips_reg_names[175][0] \
3999 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
4000 So define this for it. */
4001 #define DEBUG_REGISTER_NAMES \
4003 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
4004 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
4005 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
4006 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
4007 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
4008 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
4009 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
4010 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
4011 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
4012 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
4013 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
4014 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
4015 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
4016 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
4017 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
4018 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
4019 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
4020 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
4021 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
4022 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
4023 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
4024 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
4027 /* If defined, a C initializer for an array of structures
4028 containing a name and a register number. This macro defines
4029 additional names for hard registers, thus allowing the `asm'
4030 option in declarations to refer to registers using alternate
4033 We define both names for the integer registers here. */
4035 #define ADDITIONAL_REGISTER_NAMES \
4037 { "$0", 0 + GP_REG_FIRST }, \
4038 { "$1", 1 + GP_REG_FIRST }, \
4039 { "$2", 2 + GP_REG_FIRST }, \
4040 { "$3", 3 + GP_REG_FIRST }, \
4041 { "$4", 4 + GP_REG_FIRST }, \
4042 { "$5", 5 + GP_REG_FIRST }, \
4043 { "$6", 6 + GP_REG_FIRST }, \
4044 { "$7", 7 + GP_REG_FIRST }, \
4045 { "$8", 8 + GP_REG_FIRST }, \
4046 { "$9", 9 + GP_REG_FIRST }, \
4047 { "$10", 10 + GP_REG_FIRST }, \
4048 { "$11", 11 + GP_REG_FIRST }, \
4049 { "$12", 12 + GP_REG_FIRST }, \
4050 { "$13", 13 + GP_REG_FIRST }, \
4051 { "$14", 14 + GP_REG_FIRST }, \
4052 { "$15", 15 + GP_REG_FIRST }, \
4053 { "$16", 16 + GP_REG_FIRST }, \
4054 { "$17", 17 + GP_REG_FIRST }, \
4055 { "$18", 18 + GP_REG_FIRST }, \
4056 { "$19", 19 + GP_REG_FIRST }, \
4057 { "$20", 20 + GP_REG_FIRST }, \
4058 { "$21", 21 + GP_REG_FIRST }, \
4059 { "$22", 22 + GP_REG_FIRST }, \
4060 { "$23", 23 + GP_REG_FIRST }, \
4061 { "$24", 24 + GP_REG_FIRST }, \
4062 { "$25", 25 + GP_REG_FIRST }, \
4063 { "$26", 26 + GP_REG_FIRST }, \
4064 { "$27", 27 + GP_REG_FIRST }, \
4065 { "$28", 28 + GP_REG_FIRST }, \
4066 { "$29", 29 + GP_REG_FIRST }, \
4067 { "$30", 30 + GP_REG_FIRST }, \
4068 { "$31", 31 + GP_REG_FIRST }, \
4069 { "$sp", 29 + GP_REG_FIRST }, \
4070 { "$fp", 30 + GP_REG_FIRST }, \
4071 { "at", 1 + GP_REG_FIRST }, \
4072 { "v0", 2 + GP_REG_FIRST }, \
4073 { "v1", 3 + GP_REG_FIRST }, \
4074 { "a0", 4 + GP_REG_FIRST }, \
4075 { "a1", 5 + GP_REG_FIRST }, \
4076 { "a2", 6 + GP_REG_FIRST }, \
4077 { "a3", 7 + GP_REG_FIRST }, \
4078 { "t0", 8 + GP_REG_FIRST }, \
4079 { "t1", 9 + GP_REG_FIRST }, \
4080 { "t2", 10 + GP_REG_FIRST }, \
4081 { "t3", 11 + GP_REG_FIRST }, \
4082 { "t4", 12 + GP_REG_FIRST }, \
4083 { "t5", 13 + GP_REG_FIRST }, \
4084 { "t6", 14 + GP_REG_FIRST }, \
4085 { "t7", 15 + GP_REG_FIRST }, \
4086 { "s0", 16 + GP_REG_FIRST }, \
4087 { "s1", 17 + GP_REG_FIRST }, \
4088 { "s2", 18 + GP_REG_FIRST }, \
4089 { "s3", 19 + GP_REG_FIRST }, \
4090 { "s4", 20 + GP_REG_FIRST }, \
4091 { "s5", 21 + GP_REG_FIRST }, \
4092 { "s6", 22 + GP_REG_FIRST }, \
4093 { "s7", 23 + GP_REG_FIRST }, \
4094 { "t8", 24 + GP_REG_FIRST }, \
4095 { "t9", 25 + GP_REG_FIRST }, \
4096 { "k0", 26 + GP_REG_FIRST }, \
4097 { "k1", 27 + GP_REG_FIRST }, \
4098 { "gp", 28 + GP_REG_FIRST }, \
4099 { "sp", 29 + GP_REG_FIRST }, \
4100 { "fp", 30 + GP_REG_FIRST }, \
4101 { "ra", 31 + GP_REG_FIRST }, \
4102 { "$sp", 29 + GP_REG_FIRST }, \
4103 { "$fp", 30 + GP_REG_FIRST } \
4104 ALL_COP_ADDITIONAL_REGISTER_NAMES \
4107 /* This is meant to be redefined in the host dependent files. It is a
4108 set of alternative names and regnums for mips coprocessors. */
4110 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
4112 /* A C compound statement to output to stdio stream STREAM the
4113 assembler syntax for an instruction operand X. X is an RTL
4116 CODE is a value that can be used to specify one of several ways
4117 of printing the operand. It is used when identical operands
4118 must be printed differently depending on the context. CODE
4119 comes from the `%' specification that was used to request
4120 printing of the operand. If the specification was just `%DIGIT'
4121 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4122 is the ASCII code for LTR.
4124 If X is a register, this macro should print the register's name.
4125 The names can be found in an array `reg_names' whose type is
4126 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4128 When the machine description has a specification `%PUNCT' (a `%'
4129 followed by a punctuation character), this macro is called with
4130 a null pointer for X and the punctuation character for CODE.
4132 See mips.c for the MIPS specific codes. */
4134 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4136 /* A C expression which evaluates to true if CODE is a valid
4137 punctuation character for use in the `PRINT_OPERAND' macro. If
4138 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4139 punctuation characters (except for the standard one, `%') are
4140 used in this way. */
4142 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4144 /* A C compound statement to output to stdio stream STREAM the
4145 assembler syntax for an instruction operand that is a memory
4146 reference whose address is ADDR. ADDR is an RTL expression. */
4148 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4151 /* A C statement, to be executed after all slot-filler instructions
4152 have been output. If necessary, call `dbr_sequence_length' to
4153 determine the number of slots filled in a sequence (zero if not
4154 currently outputting a sequence), to decide how many no-ops to
4155 output, or whatever.
4157 Don't define this macro if it has nothing to do, but it is
4158 helpful in reading assembly output if the extent of the delay
4159 sequence is made explicit (e.g. with white space).
4161 Note that output routines for instructions with delay slots must
4162 be prepared to deal with not being output as part of a sequence
4163 (i.e. when the scheduling pass is not run, or when no slot
4164 fillers could be found.) The variable `final_sequence' is null
4165 when not processing a sequence, otherwise it contains the
4166 `sequence' rtx being output. */
4168 #define DBR_OUTPUT_SEQEND(STREAM) \
4171 if (set_nomacro > 0 && --set_nomacro == 0) \
4172 fputs ("\t.set\tmacro\n", STREAM); \
4174 if (set_noreorder > 0 && --set_noreorder == 0) \
4175 fputs ("\t.set\treorder\n", STREAM); \
4177 dslots_jump_filled++; \
4178 fputs ("\n", STREAM); \
4183 /* How to tell the debugger about changes of source files. Note, the
4184 mips ECOFF format cannot deal with changes of files inside of
4185 functions, which means the output of parser generators like bison
4186 is generally not debuggable without using the -l switch. Lose,
4187 lose, lose. Silicon graphics seems to want all .file's hardwired
4190 #ifndef SET_FILE_NUMBER
4191 #define SET_FILE_NUMBER() ++num_source_filenames
4194 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4195 mips_output_filename (STREAM, NAME)
4197 /* This is defined so that it can be overridden in iris6.h. */
4198 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4201 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4202 output_quoted_string (STREAM, NAME); \
4203 fputs ("\n", STREAM); \
4207 /* This is how to output a note the debugger telling it the line number
4208 to which the following sequence of instructions corresponds.
4209 Silicon graphics puts a label after each .loc. */
4211 #ifndef LABEL_AFTER_LOC
4212 #define LABEL_AFTER_LOC(STREAM)
4215 #ifndef ASM_OUTPUT_SOURCE_LINE
4216 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4217 mips_output_lineno (STREAM, LINE)
4220 /* The MIPS implementation uses some labels for its own purpose. The
4221 following lists what labels are created, and are all formed by the
4222 pattern $L[a-z].*. The machine independent portion of GCC creates
4223 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4225 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4226 $Lb[0-9]+ Begin blocks for MIPS debug support
4227 $Lc[0-9]+ Label for use in s<xx> operation.
4228 $Le[0-9]+ End blocks for MIPS debug support */
4230 /* A C statement (sans semicolon) to output to the stdio stream
4231 STREAM any text necessary for declaring the name NAME of an
4232 initialized variable which is being defined. This macro must
4233 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4234 The argument DECL is the `VAR_DECL' tree node representing the
4237 If this macro is not defined, then the variable name is defined
4238 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4240 #undef ASM_DECLARE_OBJECT_NAME
4241 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4244 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4248 /* Globalizing directive for a label. */
4249 #define GLOBAL_ASM_OP "\t.globl\t"
4251 /* This says how to define a global common symbol. */
4253 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4255 /* If the target wants uninitialized const declarations in \
4256 .rdata then don't put them in .comm */ \
4257 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4258 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4259 && (DECL_INITIAL (DECL) == 0 \
4260 || DECL_INITIAL (DECL) == error_mark_node)) \
4262 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4263 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4265 readonly_data_section (); \
4266 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4267 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4271 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4276 /* This says how to define a local common symbol (ie, not visible to
4279 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4280 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4283 /* This says how to output an external. It would be possible not to
4284 output anything and let undefined symbol become external. However
4285 the assembler uses length information on externals to allocate in
4286 data/sdata bss/sbss, thereby saving exec time. */
4288 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4289 mips_output_external(STREAM,DECL,NAME)
4291 /* This says what to print at the end of the assembly file */
4293 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4296 /* Play switch file games if we're optimizing the global pointer. */
4299 #define TEXT_SECTION() \
4301 extern FILE *asm_out_text_file; \
4302 if (TARGET_FILE_SWITCHING) \
4303 asm_out_file = asm_out_text_file; \
4304 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4305 fputc ('\n', asm_out_file); \
4309 /* This is how to declare a function name. The actual work of
4310 emitting the label is moved to function_prologue, so that we can
4311 get the line number correctly emitted before the .ent directive,
4312 and after any .file directives. Define as empty so that the function
4313 is not declared before the .ent directive elsewhere. */
4315 #undef ASM_DECLARE_FUNCTION_NAME
4316 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
4319 /* This is how to output an internal numbered label where
4320 PREFIX is the class of label and NUM is the number within the class. */
4322 #undef ASM_OUTPUT_INTERNAL_LABEL
4323 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4324 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4326 /* This is how to store into the string LABEL
4327 the symbol_ref name of an internal numbered label where
4328 PREFIX is the class of label and NUM is the number within the class.
4329 This is suitable for output with `assemble_name'. */
4331 #undef ASM_GENERATE_INTERNAL_LABEL
4332 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4333 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4335 /* This is how to output an element of a case-vector that is absolute. */
4337 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4338 fprintf (STREAM, "\t%s\t%sL%d\n", \
4339 Pmode == DImode ? ".dword" : ".word", \
4340 LOCAL_LABEL_PREFIX, \
4343 /* This is how to output an element of a case-vector that is relative.
4344 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4345 TARGET_EMBEDDED_PIC). */
4347 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4349 if (TARGET_MIPS16) \
4350 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4351 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4352 else if (TARGET_EMBEDDED_PIC) \
4353 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4354 Pmode == DImode ? ".dword" : ".word", \
4355 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4356 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4357 fprintf (STREAM, "\t%s\t%sL%d\n", \
4358 Pmode == DImode ? ".gpdword" : ".gpword", \
4359 LOCAL_LABEL_PREFIX, VALUE); \
4361 fprintf (STREAM, "\t%s\t%sL%d\n", \
4362 Pmode == DImode ? ".dword" : ".word", \
4363 LOCAL_LABEL_PREFIX, VALUE); \
4366 /* When generating embedded PIC or mips16 code we want to put the jump
4367 table in the .text section. In all other cases, we want to put the
4368 jump table in the .rdata section. Unfortunately, we can't use
4369 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4370 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4371 section if appropriate. */
4372 #undef ASM_OUTPUT_CASE_LABEL
4373 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4375 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4376 function_section (current_function_decl); \
4377 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4380 /* This is how to output an assembler line
4381 that says to advance the location counter
4382 to a multiple of 2**LOG bytes. */
4384 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4385 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4387 /* This is how to output an assembler line to advance the location
4388 counter by SIZE bytes. */
4390 #undef ASM_OUTPUT_SKIP
4391 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4392 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4394 /* This is how to output a string. */
4395 #undef ASM_OUTPUT_ASCII
4396 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4397 mips_output_ascii (STREAM, STRING, LEN)
4399 /* Output #ident as a in the read-only data section. */
4400 #undef ASM_OUTPUT_IDENT
4401 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4403 const char *p = STRING; \
4404 int size = strlen (p) + 1; \
4405 readonly_data_section (); \
4406 assemble_string (p, size); \
4409 /* Default to -G 8 */
4410 #ifndef MIPS_DEFAULT_GVALUE
4411 #define MIPS_DEFAULT_GVALUE 8
4414 /* Define the strings to put out for each section in the object file. */
4415 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4416 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4417 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4419 #undef READONLY_DATA_SECTION_ASM_OP
4420 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4422 #define SMALL_DATA_SECTION sdata_section
4424 /* What other sections we support other than the normal .data/.text. */
4426 #undef EXTRA_SECTIONS
4427 #define EXTRA_SECTIONS in_sdata
4429 /* Define the additional functions to select our additional sections. */
4431 /* on the MIPS it is not a good idea to put constants in the text
4432 section, since this defeats the sdata/data mechanism. This is
4433 especially true when -O is used. In this case an effort is made to
4434 address with faster (gp) register relative addressing, which can
4435 only get at sdata and sbss items (there is no stext !!) However,
4436 if the constant is too large for sdata, and it's readonly, it
4437 will go into the .rdata section. */
4439 #undef EXTRA_SECTION_FUNCTIONS
4440 #define EXTRA_SECTION_FUNCTIONS \
4444 if (in_section != in_sdata) \
4446 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4447 in_section = in_sdata; \
4451 /* Given a decl node or constant node, choose the section to output it in
4452 and select that section. */
4454 #undef TARGET_ASM_SELECT_SECTION
4455 #define TARGET_ASM_SELECT_SECTION mips_select_section
4457 /* Store in OUTPUT a string (made with alloca) containing
4458 an assembler-name for a local static variable named NAME.
4459 LABELNO is an integer which is different for each call. */
4461 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4462 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4463 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4465 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4468 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4469 TARGET_64BIT ? "dsubu" : "subu", \
4470 reg_names[STACK_POINTER_REGNUM], \
4471 reg_names[STACK_POINTER_REGNUM], \
4472 TARGET_64BIT ? "sd" : "sw", \
4474 reg_names[STACK_POINTER_REGNUM]); \
4478 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4481 if (! set_noreorder) \
4482 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4484 dslots_load_total++; \
4485 dslots_load_filled++; \
4486 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4487 TARGET_64BIT ? "ld" : "lw", \
4489 reg_names[STACK_POINTER_REGNUM], \
4490 TARGET_64BIT ? "daddu" : "addu", \
4491 reg_names[STACK_POINTER_REGNUM], \
4492 reg_names[STACK_POINTER_REGNUM]); \
4494 if (! set_noreorder) \
4495 fprintf (STREAM, "\t.set\treorder\n"); \
4499 /* How to start an assembler comment.
4500 The leading space is important (the mips native assembler requires it). */
4501 #ifndef ASM_COMMENT_START
4502 #define ASM_COMMENT_START " #"
4506 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4507 and mips-tdump.c to print them out.
4509 These must match the corresponding definitions in gdb/mipsread.c.
4510 Unfortunately, gcc and gdb do not currently share any directories. */
4512 #define CODE_MASK 0x8F300
4513 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4514 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4515 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4518 /* Default definitions for size_t and ptrdiff_t. */
4521 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4524 #ifndef PTRDIFF_TYPE
4525 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4528 /* See mips_expand_prologue's use of loadgp for when this should be
4531 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4532 && mips_abi != ABI_32 \
4533 && mips_abi != ABI_O64)
4535 /* In mips16 mode, we need to look through the function to check for
4536 PC relative loads that are out of range. */
4537 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4539 /* We need to use a special set of functions to handle hard floating
4540 point code in mips16 mode. */
4542 #ifndef INIT_SUBTARGET_OPTABS
4543 #define INIT_SUBTARGET_OPTABS
4546 #define INIT_TARGET_OPTABS \
4549 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4550 INIT_SUBTARGET_OPTABS; \
4553 add_optab->handlers[(int) SFmode].libfunc = \
4554 init_one_libfunc ("__mips16_addsf3"); \
4555 sub_optab->handlers[(int) SFmode].libfunc = \
4556 init_one_libfunc ("__mips16_subsf3"); \
4557 smul_optab->handlers[(int) SFmode].libfunc = \
4558 init_one_libfunc ("__mips16_mulsf3"); \
4559 sdiv_optab->handlers[(int) SFmode].libfunc = \
4560 init_one_libfunc ("__mips16_divsf3"); \
4562 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4563 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4564 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4565 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4566 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4567 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4569 floatsisf_libfunc = \
4570 init_one_libfunc ("__mips16_floatsisf"); \
4572 init_one_libfunc ("__mips16_fixsfsi"); \
4574 if (TARGET_DOUBLE_FLOAT) \
4576 add_optab->handlers[(int) DFmode].libfunc = \
4577 init_one_libfunc ("__mips16_adddf3"); \
4578 sub_optab->handlers[(int) DFmode].libfunc = \
4579 init_one_libfunc ("__mips16_subdf3"); \
4580 smul_optab->handlers[(int) DFmode].libfunc = \
4581 init_one_libfunc ("__mips16_muldf3"); \
4582 sdiv_optab->handlers[(int) DFmode].libfunc = \
4583 init_one_libfunc ("__mips16_divdf3"); \
4585 extendsfdf2_libfunc = \
4586 init_one_libfunc ("__mips16_extendsfdf2"); \
4587 truncdfsf2_libfunc = \
4588 init_one_libfunc ("__mips16_truncdfsf2"); \
4591 init_one_libfunc ("__mips16_eqdf2"); \
4593 init_one_libfunc ("__mips16_nedf2"); \
4595 init_one_libfunc ("__mips16_gtdf2"); \
4597 init_one_libfunc ("__mips16_gedf2"); \
4599 init_one_libfunc ("__mips16_ltdf2"); \
4601 init_one_libfunc ("__mips16_ledf2"); \
4603 floatsidf_libfunc = \
4604 init_one_libfunc ("__mips16_floatsidf"); \
4606 init_one_libfunc ("__mips16_fixdfsi"); \
4612 #define DFMODE_NAN \
4613 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4614 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4615 #define SFMODE_NAN \
4616 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4617 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4619 /* Generate calls to memcpy, etc., not bcopy, etc. */
4620 #define TARGET_MEM_FUNCTIONS