1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-97, 1998 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern char *language_string;
32 extern int may_call_alloca;
33 extern char **save_argv;
34 extern int target_flags;
35 extern char *version_string;
37 /* MIPS external variables defined in mips.c. */
41 CMP_SI, /* compare four byte integers */
42 CMP_DI, /* compare eight byte integers */
43 CMP_SF, /* compare single precision floats */
44 CMP_DF, /* compare double precision floats */
45 CMP_MAX /* max comparison type */
48 /* types of delay slot */
50 DELAY_NONE, /* no delay slot */
51 DELAY_LOAD, /* load from memory delay */
52 DELAY_HILO, /* move from/to hi/lo registers */
53 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
56 /* Which processor to schedule for. Since there is no difference between
57 a R2000 and R3000 in terms of the scheduler, we collapse them into
58 just an R3000. The elements of the enumeration must match exactly
59 the cpu attribute in the mips.md machine description. */
75 /* Recast the cpu class to be the cpu attribute. */
76 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
78 /* Which ABI to use. These are constants because abi64.h must check their
79 value at preprocessing time.
81 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
82 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
90 #ifndef MIPS_ABI_DEFAULT
91 /* We define this away so that there is no extra runtime cost if the target
92 doesn't support multiple ABIs. */
93 #define mips_abi ABI_32
98 /* Whether to emit abicalls code sequences or not. */
100 enum mips_abicalls_type {
105 /* Recast the abicalls class to be the abicalls attribute. */
106 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
108 /* Which type of block move to do (whether or not the last store is
109 split out so it can fill a branch delay slot). */
111 enum block_move_type {
112 BLOCK_MOVE_NORMAL, /* generate complete block move */
113 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
114 BLOCK_MOVE_LAST /* generate just the last store */
117 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
118 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
119 extern char *current_function_file; /* filename current function is in */
120 extern int num_source_filenames; /* current .file # */
121 extern int inside_function; /* != 0 if inside of a function */
122 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
123 extern int file_in_function_warning; /* warning given about .file in func */
124 extern int sdb_label_count; /* block start/end next label # */
125 extern int sdb_begin_function_line; /* Starting Line of current function */
126 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
127 extern int g_switch_value; /* value of the -G xx switch */
128 extern int g_switch_set; /* whether -G xx was passed. */
129 extern int sym_lineno; /* sgi next label # for each stmt */
130 extern int set_noreorder; /* # of nested .set noreorder's */
131 extern int set_nomacro; /* # of nested .set nomacro's */
132 extern int set_noat; /* # of nested .set noat's */
133 extern int set_volatile; /* # of nested .set volatile's */
134 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
135 extern int mips_dbx_regno[]; /* Map register # to debug register # */
136 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
137 extern enum cmp_type branch_type; /* what type of branch to use */
138 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
139 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
140 extern int mips_isa; /* architectural level */
141 extern int mips16; /* whether generating mips16 code */
142 extern int mips16_hard_float; /* mips16 without -msoft-float */
143 extern int mips_entry; /* generate entry/exit for mips16 */
144 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
145 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
146 extern char *mips_abi_string; /* for -mabi={32,n32,64} */
147 extern char *mips_entry_string; /* for -mentry */
148 extern char *mips_no_mips16_string; /* for -mno-mips16 */
149 extern int mips_split_addresses; /* perform high/lo_sum support */
150 extern int dslots_load_total; /* total # load related delay slots */
151 extern int dslots_load_filled; /* # filled load delay slots */
152 extern int dslots_jump_total; /* total # jump related delay slots */
153 extern int dslots_jump_filled; /* # filled jump delay slots */
154 extern int dslots_number_nops; /* # of nops needed by previous insn */
155 extern int num_refs[3]; /* # 1/2/3 word references */
156 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
157 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
158 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
159 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
160 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
161 extern int mips_string_length; /* length of strings for mips16 */
162 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
164 /* Functions within mips.c that we reference. Some of these return type
165 HOST_WIDE_INT, so define that here. This is a copy of code in machmode.h.
167 ??? It would be good to try to put this as common code someplace. */
169 #ifndef HOST_BITS_PER_WIDE_INT
171 #if HOST_BITS_PER_LONG > HOST_BITS_PER_INT
172 #define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONG
173 #define HOST_WIDE_INT long
175 #define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_INT
176 #define HOST_WIDE_INT int
181 extern void abort_with_insn ();
182 extern int arith32_operand ();
183 extern int arith_operand ();
184 extern int cmp_op ();
185 extern HOST_WIDE_INT compute_frame_size ();
186 extern int const_float_1_operand ();
187 extern void expand_block_move ();
188 extern int equality_op ();
189 extern void final_prescan_insn ();
190 extern struct rtx_def * function_arg ();
191 extern void function_arg_advance ();
192 extern int function_arg_partial_nregs ();
193 extern int function_arg_pass_by_reference ();
194 extern void function_epilogue ();
195 extern void function_prologue ();
196 extern void gen_conditional_branch ();
197 extern void gen_conditional_move ();
198 extern struct rtx_def * gen_int_relational ();
199 extern void init_cumulative_args ();
200 extern int large_int ();
201 extern void machine_dependent_reorg ();
202 extern int mips_address_cost ();
203 extern void mips_asm_file_end ();
204 extern void mips_asm_file_start ();
205 extern int mips_can_use_return_insn ();
206 extern int mips_const_double_ok ();
207 extern void mips_count_memory_refs ();
208 extern HOST_WIDE_INT mips_debugger_offset ();
209 extern void mips_declare_object ();
210 extern int mips_epilogue_delay_slots ();
211 extern void mips_expand_epilogue ();
212 extern void mips_expand_prologue ();
213 extern int mips_check_split ();
214 extern char *mips_fill_delay_slot ();
215 extern char *mips_move_1word ();
216 extern char *mips_move_2words ();
217 extern void mips_output_double ();
218 extern int mips_output_external ();
219 extern void mips_output_float ();
220 extern void mips_output_filename ();
221 extern void mips_output_lineno ();
222 extern char *output_block_move ();
223 extern void override_options ();
224 extern int pc_or_label_operand ();
225 extern void print_operand_address ();
226 extern void print_operand ();
227 extern void print_options ();
228 extern int reg_or_0_operand ();
229 extern int simple_epilogue_p ();
230 extern int simple_memory_operand ();
231 extern int double_memory_operand ();
232 extern int small_int ();
233 extern void trace ();
234 extern int uns_arith_operand ();
235 extern struct rtx_def * embedded_pic_offset ();
236 extern void mips_order_regs_for_local_alloc ();
237 extern struct rtx_def * mips16_gp_pseudo_reg ();
238 extern struct rtx_def * mips16_gp_offset ();
239 extern int mips16_gp_offset_p ();
240 extern int mips16_constant ();
241 extern int mips16_constant_after_function_p ();
242 extern int build_mips16_call_stub ();
244 /* Recognition functions that return if a condition is true. */
245 extern int address_operand ();
246 extern int call_insn_operand ();
247 extern int const_double_operand ();
248 extern int const_int_operand ();
249 extern int consttable_operand ();
250 extern int general_operand ();
251 extern int immediate_operand ();
252 extern int memory_address_p ();
253 extern int memory_operand ();
254 extern int nonimmediate_operand ();
255 extern int nonmemory_operand ();
256 extern int pic_address_needs_scratch ();
257 extern int register_operand ();
258 extern int scratch_operand ();
259 extern int move_operand ();
260 extern int movdi_operand ();
261 extern int se_register_operand ();
262 extern int se_reg_or_0_operand ();
263 extern int se_uns_arith_operand ();
264 extern int se_arith_operand ();
265 extern int se_nonmemory_operand ();
266 extern int se_nonimmediate_operand ();
267 extern int extend_operator ();
268 extern int highpart_shift_operator ();
269 extern int m16_uimm3_b ();
270 extern int m16_simm4_1 ();
271 extern int m16_nsimm4_1 ();
272 extern int m16_simm5_1 ();
273 extern int m16_nsimm5_1 ();
274 extern int m16_uimm5_4 ();
275 extern int m16_nuimm5_4 ();
276 extern int m16_simm8_1 ();
277 extern int m16_nsimm8_1 ();
278 extern int m16_uimm8_1 ();
279 extern int m16_nuimm8_1 ();
280 extern int m16_uimm8_m1_1 ();
281 extern int m16_uimm8_4 ();
282 extern int m16_nuimm8_4 ();
283 extern int m16_simm8_8 ();
284 extern int m16_nsimm8_8 ();
285 extern int m16_usym8_4 ();
286 extern int m16_usym5_4 ();
288 /* Functions to change what output section we are using. */
289 extern void data_section ();
290 extern void rdata_section ();
291 extern void readonly_data_section ();
292 extern void sdata_section ();
293 extern void text_section ();
294 extern void mips_select_rtx_section ();
295 extern void mips_select_section ();
297 /* Stubs for half-pic support if not OSF/1 reference platform. */
300 #define HALF_PIC_P() 0
301 #define HALF_PIC_NUMBER_PTRS 0
302 #define HALF_PIC_NUMBER_REFS 0
303 #define HALF_PIC_ENCODE(DECL)
304 #define HALF_PIC_DECLARE(NAME)
305 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
306 #define HALF_PIC_ADDRESS_P(X) 0
307 #define HALF_PIC_PTR(X) X
308 #define HALF_PIC_FINISH(STREAM)
312 /* Run-time compilation parameters selecting different hardware subsets. */
314 /* Macros used in the machine description to test the flags. */
316 /* Bits for real switches */
317 #define MASK_INT64 0x00000001 /* ints are 64 bits */
318 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
319 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
320 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
321 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
322 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
323 #define MASK_STATS 0x00000040 /* print statistics to stderr */
324 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
325 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
326 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
327 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
328 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
329 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
330 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
331 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
332 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
333 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
334 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
335 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
336 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
337 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
338 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
339 #define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */
340 #define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */
342 /* Dummy switches used only in spec's*/
343 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
345 /* Debug switches, not documented */
346 #define MASK_DEBUG 0 /* Eliminate version # in .s file */
347 #define MASK_DEBUG_A 0x40000000 /* don't allow <label>($reg) addrs */
348 #define MASK_DEBUG_B 0x20000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
349 #define MASK_DEBUG_C 0x10000000 /* don't expand seq, etc. */
350 #define MASK_DEBUG_D 0 /* don't do define_split's */
351 #define MASK_DEBUG_E 0 /* function_arg debug */
352 #define MASK_DEBUG_F 0
353 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
354 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
355 #define MASK_DEBUG_I 0 /* unused */
357 /* r4000 64 bit sizes */
358 #define TARGET_INT64 (target_flags & MASK_INT64)
359 #define TARGET_LONG64 (target_flags & MASK_LONG64)
360 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
361 #define TARGET_64BIT (target_flags & MASK_64BIT)
363 /* Mips vs. GNU linker */
364 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
366 /* generate mips 3900 insns */
367 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
369 /* Mips vs. GNU assembler */
370 #define TARGET_GAS (target_flags & MASK_GAS)
371 #define TARGET_UNIX_ASM (!TARGET_GAS)
372 #define TARGET_MIPS_AS TARGET_UNIX_ASM
375 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
376 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
377 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
378 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
379 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
380 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
381 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
382 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
383 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
384 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
386 /* Reg. Naming in .s ($21 vs. $a0) */
387 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
389 /* Optimize for Sdata/Sbss */
390 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
392 /* print program statistics */
393 #define TARGET_STATS (target_flags & MASK_STATS)
395 /* call memcpy instead of inline code */
396 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
398 /* .abicalls, etc from Pyramid V.4 */
399 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
401 /* OSF pic references to externs */
402 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
404 /* software floating point */
405 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
406 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
408 /* always call through a register */
409 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
411 /* generate embedded PIC code;
413 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
415 /* for embedded systems, optimize for
416 reduced RAM space instead of for
418 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
420 /* generate big endian code. */
421 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
423 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
424 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
426 #define TARGET_MAD (target_flags & MASK_MAD)
428 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
430 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
431 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
433 /* This is true if we must enable the assembly language file switching
436 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
438 /* We must disable the function end stabs when doing the file switching trick,
439 because the Lscope stabs end up in the wrong place, making it impossible
440 to debug the resulting code. */
441 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
443 /* Generate mips16 code */
444 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
446 /* Macro to define tables used to set the flags.
447 This is a list in braces of pairs in braces,
448 each pair being { "NAME", VALUE }
449 where VALUE is the bits to set or minus the bits to clear.
450 An empty string NAME is used to identify the default VALUE. */
452 #define TARGET_SWITCHES \
454 {"int64", MASK_INT64 | MASK_LONG64}, \
455 {"long64", MASK_LONG64}, \
456 {"split-addresses", MASK_SPLIT_ADDR}, \
457 {"no-split-addresses", -MASK_SPLIT_ADDR}, \
458 {"mips-as", -MASK_GAS}, \
460 {"rnames", MASK_NAME_REGS}, \
461 {"no-rnames", -MASK_NAME_REGS}, \
462 {"gpOPT", MASK_GPOPT}, \
463 {"gpopt", MASK_GPOPT}, \
464 {"no-gpOPT", -MASK_GPOPT}, \
465 {"no-gpopt", -MASK_GPOPT}, \
466 {"stats", MASK_STATS}, \
467 {"no-stats", -MASK_STATS}, \
468 {"memcpy", MASK_MEMCPY}, \
469 {"no-memcpy", -MASK_MEMCPY}, \
470 {"mips-tfile", MASK_MIPS_TFILE}, \
471 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
472 {"soft-float", MASK_SOFT_FLOAT}, \
473 {"hard-float", -MASK_SOFT_FLOAT}, \
474 {"fp64", MASK_FLOAT64}, \
475 {"fp32", -MASK_FLOAT64}, \
476 {"gp64", MASK_64BIT}, \
477 {"gp32", -MASK_64BIT}, \
478 {"abicalls", MASK_ABICALLS}, \
479 {"no-abicalls", -MASK_ABICALLS}, \
480 {"half-pic", MASK_HALF_PIC}, \
481 {"no-half-pic", -MASK_HALF_PIC}, \
482 {"long-calls", MASK_LONG_CALLS}, \
483 {"no-long-calls", -MASK_LONG_CALLS}, \
484 {"embedded-pic", MASK_EMBEDDED_PIC}, \
485 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
486 {"embedded-data", MASK_EMBEDDED_DATA}, \
487 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
488 {"eb", MASK_BIG_ENDIAN}, \
489 {"el", -MASK_BIG_ENDIAN}, \
490 {"single-float", MASK_SINGLE_FLOAT}, \
491 {"double-float", -MASK_SINGLE_FLOAT}, \
493 {"no-mad", -MASK_MAD}, \
494 {"fix4300", MASK_4300_MUL_FIX}, \
495 {"no-fix4300", -MASK_4300_MUL_FIX}, \
496 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
497 {"3900", MASK_MIPS3900}, \
498 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV}, \
499 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV}, \
500 {"check-range-division",MASK_CHECK_RANGE_DIV}, \
501 {"no-check-range-division",-MASK_CHECK_RANGE_DIV}, \
502 {"debug", MASK_DEBUG}, \
503 {"debuga", MASK_DEBUG_A}, \
504 {"debugb", MASK_DEBUG_B}, \
505 {"debugc", MASK_DEBUG_C}, \
506 {"debugd", MASK_DEBUG_D}, \
507 {"debuge", MASK_DEBUG_E}, \
508 {"debugf", MASK_DEBUG_F}, \
509 {"debugg", MASK_DEBUG_G}, \
510 {"debugh", MASK_DEBUG_H}, \
511 {"debugi", MASK_DEBUG_I}, \
512 {"", (TARGET_DEFAULT \
513 | TARGET_CPU_DEFAULT \
514 | TARGET_ENDIAN_DEFAULT)} \
517 /* Default target_flags if no switches are specified */
519 #ifndef TARGET_DEFAULT
520 #define TARGET_DEFAULT 0
523 #ifndef TARGET_CPU_DEFAULT
524 #define TARGET_CPU_DEFAULT 0
527 #ifndef TARGET_ENDIAN_DEFAULT
529 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
531 #define TARGET_ENDIAN_DEFAULT 0
535 #ifndef MULTILIB_DEFAULTS
536 #if TARGET_ENDIAN_DEFAULT == 0
537 #define MULTILIB_DEFAULTS { "EL", "mips1" }
539 #define MULTILIB_DEFAULTS { "EB", "mips1" }
543 /* We must pass -EL to the linker by default for little endian embedded
544 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
545 linker will default to using big-endian output files. The OUTPUT_FORMAT
546 line must be in the linker script, otherwise -EB/-EL will not work. */
548 #ifndef LINKER_ENDIAN_SPEC
549 #if TARGET_ENDIAN_DEFAULT == 0
550 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
552 #define LINKER_ENDIAN_SPEC ""
556 /* This macro is similar to `TARGET_SWITCHES' but defines names of
557 command options that have values. Its definition is an
558 initializer with a subgrouping for each command option.
560 Each subgrouping contains a string constant, that defines the
561 fixed part of the option name, and the address of a variable.
562 The variable, type `char *', is set to the variable part of the
563 given option if the fixed part matches. The actual option name
564 is made by appending `-m' to the specified name.
566 Here is an example which defines `-mshort-data-NUMBER'. If the
567 given option is `-mshort-data-512', the variable `m88k_short_data'
568 will be set to the string `"512"'.
570 extern char *m88k_short_data;
571 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
573 #define TARGET_OPTIONS \
575 SUBTARGET_TARGET_OPTIONS \
576 { "cpu=", &mips_cpu_string }, \
577 { "ips", &mips_isa_string }, \
578 { "entry", &mips_entry_string }, \
579 { "no-mips16", &mips_no_mips16_string } \
582 /* This is meant to be redefined in the host dependent files. */
583 #define SUBTARGET_TARGET_OPTIONS
585 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
587 /* Generate three-operand multiply instructions for both SImode and DImode. */
588 #define GENERATE_MULT3 (TARGET_MIPS3900 \
591 /* Macros to decide whether certain features are available or not,
592 depending on the instruction set architecture level. */
594 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
595 #define HAVE_SQRT_P() (mips_isa >= 2)
597 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
598 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
599 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
600 target_flags, and -mgp64 sets MASK_64BIT.
602 Setting MASK_64BIT in target_flags will cause gcc to assume that
603 registers are 64 bits wide. int, long and void * will be 32 bit;
604 this may be changed with -mint64 or -mlong64.
606 The gen* programs link code that refers to MASK_64BIT. They don't
607 actually use the information in target_flags; they just refer to
610 /* Switch Recognition by gcc.c. Add -G xx support */
612 #ifdef SWITCH_TAKES_ARG
613 #undef SWITCH_TAKES_ARG
616 #define SWITCH_TAKES_ARG(CHAR) \
617 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
619 /* Sometimes certain combinations of command options do not make sense
620 on a particular target machine. You can define a macro
621 `OVERRIDE_OPTIONS' to take account of this. This macro, if
622 defined, is executed once just after all the command options have
625 On the MIPS, it is used to handle -G. We also use it to set up all
626 of the tables referenced in the other macros. */
628 #define OVERRIDE_OPTIONS override_options ()
630 /* Zero or more C statements that may conditionally modify two
631 variables `fixed_regs' and `call_used_regs' (both of type `char
632 []') after they have been initialized from the two preceding
635 This is necessary in case the fixed or call-clobbered registers
636 depend on target flags.
638 You need not define this macro if it has no work to do.
640 If the usage of an entire class of registers depends on the target
641 flags, you may indicate this to GCC by using this macro to modify
642 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
643 the classes which should not be used by GCC. Also define the macro
644 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
645 letter for a class that shouldn't be used.
647 (However, if this class is not included in `GENERAL_REGS' and all
648 of the insn patterns whose constraints permit this class are
649 controlled by target switches, then GCC will automatically avoid
650 using these registers when the target switches are opposed to
653 #define CONDITIONAL_REGISTER_USAGE \
656 if (!TARGET_HARD_FLOAT) \
660 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
661 fixed_regs[regno] = call_used_regs[regno] = 1; \
662 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
663 fixed_regs[regno] = call_used_regs[regno] = 1; \
665 else if (mips_isa < 4) \
669 /* We only have a single condition code register. We \
670 implement this by hiding all the condition code registers, \
671 and generating RTL that refers directly to ST_REG_FIRST. */ \
672 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
673 fixed_regs[regno] = call_used_regs[regno] = 1; \
675 /* In mips16 mode, we permit the $t temporary registers to be used \
676 for reload. We prohibit the unused $s registers, since they \
677 are caller saved, and saving them via a mips16 register would \
678 probably waste more time than just reloading the value. */ \
681 fixed_regs[18] = call_used_regs[18] = 1; \
682 fixed_regs[19] = call_used_regs[19] = 1; \
683 fixed_regs[20] = call_used_regs[20] = 1; \
684 fixed_regs[21] = call_used_regs[21] = 1; \
685 fixed_regs[22] = call_used_regs[22] = 1; \
686 fixed_regs[23] = call_used_regs[23] = 1; \
687 fixed_regs[26] = call_used_regs[26] = 1; \
688 fixed_regs[27] = call_used_regs[27] = 1; \
689 fixed_regs[30] = call_used_regs[30] = 1; \
691 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
695 /* This is meant to be redefined in the host dependent files. */
696 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
698 /* Show we can debug even without a frame pointer. */
699 #define CAN_DEBUG_WITHOUT_FP
701 /* Complain about missing specs and predefines that should be defined in each
702 of the target tm files to override the defaults. This is mostly a place-
703 holder until I can get each of the files updated [mm]. */
705 #if defined(OSF_OS) \
706 || defined(DECSTATION) \
707 || defined(SGI_TARGET) \
708 || defined(MIPS_NEWS) \
709 || defined(MIPS_SYSV) \
710 || defined(MIPS_SVR4) \
711 || defined(MIPS_BSD43)
713 #ifndef CPP_PREDEFINES
714 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
718 #error "Define LIB_SPEC in the appropriate tm.h file"
721 #ifndef STARTFILE_SPEC
722 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
726 #error "Define MACHINE_TYPE in the appropriate tm.h file"
730 /* Tell collect what flags to pass to nm. */
732 #define NM_FLAGS "-Bn"
736 /* Names to predefine in the preprocessor for this target machine. */
738 #ifndef CPP_PREDEFINES
739 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
740 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
741 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
744 /* Assembler specs. */
746 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
749 #define MIPS_AS_ASM_SPEC "\
750 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
751 %{pipe: %e-pipe is not supported.} \
752 %{K} %(subtarget_mips_as_asm_spec)"
754 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
755 rather than gas. It may be overridden by subtargets. */
757 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
758 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
761 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
764 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
766 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
767 GAS_ASM_SPEC as the default, depending upon the value of
770 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
773 #define TARGET_ASM_SPEC "\
774 %{mmips-as: %(mips_as_asm_spec)} \
775 %{!mmips-as: %(gas_asm_spec)}"
779 #define TARGET_ASM_SPEC "\
780 %{!mgas: %(mips_as_asm_spec)} \
781 %{mgas: %(gas_asm_spec)}"
785 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
786 to the assembler. It may be overridden by subtargets. */
787 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
788 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
790 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
793 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
794 the assembler. It may be overridden by subtargets. */
795 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
796 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
797 %{g} %{g0} %{g1} %{g2} %{g3} \
798 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
799 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
800 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
801 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
804 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
805 overridden by subtargets. */
807 #ifndef SUBTARGET_ASM_SPEC
808 #define SUBTARGET_ASM_SPEC ""
811 /* ASM_SPEC is the set of arguments to pass to the assembler. */
814 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
815 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
816 %(subtarget_asm_optimizing_spec) \
817 %(subtarget_asm_debugging_spec) \
819 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
821 %(subtarget_asm_spec)"
823 /* Specify to run a post-processor, mips-tfile after the assembler
824 has run to stuff the mips debug information into the object file.
825 This is needed because the $#!%^ MIPS assembler provides no way
826 of specifying such information in the assembly file. If we are
827 cross compiling, disable mips-tfile unless the user specifies
830 #ifndef ASM_FINAL_SPEC
831 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
833 #define ASM_FINAL_SPEC "\
834 %{mmips-as: %{!mno-mips-tfile: \
835 \n mips-tfile %{v*: -v} \
837 %{!K: %{save-temps: -I %b.o~}} \
838 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
839 %{.s:%i} %{!.s:%g.s}}}"
843 #define ASM_FINAL_SPEC "\
844 %{!mgas: %{!mno-mips-tfile: \
845 \n mips-tfile %{v*: -v} \
847 %{!K: %{save-temps: -I %b.o~}} \
848 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
849 %{.s:%i} %{!.s:%g.s}}}"
852 #endif /* ASM_FINAL_SPEC */
854 /* Redefinition of libraries used. Mips doesn't support normal
855 UNIX style profiling via calling _mcount. It does offer
856 profiling that samples the PC, so do what we can... */
859 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
862 /* Extra switches sometimes passed to the linker. */
863 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
864 will interpret it as a -b option. */
868 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
869 %{bestGnum} %{shared} %{non_shared} \
870 %(linker_endian_spec)"
871 #endif /* LINK_SPEC defined */
873 /* Specs for the compiler proper */
875 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
876 overridden by subtargets. */
877 #ifndef SUBTARGET_CC1_SPEC
878 #define SUBTARGET_CC1_SPEC ""
881 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
885 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
886 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
887 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
888 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
889 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
890 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
891 %{m4650:-mcpu=r4650} \
892 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
893 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
894 %{pic-none: -mno-half-pic} \
895 %{pic-lib: -mhalf-pic} \
896 %{pic-extern: -mhalf-pic} \
897 %{pic-calls: -mhalf-pic} \
899 %(subtarget_cc1_spec) "
902 /* Preprocessor specs. */
904 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
905 be overridden by subtargets. */
907 #ifndef SUBTARGET_CPP_SIZE_SPEC
908 #define SUBTARGET_CPP_SIZE_SPEC "\
909 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
910 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
913 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
914 overridden by subtargets. */
915 #ifndef SUBTARGET_CPP_SPEC
916 #define SUBTARGET_CPP_SPEC ""
919 /* If we're using 64bit longs, then we have to define __LONG_MAX__
920 correctly. Similarly for 64bit ints and __INT_MAX__. */
921 #ifndef LONG_MAX_SPEC
922 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
923 #define LONG_MAX_SPEC "%{!mno-long64:-D__LONG_MAX__=9223372036854775807L}"
925 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
929 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
933 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
934 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
935 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
936 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
937 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
938 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
939 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
940 %(subtarget_cpp_size_spec) \
941 %{mips3:-U__mips -D__mips=3 -D__mips64} \
942 %{mips4:-U__mips -D__mips=4 -D__mips64} \
943 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
944 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
945 %{m4650:%{!msoft-float:-D__mips_single_float}} \
946 %{msoft-float:-D__mips_soft_float} \
947 %{mabi=eabi:-D__mips_eabi} \
948 %{mips16:%{!mno-mips16:-D__mips16}} \
949 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
950 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
952 %(subtarget_cpp_spec) "
955 /* This macro defines names of additional specifications to put in the specs
956 that can be used in various specifications like CC1_SPEC. Its definition
957 is an initializer with a subgrouping for each command option.
959 Each subgrouping contains a string constant, that defines the
960 specification name, and a string constant that used by the GNU CC driver
963 Do not define this macro if it does not need to do anything. */
965 #define EXTRA_SPECS \
966 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
967 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
968 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
969 { "long_max_spec", LONG_MAX_SPEC }, \
970 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
971 { "gas_asm_spec", GAS_ASM_SPEC }, \
972 { "target_asm_spec", TARGET_ASM_SPEC }, \
973 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
974 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
975 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
976 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
977 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
978 SUBTARGET_EXTRA_SPECS
980 #ifndef SUBTARGET_EXTRA_SPECS
981 #define SUBTARGET_EXTRA_SPECS
984 /* If defined, this macro is an additional prefix to try after
985 `STANDARD_EXEC_PREFIX'. */
987 #ifndef MD_EXEC_PREFIX
988 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
991 #ifndef MD_STARTFILE_PREFIX
992 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
996 /* Print subsidiary information on the compiler version in use. */
998 #define MIPS_VERSION "[AL 1.1, MM 40]"
1000 #ifndef MACHINE_TYPE
1001 #define MACHINE_TYPE "BSD Mips"
1004 #ifndef TARGET_VERSION_INTERNAL
1005 #define TARGET_VERSION_INTERNAL(STREAM) \
1006 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1009 #ifndef TARGET_VERSION
1010 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1014 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1015 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1016 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1018 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1019 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1022 /* By default, turn on GDB extensions. */
1023 #define DEFAULT_GDB_EXTENSIONS 1
1025 /* If we are passing smuggling stabs through the MIPS ECOFF object
1026 format, put a comment in front of the .stab<x> operation so
1027 that the MIPS assembler does not choke. The mips-tfile program
1028 will correctly put the stab into the object file. */
1030 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1031 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1032 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1034 /* Local compiler-generated symbols must have a prefix that the assembler
1035 understands. By default, this is $, although some targets (e.g.,
1036 NetBSD-ELF) need to override this. */
1038 #ifndef LOCAL_LABEL_PREFIX
1039 #define LOCAL_LABEL_PREFIX "$"
1042 /* By default on the mips, external symbols do not have an underscore
1043 prepended, but some targets (e.g., NetBSD) require this. */
1045 #ifndef USER_LABEL_PREFIX
1046 #define USER_LABEL_PREFIX ""
1049 /* Forward references to tags are allowed. */
1050 #define SDB_ALLOW_FORWARD_REFERENCES
1052 /* Unknown tags are also allowed. */
1053 #define SDB_ALLOW_UNKNOWN_REFERENCES
1055 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1056 since the length can run past this up to a continuation point. */
1057 #define DBX_CONTIN_LENGTH 1500
1059 /* How to renumber registers for dbx and gdb. */
1060 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1062 /* The mapping from gcc register number to DWARF 2 CFA column number.
1063 This mapping does not allow for tracking register 0, since SGI's broken
1064 dwarf reader thinks column 0 is used for the frame address, but since
1065 register 0 is fixed this is not a problem. */
1066 #define DWARF_FRAME_REGNUM(REG) \
1067 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1069 /* The DWARF 2 CFA column which tracks the return address. */
1070 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1072 /* Before the prologue, RA lives in r31. */
1073 #define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
1075 /* Overrides for the COFF debug format. */
1076 #define PUT_SDB_SCL(a) \
1078 extern FILE *asm_out_text_file; \
1079 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1082 #define PUT_SDB_INT_VAL(a) \
1084 extern FILE *asm_out_text_file; \
1085 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1088 #define PUT_SDB_VAL(a) \
1090 extern FILE *asm_out_text_file; \
1091 fputs ("\t.val\t", asm_out_text_file); \
1092 output_addr_const (asm_out_text_file, (a)); \
1093 fputc (';', asm_out_text_file); \
1096 #define PUT_SDB_DEF(a) \
1098 extern FILE *asm_out_text_file; \
1099 fprintf (asm_out_text_file, "\t%s.def\t", \
1100 (TARGET_GAS) ? "" : "#"); \
1101 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1102 fputc (';', asm_out_text_file); \
1105 #define PUT_SDB_PLAIN_DEF(a) \
1107 extern FILE *asm_out_text_file; \
1108 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1109 (TARGET_GAS) ? "" : "#", (a)); \
1112 #define PUT_SDB_ENDEF \
1114 extern FILE *asm_out_text_file; \
1115 fprintf (asm_out_text_file, "\t.endef\n"); \
1118 #define PUT_SDB_TYPE(a) \
1120 extern FILE *asm_out_text_file; \
1121 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1124 #define PUT_SDB_SIZE(a) \
1126 extern FILE *asm_out_text_file; \
1127 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1130 #define PUT_SDB_DIM(a) \
1132 extern FILE *asm_out_text_file; \
1133 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1136 #ifndef PUT_SDB_START_DIM
1137 #define PUT_SDB_START_DIM \
1139 extern FILE *asm_out_text_file; \
1140 fprintf (asm_out_text_file, "\t.dim\t"); \
1144 #ifndef PUT_SDB_NEXT_DIM
1145 #define PUT_SDB_NEXT_DIM(a) \
1147 extern FILE *asm_out_text_file; \
1148 fprintf (asm_out_text_file, "%d,", a); \
1152 #ifndef PUT_SDB_LAST_DIM
1153 #define PUT_SDB_LAST_DIM(a) \
1155 extern FILE *asm_out_text_file; \
1156 fprintf (asm_out_text_file, "%d;", a); \
1160 #define PUT_SDB_TAG(a) \
1162 extern FILE *asm_out_text_file; \
1163 fprintf (asm_out_text_file, "\t.tag\t"); \
1164 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1165 fputc (';', asm_out_text_file); \
1168 /* For block start and end, we create labels, so that
1169 later we can figure out where the correct offset is.
1170 The normal .ent/.end serve well enough for functions,
1171 so those are just commented out. */
1173 #define PUT_SDB_BLOCK_START(LINE) \
1175 extern FILE *asm_out_text_file; \
1176 fprintf (asm_out_text_file, \
1177 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1178 LOCAL_LABEL_PREFIX, \
1180 (TARGET_GAS) ? "" : "#", \
1181 LOCAL_LABEL_PREFIX, \
1184 sdb_label_count++; \
1187 #define PUT_SDB_BLOCK_END(LINE) \
1189 extern FILE *asm_out_text_file; \
1190 fprintf (asm_out_text_file, \
1191 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1192 LOCAL_LABEL_PREFIX, \
1194 (TARGET_GAS) ? "" : "#", \
1195 LOCAL_LABEL_PREFIX, \
1198 sdb_label_count++; \
1201 #define PUT_SDB_FUNCTION_START(LINE)
1203 #define PUT_SDB_FUNCTION_END(LINE) \
1205 extern FILE *asm_out_text_file; \
1206 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1209 #define PUT_SDB_EPILOGUE_END(NAME)
1211 #define PUT_SDB_SRC_FILE(FILENAME) \
1213 extern FILE *asm_out_text_file; \
1214 output_file_directive (asm_out_text_file, (FILENAME)); \
1217 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1218 sprintf ((BUFFER), ".%dfake", (NUMBER));
1220 /* Correct the offset of automatic variables and arguments. Note that
1221 the MIPS debug format wants all automatic variables and arguments
1222 to be in terms of the virtual frame pointer (stack pointer before
1223 any adjustment in the function), while the MIPS 3.0 linker wants
1224 the frame pointer to be the stack pointer after the initial
1227 #define DEBUGGER_AUTO_OFFSET(X) \
1228 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1229 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1230 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1232 /* Tell collect that the object format is ECOFF */
1233 #ifndef OBJECT_FORMAT_ROSE
1234 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1235 #define EXTENDED_COFF /* ECOFF, not normal coff */
1238 #if 0 /* These definitions normally have no effect because
1239 MIPS systems define USE_COLLECT2, so
1240 assemble_constructor does nothing anyway. */
1242 /* Don't use the default definitions, because we don't have gld.
1243 Also, we don't want stabs when generating ECOFF output.
1244 Instead we depend on collect to handle these. */
1246 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1247 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1251 /* Target machine storage layout */
1253 /* Define in order to support both big and little endian float formats
1254 in the same gcc binary. */
1255 #define REAL_ARITHMETIC
1257 /* Define this if most significant bit is lowest numbered
1258 in instructions that operate on numbered bit-fields.
1260 #define BITS_BIG_ENDIAN 0
1262 /* Define this if most significant byte of a word is the lowest numbered. */
1263 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1265 /* Define this if most significant word of a multiword number is the lowest. */
1266 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1268 /* Define this to set the endianness to use in libgcc2.c, which can
1269 not depend on target_flags. */
1270 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1271 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1273 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1276 /* Number of bits in an addressable storage unit */
1277 #define BITS_PER_UNIT 8
1279 /* Width in bits of a "word", which is the contents of a machine register.
1280 Note that this is not necessarily the width of data type `int';
1281 if using 16-bit ints on a 68000, this would still be 32.
1282 But on a machine with 16-bit registers, this would be 16. */
1283 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1284 #define MAX_BITS_PER_WORD 64
1286 /* Width of a word, in units (bytes). */
1287 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1288 #define MIN_UNITS_PER_WORD 4
1290 /* For MIPS, width of a floating point register. */
1291 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1293 /* A C expression for the size in bits of the type `int' on the
1294 target machine. If you don't define this, the default is one
1296 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1297 #define MAX_INT_TYPE_SIZE 64
1299 /* Tell the preprocessor the maximum size of wchar_t. */
1300 #ifndef MAX_WCHAR_TYPE_SIZE
1301 #ifndef WCHAR_TYPE_SIZE
1302 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1306 /* A C expression for the size in bits of the type `short' on the
1307 target machine. If you don't define this, the default is half a
1308 word. (If this would be less than one storage unit, it is
1309 rounded up to one unit.) */
1310 #define SHORT_TYPE_SIZE 16
1312 /* A C expression for the size in bits of the type `long' on the
1313 target machine. If you don't define this, the default is one
1315 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1316 #define MAX_LONG_TYPE_SIZE 64
1318 /* A C expression for the size in bits of the type `long long' on the
1319 target machine. If you don't define this, the default is two
1321 #define LONG_LONG_TYPE_SIZE 64
1323 /* A C expression for the size in bits of the type `char' on the
1324 target machine. If you don't define this, the default is one
1325 quarter of a word. (If this would be less than one storage unit,
1326 it is rounded up to one unit.) */
1327 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1329 /* A C expression for the size in bits of the type `float' on the
1330 target machine. If you don't define this, the default is one
1332 #define FLOAT_TYPE_SIZE 32
1334 /* A C expression for the size in bits of the type `double' on the
1335 target machine. If you don't define this, the default is two
1337 #define DOUBLE_TYPE_SIZE 64
1339 /* A C expression for the size in bits of the type `long double' on
1340 the target machine. If you don't define this, the default is two
1342 #define LONG_DOUBLE_TYPE_SIZE 64
1344 /* Width in bits of a pointer.
1345 See also the macro `Pmode' defined below. */
1346 #ifndef POINTER_SIZE
1347 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1350 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1351 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1353 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1354 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1356 /* Allocation boundary (in *bits*) for the code of a function. */
1357 #define FUNCTION_BOUNDARY 32
1359 /* Alignment of field after `int : 0' in a structure. */
1360 #define EMPTY_FIELD_BOUNDARY 32
1362 /* Every structure's size must be a multiple of this. */
1363 /* 8 is observed right on a DECstation and on riscos 4.02. */
1364 #define STRUCTURE_SIZE_BOUNDARY 8
1366 /* There is no point aligning anything to a rounder boundary than this. */
1367 #define BIGGEST_ALIGNMENT 64
1369 /* Set this nonzero if move instructions will actually fail to work
1370 when given unaligned data. */
1371 #define STRICT_ALIGNMENT 1
1373 /* Define this if you wish to imitate the way many other C compilers
1374 handle alignment of bitfields and the structures that contain
1377 The behavior is that the type written for a bitfield (`int',
1378 `short', or other integer type) imposes an alignment for the
1379 entire structure, as if the structure really did contain an
1380 ordinary field of that type. In addition, the bitfield is placed
1381 within the structure so that it would fit within such a field,
1382 not crossing a boundary for it.
1384 Thus, on most machines, a bitfield whose type is written as `int'
1385 would not cross a four-byte boundary, and would force four-byte
1386 alignment for the whole structure. (The alignment used may not
1387 be four bytes; it is controlled by the other alignment
1390 If the macro is defined, its definition should be a C expression;
1391 a nonzero value for the expression enables this behavior. */
1393 #define PCC_BITFIELD_TYPE_MATTERS 1
1395 /* If defined, a C expression to compute the alignment given to a
1396 constant that is being placed in memory. CONSTANT is the constant
1397 and ALIGN is the alignment that the object would ordinarily have.
1398 The value of this macro is used instead of that alignment to align
1401 If this macro is not defined, then ALIGN is used.
1403 The typical use of this macro is to increase alignment for string
1404 constants to be word aligned so that `strcpy' calls that copy
1405 constants can be done inline. */
1407 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1408 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1409 && (ALIGN) < BITS_PER_WORD \
1413 /* If defined, a C expression to compute the alignment for a static
1414 variable. TYPE is the data type, and ALIGN is the alignment that
1415 the object would ordinarily have. The value of this macro is used
1416 instead of that alignment to align the object.
1418 If this macro is not defined, then ALIGN is used.
1420 One use of this macro is to increase alignment of medium-size
1421 data to make it all fit in fewer cache lines. Another is to
1422 cause character arrays to be word-aligned so that `strcpy' calls
1423 that copy constants to character arrays can be done inline. */
1425 #undef DATA_ALIGNMENT
1426 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1427 ((((ALIGN) < BITS_PER_WORD) \
1428 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1429 || TREE_CODE (TYPE) == UNION_TYPE \
1430 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1432 /* Define this macro if an argument declared as `char' or `short' in a
1433 prototype should actually be passed as an `int'. In addition to
1434 avoiding errors in certain cases of mismatch, it also makes for
1435 better code on certain machines. */
1437 #define PROMOTE_PROTOTYPES
1439 /* Define if operations between registers always perform the operation
1440 on the full register even if a narrower mode is specified. */
1441 #define WORD_REGISTER_OPERATIONS
1443 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1444 will either zero-extend or sign-extend. The value of this macro should
1445 be the code that says which one of the two operations is implicitly
1446 done, NIL if none. */
1447 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1449 /* Define this macro if it is advisable to hold scalars in registers
1450 in a wider mode than that declared by the program. In such cases,
1451 the value is constrained to be within the bounds of the declared
1452 type, but kept valid in the wider mode. The signedness of the
1453 extension may differ from that of the type.
1455 We promote any value smaller than SImode up to SImode. We don't
1456 want to promote to DImode when in 64 bit mode, because that would
1457 prevent us from using the faster SImode multiply and divide
1460 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1461 if (GET_MODE_CLASS (MODE) == MODE_INT \
1462 && GET_MODE_SIZE (MODE) < 4) \
1465 /* Define this if function arguments should also be promoted using the above
1468 #define PROMOTE_FUNCTION_ARGS
1470 /* Likewise, if the function return value is promoted. */
1472 #define PROMOTE_FUNCTION_RETURN
1474 /* Standard register usage. */
1476 /* Number of actual hardware registers.
1477 The hardware registers are assigned numbers for the compiler
1478 from 0 to just below FIRST_PSEUDO_REGISTER.
1479 All registers that the compiler knows about must be given numbers,
1480 even those that are not normally considered general registers.
1482 On the Mips, we have 32 integer registers, 32 floating point
1483 registers, 8 condition code registers, and the special registers
1484 hi, lo, hilo, and rap. The 8 condition code registers are only
1485 used if mips_isa >= 4. The hilo register is only used in 64 bit
1486 mode. It represents a 64 bit value stored as two 32 bit values in
1487 the hi and lo registers; this is the result of the mult
1488 instruction. rap is a pointer to the stack where the return
1489 address reg ($31) was stored. This is needed for C++ exception
1492 #define FIRST_PSEUDO_REGISTER 76
1494 /* 1 for registers that have pervasive standard uses
1495 and are not available for the register allocator.
1497 On the MIPS, see conventions, page D-2 */
1499 #define FIXED_REGISTERS \
1501 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1503 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1504 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1505 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1509 /* 1 for registers not available across function calls.
1510 These must include the FIXED_REGISTERS and also any
1511 registers that can be used without being saved.
1512 The latter must include the registers where values are returned
1513 and the register where structure-value addresses are passed.
1514 Aside from that, you can include as many other registers as you like. */
1516 #define CALL_USED_REGISTERS \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1520 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1521 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1522 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1526 /* Internal macros to classify a register number as to whether it's a
1527 general purpose register, a floating point register, a
1528 multiply/divide register, or a status register. */
1530 #define GP_REG_FIRST 0
1531 #define GP_REG_LAST 31
1532 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1533 #define GP_DBX_FIRST 0
1535 #define FP_REG_FIRST 32
1536 #define FP_REG_LAST 63
1537 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1538 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1540 #define MD_REG_FIRST 64
1541 #define MD_REG_LAST 66
1542 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1544 #define ST_REG_FIRST 67
1545 #define ST_REG_LAST 74
1546 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1548 #define RAP_REG_NUM 75
1550 #define AT_REGNUM (GP_REG_FIRST + 1)
1551 #define HI_REGNUM (MD_REG_FIRST + 0)
1552 #define LO_REGNUM (MD_REG_FIRST + 1)
1553 #define HILO_REGNUM (MD_REG_FIRST + 2)
1555 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1556 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1557 should be used instead. */
1558 #define FPSW_REGNUM ST_REG_FIRST
1560 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1561 #define M16_REG_P(REGNO) \
1562 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1563 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1564 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1565 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1567 /* Return number of consecutive hard regs needed starting at reg REGNO
1568 to hold something of mode MODE.
1569 This is ordinarily the length in words of a value of mode MODE
1570 but can be less for certain modes in special long registers.
1572 On the MIPS, all general registers are one word long. Except on
1573 the R4000 with the FR bit set, the floating point uses register
1574 pairs, with the second register not being allocable. */
1576 #define HARD_REGNO_NREGS(REGNO, MODE) \
1577 (! FP_REG_P (REGNO) \
1578 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1579 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1581 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1582 MODE. In 32 bit mode, require that DImode and DFmode be in even
1583 registers. For DImode, this makes some of the insns easier to
1584 write, since you don't have to worry about a DImode value in
1585 registers 3 & 4, producing a result in 4 & 5.
1587 To make the code simpler HARD_REGNO_MODE_OK now just references an
1588 array built in override_options. Because machmodes.h is not yet
1589 included before this file is processed, the MODE bound can't be
1592 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1594 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1595 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1597 /* Value is 1 if it is a good idea to tie two pseudo registers
1598 when one has mode MODE1 and one has mode MODE2.
1599 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1600 for any hard reg, then this must be 0 for correct output. */
1601 #define MODES_TIEABLE_P(MODE1, MODE2) \
1602 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1603 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1604 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1605 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1607 /* MIPS pc is not overloaded on a register. */
1608 /* #define PC_REGNUM xx */
1610 /* Register to use for pushing function arguments. */
1611 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1613 /* Offset from the stack pointer to the first available location. Use
1614 the default value zero. */
1615 /* #define STACK_POINTER_OFFSET 0 */
1617 /* Base register for access to local variables of the function. We
1618 pretend that the frame pointer is $1, and then eliminate it to
1619 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1620 a fixed register, and will not be used for anything else. */
1621 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1623 /* $30 is not available on the mips16, so we use $17 as the frame
1625 #define HARD_FRAME_POINTER_REGNUM \
1626 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1628 /* Value should be nonzero if functions must have frame pointers.
1629 Zero means the frame pointer need not be set up (and parms
1630 may be accessed via the stack pointer) in functions that seem suitable.
1631 This is computed in `reload', in reload1.c. */
1632 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1634 /* Base register for access to arguments of the function. */
1635 #define ARG_POINTER_REGNUM GP_REG_FIRST
1637 /* Fake register that holds the address on the stack of the
1638 current function's return address. */
1639 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1641 /* Register in which static-chain is passed to a function. */
1642 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1644 /* If the structure value address is passed in a register, then
1645 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1646 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1648 /* If the structure value address is not passed in a register, define
1649 `STRUCT_VALUE' as an expression returning an RTX for the place
1650 where the address is passed. If it returns 0, the address is
1651 passed as an "invisible" first argument. */
1652 #define STRUCT_VALUE 0
1654 /* Mips registers used in prologue/epilogue code when the stack frame
1655 is larger than 32K bytes. These registers must come from the
1656 scratch register set, and not used for passing and returning
1657 arguments and any other information used in the calling sequence
1658 (such as pic). Must start at 12, since t0/t3 are parameter passing
1659 registers in the 64 bit ABI. */
1661 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1662 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1664 /* Define this macro if it is as good or better to call a constant
1665 function address than to call an address kept in a register. */
1666 #define NO_FUNCTION_CSE 1
1668 /* Define this macro if it is as good or better for a function to
1669 call itself with an explicit address than to call an address
1670 kept in a register. */
1671 #define NO_RECURSIVE_FUNCTION_CSE 1
1673 /* The register number of the register used to address a table of
1674 static data addresses in memory. In some cases this register is
1675 defined by a processor's "application binary interface" (ABI).
1676 When this macro is defined, RTL is generated for this register
1677 once, as with the stack pointer and frame pointer registers. If
1678 this macro is not defined, it is up to the machine-dependent
1679 files to allocate such a register (if necessary). */
1680 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1682 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1684 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1685 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1686 isn't always called for static inline functions. */
1687 #define INIT_EXPANDERS \
1689 embedded_pic_fnaddr_rtx = NULL; \
1690 mips16_gp_pseudo_rtx = NULL; \
1693 /* Define the classes of registers for register constraints in the
1694 machine description. Also define ranges of constants.
1696 One of the classes must always be named ALL_REGS and include all hard regs.
1697 If there is more than one class, another class must be named NO_REGS
1698 and contain no registers.
1700 The name GENERAL_REGS must be the name of a class (or an alias for
1701 another name such as ALL_REGS). This is the class of registers
1702 that is allowed by "g" or "r" in a register constraint.
1703 Also, registers outside this class are allocated only when
1704 instructions express preferences for them.
1706 The classes must be numbered in nondecreasing order; that is,
1707 a larger-numbered class must never be contained completely
1708 in a smaller-numbered class.
1710 For any two classes, it is very desirable that there be another
1711 class that represents their union. */
1715 NO_REGS, /* no registers in set */
1716 M16_NA_REGS, /* mips16 regs not used to pass args */
1717 M16_REGS, /* mips16 directly accessible registers */
1718 T_REG, /* mips16 T register ($24) */
1719 M16_T_REGS, /* mips16 registers plus T register */
1720 GR_REGS, /* integer registers */
1721 FP_REGS, /* floating point registers */
1722 HI_REG, /* hi register */
1723 LO_REG, /* lo register */
1724 HILO_REG, /* hilo register pair for 64 bit mode mult */
1725 MD_REGS, /* multiply/divide registers (hi/lo) */
1726 HI_AND_GR_REGS, /* union classes */
1729 ST_REGS, /* status registers (fp status) */
1730 ALL_REGS, /* all registers */
1731 LIM_REG_CLASSES /* max value + 1 */
1734 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1736 #define GENERAL_REGS GR_REGS
1738 /* An initializer containing the names of the register classes as C
1739 string constants. These names are used in writing some of the
1742 #define REG_CLASS_NAMES \
1757 "HILO_AND_GR_REGS", \
1762 /* An initializer containing the contents of the register classes,
1763 as integers which are bit masks. The Nth integer specifies the
1764 contents of class N. The way the integer MASK is interpreted is
1765 that register R is in the class if `MASK & (1 << R)' is 1.
1767 When the machine has more than 32 registers, an integer does not
1768 suffice. Then the integers are replaced by sub-initializers,
1769 braced groupings containing several integers. Each
1770 sub-initializer must be suitable as an initializer for the type
1771 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1773 #define REG_CLASS_CONTENTS \
1775 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1776 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1777 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1778 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1779 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1780 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1781 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1782 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1783 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1784 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1785 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1786 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1787 { 0xffffffff, 0x00000000, 0x00000002 }, \
1788 { 0xffffffff, 0x00000000, 0x00000004 }, \
1789 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1790 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1794 /* A C expression whose value is a register class containing hard
1795 register REGNO. In general there is more that one such class;
1796 choose a class which is "minimal", meaning that no smaller class
1797 also contains the register. */
1799 extern enum reg_class mips_regno_to_class[];
1801 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1803 /* A macro whose definition is the name of the class to which a
1804 valid base register must belong. A base register is one used in
1805 an address which is the register value plus a displacement. */
1807 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1809 /* A macro whose definition is the name of the class to which a
1810 valid index register must belong. An index register is one used
1811 in an address where its value is either multiplied by a scale
1812 factor or added to another register (as well as added to a
1815 #define INDEX_REG_CLASS NO_REGS
1817 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1818 registers explicitly used in the rtl to be used as spill registers
1819 but prevents the compiler from extending the lifetime of these
1822 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1824 /* This macro is used later on in the file. */
1825 #define GR_REG_CLASS_P(CLASS) \
1826 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1827 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1829 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1830 is the default value (allocate the registers in numeric order). We
1831 define it just so that we can override it for the mips16 target in
1832 ORDER_REGS_FOR_LOCAL_ALLOC. */
1834 #define REG_ALLOC_ORDER \
1835 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1836 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1837 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1838 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1839 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1842 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1843 to be rearranged based on a particular function. On the mips16, we
1844 want to allocate $24 (T_REG) before other registers for
1845 instructions for which it is possible. */
1847 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1849 /* REGISTER AND CONSTANT CLASSES */
1851 /* Get reg_class from a letter such as appears in the machine
1854 DEFINED REGISTER CLASSES:
1856 'd' General (aka integer) registers
1857 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1858 'y' General registers (in both mips16 and non mips16 mode)
1859 'e' mips16 non argument registers (M16_NA_REGS)
1860 't' mips16 temporary register ($24)
1861 'f' Floating point registers
1864 'x' Multiply/divide registers
1866 'z' FP Status register
1867 'b' All registers */
1869 extern enum reg_class mips_char_to_class[];
1871 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1873 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1874 string can be used to stand for particular ranges of immediate
1875 operands. This macro defines what the ranges are. C is the
1876 letter, and VALUE is a constant value. Return 1 if VALUE is
1877 in the range specified by C. */
1881 `I' is used for the range of constants an arithmetic insn can
1882 actually contain (16 bits signed integers).
1884 `J' is used for the range which is just zero (ie, $r0).
1886 `K' is used for the range of constants a logical insn can actually
1887 contain (16 bit zero-extended integers).
1889 `L' is used for the range of constants that be loaded with lui
1890 (ie, the bottom 16 bits are zero).
1892 `M' is used for the range of constants that take two words to load
1893 (ie, not matched by `I', `K', and `L').
1895 `N' is used for negative 16 bit constants other than -65536.
1897 `O' is a 15 bit signed integer.
1899 `P' is used for positive 16 bit constants. */
1901 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1902 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1904 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1905 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1906 : (C) == 'J' ? ((VALUE) == 0) \
1907 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1908 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1909 && (((VALUE) & ~2147483647) == 0 \
1910 || ((VALUE) & ~2147483647) == ~2147483647)) \
1911 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1912 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1913 && (((VALUE) & 0x0000ffff) != 0 \
1914 || (((VALUE) & ~2147483647) != 0 \
1915 && ((VALUE) & ~2147483647) != ~2147483647))) \
1916 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1917 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1918 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1921 /* Similar, but for floating constants, and defining letters G and H.
1922 Here VALUE is the CONST_DOUBLE rtx itself. */
1926 'G' : Floating point 0 */
1928 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1930 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1932 /* Letters in the range `Q' through `U' may be defined in a
1933 machine-dependent fashion to stand for arbitrary operand types.
1934 The machine description macro `EXTRA_CONSTRAINT' is passed the
1935 operand as its first argument and the constraint letter as its
1938 `Q' is for mips16 GP relative constants
1939 `R' is for memory references which take 1 word for the instruction.
1940 `S' is for references to extern items which are PIC for OSF/rose.
1941 `T' is for memory addresses that can be used to load two words. */
1943 #define EXTRA_CONSTRAINT(OP,CODE) \
1944 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1945 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1946 && mips16_gp_offset_p (OP)) \
1947 : (GET_CODE (OP) != MEM) ? FALSE \
1948 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1949 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1950 && HALF_PIC_ADDRESS_P (OP)) \
1953 /* Given an rtx X being reloaded into a reg required to be
1954 in class CLASS, return the class of reg to actually use.
1955 In general this is just CLASS; but on some machines
1956 in some cases it is preferable to use a more restrictive class. */
1958 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1959 ((CLASS) != ALL_REGS \
1960 ? (! TARGET_MIPS16 \
1962 : ((CLASS) != GR_REGS \
1965 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1966 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1967 ? (TARGET_SOFT_FLOAT \
1968 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1970 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1971 || GET_MODE (X) == VOIDmode) \
1972 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1975 /* Certain machines have the property that some registers cannot be
1976 copied to some other registers without using memory. Define this
1977 macro on those machines to be a C expression that is non-zero if
1978 objects of mode MODE in registers of CLASS1 can only be copied to
1979 registers of class CLASS2 by storing a register of CLASS1 into
1980 memory and loading that memory location into a register of CLASS2.
1982 Do not define this macro if its value would always be zero. */
1984 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1985 ((!TARGET_DEBUG_H_MODE \
1986 && GET_MODE_CLASS (MODE) == MODE_INT \
1987 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1988 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1989 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1990 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1991 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1993 /* The HI and LO registers can only be reloaded via the general
1994 registers. Condition code registers can only be loaded to the
1995 general registers, and from the floating point registers. */
1997 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1998 mips_secondary_reload_class (CLASS, MODE, X, 1)
1999 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2000 mips_secondary_reload_class (CLASS, MODE, X, 0)
2002 /* Not declared above, with the other functions, because enum
2003 reg_class is not declared yet. */
2004 extern enum reg_class mips_secondary_reload_class ();
2006 /* Return the maximum number of consecutive registers
2007 needed to represent mode MODE in a register of class CLASS. */
2009 #define CLASS_UNITS(mode, size) \
2010 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2012 #define CLASS_MAX_NREGS(CLASS, MODE) \
2013 ((CLASS) == FP_REGS \
2015 ? CLASS_UNITS (MODE, 8) \
2016 : 2 * CLASS_UNITS (MODE, 8)) \
2017 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2019 /* If defined, this is a C expression whose value should be
2020 nonzero if the insn INSN has the effect of mysteriously
2021 clobbering the contents of hard register number REGNO. By
2022 "mysterious" we mean that the insn's RTL expression doesn't
2023 describe such an effect.
2025 If this macro is not defined, it means that no insn clobbers
2026 registers mysteriously. This is the usual situation; all else
2027 being equal, it is best for the RTL expression to show all the
2030 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
2033 /* Stack layout; function entry, exit and calling. */
2035 /* Define this if pushing a word on the stack
2036 makes the stack pointer a smaller address. */
2037 #define STACK_GROWS_DOWNWARD
2039 /* Define this if the nominal address of the stack frame
2040 is at the high-address end of the local variables;
2041 that is, each additional local variable allocated
2042 goes at a more negative offset in the frame. */
2043 /* #define FRAME_GROWS_DOWNWARD */
2045 /* Offset within stack frame to start allocating local variables at.
2046 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2047 first local allocated. Otherwise, it is the offset to the BEGINNING
2048 of the first local allocated. */
2049 #define STARTING_FRAME_OFFSET \
2050 (current_function_outgoing_args_size \
2051 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2053 /* Offset from the stack pointer register to an item dynamically
2054 allocated on the stack, e.g., by `alloca'.
2056 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2057 length of the outgoing arguments. The default is correct for most
2058 machines. See `function.c' for details.
2060 The MIPS ABI states that functions which dynamically allocate the
2061 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2062 we are trying to create a second frame pointer to the function, so
2063 allocate some stack space to make it happy.
2065 However, the linker currently complains about linking any code that
2066 dynamically allocates stack space, and there seems to be a bug in
2067 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2070 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2071 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2072 ? 4*UNITS_PER_WORD \
2073 : current_function_outgoing_args_size)
2076 /* The return address for the current frame is in r31 is this is a leaf
2077 function. Otherwise, it is on the stack. It is at a variable offset
2078 from sp/fp/ap, so we define a fake hard register rap which is a
2079 poiner to the return address on the stack. This always gets eliminated
2080 during reload to be either the frame pointer or the stack pointer plus
2083 /* ??? This definition fails for leaf functions. There is currently no
2084 general solution for this problem. */
2086 /* ??? There appears to be no way to get the return address of any previous
2087 frame except by disassembling instructions in the prologue/epilogue.
2088 So currently we support only the current frame. */
2090 #define RETURN_ADDR_RTX(count, frame) \
2092 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2095 /* Structure to be filled in by compute_frame_size with register
2096 save masks, and offsets for the current function. */
2098 struct mips_frame_info
2100 long total_size; /* # bytes that the entire frame takes up */
2101 long var_size; /* # bytes that variables take up */
2102 long args_size; /* # bytes that outgoing arguments take up */
2103 long extra_size; /* # bytes of extra gunk */
2104 int gp_reg_size; /* # bytes needed to store gp regs */
2105 int fp_reg_size; /* # bytes needed to store fp regs */
2106 long mask; /* mask of saved gp registers */
2107 long fmask; /* mask of saved fp registers */
2108 long gp_save_offset; /* offset from vfp to store gp registers */
2109 long fp_save_offset; /* offset from vfp to store fp registers */
2110 long gp_sp_offset; /* offset from new sp to store gp registers */
2111 long fp_sp_offset; /* offset from new sp to store fp registers */
2112 int initialized; /* != 0 if frame size already calculated */
2113 int num_gp; /* number of gp registers saved */
2114 int num_fp; /* number of fp registers saved */
2115 long insns_len; /* length of insns; mips16 only */
2118 extern struct mips_frame_info current_frame_info;
2120 /* If defined, this macro specifies a table of register pairs used to
2121 eliminate unneeded registers that point into the stack frame. If
2122 it is not defined, the only elimination attempted by the compiler
2123 is to replace references to the frame pointer with references to
2126 The definition of this macro is a list of structure
2127 initializations, each of which specifies an original and
2128 replacement register.
2130 On some machines, the position of the argument pointer is not
2131 known until the compilation is completed. In such a case, a
2132 separate hard register must be used for the argument pointer.
2133 This register can be eliminated by replacing it with either the
2134 frame pointer or the argument pointer, depending on whether or not
2135 the frame pointer has been eliminated.
2137 In this case, you might specify:
2138 #define ELIMINABLE_REGS \
2139 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2140 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2141 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2143 Note that the elimination of the argument pointer with the stack
2144 pointer is specified first since that is the preferred elimination.
2146 The eliminations to $17 are only used on the mips16. See the
2147 definition of HARD_FRAME_POINTER_REGNUM. */
2149 #define ELIMINABLE_REGS \
2150 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2151 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2152 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2153 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2154 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2155 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2156 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2157 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2158 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2159 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2161 /* A C expression that returns non-zero if the compiler is allowed to
2162 try to replace register number FROM-REG with register number
2163 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2164 defined, and will usually be the constant 1, since most of the
2165 cases preventing register elimination are things that the compiler
2166 already knows about.
2168 When not in mips16 and mips64, we can always eliminate to the
2169 frame pointer. We can eliminate to the stack pointer unless
2170 a frame pointer is needed. In mips16 mode, we need a frame
2171 pointer for a large frame; otherwise, reload may be unable
2172 to compute the address of a local variable, since there is
2173 no way to add a large constant to the stack pointer
2174 without using a temporary register.
2176 In mips16, for some instructions (eg lwu), we can't eliminate the
2177 frame pointer for the stack pointer. These instructions are
2178 only generated in TARGET_64BIT mode.
2181 #define CAN_ELIMINATE(FROM, TO) \
2182 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2183 || TO == GP_REG_FIRST + 31 && leaf_function_p)) \
2184 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2185 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2186 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2187 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2188 && (! TARGET_MIPS16 \
2189 || compute_frame_size (get_frame_size ()) < 32768)))))
2191 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2192 specifies the initial difference between the specified pair of
2193 registers. This macro must be defined if `ELIMINABLE_REGS' is
2196 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2197 { compute_frame_size (get_frame_size ()); \
2198 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2199 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2200 (OFFSET) = - current_function_outgoing_args_size; \
2201 else if ((FROM) == FRAME_POINTER_REGNUM) \
2203 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2204 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2205 (OFFSET) = (current_frame_info.total_size \
2206 - current_function_outgoing_args_size \
2207 - ((mips_abi != ABI_32 \
2208 && mips_abi != ABI_O64 \
2209 && mips_abi != ABI_EABI) \
2210 ? current_function_pretend_args_size \
2212 else if ((FROM) == ARG_POINTER_REGNUM) \
2213 (OFFSET) = (current_frame_info.total_size \
2214 - ((mips_abi != ABI_32 \
2215 && mips_abi != ABI_O64 \
2216 && mips_abi != ABI_EABI) \
2217 ? current_function_pretend_args_size \
2219 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2220 so we must add 4 bytes to the offset to get the right value. */ \
2221 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2222 if (leaf_function_p ()) \
2224 else (OFFSET) = current_frame_info.gp_sp_offset \
2225 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2226 * (BYTES_BIG_ENDIAN != 0)); \
2229 /* If we generate an insn to push BYTES bytes,
2230 this says how many the stack pointer really advances by.
2231 On the vax, sp@- in a byte insn really pushes a word. */
2233 /* #define PUSH_ROUNDING(BYTES) 0 */
2235 /* If defined, the maximum amount of space required for outgoing
2236 arguments will be computed and placed into the variable
2237 `current_function_outgoing_args_size'. No space will be pushed
2238 onto the stack for each call; instead, the function prologue
2239 should increase the stack frame size by this amount.
2241 It is not proper to define both `PUSH_ROUNDING' and
2242 `ACCUMULATE_OUTGOING_ARGS'. */
2243 #define ACCUMULATE_OUTGOING_ARGS
2245 /* Offset from the argument pointer register to the first argument's
2246 address. On some machines it may depend on the data type of the
2249 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2250 the first argument's address.
2252 On the MIPS, we must skip the first argument position if we are
2253 returning a structure or a union, to account for its address being
2254 passed in $4. However, at the current time, this produces a compiler
2255 that can't bootstrap, so comment it out for now. */
2258 #define FIRST_PARM_OFFSET(FNDECL) \
2260 && TREE_TYPE (FNDECL) != 0 \
2261 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2262 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2263 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2267 #define FIRST_PARM_OFFSET(FNDECL) 0
2270 /* When a parameter is passed in a register, stack space is still
2271 allocated for it. For the MIPS, stack space must be allocated, cf
2272 Asm Lang Prog Guide page 7-8.
2274 BEWARE that some space is also allocated for non existing arguments
2275 in register. In case an argument list is of form GF used registers
2276 are a0 (a2,a3), but we should push over a1... */
2278 #define REG_PARM_STACK_SPACE(FNDECL) \
2279 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2281 /* Define this if it is the responsibility of the caller to
2282 allocate the area reserved for arguments passed in registers.
2283 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2284 of this macro is to determine whether the space is included in
2285 `current_function_outgoing_args_size'. */
2286 #define OUTGOING_REG_PARM_STACK_SPACE
2288 /* Align stack frames on 64 bits (Double Word ). */
2289 #ifndef STACK_BOUNDARY
2290 #define STACK_BOUNDARY 64
2293 /* Make sure 4 words are always allocated on the stack. */
2295 #ifndef STACK_ARGS_ADJUST
2296 #define STACK_ARGS_ADJUST(SIZE) \
2298 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2299 SIZE.constant = 4 * UNITS_PER_WORD; \
2304 /* A C expression that should indicate the number of bytes of its
2305 own arguments that a function pops on returning, or 0
2306 if the function pops no arguments and the caller must therefore
2307 pop them all after the function returns.
2309 FUNDECL is the declaration node of the function (as a tree).
2311 FUNTYPE is a C variable whose value is a tree node that
2312 describes the function in question. Normally it is a node of
2313 type `FUNCTION_TYPE' that describes the data type of the function.
2314 From this it is possible to obtain the data types of the value
2315 and arguments (if known).
2317 When a call to a library function is being considered, FUNTYPE
2318 will contain an identifier node for the library function. Thus,
2319 if you need to distinguish among various library functions, you
2320 can do so by their names. Note that "library function" in this
2321 context means a function used to perform arithmetic, whose name
2322 is known specially in the compiler and was not mentioned in the
2323 C code being compiled.
2325 STACK-SIZE is the number of bytes of arguments passed on the
2326 stack. If a variable number of bytes is passed, it is zero, and
2327 argument popping will always be the responsibility of the
2328 calling function. */
2330 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2333 /* Symbolic macros for the registers used to return integer and floating
2336 #define GP_RETURN (GP_REG_FIRST + 2)
2337 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2339 /* Symbolic macros for the first/last argument registers. */
2341 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2342 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2343 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2344 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2346 #define MAX_ARGS_IN_REGISTERS 4
2348 /* Define how to find the value returned by a library function
2349 assuming the value has mode MODE. Because we define
2350 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2351 PROMOTE_MODE does. */
2353 #define LIBCALL_VALUE(MODE) \
2355 ((GET_MODE_CLASS (MODE) != MODE_INT \
2356 || GET_MODE_SIZE (MODE) >= 4) \
2359 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2360 && (! TARGET_SINGLE_FLOAT \
2361 || GET_MODE_SIZE (MODE) <= 4)) \
2365 /* Define how to find the value returned by a function.
2366 VALTYPE is the data type of the value (as a tree).
2367 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2368 otherwise, FUNC is 0. */
2370 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2373 /* 1 if N is a possible register number for a function value.
2374 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2375 Currently, R2 and F0 are only implemented here (C has no complex type) */
2377 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2379 /* 1 if N is a possible register number for function argument passing.
2380 We have no FP argument registers when soft-float. When FP registers
2381 are 32 bits, we can't directly reference the odd numbered ones. */
2383 #define FUNCTION_ARG_REGNO_P(N) \
2384 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2385 || ((! TARGET_SOFT_FLOAT \
2386 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2387 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2388 && ! fixed_regs[N]))
2390 /* A C expression which can inhibit the returning of certain function
2391 values in registers, based on the type of value. A nonzero value says
2392 to return the function value in memory, just as large structures are
2393 always returned. Here TYPE will be a C expression of type
2394 `tree', representing the data type of the value.
2396 Note that values of mode `BLKmode' must be explicitly
2397 handled by this macro. Also, the option `-fpcc-struct-return'
2398 takes effect regardless of this macro. On most systems, it is
2399 possible to leave the macro undefined; this causes a default
2400 definition to be used, whose value is the constant 1 for BLKmode
2401 values, and 0 otherwise.
2403 GCC normally converts 1 byte structures into chars, 2 byte
2404 structs into shorts, and 4 byte structs into ints, and returns
2405 them this way. Defining the following macro overrides this,
2406 to give us MIPS cc compatibility. */
2408 #define RETURN_IN_MEMORY(TYPE) \
2409 (TYPE_MODE (TYPE) == BLKmode)
2411 /* A code distinguishing the floating point format of the target
2412 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2413 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2415 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2418 /* Define a data type for recording info about an argument list
2419 during the scan of that argument list. This data type should
2420 hold all necessary information about the function itself
2421 and about the args processed so far, enough to enable macros
2422 such as FUNCTION_ARG to determine where the next arg should go.
2424 On the mips16, we need to keep track of which floating point
2425 arguments were passed in general registers, but would have been
2426 passed in the FP regs if this were a 32 bit function, so that we
2427 can move them to the FP regs if we wind up calling a 32 bit
2428 function. We record this information in fp_code, encoded in base
2429 four. A zero digit means no floating point argument, a one digit
2430 means an SFmode argument, and a two digit means a DFmode argument,
2431 and a three digit is not used. The low order digit is the first
2432 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2433 an SFmode argument. ??? A more sophisticated approach will be
2434 needed if MIPS_ABI != ABI_32. */
2436 typedef struct mips_args {
2437 int gp_reg_found; /* whether a gp register was found yet */
2438 int arg_number; /* argument number */
2439 int arg_words; /* # total words the arguments take */
2440 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2441 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2442 int fp_code; /* Mode of FP arguments (mips16) */
2443 int num_adjusts; /* number of adjustments made */
2444 /* Adjustments made to args pass in regs. */
2445 /* ??? The size is doubled to work around a
2446 bug in the code that sets the adjustments
2448 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2451 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2452 for a call to a function whose data type is FNTYPE.
2453 For a library call, FNTYPE is 0.
2457 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2458 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2460 /* Update the data in CUM to advance over an argument
2461 of mode MODE and data type TYPE.
2462 (TYPE is null for libcalls where that information may not be available.) */
2464 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2465 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2467 /* Determine where to put an argument to a function.
2468 Value is zero to push the argument on the stack,
2469 or a hard register in which to store the argument.
2471 MODE is the argument's machine mode.
2472 TYPE is the data type of the argument (as a tree).
2473 This is null for libcalls where that information may
2475 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2476 the preceding args and about the function being called.
2477 NAMED is nonzero if this argument is a named parameter
2478 (otherwise it is an extra parameter matching an ellipsis). */
2480 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2481 function_arg( &CUM, MODE, TYPE, NAMED)
2483 /* For an arg passed partly in registers and partly in memory,
2484 this is the number of registers used.
2485 For args passed entirely in registers or entirely in memory, zero. */
2487 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2488 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2490 /* If defined, a C expression that gives the alignment boundary, in
2491 bits, of an argument with the specified mode and type. If it is
2492 not defined, `PARM_BOUNDARY' is used for all arguments. */
2494 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2496 ? ((TYPE_ALIGN(TYPE) <= (unsigned)PARM_BOUNDARY) \
2498 : TYPE_ALIGN(TYPE)) \
2499 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2501 : GET_MODE_ALIGNMENT(MODE)))
2504 /* This macro generates the assembly code for function entry.
2505 FILE is a stdio stream to output the code to.
2506 SIZE is an int: how many units of temporary storage to allocate.
2507 Refer to the array `regs_ever_live' to determine which registers
2508 to save; `regs_ever_live[I]' is nonzero if register number I
2509 is ever used in the function. This macro is responsible for
2510 knowing which registers should not be saved even if used. */
2512 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2514 /* This macro generates the assembly code for function exit,
2515 on machines that need it. If FUNCTION_EPILOGUE is not defined
2516 then individual return instructions are generated for each
2517 return statement. Args are same as for FUNCTION_PROLOGUE. */
2519 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2521 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2523 #define MUST_SAVE_REGISTER(regno) \
2524 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2525 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2526 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2528 /* ALIGN FRAMES on double word boundaries */
2529 #ifndef MIPS_STACK_ALIGN
2530 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2534 /* Output assembler code to FILE to increment profiler label # LABELNO
2535 for profiling a function entry. */
2537 #define FUNCTION_PROFILER(FILE, LABELNO) \
2539 if (TARGET_MIPS16) \
2540 sorry ("mips16 function profiling"); \
2541 fprintf (FILE, "\t.set\tnoreorder\n"); \
2542 fprintf (FILE, "\t.set\tnoat\n"); \
2543 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2544 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2545 fprintf (FILE, "\tjal\t_mcount\n"); \
2547 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2548 TARGET_64BIT ? "dsubu" : "subu", \
2549 reg_names[STACK_POINTER_REGNUM], \
2550 reg_names[STACK_POINTER_REGNUM], \
2551 Pmode == DImode ? 16 : 8); \
2552 fprintf (FILE, "\t.set\treorder\n"); \
2553 fprintf (FILE, "\t.set\tat\n"); \
2556 /* Define this macro if the code for function profiling should come
2557 before the function prologue. Normally, the profiling code comes
2560 /* #define PROFILE_BEFORE_PROLOGUE */
2562 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2563 the stack pointer does not matter. The value is tested only in
2564 functions that have frame pointers.
2565 No definition is equivalent to always zero. */
2567 #define EXIT_IGNORE_STACK 1
2570 /* A C statement to output, on the stream FILE, assembler code for a
2571 block of data that contains the constant parts of a trampoline.
2572 This code should not include a label--the label is taken care of
2575 #define TRAMPOLINE_TEMPLATE(STREAM) \
2577 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2578 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2579 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2580 if (Pmode == DImode) \
2582 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2583 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2587 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2588 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2590 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2591 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2592 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2593 if (Pmode == DImode) \
2595 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2596 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2600 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2601 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2605 /* A C expression for the size in bytes of the trampoline, as an
2608 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2610 /* Alignment required for trampolines, in bits. */
2612 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2614 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2615 program and data caches. */
2617 #ifndef CACHE_FLUSH_FUNC
2618 #define CACHE_FLUSH_FUNC "_flush_cache"
2621 /* A C statement to initialize the variable parts of a trampoline.
2622 ADDR is an RTX for the address of the trampoline; FNADDR is an
2623 RTX for the address of the nested function; STATIC_CHAIN is an
2624 RTX for the static chain value that should be passed to the
2625 function when it is called. */
2627 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2630 if (Pmode == DImode) \
2632 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2633 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2637 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2638 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2641 /* Flush both caches. We need to flush the data cache in case \
2642 the system has a write-back cache. */ \
2643 /* ??? Should check the return value for errors. */ \
2644 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC), \
2645 0, VOIDmode, 3, addr, Pmode, \
2646 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2647 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2650 /* Addressing modes, and classification of registers for them. */
2652 /* #define HAVE_POST_INCREMENT 0 */
2653 /* #define HAVE_POST_DECREMENT 0 */
2655 /* #define HAVE_PRE_DECREMENT 0 */
2656 /* #define HAVE_PRE_INCREMENT 0 */
2658 /* These assume that REGNO is a hard or pseudo reg number.
2659 They give nonzero only if REGNO is a hard reg of the suitable class
2660 or a pseudo reg currently allocated to a suitable hard reg.
2661 These definitions are NOT overridden anywhere. */
2663 #define BASE_REG_P(regno, mode) \
2665 ? (M16_REG_P (regno) \
2666 || (regno) == FRAME_POINTER_REGNUM \
2667 || (regno) == ARG_POINTER_REGNUM \
2668 || ((regno) == STACK_POINTER_REGNUM \
2669 && (GET_MODE_SIZE (mode) == 4 \
2670 || GET_MODE_SIZE (mode) == 8))) \
2673 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2674 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2677 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2678 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2680 #define REGNO_OK_FOR_INDEX_P(regno) 0
2681 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2682 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2684 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2685 and check its validity for a certain class.
2686 We have two alternate definitions for each of them.
2687 The usual definition accepts all pseudo regs; the other rejects them all.
2688 The symbol REG_OK_STRICT causes the latter definition to be used.
2690 Most source files want to accept pseudo regs in the hope that
2691 they will get allocated to the class that the insn wants them to be in.
2692 Some source files that are used after register allocation
2693 need to be strict. */
2695 #ifndef REG_OK_STRICT
2697 #define REG_OK_STRICT_P 0
2698 #define REG_OK_FOR_INDEX_P(X) 0
2699 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2700 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
2704 #define REG_OK_STRICT_P 1
2705 #define REG_OK_FOR_INDEX_P(X) 0
2706 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2707 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
2712 /* Maximum number of registers that can appear in a valid memory address. */
2714 #define MAX_REGS_PER_ADDRESS 1
2716 /* A C compound statement with a conditional `goto LABEL;' executed
2717 if X (an RTX) is a legitimate memory address on the target
2718 machine for a memory operand of mode MODE.
2720 It usually pays to define several simpler macros to serve as
2721 subroutines for this one. Otherwise it may be too complicated
2724 This macro must exist in two variants: a strict variant and a
2725 non-strict one. The strict variant is used in the reload pass.
2726 It must be defined so that any pseudo-register that has not been
2727 allocated a hard register is considered a memory reference. In
2728 contexts where some kind of register is required, a
2729 pseudo-register with no hard register must be rejected.
2731 The non-strict variant is used in other passes. It must be
2732 defined to accept all pseudo-registers in every context where
2733 some kind of register is required.
2735 Compiler source files that want to use the strict variant of
2736 this macro define the macro `REG_OK_STRICT'. You should use an
2737 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2738 in that case and the non-strict variant otherwise.
2740 Typically among the subroutines used to define
2741 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2742 acceptable registers for various purposes (one for base
2743 registers, one for index registers, and so on). Then only these
2744 subroutine macros need have two variants; the higher levels of
2745 macros may be the same whether strict or not.
2747 Normally, constant addresses which are the sum of a `symbol_ref'
2748 and an integer are stored inside a `const' RTX to mark them as
2749 constant. Therefore, there is no need to recognize such sums
2750 specifically as legitimate addresses. Normally you would simply
2751 recognize any `const' as legitimate.
2753 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2754 constant sums that are not marked with `const'. It assumes
2755 that a naked `plus' indicates indexing. If so, then you *must*
2756 reject such naked constant sums as illegitimate addresses, so
2757 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2759 On some machines, whether a symbolic address is legitimate
2760 depends on the section that the address refers to. On these
2761 machines, define the macro `ENCODE_SECTION_INFO' to store the
2762 information into the `symbol_ref', and then check for it here.
2763 When you see a `const', you will have to look inside it to find
2764 the `symbol_ref' in order to determine the section. */
2767 #define GO_PRINTF(x) trace(x)
2768 #define GO_PRINTF2(x,y) trace(x,y)
2769 #define GO_DEBUG_RTX(x) debug_rtx(x)
2772 #define GO_PRINTF(x)
2773 #define GO_PRINTF2(x,y)
2774 #define GO_DEBUG_RTX(x)
2777 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2779 register rtx xinsn = (X); \
2781 if (TARGET_DEBUG_B_MODE) \
2783 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2784 (REG_OK_STRICT_P) ? "" : "not "); \
2785 GO_DEBUG_RTX (xinsn); \
2788 /* The mips16 can only use the stack pointer as a base register when \
2789 loading SImode or DImode values. */ \
2790 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
2793 if (CONSTANT_ADDRESS_P (xinsn) \
2794 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2795 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
2798 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2800 register rtx xlow0 = XEXP (xinsn, 0); \
2801 register rtx xlow1 = XEXP (xinsn, 1); \
2803 if (GET_CODE (xlow0) == REG \
2804 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
2805 && mips_check_split (xlow1, MODE)) \
2809 if (GET_CODE (xinsn) == PLUS) \
2811 register rtx xplus0 = XEXP (xinsn, 0); \
2812 register rtx xplus1 = XEXP (xinsn, 1); \
2813 register enum rtx_code code0 = GET_CODE (xplus0); \
2814 register enum rtx_code code1 = GET_CODE (xplus1); \
2816 /* The mips16 can only use the stack pointer as a base register \
2817 when loading SImode or DImode values. */ \
2818 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
2820 if (code1 == CONST_INT \
2821 && INTVAL (xplus1) >= -32768 \
2822 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2825 /* On the mips16, we represent GP relative offsets in RTL. \
2826 These are 16 bit signed values, and can serve as register \
2829 && mips16_gp_offset_p (xplus1)) \
2832 /* For some code sequences, you actually get better code by \
2833 pretending that the MIPS supports an address mode of a \
2834 constant address + a register, even though the real \
2835 machine doesn't support it. This is because the \
2836 assembler can use $r1 to load just the high 16 bits, add \
2837 in the register, and fold the low 16 bits into the memory \
2838 reference, whereas the compiler generates a 4 instruction \
2839 sequence. On the other hand, CSE is not as effective. \
2840 It would be a win to generate the lui directly, but the \
2841 MIPS assembler does not have syntax to generate the \
2842 appropriate relocation. */ \
2844 /* Also accept CONST_INT addresses here, so no else. */ \
2845 /* Reject combining an embedded PIC text segment reference \
2846 with a register. That requires an additional \
2848 /* ??? Reject combining an address with a register for the MIPS \
2849 64 bit ABI, because the SGI assembler can not handle this. */ \
2850 if (!TARGET_DEBUG_A_MODE \
2851 && (mips_abi == ABI_32 \
2852 || mips_abi == ABI_O64 \
2853 || mips_abi == ABI_EABI) \
2854 && CONSTANT_ADDRESS_P (xplus1) \
2855 && ! mips_split_addresses \
2856 && (!TARGET_EMBEDDED_PIC \
2858 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2859 && !TARGET_MIPS16) \
2864 if (TARGET_DEBUG_B_MODE) \
2865 GO_PRINTF ("Not a legitimate address\n"); \
2869 /* A C expression that is 1 if the RTX X is a constant which is a
2870 valid address. This is defined to be the same as `CONSTANT_P (X)',
2871 but rejecting CONST_DOUBLE. */
2872 /* When pic, we must reject addresses of the form symbol+large int.
2873 This is because an instruction `sw $4,s+70000' needs to be converted
2874 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2875 assembler would use $at as a temp to load in the large offset. In this
2876 case $at is already in use. We convert such problem addresses to
2877 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2878 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2879 #define CONSTANT_ADDRESS_P(X) \
2880 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2881 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2882 || (GET_CODE (X) == CONST \
2883 && ! (flag_pic && pic_address_needs_scratch (X)) \
2884 && (mips_abi == ABI_32 \
2885 || mips_abi == ABI_O64 \
2886 || mips_abi == ABI_EABI))) \
2887 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2889 /* Define this, so that when PIC, reload won't try to reload invalid
2890 addresses which require two reload registers. */
2892 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2894 /* Nonzero if the constant value X is a legitimate general operand.
2895 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2897 At present, GAS doesn't understand li.[sd], so don't allow it
2898 to be generated at present. Also, the MIPS assembler does not
2899 grok li.d Infinity. */
2901 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2902 #define LEGITIMATE_CONSTANT_P(X) \
2903 ((GET_CODE (X) != CONST_DOUBLE \
2904 || mips_const_double_ok (X, GET_MODE (X))) \
2905 && ! (GET_CODE (X) == CONST \
2906 && mips_abi != ABI_32 \
2907 && mips_abi != ABI_O64 \
2908 && mips_abi != ABI_EABI) \
2909 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2911 /* A C compound statement that attempts to replace X with a valid
2912 memory address for an operand of mode MODE. WIN will be a C
2913 statement label elsewhere in the code; the macro definition may
2916 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2918 to avoid further processing if the address has become legitimate.
2920 X will always be the result of a call to `break_out_memory_refs',
2921 and OLDX will be the operand that was given to that function to
2924 The code generated by this macro should not alter the
2925 substructure of X. If it transforms X into a more legitimate
2926 form, it should assign X (which will always be a C variable) a
2929 It is not necessary for this macro to come up with a legitimate
2930 address. The compiler has standard ways of doing so in all
2931 cases. In fact, it is safe for this macro to do nothing. But
2932 often a machine-dependent strategy can generate better code.
2934 For the MIPS, transform:
2936 memory(X + <large int>)
2940 Y = <large int> & ~0x7fff;
2942 memory (Z + (<large int> & 0x7fff));
2944 This is for CSE to find several similar references, and only use one Z.
2946 When PIC, convert addresses of the form memory (symbol+large int) to
2947 memory (reg+large int). */
2950 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2952 register rtx xinsn = (X); \
2954 if (TARGET_DEBUG_B_MODE) \
2956 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2957 GO_DEBUG_RTX (xinsn); \
2960 if (mips_split_addresses && mips_check_split (X, MODE)) \
2962 /* ??? Is this ever executed? */ \
2963 X = gen_rtx (LO_SUM, Pmode, \
2964 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2968 if (GET_CODE (xinsn) == CONST \
2969 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2970 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2971 || (mips_abi != ABI_32 \
2972 && mips_abi != ABI_O64 \
2973 && mips_abi != ABI_EABI))) \
2975 rtx ptr_reg = gen_reg_rtx (Pmode); \
2976 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2978 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2980 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2981 if (SMALL_INT (constant)) \
2983 /* Otherwise we fall through so the code below will fix the \
2988 if (GET_CODE (xinsn) == PLUS) \
2990 register rtx xplus0 = XEXP (xinsn, 0); \
2991 register rtx xplus1 = XEXP (xinsn, 1); \
2992 register enum rtx_code code0 = GET_CODE (xplus0); \
2993 register enum rtx_code code1 = GET_CODE (xplus1); \
2995 if (code0 != REG && code1 == REG) \
2997 xplus0 = XEXP (xinsn, 1); \
2998 xplus1 = XEXP (xinsn, 0); \
2999 code0 = GET_CODE (xplus0); \
3000 code1 = GET_CODE (xplus1); \
3003 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3004 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3006 rtx int_reg = gen_reg_rtx (Pmode); \
3007 rtx ptr_reg = gen_reg_rtx (Pmode); \
3009 emit_move_insn (int_reg, \
3010 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3012 emit_insn (gen_rtx (SET, VOIDmode, \
3014 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
3016 X = gen_rtx (PLUS, Pmode, ptr_reg, \
3017 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
3022 if (TARGET_DEBUG_B_MODE) \
3023 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3027 /* A C statement or compound statement with a conditional `goto
3028 LABEL;' executed if memory address X (an RTX) can have different
3029 meanings depending on the machine mode of the memory reference it
3032 Autoincrement and autodecrement addresses typically have
3033 mode-dependent effects because the amount of the increment or
3034 decrement is the size of the operand being addressed. Some
3035 machines have other mode-dependent addresses. Many RISC machines
3036 have no mode-dependent addresses.
3038 You may assume that ADDR is a valid address for the machine. */
3040 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3043 /* Define this macro if references to a symbol must be treated
3044 differently depending on something about the variable or
3045 function named by the symbol (such as what section it is in).
3047 The macro definition, if any, is executed immediately after the
3048 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3049 The value of the rtl will be a `mem' whose address is a
3052 The usual thing for this macro to do is to a flag in the
3053 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3054 name string in the `symbol_ref' (if one bit is not enough
3057 The best way to modify the name string is by adding text to the
3058 beginning, with suitable punctuation to prevent any ambiguity.
3059 Allocate the new name in `saveable_obstack'. You will have to
3060 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3061 and output the name accordingly.
3063 You can also check the information stored in the `symbol_ref' in
3064 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3065 `PRINT_OPERAND_ADDRESS'.
3067 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3070 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3071 symbols which are not in the .text section.
3073 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3074 constants which are put in the .text section. We also record the
3075 total length of all such strings; this total is used to decide
3076 whether we need to split the constant table, and need not be
3079 When not mips16 code nor embedded PIC, if a symbol is in a
3080 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3081 splitting the reference so that gas can generate a gp relative
3085 #define ENCODE_SECTION_INFO(DECL) \
3088 if (TARGET_MIPS16) \
3090 if (TREE_CODE (DECL) == STRING_CST \
3091 && ! flag_writable_strings) \
3093 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3094 mips_string_length += TREE_STRING_LENGTH (DECL); \
3097 if (TARGET_EMBEDDED_PIC) \
3099 if (TREE_CODE (DECL) == VAR_DECL) \
3100 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3101 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3102 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3103 else if (TREE_CODE (DECL) == STRING_CST \
3104 && ! flag_writable_strings) \
3105 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3107 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3110 else if (TREE_CODE (DECL) == VAR_DECL \
3111 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3112 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3114 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3117 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3120 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
3122 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3124 if (size > 0 && size <= mips_section_threshold) \
3125 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3128 else if (HALF_PIC_P ()) \
3130 HALF_PIC_ENCODE (DECL); \
3135 /* The mips16 wants the constant pool to be after the function,
3136 because the PC relative load instructions use unsigned offsets. */
3138 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3140 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3141 mips_string_length = 0;
3144 /* In mips16 mode, put most string constants after the function. */
3145 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3146 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3149 /* Specify the machine mode that this machine uses
3150 for the index in the tablejump instruction.
3151 ??? Using HImode in mips16 mode can cause overflow. However, the
3152 overflow is no more likely than the overflow in a branch
3153 instruction. Large functions can currently break in both ways. */
3154 #define CASE_VECTOR_MODE \
3155 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3157 /* Define as C expression which evaluates to nonzero if the tablejump
3158 instruction expects the table to contain offsets from the address of the
3160 Do not define this if the table should contain absolute addresses. */
3161 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3163 /* Specify the tree operation to be used to convert reals to integers. */
3164 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3166 /* This is the kind of divide that is easiest to do in the general case. */
3167 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3169 /* Define this as 1 if `char' should by default be signed; else as 0. */
3170 #ifndef DEFAULT_SIGNED_CHAR
3171 #define DEFAULT_SIGNED_CHAR 1
3174 /* Max number of bytes we can move from memory to memory
3175 in one reasonably fast instruction. */
3176 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3177 #define MAX_MOVE_MAX 8
3179 /* Define this macro as a C expression which is nonzero if
3180 accessing less than a word of memory (i.e. a `char' or a
3181 `short') is no faster than accessing a word of memory, i.e., if
3182 such access require more than one instruction or if there is no
3183 difference in cost between byte and (aligned) word loads.
3185 On RISC machines, it tends to generate better code to define
3186 this as 1, since it avoids making a QI or HI mode register. */
3187 #define SLOW_BYTE_ACCESS 1
3189 /* We assume that the store-condition-codes instructions store 0 for false
3190 and some other value for true. This is the value stored for true. */
3192 #define STORE_FLAG_VALUE 1
3194 /* Define this if zero-extension is slow (more than one real instruction). */
3195 #define SLOW_ZERO_EXTEND
3197 /* Define this to be nonzero if shift instructions ignore all but the low-order
3199 #define SHIFT_COUNT_TRUNCATED 1
3201 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3202 is done just by pretending it is already truncated. */
3203 /* In 64 bit mode, 32 bit instructions require that register values be properly
3204 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3205 converts a value >32 bits to a value <32 bits. */
3206 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3207 Something needs to be done about this. Perhaps not use any 32 bit
3208 instructions? Perhaps use PROMOTE_MODE? */
3209 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3210 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3212 /* Specify the machine mode that pointers have.
3213 After generation of rtl, the compiler makes no further distinction
3214 between pointers and any other objects of this machine mode. */
3217 #define Pmode ((enum machine_mode)(TARGET_LONG64 ? DImode : SImode))
3220 /* A function address in a call instruction
3221 is a word address (for indexing purposes)
3222 so give the MEM rtx a words's mode. */
3224 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3226 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3227 memset, instead of the BSD functions bcopy and bzero. */
3229 #if defined(MIPS_SYSV) || defined(OSF_OS)
3230 #define TARGET_MEM_FUNCTIONS
3234 /* A part of a C `switch' statement that describes the relative
3235 costs of constant RTL expressions. It must contain `case'
3236 labels for expression codes `const_int', `const', `symbol_ref',
3237 `label_ref' and `const_double'. Each case must ultimately reach
3238 a `return' statement to return the relative cost of the use of
3239 that kind of constant value in an expression. The cost may
3240 depend on the precise value of the constant, which is available
3241 for examination in X.
3243 CODE is the expression code--redundant, since it can be obtained
3244 with `GET_CODE (X)'. */
3246 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3248 if (! TARGET_MIPS16) \
3250 /* Always return 0, since we don't have different sized \
3251 instructions, hence different costs according to Richard \
3255 if ((OUTER_CODE) == SET) \
3257 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3259 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3260 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3261 return COSTS_N_INSNS (1); \
3263 return COSTS_N_INSNS (2); \
3265 /* A PLUS could be an address. We don't want to force an address \
3266 to use a register, so accept any signed 16 bit value without \
3268 if ((OUTER_CODE) == PLUS \
3269 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3271 /* A number between 1 and 8 inclusive is efficient for a shift. \
3272 Otherwise, we will need an extended instruction. */ \
3273 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3274 || (OUTER_CODE) == LSHIFTRT) \
3276 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3278 return COSTS_N_INSNS (1); \
3280 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3281 if ((OUTER_CODE) == XOR \
3282 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3284 /* We may be able to use slt or sltu for a comparison with a \
3285 signed 16 bit value. (The boundary conditions aren't quite \
3286 right, but this is just a heuristic anyhow.) */ \
3287 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3288 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3289 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3290 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3291 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3293 /* Equality comparisons with 0 are cheap. */ \
3294 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3295 && INTVAL (X) == 0) \
3298 /* Otherwise, work out the cost to load the value into a \
3300 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3301 return COSTS_N_INSNS (1); \
3302 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3303 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3304 return COSTS_N_INSNS (2); \
3306 return COSTS_N_INSNS (3); \
3309 return COSTS_N_INSNS (2); \
3313 rtx offset = const0_rtx; \
3314 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3316 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3318 /* Treat this like a signed 16 bit CONST_INT. */ \
3319 if ((OUTER_CODE) == PLUS) \
3321 else if ((OUTER_CODE) == SET) \
3322 return COSTS_N_INSNS (1); \
3324 return COSTS_N_INSNS (2); \
3327 if (GET_CODE (symref) == LABEL_REF) \
3328 return COSTS_N_INSNS (2); \
3330 if (GET_CODE (symref) != SYMBOL_REF) \
3331 return COSTS_N_INSNS (4); \
3333 /* let's be paranoid.... */ \
3334 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3335 return COSTS_N_INSNS (2); \
3337 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3341 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3343 case CONST_DOUBLE: \
3346 if (TARGET_MIPS16) \
3347 return COSTS_N_INSNS (4); \
3348 split_double (X, &high, &low); \
3349 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3350 || low == CONST0_RTX (GET_MODE (low))) \
3354 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3355 This can be used, for example, to indicate how costly a multiply
3356 instruction is. In writing this macro, you can use the construct
3357 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3359 This macro is optional; do not define it if the default cost
3360 assumptions are adequate for the target machine.
3362 If -mdebugd is used, change the multiply cost to 2, so multiply by
3363 a constant isn't converted to a series of shifts. This helps
3364 strength reduction, and also makes it easier to identify what the
3365 compiler is doing. */
3367 /* ??? Fix this to be right for the R8000. */
3368 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3371 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3372 if (simple_memory_operand (X, GET_MODE (X))) \
3373 return COSTS_N_INSNS (num_words); \
3375 return COSTS_N_INSNS (2*num_words); \
3379 return COSTS_N_INSNS (6); \
3382 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3387 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3388 return COSTS_N_INSNS (2); \
3395 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3396 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3402 enum machine_mode xmode = GET_MODE (X); \
3403 if (xmode == SFmode || xmode == DFmode) \
3404 return COSTS_N_INSNS (1); \
3406 return COSTS_N_INSNS (4); \
3412 enum machine_mode xmode = GET_MODE (X); \
3413 if (xmode == SFmode || xmode == DFmode) \
3415 if (mips_cpu == PROCESSOR_R3000 \
3416 || mips_cpu == PROCESSOR_R3900) \
3417 return COSTS_N_INSNS (2); \
3418 else if (mips_cpu == PROCESSOR_R6000) \
3419 return COSTS_N_INSNS (3); \
3421 return COSTS_N_INSNS (6); \
3424 if (xmode == DImode && !TARGET_64BIT) \
3425 return COSTS_N_INSNS (4); \
3431 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3438 enum machine_mode xmode = GET_MODE (X); \
3439 if (xmode == SFmode) \
3441 if (mips_cpu == PROCESSOR_R3000 \
3442 || mips_cpu == PROCESSOR_R3900 \
3443 || mips_cpu == PROCESSOR_R5000) \
3444 return COSTS_N_INSNS (4); \
3445 else if (mips_cpu == PROCESSOR_R6000) \
3446 return COSTS_N_INSNS (5); \
3448 return COSTS_N_INSNS (7); \
3451 if (xmode == DFmode) \
3453 if (mips_cpu == PROCESSOR_R3000 \
3454 || mips_cpu == PROCESSOR_R3900 \
3455 || mips_cpu == PROCESSOR_R5000) \
3456 return COSTS_N_INSNS (5); \
3457 else if (mips_cpu == PROCESSOR_R6000) \
3458 return COSTS_N_INSNS (6); \
3460 return COSTS_N_INSNS (8); \
3463 if (mips_cpu == PROCESSOR_R3000) \
3464 return COSTS_N_INSNS (12); \
3465 else if (mips_cpu == PROCESSOR_R3900) \
3466 return COSTS_N_INSNS (2); \
3467 else if (mips_cpu == PROCESSOR_R6000) \
3468 return COSTS_N_INSNS (17); \
3469 else if (mips_cpu == PROCESSOR_R5000) \
3470 return COSTS_N_INSNS (5); \
3472 return COSTS_N_INSNS (10); \
3478 enum machine_mode xmode = GET_MODE (X); \
3479 if (xmode == SFmode) \
3481 if (mips_cpu == PROCESSOR_R3000 \
3482 || mips_cpu == PROCESSOR_R3900) \
3483 return COSTS_N_INSNS (12); \
3484 else if (mips_cpu == PROCESSOR_R6000) \
3485 return COSTS_N_INSNS (15); \
3487 return COSTS_N_INSNS (23); \
3490 if (xmode == DFmode) \
3492 if (mips_cpu == PROCESSOR_R3000 \
3493 || mips_cpu == PROCESSOR_R3900) \
3494 return COSTS_N_INSNS (19); \
3495 else if (mips_cpu == PROCESSOR_R6000) \
3496 return COSTS_N_INSNS (16); \
3498 return COSTS_N_INSNS (36); \
3501 /* fall through */ \
3505 if (mips_cpu == PROCESSOR_R3000 \
3506 || mips_cpu == PROCESSOR_R3900) \
3507 return COSTS_N_INSNS (35); \
3508 else if (mips_cpu == PROCESSOR_R6000) \
3509 return COSTS_N_INSNS (38); \
3510 else if (mips_cpu == PROCESSOR_R5000) \
3511 return COSTS_N_INSNS (36); \
3513 return COSTS_N_INSNS (69); \
3516 /* A sign extend from SImode to DImode in 64 bit mode is often \
3517 zero instructions, because the result can often be used \
3518 directly by another instruction; we'll call it one. */ \
3519 if (TARGET_64BIT && GET_MODE (X) == DImode \
3520 && GET_MODE (XEXP (X, 0)) == SImode) \
3521 return COSTS_N_INSNS (1); \
3523 return COSTS_N_INSNS (2); \
3526 if (TARGET_64BIT && GET_MODE (X) == DImode \
3527 && GET_MODE (XEXP (X, 0)) == SImode) \
3528 return COSTS_N_INSNS (2); \
3530 return COSTS_N_INSNS (1);
3532 /* An expression giving the cost of an addressing mode that
3533 contains ADDRESS. If not defined, the cost is computed from the
3534 form of the ADDRESS expression and the `CONST_COSTS' values.
3536 For most CISC machines, the default cost is a good approximation
3537 of the true cost of the addressing mode. However, on RISC
3538 machines, all instructions normally have the same length and
3539 execution time. Hence all addresses will have equal costs.
3541 In cases where more than one form of an address is known, the
3542 form with the lowest cost will be used. If multiple forms have
3543 the same, lowest, cost, the one that is the most complex will be
3546 For example, suppose an address that is equal to the sum of a
3547 register and a constant is used twice in the same basic block.
3548 When this macro is not defined, the address will be computed in
3549 a register and memory references will be indirect through that
3550 register. On machines where the cost of the addressing mode
3551 containing the sum is no higher than that of a simple indirect
3552 reference, this will produce an additional instruction and
3553 possibly require an additional register. Proper specification
3554 of this macro eliminates this overhead for such machines.
3556 Similar use of this macro is made in strength reduction of loops.
3558 ADDRESS need not be valid as an address. In such a case, the
3559 cost is not relevant and can be any value; invalid addresses
3560 need not be assigned a different cost.
3562 On machines where an address involving more than one register is
3563 as cheap as an address computation involving only one register,
3564 defining `ADDRESS_COST' to reflect this can cause two registers
3565 to be live over a region of code where only one would have been
3566 if `ADDRESS_COST' were not defined in that manner. This effect
3567 should be considered in the definition of this macro.
3568 Equivalent costs should probably only be given to addresses with
3569 different numbers of registers on machines with lots of registers.
3571 This macro will normally either not be defined or be defined as
3574 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3576 /* A C expression for the cost of moving data from a register in
3577 class FROM to one in class TO. The classes are expressed using
3578 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3579 the default; other values are interpreted relative to that.
3581 It is not required that the cost always equal 2 when FROM is the
3582 same as TO; on some machines it is expensive to move between
3583 registers if they are not general registers.
3585 If reload sees an insn consisting of a single `set' between two
3586 hard registers, and if `REGISTER_MOVE_COST' applied to their
3587 classes returns a value of 2, reload does not check to ensure
3588 that the constraints of the insn are met. Setting a cost of
3589 other than 2 will allow reload to verify that the constraints are
3590 met. You should do this if the `movM' pattern's constraints do
3591 not allow such copying. */
3593 #define REGISTER_MOVE_COST(FROM, TO) \
3594 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3595 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3596 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3597 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3598 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3599 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3600 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3601 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3602 : (((FROM) == HI_REG || (FROM) == LO_REG \
3603 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3604 && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \
3605 : (((FROM) == HI_REG || (FROM) == LO_REG \
3606 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3607 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 8 : 6) \
3608 : (((TO) == HI_REG || (TO) == LO_REG \
3609 || (TO) == MD_REGS || (TO) == HILO_REG) \
3610 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3611 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3612 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3615 /* ??? Fix this to be right for the R8000. */
3616 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3617 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3618 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3620 /* Define if copies to/from condition code registers should be avoided.
3622 This is needed for the MIPS because reload_outcc is not complete;
3623 it needs to handle cases where the source is a general or another
3624 condition code register. */
3625 #define AVOID_CCMODE_COPIES
3627 /* A C expression for the cost of a branch instruction. A value of
3628 1 is the default; other values are interpreted relative to that. */
3630 /* ??? Fix this to be right for the R8000. */
3631 #define BRANCH_COST \
3633 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3636 /* A C statement (sans semicolon) to update the integer variable COST
3637 based on the relationship between INSN that is dependent on
3638 DEP_INSN through the dependence LINK. The default is to make no
3639 adjustment to COST. On the MIPS, ignore the cost of anti- and
3640 output-dependencies. */
3642 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3643 if (REG_NOTE_KIND (LINK) != 0) \
3644 (COST) = 0; /* Anti or output dependence. */
3646 /* Optionally define this if you have added predicates to
3647 `MACHINE.c'. This macro is called within an initializer of an
3648 array of structures. The first field in the structure is the
3649 name of a predicate and the second field is an array of rtl
3650 codes. For each predicate, list all rtl codes that can be in
3651 expressions matched by the predicate. The list should have a
3652 trailing comma. Here is an example of two entries in the list
3653 for a typical RISC machine:
3655 #define PREDICATE_CODES \
3656 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3657 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3659 Defining this macro does not affect the generated code (however,
3660 incorrect definitions that omit an rtl code that may be matched
3661 by the predicate can cause the compiler to malfunction).
3662 Instead, it allows the table built by `genrecog' to be more
3663 compact and efficient, thus speeding up the compiler. The most
3664 important predicates to include in the list specified by this
3665 macro are thoses used in the most insn patterns. */
3667 #define PREDICATE_CODES \
3668 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3669 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3670 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3671 {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
3672 {"small_int", { CONST_INT }}, \
3673 {"large_int", { CONST_INT }}, \
3674 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3675 {"const_float_1_operand", { CONST_DOUBLE }}, \
3676 {"simple_memory_operand", { MEM, SUBREG }}, \
3677 {"equality_op", { EQ, NE }}, \
3678 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3680 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3681 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3682 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3683 SYMBOL_REF, LABEL_REF, SUBREG, \
3685 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3686 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3687 MEM, SIGN_EXTEND }}, \
3688 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3689 {"se_reg_or_0_operand", { REG, CONST_INT, SUBREG, \
3691 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3693 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3695 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3696 SYMBOL_REF, LABEL_REF, SUBREG, \
3697 REG, SIGN_EXTEND }}, \
3698 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3699 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3700 CONST_DOUBLE, CONST }}, \
3701 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3702 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3706 /* If defined, a C statement to be executed just prior to the
3707 output of assembler code for INSN, to modify the extracted
3708 operands so they will be output differently.
3710 Here the argument OPVEC is the vector containing the operands
3711 extracted from INSN, and NOPERANDS is the number of elements of
3712 the vector which contain meaningful data for this insn. The
3713 contents of this vector are what will be used to convert the
3714 insn template into assembler code, so you can change the
3715 assembler output by changing the contents of the vector.
3717 We use it to check if the current insn needs a nop in front of it
3718 because of load delays, and also to update the delay slot
3721 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3722 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3725 /* Control the assembler format that we output. */
3727 /* Output at beginning of assembler file.
3728 If we are optimizing to use the global pointer, create a temporary
3729 file to hold all of the text stuff, and write it out to the end.
3730 This is needed because the MIPS assembler is evidently one pass,
3731 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3732 declaration when the code is processed, it generates a two
3733 instruction sequence. */
3735 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3737 /* Output to assembler file text saying following lines
3738 may contain character constants, extra white space, comments, etc. */
3740 #define ASM_APP_ON " #APP\n"
3742 /* Output to assembler file text saying following lines
3743 no longer contain unusual constructs. */
3745 #define ASM_APP_OFF " #NO_APP\n"
3747 /* How to refer to registers in assembler output.
3748 This sequence is indexed by compiler's hard-register-number (see above).
3750 In order to support the two different conventions for register names,
3751 we use the name of a table set up in mips.c, which is overwritten
3752 if -mrnames is used. */
3754 #define REGISTER_NAMES \
3756 &mips_reg_names[ 0][0], \
3757 &mips_reg_names[ 1][0], \
3758 &mips_reg_names[ 2][0], \
3759 &mips_reg_names[ 3][0], \
3760 &mips_reg_names[ 4][0], \
3761 &mips_reg_names[ 5][0], \
3762 &mips_reg_names[ 6][0], \
3763 &mips_reg_names[ 7][0], \
3764 &mips_reg_names[ 8][0], \
3765 &mips_reg_names[ 9][0], \
3766 &mips_reg_names[10][0], \
3767 &mips_reg_names[11][0], \
3768 &mips_reg_names[12][0], \
3769 &mips_reg_names[13][0], \
3770 &mips_reg_names[14][0], \
3771 &mips_reg_names[15][0], \
3772 &mips_reg_names[16][0], \
3773 &mips_reg_names[17][0], \
3774 &mips_reg_names[18][0], \
3775 &mips_reg_names[19][0], \
3776 &mips_reg_names[20][0], \
3777 &mips_reg_names[21][0], \
3778 &mips_reg_names[22][0], \
3779 &mips_reg_names[23][0], \
3780 &mips_reg_names[24][0], \
3781 &mips_reg_names[25][0], \
3782 &mips_reg_names[26][0], \
3783 &mips_reg_names[27][0], \
3784 &mips_reg_names[28][0], \
3785 &mips_reg_names[29][0], \
3786 &mips_reg_names[30][0], \
3787 &mips_reg_names[31][0], \
3788 &mips_reg_names[32][0], \
3789 &mips_reg_names[33][0], \
3790 &mips_reg_names[34][0], \
3791 &mips_reg_names[35][0], \
3792 &mips_reg_names[36][0], \
3793 &mips_reg_names[37][0], \
3794 &mips_reg_names[38][0], \
3795 &mips_reg_names[39][0], \
3796 &mips_reg_names[40][0], \
3797 &mips_reg_names[41][0], \
3798 &mips_reg_names[42][0], \
3799 &mips_reg_names[43][0], \
3800 &mips_reg_names[44][0], \
3801 &mips_reg_names[45][0], \
3802 &mips_reg_names[46][0], \
3803 &mips_reg_names[47][0], \
3804 &mips_reg_names[48][0], \
3805 &mips_reg_names[49][0], \
3806 &mips_reg_names[50][0], \
3807 &mips_reg_names[51][0], \
3808 &mips_reg_names[52][0], \
3809 &mips_reg_names[53][0], \
3810 &mips_reg_names[54][0], \
3811 &mips_reg_names[55][0], \
3812 &mips_reg_names[56][0], \
3813 &mips_reg_names[57][0], \
3814 &mips_reg_names[58][0], \
3815 &mips_reg_names[59][0], \
3816 &mips_reg_names[60][0], \
3817 &mips_reg_names[61][0], \
3818 &mips_reg_names[62][0], \
3819 &mips_reg_names[63][0], \
3820 &mips_reg_names[64][0], \
3821 &mips_reg_names[65][0], \
3822 &mips_reg_names[66][0], \
3823 &mips_reg_names[67][0], \
3824 &mips_reg_names[68][0], \
3825 &mips_reg_names[69][0], \
3826 &mips_reg_names[70][0], \
3827 &mips_reg_names[71][0], \
3828 &mips_reg_names[72][0], \
3829 &mips_reg_names[73][0], \
3830 &mips_reg_names[74][0], \
3831 &mips_reg_names[75][0], \
3834 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3835 So define this for it. */
3836 #define DEBUG_REGISTER_NAMES \
3838 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3839 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3840 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3841 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3842 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3843 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3844 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3845 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3846 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3847 "$fcc5","$fcc6","$fcc7","$rap" \
3850 /* If defined, a C initializer for an array of structures
3851 containing a name and a register number. This macro defines
3852 additional names for hard registers, thus allowing the `asm'
3853 option in declarations to refer to registers using alternate
3856 We define both names for the integer registers here. */
3858 #define ADDITIONAL_REGISTER_NAMES \
3860 { "$0", 0 + GP_REG_FIRST }, \
3861 { "$1", 1 + GP_REG_FIRST }, \
3862 { "$2", 2 + GP_REG_FIRST }, \
3863 { "$3", 3 + GP_REG_FIRST }, \
3864 { "$4", 4 + GP_REG_FIRST }, \
3865 { "$5", 5 + GP_REG_FIRST }, \
3866 { "$6", 6 + GP_REG_FIRST }, \
3867 { "$7", 7 + GP_REG_FIRST }, \
3868 { "$8", 8 + GP_REG_FIRST }, \
3869 { "$9", 9 + GP_REG_FIRST }, \
3870 { "$10", 10 + GP_REG_FIRST }, \
3871 { "$11", 11 + GP_REG_FIRST }, \
3872 { "$12", 12 + GP_REG_FIRST }, \
3873 { "$13", 13 + GP_REG_FIRST }, \
3874 { "$14", 14 + GP_REG_FIRST }, \
3875 { "$15", 15 + GP_REG_FIRST }, \
3876 { "$16", 16 + GP_REG_FIRST }, \
3877 { "$17", 17 + GP_REG_FIRST }, \
3878 { "$18", 18 + GP_REG_FIRST }, \
3879 { "$19", 19 + GP_REG_FIRST }, \
3880 { "$20", 20 + GP_REG_FIRST }, \
3881 { "$21", 21 + GP_REG_FIRST }, \
3882 { "$22", 22 + GP_REG_FIRST }, \
3883 { "$23", 23 + GP_REG_FIRST }, \
3884 { "$24", 24 + GP_REG_FIRST }, \
3885 { "$25", 25 + GP_REG_FIRST }, \
3886 { "$26", 26 + GP_REG_FIRST }, \
3887 { "$27", 27 + GP_REG_FIRST }, \
3888 { "$28", 28 + GP_REG_FIRST }, \
3889 { "$29", 29 + GP_REG_FIRST }, \
3890 { "$30", 30 + GP_REG_FIRST }, \
3891 { "$31", 31 + GP_REG_FIRST }, \
3892 { "$sp", 29 + GP_REG_FIRST }, \
3893 { "$fp", 30 + GP_REG_FIRST }, \
3894 { "at", 1 + GP_REG_FIRST }, \
3895 { "v0", 2 + GP_REG_FIRST }, \
3896 { "v1", 3 + GP_REG_FIRST }, \
3897 { "a0", 4 + GP_REG_FIRST }, \
3898 { "a1", 5 + GP_REG_FIRST }, \
3899 { "a2", 6 + GP_REG_FIRST }, \
3900 { "a3", 7 + GP_REG_FIRST }, \
3901 { "t0", 8 + GP_REG_FIRST }, \
3902 { "t1", 9 + GP_REG_FIRST }, \
3903 { "t2", 10 + GP_REG_FIRST }, \
3904 { "t3", 11 + GP_REG_FIRST }, \
3905 { "t4", 12 + GP_REG_FIRST }, \
3906 { "t5", 13 + GP_REG_FIRST }, \
3907 { "t6", 14 + GP_REG_FIRST }, \
3908 { "t7", 15 + GP_REG_FIRST }, \
3909 { "s0", 16 + GP_REG_FIRST }, \
3910 { "s1", 17 + GP_REG_FIRST }, \
3911 { "s2", 18 + GP_REG_FIRST }, \
3912 { "s3", 19 + GP_REG_FIRST }, \
3913 { "s4", 20 + GP_REG_FIRST }, \
3914 { "s5", 21 + GP_REG_FIRST }, \
3915 { "s6", 22 + GP_REG_FIRST }, \
3916 { "s7", 23 + GP_REG_FIRST }, \
3917 { "t8", 24 + GP_REG_FIRST }, \
3918 { "t9", 25 + GP_REG_FIRST }, \
3919 { "k0", 26 + GP_REG_FIRST }, \
3920 { "k1", 27 + GP_REG_FIRST }, \
3921 { "gp", 28 + GP_REG_FIRST }, \
3922 { "sp", 29 + GP_REG_FIRST }, \
3923 { "fp", 30 + GP_REG_FIRST }, \
3924 { "ra", 31 + GP_REG_FIRST }, \
3925 { "$sp", 29 + GP_REG_FIRST }, \
3926 { "$fp", 30 + GP_REG_FIRST } \
3929 /* Define results of standard character escape sequences. */
3930 #define TARGET_BELL 007
3931 #define TARGET_BS 010
3932 #define TARGET_TAB 011
3933 #define TARGET_NEWLINE 012
3934 #define TARGET_VT 013
3935 #define TARGET_FF 014
3936 #define TARGET_CR 015
3938 /* A C compound statement to output to stdio stream STREAM the
3939 assembler syntax for an instruction operand X. X is an RTL
3942 CODE is a value that can be used to specify one of several ways
3943 of printing the operand. It is used when identical operands
3944 must be printed differently depending on the context. CODE
3945 comes from the `%' specification that was used to request
3946 printing of the operand. If the specification was just `%DIGIT'
3947 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3948 is the ASCII code for LTR.
3950 If X is a register, this macro should print the register's name.
3951 The names can be found in an array `reg_names' whose type is
3952 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3954 When the machine description has a specification `%PUNCT' (a `%'
3955 followed by a punctuation character), this macro is called with
3956 a null pointer for X and the punctuation character for CODE.
3958 See mips.c for the MIPS specific codes. */
3960 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3962 /* A C expression which evaluates to true if CODE is a valid
3963 punctuation character for use in the `PRINT_OPERAND' macro. If
3964 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3965 punctuation characters (except for the standard one, `%') are
3966 used in this way. */
3968 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3970 /* A C compound statement to output to stdio stream STREAM the
3971 assembler syntax for an instruction operand that is a memory
3972 reference whose address is ADDR. ADDR is an RTL expression.
3974 On some machines, the syntax for a symbolic address depends on
3975 the section that the address refers to. On these machines,
3976 define the macro `ENCODE_SECTION_INFO' to store the information
3977 into the `symbol_ref', and then check for it here. */
3979 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3982 /* A C statement, to be executed after all slot-filler instructions
3983 have been output. If necessary, call `dbr_sequence_length' to
3984 determine the number of slots filled in a sequence (zero if not
3985 currently outputting a sequence), to decide how many no-ops to
3986 output, or whatever.
3988 Don't define this macro if it has nothing to do, but it is
3989 helpful in reading assembly output if the extent of the delay
3990 sequence is made explicit (e.g. with white space).
3992 Note that output routines for instructions with delay slots must
3993 be prepared to deal with not being output as part of a sequence
3994 (i.e. when the scheduling pass is not run, or when no slot
3995 fillers could be found.) The variable `final_sequence' is null
3996 when not processing a sequence, otherwise it contains the
3997 `sequence' rtx being output. */
3999 #define DBR_OUTPUT_SEQEND(STREAM) \
4002 if (set_nomacro > 0 && --set_nomacro == 0) \
4003 fputs ("\t.set\tmacro\n", STREAM); \
4005 if (set_noreorder > 0 && --set_noreorder == 0) \
4006 fputs ("\t.set\treorder\n", STREAM); \
4008 dslots_jump_filled++; \
4009 fputs ("\n", STREAM); \
4014 /* How to tell the debugger about changes of source files. Note, the
4015 mips ECOFF format cannot deal with changes of files inside of
4016 functions, which means the output of parser generators like bison
4017 is generally not debuggable without using the -l switch. Lose,
4018 lose, lose. Silicon graphics seems to want all .file's hardwired
4021 #ifndef SET_FILE_NUMBER
4022 #define SET_FILE_NUMBER() ++num_source_filenames
4025 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4026 mips_output_filename (STREAM, NAME)
4028 /* This is defined so that it can be overridden in iris6.h. */
4029 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4032 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4033 output_quoted_string (STREAM, NAME); \
4034 fputs ("\n", STREAM); \
4038 /* This is how to output a note the debugger telling it the line number
4039 to which the following sequence of instructions corresponds.
4040 Silicon graphics puts a label after each .loc. */
4042 #ifndef LABEL_AFTER_LOC
4043 #define LABEL_AFTER_LOC(STREAM)
4046 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4047 mips_output_lineno (STREAM, LINE)
4049 /* The MIPS implementation uses some labels for its own purpose. The
4050 following lists what labels are created, and are all formed by the
4051 pattern $L[a-z].*. The machine independent portion of GCC creates
4052 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4054 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4055 $Lb[0-9]+ Begin blocks for MIPS debug support
4056 $Lc[0-9]+ Label for use in s<xx> operation.
4057 $Le[0-9]+ End blocks for MIPS debug support
4058 $Lp\..+ Half-pic labels. */
4060 /* This is how to output the definition of a user-level label named NAME,
4061 such as the label on a static function or variable NAME.
4063 If we are optimizing the gp, remember that this label has been put
4064 out, so we know not to emit an .extern for it in mips_asm_file_end.
4065 We use one of the common bits in the IDENTIFIER tree node for this,
4066 since those bits seem to be unused, and we don't have any method
4067 of getting the decl nodes from the name. */
4069 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4071 assemble_name (STREAM, NAME); \
4072 fputs (":\n", STREAM); \
4076 /* A C statement (sans semicolon) to output to the stdio stream
4077 STREAM any text necessary for declaring the name NAME of an
4078 initialized variable which is being defined. This macro must
4079 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4080 The argument DECL is the `VAR_DECL' tree node representing the
4083 If this macro is not defined, then the variable name is defined
4084 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4086 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4089 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4090 HALF_PIC_DECLARE (NAME); \
4095 /* This is how to output a command to make the user-level label named NAME
4096 defined for reference from other files. */
4098 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4100 fputs ("\t.globl\t", STREAM); \
4101 assemble_name (STREAM, NAME); \
4102 fputs ("\n", STREAM); \
4105 /* This says how to define a global common symbol. */
4107 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
4108 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
4110 /* This says how to define a local common symbol (ie, not visible to
4113 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4114 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4117 /* This says how to output an external. It would be possible not to
4118 output anything and let undefined symbol become external. However
4119 the assembler uses length information on externals to allocate in
4120 data/sdata bss/sbss, thereby saving exec time. */
4122 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4123 mips_output_external(STREAM,DECL,NAME)
4125 /* This says what to print at the end of the assembly file */
4126 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4129 /* This is how to declare a function name. The actual work of
4130 emitting the label is moved to function_prologue, so that we can
4131 get the line number correctly emitted before the .ent directive,
4132 and after any .file directives.
4134 Also, switch files if we are optimizing the global pointer. */
4136 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4138 extern FILE *asm_out_text_file; \
4139 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4141 STREAM = asm_out_text_file; \
4142 /* ??? text_section gets called too soon. If the previous \
4143 function is in a special section and we're not, we have \
4144 to switch back to the text section. We can't call \
4145 text_section again as gcc thinks we're already there. */ \
4146 /* ??? See varasm.c. There are other things that get output \
4147 too early, like alignment (before we've switched STREAM). */ \
4148 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4149 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4152 HALF_PIC_DECLARE (NAME); \
4155 /* This is how to output an internal numbered label where
4156 PREFIX is the class of label and NUM is the number within the class. */
4158 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4159 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4161 /* This is how to store into the string LABEL
4162 the symbol_ref name of an internal numbered label where
4163 PREFIX is the class of label and NUM is the number within the class.
4164 This is suitable for output with `assemble_name'. */
4166 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4167 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4169 /* This is how to output an assembler line defining a `double' constant. */
4171 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4172 mips_output_double (STREAM, VALUE)
4175 /* This is how to output an assembler line defining a `float' constant. */
4177 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4178 mips_output_float (STREAM, VALUE)
4181 /* This is how to output an assembler line defining an `int' constant. */
4183 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4185 fprintf (STREAM, "\t.word\t"); \
4186 output_addr_const (STREAM, (VALUE)); \
4187 fprintf (STREAM, "\n"); \
4190 /* Likewise for 64 bit, `char' and `short' constants. */
4192 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4196 fprintf (STREAM, "\t.dword\t"); \
4197 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4198 /* We can't use 'X' for negative numbers, because then we won't \
4199 get the right value for the upper 32 bits. */ \
4200 output_addr_const (STREAM, VALUE); \
4202 /* We must use 'X', because otherwise LONG_MIN will print as \
4203 a number that the Irix 6 assembler won't accept. */ \
4204 print_operand (STREAM, VALUE, 'X'); \
4205 fprintf (STREAM, "\n"); \
4209 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4210 UNITS_PER_WORD, 1); \
4211 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4212 UNITS_PER_WORD, 1); \
4216 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4218 fprintf (STREAM, "\t.half\t"); \
4219 output_addr_const (STREAM, (VALUE)); \
4220 fprintf (STREAM, "\n"); \
4223 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4225 fprintf (STREAM, "\t.byte\t"); \
4226 output_addr_const (STREAM, (VALUE)); \
4227 fprintf (STREAM, "\n"); \
4230 /* This is how to output an assembler line for a numeric constant byte. */
4232 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4233 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4235 /* This is how to output an element of a case-vector that is absolute. */
4237 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4238 fprintf (STREAM, "\t%s\t%sL%d\n", \
4239 Pmode == DImode ? ".dword" : ".word", \
4240 LOCAL_LABEL_PREFIX, \
4243 /* This is how to output an element of a case-vector that is relative.
4244 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4245 TARGET_EMBEDDED_PIC). */
4247 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4249 if (TARGET_MIPS16) \
4250 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4251 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4252 else if (TARGET_EMBEDDED_PIC) \
4253 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4254 Pmode == DImode ? ".dword" : ".word", \
4255 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4256 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4257 fprintf (STREAM, "\t%s\t%sL%d\n", \
4258 Pmode == DImode ? ".gpdword" : ".gpword", \
4259 LOCAL_LABEL_PREFIX, VALUE); \
4261 fprintf (STREAM, "\t%s\t%sL%d\n", \
4262 Pmode == DImode ? ".dword" : ".word", \
4263 LOCAL_LABEL_PREFIX, VALUE); \
4266 /* When generating embedded PIC or mips16 code we want to put the jump
4267 table in the .text section. In all other cases, we want to put the
4268 jump table in the .rdata section. Unfortunately, we can't use
4269 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4270 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4271 section if appropriate. */
4272 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4274 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4275 function_section (current_function_decl); \
4276 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4279 /* This is how to output an assembler line
4280 that says to advance the location counter
4281 to a multiple of 2**LOG bytes. */
4283 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4284 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4286 /* This is how to output an assembler line to advance the location
4287 counter by SIZE bytes. */
4289 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4290 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4292 /* This is how to output a string. */
4293 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4295 register int i, c, len = (LEN), cur_pos = 17; \
4296 register unsigned char *string = (unsigned char *)(STRING); \
4297 fprintf ((STREAM), "\t.ascii\t\""); \
4298 for (i = 0; i < len; i++) \
4300 register int c = string[i]; \
4306 putc ('\\', (STREAM)); \
4307 putc (c, (STREAM)); \
4311 case TARGET_NEWLINE: \
4312 fputs ("\\n", (STREAM)); \
4314 && (((c = string[i+1]) >= '\040' && c <= '~') \
4315 || c == TARGET_TAB)) \
4316 cur_pos = 32767; /* break right here */ \
4322 fputs ("\\t", (STREAM)); \
4327 fputs ("\\f", (STREAM)); \
4332 fputs ("\\b", (STREAM)); \
4337 fputs ("\\r", (STREAM)); \
4342 if (c >= ' ' && c < 0177) \
4344 putc (c, (STREAM)); \
4349 fprintf ((STREAM), "\\%03o", c); \
4354 if (cur_pos > 72 && i+1 < len) \
4357 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4360 fprintf ((STREAM), "\"\n"); \
4363 /* Handle certain cpp directives used in header files on sysV. */
4364 #define SCCS_DIRECTIVE
4366 /* Output #ident as a in the read-only data section. */
4367 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4370 int size = strlen (p) + 1; \
4372 assemble_string (p, size); \
4375 /* Default to -G 8 */
4376 #ifndef MIPS_DEFAULT_GVALUE
4377 #define MIPS_DEFAULT_GVALUE 8
4380 /* Define the strings to put out for each section in the object file. */
4381 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4382 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4383 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4384 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4385 #define READONLY_DATA_SECTION rdata_section
4386 #define SMALL_DATA_SECTION sdata_section
4388 /* What other sections we support other than the normal .data/.text. */
4390 #define EXTRA_SECTIONS in_sdata, in_rdata
4392 /* Define the additional functions to select our additional sections. */
4394 /* on the MIPS it is not a good idea to put constants in the text
4395 section, since this defeats the sdata/data mechanism. This is
4396 especially true when -O is used. In this case an effort is made to
4397 address with faster (gp) register relative addressing, which can
4398 only get at sdata and sbss items (there is no stext !!) However,
4399 if the constant is too large for sdata, and it's readonly, it
4400 will go into the .rdata section. */
4402 #define EXTRA_SECTION_FUNCTIONS \
4406 if (in_section != in_sdata) \
4408 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4409 in_section = in_sdata; \
4416 if (in_section != in_rdata) \
4418 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4419 in_section = in_rdata; \
4423 /* Given a decl node or constant node, choose the section to output it in
4424 and select that section. */
4426 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4428 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4431 /* Store in OUTPUT a string (made with alloca) containing
4432 an assembler-name for a local static variable named NAME.
4433 LABELNO is an integer which is different for each call. */
4435 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4436 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4437 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4439 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4442 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4443 TARGET_64BIT ? "dsubu" : "subu", \
4444 reg_names[STACK_POINTER_REGNUM], \
4445 reg_names[STACK_POINTER_REGNUM], \
4446 TARGET_64BIT ? "sd" : "sw", \
4448 reg_names[STACK_POINTER_REGNUM]); \
4452 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4455 if (! set_noreorder) \
4456 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4458 dslots_load_total++; \
4459 dslots_load_filled++; \
4460 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4461 TARGET_64BIT ? "ld" : "lw", \
4463 reg_names[STACK_POINTER_REGNUM], \
4464 TARGET_64BIT ? "daddu" : "addu", \
4465 reg_names[STACK_POINTER_REGNUM], \
4466 reg_names[STACK_POINTER_REGNUM]); \
4468 if (! set_noreorder) \
4469 fprintf (STREAM, "\t.set\treorder\n"); \
4473 /* Define the parentheses used to group arithmetic operations
4474 in assembler code. */
4476 #define ASM_OPEN_PAREN "("
4477 #define ASM_CLOSE_PAREN ")"
4479 /* How to start an assembler comment.
4480 The leading space is important (the mips native assembler requires it). */
4481 #ifndef ASM_COMMENT_START
4482 #define ASM_COMMENT_START " #"
4486 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4487 and mips-tdump.c to print them out.
4489 These must match the corresponding definitions in gdb/mipsread.c.
4490 Unfortunately, gcc and gdb do not currently share any directories. */
4492 #define CODE_MASK 0x8F300
4493 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4494 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4495 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4498 /* Default definitions for size_t and ptrdiff_t. */
4501 #define NO_BUILTIN_SIZE_TYPE
4502 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4505 #ifndef PTRDIFF_TYPE
4506 #define NO_BUILTIN_PTRDIFF_TYPE
4507 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4510 /* See mips_expand_prologue's use of loadgp for when this should be
4513 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4514 && mips_abi != ABI_32 \
4515 && mips_abi != ABI_O64)
4517 /* In mips16 mode, we need to look through the function to check for
4518 PC relative loads that are out of range. */
4519 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4521 /* We need to use a special set of functions to handle hard floating
4522 point code in mips16 mode. */
4524 #ifndef INIT_SUBTARGET_OPTABS
4525 #define INIT_SUBTARGET_OPTABS
4528 #define INIT_TARGET_OPTABS \
4531 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4532 INIT_SUBTARGET_OPTABS; \
4535 add_optab->handlers[(int) SFmode].libfunc = \
4536 gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3"); \
4537 sub_optab->handlers[(int) SFmode].libfunc = \
4538 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3"); \
4539 smul_optab->handlers[(int) SFmode].libfunc = \
4540 gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3"); \
4541 flodiv_optab->handlers[(int) SFmode].libfunc = \
4542 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3"); \
4544 eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2"); \
4545 nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2"); \
4546 gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2"); \
4547 gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2"); \
4548 ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2"); \
4549 lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2"); \
4551 floatsisf_libfunc = \
4552 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf"); \
4554 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi"); \
4556 if (TARGET_DOUBLE_FLOAT) \
4558 add_optab->handlers[(int) DFmode].libfunc = \
4559 gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3"); \
4560 sub_optab->handlers[(int) DFmode].libfunc = \
4561 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3"); \
4562 smul_optab->handlers[(int) DFmode].libfunc = \
4563 gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3"); \
4564 flodiv_optab->handlers[(int) DFmode].libfunc = \
4565 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3"); \
4567 extendsfdf2_libfunc = \
4568 gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2"); \
4569 truncdfsf2_libfunc = \
4570 gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2"); \
4573 gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2"); \
4575 gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2"); \
4577 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2"); \
4579 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2"); \
4581 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2"); \
4583 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2"); \
4585 floatsidf_libfunc = \
4586 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf"); \
4588 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi"); \
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