1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
27 #include "config/vxworks-dummy.h"
29 /* MIPS external variables defined in mips.c. */
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
73 /* Costs of various operations on the different architectures. */
75 struct mips_rtx_cost_data
77 unsigned short fp_add;
78 unsigned short fp_mult_sf;
79 unsigned short fp_mult_df;
80 unsigned short fp_div_sf;
81 unsigned short fp_div_df;
82 unsigned short int_mult_si;
83 unsigned short int_mult_di;
84 unsigned short int_div_si;
85 unsigned short int_div_di;
86 unsigned short branch_cost;
87 unsigned short memory_latency;
90 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
91 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
92 to work on a 64-bit machine. */
100 /* Information about one recognized processor. Defined here for the
101 benefit of TARGET_CPU_CPP_BUILTINS. */
102 struct mips_cpu_info {
103 /* The 'canonical' name of the processor as far as GCC is concerned.
104 It's typically a manufacturer's prefix followed by a numerical
105 designation. It should be lowercase. */
108 /* The internal processor number that most closely matches this
109 entry. Several processors can have the same value, if there's no
110 difference between them from GCC's point of view. */
111 enum processor_type cpu;
113 /* The ISA level that the processor implements. */
117 #ifndef USED_FOR_TARGET
118 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
119 extern const char *current_function_file; /* filename current function is in */
120 extern int num_source_filenames; /* current .file # */
121 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
122 extern int sym_lineno; /* sgi next label # for each stmt */
123 extern int set_noreorder; /* # of nested .set noreorder's */
124 extern int set_nomacro; /* # of nested .set nomacro's */
125 extern int set_noat; /* # of nested .set noat's */
126 extern int set_volatile; /* # of nested .set volatile's */
127 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
128 extern int mips_dbx_regno[];
129 extern int mips_dwarf_regno[];
130 extern bool mips_split_p[];
131 extern GTY(()) rtx cmp_operands[2];
132 extern enum processor_type mips_arch; /* which cpu to codegen for */
133 extern enum processor_type mips_tune; /* which cpu to schedule for */
134 extern int mips_isa; /* architectural level */
135 extern int mips_abi; /* which ABI to use */
136 extern int mips16_hard_float; /* mips16 without -msoft-float */
137 extern const struct mips_cpu_info mips_cpu_info_table[];
138 extern const struct mips_cpu_info *mips_arch_info;
139 extern const struct mips_cpu_info *mips_tune_info;
140 extern const struct mips_rtx_cost_data *mips_cost;
143 /* Macros to silence warnings about numbers being signed in traditional
144 C and unsigned in ISO C when compiled on 32-bit hosts. */
146 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
147 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
148 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
151 /* Run-time compilation parameters selecting different hardware subsets. */
153 /* True if we are generating position-independent VxWorks RTP code. */
154 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
156 /* True if the call patterns should be split into a jalr followed by
157 an instruction to restore $gp. It is only safe to split the load
158 from the call when every use of $gp is explicit. */
160 #define TARGET_SPLIT_CALLS \
161 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
163 /* True if we're generating a form of -mabicalls in which we can use
164 operators like %hi and %lo to refer to locally-binding symbols.
165 We can only do this for -mno-shared, and only then if we can use
166 relocation operations instead of assembly macros. It isn't really
167 worth using absolute sequences for 64-bit symbols because GOT
168 accesses are so much shorter. */
170 #define TARGET_ABSOLUTE_ABICALLS \
173 && TARGET_EXPLICIT_RELOCS \
174 && !ABI_HAS_64BIT_SYMBOLS)
176 /* True if we can optimize sibling calls. For simplicity, we only
177 handle cases in which call_insn_operand will reject invalid
178 sibcall addresses. There are two cases in which this isn't true:
180 - TARGET_MIPS16. call_insn_operand accepts constant addresses
181 but there is no direct jump instruction. It isn't worth
182 using sibling calls in this case anyway; they would usually
183 be longer than normal calls.
185 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
186 accepts global constants, but all sibcalls must be indirect. */
187 #define TARGET_SIBCALLS \
188 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
190 /* True if we need to use a global offset table to access some symbols. */
191 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
193 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
194 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
196 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
197 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
199 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
200 This is true for both the PIC and non-PIC VxWorks RTP modes. */
201 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
203 /* True if .gpword or .gpdword should be used for switch tables.
205 Although GAS does understand .gpdword, the SGI linker mishandles
206 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
207 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
208 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
210 /* Generate mips16 code */
211 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
212 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
213 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
214 /* Generate mips16e register save/restore sequences. */
215 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
217 /* Generic ISA defines. */
218 #define ISA_MIPS1 (mips_isa == 1)
219 #define ISA_MIPS2 (mips_isa == 2)
220 #define ISA_MIPS3 (mips_isa == 3)
221 #define ISA_MIPS4 (mips_isa == 4)
222 #define ISA_MIPS32 (mips_isa == 32)
223 #define ISA_MIPS32R2 (mips_isa == 33)
224 #define ISA_MIPS64 (mips_isa == 64)
226 /* Architecture target defines. */
227 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
228 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
229 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
230 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
231 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
232 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
233 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
234 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
235 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
236 || mips_arch == PROCESSOR_SB1A)
237 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
239 /* Scheduling target defines. */
240 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
241 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
242 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
243 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
244 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
245 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
246 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
247 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
248 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
249 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
250 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
251 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
252 || mips_tune == PROCESSOR_SB1A)
253 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
254 || mips_tune == PROCESSOR_24KF2_1 \
255 || mips_tune == PROCESSOR_24KF1_1)
256 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
257 || mips_tune == PROCESSOR_74KF2_1 \
258 || mips_tune == PROCESSOR_74KF1_1 \
259 || mips_tune == PROCESSOR_74KF3_2)
260 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
262 /* True if the pre-reload scheduler should try to create chains of
263 multiply-add or multiply-subtract instructions. For example,
271 t1 will have a higher priority than t2 and t3 will have a higher
272 priority than t4. However, before reload, there is no dependence
273 between t1 and t3, and they can often have similar priorities.
274 The scheduler will then tend to prefer:
281 which stops us from making full use of macc/madd-style instructions.
282 This sort of situation occurs frequently in Fourier transforms and
285 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
286 queue so that chained multiply-add and multiply-subtract instructions
287 appear ahead of any other instruction that is likely to clobber lo.
288 In the example above, if t2 and t3 become ready at the same time,
289 the code ensures that t2 is scheduled first.
291 Multiply-accumulate instructions are a bigger win for some targets
292 than others, so this macro is defined on an opt-in basis. */
293 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
298 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
299 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
301 /* Similar to TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT, but reflect the ABI
302 in use rather than whether the FPU is directly accessible. */
303 #define TARGET_HARD_FLOAT_ABI (TARGET_HARD_FLOAT || mips16_hard_float)
304 #define TARGET_SOFT_FLOAT_ABI (!TARGET_HARD_FLOAT_ABI)
306 /* IRIX specific stuff. */
307 #define TARGET_IRIX 0
308 #define TARGET_IRIX6 0
310 /* Define preprocessor macros for the -march and -mtune options.
311 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
312 processor. If INFO's canonical name is "foo", define PREFIX to
313 be "foo", and define an additional macro PREFIX_FOO. */
314 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
319 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
320 for (p = macro; *p != 0; p++) \
323 builtin_define (macro); \
324 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
329 /* Target CPU builtins. */
330 #define TARGET_CPU_CPP_BUILTINS() \
333 /* Everyone but IRIX defines this to mips. */ \
335 builtin_assert ("machine=mips"); \
337 builtin_assert ("cpu=mips"); \
338 builtin_define ("__mips__"); \
339 builtin_define ("_mips"); \
341 /* We do this here because __mips is defined below \
342 and so we can't use builtin_define_std. */ \
344 builtin_define ("mips"); \
347 builtin_define ("__mips64"); \
351 /* Treat _R3000 and _R4000 like register-size \
352 defines, which is how they've historically \
356 builtin_define_std ("R4000"); \
357 builtin_define ("_R4000"); \
361 builtin_define_std ("R3000"); \
362 builtin_define ("_R3000"); \
365 if (TARGET_FLOAT64) \
366 builtin_define ("__mips_fpr=64"); \
368 builtin_define ("__mips_fpr=32"); \
371 builtin_define ("__mips16"); \
374 builtin_define ("__mips3d"); \
376 if (TARGET_SMARTMIPS) \
377 builtin_define ("__mips_smartmips"); \
381 builtin_define ("__mips_dsp"); \
384 builtin_define ("__mips_dspr2"); \
385 builtin_define ("__mips_dsp_rev=2"); \
388 builtin_define ("__mips_dsp_rev=1"); \
391 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
392 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
396 builtin_define ("__mips=1"); \
397 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
399 else if (ISA_MIPS2) \
401 builtin_define ("__mips=2"); \
402 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
404 else if (ISA_MIPS3) \
406 builtin_define ("__mips=3"); \
407 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
409 else if (ISA_MIPS4) \
411 builtin_define ("__mips=4"); \
412 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
414 else if (ISA_MIPS32) \
416 builtin_define ("__mips=32"); \
417 builtin_define ("__mips_isa_rev=1"); \
418 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
420 else if (ISA_MIPS32R2) \
422 builtin_define ("__mips=32"); \
423 builtin_define ("__mips_isa_rev=2"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
426 else if (ISA_MIPS64) \
428 builtin_define ("__mips=64"); \
429 builtin_define ("__mips_isa_rev=1"); \
430 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
436 builtin_define ("_ABIO32=1"); \
437 builtin_define ("_MIPS_SIM=_ABIO32"); \
441 builtin_define ("_ABIN32=2"); \
442 builtin_define ("_MIPS_SIM=_ABIN32"); \
446 builtin_define ("_ABI64=3"); \
447 builtin_define ("_MIPS_SIM=_ABI64"); \
451 builtin_define ("_ABIO64=4"); \
452 builtin_define ("_MIPS_SIM=_ABIO64"); \
456 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
457 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
458 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
459 builtin_define_with_int_value ("_MIPS_FPSET", \
460 32 / MAX_FPRS_PER_FMT); \
462 /* These defines reflect the ABI in use, not whether the \
463 FPU is directly accessible. */ \
464 if (TARGET_HARD_FLOAT_ABI) \
465 builtin_define ("__mips_hard_float"); \
467 builtin_define ("__mips_soft_float"); \
469 if (TARGET_SINGLE_FLOAT) \
470 builtin_define ("__mips_single_float"); \
472 if (TARGET_PAIRED_SINGLE_FLOAT) \
473 builtin_define ("__mips_paired_single_float"); \
475 if (TARGET_BIG_ENDIAN) \
477 builtin_define_std ("MIPSEB"); \
478 builtin_define ("_MIPSEB"); \
482 builtin_define_std ("MIPSEL"); \
483 builtin_define ("_MIPSEL"); \
486 /* Macros dependent on the C dialect. */ \
487 if (preprocessing_asm_p ()) \
489 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
490 builtin_define ("_LANGUAGE_ASSEMBLY"); \
492 else if (c_dialect_cxx ()) \
494 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
495 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
496 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
500 builtin_define_std ("LANGUAGE_C"); \
501 builtin_define ("_LANGUAGE_C"); \
503 if (c_dialect_objc ()) \
505 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
506 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
507 /* Bizarre, but needed at least for Irix. */ \
508 builtin_define_std ("LANGUAGE_C"); \
509 builtin_define ("_LANGUAGE_C"); \
512 if (mips_abi == ABI_EABI) \
513 builtin_define ("__mips_eabi"); \
517 /* Default target_flags if no switches are specified */
519 #ifndef TARGET_DEFAULT
520 #define TARGET_DEFAULT 0
523 #ifndef TARGET_CPU_DEFAULT
524 #define TARGET_CPU_DEFAULT 0
527 #ifndef TARGET_ENDIAN_DEFAULT
528 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
531 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
532 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
535 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
536 #ifndef MIPS_ISA_DEFAULT
537 #ifndef MIPS_CPU_STRING_DEFAULT
538 #define MIPS_CPU_STRING_DEFAULT "from-abi"
544 /* Make this compile time constant for libgcc2 */
546 #define TARGET_64BIT 1
548 #define TARGET_64BIT 0
550 #endif /* IN_LIBGCC2 */
552 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
554 #ifndef MULTILIB_ENDIAN_DEFAULT
555 #if TARGET_ENDIAN_DEFAULT == 0
556 #define MULTILIB_ENDIAN_DEFAULT "EL"
558 #define MULTILIB_ENDIAN_DEFAULT "EB"
562 #ifndef MULTILIB_ISA_DEFAULT
563 # if MIPS_ISA_DEFAULT == 1
564 # define MULTILIB_ISA_DEFAULT "mips1"
566 # if MIPS_ISA_DEFAULT == 2
567 # define MULTILIB_ISA_DEFAULT "mips2"
569 # if MIPS_ISA_DEFAULT == 3
570 # define MULTILIB_ISA_DEFAULT "mips3"
572 # if MIPS_ISA_DEFAULT == 4
573 # define MULTILIB_ISA_DEFAULT "mips4"
575 # if MIPS_ISA_DEFAULT == 32
576 # define MULTILIB_ISA_DEFAULT "mips32"
578 # if MIPS_ISA_DEFAULT == 33
579 # define MULTILIB_ISA_DEFAULT "mips32r2"
581 # if MIPS_ISA_DEFAULT == 64
582 # define MULTILIB_ISA_DEFAULT "mips64"
584 # define MULTILIB_ISA_DEFAULT "mips1"
594 #ifndef MULTILIB_DEFAULTS
595 #define MULTILIB_DEFAULTS \
596 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
599 /* We must pass -EL to the linker by default for little endian embedded
600 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
601 linker will default to using big-endian output files. The OUTPUT_FORMAT
602 line must be in the linker script, otherwise -EB/-EL will not work. */
605 #if TARGET_ENDIAN_DEFAULT == 0
606 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
608 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
612 /* A spec condition that matches all non-mips16 -mips arguments. */
614 #define MIPS_ISA_LEVEL_OPTION_SPEC \
615 "mips1|mips2|mips3|mips4|mips32*|mips64*"
617 /* A spec condition that matches all non-mips16 architecture arguments. */
619 #define MIPS_ARCH_OPTION_SPEC \
620 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
622 /* A spec that infers a -mips argument from an -march argument,
623 or injects the default if no architecture is specified. */
625 #define MIPS_ISA_LEVEL_SPEC \
626 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
627 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
628 %{march=mips2|march=r6000:-mips2} \
629 %{march=mips3|march=r4*|march=vr4*|march=orion:-mips3} \
630 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
631 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
632 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
633 |march=34k*|march=74k*: -mips32r2} \
634 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
635 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
637 /* A spec condition that matches 32-bit options. It only works if
638 MIPS_ISA_LEVEL_SPEC has been applied. */
640 #define MIPS_32BIT_OPTION_SPEC \
641 "mips1|mips2|mips32*|mgp32"
643 /* Support for a compile-time default CPU, et cetera. The rules are:
644 --with-arch is ignored if -march is specified or a -mips is specified
645 (other than -mips16).
646 --with-tune is ignored if -mtune is specified.
647 --with-abi is ignored if -mabi is specified.
648 --with-float is ignored if -mhard-float or -msoft-float are
650 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
652 #define OPTION_DEFAULT_SPECS \
653 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
654 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
655 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
656 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
657 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
660 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
661 && ISA_HAS_COND_TRAP)
663 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
667 /* True if the ABI can only work with 64-bit integer registers. We
668 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
669 otherwise floating-point registers must also be 64-bit. */
670 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
672 /* Likewise for 32-bit regs. */
673 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
675 /* True if symbols are 64 bits wide. At present, n64 is the only
676 ABI for which this is true. */
677 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
679 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
680 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
684 /* ISA has branch likely instructions (e.g. mips2). */
685 /* Disable branchlikely for tx39 until compare rewrite. They haven't
686 been generated up to this point. */
687 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
689 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
690 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
701 /* ISA has the conditional move instructions introduced in mips4. */
702 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
706 && !TARGET_MIPS5500 \
709 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
710 branch on CC, and move (both FP and non-FP) on CC. */
711 #define ISA_HAS_8CC (ISA_MIPS4 \
716 /* This is a catch all for other mips4 instructions: indexed load, the
717 FP madd and msub instructions, and the FP recip and recip sqrt
719 #define ISA_HAS_FP4 ((ISA_MIPS4 \
720 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
724 /* ISA has conditional trap instructions. */
725 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
728 /* ISA has integer multiply-accumulate instructions, madd and msub. */
729 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
734 /* Integer multiply-accumulate instructions should be generated. */
735 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
737 /* ISA has floating-point nmadd and nmsub instructions. */
738 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
740 && (!TARGET_MIPS5400 || TARGET_MAD) \
743 /* ISA has count leading zeroes/ones instruction (not implemented). */
744 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
749 /* ISA has three operand multiply instructions that put
750 the high part in an accumulator: mulhi or mulhiu. */
751 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
756 /* ISA has three operand multiply instructions that
757 negates the result and puts the result in an accumulator. */
758 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
763 /* ISA has three operand multiply instructions that subtracts the
764 result from a 4th operand and puts the result in an accumulator. */
765 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
770 /* ISA has three operand multiply instructions that the result
771 from a 4th operand and puts the result in an accumulator. */
772 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
779 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
780 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
781 || TARGET_MIPS4130) \
784 /* ISA has the "ror" (rotate right) instructions. */
785 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
789 || TARGET_SMARTMIPS) \
792 /* ISA has data prefetch instructions. This controls use of 'pref'. */
793 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
799 /* ISA has data indexed prefetch instructions. This controls use of
800 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
801 (prefx is a cop1x instruction, so can only be used if FP is
803 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
808 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
809 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
810 also requires TARGET_DOUBLE_FLOAT. */
811 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
813 /* ISA includes the MIPS32r2 seb and seh instructions. */
814 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
817 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
818 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
821 /* ISA has instructions for accessing top part of 64-bit fp regs. */
822 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
824 /* ISA has lwxs instruction (load w/scaled index address. */
825 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
827 /* True if the result of a load is not available to the next instruction.
828 A nop will then be needed between instructions like "lw $4,..."
829 and "addiu $4,$4,1". */
830 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
831 && !TARGET_MIPS3900 \
834 /* Likewise mtc1 and mfc1. */
835 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
837 /* Likewise floating-point comparisons. */
838 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
840 /* True if mflo and mfhi can be immediately followed by instructions
841 which write to the HI and LO registers.
843 According to MIPS specifications, MIPS ISAs I, II, and III need
844 (at least) two instructions between the reads of HI/LO and
845 instructions which write them, and later ISAs do not. Contradicting
846 the MIPS specifications, some MIPS IV processor user manuals (e.g.
847 the UM for the NEC Vr5000) document needing the instructions between
848 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
849 MIPS64 and later ISAs to have the interlocks, plus any specific
850 earlier-ISA CPUs for which CPU documentation declares that the
851 instructions are really interlocked. */
852 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
857 /* ISA includes synci, jr.hb and jalr.hb. */
858 #define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16)
861 /* Add -G xx support. */
863 #undef SWITCH_TAKES_ARG
864 #define SWITCH_TAKES_ARG(CHAR) \
865 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
867 #define OVERRIDE_OPTIONS override_options ()
869 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
871 /* Show we can debug even without a frame pointer. */
872 #define CAN_DEBUG_WITHOUT_FP
874 /* Tell collect what flags to pass to nm. */
876 #define NM_FLAGS "-Bn"
880 #ifndef MIPS_ABI_DEFAULT
881 #define MIPS_ABI_DEFAULT ABI_32
884 /* Use the most portable ABI flag for the ASM specs. */
886 #if MIPS_ABI_DEFAULT == ABI_32
887 #define MULTILIB_ABI_DEFAULT "mabi=32"
890 #if MIPS_ABI_DEFAULT == ABI_O64
891 #define MULTILIB_ABI_DEFAULT "mabi=o64"
894 #if MIPS_ABI_DEFAULT == ABI_N32
895 #define MULTILIB_ABI_DEFAULT "mabi=n32"
898 #if MIPS_ABI_DEFAULT == ABI_64
899 #define MULTILIB_ABI_DEFAULT "mabi=64"
902 #if MIPS_ABI_DEFAULT == ABI_EABI
903 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
906 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
907 to the assembler. It may be overridden by subtargets. */
908 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
909 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
911 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
914 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
915 the assembler. It may be overridden by subtargets.
917 Beginning with gas 2.13, -mdebug must be passed to correctly handle
918 COFF debugging info. */
920 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
921 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
922 %{g} %{g0} %{g1} %{g2} %{g3} \
923 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
924 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
925 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
926 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
927 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
930 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
931 overridden by subtargets. */
933 #ifndef SUBTARGET_ASM_SPEC
934 #define SUBTARGET_ASM_SPEC ""
939 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
940 %{mips32} %{mips32r2} %{mips64} \
941 %{mips16} %{mno-mips16:-no-mips16} \
942 %{mips3d} %{mno-mips3d:-no-mips3d} \
943 %{mdmx} %{mno-mdmx:-no-mdmx} \
945 %{mdspr2} %{mno-dspr2} \
946 %{msmartmips} %{mno-smartmips} \
948 %{mfix-vr4120} %{mfix-vr4130} \
949 %(subtarget_asm_optimizing_spec) \
950 %(subtarget_asm_debugging_spec) \
951 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
952 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
954 %{mshared} %{mno-shared} \
955 %{msym32} %{mno-sym32} \
957 %(subtarget_asm_spec)"
959 /* Extra switches sometimes passed to the linker. */
960 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
961 will interpret it as a -b option. */
966 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
967 %{bestGnum} %{shared} %{non_shared}"
968 #endif /* LINK_SPEC defined */
971 /* Specs for the compiler proper */
973 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
974 overridden by subtargets. */
975 #ifndef SUBTARGET_CC1_SPEC
976 #define SUBTARGET_CC1_SPEC ""
979 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
983 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
984 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
986 %(subtarget_cc1_spec)"
988 /* Preprocessor specs. */
990 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
991 overridden by subtargets. */
992 #ifndef SUBTARGET_CPP_SPEC
993 #define SUBTARGET_CPP_SPEC ""
996 #define CPP_SPEC "%(subtarget_cpp_spec)"
998 /* This macro defines names of additional specifications to put in the specs
999 that can be used in various specifications like CC1_SPEC. Its definition
1000 is an initializer with a subgrouping for each command option.
1002 Each subgrouping contains a string constant, that defines the
1003 specification name, and a string constant that used by the GCC driver
1006 Do not define this macro if it does not need to do anything. */
1008 #define EXTRA_SPECS \
1009 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1010 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1011 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1012 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1013 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1014 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1015 { "endian_spec", ENDIAN_SPEC }, \
1016 SUBTARGET_EXTRA_SPECS
1018 #ifndef SUBTARGET_EXTRA_SPECS
1019 #define SUBTARGET_EXTRA_SPECS
1022 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1023 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1024 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1026 #ifndef PREFERRED_DEBUGGING_TYPE
1027 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1030 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1032 /* By default, turn on GDB extensions. */
1033 #define DEFAULT_GDB_EXTENSIONS 1
1035 /* Local compiler-generated symbols must have a prefix that the assembler
1036 understands. By default, this is $, although some targets (e.g.,
1037 NetBSD-ELF) need to override this. */
1039 #ifndef LOCAL_LABEL_PREFIX
1040 #define LOCAL_LABEL_PREFIX "$"
1043 /* By default on the mips, external symbols do not have an underscore
1044 prepended, but some targets (e.g., NetBSD) require this. */
1046 #ifndef USER_LABEL_PREFIX
1047 #define USER_LABEL_PREFIX ""
1050 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1051 since the length can run past this up to a continuation point. */
1052 #undef DBX_CONTIN_LENGTH
1053 #define DBX_CONTIN_LENGTH 1500
1055 /* How to renumber registers for dbx and gdb. */
1056 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1058 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1059 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1061 /* The DWARF 2 CFA column which tracks the return address. */
1062 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1064 /* Before the prologue, RA lives in r31. */
1065 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1067 /* Describe how we implement __builtin_eh_return. */
1068 #define EH_RETURN_DATA_REGNO(N) \
1069 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1071 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1073 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1074 The default for this in 64-bit mode is 8, which causes problems with
1075 SFmode register saves. */
1076 #define DWARF_CIE_DATA_ALIGNMENT -4
1078 /* Correct the offset of automatic variables and arguments. Note that
1079 the MIPS debug format wants all automatic variables and arguments
1080 to be in terms of the virtual frame pointer (stack pointer before
1081 any adjustment in the function), while the MIPS 3.0 linker wants
1082 the frame pointer to be the stack pointer after the initial
1085 #define DEBUGGER_AUTO_OFFSET(X) \
1086 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1087 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1088 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1090 /* Target machine storage layout */
1092 #define BITS_BIG_ENDIAN 0
1093 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1094 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1096 /* Define this to set the endianness to use in libgcc2.c, which can
1097 not depend on target_flags. */
1098 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1099 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1101 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1104 #define MAX_BITS_PER_WORD 64
1106 /* Width of a word, in units (bytes). */
1107 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1109 #define MIN_UNITS_PER_WORD 4
1112 /* For MIPS, width of a floating point register. */
1113 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1115 /* The number of consecutive floating-point registers needed to store the
1116 largest format supported by the FPU. */
1117 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1119 /* The number of consecutive floating-point registers needed to store the
1120 smallest format supported by the FPU. */
1121 #define MIN_FPRS_PER_FMT \
1122 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1124 /* The largest size of value that can be held in floating-point
1125 registers and moved with a single instruction. */
1126 #define UNITS_PER_HWFPVALUE \
1127 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1129 /* The largest size of value that can be held in floating-point
1131 #define UNITS_PER_FPVALUE \
1132 (TARGET_SOFT_FLOAT_ABI ? 0 \
1133 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1134 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1136 /* The number of bytes in a double. */
1137 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1139 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1141 /* Set the sizes of the core types. */
1142 #define SHORT_TYPE_SIZE 16
1143 #define INT_TYPE_SIZE 32
1144 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1145 #define LONG_LONG_TYPE_SIZE 64
1147 #define FLOAT_TYPE_SIZE 32
1148 #define DOUBLE_TYPE_SIZE 64
1149 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1151 /* long double is not a fixed mode, but the idea is that, if we
1152 support long double, we also want a 128-bit integer type. */
1153 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1156 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1157 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1158 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1160 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1164 /* Width in bits of a pointer. */
1165 #ifndef POINTER_SIZE
1166 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1169 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1170 #define PARM_BOUNDARY BITS_PER_WORD
1172 /* Allocation boundary (in *bits*) for the code of a function. */
1173 #define FUNCTION_BOUNDARY 32
1175 /* Alignment of field after `int : 0' in a structure. */
1176 #define EMPTY_FIELD_BOUNDARY 32
1178 /* Every structure's size must be a multiple of this. */
1179 /* 8 is observed right on a DECstation and on riscos 4.02. */
1180 #define STRUCTURE_SIZE_BOUNDARY 8
1182 /* There is no point aligning anything to a rounder boundary than this. */
1183 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1185 /* All accesses must be aligned. */
1186 #define STRICT_ALIGNMENT 1
1188 /* Define this if you wish to imitate the way many other C compilers
1189 handle alignment of bitfields and the structures that contain
1192 The behavior is that the type written for a bit-field (`int',
1193 `short', or other integer type) imposes an alignment for the
1194 entire structure, as if the structure really did contain an
1195 ordinary field of that type. In addition, the bit-field is placed
1196 within the structure so that it would fit within such a field,
1197 not crossing a boundary for it.
1199 Thus, on most machines, a bit-field whose type is written as `int'
1200 would not cross a four-byte boundary, and would force four-byte
1201 alignment for the whole structure. (The alignment used may not
1202 be four bytes; it is controlled by the other alignment
1205 If the macro is defined, its definition should be a C expression;
1206 a nonzero value for the expression enables this behavior. */
1208 #define PCC_BITFIELD_TYPE_MATTERS 1
1210 /* If defined, a C expression to compute the alignment given to a
1211 constant that is being placed in memory. CONSTANT is the constant
1212 and ALIGN is the alignment that the object would ordinarily have.
1213 The value of this macro is used instead of that alignment to align
1216 If this macro is not defined, then ALIGN is used.
1218 The typical use of this macro is to increase alignment for string
1219 constants to be word aligned so that `strcpy' calls that copy
1220 constants can be done inline. */
1222 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1223 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1224 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1226 /* If defined, a C expression to compute the alignment for a static
1227 variable. TYPE is the data type, and ALIGN is the alignment that
1228 the object would ordinarily have. The value of this macro is used
1229 instead of that alignment to align the object.
1231 If this macro is not defined, then ALIGN is used.
1233 One use of this macro is to increase alignment of medium-size
1234 data to make it all fit in fewer cache lines. Another is to
1235 cause character arrays to be word-aligned so that `strcpy' calls
1236 that copy constants to character arrays can be done inline. */
1238 #undef DATA_ALIGNMENT
1239 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1240 ((((ALIGN) < BITS_PER_WORD) \
1241 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1242 || TREE_CODE (TYPE) == UNION_TYPE \
1243 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1246 #define PAD_VARARGS_DOWN \
1247 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1249 /* Define if operations between registers always perform the operation
1250 on the full register even if a narrower mode is specified. */
1251 #define WORD_REGISTER_OPERATIONS
1253 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1254 moves. All other references are zero extended. */
1255 #define LOAD_EXTEND_OP(MODE) \
1256 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1257 ? SIGN_EXTEND : ZERO_EXTEND)
1259 /* Define this macro if it is advisable to hold scalars in registers
1260 in a wider mode than that declared by the program. In such cases,
1261 the value is constrained to be within the bounds of the declared
1262 type, but kept valid in the wider mode. The signedness of the
1263 extension may differ from that of the type. */
1265 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1266 if (GET_MODE_CLASS (MODE) == MODE_INT \
1267 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1269 if ((MODE) == SImode) \
1274 /* Define if loading short immediate values into registers sign extends. */
1275 #define SHORT_IMMEDIATES_SIGN_EXTEND
1277 /* The [d]clz instructions have the natural values at 0. */
1279 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1280 ((VALUE) = GET_MODE_BITSIZE (MODE), true)
1282 /* Standard register usage. */
1284 /* Number of hardware registers. We have:
1286 - 32 integer registers
1287 - 32 floating point registers
1288 - 8 condition code registers
1289 - 2 accumulator registers (hi and lo)
1290 - 32 registers each for coprocessors 0, 2 and 3
1292 - ARG_POINTER_REGNUM
1293 - FRAME_POINTER_REGNUM
1294 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1295 - 3 dummy entries that were used at various times in the past.
1296 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1297 - 6 DSP control registers */
1299 #define FIRST_PSEUDO_REGISTER 188
1301 /* By default, fix the kernel registers ($26 and $27), the global
1302 pointer ($28) and the stack pointer ($29). This can change
1303 depending on the command-line options.
1305 Regarding coprocessor registers: without evidence to the contrary,
1306 it's best to assume that each coprocessor register has a unique
1307 use. This can be overridden, in, e.g., override_options() or
1308 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1309 for a particular target. */
1311 #define FIXED_REGISTERS \
1313 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1314 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1315 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1316 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1317 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1318 /* COP0 registers */ \
1319 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1320 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1321 /* COP2 registers */ \
1322 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1323 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1324 /* COP3 registers */ \
1325 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1326 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1327 /* 6 DSP accumulator registers & 6 control registers */ \
1328 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1332 /* Set up this array for o32 by default.
1334 Note that we don't mark $31 as a call-clobbered register. The idea is
1335 that it's really the call instructions themselves which clobber $31.
1336 We don't care what the called function does with it afterwards.
1338 This approach makes it easier to implement sibcalls. Unlike normal
1339 calls, sibcalls don't clobber $31, so the register reaches the
1340 called function in tact. EPILOGUE_USES says that $31 is useful
1341 to the called function. */
1343 #define CALL_USED_REGISTERS \
1345 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1346 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1347 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1348 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1349 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1350 /* COP0 registers */ \
1351 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1352 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1353 /* COP2 registers */ \
1354 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1355 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1356 /* COP3 registers */ \
1357 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1358 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1359 /* 6 DSP accumulator registers & 6 control registers */ \
1360 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1364 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1366 #define CALL_REALLY_USED_REGISTERS \
1367 { /* General registers. */ \
1368 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1369 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1370 /* Floating-point registers. */ \
1371 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1372 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1374 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1375 /* COP0 registers */ \
1376 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1377 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1378 /* COP2 registers */ \
1379 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1380 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1381 /* COP3 registers */ \
1382 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1383 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1384 /* 6 DSP accumulator registers & 6 control registers */ \
1385 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1388 /* Internal macros to classify a register number as to whether it's a
1389 general purpose register, a floating point register, a
1390 multiply/divide register, or a status register. */
1392 #define GP_REG_FIRST 0
1393 #define GP_REG_LAST 31
1394 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1395 #define GP_DBX_FIRST 0
1397 #define FP_REG_FIRST 32
1398 #define FP_REG_LAST 63
1399 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1400 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1402 #define MD_REG_FIRST 64
1403 #define MD_REG_LAST 65
1404 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1405 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1407 /* The DWARF 2 CFA column which tracks the return address from a
1408 signal handler context. This means that to maintain backwards
1409 compatibility, no hard register can be assigned this column if it
1410 would need to be handled by the DWARF unwinder. */
1411 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1413 #define ST_REG_FIRST 67
1414 #define ST_REG_LAST 74
1415 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1418 /* FIXME: renumber. */
1419 #define COP0_REG_FIRST 80
1420 #define COP0_REG_LAST 111
1421 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1423 #define COP2_REG_FIRST 112
1424 #define COP2_REG_LAST 143
1425 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1427 #define COP3_REG_FIRST 144
1428 #define COP3_REG_LAST 175
1429 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1430 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1431 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1433 #define DSP_ACC_REG_FIRST 176
1434 #define DSP_ACC_REG_LAST 181
1435 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1437 #define AT_REGNUM (GP_REG_FIRST + 1)
1438 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1439 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1441 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1442 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1443 should be used instead. */
1444 #define FPSW_REGNUM ST_REG_FIRST
1446 #define GP_REG_P(REGNO) \
1447 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1448 #define M16_REG_P(REGNO) \
1449 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1450 #define FP_REG_P(REGNO) \
1451 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1452 #define MD_REG_P(REGNO) \
1453 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1454 #define ST_REG_P(REGNO) \
1455 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1456 #define COP0_REG_P(REGNO) \
1457 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1458 #define COP2_REG_P(REGNO) \
1459 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1460 #define COP3_REG_P(REGNO) \
1461 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1462 #define ALL_COP_REG_P(REGNO) \
1463 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1464 /* Test if REGNO is one of the 6 new DSP accumulators. */
1465 #define DSP_ACC_REG_P(REGNO) \
1466 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1467 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1468 #define ACC_REG_P(REGNO) \
1469 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1471 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1473 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1474 to initialize the mips16 gp pseudo register. */
1475 #define CONST_GP_P(X) \
1476 (GET_CODE (X) == CONST \
1477 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1478 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1480 /* Return coprocessor number from register number. */
1482 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1483 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1484 : COP3_REG_P (REGNO) ? '3' : '?')
1487 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1489 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1490 array built in override_options. Because machmodes.h is not yet
1491 included before this file is processed, the MODE bound can't be
1494 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1496 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1497 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1499 /* Value is 1 if it is a good idea to tie two pseudo registers
1500 when one has mode MODE1 and one has mode MODE2.
1501 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1502 for any hard reg, then this must be 0 for correct output. */
1503 #define MODES_TIEABLE_P(MODE1, MODE2) \
1504 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1505 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1506 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1507 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1509 /* Register to use for pushing function arguments. */
1510 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1512 /* These two registers don't really exist: they get eliminated to either
1513 the stack or hard frame pointer. */
1514 #define ARG_POINTER_REGNUM 77
1515 #define FRAME_POINTER_REGNUM 78
1517 /* $30 is not available on the mips16, so we use $17 as the frame
1519 #define HARD_FRAME_POINTER_REGNUM \
1520 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1522 /* Value should be nonzero if functions must have frame pointers.
1523 Zero means the frame pointer need not be set up (and parms
1524 may be accessed via the stack pointer) in functions that seem suitable.
1525 This is computed in `reload', in reload1.c. */
1526 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1528 /* Register in which static-chain is passed to a function. */
1529 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1531 /* Registers used as temporaries in prologue/epilogue code. If we're
1532 generating mips16 code, these registers must come from the core set
1533 of 8. The prologue register mustn't conflict with any incoming
1534 arguments, the static chain pointer, or the frame pointer. The
1535 epilogue temporary mustn't conflict with the return registers, the
1536 frame pointer, the EH stack adjustment, or the EH data registers. */
1538 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1539 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1541 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1542 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1544 /* Define this macro if it is as good or better to call a constant
1545 function address than to call an address kept in a register. */
1546 #define NO_FUNCTION_CSE 1
1548 /* The ABI-defined global pointer. Sometimes we use a different
1549 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1550 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1552 /* We normally use $28 as the global pointer. However, when generating
1553 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1554 register instead. They can then avoid saving and restoring $28
1555 and perhaps avoid using a frame at all.
1557 When a leaf function uses something other than $28, mips_expand_prologue
1558 will modify pic_offset_table_rtx in place. Take the register number
1559 from there after reload. */
1560 #define PIC_OFFSET_TABLE_REGNUM \
1561 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1563 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1565 /* Define the classes of registers for register constraints in the
1566 machine description. Also define ranges of constants.
1568 One of the classes must always be named ALL_REGS and include all hard regs.
1569 If there is more than one class, another class must be named NO_REGS
1570 and contain no registers.
1572 The name GENERAL_REGS must be the name of a class (or an alias for
1573 another name such as ALL_REGS). This is the class of registers
1574 that is allowed by "g" or "r" in a register constraint.
1575 Also, registers outside this class are allocated only when
1576 instructions express preferences for them.
1578 The classes must be numbered in nondecreasing order; that is,
1579 a larger-numbered class must never be contained completely
1580 in a smaller-numbered class.
1582 For any two classes, it is very desirable that there be another
1583 class that represents their union. */
1587 NO_REGS, /* no registers in set */
1588 M16_NA_REGS, /* mips16 regs not used to pass args */
1589 M16_REGS, /* mips16 directly accessible registers */
1590 T_REG, /* mips16 T register ($24) */
1591 M16_T_REGS, /* mips16 registers plus T register */
1592 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1593 V1_REG, /* Register $v1 ($3) used for TLS access. */
1594 LEA_REGS, /* Every GPR except $25 */
1595 GR_REGS, /* integer registers */
1596 FP_REGS, /* floating point registers */
1597 MD0_REG, /* first multiply/divide register */
1598 MD1_REG, /* second multiply/divide register */
1599 MD_REGS, /* multiply/divide registers (hi/lo) */
1600 COP0_REGS, /* generic coprocessor classes */
1603 HI_AND_GR_REGS, /* union classes */
1610 ALL_COP_AND_GR_REGS,
1611 ST_REGS, /* status registers (fp status) */
1612 DSP_ACC_REGS, /* DSP accumulator registers */
1613 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1614 ALL_REGS, /* all registers */
1615 LIM_REG_CLASSES /* max value + 1 */
1618 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1620 #define GENERAL_REGS GR_REGS
1622 /* An initializer containing the names of the register classes as C
1623 string constants. These names are used in writing some of the
1626 #define REG_CLASS_NAMES \
1633 "PIC_FN_ADDR_REG", \
1641 /* coprocessor registers */ \
1648 "COP0_AND_GR_REGS", \
1649 "COP2_AND_GR_REGS", \
1650 "COP3_AND_GR_REGS", \
1652 "ALL_COP_AND_GR_REGS", \
1659 /* An initializer containing the contents of the register classes,
1660 as integers which are bit masks. The Nth integer specifies the
1661 contents of class N. The way the integer MASK is interpreted is
1662 that register R is in the class if `MASK & (1 << R)' is 1.
1664 When the machine has more than 32 registers, an integer does not
1665 suffice. Then the integers are replaced by sub-initializers,
1666 braced groupings containing several integers. Each
1667 sub-initializer must be suitable as an initializer for the type
1668 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1670 #define REG_CLASS_CONTENTS \
1672 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1673 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1674 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1675 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1676 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1677 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1678 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1679 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1680 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1681 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1682 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1683 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1684 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1685 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1686 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1687 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1688 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1689 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1690 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1691 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1692 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1693 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1694 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1695 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1696 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1697 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1698 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1699 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1703 /* A C expression whose value is a register class containing hard
1704 register REGNO. In general there is more that one such class;
1705 choose a class which is "minimal", meaning that no smaller class
1706 also contains the register. */
1708 extern const enum reg_class mips_regno_to_class[];
1710 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1712 /* A macro whose definition is the name of the class to which a
1713 valid base register must belong. A base register is one used in
1714 an address which is the register value plus a displacement. */
1716 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1718 /* A macro whose definition is the name of the class to which a
1719 valid index register must belong. An index register is one used
1720 in an address where its value is either multiplied by a scale
1721 factor or added to another register (as well as added to a
1724 #define INDEX_REG_CLASS NO_REGS
1726 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1727 registers explicitly used in the rtl to be used as spill registers
1728 but prevents the compiler from extending the lifetime of these
1731 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1733 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1734 is the default value (allocate the registers in numeric order). We
1735 define it just so that we can override it for the mips16 target in
1736 ORDER_REGS_FOR_LOCAL_ALLOC. */
1738 #define REG_ALLOC_ORDER \
1739 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1740 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1741 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1742 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1743 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1744 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1745 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1746 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1747 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1748 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1749 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1750 176,177,178,179,180,181,182,183,184,185,186,187 \
1753 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1754 to be rearranged based on a particular function. On the mips16, we
1755 want to allocate $24 (T_REG) before other registers for
1756 instructions for which it is possible. */
1758 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1760 /* True if VALUE is an unsigned 6-bit number. */
1762 #define UIMM6_OPERAND(VALUE) \
1763 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1765 /* True if VALUE is a signed 10-bit number. */
1767 #define IMM10_OPERAND(VALUE) \
1768 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1770 /* True if VALUE is a signed 16-bit number. */
1772 #define SMALL_OPERAND(VALUE) \
1773 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1775 /* True if VALUE is an unsigned 16-bit number. */
1777 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1778 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1780 /* True if VALUE can be loaded into a register using LUI. */
1782 #define LUI_OPERAND(VALUE) \
1783 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1784 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1786 /* Return a value X with the low 16 bits clear, and such that
1787 VALUE - X is a signed 16-bit value. */
1789 #define CONST_HIGH_PART(VALUE) \
1790 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1792 #define CONST_LOW_PART(VALUE) \
1793 ((VALUE) - CONST_HIGH_PART (VALUE))
1795 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1796 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1797 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1799 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1800 mips_preferred_reload_class (X, CLASS)
1802 /* The HI and LO registers can only be reloaded via the general
1803 registers. Condition code registers can only be loaded to the
1804 general registers, and from the floating point registers. */
1806 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1807 mips_secondary_reload_class (CLASS, MODE, X, 1)
1808 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1809 mips_secondary_reload_class (CLASS, MODE, X, 0)
1811 /* Return the maximum number of consecutive registers
1812 needed to represent mode MODE in a register of class CLASS. */
1814 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1816 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1817 mips_cannot_change_mode_class (FROM, TO, CLASS)
1819 /* Stack layout; function entry, exit and calling. */
1821 #define STACK_GROWS_DOWNWARD
1823 /* The offset of the first local variable from the beginning of the frame.
1824 See compute_frame_size for details about the frame layout.
1826 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1827 we assume that we will need 16 bytes of argument space. This is because
1828 the value profiling code may emit calls to cmpdi2 in leaf functions.
1829 Without this hack, the local variables will start at sp+8 and the gp save
1830 area will be at sp+16, and thus they will overlap. compute_frame_size is
1831 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1832 will end up as 24 instead of 8. This won't be needed if profiling code is
1833 inserted before virtual register instantiation. */
1835 #define STARTING_FRAME_OFFSET \
1836 ((flag_profile_values && ! TARGET_64BIT \
1837 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1838 : current_function_outgoing_args_size) \
1839 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1841 #define RETURN_ADDR_RTX mips_return_addr
1843 /* Since the mips16 ISA mode is encoded in the least-significant bit
1844 of the address, mask it off return addresses for purposes of
1845 finding exception handling regions. */
1847 #define MASK_RETURN_ADDR GEN_INT (-2)
1850 /* Similarly, don't use the least-significant bit to tell pointers to
1851 code from vtable index. */
1853 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1855 /* The eliminations to $17 are only used for mips16 code. See the
1856 definition of HARD_FRAME_POINTER_REGNUM. */
1858 #define ELIMINABLE_REGS \
1859 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1860 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1861 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1862 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1863 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1864 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1866 /* We can always eliminate to the hard frame pointer. We can eliminate
1867 to the stack pointer unless a frame pointer is needed.
1869 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1870 reload may be unable to compute the address of a local variable,
1871 since there is no way to add a large constant to the stack pointer
1872 without using a temporary register. */
1873 #define CAN_ELIMINATE(FROM, TO) \
1874 ((TO) == HARD_FRAME_POINTER_REGNUM \
1875 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1876 && (!TARGET_MIPS16 \
1877 || compute_frame_size (get_frame_size ()) < 32768)))
1879 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1880 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1882 /* Allocate stack space for arguments at the beginning of each function. */
1883 #define ACCUMULATE_OUTGOING_ARGS 1
1885 /* The argument pointer always points to the first argument. */
1886 #define FIRST_PARM_OFFSET(FNDECL) 0
1888 /* o32 and o64 reserve stack space for all argument registers. */
1889 #define REG_PARM_STACK_SPACE(FNDECL) \
1891 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1894 /* Define this if it is the responsibility of the caller to
1895 allocate the area reserved for arguments passed in registers.
1896 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1897 of this macro is to determine whether the space is included in
1898 `current_function_outgoing_args_size'. */
1899 #define OUTGOING_REG_PARM_STACK_SPACE 1
1901 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1903 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1905 /* Symbolic macros for the registers used to return integer and floating
1908 #define GP_RETURN (GP_REG_FIRST + 2)
1909 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1911 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1913 /* Symbolic macros for the first/last argument registers. */
1915 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1916 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1917 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1918 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1920 #define LIBCALL_VALUE(MODE) \
1921 mips_function_value (NULL_TREE, NULL, (MODE))
1923 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1924 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1926 /* 1 if N is a possible register number for a function value.
1927 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1928 Currently, R2 and F0 are only implemented here (C has no complex type) */
1930 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1931 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1932 && (N) == FP_RETURN + 2))
1934 /* 1 if N is a possible register number for function argument passing.
1935 We have no FP argument registers when soft-float. When FP registers
1936 are 32 bits, we can't directly reference the odd numbered ones. */
1938 #define FUNCTION_ARG_REGNO_P(N) \
1939 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1940 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1943 /* This structure has to cope with two different argument allocation
1944 schemes. Most MIPS ABIs view the arguments as a structure, of which
1945 the first N words go in registers and the rest go on the stack. If I
1946 < N, the Ith word might go in Ith integer argument register or in a
1947 floating-point register. For these ABIs, we only need to remember
1948 the offset of the current argument into the structure.
1950 The EABI instead allocates the integer and floating-point arguments
1951 separately. The first N words of FP arguments go in FP registers,
1952 the rest go on the stack. Likewise, the first N words of the other
1953 arguments go in integer registers, and the rest go on the stack. We
1954 need to maintain three counts: the number of integer registers used,
1955 the number of floating-point registers used, and the number of words
1956 passed on the stack.
1958 We could keep separate information for the two ABIs (a word count for
1959 the standard ABIs, and three separate counts for the EABI). But it
1960 seems simpler to view the standard ABIs as forms of EABI that do not
1961 allocate floating-point registers.
1963 So for the standard ABIs, the first N words are allocated to integer
1964 registers, and function_arg decides on an argument-by-argument basis
1965 whether that argument should really go in an integer register, or in
1966 a floating-point one. */
1968 typedef struct mips_args {
1969 /* Always true for varargs functions. Otherwise true if at least
1970 one argument has been passed in an integer register. */
1973 /* The number of arguments seen so far. */
1974 unsigned int arg_number;
1976 /* The number of integer registers used so far. For all ABIs except
1977 EABI, this is the number of words that have been added to the
1978 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
1979 unsigned int num_gprs;
1981 /* For EABI, the number of floating-point registers used so far. */
1982 unsigned int num_fprs;
1984 /* The number of words passed on the stack. */
1985 unsigned int stack_words;
1987 /* On the mips16, we need to keep track of which floating point
1988 arguments were passed in general registers, but would have been
1989 passed in the FP regs if this were a 32-bit function, so that we
1990 can move them to the FP regs if we wind up calling a 32-bit
1991 function. We record this information in fp_code, encoded in base
1992 four. A zero digit means no floating point argument, a one digit
1993 means an SFmode argument, and a two digit means a DFmode argument,
1994 and a three digit is not used. The low order digit is the first
1995 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
1996 an SFmode argument. ??? A more sophisticated approach will be
1997 needed if MIPS_ABI != ABI_32. */
2000 /* True if the function has a prototype. */
2004 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2005 for a call to a function whose data type is FNTYPE.
2006 For a library call, FNTYPE is 0. */
2008 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2009 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2011 /* Update the data in CUM to advance over an argument
2012 of mode MODE and data type TYPE.
2013 (TYPE is null for libcalls where that information may not be available.) */
2015 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2016 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2018 /* Determine where to put an argument to a function.
2019 Value is zero to push the argument on the stack,
2020 or a hard register in which to store the argument.
2022 MODE is the argument's machine mode.
2023 TYPE is the data type of the argument (as a tree).
2024 This is null for libcalls where that information may
2026 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2027 the preceding args and about the function being called.
2028 NAMED is nonzero if this argument is a named parameter
2029 (otherwise it is an extra parameter matching an ellipsis). */
2031 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2032 function_arg( &CUM, MODE, TYPE, NAMED)
2034 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2036 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2037 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2039 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2040 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2042 /* True if using EABI and varargs can be passed in floating-point
2043 registers. Under these conditions, we need a more complex form
2044 of va_list, which tracks GPR, FPR and stack arguments separately. */
2045 #define EABI_FLOAT_VARARGS_P \
2046 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2049 /* Say that the epilogue uses the return address register. Note that
2050 in the case of sibcalls, the values "used by the epilogue" are
2051 considered live at the start of the called function. */
2052 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2054 /* Treat LOC as a byte offset from the stack pointer and round it up
2055 to the next fully-aligned offset. */
2056 #define MIPS_STACK_ALIGN(LOC) \
2057 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2060 /* Implement `va_start' for varargs and stdarg. */
2061 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2062 mips_va_start (valist, nextarg)
2064 /* Output assembler code to FILE to increment profiler label # LABELNO
2065 for profiling a function entry. */
2067 #define FUNCTION_PROFILER(FILE, LABELNO) \
2069 if (TARGET_MIPS16) \
2070 sorry ("mips16 function profiling"); \
2071 fprintf (FILE, "\t.set\tnoat\n"); \
2072 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2073 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2074 if (!TARGET_NEWABI) \
2077 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2078 TARGET_64BIT ? "dsubu" : "subu", \
2079 reg_names[STACK_POINTER_REGNUM], \
2080 reg_names[STACK_POINTER_REGNUM], \
2081 Pmode == DImode ? 16 : 8); \
2083 fprintf (FILE, "\tjal\t_mcount\n"); \
2084 fprintf (FILE, "\t.set\tat\n"); \
2087 /* No mips port has ever used the profiler counter word, so don't emit it
2088 or the label for it. */
2090 #define NO_PROFILE_COUNTERS 1
2092 /* Define this macro if the code for function profiling should come
2093 before the function prologue. Normally, the profiling code comes
2096 /* #define PROFILE_BEFORE_PROLOGUE */
2098 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2099 the stack pointer does not matter. The value is tested only in
2100 functions that have frame pointers.
2101 No definition is equivalent to always zero. */
2103 #define EXIT_IGNORE_STACK 1
2106 /* A C statement to output, on the stream FILE, assembler code for a
2107 block of data that contains the constant parts of a trampoline.
2108 This code should not include a label--the label is taken care of
2111 #define TRAMPOLINE_TEMPLATE(STREAM) \
2113 if (ptr_mode == DImode) \
2114 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2116 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2117 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2118 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2119 if (ptr_mode == DImode) \
2121 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2122 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2123 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2127 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2128 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2129 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2131 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2132 if (ptr_mode == DImode) \
2134 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2135 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2136 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2140 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2141 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2142 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2146 /* A C expression for the size in bytes of the trampoline, as an
2149 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2151 /* Alignment required for trampolines, in bits. */
2153 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2155 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2156 program and data caches. */
2158 #ifndef CACHE_FLUSH_FUNC
2159 #define CACHE_FLUSH_FUNC "_flush_cache"
2162 /* A C statement to initialize the variable parts of a trampoline.
2163 ADDR is an RTX for the address of the trampoline; FNADDR is an
2164 RTX for the address of the nested function; STATIC_CHAIN is an
2165 RTX for the static chain value that should be passed to the
2166 function when it is called. */
2168 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2170 rtx func_addr, chain_addr, end_addr; \
2172 func_addr = plus_constant (ADDR, 32); \
2173 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2174 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2175 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2176 end_addr = gen_reg_rtx (Pmode); \
2177 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2178 GEN_INT (TRAMPOLINE_SIZE))); \
2179 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2182 /* Addressing modes, and classification of registers for them. */
2184 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2185 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2186 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2188 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2189 and check its validity for a certain class.
2190 We have two alternate definitions for each of them.
2191 The usual definition accepts all pseudo regs; the other rejects them all.
2192 The symbol REG_OK_STRICT causes the latter definition to be used.
2194 Most source files want to accept pseudo regs in the hope that
2195 they will get allocated to the class that the insn wants them to be in.
2196 Some source files that are used after register allocation
2197 need to be strict. */
2199 #ifndef REG_OK_STRICT
2200 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2201 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2203 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2204 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2207 #define REG_OK_FOR_INDEX_P(X) 0
2210 /* Maximum number of registers that can appear in a valid memory address. */
2212 #define MAX_REGS_PER_ADDRESS 1
2214 #ifdef REG_OK_STRICT
2215 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2217 if (mips_legitimate_address_p (MODE, X, 1)) \
2221 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2223 if (mips_legitimate_address_p (MODE, X, 0)) \
2228 /* Check for constness inline but use mips_legitimate_address_p
2229 to check whether a constant really is an address. */
2231 #define CONSTANT_ADDRESS_P(X) \
2232 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2234 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2236 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2238 if (mips_legitimize_address (&(X), MODE)) \
2243 /* A C statement or compound statement with a conditional `goto
2244 LABEL;' executed if memory address X (an RTX) can have different
2245 meanings depending on the machine mode of the memory reference it
2248 Autoincrement and autodecrement addresses typically have
2249 mode-dependent effects because the amount of the increment or
2250 decrement is the size of the operand being addressed. Some
2251 machines have other mode-dependent addresses. Many RISC machines
2252 have no mode-dependent addresses.
2254 You may assume that ADDR is a valid address for the machine. */
2256 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2258 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2259 'the start of the function that this code is output in'. */
2261 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2262 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2263 asm_fprintf ((FILE), "%U%s", \
2264 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2266 asm_fprintf ((FILE), "%U%s", (NAME))
2268 /* Flag to mark a function decl symbol that requires a long call. */
2269 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2270 #define SYMBOL_REF_LONG_CALL_P(X) \
2271 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2273 /* Specify the machine mode that this machine uses
2274 for the index in the tablejump instruction.
2275 ??? Using HImode in mips16 mode can cause overflow. */
2276 #define CASE_VECTOR_MODE \
2277 (TARGET_MIPS16 ? HImode : ptr_mode)
2279 /* Define as C expression which evaluates to nonzero if the tablejump
2280 instruction expects the table to contain offsets from the address of the
2282 Do not define this if the table should contain absolute addresses. */
2283 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2285 /* Define this as 1 if `char' should by default be signed; else as 0. */
2286 #ifndef DEFAULT_SIGNED_CHAR
2287 #define DEFAULT_SIGNED_CHAR 1
2290 /* Max number of bytes we can move from memory to memory
2291 in one reasonably fast instruction. */
2292 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2293 #define MAX_MOVE_MAX 8
2295 /* Define this macro as a C expression which is nonzero if
2296 accessing less than a word of memory (i.e. a `char' or a
2297 `short') is no faster than accessing a word of memory, i.e., if
2298 such access require more than one instruction or if there is no
2299 difference in cost between byte and (aligned) word loads.
2301 On RISC machines, it tends to generate better code to define
2302 this as 1, since it avoids making a QI or HI mode register.
2304 But, generating word accesses for -mips16 is generally bad as shifts
2305 (often extended) would be needed for byte accesses. */
2306 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2308 /* Define this to be nonzero if shift instructions ignore all but the low-order
2310 #define SHIFT_COUNT_TRUNCATED 1
2312 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2313 is done just by pretending it is already truncated. */
2314 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2315 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2318 /* Specify the machine mode that pointers have.
2319 After generation of rtl, the compiler makes no further distinction
2320 between pointers and any other objects of this machine mode. */
2323 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2326 /* Give call MEMs SImode since it is the "most permissive" mode
2327 for both 32-bit and 64-bit targets. */
2329 #define FUNCTION_MODE SImode
2332 /* The cost of loading values from the constant pool. It should be
2333 larger than the cost of any constant we want to synthesize in-line. */
2335 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2337 /* A C expression for the cost of moving data from a register in
2338 class FROM to one in class TO. The classes are expressed using
2339 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2340 the default; other values are interpreted relative to that.
2342 It is not required that the cost always equal 2 when FROM is the
2343 same as TO; on some machines it is expensive to move between
2344 registers if they are not general registers.
2346 If reload sees an insn consisting of a single `set' between two
2347 hard registers, and if `REGISTER_MOVE_COST' applied to their
2348 classes returns a value of 2, reload does not check to ensure
2349 that the constraints of the insn are met. Setting a cost of
2350 other than 2 will allow reload to verify that the constraints are
2351 met. You should do this if the `movM' pattern's constraints do
2352 not allow such copying. */
2354 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2355 mips_register_move_cost (MODE, FROM, TO)
2357 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2358 (mips_cost->memory_latency \
2359 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2361 /* Define if copies to/from condition code registers should be avoided.
2363 This is needed for the MIPS because reload_outcc is not complete;
2364 it needs to handle cases where the source is a general or another
2365 condition code register. */
2366 #define AVOID_CCMODE_COPIES
2368 /* A C expression for the cost of a branch instruction. A value of
2369 1 is the default; other values are interpreted relative to that. */
2371 #define BRANCH_COST mips_branch_cost
2372 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2374 /* If defined, modifies the length assigned to instruction INSN as a
2375 function of the context in which it is used. LENGTH is an lvalue
2376 that contains the initially computed length of the insn and should
2377 be updated with the correct length of the insn. */
2378 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2379 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2381 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2382 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2384 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2385 "%*" OPCODE "%?\t" OPERANDS "%/"
2387 /* Return the asm template for a call. INSN is the instruction's mnemonic
2388 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2391 When generating GOT code without explicit relocation operators,
2392 all calls should use assembly macros. Otherwise, all indirect
2393 calls should use "jr" or "jalr"; we will arrange to restore $gp
2394 afterwards if necessary. Finally, we can only generate direct
2395 calls for -mabicalls by temporarily switching to non-PIC mode. */
2396 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2397 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2398 ? "%*" INSN "\t%" #OPNO "%/" \
2399 : REG_P (OPERANDS[OPNO]) \
2400 ? "%*" INSN "r\t%" #OPNO "%/" \
2402 ? (".option\tpic0\n\t" \
2403 "%*" INSN "\t%" #OPNO "%/\n\t" \
2405 : "%*" INSN "\t%" #OPNO "%/")
2407 /* Control the assembler format that we output. */
2409 /* Output to assembler file text saying following lines
2410 may contain character constants, extra white space, comments, etc. */
2413 #define ASM_APP_ON " #APP\n"
2416 /* Output to assembler file text saying following lines
2417 no longer contain unusual constructs. */
2420 #define ASM_APP_OFF " #NO_APP\n"
2423 #define REGISTER_NAMES \
2424 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2425 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2426 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2427 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2428 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2429 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2430 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2431 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2432 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2433 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2434 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2435 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2436 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2437 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2438 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2439 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2440 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2441 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2442 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2443 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2444 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2445 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2446 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2447 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2449 /* List the "software" names for each register. Also list the numerical
2450 names for $fp and $sp. */
2452 #define ADDITIONAL_REGISTER_NAMES \
2454 { "$29", 29 + GP_REG_FIRST }, \
2455 { "$30", 30 + GP_REG_FIRST }, \
2456 { "at", 1 + GP_REG_FIRST }, \
2457 { "v0", 2 + GP_REG_FIRST }, \
2458 { "v1", 3 + GP_REG_FIRST }, \
2459 { "a0", 4 + GP_REG_FIRST }, \
2460 { "a1", 5 + GP_REG_FIRST }, \
2461 { "a2", 6 + GP_REG_FIRST }, \
2462 { "a3", 7 + GP_REG_FIRST }, \
2463 { "t0", 8 + GP_REG_FIRST }, \
2464 { "t1", 9 + GP_REG_FIRST }, \
2465 { "t2", 10 + GP_REG_FIRST }, \
2466 { "t3", 11 + GP_REG_FIRST }, \
2467 { "t4", 12 + GP_REG_FIRST }, \
2468 { "t5", 13 + GP_REG_FIRST }, \
2469 { "t6", 14 + GP_REG_FIRST }, \
2470 { "t7", 15 + GP_REG_FIRST }, \
2471 { "s0", 16 + GP_REG_FIRST }, \
2472 { "s1", 17 + GP_REG_FIRST }, \
2473 { "s2", 18 + GP_REG_FIRST }, \
2474 { "s3", 19 + GP_REG_FIRST }, \
2475 { "s4", 20 + GP_REG_FIRST }, \
2476 { "s5", 21 + GP_REG_FIRST }, \
2477 { "s6", 22 + GP_REG_FIRST }, \
2478 { "s7", 23 + GP_REG_FIRST }, \
2479 { "t8", 24 + GP_REG_FIRST }, \
2480 { "t9", 25 + GP_REG_FIRST }, \
2481 { "k0", 26 + GP_REG_FIRST }, \
2482 { "k1", 27 + GP_REG_FIRST }, \
2483 { "gp", 28 + GP_REG_FIRST }, \
2484 { "sp", 29 + GP_REG_FIRST }, \
2485 { "fp", 30 + GP_REG_FIRST }, \
2486 { "ra", 31 + GP_REG_FIRST }, \
2487 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2490 /* This is meant to be redefined in the host dependent files. It is a
2491 set of alternative names and regnums for mips coprocessors. */
2493 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2495 /* A C compound statement to output to stdio stream STREAM the
2496 assembler syntax for an instruction operand X. X is an RTL
2499 CODE is a value that can be used to specify one of several ways
2500 of printing the operand. It is used when identical operands
2501 must be printed differently depending on the context. CODE
2502 comes from the `%' specification that was used to request
2503 printing of the operand. If the specification was just `%DIGIT'
2504 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2505 is the ASCII code for LTR.
2507 If X is a register, this macro should print the register's name.
2508 The names can be found in an array `reg_names' whose type is
2509 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2511 When the machine description has a specification `%PUNCT' (a `%'
2512 followed by a punctuation character), this macro is called with
2513 a null pointer for X and the punctuation character for CODE.
2515 See mips.c for the MIPS specific codes. */
2517 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2519 /* A C expression which evaluates to true if CODE is a valid
2520 punctuation character for use in the `PRINT_OPERAND' macro. If
2521 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2522 punctuation characters (except for the standard one, `%') are
2523 used in this way. */
2525 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2527 /* A C compound statement to output to stdio stream STREAM the
2528 assembler syntax for an instruction operand that is a memory
2529 reference whose address is ADDR. ADDR is an RTL expression. */
2531 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2534 /* A C statement, to be executed after all slot-filler instructions
2535 have been output. If necessary, call `dbr_sequence_length' to
2536 determine the number of slots filled in a sequence (zero if not
2537 currently outputting a sequence), to decide how many no-ops to
2538 output, or whatever.
2540 Don't define this macro if it has nothing to do, but it is
2541 helpful in reading assembly output if the extent of the delay
2542 sequence is made explicit (e.g. with white space).
2544 Note that output routines for instructions with delay slots must
2545 be prepared to deal with not being output as part of a sequence
2546 (i.e. when the scheduling pass is not run, or when no slot
2547 fillers could be found.) The variable `final_sequence' is null
2548 when not processing a sequence, otherwise it contains the
2549 `sequence' rtx being output. */
2551 #define DBR_OUTPUT_SEQEND(STREAM) \
2554 if (set_nomacro > 0 && --set_nomacro == 0) \
2555 fputs ("\t.set\tmacro\n", STREAM); \
2557 if (set_noreorder > 0 && --set_noreorder == 0) \
2558 fputs ("\t.set\treorder\n", STREAM); \
2560 fputs ("\n", STREAM); \
2565 /* How to tell the debugger about changes of source files. */
2566 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2567 mips_output_filename (STREAM, NAME)
2569 /* mips-tfile does not understand .stabd directives. */
2570 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2571 dbxout_begin_stabn_sline (LINE); \
2572 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2575 /* Use .loc directives for SDB line numbers. */
2576 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2577 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2579 /* The MIPS implementation uses some labels for its own purpose. The
2580 following lists what labels are created, and are all formed by the
2581 pattern $L[a-z].*. The machine independent portion of GCC creates
2582 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2584 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2585 $Lb[0-9]+ Begin blocks for MIPS debug support
2586 $Lc[0-9]+ Label for use in s<xx> operation.
2587 $Le[0-9]+ End blocks for MIPS debug support */
2589 #undef ASM_DECLARE_OBJECT_NAME
2590 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2591 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2593 /* Globalizing directive for a label. */
2594 #define GLOBAL_ASM_OP "\t.globl\t"
2596 /* This says how to define a global common symbol. */
2598 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2600 /* This says how to define a local common symbol (i.e., not visible to
2603 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2604 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2605 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2608 /* This says how to output an external. It would be possible not to
2609 output anything and let undefined symbol become external. However
2610 the assembler uses length information on externals to allocate in
2611 data/sdata bss/sbss, thereby saving exec time. */
2613 #undef ASM_OUTPUT_EXTERNAL
2614 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2615 mips_output_external(STREAM,DECL,NAME)
2617 /* This is how to declare a function name. The actual work of
2618 emitting the label is moved to function_prologue, so that we can
2619 get the line number correctly emitted before the .ent directive,
2620 and after any .file directives. Define as empty so that the function
2621 is not declared before the .ent directive elsewhere. */
2623 #undef ASM_DECLARE_FUNCTION_NAME
2624 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2626 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2627 #define FUNCTION_NAME_ALREADY_DECLARED 0
2630 /* This is how to store into the string LABEL
2631 the symbol_ref name of an internal numbered label where
2632 PREFIX is the class of label and NUM is the number within the class.
2633 This is suitable for output with `assemble_name'. */
2635 #undef ASM_GENERATE_INTERNAL_LABEL
2636 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2637 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2639 /* This is how to output an element of a case-vector that is absolute. */
2641 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2642 fprintf (STREAM, "\t%s\t%sL%d\n", \
2643 ptr_mode == DImode ? ".dword" : ".word", \
2644 LOCAL_LABEL_PREFIX, \
2647 /* This is how to output an element of a case-vector. We can make the
2648 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2651 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2653 if (TARGET_MIPS16) \
2654 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2655 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2656 else if (TARGET_GPWORD) \
2657 fprintf (STREAM, "\t%s\t%sL%d\n", \
2658 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2659 LOCAL_LABEL_PREFIX, VALUE); \
2660 else if (TARGET_RTP_PIC) \
2662 /* Make the entry relative to the start of the function. */ \
2663 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2664 fprintf (STREAM, "\t%s\t%sL%d-", \
2665 Pmode == DImode ? ".dword" : ".word", \
2666 LOCAL_LABEL_PREFIX, VALUE); \
2667 assemble_name (STREAM, XSTR (fnsym, 0)); \
2668 fprintf (STREAM, "\n"); \
2671 fprintf (STREAM, "\t%s\t%sL%d\n", \
2672 ptr_mode == DImode ? ".dword" : ".word", \
2673 LOCAL_LABEL_PREFIX, VALUE); \
2676 /* When generating MIPS16 code, we want the jump table to be in the text
2677 section so that we can load its address using a PC-relative addition. */
2678 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
2680 /* This is how to output an assembler line
2681 that says to advance the location counter
2682 to a multiple of 2**LOG bytes. */
2684 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2685 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2687 /* This is how to output an assembler line to advance the location
2688 counter by SIZE bytes. */
2690 #undef ASM_OUTPUT_SKIP
2691 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2692 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2694 /* This is how to output a string. */
2695 #undef ASM_OUTPUT_ASCII
2696 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2697 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2699 /* Output #ident as a in the read-only data section. */
2700 #undef ASM_OUTPUT_IDENT
2701 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2703 const char *p = STRING; \
2704 int size = strlen (p) + 1; \
2705 switch_to_section (readonly_data_section); \
2706 assemble_string (p, size); \
2709 /* Default to -G 8 */
2710 #ifndef MIPS_DEFAULT_GVALUE
2711 #define MIPS_DEFAULT_GVALUE 8
2714 /* Define the strings to put out for each section in the object file. */
2715 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2716 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2718 #undef READONLY_DATA_SECTION_ASM_OP
2719 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2721 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2724 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2725 TARGET_64BIT ? "dsubu" : "subu", \
2726 reg_names[STACK_POINTER_REGNUM], \
2727 reg_names[STACK_POINTER_REGNUM], \
2728 TARGET_64BIT ? "sd" : "sw", \
2730 reg_names[STACK_POINTER_REGNUM]); \
2734 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2737 if (! set_noreorder) \
2738 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2740 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2741 TARGET_64BIT ? "ld" : "lw", \
2743 reg_names[STACK_POINTER_REGNUM], \
2744 TARGET_64BIT ? "daddu" : "addu", \
2745 reg_names[STACK_POINTER_REGNUM], \
2746 reg_names[STACK_POINTER_REGNUM]); \
2748 if (! set_noreorder) \
2749 fprintf (STREAM, "\t.set\treorder\n"); \
2753 /* How to start an assembler comment.
2754 The leading space is important (the mips native assembler requires it). */
2755 #ifndef ASM_COMMENT_START
2756 #define ASM_COMMENT_START " #"
2759 /* Default definitions for size_t and ptrdiff_t. We must override the
2760 definitions from ../svr4.h on mips-*-linux-gnu. */
2763 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2766 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2769 /* Since the bits of the _init and _fini function is spread across
2770 many object files, each potentially with its own GP, we must assume
2771 we need to load our GP. We don't preserve $gp or $ra, since each
2772 init/fini chunk is supposed to initialize $gp, and crti/crtn
2773 already take care of preserving $ra and, when appropriate, $gp. */
2774 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2775 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2776 asm (SECTION_OP "\n\
2782 jal " USER_LABEL_PREFIX #FUNC "\n\
2783 " TEXT_SECTION_ASM_OP);
2784 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2785 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2786 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2787 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2788 asm (SECTION_OP "\n\
2793 .cpsetup $31, $2, 1b\n\
2794 jal " USER_LABEL_PREFIX #FUNC "\n\
2795 " TEXT_SECTION_ASM_OP);
2800 #define HAVE_AS_TLS 0