1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
27 #include "config/vxworks-dummy.h"
29 /* MIPS external variables defined in mips.c. */
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
50 PROCESSOR_LOONGSON_2E,
51 PROCESSOR_LOONGSON_2F,
78 /* Costs of various operations on the different architectures. */
80 struct mips_rtx_cost_data
82 unsigned short fp_add;
83 unsigned short fp_mult_sf;
84 unsigned short fp_mult_df;
85 unsigned short fp_div_sf;
86 unsigned short fp_div_df;
87 unsigned short int_mult_si;
88 unsigned short int_mult_di;
89 unsigned short int_div_si;
90 unsigned short int_div_di;
91 unsigned short branch_cost;
92 unsigned short memory_latency;
95 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
96 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
97 to work on a 64-bit machine. */
105 /* Masks that affect tuning.
107 PTF_AVOID_BRANCHLIKELY
108 Set if it is usually not profitable to use branch-likely instructions
109 for this target, typically because the branches are always predicted
110 taken and so incur a large overhead when not taken. */
111 #define PTF_AVOID_BRANCHLIKELY 0x1
113 /* Information about one recognized processor. Defined here for the
114 benefit of TARGET_CPU_CPP_BUILTINS. */
115 struct mips_cpu_info {
116 /* The 'canonical' name of the processor as far as GCC is concerned.
117 It's typically a manufacturer's prefix followed by a numerical
118 designation. It should be lowercase. */
121 /* The internal processor number that most closely matches this
122 entry. Several processors can have the same value, if there's no
123 difference between them from GCC's point of view. */
124 enum processor_type cpu;
126 /* The ISA level that the processor implements. */
129 /* A mask of PTF_* values. */
130 unsigned int tune_flags;
133 /* Enumerates the setting of the -mcode-readable option. */
134 enum mips_code_readable_setting {
140 /* Macros to silence warnings about numbers being signed in traditional
141 C and unsigned in ISO C when compiled on 32-bit hosts. */
143 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
144 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
145 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
148 /* Run-time compilation parameters selecting different hardware subsets. */
150 /* True if we are generating position-independent VxWorks RTP code. */
151 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
153 /* True if the output file is marked as ".abicalls; .option pic0"
155 #define TARGET_ABICALLS_PIC0 \
156 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
158 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
159 #define TARGET_ABICALLS_PIC2 \
160 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
162 /* True if the call patterns should be split into a jalr followed by
163 an instruction to restore $gp. It is only safe to split the load
164 from the call when every use of $gp is explicit. */
166 #define TARGET_SPLIT_CALLS \
167 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
169 /* True if we're generating a form of -mabicalls in which we can use
170 operators like %hi and %lo to refer to locally-binding symbols.
171 We can only do this for -mno-shared, and only then if we can use
172 relocation operations instead of assembly macros. It isn't really
173 worth using absolute sequences for 64-bit symbols because GOT
174 accesses are so much shorter. */
176 #define TARGET_ABSOLUTE_ABICALLS \
179 && TARGET_EXPLICIT_RELOCS \
180 && !ABI_HAS_64BIT_SYMBOLS)
182 /* True if we can optimize sibling calls. For simplicity, we only
183 handle cases in which call_insn_operand will reject invalid
184 sibcall addresses. There are two cases in which this isn't true:
186 - TARGET_MIPS16. call_insn_operand accepts constant addresses
187 but there is no direct jump instruction. It isn't worth
188 using sibling calls in this case anyway; they would usually
189 be longer than normal calls.
191 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
192 accepts global constants, but all sibcalls must be indirect. */
193 #define TARGET_SIBCALLS \
194 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
196 /* True if we need to use a global offset table to access some symbols. */
197 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
199 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
200 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
202 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
203 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
205 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
206 This is true for both the PIC and non-PIC VxWorks RTP modes. */
207 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
209 /* True if .gpword or .gpdword should be used for switch tables.
211 Although GAS does understand .gpdword, the SGI linker mishandles
212 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
213 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
214 #define TARGET_GPWORD \
216 && !TARGET_ABSOLUTE_ABICALLS \
217 && !(mips_abi == ABI_64 && TARGET_IRIX))
219 /* Generate mips16 code */
220 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
221 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
222 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
223 /* Generate mips16e register save/restore sequences. */
224 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
226 /* True if we're generating a form of MIPS16 code in which general
227 text loads are allowed. */
228 #define TARGET_MIPS16_TEXT_LOADS \
229 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
231 /* True if we're generating a form of MIPS16 code in which PC-relative
232 loads are allowed. */
233 #define TARGET_MIPS16_PCREL_LOADS \
234 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
236 /* Generic ISA defines. */
237 #define ISA_MIPS1 (mips_isa == 1)
238 #define ISA_MIPS2 (mips_isa == 2)
239 #define ISA_MIPS3 (mips_isa == 3)
240 #define ISA_MIPS4 (mips_isa == 4)
241 #define ISA_MIPS32 (mips_isa == 32)
242 #define ISA_MIPS32R2 (mips_isa == 33)
243 #define ISA_MIPS64 (mips_isa == 64)
244 #define ISA_MIPS64R2 (mips_isa == 65)
246 /* Architecture target defines. */
247 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
248 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
249 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
250 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
251 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
252 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
253 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
254 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
255 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
256 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
257 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
258 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
259 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
260 || mips_arch == PROCESSOR_SB1A)
261 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
263 /* Scheduling target defines. */
264 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
265 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
266 || mips_tune == PROCESSOR_24KF2_1 \
267 || mips_tune == PROCESSOR_24KF1_1)
268 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
269 || mips_tune == PROCESSOR_74KF2_1 \
270 || mips_tune == PROCESSOR_74KF1_1 \
271 || mips_tune == PROCESSOR_74KF3_2)
272 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
273 || mips_tune == PROCESSOR_LOONGSON_2F)
274 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
275 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
276 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
277 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
278 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
279 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
280 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
281 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
282 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
283 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
284 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
285 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
286 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
287 || mips_tune == PROCESSOR_SB1A)
289 /* Whether vector modes and intrinsics for ST Microelectronics
290 Loongson-2E/2F processors should be enabled. In o32 pairs of
291 floating-point registers provide 64-bit values. */
292 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
293 && TARGET_LOONGSON_2EF)
295 /* True if the pre-reload scheduler should try to create chains of
296 multiply-add or multiply-subtract instructions. For example,
304 t1 will have a higher priority than t2 and t3 will have a higher
305 priority than t4. However, before reload, there is no dependence
306 between t1 and t3, and they can often have similar priorities.
307 The scheduler will then tend to prefer:
314 which stops us from making full use of macc/madd-style instructions.
315 This sort of situation occurs frequently in Fourier transforms and
318 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
319 queue so that chained multiply-add and multiply-subtract instructions
320 appear ahead of any other instruction that is likely to clobber lo.
321 In the example above, if t2 and t3 become ready at the same time,
322 the code ensures that t2 is scheduled first.
324 Multiply-accumulate instructions are a bigger win for some targets
325 than others, so this macro is defined on an opt-in basis. */
326 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
331 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
332 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
334 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
335 directly accessible, while the command-line options select
336 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
338 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
339 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
341 /* IRIX specific stuff. */
342 #define TARGET_IRIX 0
343 #define TARGET_IRIX6 0
345 /* Define preprocessor macros for the -march and -mtune options.
346 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
347 processor. If INFO's canonical name is "foo", define PREFIX to
348 be "foo", and define an additional macro PREFIX_FOO. */
349 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
354 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
355 for (p = macro; *p != 0; p++) \
358 builtin_define (macro); \
359 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
364 /* Target CPU builtins. */
365 #define TARGET_CPU_CPP_BUILTINS() \
368 /* Everyone but IRIX defines this to mips. */ \
370 builtin_assert ("machine=mips"); \
372 builtin_assert ("cpu=mips"); \
373 builtin_define ("__mips__"); \
374 builtin_define ("_mips"); \
376 /* We do this here because __mips is defined below and so we \
377 can't use builtin_define_std. We don't ever want to define \
378 "mips" for VxWorks because some of the VxWorks headers \
379 construct include filenames from a root directory macro, \
380 an architecture macro and a filename, where the architecture \
381 macro expands to 'mips'. If we define 'mips' to 1, the \
382 architecture macro expands to 1 as well. */ \
383 if (!flag_iso && !TARGET_VXWORKS) \
384 builtin_define ("mips"); \
387 builtin_define ("__mips64"); \
391 /* Treat _R3000 and _R4000 like register-size \
392 defines, which is how they've historically \
396 builtin_define_std ("R4000"); \
397 builtin_define ("_R4000"); \
401 builtin_define_std ("R3000"); \
402 builtin_define ("_R3000"); \
405 if (TARGET_FLOAT64) \
406 builtin_define ("__mips_fpr=64"); \
408 builtin_define ("__mips_fpr=32"); \
410 if (mips_base_mips16) \
411 builtin_define ("__mips16"); \
414 builtin_define ("__mips3d"); \
416 if (TARGET_SMARTMIPS) \
417 builtin_define ("__mips_smartmips"); \
421 builtin_define ("__mips_dsp"); \
424 builtin_define ("__mips_dspr2"); \
425 builtin_define ("__mips_dsp_rev=2"); \
428 builtin_define ("__mips_dsp_rev=1"); \
431 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
432 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
436 builtin_define ("__mips=1"); \
437 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
439 else if (ISA_MIPS2) \
441 builtin_define ("__mips=2"); \
442 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
444 else if (ISA_MIPS3) \
446 builtin_define ("__mips=3"); \
447 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
449 else if (ISA_MIPS4) \
451 builtin_define ("__mips=4"); \
452 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
454 else if (ISA_MIPS32) \
456 builtin_define ("__mips=32"); \
457 builtin_define ("__mips_isa_rev=1"); \
458 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
460 else if (ISA_MIPS32R2) \
462 builtin_define ("__mips=32"); \
463 builtin_define ("__mips_isa_rev=2"); \
464 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
466 else if (ISA_MIPS64) \
468 builtin_define ("__mips=64"); \
469 builtin_define ("__mips_isa_rev=1"); \
470 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
472 else if (ISA_MIPS64R2) \
474 builtin_define ("__mips=64"); \
475 builtin_define ("__mips_isa_rev=2"); \
476 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
482 builtin_define ("_ABIO32=1"); \
483 builtin_define ("_MIPS_SIM=_ABIO32"); \
487 builtin_define ("_ABIN32=2"); \
488 builtin_define ("_MIPS_SIM=_ABIN32"); \
492 builtin_define ("_ABI64=3"); \
493 builtin_define ("_MIPS_SIM=_ABI64"); \
497 builtin_define ("_ABIO64=4"); \
498 builtin_define ("_MIPS_SIM=_ABIO64"); \
502 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
503 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
504 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
505 builtin_define_with_int_value ("_MIPS_FPSET", \
506 32 / MAX_FPRS_PER_FMT); \
508 /* These defines reflect the ABI in use, not whether the \
509 FPU is directly accessible. */ \
510 if (TARGET_HARD_FLOAT_ABI) \
511 builtin_define ("__mips_hard_float"); \
513 builtin_define ("__mips_soft_float"); \
515 if (TARGET_SINGLE_FLOAT) \
516 builtin_define ("__mips_single_float"); \
518 if (TARGET_PAIRED_SINGLE_FLOAT) \
519 builtin_define ("__mips_paired_single_float"); \
521 if (TARGET_BIG_ENDIAN) \
523 builtin_define_std ("MIPSEB"); \
524 builtin_define ("_MIPSEB"); \
528 builtin_define_std ("MIPSEL"); \
529 builtin_define ("_MIPSEL"); \
532 /* Whether calls should go through $25. The separate __PIC__ \
533 macro indicates whether abicalls code might use a GOT. */ \
534 if (TARGET_ABICALLS) \
535 builtin_define ("__mips_abicalls"); \
537 /* Whether Loongson vector modes are enabled. */ \
538 if (TARGET_LOONGSON_VECTORS) \
539 builtin_define ("__mips_loongson_vector_rev"); \
541 /* Historical Octeon macro. */ \
543 builtin_define ("__OCTEON__"); \
545 /* Macros dependent on the C dialect. */ \
546 if (preprocessing_asm_p ()) \
548 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
549 builtin_define ("_LANGUAGE_ASSEMBLY"); \
551 else if (c_dialect_cxx ()) \
553 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
554 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
555 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
559 builtin_define_std ("LANGUAGE_C"); \
560 builtin_define ("_LANGUAGE_C"); \
562 if (c_dialect_objc ()) \
564 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
565 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
566 /* Bizarre, but needed at least for Irix. */ \
567 builtin_define_std ("LANGUAGE_C"); \
568 builtin_define ("_LANGUAGE_C"); \
571 if (mips_abi == ABI_EABI) \
572 builtin_define ("__mips_eabi"); \
574 if (TARGET_CACHE_BUILTIN) \
575 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
579 /* Default target_flags if no switches are specified */
581 #ifndef TARGET_DEFAULT
582 #define TARGET_DEFAULT 0
585 #ifndef TARGET_CPU_DEFAULT
586 #define TARGET_CPU_DEFAULT 0
589 #ifndef TARGET_ENDIAN_DEFAULT
590 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
593 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
594 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
597 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
598 #ifndef MIPS_ISA_DEFAULT
599 #ifndef MIPS_CPU_STRING_DEFAULT
600 #define MIPS_CPU_STRING_DEFAULT "from-abi"
606 /* Make this compile time constant for libgcc2 */
608 #define TARGET_64BIT 1
610 #define TARGET_64BIT 0
612 #endif /* IN_LIBGCC2 */
614 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
615 when compiled with hardware floating point. This is because MIPS16
616 code cannot save and restore the floating-point registers, which is
617 important if in a mixed MIPS16/non-MIPS16 environment. */
620 #if __mips_hard_float
621 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
623 #endif /* IN_LIBGCC2 */
625 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
627 #ifndef MULTILIB_ENDIAN_DEFAULT
628 #if TARGET_ENDIAN_DEFAULT == 0
629 #define MULTILIB_ENDIAN_DEFAULT "EL"
631 #define MULTILIB_ENDIAN_DEFAULT "EB"
635 #ifndef MULTILIB_ISA_DEFAULT
636 # if MIPS_ISA_DEFAULT == 1
637 # define MULTILIB_ISA_DEFAULT "mips1"
639 # if MIPS_ISA_DEFAULT == 2
640 # define MULTILIB_ISA_DEFAULT "mips2"
642 # if MIPS_ISA_DEFAULT == 3
643 # define MULTILIB_ISA_DEFAULT "mips3"
645 # if MIPS_ISA_DEFAULT == 4
646 # define MULTILIB_ISA_DEFAULT "mips4"
648 # if MIPS_ISA_DEFAULT == 32
649 # define MULTILIB_ISA_DEFAULT "mips32"
651 # if MIPS_ISA_DEFAULT == 33
652 # define MULTILIB_ISA_DEFAULT "mips32r2"
654 # if MIPS_ISA_DEFAULT == 64
655 # define MULTILIB_ISA_DEFAULT "mips64"
657 # if MIPS_ISA_DEFAULT == 65
658 # define MULTILIB_ISA_DEFAULT "mips64r2"
660 # define MULTILIB_ISA_DEFAULT "mips1"
671 #ifndef MULTILIB_DEFAULTS
672 #define MULTILIB_DEFAULTS \
673 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
676 /* We must pass -EL to the linker by default for little endian embedded
677 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
678 linker will default to using big-endian output files. The OUTPUT_FORMAT
679 line must be in the linker script, otherwise -EB/-EL will not work. */
682 #if TARGET_ENDIAN_DEFAULT == 0
683 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
685 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
689 /* A spec condition that matches all non-mips16 -mips arguments. */
691 #define MIPS_ISA_LEVEL_OPTION_SPEC \
692 "mips1|mips2|mips3|mips4|mips32*|mips64*"
694 /* A spec condition that matches all non-mips16 architecture arguments. */
696 #define MIPS_ARCH_OPTION_SPEC \
697 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
699 /* A spec that infers a -mips argument from an -march argument,
700 or injects the default if no architecture is specified. */
702 #define MIPS_ISA_LEVEL_SPEC \
703 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
704 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
705 %{march=mips2|march=r6000:-mips2} \
706 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
707 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
708 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
709 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
710 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
711 |march=34k*|march=74k*: -mips32r2} \
712 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
713 %{march=mips64r2|march=octeon: -mips64r2} \
714 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
716 /* A spec that infers a -mhard-float or -msoft-float setting from an
717 -march argument. Note that soft-float and hard-float code are not
720 #define MIPS_ARCH_FLOAT_SPEC \
721 "%{mhard-float|msoft-float|march=mips*:; \
722 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
723 |march=34kc|march=74kc|march=5kc|march=octeon: -msoft-float; \
724 march=*: -mhard-float}"
726 /* A spec condition that matches 32-bit options. It only works if
727 MIPS_ISA_LEVEL_SPEC has been applied. */
729 #define MIPS_32BIT_OPTION_SPEC \
730 "mips1|mips2|mips32*|mgp32"
732 /* Support for a compile-time default CPU, et cetera. The rules are:
733 --with-arch is ignored if -march is specified or a -mips is specified
734 (other than -mips16).
735 --with-tune is ignored if -mtune is specified.
736 --with-abi is ignored if -mabi is specified.
737 --with-float is ignored if -mhard-float or -msoft-float are
739 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
741 #define OPTION_DEFAULT_SPECS \
742 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
743 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
744 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
745 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
746 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
747 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
748 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }
751 /* A spec that infers the -mdsp setting from an -march argument. */
752 #define BASE_DRIVER_SELF_SPECS \
753 "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*: -mdsp}}"
755 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
757 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
758 && ISA_HAS_COND_TRAP)
760 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
762 /* True if the ABI can only work with 64-bit integer registers. We
763 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
764 otherwise floating-point registers must also be 64-bit. */
765 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
767 /* Likewise for 32-bit regs. */
768 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
770 /* True if the file format uses 64-bit symbols. At present, this is
771 only true for n64, which uses 64-bit ELF. */
772 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
774 /* True if symbols are 64 bits wide. This is usually determined by
775 the ABI's file format, but it can be overridden by -msym32. Note that
776 overriding the size with -msym32 changes the ABI of relocatable objects,
777 although it doesn't change the ABI of a fully-linked object. */
778 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
780 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
781 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
786 /* ISA has branch likely instructions (e.g. mips2). */
787 /* Disable branchlikely for tx39 until compare rewrite. They haven't
788 been generated up to this point. */
789 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
791 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
792 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
804 /* ISA has a three-operand multiplication instruction. */
805 #define ISA_HAS_DMUL3 (TARGET_64BIT \
809 /* ISA has the floating-point conditional move instructions introduced
811 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
816 && !TARGET_MIPS5500 \
819 /* ISA has the integer conditional move instructions introduced in mips4 and
820 ST Loongson 2E/2F. */
821 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
823 /* ISA has LDC1 and SDC1. */
824 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
826 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
827 branch on CC, and move (both FP and non-FP) on CC. */
828 #define ISA_HAS_8CC (ISA_MIPS4 \
834 /* This is a catch all for other mips4 instructions: indexed load, the
835 FP madd and msub instructions, and the FP recip and recip sqrt
837 #define ISA_HAS_FP4 ((ISA_MIPS4 \
838 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
843 /* ISA has paired-single instructions. */
844 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
846 /* ISA has conditional trap instructions. */
847 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
850 /* ISA has integer multiply-accumulate instructions, madd and msub. */
851 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
857 /* Integer multiply-accumulate instructions should be generated. */
858 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
860 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
861 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
863 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
864 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
866 /* ISA has floating-point nmadd and nmsub instructions
867 'd = -((a * b) [+-] c)'. */
868 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
870 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
873 && (!TARGET_MIPS5400 || TARGET_MAD) \
876 /* ISA has floating-point nmadd and nmsub instructions
877 'c = -((a * b) [+-] c)'. */
878 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
881 /* ISA has count leading zeroes/ones instruction (not implemented). */
882 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
888 /* ISA has three operand multiply instructions that put
889 the high part in an accumulator: mulhi or mulhiu. */
890 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
895 /* ISA has three operand multiply instructions that
896 negates the result and puts the result in an accumulator. */
897 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
902 /* ISA has three operand multiply instructions that subtracts the
903 result from a 4th operand and puts the result in an accumulator. */
904 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
909 /* ISA has three operand multiply instructions that the result
910 from a 4th operand and puts the result in an accumulator. */
911 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
918 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
919 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
920 || TARGET_MIPS4130) \
923 /* ISA has the "ror" (rotate right) instructions. */
924 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
929 || TARGET_SMARTMIPS) \
932 /* ISA has data prefetch instructions. This controls use of 'pref'. */
933 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
934 || TARGET_LOONGSON_2EF \
941 /* ISA has data indexed prefetch instructions. This controls use of
942 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
943 (prefx is a cop1x instruction, so can only be used if FP is
945 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
951 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
952 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
953 also requires TARGET_DOUBLE_FLOAT. */
954 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
956 /* ISA includes the MIPS32r2 seb and seh instructions. */
957 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
961 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
962 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
966 /* ISA has instructions for accessing top part of 64-bit fp regs. */
967 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
971 /* ISA has lwxs instruction (load w/scaled index address. */
972 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
974 /* The DSP ASE is available. */
975 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
977 /* Revision 2 of the DSP ASE is available. */
978 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
980 /* True if the result of a load is not available to the next instruction.
981 A nop will then be needed between instructions like "lw $4,..."
982 and "addiu $4,$4,1". */
983 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
984 && !TARGET_MIPS3900 \
987 /* Likewise mtc1 and mfc1. */
988 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
989 && !TARGET_LOONGSON_2EF)
991 /* Likewise floating-point comparisons. */
992 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
993 && !TARGET_LOONGSON_2EF)
995 /* True if mflo and mfhi can be immediately followed by instructions
996 which write to the HI and LO registers.
998 According to MIPS specifications, MIPS ISAs I, II, and III need
999 (at least) two instructions between the reads of HI/LO and
1000 instructions which write them, and later ISAs do not. Contradicting
1001 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1002 the UM for the NEC Vr5000) document needing the instructions between
1003 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1004 MIPS64 and later ISAs to have the interlocks, plus any specific
1005 earlier-ISA CPUs for which CPU documentation declares that the
1006 instructions are really interlocked. */
1007 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1011 || TARGET_MIPS5500 \
1012 || TARGET_LOONGSON_2EF)
1014 /* ISA includes synci, jr.hb and jalr.hb. */
1015 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1019 /* ISA includes sync. */
1020 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1021 #define GENERATE_SYNC \
1022 (target_flags_explicit & MASK_LLSC \
1023 ? TARGET_LLSC && !TARGET_MIPS16 \
1026 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1027 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1029 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1030 #define GENERATE_LL_SC \
1031 (target_flags_explicit & MASK_LLSC \
1032 ? TARGET_LLSC && !TARGET_MIPS16 \
1035 /* ISA includes the baddu instruction. */
1036 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1038 /* ISA includes the bbit* instructions. */
1039 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1041 /* ISA includes the cins instruction. */
1042 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1044 /* ISA includes the exts instruction. */
1045 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1047 /* ISA includes the seq and sne instructions. */
1048 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1050 /* ISA includes the pop instruction. */
1051 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1053 /* The CACHE instruction is available in non-MIPS16 code. */
1054 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1056 /* The CACHE instruction is available. */
1057 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1059 /* Add -G xx support. */
1061 #undef SWITCH_TAKES_ARG
1062 #define SWITCH_TAKES_ARG(CHAR) \
1063 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1065 #define OVERRIDE_OPTIONS mips_override_options ()
1067 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1069 /* Show we can debug even without a frame pointer. */
1070 #define CAN_DEBUG_WITHOUT_FP
1072 /* Tell collect what flags to pass to nm. */
1074 #define NM_FLAGS "-Bn"
1078 #ifndef MIPS_ABI_DEFAULT
1079 #define MIPS_ABI_DEFAULT ABI_32
1082 /* Use the most portable ABI flag for the ASM specs. */
1084 #if MIPS_ABI_DEFAULT == ABI_32
1085 #define MULTILIB_ABI_DEFAULT "mabi=32"
1088 #if MIPS_ABI_DEFAULT == ABI_O64
1089 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1092 #if MIPS_ABI_DEFAULT == ABI_N32
1093 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1096 #if MIPS_ABI_DEFAULT == ABI_64
1097 #define MULTILIB_ABI_DEFAULT "mabi=64"
1100 #if MIPS_ABI_DEFAULT == ABI_EABI
1101 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1104 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1105 to the assembler. It may be overridden by subtargets. */
1106 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1107 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1109 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1112 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1113 the assembler. It may be overridden by subtargets.
1115 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1116 COFF debugging info. */
1118 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1119 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1120 %{g} %{g0} %{g1} %{g2} %{g3} \
1121 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1122 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1123 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1124 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1125 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1128 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1129 overridden by subtargets. */
1131 #ifndef SUBTARGET_ASM_SPEC
1132 #define SUBTARGET_ASM_SPEC ""
1137 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1138 %{mips32*} %{mips64*} \
1139 %{mips16} %{mno-mips16:-no-mips16} \
1140 %{mips3d} %{mno-mips3d:-no-mips3d} \
1141 %{mdmx} %{mno-mdmx:-no-mdmx} \
1142 %{mdsp} %{mno-dsp} \
1143 %{mdspr2} %{mno-dspr2} \
1144 %{msmartmips} %{mno-smartmips} \
1146 %{mfix-vr4120} %{mfix-vr4130} \
1147 %(subtarget_asm_optimizing_spec) \
1148 %(subtarget_asm_debugging_spec) \
1149 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1150 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1152 %{mshared} %{mno-shared} \
1153 %{msym32} %{mno-sym32} \
1155 %(subtarget_asm_spec)"
1157 /* Extra switches sometimes passed to the linker. */
1158 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1159 will interpret it as a -b option. */
1162 #define LINK_SPEC "\
1164 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1165 %{bestGnum} %{shared} %{non_shared}"
1166 #endif /* LINK_SPEC defined */
1169 /* Specs for the compiler proper */
1171 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1172 overridden by subtargets. */
1173 #ifndef SUBTARGET_CC1_SPEC
1174 #define SUBTARGET_CC1_SPEC ""
1177 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1181 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1182 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1184 %(subtarget_cc1_spec)"
1186 /* Preprocessor specs. */
1188 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1189 overridden by subtargets. */
1190 #ifndef SUBTARGET_CPP_SPEC
1191 #define SUBTARGET_CPP_SPEC ""
1194 #define CPP_SPEC "%(subtarget_cpp_spec)"
1196 /* This macro defines names of additional specifications to put in the specs
1197 that can be used in various specifications like CC1_SPEC. Its definition
1198 is an initializer with a subgrouping for each command option.
1200 Each subgrouping contains a string constant, that defines the
1201 specification name, and a string constant that used by the GCC driver
1204 Do not define this macro if it does not need to do anything. */
1206 #define EXTRA_SPECS \
1207 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1208 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1209 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1210 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1211 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1212 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1213 { "endian_spec", ENDIAN_SPEC }, \
1214 SUBTARGET_EXTRA_SPECS
1216 #ifndef SUBTARGET_EXTRA_SPECS
1217 #define SUBTARGET_EXTRA_SPECS
1220 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1221 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1223 #ifndef PREFERRED_DEBUGGING_TYPE
1224 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1227 /* The size of DWARF addresses should be the same as the size of symbols
1228 in the target file format. They shouldn't depend on things like -msym32,
1229 because many DWARF consumers do not allow the mixture of address sizes
1230 that one would then get from linking -msym32 code with -msym64 code.
1232 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1233 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1234 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1236 /* By default, turn on GDB extensions. */
1237 #define DEFAULT_GDB_EXTENSIONS 1
1239 /* Local compiler-generated symbols must have a prefix that the assembler
1240 understands. By default, this is $, although some targets (e.g.,
1241 NetBSD-ELF) need to override this. */
1243 #ifndef LOCAL_LABEL_PREFIX
1244 #define LOCAL_LABEL_PREFIX "$"
1247 /* By default on the mips, external symbols do not have an underscore
1248 prepended, but some targets (e.g., NetBSD) require this. */
1250 #ifndef USER_LABEL_PREFIX
1251 #define USER_LABEL_PREFIX ""
1254 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1255 since the length can run past this up to a continuation point. */
1256 #undef DBX_CONTIN_LENGTH
1257 #define DBX_CONTIN_LENGTH 1500
1259 /* How to renumber registers for dbx and gdb. */
1260 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1262 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1263 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1265 /* The DWARF 2 CFA column which tracks the return address. */
1266 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1268 /* Before the prologue, RA lives in r31. */
1269 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1271 /* Describe how we implement __builtin_eh_return. */
1272 #define EH_RETURN_DATA_REGNO(N) \
1273 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1275 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1277 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1278 The default for this in 64-bit mode is 8, which causes problems with
1279 SFmode register saves. */
1280 #define DWARF_CIE_DATA_ALIGNMENT -4
1282 /* Correct the offset of automatic variables and arguments. Note that
1283 the MIPS debug format wants all automatic variables and arguments
1284 to be in terms of the virtual frame pointer (stack pointer before
1285 any adjustment in the function), while the MIPS 3.0 linker wants
1286 the frame pointer to be the stack pointer after the initial
1289 #define DEBUGGER_AUTO_OFFSET(X) \
1290 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1291 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1292 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1294 /* Target machine storage layout */
1296 #define BITS_BIG_ENDIAN 0
1297 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1298 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1300 /* Define this to set the endianness to use in libgcc2.c, which can
1301 not depend on target_flags. */
1302 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1303 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1305 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1308 #define MAX_BITS_PER_WORD 64
1310 /* Width of a word, in units (bytes). */
1311 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1313 #define MIN_UNITS_PER_WORD 4
1316 /* For MIPS, width of a floating point register. */
1317 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1319 /* The number of consecutive floating-point registers needed to store the
1320 largest format supported by the FPU. */
1321 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1323 /* The number of consecutive floating-point registers needed to store the
1324 smallest format supported by the FPU. */
1325 #define MIN_FPRS_PER_FMT \
1326 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1327 ? 1 : MAX_FPRS_PER_FMT)
1329 /* The largest size of value that can be held in floating-point
1330 registers and moved with a single instruction. */
1331 #define UNITS_PER_HWFPVALUE \
1332 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1334 /* The largest size of value that can be held in floating-point
1336 #define UNITS_PER_FPVALUE \
1337 (TARGET_SOFT_FLOAT_ABI ? 0 \
1338 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1339 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1341 /* The number of bytes in a double. */
1342 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1344 #define UNITS_PER_SIMD_WORD(MODE) \
1345 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1347 /* Set the sizes of the core types. */
1348 #define SHORT_TYPE_SIZE 16
1349 #define INT_TYPE_SIZE 32
1350 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1351 #define LONG_LONG_TYPE_SIZE 64
1353 #define FLOAT_TYPE_SIZE 32
1354 #define DOUBLE_TYPE_SIZE 64
1355 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1357 /* Define the sizes of fixed-point types. */
1358 #define SHORT_FRACT_TYPE_SIZE 8
1359 #define FRACT_TYPE_SIZE 16
1360 #define LONG_FRACT_TYPE_SIZE 32
1361 #define LONG_LONG_FRACT_TYPE_SIZE 64
1363 #define SHORT_ACCUM_TYPE_SIZE 16
1364 #define ACCUM_TYPE_SIZE 32
1365 #define LONG_ACCUM_TYPE_SIZE 64
1366 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1367 doesn't support 128-bit integers for MIPS32 currently. */
1368 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1370 /* long double is not a fixed mode, but the idea is that, if we
1371 support long double, we also want a 128-bit integer type. */
1372 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1375 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1376 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1377 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1379 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1383 /* Width in bits of a pointer. */
1384 #ifndef POINTER_SIZE
1385 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1388 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1389 #define PARM_BOUNDARY BITS_PER_WORD
1391 /* Allocation boundary (in *bits*) for the code of a function. */
1392 #define FUNCTION_BOUNDARY 32
1394 /* Alignment of field after `int : 0' in a structure. */
1395 #define EMPTY_FIELD_BOUNDARY 32
1397 /* Every structure's size must be a multiple of this. */
1398 /* 8 is observed right on a DECstation and on riscos 4.02. */
1399 #define STRUCTURE_SIZE_BOUNDARY 8
1401 /* There is no point aligning anything to a rounder boundary than this. */
1402 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1404 /* All accesses must be aligned. */
1405 #define STRICT_ALIGNMENT 1
1407 /* Define this if you wish to imitate the way many other C compilers
1408 handle alignment of bitfields and the structures that contain
1411 The behavior is that the type written for a bit-field (`int',
1412 `short', or other integer type) imposes an alignment for the
1413 entire structure, as if the structure really did contain an
1414 ordinary field of that type. In addition, the bit-field is placed
1415 within the structure so that it would fit within such a field,
1416 not crossing a boundary for it.
1418 Thus, on most machines, a bit-field whose type is written as `int'
1419 would not cross a four-byte boundary, and would force four-byte
1420 alignment for the whole structure. (The alignment used may not
1421 be four bytes; it is controlled by the other alignment
1424 If the macro is defined, its definition should be a C expression;
1425 a nonzero value for the expression enables this behavior. */
1427 #define PCC_BITFIELD_TYPE_MATTERS 1
1429 /* If defined, a C expression to compute the alignment given to a
1430 constant that is being placed in memory. CONSTANT is the constant
1431 and ALIGN is the alignment that the object would ordinarily have.
1432 The value of this macro is used instead of that alignment to align
1435 If this macro is not defined, then ALIGN is used.
1437 The typical use of this macro is to increase alignment for string
1438 constants to be word aligned so that `strcpy' calls that copy
1439 constants can be done inline. */
1441 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1442 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1443 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1445 /* If defined, a C expression to compute the alignment for a static
1446 variable. TYPE is the data type, and ALIGN is the alignment that
1447 the object would ordinarily have. The value of this macro is used
1448 instead of that alignment to align the object.
1450 If this macro is not defined, then ALIGN is used.
1452 One use of this macro is to increase alignment of medium-size
1453 data to make it all fit in fewer cache lines. Another is to
1454 cause character arrays to be word-aligned so that `strcpy' calls
1455 that copy constants to character arrays can be done inline. */
1457 #undef DATA_ALIGNMENT
1458 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1459 ((((ALIGN) < BITS_PER_WORD) \
1460 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1461 || TREE_CODE (TYPE) == UNION_TYPE \
1462 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1464 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1465 character arrays to be word-aligned so that `strcpy' calls that copy
1466 constants to character arrays can be done inline, and 'strcmp' can be
1467 optimised to use word loads. */
1468 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1469 DATA_ALIGNMENT (TYPE, ALIGN)
1471 #define PAD_VARARGS_DOWN \
1472 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1474 /* Define if operations between registers always perform the operation
1475 on the full register even if a narrower mode is specified. */
1476 #define WORD_REGISTER_OPERATIONS
1478 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1479 moves. All other references are zero extended. */
1480 #define LOAD_EXTEND_OP(MODE) \
1481 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1482 ? SIGN_EXTEND : ZERO_EXTEND)
1484 /* Define this macro if it is advisable to hold scalars in registers
1485 in a wider mode than that declared by the program. In such cases,
1486 the value is constrained to be within the bounds of the declared
1487 type, but kept valid in the wider mode. The signedness of the
1488 extension may differ from that of the type. */
1490 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1491 if (GET_MODE_CLASS (MODE) == MODE_INT \
1492 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1494 if ((MODE) == SImode) \
1499 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1500 Extensions of pointers to word_mode must be signed. */
1501 #define POINTERS_EXTEND_UNSIGNED false
1503 /* Define if loading short immediate values into registers sign extends. */
1504 #define SHORT_IMMEDIATES_SIGN_EXTEND
1506 /* The [d]clz instructions have the natural values at 0. */
1508 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1509 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1511 /* Standard register usage. */
1513 /* Number of hardware registers. We have:
1515 - 32 integer registers
1516 - 32 floating point registers
1517 - 8 condition code registers
1518 - 2 accumulator registers (hi and lo)
1519 - 32 registers each for coprocessors 0, 2 and 3
1521 - ARG_POINTER_REGNUM
1522 - FRAME_POINTER_REGNUM
1523 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1524 - 3 dummy entries that were used at various times in the past.
1525 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1526 - 6 DSP control registers */
1528 #define FIRST_PSEUDO_REGISTER 188
1530 /* By default, fix the kernel registers ($26 and $27), the global
1531 pointer ($28) and the stack pointer ($29). This can change
1532 depending on the command-line options.
1534 Regarding coprocessor registers: without evidence to the contrary,
1535 it's best to assume that each coprocessor register has a unique
1536 use. This can be overridden, in, e.g., mips_override_options or
1537 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1538 for a particular target. */
1540 #define FIXED_REGISTERS \
1542 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1543 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1545 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1546 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1547 /* COP0 registers */ \
1548 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1550 /* COP2 registers */ \
1551 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1553 /* COP3 registers */ \
1554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1556 /* 6 DSP accumulator registers & 6 control registers */ \
1557 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1561 /* Set up this array for o32 by default.
1563 Note that we don't mark $31 as a call-clobbered register. The idea is
1564 that it's really the call instructions themselves which clobber $31.
1565 We don't care what the called function does with it afterwards.
1567 This approach makes it easier to implement sibcalls. Unlike normal
1568 calls, sibcalls don't clobber $31, so the register reaches the
1569 called function in tact. EPILOGUE_USES says that $31 is useful
1570 to the called function. */
1572 #define CALL_USED_REGISTERS \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1576 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1577 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1578 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1579 /* COP0 registers */ \
1580 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1582 /* COP2 registers */ \
1583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1584 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1585 /* COP3 registers */ \
1586 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1587 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1588 /* 6 DSP accumulator registers & 6 control registers */ \
1589 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1593 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1595 #define CALL_REALLY_USED_REGISTERS \
1596 { /* General registers. */ \
1597 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1598 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1599 /* Floating-point registers. */ \
1600 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1601 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1603 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1604 /* COP0 registers */ \
1605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1606 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1607 /* COP2 registers */ \
1608 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1609 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1610 /* COP3 registers */ \
1611 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1612 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1613 /* 6 DSP accumulator registers & 6 control registers */ \
1614 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1617 /* Internal macros to classify a register number as to whether it's a
1618 general purpose register, a floating point register, a
1619 multiply/divide register, or a status register. */
1621 #define GP_REG_FIRST 0
1622 #define GP_REG_LAST 31
1623 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1624 #define GP_DBX_FIRST 0
1625 #define K0_REG_NUM (GP_REG_FIRST + 26)
1626 #define K1_REG_NUM (GP_REG_FIRST + 27)
1627 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1629 #define FP_REG_FIRST 32
1630 #define FP_REG_LAST 63
1631 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1632 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1634 #define MD_REG_FIRST 64
1635 #define MD_REG_LAST 65
1636 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1637 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1639 /* The DWARF 2 CFA column which tracks the return address from a
1640 signal handler context. This means that to maintain backwards
1641 compatibility, no hard register can be assigned this column if it
1642 would need to be handled by the DWARF unwinder. */
1643 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1645 #define ST_REG_FIRST 67
1646 #define ST_REG_LAST 74
1647 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1650 /* FIXME: renumber. */
1651 #define COP0_REG_FIRST 80
1652 #define COP0_REG_LAST 111
1653 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1655 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1656 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1657 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1659 #define COP2_REG_FIRST 112
1660 #define COP2_REG_LAST 143
1661 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1663 #define COP3_REG_FIRST 144
1664 #define COP3_REG_LAST 175
1665 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1666 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1667 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1669 #define DSP_ACC_REG_FIRST 176
1670 #define DSP_ACC_REG_LAST 181
1671 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1673 #define AT_REGNUM (GP_REG_FIRST + 1)
1674 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1675 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1677 /* A few bitfield locations for the coprocessor registers. */
1678 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1679 the cause register for the EIC interrupt mode. */
1680 #define CAUSE_IPL 10
1681 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1683 /* Exception Level is at bit 1 of the status register. */
1685 /* Interrupt Enable is at bit 0 of the status register. */
1688 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1689 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1690 should be used instead. */
1691 #define FPSW_REGNUM ST_REG_FIRST
1693 #define GP_REG_P(REGNO) \
1694 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1695 #define M16_REG_P(REGNO) \
1696 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1697 #define FP_REG_P(REGNO) \
1698 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1699 #define MD_REG_P(REGNO) \
1700 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1701 #define ST_REG_P(REGNO) \
1702 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1703 #define COP0_REG_P(REGNO) \
1704 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1705 #define COP2_REG_P(REGNO) \
1706 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1707 #define COP3_REG_P(REGNO) \
1708 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1709 #define ALL_COP_REG_P(REGNO) \
1710 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1711 /* Test if REGNO is one of the 6 new DSP accumulators. */
1712 #define DSP_ACC_REG_P(REGNO) \
1713 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1714 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1715 #define ACC_REG_P(REGNO) \
1716 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1718 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1720 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1721 to initialize the mips16 gp pseudo register. */
1722 #define CONST_GP_P(X) \
1723 (GET_CODE (X) == CONST \
1724 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1725 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1727 /* Return coprocessor number from register number. */
1729 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1730 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1731 : COP3_REG_P (REGNO) ? '3' : '?')
1734 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1736 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1737 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1739 #define MODES_TIEABLE_P mips_modes_tieable_p
1741 /* Register to use for pushing function arguments. */
1742 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1744 /* These two registers don't really exist: they get eliminated to either
1745 the stack or hard frame pointer. */
1746 #define ARG_POINTER_REGNUM 77
1747 #define FRAME_POINTER_REGNUM 78
1749 /* $30 is not available on the mips16, so we use $17 as the frame
1751 #define HARD_FRAME_POINTER_REGNUM \
1752 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1754 #define FRAME_POINTER_REQUIRED (mips_frame_pointer_required ())
1756 /* Register in which static-chain is passed to a function. */
1757 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1759 /* Registers used as temporaries in prologue/epilogue code:
1761 - If a MIPS16 PIC function needs access to _gp, it first loads
1762 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1764 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1765 register. The register must not conflict with MIPS16_PIC_TEMP.
1767 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1770 If we're generating MIPS16 code, these registers must come from the
1771 core set of 8. The prologue registers mustn't conflict with any
1772 incoming arguments, the static chain pointer, or the frame pointer.
1773 The epilogue temporary mustn't conflict with the return registers,
1774 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1775 or the EH data registers.
1777 If we're generating interrupt handlers, we use K0 as a temporary register
1778 in prologue/epilogue code. */
1780 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1781 #define MIPS_PROLOGUE_TEMP_REGNUM \
1782 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1783 #define MIPS_EPILOGUE_TEMP_REGNUM \
1784 (cfun->machine->interrupt_handler_p \
1786 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1788 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1789 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1790 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1792 /* Define this macro if it is as good or better to call a constant
1793 function address than to call an address kept in a register. */
1794 #define NO_FUNCTION_CSE 1
1796 /* The ABI-defined global pointer. Sometimes we use a different
1797 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1798 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1800 /* We normally use $28 as the global pointer. However, when generating
1801 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1802 register instead. They can then avoid saving and restoring $28
1803 and perhaps avoid using a frame at all.
1805 When a leaf function uses something other than $28, mips_expand_prologue
1806 will modify pic_offset_table_rtx in place. Take the register number
1807 from there after reload. */
1808 #define PIC_OFFSET_TABLE_REGNUM \
1809 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1811 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1813 /* Define the classes of registers for register constraints in the
1814 machine description. Also define ranges of constants.
1816 One of the classes must always be named ALL_REGS and include all hard regs.
1817 If there is more than one class, another class must be named NO_REGS
1818 and contain no registers.
1820 The name GENERAL_REGS must be the name of a class (or an alias for
1821 another name such as ALL_REGS). This is the class of registers
1822 that is allowed by "g" or "r" in a register constraint.
1823 Also, registers outside this class are allocated only when
1824 instructions express preferences for them.
1826 The classes must be numbered in nondecreasing order; that is,
1827 a larger-numbered class must never be contained completely
1828 in a smaller-numbered class.
1830 For any two classes, it is very desirable that there be another
1831 class that represents their union. */
1835 NO_REGS, /* no registers in set */
1836 M16_REGS, /* mips16 directly accessible registers */
1837 T_REG, /* mips16 T register ($24) */
1838 M16_T_REGS, /* mips16 registers plus T register */
1839 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1840 V1_REG, /* Register $v1 ($3) used for TLS access. */
1841 LEA_REGS, /* Every GPR except $25 */
1842 GR_REGS, /* integer registers */
1843 FP_REGS, /* floating point registers */
1844 MD0_REG, /* first multiply/divide register */
1845 MD1_REG, /* second multiply/divide register */
1846 MD_REGS, /* multiply/divide registers (hi/lo) */
1847 COP0_REGS, /* generic coprocessor classes */
1850 ST_REGS, /* status registers (fp status) */
1851 DSP_ACC_REGS, /* DSP accumulator registers */
1852 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1853 FRAME_REGS, /* $arg and $frame */
1854 GR_AND_MD0_REGS, /* union classes */
1858 ALL_REGS, /* all registers */
1859 LIM_REG_CLASSES /* max value + 1 */
1862 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1864 #define GENERAL_REGS GR_REGS
1866 /* An initializer containing the names of the register classes as C
1867 string constants. These names are used in writing some of the
1870 #define REG_CLASS_NAMES \
1876 "PIC_FN_ADDR_REG", \
1884 /* coprocessor registers */ \
1892 "GR_AND_MD0_REGS", \
1893 "GR_AND_MD1_REGS", \
1895 "GR_AND_ACC_REGS", \
1899 /* An initializer containing the contents of the register classes,
1900 as integers which are bit masks. The Nth integer specifies the
1901 contents of class N. The way the integer MASK is interpreted is
1902 that register R is in the class if `MASK & (1 << R)' is 1.
1904 When the machine has more than 32 registers, an integer does not
1905 suffice. Then the integers are replaced by sub-initializers,
1906 braced groupings containing several integers. Each
1907 sub-initializer must be suitable as an initializer for the type
1908 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1910 #define REG_CLASS_CONTENTS \
1912 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1913 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1914 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1915 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1916 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1917 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1918 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1919 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1920 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1921 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1922 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1923 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1924 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1925 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1926 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1927 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1928 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1929 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1930 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1931 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1932 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1933 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1934 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1935 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1939 /* A C expression whose value is a register class containing hard
1940 register REGNO. In general there is more that one such class;
1941 choose a class which is "minimal", meaning that no smaller class
1942 also contains the register. */
1944 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1946 /* A macro whose definition is the name of the class to which a
1947 valid base register must belong. A base register is one used in
1948 an address which is the register value plus a displacement. */
1950 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1952 /* A macro whose definition is the name of the class to which a
1953 valid index register must belong. An index register is one used
1954 in an address where its value is either multiplied by a scale
1955 factor or added to another register (as well as added to a
1958 #define INDEX_REG_CLASS NO_REGS
1960 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1961 registers explicitly used in the rtl to be used as spill registers
1962 but prevents the compiler from extending the lifetime of these
1965 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1967 /* We generally want to put call-clobbered registers ahead of
1968 call-saved ones. (IRA expects this.) */
1970 #define REG_ALLOC_ORDER \
1971 { /* Accumulator registers. When GPRs and accumulators have equal \
1972 cost, we generally prefer to use accumulators. For example, \
1973 a division of multiplication result is better allocated to LO, \
1974 so that we put the MFLO at the point of use instead of at the \
1975 point of definition. It's also needed if we're to take advantage \
1976 of the extra accumulators available with -mdspr2. In some cases, \
1977 it can also help to reduce register pressure. */ \
1978 64, 65,176,177,178,179,180,181, \
1979 /* Call-clobbered GPRs. */ \
1980 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1982 /* The global pointer. This is call-clobbered for o32 and o64 \
1983 abicalls, call-saved for n32 and n64 abicalls, and a program \
1984 invariant otherwise. Putting it between the call-clobbered \
1985 and call-saved registers should cope with all eventualities. */ \
1987 /* Call-saved GPRs. */ \
1988 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1989 /* GPRs that can never be exposed to the register allocator. */ \
1991 /* Call-clobbered FPRs. */ \
1992 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1994 /* FPRs that are usually call-saved. The odd ones are actually \
1995 call-clobbered for n32, but listing them ahead of the even \
1996 registers might encourage the register allocator to fragment \
1997 the available FPR pairs. We need paired FPRs to store long \
1998 doubles, so it isn't clear that using a different order \
1999 for n32 would be a win. */ \
2000 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2001 /* None of the remaining classes have defined call-saved \
2003 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2004 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2005 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2006 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2007 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2008 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2009 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2010 182,183,184,185,186,187 \
2013 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2014 to be rearranged based on a particular function. On the mips16, we
2015 want to allocate $24 (T_REG) before other registers for
2016 instructions for which it is possible. */
2018 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2020 /* True if VALUE is an unsigned 6-bit number. */
2022 #define UIMM6_OPERAND(VALUE) \
2023 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2025 /* True if VALUE is a signed 10-bit number. */
2027 #define IMM10_OPERAND(VALUE) \
2028 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2030 /* True if VALUE is a signed 16-bit number. */
2032 #define SMALL_OPERAND(VALUE) \
2033 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2035 /* True if VALUE is an unsigned 16-bit number. */
2037 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2038 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2040 /* True if VALUE can be loaded into a register using LUI. */
2042 #define LUI_OPERAND(VALUE) \
2043 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2044 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2046 /* Return a value X with the low 16 bits clear, and such that
2047 VALUE - X is a signed 16-bit value. */
2049 #define CONST_HIGH_PART(VALUE) \
2050 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2052 #define CONST_LOW_PART(VALUE) \
2053 ((VALUE) - CONST_HIGH_PART (VALUE))
2055 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2056 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2057 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2059 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2060 mips_preferred_reload_class (X, CLASS)
2062 /* The HI and LO registers can only be reloaded via the general
2063 registers. Condition code registers can only be loaded to the
2064 general registers, and from the floating point registers. */
2066 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2067 mips_secondary_reload_class (CLASS, MODE, X, true)
2068 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2069 mips_secondary_reload_class (CLASS, MODE, X, false)
2071 /* Return the maximum number of consecutive registers
2072 needed to represent mode MODE in a register of class CLASS. */
2074 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2076 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2077 mips_cannot_change_mode_class (FROM, TO, CLASS)
2079 /* Stack layout; function entry, exit and calling. */
2081 #define STACK_GROWS_DOWNWARD
2083 /* The offset of the first local variable from the beginning of the frame.
2084 See mips_compute_frame_info for details about the frame layout. */
2086 #define STARTING_FRAME_OFFSET \
2087 (crtl->outgoing_args_size \
2088 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2090 #define RETURN_ADDR_RTX mips_return_addr
2092 /* Mask off the MIPS16 ISA bit in unwind addresses.
2094 The reason for this is a little subtle. When unwinding a call,
2095 we are given the call's return address, which on most targets
2096 is the address of the following instruction. However, what we
2097 actually want to find is the EH region for the call itself.
2098 The target-independent unwind code therefore searches for "RA - 1".
2100 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2101 RA - 1 is therefore the real (even-valued) start of the return
2102 instruction. EH region labels are usually odd-valued MIPS16 symbols
2103 too, so a search for an even address within a MIPS16 region would
2106 However, there is an exception. If the end of an EH region is also
2107 the end of a function, the end label is allowed to be even. This is
2108 necessary because a following non-MIPS16 function may also need EH
2109 information for its first instruction.
2111 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2112 non-ISA-encoded address. This probably isn't ideal, but it is
2113 the traditional (legacy) behavior. It is therefore only safe
2114 to search MIPS EH regions for an _odd-valued_ address.
2116 Masking off the ISA bit means that the target-independent code
2117 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2118 #define MASK_RETURN_ADDR GEN_INT (-2)
2121 /* Similarly, don't use the least-significant bit to tell pointers to
2122 code from vtable index. */
2124 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2126 /* The eliminations to $17 are only used for mips16 code. See the
2127 definition of HARD_FRAME_POINTER_REGNUM. */
2129 #define ELIMINABLE_REGS \
2130 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2131 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2132 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2133 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2134 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2135 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2137 /* Make sure that we're not trying to eliminate to the wrong hard frame
2139 #define CAN_ELIMINATE(FROM, TO) \
2140 ((TO) == HARD_FRAME_POINTER_REGNUM || (TO) == STACK_POINTER_REGNUM)
2142 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2143 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2145 /* Allocate stack space for arguments at the beginning of each function. */
2146 #define ACCUMULATE_OUTGOING_ARGS 1
2148 /* The argument pointer always points to the first argument. */
2149 #define FIRST_PARM_OFFSET(FNDECL) 0
2151 /* o32 and o64 reserve stack space for all argument registers. */
2152 #define REG_PARM_STACK_SPACE(FNDECL) \
2154 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2157 /* Define this if it is the responsibility of the caller to
2158 allocate the area reserved for arguments passed in registers.
2159 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2160 of this macro is to determine whether the space is included in
2161 `crtl->outgoing_args_size'. */
2162 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2164 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2166 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2168 /* Symbolic macros for the registers used to return integer and floating
2171 #define GP_RETURN (GP_REG_FIRST + 2)
2172 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2174 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2176 /* Symbolic macros for the first/last argument registers. */
2178 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2179 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2180 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2181 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2183 #define LIBCALL_VALUE(MODE) \
2184 mips_function_value (NULL_TREE, MODE)
2186 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2187 mips_function_value (VALTYPE, VOIDmode)
2189 /* 1 if N is a possible register number for a function value.
2190 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2191 Currently, R2 and F0 are only implemented here (C has no complex type) */
2193 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2194 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2195 && (N) == FP_RETURN + 2))
2197 /* 1 if N is a possible register number for function argument passing.
2198 We have no FP argument registers when soft-float. When FP registers
2199 are 32 bits, we can't directly reference the odd numbered ones. */
2201 #define FUNCTION_ARG_REGNO_P(N) \
2202 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2203 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2206 /* This structure has to cope with two different argument allocation
2207 schemes. Most MIPS ABIs view the arguments as a structure, of which
2208 the first N words go in registers and the rest go on the stack. If I
2209 < N, the Ith word might go in Ith integer argument register or in a
2210 floating-point register. For these ABIs, we only need to remember
2211 the offset of the current argument into the structure.
2213 The EABI instead allocates the integer and floating-point arguments
2214 separately. The first N words of FP arguments go in FP registers,
2215 the rest go on the stack. Likewise, the first N words of the other
2216 arguments go in integer registers, and the rest go on the stack. We
2217 need to maintain three counts: the number of integer registers used,
2218 the number of floating-point registers used, and the number of words
2219 passed on the stack.
2221 We could keep separate information for the two ABIs (a word count for
2222 the standard ABIs, and three separate counts for the EABI). But it
2223 seems simpler to view the standard ABIs as forms of EABI that do not
2224 allocate floating-point registers.
2226 So for the standard ABIs, the first N words are allocated to integer
2227 registers, and mips_function_arg decides on an argument-by-argument
2228 basis whether that argument should really go in an integer register,
2229 or in a floating-point one. */
2231 typedef struct mips_args {
2232 /* Always true for varargs functions. Otherwise true if at least
2233 one argument has been passed in an integer register. */
2236 /* The number of arguments seen so far. */
2237 unsigned int arg_number;
2239 /* The number of integer registers used so far. For all ABIs except
2240 EABI, this is the number of words that have been added to the
2241 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2242 unsigned int num_gprs;
2244 /* For EABI, the number of floating-point registers used so far. */
2245 unsigned int num_fprs;
2247 /* The number of words passed on the stack. */
2248 unsigned int stack_words;
2250 /* On the mips16, we need to keep track of which floating point
2251 arguments were passed in general registers, but would have been
2252 passed in the FP regs if this were a 32-bit function, so that we
2253 can move them to the FP regs if we wind up calling a 32-bit
2254 function. We record this information in fp_code, encoded in base
2255 four. A zero digit means no floating point argument, a one digit
2256 means an SFmode argument, and a two digit means a DFmode argument,
2257 and a three digit is not used. The low order digit is the first
2258 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2259 an SFmode argument. ??? A more sophisticated approach will be
2260 needed if MIPS_ABI != ABI_32. */
2263 /* True if the function has a prototype. */
2267 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2268 for a call to a function whose data type is FNTYPE.
2269 For a library call, FNTYPE is 0. */
2271 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2272 mips_init_cumulative_args (&CUM, FNTYPE)
2274 /* Update the data in CUM to advance over an argument
2275 of mode MODE and data type TYPE.
2276 (TYPE is null for libcalls where that information may not be available.) */
2278 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2279 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2281 /* Determine where to put an argument to a function.
2282 Value is zero to push the argument on the stack,
2283 or a hard register in which to store the argument.
2285 MODE is the argument's machine mode.
2286 TYPE is the data type of the argument (as a tree).
2287 This is null for libcalls where that information may
2289 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2290 the preceding args and about the function being called.
2291 NAMED is nonzero if this argument is a named parameter
2292 (otherwise it is an extra parameter matching an ellipsis). */
2294 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2295 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2297 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2299 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2300 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2302 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2303 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2305 /* True if using EABI and varargs can be passed in floating-point
2306 registers. Under these conditions, we need a more complex form
2307 of va_list, which tracks GPR, FPR and stack arguments separately. */
2308 #define EABI_FLOAT_VARARGS_P \
2309 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2312 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2314 /* Treat LOC as a byte offset from the stack pointer and round it up
2315 to the next fully-aligned offset. */
2316 #define MIPS_STACK_ALIGN(LOC) \
2317 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2320 /* Output assembler code to FILE to increment profiler label # LABELNO
2321 for profiling a function entry. */
2323 #define FUNCTION_PROFILER(FILE, LABELNO) \
2325 if (TARGET_MIPS16) \
2326 sorry ("mips16 function profiling"); \
2327 if (TARGET_LONG_CALLS) \
2329 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */ \
2330 if (Pmode == DImode) \
2331 fprintf (FILE, "\tdla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2333 fprintf (FILE, "\tla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2335 fprintf (FILE, "\t.set\tnoat\n"); \
2336 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2337 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2338 /* _mcount treats $2 as the static chain register. */ \
2339 if (cfun->static_chain_decl != NULL) \
2340 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[2], \
2341 reg_names[STATIC_CHAIN_REGNUM]); \
2342 if (!TARGET_NEWABI) \
2345 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2346 TARGET_64BIT ? "dsubu" : "subu", \
2347 reg_names[STACK_POINTER_REGNUM], \
2348 reg_names[STACK_POINTER_REGNUM], \
2349 Pmode == DImode ? 16 : 8); \
2351 if (TARGET_LONG_CALLS) \
2352 fprintf (FILE, "\tjalr\t%s\n", reg_names[GP_REG_FIRST + 3]); \
2354 fprintf (FILE, "\tjal\t_mcount\n"); \
2355 fprintf (FILE, "\t.set\tat\n"); \
2356 /* _mcount treats $2 as the static chain register. */ \
2357 if (cfun->static_chain_decl != NULL) \
2358 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], \
2362 /* The profiler preserves all interesting registers, including $31. */
2363 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2365 /* No mips port has ever used the profiler counter word, so don't emit it
2366 or the label for it. */
2368 #define NO_PROFILE_COUNTERS 1
2370 /* Define this macro if the code for function profiling should come
2371 before the function prologue. Normally, the profiling code comes
2374 /* #define PROFILE_BEFORE_PROLOGUE */
2376 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2377 the stack pointer does not matter. The value is tested only in
2378 functions that have frame pointers.
2379 No definition is equivalent to always zero. */
2381 #define EXIT_IGNORE_STACK 1
2384 /* A C statement to output, on the stream FILE, assembler code for a
2385 block of data that contains the constant parts of a trampoline.
2386 This code should not include a label--the label is taken care of
2389 #define TRAMPOLINE_TEMPLATE(STREAM) \
2391 if (ptr_mode == DImode) \
2392 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2394 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2395 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2396 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2397 if (ptr_mode == DImode) \
2399 fprintf (STREAM, "\t.word\t0xdff90014\t\t# ld $25,20($31)\n"); \
2400 fprintf (STREAM, "\t.word\t0xdfef001c\t\t# ld $15,28($31)\n"); \
2404 fprintf (STREAM, "\t.word\t0x8ff90010\t\t# lw $25,16($31)\n"); \
2405 fprintf (STREAM, "\t.word\t0x8fef0014\t\t# lw $15,20($31)\n"); \
2407 fprintf (STREAM, "\t.word\t0x03200008\t\t# jr $25\n"); \
2408 if (ptr_mode == DImode) \
2410 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2411 fprintf (STREAM, "\t.word\t0x00000000\t\t# <padding>\n"); \
2412 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2413 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2417 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2418 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2419 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2423 /* A C expression for the size in bytes of the trampoline, as an
2426 #define TRAMPOLINE_SIZE (ptr_mode == DImode ? 48 : 36)
2428 /* Alignment required for trampolines, in bits. */
2430 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2432 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2433 program and data caches. */
2435 #ifndef CACHE_FLUSH_FUNC
2436 #define CACHE_FLUSH_FUNC "_flush_cache"
2439 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2440 /* Flush both caches. We need to flush the data cache in case \
2441 the system has a write-back cache. */ \
2442 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2443 0, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2444 GEN_INT (3), TYPE_MODE (integer_type_node))
2446 /* A C statement to initialize the variable parts of a trampoline.
2447 ADDR is an RTX for the address of the trampoline; FNADDR is an
2448 RTX for the address of the nested function; STATIC_CHAIN is an
2449 RTX for the static chain value that should be passed to the
2450 function when it is called. */
2452 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2454 rtx func_addr, chain_addr, end_addr; \
2456 func_addr = plus_constant (ADDR, ptr_mode == DImode ? 32 : 28); \
2457 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2458 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2459 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2460 end_addr = gen_reg_rtx (Pmode); \
2461 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2462 GEN_INT (TRAMPOLINE_SIZE))); \
2463 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2466 /* Addressing modes, and classification of registers for them. */
2468 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2469 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2470 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2472 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2473 and check its validity for a certain class.
2474 We have two alternate definitions for each of them.
2475 The usual definition accepts all pseudo regs; the other rejects them all.
2476 The symbol REG_OK_STRICT causes the latter definition to be used.
2478 Most source files want to accept pseudo regs in the hope that
2479 they will get allocated to the class that the insn wants them to be in.
2480 Some source files that are used after register allocation
2481 need to be strict. */
2483 #ifndef REG_OK_STRICT
2484 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2485 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2487 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2488 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2491 #define REG_OK_FOR_INDEX_P(X) 0
2494 /* Maximum number of registers that can appear in a valid memory address. */
2496 #define MAX_REGS_PER_ADDRESS 1
2498 #ifdef REG_OK_STRICT
2499 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2501 if (mips_legitimate_address_p (MODE, X, 1)) \
2505 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2507 if (mips_legitimate_address_p (MODE, X, 0)) \
2512 /* Check for constness inline but use mips_legitimate_address_p
2513 to check whether a constant really is an address. */
2515 #define CONSTANT_ADDRESS_P(X) \
2516 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2518 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2520 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2522 if (mips_legitimize_address (&(X), MODE)) \
2527 /* A C statement or compound statement with a conditional `goto
2528 LABEL;' executed if memory address X (an RTX) can have different
2529 meanings depending on the machine mode of the memory reference it
2532 Autoincrement and autodecrement addresses typically have
2533 mode-dependent effects because the amount of the increment or
2534 decrement is the size of the operand being addressed. Some
2535 machines have other mode-dependent addresses. Many RISC machines
2536 have no mode-dependent addresses.
2538 You may assume that ADDR is a valid address for the machine. */
2540 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2542 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2543 'the start of the function that this code is output in'. */
2545 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2546 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2547 asm_fprintf ((FILE), "%U%s", \
2548 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2550 asm_fprintf ((FILE), "%U%s", (NAME))
2552 /* Flag to mark a function decl symbol that requires a long call. */
2553 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2554 #define SYMBOL_REF_LONG_CALL_P(X) \
2555 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2557 /* This flag marks functions that cannot be lazily bound. */
2558 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2559 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2560 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2562 /* True if we're generating a form of MIPS16 code in which jump tables
2563 are stored in the text section and encoded as 16-bit PC-relative
2564 offsets. This is only possible when general text loads are allowed,
2565 since the table access itself will be an "lh" instruction. */
2566 /* ??? 16-bit offsets can overflow in large functions. */
2567 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2569 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2571 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2573 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2575 /* Define this as 1 if `char' should by default be signed; else as 0. */
2576 #ifndef DEFAULT_SIGNED_CHAR
2577 #define DEFAULT_SIGNED_CHAR 1
2580 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2581 we generally don't want to use them for copying arbitrary data.
2582 A single N-word move is usually the same cost as N single-word moves. */
2583 #define MOVE_MAX UNITS_PER_WORD
2584 #define MAX_MOVE_MAX 8
2586 /* Define this macro as a C expression which is nonzero if
2587 accessing less than a word of memory (i.e. a `char' or a
2588 `short') is no faster than accessing a word of memory, i.e., if
2589 such access require more than one instruction or if there is no
2590 difference in cost between byte and (aligned) word loads.
2592 On RISC machines, it tends to generate better code to define
2593 this as 1, since it avoids making a QI or HI mode register.
2595 But, generating word accesses for -mips16 is generally bad as shifts
2596 (often extended) would be needed for byte accesses. */
2597 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2599 /* Define this to be nonzero if shift instructions ignore all but the low-order
2601 #define SHIFT_COUNT_TRUNCATED 1
2603 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2604 is done just by pretending it is already truncated. */
2605 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2606 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2609 /* Specify the machine mode that pointers have.
2610 After generation of rtl, the compiler makes no further distinction
2611 between pointers and any other objects of this machine mode. */
2614 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2617 /* Give call MEMs SImode since it is the "most permissive" mode
2618 for both 32-bit and 64-bit targets. */
2620 #define FUNCTION_MODE SImode
2623 /* A C expression for the cost of moving data from a register in
2624 class FROM to one in class TO. The classes are expressed using
2625 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2626 the default; other values are interpreted relative to that.
2628 It is not required that the cost always equal 2 when FROM is the
2629 same as TO; on some machines it is expensive to move between
2630 registers if they are not general registers.
2632 If reload sees an insn consisting of a single `set' between two
2633 hard registers, and if `REGISTER_MOVE_COST' applied to their
2634 classes returns a value of 2, reload does not check to ensure
2635 that the constraints of the insn are met. Setting a cost of
2636 other than 2 will allow reload to verify that the constraints are
2637 met. You should do this if the `movM' pattern's constraints do
2638 not allow such copying. */
2640 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2641 mips_register_move_cost (MODE, FROM, TO)
2643 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2644 (mips_cost->memory_latency \
2645 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2647 /* Define if copies to/from condition code registers should be avoided.
2649 This is needed for the MIPS because reload_outcc is not complete;
2650 it needs to handle cases where the source is a general or another
2651 condition code register. */
2652 #define AVOID_CCMODE_COPIES
2654 /* A C expression for the cost of a branch instruction. A value of
2655 1 is the default; other values are interpreted relative to that. */
2657 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2658 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2660 /* If defined, modifies the length assigned to instruction INSN as a
2661 function of the context in which it is used. LENGTH is an lvalue
2662 that contains the initially computed length of the insn and should
2663 be updated with the correct length of the insn. */
2664 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2665 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2667 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2668 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2670 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2671 "%*" OPCODE "%?\t" OPERANDS "%/"
2673 /* Return the asm template for a call. INSN is the instruction's mnemonic
2674 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2677 When generating GOT code without explicit relocation operators,
2678 all calls should use assembly macros. Otherwise, all indirect
2679 calls should use "jr" or "jalr"; we will arrange to restore $gp
2680 afterwards if necessary. Finally, we can only generate direct
2681 calls for -mabicalls by temporarily switching to non-PIC mode. */
2682 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2683 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2684 ? "%*" INSN "\t%" #OPNO "%/" \
2685 : REG_P (OPERANDS[OPNO]) \
2686 ? "%*" INSN "r\t%" #OPNO "%/" \
2687 : TARGET_ABICALLS_PIC2 \
2688 ? (".option\tpic0\n\t" \
2689 "%*" INSN "\t%" #OPNO "%/\n\t" \
2691 : "%*" INSN "\t%" #OPNO "%/")
2693 /* Control the assembler format that we output. */
2695 /* Output to assembler file text saying following lines
2696 may contain character constants, extra white space, comments, etc. */
2699 #define ASM_APP_ON " #APP\n"
2702 /* Output to assembler file text saying following lines
2703 no longer contain unusual constructs. */
2706 #define ASM_APP_OFF " #NO_APP\n"
2709 #define REGISTER_NAMES \
2710 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2711 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2712 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2713 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2714 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2715 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2716 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2717 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2718 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2719 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2720 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2721 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2722 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2723 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2724 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2725 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2726 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2727 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2728 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2729 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2730 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2731 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2732 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2733 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2735 /* List the "software" names for each register. Also list the numerical
2736 names for $fp and $sp. */
2738 #define ADDITIONAL_REGISTER_NAMES \
2740 { "$29", 29 + GP_REG_FIRST }, \
2741 { "$30", 30 + GP_REG_FIRST }, \
2742 { "at", 1 + GP_REG_FIRST }, \
2743 { "v0", 2 + GP_REG_FIRST }, \
2744 { "v1", 3 + GP_REG_FIRST }, \
2745 { "a0", 4 + GP_REG_FIRST }, \
2746 { "a1", 5 + GP_REG_FIRST }, \
2747 { "a2", 6 + GP_REG_FIRST }, \
2748 { "a3", 7 + GP_REG_FIRST }, \
2749 { "t0", 8 + GP_REG_FIRST }, \
2750 { "t1", 9 + GP_REG_FIRST }, \
2751 { "t2", 10 + GP_REG_FIRST }, \
2752 { "t3", 11 + GP_REG_FIRST }, \
2753 { "t4", 12 + GP_REG_FIRST }, \
2754 { "t5", 13 + GP_REG_FIRST }, \
2755 { "t6", 14 + GP_REG_FIRST }, \
2756 { "t7", 15 + GP_REG_FIRST }, \
2757 { "s0", 16 + GP_REG_FIRST }, \
2758 { "s1", 17 + GP_REG_FIRST }, \
2759 { "s2", 18 + GP_REG_FIRST }, \
2760 { "s3", 19 + GP_REG_FIRST }, \
2761 { "s4", 20 + GP_REG_FIRST }, \
2762 { "s5", 21 + GP_REG_FIRST }, \
2763 { "s6", 22 + GP_REG_FIRST }, \
2764 { "s7", 23 + GP_REG_FIRST }, \
2765 { "t8", 24 + GP_REG_FIRST }, \
2766 { "t9", 25 + GP_REG_FIRST }, \
2767 { "k0", 26 + GP_REG_FIRST }, \
2768 { "k1", 27 + GP_REG_FIRST }, \
2769 { "gp", 28 + GP_REG_FIRST }, \
2770 { "sp", 29 + GP_REG_FIRST }, \
2771 { "fp", 30 + GP_REG_FIRST }, \
2772 { "ra", 31 + GP_REG_FIRST }, \
2773 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2776 /* This is meant to be redefined in the host dependent files. It is a
2777 set of alternative names and regnums for mips coprocessors. */
2779 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2781 #define PRINT_OPERAND mips_print_operand
2782 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2783 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2785 /* A C statement, to be executed after all slot-filler instructions
2786 have been output. If necessary, call `dbr_sequence_length' to
2787 determine the number of slots filled in a sequence (zero if not
2788 currently outputting a sequence), to decide how many no-ops to
2789 output, or whatever.
2791 Don't define this macro if it has nothing to do, but it is
2792 helpful in reading assembly output if the extent of the delay
2793 sequence is made explicit (e.g. with white space).
2795 Note that output routines for instructions with delay slots must
2796 be prepared to deal with not being output as part of a sequence
2797 (i.e. when the scheduling pass is not run, or when no slot
2798 fillers could be found.) The variable `final_sequence' is null
2799 when not processing a sequence, otherwise it contains the
2800 `sequence' rtx being output. */
2802 #define DBR_OUTPUT_SEQEND(STREAM) \
2805 if (set_nomacro > 0 && --set_nomacro == 0) \
2806 fputs ("\t.set\tmacro\n", STREAM); \
2808 if (set_noreorder > 0 && --set_noreorder == 0) \
2809 fputs ("\t.set\treorder\n", STREAM); \
2811 fputs ("\n", STREAM); \
2815 /* How to tell the debugger about changes of source files. */
2816 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2818 /* mips-tfile does not understand .stabd directives. */
2819 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2820 dbxout_begin_stabn_sline (LINE); \
2821 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2824 /* Use .loc directives for SDB line numbers. */
2825 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2826 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2828 /* The MIPS implementation uses some labels for its own purpose. The
2829 following lists what labels are created, and are all formed by the
2830 pattern $L[a-z].*. The machine independent portion of GCC creates
2831 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2833 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2834 $Lb[0-9]+ Begin blocks for MIPS debug support
2835 $Lc[0-9]+ Label for use in s<xx> operation.
2836 $Le[0-9]+ End blocks for MIPS debug support */
2838 #undef ASM_DECLARE_OBJECT_NAME
2839 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2840 mips_declare_object (STREAM, NAME, "", ":\n")
2842 /* Globalizing directive for a label. */
2843 #define GLOBAL_ASM_OP "\t.globl\t"
2845 /* This says how to define a global common symbol. */
2847 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2849 /* This says how to define a local common symbol (i.e., not visible to
2852 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2853 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2854 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2857 /* This says how to output an external. It would be possible not to
2858 output anything and let undefined symbol become external. However
2859 the assembler uses length information on externals to allocate in
2860 data/sdata bss/sbss, thereby saving exec time. */
2862 #undef ASM_OUTPUT_EXTERNAL
2863 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2864 mips_output_external(STREAM,DECL,NAME)
2866 /* This is how to declare a function name. The actual work of
2867 emitting the label is moved to function_prologue, so that we can
2868 get the line number correctly emitted before the .ent directive,
2869 and after any .file directives. Define as empty so that the function
2870 is not declared before the .ent directive elsewhere. */
2872 #undef ASM_DECLARE_FUNCTION_NAME
2873 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2875 /* This is how to store into the string LABEL
2876 the symbol_ref name of an internal numbered label where
2877 PREFIX is the class of label and NUM is the number within the class.
2878 This is suitable for output with `assemble_name'. */
2880 #undef ASM_GENERATE_INTERNAL_LABEL
2881 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2882 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2884 /* Print debug labels as "foo = ." rather than "foo:" because they should
2885 represent a byte pointer rather than an ISA-encoded address. This is
2886 particularly important for code like:
2891 .section .gcc_except_table,...
2893 .uleb128 foo-$LFBxxx
2895 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2896 likewise a byte pointer rather than an ISA-encoded address.
2898 At the time of writing, this hook is not used for the function end
2904 But this doesn't matter, because GAS doesn't treat a pre-.end label
2905 as a MIPS16 one anyway. */
2907 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2908 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2910 /* This is how to output an element of a case-vector that is absolute. */
2912 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2913 fprintf (STREAM, "\t%s\t%sL%d\n", \
2914 ptr_mode == DImode ? ".dword" : ".word", \
2915 LOCAL_LABEL_PREFIX, \
2918 /* This is how to output an element of a case-vector. We can make the
2919 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2922 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2924 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2925 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2926 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2927 else if (TARGET_GPWORD) \
2928 fprintf (STREAM, "\t%s\t%sL%d\n", \
2929 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2930 LOCAL_LABEL_PREFIX, VALUE); \
2931 else if (TARGET_RTP_PIC) \
2933 /* Make the entry relative to the start of the function. */ \
2934 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2935 fprintf (STREAM, "\t%s\t%sL%d-", \
2936 Pmode == DImode ? ".dword" : ".word", \
2937 LOCAL_LABEL_PREFIX, VALUE); \
2938 assemble_name (STREAM, XSTR (fnsym, 0)); \
2939 fprintf (STREAM, "\n"); \
2942 fprintf (STREAM, "\t%s\t%sL%d\n", \
2943 ptr_mode == DImode ? ".dword" : ".word", \
2944 LOCAL_LABEL_PREFIX, VALUE); \
2947 /* This is how to output an assembler line
2948 that says to advance the location counter
2949 to a multiple of 2**LOG bytes. */
2951 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2952 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2954 /* This is how to output an assembler line to advance the location
2955 counter by SIZE bytes. */
2957 #undef ASM_OUTPUT_SKIP
2958 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2959 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2961 /* This is how to output a string. */
2962 #undef ASM_OUTPUT_ASCII
2963 #define ASM_OUTPUT_ASCII mips_output_ascii
2965 /* Output #ident as a in the read-only data section. */
2966 #undef ASM_OUTPUT_IDENT
2967 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2969 const char *p = STRING; \
2970 int size = strlen (p) + 1; \
2971 switch_to_section (readonly_data_section); \
2972 assemble_string (p, size); \
2975 /* Default to -G 8 */
2976 #ifndef MIPS_DEFAULT_GVALUE
2977 #define MIPS_DEFAULT_GVALUE 8
2980 /* Define the strings to put out for each section in the object file. */
2981 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2982 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2984 #undef READONLY_DATA_SECTION_ASM_OP
2985 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2987 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2990 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2991 TARGET_64BIT ? "daddiu" : "addiu", \
2992 reg_names[STACK_POINTER_REGNUM], \
2993 reg_names[STACK_POINTER_REGNUM], \
2994 TARGET_64BIT ? "sd" : "sw", \
2996 reg_names[STACK_POINTER_REGNUM]); \
3000 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3003 if (! set_noreorder) \
3004 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3006 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3007 TARGET_64BIT ? "ld" : "lw", \
3009 reg_names[STACK_POINTER_REGNUM], \
3010 TARGET_64BIT ? "daddu" : "addu", \
3011 reg_names[STACK_POINTER_REGNUM], \
3012 reg_names[STACK_POINTER_REGNUM]); \
3014 if (! set_noreorder) \
3015 fprintf (STREAM, "\t.set\treorder\n"); \
3019 /* How to start an assembler comment.
3020 The leading space is important (the mips native assembler requires it). */
3021 #ifndef ASM_COMMENT_START
3022 #define ASM_COMMENT_START " #"
3025 /* Default definitions for size_t and ptrdiff_t. We must override the
3026 definitions from ../svr4.h on mips-*-linux-gnu. */
3029 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3032 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3034 /* The maximum number of bytes that can be copied by one iteration of
3035 a movmemsi loop; see mips_block_move_loop. */
3036 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3037 (UNITS_PER_WORD * 4)
3039 /* The maximum number of bytes that can be copied by a straight-line
3040 implementation of movmemsi; see mips_block_move_straight. We want
3041 to make sure that any loop-based implementation will iterate at
3043 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3044 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3046 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3047 values were determined experimentally by benchmarking with CSiBE.
3048 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3049 for o32 where we have to restore $gp afterwards as well as make an
3050 indirect call), but in practice, bumping this up higher for
3051 TARGET_ABICALLS doesn't make much difference to code size. */
3053 #define MIPS_CALL_RATIO 8
3055 /* Any loop-based implementation of movmemsi will have at least
3056 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3057 moves, so allow individual copies of fewer elements.
3059 When movmemsi is not available, use a value approximating
3060 the length of a memcpy call sequence, so that move_by_pieces
3061 will generate inline code if it is shorter than a function call.
3062 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3063 we'll have to generate a load/store pair for each, halve the
3064 value of MIPS_CALL_RATIO to take that into account. */
3066 #define MOVE_RATIO(speed) \
3068 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3069 : MIPS_CALL_RATIO / 2)
3071 /* movmemsi is meant to generate code that is at least as good as
3072 move_by_pieces. However, movmemsi effectively uses a by-pieces
3073 implementation both for moves smaller than a word and for word-aligned
3074 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
3075 allow the tree-level optimisers to do such moves by pieces, as it
3076 often exposes other optimization opportunities. We might as well
3077 continue to use movmemsi at the rtl level though, as it produces
3078 better code when scheduling is disabled (such as at -O). */
3080 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
3082 ? (!currently_expanding_to_rtl \
3083 && ((ALIGN) < BITS_PER_WORD \
3084 ? (SIZE) < UNITS_PER_WORD \
3085 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
3086 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
3087 < (unsigned int) MOVE_RATIO (false)))
3089 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3090 of the length of a memset call, but use the default otherwise. */
3092 #define CLEAR_RATIO(speed)\
3093 ((speed) ? 15 : MIPS_CALL_RATIO)
3095 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3096 optimizing for size adjust the ratio to account for the overhead of
3097 loading the constant and replicating it across the word. */
3099 #define SET_RATIO(speed) \
3100 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3102 /* STORE_BY_PIECES_P can be used when copying a constant string, but
3103 in that case each word takes 3 insns (lui, ori, sw), or more in
3104 64-bit mode, instead of 2 (lw, sw). For now we always fail this
3105 and let the move_by_pieces code copy the string from read-only
3106 memory. In the future, this could be tuned further for multi-issue
3107 CPUs that can issue stores down one pipe and arithmetic instructions
3108 down another; in that case, the lui/ori/sw combination would be a
3109 win for long enough strings. */
3111 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
3114 /* Since the bits of the _init and _fini function is spread across
3115 many object files, each potentially with its own GP, we must assume
3116 we need to load our GP. We don't preserve $gp or $ra, since each
3117 init/fini chunk is supposed to initialize $gp, and crti/crtn
3118 already take care of preserving $ra and, when appropriate, $gp. */
3119 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3120 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3121 asm (SECTION_OP "\n\
3127 jal " USER_LABEL_PREFIX #FUNC "\n\
3128 " TEXT_SECTION_ASM_OP);
3129 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3130 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3131 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3132 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3133 asm (SECTION_OP "\n\
3138 .cpsetup $31, $2, 1b\n\
3139 jal " USER_LABEL_PREFIX #FUNC "\n\
3140 " TEXT_SECTION_ASM_OP);
3145 #define HAVE_AS_TLS 0
3148 /* Return an asm string that atomically:
3150 - Compares memory reference %1 to register %2 and, if they are
3151 equal, changes %1 to %3.
3153 - Sets register %0 to the old value of memory reference %1.
3155 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
3156 and OP is the instruction that should be used to load %3 into a
3158 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
3160 "1:\tll" SUFFIX "\t%0,%1\n" \
3161 "\tbne\t%0,%z2,2f\n" \
3162 "\t" OP "\t%@,%3\n" \
3163 "\tsc" SUFFIX "\t%@,%1\n" \
3164 "\tbeq%?\t%@,%.,1b\n" \
3166 "\tsync%-%]%>%)\n" \
3169 /* Return an asm string that atomically:
3171 - Given that %2 contains a bit mask and %3 the inverted mask and
3172 that %4 and %5 have already been ANDed with %2.
3174 - Compares the bits in memory reference %1 selected by mask %2 to
3175 register %4 and, if they are equal, changes the selected bits
3178 - Sets register %0 to the old value of memory reference %1.
3180 OPS are the instructions needed to OR %5 with %@. */
3181 #define MIPS_COMPARE_AND_SWAP_12(OPS) \
3184 "\tand\t%@,%0,%2\n" \
3185 "\tbne\t%@,%z4,2f\n" \
3186 "\tand\t%@,%0,%3\n" \
3189 "\tbeq%?\t%@,%.,1b\n" \
3191 "\tsync%-%]%>%)\n" \
3194 #define MIPS_COMPARE_AND_SWAP_12_ZERO_OP ""
3195 #define MIPS_COMPARE_AND_SWAP_12_NONZERO_OP "\tor\t%@,%@,%5\n"
3198 /* Return an asm string that atomically:
3200 - Sets memory reference %0 to %0 INSN %1.
3202 SUFFIX is the suffix that should be added to "ll" and "sc"
3204 #define MIPS_SYNC_OP(SUFFIX, INSN) \
3206 "1:\tll" SUFFIX "\t%@,%0\n" \
3207 "\t" INSN "\t%@,%@,%1\n" \
3208 "\tsc" SUFFIX "\t%@,%0\n" \
3209 "\tbeq%?\t%@,%.,1b\n" \
3213 /* Return an asm string that atomically:
3215 - Given that %1 contains a bit mask and %2 the inverted mask and
3216 that %3 has already been ANDed with %1.
3218 - Sets the selected bits of memory reference %0 to %0 INSN %3.
3220 - Uses scratch register %4.
3222 AND_OP is an instruction done after INSN to mask INSN's result
3223 with the mask. For most operations, this is an AND with the
3224 inclusive mask (%1). For nand operations -- where the result of
3225 INSN is already correctly masked -- it instead performs a bitwise
3227 #define MIPS_SYNC_OP_12(INSN, AND_OP) \
3230 "\tand\t%@,%4,%2\n" \
3231 "\t" INSN "\t%4,%4,%z3\n" \
3233 "\tor\t%@,%@,%4\n" \
3235 "\tbeq%?\t%@,%.,1b\n" \
3239 #define MIPS_SYNC_OP_12_AND "\tand\t%4,%4,%1\n"
3240 #define MIPS_SYNC_OP_12_XOR "\txor\t%4,%4,%1\n"
3242 /* Return an asm string that atomically:
3244 - Given that %2 contains a bit mask and %3 the inverted mask and
3245 that %4 has already been ANDed with %2.
3247 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3249 - Sets %0 to the original value of %1.
3251 - Uses scratch register %5.
3253 AND_OP is an instruction done after INSN to mask INSN's result
3254 with the mask. For most operations, this is an AND with the
3255 inclusive mask (%1). For nand operations -- where the result of
3256 INSN is already correctly masked -- it instead performs a bitwise
3258 #define MIPS_SYNC_OLD_OP_12(INSN, AND_OP) \
3261 "\tand\t%@,%0,%3\n" \
3262 "\t" INSN "\t%5,%0,%z4\n" \
3264 "\tor\t%@,%@,%5\n" \
3266 "\tbeq%?\t%@,%.,1b\n" \
3270 #define MIPS_SYNC_OLD_OP_12_AND "\tand\t%5,%5,%2\n"
3271 #define MIPS_SYNC_OLD_OP_12_XOR "\txor\t%5,%5,%2\n"
3273 /* Return an asm string that atomically:
3275 - Given that %2 contains a bit mask and %3 the inverted mask and
3276 that %4 has already been ANDed with %2.
3278 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3280 - Sets %0 to the new value of %1.
3282 AND_OP is an instruction done after INSN to mask INSN's result
3283 with the mask. For most operations, this is an AND with the
3284 inclusive mask (%1). For nand operations -- where the result of
3285 INSN is already correctly masked -- it instead performs a bitwise
3287 #define MIPS_SYNC_NEW_OP_12(INSN, AND_OP) \
3290 "\tand\t%@,%0,%3\n" \
3291 "\t" INSN "\t%0,%0,%z4\n" \
3293 "\tor\t%@,%@,%0\n" \
3295 "\tbeq%?\t%@,%.,1b\n" \
3299 #define MIPS_SYNC_NEW_OP_12_AND "\tand\t%0,%0,%2\n"
3300 #define MIPS_SYNC_NEW_OP_12_XOR "\txor\t%0,%0,%2\n"
3302 /* Return an asm string that atomically:
3304 - Sets memory reference %1 to %1 INSN %2.
3306 - Sets register %0 to the old value of memory reference %1.
3308 SUFFIX is the suffix that should be added to "ll" and "sc"
3310 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
3312 "1:\tll" SUFFIX "\t%0,%1\n" \
3313 "\t" INSN "\t%@,%0,%2\n" \
3314 "\tsc" SUFFIX "\t%@,%1\n" \
3315 "\tbeq%?\t%@,%.,1b\n" \
3319 /* Return an asm string that atomically:
3321 - Sets memory reference %1 to %1 INSN %2.
3323 - Sets register %0 to the new value of memory reference %1.
3325 SUFFIX is the suffix that should be added to "ll" and "sc"
3327 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
3329 "1:\tll" SUFFIX "\t%0,%1\n" \
3330 "\t" INSN "\t%@,%0,%2\n" \
3331 "\tsc" SUFFIX "\t%@,%1\n" \
3332 "\tbeq%?\t%@,%.,1b%~\n" \
3333 "\t" INSN "\t%0,%0,%2\n" \
3336 /* Return an asm string that atomically:
3338 - Sets memory reference %0 to ~(%0 AND %1).
3340 SUFFIX is the suffix that should be added to "ll" and "sc"
3341 instructions. INSN is the and instruction needed to and a register
3343 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
3345 "1:\tll" SUFFIX "\t%@,%0\n" \
3346 "\t" INSN "\t%@,%@,%1\n" \
3347 "\tnor\t%@,%@,%.\n" \
3348 "\tsc" SUFFIX "\t%@,%0\n" \
3349 "\tbeq%?\t%@,%.,1b\n" \
3353 /* Return an asm string that atomically:
3355 - Sets memory reference %1 to ~(%1 AND %2).
3357 - Sets register %0 to the old value of memory reference %1.
3359 SUFFIX is the suffix that should be added to "ll" and "sc"
3360 instructions. INSN is the and instruction needed to and a register
3362 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
3364 "1:\tll" SUFFIX "\t%0,%1\n" \
3365 "\t" INSN "\t%@,%0,%2\n" \
3366 "\tnor\t%@,%@,%.\n" \
3367 "\tsc" SUFFIX "\t%@,%1\n" \
3368 "\tbeq%?\t%@,%.,1b\n" \
3372 /* Return an asm string that atomically:
3374 - Sets memory reference %1 to ~(%1 AND %2).
3376 - Sets register %0 to the new value of memory reference %1.
3378 SUFFIX is the suffix that should be added to "ll" and "sc"
3379 instructions. INSN is the and instruction needed to and a register
3381 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3383 "1:\tll" SUFFIX "\t%0,%1\n" \
3384 "\t" INSN "\t%0,%0,%2\n" \
3385 "\tnor\t%@,%0,%.\n" \
3386 "\tsc" SUFFIX "\t%@,%1\n" \
3387 "\tbeq%?\t%@,%.,1b%~\n" \
3388 "\tnor\t%0,%0,%.\n" \
3391 /* Return an asm string that atomically:
3393 - Sets memory reference %1 to %2.
3395 - Sets register %0 to the old value of memory reference %1.
3397 SUFFIX is the suffix that should be added to "ll" and "sc"
3398 instructions. OP is the and instruction that should be used to
3399 load %2 into a register. */
3400 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3402 "1:\tll" SUFFIX "\t%0,%1\n" \
3403 "\t" OP "\t%@,%2\n" \
3404 "\tsc" SUFFIX "\t%@,%1\n" \
3405 "\tbeq%?\t%@,%.,1b\n" \
3409 /* Return an asm string that atomically:
3411 - Given that %2 contains an inclusive mask, %3 and exclusive mask
3412 and %4 has already been ANDed with the inclusive mask.
3414 - Sets bits selected by the inclusive mask of memory reference %1
3417 - Sets register %0 to the old value of memory reference %1.
3419 OPS are the instructions needed to OR %4 with %@.
3421 Operand %2 is unused, but needed as to give the test_and_set_12
3422 insn the five operands expected by the expander. */
3423 #define MIPS_SYNC_EXCHANGE_12(OPS) \
3426 "\tand\t%@,%0,%3\n" \
3429 "\tbeq%?\t%@,%.,1b\n" \
3433 #define MIPS_SYNC_EXCHANGE_12_ZERO_OP ""
3434 #define MIPS_SYNC_EXCHANGE_12_NONZERO_OP "\tor\t%@,%@,%4\n"
3436 #ifndef USED_FOR_TARGET
3437 extern const enum reg_class mips_regno_to_class[];
3438 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3439 extern bool mips_print_operand_punct[256];
3440 extern const char *current_function_file; /* filename current function is in */
3441 extern int num_source_filenames; /* current .file # */
3442 extern int set_noreorder; /* # of nested .set noreorder's */
3443 extern int set_nomacro; /* # of nested .set nomacro's */
3444 extern int mips_dbx_regno[];
3445 extern int mips_dwarf_regno[];
3446 extern bool mips_split_p[];
3447 extern bool mips_split_hi_p[];
3448 extern GTY(()) rtx cmp_operands[2];
3449 extern enum processor_type mips_arch; /* which cpu to codegen for */
3450 extern enum processor_type mips_tune; /* which cpu to schedule for */
3451 extern int mips_isa; /* architectural level */
3452 extern int mips_abi; /* which ABI to use */
3453 extern const struct mips_cpu_info *mips_arch_info;
3454 extern const struct mips_cpu_info *mips_tune_info;
3455 extern const struct mips_rtx_cost_data *mips_cost;
3456 extern bool mips_base_mips16;
3457 extern enum mips_code_readable_setting mips_code_readable;
3460 /* Enable querying of DFA units. */
3461 #define CPU_UNITS_QUERY 1