1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* MIPS external variables defined in mips.c. */
29 /* Which processor to schedule for. Since there is no difference between
30 a R2000 and R3000 in terms of the scheduler, we collapse them into
31 just an R3000. The elements of the enumeration must match exactly
32 the cpu attribute in the mips.md machine description. */
61 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
62 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
63 to work on a 64 bit machine. */
71 /* Information about one recognized processor. Defined here for the
72 benefit of TARGET_CPU_CPP_BUILTINS. */
73 struct mips_cpu_info {
74 /* The 'canonical' name of the processor as far as GCC is concerned.
75 It's typically a manufacturer's prefix followed by a numerical
76 designation. It should be lower case. */
79 /* The internal processor number that most closely matches this
80 entry. Several processors can have the same value, if there's no
81 difference between them from GCC's point of view. */
82 enum processor_type cpu;
84 /* The ISA level that the processor implements. */
88 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
89 extern const char *current_function_file; /* filename current function is in */
90 extern int num_source_filenames; /* current .file # */
91 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
92 extern int sym_lineno; /* sgi next label # for each stmt */
93 extern int set_noreorder; /* # of nested .set noreorder's */
94 extern int set_nomacro; /* # of nested .set nomacro's */
95 extern int set_noat; /* # of nested .set noat's */
96 extern int set_volatile; /* # of nested .set volatile's */
97 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
98 extern int mips_dbx_regno[]; /* Map register # to debug register # */
99 extern GTY(()) rtx cmp_operands[2];
100 extern enum processor_type mips_arch; /* which cpu to codegen for */
101 extern enum processor_type mips_tune; /* which cpu to schedule for */
102 extern int mips_isa; /* architectural level */
103 extern int mips_abi; /* which ABI to use */
104 extern int mips16_hard_float; /* mips16 without -msoft-float */
105 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
106 extern const struct mips_cpu_info mips_cpu_info_table[];
107 extern const struct mips_cpu_info *mips_arch_info;
108 extern const struct mips_cpu_info *mips_tune_info;
110 /* Macros to silence warnings about numbers being signed in traditional
111 C and unsigned in ISO C when compiled on 32-bit hosts. */
113 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
114 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
115 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
118 /* Run-time compilation parameters selecting different hardware subsets. */
120 /* True if the call patterns should be split into a jalr followed by
121 an instruction to restore $gp. This is only ever true for SVR4 PIC,
122 in which $gp is call-clobbered. It is only safe to split the load
123 from the call when every use of $gp is explicit. */
125 #define TARGET_SPLIT_CALLS \
126 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
128 /* True if we can optimize sibling calls. For simplicity, we only
129 handle cases in which call_insn_operand will reject invalid
130 sibcall addresses. There are two cases in which this isn't true:
132 - TARGET_MIPS16. call_insn_operand accepts constant addresses
133 but there is no direct jump instruction. It isn't worth
134 using sibling calls in this case anyway; they would usually
135 be longer than normal calls.
137 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
138 accepts global constants, but "jr $25" is the only allowed
141 #define TARGET_SIBCALLS \
142 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
144 /* True if .gpword or .gpdword should be used for switch tables.
146 Although GAS does understand .gpdword, the SGI linker mishandles
147 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
148 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
149 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
151 /* Generate mips16 code */
152 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
154 /* Generic ISA defines. */
155 #define ISA_MIPS1 (mips_isa == 1)
156 #define ISA_MIPS2 (mips_isa == 2)
157 #define ISA_MIPS3 (mips_isa == 3)
158 #define ISA_MIPS4 (mips_isa == 4)
159 #define ISA_MIPS32 (mips_isa == 32)
160 #define ISA_MIPS32R2 (mips_isa == 33)
161 #define ISA_MIPS64 (mips_isa == 64)
163 /* Architecture target defines. */
164 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
165 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
166 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
167 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
168 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
169 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
170 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
171 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
172 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
173 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
175 /* Scheduling target defines. */
176 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
177 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
178 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
179 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
180 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
181 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
182 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
183 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
184 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
185 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
186 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
187 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
189 /* True if the pre-reload scheduler should try to create chains of
190 multiply-add or multiply-subtract instructions. For example,
198 t1 will have a higher priority than t2 and t3 will have a higher
199 priority than t4. However, before reload, there is no dependence
200 between t1 and t3, and they can often have similar priorities.
201 The scheduler will then tend to prefer:
208 which stops us from making full use of macc/madd-style instructions.
209 This sort of situation occurs frequently in Fourier transforms and
212 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
213 queue so that chained multiply-add and multiply-subtract instructions
214 appear ahead of any other instruction that is likely to clobber lo.
215 In the example above, if t2 and t3 become ready at the same time,
216 the code ensures that t2 is scheduled first.
218 Multiply-accumulate instructions are a bigger win for some targets
219 than others, so this macro is defined on an opt-in basis. */
220 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
224 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
225 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
227 /* IRIX specific stuff. */
228 #define TARGET_IRIX 0
229 #define TARGET_IRIX6 0
231 /* Define preprocessor macros for the -march and -mtune options.
232 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
233 processor. If INFO's canonical name is "foo", define PREFIX to
234 be "foo", and define an additional macro PREFIX_FOO. */
235 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
240 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
241 for (p = macro; *p != 0; p++) \
244 builtin_define (macro); \
245 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
250 /* Target CPU builtins. */
251 #define TARGET_CPU_CPP_BUILTINS() \
254 /* Everyone but IRIX defines this to mips. */ \
256 builtin_assert ("machine=mips"); \
258 builtin_assert ("cpu=mips"); \
259 builtin_define ("__mips__"); \
260 builtin_define ("_mips"); \
262 /* We do this here because __mips is defined below \
263 and so we can't use builtin_define_std. */ \
265 builtin_define ("mips"); \
268 builtin_define ("__mips64"); \
272 /* Treat _R3000 and _R4000 like register-size \
273 defines, which is how they've historically \
277 builtin_define_std ("R4000"); \
278 builtin_define ("_R4000"); \
282 builtin_define_std ("R3000"); \
283 builtin_define ("_R3000"); \
286 if (TARGET_FLOAT64) \
287 builtin_define ("__mips_fpr=64"); \
289 builtin_define ("__mips_fpr=32"); \
292 builtin_define ("__mips16"); \
295 builtin_define ("__mips3d"); \
297 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
298 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
302 builtin_define ("__mips=1"); \
303 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
305 else if (ISA_MIPS2) \
307 builtin_define ("__mips=2"); \
308 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
310 else if (ISA_MIPS3) \
312 builtin_define ("__mips=3"); \
313 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
315 else if (ISA_MIPS4) \
317 builtin_define ("__mips=4"); \
318 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
320 else if (ISA_MIPS32) \
322 builtin_define ("__mips=32"); \
323 builtin_define ("__mips_isa_rev=1"); \
324 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
326 else if (ISA_MIPS32R2) \
328 builtin_define ("__mips=32"); \
329 builtin_define ("__mips_isa_rev=2"); \
330 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
332 else if (ISA_MIPS64) \
334 builtin_define ("__mips=64"); \
335 builtin_define ("__mips_isa_rev=1"); \
336 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
339 if (TARGET_HARD_FLOAT) \
340 builtin_define ("__mips_hard_float"); \
341 else if (TARGET_SOFT_FLOAT) \
342 builtin_define ("__mips_soft_float"); \
344 if (TARGET_SINGLE_FLOAT) \
345 builtin_define ("__mips_single_float"); \
347 if (TARGET_PAIRED_SINGLE_FLOAT) \
348 builtin_define ("__mips_paired_single_float"); \
350 if (TARGET_BIG_ENDIAN) \
352 builtin_define_std ("MIPSEB"); \
353 builtin_define ("_MIPSEB"); \
357 builtin_define_std ("MIPSEL"); \
358 builtin_define ("_MIPSEL"); \
361 /* Macros dependent on the C dialect. */ \
362 if (preprocessing_asm_p ()) \
364 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
365 builtin_define ("_LANGUAGE_ASSEMBLY"); \
367 else if (c_dialect_cxx ()) \
369 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
370 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
371 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
375 builtin_define_std ("LANGUAGE_C"); \
376 builtin_define ("_LANGUAGE_C"); \
378 if (c_dialect_objc ()) \
380 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
381 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
382 /* Bizarre, but needed at least for Irix. */ \
383 builtin_define_std ("LANGUAGE_C"); \
384 builtin_define ("_LANGUAGE_C"); \
387 if (mips_abi == ABI_EABI) \
388 builtin_define ("__mips_eabi"); \
392 /* Default target_flags if no switches are specified */
394 #ifndef TARGET_DEFAULT
395 #define TARGET_DEFAULT 0
398 #ifndef TARGET_CPU_DEFAULT
399 #define TARGET_CPU_DEFAULT 0
402 #ifndef TARGET_ENDIAN_DEFAULT
403 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
406 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
407 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
410 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
411 #ifndef MIPS_ISA_DEFAULT
412 #ifndef MIPS_CPU_STRING_DEFAULT
413 #define MIPS_CPU_STRING_DEFAULT "from-abi"
419 /* Make this compile time constant for libgcc2 */
421 #define TARGET_64BIT 1
423 #define TARGET_64BIT 0
425 #endif /* IN_LIBGCC2 */
427 #ifndef MULTILIB_ENDIAN_DEFAULT
428 #if TARGET_ENDIAN_DEFAULT == 0
429 #define MULTILIB_ENDIAN_DEFAULT "EL"
431 #define MULTILIB_ENDIAN_DEFAULT "EB"
435 #ifndef MULTILIB_ISA_DEFAULT
436 # if MIPS_ISA_DEFAULT == 1
437 # define MULTILIB_ISA_DEFAULT "mips1"
439 # if MIPS_ISA_DEFAULT == 2
440 # define MULTILIB_ISA_DEFAULT "mips2"
442 # if MIPS_ISA_DEFAULT == 3
443 # define MULTILIB_ISA_DEFAULT "mips3"
445 # if MIPS_ISA_DEFAULT == 4
446 # define MULTILIB_ISA_DEFAULT "mips4"
448 # if MIPS_ISA_DEFAULT == 32
449 # define MULTILIB_ISA_DEFAULT "mips32"
451 # if MIPS_ISA_DEFAULT == 33
452 # define MULTILIB_ISA_DEFAULT "mips32r2"
454 # if MIPS_ISA_DEFAULT == 64
455 # define MULTILIB_ISA_DEFAULT "mips64"
457 # define MULTILIB_ISA_DEFAULT "mips1"
467 #ifndef MULTILIB_DEFAULTS
468 #define MULTILIB_DEFAULTS \
469 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
472 /* We must pass -EL to the linker by default for little endian embedded
473 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
474 linker will default to using big-endian output files. The OUTPUT_FORMAT
475 line must be in the linker script, otherwise -EB/-EL will not work. */
478 #if TARGET_ENDIAN_DEFAULT == 0
479 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
481 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
485 /* Support for a compile-time default CPU, et cetera. The rules are:
486 --with-arch is ignored if -march is specified or a -mips is specified
487 (other than -mips16).
488 --with-tune is ignored if -mtune is specified.
489 --with-abi is ignored if -mabi is specified.
490 --with-float is ignored if -mhard-float or -msoft-float are
492 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
494 #define OPTION_DEFAULT_SPECS \
495 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
496 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
497 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
498 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
499 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
502 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
503 && ISA_HAS_COND_TRAP)
505 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
509 /* Generate three-operand multiply instructions for SImode. */
510 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
521 /* Generate three-operand multiply instructions for DImode. */
522 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
525 /* True if the ABI can only work with 64-bit integer registers. We
526 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
527 otherwise floating-point registers must also be 64-bit. */
528 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
530 /* Likewise for 32-bit regs. */
531 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
533 /* True if symbols are 64 bits wide. At present, n64 is the only
534 ABI for which this is true. */
535 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
537 /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
538 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
542 /* ISA has branch likely instructions (e.g. mips2). */
543 /* Disable branchlikely for tx39 until compare rewrite. They haven't
544 been generated up to this point. */
545 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
547 /* ISA has the conditional move instructions introduced in mips4. */
548 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
552 && !TARGET_MIPS5500 \
555 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
556 branch on CC, and move (both FP and non-FP) on CC. */
557 #define ISA_HAS_8CC (ISA_MIPS4 \
562 /* This is a catch all for other mips4 instructions: indexed load, the
563 FP madd and msub instructions, and the FP recip and recip sqrt
565 #define ISA_HAS_FP4 ((ISA_MIPS4 \
569 /* ISA has conditional trap instructions. */
570 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
573 /* ISA has integer multiply-accumulate instructions, madd and msub. */
574 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
579 /* ISA has floating-point nmadd and nmsub instructions. */
580 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
582 && (!TARGET_MIPS5400 || TARGET_MAD) \
585 /* ISA has count leading zeroes/ones instruction (not implemented). */
586 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
591 /* ISA has double-word count leading zeroes/ones instruction (not
593 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
596 /* ISA has three operand multiply instructions that put
597 the high part in an accumulator: mulhi or mulhiu. */
598 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
603 /* ISA has three operand multiply instructions that
604 negates the result and puts the result in an accumulator. */
605 #define ISA_HAS_MULS (TARGET_MIPS5400 \
610 /* ISA has three operand multiply instructions that subtracts the
611 result from a 4th operand and puts the result in an accumulator. */
612 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
616 /* ISA has three operand multiply instructions that the result
617 from a 4th operand and puts the result in an accumulator. */
618 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
619 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
625 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
626 #define ISA_HAS_MACCHI (!TARGET_MIPS16 \
627 && (TARGET_MIPS4120 \
630 /* ISA has 32-bit rotate right instruction. */
631 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
638 /* ISA has 64-bit rotate right instruction. */
639 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
641 && (TARGET_MIPS5400 \
646 /* ISA has data prefetch instructions. This controls use of 'pref'. */
647 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
653 /* ISA has data indexed prefetch instructions. This controls use of
654 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
655 (prefx is a cop1x instruction, so can only be used if FP is
657 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
661 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
662 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
663 also requires TARGET_DOUBLE_FLOAT. */
664 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
666 /* ISA includes the MIPS32r2 seb and seh instructions. */
667 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
671 /* True if the result of a load is not available to the next instruction.
672 A nop will then be needed between instructions like "lw $4,..."
673 and "addiu $4,$4,1". */
674 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
675 && !TARGET_MIPS3900 \
678 /* Likewise mtc1 and mfc1. */
679 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
681 /* Likewise floating-point comparisons. */
682 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
684 /* True if mflo and mfhi can be immediately followed by instructions
685 which write to the HI and LO registers.
687 According to MIPS specifications, MIPS ISAs I, II, and III need
688 (at least) two instructions between the reads of HI/LO and
689 instructions which write them, and later ISAs do not. Contradicting
690 the MIPS specifications, some MIPS IV processor user manuals (e.g.
691 the UM for the NEC Vr5000) document needing the instructions between
692 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
693 MIPS64 and later ISAs to have the interlocks, plus any specific
694 earlier-ISA CPUs for which CPU documentation declares that the
695 instructions are really interlocked. */
696 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
701 /* Add -G xx support. */
703 #undef SWITCH_TAKES_ARG
704 #define SWITCH_TAKES_ARG(CHAR) \
705 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
707 #define OVERRIDE_OPTIONS override_options ()
709 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
711 /* Show we can debug even without a frame pointer. */
712 #define CAN_DEBUG_WITHOUT_FP
714 /* Tell collect what flags to pass to nm. */
716 #define NM_FLAGS "-Bn"
720 #ifndef MIPS_ABI_DEFAULT
721 #define MIPS_ABI_DEFAULT ABI_32
724 /* Use the most portable ABI flag for the ASM specs. */
726 #if MIPS_ABI_DEFAULT == ABI_32
727 #define MULTILIB_ABI_DEFAULT "mabi=32"
730 #if MIPS_ABI_DEFAULT == ABI_O64
731 #define MULTILIB_ABI_DEFAULT "mabi=o64"
734 #if MIPS_ABI_DEFAULT == ABI_N32
735 #define MULTILIB_ABI_DEFAULT "mabi=n32"
738 #if MIPS_ABI_DEFAULT == ABI_64
739 #define MULTILIB_ABI_DEFAULT "mabi=64"
742 #if MIPS_ABI_DEFAULT == ABI_EABI
743 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
746 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
747 to the assembler. It may be overridden by subtargets. */
748 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
749 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
751 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
754 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
755 the assembler. It may be overridden by subtargets.
757 Beginning with gas 2.13, -mdebug must be passed to correctly handle
758 COFF debugging info. */
760 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
761 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
762 %{g} %{g0} %{g1} %{g2} %{g3} \
763 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
764 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
765 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
766 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
767 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
770 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
771 overridden by subtargets. */
773 #ifndef SUBTARGET_ASM_SPEC
774 #define SUBTARGET_ASM_SPEC ""
779 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
780 %{mips32} %{mips32r2} %{mips64} \
781 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
783 %{mfix-vr4120} %{mfix-vr4130} \
784 %(subtarget_asm_optimizing_spec) \
785 %(subtarget_asm_debugging_spec) \
786 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
787 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
788 %{msym32} %{mno-sym32} \
790 %(subtarget_asm_spec)"
792 /* Extra switches sometimes passed to the linker. */
793 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
794 will interpret it as a -b option. */
799 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
800 %{bestGnum} %{shared} %{non_shared}"
801 #endif /* LINK_SPEC defined */
804 /* Specs for the compiler proper */
806 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
807 overridden by subtargets. */
808 #ifndef SUBTARGET_CC1_SPEC
809 #define SUBTARGET_CC1_SPEC ""
812 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
816 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
817 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
819 %(subtarget_cc1_spec)"
822 /* Preprocessor specs. */
824 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
825 overridden by subtargets. */
826 #ifndef SUBTARGET_CPP_SPEC
827 #define SUBTARGET_CPP_SPEC ""
830 #define CPP_SPEC "%(subtarget_cpp_spec)"
832 /* This macro defines names of additional specifications to put in the specs
833 that can be used in various specifications like CC1_SPEC. Its definition
834 is an initializer with a subgrouping for each command option.
836 Each subgrouping contains a string constant, that defines the
837 specification name, and a string constant that used by the GCC driver
840 Do not define this macro if it does not need to do anything. */
842 #define EXTRA_SPECS \
843 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
844 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
845 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
846 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
847 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
848 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
849 { "endian_spec", ENDIAN_SPEC }, \
850 SUBTARGET_EXTRA_SPECS
852 #ifndef SUBTARGET_EXTRA_SPECS
853 #define SUBTARGET_EXTRA_SPECS
856 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
857 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
858 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
860 #ifndef PREFERRED_DEBUGGING_TYPE
861 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
864 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
866 /* By default, turn on GDB extensions. */
867 #define DEFAULT_GDB_EXTENSIONS 1
869 /* Local compiler-generated symbols must have a prefix that the assembler
870 understands. By default, this is $, although some targets (e.g.,
871 NetBSD-ELF) need to override this. */
873 #ifndef LOCAL_LABEL_PREFIX
874 #define LOCAL_LABEL_PREFIX "$"
877 /* By default on the mips, external symbols do not have an underscore
878 prepended, but some targets (e.g., NetBSD) require this. */
880 #ifndef USER_LABEL_PREFIX
881 #define USER_LABEL_PREFIX ""
884 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
885 since the length can run past this up to a continuation point. */
886 #undef DBX_CONTIN_LENGTH
887 #define DBX_CONTIN_LENGTH 1500
889 /* How to renumber registers for dbx and gdb. */
890 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
892 /* The mapping from gcc register number to DWARF 2 CFA column number. */
893 #define DWARF_FRAME_REGNUM(REG) (REG)
895 /* The DWARF 2 CFA column which tracks the return address. */
896 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
898 /* The DWARF 2 CFA column which tracks the return address from a
899 signal handler context. */
900 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
902 /* Before the prologue, RA lives in r31. */
903 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
905 /* Describe how we implement __builtin_eh_return. */
906 #define EH_RETURN_DATA_REGNO(N) \
907 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
909 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
911 /* Offsets recorded in opcodes are a multiple of this alignment factor.
912 The default for this in 64-bit mode is 8, which causes problems with
913 SFmode register saves. */
914 #define DWARF_CIE_DATA_ALIGNMENT -4
916 /* Correct the offset of automatic variables and arguments. Note that
917 the MIPS debug format wants all automatic variables and arguments
918 to be in terms of the virtual frame pointer (stack pointer before
919 any adjustment in the function), while the MIPS 3.0 linker wants
920 the frame pointer to be the stack pointer after the initial
923 #define DEBUGGER_AUTO_OFFSET(X) \
924 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
925 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
926 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
928 /* Target machine storage layout */
930 #define BITS_BIG_ENDIAN 0
931 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
932 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
934 /* Define this to set the endianness to use in libgcc2.c, which can
935 not depend on target_flags. */
936 #if !defined(MIPSEL) && !defined(__MIPSEL__)
937 #define LIBGCC2_WORDS_BIG_ENDIAN 1
939 #define LIBGCC2_WORDS_BIG_ENDIAN 0
942 #define MAX_BITS_PER_WORD 64
944 /* Width of a word, in units (bytes). */
945 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
946 #define MIN_UNITS_PER_WORD 4
948 /* For MIPS, width of a floating point register. */
949 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
951 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
952 the next available register. */
953 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
955 /* The largest size of value that can be held in floating-point
956 registers and moved with a single instruction. */
957 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
959 /* The largest size of value that can be held in floating-point
961 #define UNITS_PER_FPVALUE \
962 (TARGET_SOFT_FLOAT ? 0 \
963 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
964 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
966 /* The number of bytes in a double. */
967 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
969 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : 0)
971 /* Set the sizes of the core types. */
972 #define SHORT_TYPE_SIZE 16
973 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
974 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
975 #define LONG_LONG_TYPE_SIZE 64
977 #define FLOAT_TYPE_SIZE 32
978 #define DOUBLE_TYPE_SIZE 64
979 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
981 /* long double is not a fixed mode, but the idea is that, if we
982 support long double, we also want a 128-bit integer type. */
983 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
986 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
987 || (defined _ABI64 && _MIPS_SIM == _ABI64)
988 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
990 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
994 /* Width in bits of a pointer. */
996 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
999 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1000 #define PARM_BOUNDARY BITS_PER_WORD
1002 /* Allocation boundary (in *bits*) for the code of a function. */
1003 #define FUNCTION_BOUNDARY 32
1005 /* Alignment of field after `int : 0' in a structure. */
1006 #define EMPTY_FIELD_BOUNDARY 32
1008 /* Every structure's size must be a multiple of this. */
1009 /* 8 is observed right on a DECstation and on riscos 4.02. */
1010 #define STRUCTURE_SIZE_BOUNDARY 8
1012 /* There is no point aligning anything to a rounder boundary than this. */
1013 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1015 /* All accesses must be aligned. */
1016 #define STRICT_ALIGNMENT 1
1018 /* Define this if you wish to imitate the way many other C compilers
1019 handle alignment of bitfields and the structures that contain
1022 The behavior is that the type written for a bit-field (`int',
1023 `short', or other integer type) imposes an alignment for the
1024 entire structure, as if the structure really did contain an
1025 ordinary field of that type. In addition, the bit-field is placed
1026 within the structure so that it would fit within such a field,
1027 not crossing a boundary for it.
1029 Thus, on most machines, a bit-field whose type is written as `int'
1030 would not cross a four-byte boundary, and would force four-byte
1031 alignment for the whole structure. (The alignment used may not
1032 be four bytes; it is controlled by the other alignment
1035 If the macro is defined, its definition should be a C expression;
1036 a nonzero value for the expression enables this behavior. */
1038 #define PCC_BITFIELD_TYPE_MATTERS 1
1040 /* If defined, a C expression to compute the alignment given to a
1041 constant that is being placed in memory. CONSTANT is the constant
1042 and ALIGN is the alignment that the object would ordinarily have.
1043 The value of this macro is used instead of that alignment to align
1046 If this macro is not defined, then ALIGN is used.
1048 The typical use of this macro is to increase alignment for string
1049 constants to be word aligned so that `strcpy' calls that copy
1050 constants can be done inline. */
1052 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1053 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1054 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1056 /* If defined, a C expression to compute the alignment for a static
1057 variable. TYPE is the data type, and ALIGN is the alignment that
1058 the object would ordinarily have. The value of this macro is used
1059 instead of that alignment to align the object.
1061 If this macro is not defined, then ALIGN is used.
1063 One use of this macro is to increase alignment of medium-size
1064 data to make it all fit in fewer cache lines. Another is to
1065 cause character arrays to be word-aligned so that `strcpy' calls
1066 that copy constants to character arrays can be done inline. */
1068 #undef DATA_ALIGNMENT
1069 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1070 ((((ALIGN) < BITS_PER_WORD) \
1071 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1072 || TREE_CODE (TYPE) == UNION_TYPE \
1073 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1076 #define PAD_VARARGS_DOWN \
1077 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1079 /* Define if operations between registers always perform the operation
1080 on the full register even if a narrower mode is specified. */
1081 #define WORD_REGISTER_OPERATIONS
1083 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1084 moves. All other references are zero extended. */
1085 #define LOAD_EXTEND_OP(MODE) \
1086 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1087 ? SIGN_EXTEND : ZERO_EXTEND)
1089 /* Define this macro if it is advisable to hold scalars in registers
1090 in a wider mode than that declared by the program. In such cases,
1091 the value is constrained to be within the bounds of the declared
1092 type, but kept valid in the wider mode. The signedness of the
1093 extension may differ from that of the type. */
1095 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1096 if (GET_MODE_CLASS (MODE) == MODE_INT \
1097 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1099 if ((MODE) == SImode) \
1104 /* Define if loading short immediate values into registers sign extends. */
1105 #define SHORT_IMMEDIATES_SIGN_EXTEND
1107 /* Standard register usage. */
1109 /* Number of hardware registers. We have:
1111 - 32 integer registers
1112 - 32 floating point registers
1113 - 8 condition code registers
1114 - 2 accumulator registers (hi and lo)
1115 - 32 registers each for coprocessors 0, 2 and 3
1117 - ARG_POINTER_REGNUM
1118 - FRAME_POINTER_REGNUM
1119 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1120 - 3 dummy entries that were used at various times in the past. */
1122 #define FIRST_PSEUDO_REGISTER 176
1124 /* By default, fix the kernel registers ($26 and $27), the global
1125 pointer ($28) and the stack pointer ($29). This can change
1126 depending on the command-line options.
1128 Regarding coprocessor registers: without evidence to the contrary,
1129 it's best to assume that each coprocessor register has a unique
1130 use. This can be overridden, in, e.g., override_options() or
1131 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1132 for a particular target. */
1134 #define FIXED_REGISTERS \
1136 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1137 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1138 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1139 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1140 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1141 /* COP0 registers */ \
1142 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1143 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1144 /* COP2 registers */ \
1145 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1146 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1147 /* COP3 registers */ \
1148 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1149 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1153 /* Set up this array for o32 by default.
1155 Note that we don't mark $31 as a call-clobbered register. The idea is
1156 that it's really the call instructions themselves which clobber $31.
1157 We don't care what the called function does with it afterwards.
1159 This approach makes it easier to implement sibcalls. Unlike normal
1160 calls, sibcalls don't clobber $31, so the register reaches the
1161 called function in tact. EPILOGUE_USES says that $31 is useful
1162 to the called function. */
1164 #define CALL_USED_REGISTERS \
1166 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1167 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1168 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1169 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1170 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1171 /* COP0 registers */ \
1172 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1173 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1174 /* COP2 registers */ \
1175 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1176 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1177 /* COP3 registers */ \
1178 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1179 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1183 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1185 #define CALL_REALLY_USED_REGISTERS \
1186 { /* General registers. */ \
1187 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1188 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1189 /* Floating-point registers. */ \
1190 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1191 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1193 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1194 /* COP0 registers */ \
1195 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1196 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1197 /* COP2 registers */ \
1198 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1199 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1200 /* COP3 registers */ \
1201 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1202 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1205 /* Internal macros to classify a register number as to whether it's a
1206 general purpose register, a floating point register, a
1207 multiply/divide register, or a status register. */
1209 #define GP_REG_FIRST 0
1210 #define GP_REG_LAST 31
1211 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1212 #define GP_DBX_FIRST 0
1214 #define FP_REG_FIRST 32
1215 #define FP_REG_LAST 63
1216 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1217 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1219 #define MD_REG_FIRST 64
1220 #define MD_REG_LAST 65
1221 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1222 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1224 #define ST_REG_FIRST 67
1225 #define ST_REG_LAST 74
1226 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1229 /* FIXME: renumber. */
1230 #define COP0_REG_FIRST 80
1231 #define COP0_REG_LAST 111
1232 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1234 #define COP2_REG_FIRST 112
1235 #define COP2_REG_LAST 143
1236 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1238 #define COP3_REG_FIRST 144
1239 #define COP3_REG_LAST 175
1240 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1241 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1242 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1244 #define AT_REGNUM (GP_REG_FIRST + 1)
1245 #define HI_REGNUM (MD_REG_FIRST + 0)
1246 #define LO_REGNUM (MD_REG_FIRST + 1)
1248 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1249 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1250 should be used instead. */
1251 #define FPSW_REGNUM ST_REG_FIRST
1253 #define GP_REG_P(REGNO) \
1254 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1255 #define M16_REG_P(REGNO) \
1256 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1257 #define FP_REG_P(REGNO) \
1258 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1259 #define MD_REG_P(REGNO) \
1260 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1261 #define ST_REG_P(REGNO) \
1262 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1263 #define COP0_REG_P(REGNO) \
1264 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1265 #define COP2_REG_P(REGNO) \
1266 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1267 #define COP3_REG_P(REGNO) \
1268 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1269 #define ALL_COP_REG_P(REGNO) \
1270 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1272 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1274 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1275 to initialize the mips16 gp pseudo register. */
1276 #define CONST_GP_P(X) \
1277 (GET_CODE (X) == CONST \
1278 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1279 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1281 /* Return coprocessor number from register number. */
1283 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1284 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1285 : COP3_REG_P (REGNO) ? '3' : '?')
1288 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1290 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1291 array built in override_options. Because machmodes.h is not yet
1292 included before this file is processed, the MODE bound can't be
1295 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1297 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1298 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1300 /* Value is 1 if it is a good idea to tie two pseudo registers
1301 when one has mode MODE1 and one has mode MODE2.
1302 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1303 for any hard reg, then this must be 0 for correct output. */
1304 #define MODES_TIEABLE_P(MODE1, MODE2) \
1305 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1306 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1307 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1308 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1310 /* Register to use for pushing function arguments. */
1311 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1313 /* These two registers don't really exist: they get eliminated to either
1314 the stack or hard frame pointer. */
1315 #define ARG_POINTER_REGNUM 77
1316 #define FRAME_POINTER_REGNUM 78
1318 /* $30 is not available on the mips16, so we use $17 as the frame
1320 #define HARD_FRAME_POINTER_REGNUM \
1321 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1323 /* Value should be nonzero if functions must have frame pointers.
1324 Zero means the frame pointer need not be set up (and parms
1325 may be accessed via the stack pointer) in functions that seem suitable.
1326 This is computed in `reload', in reload1.c. */
1327 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1329 /* Register in which static-chain is passed to a function. */
1330 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1332 /* Registers used as temporaries in prologue/epilogue code. If we're
1333 generating mips16 code, these registers must come from the core set
1334 of 8. The prologue register mustn't conflict with any incoming
1335 arguments, the static chain pointer, or the frame pointer. The
1336 epilogue temporary mustn't conflict with the return registers, the
1337 frame pointer, the EH stack adjustment, or the EH data registers. */
1339 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1340 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1342 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1343 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1345 /* Define this macro if it is as good or better to call a constant
1346 function address than to call an address kept in a register. */
1347 #define NO_FUNCTION_CSE 1
1349 /* The ABI-defined global pointer. Sometimes we use a different
1350 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1351 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1353 /* We normally use $28 as the global pointer. However, when generating
1354 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1355 register instead. They can then avoid saving and restoring $28
1356 and perhaps avoid using a frame at all.
1358 When a leaf function uses something other than $28, mips_expand_prologue
1359 will modify pic_offset_table_rtx in place. Take the register number
1360 from there after reload. */
1361 #define PIC_OFFSET_TABLE_REGNUM \
1362 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1364 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1366 /* Define the classes of registers for register constraints in the
1367 machine description. Also define ranges of constants.
1369 One of the classes must always be named ALL_REGS and include all hard regs.
1370 If there is more than one class, another class must be named NO_REGS
1371 and contain no registers.
1373 The name GENERAL_REGS must be the name of a class (or an alias for
1374 another name such as ALL_REGS). This is the class of registers
1375 that is allowed by "g" or "r" in a register constraint.
1376 Also, registers outside this class are allocated only when
1377 instructions express preferences for them.
1379 The classes must be numbered in nondecreasing order; that is,
1380 a larger-numbered class must never be contained completely
1381 in a smaller-numbered class.
1383 For any two classes, it is very desirable that there be another
1384 class that represents their union. */
1388 NO_REGS, /* no registers in set */
1389 M16_NA_REGS, /* mips16 regs not used to pass args */
1390 M16_REGS, /* mips16 directly accessible registers */
1391 T_REG, /* mips16 T register ($24) */
1392 M16_T_REGS, /* mips16 registers plus T register */
1393 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1394 V1_REG, /* Register $v1 ($3) used for TLS access. */
1395 LEA_REGS, /* Every GPR except $25 */
1396 GR_REGS, /* integer registers */
1397 FP_REGS, /* floating point registers */
1398 HI_REG, /* hi register */
1399 LO_REG, /* lo register */
1400 MD_REGS, /* multiply/divide registers (hi/lo) */
1401 COP0_REGS, /* generic coprocessor classes */
1404 HI_AND_GR_REGS, /* union classes */
1411 ALL_COP_AND_GR_REGS,
1412 ST_REGS, /* status registers (fp status) */
1413 ALL_REGS, /* all registers */
1414 LIM_REG_CLASSES /* max value + 1 */
1417 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1419 #define GENERAL_REGS GR_REGS
1421 /* An initializer containing the names of the register classes as C
1422 string constants. These names are used in writing some of the
1425 #define REG_CLASS_NAMES \
1432 "PIC_FN_ADDR_REG", \
1440 /* coprocessor registers */ \
1447 "COP0_AND_GR_REGS", \
1448 "COP2_AND_GR_REGS", \
1449 "COP3_AND_GR_REGS", \
1451 "ALL_COP_AND_GR_REGS", \
1456 /* An initializer containing the contents of the register classes,
1457 as integers which are bit masks. The Nth integer specifies the
1458 contents of class N. The way the integer MASK is interpreted is
1459 that register R is in the class if `MASK & (1 << R)' is 1.
1461 When the machine has more than 32 registers, an integer does not
1462 suffice. Then the integers are replaced by sub-initializers,
1463 braced groupings containing several integers. Each
1464 sub-initializer must be suitable as an initializer for the type
1465 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1467 #define REG_CLASS_CONTENTS \
1469 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1470 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1471 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1472 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1473 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1474 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1475 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1476 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1477 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1478 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1479 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1480 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1481 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1482 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1483 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1484 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1485 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1486 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1487 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1488 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1489 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1490 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1491 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1492 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1493 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1494 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1498 /* A C expression whose value is a register class containing hard
1499 register REGNO. In general there is more that one such class;
1500 choose a class which is "minimal", meaning that no smaller class
1501 also contains the register. */
1503 extern const enum reg_class mips_regno_to_class[];
1505 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1507 /* A macro whose definition is the name of the class to which a
1508 valid base register must belong. A base register is one used in
1509 an address which is the register value plus a displacement. */
1511 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1513 /* A macro whose definition is the name of the class to which a
1514 valid index register must belong. An index register is one used
1515 in an address where its value is either multiplied by a scale
1516 factor or added to another register (as well as added to a
1519 #define INDEX_REG_CLASS NO_REGS
1521 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1522 registers explicitly used in the rtl to be used as spill registers
1523 but prevents the compiler from extending the lifetime of these
1526 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1528 /* This macro is used later on in the file. */
1529 #define GR_REG_CLASS_P(CLASS) \
1530 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1531 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1532 || (CLASS) == V1_REG \
1533 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1535 /* This macro is also used later on in the file. */
1536 #define COP_REG_CLASS_P(CLASS) \
1537 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1539 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1540 is the default value (allocate the registers in numeric order). We
1541 define it just so that we can override it for the mips16 target in
1542 ORDER_REGS_FOR_LOCAL_ALLOC. */
1544 #define REG_ALLOC_ORDER \
1545 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1546 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1547 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1548 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1549 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1550 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1551 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1552 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1553 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1554 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1555 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1558 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1559 to be rearranged based on a particular function. On the mips16, we
1560 want to allocate $24 (T_REG) before other registers for
1561 instructions for which it is possible. */
1563 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1565 /* REGISTER AND CONSTANT CLASSES */
1567 /* Get reg_class from a letter such as appears in the machine
1570 DEFINED REGISTER CLASSES:
1572 'd' General (aka integer) registers
1573 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1574 'y' General registers (in both mips16 and non mips16 mode)
1575 'e' Effective address registers (general registers except $25)
1576 't' mips16 temporary register ($24)
1577 'f' Floating point registers
1581 'x' Multiply/divide registers
1582 'z' FP Status register
1586 'b' All registers */
1588 extern enum reg_class mips_char_to_class[256];
1590 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1592 /* True if VALUE is a signed 16-bit number. */
1594 #define SMALL_OPERAND(VALUE) \
1595 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1597 /* True if VALUE is an unsigned 16-bit number. */
1599 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1600 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1602 /* True if VALUE can be loaded into a register using LUI. */
1604 #define LUI_OPERAND(VALUE) \
1605 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1606 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1608 /* Return a value X with the low 16 bits clear, and such that
1609 VALUE - X is a signed 16-bit value. */
1611 #define CONST_HIGH_PART(VALUE) \
1612 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1614 #define CONST_LOW_PART(VALUE) \
1615 ((VALUE) - CONST_HIGH_PART (VALUE))
1617 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1618 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1619 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1621 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1622 string can be used to stand for particular ranges of immediate
1623 operands. This macro defines what the ranges are. C is the
1624 letter, and VALUE is a constant value. Return 1 if VALUE is
1625 in the range specified by C. */
1629 `I' is used for the range of constants an arithmetic insn can
1630 actually contain (16 bits signed integers).
1632 `J' is used for the range which is just zero (i.e., $r0).
1634 `K' is used for the range of constants a logical insn can actually
1635 contain (16 bit zero-extended integers).
1637 `L' is used for the range of constants that be loaded with lui
1638 (i.e., the bottom 16 bits are zero).
1640 `M' is used for the range of constants that take two words to load
1641 (i.e., not matched by `I', `K', and `L').
1643 `N' is used for negative 16 bit constants other than -65536.
1645 `O' is a 15 bit signed integer.
1647 `P' is used for positive 16 bit constants. */
1649 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1650 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
1651 : (C) == 'J' ? ((VALUE) == 0) \
1652 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
1653 : (C) == 'L' ? LUI_OPERAND (VALUE) \
1654 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
1655 && !SMALL_OPERAND_UNSIGNED (VALUE) \
1656 && !LUI_OPERAND (VALUE)) \
1657 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1658 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1659 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1662 /* Similar, but for floating constants, and defining letters G and H.
1663 Here VALUE is the CONST_DOUBLE rtx itself. */
1667 'G' : Floating point 0 */
1669 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1671 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1673 /* Letters in the range `Q' through `U' may be defined in a
1674 machine-dependent fashion to stand for arbitrary operand types.
1675 The machine description macro `EXTRA_CONSTRAINT' is passed the
1676 operand as its first argument and the constraint letter as its
1679 `Q' is for signed 16-bit constants.
1680 `R' is for single-instruction memory references. Note that this
1681 constraint has often been used in linux and glibc code.
1682 `S' is for legitimate constant call addresses.
1683 `T' is for constant move_operands that cannot be safely loaded into $25.
1684 `U' is for constant move_operands that can be safely loaded into $25.
1685 `W' is for memory references that are based on a member of BASE_REG_CLASS.
1686 This is true for all non-mips16 references (although it can sometimes
1687 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
1688 stack and constant-pool references.
1689 `YG' is for 0 valued vector constants. */
1691 #define EXTRA_CONSTRAINT_Y(OP,STR) \
1692 (((STR)[1] == 'G') ? (GET_CODE (OP) == CONST_VECTOR \
1693 && (OP) == CONST0_RTX (GET_MODE (OP))) \
1697 #define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \
1698 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
1699 : ((CODE) == 'R') ? (MEM_P (OP) \
1700 && mips_fetch_insns (OP) == 1) \
1701 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
1702 && call_insn_operand (OP, VOIDmode)) \
1703 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
1704 && move_operand (OP, VOIDmode) \
1705 && mips_dangerous_for_la25_p (OP)) \
1706 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
1707 && move_operand (OP, VOIDmode) \
1708 && !mips_dangerous_for_la25_p (OP)) \
1709 : ((CODE) == 'W') ? (MEM_P (OP) \
1710 && memory_operand (OP, VOIDmode) \
1711 && (!TARGET_MIPS16 \
1712 || (!stack_operand (OP, VOIDmode) \
1713 && !CONSTANT_P (XEXP (OP, 0))))) \
1714 : ((CODE) == 'Y') ? EXTRA_CONSTRAINT_Y (OP, STR) \
1717 /* Y is the only multi-letter constraint, and has length 2. */
1719 #define CONSTRAINT_LEN(C,STR) \
1721 : DEFAULT_CONSTRAINT_LEN (C, STR))
1723 /* Say which of the above are memory constraints. */
1724 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
1726 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1727 mips_preferred_reload_class (X, CLASS)
1729 /* Certain machines have the property that some registers cannot be
1730 copied to some other registers without using memory. Define this
1731 macro on those machines to be a C expression that is nonzero if
1732 objects of mode MODE in registers of CLASS1 can only be copied to
1733 registers of class CLASS2 by storing a register of CLASS1 into
1734 memory and loading that memory location into a register of CLASS2.
1736 Do not define this macro if its value would always be zero. */
1738 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1739 ((!TARGET_DEBUG_H_MODE \
1740 && GET_MODE_CLASS (MODE) == MODE_INT \
1741 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1742 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1743 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1744 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1745 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1747 /* The HI and LO registers can only be reloaded via the general
1748 registers. Condition code registers can only be loaded to the
1749 general registers, and from the floating point registers. */
1751 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1752 mips_secondary_reload_class (CLASS, MODE, X, 1)
1753 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1754 mips_secondary_reload_class (CLASS, MODE, X, 0)
1756 /* Return the maximum number of consecutive registers
1757 needed to represent mode MODE in a register of class CLASS. */
1759 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1761 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1762 mips_cannot_change_mode_class (FROM, TO, CLASS)
1764 /* Stack layout; function entry, exit and calling. */
1766 #define STACK_GROWS_DOWNWARD
1768 /* The offset of the first local variable from the beginning of the frame.
1769 See compute_frame_size for details about the frame layout.
1771 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1772 we assume that we will need 16 bytes of argument space. This is because
1773 the value profiling code may emit calls to cmpdi2 in leaf functions.
1774 Without this hack, the local variables will start at sp+8 and the gp save
1775 area will be at sp+16, and thus they will overlap. compute_frame_size is
1776 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1777 will end up as 24 instead of 8. This won't be needed if profiling code is
1778 inserted before virtual register instantiation. */
1780 #define STARTING_FRAME_OFFSET \
1781 ((flag_profile_values && ! TARGET_64BIT \
1782 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1783 : current_function_outgoing_args_size) \
1784 + (TARGET_ABICALLS && !TARGET_NEWABI \
1785 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1787 #define RETURN_ADDR_RTX mips_return_addr
1789 /* Since the mips16 ISA mode is encoded in the least-significant bit
1790 of the address, mask it off return addresses for purposes of
1791 finding exception handling regions. */
1793 #define MASK_RETURN_ADDR GEN_INT (-2)
1796 /* Similarly, don't use the least-significant bit to tell pointers to
1797 code from vtable index. */
1799 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1801 /* The eliminations to $17 are only used for mips16 code. See the
1802 definition of HARD_FRAME_POINTER_REGNUM. */
1804 #define ELIMINABLE_REGS \
1805 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1806 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1807 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1808 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1809 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1810 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1812 /* We can always eliminate to the hard frame pointer. We can eliminate
1813 to the stack pointer unless a frame pointer is needed.
1815 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1816 reload may be unable to compute the address of a local variable,
1817 since there is no way to add a large constant to the stack pointer
1818 without using a temporary register. */
1819 #define CAN_ELIMINATE(FROM, TO) \
1820 ((TO) == HARD_FRAME_POINTER_REGNUM \
1821 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1822 && (!TARGET_MIPS16 \
1823 || compute_frame_size (get_frame_size ()) < 32768)))
1825 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1826 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1828 /* Allocate stack space for arguments at the beginning of each function. */
1829 #define ACCUMULATE_OUTGOING_ARGS 1
1831 /* The argument pointer always points to the first argument. */
1832 #define FIRST_PARM_OFFSET(FNDECL) 0
1834 /* o32 and o64 reserve stack space for all argument registers. */
1835 #define REG_PARM_STACK_SPACE(FNDECL) \
1837 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1840 /* Define this if it is the responsibility of the caller to
1841 allocate the area reserved for arguments passed in registers.
1842 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1843 of this macro is to determine whether the space is included in
1844 `current_function_outgoing_args_size'. */
1845 #define OUTGOING_REG_PARM_STACK_SPACE
1847 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1849 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1851 /* Symbolic macros for the registers used to return integer and floating
1854 #define GP_RETURN (GP_REG_FIRST + 2)
1855 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1857 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1859 /* Symbolic macros for the first/last argument registers. */
1861 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1862 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1863 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1864 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1866 #define LIBCALL_VALUE(MODE) \
1867 mips_function_value (NULL_TREE, NULL, (MODE))
1869 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1870 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1872 /* 1 if N is a possible register number for a function value.
1873 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1874 Currently, R2 and F0 are only implemented here (C has no complex type) */
1876 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1877 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1878 && (N) == FP_RETURN + 2))
1880 /* 1 if N is a possible register number for function argument passing.
1881 We have no FP argument registers when soft-float. When FP registers
1882 are 32 bits, we can't directly reference the odd numbered ones. */
1884 #define FUNCTION_ARG_REGNO_P(N) \
1885 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1886 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1889 /* This structure has to cope with two different argument allocation
1890 schemes. Most MIPS ABIs view the arguments as a structure, of which
1891 the first N words go in registers and the rest go on the stack. If I
1892 < N, the Ith word might go in Ith integer argument register or in a
1893 floating-point register. For these ABIs, we only need to remember
1894 the offset of the current argument into the structure.
1896 The EABI instead allocates the integer and floating-point arguments
1897 separately. The first N words of FP arguments go in FP registers,
1898 the rest go on the stack. Likewise, the first N words of the other
1899 arguments go in integer registers, and the rest go on the stack. We
1900 need to maintain three counts: the number of integer registers used,
1901 the number of floating-point registers used, and the number of words
1902 passed on the stack.
1904 We could keep separate information for the two ABIs (a word count for
1905 the standard ABIs, and three separate counts for the EABI). But it
1906 seems simpler to view the standard ABIs as forms of EABI that do not
1907 allocate floating-point registers.
1909 So for the standard ABIs, the first N words are allocated to integer
1910 registers, and function_arg decides on an argument-by-argument basis
1911 whether that argument should really go in an integer register, or in
1912 a floating-point one. */
1914 typedef struct mips_args {
1915 /* Always true for varargs functions. Otherwise true if at least
1916 one argument has been passed in an integer register. */
1919 /* The number of arguments seen so far. */
1920 unsigned int arg_number;
1922 /* The number of integer registers used so far. For all ABIs except
1923 EABI, this is the number of words that have been added to the
1924 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
1925 unsigned int num_gprs;
1927 /* For EABI, the number of floating-point registers used so far. */
1928 unsigned int num_fprs;
1930 /* The number of words passed on the stack. */
1931 unsigned int stack_words;
1933 /* On the mips16, we need to keep track of which floating point
1934 arguments were passed in general registers, but would have been
1935 passed in the FP regs if this were a 32 bit function, so that we
1936 can move them to the FP regs if we wind up calling a 32 bit
1937 function. We record this information in fp_code, encoded in base
1938 four. A zero digit means no floating point argument, a one digit
1939 means an SFmode argument, and a two digit means a DFmode argument,
1940 and a three digit is not used. The low order digit is the first
1941 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
1942 an SFmode argument. ??? A more sophisticated approach will be
1943 needed if MIPS_ABI != ABI_32. */
1946 /* True if the function has a prototype. */
1950 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1951 for a call to a function whose data type is FNTYPE.
1952 For a library call, FNTYPE is 0. */
1954 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1955 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
1957 /* Update the data in CUM to advance over an argument
1958 of mode MODE and data type TYPE.
1959 (TYPE is null for libcalls where that information may not be available.) */
1961 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1962 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1964 /* Determine where to put an argument to a function.
1965 Value is zero to push the argument on the stack,
1966 or a hard register in which to store the argument.
1968 MODE is the argument's machine mode.
1969 TYPE is the data type of the argument (as a tree).
1970 This is null for libcalls where that information may
1972 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1973 the preceding args and about the function being called.
1974 NAMED is nonzero if this argument is a named parameter
1975 (otherwise it is an extra parameter matching an ellipsis). */
1977 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1978 function_arg( &CUM, MODE, TYPE, NAMED)
1980 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
1982 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1983 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
1985 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1986 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
1988 /* True if using EABI and varargs can be passed in floating-point
1989 registers. Under these conditions, we need a more complex form
1990 of va_list, which tracks GPR, FPR and stack arguments separately. */
1991 #define EABI_FLOAT_VARARGS_P \
1992 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
1995 /* Say that the epilogue uses the return address register. Note that
1996 in the case of sibcalls, the values "used by the epilogue" are
1997 considered live at the start of the called function. */
1998 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2000 /* Treat LOC as a byte offset from the stack pointer and round it up
2001 to the next fully-aligned offset. */
2002 #define MIPS_STACK_ALIGN(LOC) \
2003 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2006 /* Implement `va_start' for varargs and stdarg. */
2007 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2008 mips_va_start (valist, nextarg)
2010 /* Output assembler code to FILE to increment profiler label # LABELNO
2011 for profiling a function entry. */
2013 #define FUNCTION_PROFILER(FILE, LABELNO) \
2015 if (TARGET_MIPS16) \
2016 sorry ("mips16 function profiling"); \
2017 fprintf (FILE, "\t.set\tnoat\n"); \
2018 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2019 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2020 if (!TARGET_NEWABI) \
2023 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2024 TARGET_64BIT ? "dsubu" : "subu", \
2025 reg_names[STACK_POINTER_REGNUM], \
2026 reg_names[STACK_POINTER_REGNUM], \
2027 Pmode == DImode ? 16 : 8); \
2029 fprintf (FILE, "\tjal\t_mcount\n"); \
2030 fprintf (FILE, "\t.set\tat\n"); \
2033 /* No mips port has ever used the profiler counter word, so don't emit it
2034 or the label for it. */
2036 #define NO_PROFILE_COUNTERS 1
2038 /* Define this macro if the code for function profiling should come
2039 before the function prologue. Normally, the profiling code comes
2042 /* #define PROFILE_BEFORE_PROLOGUE */
2044 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2045 the stack pointer does not matter. The value is tested only in
2046 functions that have frame pointers.
2047 No definition is equivalent to always zero. */
2049 #define EXIT_IGNORE_STACK 1
2052 /* A C statement to output, on the stream FILE, assembler code for a
2053 block of data that contains the constant parts of a trampoline.
2054 This code should not include a label--the label is taken care of
2057 #define TRAMPOLINE_TEMPLATE(STREAM) \
2059 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2060 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2061 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2062 if (ptr_mode == DImode) \
2064 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2065 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2069 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2070 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2072 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2073 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2074 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2075 if (ptr_mode == DImode) \
2077 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2078 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2082 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2083 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2087 /* A C expression for the size in bytes of the trampoline, as an
2090 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2092 /* Alignment required for trampolines, in bits. */
2094 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2096 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2097 program and data caches. */
2099 #ifndef CACHE_FLUSH_FUNC
2100 #define CACHE_FLUSH_FUNC "_flush_cache"
2103 /* A C statement to initialize the variable parts of a trampoline.
2104 ADDR is an RTX for the address of the trampoline; FNADDR is an
2105 RTX for the address of the nested function; STATIC_CHAIN is an
2106 RTX for the static chain value that should be passed to the
2107 function when it is called. */
2109 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2111 rtx func_addr, chain_addr; \
2113 func_addr = plus_constant (ADDR, 32); \
2114 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2115 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2116 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2118 /* Flush both caches. We need to flush the data cache in case \
2119 the system has a write-back cache. */ \
2120 /* ??? Should check the return value for errors. */ \
2121 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2122 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2123 0, VOIDmode, 3, ADDR, Pmode, \
2124 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2125 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2128 /* Addressing modes, and classification of registers for them. */
2130 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2131 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2132 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2134 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2135 and check its validity for a certain class.
2136 We have two alternate definitions for each of them.
2137 The usual definition accepts all pseudo regs; the other rejects them all.
2138 The symbol REG_OK_STRICT causes the latter definition to be used.
2140 Most source files want to accept pseudo regs in the hope that
2141 they will get allocated to the class that the insn wants them to be in.
2142 Some source files that are used after register allocation
2143 need to be strict. */
2145 #ifndef REG_OK_STRICT
2146 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2147 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2149 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2150 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2153 #define REG_OK_FOR_INDEX_P(X) 0
2156 /* Maximum number of registers that can appear in a valid memory address. */
2158 #define MAX_REGS_PER_ADDRESS 1
2160 #ifdef REG_OK_STRICT
2161 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2163 if (mips_legitimate_address_p (MODE, X, 1)) \
2167 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2169 if (mips_legitimate_address_p (MODE, X, 0)) \
2174 /* Check for constness inline but use mips_legitimate_address_p
2175 to check whether a constant really is an address. */
2177 #define CONSTANT_ADDRESS_P(X) \
2178 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2180 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2182 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2184 if (mips_legitimize_address (&(X), MODE)) \
2189 /* A C statement or compound statement with a conditional `goto
2190 LABEL;' executed if memory address X (an RTX) can have different
2191 meanings depending on the machine mode of the memory reference it
2194 Autoincrement and autodecrement addresses typically have
2195 mode-dependent effects because the amount of the increment or
2196 decrement is the size of the operand being addressed. Some
2197 machines have other mode-dependent addresses. Many RISC machines
2198 have no mode-dependent addresses.
2200 You may assume that ADDR is a valid address for the machine. */
2202 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2204 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2205 'the start of the function that this code is output in'. */
2207 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2208 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2209 asm_fprintf ((FILE), "%U%s", \
2210 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2212 asm_fprintf ((FILE), "%U%s", (NAME))
2214 /* Specify the machine mode that this machine uses
2215 for the index in the tablejump instruction.
2216 ??? Using HImode in mips16 mode can cause overflow. */
2217 #define CASE_VECTOR_MODE \
2218 (TARGET_MIPS16 ? HImode : ptr_mode)
2220 /* Define as C expression which evaluates to nonzero if the tablejump
2221 instruction expects the table to contain offsets from the address of the
2223 Do not define this if the table should contain absolute addresses. */
2224 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2226 /* Define this as 1 if `char' should by default be signed; else as 0. */
2227 #ifndef DEFAULT_SIGNED_CHAR
2228 #define DEFAULT_SIGNED_CHAR 1
2231 /* Max number of bytes we can move from memory to memory
2232 in one reasonably fast instruction. */
2233 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2234 #define MAX_MOVE_MAX 8
2236 /* Define this macro as a C expression which is nonzero if
2237 accessing less than a word of memory (i.e. a `char' or a
2238 `short') is no faster than accessing a word of memory, i.e., if
2239 such access require more than one instruction or if there is no
2240 difference in cost between byte and (aligned) word loads.
2242 On RISC machines, it tends to generate better code to define
2243 this as 1, since it avoids making a QI or HI mode register. */
2244 #define SLOW_BYTE_ACCESS 1
2246 /* Define this to be nonzero if shift instructions ignore all but the low-order
2248 #define SHIFT_COUNT_TRUNCATED 1
2250 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2251 is done just by pretending it is already truncated. */
2252 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2253 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2256 /* Specify the machine mode that pointers have.
2257 After generation of rtl, the compiler makes no further distinction
2258 between pointers and any other objects of this machine mode. */
2261 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2264 /* Give call MEMs SImode since it is the "most permissive" mode
2265 for both 32-bit and 64-bit targets. */
2267 #define FUNCTION_MODE SImode
2270 /* The cost of loading values from the constant pool. It should be
2271 larger than the cost of any constant we want to synthesize in-line. */
2273 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2275 /* A C expression for the cost of moving data from a register in
2276 class FROM to one in class TO. The classes are expressed using
2277 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2278 the default; other values are interpreted relative to that.
2280 It is not required that the cost always equal 2 when FROM is the
2281 same as TO; on some machines it is expensive to move between
2282 registers if they are not general registers.
2284 If reload sees an insn consisting of a single `set' between two
2285 hard registers, and if `REGISTER_MOVE_COST' applied to their
2286 classes returns a value of 2, reload does not check to ensure
2287 that the constraints of the insn are met. Setting a cost of
2288 other than 2 will allow reload to verify that the constraints are
2289 met. You should do this if the `movM' pattern's constraints do
2290 not allow such copying. */
2292 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2293 mips_register_move_cost (MODE, FROM, TO)
2295 /* ??? Fix this to be right for the R8000. */
2296 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2297 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2298 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2300 /* Define if copies to/from condition code registers should be avoided.
2302 This is needed for the MIPS because reload_outcc is not complete;
2303 it needs to handle cases where the source is a general or another
2304 condition code register. */
2305 #define AVOID_CCMODE_COPIES
2307 /* A C expression for the cost of a branch instruction. A value of
2308 1 is the default; other values are interpreted relative to that. */
2310 /* ??? Fix this to be right for the R8000. */
2311 #define BRANCH_COST \
2313 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2316 /* If defined, modifies the length assigned to instruction INSN as a
2317 function of the context in which it is used. LENGTH is an lvalue
2318 that contains the initially computed length of the insn and should
2319 be updated with the correct length of the insn. */
2320 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2321 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2323 /* Control the assembler format that we output. */
2325 /* Output to assembler file text saying following lines
2326 may contain character constants, extra white space, comments, etc. */
2329 #define ASM_APP_ON " #APP\n"
2332 /* Output to assembler file text saying following lines
2333 no longer contain unusual constructs. */
2336 #define ASM_APP_OFF " #NO_APP\n"
2339 #define REGISTER_NAMES \
2340 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2341 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2342 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2343 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2344 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2345 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2346 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2347 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2348 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2349 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2350 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2351 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2352 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2353 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2354 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2355 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2356 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2357 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2358 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2359 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2360 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2361 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31" }
2363 /* List the "software" names for each register. Also list the numerical
2364 names for $fp and $sp. */
2366 #define ADDITIONAL_REGISTER_NAMES \
2368 { "$29", 29 + GP_REG_FIRST }, \
2369 { "$30", 30 + GP_REG_FIRST }, \
2370 { "at", 1 + GP_REG_FIRST }, \
2371 { "v0", 2 + GP_REG_FIRST }, \
2372 { "v1", 3 + GP_REG_FIRST }, \
2373 { "a0", 4 + GP_REG_FIRST }, \
2374 { "a1", 5 + GP_REG_FIRST }, \
2375 { "a2", 6 + GP_REG_FIRST }, \
2376 { "a3", 7 + GP_REG_FIRST }, \
2377 { "t0", 8 + GP_REG_FIRST }, \
2378 { "t1", 9 + GP_REG_FIRST }, \
2379 { "t2", 10 + GP_REG_FIRST }, \
2380 { "t3", 11 + GP_REG_FIRST }, \
2381 { "t4", 12 + GP_REG_FIRST }, \
2382 { "t5", 13 + GP_REG_FIRST }, \
2383 { "t6", 14 + GP_REG_FIRST }, \
2384 { "t7", 15 + GP_REG_FIRST }, \
2385 { "s0", 16 + GP_REG_FIRST }, \
2386 { "s1", 17 + GP_REG_FIRST }, \
2387 { "s2", 18 + GP_REG_FIRST }, \
2388 { "s3", 19 + GP_REG_FIRST }, \
2389 { "s4", 20 + GP_REG_FIRST }, \
2390 { "s5", 21 + GP_REG_FIRST }, \
2391 { "s6", 22 + GP_REG_FIRST }, \
2392 { "s7", 23 + GP_REG_FIRST }, \
2393 { "t8", 24 + GP_REG_FIRST }, \
2394 { "t9", 25 + GP_REG_FIRST }, \
2395 { "k0", 26 + GP_REG_FIRST }, \
2396 { "k1", 27 + GP_REG_FIRST }, \
2397 { "gp", 28 + GP_REG_FIRST }, \
2398 { "sp", 29 + GP_REG_FIRST }, \
2399 { "fp", 30 + GP_REG_FIRST }, \
2400 { "ra", 31 + GP_REG_FIRST }, \
2401 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2404 /* This is meant to be redefined in the host dependent files. It is a
2405 set of alternative names and regnums for mips coprocessors. */
2407 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2409 /* A C compound statement to output to stdio stream STREAM the
2410 assembler syntax for an instruction operand X. X is an RTL
2413 CODE is a value that can be used to specify one of several ways
2414 of printing the operand. It is used when identical operands
2415 must be printed differently depending on the context. CODE
2416 comes from the `%' specification that was used to request
2417 printing of the operand. If the specification was just `%DIGIT'
2418 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2419 is the ASCII code for LTR.
2421 If X is a register, this macro should print the register's name.
2422 The names can be found in an array `reg_names' whose type is
2423 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2425 When the machine description has a specification `%PUNCT' (a `%'
2426 followed by a punctuation character), this macro is called with
2427 a null pointer for X and the punctuation character for CODE.
2429 See mips.c for the MIPS specific codes. */
2431 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2433 /* A C expression which evaluates to true if CODE is a valid
2434 punctuation character for use in the `PRINT_OPERAND' macro. If
2435 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2436 punctuation characters (except for the standard one, `%') are
2437 used in this way. */
2439 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2441 /* A C compound statement to output to stdio stream STREAM the
2442 assembler syntax for an instruction operand that is a memory
2443 reference whose address is ADDR. ADDR is an RTL expression. */
2445 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2448 /* A C statement, to be executed after all slot-filler instructions
2449 have been output. If necessary, call `dbr_sequence_length' to
2450 determine the number of slots filled in a sequence (zero if not
2451 currently outputting a sequence), to decide how many no-ops to
2452 output, or whatever.
2454 Don't define this macro if it has nothing to do, but it is
2455 helpful in reading assembly output if the extent of the delay
2456 sequence is made explicit (e.g. with white space).
2458 Note that output routines for instructions with delay slots must
2459 be prepared to deal with not being output as part of a sequence
2460 (i.e. when the scheduling pass is not run, or when no slot
2461 fillers could be found.) The variable `final_sequence' is null
2462 when not processing a sequence, otherwise it contains the
2463 `sequence' rtx being output. */
2465 #define DBR_OUTPUT_SEQEND(STREAM) \
2468 if (set_nomacro > 0 && --set_nomacro == 0) \
2469 fputs ("\t.set\tmacro\n", STREAM); \
2471 if (set_noreorder > 0 && --set_noreorder == 0) \
2472 fputs ("\t.set\treorder\n", STREAM); \
2474 fputs ("\n", STREAM); \
2479 /* How to tell the debugger about changes of source files. */
2480 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2481 mips_output_filename (STREAM, NAME)
2483 /* mips-tfile does not understand .stabd directives. */
2484 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2485 dbxout_begin_stabn_sline (LINE); \
2486 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2489 /* Use .loc directives for SDB line numbers. */
2490 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2491 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2493 /* The MIPS implementation uses some labels for its own purpose. The
2494 following lists what labels are created, and are all formed by the
2495 pattern $L[a-z].*. The machine independent portion of GCC creates
2496 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2498 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2499 $Lb[0-9]+ Begin blocks for MIPS debug support
2500 $Lc[0-9]+ Label for use in s<xx> operation.
2501 $Le[0-9]+ End blocks for MIPS debug support */
2503 #undef ASM_DECLARE_OBJECT_NAME
2504 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2505 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2507 /* Globalizing directive for a label. */
2508 #define GLOBAL_ASM_OP "\t.globl\t"
2510 /* This says how to define a global common symbol. */
2512 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2514 /* This says how to define a local common symbol (i.e., not visible to
2517 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2518 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2519 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2522 /* This says how to output an external. It would be possible not to
2523 output anything and let undefined symbol become external. However
2524 the assembler uses length information on externals to allocate in
2525 data/sdata bss/sbss, thereby saving exec time. */
2527 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2528 mips_output_external(STREAM,DECL,NAME)
2530 /* This is how to declare a function name. The actual work of
2531 emitting the label is moved to function_prologue, so that we can
2532 get the line number correctly emitted before the .ent directive,
2533 and after any .file directives. Define as empty so that the function
2534 is not declared before the .ent directive elsewhere. */
2536 #undef ASM_DECLARE_FUNCTION_NAME
2537 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2539 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2540 #define FUNCTION_NAME_ALREADY_DECLARED 0
2543 /* This is how to store into the string LABEL
2544 the symbol_ref name of an internal numbered label where
2545 PREFIX is the class of label and NUM is the number within the class.
2546 This is suitable for output with `assemble_name'. */
2548 #undef ASM_GENERATE_INTERNAL_LABEL
2549 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2550 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2552 /* This is how to output an element of a case-vector that is absolute. */
2554 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2555 fprintf (STREAM, "\t%s\t%sL%d\n", \
2556 ptr_mode == DImode ? ".dword" : ".word", \
2557 LOCAL_LABEL_PREFIX, \
2560 /* This is how to output an element of a case-vector. We can make the
2561 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2564 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2566 if (TARGET_MIPS16) \
2567 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2568 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2569 else if (TARGET_GPWORD) \
2570 fprintf (STREAM, "\t%s\t%sL%d\n", \
2571 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2572 LOCAL_LABEL_PREFIX, VALUE); \
2574 fprintf (STREAM, "\t%s\t%sL%d\n", \
2575 ptr_mode == DImode ? ".dword" : ".word", \
2576 LOCAL_LABEL_PREFIX, VALUE); \
2579 /* When generating MIPS16 code, we want the jump table to be in the text
2580 section so that we can load its address using a PC-relative addition. */
2581 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
2583 /* This is how to output an assembler line
2584 that says to advance the location counter
2585 to a multiple of 2**LOG bytes. */
2587 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2588 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2590 /* This is how to output an assembler line to advance the location
2591 counter by SIZE bytes. */
2593 #undef ASM_OUTPUT_SKIP
2594 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2595 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2597 /* This is how to output a string. */
2598 #undef ASM_OUTPUT_ASCII
2599 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2600 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2602 /* Output #ident as a in the read-only data section. */
2603 #undef ASM_OUTPUT_IDENT
2604 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2606 const char *p = STRING; \
2607 int size = strlen (p) + 1; \
2608 readonly_data_section (); \
2609 assemble_string (p, size); \
2612 /* Default to -G 8 */
2613 #ifndef MIPS_DEFAULT_GVALUE
2614 #define MIPS_DEFAULT_GVALUE 8
2617 /* Define the strings to put out for each section in the object file. */
2618 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2619 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2620 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
2622 #undef READONLY_DATA_SECTION_ASM_OP
2623 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2625 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2628 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2629 TARGET_64BIT ? "dsubu" : "subu", \
2630 reg_names[STACK_POINTER_REGNUM], \
2631 reg_names[STACK_POINTER_REGNUM], \
2632 TARGET_64BIT ? "sd" : "sw", \
2634 reg_names[STACK_POINTER_REGNUM]); \
2638 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2641 if (! set_noreorder) \
2642 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2644 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2645 TARGET_64BIT ? "ld" : "lw", \
2647 reg_names[STACK_POINTER_REGNUM], \
2648 TARGET_64BIT ? "daddu" : "addu", \
2649 reg_names[STACK_POINTER_REGNUM], \
2650 reg_names[STACK_POINTER_REGNUM]); \
2652 if (! set_noreorder) \
2653 fprintf (STREAM, "\t.set\treorder\n"); \
2657 /* How to start an assembler comment.
2658 The leading space is important (the mips native assembler requires it). */
2659 #ifndef ASM_COMMENT_START
2660 #define ASM_COMMENT_START " #"
2663 /* Default definitions for size_t and ptrdiff_t. We must override the
2664 definitions from ../svr4.h on mips-*-linux-gnu. */
2667 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2670 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2673 /* Since the bits of the _init and _fini function is spread across
2674 many object files, each potentially with its own GP, we must assume
2675 we need to load our GP. We don't preserve $gp or $ra, since each
2676 init/fini chunk is supposed to initialize $gp, and crti/crtn
2677 already take care of preserving $ra and, when appropriate, $gp. */
2678 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2679 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2680 asm (SECTION_OP "\n\
2686 jal " USER_LABEL_PREFIX #FUNC "\n\
2687 " TEXT_SECTION_ASM_OP);
2688 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2689 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2690 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2691 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2692 asm (SECTION_OP "\n\
2697 .cpsetup $31, $2, 1b\n\
2698 jal " USER_LABEL_PREFIX #FUNC "\n\
2699 " TEXT_SECTION_ASM_OP);
2704 #define HAVE_AS_TLS 0
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