1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char call_used_regs[];
30 extern int may_call_alloca;
31 extern char **save_argv;
32 extern int target_flags;
34 /* MIPS external variables defined in mips.c. */
38 CMP_SI, /* compare four byte integers */
39 CMP_DI, /* compare eight byte integers */
40 CMP_SF, /* compare single precision floats */
41 CMP_DF, /* compare double precision floats */
42 CMP_MAX /* max comparison type */
45 /* Which processor to schedule for. Since there is no difference between
46 a R2000 and R3000 in terms of the scheduler, we collapse them into
47 just an R3000. The elements of the enumeration must match exactly
48 the cpu attribute in the mips.md machine description. */
74 /* Recast the cpu class to be the cpu attribute. */
75 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
77 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
78 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
79 to work on a 64 bit machine. */
87 /* Whether to emit abicalls code sequences or not. */
89 enum mips_abicalls_type {
94 /* Recast the abicalls class to be the abicalls attribute. */
95 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
97 /* Information about one recognized processor. Defined here for the
98 benefit of TARGET_CPU_CPP_BUILTINS. */
99 struct mips_cpu_info {
100 /* The 'canonical' name of the processor as far as GCC is concerned.
101 It's typically a manufacturer's prefix followed by a numerical
102 designation. It should be lower case. */
105 /* The internal processor number that most closely matches this
106 entry. Several processors can have the same value, if there's no
107 difference between them from GCC's point of view. */
108 enum processor_type cpu;
110 /* The ISA level that the processor implements. */
114 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
115 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
116 extern const char *current_function_file; /* filename current function is in */
117 extern int num_source_filenames; /* current .file # */
118 extern int inside_function; /* != 0 if inside of a function */
119 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
120 extern int file_in_function_warning; /* warning given about .file in func */
121 extern int sdb_label_count; /* block start/end next label # */
122 extern int sdb_begin_function_line; /* Starting Line of current function */
123 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
124 extern int sym_lineno; /* sgi next label # for each stmt */
125 extern int set_noreorder; /* # of nested .set noreorder's */
126 extern int set_nomacro; /* # of nested .set nomacro's */
127 extern int set_noat; /* # of nested .set noat's */
128 extern int set_volatile; /* # of nested .set volatile's */
129 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
130 extern int mips_dbx_regno[]; /* Map register # to debug register # */
131 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
132 extern enum cmp_type branch_type; /* what type of branch to use */
133 extern enum processor_type mips_arch; /* which cpu to codegen for */
134 extern enum processor_type mips_tune; /* which cpu to schedule for */
135 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
136 extern int mips_isa; /* architectural level */
137 extern int mips16; /* whether generating mips16 code */
138 extern int mips16_hard_float; /* mips16 without -msoft-float */
139 extern int mips_entry; /* generate entry/exit for mips16 */
140 extern const char *mips_arch_string; /* for -march=<xxx> */
141 extern const char *mips_tune_string; /* for -mtune=<xxx> */
142 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
143 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
144 extern const char *mips_entry_string; /* for -mentry */
145 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
146 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
147 extern int mips_string_length; /* length of strings for mips16 */
148 extern const struct mips_cpu_info mips_cpu_info_table[];
149 extern const struct mips_cpu_info *mips_arch_info;
150 extern const struct mips_cpu_info *mips_tune_info;
152 /* Functions to change what output section we are using. */
153 extern void sdata_section PARAMS ((void));
154 extern void sbss_section PARAMS ((void));
156 /* Macros to silence warnings about numbers being signed in traditional
157 C and unsigned in ISO C when compiled on 32-bit hosts. */
159 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
160 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
161 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
164 /* Run-time compilation parameters selecting different hardware subsets. */
166 /* Macros used in the machine description to test the flags. */
168 /* Bits for real switches */
169 #define MASK_INT64 0x00000001 /* ints are 64 bits */
170 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
171 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
172 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
173 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
174 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
175 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
176 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
177 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
178 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
179 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
180 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
181 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
182 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
183 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
184 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
185 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
186 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
187 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
188 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
189 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
190 #define MASK_NO_CHECK_ZERO_DIV \
191 0x00200000 /* divide by zero checking */
192 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
194 #define MASK_UNINIT_CONST_IN_RODATA \
195 0x00800000 /* Store uninitialized
197 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
198 multiply-add operations. */
200 /* Debug switches, not documented */
201 #define MASK_DEBUG 0 /* unused */
202 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
203 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
204 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
205 #define MASK_DEBUG_D 0 /* don't do define_split's */
206 #define MASK_DEBUG_E 0 /* function_arg debug */
207 #define MASK_DEBUG_F 0 /* ??? */
208 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
209 #define MASK_DEBUG_I 0 /* unused */
211 /* Dummy switches used only in specs */
212 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
214 /* r4000 64 bit sizes */
215 #define TARGET_INT64 (target_flags & MASK_INT64)
216 #define TARGET_LONG64 (target_flags & MASK_LONG64)
217 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
218 #define TARGET_64BIT (target_flags & MASK_64BIT)
220 /* Mips vs. GNU linker */
221 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
223 /* Mips vs. GNU assembler */
224 #define TARGET_GAS (target_flags & MASK_GAS)
225 #define TARGET_MIPS_AS (!TARGET_GAS)
228 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
229 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
230 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
231 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
232 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
233 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
234 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
235 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
236 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
238 /* Reg. Naming in .s ($21 vs. $a0) */
239 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
241 /* Optimize for Sdata/Sbss */
242 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
244 /* call memcpy instead of inline code */
245 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
247 /* .abicalls, etc from Pyramid V.4 */
248 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
250 /* software floating point */
251 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
252 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
254 /* always call through a register */
255 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
257 /* generate embedded PIC code;
259 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
261 /* for embedded systems, optimize for
262 reduced RAM space instead of for
264 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
266 /* always store uninitialized const
267 variables in rodata, requires
268 TARGET_EMBEDDED_DATA. */
269 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
271 /* generate big endian code. */
272 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
274 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
275 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
277 #define TARGET_MAD (target_flags & MASK_MAD)
279 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
281 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
283 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
285 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
288 /* True if we should use NewABI-style relocation operators for
289 symbolic addresses. This is never true for mips16 code,
290 which has its own conventions. */
292 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
295 /* True if the call patterns should be split into a jalr followed by
296 an instruction to restore $gp. This is only ever true for SVR4 PIC,
297 in which $gp is call-clobbered. It is only safe to split the load
298 from the call when every use of $gp is explicit. */
300 #define TARGET_SPLIT_CALLS \
301 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
303 /* True if we can optimize sibling calls. For simplicity, we only
304 handle cases in which call_insn_operand will reject invalid
305 sibcall addresses. There are two cases in which this isn't true:
307 - TARGET_MIPS16. call_insn_operand accepts constant addresses
308 but there is no direct jump instruction. It isn't worth
309 using sibling calls in this case anyway; they would usually
310 be longer than normal calls.
312 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
313 accepts global constants, but "jr $25" is the only allowed
316 #define TARGET_SIBCALLS \
317 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
319 /* True if .gpword or .gpdword should be used for switch tables.
320 Not all SGI assemblers support this. */
322 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
324 /* Generate mips16 code */
325 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
327 /* Generic ISA defines. */
328 #define ISA_MIPS1 (mips_isa == 1)
329 #define ISA_MIPS2 (mips_isa == 2)
330 #define ISA_MIPS3 (mips_isa == 3)
331 #define ISA_MIPS4 (mips_isa == 4)
332 #define ISA_MIPS32 (mips_isa == 32)
333 #define ISA_MIPS32R2 (mips_isa == 33)
334 #define ISA_MIPS64 (mips_isa == 64)
336 /* Architecture target defines. */
337 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
338 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
339 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
340 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
341 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
342 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
343 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
344 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
345 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
346 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
347 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
349 /* Scheduling target defines. */
350 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
351 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
352 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
353 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
354 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
355 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
356 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
357 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
358 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
360 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
362 /* Define preprocessor macros for the -march and -mtune options.
363 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
364 processor. If INFO's canonical name is "foo", define PREFIX to
365 be "foo", and define an additional macro PREFIX_FOO. */
366 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
371 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
372 for (p = macro; *p != 0; p++) \
375 builtin_define (macro); \
376 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
381 /* Target CPU builtins. */
382 #define TARGET_CPU_CPP_BUILTINS() \
385 builtin_assert ("cpu=mips"); \
386 builtin_define ("__mips__"); \
387 builtin_define ("_mips"); \
389 /* We do this here because __mips is defined below \
390 and so we can't use builtin_define_std. */ \
392 builtin_define ("mips"); \
394 /* Treat _R3000 and _R4000 like register-size defines, \
395 which is how they've historically been used. */ \
398 builtin_define ("__mips64"); \
399 builtin_define_std ("R4000"); \
400 builtin_define ("_R4000"); \
404 builtin_define_std ("R3000"); \
405 builtin_define ("_R3000"); \
407 if (TARGET_FLOAT64) \
408 builtin_define ("__mips_fpr=64"); \
410 builtin_define ("__mips_fpr=32"); \
413 builtin_define ("__mips16"); \
415 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
416 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
420 builtin_define ("__mips=1"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
423 else if (ISA_MIPS2) \
425 builtin_define ("__mips=2"); \
426 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
428 else if (ISA_MIPS3) \
430 builtin_define ("__mips=3"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
433 else if (ISA_MIPS4) \
435 builtin_define ("__mips=4"); \
436 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
438 else if (ISA_MIPS32) \
440 builtin_define ("__mips=32"); \
441 builtin_define ("__mips_isa_rev=1"); \
442 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
444 else if (ISA_MIPS32R2) \
446 builtin_define ("__mips=32"); \
447 builtin_define ("__mips_isa_rev=2"); \
448 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
450 else if (ISA_MIPS64) \
452 builtin_define ("__mips=64"); \
453 builtin_define ("__mips_isa_rev=1"); \
454 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
457 if (TARGET_HARD_FLOAT) \
458 builtin_define ("__mips_hard_float"); \
459 else if (TARGET_SOFT_FLOAT) \
460 builtin_define ("__mips_soft_float"); \
462 if (TARGET_SINGLE_FLOAT) \
463 builtin_define ("__mips_single_float"); \
465 if (TARGET_BIG_ENDIAN) \
467 builtin_define_std ("MIPSEB"); \
468 builtin_define ("_MIPSEB"); \
472 builtin_define_std ("MIPSEL"); \
473 builtin_define ("_MIPSEL"); \
476 /* Macros dependent on the C dialect. */ \
477 if (preprocessing_asm_p ()) \
479 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
480 builtin_define ("_LANGUAGE_ASSEMBLY"); \
482 else if (c_language == clk_c) \
484 builtin_define_std ("LANGUAGE_C"); \
485 builtin_define ("_LANGUAGE_C"); \
487 else if (c_language == clk_cplusplus) \
489 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
490 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
491 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
495 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
496 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
497 /* Bizzare, but needed at least for Irix. */ \
498 builtin_define_std ("LANGUAGE_C"); \
499 builtin_define ("_LANGUAGE_C"); \
502 if (mips_abi == ABI_EABI) \
503 builtin_define ("__mips_eabi"); \
509 /* Macro to define tables used to set the flags.
510 This is a list in braces of pairs in braces,
511 each pair being { "NAME", VALUE }
512 where VALUE is the bits to set or minus the bits to clear.
513 An empty string NAME is used to identify the default VALUE. */
515 #define TARGET_SWITCHES \
517 SUBTARGET_TARGET_SWITCHES \
518 {"int64", MASK_INT64 | MASK_LONG64, \
519 N_("Use 64-bit int type")}, \
520 {"long64", MASK_LONG64, \
521 N_("Use 64-bit long type")}, \
522 {"long32", -(MASK_LONG64 | MASK_INT64), \
523 N_("Use 32-bit long type")}, \
524 {"split-addresses", MASK_SPLIT_ADDR, \
525 N_("Optimize lui/addiu address loads")}, \
526 {"no-split-addresses", -MASK_SPLIT_ADDR, \
527 N_("Don't optimize lui/addiu address loads")}, \
528 {"mips-as", -MASK_GAS, \
529 N_("Use MIPS as")}, \
532 {"rnames", MASK_NAME_REGS, \
533 N_("Use symbolic register names")}, \
534 {"no-rnames", -MASK_NAME_REGS, \
535 N_("Don't use symbolic register names")}, \
536 {"gpOPT", MASK_GPOPT, \
537 N_("Use GP relative sdata/sbss sections")}, \
538 {"gpopt", MASK_GPOPT, \
539 N_("Use GP relative sdata/sbss sections")}, \
540 {"no-gpOPT", -MASK_GPOPT, \
541 N_("Don't use GP relative sdata/sbss sections")}, \
542 {"no-gpopt", -MASK_GPOPT, \
543 N_("Don't use GP relative sdata/sbss sections")}, \
545 N_("Output compiler statistics (now ignored)")}, \
547 N_("Don't output compiler statistics")}, \
548 {"memcpy", MASK_MEMCPY, \
549 N_("Don't optimize block moves")}, \
550 {"no-memcpy", -MASK_MEMCPY, \
551 N_("Optimize block moves")}, \
552 {"mips-tfile", MASK_MIPS_TFILE, \
553 N_("Use mips-tfile asm postpass")}, \
554 {"no-mips-tfile", -MASK_MIPS_TFILE, \
555 N_("Don't use mips-tfile asm postpass")}, \
556 {"soft-float", MASK_SOFT_FLOAT, \
557 N_("Use software floating point")}, \
558 {"hard-float", -MASK_SOFT_FLOAT, \
559 N_("Use hardware floating point")}, \
560 {"fp64", MASK_FLOAT64, \
561 N_("Use 64-bit FP registers")}, \
562 {"fp32", -MASK_FLOAT64, \
563 N_("Use 32-bit FP registers")}, \
564 {"gp64", MASK_64BIT, \
565 N_("Use 64-bit general registers")}, \
566 {"gp32", -MASK_64BIT, \
567 N_("Use 32-bit general registers")}, \
568 {"abicalls", MASK_ABICALLS, \
569 N_("Use Irix PIC")}, \
570 {"no-abicalls", -MASK_ABICALLS, \
571 N_("Don't use Irix PIC")}, \
572 {"long-calls", MASK_LONG_CALLS, \
573 N_("Use indirect calls")}, \
574 {"no-long-calls", -MASK_LONG_CALLS, \
575 N_("Don't use indirect calls")}, \
576 {"embedded-pic", MASK_EMBEDDED_PIC, \
577 N_("Use embedded PIC")}, \
578 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
579 N_("Don't use embedded PIC")}, \
580 {"embedded-data", MASK_EMBEDDED_DATA, \
581 N_("Use ROM instead of RAM")}, \
582 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
583 N_("Don't use ROM instead of RAM")}, \
584 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
585 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
586 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
587 N_("Don't put uninitialized constants in ROM")}, \
588 {"eb", MASK_BIG_ENDIAN, \
589 N_("Use big-endian byte order")}, \
590 {"el", -MASK_BIG_ENDIAN, \
591 N_("Use little-endian byte order")}, \
592 {"single-float", MASK_SINGLE_FLOAT, \
593 N_("Use single (32-bit) FP only")}, \
594 {"double-float", -MASK_SINGLE_FLOAT, \
595 N_("Don't use single (32-bit) FP only")}, \
597 N_("Use multiply accumulate")}, \
598 {"no-mad", -MASK_MAD, \
599 N_("Don't use multiply accumulate")}, \
600 {"no-fused-madd", MASK_NO_FUSED_MADD, \
601 N_("Don't generate fused multiply/add instructions")}, \
602 {"fused-madd", -MASK_NO_FUSED_MADD, \
603 N_("Generate fused multiply/add instructions")}, \
604 {"fix4300", MASK_4300_MUL_FIX, \
605 N_("Work around early 4300 hardware bug")}, \
606 {"no-fix4300", -MASK_4300_MUL_FIX, \
607 N_("Don't work around early 4300 hardware bug")}, \
608 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
609 N_("Trap on integer divide by zero")}, \
610 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
611 N_("Don't trap on integer divide by zero")}, \
612 { "branch-likely", MASK_BRANCHLIKELY, \
613 N_("Use Branch Likely instructions, overriding default for arch")}, \
614 { "no-branch-likely", -MASK_BRANCHLIKELY, \
615 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
616 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
617 N_("Use NewABI-style %reloc() assembly operators")}, \
618 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
619 N_("Use assembler macros instead of relocation operators")}, \
620 {"debug", MASK_DEBUG, \
622 {"debuga", MASK_DEBUG_A, \
624 {"debugb", MASK_DEBUG_B, \
626 {"debugc", MASK_DEBUG_C, \
628 {"debugd", MASK_DEBUG_D, \
630 {"debuge", MASK_DEBUG_E, \
632 {"debugf", MASK_DEBUG_F, \
634 {"debugg", MASK_DEBUG_G, \
636 {"debugi", MASK_DEBUG_I, \
638 {"", (TARGET_DEFAULT \
639 | TARGET_CPU_DEFAULT \
640 | TARGET_ENDIAN_DEFAULT), \
644 /* Default target_flags if no switches are specified */
646 #ifndef TARGET_DEFAULT
647 #define TARGET_DEFAULT 0
650 #ifndef TARGET_CPU_DEFAULT
651 #define TARGET_CPU_DEFAULT 0
654 #ifndef TARGET_ENDIAN_DEFAULT
655 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
658 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
659 #ifndef MIPS_ISA_DEFAULT
660 #ifndef MIPS_CPU_STRING_DEFAULT
661 #define MIPS_CPU_STRING_DEFAULT "from-abi"
667 /* Make this compile time constant for libgcc2 */
669 #define TARGET_64BIT 1
671 #define TARGET_64BIT 0
673 #endif /* IN_LIBGCC2 */
675 #ifndef MULTILIB_ENDIAN_DEFAULT
676 #if TARGET_ENDIAN_DEFAULT == 0
677 #define MULTILIB_ENDIAN_DEFAULT "EL"
679 #define MULTILIB_ENDIAN_DEFAULT "EB"
683 #ifndef MULTILIB_ISA_DEFAULT
684 # if MIPS_ISA_DEFAULT == 1
685 # define MULTILIB_ISA_DEFAULT "mips1"
687 # if MIPS_ISA_DEFAULT == 2
688 # define MULTILIB_ISA_DEFAULT "mips2"
690 # if MIPS_ISA_DEFAULT == 3
691 # define MULTILIB_ISA_DEFAULT "mips3"
693 # if MIPS_ISA_DEFAULT == 4
694 # define MULTILIB_ISA_DEFAULT "mips4"
696 # if MIPS_ISA_DEFAULT == 32
697 # define MULTILIB_ISA_DEFAULT "mips32"
699 # if MIPS_ISA_DEFAULT == 33
700 # define MULTILIB_ISA_DEFAULT "mips32r2"
702 # if MIPS_ISA_DEFAULT == 64
703 # define MULTILIB_ISA_DEFAULT "mips64"
705 # define MULTILIB_ISA_DEFAULT "mips1"
715 #ifndef MULTILIB_DEFAULTS
716 #define MULTILIB_DEFAULTS \
717 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
720 /* We must pass -EL to the linker by default for little endian embedded
721 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
722 linker will default to using big-endian output files. The OUTPUT_FORMAT
723 line must be in the linker script, otherwise -EB/-EL will not work. */
726 #if TARGET_ENDIAN_DEFAULT == 0
727 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
729 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
733 #define TARGET_OPTIONS \
735 SUBTARGET_TARGET_OPTIONS \
736 { "tune=", &mips_tune_string, \
737 N_("Specify CPU for scheduling purposes"), 0}, \
738 { "arch=", &mips_arch_string, \
739 N_("Specify CPU for code generation purposes"), 0}, \
740 { "abi=", &mips_abi_string, \
741 N_("Specify an ABI"), 0}, \
742 { "ips", &mips_isa_string, \
743 N_("Specify a Standard MIPS ISA"), 0}, \
744 { "entry", &mips_entry_string, \
745 N_("Use mips16 entry/exit psuedo ops"), 0}, \
746 { "no-mips16", &mips_no_mips16_string, \
747 N_("Don't use MIPS16 instructions"), 0}, \
748 { "no-flush-func", &mips_cache_flush_func, \
749 N_("Don't call any cache flush functions"), 0}, \
750 { "flush-func=", &mips_cache_flush_func, \
751 N_("Specify cache flush function"), 0}, \
754 /* This is meant to be redefined in the host dependent files. */
755 #define SUBTARGET_TARGET_OPTIONS
757 /* Support for a compile-time default CPU, et cetera. The rules are:
758 --with-arch is ignored if -march is specified or a -mips is specified
759 (other than -mips16).
760 --with-tune is ignored if -mtune is specified.
761 --with-abi is ignored if -mabi is specified.
762 --with-float is ignored if -mhard-float or -msoft-float are
764 #define OPTION_DEFAULT_SPECS \
765 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
766 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
767 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
768 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
771 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
775 /* Generate three-operand multiply instructions for SImode. */
776 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
784 /* Generate three-operand multiply instructions for DImode. */
785 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
788 /* Macros to decide whether certain features are available or not,
789 depending on the instruction set architecture level. */
791 #define HAVE_SQRT_P() (!ISA_MIPS1)
793 /* True if the ABI can only work with 64-bit integer registers. We
794 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
795 otherwise floating-point registers must also be 64-bit. */
796 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
797 || mips_abi == ABI_O64 \
798 || mips_abi == ABI_N32)
800 /* Likewise for 32-bit regs. */
801 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
803 /* True if symbols are 64 bits wide. At present, n64 is the only
804 ABI for which this is true. */
805 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
807 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
808 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
812 /* ISA has branch likely instructions (eg. mips2). */
813 /* Disable branchlikely for tx39 until compare rewrite. They haven't
814 been generated up to this point. */
815 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
818 /* ISA has the conditional move instructions introduced in mips4. */
819 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
823 && !TARGET_MIPS5500 \
826 /* ISA has just the integer condition move instructions (movn,movz) */
827 #define ISA_HAS_INT_CONDMOVE 0
829 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
830 branch on CC, and move (both FP and non-FP) on CC. */
831 #define ISA_HAS_8CC (ISA_MIPS4 \
836 /* This is a catch all for the other new mips4 instructions: indexed load and
837 indexed prefetch instructions, the FP madd and msub instructions,
838 and the FP recip and recip sqrt instructions */
839 #define ISA_HAS_FP4 ((ISA_MIPS4 \
843 /* ISA has conditional trap instructions. */
844 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
847 /* ISA has integer multiply-accumulate instructions, madd and msub. */
848 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
853 /* ISA has floating-point nmadd and nmsub instructions. */
854 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
856 && (!TARGET_MIPS5400 || TARGET_MAD) \
859 /* ISA has count leading zeroes/ones instruction (not implemented). */
860 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
865 /* ISA has double-word count leading zeroes/ones instruction (not
867 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
870 /* ISA has three operand multiply instructions that put
871 the high part in an accumulator: mulhi or mulhiu. */
872 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
877 /* ISA has three operand multiply instructions that
878 negates the result and puts the result in an accumulator. */
879 #define ISA_HAS_MULS (TARGET_MIPS5400 \
884 /* ISA has three operand multiply instructions that subtracts the
885 result from a 4th operand and puts the result in an accumulator. */
886 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
890 /* ISA has three operand multiply instructions that the result
891 from a 4th operand and puts the result in an accumulator. */
892 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
898 /* ISA has 32-bit rotate right instruction. */
899 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
906 /* ISA has 64-bit rotate right instruction. */
907 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
909 && (TARGET_MIPS5400 \
914 /* ISA has data prefetch instruction. */
915 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
921 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
922 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
923 also requires TARGET_DOUBLE_FLOAT. */
924 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
926 /* ISA includes the MIPS32r2 seb and seh instructions. */
927 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
931 /* True if the result of a load is not available to the next instruction.
932 A nop will then be needed between instructions like "lw $4,..."
933 and "addiu $4,$4,1". */
934 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
935 && !TARGET_MIPS3900 \
938 /* Likewise mtc1 and mfc1. */
939 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
941 /* Likewise floating-point comparisons. */
942 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
944 /* True if mflo and mfhi can be immediately followed by instructions
945 which write to the HI and LO registers. Most targets require a
946 two-instruction gap. */
947 #define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
949 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
950 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
951 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
952 target_flags, and -mgp64 sets MASK_64BIT.
954 Setting MASK_64BIT in target_flags will cause gcc to assume that
955 registers are 64 bits wide. int, long and void * will be 32 bit;
956 this may be changed with -mint64 or -mlong64.
958 The gen* programs link code that refers to MASK_64BIT. They don't
959 actually use the information in target_flags; they just refer to
962 /* Switch Recognition by gcc.c. Add -G xx support */
964 #undef SWITCH_TAKES_ARG
965 #define SWITCH_TAKES_ARG(CHAR) \
966 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
968 /* Sometimes certain combinations of command options do not make sense
969 on a particular target machine. You can define a macro
970 `OVERRIDE_OPTIONS' to take account of this. This macro, if
971 defined, is executed once just after all the command options have
974 On the MIPS, it is used to handle -G. We also use it to set up all
975 of the tables referenced in the other macros. */
977 #define OVERRIDE_OPTIONS override_options ()
979 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
981 /* Show we can debug even without a frame pointer. */
982 #define CAN_DEBUG_WITHOUT_FP
984 /* Tell collect what flags to pass to nm. */
986 #define NM_FLAGS "-Bn"
990 /* Assembler specs. */
992 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
995 #define MIPS_AS_ASM_SPEC "\
996 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
997 %{pipe: %e-pipe is not supported} \
998 %{K} %(subtarget_mips_as_asm_spec)"
1000 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
1001 rather than gas. It may be overridden by subtargets. */
1003 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1004 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1007 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1010 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1012 #define SUBTARGET_TARGET_SWITCHES
1014 extern int mips_abi;
1016 #ifndef MIPS_ABI_DEFAULT
1017 #define MIPS_ABI_DEFAULT ABI_32
1020 /* Use the most portable ABI flag for the ASM specs. */
1022 #if MIPS_ABI_DEFAULT == ABI_32
1023 #define MULTILIB_ABI_DEFAULT "mabi=32"
1024 #define ASM_ABI_DEFAULT_SPEC "-32"
1027 #if MIPS_ABI_DEFAULT == ABI_O64
1028 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1029 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1032 #if MIPS_ABI_DEFAULT == ABI_N32
1033 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1034 #define ASM_ABI_DEFAULT_SPEC "-n32"
1037 #if MIPS_ABI_DEFAULT == ABI_64
1038 #define MULTILIB_ABI_DEFAULT "mabi=64"
1039 #define ASM_ABI_DEFAULT_SPEC "-64"
1042 #if MIPS_ABI_DEFAULT == ABI_EABI
1043 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1044 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1047 /* Only ELF targets can switch the ABI. */
1048 #ifndef OBJECT_FORMAT_ELF
1049 #undef ASM_ABI_DEFAULT_SPEC
1050 #define ASM_ABI_DEFAULT_SPEC ""
1053 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1054 GAS_ASM_SPEC as the default, depending upon the value of
1057 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1060 #define TARGET_ASM_SPEC "\
1061 %{mmips-as: %(mips_as_asm_spec)} \
1062 %{!mmips-as: %(gas_asm_spec)}"
1066 #define TARGET_ASM_SPEC "\
1067 %{!mgas: %(mips_as_asm_spec)} \
1068 %{mgas: %(gas_asm_spec)}"
1070 #endif /* not GAS */
1072 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1073 to the assembler. It may be overridden by subtargets. */
1074 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1075 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1077 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1080 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1081 the assembler. It may be overridden by subtargets. */
1082 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1083 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1084 %{g} %{g0} %{g1} %{g2} %{g3} \
1085 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1086 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1087 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1088 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1092 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1093 and stabs debugging info. */
1094 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1096 #define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1098 #define MDEBUG_ASM_SPEC ""
1099 #endif /* not GAS */
1101 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1102 overridden by subtargets. */
1104 #ifndef SUBTARGET_ASM_SPEC
1105 #define SUBTARGET_ASM_SPEC ""
1108 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1109 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1110 whether we're using GAS. These options can only be used properly
1111 with GAS, and it is better to get an error from a non-GAS assembler
1112 than to silently generate bad code. */
1116 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1117 %{mips32} %{mips32r2} %{mips64} \
1118 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1119 %(subtarget_asm_optimizing_spec) \
1120 %(subtarget_asm_debugging_spec) \
1122 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1123 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1124 %{mgp32} %{mgp64} %{march=*} \
1125 %(target_asm_spec) \
1126 %(subtarget_asm_spec)"
1128 /* Specify to run a post-processor, mips-tfile after the assembler
1129 has run to stuff the mips debug information into the object file.
1130 This is needed because the $#!%^ MIPS assembler provides no way
1131 of specifying such information in the assembly file. If we are
1132 cross compiling, disable mips-tfile unless the user specifies
1135 #ifndef ASM_FINAL_SPEC
1136 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1138 #define ASM_FINAL_SPEC "\
1139 %{mmips-as: %{!mno-mips-tfile: \
1140 \n mips-tfile %{v*: -v} \
1142 %{!K: %{save-temps: -I %b.o~}} \
1143 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1144 %{.s:%i} %{!.s:%g.s}}}"
1148 #define ASM_FINAL_SPEC "\
1149 %{!mgas: %{!mno-mips-tfile: \
1150 \n mips-tfile %{v*: -v} \
1152 %{!K: %{save-temps: -I %b.o~}} \
1153 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1154 %{.s:%i} %{!.s:%g.s}}}"
1157 #endif /* ASM_FINAL_SPEC */
1159 /* Redefinition of libraries used. Mips doesn't support normal
1160 UNIX style profiling via calling _mcount. It does offer
1161 profiling that samples the PC, so do what we can... */
1164 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1167 /* Extra switches sometimes passed to the linker. */
1168 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1169 will interpret it as a -b option. */
1172 #define LINK_SPEC "\
1174 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1175 %{bestGnum} %{shared} %{non_shared}"
1176 #endif /* LINK_SPEC defined */
1179 /* Specs for the compiler proper */
1181 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1182 overridden by subtargets. */
1183 #ifndef SUBTARGET_CC1_SPEC
1184 #define SUBTARGET_CC1_SPEC ""
1187 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1188 /* Note, we will need to adjust the following if we ever find a MIPS variant
1189 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1190 that show up in this case. */
1194 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1195 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1197 %(subtarget_cc1_spec)"
1200 /* Preprocessor specs. */
1202 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1203 overridden by subtargets. */
1204 #ifndef SUBTARGET_CPP_SPEC
1205 #define SUBTARGET_CPP_SPEC ""
1208 #define CPP_SPEC "%(subtarget_cpp_spec)"
1210 /* This macro defines names of additional specifications to put in the specs
1211 that can be used in various specifications like CC1_SPEC. Its definition
1212 is an initializer with a subgrouping for each command option.
1214 Each subgrouping contains a string constant, that defines the
1215 specification name, and a string constant that used by the GNU CC driver
1218 Do not define this macro if it does not need to do anything. */
1220 #define EXTRA_SPECS \
1221 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1222 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1223 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1224 { "gas_asm_spec", GAS_ASM_SPEC }, \
1225 { "target_asm_spec", TARGET_ASM_SPEC }, \
1226 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1227 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1228 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1229 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1230 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1231 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1232 { "endian_spec", ENDIAN_SPEC }, \
1233 SUBTARGET_EXTRA_SPECS
1235 #ifndef SUBTARGET_EXTRA_SPECS
1236 #define SUBTARGET_EXTRA_SPECS
1239 /* If defined, this macro is an additional prefix to try after
1240 `STANDARD_EXEC_PREFIX'. */
1242 #ifndef MD_EXEC_PREFIX
1243 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1246 #ifndef MD_STARTFILE_PREFIX
1247 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1251 /* Print subsidiary information on the compiler version in use. */
1253 #define MIPS_VERSION "[AL 1.1, MM 40]"
1255 #ifndef MACHINE_TYPE
1256 #define MACHINE_TYPE "BSD Mips"
1259 #ifndef TARGET_VERSION_INTERNAL
1260 #define TARGET_VERSION_INTERNAL(STREAM) \
1261 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1264 #ifndef TARGET_VERSION
1265 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1269 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1270 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1271 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1273 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1274 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1277 /* By default, turn on GDB extensions. */
1278 #define DEFAULT_GDB_EXTENSIONS 1
1280 /* If we are passing smuggling stabs through the MIPS ECOFF object
1281 format, put a comment in front of the .stab<x> operation so
1282 that the MIPS assembler does not choke. The mips-tfile program
1283 will correctly put the stab into the object file. */
1285 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1286 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1287 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1289 /* Local compiler-generated symbols must have a prefix that the assembler
1290 understands. By default, this is $, although some targets (e.g.,
1291 NetBSD-ELF) need to override this. */
1293 #ifndef LOCAL_LABEL_PREFIX
1294 #define LOCAL_LABEL_PREFIX "$"
1297 /* By default on the mips, external symbols do not have an underscore
1298 prepended, but some targets (e.g., NetBSD) require this. */
1300 #ifndef USER_LABEL_PREFIX
1301 #define USER_LABEL_PREFIX ""
1304 /* Forward references to tags are allowed. */
1305 #define SDB_ALLOW_FORWARD_REFERENCES
1307 /* Unknown tags are also allowed. */
1308 #define SDB_ALLOW_UNKNOWN_REFERENCES
1310 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1311 since the length can run past this up to a continuation point. */
1312 #undef DBX_CONTIN_LENGTH
1313 #define DBX_CONTIN_LENGTH 1500
1315 /* How to renumber registers for dbx and gdb. */
1316 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1318 /* The mapping from gcc register number to DWARF 2 CFA column number.
1319 This mapping does not allow for tracking register 0, since SGI's broken
1320 dwarf reader thinks column 0 is used for the frame address, but since
1321 register 0 is fixed this is not a problem. */
1322 #define DWARF_FRAME_REGNUM(REG) \
1323 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1325 /* The DWARF 2 CFA column which tracks the return address. */
1326 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1328 /* Before the prologue, RA lives in r31. */
1329 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1331 /* Describe how we implement __builtin_eh_return. */
1332 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1333 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1335 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1336 The default for this in 64-bit mode is 8, which causes problems with
1337 SFmode register saves. */
1338 #define DWARF_CIE_DATA_ALIGNMENT 4
1340 #define FIND_BASE_TERM(X) mips_delegitimize_address (X)
1342 #define PUT_SDB_DEF(a) \
1344 fprintf (asm_out_file, "\t%s.def\t", \
1345 (TARGET_GAS) ? "" : "#"); \
1346 ASM_OUTPUT_LABELREF (asm_out_file, a); \
1347 fputc (';', asm_out_file); \
1350 #define PUT_SDB_PLAIN_DEF(a) \
1352 fprintf (asm_out_file, "\t%s.def\t.%s;", \
1353 (TARGET_GAS) ? "" : "#", (a)); \
1356 /* For block start and end, we create labels, so that
1357 later we can figure out where the correct offset is.
1358 The normal .ent/.end serve well enough for functions,
1359 so those are just commented out. */
1361 #define PUT_SDB_BLOCK_START(LINE) \
1363 fprintf (asm_out_file, \
1364 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1365 LOCAL_LABEL_PREFIX, \
1367 (TARGET_GAS) ? "" : "#", \
1368 LOCAL_LABEL_PREFIX, \
1371 sdb_label_count++; \
1374 #define PUT_SDB_BLOCK_END(LINE) \
1376 fprintf (asm_out_file, \
1377 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1378 LOCAL_LABEL_PREFIX, \
1380 (TARGET_GAS) ? "" : "#", \
1381 LOCAL_LABEL_PREFIX, \
1384 sdb_label_count++; \
1387 #define PUT_SDB_FUNCTION_START(LINE)
1389 #define PUT_SDB_FUNCTION_END(LINE) \
1391 ASM_OUTPUT_SOURCE_LINE (asm_out_file, LINE + sdb_begin_function_line); \
1394 #define PUT_SDB_EPILOGUE_END(NAME)
1396 /* Correct the offset of automatic variables and arguments. Note that
1397 the MIPS debug format wants all automatic variables and arguments
1398 to be in terms of the virtual frame pointer (stack pointer before
1399 any adjustment in the function), while the MIPS 3.0 linker wants
1400 the frame pointer to be the stack pointer after the initial
1403 #define DEBUGGER_AUTO_OFFSET(X) \
1404 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1405 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1406 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1408 /* Tell collect that the object format is ECOFF */
1409 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1410 #define EXTENDED_COFF /* ECOFF, not normal coff */
1412 /* Target machine storage layout */
1414 /* Define this if most significant bit is lowest numbered
1415 in instructions that operate on numbered bit-fields.
1417 #define BITS_BIG_ENDIAN 0
1419 /* Define this if most significant byte of a word is the lowest numbered. */
1420 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1422 /* Define this if most significant word of a multiword number is the lowest. */
1423 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1425 /* Define this to set the endianness to use in libgcc2.c, which can
1426 not depend on target_flags. */
1427 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1428 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1430 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1433 #define MAX_BITS_PER_WORD 64
1435 /* Width of a word, in units (bytes). */
1436 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1437 #define MIN_UNITS_PER_WORD 4
1439 /* For MIPS, width of a floating point register. */
1440 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1442 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1443 the next available register. */
1444 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1446 /* The largest size of value that can be held in floating-point
1447 registers and moved with a single instruction. */
1448 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1450 /* The largest size of value that can be held in floating-point
1452 #define UNITS_PER_FPVALUE \
1453 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1455 /* The number of bytes in a double. */
1456 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1458 /* A C expression for the size in bits of the type `int' on the
1459 target machine. If you don't define this, the default is one
1461 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1463 /* Tell the preprocessor the maximum size of wchar_t. */
1464 #ifndef MAX_WCHAR_TYPE_SIZE
1465 #ifndef WCHAR_TYPE_SIZE
1466 #define MAX_WCHAR_TYPE_SIZE 64
1470 /* A C expression for the size in bits of the type `short' on the
1471 target machine. If you don't define this, the default is half a
1472 word. (If this would be less than one storage unit, it is
1473 rounded up to one unit.) */
1474 #define SHORT_TYPE_SIZE 16
1476 /* A C expression for the size in bits of the type `long' on the
1477 target machine. If you don't define this, the default is one
1479 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1480 #define MAX_LONG_TYPE_SIZE 64
1482 /* A C expression for the size in bits of the type `long long' on the
1483 target machine. If you don't define this, the default is two
1485 #define LONG_LONG_TYPE_SIZE 64
1487 /* A C expression for the size in bits of the type `float' on the
1488 target machine. If you don't define this, the default is one
1490 #define FLOAT_TYPE_SIZE 32
1492 /* A C expression for the size in bits of the type `double' on the
1493 target machine. If you don't define this, the default is two
1495 #define DOUBLE_TYPE_SIZE 64
1497 /* A C expression for the size in bits of the type `long double' on
1498 the target machine. If you don't define this, the default is two
1500 #define LONG_DOUBLE_TYPE_SIZE \
1501 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1503 /* long double is not a fixed mode, but the idea is that, if we
1504 support long double, we also want a 128-bit integer type. */
1505 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1508 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1509 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1510 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1512 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1516 /* Width in bits of a pointer. */
1517 #ifndef POINTER_SIZE
1518 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1521 #define POINTERS_EXTEND_UNSIGNED 0
1523 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1524 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1525 || mips_abi == ABI_64 \
1526 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1529 /* Allocation boundary (in *bits*) for the code of a function. */
1530 #define FUNCTION_BOUNDARY 32
1532 /* Alignment of field after `int : 0' in a structure. */
1533 #define EMPTY_FIELD_BOUNDARY 32
1535 /* Every structure's size must be a multiple of this. */
1536 /* 8 is observed right on a DECstation and on riscos 4.02. */
1537 #define STRUCTURE_SIZE_BOUNDARY 8
1539 /* There is no point aligning anything to a rounder boundary than this. */
1540 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1542 /* Set this nonzero if move instructions will actually fail to work
1543 when given unaligned data. */
1544 #define STRICT_ALIGNMENT 1
1546 /* Define this if you wish to imitate the way many other C compilers
1547 handle alignment of bitfields and the structures that contain
1550 The behavior is that the type written for a bit-field (`int',
1551 `short', or other integer type) imposes an alignment for the
1552 entire structure, as if the structure really did contain an
1553 ordinary field of that type. In addition, the bit-field is placed
1554 within the structure so that it would fit within such a field,
1555 not crossing a boundary for it.
1557 Thus, on most machines, a bit-field whose type is written as `int'
1558 would not cross a four-byte boundary, and would force four-byte
1559 alignment for the whole structure. (The alignment used may not
1560 be four bytes; it is controlled by the other alignment
1563 If the macro is defined, its definition should be a C expression;
1564 a nonzero value for the expression enables this behavior. */
1566 #define PCC_BITFIELD_TYPE_MATTERS 1
1568 /* If defined, a C expression to compute the alignment given to a
1569 constant that is being placed in memory. CONSTANT is the constant
1570 and ALIGN is the alignment that the object would ordinarily have.
1571 The value of this macro is used instead of that alignment to align
1574 If this macro is not defined, then ALIGN is used.
1576 The typical use of this macro is to increase alignment for string
1577 constants to be word aligned so that `strcpy' calls that copy
1578 constants can be done inline. */
1580 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1581 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1582 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1584 /* If defined, a C expression to compute the alignment for a static
1585 variable. TYPE is the data type, and ALIGN is the alignment that
1586 the object would ordinarily have. The value of this macro is used
1587 instead of that alignment to align the object.
1589 If this macro is not defined, then ALIGN is used.
1591 One use of this macro is to increase alignment of medium-size
1592 data to make it all fit in fewer cache lines. Another is to
1593 cause character arrays to be word-aligned so that `strcpy' calls
1594 that copy constants to character arrays can be done inline. */
1596 #undef DATA_ALIGNMENT
1597 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1598 ((((ALIGN) < BITS_PER_WORD) \
1599 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1600 || TREE_CODE (TYPE) == UNION_TYPE \
1601 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1604 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1606 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1608 /* Define this macro if an argument declared as `char' or `short' in a
1609 prototype should actually be passed as an `int'. In addition to
1610 avoiding errors in certain cases of mismatch, it also makes for
1611 better code on certain machines. */
1613 #define PROMOTE_PROTOTYPES 1
1615 /* Define if operations between registers always perform the operation
1616 on the full register even if a narrower mode is specified. */
1617 #define WORD_REGISTER_OPERATIONS
1619 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1620 will either zero-extend or sign-extend. The value of this macro should
1621 be the code that says which one of the two operations is implicitly
1624 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1625 moves. All other referces are zero extended. */
1626 #define LOAD_EXTEND_OP(MODE) \
1627 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1628 ? SIGN_EXTEND : ZERO_EXTEND)
1630 /* Define this macro if it is advisable to hold scalars in registers
1631 in a wider mode than that declared by the program. In such cases,
1632 the value is constrained to be within the bounds of the declared
1633 type, but kept valid in the wider mode. The signedness of the
1634 extension may differ from that of the type. */
1636 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1637 if (GET_MODE_CLASS (MODE) == MODE_INT \
1638 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1640 if ((MODE) == SImode) \
1645 /* Define if loading short immediate values into registers sign extends. */
1646 #define SHORT_IMMEDIATES_SIGN_EXTEND
1649 /* Define this if function arguments should also be promoted using the above
1651 #define PROMOTE_FUNCTION_ARGS
1653 /* Likewise, if the function return value is promoted. */
1654 #define PROMOTE_FUNCTION_RETURN
1657 /* Standard register usage. */
1659 /* Number of actual hardware registers.
1660 The hardware registers are assigned numbers for the compiler
1661 from 0 to just below FIRST_PSEUDO_REGISTER.
1662 All registers that the compiler knows about must be given numbers,
1663 even those that are not normally considered general registers.
1665 On the Mips, we have 32 integer registers, 32 floating point
1666 registers, 8 condition code registers, and the special registers
1667 hi and lo. After that we have 32 COP0 registers, 32 COP2 registers,
1668 and 32 COP3 registers. (COP1 is the floating-point processor.)
1669 The 8 condition code registers are only used if mips_isa >= 4. */
1671 #define FIRST_PSEUDO_REGISTER 176
1673 /* 1 for registers that have pervasive standard uses
1674 and are not available for the register allocator.
1676 On the MIPS, see conventions, page D-2 */
1678 /* Regarding coprocessor registers: without evidence to the contrary,
1679 it's best to assume that each coprocessor register has a unique
1680 use. This can be overridden, in, e.g., override_options() or
1681 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1682 for a particular target. */
1684 #define FIXED_REGISTERS \
1686 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1687 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1688 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1689 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1690 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1691 /* COP0 registers */ \
1692 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1693 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1694 /* COP2 registers */ \
1695 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1696 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1697 /* COP3 registers */ \
1698 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1699 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1703 /* Don't mark $31 as a call-clobbered register. The idea is that
1704 it's really the call instructions themselves which clobber $31.
1705 We don't care what the called function does with it afterwards.
1707 This approach makes it easier to implement sibcalls. Unlike normal
1708 calls, sibcalls don't clobber $31, so the register reaches the
1709 called function in tact. EPILOGUE_USES says that $31 is useful
1710 to the called function. */
1712 #define CALL_USED_REGISTERS \
1714 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1715 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1716 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1717 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1718 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1719 /* COP0 registers */ \
1720 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1721 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1722 /* COP2 registers */ \
1723 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1724 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1725 /* COP3 registers */ \
1726 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1727 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1730 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1731 problem which makes CALL_USED_REGISTERS *always* include
1732 all the FIXED_REGISTERS. Until this problem has been
1733 resolved this macro can be used to overcome this situation.
1734 In particular, block_propagate() requires this list
1735 be acurate, or we can remove registers which should be live.
1736 This macro is used in regs_invalidated_by_call. */
1739 #define CALL_REALLY_USED_REGISTERS \
1740 { /* General registers. */ \
1741 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1742 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1743 /* Floating-point registers. */ \
1744 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1745 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1747 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1748 /* COP0 registers */ \
1749 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1750 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1751 /* COP2 registers */ \
1752 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1753 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1754 /* COP3 registers */ \
1755 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1756 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1759 /* Internal macros to classify a register number as to whether it's a
1760 general purpose register, a floating point register, a
1761 multiply/divide register, or a status register. */
1763 #define GP_REG_FIRST 0
1764 #define GP_REG_LAST 31
1765 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1766 #define GP_DBX_FIRST 0
1768 #define FP_REG_FIRST 32
1769 #define FP_REG_LAST 63
1770 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1771 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1773 #define MD_REG_FIRST 64
1774 #define MD_REG_LAST 65
1775 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1776 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1778 #define ST_REG_FIRST 67
1779 #define ST_REG_LAST 74
1780 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1783 /* FIXME: renumber. */
1784 #define COP0_REG_FIRST 80
1785 #define COP0_REG_LAST 111
1786 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1788 #define COP2_REG_FIRST 112
1789 #define COP2_REG_LAST 143
1790 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1792 #define COP3_REG_FIRST 144
1793 #define COP3_REG_LAST 175
1794 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1795 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1796 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1798 #define AT_REGNUM (GP_REG_FIRST + 1)
1799 #define HI_REGNUM (MD_REG_FIRST + 0)
1800 #define LO_REGNUM (MD_REG_FIRST + 1)
1802 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1803 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1804 should be used instead. */
1805 #define FPSW_REGNUM ST_REG_FIRST
1807 #define GP_REG_P(REGNO) \
1808 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1809 #define M16_REG_P(REGNO) \
1810 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1811 #define FP_REG_P(REGNO) \
1812 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1813 #define MD_REG_P(REGNO) \
1814 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1815 #define ST_REG_P(REGNO) \
1816 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1817 #define COP0_REG_P(REGNO) \
1818 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1819 #define COP2_REG_P(REGNO) \
1820 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1821 #define COP3_REG_P(REGNO) \
1822 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1823 #define ALL_COP_REG_P(REGNO) \
1824 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1826 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1828 /* Return coprocessor number from register number. */
1830 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1831 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1832 : COP3_REG_P (REGNO) ? '3' : '?')
1834 /* Return number of consecutive hard regs needed starting at reg REGNO
1835 to hold something of mode MODE.
1836 This is ordinarily the length in words of a value of mode MODE
1837 but can be less for certain modes in special long registers.
1839 On the MIPS, all general registers are one word long. Except on
1840 the R4000 with the FR bit set, the floating point uses register
1841 pairs, with the second register not being allocable. */
1843 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1845 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1846 MODE. In 32 bit mode, require that DImode and DFmode be in even
1847 registers. For DImode, this makes some of the insns easier to
1848 write, since you don't have to worry about a DImode value in
1849 registers 3 & 4, producing a result in 4 & 5.
1851 To make the code simpler HARD_REGNO_MODE_OK now just references an
1852 array built in override_options. Because machmodes.h is not yet
1853 included before this file is processed, the MODE bound can't be
1856 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1858 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1859 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1861 /* Value is 1 if it is a good idea to tie two pseudo registers
1862 when one has mode MODE1 and one has mode MODE2.
1863 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1864 for any hard reg, then this must be 0 for correct output. */
1865 #define MODES_TIEABLE_P(MODE1, MODE2) \
1866 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1867 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1868 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1869 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1871 /* MIPS pc is not overloaded on a register. */
1872 /* #define PC_REGNUM xx */
1874 /* Register to use for pushing function arguments. */
1875 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1877 /* Offset from the stack pointer to the first available location. Use
1878 the default value zero. */
1879 /* #define STACK_POINTER_OFFSET 0 */
1881 /* Base register for access to local variables of the function. We
1882 pretend that the frame pointer is $1, and then eliminate it to
1883 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1884 a fixed register, and will not be used for anything else. */
1885 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1887 /* Temporary scratch register for use by the assembler. */
1888 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1890 /* $30 is not available on the mips16, so we use $17 as the frame
1892 #define HARD_FRAME_POINTER_REGNUM \
1893 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1895 /* Value should be nonzero if functions must have frame pointers.
1896 Zero means the frame pointer need not be set up (and parms
1897 may be accessed via the stack pointer) in functions that seem suitable.
1898 This is computed in `reload', in reload1.c. */
1899 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1901 /* Base register for access to arguments of the function. */
1902 #define ARG_POINTER_REGNUM GP_REG_FIRST
1904 /* Register in which static-chain is passed to a function. */
1905 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1907 /* If the structure value address is passed in a register, then
1908 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1909 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1911 /* If the structure value address is not passed in a register, define
1912 `STRUCT_VALUE' as an expression returning an RTX for the place
1913 where the address is passed. If it returns 0, the address is
1914 passed as an "invisible" first argument. */
1915 #define STRUCT_VALUE 0
1917 /* Mips registers used in prologue/epilogue code when the stack frame
1918 is larger than 32K bytes. These registers must come from the
1919 scratch register set, and not used for passing and returning
1920 arguments and any other information used in the calling sequence
1921 (such as pic). Must start at 12, since t0/t3 are parameter passing
1922 registers in the 64 bit ABI. */
1924 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1925 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1927 /* Define this macro if it is as good or better to call a constant
1928 function address than to call an address kept in a register. */
1929 #define NO_FUNCTION_CSE 1
1931 /* Define this macro if it is as good or better for a function to
1932 call itself with an explicit address than to call an address
1933 kept in a register. */
1934 #define NO_RECURSIVE_FUNCTION_CSE 1
1936 /* The ABI-defined global pointer. Sometimes we use a different
1937 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1938 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1940 /* We normally use $28 as the global pointer. However, when generating
1941 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1942 register instead. They can then avoid saving and restoring $28
1943 and perhaps avoid using a frame at all.
1945 When a leaf function uses something other than $28, mips_expand_prologue
1946 will modify pic_offset_table_rtx in place. Take the register number
1947 from there after reload. */
1948 #define PIC_OFFSET_TABLE_REGNUM \
1949 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1951 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1953 /* Define the classes of registers for register constraints in the
1954 machine description. Also define ranges of constants.
1956 One of the classes must always be named ALL_REGS and include all hard regs.
1957 If there is more than one class, another class must be named NO_REGS
1958 and contain no registers.
1960 The name GENERAL_REGS must be the name of a class (or an alias for
1961 another name such as ALL_REGS). This is the class of registers
1962 that is allowed by "g" or "r" in a register constraint.
1963 Also, registers outside this class are allocated only when
1964 instructions express preferences for them.
1966 The classes must be numbered in nondecreasing order; that is,
1967 a larger-numbered class must never be contained completely
1968 in a smaller-numbered class.
1970 For any two classes, it is very desirable that there be another
1971 class that represents their union. */
1975 NO_REGS, /* no registers in set */
1976 M16_NA_REGS, /* mips16 regs not used to pass args */
1977 M16_REGS, /* mips16 directly accessible registers */
1978 T_REG, /* mips16 T register ($24) */
1979 M16_T_REGS, /* mips16 registers plus T register */
1980 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1981 LEA_REGS, /* Every GPR except $25 */
1982 GR_REGS, /* integer registers */
1983 FP_REGS, /* floating point registers */
1984 HI_REG, /* hi register */
1985 LO_REG, /* lo register */
1986 MD_REGS, /* multiply/divide registers (hi/lo) */
1987 COP0_REGS, /* generic coprocessor classes */
1990 HI_AND_GR_REGS, /* union classes */
1997 ALL_COP_AND_GR_REGS,
1998 ST_REGS, /* status registers (fp status) */
1999 ALL_REGS, /* all registers */
2000 LIM_REG_CLASSES /* max value + 1 */
2003 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2005 #define GENERAL_REGS GR_REGS
2007 /* An initializer containing the names of the register classes as C
2008 string constants. These names are used in writing some of the
2011 #define REG_CLASS_NAMES \
2018 "PIC_FN_ADDR_REG", \
2025 /* coprocessor registers */ \
2032 "COP0_AND_GR_REGS", \
2033 "COP2_AND_GR_REGS", \
2034 "COP3_AND_GR_REGS", \
2036 "ALL_COP_AND_GR_REGS", \
2041 /* An initializer containing the contents of the register classes,
2042 as integers which are bit masks. The Nth integer specifies the
2043 contents of class N. The way the integer MASK is interpreted is
2044 that register R is in the class if `MASK & (1 << R)' is 1.
2046 When the machine has more than 32 registers, an integer does not
2047 suffice. Then the integers are replaced by sub-initializers,
2048 braced groupings containing several integers. Each
2049 sub-initializer must be suitable as an initializer for the type
2050 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2052 #define REG_CLASS_CONTENTS \
2054 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2055 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2056 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2057 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2058 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2059 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
2060 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
2061 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2062 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2063 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2064 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2065 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2066 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2067 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2068 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2069 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2070 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2071 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2072 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2073 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2074 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2075 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2076 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2077 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2078 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2082 /* A C expression whose value is a register class containing hard
2083 register REGNO. In general there is more that one such class;
2084 choose a class which is "minimal", meaning that no smaller class
2085 also contains the register. */
2087 extern const enum reg_class mips_regno_to_class[];
2089 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2091 /* A macro whose definition is the name of the class to which a
2092 valid base register must belong. A base register is one used in
2093 an address which is the register value plus a displacement. */
2095 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2097 /* A macro whose definition is the name of the class to which a
2098 valid index register must belong. An index register is one used
2099 in an address where its value is either multiplied by a scale
2100 factor or added to another register (as well as added to a
2103 #define INDEX_REG_CLASS NO_REGS
2105 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2106 registers explicitly used in the rtl to be used as spill registers
2107 but prevents the compiler from extending the lifetime of these
2110 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2112 /* This macro is used later on in the file. */
2113 #define GR_REG_CLASS_P(CLASS) \
2114 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2115 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
2116 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
2118 /* This macro is also used later on in the file. */
2119 #define COP_REG_CLASS_P(CLASS) \
2120 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2122 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2123 is the default value (allocate the registers in numeric order). We
2124 define it just so that we can override it for the mips16 target in
2125 ORDER_REGS_FOR_LOCAL_ALLOC. */
2127 #define REG_ALLOC_ORDER \
2128 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2129 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2130 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2131 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2132 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2133 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2134 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2135 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2136 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2137 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2138 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2141 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2142 to be rearranged based on a particular function. On the mips16, we
2143 want to allocate $24 (T_REG) before other registers for
2144 instructions for which it is possible. */
2146 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2148 /* REGISTER AND CONSTANT CLASSES */
2150 /* Get reg_class from a letter such as appears in the machine
2153 DEFINED REGISTER CLASSES:
2155 'd' General (aka integer) registers
2156 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2157 'y' General registers (in both mips16 and non mips16 mode)
2158 'e' mips16 non argument registers (M16_NA_REGS)
2159 't' mips16 temporary register ($24)
2160 'f' Floating point registers
2163 'x' Multiply/divide registers
2164 'z' FP Status register
2168 'b' All registers */
2170 extern enum reg_class mips_char_to_class[256];
2172 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2174 /* True if VALUE is a signed 16-bit number. */
2176 #define SMALL_OPERAND(VALUE) \
2177 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2179 /* True if VALUE is an unsigned 16-bit number. */
2181 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2182 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2184 /* True if VALUE can be loaded into a register using LUI. */
2186 #define LUI_OPERAND(VALUE) \
2187 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2188 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2190 /* Return a value X with the low 16 bits clear, and such that
2191 VALUE - X is a signed 16-bit value. */
2193 #define CONST_HIGH_PART(VALUE) \
2194 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2196 #define CONST_LOW_PART(VALUE) \
2197 ((VALUE) - CONST_HIGH_PART (VALUE))
2199 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2200 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2201 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2203 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2204 string can be used to stand for particular ranges of immediate
2205 operands. This macro defines what the ranges are. C is the
2206 letter, and VALUE is a constant value. Return 1 if VALUE is
2207 in the range specified by C. */
2211 `I' is used for the range of constants an arithmetic insn can
2212 actually contain (16 bits signed integers).
2214 `J' is used for the range which is just zero (ie, $r0).
2216 `K' is used for the range of constants a logical insn can actually
2217 contain (16 bit zero-extended integers).
2219 `L' is used for the range of constants that be loaded with lui
2220 (ie, the bottom 16 bits are zero).
2222 `M' is used for the range of constants that take two words to load
2223 (ie, not matched by `I', `K', and `L').
2225 `N' is used for negative 16 bit constants other than -65536.
2227 `O' is a 15 bit signed integer.
2229 `P' is used for positive 16 bit constants. */
2231 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2232 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2233 : (C) == 'J' ? ((VALUE) == 0) \
2234 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2235 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2236 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2237 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2238 && !LUI_OPERAND (VALUE)) \
2239 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2240 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2241 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2244 /* Similar, but for floating constants, and defining letters G and H.
2245 Here VALUE is the CONST_DOUBLE rtx itself. */
2249 'G' : Floating point 0 */
2251 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2253 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2255 /* True if OP is a constant that should not be moved into $25.
2256 We need this because many versions of gas treat 'la $25,foo' as
2257 part of a call sequence and allow a global 'foo' to be lazily bound. */
2259 #define DANGEROUS_FOR_LA25_P(OP) \
2261 && !TARGET_EXPLICIT_RELOCS \
2262 && mips_global_pic_constant_p (OP))
2264 /* Letters in the range `Q' through `U' may be defined in a
2265 machine-dependent fashion to stand for arbitrary operand types.
2266 The machine description macro `EXTRA_CONSTRAINT' is passed the
2267 operand as its first argument and the constraint letter as its
2270 `Q' is for signed 16-bit constants.
2271 `R' is for single-instruction memory references. Note that this
2272 constraint has often been used in linux and glibc code.
2273 `S' is for legitimate constant call addresses.
2274 `T' is for constant move_operands that cannot be safely loaded into $25.
2275 `U' is for constant move_operands that can be safely loaded into $25. */
2277 #define EXTRA_CONSTRAINT(OP,CODE) \
2278 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2279 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2280 && mips_fetch_insns (OP) == 1) \
2281 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2282 && call_insn_operand (OP, VOIDmode)) \
2283 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2284 && move_operand (OP, VOIDmode) \
2285 && DANGEROUS_FOR_LA25_P (OP)) \
2286 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2287 && move_operand (OP, VOIDmode) \
2288 && !DANGEROUS_FOR_LA25_P (OP)) \
2291 /* Given an rtx X being reloaded into a reg required to be
2292 in class CLASS, return the class of reg to actually use.
2293 In general this is just CLASS; but on some machines
2294 in some cases it is preferable to use a more restrictive class. */
2296 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2297 ((CLASS) != ALL_REGS \
2298 ? (! TARGET_MIPS16 \
2300 : ((CLASS) != GR_REGS \
2303 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2304 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2305 ? (TARGET_SOFT_FLOAT \
2306 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2308 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2309 || GET_MODE (X) == VOIDmode) \
2310 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2313 /* Certain machines have the property that some registers cannot be
2314 copied to some other registers without using memory. Define this
2315 macro on those machines to be a C expression that is nonzero if
2316 objects of mode MODE in registers of CLASS1 can only be copied to
2317 registers of class CLASS2 by storing a register of CLASS1 into
2318 memory and loading that memory location into a register of CLASS2.
2320 Do not define this macro if its value would always be zero. */
2322 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2323 ((!TARGET_DEBUG_H_MODE \
2324 && GET_MODE_CLASS (MODE) == MODE_INT \
2325 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2326 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2327 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2328 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2329 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2331 /* The HI and LO registers can only be reloaded via the general
2332 registers. Condition code registers can only be loaded to the
2333 general registers, and from the floating point registers. */
2335 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2336 mips_secondary_reload_class (CLASS, MODE, X, 1)
2337 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2338 mips_secondary_reload_class (CLASS, MODE, X, 0)
2340 /* Return the maximum number of consecutive registers
2341 needed to represent mode MODE in a register of class CLASS. */
2343 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2345 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2346 mips_cannot_change_mode_class (FROM, TO, CLASS)
2348 /* Stack layout; function entry, exit and calling. */
2350 #define STACK_GROWS_DOWNWARD
2352 /* The offset of the first local variable from the beginning of the frame.
2353 See compute_frame_size for details about the frame layout. */
2354 #define STARTING_FRAME_OFFSET \
2355 (current_function_outgoing_args_size \
2356 + (TARGET_ABICALLS && !TARGET_NEWABI \
2357 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2359 /* Offset from the stack pointer register to an item dynamically
2360 allocated on the stack, e.g., by `alloca'.
2362 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2363 length of the outgoing arguments. The default is correct for most
2364 machines. See `function.c' for details.
2366 The MIPS ABI states that functions which dynamically allocate the
2367 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2368 we are trying to create a second frame pointer to the function, so
2369 allocate some stack space to make it happy.
2371 However, the linker currently complains about linking any code that
2372 dynamically allocates stack space, and there seems to be a bug in
2373 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2376 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2377 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2378 ? 4*UNITS_PER_WORD \
2379 : current_function_outgoing_args_size)
2382 /* The return address for the current frame is in r31 if this is a leaf
2383 function. Otherwise, it is on the stack. It is at a variable offset
2384 from sp/fp/ap, so we define a fake hard register rap which is a
2385 poiner to the return address on the stack. This always gets eliminated
2386 during reload to be either the frame pointer or the stack pointer plus
2389 #define RETURN_ADDR_RTX mips_return_addr
2391 /* Since the mips16 ISA mode is encoded in the least-significant bit
2392 of the address, mask it off return addresses for purposes of
2393 finding exception handling regions. */
2395 #define MASK_RETURN_ADDR GEN_INT (-2)
2398 /* Similarly, don't use the least-significant bit to tell pointers to
2399 code from vtable index. */
2401 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2403 /* If defined, this macro specifies a table of register pairs used to
2404 eliminate unneeded registers that point into the stack frame. If
2405 it is not defined, the only elimination attempted by the compiler
2406 is to replace references to the frame pointer with references to
2409 The definition of this macro is a list of structure
2410 initializations, each of which specifies an original and
2411 replacement register.
2413 On some machines, the position of the argument pointer is not
2414 known until the compilation is completed. In such a case, a
2415 separate hard register must be used for the argument pointer.
2416 This register can be eliminated by replacing it with either the
2417 frame pointer or the argument pointer, depending on whether or not
2418 the frame pointer has been eliminated.
2420 In this case, you might specify:
2421 #define ELIMINABLE_REGS \
2422 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2423 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2424 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2426 Note that the elimination of the argument pointer with the stack
2427 pointer is specified first since that is the preferred elimination.
2429 The eliminations to $17 are only used on the mips16. See the
2430 definition of HARD_FRAME_POINTER_REGNUM. */
2432 #define ELIMINABLE_REGS \
2433 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2434 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2435 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2436 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2437 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2438 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2440 /* A C expression that returns nonzero if the compiler is allowed to
2441 try to replace register number FROM-REG with register number
2442 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2443 defined, and will usually be the constant 1, since most of the
2444 cases preventing register elimination are things that the compiler
2445 already knows about.
2447 When not in mips16 and mips64, we can always eliminate to the
2448 frame pointer. We can eliminate to the stack pointer unless
2449 a frame pointer is needed. In mips16 mode, we need a frame
2450 pointer for a large frame; otherwise, reload may be unable
2451 to compute the address of a local variable, since there is
2452 no way to add a large constant to the stack pointer
2453 without using a temporary register.
2455 In mips16, for some instructions (eg lwu), we can't eliminate the
2456 frame pointer for the stack pointer. These instructions are
2457 only generated in TARGET_64BIT mode.
2460 #define CAN_ELIMINATE(FROM, TO) \
2461 (((TO) == HARD_FRAME_POINTER_REGNUM \
2462 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2463 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2464 && (! TARGET_MIPS16 \
2465 || compute_frame_size (get_frame_size ()) < 32768))))
2467 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2468 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2470 /* If we generate an insn to push BYTES bytes,
2471 this says how many the stack pointer really advances by.
2472 On the VAX, sp@- in a byte insn really pushes a word. */
2474 /* #define PUSH_ROUNDING(BYTES) 0 */
2476 /* If defined, the maximum amount of space required for outgoing
2477 arguments will be computed and placed into the variable
2478 `current_function_outgoing_args_size'. No space will be pushed
2479 onto the stack for each call; instead, the function prologue
2480 should increase the stack frame size by this amount.
2482 It is not proper to define both `PUSH_ROUNDING' and
2483 `ACCUMULATE_OUTGOING_ARGS'. */
2484 #define ACCUMULATE_OUTGOING_ARGS 1
2486 /* Offset from the argument pointer register to the first argument's
2487 address. On some machines it may depend on the data type of the
2490 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2491 the first argument's address.
2493 On the MIPS, we must skip the first argument position if we are
2494 returning a structure or a union, to account for its address being
2495 passed in $4. However, at the current time, this produces a compiler
2496 that can't bootstrap, so comment it out for now. */
2499 #define FIRST_PARM_OFFSET(FNDECL) \
2501 && TREE_TYPE (FNDECL) != 0 \
2502 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2503 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2504 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2508 #define FIRST_PARM_OFFSET(FNDECL) 0
2511 /* When a parameter is passed in a register, stack space is still
2512 allocated for it. For the MIPS, stack space must be allocated, cf
2513 Asm Lang Prog Guide page 7-8.
2515 BEWARE that some space is also allocated for non existing arguments
2516 in register. In case an argument list is of form GF used registers
2517 are a0 (a2,a3), but we should push over a1... */
2519 #define REG_PARM_STACK_SPACE(FNDECL) \
2520 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2521 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2524 /* Define this if it is the responsibility of the caller to
2525 allocate the area reserved for arguments passed in registers.
2526 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2527 of this macro is to determine whether the space is included in
2528 `current_function_outgoing_args_size'. */
2529 #define OUTGOING_REG_PARM_STACK_SPACE
2531 #define STACK_BOUNDARY \
2532 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2535 /* Make sure 4 words are always allocated on the stack. */
2537 #ifndef STACK_ARGS_ADJUST
2538 #define STACK_ARGS_ADJUST(SIZE) \
2540 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2541 SIZE.constant = 4 * UNITS_PER_WORD; \
2546 /* A C expression that should indicate the number of bytes of its
2547 own arguments that a function pops on returning, or 0
2548 if the function pops no arguments and the caller must therefore
2549 pop them all after the function returns.
2551 FUNDECL is the declaration node of the function (as a tree).
2553 FUNTYPE is a C variable whose value is a tree node that
2554 describes the function in question. Normally it is a node of
2555 type `FUNCTION_TYPE' that describes the data type of the function.
2556 From this it is possible to obtain the data types of the value
2557 and arguments (if known).
2559 When a call to a library function is being considered, FUNTYPE
2560 will contain an identifier node for the library function. Thus,
2561 if you need to distinguish among various library functions, you
2562 can do so by their names. Note that "library function" in this
2563 context means a function used to perform arithmetic, whose name
2564 is known specially in the compiler and was not mentioned in the
2565 C code being compiled.
2567 STACK-SIZE is the number of bytes of arguments passed on the
2568 stack. If a variable number of bytes is passed, it is zero, and
2569 argument popping will always be the responsibility of the
2570 calling function. */
2572 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2575 /* Symbolic macros for the registers used to return integer and floating
2578 #define GP_RETURN (GP_REG_FIRST + 2)
2579 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2581 #define MAX_ARGS_IN_REGISTERS \
2582 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2584 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2586 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2588 /* Symbolic macros for the first/last argument registers. */
2590 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2591 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2592 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2593 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2595 /* Define how to find the value returned by a library function
2596 assuming the value has mode MODE. Because we define
2597 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2598 PROMOTE_MODE does. */
2600 #define LIBCALL_VALUE(MODE) \
2601 mips_function_value (NULL_TREE, NULL, (MODE))
2603 /* Define how to find the value returned by a function.
2604 VALTYPE is the data type of the value (as a tree).
2605 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2606 otherwise, FUNC is 0. */
2608 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2609 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2611 /* 1 if N is a possible register number for a function value.
2612 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2613 Currently, R2 and F0 are only implemented here (C has no complex type) */
2615 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2616 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2617 && (N) == FP_RETURN + 2))
2619 /* 1 if N is a possible register number for function argument passing.
2620 We have no FP argument registers when soft-float. When FP registers
2621 are 32 bits, we can't directly reference the odd numbered ones. */
2623 #define FUNCTION_ARG_REGNO_P(N) \
2624 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2625 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2626 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2629 /* A C expression which can inhibit the returning of certain function
2630 values in registers, based on the type of value. A nonzero value says
2631 to return the function value in memory, just as large structures are
2632 always returned. Here TYPE will be a C expression of type
2633 `tree', representing the data type of the value.
2635 Note that values of mode `BLKmode' must be explicitly
2636 handled by this macro. Also, the option `-fpcc-struct-return'
2637 takes effect regardless of this macro. On most systems, it is
2638 possible to leave the macro undefined; this causes a default
2639 definition to be used, whose value is the constant 1 for BLKmode
2640 values, and 0 otherwise.
2642 GCC normally converts 1 byte structures into chars, 2 byte
2643 structs into shorts, and 4 byte structs into ints, and returns
2644 them this way. Defining the following macro overrides this,
2645 to give us MIPS cc compatibility. */
2647 #define RETURN_IN_MEMORY(TYPE) \
2648 mips_return_in_memory (TYPE)
2650 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2651 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2654 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2656 /* Define a data type for recording info about an argument list
2657 during the scan of that argument list. This data type should
2658 hold all necessary information about the function itself
2659 and about the args processed so far, enough to enable macros
2660 such as FUNCTION_ARG to determine where the next arg should go.
2662 This structure has to cope with two different argument allocation
2663 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2664 first N words go in registers and the rest go on the stack. If I < N,
2665 the Ith word might go in Ith integer argument register or the
2666 Ith floating-point one. In some cases, it has to go in both (see
2667 function_arg). For these ABIs, we only need to remember the number
2668 of words passed so far.
2670 The EABI instead allocates the integer and floating-point arguments
2671 separately. The first N words of FP arguments go in FP registers,
2672 the rest go on the stack. Likewise, the first N words of the other
2673 arguments go in integer registers, and the rest go on the stack. We
2674 need to maintain three counts: the number of integer registers used,
2675 the number of floating-point registers used, and the number of words
2676 passed on the stack.
2678 We could keep separate information for the two ABIs (a word count for
2679 the standard ABIs, and three separate counts for the EABI). But it
2680 seems simpler to view the standard ABIs as forms of EABI that do not
2681 allocate floating-point registers.
2683 So for the standard ABIs, the first N words are allocated to integer
2684 registers, and function_arg decides on an argument-by-argument basis
2685 whether that argument should really go in an integer register, or in
2686 a floating-point one. */
2688 typedef struct mips_args {
2689 /* Always true for varargs functions. Otherwise true if at least
2690 one argument has been passed in an integer register. */
2693 /* The number of arguments seen so far. */
2694 unsigned int arg_number;
2696 /* For EABI, the number of integer registers used so far. For other
2697 ABIs, the number of words passed in registers (whether integer
2698 or floating-point). */
2699 unsigned int num_gprs;
2701 /* For EABI, the number of floating-point registers used so far. */
2702 unsigned int num_fprs;
2704 /* The number of words passed on the stack. */
2705 unsigned int stack_words;
2707 /* On the mips16, we need to keep track of which floating point
2708 arguments were passed in general registers, but would have been
2709 passed in the FP regs if this were a 32 bit function, so that we
2710 can move them to the FP regs if we wind up calling a 32 bit
2711 function. We record this information in fp_code, encoded in base
2712 four. A zero digit means no floating point argument, a one digit
2713 means an SFmode argument, and a two digit means a DFmode argument,
2714 and a three digit is not used. The low order digit is the first
2715 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2716 an SFmode argument. ??? A more sophisticated approach will be
2717 needed if MIPS_ABI != ABI_32. */
2720 /* True if the function has a prototype. */
2723 /* When a structure does not take up a full register, the argument
2724 should sometimes be shifted left so that it occupies the high part
2725 of the register. These two fields describe an array of ashl
2726 patterns for doing this. See function_arg_advance, which creates
2727 the shift patterns, and function_arg, which returns them when given
2728 a VOIDmode argument. */
2729 unsigned int num_adjusts;
2730 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2733 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2734 for a call to a function whose data type is FNTYPE.
2735 For a library call, FNTYPE is 0.
2739 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2740 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2742 /* Update the data in CUM to advance over an argument
2743 of mode MODE and data type TYPE.
2744 (TYPE is null for libcalls where that information may not be available.) */
2746 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2747 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2749 /* Determine where to put an argument to a function.
2750 Value is zero to push the argument on the stack,
2751 or a hard register in which to store the argument.
2753 MODE is the argument's machine mode.
2754 TYPE is the data type of the argument (as a tree).
2755 This is null for libcalls where that information may
2757 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2758 the preceding args and about the function being called.
2759 NAMED is nonzero if this argument is a named parameter
2760 (otherwise it is an extra parameter matching an ellipsis). */
2762 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2763 function_arg( &CUM, MODE, TYPE, NAMED)
2765 /* For an arg passed partly in registers and partly in memory,
2766 this is the number of registers used.
2767 For args passed entirely in registers or entirely in memory, zero. */
2769 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2770 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2772 /* If defined, a C expression that gives the alignment boundary, in
2773 bits, of an argument with the specified mode and type. If it is
2774 not defined, `PARM_BOUNDARY' is used for all arguments. */
2776 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2778 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2780 : TYPE_ALIGN(TYPE)) \
2781 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2783 : GET_MODE_ALIGNMENT(MODE)))
2785 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2786 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2788 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2789 (! BYTES_BIG_ENDIAN \
2791 : (((MODE) == BLKmode \
2792 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2793 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2794 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2795 && (mips_abi == ABI_32 \
2796 || mips_abi == ABI_O64 \
2797 || mips_abi == ABI_EABI \
2798 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2799 ? downward : upward))
2801 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2802 (mips_abi == ABI_EABI && (NAMED) \
2803 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2805 /* Modified version of the macro in expr.h. */
2806 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2808 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2809 || TREE_ADDRESSABLE (TYPE) \
2810 || ((MODE) == BLKmode \
2811 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2812 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2813 && 0 == (int_size_in_bytes (TYPE) \
2814 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2815 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2816 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2818 /* True if using EABI and varargs can be passed in floating-point
2819 registers. Under these conditions, we need a more complex form
2820 of va_list, which tracks GPR, FPR and stack arguments separately. */
2821 #define EABI_FLOAT_VARARGS_P \
2822 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2825 /* Say that the epilogue uses the return address register. Note that
2826 in the case of sibcalls, the values "used by the epilogue" are
2827 considered live at the start of the called function. */
2828 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2830 /* Treat LOC as a byte offset from the stack pointer and round it up
2831 to the next fully-aligned offset. */
2832 #define MIPS_STACK_ALIGN(LOC) \
2833 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2834 ? ((LOC) + 7) & ~7 \
2835 : ((LOC) + 15) & ~15)
2838 /* Define the `__builtin_va_list' type for the ABI. */
2839 #define BUILD_VA_LIST_TYPE(VALIST) \
2840 (VALIST) = mips_build_va_list ()
2842 /* Implement `va_start' for varargs and stdarg. */
2843 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2844 mips_va_start (valist, nextarg)
2846 /* Implement `va_arg'. */
2847 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2848 mips_va_arg (valist, type)
2850 /* Output assembler code to FILE to increment profiler label # LABELNO
2851 for profiling a function entry. */
2853 #define FUNCTION_PROFILER(FILE, LABELNO) \
2855 if (TARGET_MIPS16) \
2856 sorry ("mips16 function profiling"); \
2857 fprintf (FILE, "\t.set\tnoat\n"); \
2858 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2859 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2860 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2863 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2864 TARGET_64BIT ? "dsubu" : "subu", \
2865 reg_names[STACK_POINTER_REGNUM], \
2866 reg_names[STACK_POINTER_REGNUM], \
2867 Pmode == DImode ? 16 : 8); \
2869 fprintf (FILE, "\tjal\t_mcount\n"); \
2870 fprintf (FILE, "\t.set\tat\n"); \
2873 /* Define this macro if the code for function profiling should come
2874 before the function prologue. Normally, the profiling code comes
2877 /* #define PROFILE_BEFORE_PROLOGUE */
2879 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2880 the stack pointer does not matter. The value is tested only in
2881 functions that have frame pointers.
2882 No definition is equivalent to always zero. */
2884 #define EXIT_IGNORE_STACK 1
2887 /* A C statement to output, on the stream FILE, assembler code for a
2888 block of data that contains the constant parts of a trampoline.
2889 This code should not include a label--the label is taken care of
2892 #define TRAMPOLINE_TEMPLATE(STREAM) \
2894 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2895 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2896 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2897 if (ptr_mode == DImode) \
2899 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2900 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2904 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2905 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2907 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2908 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2909 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2910 if (ptr_mode == DImode) \
2912 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2913 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2917 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2918 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2922 /* A C expression for the size in bytes of the trampoline, as an
2925 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2927 /* Alignment required for trampolines, in bits. */
2929 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2931 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2932 program and data caches. */
2934 #ifndef CACHE_FLUSH_FUNC
2935 #define CACHE_FLUSH_FUNC "_flush_cache"
2938 /* A C statement to initialize the variable parts of a trampoline.
2939 ADDR is an RTX for the address of the trampoline; FNADDR is an
2940 RTX for the address of the nested function; STATIC_CHAIN is an
2941 RTX for the static chain value that should be passed to the
2942 function when it is called. */
2944 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2946 rtx func_addr, chain_addr; \
2948 func_addr = plus_constant (ADDR, 32); \
2949 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2950 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
2951 gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
2952 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
2953 gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
2955 /* Flush both caches. We need to flush the data cache in case \
2956 the system has a write-back cache. */ \
2957 /* ??? Should check the return value for errors. */ \
2958 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2959 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2960 0, VOIDmode, 3, ADDR, Pmode, \
2961 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2962 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2965 /* Addressing modes, and classification of registers for them. */
2967 /* These assume that REGNO is a hard or pseudo reg number.
2968 They give nonzero only if REGNO is a hard reg of the suitable class
2969 or a pseudo reg currently allocated to a suitable hard reg.
2970 These definitions are NOT overridden anywhere. */
2972 #define BASE_REG_P(regno, mode) \
2974 ? (M16_REG_P (regno) \
2975 || (regno) == FRAME_POINTER_REGNUM \
2976 || (regno) == ARG_POINTER_REGNUM \
2977 || ((regno) == STACK_POINTER_REGNUM \
2978 && (GET_MODE_SIZE (mode) == 4 \
2979 || GET_MODE_SIZE (mode) == 8))) \
2982 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2983 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2986 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2987 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2989 #define REGNO_OK_FOR_INDEX_P(regno) 0
2990 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2991 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2993 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2994 and check its validity for a certain class.
2995 We have two alternate definitions for each of them.
2996 The usual definition accepts all pseudo regs; the other rejects them all.
2997 The symbol REG_OK_STRICT causes the latter definition to be used.
2999 Most source files want to accept pseudo regs in the hope that
3000 they will get allocated to the class that the insn wants them to be in.
3001 Some source files that are used after register allocation
3002 need to be strict. */
3004 #ifndef REG_OK_STRICT
3005 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3006 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3008 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3009 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3012 #define REG_OK_FOR_INDEX_P(X) 0
3015 /* Maximum number of registers that can appear in a valid memory address. */
3017 #define MAX_REGS_PER_ADDRESS 1
3019 /* A C compound statement with a conditional `goto LABEL;' executed
3020 if X (an RTX) is a legitimate memory address on the target
3021 machine for a memory operand of mode MODE. */
3024 #define GO_PRINTF(x) fprintf(stderr, (x))
3025 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3026 #define GO_DEBUG_RTX(x) debug_rtx(x)
3029 #define GO_PRINTF(x)
3030 #define GO_PRINTF2(x,y)
3031 #define GO_DEBUG_RTX(x)
3034 #ifdef REG_OK_STRICT
3035 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3037 if (mips_legitimate_address_p (MODE, X, 1)) \
3041 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3043 if (mips_legitimate_address_p (MODE, X, 0)) \
3048 /* Check for constness inline but use mips_legitimate_address_p
3049 to check whether a constant really is an address. */
3051 #define CONSTANT_ADDRESS_P(X) \
3052 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
3055 /* Nonzero if the constant value X is a legitimate general operand.
3056 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3058 At present, GAS doesn't understand li.[sd], so don't allow it
3059 to be generated at present. Also, the MIPS assembler does not
3060 grok li.d Infinity. */
3062 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3063 Note that the Irix 6 assembler problem may already be fixed.
3064 Note also that the GET_CODE (X) == CONST test catches the mips16
3065 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3066 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3067 ABI_64 to work together, we'll need to fix this. */
3068 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
3070 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3072 if (mips_legitimize_address (&(X), MODE)) \
3077 /* A C statement or compound statement with a conditional `goto
3078 LABEL;' executed if memory address X (an RTX) can have different
3079 meanings depending on the machine mode of the memory reference it
3082 Autoincrement and autodecrement addresses typically have
3083 mode-dependent effects because the amount of the increment or
3084 decrement is the size of the operand being addressed. Some
3085 machines have other mode-dependent addresses. Many RISC machines
3086 have no mode-dependent addresses.
3088 You may assume that ADDR is a valid address for the machine. */
3090 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3092 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3093 'the start of the function that this code is output in'. */
3095 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3096 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3097 asm_fprintf ((FILE), "%U%s", \
3098 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3100 asm_fprintf ((FILE), "%U%s", (NAME))
3102 /* The mips16 wants the constant pool to be after the function,
3103 because the PC relative load instructions use unsigned offsets. */
3105 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3107 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3108 mips_string_length = 0;
3110 /* Specify the machine mode that this machine uses
3111 for the index in the tablejump instruction.
3112 ??? Using HImode in mips16 mode can cause overflow. However, the
3113 overflow is no more likely than the overflow in a branch
3114 instruction. Large functions can currently break in both ways. */
3115 #define CASE_VECTOR_MODE \
3116 (TARGET_MIPS16 ? HImode : ptr_mode)
3118 /* Define as C expression which evaluates to nonzero if the tablejump
3119 instruction expects the table to contain offsets from the address of the
3121 Do not define this if the table should contain absolute addresses. */
3122 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3124 /* Define this as 1 if `char' should by default be signed; else as 0. */
3125 #ifndef DEFAULT_SIGNED_CHAR
3126 #define DEFAULT_SIGNED_CHAR 1
3129 /* Max number of bytes we can move from memory to memory
3130 in one reasonably fast instruction. */
3131 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3132 #define MAX_MOVE_MAX 8
3134 /* Define this macro as a C expression which is nonzero if
3135 accessing less than a word of memory (i.e. a `char' or a
3136 `short') is no faster than accessing a word of memory, i.e., if
3137 such access require more than one instruction or if there is no
3138 difference in cost between byte and (aligned) word loads.
3140 On RISC machines, it tends to generate better code to define
3141 this as 1, since it avoids making a QI or HI mode register. */
3142 #define SLOW_BYTE_ACCESS 1
3144 /* Define this to be nonzero if shift instructions ignore all but the low-order
3146 #define SHIFT_COUNT_TRUNCATED 1
3148 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3149 is done just by pretending it is already truncated. */
3150 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3151 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3154 /* Specify the machine mode that pointers have.
3155 After generation of rtl, the compiler makes no further distinction
3156 between pointers and any other objects of this machine mode. */
3159 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
3162 /* Give call MEMs SImode since it is the "most permissive" mode
3163 for both 32-bit and 64-bit targets. */
3165 #define FUNCTION_MODE SImode
3168 /* The cost of loading values from the constant pool. It should be
3169 larger than the cost of any constant we want to synthesise in-line. */
3171 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
3173 /* A C expression for the cost of moving data from a register in
3174 class FROM to one in class TO. The classes are expressed using
3175 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3176 the default; other values are interpreted relative to that.
3178 It is not required that the cost always equal 2 when FROM is the
3179 same as TO; on some machines it is expensive to move between
3180 registers if they are not general registers.
3182 If reload sees an insn consisting of a single `set' between two
3183 hard registers, and if `REGISTER_MOVE_COST' applied to their
3184 classes returns a value of 2, reload does not check to ensure
3185 that the constraints of the insn are met. Setting a cost of
3186 other than 2 will allow reload to verify that the constraints are
3187 met. You should do this if the `movM' pattern's constraints do
3188 not allow such copying. */
3190 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3191 mips_register_move_cost (MODE, FROM, TO)
3193 /* ??? Fix this to be right for the R8000. */
3194 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3195 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3196 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3198 /* Define if copies to/from condition code registers should be avoided.
3200 This is needed for the MIPS because reload_outcc is not complete;
3201 it needs to handle cases where the source is a general or another
3202 condition code register. */
3203 #define AVOID_CCMODE_COPIES
3205 /* A C expression for the cost of a branch instruction. A value of
3206 1 is the default; other values are interpreted relative to that. */
3208 /* ??? Fix this to be right for the R8000. */
3209 #define BRANCH_COST \
3211 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3214 /* If defined, modifies the length assigned to instruction INSN as a
3215 function of the context in which it is used. LENGTH is an lvalue
3216 that contains the initially computed length of the insn and should
3217 be updated with the correct length of the insn. */
3218 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3219 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3222 /* Optionally define this if you have added predicates to
3223 `MACHINE.c'. This macro is called within an initializer of an
3224 array of structures. The first field in the structure is the
3225 name of a predicate and the second field is an array of rtl
3226 codes. For each predicate, list all rtl codes that can be in
3227 expressions matched by the predicate. The list should have a
3228 trailing comma. Here is an example of two entries in the list
3229 for a typical RISC machine:
3231 #define PREDICATE_CODES \
3232 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3233 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3235 Defining this macro does not affect the generated code (however,
3236 incorrect definitions that omit an rtl code that may be matched
3237 by the predicate can cause the compiler to malfunction).
3238 Instead, it allows the table built by `genrecog' to be more
3239 compact and efficient, thus speeding up the compiler. The most
3240 important predicates to include in the list specified by this
3241 macro are thoses used in the most insn patterns. */
3243 #define PREDICATE_CODES \
3244 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3245 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
3246 {"const_arith_operand", { CONST, CONST_INT }}, \
3247 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
3248 {"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3249 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3250 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3251 {"small_int", { CONST_INT }}, \
3252 {"large_int", { CONST_INT }}, \
3253 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3254 {"const_float_1_operand", { CONST_DOUBLE }}, \
3255 {"simple_memory_operand", { MEM, SUBREG }}, \
3256 {"equality_op", { EQ, NE }}, \
3257 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3259 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3260 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3261 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
3262 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3263 SYMBOL_REF, LABEL_REF, SUBREG, \
3265 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3266 CONST_DOUBLE, CONST }}, \
3267 {"fcc_register_operand", { REG, SUBREG }}, \
3268 {"hilo_operand", { REG }}, \
3269 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
3271 /* A list of predicates that do special things with modes, and so
3272 should not elicit warnings for VOIDmode match_operand. */
3274 #define SPECIAL_MODE_PREDICATES \
3275 "pc_or_label_operand",
3277 /* Control the assembler format that we output. */
3279 /* Output at beginning of assembler file.
3280 If we are optimizing to use the global pointer, create a temporary
3281 file to hold all of the text stuff, and write it out to the end.
3282 This is needed because the MIPS assembler is evidently one pass,
3283 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3284 declaration when the code is processed, it generates a two
3285 instruction sequence. */
3287 #undef ASM_FILE_START
3288 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3290 /* Output to assembler file text saying following lines
3291 may contain character constants, extra white space, comments, etc. */
3294 #define ASM_APP_ON " #APP\n"
3297 /* Output to assembler file text saying following lines
3298 no longer contain unusual constructs. */
3301 #define ASM_APP_OFF " #NO_APP\n"
3304 /* How to refer to registers in assembler output.
3305 This sequence is indexed by compiler's hard-register-number (see above).
3307 In order to support the two different conventions for register names,
3308 we use the name of a table set up in mips.c, which is overwritten
3309 if -mrnames is used. */
3311 #define REGISTER_NAMES \
3313 &mips_reg_names[ 0][0], \
3314 &mips_reg_names[ 1][0], \
3315 &mips_reg_names[ 2][0], \
3316 &mips_reg_names[ 3][0], \
3317 &mips_reg_names[ 4][0], \
3318 &mips_reg_names[ 5][0], \
3319 &mips_reg_names[ 6][0], \
3320 &mips_reg_names[ 7][0], \
3321 &mips_reg_names[ 8][0], \
3322 &mips_reg_names[ 9][0], \
3323 &mips_reg_names[10][0], \
3324 &mips_reg_names[11][0], \
3325 &mips_reg_names[12][0], \
3326 &mips_reg_names[13][0], \
3327 &mips_reg_names[14][0], \
3328 &mips_reg_names[15][0], \
3329 &mips_reg_names[16][0], \
3330 &mips_reg_names[17][0], \
3331 &mips_reg_names[18][0], \
3332 &mips_reg_names[19][0], \
3333 &mips_reg_names[20][0], \
3334 &mips_reg_names[21][0], \
3335 &mips_reg_names[22][0], \
3336 &mips_reg_names[23][0], \
3337 &mips_reg_names[24][0], \
3338 &mips_reg_names[25][0], \
3339 &mips_reg_names[26][0], \
3340 &mips_reg_names[27][0], \
3341 &mips_reg_names[28][0], \
3342 &mips_reg_names[29][0], \
3343 &mips_reg_names[30][0], \
3344 &mips_reg_names[31][0], \
3345 &mips_reg_names[32][0], \
3346 &mips_reg_names[33][0], \
3347 &mips_reg_names[34][0], \
3348 &mips_reg_names[35][0], \
3349 &mips_reg_names[36][0], \
3350 &mips_reg_names[37][0], \
3351 &mips_reg_names[38][0], \
3352 &mips_reg_names[39][0], \
3353 &mips_reg_names[40][0], \
3354 &mips_reg_names[41][0], \
3355 &mips_reg_names[42][0], \
3356 &mips_reg_names[43][0], \
3357 &mips_reg_names[44][0], \
3358 &mips_reg_names[45][0], \
3359 &mips_reg_names[46][0], \
3360 &mips_reg_names[47][0], \
3361 &mips_reg_names[48][0], \
3362 &mips_reg_names[49][0], \
3363 &mips_reg_names[50][0], \
3364 &mips_reg_names[51][0], \
3365 &mips_reg_names[52][0], \
3366 &mips_reg_names[53][0], \
3367 &mips_reg_names[54][0], \
3368 &mips_reg_names[55][0], \
3369 &mips_reg_names[56][0], \
3370 &mips_reg_names[57][0], \
3371 &mips_reg_names[58][0], \
3372 &mips_reg_names[59][0], \
3373 &mips_reg_names[60][0], \
3374 &mips_reg_names[61][0], \
3375 &mips_reg_names[62][0], \
3376 &mips_reg_names[63][0], \
3377 &mips_reg_names[64][0], \
3378 &mips_reg_names[65][0], \
3379 &mips_reg_names[66][0], \
3380 &mips_reg_names[67][0], \
3381 &mips_reg_names[68][0], \
3382 &mips_reg_names[69][0], \
3383 &mips_reg_names[70][0], \
3384 &mips_reg_names[71][0], \
3385 &mips_reg_names[72][0], \
3386 &mips_reg_names[73][0], \
3387 &mips_reg_names[74][0], \
3388 &mips_reg_names[75][0], \
3389 &mips_reg_names[76][0], \
3390 &mips_reg_names[77][0], \
3391 &mips_reg_names[78][0], \
3392 &mips_reg_names[79][0], \
3393 &mips_reg_names[80][0], \
3394 &mips_reg_names[81][0], \
3395 &mips_reg_names[82][0], \
3396 &mips_reg_names[83][0], \
3397 &mips_reg_names[84][0], \
3398 &mips_reg_names[85][0], \
3399 &mips_reg_names[86][0], \
3400 &mips_reg_names[87][0], \
3401 &mips_reg_names[88][0], \
3402 &mips_reg_names[89][0], \
3403 &mips_reg_names[90][0], \
3404 &mips_reg_names[91][0], \
3405 &mips_reg_names[92][0], \
3406 &mips_reg_names[93][0], \
3407 &mips_reg_names[94][0], \
3408 &mips_reg_names[95][0], \
3409 &mips_reg_names[96][0], \
3410 &mips_reg_names[97][0], \
3411 &mips_reg_names[98][0], \
3412 &mips_reg_names[99][0], \
3413 &mips_reg_names[100][0], \
3414 &mips_reg_names[101][0], \
3415 &mips_reg_names[102][0], \
3416 &mips_reg_names[103][0], \
3417 &mips_reg_names[104][0], \
3418 &mips_reg_names[105][0], \
3419 &mips_reg_names[106][0], \
3420 &mips_reg_names[107][0], \
3421 &mips_reg_names[108][0], \
3422 &mips_reg_names[109][0], \
3423 &mips_reg_names[110][0], \
3424 &mips_reg_names[111][0], \
3425 &mips_reg_names[112][0], \
3426 &mips_reg_names[113][0], \
3427 &mips_reg_names[114][0], \
3428 &mips_reg_names[115][0], \
3429 &mips_reg_names[116][0], \
3430 &mips_reg_names[117][0], \
3431 &mips_reg_names[118][0], \
3432 &mips_reg_names[119][0], \
3433 &mips_reg_names[120][0], \
3434 &mips_reg_names[121][0], \
3435 &mips_reg_names[122][0], \
3436 &mips_reg_names[123][0], \
3437 &mips_reg_names[124][0], \
3438 &mips_reg_names[125][0], \
3439 &mips_reg_names[126][0], \
3440 &mips_reg_names[127][0], \
3441 &mips_reg_names[128][0], \
3442 &mips_reg_names[129][0], \
3443 &mips_reg_names[130][0], \
3444 &mips_reg_names[131][0], \
3445 &mips_reg_names[132][0], \
3446 &mips_reg_names[133][0], \
3447 &mips_reg_names[134][0], \
3448 &mips_reg_names[135][0], \
3449 &mips_reg_names[136][0], \
3450 &mips_reg_names[137][0], \
3451 &mips_reg_names[138][0], \
3452 &mips_reg_names[139][0], \
3453 &mips_reg_names[140][0], \
3454 &mips_reg_names[141][0], \
3455 &mips_reg_names[142][0], \
3456 &mips_reg_names[143][0], \
3457 &mips_reg_names[144][0], \
3458 &mips_reg_names[145][0], \
3459 &mips_reg_names[146][0], \
3460 &mips_reg_names[147][0], \
3461 &mips_reg_names[148][0], \
3462 &mips_reg_names[149][0], \
3463 &mips_reg_names[150][0], \
3464 &mips_reg_names[151][0], \
3465 &mips_reg_names[152][0], \
3466 &mips_reg_names[153][0], \
3467 &mips_reg_names[154][0], \
3468 &mips_reg_names[155][0], \
3469 &mips_reg_names[156][0], \
3470 &mips_reg_names[157][0], \
3471 &mips_reg_names[158][0], \
3472 &mips_reg_names[159][0], \
3473 &mips_reg_names[160][0], \
3474 &mips_reg_names[161][0], \
3475 &mips_reg_names[162][0], \
3476 &mips_reg_names[163][0], \
3477 &mips_reg_names[164][0], \
3478 &mips_reg_names[165][0], \
3479 &mips_reg_names[166][0], \
3480 &mips_reg_names[167][0], \
3481 &mips_reg_names[168][0], \
3482 &mips_reg_names[169][0], \
3483 &mips_reg_names[170][0], \
3484 &mips_reg_names[171][0], \
3485 &mips_reg_names[172][0], \
3486 &mips_reg_names[173][0], \
3487 &mips_reg_names[174][0], \
3488 &mips_reg_names[175][0] \
3491 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3492 So define this for it. */
3493 #define DEBUG_REGISTER_NAMES \
3495 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3496 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3497 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3498 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3499 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3500 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3501 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3502 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3503 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3504 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
3505 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3506 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3507 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3508 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3509 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3510 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3511 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3512 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3513 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3514 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3515 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3516 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
3519 /* If defined, a C initializer for an array of structures
3520 containing a name and a register number. This macro defines
3521 additional names for hard registers, thus allowing the `asm'
3522 option in declarations to refer to registers using alternate
3525 We define both names for the integer registers here. */
3527 #define ADDITIONAL_REGISTER_NAMES \
3529 { "$0", 0 + GP_REG_FIRST }, \
3530 { "$1", 1 + GP_REG_FIRST }, \
3531 { "$2", 2 + GP_REG_FIRST }, \
3532 { "$3", 3 + GP_REG_FIRST }, \
3533 { "$4", 4 + GP_REG_FIRST }, \
3534 { "$5", 5 + GP_REG_FIRST }, \
3535 { "$6", 6 + GP_REG_FIRST }, \
3536 { "$7", 7 + GP_REG_FIRST }, \
3537 { "$8", 8 + GP_REG_FIRST }, \
3538 { "$9", 9 + GP_REG_FIRST }, \
3539 { "$10", 10 + GP_REG_FIRST }, \
3540 { "$11", 11 + GP_REG_FIRST }, \
3541 { "$12", 12 + GP_REG_FIRST }, \
3542 { "$13", 13 + GP_REG_FIRST }, \
3543 { "$14", 14 + GP_REG_FIRST }, \
3544 { "$15", 15 + GP_REG_FIRST }, \
3545 { "$16", 16 + GP_REG_FIRST }, \
3546 { "$17", 17 + GP_REG_FIRST }, \
3547 { "$18", 18 + GP_REG_FIRST }, \
3548 { "$19", 19 + GP_REG_FIRST }, \
3549 { "$20", 20 + GP_REG_FIRST }, \
3550 { "$21", 21 + GP_REG_FIRST }, \
3551 { "$22", 22 + GP_REG_FIRST }, \
3552 { "$23", 23 + GP_REG_FIRST }, \
3553 { "$24", 24 + GP_REG_FIRST }, \
3554 { "$25", 25 + GP_REG_FIRST }, \
3555 { "$26", 26 + GP_REG_FIRST }, \
3556 { "$27", 27 + GP_REG_FIRST }, \
3557 { "$28", 28 + GP_REG_FIRST }, \
3558 { "$29", 29 + GP_REG_FIRST }, \
3559 { "$30", 30 + GP_REG_FIRST }, \
3560 { "$31", 31 + GP_REG_FIRST }, \
3561 { "$sp", 29 + GP_REG_FIRST }, \
3562 { "$fp", 30 + GP_REG_FIRST }, \
3563 { "at", 1 + GP_REG_FIRST }, \
3564 { "v0", 2 + GP_REG_FIRST }, \
3565 { "v1", 3 + GP_REG_FIRST }, \
3566 { "a0", 4 + GP_REG_FIRST }, \
3567 { "a1", 5 + GP_REG_FIRST }, \
3568 { "a2", 6 + GP_REG_FIRST }, \
3569 { "a3", 7 + GP_REG_FIRST }, \
3570 { "t0", 8 + GP_REG_FIRST }, \
3571 { "t1", 9 + GP_REG_FIRST }, \
3572 { "t2", 10 + GP_REG_FIRST }, \
3573 { "t3", 11 + GP_REG_FIRST }, \
3574 { "t4", 12 + GP_REG_FIRST }, \
3575 { "t5", 13 + GP_REG_FIRST }, \
3576 { "t6", 14 + GP_REG_FIRST }, \
3577 { "t7", 15 + GP_REG_FIRST }, \
3578 { "s0", 16 + GP_REG_FIRST }, \
3579 { "s1", 17 + GP_REG_FIRST }, \
3580 { "s2", 18 + GP_REG_FIRST }, \
3581 { "s3", 19 + GP_REG_FIRST }, \
3582 { "s4", 20 + GP_REG_FIRST }, \
3583 { "s5", 21 + GP_REG_FIRST }, \
3584 { "s6", 22 + GP_REG_FIRST }, \
3585 { "s7", 23 + GP_REG_FIRST }, \
3586 { "t8", 24 + GP_REG_FIRST }, \
3587 { "t9", 25 + GP_REG_FIRST }, \
3588 { "k0", 26 + GP_REG_FIRST }, \
3589 { "k1", 27 + GP_REG_FIRST }, \
3590 { "gp", 28 + GP_REG_FIRST }, \
3591 { "sp", 29 + GP_REG_FIRST }, \
3592 { "fp", 30 + GP_REG_FIRST }, \
3593 { "ra", 31 + GP_REG_FIRST }, \
3594 { "$sp", 29 + GP_REG_FIRST }, \
3595 { "$fp", 30 + GP_REG_FIRST } \
3596 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3599 /* This is meant to be redefined in the host dependent files. It is a
3600 set of alternative names and regnums for mips coprocessors. */
3602 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3604 /* A C compound statement to output to stdio stream STREAM the
3605 assembler syntax for an instruction operand X. X is an RTL
3608 CODE is a value that can be used to specify one of several ways
3609 of printing the operand. It is used when identical operands
3610 must be printed differently depending on the context. CODE
3611 comes from the `%' specification that was used to request
3612 printing of the operand. If the specification was just `%DIGIT'
3613 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3614 is the ASCII code for LTR.
3616 If X is a register, this macro should print the register's name.
3617 The names can be found in an array `reg_names' whose type is
3618 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3620 When the machine description has a specification `%PUNCT' (a `%'
3621 followed by a punctuation character), this macro is called with
3622 a null pointer for X and the punctuation character for CODE.
3624 See mips.c for the MIPS specific codes. */
3626 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3628 /* A C expression which evaluates to true if CODE is a valid
3629 punctuation character for use in the `PRINT_OPERAND' macro. If
3630 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3631 punctuation characters (except for the standard one, `%') are
3632 used in this way. */
3634 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3636 /* A C compound statement to output to stdio stream STREAM the
3637 assembler syntax for an instruction operand that is a memory
3638 reference whose address is ADDR. ADDR is an RTL expression. */
3640 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3643 /* A C statement, to be executed after all slot-filler instructions
3644 have been output. If necessary, call `dbr_sequence_length' to
3645 determine the number of slots filled in a sequence (zero if not
3646 currently outputting a sequence), to decide how many no-ops to
3647 output, or whatever.
3649 Don't define this macro if it has nothing to do, but it is
3650 helpful in reading assembly output if the extent of the delay
3651 sequence is made explicit (e.g. with white space).
3653 Note that output routines for instructions with delay slots must
3654 be prepared to deal with not being output as part of a sequence
3655 (i.e. when the scheduling pass is not run, or when no slot
3656 fillers could be found.) The variable `final_sequence' is null
3657 when not processing a sequence, otherwise it contains the
3658 `sequence' rtx being output. */
3660 #define DBR_OUTPUT_SEQEND(STREAM) \
3663 if (set_nomacro > 0 && --set_nomacro == 0) \
3664 fputs ("\t.set\tmacro\n", STREAM); \
3666 if (set_noreorder > 0 && --set_noreorder == 0) \
3667 fputs ("\t.set\treorder\n", STREAM); \
3669 fputs ("\n", STREAM); \
3674 /* How to tell the debugger about changes of source files. Note, the
3675 mips ECOFF format cannot deal with changes of files inside of
3676 functions, which means the output of parser generators like bison
3677 is generally not debuggable without using the -l switch. Lose,
3678 lose, lose. Silicon graphics seems to want all .file's hardwired
3681 #ifndef SET_FILE_NUMBER
3682 #define SET_FILE_NUMBER() ++num_source_filenames
3685 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3686 mips_output_filename (STREAM, NAME)
3688 /* This is defined so that it can be overridden in iris6.h. */
3689 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3692 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3693 output_quoted_string (STREAM, NAME); \
3694 fputs ("\n", STREAM); \
3698 /* This is how to output a note the debugger telling it the line number
3699 to which the following sequence of instructions corresponds.
3700 Silicon graphics puts a label after each .loc. */
3702 #ifndef LABEL_AFTER_LOC
3703 #define LABEL_AFTER_LOC(STREAM)
3706 #ifndef ASM_OUTPUT_SOURCE_LINE
3707 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3708 mips_output_lineno (STREAM, LINE)
3711 /* The MIPS implementation uses some labels for its own purpose. The
3712 following lists what labels are created, and are all formed by the
3713 pattern $L[a-z].*. The machine independent portion of GCC creates
3714 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3716 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3717 $Lb[0-9]+ Begin blocks for MIPS debug support
3718 $Lc[0-9]+ Label for use in s<xx> operation.
3719 $Le[0-9]+ End blocks for MIPS debug support */
3721 /* A C statement (sans semicolon) to output to the stdio stream
3722 STREAM any text necessary for declaring the name NAME of an
3723 initialized variable which is being defined. This macro must
3724 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3725 The argument DECL is the `VAR_DECL' tree node representing the
3728 If this macro is not defined, then the variable name is defined
3729 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3731 #undef ASM_DECLARE_OBJECT_NAME
3732 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3735 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3739 /* Globalizing directive for a label. */
3740 #define GLOBAL_ASM_OP "\t.globl\t"
3742 /* This says how to define a global common symbol. */
3744 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3746 /* If the target wants uninitialized const declarations in \
3747 .rdata then don't put them in .comm */ \
3748 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3749 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3750 && (DECL_INITIAL (DECL) == 0 \
3751 || DECL_INITIAL (DECL) == error_mark_node)) \
3753 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3754 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3756 readonly_data_section (); \
3757 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3758 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3762 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3767 /* This says how to define a local common symbol (ie, not visible to
3770 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3771 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3774 /* This says how to output an external. It would be possible not to
3775 output anything and let undefined symbol become external. However
3776 the assembler uses length information on externals to allocate in
3777 data/sdata bss/sbss, thereby saving exec time. */
3779 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3780 mips_output_external(STREAM,DECL,NAME)
3783 /* This is how to declare a function name. The actual work of
3784 emitting the label is moved to function_prologue, so that we can
3785 get the line number correctly emitted before the .ent directive,
3786 and after any .file directives. Define as empty so that the function
3787 is not declared before the .ent directive elsewhere. */
3789 #undef ASM_DECLARE_FUNCTION_NAME
3790 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3792 /* This is how to store into the string LABEL
3793 the symbol_ref name of an internal numbered label where
3794 PREFIX is the class of label and NUM is the number within the class.
3795 This is suitable for output with `assemble_name'. */
3797 #undef ASM_GENERATE_INTERNAL_LABEL
3798 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3799 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3801 /* This is how to output an element of a case-vector that is absolute. */
3803 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3804 fprintf (STREAM, "\t%s\t%sL%d\n", \
3805 ptr_mode == DImode ? ".dword" : ".word", \
3806 LOCAL_LABEL_PREFIX, \
3809 /* This is how to output an element of a case-vector that is relative.
3810 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3811 TARGET_EMBEDDED_PIC). */
3813 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3815 if (TARGET_MIPS16) \
3816 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3817 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3818 else if (TARGET_EMBEDDED_PIC) \
3819 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3820 ptr_mode == DImode ? ".dword" : ".word", \
3821 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3822 else if (TARGET_GPWORD) \
3823 fprintf (STREAM, "\t%s\t%sL%d\n", \
3824 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3825 LOCAL_LABEL_PREFIX, VALUE); \
3827 fprintf (STREAM, "\t%s\t%sL%d\n", \
3828 ptr_mode == DImode ? ".dword" : ".word", \
3829 LOCAL_LABEL_PREFIX, VALUE); \
3832 /* When generating embedded PIC or mips16 code we want to put the jump
3833 table in the .text section. In all other cases, we want to put the
3834 jump table in the .rdata section. Unfortunately, we can't use
3835 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3836 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3837 section if appropriate. */
3838 #undef ASM_OUTPUT_CASE_LABEL
3839 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3841 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3842 function_section (current_function_decl); \
3843 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3846 /* This is how to output an assembler line
3847 that says to advance the location counter
3848 to a multiple of 2**LOG bytes. */
3850 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3851 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3853 /* This is how to output an assembler line to advance the location
3854 counter by SIZE bytes. */
3856 #undef ASM_OUTPUT_SKIP
3857 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3858 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3860 /* This is how to output a string. */
3861 #undef ASM_OUTPUT_ASCII
3862 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3863 mips_output_ascii (STREAM, STRING, LEN)
3865 /* Output #ident as a in the read-only data section. */
3866 #undef ASM_OUTPUT_IDENT
3867 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3869 const char *p = STRING; \
3870 int size = strlen (p) + 1; \
3871 readonly_data_section (); \
3872 assemble_string (p, size); \
3875 /* Default to -G 8 */
3876 #ifndef MIPS_DEFAULT_GVALUE
3877 #define MIPS_DEFAULT_GVALUE 8
3880 /* Define the strings to put out for each section in the object file. */
3881 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3882 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3883 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3885 #undef READONLY_DATA_SECTION_ASM_OP
3886 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3888 #define SMALL_DATA_SECTION sdata_section
3890 /* What other sections we support other than the normal .data/.text. */
3892 #undef EXTRA_SECTIONS
3893 #define EXTRA_SECTIONS in_sdata
3895 /* Define the additional functions to select our additional sections. */
3897 /* on the MIPS it is not a good idea to put constants in the text
3898 section, since this defeats the sdata/data mechanism. This is
3899 especially true when -O is used. In this case an effort is made to
3900 address with faster (gp) register relative addressing, which can
3901 only get at sdata and sbss items (there is no stext !!) However,
3902 if the constant is too large for sdata, and it's readonly, it
3903 will go into the .rdata section. */
3905 #undef EXTRA_SECTION_FUNCTIONS
3906 #define EXTRA_SECTION_FUNCTIONS \
3910 if (in_section != in_sdata) \
3912 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
3913 in_section = in_sdata; \
3917 /* Given a decl node or constant node, choose the section to output it in
3918 and select that section. */
3920 #undef TARGET_ASM_SELECT_SECTION
3921 #define TARGET_ASM_SELECT_SECTION mips_select_section
3923 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3926 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3927 TARGET_64BIT ? "dsubu" : "subu", \
3928 reg_names[STACK_POINTER_REGNUM], \
3929 reg_names[STACK_POINTER_REGNUM], \
3930 TARGET_64BIT ? "sd" : "sw", \
3932 reg_names[STACK_POINTER_REGNUM]); \
3936 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3939 if (! set_noreorder) \
3940 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3942 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3943 TARGET_64BIT ? "ld" : "lw", \
3945 reg_names[STACK_POINTER_REGNUM], \
3946 TARGET_64BIT ? "daddu" : "addu", \
3947 reg_names[STACK_POINTER_REGNUM], \
3948 reg_names[STACK_POINTER_REGNUM]); \
3950 if (! set_noreorder) \
3951 fprintf (STREAM, "\t.set\treorder\n"); \
3955 /* How to start an assembler comment.
3956 The leading space is important (the mips native assembler requires it). */
3957 #ifndef ASM_COMMENT_START
3958 #define ASM_COMMENT_START " #"
3962 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
3963 and mips-tdump.c to print them out.
3965 These must match the corresponding definitions in gdb/mipsread.c.
3966 Unfortunately, gcc and gdb do not currently share any directories. */
3968 #define CODE_MASK 0x8F300
3969 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
3970 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
3971 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
3974 /* Default definitions for size_t and ptrdiff_t. We must override the
3975 definitions from ../svr4.h on mips-*-linux-gnu. */
3978 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3981 #ifndef PTRDIFF_TYPE
3982 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3985 /* See mips_expand_prologue's use of loadgp for when this should be
3988 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
3989 && mips_abi != ABI_32 \
3990 && mips_abi != ABI_O64)
3992 /* We need to use a special set of functions to handle hard floating
3993 point code in mips16 mode. */
3995 #ifndef INIT_SUBTARGET_OPTABS
3996 #define INIT_SUBTARGET_OPTABS
3999 #define INIT_TARGET_OPTABS \
4002 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4003 INIT_SUBTARGET_OPTABS; \
4006 add_optab->handlers[(int) SFmode].libfunc = \
4007 init_one_libfunc ("__mips16_addsf3"); \
4008 sub_optab->handlers[(int) SFmode].libfunc = \
4009 init_one_libfunc ("__mips16_subsf3"); \
4010 smul_optab->handlers[(int) SFmode].libfunc = \
4011 init_one_libfunc ("__mips16_mulsf3"); \
4012 sdiv_optab->handlers[(int) SFmode].libfunc = \
4013 init_one_libfunc ("__mips16_divsf3"); \
4015 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4016 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4017 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4018 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4019 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4020 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4022 floatsisf_libfunc = \
4023 init_one_libfunc ("__mips16_floatsisf"); \
4025 init_one_libfunc ("__mips16_fixsfsi"); \
4027 if (TARGET_DOUBLE_FLOAT) \
4029 add_optab->handlers[(int) DFmode].libfunc = \
4030 init_one_libfunc ("__mips16_adddf3"); \
4031 sub_optab->handlers[(int) DFmode].libfunc = \
4032 init_one_libfunc ("__mips16_subdf3"); \
4033 smul_optab->handlers[(int) DFmode].libfunc = \
4034 init_one_libfunc ("__mips16_muldf3"); \
4035 sdiv_optab->handlers[(int) DFmode].libfunc = \
4036 init_one_libfunc ("__mips16_divdf3"); \
4038 extendsfdf2_libfunc = \
4039 init_one_libfunc ("__mips16_extendsfdf2"); \
4040 truncdfsf2_libfunc = \
4041 init_one_libfunc ("__mips16_truncdfsf2"); \
4044 init_one_libfunc ("__mips16_eqdf2"); \
4046 init_one_libfunc ("__mips16_nedf2"); \
4048 init_one_libfunc ("__mips16_gtdf2"); \
4050 init_one_libfunc ("__mips16_gedf2"); \
4052 init_one_libfunc ("__mips16_ltdf2"); \
4054 init_one_libfunc ("__mips16_ledf2"); \
4056 floatsidf_libfunc = \
4057 init_one_libfunc ("__mips16_floatsidf"); \
4059 init_one_libfunc ("__mips16_fixdfsi"); \
4065 #define DFMODE_NAN \
4066 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4067 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4068 #define SFMODE_NAN \
4069 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4070 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4072 /* Generate calls to memcpy, etc., not bcopy, etc. */
4073 #define TARGET_MEM_FUNCTIONS
4076 /* Since the bits of the _init and _fini function is spread across
4077 many object files, each potentially with its own GP, we must assume
4078 we need to load our GP. We don't preserve $gp or $ra, since each
4079 init/fini chunk is supposed to initialize $gp, and crti/crtn
4080 already take care of preserving $ra and, when appropriate, $gp. */
4081 #if _MIPS_SIM == _MIPS_SIM_ABI32
4082 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4083 asm (SECTION_OP "\n\
4089 jal " USER_LABEL_PREFIX #FUNC "\n\
4090 " TEXT_SECTION_ASM_OP);
4091 #endif /* Switch to #elif when we're no longer limited by K&R C. */
4092 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
4093 || (defined _ABI64 && _MIPS_SIM == _ABI64)
4094 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4095 asm (SECTION_OP "\n\
4100 .cpsetup $31, $2, 1b\n\
4101 jal " USER_LABEL_PREFIX #FUNC "\n\
4102 " TEXT_SECTION_ASM_OP);