1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
27 #include "config/vxworks-dummy.h"
29 /* MIPS external variables defined in mips.c. */
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
50 PROCESSOR_LOONGSON_2E,
51 PROCESSOR_LOONGSON_2F,
78 /* Costs of various operations on the different architectures. */
80 struct mips_rtx_cost_data
82 unsigned short fp_add;
83 unsigned short fp_mult_sf;
84 unsigned short fp_mult_df;
85 unsigned short fp_div_sf;
86 unsigned short fp_div_df;
87 unsigned short int_mult_si;
88 unsigned short int_mult_di;
89 unsigned short int_div_si;
90 unsigned short int_div_di;
91 unsigned short branch_cost;
92 unsigned short memory_latency;
95 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
96 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
97 to work on a 64-bit machine. */
105 /* Masks that affect tuning.
107 PTF_AVOID_BRANCHLIKELY
108 Set if it is usually not profitable to use branch-likely instructions
109 for this target, typically because the branches are always predicted
110 taken and so incur a large overhead when not taken. */
111 #define PTF_AVOID_BRANCHLIKELY 0x1
113 /* Information about one recognized processor. Defined here for the
114 benefit of TARGET_CPU_CPP_BUILTINS. */
115 struct mips_cpu_info {
116 /* The 'canonical' name of the processor as far as GCC is concerned.
117 It's typically a manufacturer's prefix followed by a numerical
118 designation. It should be lowercase. */
121 /* The internal processor number that most closely matches this
122 entry. Several processors can have the same value, if there's no
123 difference between them from GCC's point of view. */
124 enum processor_type cpu;
126 /* The ISA level that the processor implements. */
129 /* A mask of PTF_* values. */
130 unsigned int tune_flags;
133 /* Enumerates the setting of the -mcode-readable option. */
134 enum mips_code_readable_setting {
140 /* Macros to silence warnings about numbers being signed in traditional
141 C and unsigned in ISO C when compiled on 32-bit hosts. */
143 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
144 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
145 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
148 /* Run-time compilation parameters selecting different hardware subsets. */
150 /* True if we are generating position-independent VxWorks RTP code. */
151 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
153 /* True if the output file is marked as ".abicalls; .option pic0"
155 #define TARGET_ABICALLS_PIC0 \
156 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
158 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
159 #define TARGET_ABICALLS_PIC2 \
160 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
162 /* True if the call patterns should be split into a jalr followed by
163 an instruction to restore $gp. It is only safe to split the load
164 from the call when every use of $gp is explicit. */
166 #define TARGET_SPLIT_CALLS \
167 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
169 /* True if we're generating a form of -mabicalls in which we can use
170 operators like %hi and %lo to refer to locally-binding symbols.
171 We can only do this for -mno-shared, and only then if we can use
172 relocation operations instead of assembly macros. It isn't really
173 worth using absolute sequences for 64-bit symbols because GOT
174 accesses are so much shorter. */
176 #define TARGET_ABSOLUTE_ABICALLS \
179 && TARGET_EXPLICIT_RELOCS \
180 && !ABI_HAS_64BIT_SYMBOLS)
182 /* True if we can optimize sibling calls. For simplicity, we only
183 handle cases in which call_insn_operand will reject invalid
184 sibcall addresses. There are two cases in which this isn't true:
186 - TARGET_MIPS16. call_insn_operand accepts constant addresses
187 but there is no direct jump instruction. It isn't worth
188 using sibling calls in this case anyway; they would usually
189 be longer than normal calls.
191 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
192 accepts global constants, but all sibcalls must be indirect. */
193 #define TARGET_SIBCALLS \
194 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
196 /* True if we need to use a global offset table to access some symbols. */
197 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
199 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
200 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
202 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
203 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
205 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
206 This is true for both the PIC and non-PIC VxWorks RTP modes. */
207 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
209 /* True if .gpword or .gpdword should be used for switch tables.
211 Although GAS does understand .gpdword, the SGI linker mishandles
212 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
213 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
214 #define TARGET_GPWORD \
216 && !TARGET_ABSOLUTE_ABICALLS \
217 && !(mips_abi == ABI_64 && TARGET_IRIX))
219 /* Generate mips16 code */
220 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
221 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
222 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
223 /* Generate mips16e register save/restore sequences. */
224 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
226 /* True if we're generating a form of MIPS16 code in which general
227 text loads are allowed. */
228 #define TARGET_MIPS16_TEXT_LOADS \
229 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
231 /* True if we're generating a form of MIPS16 code in which PC-relative
232 loads are allowed. */
233 #define TARGET_MIPS16_PCREL_LOADS \
234 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
236 /* Generic ISA defines. */
237 #define ISA_MIPS1 (mips_isa == 1)
238 #define ISA_MIPS2 (mips_isa == 2)
239 #define ISA_MIPS3 (mips_isa == 3)
240 #define ISA_MIPS4 (mips_isa == 4)
241 #define ISA_MIPS32 (mips_isa == 32)
242 #define ISA_MIPS32R2 (mips_isa == 33)
243 #define ISA_MIPS64 (mips_isa == 64)
244 #define ISA_MIPS64R2 (mips_isa == 65)
246 /* Architecture target defines. */
247 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
248 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
249 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
250 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
251 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
252 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
253 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
254 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
255 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
256 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
257 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
258 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
259 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
260 || mips_arch == PROCESSOR_SB1A)
261 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
263 /* Scheduling target defines. */
264 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
265 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
266 || mips_tune == PROCESSOR_24KF2_1 \
267 || mips_tune == PROCESSOR_24KF1_1)
268 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
269 || mips_tune == PROCESSOR_74KF2_1 \
270 || mips_tune == PROCESSOR_74KF1_1 \
271 || mips_tune == PROCESSOR_74KF3_2)
272 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
273 || mips_tune == PROCESSOR_LOONGSON_2F)
274 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
275 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
276 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
277 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
278 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
279 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
280 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
281 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
282 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
283 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
284 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
285 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
286 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
287 || mips_tune == PROCESSOR_SB1A)
289 /* Whether vector modes and intrinsics for ST Microelectronics
290 Loongson-2E/2F processors should be enabled. In o32 pairs of
291 floating-point registers provide 64-bit values. */
292 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
293 && TARGET_LOONGSON_2EF)
295 /* True if the pre-reload scheduler should try to create chains of
296 multiply-add or multiply-subtract instructions. For example,
304 t1 will have a higher priority than t2 and t3 will have a higher
305 priority than t4. However, before reload, there is no dependence
306 between t1 and t3, and they can often have similar priorities.
307 The scheduler will then tend to prefer:
314 which stops us from making full use of macc/madd-style instructions.
315 This sort of situation occurs frequently in Fourier transforms and
318 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
319 queue so that chained multiply-add and multiply-subtract instructions
320 appear ahead of any other instruction that is likely to clobber lo.
321 In the example above, if t2 and t3 become ready at the same time,
322 the code ensures that t2 is scheduled first.
324 Multiply-accumulate instructions are a bigger win for some targets
325 than others, so this macro is defined on an opt-in basis. */
326 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
331 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
332 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
334 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
335 directly accessible, while the command-line options select
336 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
338 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
339 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
341 /* IRIX specific stuff. */
342 #define TARGET_IRIX 0
343 #define TARGET_IRIX6 0
345 /* Define preprocessor macros for the -march and -mtune options.
346 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
347 processor. If INFO's canonical name is "foo", define PREFIX to
348 be "foo", and define an additional macro PREFIX_FOO. */
349 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
354 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
355 for (p = macro; *p != 0; p++) \
358 builtin_define (macro); \
359 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
364 /* Target CPU builtins. */
365 #define TARGET_CPU_CPP_BUILTINS() \
368 /* Everyone but IRIX defines this to mips. */ \
370 builtin_assert ("machine=mips"); \
372 builtin_assert ("cpu=mips"); \
373 builtin_define ("__mips__"); \
374 builtin_define ("_mips"); \
376 /* We do this here because __mips is defined below and so we \
377 can't use builtin_define_std. We don't ever want to define \
378 "mips" for VxWorks because some of the VxWorks headers \
379 construct include filenames from a root directory macro, \
380 an architecture macro and a filename, where the architecture \
381 macro expands to 'mips'. If we define 'mips' to 1, the \
382 architecture macro expands to 1 as well. */ \
383 if (!flag_iso && !TARGET_VXWORKS) \
384 builtin_define ("mips"); \
387 builtin_define ("__mips64"); \
391 /* Treat _R3000 and _R4000 like register-size \
392 defines, which is how they've historically \
396 builtin_define_std ("R4000"); \
397 builtin_define ("_R4000"); \
401 builtin_define_std ("R3000"); \
402 builtin_define ("_R3000"); \
405 if (TARGET_FLOAT64) \
406 builtin_define ("__mips_fpr=64"); \
408 builtin_define ("__mips_fpr=32"); \
410 if (mips_base_mips16) \
411 builtin_define ("__mips16"); \
414 builtin_define ("__mips3d"); \
416 if (TARGET_SMARTMIPS) \
417 builtin_define ("__mips_smartmips"); \
421 builtin_define ("__mips_dsp"); \
424 builtin_define ("__mips_dspr2"); \
425 builtin_define ("__mips_dsp_rev=2"); \
428 builtin_define ("__mips_dsp_rev=1"); \
431 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
432 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
436 builtin_define ("__mips=1"); \
437 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
439 else if (ISA_MIPS2) \
441 builtin_define ("__mips=2"); \
442 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
444 else if (ISA_MIPS3) \
446 builtin_define ("__mips=3"); \
447 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
449 else if (ISA_MIPS4) \
451 builtin_define ("__mips=4"); \
452 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
454 else if (ISA_MIPS32) \
456 builtin_define ("__mips=32"); \
457 builtin_define ("__mips_isa_rev=1"); \
458 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
460 else if (ISA_MIPS32R2) \
462 builtin_define ("__mips=32"); \
463 builtin_define ("__mips_isa_rev=2"); \
464 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
466 else if (ISA_MIPS64) \
468 builtin_define ("__mips=64"); \
469 builtin_define ("__mips_isa_rev=1"); \
470 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
472 else if (ISA_MIPS64R2) \
474 builtin_define ("__mips=64"); \
475 builtin_define ("__mips_isa_rev=2"); \
476 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
482 builtin_define ("_ABIO32=1"); \
483 builtin_define ("_MIPS_SIM=_ABIO32"); \
487 builtin_define ("_ABIN32=2"); \
488 builtin_define ("_MIPS_SIM=_ABIN32"); \
492 builtin_define ("_ABI64=3"); \
493 builtin_define ("_MIPS_SIM=_ABI64"); \
497 builtin_define ("_ABIO64=4"); \
498 builtin_define ("_MIPS_SIM=_ABIO64"); \
502 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
503 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
504 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
505 builtin_define_with_int_value ("_MIPS_FPSET", \
506 32 / MAX_FPRS_PER_FMT); \
508 /* These defines reflect the ABI in use, not whether the \
509 FPU is directly accessible. */ \
510 if (TARGET_HARD_FLOAT_ABI) \
511 builtin_define ("__mips_hard_float"); \
513 builtin_define ("__mips_soft_float"); \
515 if (TARGET_SINGLE_FLOAT) \
516 builtin_define ("__mips_single_float"); \
518 if (TARGET_PAIRED_SINGLE_FLOAT) \
519 builtin_define ("__mips_paired_single_float"); \
521 if (TARGET_BIG_ENDIAN) \
523 builtin_define_std ("MIPSEB"); \
524 builtin_define ("_MIPSEB"); \
528 builtin_define_std ("MIPSEL"); \
529 builtin_define ("_MIPSEL"); \
532 /* Whether Loongson vector modes are enabled. */ \
533 if (TARGET_LOONGSON_VECTORS) \
534 builtin_define ("__mips_loongson_vector_rev"); \
536 /* Historical Octeon macro. */ \
538 builtin_define ("__OCTEON__"); \
540 /* Macros dependent on the C dialect. */ \
541 if (preprocessing_asm_p ()) \
543 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
544 builtin_define ("_LANGUAGE_ASSEMBLY"); \
546 else if (c_dialect_cxx ()) \
548 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
549 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
550 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
554 builtin_define_std ("LANGUAGE_C"); \
555 builtin_define ("_LANGUAGE_C"); \
557 if (c_dialect_objc ()) \
559 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
560 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
561 /* Bizarre, but needed at least for Irix. */ \
562 builtin_define_std ("LANGUAGE_C"); \
563 builtin_define ("_LANGUAGE_C"); \
566 if (mips_abi == ABI_EABI) \
567 builtin_define ("__mips_eabi"); \
569 if (TARGET_CACHE_BUILTIN) \
570 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
574 /* Default target_flags if no switches are specified */
576 #ifndef TARGET_DEFAULT
577 #define TARGET_DEFAULT 0
580 #ifndef TARGET_CPU_DEFAULT
581 #define TARGET_CPU_DEFAULT 0
584 #ifndef TARGET_ENDIAN_DEFAULT
585 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
588 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
589 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
592 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
593 #ifndef MIPS_ISA_DEFAULT
594 #ifndef MIPS_CPU_STRING_DEFAULT
595 #define MIPS_CPU_STRING_DEFAULT "from-abi"
601 /* Make this compile time constant for libgcc2 */
603 #define TARGET_64BIT 1
605 #define TARGET_64BIT 0
607 #endif /* IN_LIBGCC2 */
609 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
610 when compiled with hardware floating point. This is because MIPS16
611 code cannot save and restore the floating-point registers, which is
612 important if in a mixed MIPS16/non-MIPS16 environment. */
615 #if __mips_hard_float
616 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
618 #endif /* IN_LIBGCC2 */
620 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
622 #ifndef MULTILIB_ENDIAN_DEFAULT
623 #if TARGET_ENDIAN_DEFAULT == 0
624 #define MULTILIB_ENDIAN_DEFAULT "EL"
626 #define MULTILIB_ENDIAN_DEFAULT "EB"
630 #ifndef MULTILIB_ISA_DEFAULT
631 # if MIPS_ISA_DEFAULT == 1
632 # define MULTILIB_ISA_DEFAULT "mips1"
634 # if MIPS_ISA_DEFAULT == 2
635 # define MULTILIB_ISA_DEFAULT "mips2"
637 # if MIPS_ISA_DEFAULT == 3
638 # define MULTILIB_ISA_DEFAULT "mips3"
640 # if MIPS_ISA_DEFAULT == 4
641 # define MULTILIB_ISA_DEFAULT "mips4"
643 # if MIPS_ISA_DEFAULT == 32
644 # define MULTILIB_ISA_DEFAULT "mips32"
646 # if MIPS_ISA_DEFAULT == 33
647 # define MULTILIB_ISA_DEFAULT "mips32r2"
649 # if MIPS_ISA_DEFAULT == 64
650 # define MULTILIB_ISA_DEFAULT "mips64"
652 # if MIPS_ISA_DEFAULT == 65
653 # define MULTILIB_ISA_DEFAULT "mips64r2"
655 # define MULTILIB_ISA_DEFAULT "mips1"
666 #ifndef MULTILIB_DEFAULTS
667 #define MULTILIB_DEFAULTS \
668 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
671 /* We must pass -EL to the linker by default for little endian embedded
672 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
673 linker will default to using big-endian output files. The OUTPUT_FORMAT
674 line must be in the linker script, otherwise -EB/-EL will not work. */
677 #if TARGET_ENDIAN_DEFAULT == 0
678 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
680 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
684 /* A spec condition that matches all non-mips16 -mips arguments. */
686 #define MIPS_ISA_LEVEL_OPTION_SPEC \
687 "mips1|mips2|mips3|mips4|mips32*|mips64*"
689 /* A spec condition that matches all non-mips16 architecture arguments. */
691 #define MIPS_ARCH_OPTION_SPEC \
692 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
694 /* A spec that infers a -mips argument from an -march argument,
695 or injects the default if no architecture is specified. */
697 #define MIPS_ISA_LEVEL_SPEC \
698 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
699 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
700 %{march=mips2|march=r6000:-mips2} \
701 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
702 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
703 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
704 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
705 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
706 |march=34k*|march=74k*: -mips32r2} \
707 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
708 %{march=mips64r2|march=octeon: -mips64r2} \
709 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
711 /* A spec that infers a -mhard-float or -msoft-float setting from an
712 -march argument. Note that soft-float and hard-float code are not
715 #define MIPS_ARCH_FLOAT_SPEC \
716 "%{mhard-float|msoft-float|march=mips*:; \
717 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
718 |march=34kc|march=74kc|march=5kc|march=octeon: -msoft-float; \
719 march=*: -mhard-float}"
721 /* A spec condition that matches 32-bit options. It only works if
722 MIPS_ISA_LEVEL_SPEC has been applied. */
724 #define MIPS_32BIT_OPTION_SPEC \
725 "mips1|mips2|mips32*|mgp32"
727 /* Support for a compile-time default CPU, et cetera. The rules are:
728 --with-arch is ignored if -march is specified or a -mips is specified
729 (other than -mips16).
730 --with-tune is ignored if -mtune is specified.
731 --with-abi is ignored if -mabi is specified.
732 --with-float is ignored if -mhard-float or -msoft-float are
734 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
736 #define OPTION_DEFAULT_SPECS \
737 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
738 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
739 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
740 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
741 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
742 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
743 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }
746 /* A spec that infers the -mdsp setting from an -march argument. */
747 #define BASE_DRIVER_SELF_SPECS \
748 "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*: -mdsp}}"
750 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
752 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
753 && ISA_HAS_COND_TRAP)
755 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
757 /* True if the ABI can only work with 64-bit integer registers. We
758 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
759 otherwise floating-point registers must also be 64-bit. */
760 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
762 /* Likewise for 32-bit regs. */
763 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
765 /* True if symbols are 64 bits wide. At present, n64 is the only
766 ABI for which this is true. */
767 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
769 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
770 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
775 /* ISA has branch likely instructions (e.g. mips2). */
776 /* Disable branchlikely for tx39 until compare rewrite. They haven't
777 been generated up to this point. */
778 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
780 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
781 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
793 /* ISA has a three-operand multiplication instruction. */
794 #define ISA_HAS_DMUL3 (TARGET_64BIT \
798 /* ISA has the floating-point conditional move instructions introduced
800 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
805 && !TARGET_MIPS5500 \
808 /* ISA has the integer conditional move instructions introduced in mips4 and
809 ST Loongson 2E/2F. */
810 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
812 /* ISA has LDC1 and SDC1. */
813 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
815 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
816 branch on CC, and move (both FP and non-FP) on CC. */
817 #define ISA_HAS_8CC (ISA_MIPS4 \
823 /* This is a catch all for other mips4 instructions: indexed load, the
824 FP madd and msub instructions, and the FP recip and recip sqrt
826 #define ISA_HAS_FP4 ((ISA_MIPS4 \
827 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
832 /* ISA has paired-single instructions. */
833 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
835 /* ISA has conditional trap instructions. */
836 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
839 /* ISA has integer multiply-accumulate instructions, madd and msub. */
840 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
846 /* Integer multiply-accumulate instructions should be generated. */
847 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
849 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
850 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
852 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
853 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
855 /* ISA has floating-point nmadd and nmsub instructions
856 'd = -((a * b) [+-] c)'. */
857 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
859 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
862 && (!TARGET_MIPS5400 || TARGET_MAD) \
865 /* ISA has floating-point nmadd and nmsub instructions
866 'c = -((a * b) [+-] c)'. */
867 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
870 /* ISA has count leading zeroes/ones instruction (not implemented). */
871 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
877 /* ISA has three operand multiply instructions that put
878 the high part in an accumulator: mulhi or mulhiu. */
879 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
884 /* ISA has three operand multiply instructions that
885 negates the result and puts the result in an accumulator. */
886 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
891 /* ISA has three operand multiply instructions that subtracts the
892 result from a 4th operand and puts the result in an accumulator. */
893 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
898 /* ISA has three operand multiply instructions that the result
899 from a 4th operand and puts the result in an accumulator. */
900 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
907 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
908 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
909 || TARGET_MIPS4130) \
912 /* ISA has the "ror" (rotate right) instructions. */
913 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
918 || TARGET_SMARTMIPS) \
921 /* ISA has data prefetch instructions. This controls use of 'pref'. */
922 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
923 || TARGET_LOONGSON_2EF \
930 /* ISA has data indexed prefetch instructions. This controls use of
931 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
932 (prefx is a cop1x instruction, so can only be used if FP is
934 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
940 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
941 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
942 also requires TARGET_DOUBLE_FLOAT. */
943 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
945 /* ISA includes the MIPS32r2 seb and seh instructions. */
946 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
950 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
951 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
955 /* ISA has instructions for accessing top part of 64-bit fp regs. */
956 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
960 /* ISA has lwxs instruction (load w/scaled index address. */
961 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
963 /* The DSP ASE is available. */
964 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
966 /* Revision 2 of the DSP ASE is available. */
967 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
969 /* True if the result of a load is not available to the next instruction.
970 A nop will then be needed between instructions like "lw $4,..."
971 and "addiu $4,$4,1". */
972 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
973 && !TARGET_MIPS3900 \
976 /* Likewise mtc1 and mfc1. */
977 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
978 && !TARGET_LOONGSON_2EF)
980 /* Likewise floating-point comparisons. */
981 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
982 && !TARGET_LOONGSON_2EF)
984 /* True if mflo and mfhi can be immediately followed by instructions
985 which write to the HI and LO registers.
987 According to MIPS specifications, MIPS ISAs I, II, and III need
988 (at least) two instructions between the reads of HI/LO and
989 instructions which write them, and later ISAs do not. Contradicting
990 the MIPS specifications, some MIPS IV processor user manuals (e.g.
991 the UM for the NEC Vr5000) document needing the instructions between
992 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
993 MIPS64 and later ISAs to have the interlocks, plus any specific
994 earlier-ISA CPUs for which CPU documentation declares that the
995 instructions are really interlocked. */
996 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1000 || TARGET_MIPS5500 \
1001 || TARGET_LOONGSON_2EF)
1003 /* ISA includes synci, jr.hb and jalr.hb. */
1004 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1008 /* ISA includes sync. */
1009 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1010 #define GENERATE_SYNC \
1011 (target_flags_explicit & MASK_LLSC \
1012 ? TARGET_LLSC && !TARGET_MIPS16 \
1015 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1016 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1018 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1019 #define GENERATE_LL_SC \
1020 (target_flags_explicit & MASK_LLSC \
1021 ? TARGET_LLSC && !TARGET_MIPS16 \
1024 /* ISA includes the baddu instruction. */
1025 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1027 /* ISA includes the bbit* instructions. */
1028 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1030 /* ISA includes the cins instruction. */
1031 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1033 /* ISA includes the exts instruction. */
1034 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1036 /* ISA includes the seq and sne instructions. */
1037 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1039 /* ISA includes the pop instruction. */
1040 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1042 /* The CACHE instruction is available in non-MIPS16 code. */
1043 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1045 /* The CACHE instruction is available. */
1046 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1048 /* Add -G xx support. */
1050 #undef SWITCH_TAKES_ARG
1051 #define SWITCH_TAKES_ARG(CHAR) \
1052 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1054 #define OVERRIDE_OPTIONS mips_override_options ()
1056 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1058 /* Show we can debug even without a frame pointer. */
1059 #define CAN_DEBUG_WITHOUT_FP
1061 /* Tell collect what flags to pass to nm. */
1063 #define NM_FLAGS "-Bn"
1067 #ifndef MIPS_ABI_DEFAULT
1068 #define MIPS_ABI_DEFAULT ABI_32
1071 /* Use the most portable ABI flag for the ASM specs. */
1073 #if MIPS_ABI_DEFAULT == ABI_32
1074 #define MULTILIB_ABI_DEFAULT "mabi=32"
1077 #if MIPS_ABI_DEFAULT == ABI_O64
1078 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1081 #if MIPS_ABI_DEFAULT == ABI_N32
1082 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1085 #if MIPS_ABI_DEFAULT == ABI_64
1086 #define MULTILIB_ABI_DEFAULT "mabi=64"
1089 #if MIPS_ABI_DEFAULT == ABI_EABI
1090 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1093 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1094 to the assembler. It may be overridden by subtargets. */
1095 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1096 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1098 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1101 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1102 the assembler. It may be overridden by subtargets.
1104 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1105 COFF debugging info. */
1107 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1108 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1109 %{g} %{g0} %{g1} %{g2} %{g3} \
1110 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1111 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1112 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1113 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1114 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1117 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1118 overridden by subtargets. */
1120 #ifndef SUBTARGET_ASM_SPEC
1121 #define SUBTARGET_ASM_SPEC ""
1126 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1127 %{mips32*} %{mips64*} \
1128 %{mips16} %{mno-mips16:-no-mips16} \
1129 %{mips3d} %{mno-mips3d:-no-mips3d} \
1130 %{mdmx} %{mno-mdmx:-no-mdmx} \
1131 %{mdsp} %{mno-dsp} \
1132 %{mdspr2} %{mno-dspr2} \
1133 %{msmartmips} %{mno-smartmips} \
1135 %{mfix-vr4120} %{mfix-vr4130} \
1136 %(subtarget_asm_optimizing_spec) \
1137 %(subtarget_asm_debugging_spec) \
1138 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1139 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1141 %{mshared} %{mno-shared} \
1142 %{msym32} %{mno-sym32} \
1144 %(subtarget_asm_spec)"
1146 /* Extra switches sometimes passed to the linker. */
1147 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1148 will interpret it as a -b option. */
1151 #define LINK_SPEC "\
1153 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1154 %{bestGnum} %{shared} %{non_shared}"
1155 #endif /* LINK_SPEC defined */
1158 /* Specs for the compiler proper */
1160 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1161 overridden by subtargets. */
1162 #ifndef SUBTARGET_CC1_SPEC
1163 #define SUBTARGET_CC1_SPEC ""
1166 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1170 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1171 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1173 %(subtarget_cc1_spec)"
1175 /* Preprocessor specs. */
1177 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1178 overridden by subtargets. */
1179 #ifndef SUBTARGET_CPP_SPEC
1180 #define SUBTARGET_CPP_SPEC ""
1183 #define CPP_SPEC "%(subtarget_cpp_spec)"
1185 /* This macro defines names of additional specifications to put in the specs
1186 that can be used in various specifications like CC1_SPEC. Its definition
1187 is an initializer with a subgrouping for each command option.
1189 Each subgrouping contains a string constant, that defines the
1190 specification name, and a string constant that used by the GCC driver
1193 Do not define this macro if it does not need to do anything. */
1195 #define EXTRA_SPECS \
1196 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1197 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1198 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1199 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1200 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1201 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1202 { "endian_spec", ENDIAN_SPEC }, \
1203 SUBTARGET_EXTRA_SPECS
1205 #ifndef SUBTARGET_EXTRA_SPECS
1206 #define SUBTARGET_EXTRA_SPECS
1209 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1210 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1212 #ifndef PREFERRED_DEBUGGING_TYPE
1213 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1216 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1218 /* By default, turn on GDB extensions. */
1219 #define DEFAULT_GDB_EXTENSIONS 1
1221 /* Local compiler-generated symbols must have a prefix that the assembler
1222 understands. By default, this is $, although some targets (e.g.,
1223 NetBSD-ELF) need to override this. */
1225 #ifndef LOCAL_LABEL_PREFIX
1226 #define LOCAL_LABEL_PREFIX "$"
1229 /* By default on the mips, external symbols do not have an underscore
1230 prepended, but some targets (e.g., NetBSD) require this. */
1232 #ifndef USER_LABEL_PREFIX
1233 #define USER_LABEL_PREFIX ""
1236 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1237 since the length can run past this up to a continuation point. */
1238 #undef DBX_CONTIN_LENGTH
1239 #define DBX_CONTIN_LENGTH 1500
1241 /* How to renumber registers for dbx and gdb. */
1242 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1244 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1245 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1247 /* The DWARF 2 CFA column which tracks the return address. */
1248 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1250 /* Before the prologue, RA lives in r31. */
1251 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1253 /* Describe how we implement __builtin_eh_return. */
1254 #define EH_RETURN_DATA_REGNO(N) \
1255 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1257 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1259 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1260 The default for this in 64-bit mode is 8, which causes problems with
1261 SFmode register saves. */
1262 #define DWARF_CIE_DATA_ALIGNMENT -4
1264 /* Correct the offset of automatic variables and arguments. Note that
1265 the MIPS debug format wants all automatic variables and arguments
1266 to be in terms of the virtual frame pointer (stack pointer before
1267 any adjustment in the function), while the MIPS 3.0 linker wants
1268 the frame pointer to be the stack pointer after the initial
1271 #define DEBUGGER_AUTO_OFFSET(X) \
1272 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1273 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1274 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1276 /* Target machine storage layout */
1278 #define BITS_BIG_ENDIAN 0
1279 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1280 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1282 /* Define this to set the endianness to use in libgcc2.c, which can
1283 not depend on target_flags. */
1284 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1285 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1287 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1290 #define MAX_BITS_PER_WORD 64
1292 /* Width of a word, in units (bytes). */
1293 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1295 #define MIN_UNITS_PER_WORD 4
1298 /* For MIPS, width of a floating point register. */
1299 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1301 /* The number of consecutive floating-point registers needed to store the
1302 largest format supported by the FPU. */
1303 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1305 /* The number of consecutive floating-point registers needed to store the
1306 smallest format supported by the FPU. */
1307 #define MIN_FPRS_PER_FMT \
1308 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1309 ? 1 : MAX_FPRS_PER_FMT)
1311 /* The largest size of value that can be held in floating-point
1312 registers and moved with a single instruction. */
1313 #define UNITS_PER_HWFPVALUE \
1314 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1316 /* The largest size of value that can be held in floating-point
1318 #define UNITS_PER_FPVALUE \
1319 (TARGET_SOFT_FLOAT_ABI ? 0 \
1320 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1321 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1323 /* The number of bytes in a double. */
1324 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1326 #define UNITS_PER_SIMD_WORD(MODE) \
1327 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1329 /* Set the sizes of the core types. */
1330 #define SHORT_TYPE_SIZE 16
1331 #define INT_TYPE_SIZE 32
1332 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1333 #define LONG_LONG_TYPE_SIZE 64
1335 #define FLOAT_TYPE_SIZE 32
1336 #define DOUBLE_TYPE_SIZE 64
1337 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1339 /* Define the sizes of fixed-point types. */
1340 #define SHORT_FRACT_TYPE_SIZE 8
1341 #define FRACT_TYPE_SIZE 16
1342 #define LONG_FRACT_TYPE_SIZE 32
1343 #define LONG_LONG_FRACT_TYPE_SIZE 64
1345 #define SHORT_ACCUM_TYPE_SIZE 16
1346 #define ACCUM_TYPE_SIZE 32
1347 #define LONG_ACCUM_TYPE_SIZE 64
1348 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1349 doesn't support 128-bit integers for MIPS32 currently. */
1350 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1352 /* long double is not a fixed mode, but the idea is that, if we
1353 support long double, we also want a 128-bit integer type. */
1354 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1357 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1358 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1359 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1361 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1365 /* Width in bits of a pointer. */
1366 #ifndef POINTER_SIZE
1367 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1370 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1371 #define PARM_BOUNDARY BITS_PER_WORD
1373 /* Allocation boundary (in *bits*) for the code of a function. */
1374 #define FUNCTION_BOUNDARY 32
1376 /* Alignment of field after `int : 0' in a structure. */
1377 #define EMPTY_FIELD_BOUNDARY 32
1379 /* Every structure's size must be a multiple of this. */
1380 /* 8 is observed right on a DECstation and on riscos 4.02. */
1381 #define STRUCTURE_SIZE_BOUNDARY 8
1383 /* There is no point aligning anything to a rounder boundary than this. */
1384 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1386 /* All accesses must be aligned. */
1387 #define STRICT_ALIGNMENT 1
1389 /* Define this if you wish to imitate the way many other C compilers
1390 handle alignment of bitfields and the structures that contain
1393 The behavior is that the type written for a bit-field (`int',
1394 `short', or other integer type) imposes an alignment for the
1395 entire structure, as if the structure really did contain an
1396 ordinary field of that type. In addition, the bit-field is placed
1397 within the structure so that it would fit within such a field,
1398 not crossing a boundary for it.
1400 Thus, on most machines, a bit-field whose type is written as `int'
1401 would not cross a four-byte boundary, and would force four-byte
1402 alignment for the whole structure. (The alignment used may not
1403 be four bytes; it is controlled by the other alignment
1406 If the macro is defined, its definition should be a C expression;
1407 a nonzero value for the expression enables this behavior. */
1409 #define PCC_BITFIELD_TYPE_MATTERS 1
1411 /* If defined, a C expression to compute the alignment given to a
1412 constant that is being placed in memory. CONSTANT is the constant
1413 and ALIGN is the alignment that the object would ordinarily have.
1414 The value of this macro is used instead of that alignment to align
1417 If this macro is not defined, then ALIGN is used.
1419 The typical use of this macro is to increase alignment for string
1420 constants to be word aligned so that `strcpy' calls that copy
1421 constants can be done inline. */
1423 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1424 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1425 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1427 /* If defined, a C expression to compute the alignment for a static
1428 variable. TYPE is the data type, and ALIGN is the alignment that
1429 the object would ordinarily have. The value of this macro is used
1430 instead of that alignment to align the object.
1432 If this macro is not defined, then ALIGN is used.
1434 One use of this macro is to increase alignment of medium-size
1435 data to make it all fit in fewer cache lines. Another is to
1436 cause character arrays to be word-aligned so that `strcpy' calls
1437 that copy constants to character arrays can be done inline. */
1439 #undef DATA_ALIGNMENT
1440 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1441 ((((ALIGN) < BITS_PER_WORD) \
1442 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1443 || TREE_CODE (TYPE) == UNION_TYPE \
1444 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1446 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1447 character arrays to be word-aligned so that `strcpy' calls that copy
1448 constants to character arrays can be done inline, and 'strcmp' can be
1449 optimised to use word loads. */
1450 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1451 DATA_ALIGNMENT (TYPE, ALIGN)
1453 #define PAD_VARARGS_DOWN \
1454 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1456 /* Define if operations between registers always perform the operation
1457 on the full register even if a narrower mode is specified. */
1458 #define WORD_REGISTER_OPERATIONS
1460 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1461 moves. All other references are zero extended. */
1462 #define LOAD_EXTEND_OP(MODE) \
1463 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1464 ? SIGN_EXTEND : ZERO_EXTEND)
1466 /* Define this macro if it is advisable to hold scalars in registers
1467 in a wider mode than that declared by the program. In such cases,
1468 the value is constrained to be within the bounds of the declared
1469 type, but kept valid in the wider mode. The signedness of the
1470 extension may differ from that of the type. */
1472 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1473 if (GET_MODE_CLASS (MODE) == MODE_INT \
1474 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1476 if ((MODE) == SImode) \
1481 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1482 Extensions of pointers to word_mode must be signed. */
1483 #define POINTERS_EXTEND_UNSIGNED false
1485 /* Define if loading short immediate values into registers sign extends. */
1486 #define SHORT_IMMEDIATES_SIGN_EXTEND
1488 /* The [d]clz instructions have the natural values at 0. */
1490 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1491 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1493 /* Standard register usage. */
1495 /* Number of hardware registers. We have:
1497 - 32 integer registers
1498 - 32 floating point registers
1499 - 8 condition code registers
1500 - 2 accumulator registers (hi and lo)
1501 - 32 registers each for coprocessors 0, 2 and 3
1503 - ARG_POINTER_REGNUM
1504 - FRAME_POINTER_REGNUM
1505 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1506 - 3 dummy entries that were used at various times in the past.
1507 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1508 - 6 DSP control registers */
1510 #define FIRST_PSEUDO_REGISTER 188
1512 /* By default, fix the kernel registers ($26 and $27), the global
1513 pointer ($28) and the stack pointer ($29). This can change
1514 depending on the command-line options.
1516 Regarding coprocessor registers: without evidence to the contrary,
1517 it's best to assume that each coprocessor register has a unique
1518 use. This can be overridden, in, e.g., mips_override_options or
1519 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1520 for a particular target. */
1522 #define FIXED_REGISTERS \
1524 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1526 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1528 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1529 /* COP0 registers */ \
1530 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1531 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1532 /* COP2 registers */ \
1533 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1534 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1535 /* COP3 registers */ \
1536 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1537 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1538 /* 6 DSP accumulator registers & 6 control registers */ \
1539 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1543 /* Set up this array for o32 by default.
1545 Note that we don't mark $31 as a call-clobbered register. The idea is
1546 that it's really the call instructions themselves which clobber $31.
1547 We don't care what the called function does with it afterwards.
1549 This approach makes it easier to implement sibcalls. Unlike normal
1550 calls, sibcalls don't clobber $31, so the register reaches the
1551 called function in tact. EPILOGUE_USES says that $31 is useful
1552 to the called function. */
1554 #define CALL_USED_REGISTERS \
1556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1557 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1559 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 /* COP0 registers */ \
1562 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1563 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1564 /* COP2 registers */ \
1565 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1567 /* COP3 registers */ \
1568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1570 /* 6 DSP accumulator registers & 6 control registers */ \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1575 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1577 #define CALL_REALLY_USED_REGISTERS \
1578 { /* General registers. */ \
1579 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1580 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1581 /* Floating-point registers. */ \
1582 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1583 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1585 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1586 /* COP0 registers */ \
1587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1588 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1589 /* COP2 registers */ \
1590 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1591 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1592 /* COP3 registers */ \
1593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1595 /* 6 DSP accumulator registers & 6 control registers */ \
1596 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1599 /* Internal macros to classify a register number as to whether it's a
1600 general purpose register, a floating point register, a
1601 multiply/divide register, or a status register. */
1603 #define GP_REG_FIRST 0
1604 #define GP_REG_LAST 31
1605 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1606 #define GP_DBX_FIRST 0
1608 #define FP_REG_FIRST 32
1609 #define FP_REG_LAST 63
1610 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1611 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1613 #define MD_REG_FIRST 64
1614 #define MD_REG_LAST 65
1615 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1616 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1618 /* The DWARF 2 CFA column which tracks the return address from a
1619 signal handler context. This means that to maintain backwards
1620 compatibility, no hard register can be assigned this column if it
1621 would need to be handled by the DWARF unwinder. */
1622 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1624 #define ST_REG_FIRST 67
1625 #define ST_REG_LAST 74
1626 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1629 /* FIXME: renumber. */
1630 #define COP0_REG_FIRST 80
1631 #define COP0_REG_LAST 111
1632 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1634 #define COP2_REG_FIRST 112
1635 #define COP2_REG_LAST 143
1636 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1638 #define COP3_REG_FIRST 144
1639 #define COP3_REG_LAST 175
1640 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1641 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1642 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1644 #define DSP_ACC_REG_FIRST 176
1645 #define DSP_ACC_REG_LAST 181
1646 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1648 #define AT_REGNUM (GP_REG_FIRST + 1)
1649 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1650 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1652 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1653 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1654 should be used instead. */
1655 #define FPSW_REGNUM ST_REG_FIRST
1657 #define GP_REG_P(REGNO) \
1658 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1659 #define M16_REG_P(REGNO) \
1660 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1661 #define FP_REG_P(REGNO) \
1662 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1663 #define MD_REG_P(REGNO) \
1664 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1665 #define ST_REG_P(REGNO) \
1666 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1667 #define COP0_REG_P(REGNO) \
1668 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1669 #define COP2_REG_P(REGNO) \
1670 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1671 #define COP3_REG_P(REGNO) \
1672 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1673 #define ALL_COP_REG_P(REGNO) \
1674 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1675 /* Test if REGNO is one of the 6 new DSP accumulators. */
1676 #define DSP_ACC_REG_P(REGNO) \
1677 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1678 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1679 #define ACC_REG_P(REGNO) \
1680 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1682 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1684 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1685 to initialize the mips16 gp pseudo register. */
1686 #define CONST_GP_P(X) \
1687 (GET_CODE (X) == CONST \
1688 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1689 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1691 /* Return coprocessor number from register number. */
1693 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1694 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1695 : COP3_REG_P (REGNO) ? '3' : '?')
1698 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1700 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1701 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1703 #define MODES_TIEABLE_P mips_modes_tieable_p
1705 /* Register to use for pushing function arguments. */
1706 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1708 /* These two registers don't really exist: they get eliminated to either
1709 the stack or hard frame pointer. */
1710 #define ARG_POINTER_REGNUM 77
1711 #define FRAME_POINTER_REGNUM 78
1713 /* $30 is not available on the mips16, so we use $17 as the frame
1715 #define HARD_FRAME_POINTER_REGNUM \
1716 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1718 #define FRAME_POINTER_REQUIRED (mips_frame_pointer_required ())
1720 /* Register in which static-chain is passed to a function. */
1721 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1723 /* Registers used as temporaries in prologue/epilogue code:
1725 - If a MIPS16 PIC function needs access to _gp, it first loads
1726 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1728 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1729 register. The register must not conflict with MIPS16_PIC_TEMP.
1731 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1734 If we're generating MIPS16 code, these registers must come from the
1735 core set of 8. The prologue registers mustn't conflict with any
1736 incoming arguments, the static chain pointer, or the frame pointer.
1737 The epilogue temporary mustn't conflict with the return registers,
1738 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1739 or the EH data registers. */
1741 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1742 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1743 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1745 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1746 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1747 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1749 /* Define this macro if it is as good or better to call a constant
1750 function address than to call an address kept in a register. */
1751 #define NO_FUNCTION_CSE 1
1753 /* The ABI-defined global pointer. Sometimes we use a different
1754 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1755 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1757 /* We normally use $28 as the global pointer. However, when generating
1758 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1759 register instead. They can then avoid saving and restoring $28
1760 and perhaps avoid using a frame at all.
1762 When a leaf function uses something other than $28, mips_expand_prologue
1763 will modify pic_offset_table_rtx in place. Take the register number
1764 from there after reload. */
1765 #define PIC_OFFSET_TABLE_REGNUM \
1766 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1768 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1770 /* Define the classes of registers for register constraints in the
1771 machine description. Also define ranges of constants.
1773 One of the classes must always be named ALL_REGS and include all hard regs.
1774 If there is more than one class, another class must be named NO_REGS
1775 and contain no registers.
1777 The name GENERAL_REGS must be the name of a class (or an alias for
1778 another name such as ALL_REGS). This is the class of registers
1779 that is allowed by "g" or "r" in a register constraint.
1780 Also, registers outside this class are allocated only when
1781 instructions express preferences for them.
1783 The classes must be numbered in nondecreasing order; that is,
1784 a larger-numbered class must never be contained completely
1785 in a smaller-numbered class.
1787 For any two classes, it is very desirable that there be another
1788 class that represents their union. */
1792 NO_REGS, /* no registers in set */
1793 M16_REGS, /* mips16 directly accessible registers */
1794 T_REG, /* mips16 T register ($24) */
1795 M16_T_REGS, /* mips16 registers plus T register */
1796 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1797 V1_REG, /* Register $v1 ($3) used for TLS access. */
1798 LEA_REGS, /* Every GPR except $25 */
1799 GR_REGS, /* integer registers */
1800 FP_REGS, /* floating point registers */
1801 MD0_REG, /* first multiply/divide register */
1802 MD1_REG, /* second multiply/divide register */
1803 MD_REGS, /* multiply/divide registers (hi/lo) */
1804 COP0_REGS, /* generic coprocessor classes */
1807 ST_REGS, /* status registers (fp status) */
1808 DSP_ACC_REGS, /* DSP accumulator registers */
1809 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1810 FRAME_REGS, /* $arg and $frame */
1811 GR_AND_MD0_REGS, /* union classes */
1815 ALL_REGS, /* all registers */
1816 LIM_REG_CLASSES /* max value + 1 */
1819 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1821 #define GENERAL_REGS GR_REGS
1823 /* An initializer containing the names of the register classes as C
1824 string constants. These names are used in writing some of the
1827 #define REG_CLASS_NAMES \
1833 "PIC_FN_ADDR_REG", \
1841 /* coprocessor registers */ \
1849 "GR_AND_MD0_REGS", \
1850 "GR_AND_MD1_REGS", \
1852 "GR_AND_ACC_REGS", \
1856 /* An initializer containing the contents of the register classes,
1857 as integers which are bit masks. The Nth integer specifies the
1858 contents of class N. The way the integer MASK is interpreted is
1859 that register R is in the class if `MASK & (1 << R)' is 1.
1861 When the machine has more than 32 registers, an integer does not
1862 suffice. Then the integers are replaced by sub-initializers,
1863 braced groupings containing several integers. Each
1864 sub-initializer must be suitable as an initializer for the type
1865 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1867 #define REG_CLASS_CONTENTS \
1869 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1870 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1871 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1872 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1873 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1874 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1875 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1876 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1877 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1878 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1879 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1880 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1881 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1882 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1883 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1884 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1885 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1886 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1887 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1888 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1889 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1890 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1891 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1892 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1896 /* A C expression whose value is a register class containing hard
1897 register REGNO. In general there is more that one such class;
1898 choose a class which is "minimal", meaning that no smaller class
1899 also contains the register. */
1901 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1903 /* A macro whose definition is the name of the class to which a
1904 valid base register must belong. A base register is one used in
1905 an address which is the register value plus a displacement. */
1907 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1909 /* A macro whose definition is the name of the class to which a
1910 valid index register must belong. An index register is one used
1911 in an address where its value is either multiplied by a scale
1912 factor or added to another register (as well as added to a
1915 #define INDEX_REG_CLASS NO_REGS
1917 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1918 registers explicitly used in the rtl to be used as spill registers
1919 but prevents the compiler from extending the lifetime of these
1922 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1924 /* We generally want to put call-clobbered registers ahead of
1925 call-saved ones. (IRA expects this.) */
1927 #define REG_ALLOC_ORDER \
1928 { /* Accumulator registers. When GPRs and accumulators have equal \
1929 cost, we generally prefer to use accumulators. For example, \
1930 a division of multiplication result is better allocated to LO, \
1931 so that we put the MFLO at the point of use instead of at the \
1932 point of definition. It's also needed if we're to take advantage \
1933 of the extra accumulators available with -mdspr2. In some cases, \
1934 it can also help to reduce register pressure. */ \
1935 64, 65,176,177,178,179,180,181, \
1936 /* Call-clobbered GPRs. */ \
1937 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1939 /* The global pointer. This is call-clobbered for o32 and o64 \
1940 abicalls, call-saved for n32 and n64 abicalls, and a program \
1941 invariant otherwise. Putting it between the call-clobbered \
1942 and call-saved registers should cope with all eventualities. */ \
1944 /* Call-saved GPRs. */ \
1945 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1946 /* GPRs that can never be exposed to the register allocator. */ \
1948 /* Call-clobbered FPRs. */ \
1949 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1951 /* FPRs that are usually call-saved. The odd ones are actually \
1952 call-clobbered for n32, but listing them ahead of the even \
1953 registers might encourage the register allocator to fragment \
1954 the available FPR pairs. We need paired FPRs to store long \
1955 doubles, so it isn't clear that using a different order \
1956 for n32 would be a win. */ \
1957 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1958 /* None of the remaining classes have defined call-saved \
1960 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1961 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1962 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1963 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1964 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1965 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1966 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1967 182,183,184,185,186,187 \
1970 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1971 to be rearranged based on a particular function. On the mips16, we
1972 want to allocate $24 (T_REG) before other registers for
1973 instructions for which it is possible. */
1975 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1977 /* True if VALUE is an unsigned 6-bit number. */
1979 #define UIMM6_OPERAND(VALUE) \
1980 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1982 /* True if VALUE is a signed 10-bit number. */
1984 #define IMM10_OPERAND(VALUE) \
1985 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1987 /* True if VALUE is a signed 16-bit number. */
1989 #define SMALL_OPERAND(VALUE) \
1990 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1992 /* True if VALUE is an unsigned 16-bit number. */
1994 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1995 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1997 /* True if VALUE can be loaded into a register using LUI. */
1999 #define LUI_OPERAND(VALUE) \
2000 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2001 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2003 /* Return a value X with the low 16 bits clear, and such that
2004 VALUE - X is a signed 16-bit value. */
2006 #define CONST_HIGH_PART(VALUE) \
2007 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2009 #define CONST_LOW_PART(VALUE) \
2010 ((VALUE) - CONST_HIGH_PART (VALUE))
2012 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2013 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2014 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2016 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2017 mips_preferred_reload_class (X, CLASS)
2019 /* The HI and LO registers can only be reloaded via the general
2020 registers. Condition code registers can only be loaded to the
2021 general registers, and from the floating point registers. */
2023 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2024 mips_secondary_reload_class (CLASS, MODE, X, true)
2025 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2026 mips_secondary_reload_class (CLASS, MODE, X, false)
2028 /* Return the maximum number of consecutive registers
2029 needed to represent mode MODE in a register of class CLASS. */
2031 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2033 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2034 mips_cannot_change_mode_class (FROM, TO, CLASS)
2036 /* Stack layout; function entry, exit and calling. */
2038 #define STACK_GROWS_DOWNWARD
2040 /* The offset of the first local variable from the beginning of the frame.
2041 See mips_compute_frame_info for details about the frame layout. */
2043 #define STARTING_FRAME_OFFSET \
2044 (crtl->outgoing_args_size \
2045 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2047 #define RETURN_ADDR_RTX mips_return_addr
2049 /* Mask off the MIPS16 ISA bit in unwind addresses.
2051 The reason for this is a little subtle. When unwinding a call,
2052 we are given the call's return address, which on most targets
2053 is the address of the following instruction. However, what we
2054 actually want to find is the EH region for the call itself.
2055 The target-independent unwind code therefore searches for "RA - 1".
2057 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2058 RA - 1 is therefore the real (even-valued) start of the return
2059 instruction. EH region labels are usually odd-valued MIPS16 symbols
2060 too, so a search for an even address within a MIPS16 region would
2063 However, there is an exception. If the end of an EH region is also
2064 the end of a function, the end label is allowed to be even. This is
2065 necessary because a following non-MIPS16 function may also need EH
2066 information for its first instruction.
2068 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2069 non-ISA-encoded address. This probably isn't ideal, but it is
2070 the traditional (legacy) behavior. It is therefore only safe
2071 to search MIPS EH regions for an _odd-valued_ address.
2073 Masking off the ISA bit means that the target-independent code
2074 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2075 #define MASK_RETURN_ADDR GEN_INT (-2)
2078 /* Similarly, don't use the least-significant bit to tell pointers to
2079 code from vtable index. */
2081 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2083 /* The eliminations to $17 are only used for mips16 code. See the
2084 definition of HARD_FRAME_POINTER_REGNUM. */
2086 #define ELIMINABLE_REGS \
2087 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2088 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2089 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2090 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2091 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2092 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2094 /* Make sure that we're not trying to eliminate to the wrong hard frame
2096 #define CAN_ELIMINATE(FROM, TO) \
2097 ((TO) == HARD_FRAME_POINTER_REGNUM || (TO) == STACK_POINTER_REGNUM)
2099 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2100 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2102 /* Allocate stack space for arguments at the beginning of each function. */
2103 #define ACCUMULATE_OUTGOING_ARGS 1
2105 /* The argument pointer always points to the first argument. */
2106 #define FIRST_PARM_OFFSET(FNDECL) 0
2108 /* o32 and o64 reserve stack space for all argument registers. */
2109 #define REG_PARM_STACK_SPACE(FNDECL) \
2111 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2114 /* Define this if it is the responsibility of the caller to
2115 allocate the area reserved for arguments passed in registers.
2116 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2117 of this macro is to determine whether the space is included in
2118 `crtl->outgoing_args_size'. */
2119 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2121 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2123 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2125 /* Symbolic macros for the registers used to return integer and floating
2128 #define GP_RETURN (GP_REG_FIRST + 2)
2129 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2131 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2133 /* Symbolic macros for the first/last argument registers. */
2135 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2136 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2137 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2138 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2140 #define LIBCALL_VALUE(MODE) \
2141 mips_function_value (NULL_TREE, MODE)
2143 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2144 mips_function_value (VALTYPE, VOIDmode)
2146 /* 1 if N is a possible register number for a function value.
2147 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2148 Currently, R2 and F0 are only implemented here (C has no complex type) */
2150 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2151 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2152 && (N) == FP_RETURN + 2))
2154 /* 1 if N is a possible register number for function argument passing.
2155 We have no FP argument registers when soft-float. When FP registers
2156 are 32 bits, we can't directly reference the odd numbered ones. */
2158 #define FUNCTION_ARG_REGNO_P(N) \
2159 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2160 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2163 /* This structure has to cope with two different argument allocation
2164 schemes. Most MIPS ABIs view the arguments as a structure, of which
2165 the first N words go in registers and the rest go on the stack. If I
2166 < N, the Ith word might go in Ith integer argument register or in a
2167 floating-point register. For these ABIs, we only need to remember
2168 the offset of the current argument into the structure.
2170 The EABI instead allocates the integer and floating-point arguments
2171 separately. The first N words of FP arguments go in FP registers,
2172 the rest go on the stack. Likewise, the first N words of the other
2173 arguments go in integer registers, and the rest go on the stack. We
2174 need to maintain three counts: the number of integer registers used,
2175 the number of floating-point registers used, and the number of words
2176 passed on the stack.
2178 We could keep separate information for the two ABIs (a word count for
2179 the standard ABIs, and three separate counts for the EABI). But it
2180 seems simpler to view the standard ABIs as forms of EABI that do not
2181 allocate floating-point registers.
2183 So for the standard ABIs, the first N words are allocated to integer
2184 registers, and mips_function_arg decides on an argument-by-argument
2185 basis whether that argument should really go in an integer register,
2186 or in a floating-point one. */
2188 typedef struct mips_args {
2189 /* Always true for varargs functions. Otherwise true if at least
2190 one argument has been passed in an integer register. */
2193 /* The number of arguments seen so far. */
2194 unsigned int arg_number;
2196 /* The number of integer registers used so far. For all ABIs except
2197 EABI, this is the number of words that have been added to the
2198 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2199 unsigned int num_gprs;
2201 /* For EABI, the number of floating-point registers used so far. */
2202 unsigned int num_fprs;
2204 /* The number of words passed on the stack. */
2205 unsigned int stack_words;
2207 /* On the mips16, we need to keep track of which floating point
2208 arguments were passed in general registers, but would have been
2209 passed in the FP regs if this were a 32-bit function, so that we
2210 can move them to the FP regs if we wind up calling a 32-bit
2211 function. We record this information in fp_code, encoded in base
2212 four. A zero digit means no floating point argument, a one digit
2213 means an SFmode argument, and a two digit means a DFmode argument,
2214 and a three digit is not used. The low order digit is the first
2215 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2216 an SFmode argument. ??? A more sophisticated approach will be
2217 needed if MIPS_ABI != ABI_32. */
2220 /* True if the function has a prototype. */
2224 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2225 for a call to a function whose data type is FNTYPE.
2226 For a library call, FNTYPE is 0. */
2228 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2229 mips_init_cumulative_args (&CUM, FNTYPE)
2231 /* Update the data in CUM to advance over an argument
2232 of mode MODE and data type TYPE.
2233 (TYPE is null for libcalls where that information may not be available.) */
2235 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2236 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2238 /* Determine where to put an argument to a function.
2239 Value is zero to push the argument on the stack,
2240 or a hard register in which to store the argument.
2242 MODE is the argument's machine mode.
2243 TYPE is the data type of the argument (as a tree).
2244 This is null for libcalls where that information may
2246 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2247 the preceding args and about the function being called.
2248 NAMED is nonzero if this argument is a named parameter
2249 (otherwise it is an extra parameter matching an ellipsis). */
2251 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2252 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2254 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2256 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2257 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2259 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2260 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2262 /* True if using EABI and varargs can be passed in floating-point
2263 registers. Under these conditions, we need a more complex form
2264 of va_list, which tracks GPR, FPR and stack arguments separately. */
2265 #define EABI_FLOAT_VARARGS_P \
2266 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2269 /* Say that the epilogue uses the return address register. Note that
2270 in the case of sibcalls, the values "used by the epilogue" are
2271 considered live at the start of the called function.
2273 If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
2274 See the comment above load_call<mode> for details. */
2275 #define EPILOGUE_USES(REGNO) \
2276 ((REGNO) == 31 || (TARGET_USE_GOT && (REGNO) == GOT_VERSION_REGNUM))
2278 /* Treat LOC as a byte offset from the stack pointer and round it up
2279 to the next fully-aligned offset. */
2280 #define MIPS_STACK_ALIGN(LOC) \
2281 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2284 /* Output assembler code to FILE to increment profiler label # LABELNO
2285 for profiling a function entry. */
2287 #define FUNCTION_PROFILER(FILE, LABELNO) \
2289 if (TARGET_MIPS16) \
2290 sorry ("mips16 function profiling"); \
2291 if (TARGET_LONG_CALLS) \
2293 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */ \
2294 if (Pmode == DImode) \
2295 fprintf (FILE, "\tdla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2297 fprintf (FILE, "\tla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2299 fprintf (FILE, "\t.set\tnoat\n"); \
2300 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2301 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2302 /* _mcount treats $2 as the static chain register. */ \
2303 if (cfun->static_chain_decl != NULL) \
2304 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[2], \
2305 reg_names[STATIC_CHAIN_REGNUM]); \
2306 if (!TARGET_NEWABI) \
2309 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2310 TARGET_64BIT ? "dsubu" : "subu", \
2311 reg_names[STACK_POINTER_REGNUM], \
2312 reg_names[STACK_POINTER_REGNUM], \
2313 Pmode == DImode ? 16 : 8); \
2315 if (TARGET_LONG_CALLS) \
2316 fprintf (FILE, "\tjalr\t%s\n", reg_names[GP_REG_FIRST + 3]); \
2318 fprintf (FILE, "\tjal\t_mcount\n"); \
2319 fprintf (FILE, "\t.set\tat\n"); \
2320 /* _mcount treats $2 as the static chain register. */ \
2321 if (cfun->static_chain_decl != NULL) \
2322 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], \
2326 /* The profiler preserves all interesting registers, including $31. */
2327 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2329 /* No mips port has ever used the profiler counter word, so don't emit it
2330 or the label for it. */
2332 #define NO_PROFILE_COUNTERS 1
2334 /* Define this macro if the code for function profiling should come
2335 before the function prologue. Normally, the profiling code comes
2338 /* #define PROFILE_BEFORE_PROLOGUE */
2340 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2341 the stack pointer does not matter. The value is tested only in
2342 functions that have frame pointers.
2343 No definition is equivalent to always zero. */
2345 #define EXIT_IGNORE_STACK 1
2348 /* A C statement to output, on the stream FILE, assembler code for a
2349 block of data that contains the constant parts of a trampoline.
2350 This code should not include a label--the label is taken care of
2353 #define TRAMPOLINE_TEMPLATE(STREAM) \
2355 if (ptr_mode == DImode) \
2356 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2358 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2359 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2360 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2361 if (ptr_mode == DImode) \
2363 fprintf (STREAM, "\t.word\t0xdff90014\t\t# ld $25,20($31)\n"); \
2364 fprintf (STREAM, "\t.word\t0xdfef001c\t\t# ld $15,28($31)\n"); \
2368 fprintf (STREAM, "\t.word\t0x8ff90010\t\t# lw $25,16($31)\n"); \
2369 fprintf (STREAM, "\t.word\t0x8fef0014\t\t# lw $15,20($31)\n"); \
2371 fprintf (STREAM, "\t.word\t0x03200008\t\t# jr $25\n"); \
2372 if (ptr_mode == DImode) \
2374 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2375 fprintf (STREAM, "\t.word\t0x00000000\t\t# <padding>\n"); \
2376 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2377 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2381 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2382 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2383 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2387 /* A C expression for the size in bytes of the trampoline, as an
2390 #define TRAMPOLINE_SIZE (ptr_mode == DImode ? 48 : 36)
2392 /* Alignment required for trampolines, in bits. */
2394 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2396 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2397 program and data caches. */
2399 #ifndef CACHE_FLUSH_FUNC
2400 #define CACHE_FLUSH_FUNC "_flush_cache"
2403 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2404 /* Flush both caches. We need to flush the data cache in case \
2405 the system has a write-back cache. */ \
2406 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2407 0, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2408 GEN_INT (3), TYPE_MODE (integer_type_node))
2410 /* A C statement to initialize the variable parts of a trampoline.
2411 ADDR is an RTX for the address of the trampoline; FNADDR is an
2412 RTX for the address of the nested function; STATIC_CHAIN is an
2413 RTX for the static chain value that should be passed to the
2414 function when it is called. */
2416 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2418 rtx func_addr, chain_addr, end_addr; \
2420 func_addr = plus_constant (ADDR, ptr_mode == DImode ? 32 : 28); \
2421 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2422 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2423 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2424 end_addr = gen_reg_rtx (Pmode); \
2425 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2426 GEN_INT (TRAMPOLINE_SIZE))); \
2427 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2430 /* Addressing modes, and classification of registers for them. */
2432 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2433 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2434 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2436 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2437 and check its validity for a certain class.
2438 We have two alternate definitions for each of them.
2439 The usual definition accepts all pseudo regs; the other rejects them all.
2440 The symbol REG_OK_STRICT causes the latter definition to be used.
2442 Most source files want to accept pseudo regs in the hope that
2443 they will get allocated to the class that the insn wants them to be in.
2444 Some source files that are used after register allocation
2445 need to be strict. */
2447 #ifndef REG_OK_STRICT
2448 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2449 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2451 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2452 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2455 #define REG_OK_FOR_INDEX_P(X) 0
2458 /* Maximum number of registers that can appear in a valid memory address. */
2460 #define MAX_REGS_PER_ADDRESS 1
2462 #ifdef REG_OK_STRICT
2463 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2465 if (mips_legitimate_address_p (MODE, X, 1)) \
2469 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2471 if (mips_legitimate_address_p (MODE, X, 0)) \
2476 /* Check for constness inline but use mips_legitimate_address_p
2477 to check whether a constant really is an address. */
2479 #define CONSTANT_ADDRESS_P(X) \
2480 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2482 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2484 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2486 if (mips_legitimize_address (&(X), MODE)) \
2491 /* A C statement or compound statement with a conditional `goto
2492 LABEL;' executed if memory address X (an RTX) can have different
2493 meanings depending on the machine mode of the memory reference it
2496 Autoincrement and autodecrement addresses typically have
2497 mode-dependent effects because the amount of the increment or
2498 decrement is the size of the operand being addressed. Some
2499 machines have other mode-dependent addresses. Many RISC machines
2500 have no mode-dependent addresses.
2502 You may assume that ADDR is a valid address for the machine. */
2504 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2506 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2507 'the start of the function that this code is output in'. */
2509 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2510 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2511 asm_fprintf ((FILE), "%U%s", \
2512 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2514 asm_fprintf ((FILE), "%U%s", (NAME))
2516 /* Flag to mark a function decl symbol that requires a long call. */
2517 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2518 #define SYMBOL_REF_LONG_CALL_P(X) \
2519 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2521 /* This flag marks functions that cannot be lazily bound. */
2522 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2523 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2524 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2526 /* True if we're generating a form of MIPS16 code in which jump tables
2527 are stored in the text section and encoded as 16-bit PC-relative
2528 offsets. This is only possible when general text loads are allowed,
2529 since the table access itself will be an "lh" instruction. */
2530 /* ??? 16-bit offsets can overflow in large functions. */
2531 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2533 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2535 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2537 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2539 /* Define this as 1 if `char' should by default be signed; else as 0. */
2540 #ifndef DEFAULT_SIGNED_CHAR
2541 #define DEFAULT_SIGNED_CHAR 1
2544 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2545 we generally don't want to use them for copying arbitrary data.
2546 A single N-word move is usually the same cost as N single-word moves. */
2547 #define MOVE_MAX UNITS_PER_WORD
2548 #define MAX_MOVE_MAX 8
2550 /* Define this macro as a C expression which is nonzero if
2551 accessing less than a word of memory (i.e. a `char' or a
2552 `short') is no faster than accessing a word of memory, i.e., if
2553 such access require more than one instruction or if there is no
2554 difference in cost between byte and (aligned) word loads.
2556 On RISC machines, it tends to generate better code to define
2557 this as 1, since it avoids making a QI or HI mode register.
2559 But, generating word accesses for -mips16 is generally bad as shifts
2560 (often extended) would be needed for byte accesses. */
2561 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2563 /* Define this to be nonzero if shift instructions ignore all but the low-order
2565 #define SHIFT_COUNT_TRUNCATED 1
2567 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2568 is done just by pretending it is already truncated. */
2569 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2570 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2573 /* Specify the machine mode that pointers have.
2574 After generation of rtl, the compiler makes no further distinction
2575 between pointers and any other objects of this machine mode. */
2578 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2581 /* Give call MEMs SImode since it is the "most permissive" mode
2582 for both 32-bit and 64-bit targets. */
2584 #define FUNCTION_MODE SImode
2587 /* A C expression for the cost of moving data from a register in
2588 class FROM to one in class TO. The classes are expressed using
2589 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2590 the default; other values are interpreted relative to that.
2592 It is not required that the cost always equal 2 when FROM is the
2593 same as TO; on some machines it is expensive to move between
2594 registers if they are not general registers.
2596 If reload sees an insn consisting of a single `set' between two
2597 hard registers, and if `REGISTER_MOVE_COST' applied to their
2598 classes returns a value of 2, reload does not check to ensure
2599 that the constraints of the insn are met. Setting a cost of
2600 other than 2 will allow reload to verify that the constraints are
2601 met. You should do this if the `movM' pattern's constraints do
2602 not allow such copying. */
2604 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2605 mips_register_move_cost (MODE, FROM, TO)
2607 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2608 (mips_cost->memory_latency \
2609 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2611 /* Define if copies to/from condition code registers should be avoided.
2613 This is needed for the MIPS because reload_outcc is not complete;
2614 it needs to handle cases where the source is a general or another
2615 condition code register. */
2616 #define AVOID_CCMODE_COPIES
2618 /* A C expression for the cost of a branch instruction. A value of
2619 1 is the default; other values are interpreted relative to that. */
2621 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2622 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2624 /* If defined, modifies the length assigned to instruction INSN as a
2625 function of the context in which it is used. LENGTH is an lvalue
2626 that contains the initially computed length of the insn and should
2627 be updated with the correct length of the insn. */
2628 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2629 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2631 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2632 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2634 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2635 "%*" OPCODE "%?\t" OPERANDS "%/"
2637 /* Return the asm template for a call. INSN is the instruction's mnemonic
2638 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2641 When generating GOT code without explicit relocation operators,
2642 all calls should use assembly macros. Otherwise, all indirect
2643 calls should use "jr" or "jalr"; we will arrange to restore $gp
2644 afterwards if necessary. Finally, we can only generate direct
2645 calls for -mabicalls by temporarily switching to non-PIC mode. */
2646 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2647 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2648 ? "%*" INSN "\t%" #OPNO "%/" \
2649 : REG_P (OPERANDS[OPNO]) \
2650 ? "%*" INSN "r\t%" #OPNO "%/" \
2651 : TARGET_ABICALLS_PIC2 \
2652 ? (".option\tpic0\n\t" \
2653 "%*" INSN "\t%" #OPNO "%/\n\t" \
2655 : "%*" INSN "\t%" #OPNO "%/")
2657 /* Control the assembler format that we output. */
2659 /* Output to assembler file text saying following lines
2660 may contain character constants, extra white space, comments, etc. */
2663 #define ASM_APP_ON " #APP\n"
2666 /* Output to assembler file text saying following lines
2667 no longer contain unusual constructs. */
2670 #define ASM_APP_OFF " #NO_APP\n"
2673 #define REGISTER_NAMES \
2674 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2675 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2676 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2677 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2678 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2679 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2680 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2681 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2682 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2683 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2684 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2685 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2686 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2687 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2688 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2689 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2690 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2691 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2692 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2693 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2694 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2695 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2696 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2697 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2699 /* List the "software" names for each register. Also list the numerical
2700 names for $fp and $sp. */
2702 #define ADDITIONAL_REGISTER_NAMES \
2704 { "$29", 29 + GP_REG_FIRST }, \
2705 { "$30", 30 + GP_REG_FIRST }, \
2706 { "at", 1 + GP_REG_FIRST }, \
2707 { "v0", 2 + GP_REG_FIRST }, \
2708 { "v1", 3 + GP_REG_FIRST }, \
2709 { "a0", 4 + GP_REG_FIRST }, \
2710 { "a1", 5 + GP_REG_FIRST }, \
2711 { "a2", 6 + GP_REG_FIRST }, \
2712 { "a3", 7 + GP_REG_FIRST }, \
2713 { "t0", 8 + GP_REG_FIRST }, \
2714 { "t1", 9 + GP_REG_FIRST }, \
2715 { "t2", 10 + GP_REG_FIRST }, \
2716 { "t3", 11 + GP_REG_FIRST }, \
2717 { "t4", 12 + GP_REG_FIRST }, \
2718 { "t5", 13 + GP_REG_FIRST }, \
2719 { "t6", 14 + GP_REG_FIRST }, \
2720 { "t7", 15 + GP_REG_FIRST }, \
2721 { "s0", 16 + GP_REG_FIRST }, \
2722 { "s1", 17 + GP_REG_FIRST }, \
2723 { "s2", 18 + GP_REG_FIRST }, \
2724 { "s3", 19 + GP_REG_FIRST }, \
2725 { "s4", 20 + GP_REG_FIRST }, \
2726 { "s5", 21 + GP_REG_FIRST }, \
2727 { "s6", 22 + GP_REG_FIRST }, \
2728 { "s7", 23 + GP_REG_FIRST }, \
2729 { "t8", 24 + GP_REG_FIRST }, \
2730 { "t9", 25 + GP_REG_FIRST }, \
2731 { "k0", 26 + GP_REG_FIRST }, \
2732 { "k1", 27 + GP_REG_FIRST }, \
2733 { "gp", 28 + GP_REG_FIRST }, \
2734 { "sp", 29 + GP_REG_FIRST }, \
2735 { "fp", 30 + GP_REG_FIRST }, \
2736 { "ra", 31 + GP_REG_FIRST }, \
2737 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2740 /* This is meant to be redefined in the host dependent files. It is a
2741 set of alternative names and regnums for mips coprocessors. */
2743 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2745 #define PRINT_OPERAND mips_print_operand
2746 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2747 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2749 /* A C statement, to be executed after all slot-filler instructions
2750 have been output. If necessary, call `dbr_sequence_length' to
2751 determine the number of slots filled in a sequence (zero if not
2752 currently outputting a sequence), to decide how many no-ops to
2753 output, or whatever.
2755 Don't define this macro if it has nothing to do, but it is
2756 helpful in reading assembly output if the extent of the delay
2757 sequence is made explicit (e.g. with white space).
2759 Note that output routines for instructions with delay slots must
2760 be prepared to deal with not being output as part of a sequence
2761 (i.e. when the scheduling pass is not run, or when no slot
2762 fillers could be found.) The variable `final_sequence' is null
2763 when not processing a sequence, otherwise it contains the
2764 `sequence' rtx being output. */
2766 #define DBR_OUTPUT_SEQEND(STREAM) \
2769 if (set_nomacro > 0 && --set_nomacro == 0) \
2770 fputs ("\t.set\tmacro\n", STREAM); \
2772 if (set_noreorder > 0 && --set_noreorder == 0) \
2773 fputs ("\t.set\treorder\n", STREAM); \
2775 fputs ("\n", STREAM); \
2779 /* How to tell the debugger about changes of source files. */
2780 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2782 /* mips-tfile does not understand .stabd directives. */
2783 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2784 dbxout_begin_stabn_sline (LINE); \
2785 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2788 /* Use .loc directives for SDB line numbers. */
2789 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2790 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2792 /* The MIPS implementation uses some labels for its own purpose. The
2793 following lists what labels are created, and are all formed by the
2794 pattern $L[a-z].*. The machine independent portion of GCC creates
2795 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2797 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2798 $Lb[0-9]+ Begin blocks for MIPS debug support
2799 $Lc[0-9]+ Label for use in s<xx> operation.
2800 $Le[0-9]+ End blocks for MIPS debug support */
2802 #undef ASM_DECLARE_OBJECT_NAME
2803 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2804 mips_declare_object (STREAM, NAME, "", ":\n")
2806 /* Globalizing directive for a label. */
2807 #define GLOBAL_ASM_OP "\t.globl\t"
2809 /* This says how to define a global common symbol. */
2811 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2813 /* This says how to define a local common symbol (i.e., not visible to
2816 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2817 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2818 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2821 /* This says how to output an external. It would be possible not to
2822 output anything and let undefined symbol become external. However
2823 the assembler uses length information on externals to allocate in
2824 data/sdata bss/sbss, thereby saving exec time. */
2826 #undef ASM_OUTPUT_EXTERNAL
2827 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2828 mips_output_external(STREAM,DECL,NAME)
2830 /* This is how to declare a function name. The actual work of
2831 emitting the label is moved to function_prologue, so that we can
2832 get the line number correctly emitted before the .ent directive,
2833 and after any .file directives. Define as empty so that the function
2834 is not declared before the .ent directive elsewhere. */
2836 #undef ASM_DECLARE_FUNCTION_NAME
2837 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2839 /* This is how to store into the string LABEL
2840 the symbol_ref name of an internal numbered label where
2841 PREFIX is the class of label and NUM is the number within the class.
2842 This is suitable for output with `assemble_name'. */
2844 #undef ASM_GENERATE_INTERNAL_LABEL
2845 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2846 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2848 /* Print debug labels as "foo = ." rather than "foo:" because they should
2849 represent a byte pointer rather than an ISA-encoded address. This is
2850 particularly important for code like:
2855 .section .gcc_except_table,...
2857 .uleb128 foo-$LFBxxx
2859 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2860 likewise a byte pointer rather than an ISA-encoded address.
2862 At the time of writing, this hook is not used for the function end
2868 But this doesn't matter, because GAS doesn't treat a pre-.end label
2869 as a MIPS16 one anyway. */
2871 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2872 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2874 /* This is how to output an element of a case-vector that is absolute. */
2876 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2877 fprintf (STREAM, "\t%s\t%sL%d\n", \
2878 ptr_mode == DImode ? ".dword" : ".word", \
2879 LOCAL_LABEL_PREFIX, \
2882 /* This is how to output an element of a case-vector. We can make the
2883 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2886 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2888 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2889 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2890 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2891 else if (TARGET_GPWORD) \
2892 fprintf (STREAM, "\t%s\t%sL%d\n", \
2893 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2894 LOCAL_LABEL_PREFIX, VALUE); \
2895 else if (TARGET_RTP_PIC) \
2897 /* Make the entry relative to the start of the function. */ \
2898 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2899 fprintf (STREAM, "\t%s\t%sL%d-", \
2900 Pmode == DImode ? ".dword" : ".word", \
2901 LOCAL_LABEL_PREFIX, VALUE); \
2902 assemble_name (STREAM, XSTR (fnsym, 0)); \
2903 fprintf (STREAM, "\n"); \
2906 fprintf (STREAM, "\t%s\t%sL%d\n", \
2907 ptr_mode == DImode ? ".dword" : ".word", \
2908 LOCAL_LABEL_PREFIX, VALUE); \
2911 /* This is how to output an assembler line
2912 that says to advance the location counter
2913 to a multiple of 2**LOG bytes. */
2915 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2916 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2918 /* This is how to output an assembler line to advance the location
2919 counter by SIZE bytes. */
2921 #undef ASM_OUTPUT_SKIP
2922 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2923 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2925 /* This is how to output a string. */
2926 #undef ASM_OUTPUT_ASCII
2927 #define ASM_OUTPUT_ASCII mips_output_ascii
2929 /* Output #ident as a in the read-only data section. */
2930 #undef ASM_OUTPUT_IDENT
2931 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2933 const char *p = STRING; \
2934 int size = strlen (p) + 1; \
2935 switch_to_section (readonly_data_section); \
2936 assemble_string (p, size); \
2939 /* Default to -G 8 */
2940 #ifndef MIPS_DEFAULT_GVALUE
2941 #define MIPS_DEFAULT_GVALUE 8
2944 /* Define the strings to put out for each section in the object file. */
2945 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2946 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2948 #undef READONLY_DATA_SECTION_ASM_OP
2949 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2951 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2954 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2955 TARGET_64BIT ? "daddiu" : "addiu", \
2956 reg_names[STACK_POINTER_REGNUM], \
2957 reg_names[STACK_POINTER_REGNUM], \
2958 TARGET_64BIT ? "sd" : "sw", \
2960 reg_names[STACK_POINTER_REGNUM]); \
2964 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2967 if (! set_noreorder) \
2968 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2970 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2971 TARGET_64BIT ? "ld" : "lw", \
2973 reg_names[STACK_POINTER_REGNUM], \
2974 TARGET_64BIT ? "daddu" : "addu", \
2975 reg_names[STACK_POINTER_REGNUM], \
2976 reg_names[STACK_POINTER_REGNUM]); \
2978 if (! set_noreorder) \
2979 fprintf (STREAM, "\t.set\treorder\n"); \
2983 /* How to start an assembler comment.
2984 The leading space is important (the mips native assembler requires it). */
2985 #ifndef ASM_COMMENT_START
2986 #define ASM_COMMENT_START " #"
2989 /* Default definitions for size_t and ptrdiff_t. We must override the
2990 definitions from ../svr4.h on mips-*-linux-gnu. */
2993 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2996 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2998 /* The maximum number of bytes that can be copied by one iteration of
2999 a movmemsi loop; see mips_block_move_loop. */
3000 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3001 (UNITS_PER_WORD * 4)
3003 /* The maximum number of bytes that can be copied by a straight-line
3004 implementation of movmemsi; see mips_block_move_straight. We want
3005 to make sure that any loop-based implementation will iterate at
3007 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3008 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3010 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3011 values were determined experimentally by benchmarking with CSiBE.
3012 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3013 for o32 where we have to restore $gp afterwards as well as make an
3014 indirect call), but in practice, bumping this up higher for
3015 TARGET_ABICALLS doesn't make much difference to code size. */
3017 #define MIPS_CALL_RATIO 8
3019 /* Any loop-based implementation of movmemsi will have at least
3020 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3021 moves, so allow individual copies of fewer elements.
3023 When movmemsi is not available, use a value approximating
3024 the length of a memcpy call sequence, so that move_by_pieces
3025 will generate inline code if it is shorter than a function call.
3026 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3027 we'll have to generate a load/store pair for each, halve the
3028 value of MIPS_CALL_RATIO to take that into account. */
3030 #define MOVE_RATIO(speed) \
3032 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3033 : MIPS_CALL_RATIO / 2)
3035 /* movmemsi is meant to generate code that is at least as good as
3036 move_by_pieces. However, movmemsi effectively uses a by-pieces
3037 implementation both for moves smaller than a word and for word-aligned
3038 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
3039 allow the tree-level optimisers to do such moves by pieces, as it
3040 often exposes other optimization opportunities. We might as well
3041 continue to use movmemsi at the rtl level though, as it produces
3042 better code when scheduling is disabled (such as at -O). */
3044 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
3046 ? (!currently_expanding_to_rtl \
3047 && ((ALIGN) < BITS_PER_WORD \
3048 ? (SIZE) < UNITS_PER_WORD \
3049 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
3050 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
3051 < (unsigned int) MOVE_RATIO (false)))
3053 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3054 of the length of a memset call, but use the default otherwise. */
3056 #define CLEAR_RATIO(speed)\
3057 ((speed) ? 15 : MIPS_CALL_RATIO)
3059 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3060 optimizing for size adjust the ratio to account for the overhead of
3061 loading the constant and replicating it across the word. */
3063 #define SET_RATIO(speed) \
3064 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3066 /* STORE_BY_PIECES_P can be used when copying a constant string, but
3067 in that case each word takes 3 insns (lui, ori, sw), or more in
3068 64-bit mode, instead of 2 (lw, sw). For now we always fail this
3069 and let the move_by_pieces code copy the string from read-only
3070 memory. In the future, this could be tuned further for multi-issue
3071 CPUs that can issue stores down one pipe and arithmetic instructions
3072 down another; in that case, the lui/ori/sw combination would be a
3073 win for long enough strings. */
3075 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
3078 /* Since the bits of the _init and _fini function is spread across
3079 many object files, each potentially with its own GP, we must assume
3080 we need to load our GP. We don't preserve $gp or $ra, since each
3081 init/fini chunk is supposed to initialize $gp, and crti/crtn
3082 already take care of preserving $ra and, when appropriate, $gp. */
3083 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3084 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3085 asm (SECTION_OP "\n\
3091 jal " USER_LABEL_PREFIX #FUNC "\n\
3092 " TEXT_SECTION_ASM_OP);
3093 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3094 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3095 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3096 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3097 asm (SECTION_OP "\n\
3102 .cpsetup $31, $2, 1b\n\
3103 jal " USER_LABEL_PREFIX #FUNC "\n\
3104 " TEXT_SECTION_ASM_OP);
3109 #define HAVE_AS_TLS 0
3112 /* Return an asm string that atomically:
3114 - Compares memory reference %1 to register %2 and, if they are
3115 equal, changes %1 to %3.
3117 - Sets register %0 to the old value of memory reference %1.
3119 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
3120 and OP is the instruction that should be used to load %3 into a
3122 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
3124 "1:\tll" SUFFIX "\t%0,%1\n" \
3125 "\tbne\t%0,%z2,2f\n" \
3126 "\t" OP "\t%@,%3\n" \
3127 "\tsc" SUFFIX "\t%@,%1\n" \
3128 "\tbeq%?\t%@,%.,1b\n" \
3130 "\tsync%-%]%>%)\n" \
3133 /* Return an asm string that atomically:
3135 - Given that %2 contains a bit mask and %3 the inverted mask and
3136 that %4 and %5 have already been ANDed with %2.
3138 - Compares the bits in memory reference %1 selected by mask %2 to
3139 register %4 and, if they are equal, changes the selected bits
3142 - Sets register %0 to the old value of memory reference %1.
3144 OPS are the instructions needed to OR %5 with %@. */
3145 #define MIPS_COMPARE_AND_SWAP_12(OPS) \
3148 "\tand\t%@,%0,%2\n" \
3149 "\tbne\t%@,%z4,2f\n" \
3150 "\tand\t%@,%0,%3\n" \
3153 "\tbeq%?\t%@,%.,1b\n" \
3155 "\tsync%-%]%>%)\n" \
3158 #define MIPS_COMPARE_AND_SWAP_12_ZERO_OP ""
3159 #define MIPS_COMPARE_AND_SWAP_12_NONZERO_OP "\tor\t%@,%@,%5\n"
3162 /* Return an asm string that atomically:
3164 - Sets memory reference %0 to %0 INSN %1.
3166 SUFFIX is the suffix that should be added to "ll" and "sc"
3168 #define MIPS_SYNC_OP(SUFFIX, INSN) \
3170 "1:\tll" SUFFIX "\t%@,%0\n" \
3171 "\t" INSN "\t%@,%@,%1\n" \
3172 "\tsc" SUFFIX "\t%@,%0\n" \
3173 "\tbeq%?\t%@,%.,1b\n" \
3177 /* Return an asm string that atomically:
3179 - Given that %1 contains a bit mask and %2 the inverted mask and
3180 that %3 has already been ANDed with %1.
3182 - Sets the selected bits of memory reference %0 to %0 INSN %3.
3184 - Uses scratch register %4.
3186 AND_OP is an instruction done after INSN to mask INSN's result
3187 with the mask. For most operations, this is an AND with the
3188 inclusive mask (%1). For nand operations -- where the result of
3189 INSN is already correctly masked -- it instead performs a bitwise
3191 #define MIPS_SYNC_OP_12(INSN, AND_OP) \
3194 "\tand\t%@,%4,%2\n" \
3195 "\t" INSN "\t%4,%4,%z3\n" \
3197 "\tor\t%@,%@,%4\n" \
3199 "\tbeq%?\t%@,%.,1b\n" \
3203 #define MIPS_SYNC_OP_12_AND "\tand\t%4,%4,%1\n"
3204 #define MIPS_SYNC_OP_12_XOR "\txor\t%4,%4,%1\n"
3206 /* Return an asm string that atomically:
3208 - Given that %2 contains a bit mask and %3 the inverted mask and
3209 that %4 has already been ANDed with %2.
3211 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3213 - Sets %0 to the original value of %1.
3215 - Uses scratch register %5.
3217 AND_OP is an instruction done after INSN to mask INSN's result
3218 with the mask. For most operations, this is an AND with the
3219 inclusive mask (%1). For nand operations -- where the result of
3220 INSN is already correctly masked -- it instead performs a bitwise
3222 #define MIPS_SYNC_OLD_OP_12(INSN, AND_OP) \
3225 "\tand\t%@,%0,%3\n" \
3226 "\t" INSN "\t%5,%0,%z4\n" \
3228 "\tor\t%@,%@,%5\n" \
3230 "\tbeq%?\t%@,%.,1b\n" \
3234 #define MIPS_SYNC_OLD_OP_12_AND "\tand\t%5,%5,%2\n"
3235 #define MIPS_SYNC_OLD_OP_12_XOR "\txor\t%5,%5,%2\n"
3237 /* Return an asm string that atomically:
3239 - Given that %2 contains a bit mask and %3 the inverted mask and
3240 that %4 has already been ANDed with %2.
3242 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3244 - Sets %0 to the new value of %1.
3246 AND_OP is an instruction done after INSN to mask INSN's result
3247 with the mask. For most operations, this is an AND with the
3248 inclusive mask (%1). For nand operations -- where the result of
3249 INSN is already correctly masked -- it instead performs a bitwise
3251 #define MIPS_SYNC_NEW_OP_12(INSN, AND_OP) \
3254 "\tand\t%@,%0,%3\n" \
3255 "\t" INSN "\t%0,%0,%z4\n" \
3257 "\tor\t%@,%@,%0\n" \
3259 "\tbeq%?\t%@,%.,1b\n" \
3263 #define MIPS_SYNC_NEW_OP_12_AND "\tand\t%0,%0,%2\n"
3264 #define MIPS_SYNC_NEW_OP_12_XOR "\txor\t%0,%0,%2\n"
3266 /* Return an asm string that atomically:
3268 - Sets memory reference %1 to %1 INSN %2.
3270 - Sets register %0 to the old value of memory reference %1.
3272 SUFFIX is the suffix that should be added to "ll" and "sc"
3274 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
3276 "1:\tll" SUFFIX "\t%0,%1\n" \
3277 "\t" INSN "\t%@,%0,%2\n" \
3278 "\tsc" SUFFIX "\t%@,%1\n" \
3279 "\tbeq%?\t%@,%.,1b\n" \
3283 /* Return an asm string that atomically:
3285 - Sets memory reference %1 to %1 INSN %2.
3287 - Sets register %0 to the new value of memory reference %1.
3289 SUFFIX is the suffix that should be added to "ll" and "sc"
3291 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
3293 "1:\tll" SUFFIX "\t%0,%1\n" \
3294 "\t" INSN "\t%@,%0,%2\n" \
3295 "\tsc" SUFFIX "\t%@,%1\n" \
3296 "\tbeq%?\t%@,%.,1b%~\n" \
3297 "\t" INSN "\t%0,%0,%2\n" \
3300 /* Return an asm string that atomically:
3302 - Sets memory reference %0 to ~(%0 AND %1).
3304 SUFFIX is the suffix that should be added to "ll" and "sc"
3305 instructions. INSN is the and instruction needed to and a register
3307 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
3309 "1:\tll" SUFFIX "\t%@,%0\n" \
3310 "\t" INSN "\t%@,%@,%1\n" \
3311 "\tnor\t%@,%@,%.\n" \
3312 "\tsc" SUFFIX "\t%@,%0\n" \
3313 "\tbeq%?\t%@,%.,1b\n" \
3317 /* Return an asm string that atomically:
3319 - Sets memory reference %1 to ~(%1 AND %2).
3321 - Sets register %0 to the old value of memory reference %1.
3323 SUFFIX is the suffix that should be added to "ll" and "sc"
3324 instructions. INSN is the and instruction needed to and a register
3326 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
3328 "1:\tll" SUFFIX "\t%0,%1\n" \
3329 "\t" INSN "\t%@,%0,%2\n" \
3330 "\tnor\t%@,%@,%.\n" \
3331 "\tsc" SUFFIX "\t%@,%1\n" \
3332 "\tbeq%?\t%@,%.,1b\n" \
3336 /* Return an asm string that atomically:
3338 - Sets memory reference %1 to ~(%1 AND %2).
3340 - Sets register %0 to the new value of memory reference %1.
3342 SUFFIX is the suffix that should be added to "ll" and "sc"
3343 instructions. INSN is the and instruction needed to and a register
3345 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3347 "1:\tll" SUFFIX "\t%0,%1\n" \
3348 "\t" INSN "\t%0,%0,%2\n" \
3349 "\tnor\t%@,%0,%.\n" \
3350 "\tsc" SUFFIX "\t%@,%1\n" \
3351 "\tbeq%?\t%@,%.,1b%~\n" \
3352 "\tnor\t%0,%0,%.\n" \
3355 /* Return an asm string that atomically:
3357 - Sets memory reference %1 to %2.
3359 - Sets register %0 to the old value of memory reference %1.
3361 SUFFIX is the suffix that should be added to "ll" and "sc"
3362 instructions. OP is the and instruction that should be used to
3363 load %2 into a register. */
3364 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3366 "1:\tll" SUFFIX "\t%0,%1\n" \
3367 "\t" OP "\t%@,%2\n" \
3368 "\tsc" SUFFIX "\t%@,%1\n" \
3369 "\tbeq%?\t%@,%.,1b\n" \
3373 /* Return an asm string that atomically:
3375 - Given that %2 contains an inclusive mask, %3 and exclusive mask
3376 and %4 has already been ANDed with the inclusive mask.
3378 - Sets bits selected by the inclusive mask of memory reference %1
3381 - Sets register %0 to the old value of memory reference %1.
3383 OPS are the instructions needed to OR %4 with %@.
3385 Operand %2 is unused, but needed as to give the test_and_set_12
3386 insn the five operands expected by the expander. */
3387 #define MIPS_SYNC_EXCHANGE_12(OPS) \
3390 "\tand\t%@,%0,%3\n" \
3393 "\tbeq%?\t%@,%.,1b\n" \
3397 #define MIPS_SYNC_EXCHANGE_12_ZERO_OP ""
3398 #define MIPS_SYNC_EXCHANGE_12_NONZERO_OP "\tor\t%@,%@,%4\n"
3400 #ifndef USED_FOR_TARGET
3401 extern const enum reg_class mips_regno_to_class[];
3402 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3403 extern bool mips_print_operand_punct[256];
3404 extern const char *current_function_file; /* filename current function is in */
3405 extern int num_source_filenames; /* current .file # */
3406 extern int set_noreorder; /* # of nested .set noreorder's */
3407 extern int set_nomacro; /* # of nested .set nomacro's */
3408 extern int mips_dbx_regno[];
3409 extern int mips_dwarf_regno[];
3410 extern bool mips_split_p[];
3411 extern bool mips_split_hi_p[];
3412 extern GTY(()) rtx cmp_operands[2];
3413 extern enum processor_type mips_arch; /* which cpu to codegen for */
3414 extern enum processor_type mips_tune; /* which cpu to schedule for */
3415 extern int mips_isa; /* architectural level */
3416 extern int mips_abi; /* which ABI to use */
3417 extern const struct mips_cpu_info *mips_arch_info;
3418 extern const struct mips_cpu_info *mips_tune_info;
3419 extern const struct mips_rtx_cost_data *mips_cost;
3420 extern bool mips_base_mips16;
3421 extern enum mips_code_readable_setting mips_code_readable;
3424 /* Enable querying of DFA units. */
3425 #define CPU_UNITS_QUERY 1
OSDN Git Service
