1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* Which processor to schedule for. Since there is no difference between
47 a R2000 and R3000 in terms of the scheduler, we collapse them into
48 just an R3000. The elements of the enumeration must match exactly
49 the cpu attribute in the mips.md machine description. */
75 /* Recast the cpu class to be the cpu attribute. */
76 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
78 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
79 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
80 to work on a 64 bit machine. */
88 /* Whether to emit abicalls code sequences or not. */
90 enum mips_abicalls_type {
95 /* Recast the abicalls class to be the abicalls attribute. */
96 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
98 /* Which type of block move to do (whether or not the last store is
99 split out so it can fill a branch delay slot). */
101 enum block_move_type {
102 BLOCK_MOVE_NORMAL, /* generate complete block move */
103 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
104 BLOCK_MOVE_LAST /* generate just the last store */
107 /* Information about one recognized processor. Defined here for the
108 benefit of TARGET_CPU_CPP_BUILTINS. */
109 struct mips_cpu_info {
110 /* The 'canonical' name of the processor as far as GCC is concerned.
111 It's typically a manufacturer's prefix followed by a numerical
112 designation. It should be lower case. */
115 /* The internal processor number that most closely matches this
116 entry. Several processors can have the same value, if there's no
117 difference between them from GCC's point of view. */
118 enum processor_type cpu;
120 /* The ISA level that the processor implements. */
124 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
125 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
126 extern const char *current_function_file; /* filename current function is in */
127 extern int num_source_filenames; /* current .file # */
128 extern int inside_function; /* != 0 if inside of a function */
129 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
130 extern int file_in_function_warning; /* warning given about .file in func */
131 extern int sdb_label_count; /* block start/end next label # */
132 extern int sdb_begin_function_line; /* Starting Line of current function */
133 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
134 /* extern unsigned HOST_WIDE_INT g_switch_value; */ /* value of the -G xx switch */
135 extern int g_switch_set; /* whether -G xx was passed. */
136 extern int sym_lineno; /* sgi next label # for each stmt */
137 extern int set_noreorder; /* # of nested .set noreorder's */
138 extern int set_nomacro; /* # of nested .set nomacro's */
139 extern int set_noat; /* # of nested .set noat's */
140 extern int set_volatile; /* # of nested .set volatile's */
141 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
142 extern int mips_dbx_regno[]; /* Map register # to debug register # */
143 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
144 extern enum cmp_type branch_type; /* what type of branch to use */
145 extern enum processor_type mips_arch; /* which cpu to codegen for */
146 extern enum processor_type mips_tune; /* which cpu to schedule for */
147 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
148 extern int mips_isa; /* architectural level */
149 extern int mips16; /* whether generating mips16 code */
150 extern int mips16_hard_float; /* mips16 without -msoft-float */
151 extern int mips_entry; /* generate entry/exit for mips16 */
152 extern const char *mips_arch_string; /* for -march=<xxx> */
153 extern const char *mips_tune_string; /* for -mtune=<xxx> */
154 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
155 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
156 extern const char *mips_entry_string; /* for -mentry */
157 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
158 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
159 extern int mips_string_length; /* length of strings for mips16 */
160 extern const struct mips_cpu_info mips_cpu_info_table[];
161 extern const struct mips_cpu_info *mips_arch_info;
162 extern const struct mips_cpu_info *mips_tune_info;
164 /* Functions to change what output section we are using. */
165 extern void sdata_section PARAMS ((void));
166 extern void sbss_section PARAMS ((void));
168 /* Macros to silence warnings about numbers being signed in traditional
169 C and unsigned in ISO C when compiled on 32-bit hosts. */
171 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
172 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
173 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
176 /* Run-time compilation parameters selecting different hardware subsets. */
178 /* Macros used in the machine description to test the flags. */
180 /* Bits for real switches */
181 #define MASK_INT64 0x00000001 /* ints are 64 bits */
182 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
183 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
184 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
185 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
186 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
187 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
188 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
189 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
190 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
191 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
192 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
193 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
194 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
195 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
196 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
197 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
198 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
199 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
200 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
201 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
202 #define MASK_NO_CHECK_ZERO_DIV \
203 0x00200000 /* divide by zero checking */
204 #define MASK_CHECK_RANGE_DIV \
205 0x00400000 /* divide result range checking */
206 #define MASK_UNINIT_CONST_IN_RODATA \
207 0x00800000 /* Store uninitialized
209 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
210 multiply-add operations. */
211 #define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
214 /* Debug switches, not documented */
215 #define MASK_DEBUG 0 /* unused */
216 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
217 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
218 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
219 #define MASK_DEBUG_D 0 /* don't do define_split's */
220 #define MASK_DEBUG_E 0 /* function_arg debug */
221 #define MASK_DEBUG_F 0 /* ??? */
222 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
223 #define MASK_DEBUG_I 0 /* unused */
225 /* Dummy switches used only in specs */
226 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
228 /* r4000 64 bit sizes */
229 #define TARGET_INT64 (target_flags & MASK_INT64)
230 #define TARGET_LONG64 (target_flags & MASK_LONG64)
231 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
232 #define TARGET_64BIT (target_flags & MASK_64BIT)
234 /* Mips vs. GNU linker */
235 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
237 /* Mips vs. GNU assembler */
238 #define TARGET_GAS (target_flags & MASK_GAS)
239 #define TARGET_MIPS_AS (!TARGET_GAS)
242 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
243 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
244 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
245 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
246 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
247 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
248 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
249 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
250 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
252 /* Reg. Naming in .s ($21 vs. $a0) */
253 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
255 /* Optimize for Sdata/Sbss */
256 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
258 /* call memcpy instead of inline code */
259 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
261 /* .abicalls, etc from Pyramid V.4 */
262 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
264 /* software floating point */
265 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
266 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
268 /* always call through a register */
269 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
271 /* generate embedded PIC code;
273 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
275 /* for embedded systems, optimize for
276 reduced RAM space instead of for
278 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
280 /* always store uninitialized const
281 variables in rodata, requires
282 TARGET_EMBEDDED_DATA. */
283 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
285 /* generate big endian code. */
286 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
288 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
289 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
291 #define TARGET_MAD (target_flags & MASK_MAD)
293 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
295 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
297 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
298 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
300 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
303 /* True if we should use NewABI-style relocation operators for
304 symbolic addresses. This is never true for mips16 code,
305 which has its own conventions. */
307 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
310 /* True if the call patterns should be split into a jalr followed by
311 an instruction to restore $gp. This is only ever true for SVR4 PIC,
312 in which $gp is call-clobbered. It is only safe to split the load
313 from the call when every use of $gp is explicit. */
315 #define TARGET_SPLIT_CALLS \
316 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
318 /* True if we can optimize sibling calls. For simplicity, we only
319 handle cases in which call_insn_operand will reject invalid
320 sibcall addresses. There are two cases in which this isn't true:
322 - TARGET_MIPS16. call_insn_operand accepts constant addresses
323 but there is no direct jump instruction. It isn't worth
324 using sibling calls in this case anyway; they would usually
325 be longer than normal calls.
327 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
328 accepts global constants, but "jr $25" is the only allowed
331 #define TARGET_SIBCALLS \
332 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
334 /* True if .gpword or .gpdword should be used for switch tables.
335 Not all SGI assemblers support this. */
337 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
339 /* Generate mips16 code */
340 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
342 /* Generic ISA defines. */
343 #define ISA_MIPS1 (mips_isa == 1)
344 #define ISA_MIPS2 (mips_isa == 2)
345 #define ISA_MIPS3 (mips_isa == 3)
346 #define ISA_MIPS4 (mips_isa == 4)
347 #define ISA_MIPS32 (mips_isa == 32)
348 #define ISA_MIPS32R2 (mips_isa == 33)
349 #define ISA_MIPS64 (mips_isa == 64)
351 /* Architecture target defines. */
352 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
353 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
354 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
355 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
356 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
357 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
358 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
359 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
360 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
361 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
362 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
364 /* Scheduling target defines. */
365 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
366 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
367 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
368 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
369 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
370 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
371 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
372 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
373 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
375 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
377 /* Define preprocessor macros for the -march and -mtune options.
378 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
379 processor. If INFO's canonical name is "foo", define PREFIX to
380 be "foo", and define an additional macro PREFIX_FOO. */
381 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
386 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
387 for (p = macro; *p != 0; p++) \
390 builtin_define (macro); \
391 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
396 /* Target CPU builtins. */
397 #define TARGET_CPU_CPP_BUILTINS() \
400 builtin_assert ("cpu=mips"); \
401 builtin_define ("__mips__"); \
402 builtin_define ("_mips"); \
404 /* We do this here because __mips is defined below \
405 and so we can't use builtin_define_std. */ \
407 builtin_define ("mips"); \
409 /* Treat _R3000 and _R4000 like register-size defines, \
410 which is how they've historically been used. */ \
413 builtin_define ("__mips64"); \
414 builtin_define_std ("R4000"); \
415 builtin_define ("_R4000"); \
419 builtin_define_std ("R3000"); \
420 builtin_define ("_R3000"); \
422 if (TARGET_FLOAT64) \
423 builtin_define ("__mips_fpr=64"); \
425 builtin_define ("__mips_fpr=32"); \
428 builtin_define ("__mips16"); \
430 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
431 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
435 builtin_define ("__mips=1"); \
436 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
438 else if (ISA_MIPS2) \
440 builtin_define ("__mips=2"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
443 else if (ISA_MIPS3) \
445 builtin_define ("__mips=3"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
448 else if (ISA_MIPS4) \
450 builtin_define ("__mips=4"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
453 else if (ISA_MIPS32) \
455 builtin_define ("__mips=32"); \
456 builtin_define ("__mips_isa_rev=1"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
459 else if (ISA_MIPS32R2) \
461 builtin_define ("__mips=32"); \
462 builtin_define ("__mips_isa_rev=2"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
465 else if (ISA_MIPS64) \
467 builtin_define ("__mips=64"); \
468 builtin_define ("__mips_isa_rev=1"); \
469 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
472 if (TARGET_HARD_FLOAT) \
473 builtin_define ("__mips_hard_float"); \
474 else if (TARGET_SOFT_FLOAT) \
475 builtin_define ("__mips_soft_float"); \
477 if (TARGET_SINGLE_FLOAT) \
478 builtin_define ("__mips_single_float"); \
480 if (TARGET_BIG_ENDIAN) \
482 builtin_define_std ("MIPSEB"); \
483 builtin_define ("_MIPSEB"); \
487 builtin_define_std ("MIPSEL"); \
488 builtin_define ("_MIPSEL"); \
491 /* Macros dependent on the C dialect. */ \
492 if (preprocessing_asm_p ()) \
494 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
495 builtin_define ("_LANGUAGE_ASSEMBLY"); \
497 else if (c_language == clk_c) \
499 builtin_define_std ("LANGUAGE_C"); \
500 builtin_define ("_LANGUAGE_C"); \
502 else if (c_language == clk_cplusplus) \
504 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
505 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
506 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
510 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
511 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
512 /* Bizzare, but needed at least for Irix. */ \
513 builtin_define_std ("LANGUAGE_C"); \
514 builtin_define ("_LANGUAGE_C"); \
517 if (mips_abi == ABI_EABI) \
518 builtin_define ("__mips_eabi"); \
524 /* Macro to define tables used to set the flags.
525 This is a list in braces of pairs in braces,
526 each pair being { "NAME", VALUE }
527 where VALUE is the bits to set or minus the bits to clear.
528 An empty string NAME is used to identify the default VALUE. */
530 #define TARGET_SWITCHES \
532 SUBTARGET_TARGET_SWITCHES \
533 {"int64", MASK_INT64 | MASK_LONG64, \
534 N_("Use 64-bit int type")}, \
535 {"long64", MASK_LONG64, \
536 N_("Use 64-bit long type")}, \
537 {"long32", -(MASK_LONG64 | MASK_INT64), \
538 N_("Use 32-bit long type")}, \
539 {"split-addresses", MASK_SPLIT_ADDR, \
540 N_("Optimize lui/addiu address loads")}, \
541 {"no-split-addresses", -MASK_SPLIT_ADDR, \
542 N_("Don't optimize lui/addiu address loads")}, \
543 {"mips-as", -MASK_GAS, \
544 N_("Use MIPS as")}, \
547 {"rnames", MASK_NAME_REGS, \
548 N_("Use symbolic register names")}, \
549 {"no-rnames", -MASK_NAME_REGS, \
550 N_("Don't use symbolic register names")}, \
551 {"gpOPT", MASK_GPOPT, \
552 N_("Use GP relative sdata/sbss sections")}, \
553 {"gpopt", MASK_GPOPT, \
554 N_("Use GP relative sdata/sbss sections")}, \
555 {"no-gpOPT", -MASK_GPOPT, \
556 N_("Don't use GP relative sdata/sbss sections")}, \
557 {"no-gpopt", -MASK_GPOPT, \
558 N_("Don't use GP relative sdata/sbss sections")}, \
560 N_("Output compiler statistics (now ignored)")}, \
562 N_("Don't output compiler statistics")}, \
563 {"memcpy", MASK_MEMCPY, \
564 N_("Don't optimize block moves")}, \
565 {"no-memcpy", -MASK_MEMCPY, \
566 N_("Optimize block moves")}, \
567 {"mips-tfile", MASK_MIPS_TFILE, \
568 N_("Use mips-tfile asm postpass")}, \
569 {"no-mips-tfile", -MASK_MIPS_TFILE, \
570 N_("Don't use mips-tfile asm postpass")}, \
571 {"soft-float", MASK_SOFT_FLOAT, \
572 N_("Use software floating point")}, \
573 {"hard-float", -MASK_SOFT_FLOAT, \
574 N_("Use hardware floating point")}, \
575 {"fp64", MASK_FLOAT64, \
576 N_("Use 64-bit FP registers")}, \
577 {"fp32", -MASK_FLOAT64, \
578 N_("Use 32-bit FP registers")}, \
579 {"gp64", MASK_64BIT, \
580 N_("Use 64-bit general registers")}, \
581 {"gp32", -MASK_64BIT, \
582 N_("Use 32-bit general registers")}, \
583 {"abicalls", MASK_ABICALLS, \
584 N_("Use Irix PIC")}, \
585 {"no-abicalls", -MASK_ABICALLS, \
586 N_("Don't use Irix PIC")}, \
587 {"long-calls", MASK_LONG_CALLS, \
588 N_("Use indirect calls")}, \
589 {"no-long-calls", -MASK_LONG_CALLS, \
590 N_("Don't use indirect calls")}, \
591 {"embedded-pic", MASK_EMBEDDED_PIC, \
592 N_("Use embedded PIC")}, \
593 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
594 N_("Don't use embedded PIC")}, \
595 {"embedded-data", MASK_EMBEDDED_DATA, \
596 N_("Use ROM instead of RAM")}, \
597 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
598 N_("Don't use ROM instead of RAM")}, \
599 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
600 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
601 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
602 N_("Don't put uninitialized constants in ROM")}, \
603 {"eb", MASK_BIG_ENDIAN, \
604 N_("Use big-endian byte order")}, \
605 {"el", -MASK_BIG_ENDIAN, \
606 N_("Use little-endian byte order")}, \
607 {"single-float", MASK_SINGLE_FLOAT, \
608 N_("Use single (32-bit) FP only")}, \
609 {"double-float", -MASK_SINGLE_FLOAT, \
610 N_("Don't use single (32-bit) FP only")}, \
612 N_("Use multiply accumulate")}, \
613 {"no-mad", -MASK_MAD, \
614 N_("Don't use multiply accumulate")}, \
615 {"no-fused-madd", MASK_NO_FUSED_MADD, \
616 N_("Don't generate fused multiply/add instructions")}, \
617 {"fused-madd", -MASK_NO_FUSED_MADD, \
618 N_("Generate fused multiply/add instructions")}, \
619 {"fix4300", MASK_4300_MUL_FIX, \
620 N_("Work around early 4300 hardware bug")}, \
621 {"no-fix4300", -MASK_4300_MUL_FIX, \
622 N_("Don't work around early 4300 hardware bug")}, \
623 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
624 N_("Trap on integer divide by zero")}, \
625 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
626 N_("Don't trap on integer divide by zero")}, \
627 {"check-range-division",MASK_CHECK_RANGE_DIV, \
628 N_("Trap on integer divide overflow")}, \
629 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
630 N_("Don't trap on integer divide overflow")}, \
631 { "branch-likely", MASK_BRANCHLIKELY, \
632 N_("Use Branch Likely instructions, overriding default for arch")}, \
633 { "no-branch-likely", -MASK_BRANCHLIKELY, \
634 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
635 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
636 N_("Use NewABI-style %reloc() assembly operators")}, \
637 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
638 N_("Use assembler macros instead of relocation operators")}, \
639 {"debug", MASK_DEBUG, \
641 {"debuga", MASK_DEBUG_A, \
643 {"debugb", MASK_DEBUG_B, \
645 {"debugc", MASK_DEBUG_C, \
647 {"debugd", MASK_DEBUG_D, \
649 {"debuge", MASK_DEBUG_E, \
651 {"debugf", MASK_DEBUG_F, \
653 {"debugg", MASK_DEBUG_G, \
655 {"debugi", MASK_DEBUG_I, \
657 {"", (TARGET_DEFAULT \
658 | TARGET_CPU_DEFAULT \
659 | TARGET_ENDIAN_DEFAULT), \
663 /* Default target_flags if no switches are specified */
665 #ifndef TARGET_DEFAULT
666 #define TARGET_DEFAULT 0
669 #ifndef TARGET_CPU_DEFAULT
670 #define TARGET_CPU_DEFAULT 0
673 #ifndef TARGET_ENDIAN_DEFAULT
674 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
677 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
678 #ifndef MIPS_ISA_DEFAULT
679 #ifndef MIPS_CPU_STRING_DEFAULT
680 #define MIPS_CPU_STRING_DEFAULT "from-abi"
686 /* Make this compile time constant for libgcc2 */
688 #define TARGET_64BIT 1
690 #define TARGET_64BIT 0
692 #endif /* IN_LIBGCC2 */
694 #ifndef MULTILIB_ENDIAN_DEFAULT
695 #if TARGET_ENDIAN_DEFAULT == 0
696 #define MULTILIB_ENDIAN_DEFAULT "EL"
698 #define MULTILIB_ENDIAN_DEFAULT "EB"
702 #ifndef MULTILIB_ISA_DEFAULT
703 # if MIPS_ISA_DEFAULT == 1
704 # define MULTILIB_ISA_DEFAULT "mips1"
706 # if MIPS_ISA_DEFAULT == 2
707 # define MULTILIB_ISA_DEFAULT "mips2"
709 # if MIPS_ISA_DEFAULT == 3
710 # define MULTILIB_ISA_DEFAULT "mips3"
712 # if MIPS_ISA_DEFAULT == 4
713 # define MULTILIB_ISA_DEFAULT "mips4"
715 # if MIPS_ISA_DEFAULT == 32
716 # define MULTILIB_ISA_DEFAULT "mips32"
718 # if MIPS_ISA_DEFAULT == 33
719 # define MULTILIB_ISA_DEFAULT "mips32r2"
721 # if MIPS_ISA_DEFAULT == 64
722 # define MULTILIB_ISA_DEFAULT "mips64"
724 # define MULTILIB_ISA_DEFAULT "mips1"
734 #ifndef MULTILIB_DEFAULTS
735 #define MULTILIB_DEFAULTS \
736 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
739 /* We must pass -EL to the linker by default for little endian embedded
740 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
741 linker will default to using big-endian output files. The OUTPUT_FORMAT
742 line must be in the linker script, otherwise -EB/-EL will not work. */
745 #if TARGET_ENDIAN_DEFAULT == 0
746 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
748 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
752 #define TARGET_OPTIONS \
754 SUBTARGET_TARGET_OPTIONS \
755 { "tune=", &mips_tune_string, \
756 N_("Specify CPU for scheduling purposes"), 0}, \
757 { "arch=", &mips_arch_string, \
758 N_("Specify CPU for code generation purposes"), 0}, \
759 { "abi=", &mips_abi_string, \
760 N_("Specify an ABI"), 0}, \
761 { "ips", &mips_isa_string, \
762 N_("Specify a Standard MIPS ISA"), 0}, \
763 { "entry", &mips_entry_string, \
764 N_("Use mips16 entry/exit psuedo ops"), 0}, \
765 { "no-mips16", &mips_no_mips16_string, \
766 N_("Don't use MIPS16 instructions"), 0}, \
767 { "no-flush-func", &mips_cache_flush_func, \
768 N_("Don't call any cache flush functions"), 0}, \
769 { "flush-func=", &mips_cache_flush_func, \
770 N_("Specify cache flush function"), 0}, \
773 /* This is meant to be redefined in the host dependent files. */
774 #define SUBTARGET_TARGET_OPTIONS
776 /* Support for a compile-time default CPU, et cetera. The rules are:
777 --with-arch is ignored if -march is specified or a -mips is specified
778 (other than -mips16).
779 --with-tune is ignored if -mtune is specified.
780 --with-abi is ignored if -mabi is specified.
781 --with-float is ignored if -mhard-float or -msoft-float are
783 #define OPTION_DEFAULT_SPECS \
784 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
785 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
786 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
787 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
790 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
794 /* Generate three-operand multiply instructions for SImode. */
795 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
803 /* Generate three-operand multiply instructions for DImode. */
804 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
807 /* Macros to decide whether certain features are available or not,
808 depending on the instruction set architecture level. */
810 #define HAVE_SQRT_P() (!ISA_MIPS1)
812 /* True if the ABI can only work with 64-bit integer registers. We
813 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
814 otherwise floating-point registers must also be 64-bit. */
815 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
816 || mips_abi == ABI_O64 \
817 || mips_abi == ABI_N32)
819 /* Likewise for 32-bit regs. */
820 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
822 /* True if symbols are 64 bits wide. At present, n64 is the only
823 ABI for which this is true. */
824 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
826 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
827 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
831 /* ISA has branch likely instructions (eg. mips2). */
832 /* Disable branchlikely for tx39 until compare rewrite. They haven't
833 been generated up to this point. */
834 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
837 /* ISA has the conditional move instructions introduced in mips4. */
838 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
842 && !TARGET_MIPS5500 \
845 /* ISA has just the integer condition move instructions (movn,movz) */
846 #define ISA_HAS_INT_CONDMOVE 0
848 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
849 branch on CC, and move (both FP and non-FP) on CC. */
850 #define ISA_HAS_8CC (ISA_MIPS4 \
855 /* This is a catch all for the other new mips4 instructions: indexed load and
856 indexed prefetch instructions, the FP madd and msub instructions,
857 and the FP recip and recip sqrt instructions */
858 #define ISA_HAS_FP4 ((ISA_MIPS4 \
862 /* ISA has conditional trap instructions. */
863 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
866 /* ISA has integer multiply-accumulate instructions, madd and msub. */
867 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
872 /* ISA has floating-point nmadd and nmsub instructions. */
873 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
875 && (!TARGET_MIPS5400 || TARGET_MAD) \
878 /* ISA has count leading zeroes/ones instruction (not implemented). */
879 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
884 /* ISA has double-word count leading zeroes/ones instruction (not
886 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
889 /* ISA has three operand multiply instructions that put
890 the high part in an accumulator: mulhi or mulhiu. */
891 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
896 /* ISA has three operand multiply instructions that
897 negates the result and puts the result in an accumulator. */
898 #define ISA_HAS_MULS (TARGET_MIPS5400 \
903 /* ISA has three operand multiply instructions that subtracts the
904 result from a 4th operand and puts the result in an accumulator. */
905 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
909 /* ISA has three operand multiply instructions that the result
910 from a 4th operand and puts the result in an accumulator. */
911 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
917 /* ISA has 32-bit rotate right instruction. */
918 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
925 /* ISA has 64-bit rotate right instruction. */
926 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
928 && (TARGET_MIPS5400 \
933 /* ISA has data prefetch instruction. */
934 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
940 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
941 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
942 also requires TARGET_DOUBLE_FLOAT. */
943 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
945 /* ISA includes the MIPS32r2 seb and seh instructions. */
946 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
950 /* True if the result of a load is not available to the next instruction.
951 A nop will then be needed between instructions like "lw $4,..."
952 and "addiu $4,$4,1". */
953 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
954 && !TARGET_MIPS3900 \
957 /* Likewise mtc1 and mfc1. */
958 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
960 /* Likewise floating-point comparisons. */
961 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
963 /* True if mflo and mfhi can be immediately followed by instructions
964 which write to the HI and LO registers. Most targets require a
965 two-instruction gap. */
966 #define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
968 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
969 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
970 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
971 target_flags, and -mgp64 sets MASK_64BIT.
973 Setting MASK_64BIT in target_flags will cause gcc to assume that
974 registers are 64 bits wide. int, long and void * will be 32 bit;
975 this may be changed with -mint64 or -mlong64.
977 The gen* programs link code that refers to MASK_64BIT. They don't
978 actually use the information in target_flags; they just refer to
981 /* Switch Recognition by gcc.c. Add -G xx support */
983 #undef SWITCH_TAKES_ARG
984 #define SWITCH_TAKES_ARG(CHAR) \
985 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
987 /* Sometimes certain combinations of command options do not make sense
988 on a particular target machine. You can define a macro
989 `OVERRIDE_OPTIONS' to take account of this. This macro, if
990 defined, is executed once just after all the command options have
993 On the MIPS, it is used to handle -G. We also use it to set up all
994 of the tables referenced in the other macros. */
996 #define OVERRIDE_OPTIONS override_options ()
998 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1000 /* Show we can debug even without a frame pointer. */
1001 #define CAN_DEBUG_WITHOUT_FP
1003 /* Tell collect what flags to pass to nm. */
1005 #define NM_FLAGS "-Bn"
1009 /* Assembler specs. */
1011 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
1014 #define MIPS_AS_ASM_SPEC "\
1015 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
1016 %{pipe: %e-pipe is not supported} \
1017 %{K} %(subtarget_mips_as_asm_spec)"
1019 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
1020 rather than gas. It may be overridden by subtargets. */
1022 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1023 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1026 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1029 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1031 #define SUBTARGET_TARGET_SWITCHES
1033 extern int mips_abi;
1035 #ifndef MIPS_ABI_DEFAULT
1036 #define MIPS_ABI_DEFAULT ABI_32
1039 /* Use the most portable ABI flag for the ASM specs. */
1041 #if MIPS_ABI_DEFAULT == ABI_32
1042 #define MULTILIB_ABI_DEFAULT "mabi=32"
1043 #define ASM_ABI_DEFAULT_SPEC "-32"
1046 #if MIPS_ABI_DEFAULT == ABI_O64
1047 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1048 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1051 #if MIPS_ABI_DEFAULT == ABI_N32
1052 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1053 #define ASM_ABI_DEFAULT_SPEC "-n32"
1056 #if MIPS_ABI_DEFAULT == ABI_64
1057 #define MULTILIB_ABI_DEFAULT "mabi=64"
1058 #define ASM_ABI_DEFAULT_SPEC "-64"
1061 #if MIPS_ABI_DEFAULT == ABI_EABI
1062 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1063 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1066 /* Only ELF targets can switch the ABI. */
1067 #ifndef OBJECT_FORMAT_ELF
1068 #undef ASM_ABI_DEFAULT_SPEC
1069 #define ASM_ABI_DEFAULT_SPEC ""
1072 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1073 GAS_ASM_SPEC as the default, depending upon the value of
1076 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1079 #define TARGET_ASM_SPEC "\
1080 %{mmips-as: %(mips_as_asm_spec)} \
1081 %{!mmips-as: %(gas_asm_spec)}"
1085 #define TARGET_ASM_SPEC "\
1086 %{!mgas: %(mips_as_asm_spec)} \
1087 %{mgas: %(gas_asm_spec)}"
1089 #endif /* not GAS */
1091 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1092 to the assembler. It may be overridden by subtargets. */
1093 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1094 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1096 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1099 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1100 the assembler. It may be overridden by subtargets. */
1101 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1102 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1103 %{g} %{g0} %{g1} %{g2} %{g3} \
1104 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1105 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1106 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1107 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1111 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1112 and stabs debugging info. */
1113 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1115 #define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1117 #define MDEBUG_ASM_SPEC ""
1118 #endif /* not GAS */
1120 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1121 overridden by subtargets. */
1123 #ifndef SUBTARGET_ASM_SPEC
1124 #define SUBTARGET_ASM_SPEC ""
1127 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1128 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1129 whether we're using GAS. These options can only be used properly
1130 with GAS, and it is better to get an error from a non-GAS assembler
1131 than to silently generate bad code. */
1135 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1136 %{mips32} %{mips32r2} %{mips64} \
1137 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1138 %(subtarget_asm_optimizing_spec) \
1139 %(subtarget_asm_debugging_spec) \
1141 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1142 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1143 %{mgp32} %{mgp64} %{march=*} \
1144 %(target_asm_spec) \
1145 %(subtarget_asm_spec)"
1147 /* Specify to run a post-processor, mips-tfile after the assembler
1148 has run to stuff the mips debug information into the object file.
1149 This is needed because the $#!%^ MIPS assembler provides no way
1150 of specifying such information in the assembly file. If we are
1151 cross compiling, disable mips-tfile unless the user specifies
1154 #ifndef ASM_FINAL_SPEC
1155 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1157 #define ASM_FINAL_SPEC "\
1158 %{mmips-as: %{!mno-mips-tfile: \
1159 \n mips-tfile %{v*: -v} \
1161 %{!K: %{save-temps: -I %b.o~}} \
1162 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1163 %{.s:%i} %{!.s:%g.s}}}"
1167 #define ASM_FINAL_SPEC "\
1168 %{!mgas: %{!mno-mips-tfile: \
1169 \n mips-tfile %{v*: -v} \
1171 %{!K: %{save-temps: -I %b.o~}} \
1172 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1173 %{.s:%i} %{!.s:%g.s}}}"
1176 #endif /* ASM_FINAL_SPEC */
1178 /* Redefinition of libraries used. Mips doesn't support normal
1179 UNIX style profiling via calling _mcount. It does offer
1180 profiling that samples the PC, so do what we can... */
1183 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1186 /* Extra switches sometimes passed to the linker. */
1187 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1188 will interpret it as a -b option. */
1191 #define LINK_SPEC "\
1193 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1194 %{bestGnum} %{shared} %{non_shared}"
1195 #endif /* LINK_SPEC defined */
1198 /* Specs for the compiler proper */
1200 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1201 overridden by subtargets. */
1202 #ifndef SUBTARGET_CC1_SPEC
1203 #define SUBTARGET_CC1_SPEC ""
1206 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1207 /* Note, we will need to adjust the following if we ever find a MIPS variant
1208 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1209 that show up in this case. */
1213 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1214 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1216 %(subtarget_cc1_spec)"
1219 /* Preprocessor specs. */
1221 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1222 overridden by subtargets. */
1223 #ifndef SUBTARGET_CPP_SPEC
1224 #define SUBTARGET_CPP_SPEC ""
1227 #define CPP_SPEC "%(subtarget_cpp_spec)"
1229 /* This macro defines names of additional specifications to put in the specs
1230 that can be used in various specifications like CC1_SPEC. Its definition
1231 is an initializer with a subgrouping for each command option.
1233 Each subgrouping contains a string constant, that defines the
1234 specification name, and a string constant that used by the GNU CC driver
1237 Do not define this macro if it does not need to do anything. */
1239 #define EXTRA_SPECS \
1240 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1241 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1242 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1243 { "gas_asm_spec", GAS_ASM_SPEC }, \
1244 { "target_asm_spec", TARGET_ASM_SPEC }, \
1245 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1246 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1247 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1248 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1249 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1250 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1251 { "endian_spec", ENDIAN_SPEC }, \
1252 SUBTARGET_EXTRA_SPECS
1254 #ifndef SUBTARGET_EXTRA_SPECS
1255 #define SUBTARGET_EXTRA_SPECS
1258 /* If defined, this macro is an additional prefix to try after
1259 `STANDARD_EXEC_PREFIX'. */
1261 #ifndef MD_EXEC_PREFIX
1262 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1265 #ifndef MD_STARTFILE_PREFIX
1266 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1270 /* Print subsidiary information on the compiler version in use. */
1272 #define MIPS_VERSION "[AL 1.1, MM 40]"
1274 #ifndef MACHINE_TYPE
1275 #define MACHINE_TYPE "BSD Mips"
1278 #ifndef TARGET_VERSION_INTERNAL
1279 #define TARGET_VERSION_INTERNAL(STREAM) \
1280 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1283 #ifndef TARGET_VERSION
1284 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1288 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1289 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1290 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1292 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1293 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1296 /* By default, turn on GDB extensions. */
1297 #define DEFAULT_GDB_EXTENSIONS 1
1299 /* If we are passing smuggling stabs through the MIPS ECOFF object
1300 format, put a comment in front of the .stab<x> operation so
1301 that the MIPS assembler does not choke. The mips-tfile program
1302 will correctly put the stab into the object file. */
1304 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1305 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1306 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1308 /* Local compiler-generated symbols must have a prefix that the assembler
1309 understands. By default, this is $, although some targets (e.g.,
1310 NetBSD-ELF) need to override this. */
1312 #ifndef LOCAL_LABEL_PREFIX
1313 #define LOCAL_LABEL_PREFIX "$"
1316 /* By default on the mips, external symbols do not have an underscore
1317 prepended, but some targets (e.g., NetBSD) require this. */
1319 #ifndef USER_LABEL_PREFIX
1320 #define USER_LABEL_PREFIX ""
1323 /* Forward references to tags are allowed. */
1324 #define SDB_ALLOW_FORWARD_REFERENCES
1326 /* Unknown tags are also allowed. */
1327 #define SDB_ALLOW_UNKNOWN_REFERENCES
1329 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1330 since the length can run past this up to a continuation point. */
1331 #undef DBX_CONTIN_LENGTH
1332 #define DBX_CONTIN_LENGTH 1500
1334 /* How to renumber registers for dbx and gdb. */
1335 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1337 /* The mapping from gcc register number to DWARF 2 CFA column number.
1338 This mapping does not allow for tracking register 0, since SGI's broken
1339 dwarf reader thinks column 0 is used for the frame address, but since
1340 register 0 is fixed this is not a problem. */
1341 #define DWARF_FRAME_REGNUM(REG) \
1342 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1344 /* The DWARF 2 CFA column which tracks the return address. */
1345 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1347 /* Before the prologue, RA lives in r31. */
1348 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1350 /* Describe how we implement __builtin_eh_return. */
1351 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1352 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1354 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1355 The default for this in 64-bit mode is 8, which causes problems with
1356 SFmode register saves. */
1357 #define DWARF_CIE_DATA_ALIGNMENT 4
1359 #define FIND_BASE_TERM(X) mips_delegitimize_address (X)
1361 #define PUT_SDB_DEF(a) \
1363 fprintf (asm_out_file, "\t%s.def\t", \
1364 (TARGET_GAS) ? "" : "#"); \
1365 ASM_OUTPUT_LABELREF (asm_out_file, a); \
1366 fputc (';', asm_out_file); \
1369 #define PUT_SDB_PLAIN_DEF(a) \
1371 fprintf (asm_out_file, "\t%s.def\t.%s;", \
1372 (TARGET_GAS) ? "" : "#", (a)); \
1375 /* For block start and end, we create labels, so that
1376 later we can figure out where the correct offset is.
1377 The normal .ent/.end serve well enough for functions,
1378 so those are just commented out. */
1380 #define PUT_SDB_BLOCK_START(LINE) \
1382 fprintf (asm_out_file, \
1383 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1384 LOCAL_LABEL_PREFIX, \
1386 (TARGET_GAS) ? "" : "#", \
1387 LOCAL_LABEL_PREFIX, \
1390 sdb_label_count++; \
1393 #define PUT_SDB_BLOCK_END(LINE) \
1395 fprintf (asm_out_file, \
1396 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1397 LOCAL_LABEL_PREFIX, \
1399 (TARGET_GAS) ? "" : "#", \
1400 LOCAL_LABEL_PREFIX, \
1403 sdb_label_count++; \
1406 #define PUT_SDB_FUNCTION_START(LINE)
1408 #define PUT_SDB_FUNCTION_END(LINE) \
1410 ASM_OUTPUT_SOURCE_LINE (asm_out_file, LINE + sdb_begin_function_line); \
1413 #define PUT_SDB_EPILOGUE_END(NAME)
1415 /* Correct the offset of automatic variables and arguments. Note that
1416 the MIPS debug format wants all automatic variables and arguments
1417 to be in terms of the virtual frame pointer (stack pointer before
1418 any adjustment in the function), while the MIPS 3.0 linker wants
1419 the frame pointer to be the stack pointer after the initial
1422 #define DEBUGGER_AUTO_OFFSET(X) \
1423 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1424 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1425 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1427 /* Tell collect that the object format is ECOFF */
1428 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1429 #define EXTENDED_COFF /* ECOFF, not normal coff */
1431 /* Target machine storage layout */
1433 /* Define this if most significant bit is lowest numbered
1434 in instructions that operate on numbered bit-fields.
1436 #define BITS_BIG_ENDIAN 0
1438 /* Define this if most significant byte of a word is the lowest numbered. */
1439 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1441 /* Define this if most significant word of a multiword number is the lowest. */
1442 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1444 /* Define this to set the endianness to use in libgcc2.c, which can
1445 not depend on target_flags. */
1446 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1447 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1449 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1452 #define MAX_BITS_PER_WORD 64
1454 /* Width of a word, in units (bytes). */
1455 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1456 #define MIN_UNITS_PER_WORD 4
1458 /* For MIPS, width of a floating point register. */
1459 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1461 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1462 the next available register. */
1463 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1465 /* The largest size of value that can be held in floating-point
1466 registers and moved with a single instruction. */
1467 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1469 /* The largest size of value that can be held in floating-point
1471 #define UNITS_PER_FPVALUE \
1472 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1474 /* The number of bytes in a double. */
1475 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1477 /* A C expression for the size in bits of the type `int' on the
1478 target machine. If you don't define this, the default is one
1480 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1482 /* Tell the preprocessor the maximum size of wchar_t. */
1483 #ifndef MAX_WCHAR_TYPE_SIZE
1484 #ifndef WCHAR_TYPE_SIZE
1485 #define MAX_WCHAR_TYPE_SIZE 64
1489 /* A C expression for the size in bits of the type `short' on the
1490 target machine. If you don't define this, the default is half a
1491 word. (If this would be less than one storage unit, it is
1492 rounded up to one unit.) */
1493 #define SHORT_TYPE_SIZE 16
1495 /* A C expression for the size in bits of the type `long' on the
1496 target machine. If you don't define this, the default is one
1498 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1499 #define MAX_LONG_TYPE_SIZE 64
1501 /* A C expression for the size in bits of the type `long long' on the
1502 target machine. If you don't define this, the default is two
1504 #define LONG_LONG_TYPE_SIZE 64
1506 /* A C expression for the size in bits of the type `float' on the
1507 target machine. If you don't define this, the default is one
1509 #define FLOAT_TYPE_SIZE 32
1511 /* A C expression for the size in bits of the type `double' on the
1512 target machine. If you don't define this, the default is two
1514 #define DOUBLE_TYPE_SIZE 64
1516 /* A C expression for the size in bits of the type `long double' on
1517 the target machine. If you don't define this, the default is two
1519 #define LONG_DOUBLE_TYPE_SIZE \
1520 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1522 /* long double is not a fixed mode, but the idea is that, if we
1523 support long double, we also want a 128-bit integer type. */
1524 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1527 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1528 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1529 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1531 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1535 /* Width in bits of a pointer. */
1536 #ifndef POINTER_SIZE
1537 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1540 #define POINTERS_EXTEND_UNSIGNED 0
1542 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1543 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1544 || mips_abi == ABI_64 \
1545 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1548 /* Allocation boundary (in *bits*) for the code of a function. */
1549 #define FUNCTION_BOUNDARY 32
1551 /* Alignment of field after `int : 0' in a structure. */
1552 #define EMPTY_FIELD_BOUNDARY 32
1554 /* Every structure's size must be a multiple of this. */
1555 /* 8 is observed right on a DECstation and on riscos 4.02. */
1556 #define STRUCTURE_SIZE_BOUNDARY 8
1558 /* There is no point aligning anything to a rounder boundary than this. */
1559 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1561 /* Set this nonzero if move instructions will actually fail to work
1562 when given unaligned data. */
1563 #define STRICT_ALIGNMENT 1
1565 /* Define this if you wish to imitate the way many other C compilers
1566 handle alignment of bitfields and the structures that contain
1569 The behavior is that the type written for a bit-field (`int',
1570 `short', or other integer type) imposes an alignment for the
1571 entire structure, as if the structure really did contain an
1572 ordinary field of that type. In addition, the bit-field is placed
1573 within the structure so that it would fit within such a field,
1574 not crossing a boundary for it.
1576 Thus, on most machines, a bit-field whose type is written as `int'
1577 would not cross a four-byte boundary, and would force four-byte
1578 alignment for the whole structure. (The alignment used may not
1579 be four bytes; it is controlled by the other alignment
1582 If the macro is defined, its definition should be a C expression;
1583 a nonzero value for the expression enables this behavior. */
1585 #define PCC_BITFIELD_TYPE_MATTERS 1
1587 /* If defined, a C expression to compute the alignment given to a
1588 constant that is being placed in memory. CONSTANT is the constant
1589 and ALIGN is the alignment that the object would ordinarily have.
1590 The value of this macro is used instead of that alignment to align
1593 If this macro is not defined, then ALIGN is used.
1595 The typical use of this macro is to increase alignment for string
1596 constants to be word aligned so that `strcpy' calls that copy
1597 constants can be done inline. */
1599 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1600 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1601 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1603 /* If defined, a C expression to compute the alignment for a static
1604 variable. TYPE is the data type, and ALIGN is the alignment that
1605 the object would ordinarily have. The value of this macro is used
1606 instead of that alignment to align the object.
1608 If this macro is not defined, then ALIGN is used.
1610 One use of this macro is to increase alignment of medium-size
1611 data to make it all fit in fewer cache lines. Another is to
1612 cause character arrays to be word-aligned so that `strcpy' calls
1613 that copy constants to character arrays can be done inline. */
1615 #undef DATA_ALIGNMENT
1616 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1617 ((((ALIGN) < BITS_PER_WORD) \
1618 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1619 || TREE_CODE (TYPE) == UNION_TYPE \
1620 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1623 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1625 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1627 /* Define this macro if an argument declared as `char' or `short' in a
1628 prototype should actually be passed as an `int'. In addition to
1629 avoiding errors in certain cases of mismatch, it also makes for
1630 better code on certain machines. */
1632 #define PROMOTE_PROTOTYPES 1
1634 /* Define if operations between registers always perform the operation
1635 on the full register even if a narrower mode is specified. */
1636 #define WORD_REGISTER_OPERATIONS
1638 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1639 will either zero-extend or sign-extend. The value of this macro should
1640 be the code that says which one of the two operations is implicitly
1643 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1644 moves. All other referces are zero extended. */
1645 #define LOAD_EXTEND_OP(MODE) \
1646 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1647 ? SIGN_EXTEND : ZERO_EXTEND)
1649 /* Define this macro if it is advisable to hold scalars in registers
1650 in a wider mode than that declared by the program. In such cases,
1651 the value is constrained to be within the bounds of the declared
1652 type, but kept valid in the wider mode. The signedness of the
1653 extension may differ from that of the type. */
1655 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1656 if (GET_MODE_CLASS (MODE) == MODE_INT \
1657 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1659 if ((MODE) == SImode) \
1664 /* Define if loading short immediate values into registers sign extends. */
1665 #define SHORT_IMMEDIATES_SIGN_EXTEND
1668 /* Define this if function arguments should also be promoted using the above
1670 #define PROMOTE_FUNCTION_ARGS
1672 /* Likewise, if the function return value is promoted. */
1673 #define PROMOTE_FUNCTION_RETURN
1676 /* Standard register usage. */
1678 /* Number of actual hardware registers.
1679 The hardware registers are assigned numbers for the compiler
1680 from 0 to just below FIRST_PSEUDO_REGISTER.
1681 All registers that the compiler knows about must be given numbers,
1682 even those that are not normally considered general registers.
1684 On the Mips, we have 32 integer registers, 32 floating point
1685 registers, 8 condition code registers, and the special registers
1686 hi and lo. After that we have 32 COP0 registers, 32 COP2 registers,
1687 and 32 COP3 registers. (COP1 is the floating-point processor.)
1688 The 8 condition code registers are only used if mips_isa >= 4. */
1690 #define FIRST_PSEUDO_REGISTER 176
1692 /* 1 for registers that have pervasive standard uses
1693 and are not available for the register allocator.
1695 On the MIPS, see conventions, page D-2 */
1697 /* Regarding coprocessor registers: without evidence to the contrary,
1698 it's best to assume that each coprocessor register has a unique
1699 use. This can be overridden, in, e.g., override_options() or
1700 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1701 for a particular target. */
1703 #define FIXED_REGISTERS \
1705 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1706 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1707 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1708 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1709 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1710 /* COP0 registers */ \
1711 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1712 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1713 /* COP2 registers */ \
1714 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1715 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1716 /* COP3 registers */ \
1717 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1718 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1722 /* Don't mark $31 as a call-clobbered register. The idea is that
1723 it's really the call instructions themselves which clobber $31.
1724 We don't care what the called function does with it afterwards.
1726 This approach makes it easier to implement sibcalls. Unlike normal
1727 calls, sibcalls don't clobber $31, so the register reaches the
1728 called function in tact. EPILOGUE_USES says that $31 is useful
1729 to the called function. */
1731 #define CALL_USED_REGISTERS \
1733 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1734 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1735 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1736 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1737 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1738 /* COP0 registers */ \
1739 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1740 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1741 /* COP2 registers */ \
1742 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1743 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1744 /* COP3 registers */ \
1745 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1746 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1749 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1750 problem which makes CALL_USED_REGISTERS *always* include
1751 all the FIXED_REGISTERS. Until this problem has been
1752 resolved this macro can be used to overcome this situation.
1753 In particular, block_propagate() requires this list
1754 be acurate, or we can remove registers which should be live.
1755 This macro is used in regs_invalidated_by_call. */
1758 #define CALL_REALLY_USED_REGISTERS \
1759 { /* General registers. */ \
1760 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1761 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1762 /* Floating-point registers. */ \
1763 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1764 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1766 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1767 /* COP0 registers */ \
1768 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1769 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1770 /* COP2 registers */ \
1771 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1772 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1773 /* COP3 registers */ \
1774 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1775 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1778 /* Internal macros to classify a register number as to whether it's a
1779 general purpose register, a floating point register, a
1780 multiply/divide register, or a status register. */
1782 #define GP_REG_FIRST 0
1783 #define GP_REG_LAST 31
1784 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1785 #define GP_DBX_FIRST 0
1787 #define FP_REG_FIRST 32
1788 #define FP_REG_LAST 63
1789 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1790 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1792 #define MD_REG_FIRST 64
1793 #define MD_REG_LAST 65
1794 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1795 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1797 #define ST_REG_FIRST 67
1798 #define ST_REG_LAST 74
1799 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1802 /* FIXME: renumber. */
1803 #define COP0_REG_FIRST 80
1804 #define COP0_REG_LAST 111
1805 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1807 #define COP2_REG_FIRST 112
1808 #define COP2_REG_LAST 143
1809 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1811 #define COP3_REG_FIRST 144
1812 #define COP3_REG_LAST 175
1813 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1814 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1815 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1817 #define AT_REGNUM (GP_REG_FIRST + 1)
1818 #define HI_REGNUM (MD_REG_FIRST + 0)
1819 #define LO_REGNUM (MD_REG_FIRST + 1)
1821 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1822 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1823 should be used instead. */
1824 #define FPSW_REGNUM ST_REG_FIRST
1826 #define GP_REG_P(REGNO) \
1827 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1828 #define M16_REG_P(REGNO) \
1829 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1830 #define FP_REG_P(REGNO) \
1831 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1832 #define MD_REG_P(REGNO) \
1833 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1834 #define ST_REG_P(REGNO) \
1835 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1836 #define COP0_REG_P(REGNO) \
1837 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1838 #define COP2_REG_P(REGNO) \
1839 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1840 #define COP3_REG_P(REGNO) \
1841 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1842 #define ALL_COP_REG_P(REGNO) \
1843 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1845 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1847 /* Return coprocessor number from register number. */
1849 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1850 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1851 : COP3_REG_P (REGNO) ? '3' : '?')
1853 /* Return number of consecutive hard regs needed starting at reg REGNO
1854 to hold something of mode MODE.
1855 This is ordinarily the length in words of a value of mode MODE
1856 but can be less for certain modes in special long registers.
1858 On the MIPS, all general registers are one word long. Except on
1859 the R4000 with the FR bit set, the floating point uses register
1860 pairs, with the second register not being allocable. */
1862 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1864 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1865 MODE. In 32 bit mode, require that DImode and DFmode be in even
1866 registers. For DImode, this makes some of the insns easier to
1867 write, since you don't have to worry about a DImode value in
1868 registers 3 & 4, producing a result in 4 & 5.
1870 To make the code simpler HARD_REGNO_MODE_OK now just references an
1871 array built in override_options. Because machmodes.h is not yet
1872 included before this file is processed, the MODE bound can't be
1875 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1877 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1878 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1880 /* Value is 1 if it is a good idea to tie two pseudo registers
1881 when one has mode MODE1 and one has mode MODE2.
1882 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1883 for any hard reg, then this must be 0 for correct output. */
1884 #define MODES_TIEABLE_P(MODE1, MODE2) \
1885 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1886 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1887 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1888 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1890 /* MIPS pc is not overloaded on a register. */
1891 /* #define PC_REGNUM xx */
1893 /* Register to use for pushing function arguments. */
1894 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1896 /* Offset from the stack pointer to the first available location. Use
1897 the default value zero. */
1898 /* #define STACK_POINTER_OFFSET 0 */
1900 /* Base register for access to local variables of the function. We
1901 pretend that the frame pointer is $1, and then eliminate it to
1902 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1903 a fixed register, and will not be used for anything else. */
1904 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1906 /* Temporary scratch register for use by the assembler. */
1907 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1909 /* $30 is not available on the mips16, so we use $17 as the frame
1911 #define HARD_FRAME_POINTER_REGNUM \
1912 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1914 /* Value should be nonzero if functions must have frame pointers.
1915 Zero means the frame pointer need not be set up (and parms
1916 may be accessed via the stack pointer) in functions that seem suitable.
1917 This is computed in `reload', in reload1.c. */
1918 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1920 /* Base register for access to arguments of the function. */
1921 #define ARG_POINTER_REGNUM GP_REG_FIRST
1923 /* Register in which static-chain is passed to a function. */
1924 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1926 /* If the structure value address is passed in a register, then
1927 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1928 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1930 /* If the structure value address is not passed in a register, define
1931 `STRUCT_VALUE' as an expression returning an RTX for the place
1932 where the address is passed. If it returns 0, the address is
1933 passed as an "invisible" first argument. */
1934 #define STRUCT_VALUE 0
1936 /* Mips registers used in prologue/epilogue code when the stack frame
1937 is larger than 32K bytes. These registers must come from the
1938 scratch register set, and not used for passing and returning
1939 arguments and any other information used in the calling sequence
1940 (such as pic). Must start at 12, since t0/t3 are parameter passing
1941 registers in the 64 bit ABI. */
1943 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1944 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1946 /* Define this macro if it is as good or better to call a constant
1947 function address than to call an address kept in a register. */
1948 #define NO_FUNCTION_CSE 1
1950 /* Define this macro if it is as good or better for a function to
1951 call itself with an explicit address than to call an address
1952 kept in a register. */
1953 #define NO_RECURSIVE_FUNCTION_CSE 1
1955 /* The register number of the register used to address a table of
1956 static data addresses in memory. In some cases this register is
1957 defined by a processor's "application binary interface" (ABI).
1958 When this macro is defined, RTL is generated for this register
1959 once, as with the stack pointer and frame pointer registers. If
1960 this macro is not defined, it is up to the machine-dependent
1961 files to allocate such a register (if necessary). */
1962 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1964 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1966 /* Define the classes of registers for register constraints in the
1967 machine description. Also define ranges of constants.
1969 One of the classes must always be named ALL_REGS and include all hard regs.
1970 If there is more than one class, another class must be named NO_REGS
1971 and contain no registers.
1973 The name GENERAL_REGS must be the name of a class (or an alias for
1974 another name such as ALL_REGS). This is the class of registers
1975 that is allowed by "g" or "r" in a register constraint.
1976 Also, registers outside this class are allocated only when
1977 instructions express preferences for them.
1979 The classes must be numbered in nondecreasing order; that is,
1980 a larger-numbered class must never be contained completely
1981 in a smaller-numbered class.
1983 For any two classes, it is very desirable that there be another
1984 class that represents their union. */
1988 NO_REGS, /* no registers in set */
1989 M16_NA_REGS, /* mips16 regs not used to pass args */
1990 M16_REGS, /* mips16 directly accessible registers */
1991 T_REG, /* mips16 T register ($24) */
1992 M16_T_REGS, /* mips16 registers plus T register */
1993 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1994 LEA_REGS, /* Every GPR except $25 */
1995 GR_REGS, /* integer registers */
1996 FP_REGS, /* floating point registers */
1997 HI_REG, /* hi register */
1998 LO_REG, /* lo register */
1999 MD_REGS, /* multiply/divide registers (hi/lo) */
2000 COP0_REGS, /* generic coprocessor classes */
2003 HI_AND_GR_REGS, /* union classes */
2010 ALL_COP_AND_GR_REGS,
2011 ST_REGS, /* status registers (fp status) */
2012 ALL_REGS, /* all registers */
2013 LIM_REG_CLASSES /* max value + 1 */
2016 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2018 #define GENERAL_REGS GR_REGS
2020 /* An initializer containing the names of the register classes as C
2021 string constants. These names are used in writing some of the
2024 #define REG_CLASS_NAMES \
2031 "PIC_FN_ADDR_REG", \
2038 /* coprocessor registers */ \
2045 "COP0_AND_GR_REGS", \
2046 "COP2_AND_GR_REGS", \
2047 "COP3_AND_GR_REGS", \
2049 "ALL_COP_AND_GR_REGS", \
2054 /* An initializer containing the contents of the register classes,
2055 as integers which are bit masks. The Nth integer specifies the
2056 contents of class N. The way the integer MASK is interpreted is
2057 that register R is in the class if `MASK & (1 << R)' is 1.
2059 When the machine has more than 32 registers, an integer does not
2060 suffice. Then the integers are replaced by sub-initializers,
2061 braced groupings containing several integers. Each
2062 sub-initializer must be suitable as an initializer for the type
2063 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2065 #define REG_CLASS_CONTENTS \
2067 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2068 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2069 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2070 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2071 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2072 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
2073 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
2074 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2075 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2076 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2077 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2078 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2079 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2080 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2081 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2082 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2083 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2084 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2085 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2086 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2087 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2088 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2089 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2090 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2091 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2095 /* A C expression whose value is a register class containing hard
2096 register REGNO. In general there is more that one such class;
2097 choose a class which is "minimal", meaning that no smaller class
2098 also contains the register. */
2100 extern const enum reg_class mips_regno_to_class[];
2102 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2104 /* A macro whose definition is the name of the class to which a
2105 valid base register must belong. A base register is one used in
2106 an address which is the register value plus a displacement. */
2108 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2110 /* A macro whose definition is the name of the class to which a
2111 valid index register must belong. An index register is one used
2112 in an address where its value is either multiplied by a scale
2113 factor or added to another register (as well as added to a
2116 #define INDEX_REG_CLASS NO_REGS
2118 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2119 registers explicitly used in the rtl to be used as spill registers
2120 but prevents the compiler from extending the lifetime of these
2123 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2125 /* This macro is used later on in the file. */
2126 #define GR_REG_CLASS_P(CLASS) \
2127 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2128 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
2129 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
2131 /* This macro is also used later on in the file. */
2132 #define COP_REG_CLASS_P(CLASS) \
2133 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2135 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2136 is the default value (allocate the registers in numeric order). We
2137 define it just so that we can override it for the mips16 target in
2138 ORDER_REGS_FOR_LOCAL_ALLOC. */
2140 #define REG_ALLOC_ORDER \
2141 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2142 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2143 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2144 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2145 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2146 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2147 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2148 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2149 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2150 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2151 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2154 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2155 to be rearranged based on a particular function. On the mips16, we
2156 want to allocate $24 (T_REG) before other registers for
2157 instructions for which it is possible. */
2159 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2161 /* REGISTER AND CONSTANT CLASSES */
2163 /* Get reg_class from a letter such as appears in the machine
2166 DEFINED REGISTER CLASSES:
2168 'd' General (aka integer) registers
2169 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2170 'y' General registers (in both mips16 and non mips16 mode)
2171 'e' mips16 non argument registers (M16_NA_REGS)
2172 't' mips16 temporary register ($24)
2173 'f' Floating point registers
2176 'x' Multiply/divide registers
2177 'z' FP Status register
2181 'b' All registers */
2183 extern enum reg_class mips_char_to_class[256];
2185 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2187 /* True if VALUE is a signed 16-bit number. */
2189 #define SMALL_OPERAND(VALUE) \
2190 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2192 /* True if VALUE is an unsigned 16-bit number. */
2194 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2195 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2197 /* True if VALUE can be loaded into a register using LUI. */
2199 #define LUI_OPERAND(VALUE) \
2200 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2201 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2203 /* Return a value X with the low 16 bits clear, and such that
2204 VALUE - X is a signed 16-bit value. */
2206 #define CONST_HIGH_PART(VALUE) \
2207 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2209 #define CONST_LOW_PART(VALUE) \
2210 ((VALUE) - CONST_HIGH_PART (VALUE))
2212 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2213 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2214 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2216 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2217 string can be used to stand for particular ranges of immediate
2218 operands. This macro defines what the ranges are. C is the
2219 letter, and VALUE is a constant value. Return 1 if VALUE is
2220 in the range specified by C. */
2224 `I' is used for the range of constants an arithmetic insn can
2225 actually contain (16 bits signed integers).
2227 `J' is used for the range which is just zero (ie, $r0).
2229 `K' is used for the range of constants a logical insn can actually
2230 contain (16 bit zero-extended integers).
2232 `L' is used for the range of constants that be loaded with lui
2233 (ie, the bottom 16 bits are zero).
2235 `M' is used for the range of constants that take two words to load
2236 (ie, not matched by `I', `K', and `L').
2238 `N' is used for negative 16 bit constants other than -65536.
2240 `O' is a 15 bit signed integer.
2242 `P' is used for positive 16 bit constants. */
2244 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2245 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2246 : (C) == 'J' ? ((VALUE) == 0) \
2247 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2248 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2249 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2250 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2251 && !LUI_OPERAND (VALUE)) \
2252 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2253 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2254 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2257 /* Similar, but for floating constants, and defining letters G and H.
2258 Here VALUE is the CONST_DOUBLE rtx itself. */
2262 'G' : Floating point 0 */
2264 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2266 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2268 /* True if OP is a constant that should not be moved into $25.
2269 We need this because many versions of gas treat 'la $25,foo' as
2270 part of a call sequence and allow a global 'foo' to be lazily bound. */
2272 #define DANGEROUS_FOR_LA25_P(OP) \
2274 && !TARGET_EXPLICIT_RELOCS \
2275 && mips_global_pic_constant_p (OP))
2277 /* Letters in the range `Q' through `U' may be defined in a
2278 machine-dependent fashion to stand for arbitrary operand types.
2279 The machine description macro `EXTRA_CONSTRAINT' is passed the
2280 operand as its first argument and the constraint letter as its
2283 `Q' is for signed 16-bit constants.
2284 `R' is for single-instruction memory references. Note that this
2285 constraint has often been used in linux and glibc code.
2286 `S' is for legitimate constant call addresses.
2287 `T' is for constant move_operands that cannot be safely loaded into $25.
2288 `U' is for constant move_operands that can be safely loaded into $25. */
2290 #define EXTRA_CONSTRAINT(OP,CODE) \
2291 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2292 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2293 && mips_fetch_insns (OP) == 1) \
2294 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2295 && call_insn_operand (OP, VOIDmode)) \
2296 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2297 && move_operand (OP, VOIDmode) \
2298 && DANGEROUS_FOR_LA25_P (OP)) \
2299 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2300 && move_operand (OP, VOIDmode) \
2301 && !DANGEROUS_FOR_LA25_P (OP)) \
2304 /* Given an rtx X being reloaded into a reg required to be
2305 in class CLASS, return the class of reg to actually use.
2306 In general this is just CLASS; but on some machines
2307 in some cases it is preferable to use a more restrictive class. */
2309 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2310 ((CLASS) != ALL_REGS \
2311 ? (! TARGET_MIPS16 \
2313 : ((CLASS) != GR_REGS \
2316 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2317 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2318 ? (TARGET_SOFT_FLOAT \
2319 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2321 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2322 || GET_MODE (X) == VOIDmode) \
2323 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2326 /* Certain machines have the property that some registers cannot be
2327 copied to some other registers without using memory. Define this
2328 macro on those machines to be a C expression that is nonzero if
2329 objects of mode MODE in registers of CLASS1 can only be copied to
2330 registers of class CLASS2 by storing a register of CLASS1 into
2331 memory and loading that memory location into a register of CLASS2.
2333 Do not define this macro if its value would always be zero. */
2335 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2336 ((!TARGET_DEBUG_H_MODE \
2337 && GET_MODE_CLASS (MODE) == MODE_INT \
2338 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2339 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2340 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2341 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2342 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2344 /* The HI and LO registers can only be reloaded via the general
2345 registers. Condition code registers can only be loaded to the
2346 general registers, and from the floating point registers. */
2348 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2349 mips_secondary_reload_class (CLASS, MODE, X, 1)
2350 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2351 mips_secondary_reload_class (CLASS, MODE, X, 0)
2353 /* Return the maximum number of consecutive registers
2354 needed to represent mode MODE in a register of class CLASS. */
2356 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2358 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2359 mips_cannot_change_mode_class (FROM, TO, CLASS)
2361 /* Stack layout; function entry, exit and calling. */
2363 /* Define this if pushing a word on the stack
2364 makes the stack pointer a smaller address. */
2365 #define STACK_GROWS_DOWNWARD
2367 /* Define this if the nominal address of the stack frame
2368 is at the high-address end of the local variables;
2369 that is, each additional local variable allocated
2370 goes at a more negative offset in the frame. */
2371 /* #define FRAME_GROWS_DOWNWARD */
2373 /* Offset within stack frame to start allocating local variables at.
2374 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2375 first local allocated. Otherwise, it is the offset to the BEGINNING
2376 of the first local allocated. */
2377 #define STARTING_FRAME_OFFSET \
2378 (current_function_outgoing_args_size \
2379 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2381 /* Offset from the stack pointer register to an item dynamically
2382 allocated on the stack, e.g., by `alloca'.
2384 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2385 length of the outgoing arguments. The default is correct for most
2386 machines. See `function.c' for details.
2388 The MIPS ABI states that functions which dynamically allocate the
2389 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2390 we are trying to create a second frame pointer to the function, so
2391 allocate some stack space to make it happy.
2393 However, the linker currently complains about linking any code that
2394 dynamically allocates stack space, and there seems to be a bug in
2395 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2398 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2399 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2400 ? 4*UNITS_PER_WORD \
2401 : current_function_outgoing_args_size)
2404 /* The return address for the current frame is in r31 if this is a leaf
2405 function. Otherwise, it is on the stack. It is at a variable offset
2406 from sp/fp/ap, so we define a fake hard register rap which is a
2407 poiner to the return address on the stack. This always gets eliminated
2408 during reload to be either the frame pointer or the stack pointer plus
2411 #define RETURN_ADDR_RTX mips_return_addr
2413 /* Since the mips16 ISA mode is encoded in the least-significant bit
2414 of the address, mask it off return addresses for purposes of
2415 finding exception handling regions. */
2417 #define MASK_RETURN_ADDR GEN_INT (-2)
2420 /* Similarly, don't use the least-significant bit to tell pointers to
2421 code from vtable index. */
2423 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2425 /* If defined, this macro specifies a table of register pairs used to
2426 eliminate unneeded registers that point into the stack frame. If
2427 it is not defined, the only elimination attempted by the compiler
2428 is to replace references to the frame pointer with references to
2431 The definition of this macro is a list of structure
2432 initializations, each of which specifies an original and
2433 replacement register.
2435 On some machines, the position of the argument pointer is not
2436 known until the compilation is completed. In such a case, a
2437 separate hard register must be used for the argument pointer.
2438 This register can be eliminated by replacing it with either the
2439 frame pointer or the argument pointer, depending on whether or not
2440 the frame pointer has been eliminated.
2442 In this case, you might specify:
2443 #define ELIMINABLE_REGS \
2444 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2445 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2446 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2448 Note that the elimination of the argument pointer with the stack
2449 pointer is specified first since that is the preferred elimination.
2451 The eliminations to $17 are only used on the mips16. See the
2452 definition of HARD_FRAME_POINTER_REGNUM. */
2454 #define ELIMINABLE_REGS \
2455 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2456 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2457 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2458 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2459 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2460 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2462 /* A C expression that returns nonzero if the compiler is allowed to
2463 try to replace register number FROM-REG with register number
2464 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2465 defined, and will usually be the constant 1, since most of the
2466 cases preventing register elimination are things that the compiler
2467 already knows about.
2469 When not in mips16 and mips64, we can always eliminate to the
2470 frame pointer. We can eliminate to the stack pointer unless
2471 a frame pointer is needed. In mips16 mode, we need a frame
2472 pointer for a large frame; otherwise, reload may be unable
2473 to compute the address of a local variable, since there is
2474 no way to add a large constant to the stack pointer
2475 without using a temporary register.
2477 In mips16, for some instructions (eg lwu), we can't eliminate the
2478 frame pointer for the stack pointer. These instructions are
2479 only generated in TARGET_64BIT mode.
2482 #define CAN_ELIMINATE(FROM, TO) \
2483 (((TO) == HARD_FRAME_POINTER_REGNUM \
2484 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2485 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2486 && (! TARGET_MIPS16 \
2487 || compute_frame_size (get_frame_size ()) < 32768))))
2489 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2490 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2492 /* If we generate an insn to push BYTES bytes,
2493 this says how many the stack pointer really advances by.
2494 On the VAX, sp@- in a byte insn really pushes a word. */
2496 /* #define PUSH_ROUNDING(BYTES) 0 */
2498 /* If defined, the maximum amount of space required for outgoing
2499 arguments will be computed and placed into the variable
2500 `current_function_outgoing_args_size'. No space will be pushed
2501 onto the stack for each call; instead, the function prologue
2502 should increase the stack frame size by this amount.
2504 It is not proper to define both `PUSH_ROUNDING' and
2505 `ACCUMULATE_OUTGOING_ARGS'. */
2506 #define ACCUMULATE_OUTGOING_ARGS 1
2508 /* Offset from the argument pointer register to the first argument's
2509 address. On some machines it may depend on the data type of the
2512 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2513 the first argument's address.
2515 On the MIPS, we must skip the first argument position if we are
2516 returning a structure or a union, to account for its address being
2517 passed in $4. However, at the current time, this produces a compiler
2518 that can't bootstrap, so comment it out for now. */
2521 #define FIRST_PARM_OFFSET(FNDECL) \
2523 && TREE_TYPE (FNDECL) != 0 \
2524 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2525 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2526 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2530 #define FIRST_PARM_OFFSET(FNDECL) 0
2533 /* When a parameter is passed in a register, stack space is still
2534 allocated for it. For the MIPS, stack space must be allocated, cf
2535 Asm Lang Prog Guide page 7-8.
2537 BEWARE that some space is also allocated for non existing arguments
2538 in register. In case an argument list is of form GF used registers
2539 are a0 (a2,a3), but we should push over a1... */
2541 #define REG_PARM_STACK_SPACE(FNDECL) \
2542 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2543 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2546 /* Define this if it is the responsibility of the caller to
2547 allocate the area reserved for arguments passed in registers.
2548 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2549 of this macro is to determine whether the space is included in
2550 `current_function_outgoing_args_size'. */
2551 #define OUTGOING_REG_PARM_STACK_SPACE
2553 #define STACK_BOUNDARY \
2554 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2557 /* Make sure 4 words are always allocated on the stack. */
2559 #ifndef STACK_ARGS_ADJUST
2560 #define STACK_ARGS_ADJUST(SIZE) \
2562 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2563 SIZE.constant = 4 * UNITS_PER_WORD; \
2568 /* A C expression that should indicate the number of bytes of its
2569 own arguments that a function pops on returning, or 0
2570 if the function pops no arguments and the caller must therefore
2571 pop them all after the function returns.
2573 FUNDECL is the declaration node of the function (as a tree).
2575 FUNTYPE is a C variable whose value is a tree node that
2576 describes the function in question. Normally it is a node of
2577 type `FUNCTION_TYPE' that describes the data type of the function.
2578 From this it is possible to obtain the data types of the value
2579 and arguments (if known).
2581 When a call to a library function is being considered, FUNTYPE
2582 will contain an identifier node for the library function. Thus,
2583 if you need to distinguish among various library functions, you
2584 can do so by their names. Note that "library function" in this
2585 context means a function used to perform arithmetic, whose name
2586 is known specially in the compiler and was not mentioned in the
2587 C code being compiled.
2589 STACK-SIZE is the number of bytes of arguments passed on the
2590 stack. If a variable number of bytes is passed, it is zero, and
2591 argument popping will always be the responsibility of the
2592 calling function. */
2594 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2597 /* Symbolic macros for the registers used to return integer and floating
2600 #define GP_RETURN (GP_REG_FIRST + 2)
2601 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2603 #define MAX_ARGS_IN_REGISTERS \
2604 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2606 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2608 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2610 /* Symbolic macros for the first/last argument registers. */
2612 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2613 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2614 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2615 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2617 /* Define how to find the value returned by a library function
2618 assuming the value has mode MODE. Because we define
2619 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2620 PROMOTE_MODE does. */
2622 #define LIBCALL_VALUE(MODE) \
2623 mips_function_value (NULL_TREE, NULL, (MODE))
2625 /* Define how to find the value returned by a function.
2626 VALTYPE is the data type of the value (as a tree).
2627 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2628 otherwise, FUNC is 0. */
2630 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2631 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2633 /* 1 if N is a possible register number for a function value.
2634 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2635 Currently, R2 and F0 are only implemented here (C has no complex type) */
2637 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2638 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2639 && (N) == FP_RETURN + 2))
2641 /* 1 if N is a possible register number for function argument passing.
2642 We have no FP argument registers when soft-float. When FP registers
2643 are 32 bits, we can't directly reference the odd numbered ones. */
2645 #define FUNCTION_ARG_REGNO_P(N) \
2646 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2647 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2648 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2651 /* A C expression which can inhibit the returning of certain function
2652 values in registers, based on the type of value. A nonzero value says
2653 to return the function value in memory, just as large structures are
2654 always returned. Here TYPE will be a C expression of type
2655 `tree', representing the data type of the value.
2657 Note that values of mode `BLKmode' must be explicitly
2658 handled by this macro. Also, the option `-fpcc-struct-return'
2659 takes effect regardless of this macro. On most systems, it is
2660 possible to leave the macro undefined; this causes a default
2661 definition to be used, whose value is the constant 1 for BLKmode
2662 values, and 0 otherwise.
2664 GCC normally converts 1 byte structures into chars, 2 byte
2665 structs into shorts, and 4 byte structs into ints, and returns
2666 them this way. Defining the following macro overrides this,
2667 to give us MIPS cc compatibility. */
2669 #define RETURN_IN_MEMORY(TYPE) \
2670 mips_return_in_memory (TYPE)
2672 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2673 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2676 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2678 /* Define a data type for recording info about an argument list
2679 during the scan of that argument list. This data type should
2680 hold all necessary information about the function itself
2681 and about the args processed so far, enough to enable macros
2682 such as FUNCTION_ARG to determine where the next arg should go.
2684 This structure has to cope with two different argument allocation
2685 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2686 first N words go in registers and the rest go on the stack. If I < N,
2687 the Ith word might go in Ith integer argument register or the
2688 Ith floating-point one. In some cases, it has to go in both (see
2689 function_arg). For these ABIs, we only need to remember the number
2690 of words passed so far.
2692 The EABI instead allocates the integer and floating-point arguments
2693 separately. The first N words of FP arguments go in FP registers,
2694 the rest go on the stack. Likewise, the first N words of the other
2695 arguments go in integer registers, and the rest go on the stack. We
2696 need to maintain three counts: the number of integer registers used,
2697 the number of floating-point registers used, and the number of words
2698 passed on the stack.
2700 We could keep separate information for the two ABIs (a word count for
2701 the standard ABIs, and three separate counts for the EABI). But it
2702 seems simpler to view the standard ABIs as forms of EABI that do not
2703 allocate floating-point registers.
2705 So for the standard ABIs, the first N words are allocated to integer
2706 registers, and function_arg decides on an argument-by-argument basis
2707 whether that argument should really go in an integer register, or in
2708 a floating-point one. */
2710 typedef struct mips_args {
2711 /* Always true for varargs functions. Otherwise true if at least
2712 one argument has been passed in an integer register. */
2715 /* The number of arguments seen so far. */
2716 unsigned int arg_number;
2718 /* For EABI, the number of integer registers used so far. For other
2719 ABIs, the number of words passed in registers (whether integer
2720 or floating-point). */
2721 unsigned int num_gprs;
2723 /* For EABI, the number of floating-point registers used so far. */
2724 unsigned int num_fprs;
2726 /* The number of words passed on the stack. */
2727 unsigned int stack_words;
2729 /* On the mips16, we need to keep track of which floating point
2730 arguments were passed in general registers, but would have been
2731 passed in the FP regs if this were a 32 bit function, so that we
2732 can move them to the FP regs if we wind up calling a 32 bit
2733 function. We record this information in fp_code, encoded in base
2734 four. A zero digit means no floating point argument, a one digit
2735 means an SFmode argument, and a two digit means a DFmode argument,
2736 and a three digit is not used. The low order digit is the first
2737 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2738 an SFmode argument. ??? A more sophisticated approach will be
2739 needed if MIPS_ABI != ABI_32. */
2742 /* True if the function has a prototype. */
2745 /* When a structure does not take up a full register, the argument
2746 should sometimes be shifted left so that it occupies the high part
2747 of the register. These two fields describe an array of ashl
2748 patterns for doing this. See function_arg_advance, which creates
2749 the shift patterns, and function_arg, which returns them when given
2750 a VOIDmode argument. */
2751 unsigned int num_adjusts;
2752 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2755 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2756 for a call to a function whose data type is FNTYPE.
2757 For a library call, FNTYPE is 0.
2761 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2762 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2764 /* Update the data in CUM to advance over an argument
2765 of mode MODE and data type TYPE.
2766 (TYPE is null for libcalls where that information may not be available.) */
2768 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2769 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2771 /* Determine where to put an argument to a function.
2772 Value is zero to push the argument on the stack,
2773 or a hard register in which to store the argument.
2775 MODE is the argument's machine mode.
2776 TYPE is the data type of the argument (as a tree).
2777 This is null for libcalls where that information may
2779 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2780 the preceding args and about the function being called.
2781 NAMED is nonzero if this argument is a named parameter
2782 (otherwise it is an extra parameter matching an ellipsis). */
2784 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2785 function_arg( &CUM, MODE, TYPE, NAMED)
2787 /* For an arg passed partly in registers and partly in memory,
2788 this is the number of registers used.
2789 For args passed entirely in registers or entirely in memory, zero. */
2791 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2792 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2794 /* If defined, a C expression that gives the alignment boundary, in
2795 bits, of an argument with the specified mode and type. If it is
2796 not defined, `PARM_BOUNDARY' is used for all arguments. */
2798 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2800 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2802 : TYPE_ALIGN(TYPE)) \
2803 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2805 : GET_MODE_ALIGNMENT(MODE)))
2807 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2808 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2810 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2811 (! BYTES_BIG_ENDIAN \
2813 : (((MODE) == BLKmode \
2814 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2815 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2816 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2817 && (mips_abi == ABI_32 \
2818 || mips_abi == ABI_O64 \
2819 || mips_abi == ABI_EABI \
2820 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2821 ? downward : upward))
2823 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2824 (mips_abi == ABI_EABI && (NAMED) \
2825 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2827 /* Modified version of the macro in expr.h. */
2828 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2830 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2831 || TREE_ADDRESSABLE (TYPE) \
2832 || ((MODE) == BLKmode \
2833 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2834 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2835 && 0 == (int_size_in_bytes (TYPE) \
2836 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2837 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2838 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2840 /* True if using EABI and varargs can be passed in floating-point
2841 registers. Under these conditions, we need a more complex form
2842 of va_list, which tracks GPR, FPR and stack arguments separately. */
2843 #define EABI_FLOAT_VARARGS_P \
2844 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2847 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2849 #define MUST_SAVE_REGISTER(regno) \
2850 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2851 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2852 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2854 /* Say that the epilogue uses the return address register. Note that
2855 in the case of sibcalls, the values "used by the epilogue" are
2856 considered live at the start of the called function. */
2857 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2859 /* Treat LOC as a byte offset from the stack pointer and round it up
2860 to the next fully-aligned offset. */
2861 #define MIPS_STACK_ALIGN(LOC) \
2862 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2863 ? ((LOC) + 7) & ~7 \
2864 : ((LOC) + 15) & ~15)
2867 /* Define the `__builtin_va_list' type for the ABI. */
2868 #define BUILD_VA_LIST_TYPE(VALIST) \
2869 (VALIST) = mips_build_va_list ()
2871 /* Implement `va_start' for varargs and stdarg. */
2872 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2873 mips_va_start (valist, nextarg)
2875 /* Implement `va_arg'. */
2876 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2877 mips_va_arg (valist, type)
2879 /* Output assembler code to FILE to increment profiler label # LABELNO
2880 for profiling a function entry. */
2882 #define FUNCTION_PROFILER(FILE, LABELNO) \
2884 if (TARGET_MIPS16) \
2885 sorry ("mips16 function profiling"); \
2886 fprintf (FILE, "\t.set\tnoat\n"); \
2887 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2888 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2889 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2892 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2893 TARGET_64BIT ? "dsubu" : "subu", \
2894 reg_names[STACK_POINTER_REGNUM], \
2895 reg_names[STACK_POINTER_REGNUM], \
2896 Pmode == DImode ? 16 : 8); \
2898 fprintf (FILE, "\tjal\t_mcount\n"); \
2899 fprintf (FILE, "\t.set\tat\n"); \
2902 /* Define this macro if the code for function profiling should come
2903 before the function prologue. Normally, the profiling code comes
2906 /* #define PROFILE_BEFORE_PROLOGUE */
2908 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2909 the stack pointer does not matter. The value is tested only in
2910 functions that have frame pointers.
2911 No definition is equivalent to always zero. */
2913 #define EXIT_IGNORE_STACK 1
2916 /* A C statement to output, on the stream FILE, assembler code for a
2917 block of data that contains the constant parts of a trampoline.
2918 This code should not include a label--the label is taken care of
2921 #define TRAMPOLINE_TEMPLATE(STREAM) \
2923 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2924 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2925 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2926 if (ptr_mode == DImode) \
2928 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2929 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2933 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2934 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2936 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2937 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2938 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2939 if (ptr_mode == DImode) \
2941 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2942 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2946 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2947 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2951 /* A C expression for the size in bytes of the trampoline, as an
2954 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2956 /* Alignment required for trampolines, in bits. */
2958 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2960 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2961 program and data caches. */
2963 #ifndef CACHE_FLUSH_FUNC
2964 #define CACHE_FLUSH_FUNC "_flush_cache"
2967 /* A C statement to initialize the variable parts of a trampoline.
2968 ADDR is an RTX for the address of the trampoline; FNADDR is an
2969 RTX for the address of the nested function; STATIC_CHAIN is an
2970 RTX for the static chain value that should be passed to the
2971 function when it is called. */
2973 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2975 rtx func_addr, chain_addr; \
2977 func_addr = plus_constant (ADDR, 32); \
2978 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2979 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
2980 gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
2981 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
2982 gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
2984 /* Flush both caches. We need to flush the data cache in case \
2985 the system has a write-back cache. */ \
2986 /* ??? Should check the return value for errors. */ \
2987 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2988 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2989 0, VOIDmode, 3, ADDR, Pmode, \
2990 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2991 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2994 /* Addressing modes, and classification of registers for them. */
2996 /* These assume that REGNO is a hard or pseudo reg number.
2997 They give nonzero only if REGNO is a hard reg of the suitable class
2998 or a pseudo reg currently allocated to a suitable hard reg.
2999 These definitions are NOT overridden anywhere. */
3001 #define BASE_REG_P(regno, mode) \
3003 ? (M16_REG_P (regno) \
3004 || (regno) == FRAME_POINTER_REGNUM \
3005 || (regno) == ARG_POINTER_REGNUM \
3006 || ((regno) == STACK_POINTER_REGNUM \
3007 && (GET_MODE_SIZE (mode) == 4 \
3008 || GET_MODE_SIZE (mode) == 8))) \
3011 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
3012 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
3015 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
3016 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3018 #define REGNO_OK_FOR_INDEX_P(regno) 0
3019 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3020 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3022 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3023 and check its validity for a certain class.
3024 We have two alternate definitions for each of them.
3025 The usual definition accepts all pseudo regs; the other rejects them all.
3026 The symbol REG_OK_STRICT causes the latter definition to be used.
3028 Most source files want to accept pseudo regs in the hope that
3029 they will get allocated to the class that the insn wants them to be in.
3030 Some source files that are used after register allocation
3031 need to be strict. */
3033 #ifndef REG_OK_STRICT
3034 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3035 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3037 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3038 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3041 #define REG_OK_FOR_INDEX_P(X) 0
3044 /* Maximum number of registers that can appear in a valid memory address. */
3046 #define MAX_REGS_PER_ADDRESS 1
3048 /* A C compound statement with a conditional `goto LABEL;' executed
3049 if X (an RTX) is a legitimate memory address on the target
3050 machine for a memory operand of mode MODE. */
3053 #define GO_PRINTF(x) fprintf(stderr, (x))
3054 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3055 #define GO_DEBUG_RTX(x) debug_rtx(x)
3058 #define GO_PRINTF(x)
3059 #define GO_PRINTF2(x,y)
3060 #define GO_DEBUG_RTX(x)
3063 #ifdef REG_OK_STRICT
3064 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3066 if (mips_legitimate_address_p (MODE, X, 1)) \
3070 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3072 if (mips_legitimate_address_p (MODE, X, 0)) \
3077 /* Check for constness inline but use mips_legitimate_address_p
3078 to check whether a constant really is an address. */
3080 #define CONSTANT_ADDRESS_P(X) \
3081 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
3084 /* Nonzero if the constant value X is a legitimate general operand.
3085 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3087 At present, GAS doesn't understand li.[sd], so don't allow it
3088 to be generated at present. Also, the MIPS assembler does not
3089 grok li.d Infinity. */
3091 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3092 Note that the Irix 6 assembler problem may already be fixed.
3093 Note also that the GET_CODE (X) == CONST test catches the mips16
3094 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3095 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3096 ABI_64 to work together, we'll need to fix this. */
3097 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
3099 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3101 if (mips_legitimize_address (&(X), MODE)) \
3106 /* A C statement or compound statement with a conditional `goto
3107 LABEL;' executed if memory address X (an RTX) can have different
3108 meanings depending on the machine mode of the memory reference it
3111 Autoincrement and autodecrement addresses typically have
3112 mode-dependent effects because the amount of the increment or
3113 decrement is the size of the operand being addressed. Some
3114 machines have other mode-dependent addresses. Many RISC machines
3115 have no mode-dependent addresses.
3117 You may assume that ADDR is a valid address for the machine. */
3119 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3121 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3122 'the start of the function that this code is output in'. */
3124 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3125 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3126 asm_fprintf ((FILE), "%U%s", \
3127 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3129 asm_fprintf ((FILE), "%U%s", (NAME))
3131 /* The mips16 wants the constant pool to be after the function,
3132 because the PC relative load instructions use unsigned offsets. */
3134 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3136 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3137 mips_string_length = 0;
3139 /* Specify the machine mode that this machine uses
3140 for the index in the tablejump instruction.
3141 ??? Using HImode in mips16 mode can cause overflow. However, the
3142 overflow is no more likely than the overflow in a branch
3143 instruction. Large functions can currently break in both ways. */
3144 #define CASE_VECTOR_MODE \
3145 (TARGET_MIPS16 ? HImode : ptr_mode)
3147 /* Define as C expression which evaluates to nonzero if the tablejump
3148 instruction expects the table to contain offsets from the address of the
3150 Do not define this if the table should contain absolute addresses. */
3151 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3153 /* Define this as 1 if `char' should by default be signed; else as 0. */
3154 #ifndef DEFAULT_SIGNED_CHAR
3155 #define DEFAULT_SIGNED_CHAR 1
3158 /* Max number of bytes we can move from memory to memory
3159 in one reasonably fast instruction. */
3160 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3161 #define MAX_MOVE_MAX 8
3163 /* Define this macro as a C expression which is nonzero if
3164 accessing less than a word of memory (i.e. a `char' or a
3165 `short') is no faster than accessing a word of memory, i.e., if
3166 such access require more than one instruction or if there is no
3167 difference in cost between byte and (aligned) word loads.
3169 On RISC machines, it tends to generate better code to define
3170 this as 1, since it avoids making a QI or HI mode register. */
3171 #define SLOW_BYTE_ACCESS 1
3173 /* We assume that the store-condition-codes instructions store 0 for false
3174 and some other value for true. This is the value stored for true. */
3176 #define STORE_FLAG_VALUE 1
3178 /* Define this to be nonzero if shift instructions ignore all but the low-order
3180 #define SHIFT_COUNT_TRUNCATED 1
3182 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3183 is done just by pretending it is already truncated. */
3184 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3185 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3188 /* Specify the machine mode that pointers have.
3189 After generation of rtl, the compiler makes no further distinction
3190 between pointers and any other objects of this machine mode. */
3193 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
3196 /* Give call MEMs SImode since it is the "most permissive" mode
3197 for both 32-bit and 64-bit targets. */
3199 #define FUNCTION_MODE SImode
3202 /* The cost of loading values from the constant pool. It should be
3203 larger than the cost of any constant we want to synthesise in-line. */
3205 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
3207 /* A C expression for the cost of moving data from a register in
3208 class FROM to one in class TO. The classes are expressed using
3209 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3210 the default; other values are interpreted relative to that.
3212 It is not required that the cost always equal 2 when FROM is the
3213 same as TO; on some machines it is expensive to move between
3214 registers if they are not general registers.
3216 If reload sees an insn consisting of a single `set' between two
3217 hard registers, and if `REGISTER_MOVE_COST' applied to their
3218 classes returns a value of 2, reload does not check to ensure
3219 that the constraints of the insn are met. Setting a cost of
3220 other than 2 will allow reload to verify that the constraints are
3221 met. You should do this if the `movM' pattern's constraints do
3222 not allow such copying. */
3224 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3225 mips_register_move_cost (MODE, FROM, TO)
3227 /* ??? Fix this to be right for the R8000. */
3228 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3229 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3230 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3232 /* Define if copies to/from condition code registers should be avoided.
3234 This is needed for the MIPS because reload_outcc is not complete;
3235 it needs to handle cases where the source is a general or another
3236 condition code register. */
3237 #define AVOID_CCMODE_COPIES
3239 /* A C expression for the cost of a branch instruction. A value of
3240 1 is the default; other values are interpreted relative to that. */
3242 /* ??? Fix this to be right for the R8000. */
3243 #define BRANCH_COST \
3245 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3248 /* If defined, modifies the length assigned to instruction INSN as a
3249 function of the context in which it is used. LENGTH is an lvalue
3250 that contains the initially computed length of the insn and should
3251 be updated with the correct length of the insn. */
3252 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3253 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3256 /* Optionally define this if you have added predicates to
3257 `MACHINE.c'. This macro is called within an initializer of an
3258 array of structures. The first field in the structure is the
3259 name of a predicate and the second field is an array of rtl
3260 codes. For each predicate, list all rtl codes that can be in
3261 expressions matched by the predicate. The list should have a
3262 trailing comma. Here is an example of two entries in the list
3263 for a typical RISC machine:
3265 #define PREDICATE_CODES \
3266 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3267 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3269 Defining this macro does not affect the generated code (however,
3270 incorrect definitions that omit an rtl code that may be matched
3271 by the predicate can cause the compiler to malfunction).
3272 Instead, it allows the table built by `genrecog' to be more
3273 compact and efficient, thus speeding up the compiler. The most
3274 important predicates to include in the list specified by this
3275 macro are thoses used in the most insn patterns. */
3277 #define PREDICATE_CODES \
3278 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3279 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
3280 {"const_arith_operand", { CONST, CONST_INT }}, \
3281 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
3282 {"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3283 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3284 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3285 {"small_int", { CONST_INT }}, \
3286 {"large_int", { CONST_INT }}, \
3287 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3288 {"const_float_1_operand", { CONST_DOUBLE }}, \
3289 {"simple_memory_operand", { MEM, SUBREG }}, \
3290 {"equality_op", { EQ, NE }}, \
3291 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3293 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3294 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3295 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
3296 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3297 SYMBOL_REF, LABEL_REF, SUBREG, \
3299 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3300 CONST_DOUBLE, CONST }}, \
3301 {"fcc_register_operand", { REG, SUBREG }}, \
3302 {"hilo_operand", { REG }}, \
3303 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
3305 /* A list of predicates that do special things with modes, and so
3306 should not elicit warnings for VOIDmode match_operand. */
3308 #define SPECIAL_MODE_PREDICATES \
3309 "pc_or_label_operand",
3311 /* Control the assembler format that we output. */
3313 /* Output at beginning of assembler file.
3314 If we are optimizing to use the global pointer, create a temporary
3315 file to hold all of the text stuff, and write it out to the end.
3316 This is needed because the MIPS assembler is evidently one pass,
3317 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3318 declaration when the code is processed, it generates a two
3319 instruction sequence. */
3321 #undef ASM_FILE_START
3322 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3324 /* Output to assembler file text saying following lines
3325 may contain character constants, extra white space, comments, etc. */
3328 #define ASM_APP_ON " #APP\n"
3331 /* Output to assembler file text saying following lines
3332 no longer contain unusual constructs. */
3335 #define ASM_APP_OFF " #NO_APP\n"
3338 /* How to refer to registers in assembler output.
3339 This sequence is indexed by compiler's hard-register-number (see above).
3341 In order to support the two different conventions for register names,
3342 we use the name of a table set up in mips.c, which is overwritten
3343 if -mrnames is used. */
3345 #define REGISTER_NAMES \
3347 &mips_reg_names[ 0][0], \
3348 &mips_reg_names[ 1][0], \
3349 &mips_reg_names[ 2][0], \
3350 &mips_reg_names[ 3][0], \
3351 &mips_reg_names[ 4][0], \
3352 &mips_reg_names[ 5][0], \
3353 &mips_reg_names[ 6][0], \
3354 &mips_reg_names[ 7][0], \
3355 &mips_reg_names[ 8][0], \
3356 &mips_reg_names[ 9][0], \
3357 &mips_reg_names[10][0], \
3358 &mips_reg_names[11][0], \
3359 &mips_reg_names[12][0], \
3360 &mips_reg_names[13][0], \
3361 &mips_reg_names[14][0], \
3362 &mips_reg_names[15][0], \
3363 &mips_reg_names[16][0], \
3364 &mips_reg_names[17][0], \
3365 &mips_reg_names[18][0], \
3366 &mips_reg_names[19][0], \
3367 &mips_reg_names[20][0], \
3368 &mips_reg_names[21][0], \
3369 &mips_reg_names[22][0], \
3370 &mips_reg_names[23][0], \
3371 &mips_reg_names[24][0], \
3372 &mips_reg_names[25][0], \
3373 &mips_reg_names[26][0], \
3374 &mips_reg_names[27][0], \
3375 &mips_reg_names[28][0], \
3376 &mips_reg_names[29][0], \
3377 &mips_reg_names[30][0], \
3378 &mips_reg_names[31][0], \
3379 &mips_reg_names[32][0], \
3380 &mips_reg_names[33][0], \
3381 &mips_reg_names[34][0], \
3382 &mips_reg_names[35][0], \
3383 &mips_reg_names[36][0], \
3384 &mips_reg_names[37][0], \
3385 &mips_reg_names[38][0], \
3386 &mips_reg_names[39][0], \
3387 &mips_reg_names[40][0], \
3388 &mips_reg_names[41][0], \
3389 &mips_reg_names[42][0], \
3390 &mips_reg_names[43][0], \
3391 &mips_reg_names[44][0], \
3392 &mips_reg_names[45][0], \
3393 &mips_reg_names[46][0], \
3394 &mips_reg_names[47][0], \
3395 &mips_reg_names[48][0], \
3396 &mips_reg_names[49][0], \
3397 &mips_reg_names[50][0], \
3398 &mips_reg_names[51][0], \
3399 &mips_reg_names[52][0], \
3400 &mips_reg_names[53][0], \
3401 &mips_reg_names[54][0], \
3402 &mips_reg_names[55][0], \
3403 &mips_reg_names[56][0], \
3404 &mips_reg_names[57][0], \
3405 &mips_reg_names[58][0], \
3406 &mips_reg_names[59][0], \
3407 &mips_reg_names[60][0], \
3408 &mips_reg_names[61][0], \
3409 &mips_reg_names[62][0], \
3410 &mips_reg_names[63][0], \
3411 &mips_reg_names[64][0], \
3412 &mips_reg_names[65][0], \
3413 &mips_reg_names[66][0], \
3414 &mips_reg_names[67][0], \
3415 &mips_reg_names[68][0], \
3416 &mips_reg_names[69][0], \
3417 &mips_reg_names[70][0], \
3418 &mips_reg_names[71][0], \
3419 &mips_reg_names[72][0], \
3420 &mips_reg_names[73][0], \
3421 &mips_reg_names[74][0], \
3422 &mips_reg_names[75][0], \
3423 &mips_reg_names[76][0], \
3424 &mips_reg_names[77][0], \
3425 &mips_reg_names[78][0], \
3426 &mips_reg_names[79][0], \
3427 &mips_reg_names[80][0], \
3428 &mips_reg_names[81][0], \
3429 &mips_reg_names[82][0], \
3430 &mips_reg_names[83][0], \
3431 &mips_reg_names[84][0], \
3432 &mips_reg_names[85][0], \
3433 &mips_reg_names[86][0], \
3434 &mips_reg_names[87][0], \
3435 &mips_reg_names[88][0], \
3436 &mips_reg_names[89][0], \
3437 &mips_reg_names[90][0], \
3438 &mips_reg_names[91][0], \
3439 &mips_reg_names[92][0], \
3440 &mips_reg_names[93][0], \
3441 &mips_reg_names[94][0], \
3442 &mips_reg_names[95][0], \
3443 &mips_reg_names[96][0], \
3444 &mips_reg_names[97][0], \
3445 &mips_reg_names[98][0], \
3446 &mips_reg_names[99][0], \
3447 &mips_reg_names[100][0], \
3448 &mips_reg_names[101][0], \
3449 &mips_reg_names[102][0], \
3450 &mips_reg_names[103][0], \
3451 &mips_reg_names[104][0], \
3452 &mips_reg_names[105][0], \
3453 &mips_reg_names[106][0], \
3454 &mips_reg_names[107][0], \
3455 &mips_reg_names[108][0], \
3456 &mips_reg_names[109][0], \
3457 &mips_reg_names[110][0], \
3458 &mips_reg_names[111][0], \
3459 &mips_reg_names[112][0], \
3460 &mips_reg_names[113][0], \
3461 &mips_reg_names[114][0], \
3462 &mips_reg_names[115][0], \
3463 &mips_reg_names[116][0], \
3464 &mips_reg_names[117][0], \
3465 &mips_reg_names[118][0], \
3466 &mips_reg_names[119][0], \
3467 &mips_reg_names[120][0], \
3468 &mips_reg_names[121][0], \
3469 &mips_reg_names[122][0], \
3470 &mips_reg_names[123][0], \
3471 &mips_reg_names[124][0], \
3472 &mips_reg_names[125][0], \
3473 &mips_reg_names[126][0], \
3474 &mips_reg_names[127][0], \
3475 &mips_reg_names[128][0], \
3476 &mips_reg_names[129][0], \
3477 &mips_reg_names[130][0], \
3478 &mips_reg_names[131][0], \
3479 &mips_reg_names[132][0], \
3480 &mips_reg_names[133][0], \
3481 &mips_reg_names[134][0], \
3482 &mips_reg_names[135][0], \
3483 &mips_reg_names[136][0], \
3484 &mips_reg_names[137][0], \
3485 &mips_reg_names[138][0], \
3486 &mips_reg_names[139][0], \
3487 &mips_reg_names[140][0], \
3488 &mips_reg_names[141][0], \
3489 &mips_reg_names[142][0], \
3490 &mips_reg_names[143][0], \
3491 &mips_reg_names[144][0], \
3492 &mips_reg_names[145][0], \
3493 &mips_reg_names[146][0], \
3494 &mips_reg_names[147][0], \
3495 &mips_reg_names[148][0], \
3496 &mips_reg_names[149][0], \
3497 &mips_reg_names[150][0], \
3498 &mips_reg_names[151][0], \
3499 &mips_reg_names[152][0], \
3500 &mips_reg_names[153][0], \
3501 &mips_reg_names[154][0], \
3502 &mips_reg_names[155][0], \
3503 &mips_reg_names[156][0], \
3504 &mips_reg_names[157][0], \
3505 &mips_reg_names[158][0], \
3506 &mips_reg_names[159][0], \
3507 &mips_reg_names[160][0], \
3508 &mips_reg_names[161][0], \
3509 &mips_reg_names[162][0], \
3510 &mips_reg_names[163][0], \
3511 &mips_reg_names[164][0], \
3512 &mips_reg_names[165][0], \
3513 &mips_reg_names[166][0], \
3514 &mips_reg_names[167][0], \
3515 &mips_reg_names[168][0], \
3516 &mips_reg_names[169][0], \
3517 &mips_reg_names[170][0], \
3518 &mips_reg_names[171][0], \
3519 &mips_reg_names[172][0], \
3520 &mips_reg_names[173][0], \
3521 &mips_reg_names[174][0], \
3522 &mips_reg_names[175][0] \
3525 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3526 So define this for it. */
3527 #define DEBUG_REGISTER_NAMES \
3529 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3530 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3531 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3532 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3533 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3534 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3535 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3536 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3537 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3538 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
3539 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3540 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3541 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3542 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3543 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3544 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3545 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3546 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3547 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3548 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3549 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3550 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
3553 /* If defined, a C initializer for an array of structures
3554 containing a name and a register number. This macro defines
3555 additional names for hard registers, thus allowing the `asm'
3556 option in declarations to refer to registers using alternate
3559 We define both names for the integer registers here. */
3561 #define ADDITIONAL_REGISTER_NAMES \
3563 { "$0", 0 + GP_REG_FIRST }, \
3564 { "$1", 1 + GP_REG_FIRST }, \
3565 { "$2", 2 + GP_REG_FIRST }, \
3566 { "$3", 3 + GP_REG_FIRST }, \
3567 { "$4", 4 + GP_REG_FIRST }, \
3568 { "$5", 5 + GP_REG_FIRST }, \
3569 { "$6", 6 + GP_REG_FIRST }, \
3570 { "$7", 7 + GP_REG_FIRST }, \
3571 { "$8", 8 + GP_REG_FIRST }, \
3572 { "$9", 9 + GP_REG_FIRST }, \
3573 { "$10", 10 + GP_REG_FIRST }, \
3574 { "$11", 11 + GP_REG_FIRST }, \
3575 { "$12", 12 + GP_REG_FIRST }, \
3576 { "$13", 13 + GP_REG_FIRST }, \
3577 { "$14", 14 + GP_REG_FIRST }, \
3578 { "$15", 15 + GP_REG_FIRST }, \
3579 { "$16", 16 + GP_REG_FIRST }, \
3580 { "$17", 17 + GP_REG_FIRST }, \
3581 { "$18", 18 + GP_REG_FIRST }, \
3582 { "$19", 19 + GP_REG_FIRST }, \
3583 { "$20", 20 + GP_REG_FIRST }, \
3584 { "$21", 21 + GP_REG_FIRST }, \
3585 { "$22", 22 + GP_REG_FIRST }, \
3586 { "$23", 23 + GP_REG_FIRST }, \
3587 { "$24", 24 + GP_REG_FIRST }, \
3588 { "$25", 25 + GP_REG_FIRST }, \
3589 { "$26", 26 + GP_REG_FIRST }, \
3590 { "$27", 27 + GP_REG_FIRST }, \
3591 { "$28", 28 + GP_REG_FIRST }, \
3592 { "$29", 29 + GP_REG_FIRST }, \
3593 { "$30", 30 + GP_REG_FIRST }, \
3594 { "$31", 31 + GP_REG_FIRST }, \
3595 { "$sp", 29 + GP_REG_FIRST }, \
3596 { "$fp", 30 + GP_REG_FIRST }, \
3597 { "at", 1 + GP_REG_FIRST }, \
3598 { "v0", 2 + GP_REG_FIRST }, \
3599 { "v1", 3 + GP_REG_FIRST }, \
3600 { "a0", 4 + GP_REG_FIRST }, \
3601 { "a1", 5 + GP_REG_FIRST }, \
3602 { "a2", 6 + GP_REG_FIRST }, \
3603 { "a3", 7 + GP_REG_FIRST }, \
3604 { "t0", 8 + GP_REG_FIRST }, \
3605 { "t1", 9 + GP_REG_FIRST }, \
3606 { "t2", 10 + GP_REG_FIRST }, \
3607 { "t3", 11 + GP_REG_FIRST }, \
3608 { "t4", 12 + GP_REG_FIRST }, \
3609 { "t5", 13 + GP_REG_FIRST }, \
3610 { "t6", 14 + GP_REG_FIRST }, \
3611 { "t7", 15 + GP_REG_FIRST }, \
3612 { "s0", 16 + GP_REG_FIRST }, \
3613 { "s1", 17 + GP_REG_FIRST }, \
3614 { "s2", 18 + GP_REG_FIRST }, \
3615 { "s3", 19 + GP_REG_FIRST }, \
3616 { "s4", 20 + GP_REG_FIRST }, \
3617 { "s5", 21 + GP_REG_FIRST }, \
3618 { "s6", 22 + GP_REG_FIRST }, \
3619 { "s7", 23 + GP_REG_FIRST }, \
3620 { "t8", 24 + GP_REG_FIRST }, \
3621 { "t9", 25 + GP_REG_FIRST }, \
3622 { "k0", 26 + GP_REG_FIRST }, \
3623 { "k1", 27 + GP_REG_FIRST }, \
3624 { "gp", 28 + GP_REG_FIRST }, \
3625 { "sp", 29 + GP_REG_FIRST }, \
3626 { "fp", 30 + GP_REG_FIRST }, \
3627 { "ra", 31 + GP_REG_FIRST }, \
3628 { "$sp", 29 + GP_REG_FIRST }, \
3629 { "$fp", 30 + GP_REG_FIRST } \
3630 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3633 /* This is meant to be redefined in the host dependent files. It is a
3634 set of alternative names and regnums for mips coprocessors. */
3636 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3638 /* A C compound statement to output to stdio stream STREAM the
3639 assembler syntax for an instruction operand X. X is an RTL
3642 CODE is a value that can be used to specify one of several ways
3643 of printing the operand. It is used when identical operands
3644 must be printed differently depending on the context. CODE
3645 comes from the `%' specification that was used to request
3646 printing of the operand. If the specification was just `%DIGIT'
3647 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3648 is the ASCII code for LTR.
3650 If X is a register, this macro should print the register's name.
3651 The names can be found in an array `reg_names' whose type is
3652 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3654 When the machine description has a specification `%PUNCT' (a `%'
3655 followed by a punctuation character), this macro is called with
3656 a null pointer for X and the punctuation character for CODE.
3658 See mips.c for the MIPS specific codes. */
3660 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3662 /* A C expression which evaluates to true if CODE is a valid
3663 punctuation character for use in the `PRINT_OPERAND' macro. If
3664 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3665 punctuation characters (except for the standard one, `%') are
3666 used in this way. */
3668 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3670 /* A C compound statement to output to stdio stream STREAM the
3671 assembler syntax for an instruction operand that is a memory
3672 reference whose address is ADDR. ADDR is an RTL expression. */
3674 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3677 /* A C statement, to be executed after all slot-filler instructions
3678 have been output. If necessary, call `dbr_sequence_length' to
3679 determine the number of slots filled in a sequence (zero if not
3680 currently outputting a sequence), to decide how many no-ops to
3681 output, or whatever.
3683 Don't define this macro if it has nothing to do, but it is
3684 helpful in reading assembly output if the extent of the delay
3685 sequence is made explicit (e.g. with white space).
3687 Note that output routines for instructions with delay slots must
3688 be prepared to deal with not being output as part of a sequence
3689 (i.e. when the scheduling pass is not run, or when no slot
3690 fillers could be found.) The variable `final_sequence' is null
3691 when not processing a sequence, otherwise it contains the
3692 `sequence' rtx being output. */
3694 #define DBR_OUTPUT_SEQEND(STREAM) \
3697 if (set_nomacro > 0 && --set_nomacro == 0) \
3698 fputs ("\t.set\tmacro\n", STREAM); \
3700 if (set_noreorder > 0 && --set_noreorder == 0) \
3701 fputs ("\t.set\treorder\n", STREAM); \
3703 fputs ("\n", STREAM); \
3708 /* How to tell the debugger about changes of source files. Note, the
3709 mips ECOFF format cannot deal with changes of files inside of
3710 functions, which means the output of parser generators like bison
3711 is generally not debuggable without using the -l switch. Lose,
3712 lose, lose. Silicon graphics seems to want all .file's hardwired
3715 #ifndef SET_FILE_NUMBER
3716 #define SET_FILE_NUMBER() ++num_source_filenames
3719 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3720 mips_output_filename (STREAM, NAME)
3722 /* This is defined so that it can be overridden in iris6.h. */
3723 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3726 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3727 output_quoted_string (STREAM, NAME); \
3728 fputs ("\n", STREAM); \
3732 /* This is how to output a note the debugger telling it the line number
3733 to which the following sequence of instructions corresponds.
3734 Silicon graphics puts a label after each .loc. */
3736 #ifndef LABEL_AFTER_LOC
3737 #define LABEL_AFTER_LOC(STREAM)
3740 #ifndef ASM_OUTPUT_SOURCE_LINE
3741 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3742 mips_output_lineno (STREAM, LINE)
3745 /* The MIPS implementation uses some labels for its own purpose. The
3746 following lists what labels are created, and are all formed by the
3747 pattern $L[a-z].*. The machine independent portion of GCC creates
3748 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3750 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3751 $Lb[0-9]+ Begin blocks for MIPS debug support
3752 $Lc[0-9]+ Label for use in s<xx> operation.
3753 $Le[0-9]+ End blocks for MIPS debug support */
3755 /* A C statement (sans semicolon) to output to the stdio stream
3756 STREAM any text necessary for declaring the name NAME of an
3757 initialized variable which is being defined. This macro must
3758 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3759 The argument DECL is the `VAR_DECL' tree node representing the
3762 If this macro is not defined, then the variable name is defined
3763 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3765 #undef ASM_DECLARE_OBJECT_NAME
3766 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3769 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3773 /* Globalizing directive for a label. */
3774 #define GLOBAL_ASM_OP "\t.globl\t"
3776 /* This says how to define a global common symbol. */
3778 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3780 /* If the target wants uninitialized const declarations in \
3781 .rdata then don't put them in .comm */ \
3782 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3783 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3784 && (DECL_INITIAL (DECL) == 0 \
3785 || DECL_INITIAL (DECL) == error_mark_node)) \
3787 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3788 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3790 readonly_data_section (); \
3791 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3792 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3796 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3801 /* This says how to define a local common symbol (ie, not visible to
3804 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3805 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3808 /* This says how to output an external. It would be possible not to
3809 output anything and let undefined symbol become external. However
3810 the assembler uses length information on externals to allocate in
3811 data/sdata bss/sbss, thereby saving exec time. */
3813 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3814 mips_output_external(STREAM,DECL,NAME)
3817 /* This is how to declare a function name. The actual work of
3818 emitting the label is moved to function_prologue, so that we can
3819 get the line number correctly emitted before the .ent directive,
3820 and after any .file directives. Define as empty so that the function
3821 is not declared before the .ent directive elsewhere. */
3823 #undef ASM_DECLARE_FUNCTION_NAME
3824 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3826 /* This is how to store into the string LABEL
3827 the symbol_ref name of an internal numbered label where
3828 PREFIX is the class of label and NUM is the number within the class.
3829 This is suitable for output with `assemble_name'. */
3831 #undef ASM_GENERATE_INTERNAL_LABEL
3832 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3833 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3835 /* This is how to output an element of a case-vector that is absolute. */
3837 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3838 fprintf (STREAM, "\t%s\t%sL%d\n", \
3839 ptr_mode == DImode ? ".dword" : ".word", \
3840 LOCAL_LABEL_PREFIX, \
3843 /* This is how to output an element of a case-vector that is relative.
3844 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3845 TARGET_EMBEDDED_PIC). */
3847 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3849 if (TARGET_MIPS16) \
3850 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3851 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3852 else if (TARGET_EMBEDDED_PIC) \
3853 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3854 ptr_mode == DImode ? ".dword" : ".word", \
3855 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3856 else if (TARGET_GPWORD) \
3857 fprintf (STREAM, "\t%s\t%sL%d\n", \
3858 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3859 LOCAL_LABEL_PREFIX, VALUE); \
3861 fprintf (STREAM, "\t%s\t%sL%d\n", \
3862 ptr_mode == DImode ? ".dword" : ".word", \
3863 LOCAL_LABEL_PREFIX, VALUE); \
3866 /* When generating embedded PIC or mips16 code we want to put the jump
3867 table in the .text section. In all other cases, we want to put the
3868 jump table in the .rdata section. Unfortunately, we can't use
3869 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3870 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3871 section if appropriate. */
3872 #undef ASM_OUTPUT_CASE_LABEL
3873 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3875 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3876 function_section (current_function_decl); \
3877 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3880 /* This is how to output an assembler line
3881 that says to advance the location counter
3882 to a multiple of 2**LOG bytes. */
3884 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3885 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3887 /* This is how to output an assembler line to advance the location
3888 counter by SIZE bytes. */
3890 #undef ASM_OUTPUT_SKIP
3891 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3892 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3894 /* This is how to output a string. */
3895 #undef ASM_OUTPUT_ASCII
3896 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3897 mips_output_ascii (STREAM, STRING, LEN)
3899 /* Output #ident as a in the read-only data section. */
3900 #undef ASM_OUTPUT_IDENT
3901 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3903 const char *p = STRING; \
3904 int size = strlen (p) + 1; \
3905 readonly_data_section (); \
3906 assemble_string (p, size); \
3909 /* Default to -G 8 */
3910 #ifndef MIPS_DEFAULT_GVALUE
3911 #define MIPS_DEFAULT_GVALUE 8
3914 /* Define the strings to put out for each section in the object file. */
3915 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3916 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3917 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3919 #undef READONLY_DATA_SECTION_ASM_OP
3920 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3922 #define SMALL_DATA_SECTION sdata_section
3924 /* What other sections we support other than the normal .data/.text. */
3926 #undef EXTRA_SECTIONS
3927 #define EXTRA_SECTIONS in_sdata
3929 /* Define the additional functions to select our additional sections. */
3931 /* on the MIPS it is not a good idea to put constants in the text
3932 section, since this defeats the sdata/data mechanism. This is
3933 especially true when -O is used. In this case an effort is made to
3934 address with faster (gp) register relative addressing, which can
3935 only get at sdata and sbss items (there is no stext !!) However,
3936 if the constant is too large for sdata, and it's readonly, it
3937 will go into the .rdata section. */
3939 #undef EXTRA_SECTION_FUNCTIONS
3940 #define EXTRA_SECTION_FUNCTIONS \
3944 if (in_section != in_sdata) \
3946 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
3947 in_section = in_sdata; \
3951 /* Given a decl node or constant node, choose the section to output it in
3952 and select that section. */
3954 #undef TARGET_ASM_SELECT_SECTION
3955 #define TARGET_ASM_SELECT_SECTION mips_select_section
3957 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3960 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3961 TARGET_64BIT ? "dsubu" : "subu", \
3962 reg_names[STACK_POINTER_REGNUM], \
3963 reg_names[STACK_POINTER_REGNUM], \
3964 TARGET_64BIT ? "sd" : "sw", \
3966 reg_names[STACK_POINTER_REGNUM]); \
3970 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3973 if (! set_noreorder) \
3974 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3976 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3977 TARGET_64BIT ? "ld" : "lw", \
3979 reg_names[STACK_POINTER_REGNUM], \
3980 TARGET_64BIT ? "daddu" : "addu", \
3981 reg_names[STACK_POINTER_REGNUM], \
3982 reg_names[STACK_POINTER_REGNUM]); \
3984 if (! set_noreorder) \
3985 fprintf (STREAM, "\t.set\treorder\n"); \
3989 /* How to start an assembler comment.
3990 The leading space is important (the mips native assembler requires it). */
3991 #ifndef ASM_COMMENT_START
3992 #define ASM_COMMENT_START " #"
3996 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
3997 and mips-tdump.c to print them out.
3999 These must match the corresponding definitions in gdb/mipsread.c.
4000 Unfortunately, gcc and gdb do not currently share any directories. */
4002 #define CODE_MASK 0x8F300
4003 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4004 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4005 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4008 /* Default definitions for size_t and ptrdiff_t. We must override the
4009 definitions from ../svr4.h on mips-*-linux-gnu. */
4012 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
4015 #ifndef PTRDIFF_TYPE
4016 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
4019 /* See mips_expand_prologue's use of loadgp for when this should be
4022 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4023 && mips_abi != ABI_32 \
4024 && mips_abi != ABI_O64)
4026 /* We need to use a special set of functions to handle hard floating
4027 point code in mips16 mode. */
4029 #ifndef INIT_SUBTARGET_OPTABS
4030 #define INIT_SUBTARGET_OPTABS
4033 #define INIT_TARGET_OPTABS \
4036 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4037 INIT_SUBTARGET_OPTABS; \
4040 add_optab->handlers[(int) SFmode].libfunc = \
4041 init_one_libfunc ("__mips16_addsf3"); \
4042 sub_optab->handlers[(int) SFmode].libfunc = \
4043 init_one_libfunc ("__mips16_subsf3"); \
4044 smul_optab->handlers[(int) SFmode].libfunc = \
4045 init_one_libfunc ("__mips16_mulsf3"); \
4046 sdiv_optab->handlers[(int) SFmode].libfunc = \
4047 init_one_libfunc ("__mips16_divsf3"); \
4049 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4050 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4051 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4052 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4053 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4054 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4056 floatsisf_libfunc = \
4057 init_one_libfunc ("__mips16_floatsisf"); \
4059 init_one_libfunc ("__mips16_fixsfsi"); \
4061 if (TARGET_DOUBLE_FLOAT) \
4063 add_optab->handlers[(int) DFmode].libfunc = \
4064 init_one_libfunc ("__mips16_adddf3"); \
4065 sub_optab->handlers[(int) DFmode].libfunc = \
4066 init_one_libfunc ("__mips16_subdf3"); \
4067 smul_optab->handlers[(int) DFmode].libfunc = \
4068 init_one_libfunc ("__mips16_muldf3"); \
4069 sdiv_optab->handlers[(int) DFmode].libfunc = \
4070 init_one_libfunc ("__mips16_divdf3"); \
4072 extendsfdf2_libfunc = \
4073 init_one_libfunc ("__mips16_extendsfdf2"); \
4074 truncdfsf2_libfunc = \
4075 init_one_libfunc ("__mips16_truncdfsf2"); \
4078 init_one_libfunc ("__mips16_eqdf2"); \
4080 init_one_libfunc ("__mips16_nedf2"); \
4082 init_one_libfunc ("__mips16_gtdf2"); \
4084 init_one_libfunc ("__mips16_gedf2"); \
4086 init_one_libfunc ("__mips16_ltdf2"); \
4088 init_one_libfunc ("__mips16_ledf2"); \
4090 floatsidf_libfunc = \
4091 init_one_libfunc ("__mips16_floatsidf"); \
4093 init_one_libfunc ("__mips16_fixdfsi"); \
4099 #define DFMODE_NAN \
4100 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4101 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4102 #define SFMODE_NAN \
4103 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4104 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4106 /* Generate calls to memcpy, etc., not bcopy, etc. */
4107 #define TARGET_MEM_FUNCTIONS
4110 /* Since the bits of the _init and _fini function is spread across
4111 many object files, each potentially with its own GP, we must assume
4112 we need to load our GP. We don't preserve $gp or $ra, since each
4113 init/fini chunk is supposed to initialize $gp, and crti/crtn
4114 already take care of preserving $ra and, when appropriate, $gp. */
4115 #if _MIPS_SIM == _MIPS_SIM_ABI32
4116 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4117 asm (SECTION_OP "\n\
4123 jal " USER_LABEL_PREFIX #FUNC "\n\
4124 " TEXT_SECTION_ASM_OP);
4125 #endif /* Switch to #elif when we're no longer limited by K&R C. */
4126 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
4127 || (defined _ABI64 && _MIPS_SIM == _ABI64)
4128 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4129 asm (SECTION_OP "\n\
4134 .cpsetup $31, $2, 1b\n\
4135 jal " USER_LABEL_PREFIX #FUNC "\n\
4136 " TEXT_SECTION_ASM_OP);