1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
58 /* Enumeration for all of the relational tests, so that we can build
59 arrays indexed by the test type, and not worry about the order
76 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
77 #define UNSPEC_ADDRESS_P(X) \
78 (GET_CODE (X) == UNSPEC \
79 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
80 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
82 /* Extract the symbol or label from UNSPEC wrapper X. */
83 #define UNSPEC_ADDRESS(X) \
86 /* Extract the symbol type from UNSPEC wrapper X. */
87 #define UNSPEC_ADDRESS_TYPE(X) \
88 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
90 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
91 to initialize the mips16 gp pseudo register. */
92 #define CONST_GP_P(X) \
93 (GET_CODE (X) == CONST \
94 && GET_CODE (XEXP (X, 0)) == UNSPEC \
95 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
97 /* The maximum distance between the top of the stack frame and the
98 value $sp has when we save & restore registers.
100 Use a maximum gap of 0x100 in the mips16 case. We can then use
101 unextended instructions to save and restore registers, and to
102 allocate and deallocate the top part of the frame.
104 The value in the !mips16 case must be a SMALL_OPERAND and must
105 preserve the maximum stack alignment. It could really be 0x7ff0,
106 but SGI's assemblers implement daddiu $sp,$sp,-0x7ff0 as a
107 multi-instruction addu sequence. Use 0x7fe0 to work around this. */
108 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7fe0)
111 /* Classifies an address.
114 A natural register + offset address. The register satisfies
115 mips_valid_base_register_p and the offset is a const_arith_operand.
118 A LO_SUM rtx. The first operand is a valid base register and
119 the second operand is a symbolic address.
122 A signed 16-bit constant address.
125 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
126 enum mips_address_type {
133 /* A function to save or store a register. The first argument is the
134 register and the second is the stack slot. */
135 typedef void (*mips_save_restore_fn) (rtx, rtx);
138 struct mips_arg_info;
139 struct mips_address_info;
140 struct mips_integer_op;
142 static enum mips_symbol_type mips_classify_symbol (rtx);
143 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
144 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
145 static bool mips_symbolic_constant_p (rtx, enum mips_symbol_type *);
146 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
147 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
148 static bool mips_classify_address (struct mips_address_info *, rtx,
149 enum machine_mode, int);
150 static int mips_symbol_insns (enum mips_symbol_type);
151 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
152 static rtx mips_force_temporary (rtx, rtx);
153 static rtx mips_split_symbol (rtx, rtx);
154 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
155 static rtx mips_add_offset (rtx, HOST_WIDE_INT);
156 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
157 static unsigned int mips_build_lower (struct mips_integer_op *,
158 unsigned HOST_WIDE_INT);
159 static unsigned int mips_build_integer (struct mips_integer_op *,
160 unsigned HOST_WIDE_INT);
161 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
162 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
163 static int m16_check_op (rtx, int, int, int);
164 static bool mips_rtx_costs (rtx, int, int, int *);
165 static int mips_address_cost (rtx);
166 static enum internal_test map_test_to_internal_test (enum rtx_code);
167 static void get_float_compare_codes (enum rtx_code, enum rtx_code *,
169 static void mips_load_call_address (rtx, rtx, int);
170 static bool mips_function_ok_for_sibcall (tree, tree);
171 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
172 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
173 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
174 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
175 tree, int, struct mips_arg_info *);
176 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
177 static void mips_set_architecture (const struct mips_cpu_info *);
178 static void mips_set_tune (const struct mips_cpu_info *);
179 static struct machine_function *mips_init_machine_status (void);
180 static void print_operand_reloc (FILE *, rtx, const char **);
181 static bool mips_assemble_integer (rtx, unsigned int, int);
182 static void mips_file_start (void);
183 static void mips_file_end (void);
184 static bool mips_rewrite_small_data_p (rtx);
185 static int small_data_pattern_1 (rtx *, void *);
186 static int mips_rewrite_small_data_1 (rtx *, void *);
187 static bool mips_function_has_gp_insn (void);
188 static unsigned int mips_global_pointer (void);
189 static bool mips_save_reg_p (unsigned int);
190 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
191 mips_save_restore_fn);
192 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
193 static void mips_output_cplocal (void);
194 static void mips_emit_loadgp (void);
195 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
196 static void mips_set_frame_expr (rtx);
197 static rtx mips_frame_set (rtx, rtx);
198 static void mips_save_reg (rtx, rtx);
199 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
200 static void mips_restore_reg (rtx, rtx);
201 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
202 HOST_WIDE_INT, tree);
203 static int symbolic_expression_p (rtx);
204 static void mips_select_rtx_section (enum machine_mode, rtx,
205 unsigned HOST_WIDE_INT);
206 static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
208 static bool mips_in_small_data_p (tree);
209 static void mips_encode_section_info (tree, rtx, int);
210 static int mips_fpr_return_fields (tree, tree *);
211 static bool mips_return_in_msb (tree);
212 static rtx mips_return_fpr_pair (enum machine_mode mode,
213 enum machine_mode mode1, HOST_WIDE_INT,
214 enum machine_mode mode2, HOST_WIDE_INT);
215 static rtx mips16_gp_pseudo_reg (void);
216 static void mips16_fp_args (FILE *, int, int);
217 static void build_mips16_function_stub (FILE *);
218 static rtx add_constant (struct constant **, rtx, enum machine_mode);
219 static void dump_constants (struct constant *, rtx);
220 static rtx mips_find_symbol (rtx);
221 static void mips16_lay_out_constants (void);
222 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
223 static void mips_avoid_hazards (void);
224 static void mips_reorg (void);
225 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
226 static bool mips_matching_cpu_name_p (const char *, const char *);
227 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
228 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
229 static int mips_adjust_cost (rtx, rtx, rtx, int);
230 static bool mips_return_in_memory (tree, tree);
231 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
232 static int mips_issue_rate (void);
233 static int mips_use_dfa_pipeline_interface (void);
234 static void mips_init_libfuncs (void);
235 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
237 static tree mips_build_builtin_va_list (void);
240 static void irix_asm_named_section_1 (const char *, unsigned int,
242 static void irix_asm_named_section (const char *, unsigned int);
243 static int irix_section_align_entry_eq (const void *, const void *);
244 static hashval_t irix_section_align_entry_hash (const void *);
245 static void irix_file_start (void);
246 static int irix_section_align_1 (void **, void *);
247 static void copy_file_data (FILE *, FILE *);
248 static void irix_file_end (void);
249 static unsigned int irix_section_type_flags (tree, const char *, int);
252 /* Structure to be filled in by compute_frame_size with register
253 save masks, and offsets for the current function. */
255 struct mips_frame_info GTY(())
257 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
258 HOST_WIDE_INT var_size; /* # bytes that variables take up */
259 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
260 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
261 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
262 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
263 unsigned int mask; /* mask of saved gp registers */
264 unsigned int fmask; /* mask of saved fp registers */
265 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
266 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
267 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
268 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
269 bool initialized; /* true if frame size already calculated */
270 int num_gp; /* number of gp registers saved */
271 int num_fp; /* number of fp registers saved */
274 struct machine_function GTY(()) {
275 /* Pseudo-reg holding the address of the current function when
276 generating embedded PIC code. */
277 rtx embedded_pic_fnaddr_rtx;
279 /* Pseudo-reg holding the value of $28 in a mips16 function which
280 refers to GP relative global variables. */
281 rtx mips16_gp_pseudo_rtx;
283 /* Current frame information, calculated by compute_frame_size. */
284 struct mips_frame_info frame;
286 /* Length of instructions in function; mips16 only. */
289 /* The register to use as the global pointer within this function. */
290 unsigned int global_pointer;
292 /* True if mips_adjust_insn_length should ignore an instruction's
294 bool ignore_hazard_length_p;
296 /* True if the whole function is suitable for .set noreorder and
298 bool all_noreorder_p;
300 /* True if the function is known to have an instruction that needs $gp. */
304 /* Information about a single argument. */
307 /* True if the argument is passed in a floating-point register, or
308 would have been if we hadn't run out of registers. */
311 /* The argument's size, in bytes. */
312 unsigned int num_bytes;
314 /* The number of words passed in registers, rounded up. */
315 unsigned int reg_words;
317 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
318 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
320 unsigned int reg_offset;
322 /* The number of words that must be passed on the stack, rounded up. */
323 unsigned int stack_words;
325 /* The offset from the start of the stack overflow area of the argument's
326 first stack word. Only meaningful when STACK_WORDS is nonzero. */
327 unsigned int stack_offset;
331 /* Information about an address described by mips_address_type.
337 REG is the base register and OFFSET is the constant offset.
340 REG is the register that contains the high part of the address,
341 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
342 is the type of OFFSET's symbol.
345 SYMBOL_TYPE is the type of symbol being referenced. */
347 struct mips_address_info
349 enum mips_address_type type;
352 enum mips_symbol_type symbol_type;
356 /* One stage in a constant building sequence. These sequences have
360 A = A CODE[1] VALUE[1]
361 A = A CODE[2] VALUE[2]
364 where A is an accumulator, each CODE[i] is a binary rtl operation
365 and each VALUE[i] is a constant integer. */
366 struct mips_integer_op {
368 unsigned HOST_WIDE_INT value;
372 /* The largest number of operations needed to load an integer constant.
373 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
374 When the lowest bit is clear, we can try, but reject a sequence with
375 an extra SLL at the end. */
376 #define MIPS_MAX_INTEGER_OPS 7
379 /* Global variables for machine-dependent things. */
381 /* Threshold for data being put into the small data/bss area, instead
382 of the normal data area. */
383 int mips_section_threshold = -1;
385 /* Count the number of .file directives, so that .loc is up to date. */
386 int num_source_filenames = 0;
388 /* Count the number of sdb related labels are generated (to find block
389 start and end boundaries). */
390 int sdb_label_count = 0;
392 /* Next label # for each statement for Silicon Graphics IRIS systems. */
395 /* Linked list of all externals that are to be emitted when optimizing
396 for the global pointer if they haven't been declared by the end of
397 the program with an appropriate .comm or initialization. */
399 struct extern_list GTY (())
401 struct extern_list *next; /* next external */
402 const char *name; /* name of the external */
403 int size; /* size in bytes */
406 static GTY (()) struct extern_list *extern_head = 0;
408 /* Name of the file containing the current function. */
409 const char *current_function_file = "";
411 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
417 /* The next branch instruction is a branch likely, not branch normal. */
418 int mips_branch_likely;
420 /* Cached operands, and operator to compare for use in set/branch/trap
421 on condition codes. */
424 /* what type of branch to use */
425 enum cmp_type branch_type;
427 /* The target cpu for code generation. */
428 enum processor_type mips_arch;
429 const struct mips_cpu_info *mips_arch_info;
431 /* The target cpu for optimization and scheduling. */
432 enum processor_type mips_tune;
433 const struct mips_cpu_info *mips_tune_info;
435 /* Which instruction set architecture to use. */
438 /* Which ABI to use. */
441 /* Strings to hold which cpu and instruction set architecture to use. */
442 const char *mips_arch_string; /* for -march=<xxx> */
443 const char *mips_tune_string; /* for -mtune=<xxx> */
444 const char *mips_isa_string; /* for -mips{1,2,3,4} */
445 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
447 /* Whether we are generating mips16 hard float code. In mips16 mode
448 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
449 -msoft-float was not specified by the user, which means that we
450 should arrange to call mips32 hard floating point code. */
451 int mips16_hard_float;
453 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
455 /* If TRUE, we split addresses into their high and low parts in the RTL. */
456 int mips_split_addresses;
458 /* Mode used for saving/restoring general purpose registers. */
459 static enum machine_mode gpr_mode;
461 /* Array giving truth value on whether or not a given hard register
462 can support a given mode. */
463 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
465 /* The length of all strings seen when compiling for the mips16. This
466 is used to tell how many strings are in the constant pool, so that
467 we can see if we may have an overflow. This is reset each time the
468 constant pool is output. */
469 int mips_string_length;
471 /* When generating mips16 code, a list of all strings that are to be
472 output after the current function. */
474 static GTY(()) rtx mips16_strings;
476 /* In mips16 mode, we build a list of all the string constants we see
477 in a particular function. */
479 struct string_constant
481 struct string_constant *next;
485 static struct string_constant *string_constants;
487 /* List of all MIPS punctuation characters used by print_operand. */
488 char mips_print_operand_punct[256];
490 /* Map GCC register number to debugger register number. */
491 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
493 /* A copy of the original flag_delayed_branch: see override_options. */
494 static int mips_flag_delayed_branch;
496 static GTY (()) int mips_output_filename_first_time = 1;
498 /* mips_split_p[X] is true if symbols of type X can be split by
499 mips_split_symbol(). */
500 static bool mips_split_p[NUM_SYMBOL_TYPES];
502 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
503 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
504 if they are matched by a special .md file pattern. */
505 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
507 /* Likewise for HIGHs. */
508 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
510 /* Hardware names for the registers. If -mrnames is used, this
511 will be overwritten with mips_sw_reg_names. */
513 char mips_reg_names[][8] =
515 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
516 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
517 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
518 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
519 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
520 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
521 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
522 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
523 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
524 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec",
525 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
526 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
527 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
528 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
529 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
530 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
531 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
532 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
533 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
534 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
535 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
536 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
539 /* Mips software names for the registers, used to overwrite the
540 mips_reg_names array. */
542 char mips_sw_reg_names[][8] =
544 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
545 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
546 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
547 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
548 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
549 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
550 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
551 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
552 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
553 "$fcc5","$fcc6","$fcc7","$rap", "", "$arg", "$frame", "$fakec",
554 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
555 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
556 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
557 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
558 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
559 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
560 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
561 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
562 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
563 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
564 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
565 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
568 /* Map hard register number to register class */
569 const enum reg_class mips_regno_to_class[] =
571 LEA_REGS, LEA_REGS, M16_NA_REGS, M16_NA_REGS,
572 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
573 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
574 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
575 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
576 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
577 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
578 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
579 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
580 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
581 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
582 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
583 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
584 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
585 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
586 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
587 HI_REG, LO_REG, NO_REGS, ST_REGS,
588 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
589 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
590 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
591 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
592 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
593 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
594 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
595 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
596 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
597 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
598 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
599 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
600 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
601 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
602 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
603 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
604 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
605 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
606 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
607 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
608 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
609 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
610 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
611 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
612 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
613 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
614 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
617 /* Map register constraint character to register class. */
618 enum reg_class mips_char_to_class[256];
620 /* A table describing all the processors gcc knows about. Names are
621 matched in the order listed. The first mention of an ISA level is
622 taken as the canonical name for that ISA.
624 To ease comparison, please keep this table in the same order as
625 gas's mips_cpu_info_table[]. */
626 const struct mips_cpu_info mips_cpu_info_table[] = {
627 /* Entries for generic ISAs */
628 { "mips1", PROCESSOR_R3000, 1 },
629 { "mips2", PROCESSOR_R6000, 2 },
630 { "mips3", PROCESSOR_R4000, 3 },
631 { "mips4", PROCESSOR_R8000, 4 },
632 { "mips32", PROCESSOR_4KC, 32 },
633 { "mips32r2", PROCESSOR_M4K, 33 },
634 { "mips64", PROCESSOR_5KC, 64 },
637 { "r3000", PROCESSOR_R3000, 1 },
638 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
639 { "r3900", PROCESSOR_R3900, 1 },
642 { "r6000", PROCESSOR_R6000, 2 },
645 { "r4000", PROCESSOR_R4000, 3 },
646 { "vr4100", PROCESSOR_R4100, 3 },
647 { "vr4111", PROCESSOR_R4111, 3 },
648 { "vr4120", PROCESSOR_R4120, 3 },
649 { "vr4130", PROCESSOR_R4130, 3 },
650 { "vr4300", PROCESSOR_R4300, 3 },
651 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
652 { "r4600", PROCESSOR_R4600, 3 },
653 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
654 { "r4650", PROCESSOR_R4650, 3 },
657 { "r8000", PROCESSOR_R8000, 4 },
658 { "vr5000", PROCESSOR_R5000, 4 },
659 { "vr5400", PROCESSOR_R5400, 4 },
660 { "vr5500", PROCESSOR_R5500, 4 },
661 { "rm7000", PROCESSOR_R7000, 4 },
662 { "rm9000", PROCESSOR_R9000, 4 },
665 { "4kc", PROCESSOR_4KC, 32 },
666 { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
668 /* MIPS32 Release 2 */
669 { "m4k", PROCESSOR_M4K, 33 },
672 { "5kc", PROCESSOR_5KC, 64 },
673 { "20kc", PROCESSOR_20KC, 64 },
674 { "sb1", PROCESSOR_SB1, 64 },
675 { "sr71000", PROCESSOR_SR71000, 64 },
681 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
682 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
683 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
686 /* Initialize the GCC target structure. */
687 #undef TARGET_ASM_ALIGNED_HI_OP
688 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
689 #undef TARGET_ASM_ALIGNED_SI_OP
690 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
691 #undef TARGET_ASM_INTEGER
692 #define TARGET_ASM_INTEGER mips_assemble_integer
694 #undef TARGET_ASM_FUNCTION_PROLOGUE
695 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
696 #undef TARGET_ASM_FUNCTION_EPILOGUE
697 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
698 #undef TARGET_ASM_SELECT_RTX_SECTION
699 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
701 #undef TARGET_SCHED_ADJUST_COST
702 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
703 #undef TARGET_SCHED_ISSUE_RATE
704 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
705 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
706 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
708 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
709 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
711 #undef TARGET_VALID_POINTER_MODE
712 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
713 #undef TARGET_RTX_COSTS
714 #define TARGET_RTX_COSTS mips_rtx_costs
715 #undef TARGET_ADDRESS_COST
716 #define TARGET_ADDRESS_COST mips_address_cost
718 #undef TARGET_ENCODE_SECTION_INFO
719 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
720 #undef TARGET_IN_SMALL_DATA_P
721 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
723 #undef TARGET_MACHINE_DEPENDENT_REORG
724 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
726 #undef TARGET_ASM_FILE_START
727 #undef TARGET_ASM_FILE_END
729 #define TARGET_ASM_FILE_START irix_file_start
730 #define TARGET_ASM_FILE_END irix_file_end
732 #define TARGET_ASM_FILE_START mips_file_start
733 #define TARGET_ASM_FILE_END mips_file_end
735 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
736 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
739 #undef TARGET_SECTION_TYPE_FLAGS
740 #define TARGET_SECTION_TYPE_FLAGS irix_section_type_flags
743 #undef TARGET_INIT_LIBFUNCS
744 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
746 #undef TARGET_BUILD_BUILTIN_VA_LIST
747 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
749 #undef TARGET_PROMOTE_FUNCTION_ARGS
750 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
751 #undef TARGET_PROMOTE_FUNCTION_RETURN
752 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
753 #undef TARGET_PROMOTE_PROTOTYPES
754 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
756 #undef TARGET_RETURN_IN_MEMORY
757 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
758 #undef TARGET_RETURN_IN_MSB
759 #define TARGET_RETURN_IN_MSB mips_return_in_msb
761 #undef TARGET_ASM_OUTPUT_MI_THUNK
762 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
763 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
764 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
766 #undef TARGET_SETUP_INCOMING_VARARGS
767 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
768 #undef TARGET_STRICT_ARGUMENT_NAMING
769 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
771 struct gcc_target targetm = TARGET_INITIALIZER;
773 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
775 static enum mips_symbol_type
776 mips_classify_symbol (rtx x)
778 if (GET_CODE (x) == LABEL_REF)
779 return (TARGET_ABICALLS ? SYMBOL_GOT_LOCAL : SYMBOL_GENERAL);
781 if (GET_CODE (x) != SYMBOL_REF)
784 if (CONSTANT_POOL_ADDRESS_P (x))
787 return SYMBOL_CONSTANT_POOL;
790 return SYMBOL_GOT_LOCAL;
792 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
793 return SYMBOL_SMALL_DATA;
795 return SYMBOL_GENERAL;
798 if (SYMBOL_REF_SMALL_P (x))
799 return SYMBOL_SMALL_DATA;
801 /* When generating mips16 code, SYMBOL_REF_FLAG indicates a string
802 in the current function's constant pool. */
803 if (TARGET_MIPS16 && SYMBOL_REF_FLAG (x))
804 return SYMBOL_CONSTANT_POOL;
808 if (SYMBOL_REF_DECL (x) == 0)
809 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
811 /* There are three cases to consider:
813 - o32 PIC (either with or without explicit relocs)
814 - n32/n64 PIC without explicit relocs
815 - n32/n64 PIC with explicit relocs
817 In the first case, both local and global accesses will use an
818 R_MIPS_GOT16 relocation. We must correctly predict which of
819 the two semantics (local or global) the assembler and linker
820 will apply. The choice doesn't depend on the symbol's
821 visibility, so we deliberately ignore decl_visibility and
824 In the second case, the assembler will not use R_MIPS_GOT16
825 relocations, but it chooses between local and global accesses
826 in the same way as for o32 PIC.
828 In the third case we have more freedom since both forms of
829 access will work for any kind of symbol. However, there seems
830 little point in doing things differently. */
831 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
832 return SYMBOL_GOT_GLOBAL;
834 return SYMBOL_GOT_LOCAL;
837 return SYMBOL_GENERAL;
841 /* Split X into a base and a constant offset, storing them in *BASE
842 and *OFFSET respectively. */
845 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
849 if (GET_CODE (x) == CONST)
852 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
854 *offset += INTVAL (XEXP (x, 1));
861 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
862 to the same object as SYMBOL. */
865 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
867 if (GET_CODE (symbol) != SYMBOL_REF)
870 if (CONSTANT_POOL_ADDRESS_P (symbol)
872 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
875 if (SYMBOL_REF_DECL (symbol) != 0
877 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
884 /* Return true if X is a symbolic constant that can be calculated in
885 the same way as a bare symbol. If it is, store the type of the
886 symbol in *SYMBOL_TYPE. */
889 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
891 HOST_WIDE_INT offset;
893 mips_split_const (x, &x, &offset);
894 if (UNSPEC_ADDRESS_P (x))
895 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
896 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
897 *symbol_type = mips_classify_symbol (x);
904 /* Check whether a nonzero offset is valid for the underlying
906 switch (*symbol_type)
912 /* If the target has 64-bit pointers and the object file only
913 supports 32-bit symbols, the values of those symbols will be
914 sign-extended. In this case we can't allow an arbitrary offset
915 in case the 32-bit value X + OFFSET has a different sign from X. */
916 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
917 return mips_offset_within_object_p (x, offset);
919 /* In other cases the relocations can handle any offset. */
922 case SYMBOL_SMALL_DATA:
923 case SYMBOL_CONSTANT_POOL:
924 /* Make sure that the offset refers to something within the
925 underlying object. This should guarantee that the final
926 PC- or GP-relative offset is within the 16-bit limit. */
927 return mips_offset_within_object_p (x, offset);
929 case SYMBOL_GOT_LOCAL:
930 case SYMBOL_GOTOFF_PAGE:
931 /* The linker should provide enough local GOT entries for a
932 16-bit offset. Larger offsets may lead to GOT overflow. */
933 return SMALL_OPERAND (offset);
935 case SYMBOL_GOT_GLOBAL:
936 case SYMBOL_GOTOFF_GLOBAL:
937 case SYMBOL_GOTOFF_CALL:
938 case SYMBOL_GOTOFF_LOADGP:
945 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
948 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
950 if (regno >= FIRST_PSEUDO_REGISTER)
954 regno = reg_renumber[regno];
957 /* These fake registers will be eliminated to either the stack or
958 hard frame pointer, both of which are usually valid base registers.
959 Reload deals with the cases where the eliminated form isn't valid. */
960 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
963 /* In mips16 mode, the stack pointer can only address word and doubleword
964 values, nothing smaller. There are two problems here:
966 (a) Instantiating virtual registers can introduce new uses of the
967 stack pointer. If these virtual registers are valid addresses,
968 the stack pointer should be too.
970 (b) Most uses of the stack pointer are not made explicit until
971 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
972 We don't know until that stage whether we'll be eliminating to the
973 stack pointer (which needs the restriction) or the hard frame
974 pointer (which doesn't).
976 All in all, it seems more consistent to only enforce this restriction
977 during and after reload. */
978 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
979 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
981 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
985 /* Return true if X is a valid base register for the given mode.
986 Allow only hard registers if STRICT. */
989 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
991 if (!strict && GET_CODE (x) == SUBREG)
994 return (GET_CODE (x) == REG
995 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
999 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1000 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1003 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1004 enum machine_mode mode)
1006 switch (symbol_type)
1008 case SYMBOL_GENERAL:
1009 return !TARGET_MIPS16;
1011 case SYMBOL_SMALL_DATA:
1014 case SYMBOL_CONSTANT_POOL:
1015 /* PC-relative addressing is only available for lw, sw, ld and sd. */
1016 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1018 case SYMBOL_GOT_LOCAL:
1021 case SYMBOL_GOT_GLOBAL:
1022 /* The address will have to be loaded from the GOT first. */
1025 case SYMBOL_GOTOFF_PAGE:
1026 case SYMBOL_GOTOFF_GLOBAL:
1027 case SYMBOL_GOTOFF_CALL:
1028 case SYMBOL_GOTOFF_LOADGP:
1029 case SYMBOL_64_HIGH:
1038 /* Return true if X is a valid address for machine mode MODE. If it is,
1039 fill in INFO appropriately. STRICT is true if we should only accept
1040 hard base registers. */
1043 mips_classify_address (struct mips_address_info *info, rtx x,
1044 enum machine_mode mode, int strict)
1046 switch (GET_CODE (x))
1050 info->type = ADDRESS_REG;
1052 info->offset = const0_rtx;
1053 return mips_valid_base_register_p (info->reg, mode, strict);
1056 info->type = ADDRESS_REG;
1057 info->reg = XEXP (x, 0);
1058 info->offset = XEXP (x, 1);
1059 return (mips_valid_base_register_p (info->reg, mode, strict)
1060 && const_arith_operand (info->offset, VOIDmode));
1063 info->type = ADDRESS_LO_SUM;
1064 info->reg = XEXP (x, 0);
1065 info->offset = XEXP (x, 1);
1066 return (mips_valid_base_register_p (info->reg, mode, strict)
1067 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1068 && mips_symbolic_address_p (info->symbol_type, mode)
1069 && mips_lo_relocs[info->symbol_type] != 0);
1072 /* Small-integer addresses don't occur very often, but they
1073 are legitimate if $0 is a valid base register. */
1074 info->type = ADDRESS_CONST_INT;
1075 return !TARGET_MIPS16 && SMALL_INT (x);
1080 info->type = ADDRESS_SYMBOLIC;
1081 return (mips_symbolic_constant_p (x, &info->symbol_type)
1082 && mips_symbolic_address_p (info->symbol_type, mode)
1083 && !mips_split_p[info->symbol_type]);
1090 /* Return the number of instructions needed to load a symbol of the
1091 given type into a register. If valid in an address, the same number
1092 of instructions are needed for loads and stores. Treat extended
1093 mips16 instructions as two instructions. */
1096 mips_symbol_insns (enum mips_symbol_type type)
1100 case SYMBOL_GENERAL:
1101 /* In mips16 code, general symbols must be fetched from the
1106 /* When using 64-bit symbols, we need 5 preparatory instructions,
1109 lui $at,%highest(symbol)
1110 daddiu $at,$at,%higher(symbol)
1112 daddiu $at,$at,%hi(symbol)
1115 The final address is then $at + %lo(symbol). With 32-bit
1116 symbols we just need a preparatory lui. */
1117 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1119 case SYMBOL_SMALL_DATA:
1122 case SYMBOL_CONSTANT_POOL:
1123 /* This case is for mips16 only. Assume we'll need an
1124 extended instruction. */
1127 case SYMBOL_GOT_LOCAL:
1128 case SYMBOL_GOT_GLOBAL:
1129 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1130 the local/global classification is accurate. See override_options
1133 The worst cases are:
1135 (1) For local symbols when generating o32 or o64 code. The assembler
1141 ...and the final address will be $at + %lo(symbol).
1143 (2) For global symbols when -mxgot. The assembler will use:
1145 lui $at,%got_hi(symbol)
1148 ...and the final address will be $at + %got_lo(symbol). */
1151 case SYMBOL_GOTOFF_PAGE:
1152 case SYMBOL_GOTOFF_GLOBAL:
1153 case SYMBOL_GOTOFF_CALL:
1154 case SYMBOL_GOTOFF_LOADGP:
1155 case SYMBOL_64_HIGH:
1158 /* Check whether the offset is a 16- or 32-bit value. */
1159 return mips_split_p[type] ? 2 : 1;
1165 /* Return true if a value at OFFSET bytes from BASE can be accessed
1166 using an unextended mips16 instruction. MODE is the mode of the
1169 Usually the offset in an unextended instruction is a 5-bit field.
1170 The offset is unsigned and shifted left once for HIs, twice
1171 for SIs, and so on. An exception is SImode accesses off the
1172 stack pointer, which have an 8-bit immediate field. */
1175 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1178 && GET_CODE (offset) == CONST_INT
1179 && INTVAL (offset) >= 0
1180 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1182 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1183 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1184 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1190 /* Return the number of instructions needed to load or store a value
1191 of mode MODE at X. Return 0 if X isn't valid for MODE.
1193 For mips16 code, count extended instructions as two instructions. */
1196 mips_address_insns (rtx x, enum machine_mode mode)
1198 struct mips_address_info addr;
1201 if (mode == BLKmode)
1202 /* BLKmode is used for single unaligned loads and stores. */
1205 /* Each word of a multi-word value will be accessed individually. */
1206 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1208 if (mips_classify_address (&addr, x, mode, false))
1213 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1217 case ADDRESS_LO_SUM:
1218 return (TARGET_MIPS16 ? factor * 2 : factor);
1220 case ADDRESS_CONST_INT:
1223 case ADDRESS_SYMBOLIC:
1224 return factor * mips_symbol_insns (addr.symbol_type);
1230 /* Likewise for constant X. */
1233 mips_const_insns (rtx x)
1235 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1236 enum mips_symbol_type symbol_type;
1237 HOST_WIDE_INT offset;
1239 switch (GET_CODE (x))
1241 case CONSTANT_P_RTX:
1246 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1247 || !mips_split_p[symbol_type])
1254 /* Unsigned 8-bit constants can be loaded using an unextended
1255 LI instruction. Unsigned 16-bit constants can be loaded
1256 using an extended LI. Negative constants must be loaded
1257 using LI and then negated. */
1258 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1259 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1260 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1261 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1264 return mips_build_integer (codes, INTVAL (x));
1267 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1273 /* See if we can refer to X directly. */
1274 if (mips_symbolic_constant_p (x, &symbol_type))
1275 return mips_symbol_insns (symbol_type);
1277 /* Otherwise try splitting the constant into a base and offset.
1278 16-bit offsets can be added using an extra addiu. Larger offsets
1279 must be calculated separately and then added to the base. */
1280 mips_split_const (x, &x, &offset);
1283 int n = mips_const_insns (x);
1286 if (SMALL_OPERAND (offset))
1289 return n + 1 + mips_build_integer (codes, offset);
1296 return mips_symbol_insns (mips_classify_symbol (x));
1304 /* Return the number of instructions needed for memory reference X.
1305 Count extended mips16 instructions as two instructions. */
1308 mips_fetch_insns (rtx x)
1310 if (GET_CODE (x) != MEM)
1313 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1317 /* Return the number of instructions needed for an integer division. */
1320 mips_idiv_insns (void)
1325 if (TARGET_CHECK_ZERO_DIV)
1327 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1333 /* Return truth value of whether OP can be used as an operands
1334 where a register or 16 bit unsigned integer is needed. */
1337 uns_arith_operand (rtx op, enum machine_mode mode)
1339 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
1342 return register_operand (op, mode);
1346 /* True if OP can be treated as a signed 16-bit constant. */
1349 const_arith_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1351 return GET_CODE (op) == CONST_INT && SMALL_INT (op);
1355 /* Return true if OP is a register operand or a signed 16-bit constant. */
1358 arith_operand (rtx op, enum machine_mode mode)
1360 return const_arith_operand (op, mode) || register_operand (op, mode);
1363 /* Return truth value of whether OP is an integer which fits in 16 bits. */
1366 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1368 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1371 /* Return truth value of whether OP is a register or the constant 0.
1372 Do not accept 0 in mips16 mode since $0 is not one of the core 8
1376 reg_or_0_operand (rtx op, enum machine_mode mode)
1378 switch (GET_CODE (op))
1383 return INTVAL (op) == 0;
1388 return op == CONST0_RTX (mode);
1391 return register_operand (op, mode);
1395 /* Accept a register or the floating point constant 1 in the appropriate mode. */
1398 reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
1402 switch (GET_CODE (op))
1405 if (mode != GET_MODE (op)
1406 || (mode != DFmode && mode != SFmode))
1409 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1410 return REAL_VALUES_EQUAL (d, dconst1);
1413 return register_operand (op, mode);
1417 /* Accept the floating point constant 1 in the appropriate mode. */
1420 const_float_1_operand (rtx op, enum machine_mode mode)
1424 if (GET_CODE (op) != CONST_DOUBLE
1425 || mode != GET_MODE (op)
1426 || (mode != DFmode && mode != SFmode))
1429 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1431 return REAL_VALUES_EQUAL (d, dconst1);
1434 /* Return true if OP is either the HI or LO register. */
1437 hilo_operand (rtx op, enum machine_mode mode)
1439 return ((mode == VOIDmode || mode == GET_MODE (op))
1440 && REG_P (op) && MD_REG_P (REGNO (op)));
1443 /* Return true if OP is an extension operator. */
1446 extend_operator (rtx op, enum machine_mode mode)
1448 return ((mode == VOIDmode || mode == GET_MODE (op))
1449 && (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
1452 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1455 equality_op (rtx op, enum machine_mode mode)
1457 if (mode != GET_MODE (op))
1460 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
1463 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1466 cmp_op (rtx op, enum machine_mode mode)
1468 if (mode != GET_MODE (op))
1471 return COMPARISON_P (op);
1474 /* Return nonzero if the code is a relational operation suitable for a
1475 conditional trap instruction (only EQ, NE, LT, LTU, GE, GEU).
1476 We need this in the insn that expands `trap_if' in order to prevent
1477 combine from erroneously altering the condition. */
1480 trap_cmp_op (rtx op, enum machine_mode mode)
1482 if (mode != GET_MODE (op))
1485 switch (GET_CODE (op))
1500 /* Return nonzero if the operand is either the PC or a label_ref. */
1503 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1508 if (GET_CODE (op) == LABEL_REF)
1514 /* Test for a valid call address. */
1517 call_insn_operand (rtx op, enum machine_mode mode)
1519 enum mips_symbol_type symbol_type;
1521 if (mips_symbolic_constant_p (op, &symbol_type))
1522 switch (symbol_type)
1524 case SYMBOL_GENERAL:
1525 /* If -mlong-calls, force all calls to use register addressing. */
1526 return !TARGET_LONG_CALLS;
1528 case SYMBOL_GOT_GLOBAL:
1529 /* Without explicit relocs, there is no special syntax for
1530 loading the address of a call destination into a register.
1531 Using "la $25,foo; jal $25" would prevent the lazy binding
1532 of "foo", so keep the address of global symbols with the
1534 return !TARGET_EXPLICIT_RELOCS;
1539 return register_operand (op, mode);
1543 /* Return nonzero if OP is valid as a source operand for a move
1547 move_operand (rtx op, enum machine_mode mode)
1549 enum mips_symbol_type symbol_type;
1551 if (!general_operand (op, mode))
1554 switch (GET_CODE (op))
1557 /* When generating mips16 code, LEGITIMATE_CONSTANT_P rejects
1558 CONST_INTs that can't be loaded using simple insns. */
1562 /* When generating 32-bit code, allow DImode move_operands to
1563 match arbitrary constants. We split them after reload. */
1564 if (!TARGET_64BIT && mode == DImode)
1567 /* Otherwise check whether the constant can be loaded in a single
1569 return LUI_INT (op) || SMALL_INT (op) || SMALL_INT_UNSIGNED (op);
1574 if (CONST_GP_P (op))
1577 return (mips_symbolic_constant_p (op, &symbol_type)
1578 && !mips_split_p[symbol_type]);
1586 /* Accept any operand that can appear in a mips16 constant table
1587 instruction. We can't use any of the standard operand functions
1588 because for these instructions we accept values that are not
1589 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1592 consttable_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1594 return CONSTANT_P (op);
1597 /* Return 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1598 possibly with an offset. */
1601 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1603 enum mips_symbol_type symbol_type;
1605 return mips_symbolic_constant_p (op, &symbol_type);
1609 /* Return true if OP is a symbolic constant of type SYMBOL_GENERAL. */
1612 general_symbolic_operand (rtx op, enum machine_mode mode)
1614 enum mips_symbol_type symbol_type;
1616 return ((mode == VOIDmode || mode == GET_MODE (op))
1617 && mips_symbolic_constant_p (op, &symbol_type)
1618 && symbol_type == SYMBOL_GENERAL);
1622 /* Return true if we're generating PIC and OP is a global symbol. */
1625 global_got_operand (rtx op, enum machine_mode mode)
1627 enum mips_symbol_type symbol_type;
1629 return ((mode == VOIDmode || mode == GET_MODE (op))
1630 && mips_symbolic_constant_p (op, &symbol_type)
1631 && symbol_type == SYMBOL_GOT_GLOBAL);
1635 /* Likewise for local symbols. */
1638 local_got_operand (rtx op, enum machine_mode mode)
1640 enum mips_symbol_type symbol_type;
1642 return ((mode == VOIDmode || mode == GET_MODE (op))
1643 && mips_symbolic_constant_p (op, &symbol_type)
1644 && symbol_type == SYMBOL_GOT_LOCAL);
1648 /* Return true if OP is a memory reference that uses the stack pointer
1649 as a base register. */
1652 stack_operand (rtx op, enum machine_mode mode)
1654 struct mips_address_info addr;
1656 return ((mode == VOIDmode || mode == GET_MODE (op))
1657 && GET_CODE (op) == MEM
1658 && mips_classify_address (&addr, XEXP (op, 0), GET_MODE (op), false)
1659 && addr.type == ADDRESS_REG
1660 && addr.reg == stack_pointer_rtx);
1664 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1665 returns a nonzero value if X is a legitimate address for a memory
1666 operand of the indicated MODE. STRICT is nonzero if this function
1667 is called during reload. */
1670 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1672 struct mips_address_info addr;
1674 return mips_classify_address (&addr, x, mode, strict);
1678 /* Copy VALUE to a register and return that register. If new psuedos
1679 are allowed, copy it into a new register, otherwise use DEST. */
1682 mips_force_temporary (rtx dest, rtx value)
1684 if (!no_new_pseudos)
1685 return force_reg (Pmode, value);
1688 emit_move_insn (copy_rtx (dest), value);
1694 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1695 and is used to load the high part into a register. */
1698 mips_split_symbol (rtx temp, rtx addr)
1703 high = mips16_gp_pseudo_reg ();
1705 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1706 return gen_rtx_LO_SUM (Pmode, high, addr);
1710 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1711 type SYMBOL_TYPE. */
1714 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1717 HOST_WIDE_INT offset;
1719 mips_split_const (address, &base, &offset);
1720 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1721 UNSPEC_ADDRESS_FIRST + symbol_type);
1722 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1726 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1727 high part to BASE and return the result. Just return BASE otherwise.
1728 TEMP is available as a temporary register if needed.
1730 The returned expression can be used as the first operand to a LO_SUM. */
1733 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1734 enum mips_symbol_type symbol_type)
1736 if (mips_split_p[symbol_type])
1738 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1739 addr = mips_force_temporary (temp, addr);
1740 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1746 /* Return a legitimate address for REG + OFFSET. This function will
1747 create a temporary register if OFFSET is not a SMALL_OPERAND. */
1750 mips_add_offset (rtx reg, HOST_WIDE_INT offset)
1752 if (!SMALL_OPERAND (offset))
1753 reg = expand_simple_binop (GET_MODE (reg), PLUS,
1754 GEN_INT (CONST_HIGH_PART (offset)),
1755 reg, NULL, 0, OPTAB_WIDEN);
1757 return plus_constant (reg, CONST_LOW_PART (offset));
1761 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1762 be legitimized in a way that the generic machinery might not expect,
1763 put the new address in *XLOC and return true. MODE is the mode of
1764 the memory being accessed. */
1767 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
1769 enum mips_symbol_type symbol_type;
1771 /* See if the address can split into a high part and a LO_SUM. */
1772 if (mips_symbolic_constant_p (*xloc, &symbol_type)
1773 && mips_symbolic_address_p (symbol_type, mode)
1774 && mips_split_p[symbol_type])
1776 *xloc = mips_split_symbol (0, *xloc);
1780 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1782 /* Handle REG + CONSTANT using mips_add_offset. */
1785 reg = XEXP (*xloc, 0);
1786 if (!mips_valid_base_register_p (reg, mode, 0))
1787 reg = copy_to_mode_reg (Pmode, reg);
1788 *xloc = mips_add_offset (reg, INTVAL (XEXP (*xloc, 1)));
1796 /* Subroutine of mips_build_integer (with the same interface).
1797 Assume that the final action in the sequence should be a left shift. */
1800 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1802 unsigned int i, shift;
1804 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1805 since signed numbers are easier to load than unsigned ones. */
1807 while ((value & 1) == 0)
1808 value /= 2, shift++;
1810 i = mips_build_integer (codes, value);
1811 codes[i].code = ASHIFT;
1812 codes[i].value = shift;
1817 /* As for mips_build_shift, but assume that the final action will be
1818 an IOR or PLUS operation. */
1821 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1823 unsigned HOST_WIDE_INT high;
1826 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1827 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1829 /* The constant is too complex to load with a simple lui/ori pair
1830 so our goal is to clear as many trailing zeros as possible.
1831 In this case, we know bit 16 is set and that the low 16 bits
1832 form a negative number. If we subtract that number from VALUE,
1833 we will clear at least the lowest 17 bits, maybe more. */
1834 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1835 codes[i].code = PLUS;
1836 codes[i].value = CONST_LOW_PART (value);
1840 i = mips_build_integer (codes, high);
1841 codes[i].code = IOR;
1842 codes[i].value = value & 0xffff;
1848 /* Fill CODES with a sequence of rtl operations to load VALUE.
1849 Return the number of operations needed. */
1852 mips_build_integer (struct mips_integer_op *codes,
1853 unsigned HOST_WIDE_INT value)
1855 if (SMALL_OPERAND (value)
1856 || SMALL_OPERAND_UNSIGNED (value)
1857 || LUI_OPERAND (value))
1859 /* The value can be loaded with a single instruction. */
1860 codes[0].code = NIL;
1861 codes[0].value = value;
1864 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1866 /* Either the constant is a simple LUI/ORI combination or its
1867 lowest bit is set. We don't want to shift in this case. */
1868 return mips_build_lower (codes, value);
1870 else if ((value & 0xffff) == 0)
1872 /* The constant will need at least three actions. The lowest
1873 16 bits are clear, so the final action will be a shift. */
1874 return mips_build_shift (codes, value);
1878 /* The final action could be a shift, add or inclusive OR.
1879 Rather than use a complex condition to select the best
1880 approach, try both mips_build_shift and mips_build_lower
1881 and pick the one that gives the shortest sequence.
1882 Note that this case is only used once per constant. */
1883 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1884 unsigned int cost, alt_cost;
1886 cost = mips_build_shift (codes, value);
1887 alt_cost = mips_build_lower (alt_codes, value);
1888 if (alt_cost < cost)
1890 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1898 /* Move VALUE into register DEST. */
1901 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
1903 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1904 enum machine_mode mode;
1905 unsigned int i, cost;
1908 mode = GET_MODE (dest);
1909 cost = mips_build_integer (codes, value);
1911 /* Apply each binary operation to X. Invariant: X is a legitimate
1912 source operand for a SET pattern. */
1913 x = GEN_INT (codes[0].value);
1914 for (i = 1; i < cost; i++)
1917 emit_move_insn (dest, x), x = dest;
1919 x = force_reg (mode, x);
1920 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
1923 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1927 /* Subroutine of mips_legitimize_move. Move constant SRC into register
1928 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1932 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
1935 HOST_WIDE_INT offset;
1936 enum mips_symbol_type symbol_type;
1938 /* Split moves of big integers into smaller pieces. In mips16 code,
1939 it's better to force the constant into memory instead. */
1940 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
1942 mips_move_integer (dest, INTVAL (src));
1946 /* See if the symbol can be split. For mips16, this is often worse than
1947 forcing it in the constant pool since it needs the single-register form
1948 of addiu or daddiu. */
1950 && mips_symbolic_constant_p (src, &symbol_type)
1951 && mips_split_p[symbol_type])
1953 emit_move_insn (dest, mips_split_symbol (dest, src));
1957 /* If we have (const (plus symbol offset)), load the symbol first
1958 and then add in the offset. This is usually better than forcing
1959 the constant into memory, at least in non-mips16 code. */
1960 mips_split_const (src, &base, &offset);
1963 && (!no_new_pseudos || SMALL_OPERAND (offset)))
1965 base = mips_force_temporary (dest, base);
1966 emit_move_insn (dest, mips_add_offset (base, offset));
1970 src = force_const_mem (mode, src);
1972 /* When using explicit relocs, constant pool references are sometimes
1973 not legitimate addresses. */
1974 if (!memory_operand (src, VOIDmode))
1975 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
1976 emit_move_insn (dest, src);
1980 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
1981 sequence that is valid. */
1984 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
1986 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1988 emit_move_insn (dest, force_reg (mode, src));
1992 /* We need to deal with constants that would be legitimate
1993 immediate_operands but not legitimate move_operands. */
1994 if (CONSTANT_P (src) && !move_operand (src, mode))
1996 mips_legitimize_const_move (mode, dest, src);
1997 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2003 /* We need a lot of little routines to check constant values on the
2004 mips16. These are used to figure out how long the instruction will
2005 be. It would be much better to do this using constraints, but
2006 there aren't nearly enough letters available. */
2009 m16_check_op (rtx op, int low, int high, int mask)
2011 return (GET_CODE (op) == CONST_INT
2012 && INTVAL (op) >= low
2013 && INTVAL (op) <= high
2014 && (INTVAL (op) & mask) == 0);
2018 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2020 return m16_check_op (op, 0x1, 0x8, 0);
2024 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2026 return m16_check_op (op, - 0x8, 0x7, 0);
2030 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2032 return m16_check_op (op, - 0x7, 0x8, 0);
2036 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2038 return m16_check_op (op, - 0x10, 0xf, 0);
2042 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2044 return m16_check_op (op, - 0xf, 0x10, 0);
2048 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2050 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2054 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2056 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2060 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2062 return m16_check_op (op, - 0x80, 0x7f, 0);
2066 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2068 return m16_check_op (op, - 0x7f, 0x80, 0);
2072 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2074 return m16_check_op (op, 0x0, 0xff, 0);
2078 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2080 return m16_check_op (op, - 0xff, 0x0, 0);
2084 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2086 return m16_check_op (op, - 0x1, 0xfe, 0);
2090 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2092 return m16_check_op (op, 0x0, 0xff << 2, 3);
2096 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2098 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2102 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2104 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2108 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2110 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2113 /* References to the string table on the mips16 only use a small
2114 offset if the function is small. We can't check for LABEL_REF here,
2115 because the offset is always large if the label is before the
2116 referencing instruction. */
2119 m16_usym8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2121 if (GET_CODE (op) == SYMBOL_REF
2122 && SYMBOL_REF_FLAG (op)
2123 && cfun->machine->insns_len > 0
2124 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2127 struct string_constant *l;
2129 /* Make sure this symbol is on thelist of string constants to be
2130 output for this function. It is possible that it has already
2131 been output, in which case this requires a large offset. */
2132 for (l = string_constants; l != NULL; l = l->next)
2133 if (strcmp (l->label, XSTR (op, 0)) == 0)
2141 m16_usym5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2143 if (GET_CODE (op) == SYMBOL_REF
2144 && SYMBOL_REF_FLAG (op)
2145 && cfun->machine->insns_len > 0
2146 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2149 struct string_constant *l;
2151 /* Make sure this symbol is on thelist of string constants to be
2152 output for this function. It is possible that it has already
2153 been output, in which case this requires a large offset. */
2154 for (l = string_constants; l != NULL; l = l->next)
2155 if (strcmp (l->label, XSTR (op, 0)) == 0)
2163 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2165 enum machine_mode mode = GET_MODE (x);
2172 /* Always return 0, since we don't have different sized
2173 instructions, hence different costs according to Richard
2179 /* A number between 1 and 8 inclusive is efficient for a shift.
2180 Otherwise, we will need an extended instruction. */
2181 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2182 || (outer_code) == LSHIFTRT)
2184 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2187 *total = COSTS_N_INSNS (1);
2191 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2192 if ((outer_code) == XOR
2193 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2199 /* We may be able to use slt or sltu for a comparison with a
2200 signed 16 bit value. (The boundary conditions aren't quite
2201 right, but this is just a heuristic anyhow.) */
2202 if (((outer_code) == LT || (outer_code) == LE
2203 || (outer_code) == GE || (outer_code) == GT
2204 || (outer_code) == LTU || (outer_code) == LEU
2205 || (outer_code) == GEU || (outer_code) == GTU)
2206 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2212 /* Equality comparisons with 0 are cheap. */
2213 if (((outer_code) == EQ || (outer_code) == NE)
2220 /* Otherwise fall through to the handling below. */
2226 if (LEGITIMATE_CONSTANT_P (x))
2228 *total = COSTS_N_INSNS (1);
2233 /* The value will need to be fetched from the constant pool. */
2234 *total = CONSTANT_POOL_COST;
2240 /* If the address is legitimate, return the number of
2241 instructions it needs, otherwise use the default handling. */
2242 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2245 *total = COSTS_N_INSNS (1 + n);
2252 *total = COSTS_N_INSNS (6);
2256 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2262 if (mode == DImode && !TARGET_64BIT)
2264 *total = COSTS_N_INSNS (2);
2272 if (mode == DImode && !TARGET_64BIT)
2274 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2281 if (mode == SFmode || mode == DFmode)
2282 *total = COSTS_N_INSNS (1);
2284 *total = COSTS_N_INSNS (4);
2288 *total = COSTS_N_INSNS (1);
2293 if (mode == SFmode || mode == DFmode)
2295 if (TUNE_MIPS3000 || TUNE_MIPS3900)
2296 *total = COSTS_N_INSNS (2);
2297 else if (TUNE_MIPS6000)
2298 *total = COSTS_N_INSNS (3);
2300 *total = COSTS_N_INSNS (6);
2303 if (mode == DImode && !TARGET_64BIT)
2305 *total = COSTS_N_INSNS (4);
2311 if (mode == DImode && !TARGET_64BIT)
2324 *total = COSTS_N_INSNS (4);
2325 else if (TUNE_MIPS6000
2328 *total = COSTS_N_INSNS (5);
2330 *total = COSTS_N_INSNS (7);
2339 *total = COSTS_N_INSNS (5);
2340 else if (TUNE_MIPS6000
2343 *total = COSTS_N_INSNS (6);
2345 *total = COSTS_N_INSNS (8);
2350 *total = COSTS_N_INSNS (12);
2351 else if (TUNE_MIPS3900)
2352 *total = COSTS_N_INSNS (2);
2353 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2354 *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
2355 else if (TUNE_MIPS7000)
2356 *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
2357 else if (TUNE_MIPS9000)
2358 *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
2359 else if (TUNE_MIPS6000)
2360 *total = COSTS_N_INSNS (17);
2361 else if (TUNE_MIPS5000)
2362 *total = COSTS_N_INSNS (5);
2364 *total = COSTS_N_INSNS (10);
2373 *total = COSTS_N_INSNS (12);
2374 else if (TUNE_MIPS6000)
2375 *total = COSTS_N_INSNS (15);
2376 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2377 *total = COSTS_N_INSNS (30);
2379 *total = COSTS_N_INSNS (23);
2387 *total = COSTS_N_INSNS (19);
2388 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2389 *total = COSTS_N_INSNS (59);
2390 else if (TUNE_MIPS6000)
2391 *total = COSTS_N_INSNS (16);
2393 *total = COSTS_N_INSNS (36);
2402 *total = COSTS_N_INSNS (35);
2403 else if (TUNE_MIPS6000)
2404 *total = COSTS_N_INSNS (38);
2405 else if (TUNE_MIPS5000)
2406 *total = COSTS_N_INSNS (36);
2407 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2408 *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
2410 *total = COSTS_N_INSNS (69);
2414 /* A sign extend from SImode to DImode in 64 bit mode is often
2415 zero instructions, because the result can often be used
2416 directly by another instruction; we'll call it one. */
2417 if (TARGET_64BIT && mode == DImode
2418 && GET_MODE (XEXP (x, 0)) == SImode)
2419 *total = COSTS_N_INSNS (1);
2421 *total = COSTS_N_INSNS (2);
2425 if (TARGET_64BIT && mode == DImode
2426 && GET_MODE (XEXP (x, 0)) == SImode)
2427 *total = COSTS_N_INSNS (2);
2429 *total = COSTS_N_INSNS (1);
2437 /* Provide the costs of an addressing mode that contains ADDR.
2438 If ADDR is not a valid address, its cost is irrelevant. */
2441 mips_address_cost (rtx addr)
2443 return mips_address_insns (addr, SImode);
2446 /* Return a pseudo that points to the address of the current function.
2447 The first time it is called for a function, an initializer for the
2448 pseudo is emitted in the beginning of the function. */
2451 embedded_pic_fnaddr_reg (void)
2453 if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
2457 cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
2459 /* Output code at function start to initialize the pseudo-reg. */
2460 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
2461 inline functions, because it is called after RTL for the function
2462 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
2463 does not get copied, and ends up not matching the rest of the RTL.
2464 This solution works, but means that we get unnecessary code to
2465 initialize this value every time a function is inlined into another
2468 emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
2469 XEXP (DECL_RTL (current_function_decl), 0)));
2472 push_topmost_sequence ();
2473 emit_insn_after (seq, get_insns ());
2474 pop_topmost_sequence ();
2477 return cfun->machine->embedded_pic_fnaddr_rtx;
2480 /* Return RTL for the offset from the current function to the argument.
2481 X is the symbol whose offset from the current function we want. */
2484 embedded_pic_offset (rtx x)
2486 /* Make sure it is emitted. */
2487 embedded_pic_fnaddr_reg ();
2490 gen_rtx_CONST (Pmode,
2491 gen_rtx_MINUS (Pmode, x,
2492 XEXP (DECL_RTL (current_function_decl), 0)));
2495 /* Return one word of double-word value OP, taking into account the fixed
2496 endianness of certain registers. HIGH_P is true to select the high part,
2497 false to select the low part. */
2500 mips_subword (rtx op, int high_p)
2503 enum machine_mode mode;
2505 mode = GET_MODE (op);
2506 if (mode == VOIDmode)
2509 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2510 byte = UNITS_PER_WORD;
2514 if (GET_CODE (op) == REG)
2516 if (FP_REG_P (REGNO (op)))
2517 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2518 if (REGNO (op) == HI_REGNUM)
2519 return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
2522 if (GET_CODE (op) == MEM)
2523 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2525 return simplify_gen_subreg (word_mode, op, mode, byte);
2529 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2532 mips_split_64bit_move_p (rtx dest, rtx src)
2537 /* FP->FP moves can be done in a single instruction. */
2538 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2541 /* Check for floating-point loads and stores. They can be done using
2542 ldc1 and sdc1 on MIPS II and above. */
2545 if (FP_REG_RTX_P (dest) && GET_CODE (src) == MEM)
2547 if (FP_REG_RTX_P (src) && GET_CODE (dest) == MEM)
2554 /* Split a 64-bit move from SRC to DEST assuming that
2555 mips_split_64bit_move_p holds.
2557 Moves into and out of FPRs cause some difficulty here. Such moves
2558 will always be DFmode, since paired FPRs are not allowed to store
2559 DImode values. The most natural representation would be two separate
2560 32-bit moves, such as:
2562 (set (reg:SI $f0) (mem:SI ...))
2563 (set (reg:SI $f1) (mem:SI ...))
2565 However, the second insn is invalid because odd-numbered FPRs are
2566 not allowed to store independent values. Use the patterns load_df_low,
2567 load_df_high and store_df_high instead. */
2570 mips_split_64bit_move (rtx dest, rtx src)
2572 if (FP_REG_RTX_P (dest))
2574 /* Loading an FPR from memory or from GPRs. */
2575 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2576 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2579 else if (FP_REG_RTX_P (src))
2581 /* Storing an FPR into memory or GPRs. */
2582 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2583 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2587 /* The operation can be split into two normal moves. Decide in
2588 which order to do them. */
2591 low_dest = mips_subword (dest, 0);
2592 if (GET_CODE (low_dest) == REG
2593 && reg_overlap_mentioned_p (low_dest, src))
2595 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2596 emit_move_insn (low_dest, mips_subword (src, 0));
2600 emit_move_insn (low_dest, mips_subword (src, 0));
2601 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2606 /* Return the appropriate instructions to move SRC into DEST. Assume
2607 that SRC is operand 1 and DEST is operand 0. */
2610 mips_output_move (rtx dest, rtx src)
2612 enum rtx_code dest_code, src_code;
2615 dest_code = GET_CODE (dest);
2616 src_code = GET_CODE (src);
2617 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2619 if (dbl_p && mips_split_64bit_move_p (dest, src))
2622 if ((src_code == REG && GP_REG_P (REGNO (src)))
2623 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2625 if (dest_code == REG)
2627 if (GP_REG_P (REGNO (dest)))
2628 return "move\t%0,%z1";
2630 if (MD_REG_P (REGNO (dest)))
2633 if (FP_REG_P (REGNO (dest)))
2634 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2636 if (ALL_COP_REG_P (REGNO (dest)))
2638 static char retval[] = "dmtc_\t%z1,%0";
2640 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2641 return (dbl_p ? retval : retval + 1);
2644 if (dest_code == MEM)
2645 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2647 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2649 if (src_code == REG)
2651 if (MD_REG_P (REGNO (src)))
2654 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2655 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2657 if (FP_REG_P (REGNO (src)))
2658 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2660 if (ALL_COP_REG_P (REGNO (src)))
2662 static char retval[] = "dmfc_\t%0,%1";
2664 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2665 return (dbl_p ? retval : retval + 1);
2669 if (src_code == MEM)
2670 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2672 if (src_code == CONST_INT)
2674 /* Don't use the X format, because that will give out of
2675 range numbers for 64 bit hosts and 32 bit targets. */
2677 return "li\t%0,%1\t\t\t# %X1";
2679 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2682 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2683 return "li\t%0,%n1\n\tneg\t%0";
2686 if (src_code == HIGH)
2687 return "lui\t%0,%h1";
2689 if (CONST_GP_P (src))
2690 return "move\t%0,%1";
2692 if (symbolic_operand (src, VOIDmode))
2693 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2695 if (src_code == REG && FP_REG_P (REGNO (src)))
2697 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2698 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2700 if (dest_code == MEM)
2701 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2703 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2705 if (src_code == MEM)
2706 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2708 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2710 static char retval[] = "l_c_\t%0,%1";
2712 retval[1] = (dbl_p ? 'd' : 'w');
2713 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2716 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2718 static char retval[] = "s_c_\t%1,%0";
2720 retval[1] = (dbl_p ? 'd' : 'w');
2721 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2727 /* Return an rtx for the gp save slot. Valid only when using o32 or
2731 mips_gp_save_slot (void)
2735 if (!TARGET_ABICALLS || TARGET_NEWABI)
2738 if (frame_pointer_needed)
2739 loc = hard_frame_pointer_rtx;
2741 loc = stack_pointer_rtx;
2742 loc = plus_constant (loc, current_function_outgoing_args_size);
2743 loc = gen_rtx_MEM (Pmode, loc);
2744 RTX_UNCHANGING_P (loc) = 1;
2748 /* Make normal rtx_code into something we can index from an array */
2750 static enum internal_test
2751 map_test_to_internal_test (enum rtx_code test_code)
2753 enum internal_test test = ITEST_MAX;
2757 case EQ: test = ITEST_EQ; break;
2758 case NE: test = ITEST_NE; break;
2759 case GT: test = ITEST_GT; break;
2760 case GE: test = ITEST_GE; break;
2761 case LT: test = ITEST_LT; break;
2762 case LE: test = ITEST_LE; break;
2763 case GTU: test = ITEST_GTU; break;
2764 case GEU: test = ITEST_GEU; break;
2765 case LTU: test = ITEST_LTU; break;
2766 case LEU: test = ITEST_LEU; break;
2774 /* Generate the code to compare two integer values. The return value is:
2775 (reg:SI xx) The pseudo register the comparison is in
2776 0 No register, generate a simple branch.
2778 ??? This is called with result nonzero by the Scond patterns in
2779 mips.md. These patterns are called with a target in the mode of
2780 the Scond instruction pattern. Since this must be a constant, we
2781 must use SImode. This means that if RESULT is nonzero, it will
2782 always be an SImode register, even if TARGET_64BIT is true. We
2783 cope with this by calling convert_move rather than emit_move_insn.
2784 This will sometimes lead to an unnecessary extension of the result;
2793 TEST_CODE is the rtx code for the comparison.
2794 CMP0 and CMP1 are the two operands to compare.
2795 RESULT is the register in which the result should be stored (null for
2797 For branches, P_INVERT points to an integer that is nonzero on return
2798 if the branch should be inverted. */
2801 gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0,
2802 rtx cmp1, int *p_invert)
2806 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2807 int const_low; /* low bound of constant we can accept */
2808 int const_high; /* high bound of constant we can accept */
2809 int const_add; /* constant to add (convert LE -> LT) */
2810 int reverse_regs; /* reverse registers in test */
2811 int invert_const; /* != 0 if invert value if cmp1 is constant */
2812 int invert_reg; /* != 0 if invert value if cmp1 is register */
2813 int unsignedp; /* != 0 for unsigned comparisons. */
2816 static const struct cmp_info info[ (int)ITEST_MAX ] = {
2818 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2819 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2820 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2821 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2822 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2823 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2824 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2825 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2826 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2827 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2830 enum internal_test test;
2831 enum machine_mode mode;
2832 const struct cmp_info *p_info;
2839 test = map_test_to_internal_test (test_code);
2840 if (test == ITEST_MAX)
2843 p_info = &info[(int) test];
2844 eqne_p = (p_info->test_code == XOR);
2846 mode = GET_MODE (cmp0);
2847 if (mode == VOIDmode)
2848 mode = GET_MODE (cmp1);
2850 /* Eliminate simple branches. */
2851 branch_p = (result == 0);
2854 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2856 /* Comparisons against zero are simple branches. */
2857 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2858 && (! TARGET_MIPS16 || eqne_p))
2861 /* Test for beq/bne. */
2862 if (eqne_p && ! TARGET_MIPS16)
2866 /* Allocate a pseudo to calculate the value in. */
2867 result = gen_reg_rtx (mode);
2870 /* Make sure we can handle any constants given to us. */
2871 if (GET_CODE (cmp0) == CONST_INT)
2872 cmp0 = force_reg (mode, cmp0);
2874 if (GET_CODE (cmp1) == CONST_INT)
2876 HOST_WIDE_INT value = INTVAL (cmp1);
2878 if (value < p_info->const_low
2879 || value > p_info->const_high
2880 /* ??? Why? And why wasn't the similar code below modified too? */
2882 && HOST_BITS_PER_WIDE_INT < 64
2883 && p_info->const_add != 0
2884 && ((p_info->unsignedp
2885 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2886 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2887 : (value + p_info->const_add) > INTVAL (cmp1))
2888 != (p_info->const_add > 0))))
2889 cmp1 = force_reg (mode, cmp1);
2892 /* See if we need to invert the result. */
2893 invert = (GET_CODE (cmp1) == CONST_INT
2894 ? p_info->invert_const : p_info->invert_reg);
2896 if (p_invert != (int *)0)
2902 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2903 Comparison between two registers, may involve switching operands. */
2904 if (GET_CODE (cmp1) == CONST_INT)
2906 if (p_info->const_add != 0)
2908 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2910 /* If modification of cmp1 caused overflow,
2911 we would get the wrong answer if we follow the usual path;
2912 thus, x > 0xffffffffU would turn into x > 0U. */
2913 if ((p_info->unsignedp
2914 ? (unsigned HOST_WIDE_INT) new >
2915 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2916 : new > INTVAL (cmp1))
2917 != (p_info->const_add > 0))
2919 /* This test is always true, but if INVERT is true then
2920 the result of the test needs to be inverted so 0 should
2921 be returned instead. */
2922 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2926 cmp1 = GEN_INT (new);
2930 else if (p_info->reverse_regs)
2937 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2941 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2942 convert_move (reg, gen_rtx_fmt_ee (p_info->test_code,
2943 mode, cmp0, cmp1), 0);
2946 if (test == ITEST_NE)
2948 if (! TARGET_MIPS16)
2950 convert_move (result, gen_rtx_GTU (mode, reg, const0_rtx), 0);
2951 if (p_invert != NULL)
2957 reg2 = invert ? gen_reg_rtx (mode) : result;
2958 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2963 else if (test == ITEST_EQ)
2965 reg2 = invert ? gen_reg_rtx (mode) : result;
2966 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2974 if (! TARGET_MIPS16)
2978 /* The value is in $24. Copy it to another register, so
2979 that reload doesn't think it needs to store the $24 and
2980 the input to the XOR in the same location. */
2981 reg2 = gen_reg_rtx (mode);
2982 emit_move_insn (reg2, reg);
2984 one = force_reg (mode, const1_rtx);
2986 convert_move (result, gen_rtx_XOR (mode, reg, one), 0);
2992 /* Work out how to check a floating-point condition. We need a
2993 separate comparison instruction (C.cond.fmt), followed by a
2994 branch or conditional move. Given that IN_CODE is the
2995 required condition, set *CMP_CODE to the C.cond.fmt code
2996 and *action_code to the branch or move code. */
2999 get_float_compare_codes (enum rtx_code in_code, enum rtx_code *cmp_code,
3000 enum rtx_code *action_code)
3009 *cmp_code = reverse_condition_maybe_unordered (in_code);
3014 *cmp_code = in_code;
3020 /* Emit the common code for doing conditional branches.
3021 operand[0] is the label to jump to.
3022 The comparison operands are saved away by cmp{si,di,sf,df}. */
3025 gen_conditional_branch (rtx *operands, enum rtx_code test_code)
3027 enum cmp_type type = branch_type;
3028 rtx cmp0 = branch_cmp[0];
3029 rtx cmp1 = branch_cmp[1];
3030 enum machine_mode mode;
3031 enum rtx_code cmp_code;
3040 mode = type == CMP_SI ? SImode : DImode;
3042 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3050 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3051 /* We don't want to build a comparison against a nonzero
3053 cmp1 = force_reg (mode, cmp1);
3060 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3062 reg = gen_reg_rtx (CCmode);
3064 get_float_compare_codes (test_code, &cmp_code, &test_code);
3065 emit_insn (gen_rtx_SET (VOIDmode, reg,
3066 gen_rtx_fmt_ee (cmp_code, CCmode, cmp0, cmp1)));
3075 fatal_insn ("bad test",
3076 gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
3079 /* Generate the branch. */
3081 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3091 (gen_rtx_SET (VOIDmode, pc_rtx,
3092 gen_rtx_IF_THEN_ELSE (VOIDmode,
3093 gen_rtx_fmt_ee (test_code, mode,
3098 /* Emit the common code for conditional moves. OPERANDS is the array
3099 of operands passed to the conditional move define_expand. */
3102 gen_conditional_move (rtx *operands)
3104 rtx op0 = branch_cmp[0];
3105 rtx op1 = branch_cmp[1];
3106 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3107 enum rtx_code cmp_code = GET_CODE (operands[1]);
3108 enum rtx_code move_code = NE;
3109 enum machine_mode op_mode = GET_MODE (operands[0]);
3110 enum machine_mode cmp_mode;
3113 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3132 op0 = force_reg (mode, branch_cmp[1]);
3133 op1 = branch_cmp[0];
3137 op0 = force_reg (mode, branch_cmp[1]);
3138 op1 = branch_cmp[0];
3149 op0 = force_reg (mode, branch_cmp[1]);
3150 op1 = branch_cmp[0];
3154 op0 = force_reg (mode, branch_cmp[1]);
3155 op1 = branch_cmp[0];
3163 get_float_compare_codes (cmp_code, &cmp_code, &move_code);
3165 if (mode == SImode || mode == DImode)
3167 else if (mode == SFmode || mode == DFmode)
3172 cmp_reg = gen_reg_rtx (cmp_mode);
3173 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3174 gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1)));
3176 emit_insn (gen_rtx_SET (op_mode, operands[0],
3177 gen_rtx_IF_THEN_ELSE (op_mode,
3178 gen_rtx_fmt_ee (move_code,
3182 operands[2], operands[3])));
3185 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3186 the conditional_trap expander. */
3189 mips_gen_conditional_trap (rtx *operands)
3192 enum rtx_code cmp_code = GET_CODE (operands[0]);
3193 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3195 /* MIPS conditional trap machine instructions don't have GT or LE
3196 flavors, so we must invert the comparison and convert to LT and
3197 GE, respectively. */
3200 case GT: cmp_code = LT; break;
3201 case LE: cmp_code = GE; break;
3202 case GTU: cmp_code = LTU; break;
3203 case LEU: cmp_code = GEU; break;
3206 if (cmp_code == GET_CODE (operands[0]))
3208 op0 = force_reg (mode, branch_cmp[0]);
3209 op1 = branch_cmp[1];
3213 op0 = force_reg (mode, branch_cmp[1]);
3214 op1 = branch_cmp[0];
3216 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3217 op1 = force_reg (mode, op1);
3219 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3220 gen_rtx_fmt_ee (cmp_code, GET_MODE (operands[0]),
3225 /* Load function address ADDR into register DEST. SIBCALL_P is true
3226 if the address is needed for a sibling call. */
3229 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3231 /* If we're generating PIC, and this call is to a global function,
3232 try to allow its address to be resolved lazily. This isn't
3233 possible for NewABI sibcalls since the value of $gp on entry
3234 to the stub would be our caller's gp, not ours. */
3235 if (TARGET_EXPLICIT_RELOCS
3236 && !(sibcall_p && TARGET_NEWABI)
3237 && global_got_operand (addr, VOIDmode))
3239 rtx high, lo_sum_symbol;
3241 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3242 addr, SYMBOL_GOTOFF_CALL);
3243 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3244 if (Pmode == SImode)
3245 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3247 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3250 emit_move_insn (dest, addr);
3254 /* Expand a call or call_value instruction. RESULT is where the
3255 result will go (null for calls), ADDR is the address of the
3256 function, ARGS_SIZE is the size of the arguments and AUX is
3257 the value passed to us by mips_function_arg. SIBCALL_P is true
3258 if we are expanding a sibling call, false if we're expanding
3262 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3264 rtx orig_addr, pattern, insn;
3267 if (!call_insn_operand (addr, VOIDmode))
3269 addr = gen_reg_rtx (Pmode);
3270 mips_load_call_address (addr, orig_addr, sibcall_p);
3274 && mips16_hard_float
3275 && build_mips16_call_stub (result, addr, args_size,
3276 aux == 0 ? 0 : (int) GET_MODE (aux)))
3280 pattern = (sibcall_p
3281 ? gen_sibcall_internal (addr, args_size)
3282 : gen_call_internal (addr, args_size));
3283 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3287 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3288 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3291 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3292 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3295 pattern = (sibcall_p
3296 ? gen_sibcall_value_internal (result, addr, args_size)
3297 : gen_call_value_internal (result, addr, args_size));
3299 insn = emit_call_insn (pattern);
3301 /* Lazy-binding stubs require $gp to be valid on entry. */
3302 if (global_got_operand (orig_addr, VOIDmode))
3303 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3307 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3310 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3311 tree exp ATTRIBUTE_UNUSED)
3313 return TARGET_SIBCALLS;
3316 /* Return true if operand OP is a condition code register.
3317 Only for use during or after reload. */
3320 fcc_register_operand (rtx op, enum machine_mode mode)
3322 return ((mode == VOIDmode || mode == GET_MODE (op))
3323 && (reload_in_progress || reload_completed)
3324 && (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
3325 && ST_REG_P (true_regnum (op)));
3328 /* Emit code to move general operand SRC into condition-code
3329 register DEST. SCRATCH is a scratch TFmode float register.
3336 where FP1 and FP2 are single-precision float registers
3337 taken from SCRATCH. */
3340 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3344 /* Change the source to SFmode. */
3345 if (GET_CODE (src) == MEM)
3346 src = adjust_address (src, SFmode, 0);
3347 else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
3348 src = gen_rtx_REG (SFmode, true_regnum (src));
3350 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3351 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3353 emit_move_insn (copy_rtx (fp1), src);
3354 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3355 emit_insn (gen_slt_sf (dest, fp2, fp1));
3358 /* Emit code to change the current function's return address to
3359 ADDRESS. SCRATCH is available as a scratch register, if needed.
3360 ADDRESS and SCRATCH are both word-mode GPRs. */
3363 mips_set_return_address (rtx address, rtx scratch)
3365 HOST_WIDE_INT gp_offset;
3367 compute_frame_size (get_frame_size ());
3368 if (((cfun->machine->frame.mask >> 31) & 1) == 0)
3370 gp_offset = cfun->machine->frame.gp_sp_offset;
3372 /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH. */
3373 if (gp_offset < 32768)
3374 scratch = plus_constant (stack_pointer_rtx, gp_offset);
3377 emit_move_insn (scratch, GEN_INT (gp_offset));
3378 if (Pmode == DImode)
3379 emit_insn (gen_adddi3 (scratch, scratch, stack_pointer_rtx));
3381 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
3384 emit_move_insn (gen_rtx_MEM (GET_MODE (address), scratch), address);
3387 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3388 Assume that the areas do not overlap. */
3391 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3393 HOST_WIDE_INT offset, delta;
3394 unsigned HOST_WIDE_INT bits;
3396 enum machine_mode mode;
3399 /* Work out how many bits to move at a time. If both operands have
3400 half-word alignment, it is usually better to move in half words.
3401 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3402 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3403 Otherwise move word-sized chunks. */
3404 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3405 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3406 bits = BITS_PER_WORD / 2;
3408 bits = BITS_PER_WORD;
3410 mode = mode_for_size (bits, MODE_INT, 0);
3411 delta = bits / BITS_PER_UNIT;
3413 /* Allocate a buffer for the temporary registers. */
3414 regs = alloca (sizeof (rtx) * length / delta);
3416 /* Load as many BITS-sized chunks as possible. Use a normal load if
3417 the source has enough alignment, otherwise use left/right pairs. */
3418 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3422 regs[i] = gen_reg_rtx (mode);
3423 part = adjust_address (src, mode, offset);
3424 if (MEM_ALIGN (part) >= bits)
3425 emit_move_insn (regs[i], part);
3426 else if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3430 /* Copy the chunks to the destination. */
3431 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3435 part = adjust_address (dest, mode, offset);
3436 if (MEM_ALIGN (part) >= bits)
3437 emit_move_insn (part, regs[i]);
3438 else if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3442 /* Mop up any left-over bytes. */
3443 if (offset < length)
3445 src = adjust_address (src, mode, offset);
3446 dest = adjust_address (dest, mode, offset);
3447 move_by_pieces (dest, src, length - offset,
3448 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3452 #define MAX_MOVE_REGS 4
3453 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3456 /* Helper function for doing a loop-based block operation on memory
3457 reference MEM. Each iteration of the loop will operate on LENGTH
3460 Create a new base register for use within the loop and point it to
3461 the start of MEM. Create a new memory reference that uses this
3462 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3465 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3466 rtx *loop_reg, rtx *loop_mem)
3468 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3470 /* Although the new mem does not refer to a known location,
3471 it does keep up to LENGTH bytes of alignment. */
3472 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3473 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3477 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3478 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3479 memory regions do not overlap. */
3482 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3484 rtx label, src_reg, dest_reg, final_src;
3485 HOST_WIDE_INT leftover;
3487 leftover = length % MAX_MOVE_BYTES;
3490 /* Create registers and memory references for use within the loop. */
3491 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3492 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3494 /* Calculate the value that SRC_REG should have after the last iteration
3496 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3499 /* Emit the start of the loop. */
3500 label = gen_label_rtx ();
3503 /* Emit the loop body. */
3504 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3506 /* Move on to the next block. */
3507 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3508 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3510 /* Emit the loop condition. */
3511 if (Pmode == DImode)
3512 emit_insn (gen_cmpdi (src_reg, final_src));
3514 emit_insn (gen_cmpsi (src_reg, final_src));
3515 emit_jump_insn (gen_bne (label));
3517 /* Mop up any left-over bytes. */
3519 mips_block_move_straight (dest, src, leftover);
3522 /* Expand a movstrsi instruction. */
3525 mips_expand_block_move (rtx dest, rtx src, rtx length)
3527 if (GET_CODE (length) == CONST_INT)
3529 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3531 mips_block_move_straight (dest, src, INTVAL (length));
3536 mips_block_move_loop (dest, src, INTVAL (length));
3543 /* Argument support functions. */
3545 /* Initialize CUMULATIVE_ARGS for a function. */
3548 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3549 rtx libname ATTRIBUTE_UNUSED)
3551 static CUMULATIVE_ARGS zero_cum;
3552 tree param, next_param;
3555 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3557 /* Determine if this function has variable arguments. This is
3558 indicated by the last argument being 'void_type_mode' if there
3559 are no variable arguments. The standard MIPS calling sequence
3560 passes all arguments in the general purpose registers in this case. */
3562 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3563 param != 0; param = next_param)
3565 next_param = TREE_CHAIN (param);
3566 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3567 cum->gp_reg_found = 1;
3572 /* Fill INFO with information about a single argument. CUM is the
3573 cumulative state for earlier arguments. MODE is the mode of this
3574 argument and TYPE is its type (if known). NAMED is true if this
3575 is a named (fixed) argument rather than a variable one. */
3578 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3579 tree type, int named, struct mips_arg_info *info)
3582 unsigned int num_words, max_regs;
3584 /* Decide whether this argument should go in a floating-point register,
3585 assuming one is free. Later code checks for availability. */
3587 info->fpr_p = (GET_MODE_CLASS (mode) == MODE_FLOAT
3588 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3595 info->fpr_p = (!cum->gp_reg_found
3596 && cum->arg_number < 2
3597 && (type == 0 || FLOAT_TYPE_P (type)));
3602 info->fpr_p = (named && (type == 0 || FLOAT_TYPE_P (type)));
3606 /* Now decide whether the argument must go in an even-numbered register. */
3611 /* Under the O64 ABI, the second float argument goes in $f13 if it
3612 is a double, but $f14 if it is a single. Otherwise, on a
3613 32-bit double-float machine, each FP argument must start in a
3614 new register pair. */
3615 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_HWFPVALUE
3616 || (mips_abi == ABI_O64 && mode == SFmode)
3619 else if (!TARGET_64BIT || LONG_DOUBLE_TYPE_SIZE == 128)
3621 if (GET_MODE_CLASS (mode) == MODE_INT
3622 || GET_MODE_CLASS (mode) == MODE_FLOAT)
3623 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
3625 else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
3629 if (mips_abi != ABI_EABI && MUST_PASS_IN_STACK (mode, type))
3630 /* This argument must be passed on the stack. Eat up all the
3631 remaining registers. */
3632 info->reg_offset = MAX_ARGS_IN_REGISTERS;
3635 /* Set REG_OFFSET to the register count we're interested in.
3636 The EABI allocates the floating-point registers separately,
3637 but the other ABIs allocate them like integer registers. */
3638 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3643 info->reg_offset += info->reg_offset & 1;
3646 /* The alignment applied to registers is also applied to stack arguments. */
3647 info->stack_offset = cum->stack_words;
3649 info->stack_offset += info->stack_offset & 1;
3651 if (mode == BLKmode)
3652 info->num_bytes = int_size_in_bytes (type);
3654 info->num_bytes = GET_MODE_SIZE (mode);
3656 num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3657 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3659 /* Partition the argument between registers and stack. */
3660 info->reg_words = MIN (num_words, max_regs);
3661 info->stack_words = num_words - info->reg_words;
3665 /* Implement FUNCTION_ARG_ADVANCE. */
3668 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3669 tree type, int named)
3671 struct mips_arg_info info;
3673 mips_arg_info (cum, mode, type, named, &info);
3676 cum->gp_reg_found = true;
3678 /* See the comment above the cumulative args structure in mips.h
3679 for an explanation of what this code does. It assumes the O32
3680 ABI, which passes at most 2 arguments in float registers. */
3681 if (cum->arg_number < 2 && info.fpr_p)
3682 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3684 if (mips_abi != ABI_EABI || !info.fpr_p)
3685 cum->num_gprs = info.reg_offset + info.reg_words;
3686 else if (info.reg_words > 0)
3687 cum->num_fprs += FP_INC;
3689 if (info.stack_words > 0)
3690 cum->stack_words = info.stack_offset + info.stack_words;
3695 /* Implement FUNCTION_ARG. */
3698 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3699 tree type, int named)
3701 struct mips_arg_info info;
3703 /* We will be called with a mode of VOIDmode after the last argument
3704 has been seen. Whatever we return will be passed to the call
3705 insn. If we need a mips16 fp_code, return a REG with the code
3706 stored as the mode. */
3707 if (mode == VOIDmode)
3709 if (TARGET_MIPS16 && cum->fp_code != 0)
3710 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3716 mips_arg_info (cum, mode, type, named, &info);
3718 /* Return straight away if the whole argument is passed on the stack. */
3719 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3723 && TREE_CODE (type) == RECORD_TYPE
3725 && TYPE_SIZE_UNIT (type)
3726 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3729 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3730 structure contains a double in its entirety, then that 64 bit
3731 chunk is passed in a floating point register. */
3734 /* First check to see if there is any such field. */
3735 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3736 if (TREE_CODE (field) == FIELD_DECL
3737 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3738 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3739 && host_integerp (bit_position (field), 0)
3740 && int_bit_position (field) % BITS_PER_WORD == 0)
3745 /* Now handle the special case by returning a PARALLEL
3746 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3747 chunks are passed in registers. */
3749 HOST_WIDE_INT bitpos;
3752 /* assign_parms checks the mode of ENTRY_PARM, so we must
3753 use the actual mode here. */
3754 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3757 field = TYPE_FIELDS (type);
3758 for (i = 0; i < info.reg_words; i++)
3762 for (; field; field = TREE_CHAIN (field))
3763 if (TREE_CODE (field) == FIELD_DECL
3764 && int_bit_position (field) >= bitpos)
3768 && int_bit_position (field) == bitpos
3769 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3770 && !TARGET_SOFT_FLOAT
3771 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3772 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3774 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3777 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3778 GEN_INT (bitpos / BITS_PER_UNIT));
3780 bitpos += BITS_PER_WORD;
3787 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3789 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3793 /* Implement FUNCTION_ARG_PARTIAL_NREGS. */
3796 function_arg_partial_nregs (const CUMULATIVE_ARGS *cum,
3797 enum machine_mode mode, tree type, int named)
3799 struct mips_arg_info info;
3801 mips_arg_info (cum, mode, type, named, &info);
3802 return info.stack_words > 0 ? info.reg_words : 0;
3806 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3807 upward rather than downward. In other words, return true if the
3808 first byte of the stack slot has useful data, false if the last
3812 mips_pad_arg_upward (enum machine_mode mode, tree type)
3814 /* On little-endian targets, the first byte of every stack argument
3815 is passed in the first byte of the stack slot. */
3816 if (!BYTES_BIG_ENDIAN)
3819 /* Otherwise, integral types are padded downward: the last byte of a
3820 stack argument is passed in the last byte of the stack slot. */
3822 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3823 : GET_MODE_CLASS (mode) == MODE_INT)
3826 /* Big-endian o64 pads floating-point arguments downward. */
3827 if (mips_abi == ABI_O64)
3828 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3831 /* Other types are padded upward for o32, o64, n32 and n64. */
3832 if (mips_abi != ABI_EABI)
3835 /* Arguments smaller than a stack slot are padded downward. */
3836 if (mode != BLKmode)
3837 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3839 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3843 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3844 if the least significant byte of the register has useful data. Return
3845 the opposite if the most significant byte does. */
3848 mips_pad_reg_upward (enum machine_mode mode, tree type)
3850 /* No shifting is required for floating-point arguments. */
3851 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3852 return !BYTES_BIG_ENDIAN;
3854 /* Otherwise, apply the same padding to register arguments as we do
3855 to stack arguments. */
3856 return mips_pad_arg_upward (mode, type);
3860 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3861 tree type, int *pretend_size, int no_rtl)
3863 CUMULATIVE_ARGS local_cum;
3864 int gp_saved, fp_saved;
3866 /* The caller has advanced CUM up to, but not beyond, the last named
3867 argument. Advance a local copy of CUM past the last "real" named
3868 argument, to find out how many registers are left over. */
3871 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3873 /* Found out how many registers we need to save. */
3874 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3875 fp_saved = (EABI_FLOAT_VARARGS_P
3876 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3885 ptr = virtual_incoming_args_rtx;
3890 ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
3894 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
3897 mem = gen_rtx_MEM (BLKmode, ptr);
3898 set_mem_alias_set (mem, get_varargs_alias_set ());
3900 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3905 /* We can't use move_block_from_reg, because it will use
3907 enum machine_mode mode;
3910 /* Set OFF to the offset from virtual_incoming_args_rtx of
3911 the first float register. The FP save area lies below
3912 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3913 off = -gp_saved * UNITS_PER_WORD;
3914 off &= ~(UNITS_PER_FPVALUE - 1);
3915 off -= fp_saved * UNITS_PER_FPREG;
3917 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3919 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3923 ptr = plus_constant (virtual_incoming_args_rtx, off);
3924 mem = gen_rtx_MEM (mode, ptr);
3925 set_mem_alias_set (mem, get_varargs_alias_set ());
3926 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3927 off += UNITS_PER_HWFPVALUE;
3933 /* No need for pretend arguments: the register parameter area was
3934 allocated by the caller. */
3938 *pretend_size = (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
3941 /* Create the va_list data type.
3942 We keep 3 pointers, and two offsets.
3943 Two pointers are to the overflow area, which starts at the CFA.
3944 One of these is constant, for addressing into the GPR save area below it.
3945 The other is advanced up the stack through the overflow region.
3946 The third pointer is to the GPR save area. Since the FPR save area
3947 is just below it, we can address FPR slots off this pointer.
3948 We also keep two one-byte offsets, which are to be subtracted from the
3949 constant pointers to yield addresses in the GPR and FPR save areas.
3950 These are downcounted as float or non-float arguments are used,
3951 and when they get to zero, the argument must be obtained from the
3953 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
3954 pointer is enough. It's started at the GPR save area, and is
3956 Note that the GPR save area is not constant size, due to optimization
3957 in the prologue. Hence, we can't use a design with two pointers
3958 and two offsets, although we could have designed this with two pointers
3959 and three offsets. */
3962 mips_build_builtin_va_list (void)
3964 if (EABI_FLOAT_VARARGS_P)
3966 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
3969 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3971 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
3973 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
3975 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
3977 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
3978 unsigned_char_type_node);
3979 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
3980 unsigned_char_type_node);
3981 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
3982 warn on every user file. */
3983 index = build_int_2 (GET_MODE_SIZE (ptr_mode) - 2 - 1, 0);
3984 array = build_array_type (unsigned_char_type_node,
3985 build_index_type (index));
3986 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
3988 DECL_FIELD_CONTEXT (f_ovfl) = record;
3989 DECL_FIELD_CONTEXT (f_gtop) = record;
3990 DECL_FIELD_CONTEXT (f_ftop) = record;
3991 DECL_FIELD_CONTEXT (f_goff) = record;
3992 DECL_FIELD_CONTEXT (f_foff) = record;
3993 DECL_FIELD_CONTEXT (f_res) = record;
3995 TYPE_FIELDS (record) = f_ovfl;
3996 TREE_CHAIN (f_ovfl) = f_gtop;
3997 TREE_CHAIN (f_gtop) = f_ftop;
3998 TREE_CHAIN (f_ftop) = f_goff;
3999 TREE_CHAIN (f_goff) = f_foff;
4000 TREE_CHAIN (f_foff) = f_res;
4002 layout_type (record);
4005 else if (TARGET_IRIX && !TARGET_IRIX5)
4006 /* On IRIX 6, this type is 'char *'. */
4007 return build_pointer_type (char_type_node);
4009 /* Otherwise, we use 'void *'. */
4010 return ptr_type_node;
4013 /* Implement va_start. */
4016 mips_va_start (tree valist, rtx nextarg)
4018 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
4020 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
4021 since the stack is aligned for a pair of argument-passing slots,
4022 and the beginning of a variable argument list may be an odd slot,
4023 we have to decrease its alignment. */
4024 if (cfun && cfun->emit->regno_pointer_align)
4025 while (((current_function_pretend_args_size * BITS_PER_UNIT)
4026 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
4027 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
4029 if (mips_abi == ABI_EABI)
4031 int gpr_save_area_size;
4034 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4036 if (EABI_FLOAT_VARARGS_P)
4038 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4039 tree ovfl, gtop, ftop, goff, foff;
4042 int fpr_save_area_size;
4044 f_ovfl = TYPE_FIELDS (va_list_type_node);
4045 f_gtop = TREE_CHAIN (f_ovfl);
4046 f_ftop = TREE_CHAIN (f_gtop);
4047 f_goff = TREE_CHAIN (f_ftop);
4048 f_foff = TREE_CHAIN (f_goff);
4050 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4051 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4052 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4053 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4054 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4056 /* Emit code to initialize OVFL, which points to the next varargs
4057 stack argument. CUM->STACK_WORDS gives the number of stack
4058 words used by named arguments. */
4059 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4060 if (cum->stack_words > 0)
4061 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4062 build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
4063 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4064 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4066 /* Emit code to initialize GTOP, the top of the GPR save area. */
4067 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4068 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4069 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4071 /* Emit code to initialize FTOP, the top of the FPR save area.
4072 This address is gpr_save_area_bytes below GTOP, rounded
4073 down to the next fp-aligned boundary. */
4074 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4075 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4076 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4078 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4079 build_int_2 (-fpr_offset, -1));
4080 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4081 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4083 /* Emit code to initialize GOFF, the offset from GTOP of the
4084 next GPR argument. */
4085 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4086 build_int_2 (gpr_save_area_size, 0));
4087 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4089 /* Likewise emit code to initialize FOFF, the offset from FTOP
4090 of the next FPR argument. */
4092 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4093 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4094 build_int_2 (fpr_save_area_size, 0));
4095 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4099 /* Everything is in the GPR save area, or in the overflow
4100 area which is contiguous with it. */
4101 nextarg = plus_constant (nextarg, -gpr_save_area_size);
4102 std_expand_builtin_va_start (valist, nextarg);
4106 std_expand_builtin_va_start (valist, nextarg);
4109 /* Implement va_arg. */
4112 mips_va_arg (tree valist, tree type)
4114 HOST_WIDE_INT size, rsize;
4118 size = int_size_in_bytes (type);
4119 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4121 if (mips_abi == ABI_EABI)
4127 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4131 size = POINTER_SIZE / BITS_PER_UNIT;
4132 rsize = UNITS_PER_WORD;
4135 addr_rtx = gen_reg_rtx (Pmode);
4137 if (!EABI_FLOAT_VARARGS_P)
4139 /* Case of all args in a merged stack. No need to check bounds,
4140 just advance valist along the stack. */
4145 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4147 /* Align the pointer using: ap = (ap + align - 1) & -align,
4148 where align is 2 * UNITS_PER_WORD. */
4149 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4150 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4151 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4152 build_int_2 (-2 * UNITS_PER_WORD, -1));
4153 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4154 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4157 /* Emit code to set addr_rtx to the valist, and postincrement
4158 the valist by the size of the argument, rounded up to the
4160 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4162 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4164 emit_move_insn (addr_rtx, r);
4166 /* Flush the POSTINCREMENT. */
4171 /* Not a simple merged stack. */
4173 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4174 tree ovfl, top, off;
4175 rtx lab_over = NULL_RTX, lab_false;
4176 HOST_WIDE_INT osize;
4178 f_ovfl = TYPE_FIELDS (va_list_type_node);
4179 f_gtop = TREE_CHAIN (f_ovfl);
4180 f_ftop = TREE_CHAIN (f_gtop);
4181 f_goff = TREE_CHAIN (f_ftop);
4182 f_foff = TREE_CHAIN (f_goff);
4184 /* We maintain separate pointers and offsets for floating-point
4185 and integer arguments, but we need similar code in both cases.
4188 TOP be the top of the register save area;
4189 OFF be the offset from TOP of the next register;
4190 ADDR_RTX be the address of the argument;
4191 RSIZE be the number of bytes used to store the argument
4192 when it's in the register save area;
4193 OSIZE be the number of bytes used to store it when it's
4194 in the stack overflow area; and
4195 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4197 The code we want is:
4199 1: off &= -rsize; // round down
4202 4: addr_rtx = top - off;
4207 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4208 10: addr_rtx = ovfl + PADDING;
4212 [1] and [9] can sometimes be optimized away. */
4214 lab_false = gen_label_rtx ();
4215 lab_over = gen_label_rtx ();
4217 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4218 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4219 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4221 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4222 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4224 /* When floating-point registers are saved to the stack,
4225 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4226 of the float's precision. */
4227 rsize = UNITS_PER_HWFPVALUE;
4231 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4232 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4233 if (rsize > UNITS_PER_WORD)
4235 /* [1] Emit code for: off &= -rsize. */
4236 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4237 build_int_2 (-rsize, -1));
4238 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4239 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4242 /* Every overflow argument must take up at least UNITS_PER_WORD
4243 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
4244 than that, such as in the combination -mgp64 -msingle-float
4245 -fshort-double. Doubles passed in registers will then take
4246 up UNITS_PER_HWFPVALUE bytes, but those passed on the stack
4247 take up UNITS_PER_WORD bytes. */
4248 osize = MAX (rsize, UNITS_PER_WORD);
4250 /* [2] Emit code to branch if off == 0. */
4251 r = expand_expr (off, NULL_RTX, TYPE_MODE (TREE_TYPE (off)),
4253 emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
4256 /* [4] Emit code for: addr_rtx = top - off. */
4257 t = build (MINUS_EXPR, TREE_TYPE (top), top, off);
4258 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4260 emit_move_insn (addr_rtx, r);
4262 /* [5] Emit code for: off -= rsize. */
4263 t = build (MINUS_EXPR, TREE_TYPE (off), off, build_int_2 (rsize, 0));
4264 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4265 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4267 /* [7] Emit code to jump over the else clause, then the label
4270 emit_jump (lab_over);
4272 emit_label (lab_false);
4274 if (osize > UNITS_PER_WORD)
4276 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4277 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl,
4278 build_int_2 (osize - 1, 0));
4279 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t,
4280 build_int_2 (-osize, -1));
4281 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4282 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4285 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4286 post-increment ovfl by osize. On big-endian machines,
4287 the argument has OSIZE - RSIZE bytes of leading padding. */
4288 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl,
4290 if (BYTES_BIG_ENDIAN && osize > rsize)
4291 t = build (PLUS_EXPR, TREE_TYPE (t), t,
4292 build_int_2 (osize - rsize, 0));
4293 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4295 emit_move_insn (addr_rtx, r);
4298 emit_label (lab_over);
4300 if (BYTES_BIG_ENDIAN && rsize != size)
4301 addr_rtx = plus_constant (addr_rtx, rsize - size);
4304 addr_rtx = force_reg (Pmode, addr_rtx);
4305 r = gen_rtx_MEM (Pmode, addr_rtx);
4306 set_mem_alias_set (r, get_varargs_alias_set ());
4307 emit_move_insn (addr_rtx, r);
4315 HOST_WIDE_INT min_offset;
4317 /* ??? The original va-mips.h did always align, despite the fact
4318 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4319 increment mechanism. */
4321 if (TARGET_NEWABI && TYPE_ALIGN (type) > 64)
4323 else if (TARGET_64BIT)
4325 else if (TYPE_ALIGN (type) > 32)
4330 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4331 build_int_2 (align - 1, 0));
4332 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4334 /* If arguments of type TYPE must be passed on the stack,
4335 set MIN_OFFSET to the offset of the first stack parameter. */
4336 if (!MUST_PASS_IN_STACK (TYPE_MODE (type), type))
4338 else if (TARGET_NEWABI)
4339 min_offset = current_function_pretend_args_size;
4341 min_offset = REG_PARM_STACK_SPACE (current_function_decl);
4343 /* Make sure the new address is at least MIN_OFFSET bytes from
4344 the incoming argument pointer. */
4346 t = build (MAX_EXPR, TREE_TYPE (valist), t,
4347 make_tree (TREE_TYPE (valist),
4348 plus_constant (virtual_incoming_args_rtx,
4351 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4352 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4354 /* Everything past the alignment is standard. */
4355 return std_expand_builtin_va_arg (valist, type);
4359 /* Return true if it is possible to use left/right accesses for a
4360 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4361 returning true, update *OP, *LEFT and *RIGHT as follows:
4363 *OP is a BLKmode reference to the whole field.
4365 *LEFT is a QImode reference to the first byte if big endian or
4366 the last byte if little endian. This address can be used in the
4367 left-side instructions (lwl, swl, ldl, sdl).
4369 *RIGHT is a QImode reference to the opposite end of the field and
4370 can be used in the parterning right-side instruction. */
4373 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4374 rtx *left, rtx *right)
4378 /* Check that the operand really is a MEM. Not all the extv and
4379 extzv predicates are checked. */
4380 if (GET_CODE (*op) != MEM)
4383 /* Check that the size is valid. */
4384 if (width != 32 && (!TARGET_64BIT || width != 64))
4387 /* We can only access byte-aligned values. Since we are always passed
4388 a reference to the first byte of the field, it is not necessary to
4389 do anything with BITPOS after this check. */
4390 if (bitpos % BITS_PER_UNIT != 0)
4393 /* Reject aligned bitfields: we want to use a normal load or store
4394 instead of a left/right pair. */
4395 if (MEM_ALIGN (*op) >= width)
4398 /* Adjust *OP to refer to the whole field. This also has the effect
4399 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4400 *op = adjust_address (*op, BLKmode, 0);
4401 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4403 /* Get references to both ends of the field. We deliberately don't
4404 use the original QImode *OP for FIRST since the new BLKmode one
4405 might have a simpler address. */
4406 first = adjust_address (*op, QImode, 0);
4407 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4409 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4410 be the upper word and RIGHT the lower word. */
4411 if (TARGET_BIG_ENDIAN)
4412 *left = first, *right = last;
4414 *left = last, *right = first;
4420 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4421 Return true on success. We only handle cases where zero_extract is
4422 equivalent to sign_extract. */
4425 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4429 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4430 paradoxical word_mode subreg. This is the only case in which
4431 we allow the destination to be larger than the source. */
4432 if (GET_CODE (dest) == SUBREG
4433 && GET_MODE (dest) == DImode
4434 && SUBREG_BYTE (dest) == 0
4435 && GET_MODE (SUBREG_REG (dest)) == SImode)
4436 dest = SUBREG_REG (dest);
4438 /* After the above adjustment, the destination must be the same
4439 width as the source. */
4440 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4443 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4446 if (GET_MODE (dest) == DImode)
4448 emit_insn (gen_mov_ldl (dest, src, left));
4449 emit_insn (gen_mov_ldr (copy_rtx (dest), copy_rtx (src),
4450 right, copy_rtx (dest)));
4454 emit_insn (gen_mov_lwl (dest, src, left));
4455 emit_insn (gen_mov_lwr (copy_rtx (dest), copy_rtx (src),
4456 right, copy_rtx (dest)));
4462 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4466 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4470 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4473 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4475 if (GET_MODE (src) == DImode)
4477 emit_insn (gen_mov_sdl (dest, src, left));
4478 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4482 emit_insn (gen_mov_swl (dest, src, left));
4483 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4488 /* Set up globals to generate code for the ISA or processor
4489 described by INFO. */
4492 mips_set_architecture (const struct mips_cpu_info *info)
4496 mips_arch_info = info;
4497 mips_arch = info->cpu;
4498 mips_isa = info->isa;
4503 /* Likewise for tuning. */
4506 mips_set_tune (const struct mips_cpu_info *info)
4510 mips_tune_info = info;
4511 mips_tune = info->cpu;
4516 /* Set up the threshold for data to go into the small data area, instead
4517 of the normal data area, and detect any conflicts in the switches. */
4520 override_options (void)
4522 int i, start, regno;
4523 enum machine_mode mode;
4525 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4527 /* Interpret -mabi. */
4528 mips_abi = MIPS_ABI_DEFAULT;
4529 if (mips_abi_string != 0)
4531 if (strcmp (mips_abi_string, "32") == 0)
4533 else if (strcmp (mips_abi_string, "o64") == 0)
4535 else if (strcmp (mips_abi_string, "n32") == 0)
4537 else if (strcmp (mips_abi_string, "64") == 0)
4539 else if (strcmp (mips_abi_string, "eabi") == 0)
4540 mips_abi = ABI_EABI;
4542 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
4545 /* The following code determines the architecture and register size.
4546 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4547 The GAS and GCC code should be kept in sync as much as possible. */
4549 if (mips_arch_string != 0)
4550 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
4552 if (mips_isa_string != 0)
4554 /* Handle -mipsN. */
4555 char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
4556 const struct mips_cpu_info *isa_info;
4558 isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
4559 free (whole_isa_str);
4561 /* -march takes precedence over -mipsN, since it is more descriptive.
4562 There's no harm in specifying both as long as the ISA levels
4564 if (mips_arch_info != 0 && mips_isa != isa_info->isa)
4565 error ("-mips%s conflicts with the other architecture options, "
4566 "which specify a MIPS%d processor",
4567 mips_isa_string, mips_isa);
4569 /* Set architecture based on the given option. */
4570 mips_set_architecture (isa_info);
4573 if (mips_arch_info == 0)
4575 #ifdef MIPS_CPU_STRING_DEFAULT
4576 mips_set_architecture (mips_parse_cpu ("default CPU",
4577 MIPS_CPU_STRING_DEFAULT));
4579 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4583 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4584 error ("-march=%s is not compatible with the selected ABI",
4585 mips_arch_info->name);
4587 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4588 if (mips_tune_string != 0)
4589 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
4591 if (mips_tune_info == 0)
4592 mips_set_tune (mips_arch_info);
4594 if ((target_flags_explicit & MASK_64BIT) != 0)
4596 /* The user specified the size of the integer registers. Make sure
4597 it agrees with the ABI and ISA. */
4598 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4599 error ("-mgp64 used with a 32-bit processor");
4600 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4601 error ("-mgp32 used with a 64-bit ABI");
4602 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4603 error ("-mgp64 used with a 32-bit ABI");
4607 /* Infer the integer register size from the ABI and processor.
4608 Restrict ourselves to 32-bit registers if that's all the
4609 processor has, or if the ABI cannot handle 64-bit registers. */
4610 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4611 target_flags &= ~MASK_64BIT;
4613 target_flags |= MASK_64BIT;
4616 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4618 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4619 only one right answer here. */
4620 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4621 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4622 else if (!TARGET_64BIT && TARGET_FLOAT64)
4623 error ("unsupported combination: %s", "-mgp32 -mfp64");
4624 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4625 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4629 /* -msingle-float selects 32-bit float registers. Otherwise the
4630 float registers should be the same size as the integer ones. */
4631 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4632 target_flags |= MASK_FLOAT64;
4634 target_flags &= ~MASK_FLOAT64;
4637 /* End of code shared with GAS. */
4639 if ((target_flags_explicit & MASK_LONG64) == 0)
4641 /* If no type size setting options (-mlong64,-mint64,-mlong32)
4642 were used, then set the type sizes. In the EABI in 64 bit mode,
4643 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
4645 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4646 target_flags |= MASK_LONG64;
4648 target_flags &= ~MASK_LONG64;
4651 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4652 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4654 /* For some configurations, it is useful to have -march control
4655 the default setting of MASK_SOFT_FLOAT. */
4656 switch ((int) mips_arch)
4658 case PROCESSOR_R4100:
4659 case PROCESSOR_R4111:
4660 case PROCESSOR_R4120:
4661 case PROCESSOR_R4130:
4662 target_flags |= MASK_SOFT_FLOAT;
4666 target_flags &= ~MASK_SOFT_FLOAT;
4672 flag_pcc_struct_return = 0;
4674 #if defined(USE_COLLECT2)
4675 /* For IRIX 5 or IRIX 6 with integrated O32 ABI support, USE_COLLECT2 is
4676 always defined when GNU as is not in use, but collect2 is only used
4677 for the O32 ABI, so override the toplev.c and target-def.h defaults
4678 for flag_gnu_linker, TARGET_ASM_{CONSTRUCTOR, DESTRUCTOR} and
4679 TARGET_HAVE_CTORS_DTORS.
4681 Since the IRIX 5 and IRIX 6 O32 assemblers cannot handle named
4682 sections, constructor/destructor handling depends on the ABI in use.
4684 Since USE_COLLECT2 is defined, we only need to restore the non-collect2
4685 defaults for the N32/N64 ABIs. */
4686 if (TARGET_IRIX && !TARGET_SGI_O32_AS)
4688 targetm.have_ctors_dtors = true;
4689 targetm.asm_out.constructor = default_named_section_asm_out_constructor;
4690 targetm.asm_out.destructor = default_named_section_asm_out_destructor;
4694 /* Handle some quirks of the IRIX 5 and IRIX 6 O32 assemblers. */
4696 if (TARGET_SGI_O32_AS)
4698 /* They don't recognize `.[248]byte'. */
4699 targetm.asm_out.unaligned_op.hi = "\t.align 0\n\t.half\t";
4700 targetm.asm_out.unaligned_op.si = "\t.align 0\n\t.word\t";
4701 /* The IRIX 6 O32 assembler gives an error for `align 0; .dword',
4702 contrary to the documentation, so disable it. */
4703 targetm.asm_out.unaligned_op.di = NULL;
4705 /* They cannot handle named sections. */
4706 targetm.have_named_sections = false;
4707 /* Therefore, EH_FRAME_SECTION_NAME isn't defined and we must use
4709 targetm.terminate_dw2_eh_frame_info = true;
4710 targetm.asm_out.eh_frame_section = collect2_eh_frame_section;
4712 /* They cannot handle debug information. */
4713 if (write_symbols != NO_DEBUG)
4715 /* Adapt wording to IRIX version: IRIX 5 only had a single ABI,
4716 so -mabi=32 isn't usually specified. */
4718 inform ("-g is only supported using GNU as,");
4720 inform ("-g is only supported using GNU as with -mabi=32,");
4721 inform ("-g option disabled");
4722 write_symbols = NO_DEBUG;
4726 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4728 /* If neither -mbranch-likely nor -mno-branch-likely was given
4729 on the command line, set MASK_BRANCHLIKELY based on the target
4732 By default, we enable use of Branch Likely instructions on
4733 all architectures which support them except for MIPS32 and MIPS64
4734 (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
4737 The MIPS32 and MIPS64 architecture specifications say "Software
4738 is strongly encouraged to avoid use of Branch Likely
4739 instructions, as they will be removed from a future revision
4740 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4741 issue those instructions unless instructed to do so by
4743 if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64))
4744 target_flags |= MASK_BRANCHLIKELY;
4746 target_flags &= ~MASK_BRANCHLIKELY;
4748 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4749 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
4751 /* The effect of -mabicalls isn't defined for the EABI. */
4752 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4754 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4755 target_flags &= ~MASK_ABICALLS;
4758 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4759 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4760 /* ??? -non_shared turns off pic code generation, but this is not
4762 if (TARGET_ABICALLS)
4765 if (mips_section_threshold > 0)
4766 warning ("-G is incompatible with PIC code which is the default");
4769 /* The MIPS and SGI o32 assemblers expect small-data variables to
4770 be declared before they are used. Although we once had code to
4771 do this, it was very invasive and fragile. It no longer seems
4772 worth the effort. */
4773 if (!TARGET_EXPLICIT_RELOCS && !TARGET_GAS)
4774 mips_section_threshold = 0;
4776 /* We switch to small data sections using ".section", which the native
4777 o32 irix assemblers don't understand. Disable -G accordingly.
4778 We must do this regardless of command-line options since otherwise
4779 the compiler would abort. */
4780 if (!targetm.have_named_sections)
4781 mips_section_threshold = 0;
4783 /* -membedded-pic is a form of PIC code suitable for embedded
4784 systems. All calls are made using PC relative addressing, and
4785 all data is addressed using the $gp register. This requires gas,
4786 which does most of the work, and GNU ld, which automatically
4787 expands PC relative calls which are out of range into a longer
4788 instruction sequence. All gcc really does differently is
4789 generate a different sequence for a switch. */
4790 if (TARGET_EMBEDDED_PIC)
4793 if (TARGET_ABICALLS)
4794 warning ("-membedded-pic and -mabicalls are incompatible");
4797 warning ("-G and -membedded-pic are incompatible");
4799 /* Setting mips_section_threshold is not required, because gas
4800 will force everything to be GP addressable anyhow, but
4801 setting it will cause gcc to make better estimates of the
4802 number of instructions required to access a particular data
4804 mips_section_threshold = 0x7fffffff;
4807 /* mips_split_addresses is a half-way house between explicit
4808 relocations and the traditional assembler macros. It can
4809 split absolute 32-bit symbolic constants into a high/lo_sum
4810 pair but uses macros for other sorts of access.
4812 Like explicit relocation support for REL targets, it relies
4813 on GNU extensions in the assembler and the linker.
4815 Although this code should work for -O0, it has traditionally
4816 been treated as an optimization. */
4817 if (TARGET_GAS && !TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4818 && optimize && !flag_pic
4819 && !ABI_HAS_64BIT_SYMBOLS)
4820 mips_split_addresses = 1;
4822 mips_split_addresses = 0;
4824 /* Explicit relocations for "old" ABIs are a GNU extension. Unless
4825 the user has said otherwise, assume that they are not available
4826 with assemblers other than gas. */
4827 if (!TARGET_NEWABI && !TARGET_GAS
4828 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4829 target_flags &= ~MASK_EXPLICIT_RELOCS;
4831 /* Make -mabicalls -fno-unit-at-a-time imply -mno-explicit-relocs
4832 unless the user says otherwise.
4834 There are two problems here:
4836 (1) The value of an R_MIPS_GOT16 relocation depends on whether
4837 the symbol is local or global. We therefore need to know
4838 a symbol's binding before refering to it using %got().
4840 (2) R_MIPS_CALL16 can only be applied to global symbols.
4842 When not using -funit-at-a-time, a symbol's binding may change
4843 after it has been used. For example, the C++ front-end will
4844 initially assume that the typeinfo for an incomplete type will be
4845 comdat, on the basis that the type could be completed later in the
4846 file. But if the type never is completed, the typeinfo will become
4848 if (!flag_unit_at_a_time
4850 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4851 target_flags &= ~MASK_EXPLICIT_RELOCS;
4853 /* -mrnames says to use the MIPS software convention for register
4854 names instead of the hardware names (ie, $a0 instead of $4).
4855 We do this by switching the names in mips_reg_names, which the
4856 reg_names points into via the REGISTER_NAMES macro. */
4858 if (TARGET_NAME_REGS)
4859 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
4861 /* When compiling for the mips16, we can not use floating point. We
4862 record the original hard float value in mips16_hard_float. */
4865 if (TARGET_SOFT_FLOAT)
4866 mips16_hard_float = 0;
4868 mips16_hard_float = 1;
4869 target_flags |= MASK_SOFT_FLOAT;
4871 /* Don't run the scheduler before reload, since it tends to
4872 increase register pressure. */
4873 flag_schedule_insns = 0;
4875 /* Silently disable -mexplicit-relocs since it doesn't apply
4876 to mips16 code. Even so, it would overly pedantic to warn
4877 about "-mips16 -mexplicit-relocs", especially given that
4878 we use a %gprel() operator. */
4879 target_flags &= ~MASK_EXPLICIT_RELOCS;
4882 /* When using explicit relocs, we call dbr_schedule from within
4884 if (TARGET_EXPLICIT_RELOCS)
4886 mips_flag_delayed_branch = flag_delayed_branch;
4887 flag_delayed_branch = 0;
4890 #ifdef MIPS_TFMODE_FORMAT
4891 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4894 mips_print_operand_punct['?'] = 1;
4895 mips_print_operand_punct['#'] = 1;
4896 mips_print_operand_punct['/'] = 1;
4897 mips_print_operand_punct['&'] = 1;
4898 mips_print_operand_punct['!'] = 1;
4899 mips_print_operand_punct['*'] = 1;
4900 mips_print_operand_punct['@'] = 1;
4901 mips_print_operand_punct['.'] = 1;
4902 mips_print_operand_punct['('] = 1;
4903 mips_print_operand_punct[')'] = 1;
4904 mips_print_operand_punct['['] = 1;
4905 mips_print_operand_punct[']'] = 1;
4906 mips_print_operand_punct['<'] = 1;
4907 mips_print_operand_punct['>'] = 1;
4908 mips_print_operand_punct['{'] = 1;
4909 mips_print_operand_punct['}'] = 1;
4910 mips_print_operand_punct['^'] = 1;
4911 mips_print_operand_punct['$'] = 1;
4912 mips_print_operand_punct['+'] = 1;
4913 mips_print_operand_punct['~'] = 1;
4915 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4916 mips_char_to_class['t'] = T_REG;
4917 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4918 mips_char_to_class['h'] = HI_REG;
4919 mips_char_to_class['l'] = LO_REG;
4920 mips_char_to_class['x'] = MD_REGS;
4921 mips_char_to_class['b'] = ALL_REGS;
4922 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4923 TARGET_MIPS16 ? M16_NA_REGS :
4925 mips_char_to_class['e'] = LEA_REGS;
4926 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4927 mips_char_to_class['y'] = GR_REGS;
4928 mips_char_to_class['z'] = ST_REGS;
4929 mips_char_to_class['B'] = COP0_REGS;
4930 mips_char_to_class['C'] = COP2_REGS;
4931 mips_char_to_class['D'] = COP3_REGS;
4933 /* Set up array to map GCC register number to debug register number.
4934 Ignore the special purpose register numbers. */
4936 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4937 mips_dbx_regno[i] = -1;
4939 start = GP_DBX_FIRST - GP_REG_FIRST;
4940 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4941 mips_dbx_regno[i] = i + start;
4943 start = FP_DBX_FIRST - FP_REG_FIRST;
4944 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4945 mips_dbx_regno[i] = i + start;
4947 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4948 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4950 /* Set up array giving whether a given register can hold a given mode. */
4952 for (mode = VOIDmode;
4953 mode != MAX_MACHINE_MODE;
4954 mode = (enum machine_mode) ((int)mode + 1))
4956 register int size = GET_MODE_SIZE (mode);
4957 register enum mode_class class = GET_MODE_CLASS (mode);
4959 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4966 temp = (regno == FPSW_REGNUM);
4968 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4969 || FP_REG_P (regno));
4972 else if (GP_REG_P (regno))
4973 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4975 else if (FP_REG_P (regno))
4976 temp = ((regno % FP_INC) == 0)
4977 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
4978 && size <= UNITS_PER_FPVALUE)
4979 /* Allow integer modes that fit into a single
4980 register. We need to put integers into FPRs
4981 when using instructions like cvt and trunc. */
4982 || (class == MODE_INT && size <= UNITS_PER_FPREG)
4983 /* Allow TFmode for CCmode reloads. */
4984 || (ISA_HAS_8CC && mode == TFmode));
4986 else if (MD_REG_P (regno))
4987 temp = (class == MODE_INT
4988 && (size <= UNITS_PER_WORD
4989 || (regno == MD_REG_FIRST
4990 && size == 2 * UNITS_PER_WORD)));
4992 else if (ALL_COP_REG_P (regno))
4993 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
4997 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5001 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5002 initialized yet, so we can't use that here. */
5003 gpr_mode = TARGET_64BIT ? DImode : SImode;
5005 /* Provide default values for align_* for 64-bit targets. */
5006 if (TARGET_64BIT && !TARGET_MIPS16)
5008 if (align_loops == 0)
5010 if (align_jumps == 0)
5012 if (align_functions == 0)
5013 align_functions = 8;
5016 /* Function to allocate machine-dependent function status. */
5017 init_machine_status = &mips_init_machine_status;
5019 if (ABI_HAS_64BIT_SYMBOLS)
5021 if (TARGET_EXPLICIT_RELOCS)
5023 mips_split_p[SYMBOL_64_HIGH] = true;
5024 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5025 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5027 mips_split_p[SYMBOL_64_MID] = true;
5028 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5029 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5031 mips_split_p[SYMBOL_64_LOW] = true;
5032 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5033 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5035 mips_split_p[SYMBOL_GENERAL] = true;
5036 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5041 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5043 mips_split_p[SYMBOL_GENERAL] = true;
5044 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5045 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5051 /* The high part is provided by a pseudo copy of $gp. */
5052 mips_split_p[SYMBOL_SMALL_DATA] = true;
5053 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5056 if (TARGET_EXPLICIT_RELOCS)
5058 /* Small data constants are kept whole until after reload,
5059 then lowered by mips_rewrite_small_data. */
5060 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5062 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5065 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5066 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5070 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5071 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5076 /* The HIGH and LO_SUM are matched by special .md patterns. */
5077 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5079 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5080 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5081 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5083 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5084 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5085 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5090 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5092 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5093 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5099 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5100 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5101 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5104 /* Default to working around R4000 errata only if the processor
5105 was selected explicitly. */
5106 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5107 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5108 target_flags |= MASK_FIX_R4000;
5110 /* Default to working around R4400 errata only if the processor
5111 was selected explicitly. */
5112 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5113 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5114 target_flags |= MASK_FIX_R4400;
5117 /* Implement CONDITIONAL_REGISTER_USAGE. */
5120 mips_conditional_register_usage (void)
5122 if (!TARGET_HARD_FLOAT)
5126 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5127 fixed_regs[regno] = call_used_regs[regno] = 1;
5128 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5129 fixed_regs[regno] = call_used_regs[regno] = 1;
5131 else if (! ISA_HAS_8CC)
5135 /* We only have a single condition code register. We
5136 implement this by hiding all the condition code registers,
5137 and generating RTL that refers directly to ST_REG_FIRST. */
5138 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5139 fixed_regs[regno] = call_used_regs[regno] = 1;
5141 /* In mips16 mode, we permit the $t temporary registers to be used
5142 for reload. We prohibit the unused $s registers, since they
5143 are caller saved, and saving them via a mips16 register would
5144 probably waste more time than just reloading the value. */
5147 fixed_regs[18] = call_used_regs[18] = 1;
5148 fixed_regs[19] = call_used_regs[19] = 1;
5149 fixed_regs[20] = call_used_regs[20] = 1;
5150 fixed_regs[21] = call_used_regs[21] = 1;
5151 fixed_regs[22] = call_used_regs[22] = 1;
5152 fixed_regs[23] = call_used_regs[23] = 1;
5153 fixed_regs[26] = call_used_regs[26] = 1;
5154 fixed_regs[27] = call_used_regs[27] = 1;
5155 fixed_regs[30] = call_used_regs[30] = 1;
5157 /* fp20-23 are now caller saved. */
5158 if (mips_abi == ABI_64)
5161 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5162 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5164 /* Odd registers from fp21 to fp31 are now caller saved. */
5165 if (mips_abi == ABI_N32)
5168 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5169 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5173 /* Allocate a chunk of memory for per-function machine-dependent data. */
5174 static struct machine_function *
5175 mips_init_machine_status (void)
5177 return ((struct machine_function *)
5178 ggc_alloc_cleared (sizeof (struct machine_function)));
5181 /* On the mips16, we want to allocate $24 (T_REG) before other
5182 registers for instructions for which it is possible. This helps
5183 avoid shuffling registers around in order to set up for an xor,
5184 encouraging the compiler to use a cmp instead. */
5187 mips_order_regs_for_local_alloc (void)
5191 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5192 reg_alloc_order[i] = i;
5196 /* It really doesn't matter where we put register 0, since it is
5197 a fixed register anyhow. */
5198 reg_alloc_order[0] = 24;
5199 reg_alloc_order[24] = 0;
5204 /* The MIPS debug format wants all automatic variables and arguments
5205 to be in terms of the virtual frame pointer (stack pointer before
5206 any adjustment in the function), while the MIPS 3.0 linker wants
5207 the frame pointer to be the stack pointer after the initial
5208 adjustment. So, we do the adjustment here. The arg pointer (which
5209 is eliminated) points to the virtual frame pointer, while the frame
5210 pointer (which may be eliminated) points to the stack pointer after
5211 the initial adjustments. */
5214 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5216 rtx offset2 = const0_rtx;
5217 rtx reg = eliminate_constant_term (addr, &offset2);
5220 offset = INTVAL (offset2);
5222 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5223 || reg == hard_frame_pointer_rtx)
5225 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5226 ? compute_frame_size (get_frame_size ())
5227 : cfun->machine->frame.total_size;
5229 /* MIPS16 frame is smaller */
5230 if (frame_pointer_needed && TARGET_MIPS16)
5231 frame_size -= cfun->machine->frame.args_size;
5233 offset = offset - frame_size;
5236 /* sdbout_parms does not want this to crash for unrecognized cases. */
5238 else if (reg != arg_pointer_rtx)
5239 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5246 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5248 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5249 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5250 'h' OP is HIGH, prints %hi(X),
5251 'd' output integer constant in decimal,
5252 'z' if the operand is 0, use $0 instead of normal operand.
5253 'D' print second part of double-word register or memory operand.
5254 'L' print low-order register of double-word register operand.
5255 'M' print high-order register of double-word register operand.
5256 'C' print part of opcode for a branch condition.
5257 'F' print part of opcode for a floating-point branch condition.
5258 'N' print part of opcode for a branch condition, inverted.
5259 'W' print part of opcode for a floating-point branch condition, inverted.
5260 'S' OP is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5261 'B' print 'z' for EQ, 'n' for NE
5262 'b' print 'n' for EQ, 'z' for NE
5263 'T' print 'f' for EQ, 't' for NE
5264 't' print 't' for EQ, 'f' for NE
5265 'Z' print register and a comma, but print nothing for $fcc0
5266 'R' print the reloc associated with LO_SUM
5268 The punctuation characters are:
5270 '(' Turn on .set noreorder
5271 ')' Turn on .set reorder
5272 '[' Turn on .set noat
5274 '<' Turn on .set nomacro
5275 '>' Turn on .set macro
5276 '{' Turn on .set volatile (not GAS)
5277 '}' Turn on .set novolatile (not GAS)
5278 '&' Turn on .set noreorder if filling delay slots
5279 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5280 '!' Turn on .set nomacro if filling delay slots
5281 '#' Print nop if in a .set noreorder section.
5282 '/' Like '#', but does nothing within a delayed branch sequence
5283 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5284 '@' Print the name of the assembler temporary register (at or $1).
5285 '.' Print the name of the register with a hard-wired zero (zero or $0).
5286 '^' Print the name of the pic call-through register (t9 or $25).
5287 '$' Print the name of the stack pointer register (sp or $29).
5288 '+' Print the name of the gp register (usually gp or $28).
5289 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5292 print_operand (FILE *file, rtx op, int letter)
5294 register enum rtx_code code;
5296 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5301 if (mips_branch_likely)
5306 fputs (reg_names [GP_REG_FIRST + 1], file);
5310 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5314 fputs (reg_names [GP_REG_FIRST + 0], file);
5318 fputs (reg_names[STACK_POINTER_REGNUM], file);
5322 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5326 if (final_sequence != 0 && set_noreorder++ == 0)
5327 fputs (".set\tnoreorder\n\t", file);
5331 if (final_sequence != 0)
5333 if (set_noreorder++ == 0)
5334 fputs (".set\tnoreorder\n\t", file);
5336 if (set_nomacro++ == 0)
5337 fputs (".set\tnomacro\n\t", file);
5342 if (final_sequence != 0 && set_nomacro++ == 0)
5343 fputs ("\n\t.set\tnomacro", file);
5347 if (set_noreorder != 0)
5348 fputs ("\n\tnop", file);
5352 /* Print an extra newline so that the delayed insn is separated
5353 from the following ones. This looks neater and is consistent
5354 with non-nop delayed sequences. */
5355 if (set_noreorder != 0 && final_sequence == 0)
5356 fputs ("\n\tnop\n", file);
5360 if (set_noreorder++ == 0)
5361 fputs (".set\tnoreorder\n\t", file);
5365 if (set_noreorder == 0)
5366 error ("internal error: %%) found without a %%( in assembler pattern");
5368 else if (--set_noreorder == 0)
5369 fputs ("\n\t.set\treorder", file);
5374 if (set_noat++ == 0)
5375 fputs (".set\tnoat\n\t", file);
5380 error ("internal error: %%] found without a %%[ in assembler pattern");
5381 else if (--set_noat == 0)
5382 fputs ("\n\t.set\tat", file);
5387 if (set_nomacro++ == 0)
5388 fputs (".set\tnomacro\n\t", file);
5392 if (set_nomacro == 0)
5393 error ("internal error: %%> found without a %%< in assembler pattern");
5394 else if (--set_nomacro == 0)
5395 fputs ("\n\t.set\tmacro", file);
5400 if (set_volatile++ == 0)
5401 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5405 if (set_volatile == 0)
5406 error ("internal error: %%} found without a %%{ in assembler pattern");
5407 else if (--set_volatile == 0)
5408 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5414 if (align_labels_log > 0)
5415 ASM_OUTPUT_ALIGN (file, align_labels_log);
5420 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5429 error ("PRINT_OPERAND null pointer");
5433 code = GET_CODE (op);
5438 case EQ: fputs ("eq", file); break;
5439 case NE: fputs ("ne", file); break;
5440 case GT: fputs ("gt", file); break;
5441 case GE: fputs ("ge", file); break;
5442 case LT: fputs ("lt", file); break;
5443 case LE: fputs ("le", file); break;
5444 case GTU: fputs ("gtu", file); break;
5445 case GEU: fputs ("geu", file); break;
5446 case LTU: fputs ("ltu", file); break;
5447 case LEU: fputs ("leu", file); break;
5449 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5452 else if (letter == 'N')
5455 case EQ: fputs ("ne", file); break;
5456 case NE: fputs ("eq", file); break;
5457 case GT: fputs ("le", file); break;
5458 case GE: fputs ("lt", file); break;
5459 case LT: fputs ("ge", file); break;
5460 case LE: fputs ("gt", file); break;
5461 case GTU: fputs ("leu", file); break;
5462 case GEU: fputs ("ltu", file); break;
5463 case LTU: fputs ("geu", file); break;
5464 case LEU: fputs ("gtu", file); break;
5466 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5469 else if (letter == 'F')
5472 case EQ: fputs ("c1f", file); break;
5473 case NE: fputs ("c1t", file); break;
5475 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5478 else if (letter == 'W')
5481 case EQ: fputs ("c1t", file); break;
5482 case NE: fputs ("c1f", file); break;
5484 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5487 else if (letter == 'h')
5489 if (GET_CODE (op) == HIGH)
5492 print_operand_reloc (file, op, mips_hi_relocs);
5495 else if (letter == 'R')
5496 print_operand_reloc (file, op, mips_lo_relocs);
5498 else if (letter == 'S')
5502 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5503 assemble_name (file, buffer);
5506 else if (letter == 'Z')
5508 register int regnum;
5513 regnum = REGNO (op);
5514 if (! ST_REG_P (regnum))
5517 if (regnum != ST_REG_FIRST)
5518 fprintf (file, "%s,", reg_names[regnum]);
5521 else if (code == REG || code == SUBREG)
5523 register int regnum;
5526 regnum = REGNO (op);
5528 regnum = true_regnum (op);
5530 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5531 || (letter == 'L' && WORDS_BIG_ENDIAN)
5535 fprintf (file, "%s", reg_names[regnum]);
5538 else if (code == MEM)
5541 output_address (plus_constant (XEXP (op, 0), 4));
5543 output_address (XEXP (op, 0));
5546 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5547 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5549 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5550 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5552 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5553 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5555 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5556 fputs (reg_names[GP_REG_FIRST], file);
5558 else if (letter == 'd' || letter == 'x' || letter == 'X')
5559 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5561 else if (letter == 'B')
5562 fputs (code == EQ ? "z" : "n", file);
5563 else if (letter == 'b')
5564 fputs (code == EQ ? "n" : "z", file);
5565 else if (letter == 'T')
5566 fputs (code == EQ ? "f" : "t", file);
5567 else if (letter == 't')
5568 fputs (code == EQ ? "t" : "f", file);
5570 else if (CONST_GP_P (op))
5571 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5574 output_addr_const (file, op);
5578 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5579 RELOCS is the array of relocations to use. */
5582 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5584 enum mips_symbol_type symbol_type;
5587 HOST_WIDE_INT offset;
5589 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5590 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5592 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5593 mips_split_const (op, &base, &offset);
5594 if (UNSPEC_ADDRESS_P (base))
5595 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5597 fputs (relocs[symbol_type], file);
5598 output_addr_const (file, op);
5599 for (p = relocs[symbol_type]; *p != 0; p++)
5604 /* Output address operand X to FILE. */
5607 print_operand_address (FILE *file, rtx x)
5609 struct mips_address_info addr;
5611 if (mips_classify_address (&addr, x, word_mode, true))
5615 print_operand (file, addr.offset, 0);
5616 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5619 case ADDRESS_LO_SUM:
5620 print_operand (file, addr.offset, 'R');
5621 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5624 case ADDRESS_CONST_INT:
5625 case ADDRESS_SYMBOLIC:
5626 output_addr_const (file, x);
5632 /* Target hook for assembling integer objects. It appears that the Irix
5633 6 assembler can't handle 64-bit decimal integers, so avoid printing
5634 such an integer here. */
5637 mips_assemble_integer (rtx x, unsigned int size, int aligned_p)
5639 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
5641 fputs ("\t.dword\t", asm_out_file);
5642 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
5643 output_addr_const (asm_out_file, x);
5645 print_operand (asm_out_file, x, 'X');
5646 fputc ('\n', asm_out_file);
5649 return default_assemble_integer (x, size, aligned_p);
5652 /* When using assembler macros, keep track of all of small-data externs
5653 so that mips_file_end can emit the appropriate declarations for them.
5655 In most cases it would be safe (though pointless) to emit .externs
5656 for other symbols too. One exception is when an object is within
5657 the -G limit but declared by the user to be in a section other
5658 than .sbss or .sdata. */
5661 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5663 register struct extern_list *p;
5665 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5667 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5668 p->next = extern_head;
5670 p->size = int_size_in_bytes (TREE_TYPE (decl));
5674 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5676 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5677 p->next = extern_head;
5688 irix_output_external_libcall (rtx fun)
5690 register struct extern_list *p;
5692 if (mips_abi == ABI_32)
5694 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5695 p->next = extern_head;
5696 p->name = XSTR (fun, 0);
5703 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5704 put out a MIPS ECOFF file and a stab. */
5707 mips_output_filename (FILE *stream, const char *name)
5709 char ltext_label_name[100];
5711 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5713 if (write_symbols == DWARF2_DEBUG)
5715 else if (mips_output_filename_first_time)
5717 mips_output_filename_first_time = 0;
5719 current_function_file = name;
5720 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5721 /* This tells mips-tfile that stabs will follow. */
5722 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5723 fprintf (stream, "\t#@stabs\n");
5726 else if (write_symbols == DBX_DEBUG)
5728 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5729 fprintf (stream, "%s", ASM_STABS_OP);
5730 output_quoted_string (stream, name);
5731 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5734 else if (name != current_function_file
5735 && strcmp (name, current_function_file) != 0)
5738 current_function_file = name;
5739 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5743 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5744 as well as a .loc, since it is possible that MIPS ECOFF might not be
5745 able to represent the location for inlines that come from a different
5749 mips_output_lineno (FILE *stream, int line)
5751 if (write_symbols == DBX_DEBUG)
5754 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5755 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5756 LOCAL_LABEL_PREFIX, sym_lineno);
5760 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
5761 LABEL_AFTER_LOC (stream);
5765 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5766 that should be written before the opening quote, such as "\t.ascii\t"
5767 for real string data or "\t# " for a comment. */
5770 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5775 register const unsigned char *string =
5776 (const unsigned char *)string_param;
5778 fprintf (stream, "%s\"", prefix);
5779 for (i = 0; i < len; i++)
5781 register int c = string[i];
5787 putc ('\\', stream);
5792 case TARGET_NEWLINE:
5793 fputs ("\\n", stream);
5795 && (((c = string[i+1]) >= '\040' && c <= '~')
5796 || c == TARGET_TAB))
5797 cur_pos = 32767; /* break right here */
5803 fputs ("\\t", stream);
5808 fputs ("\\f", stream);
5813 fputs ("\\b", stream);
5818 fputs ("\\r", stream);
5823 if (c >= ' ' && c < 0177)
5830 fprintf (stream, "\\%03o", c);
5835 if (cur_pos > 72 && i+1 < len)
5838 fprintf (stream, "\"\n%s\"", prefix);
5841 fprintf (stream, "\"\n");
5844 /* Implement TARGET_ASM_FILE_START. */
5847 mips_file_start (void)
5849 default_file_start ();
5851 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5852 inside of a .set noreorder section jumps to a label outside of the .set
5853 noreorder section. Revision 2.20 just set nobopt silently rather than
5856 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5857 fprintf (asm_out_file, "\t.set\tnobopt\n");
5861 #if defined(OBJECT_FORMAT_ELF) && !TARGET_IRIX
5862 /* Generate a special section to describe the ABI switches used to
5863 produce the resultant binary. This used to be done by the assembler
5864 setting bits in the ELF header's flags field, but we have run out of
5865 bits. GDB needs this information in order to be able to correctly
5866 debug these binaries. See the function mips_gdbarch_init() in
5867 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5868 causes unnecessary IRIX 6 ld warnings. */
5869 const char * abi_string = NULL;
5873 case ABI_32: abi_string = "abi32"; break;
5874 case ABI_N32: abi_string = "abiN32"; break;
5875 case ABI_64: abi_string = "abi64"; break;
5876 case ABI_O64: abi_string = "abiO64"; break;
5877 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5881 /* Note - we use fprintf directly rather than called named_section()
5882 because in this way we can avoid creating an allocated section. We
5883 do not want this section to take up any space in the running
5885 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5887 /* Restore the default section. */
5888 fprintf (asm_out_file, "\t.previous\n");
5892 /* Generate the pseudo ops that System V.4 wants. */
5893 #ifndef ABICALLS_ASM_OP
5894 #define ABICALLS_ASM_OP "\t.abicalls"
5896 if (TARGET_ABICALLS)
5897 /* ??? but do not want this (or want pic0) if -non-shared? */
5898 fprintf (asm_out_file, "%s\n", ABICALLS_ASM_OP);
5901 fprintf (asm_out_file, "\t.set\tmips16\n");
5903 if (flag_verbose_asm)
5904 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5906 mips_section_threshold, mips_arch_info->name, mips_isa);
5909 #ifdef BSS_SECTION_ASM_OP
5910 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5911 in the use of sbss. */
5914 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5915 unsigned HOST_WIDE_INT size, int align)
5917 extern tree last_assemble_variable_decl;
5919 if (mips_in_small_data_p (decl))
5920 named_section (0, ".sbss", 0);
5923 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5924 last_assemble_variable_decl = decl;
5925 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5926 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5930 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5931 .externs for any small-data variables that turned out to be external. */
5934 mips_file_end (void)
5937 struct extern_list *p;
5941 fputs ("\n", asm_out_file);
5943 for (p = extern_head; p != 0; p = p->next)
5945 name_tree = get_identifier (p->name);
5947 /* Positively ensure only one .extern for any given symbol. */
5948 if (!TREE_ASM_WRITTEN (name_tree)
5949 && TREE_SYMBOL_REFERENCED (name_tree))
5951 TREE_ASM_WRITTEN (name_tree) = 1;
5952 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5953 `.global name .text' directive for every used but
5954 undefined function. If we don't, the linker may perform
5955 an optimization (skipping over the insns that set $gp)
5956 when it is unsafe. */
5957 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5959 fputs ("\t.globl ", asm_out_file);
5960 assemble_name (asm_out_file, p->name);
5961 fputs (" .text\n", asm_out_file);
5965 fputs ("\t.extern\t", asm_out_file);
5966 assemble_name (asm_out_file, p->name);
5967 fprintf (asm_out_file, ", %d\n", p->size);
5974 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as
5975 the elfos.h version, but we also need to handle -muninit-const-in-rodata
5976 and the limitations of the SGI o32 assembler. */
5979 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5980 unsigned HOST_WIDE_INT size,
5983 /* If the target wants uninitialized const declarations in
5984 .rdata then don't put them in .comm. */
5985 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5986 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5987 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5989 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5990 targetm.asm_out.globalize_label (stream, name);
5992 readonly_data_section ();
5993 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5994 mips_declare_object (stream, name, "",
5995 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5998 else if (TARGET_SGI_O32_AS)
6000 /* The SGI o32 assembler doesn't accept an alignment, so round up
6001 the size instead. */
6002 size += (align / BITS_PER_UNIT) - 1;
6003 size -= size % (align / BITS_PER_UNIT);
6004 mips_declare_object (stream, name, "\n\t.comm\t",
6005 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6008 mips_declare_object (stream, name, "\n\t.comm\t",
6009 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6010 size, align / BITS_PER_UNIT);
6013 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6014 macros, mark the symbol as written so that mips_file_end won't emit an
6015 .extern for it. STREAM is the output file, NAME is the name of the
6016 symbol, INIT_STRING is the string that should be written before the
6017 symbol and FINAL_STRING is the string that should be written after it.
6018 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6021 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6022 const char *final_string, ...)
6026 fputs (init_string, stream);
6027 assemble_name (stream, name);
6028 va_start (ap, final_string);
6029 vfprintf (stream, final_string, ap);
6032 if (!TARGET_EXPLICIT_RELOCS)
6034 tree name_tree = get_identifier (name);
6035 TREE_ASM_WRITTEN (name_tree) = 1;
6039 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6040 extern int size_directive_output;
6042 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6043 definitions except that it uses mips_declare_object() to emit the label. */
6046 mips_declare_object_name (FILE *stream, const char *name,
6047 tree decl ATTRIBUTE_UNUSED)
6049 if (!TARGET_SGI_O32_AS)
6051 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6052 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6055 size_directive_output = 0;
6056 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6060 size_directive_output = 1;
6061 size = int_size_in_bytes (TREE_TYPE (decl));
6062 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6066 mips_declare_object (stream, name, "", ":\n", 0);
6069 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6072 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6076 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6077 if (!TARGET_SGI_O32_AS
6078 && !flag_inhibit_size_directive
6079 && DECL_SIZE (decl) != 0
6080 && !at_end && top_level
6081 && DECL_INITIAL (decl) == error_mark_node
6082 && !size_directive_output)
6086 size_directive_output = 1;
6087 size = int_size_in_bytes (TREE_TYPE (decl));
6088 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6093 /* Return true if X is a small data address that can be rewritten
6097 mips_rewrite_small_data_p (rtx x)
6099 enum mips_symbol_type symbol_type;
6101 return (TARGET_EXPLICIT_RELOCS
6102 && mips_symbolic_constant_p (x, &symbol_type)
6103 && symbol_type == SYMBOL_SMALL_DATA);
6107 /* A for_each_rtx callback for small_data_pattern. */
6110 small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6112 if (GET_CODE (*loc) == LO_SUM)
6115 return mips_rewrite_small_data_p (*loc);
6118 /* Return true if OP refers to small data symbols directly, not through
6122 small_data_pattern (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
6124 return (GET_CODE (op) != SEQUENCE
6125 && for_each_rtx (&op, small_data_pattern_1, 0));
6128 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6131 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6133 if (mips_rewrite_small_data_p (*loc))
6134 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6136 if (GET_CODE (*loc) == LO_SUM)
6142 /* If possible, rewrite OP so that it refers to small data using
6143 explicit relocations. */
6146 mips_rewrite_small_data (rtx op)
6148 op = copy_insn (op);
6149 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6153 /* Return true if the current function has an insn that implicitly
6157 mips_function_has_gp_insn (void)
6159 /* Don't bother rechecking if we found one last time. */
6160 if (!cfun->machine->has_gp_insn_p)
6164 push_topmost_sequence ();
6165 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6167 && GET_CODE (PATTERN (insn)) != USE
6168 && GET_CODE (PATTERN (insn)) != CLOBBER
6169 && (get_attr_got (insn) != GOT_UNSET
6170 || small_data_pattern (PATTERN (insn), VOIDmode)))
6172 pop_topmost_sequence ();
6174 cfun->machine->has_gp_insn_p = (insn != 0);
6176 return cfun->machine->has_gp_insn_p;
6180 /* Return the register that should be used as the global pointer
6181 within this function. Return 0 if the function doesn't need
6182 a global pointer. */
6185 mips_global_pointer (void)
6189 /* $gp is always available in non-abicalls code. */
6190 if (!TARGET_ABICALLS)
6191 return GLOBAL_POINTER_REGNUM;
6193 /* We must always provide $gp when it is used implicitly. */
6194 if (!TARGET_EXPLICIT_RELOCS)
6195 return GLOBAL_POINTER_REGNUM;
6197 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6199 if (current_function_profile)
6200 return GLOBAL_POINTER_REGNUM;
6202 /* If the function has a nonlocal goto, $gp must hold the correct
6203 global pointer for the target function. */
6204 if (current_function_has_nonlocal_goto)
6205 return GLOBAL_POINTER_REGNUM;
6207 /* If the gp is never referenced, there's no need to initialize it.
6208 Note that reload can sometimes introduce constant pool references
6209 into a function that otherwise didn't need them. For example,
6210 suppose we have an instruction like:
6212 (set (reg:DF R1) (float:DF (reg:SI R2)))
6214 If R2 turns out to be constant such as 1, the instruction may have a
6215 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6216 using this constant if R2 doesn't get allocated to a register.
6218 In cases like these, reload will have added the constant to the pool
6219 but no instruction will yet refer to it. */
6220 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6221 && !current_function_uses_const_pool
6222 && !mips_function_has_gp_insn ())
6225 /* We need a global pointer, but perhaps we can use a call-clobbered
6226 register instead of $gp. */
6227 if (TARGET_NEWABI && current_function_is_leaf)
6228 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6229 if (!regs_ever_live[regno]
6230 && call_used_regs[regno]
6231 && !fixed_regs[regno]
6232 && regno != PIC_FUNCTION_ADDR_REGNUM)
6235 return GLOBAL_POINTER_REGNUM;
6239 /* Return true if the current function must save REGNO. */
6242 mips_save_reg_p (unsigned int regno)
6244 /* We only need to save $gp for NewABI PIC. */
6245 if (regno == GLOBAL_POINTER_REGNUM)
6246 return (TARGET_ABICALLS && TARGET_NEWABI
6247 && cfun->machine->global_pointer == regno);
6249 /* Check call-saved registers. */
6250 if (regs_ever_live[regno] && !call_used_regs[regno])
6253 /* We need to save the old frame pointer before setting up a new one. */
6254 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6257 /* We need to save the incoming return address if it is ever clobbered
6258 within the function. */
6259 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6266 return_type = DECL_RESULT (current_function_decl);
6268 /* $18 is a special case in mips16 code. It may be used to call
6269 a function which returns a floating point value, but it is
6270 marked in call_used_regs. */
6271 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6274 /* $31 is also a special case. It will be used to copy a return
6275 value into the floating point registers if the return value is
6277 if (regno == GP_REG_FIRST + 31
6278 && mips16_hard_float
6279 && !aggregate_value_p (return_type, current_function_decl)
6280 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6281 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6289 /* Return the bytes needed to compute the frame pointer from the current
6290 stack pointer. SIZE is the size (in bytes) of the local variables.
6292 Mips stack frames look like:
6294 Before call After call
6295 +-----------------------+ +-----------------------+
6298 | caller's temps. | | caller's temps. |
6300 +-----------------------+ +-----------------------+
6302 | arguments on stack. | | arguments on stack. |
6304 +-----------------------+ +-----------------------+
6305 | 4 words to save | | 4 words to save |
6306 | arguments passed | | arguments passed |
6307 | in registers, even | | in registers, even |
6308 SP->| if not passed. | VFP->| if not passed. |
6309 +-----------------------+ +-----------------------+
6311 | fp register save |
6313 +-----------------------+
6315 | gp register save |
6317 +-----------------------+
6321 +-----------------------+
6323 | alloca allocations |
6325 +-----------------------+
6327 | GP save for V.4 abi |
6329 +-----------------------+
6331 | arguments on stack |
6333 +-----------------------+
6335 | arguments passed |
6336 | in registers, even |
6337 low SP->| if not passed. |
6338 memory +-----------------------+
6343 compute_frame_size (HOST_WIDE_INT size)
6346 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6347 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6348 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6349 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6350 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6351 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6352 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6353 unsigned int mask; /* mask of saved gp registers */
6354 unsigned int fmask; /* mask of saved fp registers */
6356 cfun->machine->global_pointer = mips_global_pointer ();
6362 var_size = MIPS_STACK_ALIGN (size);
6363 args_size = current_function_outgoing_args_size;
6364 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6366 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6367 functions. If the function has local variables, we're committed
6368 to allocating it anyway. Otherwise reclaim it here. */
6369 if (var_size == 0 && current_function_is_leaf)
6370 cprestore_size = args_size = 0;
6372 /* The MIPS 3.0 linker does not like functions that dynamically
6373 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6374 looks like we are trying to create a second frame pointer to the
6375 function, so allocate some stack space to make it happy. */
6377 if (args_size == 0 && current_function_calls_alloca)
6378 args_size = 4 * UNITS_PER_WORD;
6380 total_size = var_size + args_size + cprestore_size;
6382 /* Calculate space needed for gp registers. */
6383 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6384 if (mips_save_reg_p (regno))
6386 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6387 mask |= 1 << (regno - GP_REG_FIRST);
6390 /* We need to restore these for the handler. */
6391 if (current_function_calls_eh_return)
6396 regno = EH_RETURN_DATA_REGNO (i);
6397 if (regno == INVALID_REGNUM)
6399 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6400 mask |= 1 << (regno - GP_REG_FIRST);
6404 /* This loop must iterate over the same space as its companion in
6405 save_restore_insns. */
6406 for (regno = (FP_REG_LAST - FP_INC + 1);
6407 regno >= FP_REG_FIRST;
6410 if (mips_save_reg_p (regno))
6412 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6413 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6417 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6418 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6420 /* Add in space reserved on the stack by the callee for storing arguments
6421 passed in registers. */
6423 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6425 /* Save other computed information. */
6426 cfun->machine->frame.total_size = total_size;
6427 cfun->machine->frame.var_size = var_size;
6428 cfun->machine->frame.args_size = args_size;
6429 cfun->machine->frame.cprestore_size = cprestore_size;
6430 cfun->machine->frame.gp_reg_size = gp_reg_size;
6431 cfun->machine->frame.fp_reg_size = fp_reg_size;
6432 cfun->machine->frame.mask = mask;
6433 cfun->machine->frame.fmask = fmask;
6434 cfun->machine->frame.initialized = reload_completed;
6435 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6436 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6440 HOST_WIDE_INT offset;
6442 offset = (args_size + cprestore_size + var_size
6443 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6444 cfun->machine->frame.gp_sp_offset = offset;
6445 cfun->machine->frame.gp_save_offset = offset - total_size;
6449 cfun->machine->frame.gp_sp_offset = 0;
6450 cfun->machine->frame.gp_save_offset = 0;
6455 HOST_WIDE_INT offset;
6457 offset = (args_size + cprestore_size + var_size
6458 + gp_reg_rounded + fp_reg_size
6459 - FP_INC * UNITS_PER_FPREG);
6460 cfun->machine->frame.fp_sp_offset = offset;
6461 cfun->machine->frame.fp_save_offset = offset - total_size;
6465 cfun->machine->frame.fp_sp_offset = 0;
6466 cfun->machine->frame.fp_save_offset = 0;
6469 /* Ok, we're done. */
6473 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6474 pointer or argument pointer. TO is either the stack pointer or
6475 hard frame pointer. */
6478 mips_initial_elimination_offset (int from, int to)
6480 HOST_WIDE_INT offset;
6482 compute_frame_size (get_frame_size ());
6484 /* Set OFFSET to the offset from the stack pointer. */
6487 case FRAME_POINTER_REGNUM:
6491 case ARG_POINTER_REGNUM:
6492 offset = cfun->machine->frame.total_size;
6494 offset -= current_function_pretend_args_size;
6501 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6502 offset -= cfun->machine->frame.args_size;
6507 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6508 back to a previous frame. */
6510 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6515 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6518 /* Use FN to save or restore register REGNO. MODE is the register's
6519 mode and OFFSET is the offset of its save slot from the current
6523 mips_save_restore_reg (enum machine_mode mode, int regno,
6524 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6528 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6529 if (!current_function_calls_eh_return)
6530 RTX_UNCHANGING_P (mem) = 1;
6532 fn (gen_rtx_REG (mode, regno), mem);
6536 /* Call FN for each register that is saved by the current function.
6537 SP_OFFSET is the offset of the current stack pointer from the start
6541 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6543 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6545 enum machine_mode fpr_mode;
6546 HOST_WIDE_INT offset;
6549 /* Save registers starting from high to low. The debuggers prefer at least
6550 the return register be stored at func+4, and also it allows us not to
6551 need a nop in the epilog if at least one register is reloaded in
6552 addition to return address. */
6553 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6554 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6555 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6557 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6558 offset -= GET_MODE_SIZE (gpr_mode);
6561 /* This loop must iterate over the same space as its companion in
6562 compute_frame_size. */
6563 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6564 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6565 for (regno = (FP_REG_LAST - FP_INC + 1);
6566 regno >= FP_REG_FIRST;
6568 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6570 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6571 offset -= GET_MODE_SIZE (fpr_mode);
6576 /* If we're generating n32 or n64 abicalls, and the current function
6577 does not use $28 as its global pointer, emit a cplocal directive.
6578 Use pic_offset_table_rtx as the argument to the directive. */
6581 mips_output_cplocal (void)
6583 if (!TARGET_EXPLICIT_RELOCS
6584 && cfun->machine->global_pointer > 0
6585 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6586 output_asm_insn (".cplocal %+", 0);
6589 /* If we're generating n32 or n64 abicalls, emit instructions
6590 to set up the global pointer. */
6593 mips_emit_loadgp (void)
6595 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6597 rtx addr, offset, incoming_address;
6599 addr = XEXP (DECL_RTL (current_function_decl), 0);
6600 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6601 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6602 emit_insn (gen_loadgp (offset, incoming_address));
6603 if (!TARGET_EXPLICIT_RELOCS)
6604 emit_insn (gen_loadgp_blockage ());
6608 /* Set up the stack and frame (if desired) for the function. */
6611 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6614 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6616 /* ??? When is this really needed? At least the GNU assembler does not
6617 need the source filename more than once in the file, beyond what is
6618 emitted by the debug information. */
6620 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6622 #ifdef SDB_DEBUGGING_INFO
6623 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6624 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl), 0);
6627 /* In mips16 mode, we may need to generate a 32 bit to handle
6628 floating point arguments. The linker will arrange for any 32 bit
6629 functions to call this stub, which will then jump to the 16 bit
6631 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6632 && current_function_args_info.fp_code != 0)
6633 build_mips16_function_stub (file);
6635 if (!FUNCTION_NAME_ALREADY_DECLARED)
6637 /* Get the function name the same way that toplev.c does before calling
6638 assemble_start_function. This is needed so that the name used here
6639 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6640 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6642 if (!flag_inhibit_size_directive)
6644 fputs ("\t.ent\t", file);
6645 assemble_name (file, fnname);
6649 assemble_name (file, fnname);
6650 fputs (":\n", file);
6653 if (!flag_inhibit_size_directive)
6655 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6657 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6658 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6659 ", args= " HOST_WIDE_INT_PRINT_DEC
6660 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6661 (reg_names[(frame_pointer_needed)
6662 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6663 ((frame_pointer_needed && TARGET_MIPS16)
6664 ? tsize - cfun->machine->frame.args_size
6666 reg_names[GP_REG_FIRST + 31],
6667 cfun->machine->frame.var_size,
6668 cfun->machine->frame.num_gp,
6669 cfun->machine->frame.num_fp,
6670 cfun->machine->frame.args_size,
6671 cfun->machine->frame.cprestore_size);
6673 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6674 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6675 cfun->machine->frame.mask,
6676 cfun->machine->frame.gp_save_offset);
6677 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6678 cfun->machine->frame.fmask,
6679 cfun->machine->frame.fp_save_offset);
6682 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6683 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6686 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6688 /* Handle the initialization of $gp for SVR4 PIC. */
6689 if (!cfun->machine->all_noreorder_p)
6690 output_asm_insn ("%(.cpload\t%^%)", 0);
6692 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6694 else if (cfun->machine->all_noreorder_p)
6695 output_asm_insn ("%(%<", 0);
6697 /* Tell the assembler which register we're using as the global
6698 pointer. This is needed for thunks, since they can use either
6699 explicit relocs or assembler macros. */
6700 mips_output_cplocal ();
6703 /* Make the last instruction frame related and note that it performs
6704 the operation described by FRAME_PATTERN. */
6707 mips_set_frame_expr (rtx frame_pattern)
6711 insn = get_last_insn ();
6712 RTX_FRAME_RELATED_P (insn) = 1;
6713 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6719 /* Return a frame-related rtx that stores REG at MEM.
6720 REG must be a single register. */
6723 mips_frame_set (rtx mem, rtx reg)
6725 rtx set = gen_rtx_SET (VOIDmode, mem, reg);
6726 RTX_FRAME_RELATED_P (set) = 1;
6731 /* Save register REG to MEM. Make the instruction frame-related. */
6734 mips_save_reg (rtx reg, rtx mem)
6736 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6740 if (mips_split_64bit_move_p (mem, reg))
6741 mips_split_64bit_move (mem, reg);
6743 emit_move_insn (mem, reg);
6745 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6746 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6747 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6752 && REGNO (reg) != GP_REG_FIRST + 31
6753 && !M16_REG_P (REGNO (reg)))
6755 /* Save a non-mips16 register by moving it through a temporary.
6756 We don't need to do this for $31 since there's a special
6757 instruction for it. */
6758 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6759 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6762 emit_move_insn (mem, reg);
6764 mips_set_frame_expr (mips_frame_set (mem, reg));
6769 /* Expand the prologue into a bunch of separate insns. */
6772 mips_expand_prologue (void)
6776 if (cfun->machine->global_pointer > 0)
6777 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6779 size = compute_frame_size (get_frame_size ());
6781 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6782 bytes beforehand; this is enough to cover the register save area
6783 without going out of range. */
6784 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6786 HOST_WIDE_INT step1;
6788 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6789 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6791 GEN_INT (-step1)))) = 1;
6793 mips_for_each_saved_reg (size, mips_save_reg);
6796 /* Allocate the rest of the frame. */
6799 if (SMALL_OPERAND (-size))
6800 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6802 GEN_INT (-size)))) = 1;
6805 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6808 /* There are no instructions to add or subtract registers
6809 from the stack pointer, so use the frame pointer as a
6810 temporary. We should always be using a frame pointer
6811 in this case anyway. */
6812 if (!frame_pointer_needed)
6815 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6816 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6817 hard_frame_pointer_rtx,
6818 MIPS_PROLOGUE_TEMP (Pmode)));
6819 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6822 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6824 MIPS_PROLOGUE_TEMP (Pmode)));
6826 /* Describe the combined effect of the previous instructions. */
6828 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6829 plus_constant (stack_pointer_rtx, -size)));
6833 /* Set up the frame pointer, if we're using one. In mips16 code,
6834 we point the frame pointer ahead of the outgoing argument area.
6835 This should allow more variables & incoming arguments to be
6836 accessed with unextended instructions. */
6837 if (frame_pointer_needed)
6839 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6841 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6843 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6848 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6849 stack_pointer_rtx)) = 1;
6852 /* If generating o32/o64 abicalls, save $gp on the stack. */
6853 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6854 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6856 mips_emit_loadgp ();
6858 /* If we are profiling, make sure no instructions are scheduled before
6859 the call to mcount. */
6861 if (current_function_profile)
6862 emit_insn (gen_blockage ());
6865 /* Do any necessary cleanup after a function to restore stack, frame,
6868 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6871 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6872 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6876 /* Reinstate the normal $gp. */
6877 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6878 mips_output_cplocal ();
6880 if (cfun->machine->all_noreorder_p)
6882 /* Avoid using %>%) since it adds excess whitespace. */
6883 output_asm_insn (".set\tmacro", 0);
6884 output_asm_insn (".set\treorder", 0);
6885 set_noreorder = set_nomacro = 0;
6888 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6892 /* Get the function name the same way that toplev.c does before calling
6893 assemble_start_function. This is needed so that the name used here
6894 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6895 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6896 fputs ("\t.end\t", file);
6897 assemble_name (file, fnname);
6901 while (string_constants != NULL)
6903 struct string_constant *next;
6905 next = string_constants->next;
6906 free (string_constants);
6907 string_constants = next;
6910 /* If any following function uses the same strings as this one, force
6911 them to refer those strings indirectly. Nearby functions could
6912 refer them using pc-relative addressing, but it isn't safe in
6913 general. For instance, some functions may be placed in sections
6914 other than .text, and we don't know whether they be close enough
6915 to this one. In large files, even other .text functions can be
6917 for (string = mips16_strings; string != 0; string = XEXP (string, 1))
6918 SYMBOL_REF_FLAG (XEXP (string, 0)) = 0;
6919 free_EXPR_LIST_list (&mips16_strings);
6922 /* Emit instructions to restore register REG from slot MEM. */
6925 mips_restore_reg (rtx reg, rtx mem)
6927 /* There's no mips16 instruction to load $31 directly. Load into
6928 $7 instead and adjust the return insn appropriately. */
6929 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6930 reg = gen_rtx_REG (GET_MODE (reg), 7);
6932 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6934 /* Can't restore directly; move through a temporary. */
6935 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6936 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6939 emit_move_insn (reg, mem);
6943 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6944 if this epilogue precedes a sibling call, false if it is for a normal
6945 "epilogue" pattern. */
6948 mips_expand_epilogue (int sibcall_p)
6950 HOST_WIDE_INT step1, step2;
6953 if (!sibcall_p && mips_can_use_return_insn ())
6955 emit_jump_insn (gen_return ());
6959 /* Split the frame into two. STEP1 is the amount of stack we should
6960 deallocate before restoring the registers. STEP2 is the amount we
6961 should deallocate afterwards.
6963 Start off by assuming that no registers need to be restored. */
6964 step1 = cfun->machine->frame.total_size;
6967 /* Work out which register holds the frame address. Account for the
6968 frame pointer offset used by mips16 code. */
6969 if (!frame_pointer_needed)
6970 base = stack_pointer_rtx;
6973 base = hard_frame_pointer_rtx;
6975 step1 -= cfun->machine->frame.args_size;
6978 /* If we need to restore registers, deallocate as much stack as
6979 possible in the second step without going out of range. */
6980 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6982 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6986 /* Set TARGET to BASE + STEP1. */
6992 /* Get an rtx for STEP1 that we can add to BASE. */
6993 adjust = GEN_INT (step1);
6994 if (!SMALL_OPERAND (step1))
6996 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6997 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7000 /* Normal mode code can copy the result straight into $sp. */
7002 target = stack_pointer_rtx;
7004 emit_insn (gen_add3_insn (target, base, adjust));
7007 /* Copy TARGET into the stack pointer. */
7008 if (target != stack_pointer_rtx)
7009 emit_move_insn (stack_pointer_rtx, target);
7011 /* If we're using addressing macros for n32/n64 abicalls, $gp is
7012 implicitly used by all SYMBOL_REFs. We must emit a blockage
7013 insn before restoring it. */
7014 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
7015 emit_insn (gen_blockage ());
7017 /* Restore the registers. */
7018 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7021 /* Deallocate the final bit of the frame. */
7023 emit_insn (gen_add3_insn (stack_pointer_rtx,
7027 /* Add in the __builtin_eh_return stack adjustment. We need to
7028 use a temporary in mips16 code. */
7029 if (current_function_calls_eh_return)
7033 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7034 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7035 MIPS_EPILOGUE_TEMP (Pmode),
7036 EH_RETURN_STACKADJ_RTX));
7037 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7040 emit_insn (gen_add3_insn (stack_pointer_rtx,
7042 EH_RETURN_STACKADJ_RTX));
7047 /* The mips16 loads the return address into $7, not $31. */
7048 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7049 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7050 GP_REG_FIRST + 7)));
7052 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7053 GP_REG_FIRST + 31)));
7057 /* Return nonzero if this function is known to have a null epilogue.
7058 This allows the optimizer to omit jumps to jumps if no stack
7062 mips_can_use_return_insn (void)
7066 if (! reload_completed)
7069 if (regs_ever_live[31] || current_function_profile)
7072 return_type = DECL_RESULT (current_function_decl);
7074 /* In mips16 mode, a function which returns a floating point value
7075 needs to arrange to copy the return value into the floating point
7078 && mips16_hard_float
7079 && ! aggregate_value_p (return_type, current_function_decl)
7080 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7081 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7084 if (cfun->machine->frame.initialized)
7085 return cfun->machine->frame.total_size == 0;
7087 return compute_frame_size (get_frame_size ()) == 0;
7090 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7091 in order to avoid duplicating too much logic from elsewhere. */
7094 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7095 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7098 rtx this, temp1, temp2, insn, fnaddr;
7100 /* Pretend to be a post-reload pass while generating rtl. */
7102 reload_completed = 1;
7104 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7105 for TARGET_NEWABI since the latter is a call-saved register. */
7106 if (TARGET_ABICALLS)
7107 cfun->machine->global_pointer
7108 = REGNO (pic_offset_table_rtx)
7109 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7111 /* Set up the global pointer for n32 or n64 abicalls. */
7112 mips_emit_loadgp ();
7114 /* We need two temporary registers in some cases. */
7115 temp1 = gen_rtx_REG (Pmode, 2);
7116 temp2 = gen_rtx_REG (Pmode, 3);
7118 /* Find out which register contains the "this" pointer. */
7119 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7120 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7122 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7124 /* Add DELTA to THIS. */
7127 rtx offset = GEN_INT (delta);
7128 if (!SMALL_OPERAND (delta))
7130 emit_move_insn (temp1, offset);
7133 emit_insn (gen_add3_insn (this, this, offset));
7136 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7137 if (vcall_offset != 0)
7141 /* Set TEMP1 to *THIS. */
7142 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7144 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7145 if (SMALL_OPERAND (vcall_offset))
7146 addr = gen_rtx_PLUS (Pmode, temp1, GEN_INT (vcall_offset));
7147 else if (TARGET_MIPS16)
7149 /* Load the full offset into a register so that we can use
7150 an unextended instruction for the load itself. */
7151 emit_move_insn (temp2, GEN_INT (vcall_offset));
7152 emit_insn (gen_add3_insn (temp1, temp1, temp2));
7157 /* Load the high part of the offset into a register and
7158 leave the low part for the address. */
7159 emit_move_insn (temp2, GEN_INT (CONST_HIGH_PART (vcall_offset)));
7160 emit_insn (gen_add3_insn (temp1, temp1, temp2));
7161 addr = gen_rtx_PLUS (Pmode, temp1,
7162 GEN_INT (CONST_LOW_PART (vcall_offset)));
7165 /* Load the offset and add it to THIS. */
7166 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7167 emit_insn (gen_add3_insn (this, this, temp1));
7170 /* Jump to the target function. Use a sibcall if direct jumps are
7171 allowed, otherwise load the address into a register first. */
7172 fnaddr = XEXP (DECL_RTL (function), 0);
7173 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7175 /* This is messy. gas treats "la $25,foo" as part of a call
7176 sequence and may allow a global "foo" to be lazily bound.
7177 The general move patterns therefore reject this combination.
7179 In this context, lazy binding would actually be OK for o32 and o64,
7180 but it's still wrong for n32 and n64; see mips_load_call_address.
7181 We must therefore load the address via a temporary register if
7182 mips_dangerous_for_la25_p.
7184 If we jump to the temporary register rather than $25, the assembler
7185 can use the move insn to fill the jump's delay slot. */
7186 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7187 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7188 mips_load_call_address (temp1, fnaddr, true);
7190 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7191 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7192 emit_jump_insn (gen_indirect_jump (temp1));
7196 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7197 SIBLING_CALL_P (insn) = 1;
7200 /* Run just enough of rest_of_compilation. This sequence was
7201 "borrowed" from alpha.c. */
7202 insn = get_insns ();
7203 insn_locators_initialize ();
7204 split_all_insns_noflow ();
7205 shorten_branches (insn);
7206 final_start_function (insn, file, 1);
7207 final (insn, file, 1, 0);
7208 final_end_function ();
7210 /* Clean up the vars set above. Note that final_end_function resets
7211 the global pointer for us. */
7212 reload_completed = 0;
7216 /* Returns nonzero if X contains a SYMBOL_REF. */
7219 symbolic_expression_p (rtx x)
7221 if (GET_CODE (x) == SYMBOL_REF)
7224 if (GET_CODE (x) == CONST)
7225 return symbolic_expression_p (XEXP (x, 0));
7228 return symbolic_expression_p (XEXP (x, 0));
7230 if (ARITHMETIC_P (x))
7231 return (symbolic_expression_p (XEXP (x, 0))
7232 || symbolic_expression_p (XEXP (x, 1)));
7237 /* Choose the section to use for the constant rtx expression X that has
7241 mips_select_rtx_section (enum machine_mode mode, rtx x,
7242 unsigned HOST_WIDE_INT align)
7246 /* In mips16 mode, the constant table always goes in the same section
7247 as the function, so that constants can be loaded using PC relative
7249 function_section (current_function_decl);
7251 else if (TARGET_EMBEDDED_DATA)
7253 /* For embedded applications, always put constants in read-only data,
7254 in order to reduce RAM usage. */
7255 mergeable_constant_section (mode, align, 0);
7259 /* For hosted applications, always put constants in small data if
7260 possible, as this gives the best performance. */
7261 /* ??? Consider using mergeable small data sections. */
7263 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7264 && mips_section_threshold > 0)
7265 named_section (0, ".sdata", 0);
7266 else if (flag_pic && symbolic_expression_p (x))
7268 if (targetm.have_named_sections)
7269 named_section (0, ".data.rel.ro", 3);
7274 mergeable_constant_section (mode, align, 0);
7278 /* Choose the section to use for DECL. RELOC is true if its value contains
7279 any relocatable expression. */
7282 mips_select_section (tree decl, int reloc,
7283 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
7285 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7286 && TREE_CODE (decl) == STRING_CST)
7287 /* For embedded position independent code, put constant strings in the
7288 text section, because the data section is limited to 64K in size.
7289 For mips16 code, put strings in the text section so that a PC
7290 relative load instruction can be used to get their address. */
7292 else if (targetm.have_named_sections)
7293 default_elf_select_section (decl, reloc, align);
7295 /* The native irix o32 assembler doesn't support named sections. */
7296 default_select_section (decl, reloc, align);
7300 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7301 access DECL using %gp_rel(...)($gp). */
7304 mips_in_small_data_p (tree decl)
7308 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7311 /* We don't yet generate small-data references for -mabicalls. See related
7312 -G handling in override_options. */
7313 if (TARGET_ABICALLS)
7316 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7320 /* Reject anything that isn't in a known small-data section. */
7321 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7322 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7325 /* If a symbol is defined externally, the assembler will use the
7326 usual -G rules when deciding how to implement macros. */
7327 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7330 else if (TARGET_EMBEDDED_DATA)
7332 /* Don't put constants into the small data section: we want them
7333 to be in ROM rather than RAM. */
7334 if (TREE_CODE (decl) != VAR_DECL)
7337 if (TREE_READONLY (decl)
7338 && !TREE_SIDE_EFFECTS (decl)
7339 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7343 size = int_size_in_bytes (TREE_TYPE (decl));
7344 return (size > 0 && size <= mips_section_threshold);
7348 /* When generating embedded PIC code, SYMBOL_REF_FLAG is set for
7349 symbols which are not in the .text section.
7351 When generating mips16 code, SYMBOL_REF_FLAG is set for string
7352 constants which are put in the .text section. We also record the
7353 total length of all such strings; this total is used to decide
7354 whether we need to split the constant table, and need not be
7355 precisely correct. */
7358 mips_encode_section_info (tree decl, rtx rtl, int first)
7362 if (GET_CODE (rtl) != MEM)
7365 symbol = XEXP (rtl, 0);
7367 if (GET_CODE (symbol) != SYMBOL_REF)
7372 if (first && TREE_CODE (decl) == STRING_CST
7373 /* If this string is from a function, and the function will
7374 go in a gnu linkonce section, then we can't directly
7375 access the string. This gets an assembler error
7376 "unsupported PC relative reference to different section".
7377 If we modify SELECT_SECTION to put it in function_section
7378 instead of text_section, it still fails because
7379 DECL_SECTION_NAME isn't set until assemble_start_function.
7380 If we fix that, it still fails because strings are shared
7381 among multiple functions, and we have cross section
7382 references again. We force it to work by putting string
7383 addresses in the constant pool and indirecting. */
7384 && (! current_function_decl
7385 || ! DECL_ONE_ONLY (current_function_decl)))
7387 mips16_strings = alloc_EXPR_LIST (0, symbol, mips16_strings);
7388 SYMBOL_REF_FLAG (symbol) = 1;
7389 mips_string_length += TREE_STRING_LENGTH (decl);
7393 if (TARGET_EMBEDDED_PIC)
7395 if (TREE_CODE (decl) == VAR_DECL)
7396 SYMBOL_REF_FLAG (symbol) = 1;
7397 else if (TREE_CODE (decl) == FUNCTION_DECL)
7398 SYMBOL_REF_FLAG (symbol) = 0;
7399 else if (TREE_CODE (decl) == STRING_CST)
7400 SYMBOL_REF_FLAG (symbol) = 0;
7402 SYMBOL_REF_FLAG (symbol) = 1;
7405 default_encode_section_info (decl, rtl, first);
7408 /* See whether VALTYPE is a record whose fields should be returned in
7409 floating-point registers. If so, return the number of fields and
7410 list them in FIELDS (which should have two elements). Return 0
7413 For n32 & n64, a structure with one or two fields is returned in
7414 floating-point registers as long as every field has a floating-point
7418 mips_fpr_return_fields (tree valtype, tree *fields)
7426 if (TREE_CODE (valtype) != RECORD_TYPE)
7430 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7432 if (TREE_CODE (field) != FIELD_DECL)
7435 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7441 fields[i++] = field;
7447 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7448 a value in the most significant part of $2/$3 if:
7450 - the target is big-endian;
7452 - the value has a structure or union type (we generalize this to
7453 cover aggregates from other languages too); and
7455 - the structure is not returned in floating-point registers. */
7458 mips_return_in_msb (tree valtype)
7462 return (TARGET_NEWABI
7463 && TARGET_BIG_ENDIAN
7464 && AGGREGATE_TYPE_P (valtype)
7465 && mips_fpr_return_fields (valtype, fields) == 0);
7469 /* Return a composite value in a pair of floating-point registers.
7470 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7471 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7474 For n32 & n64, $f0 always holds the first value and $f2 the second.
7475 Otherwise the values are packed together as closely as possible. */
7478 mips_return_fpr_pair (enum machine_mode mode,
7479 enum machine_mode mode1, HOST_WIDE_INT offset1,
7480 enum machine_mode mode2, HOST_WIDE_INT offset2)
7484 inc = (TARGET_NEWABI ? 2 : FP_INC);
7485 return gen_rtx_PARALLEL
7488 gen_rtx_EXPR_LIST (VOIDmode,
7489 gen_rtx_REG (mode1, FP_RETURN),
7491 gen_rtx_EXPR_LIST (VOIDmode,
7492 gen_rtx_REG (mode2, FP_RETURN + inc),
7493 GEN_INT (offset2))));
7498 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7499 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7500 VALTYPE is null and MODE is the mode of the return value. */
7503 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7504 enum machine_mode mode)
7511 mode = TYPE_MODE (valtype);
7512 unsignedp = TYPE_UNSIGNED (valtype);
7514 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7515 true, we must promote the mode just as PROMOTE_MODE does. */
7516 mode = promote_mode (valtype, mode, &unsignedp, 1);
7518 /* Handle structures whose fields are returned in $f0/$f2. */
7519 switch (mips_fpr_return_fields (valtype, fields))
7522 return gen_rtx_REG (mode, FP_RETURN);
7525 return mips_return_fpr_pair (mode,
7526 TYPE_MODE (TREE_TYPE (fields[0])),
7527 int_byte_position (fields[0]),
7528 TYPE_MODE (TREE_TYPE (fields[1])),
7529 int_byte_position (fields[1]));
7532 /* If a value is passed in the most significant part of a register, see
7533 whether we have to round the mode up to a whole number of words. */
7534 if (mips_return_in_msb (valtype))
7536 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7537 if (size % UNITS_PER_WORD != 0)
7539 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7540 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7545 if (GET_MODE_CLASS (mode) == MODE_FLOAT
7546 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7547 return gen_rtx_REG (mode, FP_RETURN);
7549 /* Handle long doubles for n32 & n64. */
7551 return mips_return_fpr_pair (mode,
7553 DImode, GET_MODE_SIZE (mode) / 2);
7555 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7556 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7557 return mips_return_fpr_pair (mode,
7558 GET_MODE_INNER (mode), 0,
7559 GET_MODE_INNER (mode),
7560 GET_MODE_SIZE (mode) / 2);
7562 return gen_rtx_REG (mode, GP_RETURN);
7565 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7566 nonzero when an argument must be passed by reference. */
7569 function_arg_pass_by_reference (const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7570 enum machine_mode mode, tree type,
7571 int named ATTRIBUTE_UNUSED)
7575 /* The EABI is the only one to pass args by reference. */
7576 if (mips_abi != ABI_EABI)
7579 /* ??? How should SCmode be handled? */
7580 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7583 size = int_size_in_bytes (type);
7584 return size == -1 || size > UNITS_PER_WORD;
7587 /* Return the class of registers for which a mode change from FROM to TO
7590 In little-endian mode, the hi-lo registers are numbered backwards,
7591 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
7594 Similarly, when using paired floating-point registers, the first
7595 register holds the low word, regardless of endianness. So in big
7596 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
7599 Also, loading a 32-bit value into a 64-bit floating-point register
7600 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7601 We can't allow 64-bit float registers to change from a 32-bit
7602 mode to a 64-bit mode. */
7605 mips_cannot_change_mode_class (enum machine_mode from,
7606 enum machine_mode to, enum reg_class class)
7608 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
7610 if (TARGET_BIG_ENDIAN)
7611 return reg_classes_intersect_p (FP_REGS, class);
7613 return reg_classes_intersect_p (HI_AND_FP_REGS, class);
7614 return reg_classes_intersect_p (HI_REG, class);
7619 /* Return true if X should not be moved directly into register $25.
7620 We need this because many versions of GAS will treat "la $25,foo" as
7621 part of a call sequence and so allow a global "foo" to be lazily bound. */
7624 mips_dangerous_for_la25_p (rtx x)
7626 HOST_WIDE_INT offset;
7628 if (TARGET_EXPLICIT_RELOCS)
7631 mips_split_const (x, &x, &offset);
7632 return global_got_operand (x, VOIDmode);
7635 /* Implement PREFERRED_RELOAD_CLASS. */
7638 mips_preferred_reload_class (rtx x, enum reg_class class)
7640 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7643 if (TARGET_HARD_FLOAT
7644 && FLOAT_MODE_P (GET_MODE (x))
7645 && reg_class_subset_p (FP_REGS, class))
7648 if (reg_class_subset_p (GR_REGS, class))
7651 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7657 /* This function returns the register class required for a secondary
7658 register when copying between one of the registers in CLASS, and X,
7659 using MODE. If IN_P is nonzero, the copy is going from X to the
7660 register, otherwise the register is the source. A return value of
7661 NO_REGS means that no secondary register is required. */
7664 mips_secondary_reload_class (enum reg_class class,
7665 enum machine_mode mode, rtx x, int in_p)
7667 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7671 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7672 regno = true_regnum (x);
7674 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7676 if (mips_dangerous_for_la25_p (x))
7679 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7683 /* Copying from HI or LO to anywhere other than a general register
7684 requires a general register. */
7685 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7687 if (TARGET_MIPS16 && in_p)
7689 /* We can't really copy to HI or LO at all in mips16 mode. */
7692 return gp_reg_p ? NO_REGS : gr_regs;
7694 if (MD_REG_P (regno))
7696 if (TARGET_MIPS16 && ! in_p)
7698 /* We can't really copy to HI or LO at all in mips16 mode. */
7701 return class == gr_regs ? NO_REGS : gr_regs;
7704 /* We can only copy a value to a condition code register from a
7705 floating point register, and even then we require a scratch
7706 floating point register. We can only copy a value out of a
7707 condition code register into a general register. */
7708 if (class == ST_REGS)
7712 return gp_reg_p ? NO_REGS : gr_regs;
7714 if (ST_REG_P (regno))
7718 return class == gr_regs ? NO_REGS : gr_regs;
7721 if (class == FP_REGS)
7723 if (GET_CODE (x) == MEM)
7725 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7728 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7730 /* We can use the l.s and l.d macros to load floating-point
7731 constants. ??? For l.s, we could probably get better
7732 code by returning GR_REGS here. */
7735 else if (gp_reg_p || x == CONST0_RTX (mode))
7737 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7740 else if (FP_REG_P (regno))
7742 /* In this case we can use mov.s or mov.d. */
7747 /* Otherwise, we need to reload through an integer register. */
7752 /* In mips16 mode, going between memory and anything but M16_REGS
7753 requires an M16_REG. */
7756 if (class != M16_REGS && class != M16_NA_REGS)
7764 if (class == M16_REGS || class == M16_NA_REGS)
7773 /* Implement CLASS_MAX_NREGS.
7775 Usually all registers are word-sized. The only supported exception
7776 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7777 registers. A word-based calculation is correct even in that case,
7778 since -msingle-float disallows multi-FPR values. */
7781 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7782 enum machine_mode mode)
7784 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7788 mips_valid_pointer_mode (enum machine_mode mode)
7790 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7794 /* If we can access small data directly (using gp-relative relocation
7795 operators) return the small data pointer, otherwise return null.
7797 For each mips16 function which refers to GP relative symbols, we
7798 use a pseudo register, initialized at the start of the function, to
7799 hold the $gp value. */
7802 mips16_gp_pseudo_reg (void)
7804 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7809 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7810 RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
7812 /* We want to initialize this to a value which gcc will believe
7815 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7816 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7817 gen_rtx_CONST (Pmode, unspec));
7818 insn = get_insns ();
7821 push_topmost_sequence ();
7822 /* We need to emit the initialization after the FUNCTION_BEG
7823 note, so that it will be integrated. */
7824 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7825 if (GET_CODE (scan) == NOTE
7826 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7828 if (scan == NULL_RTX)
7829 scan = get_insns ();
7830 insn = emit_insn_after (insn, scan);
7831 pop_topmost_sequence ();
7834 return cfun->machine->mips16_gp_pseudo_rtx;
7837 /* Write out code to move floating point arguments in or out of
7838 general registers. Output the instructions to FILE. FP_CODE is
7839 the code describing which arguments are present (see the comment at
7840 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7841 we are copying from the floating point registers. */
7844 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7850 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7858 gparg = GP_ARG_FIRST;
7859 fparg = FP_ARG_FIRST;
7860 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7864 if ((fparg & 1) != 0)
7866 fprintf (file, "\t%s\t%s,%s\n", s,
7867 reg_names[gparg], reg_names[fparg]);
7869 else if ((f & 3) == 2)
7872 fprintf (file, "\td%s\t%s,%s\n", s,
7873 reg_names[gparg], reg_names[fparg]);
7876 if ((fparg & 1) != 0)
7878 if (TARGET_BIG_ENDIAN)
7879 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7880 reg_names[gparg], reg_names[fparg + 1], s,
7881 reg_names[gparg + 1], reg_names[fparg]);
7883 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7884 reg_names[gparg], reg_names[fparg], s,
7885 reg_names[gparg + 1], reg_names[fparg + 1]);
7898 /* Build a mips16 function stub. This is used for functions which
7899 take arguments in the floating point registers. It is 32 bit code
7900 that moves the floating point args into the general registers, and
7901 then jumps to the 16 bit code. */
7904 build_mips16_function_stub (FILE *file)
7907 char *secname, *stubname;
7908 tree stubid, stubdecl;
7912 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7913 secname = (char *) alloca (strlen (fnname) + 20);
7914 sprintf (secname, ".mips16.fn.%s", fnname);
7915 stubname = (char *) alloca (strlen (fnname) + 20);
7916 sprintf (stubname, "__fn_stub_%s", fnname);
7917 stubid = get_identifier (stubname);
7918 stubdecl = build_decl (FUNCTION_DECL, stubid,
7919 build_function_type (void_type_node, NULL_TREE));
7920 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7922 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7924 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7926 fprintf (file, "%s%s",
7927 need_comma ? ", " : "",
7928 (f & 3) == 1 ? "float" : "double");
7931 fprintf (file, ")\n");
7933 fprintf (file, "\t.set\tnomips16\n");
7934 function_section (stubdecl);
7935 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7937 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7938 within a .ent, and we can not emit another .ent. */
7939 if (!FUNCTION_NAME_ALREADY_DECLARED)
7941 fputs ("\t.ent\t", file);
7942 assemble_name (file, stubname);
7946 assemble_name (file, stubname);
7947 fputs (":\n", file);
7949 /* We don't want the assembler to insert any nops here. */
7950 fprintf (file, "\t.set\tnoreorder\n");
7952 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7954 fprintf (asm_out_file, "\t.set\tnoat\n");
7955 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7956 assemble_name (file, fnname);
7957 fprintf (file, "\n");
7958 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7959 fprintf (asm_out_file, "\t.set\tat\n");
7961 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7962 with one of the mfc1 instructions, because the result is not
7963 available for one instruction, so if the very first instruction
7964 in the function refers to the register, it will see the wrong
7966 fprintf (file, "\tnop\n");
7968 fprintf (file, "\t.set\treorder\n");
7970 if (!FUNCTION_NAME_ALREADY_DECLARED)
7972 fputs ("\t.end\t", file);
7973 assemble_name (file, stubname);
7977 fprintf (file, "\t.set\tmips16\n");
7979 function_section (current_function_decl);
7982 /* We keep a list of functions for which we have already built stubs
7983 in build_mips16_call_stub. */
7987 struct mips16_stub *next;
7992 static struct mips16_stub *mips16_stubs;
7994 /* Build a call stub for a mips16 call. A stub is needed if we are
7995 passing any floating point values which should go into the floating
7996 point registers. If we are, and the call turns out to be to a 32
7997 bit function, the stub will be used to move the values into the
7998 floating point registers before calling the 32 bit function. The
7999 linker will magically adjust the function call to either the 16 bit
8000 function or the 32 bit stub, depending upon where the function call
8001 is actually defined.
8003 Similarly, we need a stub if the return value might come back in a
8004 floating point register.
8006 RETVAL is the location of the return value, or null if this is
8007 a call rather than a call_value. FN is the address of the
8008 function and ARG_SIZE is the size of the arguments. FP_CODE
8009 is the code built by function_arg. This function returns a nonzero
8010 value if it builds the call instruction itself. */
8013 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8017 char *secname, *stubname;
8018 struct mips16_stub *l;
8019 tree stubid, stubdecl;
8023 /* We don't need to do anything if we aren't in mips16 mode, or if
8024 we were invoked with the -msoft-float option. */
8025 if (! TARGET_MIPS16 || ! mips16_hard_float)
8028 /* Figure out whether the value might come back in a floating point
8030 fpret = (retval != 0
8031 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8032 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8034 /* We don't need to do anything if there were no floating point
8035 arguments and the value will not be returned in a floating point
8037 if (fp_code == 0 && ! fpret)
8040 /* We don't need to do anything if this is a call to a special
8041 mips16 support function. */
8042 if (GET_CODE (fn) == SYMBOL_REF
8043 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8046 /* This code will only work for o32 and o64 abis. The other ABI's
8047 require more sophisticated support. */
8051 /* We can only handle SFmode and DFmode floating point return
8053 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8056 /* If we're calling via a function pointer, then we must always call
8057 via a stub. There are magic stubs provided in libgcc.a for each
8058 of the required cases. Each of them expects the function address
8059 to arrive in register $2. */
8061 if (GET_CODE (fn) != SYMBOL_REF)
8067 /* ??? If this code is modified to support other ABI's, we need
8068 to handle PARALLEL return values here. */
8070 sprintf (buf, "__mips16_call_stub_%s%d",
8072 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8075 id = get_identifier (buf);
8076 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8078 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8080 if (retval == NULL_RTX)
8081 insn = gen_call_internal (stub_fn, arg_size);
8083 insn = gen_call_value_internal (retval, stub_fn, arg_size);
8084 insn = emit_call_insn (insn);
8086 /* Put the register usage information on the CALL. */
8087 if (GET_CODE (insn) != CALL_INSN)
8089 CALL_INSN_FUNCTION_USAGE (insn) =
8090 gen_rtx_EXPR_LIST (VOIDmode,
8091 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8092 CALL_INSN_FUNCTION_USAGE (insn));
8094 /* If we are handling a floating point return value, we need to
8095 save $18 in the function prologue. Putting a note on the
8096 call will mean that regs_ever_live[$18] will be true if the
8097 call is not eliminated, and we can check that in the prologue
8100 CALL_INSN_FUNCTION_USAGE (insn) =
8101 gen_rtx_EXPR_LIST (VOIDmode,
8102 gen_rtx_USE (VOIDmode,
8103 gen_rtx_REG (word_mode, 18)),
8104 CALL_INSN_FUNCTION_USAGE (insn));
8106 /* Return 1 to tell the caller that we've generated the call
8111 /* We know the function we are going to call. If we have already
8112 built a stub, we don't need to do anything further. */
8114 fnname = XSTR (fn, 0);
8115 for (l = mips16_stubs; l != NULL; l = l->next)
8116 if (strcmp (l->name, fnname) == 0)
8121 /* Build a special purpose stub. When the linker sees a
8122 function call in mips16 code, it will check where the target
8123 is defined. If the target is a 32 bit call, the linker will
8124 search for the section defined here. It can tell which
8125 symbol this section is associated with by looking at the
8126 relocation information (the name is unreliable, since this
8127 might be a static function). If such a section is found, the
8128 linker will redirect the call to the start of the magic
8131 If the function does not return a floating point value, the
8132 special stub section is named
8135 If the function does return a floating point value, the stub
8137 .mips16.call.fp.FNNAME
8140 secname = (char *) alloca (strlen (fnname) + 40);
8141 sprintf (secname, ".mips16.call.%s%s",
8144 stubname = (char *) alloca (strlen (fnname) + 20);
8145 sprintf (stubname, "__call_stub_%s%s",
8148 stubid = get_identifier (stubname);
8149 stubdecl = build_decl (FUNCTION_DECL, stubid,
8150 build_function_type (void_type_node, NULL_TREE));
8151 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8153 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8155 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8159 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8161 fprintf (asm_out_file, "%s%s",
8162 need_comma ? ", " : "",
8163 (f & 3) == 1 ? "float" : "double");
8166 fprintf (asm_out_file, ")\n");
8168 fprintf (asm_out_file, "\t.set\tnomips16\n");
8169 assemble_start_function (stubdecl, stubname);
8171 if (!FUNCTION_NAME_ALREADY_DECLARED)
8173 fputs ("\t.ent\t", asm_out_file);
8174 assemble_name (asm_out_file, stubname);
8175 fputs ("\n", asm_out_file);
8177 assemble_name (asm_out_file, stubname);
8178 fputs (":\n", asm_out_file);
8181 /* We build the stub code by hand. That's the only way we can
8182 do it, since we can't generate 32 bit code during a 16 bit
8185 /* We don't want the assembler to insert any nops here. */
8186 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8188 mips16_fp_args (asm_out_file, fp_code, 0);
8192 fprintf (asm_out_file, "\t.set\tnoat\n");
8193 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8195 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8196 fprintf (asm_out_file, "\t.set\tat\n");
8197 /* Unfortunately, we can't fill the jump delay slot. We
8198 can't fill with one of the mtc1 instructions, because the
8199 result is not available for one instruction, so if the
8200 very first instruction in the function refers to the
8201 register, it will see the wrong value. */
8202 fprintf (asm_out_file, "\tnop\n");
8206 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8207 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8208 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8209 /* As above, we can't fill the delay slot. */
8210 fprintf (asm_out_file, "\tnop\n");
8211 if (GET_MODE (retval) == SFmode)
8212 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8213 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8216 if (TARGET_BIG_ENDIAN)
8218 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8219 reg_names[GP_REG_FIRST + 2],
8220 reg_names[FP_REG_FIRST + 1]);
8221 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8222 reg_names[GP_REG_FIRST + 3],
8223 reg_names[FP_REG_FIRST + 0]);
8227 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8228 reg_names[GP_REG_FIRST + 2],
8229 reg_names[FP_REG_FIRST + 0]);
8230 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8231 reg_names[GP_REG_FIRST + 3],
8232 reg_names[FP_REG_FIRST + 1]);
8235 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8236 /* As above, we can't fill the delay slot. */
8237 fprintf (asm_out_file, "\tnop\n");
8240 fprintf (asm_out_file, "\t.set\treorder\n");
8242 #ifdef ASM_DECLARE_FUNCTION_SIZE
8243 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8246 if (!FUNCTION_NAME_ALREADY_DECLARED)
8248 fputs ("\t.end\t", asm_out_file);
8249 assemble_name (asm_out_file, stubname);
8250 fputs ("\n", asm_out_file);
8253 fprintf (asm_out_file, "\t.set\tmips16\n");
8255 /* Record this stub. */
8256 l = (struct mips16_stub *) xmalloc (sizeof *l);
8257 l->name = xstrdup (fnname);
8259 l->next = mips16_stubs;
8263 /* If we expect a floating point return value, but we've built a
8264 stub which does not expect one, then we're in trouble. We can't
8265 use the existing stub, because it won't handle the floating point
8266 value. We can't build a new stub, because the linker won't know
8267 which stub to use for the various calls in this object file.
8268 Fortunately, this case is illegal, since it means that a function
8269 was declared in two different ways in a single compilation. */
8270 if (fpret && ! l->fpret)
8271 error ("can not handle inconsistent calls to `%s'", fnname);
8273 /* If we are calling a stub which handles a floating point return
8274 value, we need to arrange to save $18 in the prologue. We do
8275 this by marking the function call as using the register. The
8276 prologue will later see that it is used, and emit code to save
8283 if (retval == NULL_RTX)
8284 insn = gen_call_internal (fn, arg_size);
8286 insn = gen_call_value_internal (retval, fn, arg_size);
8287 insn = emit_call_insn (insn);
8289 if (GET_CODE (insn) != CALL_INSN)
8292 CALL_INSN_FUNCTION_USAGE (insn) =
8293 gen_rtx_EXPR_LIST (VOIDmode,
8294 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8295 CALL_INSN_FUNCTION_USAGE (insn));
8297 /* Return 1 to tell the caller that we've generated the call
8302 /* Return 0 to let the caller generate the call insn. */
8306 /* We keep a list of constants we which we have to add to internal
8307 constant tables in the middle of large functions. */
8311 struct constant *next;
8314 enum machine_mode mode;
8317 /* Add a constant to the list in *PCONSTANTS. */
8320 add_constant (struct constant **pconstants, rtx val, enum machine_mode mode)
8324 for (c = *pconstants; c != NULL; c = c->next)
8325 if (mode == c->mode && rtx_equal_p (val, c->value))
8328 c = (struct constant *) xmalloc (sizeof *c);
8331 c->label = gen_label_rtx ();
8332 c->next = *pconstants;
8337 /* Dump out the constants in CONSTANTS after INSN. */
8340 dump_constants (struct constant *constants, rtx insn)
8350 struct constant *next;
8352 switch (GET_MODE_SIZE (c->mode))
8359 insn = emit_insn_after (gen_align_2 (), insn);
8364 insn = emit_insn_after (gen_align_4 (), insn);
8369 insn = emit_insn_after (gen_align_8 (), insn);
8374 insn = emit_label_after (c->label, insn);
8379 r = gen_consttable_qi (c->value);
8382 r = gen_consttable_hi (c->value);
8385 r = gen_consttable_si (c->value);
8388 r = gen_consttable_sf (c->value);
8391 r = gen_consttable_di (c->value);
8394 r = gen_consttable_df (c->value);
8400 insn = emit_insn_after (r, insn);
8407 emit_barrier_after (insn);
8410 /* Find the symbol in an address expression. */
8413 mips_find_symbol (rtx addr)
8415 if (GET_CODE (addr) == MEM)
8416 addr = XEXP (addr, 0);
8417 while (GET_CODE (addr) == CONST)
8418 addr = XEXP (addr, 0);
8419 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
8421 if (GET_CODE (addr) == PLUS)
8425 l1 = mips_find_symbol (XEXP (addr, 0));
8426 l2 = mips_find_symbol (XEXP (addr, 1));
8427 if (l1 != NULL_RTX && l2 == NULL_RTX)
8429 else if (l1 == NULL_RTX && l2 != NULL_RTX)
8435 /* In mips16 mode, we need to look through the function to check for
8436 PC relative loads that are out of range. */
8439 mips16_lay_out_constants (void)
8441 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
8443 struct constant *constants;
8445 first = get_insns ();
8447 /* Scan the function looking for PC relative loads which may be out
8448 of range. All such loads will either be from the constant table,
8449 or be getting the address of a constant string. If the size of
8450 the function plus the size of the constant table is less than
8451 0x8000, then all loads are in range. */
8454 for (insn = first; insn; insn = NEXT_INSN (insn))
8456 insns_len += get_attr_length (insn);
8458 /* ??? We put switch tables in .text, but we don't define
8459 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8460 compute their lengths correctly. */
8461 if (GET_CODE (insn) == JUMP_INSN)
8465 body = PATTERN (insn);
8466 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8467 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8468 * GET_MODE_SIZE (GET_MODE (body)));
8469 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
8473 /* Store the original value of insns_len in cfun->machine, so
8474 that m16_usym8_4 and m16_usym5_4 can look at it. */
8475 cfun->machine->insns_len = insns_len;
8477 pool_size = get_pool_size ();
8478 if (insns_len + pool_size + mips_string_length < 0x8000)
8481 /* Loop over the insns and figure out what the maximum internal pool
8483 max_internal_pool_size = 0;
8484 for (insn = first; insn; insn = NEXT_INSN (insn))
8486 if (GET_CODE (insn) == INSN
8487 && GET_CODE (PATTERN (insn)) == SET)
8491 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8492 if (src == NULL_RTX)
8494 if (CONSTANT_POOL_ADDRESS_P (src))
8495 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
8496 else if (SYMBOL_REF_FLAG (src))
8497 max_internal_pool_size += GET_MODE_SIZE (Pmode);
8503 first_constant_ref = -1;
8505 for (insn = first; insn; insn = NEXT_INSN (insn))
8507 if (GET_CODE (insn) == INSN
8508 && GET_CODE (PATTERN (insn)) == SET)
8511 enum machine_mode mode = VOIDmode;
8514 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8515 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
8517 /* ??? This is very conservative, which means that we
8518 will generate too many copies of the constant table.
8519 The only solution would seem to be some form of
8521 if (((insns_len - addr)
8522 + max_internal_pool_size
8523 + get_pool_offset (src))
8526 val = get_pool_constant (src);
8527 mode = get_pool_mode (src);
8529 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
8531 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
8533 /* Including all of mips_string_length is conservative,
8534 and so is including all of max_internal_pool_size. */
8535 if (((insns_len - addr)
8536 + max_internal_pool_size
8538 + mips_string_length)
8544 max_internal_pool_size -= Pmode;
8547 if (val != NULL_RTX)
8551 /* This PC relative load is out of range. ??? In the
8552 case of a string constant, we are only guessing that
8553 it is range, since we don't know the offset of a
8554 particular string constant. */
8556 lab = add_constant (&constants, val, mode);
8557 newsrc = gen_rtx_MEM (mode,
8558 gen_rtx_LABEL_REF (VOIDmode, lab));
8559 RTX_UNCHANGING_P (newsrc) = 1;
8560 PATTERN (insn) = gen_rtx_SET (VOIDmode,
8561 SET_DEST (PATTERN (insn)),
8563 INSN_CODE (insn) = -1;
8565 if (first_constant_ref < 0)
8566 first_constant_ref = addr;
8570 addr += get_attr_length (insn);
8572 /* ??? We put switch tables in .text, but we don't define
8573 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8574 compute their lengths correctly. */
8575 if (GET_CODE (insn) == JUMP_INSN)
8579 body = PATTERN (insn);
8580 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8581 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8582 * GET_MODE_SIZE (GET_MODE (body)));
8583 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
8586 if (GET_CODE (insn) == BARRIER)
8588 /* Output any constants we have accumulated. Note that we
8589 don't need to change ADDR, since its only use is
8590 subtraction from INSNS_LEN, and both would be changed by
8592 ??? If the instructions up to the next barrier reuse a
8593 constant, it would often be better to continue
8595 if (constants != NULL)
8596 dump_constants (constants, insn);
8598 first_constant_ref = -1;
8601 if (constants != NULL
8602 && (NEXT_INSN (insn) == NULL
8603 || (first_constant_ref >= 0
8604 && (((addr - first_constant_ref)
8605 + 2 /* for alignment */
8606 + 2 /* for a short jump insn */
8610 /* If we haven't had a barrier within 0x8000 bytes of a
8611 constant reference or we are at the end of the function,
8612 emit a barrier now. */
8614 rtx label, jump, barrier;
8616 label = gen_label_rtx ();
8617 jump = emit_jump_insn_after (gen_jump (label), insn);
8618 JUMP_LABEL (jump) = label;
8619 LABEL_NUSES (label) = 1;
8620 barrier = emit_barrier_after (jump);
8621 emit_label_after (label, barrier);
8622 first_constant_ref = -1;
8626 /* ??? If we output all references to a constant in internal
8627 constants table, we don't need to output the constant in the real
8628 constant table, but we have no way to prevent that. */
8632 /* Subroutine of mips_reorg. If there is a hazard between INSN
8633 and a previous instruction, avoid it by inserting nops after
8636 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8637 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8638 before using the value of that register. *HILO_DELAY counts the
8639 number of instructions since the last hilo hazard (that is,
8640 the number of instructions since the last mflo or mfhi).
8642 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8643 for the next instruction.
8645 LO_REG is an rtx for the LO register, used in dependence checking. */
8648 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8649 rtx *delayed_reg, rtx lo_reg)
8657 pattern = PATTERN (insn);
8659 /* Do not put the whole function in .set noreorder if it contains
8660 an asm statement. We don't know whether there will be hazards
8661 between the asm statement and the gcc-generated code. */
8662 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8663 cfun->machine->all_noreorder_p = false;
8665 /* Ignore zero-length instructions (barriers and the like). */
8666 ninsns = get_attr_length (insn) / 4;
8670 /* Work out how many nops are needed. Note that we only care about
8671 registers that are explicitly mentioned in the instruction's pattern.
8672 It doesn't matter that calls use the argument registers or that they
8673 clobber hi and lo. */
8674 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8675 nops = 2 - *hilo_delay;
8676 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8681 /* Insert the nops between this instruction and the previous one.
8682 Each new nop takes us further from the last hilo hazard. */
8683 *hilo_delay += nops;
8685 emit_insn_after (gen_hazard_nop (), after);
8687 /* Set up the state for the next instruction. */
8688 *hilo_delay += ninsns;
8690 if (INSN_CODE (insn) >= 0)
8691 switch (get_attr_hazard (insn))
8701 set = single_set (insn);
8704 *delayed_reg = SET_DEST (set);
8710 /* Go through the instruction stream and insert nops where necessary.
8711 See if the whole function can then be put into .set noreorder &
8715 mips_avoid_hazards (void)
8717 rtx insn, last_insn, lo_reg, delayed_reg;
8720 /* Recalculate instruction lengths without taking nops into account. */
8721 cfun->machine->ignore_hazard_length_p = true;
8722 shorten_branches (get_insns ());
8724 /* The profiler code uses assembler macros. -mfix-vr4122-bugs
8725 relies on assembler nop insertion. */
8726 cfun->machine->all_noreorder_p = (!current_function_profile
8727 && !TARGET_FIX_VR4122);
8732 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8734 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8737 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8738 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8739 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8740 &hilo_delay, &delayed_reg, lo_reg);
8742 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8743 &delayed_reg, lo_reg);
8750 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8756 mips16_lay_out_constants ();
8757 else if (TARGET_EXPLICIT_RELOCS)
8759 if (mips_flag_delayed_branch)
8760 dbr_schedule (get_insns (), dump_file);
8761 mips_avoid_hazards ();
8765 /* This function does three things:
8767 - Register the special divsi3 and modsi3 functions if -mfix-vr4122-bugs.
8768 - Register the mips16 hardware floating point stubs.
8769 - Register the gofast functions if selected using --enable-gofast. */
8771 #include "config/gofast.h"
8774 mips_init_libfuncs (void)
8776 if (TARGET_FIX_VR4122)
8778 set_optab_libfunc (sdiv_optab, SImode, "__vr4122_divsi3");
8779 set_optab_libfunc (smod_optab, SImode, "__vr4122_modsi3");
8782 if (TARGET_MIPS16 && mips16_hard_float)
8784 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8785 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8786 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8787 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8789 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8790 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8791 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8792 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8793 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8794 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8796 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
8797 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8799 if (TARGET_DOUBLE_FLOAT)
8801 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8802 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8803 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8804 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8806 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8807 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8808 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8809 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8810 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8811 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8813 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8814 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8816 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
8817 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8821 gofast_maybe_init_libfuncs ();
8824 /* Return a number assessing the cost of moving a register in class
8825 FROM to class TO. The classes are expressed using the enumeration
8826 values such as `GENERAL_REGS'. A value of 2 is the default; other
8827 values are interpreted relative to that.
8829 It is not required that the cost always equal 2 when FROM is the
8830 same as TO; on some machines it is expensive to move between
8831 registers if they are not general registers.
8833 If reload sees an insn consisting of a single `set' between two
8834 hard registers, and if `REGISTER_MOVE_COST' applied to their
8835 classes returns a value of 2, reload does not check to ensure that
8836 the constraints of the insn are met. Setting a cost of other than
8837 2 will allow reload to verify that the constraints are met. You
8838 should do this if the `movM' pattern's constraints do not allow
8841 ??? We make the cost of moving from HI/LO into general
8842 registers the same as for one of moving general registers to
8843 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8844 pseudo to HI/LO. This might hurt optimizations though, it
8845 isn't clear if it is wise. And it might not work in all cases. We
8846 could solve the DImode LO reg problem by using a multiply, just
8847 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8848 problem by using divide instructions. divu puts the remainder in
8849 the HI reg, so doing a divide by -1 will move the value in the HI
8850 reg for all values except -1. We could handle that case by using a
8851 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8852 a compare/branch to test the input value to see which instruction
8853 we need to use. This gets pretty messy, but it is feasible. */
8856 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8857 enum reg_class to, enum reg_class from)
8859 if (from == M16_REGS && GR_REG_CLASS_P (to))
8861 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8863 else if (GR_REG_CLASS_P (from))
8867 else if (to == M16_NA_REGS)
8869 else if (GR_REG_CLASS_P (to))
8876 else if (to == FP_REGS)
8878 else if (to == HI_REG || to == LO_REG || to == MD_REGS)
8885 else if (COP_REG_CLASS_P (to))
8889 } /* GR_REG_CLASS_P (from) */
8890 else if (from == FP_REGS)
8892 if (GR_REG_CLASS_P (to))
8894 else if (to == FP_REGS)
8896 else if (to == ST_REGS)
8898 } /* from == FP_REGS */
8899 else if (from == HI_REG || from == LO_REG || from == MD_REGS)
8901 if (GR_REG_CLASS_P (to))
8908 } /* from == HI_REG, etc. */
8909 else if (from == ST_REGS && GR_REG_CLASS_P (to))
8911 else if (COP_REG_CLASS_P (from))
8914 } /* COP_REG_CLASS_P (from) */
8921 /* Return the length of INSN. LENGTH is the initial length computed by
8922 attributes in the machine-description file. */
8925 mips_adjust_insn_length (rtx insn, int length)
8927 /* A unconditional jump has an unfilled delay slot if it is not part
8928 of a sequence. A conditional jump normally has a delay slot, but
8929 does not on MIPS16. */
8930 if (simplejump_p (insn)
8931 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
8932 || GET_CODE (insn) == CALL_INSN)))
8935 /* See how many nops might be needed to avoid hardware hazards. */
8936 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
8937 switch (get_attr_hazard (insn))
8951 /* All MIPS16 instructions are a measly two bytes. */
8959 /* Return an asm sequence to start a noat block and load the address
8960 of a label into $1. */
8963 mips_output_load_label (void)
8965 if (TARGET_EXPLICIT_RELOCS)
8969 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
8972 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
8975 if (ISA_HAS_LOAD_DELAY)
8976 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
8977 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
8981 if (Pmode == DImode)
8982 return "%[dla\t%@,%0";
8984 return "%[la\t%@,%0";
8989 /* Output assembly instructions to peform a conditional branch.
8991 INSN is the branch instruction. OPERANDS[0] is the condition.
8992 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8993 of the first operand to the condition. If TWO_OPERANDS_P is
8994 nonzero the comparison takes two operands; OPERANDS[3] will be the
8997 If INVERTED_P is nonzero we are to branch if the condition does
8998 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
9000 LENGTH is the length (in bytes) of the sequence we are to generate.
9001 That tells us whether to generate a simple conditional branch, or a
9002 reversed conditional branch around a `jr' instruction. */
9004 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
9005 int float_p, int inverted_p, int length)
9007 static char buffer[200];
9008 /* The kind of comparison we are doing. */
9009 enum rtx_code code = GET_CODE (operands[0]);
9010 /* Nonzero if the opcode for the comparison needs a `z' indicating
9011 that it is a comparison against zero. */
9013 /* A string to use in the assembly output to represent the first
9015 const char *op1 = "%z2";
9016 /* A string to use in the assembly output to represent the second
9017 operand. Use the hard-wired zero register if there's no second
9019 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9020 /* The operand-printing string for the comparison. */
9021 const char *const comp = (float_p ? "%F0" : "%C0");
9022 /* The operand-printing string for the inverted comparison. */
9023 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
9025 /* The MIPS processors (for levels of the ISA at least two), have
9026 "likely" variants of each branch instruction. These instructions
9027 annul the instruction in the delay slot if the branch is not
9029 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9031 if (!two_operands_p)
9033 /* To compute whether than A > B, for example, we normally
9034 subtract B from A and then look at the sign bit. But, if we
9035 are doing an unsigned comparison, and B is zero, we don't
9036 have to do the subtraction. Instead, we can just check to
9037 see if A is nonzero. Thus, we change the CODE here to
9038 reflect the simpler comparison operation. */
9050 /* A condition which will always be true. */
9056 /* A condition which will always be false. */
9062 /* Not a special case. */
9067 /* Relative comparisons are always done against zero. But
9068 equality comparisons are done between two operands, and therefore
9069 do not require a `z' in the assembly language output. */
9070 need_z_p = (!float_p && code != EQ && code != NE);
9071 /* For comparisons against zero, the zero is not provided
9076 /* Begin by terminating the buffer. That way we can always use
9077 strcat to add to it. */
9084 /* Just a simple conditional branch. */
9086 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
9087 inverted_p ? inverted_comp : comp);
9089 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
9090 inverted_p ? inverted_comp : comp,
9091 need_z_p ? "z" : "",
9101 /* Generate a reversed conditional branch around ` j'
9114 If the original branch was a likely branch, the delay slot
9115 must be executed only if the branch is taken, so generate:
9127 When generating non-embedded PIC, instead of:
9140 rtx target = gen_label_rtx ();
9142 orig_target = operands[1];
9143 operands[1] = target;
9144 /* Generate the reversed comparison. This takes four
9147 sprintf (buffer, "%%*b%s\t%%Z2%%1",
9148 inverted_p ? comp : inverted_comp);
9150 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
9151 inverted_p ? comp : inverted_comp,
9152 need_z_p ? "z" : "",
9155 output_asm_insn (buffer, operands);
9157 if (length != 16 && length != 28 && ! mips_branch_likely)
9159 /* Output delay slot instruction. */
9160 rtx insn = final_sequence;
9161 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9162 optimize, 0, 1, NULL);
9163 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9166 output_asm_insn ("%#", 0);
9169 output_asm_insn ("j\t%0", &orig_target);
9172 output_asm_insn (mips_output_load_label (), &orig_target);
9173 output_asm_insn ("jr\t%@%]", 0);
9176 if (length != 16 && length != 28 && mips_branch_likely)
9178 /* Output delay slot instruction. */
9179 rtx insn = final_sequence;
9180 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9181 optimize, 0, 1, NULL);
9182 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9185 output_asm_insn ("%#", 0);
9187 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9188 CODE_LABEL_NUMBER (target));
9201 /* Used to output div or ddiv instruction DIVISION, which has the operands
9202 given by OPERANDS. Add in a divide-by-zero check if needed.
9204 When working around R4000 and R4400 errata, we need to make sure that
9205 the division is not immediately followed by a shift[1][2]. We also
9206 need to stop the division from being put into a branch delay slot[3].
9207 The easiest way to avoid both problems is to add a nop after the
9208 division. When a divide-by-zero check is needed, this nop can be
9209 used to fill the branch delay slot.
9211 [1] If a double-word or a variable shift executes immediately
9212 after starting an integer division, the shift may give an
9213 incorrect result. See quotations of errata #16 and #28 from
9214 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9215 in mips.md for details.
9217 [2] A similar bug to [1] exists for all revisions of the
9218 R4000 and the R4400 when run in an MC configuration.
9219 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9221 "19. In this following sequence:
9223 ddiv (or ddivu or div or divu)
9224 dsll32 (or dsrl32, dsra32)
9226 if an MPT stall occurs, while the divide is slipping the cpu
9227 pipeline, then the following double shift would end up with an
9230 Workaround: The compiler needs to avoid generating any
9231 sequence with divide followed by extended double shift."
9233 This erratum is also present in "MIPS R4400MC Errata, Processor
9234 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9235 & 3.0" as errata #10 and #4, respectively.
9237 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9238 (also valid for MIPS R4000MC processors):
9240 "52. R4000SC: This bug does not apply for the R4000PC.
9242 There are two flavors of this bug:
9244 1) If the instruction just after divide takes an RF exception
9245 (tlb-refill, tlb-invalid) and gets an instruction cache
9246 miss (both primary and secondary) and the line which is
9247 currently in secondary cache at this index had the first
9248 data word, where the bits 5..2 are set, then R4000 would
9249 get a wrong result for the div.
9254 ------------------- # end-of page. -tlb-refill
9259 ------------------- # end-of page. -tlb-invalid
9262 2) If the divide is in the taken branch delay slot, where the
9263 target takes RF exception and gets an I-cache miss for the
9264 exception vector or where I-cache miss occurs for the
9265 target address, under the above mentioned scenarios, the
9266 div would get wrong results.
9269 j r2 # to next page mapped or unmapped
9270 div r8,r9 # this bug would be there as long
9271 # as there is an ICache miss and
9272 nop # the "data pattern" is present
9275 beq r0, r0, NextPage # to Next page
9279 This bug is present for div, divu, ddiv, and ddivu
9282 Workaround: For item 1), OS could make sure that the next page
9283 after the divide instruction is also mapped. For item 2), the
9284 compiler could make sure that the divide instruction is not in
9285 the branch delay slot."
9287 These processors have PRId values of 0x00004220 and 0x00004300 for
9288 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9291 mips_output_division (const char *division, rtx *operands)
9296 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9298 output_asm_insn (s, operands);
9301 if (TARGET_CHECK_ZERO_DIV)
9305 output_asm_insn (s, operands);
9306 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9310 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9311 output_asm_insn (s, operands);
9312 s = "break\t7%)\n1:";
9318 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9319 with a final "000" replaced by "k". Ignore case.
9321 Note: this function is shared between GCC and GAS. */
9324 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9326 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9327 given++, canonical++;
9329 return ((*given == 0 && *canonical == 0)
9330 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9334 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9335 CPU name. We've traditionally allowed a lot of variation here.
9337 Note: this function is shared between GCC and GAS. */
9340 mips_matching_cpu_name_p (const char *canonical, const char *given)
9342 /* First see if the name matches exactly, or with a final "000"
9344 if (mips_strict_matching_cpu_name_p (canonical, given))
9347 /* If not, try comparing based on numerical designation alone.
9348 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9349 if (TOLOWER (*given) == 'r')
9351 if (!ISDIGIT (*given))
9354 /* Skip over some well-known prefixes in the canonical name,
9355 hoping to find a number there too. */
9356 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9358 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9360 else if (TOLOWER (canonical[0]) == 'r')
9363 return mips_strict_matching_cpu_name_p (canonical, given);
9367 /* Parse an option that takes the name of a processor as its argument.
9368 OPTION is the name of the option and CPU_STRING is the argument.
9369 Return the corresponding processor enumeration if the CPU_STRING is
9370 recognized, otherwise report an error and return null.
9372 A similar function exists in GAS. */
9374 static const struct mips_cpu_info *
9375 mips_parse_cpu (const char *option, const char *cpu_string)
9377 const struct mips_cpu_info *p;
9380 /* In the past, we allowed upper-case CPU names, but it doesn't
9381 work well with the multilib machinery. */
9382 for (s = cpu_string; *s != 0; s++)
9385 warning ("the cpu name must be lower case");
9389 /* 'from-abi' selects the most compatible architecture for the given
9390 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9391 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9392 version. Look first at the -mgp options, if given, otherwise base
9393 the choice on MASK_64BIT in TARGET_DEFAULT. */
9394 if (strcasecmp (cpu_string, "from-abi") == 0)
9395 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9396 : ABI_NEEDS_64BIT_REGS ? 3
9397 : (TARGET_64BIT ? 3 : 1));
9399 /* 'default' has traditionally been a no-op. Probably not very useful. */
9400 if (strcasecmp (cpu_string, "default") == 0)
9403 for (p = mips_cpu_info_table; p->name != 0; p++)
9404 if (mips_matching_cpu_name_p (p->name, cpu_string))
9407 error ("bad value (%s) for %s", cpu_string, option);
9412 /* Return the processor associated with the given ISA level, or null
9413 if the ISA isn't valid. */
9415 static const struct mips_cpu_info *
9416 mips_cpu_info_from_isa (int isa)
9418 const struct mips_cpu_info *p;
9420 for (p = mips_cpu_info_table; p->name != 0; p++)
9427 /* Adjust the cost of INSN based on the relationship between INSN that
9428 is dependent on DEP_INSN through the dependence LINK. The default
9429 is to make no adjustment to COST.
9431 On the MIPS, ignore the cost of anti- and output-dependencies. */
9433 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9434 rtx dep ATTRIBUTE_UNUSED, int cost)
9436 if (REG_NOTE_KIND (link) != 0)
9437 return 0; /* Anti or output dependence. */
9441 /* Implement HARD_REGNO_NREGS. The size of FP registers are controlled
9442 by UNITS_PER_FPREG. All other registers are word sized. */
9445 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9447 if (! FP_REG_P (regno))
9448 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9450 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9453 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9454 all BLKmode objects are returned in memory. Under the new (N32 and
9455 64-bit MIPS ABIs) small structures are returned in a register.
9456 Objects with varying size must still be returned in memory, of
9460 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9463 return (TYPE_MODE (type) == BLKmode);
9465 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9466 || (int_size_in_bytes (type) == -1));
9470 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9472 return !TARGET_OLDABI;
9476 mips_issue_rate (void)
9480 case PROCESSOR_R5400:
9481 case PROCESSOR_R5500:
9482 case PROCESSOR_R7000:
9483 case PROCESSOR_R9000:
9494 /* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
9495 processors that have a DFA pipeline description. */
9498 mips_use_dfa_pipeline_interface (void)
9502 case PROCESSOR_R5400:
9503 case PROCESSOR_R5500:
9504 case PROCESSOR_R7000:
9505 case PROCESSOR_R9000:
9506 case PROCESSOR_SR71000:
9516 mips_emit_prefetch (rtx *operands)
9518 int write = INTVAL (operands[1]);
9519 int locality = INTVAL (operands[2]);
9520 int indexed = GET_CODE (operands[3]) == REG;
9525 code = (write ? 5 : 4); /* store_streamed / load_streamed. */
9526 else if (locality <= 2)
9527 code = (write ? 1 : 0); /* store / load. */
9529 code = (write ? 7 : 6); /* store_retained / load_retained. */
9531 sprintf (buffer, "%s\t%d,%%3(%%0)", indexed ? "prefx" : "pref", code);
9532 output_asm_insn (buffer, operands);
9539 /* Output assembly to switch to section NAME with attribute FLAGS. */
9542 irix_asm_named_section_1 (const char *name, unsigned int flags,
9545 unsigned int sh_type, sh_flags, sh_entsize;
9548 if (!(flags & SECTION_DEBUG))
9549 sh_flags |= 2; /* SHF_ALLOC */
9550 if (flags & SECTION_WRITE)
9551 sh_flags |= 1; /* SHF_WRITE */
9552 if (flags & SECTION_CODE)
9553 sh_flags |= 4; /* SHF_EXECINSTR */
9554 if (flags & SECTION_SMALL)
9555 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
9556 if (strcmp (name, ".debug_frame") == 0)
9557 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
9558 if (flags & SECTION_DEBUG)
9559 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
9560 else if (flags & SECTION_BSS)
9561 sh_type = 8; /* SHT_NOBITS */
9563 sh_type = 1; /* SHT_PROGBITS */
9565 if (flags & SECTION_CODE)
9570 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
9571 name, sh_type, sh_flags, sh_entsize, align);
9575 irix_asm_named_section (const char *name, unsigned int flags)
9577 if (TARGET_SGI_O32_AS)
9578 default_no_named_section (name, flags);
9579 else if (mips_abi == ABI_32 && TARGET_GAS)
9580 default_elf_asm_named_section (name, flags);
9582 irix_asm_named_section_1 (name, flags, 0);
9585 /* In addition to emitting a .align directive, record the maximum
9586 alignment requested for the current section. */
9588 struct GTY (()) irix_section_align_entry
9595 static htab_t irix_section_align_htab;
9596 static FILE *irix_orig_asm_out_file;
9599 irix_section_align_entry_eq (const void *p1, const void *p2)
9601 const struct irix_section_align_entry *old = p1;
9602 const char *new = p2;
9604 return strcmp (old->name, new) == 0;
9608 irix_section_align_entry_hash (const void *p)
9610 const struct irix_section_align_entry *old = p;
9611 return htab_hash_string (old->name);
9615 irix_asm_output_align (FILE *file, unsigned int log)
9617 const char *section = current_section_name ();
9618 struct irix_section_align_entry **slot, *entry;
9620 if (mips_abi != ABI_32)
9625 slot = (struct irix_section_align_entry **)
9626 htab_find_slot_with_hash (irix_section_align_htab, section,
9627 htab_hash_string (section), INSERT);
9631 entry = (struct irix_section_align_entry *)
9632 xmalloc (sizeof (struct irix_section_align_entry));
9634 entry->name = section;
9636 entry->flags = current_section_flags ();
9638 else if (entry->log < log)
9642 fprintf (file, "\t.align\t%u\n", log);
9645 /* The IRIX assembler does not record alignment from .align directives,
9646 but takes it from the first .section directive seen. Play file
9647 switching games so that we can emit a .section directive at the
9648 beginning of the file with the proper alignment attached. */
9651 irix_file_start (void)
9655 if (mips_abi == ABI_32)
9658 irix_orig_asm_out_file = asm_out_file;
9659 asm_out_file = tmpfile ();
9661 irix_section_align_htab = htab_create (31, irix_section_align_entry_hash,
9662 irix_section_align_entry_eq, NULL);
9666 irix_section_align_1 (void **slot, void *data ATTRIBUTE_UNUSED)
9668 const struct irix_section_align_entry *entry
9669 = *(const struct irix_section_align_entry **) slot;
9671 irix_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
9676 copy_file_data (FILE *to, FILE *from)
9682 fatal_error ("can't rewind temp file: %m");
9684 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
9685 if (fwrite (buffer, 1, len, to) != len)
9686 fatal_error ("can't write to output file: %m");
9689 fatal_error ("can't read from temp file: %m");
9692 fatal_error ("can't close temp file: %m");
9696 irix_file_end (void)
9698 if (mips_abi != ABI_32)
9700 /* Emit section directives with the proper alignment at the top of the
9701 real output file. */
9702 FILE *temp = asm_out_file;
9703 asm_out_file = irix_orig_asm_out_file;
9704 htab_traverse (irix_section_align_htab, irix_section_align_1, NULL);
9706 /* Copy the data emitted to the temp file to the real output file. */
9707 copy_file_data (asm_out_file, temp);
9714 /* Implement TARGET_SECTION_TYPE_FLAGS. Make sure that .sdata and
9715 .sbss sections get the SECTION_SMALL flag: this isn't set by the
9719 irix_section_type_flags (tree decl, const char *section, int relocs_p)
9723 flags = default_section_type_flags (decl, section, relocs_p);
9725 if (strcmp (section, ".sdata") == 0
9726 || strcmp (section, ".sbss") == 0
9727 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9728 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9729 flags |= SECTION_SMALL;
9734 #endif /* TARGET_IRIX */
9736 #include "gt-mips.h"