1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Classifies an address.
132 A natural register + offset address. The register satisfies
133 mips_valid_base_register_p and the offset is a const_arith_operand.
136 A LO_SUM rtx. The first operand is a valid base register and
137 the second operand is a symbolic address.
140 A signed 16-bit constant address.
143 A constant symbolic address. */
144 enum mips_address_type {
151 /* Macros to create an enumeration identifier for a function prototype. */
152 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
153 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
154 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
155 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
157 /* Classifies the prototype of a built-in function. */
158 enum mips_function_type {
159 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
160 #include "config/mips/mips-ftypes.def"
161 #undef DEF_MIPS_FTYPE
165 /* Specifies how a built-in function should be converted into rtl. */
166 enum mips_builtin_type {
167 /* The function corresponds directly to an .md pattern. The return
168 value is mapped to operand 0 and the arguments are mapped to
169 operands 1 and above. */
172 /* The function corresponds directly to an .md pattern. There is no return
173 value and the arguments are mapped to operands 0 and above. */
174 MIPS_BUILTIN_DIRECT_NO_TARGET,
176 /* The function corresponds to a comparison instruction followed by
177 a mips_cond_move_tf_ps pattern. The first two arguments are the
178 values to compare and the second two arguments are the vector
179 operands for the movt.ps or movf.ps instruction (in assembly order). */
183 /* The function corresponds to a V2SF comparison instruction. Operand 0
184 of this instruction is the result of the comparison, which has mode
185 CCV2 or CCV4. The function arguments are mapped to operands 1 and
186 above. The function's return value is an SImode boolean that is
187 true under the following conditions:
189 MIPS_BUILTIN_CMP_ANY: one of the registers is true
190 MIPS_BUILTIN_CMP_ALL: all of the registers are true
191 MIPS_BUILTIN_CMP_LOWER: the first register is true
192 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
193 MIPS_BUILTIN_CMP_ANY,
194 MIPS_BUILTIN_CMP_ALL,
195 MIPS_BUILTIN_CMP_UPPER,
196 MIPS_BUILTIN_CMP_LOWER,
198 /* As above, but the instruction only sets a single $fcc register. */
199 MIPS_BUILTIN_CMP_SINGLE,
201 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
202 MIPS_BUILTIN_BPOSGE32
205 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
206 #define MIPS_FP_CONDITIONS(MACRO) \
224 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
225 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
226 enum mips_fp_condition {
227 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
230 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
231 #define STRINGIFY(X) #X
232 static const char *const mips_fp_conditions[] = {
233 MIPS_FP_CONDITIONS (STRINGIFY)
236 /* Information about a function's frame layout. */
237 struct mips_frame_info GTY(()) {
238 /* The size of the frame in bytes. */
239 HOST_WIDE_INT total_size;
241 /* The number of bytes allocated to variables. */
242 HOST_WIDE_INT var_size;
244 /* The number of bytes allocated to outgoing function arguments. */
245 HOST_WIDE_INT args_size;
247 /* The number of bytes allocated to the .cprestore slot, or 0 if there
249 HOST_WIDE_INT cprestore_size;
251 /* Bit X is set if the function saves or restores GPR X. */
254 /* Likewise FPR X. */
257 /* The number of GPRs and FPRs saved. */
261 /* The offset of the topmost GPR and FPR save slots from the top of
262 the frame, or zero if no such slots are needed. */
263 HOST_WIDE_INT gp_save_offset;
264 HOST_WIDE_INT fp_save_offset;
266 /* Likewise, but giving offsets from the bottom of the frame. */
267 HOST_WIDE_INT gp_sp_offset;
268 HOST_WIDE_INT fp_sp_offset;
270 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
271 HOST_WIDE_INT arg_pointer_offset;
273 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
274 HOST_WIDE_INT hard_frame_pointer_offset;
277 struct machine_function GTY(()) {
278 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
279 rtx mips16_gp_pseudo_rtx;
281 /* The number of extra stack bytes taken up by register varargs.
282 This area is allocated by the callee at the very top of the frame. */
285 /* The current frame information, calculated by mips_compute_frame_info. */
286 struct mips_frame_info frame;
288 /* The register to use as the function's global pointer. */
289 unsigned int global_pointer;
291 /* True if mips_adjust_insn_length should ignore an instruction's
293 bool ignore_hazard_length_p;
295 /* True if the whole function is suitable for .set noreorder and
297 bool all_noreorder_p;
299 /* True if the function is known to have an instruction that needs $gp. */
302 /* True if we have emitted an instruction to initialize
303 mips16_gp_pseudo_rtx. */
304 bool initialized_mips16_gp_pseudo_p;
307 /* Information about a single argument. */
308 struct mips_arg_info {
309 /* True if the argument is passed in a floating-point register, or
310 would have been if we hadn't run out of registers. */
313 /* The number of words passed in registers, rounded up. */
314 unsigned int reg_words;
316 /* For EABI, the offset of the first register from GP_ARG_FIRST or
317 FP_ARG_FIRST. For other ABIs, the offset of the first register from
318 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
319 comment for details).
321 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
323 unsigned int reg_offset;
325 /* The number of words that must be passed on the stack, rounded up. */
326 unsigned int stack_words;
328 /* The offset from the start of the stack overflow area of the argument's
329 first stack word. Only meaningful when STACK_WORDS is nonzero. */
330 unsigned int stack_offset;
333 /* Information about an address described by mips_address_type.
339 REG is the base register and OFFSET is the constant offset.
342 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
343 is the type of symbol it references.
346 SYMBOL_TYPE is the type of symbol that the address references. */
347 struct mips_address_info {
348 enum mips_address_type type;
351 enum mips_symbol_type symbol_type;
354 /* One stage in a constant building sequence. These sequences have
358 A = A CODE[1] VALUE[1]
359 A = A CODE[2] VALUE[2]
362 where A is an accumulator, each CODE[i] is a binary rtl operation
363 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
364 struct mips_integer_op {
366 unsigned HOST_WIDE_INT value;
369 /* The largest number of operations needed to load an integer constant.
370 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
371 When the lowest bit is clear, we can try, but reject a sequence with
372 an extra SLL at the end. */
373 #define MIPS_MAX_INTEGER_OPS 7
375 /* Information about a MIPS16e SAVE or RESTORE instruction. */
376 struct mips16e_save_restore_info {
377 /* The number of argument registers saved by a SAVE instruction.
378 0 for RESTORE instructions. */
381 /* Bit X is set if the instruction saves or restores GPR X. */
384 /* The total number of bytes to allocate. */
388 /* Global variables for machine-dependent things. */
390 /* The -G setting, or the configuration's default small-data limit if
391 no -G option is given. */
392 static unsigned int mips_small_data_threshold;
394 /* The number of file directives written by mips_output_filename. */
395 int num_source_filenames;
397 /* The name that appeared in the last .file directive written by
398 mips_output_filename, or "" if mips_output_filename hasn't
399 written anything yet. */
400 const char *current_function_file = "";
402 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
405 /* Arrays that map GCC register numbers to debugger register numbers. */
406 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
407 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
409 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
414 /* True if we're writing out a branch-likely instruction rather than a
416 static bool mips_branch_likely;
418 /* The operands passed to the last cmpMM expander. */
421 /* The current instruction-set architecture. */
422 enum processor_type mips_arch;
423 const struct mips_cpu_info *mips_arch_info;
425 /* The processor that we should tune the code for. */
426 enum processor_type mips_tune;
427 const struct mips_cpu_info *mips_tune_info;
429 /* The ISA level associated with mips_arch. */
432 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
433 static const struct mips_cpu_info *mips_isa_option_info;
435 /* Which ABI to use. */
436 int mips_abi = MIPS_ABI_DEFAULT;
438 /* Which cost information to use. */
439 const struct mips_rtx_cost_data *mips_cost;
441 /* The ambient target flags, excluding MASK_MIPS16. */
442 static int mips_base_target_flags;
444 /* True if MIPS16 is the default mode. */
445 bool mips_base_mips16;
447 /* The ambient values of other global variables. */
448 static int mips_base_delayed_branch; /* flag_delayed_branch */
449 static int mips_base_schedule_insns; /* flag_schedule_insns */
450 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
451 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
452 static int mips_base_align_loops; /* align_loops */
453 static int mips_base_align_jumps; /* align_jumps */
454 static int mips_base_align_functions; /* align_functions */
456 /* The -mcode-readable setting. */
457 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
459 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
460 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
462 /* Index C is true if character C is a valid PRINT_OPERAND punctation
464 bool mips_print_operand_punct[256];
466 static GTY (()) int mips_output_filename_first_time = 1;
468 /* mips_split_p[X] is true if symbols of type X can be split by
469 mips_split_symbol. */
470 bool mips_split_p[NUM_SYMBOL_TYPES];
472 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
473 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
474 if they are matched by a special .md file pattern. */
475 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
477 /* Likewise for HIGHs. */
478 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
480 /* Index R is the smallest register class that contains register R. */
481 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
482 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
483 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
484 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
485 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
486 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
487 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
488 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
489 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
490 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
491 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
492 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
493 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
494 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
495 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
496 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
497 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
498 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
499 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
500 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
501 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
502 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
503 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
504 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
505 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
506 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
507 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
508 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
509 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
510 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
511 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
512 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
513 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
514 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
515 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
516 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
517 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
518 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
519 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
520 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
521 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
522 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
523 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
524 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
525 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
526 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
527 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
528 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
531 /* The value of TARGET_ATTRIBUTE_TABLE. */
532 const struct attribute_spec mips_attribute_table[] = {
533 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
534 { "long_call", 0, 0, false, true, true, NULL },
535 { "far", 0, 0, false, true, true, NULL },
536 { "near", 0, 0, false, true, true, NULL },
537 /* We would really like to treat "mips16" and "nomips16" as type
538 attributes, but GCC doesn't provide the hooks we need to support
539 the right conversion rules. As declaration attributes, they affect
540 code generation but don't carry other semantics. */
541 { "mips16", 0, 0, true, false, false, NULL },
542 { "nomips16", 0, 0, true, false, false, NULL },
543 { NULL, 0, 0, false, false, false, NULL }
546 /* A table describing all the processors GCC knows about. Names are
547 matched in the order listed. The first mention of an ISA level is
548 taken as the canonical name for that ISA.
550 To ease comparison, please keep this table in the same order
551 as GAS's mips_cpu_info_table. Please also make sure that
552 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
553 options correctly. */
554 static const struct mips_cpu_info mips_cpu_info_table[] = {
555 /* Entries for generic ISAs. */
556 { "mips1", PROCESSOR_R3000, 1, 0 },
557 { "mips2", PROCESSOR_R6000, 2, 0 },
558 { "mips3", PROCESSOR_R4000, 3, 0 },
559 { "mips4", PROCESSOR_R8000, 4, 0 },
560 /* Prefer not to use branch-likely instructions for generic MIPS32rX
561 and MIPS64rX code. The instructions were officially deprecated
562 in revisions 2 and earlier, but revision 3 is likely to downgrade
563 that to a recommendation to avoid the instructions in code that
564 isn't tuned to a specific processor. */
565 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
566 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
567 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
568 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
569 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
571 /* MIPS I processors. */
572 { "r3000", PROCESSOR_R3000, 1, 0 },
573 { "r2000", PROCESSOR_R3000, 1, 0 },
574 { "r3900", PROCESSOR_R3900, 1, 0 },
576 /* MIPS II processors. */
577 { "r6000", PROCESSOR_R6000, 2, 0 },
579 /* MIPS III processors. */
580 { "r4000", PROCESSOR_R4000, 3, 0 },
581 { "vr4100", PROCESSOR_R4100, 3, 0 },
582 { "vr4111", PROCESSOR_R4111, 3, 0 },
583 { "vr4120", PROCESSOR_R4120, 3, 0 },
584 { "vr4130", PROCESSOR_R4130, 3, 0 },
585 { "vr4300", PROCESSOR_R4300, 3, 0 },
586 { "r4400", PROCESSOR_R4000, 3, 0 },
587 { "r4600", PROCESSOR_R4600, 3, 0 },
588 { "orion", PROCESSOR_R4600, 3, 0 },
589 { "r4650", PROCESSOR_R4650, 3, 0 },
590 /* ST Loongson 2E/2F processors. */
591 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
592 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
594 /* MIPS IV processors. */
595 { "r8000", PROCESSOR_R8000, 4, 0 },
596 { "vr5000", PROCESSOR_R5000, 4, 0 },
597 { "vr5400", PROCESSOR_R5400, 4, 0 },
598 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
599 { "rm7000", PROCESSOR_R7000, 4, 0 },
600 { "rm9000", PROCESSOR_R9000, 4, 0 },
602 /* MIPS32 processors. */
603 { "4kc", PROCESSOR_4KC, 32, 0 },
604 { "4km", PROCESSOR_4KC, 32, 0 },
605 { "4kp", PROCESSOR_4KP, 32, 0 },
606 { "4ksc", PROCESSOR_4KC, 32, 0 },
608 /* MIPS32 Release 2 processors. */
609 { "m4k", PROCESSOR_M4K, 33, 0 },
610 { "4kec", PROCESSOR_4KC, 33, 0 },
611 { "4kem", PROCESSOR_4KC, 33, 0 },
612 { "4kep", PROCESSOR_4KP, 33, 0 },
613 { "4ksd", PROCESSOR_4KC, 33, 0 },
615 { "24kc", PROCESSOR_24KC, 33, 0 },
616 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
617 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
618 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
619 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
620 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
622 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
623 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
624 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
625 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
626 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
627 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
629 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
630 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
631 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
632 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
633 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
634 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
636 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
637 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
638 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
639 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
640 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
641 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
642 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
644 /* MIPS64 processors. */
645 { "5kc", PROCESSOR_5KC, 64, 0 },
646 { "5kf", PROCESSOR_5KF, 64, 0 },
647 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
648 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
649 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
650 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
651 { "xlr", PROCESSOR_XLR, 64, 0 }
654 /* Default costs. If these are used for a processor we should look
655 up the actual costs. */
656 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
657 COSTS_N_INSNS (7), /* fp_mult_sf */ \
658 COSTS_N_INSNS (8), /* fp_mult_df */ \
659 COSTS_N_INSNS (23), /* fp_div_sf */ \
660 COSTS_N_INSNS (36), /* fp_div_df */ \
661 COSTS_N_INSNS (10), /* int_mult_si */ \
662 COSTS_N_INSNS (10), /* int_mult_di */ \
663 COSTS_N_INSNS (69), /* int_div_si */ \
664 COSTS_N_INSNS (69), /* int_div_di */ \
665 2, /* branch_cost */ \
666 4 /* memory_latency */
668 /* Floating-point costs for processors without an FPU. Just assume that
669 all floating-point libcalls are very expensive. */
670 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
671 COSTS_N_INSNS (256), /* fp_mult_sf */ \
672 COSTS_N_INSNS (256), /* fp_mult_df */ \
673 COSTS_N_INSNS (256), /* fp_div_sf */ \
674 COSTS_N_INSNS (256) /* fp_div_df */
676 /* Costs to use when optimizing for size. */
677 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
678 COSTS_N_INSNS (1), /* fp_add */
679 COSTS_N_INSNS (1), /* fp_mult_sf */
680 COSTS_N_INSNS (1), /* fp_mult_df */
681 COSTS_N_INSNS (1), /* fp_div_sf */
682 COSTS_N_INSNS (1), /* fp_div_df */
683 COSTS_N_INSNS (1), /* int_mult_si */
684 COSTS_N_INSNS (1), /* int_mult_di */
685 COSTS_N_INSNS (1), /* int_div_si */
686 COSTS_N_INSNS (1), /* int_div_di */
688 4 /* memory_latency */
691 /* Costs to use when optimizing for speed, indexed by processor. */
692 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
694 COSTS_N_INSNS (2), /* fp_add */
695 COSTS_N_INSNS (4), /* fp_mult_sf */
696 COSTS_N_INSNS (5), /* fp_mult_df */
697 COSTS_N_INSNS (12), /* fp_div_sf */
698 COSTS_N_INSNS (19), /* fp_div_df */
699 COSTS_N_INSNS (12), /* int_mult_si */
700 COSTS_N_INSNS (12), /* int_mult_di */
701 COSTS_N_INSNS (35), /* int_div_si */
702 COSTS_N_INSNS (35), /* int_div_di */
704 4 /* memory_latency */
708 COSTS_N_INSNS (6), /* int_mult_si */
709 COSTS_N_INSNS (6), /* int_mult_di */
710 COSTS_N_INSNS (36), /* int_div_si */
711 COSTS_N_INSNS (36), /* int_div_di */
713 4 /* memory_latency */
717 COSTS_N_INSNS (36), /* int_mult_si */
718 COSTS_N_INSNS (36), /* int_mult_di */
719 COSTS_N_INSNS (37), /* int_div_si */
720 COSTS_N_INSNS (37), /* int_div_di */
722 4 /* memory_latency */
726 COSTS_N_INSNS (4), /* int_mult_si */
727 COSTS_N_INSNS (11), /* int_mult_di */
728 COSTS_N_INSNS (36), /* int_div_si */
729 COSTS_N_INSNS (68), /* int_div_di */
731 4 /* memory_latency */
734 COSTS_N_INSNS (4), /* fp_add */
735 COSTS_N_INSNS (4), /* fp_mult_sf */
736 COSTS_N_INSNS (5), /* fp_mult_df */
737 COSTS_N_INSNS (17), /* fp_div_sf */
738 COSTS_N_INSNS (32), /* fp_div_df */
739 COSTS_N_INSNS (4), /* int_mult_si */
740 COSTS_N_INSNS (11), /* int_mult_di */
741 COSTS_N_INSNS (36), /* int_div_si */
742 COSTS_N_INSNS (68), /* int_div_di */
744 4 /* memory_latency */
747 COSTS_N_INSNS (4), /* fp_add */
748 COSTS_N_INSNS (4), /* fp_mult_sf */
749 COSTS_N_INSNS (5), /* fp_mult_df */
750 COSTS_N_INSNS (17), /* fp_div_sf */
751 COSTS_N_INSNS (32), /* fp_div_df */
752 COSTS_N_INSNS (4), /* int_mult_si */
753 COSTS_N_INSNS (7), /* int_mult_di */
754 COSTS_N_INSNS (42), /* int_div_si */
755 COSTS_N_INSNS (72), /* int_div_di */
757 4 /* memory_latency */
761 COSTS_N_INSNS (5), /* int_mult_si */
762 COSTS_N_INSNS (5), /* int_mult_di */
763 COSTS_N_INSNS (41), /* int_div_si */
764 COSTS_N_INSNS (41), /* int_div_di */
766 4 /* memory_latency */
769 COSTS_N_INSNS (8), /* fp_add */
770 COSTS_N_INSNS (8), /* fp_mult_sf */
771 COSTS_N_INSNS (10), /* fp_mult_df */
772 COSTS_N_INSNS (34), /* fp_div_sf */
773 COSTS_N_INSNS (64), /* fp_div_df */
774 COSTS_N_INSNS (5), /* int_mult_si */
775 COSTS_N_INSNS (5), /* int_mult_di */
776 COSTS_N_INSNS (41), /* int_div_si */
777 COSTS_N_INSNS (41), /* int_div_di */
779 4 /* memory_latency */
782 COSTS_N_INSNS (4), /* fp_add */
783 COSTS_N_INSNS (4), /* fp_mult_sf */
784 COSTS_N_INSNS (5), /* fp_mult_df */
785 COSTS_N_INSNS (17), /* fp_div_sf */
786 COSTS_N_INSNS (32), /* fp_div_df */
787 COSTS_N_INSNS (5), /* int_mult_si */
788 COSTS_N_INSNS (5), /* int_mult_di */
789 COSTS_N_INSNS (41), /* int_div_si */
790 COSTS_N_INSNS (41), /* int_div_di */
792 4 /* memory_latency */
796 COSTS_N_INSNS (5), /* int_mult_si */
797 COSTS_N_INSNS (5), /* int_mult_di */
798 COSTS_N_INSNS (41), /* int_div_si */
799 COSTS_N_INSNS (41), /* int_div_di */
801 4 /* memory_latency */
804 COSTS_N_INSNS (8), /* fp_add */
805 COSTS_N_INSNS (8), /* fp_mult_sf */
806 COSTS_N_INSNS (10), /* fp_mult_df */
807 COSTS_N_INSNS (34), /* fp_div_sf */
808 COSTS_N_INSNS (64), /* fp_div_df */
809 COSTS_N_INSNS (5), /* int_mult_si */
810 COSTS_N_INSNS (5), /* int_mult_di */
811 COSTS_N_INSNS (41), /* int_div_si */
812 COSTS_N_INSNS (41), /* int_div_di */
814 4 /* memory_latency */
817 COSTS_N_INSNS (4), /* fp_add */
818 COSTS_N_INSNS (4), /* fp_mult_sf */
819 COSTS_N_INSNS (5), /* fp_mult_df */
820 COSTS_N_INSNS (17), /* fp_div_sf */
821 COSTS_N_INSNS (32), /* fp_div_df */
822 COSTS_N_INSNS (5), /* int_mult_si */
823 COSTS_N_INSNS (5), /* int_mult_di */
824 COSTS_N_INSNS (41), /* int_div_si */
825 COSTS_N_INSNS (41), /* int_div_di */
827 4 /* memory_latency */
830 COSTS_N_INSNS (6), /* fp_add */
831 COSTS_N_INSNS (6), /* fp_mult_sf */
832 COSTS_N_INSNS (7), /* fp_mult_df */
833 COSTS_N_INSNS (25), /* fp_div_sf */
834 COSTS_N_INSNS (48), /* fp_div_df */
835 COSTS_N_INSNS (5), /* int_mult_si */
836 COSTS_N_INSNS (5), /* int_mult_di */
837 COSTS_N_INSNS (41), /* int_div_si */
838 COSTS_N_INSNS (41), /* int_div_di */
840 4 /* memory_latency */
852 COSTS_N_INSNS (2), /* fp_add */
853 COSTS_N_INSNS (4), /* fp_mult_sf */
854 COSTS_N_INSNS (5), /* fp_mult_df */
855 COSTS_N_INSNS (12), /* fp_div_sf */
856 COSTS_N_INSNS (19), /* fp_div_df */
857 COSTS_N_INSNS (2), /* int_mult_si */
858 COSTS_N_INSNS (2), /* int_mult_di */
859 COSTS_N_INSNS (35), /* int_div_si */
860 COSTS_N_INSNS (35), /* int_div_di */
862 4 /* memory_latency */
865 COSTS_N_INSNS (3), /* fp_add */
866 COSTS_N_INSNS (5), /* fp_mult_sf */
867 COSTS_N_INSNS (6), /* fp_mult_df */
868 COSTS_N_INSNS (15), /* fp_div_sf */
869 COSTS_N_INSNS (16), /* fp_div_df */
870 COSTS_N_INSNS (17), /* int_mult_si */
871 COSTS_N_INSNS (17), /* int_mult_di */
872 COSTS_N_INSNS (38), /* int_div_si */
873 COSTS_N_INSNS (38), /* int_div_di */
875 6 /* memory_latency */
878 COSTS_N_INSNS (6), /* fp_add */
879 COSTS_N_INSNS (7), /* fp_mult_sf */
880 COSTS_N_INSNS (8), /* fp_mult_df */
881 COSTS_N_INSNS (23), /* fp_div_sf */
882 COSTS_N_INSNS (36), /* fp_div_df */
883 COSTS_N_INSNS (10), /* int_mult_si */
884 COSTS_N_INSNS (10), /* int_mult_di */
885 COSTS_N_INSNS (69), /* int_div_si */
886 COSTS_N_INSNS (69), /* int_div_di */
888 6 /* memory_latency */
900 /* The only costs that appear to be updated here are
901 integer multiplication. */
903 COSTS_N_INSNS (4), /* int_mult_si */
904 COSTS_N_INSNS (6), /* int_mult_di */
905 COSTS_N_INSNS (69), /* int_div_si */
906 COSTS_N_INSNS (69), /* int_div_di */
908 4 /* memory_latency */
920 COSTS_N_INSNS (6), /* fp_add */
921 COSTS_N_INSNS (4), /* fp_mult_sf */
922 COSTS_N_INSNS (5), /* fp_mult_df */
923 COSTS_N_INSNS (23), /* fp_div_sf */
924 COSTS_N_INSNS (36), /* fp_div_df */
925 COSTS_N_INSNS (5), /* int_mult_si */
926 COSTS_N_INSNS (5), /* int_mult_di */
927 COSTS_N_INSNS (36), /* int_div_si */
928 COSTS_N_INSNS (36), /* int_div_di */
930 4 /* memory_latency */
933 COSTS_N_INSNS (6), /* fp_add */
934 COSTS_N_INSNS (5), /* fp_mult_sf */
935 COSTS_N_INSNS (6), /* fp_mult_df */
936 COSTS_N_INSNS (30), /* fp_div_sf */
937 COSTS_N_INSNS (59), /* fp_div_df */
938 COSTS_N_INSNS (3), /* int_mult_si */
939 COSTS_N_INSNS (4), /* int_mult_di */
940 COSTS_N_INSNS (42), /* int_div_si */
941 COSTS_N_INSNS (74), /* int_div_di */
943 4 /* memory_latency */
946 COSTS_N_INSNS (6), /* fp_add */
947 COSTS_N_INSNS (5), /* fp_mult_sf */
948 COSTS_N_INSNS (6), /* fp_mult_df */
949 COSTS_N_INSNS (30), /* fp_div_sf */
950 COSTS_N_INSNS (59), /* fp_div_df */
951 COSTS_N_INSNS (5), /* int_mult_si */
952 COSTS_N_INSNS (9), /* int_mult_di */
953 COSTS_N_INSNS (42), /* int_div_si */
954 COSTS_N_INSNS (74), /* int_div_di */
956 4 /* memory_latency */
959 /* The only costs that are changed here are
960 integer multiplication. */
961 COSTS_N_INSNS (6), /* fp_add */
962 COSTS_N_INSNS (7), /* fp_mult_sf */
963 COSTS_N_INSNS (8), /* fp_mult_df */
964 COSTS_N_INSNS (23), /* fp_div_sf */
965 COSTS_N_INSNS (36), /* fp_div_df */
966 COSTS_N_INSNS (5), /* int_mult_si */
967 COSTS_N_INSNS (9), /* int_mult_di */
968 COSTS_N_INSNS (69), /* int_div_si */
969 COSTS_N_INSNS (69), /* int_div_di */
971 4 /* memory_latency */
977 /* The only costs that are changed here are
978 integer multiplication. */
979 COSTS_N_INSNS (6), /* fp_add */
980 COSTS_N_INSNS (7), /* fp_mult_sf */
981 COSTS_N_INSNS (8), /* fp_mult_df */
982 COSTS_N_INSNS (23), /* fp_div_sf */
983 COSTS_N_INSNS (36), /* fp_div_df */
984 COSTS_N_INSNS (3), /* int_mult_si */
985 COSTS_N_INSNS (8), /* int_mult_di */
986 COSTS_N_INSNS (69), /* int_div_si */
987 COSTS_N_INSNS (69), /* int_div_di */
989 4 /* memory_latency */
992 /* These costs are the same as the SB-1A below. */
993 COSTS_N_INSNS (4), /* fp_add */
994 COSTS_N_INSNS (4), /* fp_mult_sf */
995 COSTS_N_INSNS (4), /* fp_mult_df */
996 COSTS_N_INSNS (24), /* fp_div_sf */
997 COSTS_N_INSNS (32), /* fp_div_df */
998 COSTS_N_INSNS (3), /* int_mult_si */
999 COSTS_N_INSNS (4), /* int_mult_di */
1000 COSTS_N_INSNS (36), /* int_div_si */
1001 COSTS_N_INSNS (68), /* int_div_di */
1002 1, /* branch_cost */
1003 4 /* memory_latency */
1006 /* These costs are the same as the SB-1 above. */
1007 COSTS_N_INSNS (4), /* fp_add */
1008 COSTS_N_INSNS (4), /* fp_mult_sf */
1009 COSTS_N_INSNS (4), /* fp_mult_df */
1010 COSTS_N_INSNS (24), /* fp_div_sf */
1011 COSTS_N_INSNS (32), /* fp_div_df */
1012 COSTS_N_INSNS (3), /* int_mult_si */
1013 COSTS_N_INSNS (4), /* int_mult_di */
1014 COSTS_N_INSNS (36), /* int_div_si */
1015 COSTS_N_INSNS (68), /* int_div_di */
1016 1, /* branch_cost */
1017 4 /* memory_latency */
1023 /* Need to replace first five with the costs of calling the appropriate
1025 COSTS_N_INSNS (256), /* fp_add */
1026 COSTS_N_INSNS (256), /* fp_mult_sf */
1027 COSTS_N_INSNS (256), /* fp_mult_df */
1028 COSTS_N_INSNS (256), /* fp_div_sf */
1029 COSTS_N_INSNS (256), /* fp_div_df */
1030 COSTS_N_INSNS (8), /* int_mult_si */
1031 COSTS_N_INSNS (8), /* int_mult_di */
1032 COSTS_N_INSNS (72), /* int_div_si */
1033 COSTS_N_INSNS (72), /* int_div_di */
1034 1, /* branch_cost */
1035 4 /* memory_latency */
1039 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1040 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1041 struct mflip_mips16_entry GTY (()) {
1045 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1047 /* Hash table callbacks for mflip_mips16_htab. */
1050 mflip_mips16_htab_hash (const void *entry)
1052 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1056 mflip_mips16_htab_eq (const void *entry, const void *name)
1058 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1059 (const char *) name) == 0;
1062 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1063 mode, false if it should next add an attribute for the opposite mode. */
1064 static GTY(()) bool mips16_flipper;
1066 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1067 for -mflip-mips16. Return true if it should use "mips16" and false if
1068 it should use "nomips16". */
1071 mflip_mips16_use_mips16_p (tree decl)
1073 struct mflip_mips16_entry *entry;
1078 /* Use the opposite of the command-line setting for anonymous decls. */
1079 if (!DECL_NAME (decl))
1080 return !mips_base_mips16;
1082 if (!mflip_mips16_htab)
1083 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1084 mflip_mips16_htab_eq, NULL);
1086 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1087 hash = htab_hash_string (name);
1088 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1089 entry = (struct mflip_mips16_entry *) *slot;
1092 mips16_flipper = !mips16_flipper;
1093 entry = GGC_NEW (struct mflip_mips16_entry);
1095 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1098 return entry->mips16_p;
1101 /* Predicates to test for presence of "near" and "far"/"long_call"
1102 attributes on the given TYPE. */
1105 mips_near_type_p (const_tree type)
1107 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1111 mips_far_type_p (const_tree type)
1113 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1114 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1117 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1120 mips_mips16_decl_p (const_tree decl)
1122 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1126 mips_nomips16_decl_p (const_tree decl)
1128 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1131 /* Return true if function DECL is a MIPS16 function. Return the ambient
1132 setting if DECL is null. */
1135 mips_use_mips16_mode_p (tree decl)
1139 /* Nested functions must use the same frame pointer as their
1140 parent and must therefore use the same ISA mode. */
1141 tree parent = decl_function_context (decl);
1144 if (mips_mips16_decl_p (decl))
1146 if (mips_nomips16_decl_p (decl))
1149 return mips_base_mips16;
1152 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1155 mips_comp_type_attributes (const_tree type1, const_tree type2)
1157 /* Disallow mixed near/far attributes. */
1158 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1160 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1165 /* Implement TARGET_INSERT_ATTRIBUTES. */
1168 mips_insert_attributes (tree decl, tree *attributes)
1171 bool mips16_p, nomips16_p;
1173 /* Check for "mips16" and "nomips16" attributes. */
1174 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1175 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1176 if (TREE_CODE (decl) != FUNCTION_DECL)
1179 error ("%qs attribute only applies to functions", "mips16");
1181 error ("%qs attribute only applies to functions", "nomips16");
1185 mips16_p |= mips_mips16_decl_p (decl);
1186 nomips16_p |= mips_nomips16_decl_p (decl);
1187 if (mips16_p || nomips16_p)
1189 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1190 if (mips16_p && nomips16_p)
1191 error ("%qs cannot have both %<mips16%> and "
1192 "%<nomips16%> attributes",
1193 IDENTIFIER_POINTER (DECL_NAME (decl)));
1195 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1197 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1198 "mips16" attribute, arbitrarily pick one. We must pick the same
1199 setting for duplicate declarations of a function. */
1200 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1201 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1206 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1209 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1211 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1212 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1213 error ("%qs redeclared with conflicting %qs attributes",
1214 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "mips16");
1215 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1216 error ("%qs redeclared with conflicting %qs attributes",
1217 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "nomips16");
1219 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1220 DECL_ATTRIBUTES (newdecl));
1223 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1224 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1227 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1229 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1231 *base_ptr = XEXP (x, 0);
1232 *offset_ptr = INTVAL (XEXP (x, 1));
1241 static unsigned int mips_build_integer (struct mips_integer_op *,
1242 unsigned HOST_WIDE_INT);
1244 /* A subroutine of mips_build_integer, with the same interface.
1245 Assume that the final action in the sequence should be a left shift. */
1248 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1250 unsigned int i, shift;
1252 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1253 since signed numbers are easier to load than unsigned ones. */
1255 while ((value & 1) == 0)
1256 value /= 2, shift++;
1258 i = mips_build_integer (codes, value);
1259 codes[i].code = ASHIFT;
1260 codes[i].value = shift;
1264 /* As for mips_build_shift, but assume that the final action will be
1265 an IOR or PLUS operation. */
1268 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1270 unsigned HOST_WIDE_INT high;
1273 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1274 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1276 /* The constant is too complex to load with a simple LUI/ORI pair,
1277 so we want to give the recursive call as many trailing zeros as
1278 possible. In this case, we know bit 16 is set and that the
1279 low 16 bits form a negative number. If we subtract that number
1280 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1281 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1282 codes[i].code = PLUS;
1283 codes[i].value = CONST_LOW_PART (value);
1287 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1288 bits gives a value with at least 17 trailing zeros. */
1289 i = mips_build_integer (codes, high);
1290 codes[i].code = IOR;
1291 codes[i].value = value & 0xffff;
1296 /* Fill CODES with a sequence of rtl operations to load VALUE.
1297 Return the number of operations needed. */
1300 mips_build_integer (struct mips_integer_op *codes,
1301 unsigned HOST_WIDE_INT value)
1303 if (SMALL_OPERAND (value)
1304 || SMALL_OPERAND_UNSIGNED (value)
1305 || LUI_OPERAND (value))
1307 /* The value can be loaded with a single instruction. */
1308 codes[0].code = UNKNOWN;
1309 codes[0].value = value;
1312 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1314 /* Either the constant is a simple LUI/ORI combination or its
1315 lowest bit is set. We don't want to shift in this case. */
1316 return mips_build_lower (codes, value);
1318 else if ((value & 0xffff) == 0)
1320 /* The constant will need at least three actions. The lowest
1321 16 bits are clear, so the final action will be a shift. */
1322 return mips_build_shift (codes, value);
1326 /* The final action could be a shift, add or inclusive OR.
1327 Rather than use a complex condition to select the best
1328 approach, try both mips_build_shift and mips_build_lower
1329 and pick the one that gives the shortest sequence.
1330 Note that this case is only used once per constant. */
1331 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1332 unsigned int cost, alt_cost;
1334 cost = mips_build_shift (codes, value);
1335 alt_cost = mips_build_lower (alt_codes, value);
1336 if (alt_cost < cost)
1338 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1345 /* Return true if X is a thread-local symbol. */
1348 mips_tls_symbol_p (rtx x)
1350 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1353 /* Return true if SYMBOL_REF X is associated with a global symbol
1354 (in the STB_GLOBAL sense). */
1357 mips_global_symbol_p (const_rtx x)
1359 const_tree decl = SYMBOL_REF_DECL (x);
1362 return !SYMBOL_REF_LOCAL_P (x);
1364 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1365 or weak symbols. Relocations in the object file will be against
1366 the target symbol, so it's that symbol's binding that matters here. */
1367 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1370 /* Return true if SYMBOL_REF X binds locally. */
1373 mips_symbol_binds_local_p (const_rtx x)
1375 return (SYMBOL_REF_DECL (x)
1376 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1377 : SYMBOL_REF_LOCAL_P (x));
1380 /* Return true if rtx constants of mode MODE should be put into a small
1384 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1386 return (!TARGET_EMBEDDED_DATA
1387 && TARGET_LOCAL_SDATA
1388 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1391 /* Return true if X should not be moved directly into register $25.
1392 We need this because many versions of GAS will treat "la $25,foo" as
1393 part of a call sequence and so allow a global "foo" to be lazily bound. */
1396 mips_dangerous_for_la25_p (rtx x)
1398 return (!TARGET_EXPLICIT_RELOCS
1400 && GET_CODE (x) == SYMBOL_REF
1401 && mips_global_symbol_p (x));
1404 /* Return the method that should be used to access SYMBOL_REF or
1405 LABEL_REF X in context CONTEXT. */
1407 static enum mips_symbol_type
1408 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1411 return SYMBOL_GOT_DISP;
1413 if (GET_CODE (x) == LABEL_REF)
1415 /* LABEL_REFs are used for jump tables as well as text labels.
1416 Only return SYMBOL_PC_RELATIVE if we know the label is in
1417 the text section. */
1418 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1419 return SYMBOL_PC_RELATIVE;
1421 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1422 return SYMBOL_GOT_PAGE_OFST;
1424 return SYMBOL_ABSOLUTE;
1427 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1429 if (SYMBOL_REF_TLS_MODEL (x))
1432 if (CONSTANT_POOL_ADDRESS_P (x))
1434 if (TARGET_MIPS16_TEXT_LOADS)
1435 return SYMBOL_PC_RELATIVE;
1437 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1438 return SYMBOL_PC_RELATIVE;
1440 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1441 return SYMBOL_GP_RELATIVE;
1444 /* Do not use small-data accesses for weak symbols; they may end up
1446 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1447 return SYMBOL_GP_RELATIVE;
1449 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1452 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1454 /* There are three cases to consider:
1456 - o32 PIC (either with or without explicit relocs)
1457 - n32/n64 PIC without explicit relocs
1458 - n32/n64 PIC with explicit relocs
1460 In the first case, both local and global accesses will use an
1461 R_MIPS_GOT16 relocation. We must correctly predict which of
1462 the two semantics (local or global) the assembler and linker
1463 will apply. The choice depends on the symbol's binding rather
1464 than its visibility.
1466 In the second case, the assembler will not use R_MIPS_GOT16
1467 relocations, but it chooses between local and global accesses
1468 in the same way as for o32 PIC.
1470 In the third case we have more freedom since both forms of
1471 access will work for any kind of symbol. However, there seems
1472 little point in doing things differently. */
1473 if (mips_global_symbol_p (x))
1474 return SYMBOL_GOT_DISP;
1476 return SYMBOL_GOT_PAGE_OFST;
1479 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1480 return SYMBOL_FORCE_TO_MEM;
1482 return SYMBOL_ABSOLUTE;
1485 /* Classify the base of symbolic expression X, given that X appears in
1488 static enum mips_symbol_type
1489 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1493 split_const (x, &x, &offset);
1494 if (UNSPEC_ADDRESS_P (x))
1495 return UNSPEC_ADDRESS_TYPE (x);
1497 return mips_classify_symbol (x, context);
1500 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1501 is the alignment in bytes of SYMBOL_REF X. */
1504 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1506 HOST_WIDE_INT align;
1508 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1509 return IN_RANGE (offset, 0, align - 1);
1512 /* Return true if X is a symbolic constant that can be used in context
1513 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1516 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1517 enum mips_symbol_type *symbol_type)
1521 split_const (x, &x, &offset);
1522 if (UNSPEC_ADDRESS_P (x))
1524 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1525 x = UNSPEC_ADDRESS (x);
1527 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1529 *symbol_type = mips_classify_symbol (x, context);
1530 if (*symbol_type == SYMBOL_TLS)
1536 if (offset == const0_rtx)
1539 /* Check whether a nonzero offset is valid for the underlying
1541 switch (*symbol_type)
1543 case SYMBOL_ABSOLUTE:
1544 case SYMBOL_FORCE_TO_MEM:
1545 case SYMBOL_32_HIGH:
1546 case SYMBOL_64_HIGH:
1549 /* If the target has 64-bit pointers and the object file only
1550 supports 32-bit symbols, the values of those symbols will be
1551 sign-extended. In this case we can't allow an arbitrary offset
1552 in case the 32-bit value X + OFFSET has a different sign from X. */
1553 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1554 return offset_within_block_p (x, INTVAL (offset));
1556 /* In other cases the relocations can handle any offset. */
1559 case SYMBOL_PC_RELATIVE:
1560 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1561 In this case, we no longer have access to the underlying constant,
1562 but the original symbol-based access was known to be valid. */
1563 if (GET_CODE (x) == LABEL_REF)
1568 case SYMBOL_GP_RELATIVE:
1569 /* Make sure that the offset refers to something within the
1570 same object block. This should guarantee that the final
1571 PC- or GP-relative offset is within the 16-bit limit. */
1572 return offset_within_block_p (x, INTVAL (offset));
1574 case SYMBOL_GOT_PAGE_OFST:
1575 case SYMBOL_GOTOFF_PAGE:
1576 /* If the symbol is global, the GOT entry will contain the symbol's
1577 address, and we will apply a 16-bit offset after loading it.
1578 If the symbol is local, the linker should provide enough local
1579 GOT entries for a 16-bit offset, but larger offsets may lead
1581 return SMALL_INT (offset);
1585 /* There is no carry between the HI and LO REL relocations, so the
1586 offset is only valid if we know it won't lead to such a carry. */
1587 return mips_offset_within_alignment_p (x, INTVAL (offset));
1589 case SYMBOL_GOT_DISP:
1590 case SYMBOL_GOTOFF_DISP:
1591 case SYMBOL_GOTOFF_CALL:
1592 case SYMBOL_GOTOFF_LOADGP:
1595 case SYMBOL_GOTTPREL:
1603 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1604 single instruction. We rely on the fact that, in the worst case,
1605 all instructions involved in a MIPS16 address calculation are usually
1609 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1613 case SYMBOL_ABSOLUTE:
1614 /* When using 64-bit symbols, we need 5 preparatory instructions,
1617 lui $at,%highest(symbol)
1618 daddiu $at,$at,%higher(symbol)
1620 daddiu $at,$at,%hi(symbol)
1623 The final address is then $at + %lo(symbol). With 32-bit
1624 symbols we just need a preparatory LUI for normal mode and
1625 a preparatory LI and SLL for MIPS16. */
1626 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1628 case SYMBOL_GP_RELATIVE:
1629 /* Treat GP-relative accesses as taking a single instruction on
1630 MIPS16 too; the copy of $gp can often be shared. */
1633 case SYMBOL_PC_RELATIVE:
1634 /* PC-relative constants can be only be used with ADDIUPC,
1635 DADDIUPC, LWPC and LDPC. */
1636 if (mode == MAX_MACHINE_MODE
1637 || GET_MODE_SIZE (mode) == 4
1638 || GET_MODE_SIZE (mode) == 8)
1641 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1644 case SYMBOL_FORCE_TO_MEM:
1645 /* LEAs will be converted into constant-pool references by
1647 if (mode == MAX_MACHINE_MODE)
1650 /* The constant must be loaded and then dereferenced. */
1653 case SYMBOL_GOT_DISP:
1654 /* The constant will have to be loaded from the GOT before it
1655 is used in an address. */
1656 if (mode != MAX_MACHINE_MODE)
1661 case SYMBOL_GOT_PAGE_OFST:
1662 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1663 local/global classification is accurate. The worst cases are:
1665 (1) For local symbols when generating o32 or o64 code. The assembler
1671 ...and the final address will be $at + %lo(symbol).
1673 (2) For global symbols when -mxgot. The assembler will use:
1675 lui $at,%got_hi(symbol)
1678 ...and the final address will be $at + %got_lo(symbol). */
1681 case SYMBOL_GOTOFF_PAGE:
1682 case SYMBOL_GOTOFF_DISP:
1683 case SYMBOL_GOTOFF_CALL:
1684 case SYMBOL_GOTOFF_LOADGP:
1685 case SYMBOL_32_HIGH:
1686 case SYMBOL_64_HIGH:
1692 case SYMBOL_GOTTPREL:
1695 /* A 16-bit constant formed by a single relocation, or a 32-bit
1696 constant formed from a high 16-bit relocation and a low 16-bit
1697 relocation. Use mips_split_p to determine which. 32-bit
1698 constants need an "lui; addiu" sequence for normal mode and
1699 an "li; sll; addiu" sequence for MIPS16 mode. */
1700 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1703 /* We don't treat a bare TLS symbol as a constant. */
1709 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1710 to load symbols of type TYPE into a register. Return 0 if the given
1711 type of symbol cannot be used as an immediate operand.
1713 Otherwise, return the number of instructions needed to load or store
1714 values of mode MODE to or from addresses of type TYPE. Return 0 if
1715 the given type of symbol is not valid in addresses.
1717 In both cases, treat extended MIPS16 instructions as two instructions. */
1720 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1722 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1725 /* A for_each_rtx callback. Stop the search if *X references a
1726 thread-local symbol. */
1729 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1731 return mips_tls_symbol_p (*x);
1734 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1737 mips_cannot_force_const_mem (rtx x)
1743 /* As an optimization, reject constants that mips_legitimize_move
1746 Suppose we have a multi-instruction sequence that loads constant C
1747 into register R. If R does not get allocated a hard register, and
1748 R is used in an operand that allows both registers and memory
1749 references, reload will consider forcing C into memory and using
1750 one of the instruction's memory alternatives. Returning false
1751 here will force it to use an input reload instead. */
1752 if (GET_CODE (x) == CONST_INT)
1755 split_const (x, &base, &offset);
1756 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1760 /* TLS symbols must be computed by mips_legitimize_move. */
1761 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1767 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1768 constants when we're using a per-function constant pool. */
1771 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1772 const_rtx x ATTRIBUTE_UNUSED)
1774 return !TARGET_MIPS16_PCREL_LOADS;
1777 /* Return true if register REGNO is a valid base register for mode MODE.
1778 STRICT_P is true if REG_OK_STRICT is in effect. */
1781 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1784 if (!HARD_REGISTER_NUM_P (regno))
1788 regno = reg_renumber[regno];
1791 /* These fake registers will be eliminated to either the stack or
1792 hard frame pointer, both of which are usually valid base registers.
1793 Reload deals with the cases where the eliminated form isn't valid. */
1794 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1797 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1798 values, nothing smaller. There are two problems here:
1800 (a) Instantiating virtual registers can introduce new uses of the
1801 stack pointer. If these virtual registers are valid addresses,
1802 the stack pointer should be too.
1804 (b) Most uses of the stack pointer are not made explicit until
1805 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1806 We don't know until that stage whether we'll be eliminating to the
1807 stack pointer (which needs the restriction) or the hard frame
1808 pointer (which doesn't).
1810 All in all, it seems more consistent to only enforce this restriction
1811 during and after reload. */
1812 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1813 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1815 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1818 /* Return true if X is a valid base register for mode MODE.
1819 STRICT_P is true if REG_OK_STRICT is in effect. */
1822 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
1824 if (!strict_p && GET_CODE (x) == SUBREG)
1828 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
1831 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
1832 can address a value of mode MODE. */
1835 mips_valid_offset_p (rtx x, enum machine_mode mode)
1837 /* Check that X is a signed 16-bit number. */
1838 if (!const_arith_operand (x, Pmode))
1841 /* We may need to split multiword moves, so make sure that every word
1843 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
1844 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
1850 /* Return true if a LO_SUM can address a value of mode MODE when the
1851 LO_SUM symbol has type SYMBOL_TYPE. */
1854 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
1856 /* Check that symbols of type SYMBOL_TYPE can be used to access values
1858 if (mips_symbol_insns (symbol_type, mode) == 0)
1861 /* Check that there is a known low-part relocation. */
1862 if (mips_lo_relocs[symbol_type] == NULL)
1865 /* We may need to split multiword moves, so make sure that each word
1866 can be accessed without inducing a carry. This is mainly needed
1867 for o64, which has historically only guaranteed 64-bit alignment
1868 for 128-bit types. */
1869 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
1870 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
1876 /* Return true if X is a valid address for machine mode MODE. If it is,
1877 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
1881 mips_classify_address (struct mips_address_info *info, rtx x,
1882 enum machine_mode mode, bool strict_p)
1884 switch (GET_CODE (x))
1888 info->type = ADDRESS_REG;
1890 info->offset = const0_rtx;
1891 return mips_valid_base_register_p (info->reg, mode, strict_p);
1894 info->type = ADDRESS_REG;
1895 info->reg = XEXP (x, 0);
1896 info->offset = XEXP (x, 1);
1897 return (mips_valid_base_register_p (info->reg, mode, strict_p)
1898 && mips_valid_offset_p (info->offset, mode));
1901 info->type = ADDRESS_LO_SUM;
1902 info->reg = XEXP (x, 0);
1903 info->offset = XEXP (x, 1);
1904 /* We have to trust the creator of the LO_SUM to do something vaguely
1905 sane. Target-independent code that creates a LO_SUM should also
1906 create and verify the matching HIGH. Target-independent code that
1907 adds an offset to a LO_SUM must prove that the offset will not
1908 induce a carry. Failure to do either of these things would be
1909 a bug, and we are not required to check for it here. The MIPS
1910 backend itself should only create LO_SUMs for valid symbolic
1911 constants, with the high part being either a HIGH or a copy
1914 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
1915 return (mips_valid_base_register_p (info->reg, mode, strict_p)
1916 && mips_valid_lo_sum_p (info->symbol_type, mode));
1919 /* Small-integer addresses don't occur very often, but they
1920 are legitimate if $0 is a valid base register. */
1921 info->type = ADDRESS_CONST_INT;
1922 return !TARGET_MIPS16 && SMALL_INT (x);
1927 info->type = ADDRESS_SYMBOLIC;
1928 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
1930 && mips_symbol_insns (info->symbol_type, mode) > 0
1931 && !mips_split_p[info->symbol_type]);
1938 /* Return true if X is a legitimate address for a memory operand of mode
1939 MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
1942 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
1944 struct mips_address_info addr;
1946 return mips_classify_address (&addr, x, mode, strict_p);
1949 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1952 mips_stack_address_p (rtx x, enum machine_mode mode)
1954 struct mips_address_info addr;
1956 return (mips_classify_address (&addr, x, mode, false)
1957 && addr.type == ADDRESS_REG
1958 && addr.reg == stack_pointer_rtx);
1961 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
1962 address instruction. Note that such addresses are not considered
1963 legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
1964 is so restricted. */
1967 mips_lwxs_address_p (rtx addr)
1970 && GET_CODE (addr) == PLUS
1971 && REG_P (XEXP (addr, 1)))
1973 rtx offset = XEXP (addr, 0);
1974 if (GET_CODE (offset) == MULT
1975 && REG_P (XEXP (offset, 0))
1976 && GET_CODE (XEXP (offset, 1)) == CONST_INT
1977 && INTVAL (XEXP (offset, 1)) == 4)
1983 /* Return true if a value at OFFSET bytes from base register BASE can be
1984 accessed using an unextended MIPS16 instruction. MODE is the mode of
1987 Usually the offset in an unextended instruction is a 5-bit field.
1988 The offset is unsigned and shifted left once for LH and SH, twice
1989 for LW and SW, and so on. An exception is LWSP and SWSP, which have
1990 an 8-bit immediate field that's shifted left twice. */
1993 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
1994 unsigned HOST_WIDE_INT offset)
1996 if (offset % GET_MODE_SIZE (mode) == 0)
1998 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1999 return offset < 256U * GET_MODE_SIZE (mode);
2000 return offset < 32U * GET_MODE_SIZE (mode);
2005 /* Return the number of instructions needed to load or store a value
2006 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2007 Assume that multiword moves may need to be split into word moves
2008 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2011 For MIPS16 code, count extended instructions as two instructions. */
2014 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2016 struct mips_address_info addr;
2019 /* BLKmode is used for single unaligned loads and stores and should
2020 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2021 meaningless, so we have to single it out as a special case one way
2023 if (mode != BLKmode && might_split_p)
2024 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2028 if (mips_classify_address (&addr, x, mode, false))
2033 && !mips16_unextended_reference_p (mode, addr.reg,
2034 UINTVAL (addr.offset)))
2038 case ADDRESS_LO_SUM:
2039 return TARGET_MIPS16 ? factor * 2 : factor;
2041 case ADDRESS_CONST_INT:
2044 case ADDRESS_SYMBOLIC:
2045 return factor * mips_symbol_insns (addr.symbol_type, mode);
2050 /* Return the number of instructions needed to load constant X.
2051 Return 0 if X isn't a valid constant. */
2054 mips_const_insns (rtx x)
2056 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2057 enum mips_symbol_type symbol_type;
2060 switch (GET_CODE (x))
2063 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2065 || !mips_split_p[symbol_type])
2068 /* This is simply an LUI for normal mode. It is an extended
2069 LI followed by an extended SLL for MIPS16. */
2070 return TARGET_MIPS16 ? 4 : 1;
2074 /* Unsigned 8-bit constants can be loaded using an unextended
2075 LI instruction. Unsigned 16-bit constants can be loaded
2076 using an extended LI. Negative constants must be loaded
2077 using LI and then negated. */
2078 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2079 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2080 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2081 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2084 return mips_build_integer (codes, INTVAL (x));
2088 /* Allow zeros for normal mode, where we can use $0. */
2089 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2095 /* See if we can refer to X directly. */
2096 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2097 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2099 /* Otherwise try splitting the constant into a base and offset.
2100 16-bit offsets can be added using an extra ADDIU. Larger offsets
2101 must be calculated separately and then added to the base. */
2102 split_const (x, &x, &offset);
2105 int n = mips_const_insns (x);
2108 if (SMALL_INT (offset))
2111 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2118 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2126 /* X is a doubleword constant that can be handled by splitting it into
2127 two words and loading each word separately. Return the number of
2128 instructions required to do this. */
2131 mips_split_const_insns (rtx x)
2133 unsigned int low, high;
2135 low = mips_const_insns (mips_subword (x, false));
2136 high = mips_const_insns (mips_subword (x, true));
2137 gcc_assert (low > 0 && high > 0);
2141 /* Return the number of instructions needed to implement INSN,
2142 given that it loads from or stores to MEM. Count extended
2143 MIPS16 instructions as two instructions. */
2146 mips_load_store_insns (rtx mem, rtx insn)
2148 enum machine_mode mode;
2152 gcc_assert (MEM_P (mem));
2153 mode = GET_MODE (mem);
2155 /* Try to prove that INSN does not need to be split. */
2156 might_split_p = true;
2157 if (GET_MODE_BITSIZE (mode) == 64)
2159 set = single_set (insn);
2160 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2161 might_split_p = false;
2164 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2167 /* Return the number of instructions needed for an integer division. */
2170 mips_idiv_insns (void)
2175 if (TARGET_CHECK_ZERO_DIV)
2177 if (GENERATE_DIVIDE_TRAPS)
2183 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2188 /* Emit a move from SRC to DEST. Assume that the move expanders can
2189 handle all moves if !can_create_pseudo_p (). The distinction is
2190 important because, unlike emit_move_insn, the move expanders know
2191 how to force Pmode objects into the constant pool even when the
2192 constant pool address is not itself legitimate. */
2195 mips_emit_move (rtx dest, rtx src)
2197 return (can_create_pseudo_p ()
2198 ? emit_move_insn (dest, src)
2199 : emit_move_insn_1 (dest, src));
2202 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2205 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2207 emit_insn (gen_rtx_SET (VOIDmode, target,
2208 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2211 /* Compute (CODE OP0 OP1) and store the result in a new register
2212 of mode MODE. Return that new register. */
2215 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2219 reg = gen_reg_rtx (mode);
2220 mips_emit_binary (code, reg, op0, op1);
2224 /* Copy VALUE to a register and return that register. If new pseudos
2225 are allowed, copy it into a new register, otherwise use DEST. */
2228 mips_force_temporary (rtx dest, rtx value)
2230 if (can_create_pseudo_p ())
2231 return force_reg (Pmode, value);
2234 mips_emit_move (dest, value);
2239 /* Emit a call sequence with call pattern PATTERN and return the call
2240 instruction itself (which is not necessarily the last instruction
2241 emitted). LAZY_P is true if the call address is lazily-bound. */
2244 mips_emit_call_insn (rtx pattern, bool lazy_p)
2248 insn = emit_call_insn (pattern);
2250 /* Lazy-binding stubs require $gp to be valid on entry. */
2252 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2256 /* See the comment above load_call<mode> for details. */
2257 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2258 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2259 emit_insn (gen_update_got_version ());
2264 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2265 then add CONST_INT OFFSET to the result. */
2268 mips_unspec_address_offset (rtx base, rtx offset,
2269 enum mips_symbol_type symbol_type)
2271 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2272 UNSPEC_ADDRESS_FIRST + symbol_type);
2273 if (offset != const0_rtx)
2274 base = gen_rtx_PLUS (Pmode, base, offset);
2275 return gen_rtx_CONST (Pmode, base);
2278 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2279 type SYMBOL_TYPE. */
2282 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2286 split_const (address, &base, &offset);
2287 return mips_unspec_address_offset (base, offset, symbol_type);
2290 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2291 high part to BASE and return the result. Just return BASE otherwise.
2292 TEMP is as for mips_force_temporary.
2294 The returned expression can be used as the first operand to a LO_SUM. */
2297 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2298 enum mips_symbol_type symbol_type)
2300 if (mips_split_p[symbol_type])
2302 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2303 addr = mips_force_temporary (temp, addr);
2304 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2309 /* Return an instruction that copies $gp into register REG. We want
2310 GCC to treat the register's value as constant, so that its value
2311 can be rematerialized on demand. */
2314 gen_load_const_gp (rtx reg)
2316 return (Pmode == SImode
2317 ? gen_load_const_gp_si (reg)
2318 : gen_load_const_gp_di (reg));
2321 /* Return a pseudo register that contains the value of $gp throughout
2322 the current function. Such registers are needed by MIPS16 functions,
2323 for which $gp itself is not a valid base register or addition operand. */
2326 mips16_gp_pseudo_reg (void)
2328 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2329 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2331 /* Don't emit an instruction to initialize the pseudo register if
2332 we are being called from the tree optimizers' cost-calculation
2334 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2335 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2337 rtx insn, scan, after;
2339 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2341 push_topmost_sequence ();
2342 /* We need to emit the initialization after the FUNCTION_BEG
2343 note, so that it will be integrated. */
2344 after = get_insns ();
2345 for (scan = after; scan != NULL_RTX; scan = NEXT_INSN (scan))
2346 if (NOTE_P (scan) && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
2351 insn = emit_insn_after (insn, after);
2352 pop_topmost_sequence ();
2354 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2357 return cfun->machine->mips16_gp_pseudo_rtx;
2360 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2361 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2362 constant in that context and can be split into a high part and a LO_SUM.
2363 If so, and if LO_SUM_OUT is nonnull, emit the high part and return
2364 the LO_SUM in *LO_SUM_OUT. Leave *LO_SUM_OUT unchanged otherwise.
2366 TEMP is as for mips_force_temporary and is used to load the high
2367 part into a register. */
2370 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *lo_sum_out)
2372 enum mips_symbol_context context;
2373 enum mips_symbol_type symbol_type;
2376 context = (mode == MAX_MACHINE_MODE
2377 ? SYMBOL_CONTEXT_LEA
2378 : SYMBOL_CONTEXT_MEM);
2379 if (!mips_symbolic_constant_p (addr, context, &symbol_type)
2380 || mips_symbol_insns (symbol_type, mode) == 0
2381 || !mips_split_p[symbol_type])
2386 if (symbol_type == SYMBOL_GP_RELATIVE)
2388 if (!can_create_pseudo_p ())
2390 emit_insn (gen_load_const_gp (temp));
2394 high = mips16_gp_pseudo_reg ();
2398 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2399 high = mips_force_temporary (temp, high);
2401 *lo_sum_out = gen_rtx_LO_SUM (Pmode, high, addr);
2406 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2407 mips_force_temporary; it is only needed when OFFSET is not a
2411 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2413 if (!SMALL_OPERAND (offset))
2419 /* Load the full offset into a register so that we can use
2420 an unextended instruction for the address itself. */
2421 high = GEN_INT (offset);
2426 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2427 high = GEN_INT (CONST_HIGH_PART (offset));
2428 offset = CONST_LOW_PART (offset);
2430 high = mips_force_temporary (temp, high);
2431 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2433 return plus_constant (reg, offset);
2436 /* The __tls_get_attr symbol. */
2437 static GTY(()) rtx mips_tls_symbol;
2439 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2440 the TLS symbol we are referencing and TYPE is the symbol type to use
2441 (either global dynamic or local dynamic). V0 is an RTX for the
2442 return value location. */
2445 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2449 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2451 if (!mips_tls_symbol)
2452 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2454 loc = mips_unspec_address (sym, type);
2458 emit_insn (gen_rtx_SET (Pmode, a0,
2459 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2460 insn = mips_expand_call (v0, mips_tls_symbol, const0_rtx, const0_rtx, false);
2461 RTL_CONST_CALL_P (insn) = 1;
2462 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2463 insn = get_insns ();
2470 /* Return a pseudo register that contains the current thread pointer. */
2477 tp = gen_reg_rtx (Pmode);
2478 if (Pmode == DImode)
2479 emit_insn (gen_tls_get_tp_di (tp));
2481 emit_insn (gen_tls_get_tp_si (tp));
2485 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2486 its address. The return value will be both a valid address and a valid
2487 SET_SRC (either a REG or a LO_SUM). */
2490 mips_legitimize_tls_address (rtx loc)
2492 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2493 enum tls_model model;
2497 sorry ("MIPS16 TLS");
2498 return gen_reg_rtx (Pmode);
2501 model = SYMBOL_REF_TLS_MODEL (loc);
2502 /* Only TARGET_ABICALLS code can have more than one module; other
2503 code must be be static and should not use a GOT. All TLS models
2504 reduce to local exec in this situation. */
2505 if (!TARGET_ABICALLS)
2506 model = TLS_MODEL_LOCAL_EXEC;
2510 case TLS_MODEL_GLOBAL_DYNAMIC:
2511 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2512 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2513 dest = gen_reg_rtx (Pmode);
2514 emit_libcall_block (insn, dest, v0, loc);
2517 case TLS_MODEL_LOCAL_DYNAMIC:
2518 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2519 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2520 tmp1 = gen_reg_rtx (Pmode);
2522 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2523 share the LDM result with other LD model accesses. */
2524 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2526 emit_libcall_block (insn, tmp1, v0, eqv);
2528 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2529 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2530 mips_unspec_address (loc, SYMBOL_DTPREL));
2533 case TLS_MODEL_INITIAL_EXEC:
2534 tp = mips_get_tp ();
2535 tmp1 = gen_reg_rtx (Pmode);
2536 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2537 if (Pmode == DImode)
2538 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2540 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2541 dest = gen_reg_rtx (Pmode);
2542 emit_insn (gen_add3_insn (dest, tmp1, tp));
2545 case TLS_MODEL_LOCAL_EXEC:
2546 tp = mips_get_tp ();
2547 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2548 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2549 mips_unspec_address (loc, SYMBOL_TPREL));
2558 /* If X is not a valid address for mode MODE, force it into a register. */
2561 mips_force_address (rtx x, enum machine_mode mode)
2563 if (!mips_legitimate_address_p (mode, x, false))
2564 x = force_reg (Pmode, x);
2568 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2569 be legitimized in a way that the generic machinery might not expect,
2570 put the new address in *XLOC and return true. MODE is the mode of
2571 the memory being accessed. */
2574 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2577 HOST_WIDE_INT offset;
2579 if (mips_tls_symbol_p (*xloc))
2581 *xloc = mips_legitimize_tls_address (*xloc);
2585 /* See if the address can split into a high part and a LO_SUM. */
2586 if (mips_split_symbol (NULL, *xloc, mode, &addr))
2588 *xloc = mips_force_address (addr, mode);
2592 /* Handle BASE + OFFSET using mips_add_offset. */
2593 mips_split_plus (*xloc, &base, &offset);
2596 if (!mips_valid_base_register_p (base, mode, false))
2597 base = copy_to_mode_reg (Pmode, base);
2598 addr = mips_add_offset (NULL, base, offset);
2599 *xloc = mips_force_address (addr, mode);
2605 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2608 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2610 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2611 enum machine_mode mode;
2612 unsigned int i, num_ops;
2615 mode = GET_MODE (dest);
2616 num_ops = mips_build_integer (codes, value);
2618 /* Apply each binary operation to X. Invariant: X is a legitimate
2619 source operand for a SET pattern. */
2620 x = GEN_INT (codes[0].value);
2621 for (i = 1; i < num_ops; i++)
2623 if (!can_create_pseudo_p ())
2625 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2629 x = force_reg (mode, x);
2630 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2633 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2636 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2637 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2641 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2645 /* Split moves of big integers into smaller pieces. */
2646 if (splittable_const_int_operand (src, mode))
2648 mips_move_integer (dest, dest, INTVAL (src));
2652 /* Split moves of symbolic constants into high/low pairs. */
2653 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2655 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2659 /* Generate the appropriate access sequences for TLS symbols. */
2660 if (mips_tls_symbol_p (src))
2662 mips_emit_move (dest, mips_legitimize_tls_address (src));
2666 /* If we have (const (plus symbol offset)), and that expression cannot
2667 be forced into memory, load the symbol first and add in the offset.
2668 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2669 forced into memory, as it usually produces better code. */
2670 split_const (src, &base, &offset);
2671 if (offset != const0_rtx
2672 && (targetm.cannot_force_const_mem (src)
2673 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2675 base = mips_force_temporary (dest, base);
2676 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2680 src = force_const_mem (mode, src);
2682 /* When using explicit relocs, constant pool references are sometimes
2683 not legitimate addresses. */
2684 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2685 mips_emit_move (dest, src);
2688 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2689 sequence that is valid. */
2692 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2694 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2696 mips_emit_move (dest, force_reg (mode, src));
2700 /* We need to deal with constants that would be legitimate
2701 immediate_operands but aren't legitimate move_operands. */
2702 if (CONSTANT_P (src) && !move_operand (src, mode))
2704 mips_legitimize_const_move (mode, dest, src);
2705 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2711 /* Return true if value X in context CONTEXT is a small-data address
2712 that can be rewritten as a LO_SUM. */
2715 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
2717 enum mips_symbol_type symbol_type;
2719 return (TARGET_EXPLICIT_RELOCS
2720 && mips_symbolic_constant_p (x, context, &symbol_type)
2721 && symbol_type == SYMBOL_GP_RELATIVE);
2724 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
2725 containing MEM, or null if none. */
2728 mips_small_data_pattern_1 (rtx *loc, void *data)
2730 enum mips_symbol_context context;
2732 if (GET_CODE (*loc) == LO_SUM)
2737 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
2742 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2743 return mips_rewrite_small_data_p (*loc, context);
2746 /* Return true if OP refers to small data symbols directly, not through
2750 mips_small_data_pattern_p (rtx op)
2752 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
2755 /* A for_each_rtx callback, used by mips_rewrite_small_data.
2756 DATA is the containing MEM, or null if none. */
2759 mips_rewrite_small_data_1 (rtx *loc, void *data)
2761 enum mips_symbol_context context;
2765 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
2769 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2770 if (mips_rewrite_small_data_p (*loc, context))
2771 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
2773 if (GET_CODE (*loc) == LO_SUM)
2779 /* Rewrite instruction pattern PATTERN so that it refers to small data
2780 using explicit relocations. */
2783 mips_rewrite_small_data (rtx pattern)
2785 pattern = copy_insn (pattern);
2786 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
2790 /* We need a lot of little routines to check the range of MIPS16 immediate
2794 m16_check_op (rtx op, int low, int high, int mask)
2796 return (GET_CODE (op) == CONST_INT
2797 && IN_RANGE (INTVAL (op), low, high)
2798 && (INTVAL (op) & mask) == 0);
2802 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2804 return m16_check_op (op, 0x1, 0x8, 0);
2808 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2810 return m16_check_op (op, -0x8, 0x7, 0);
2814 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2816 return m16_check_op (op, -0x7, 0x8, 0);
2820 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2822 return m16_check_op (op, -0x10, 0xf, 0);
2826 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2828 return m16_check_op (op, -0xf, 0x10, 0);
2832 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2834 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
2838 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2840 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
2844 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2846 return m16_check_op (op, -0x80, 0x7f, 0);
2850 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2852 return m16_check_op (op, -0x7f, 0x80, 0);
2856 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2858 return m16_check_op (op, 0x0, 0xff, 0);
2862 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2864 return m16_check_op (op, -0xff, 0x0, 0);
2868 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2870 return m16_check_op (op, -0x1, 0xfe, 0);
2874 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2876 return m16_check_op (op, 0x0, 0xff << 2, 3);
2880 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2882 return m16_check_op (op, -0xff << 2, 0x0, 3);
2886 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2888 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
2892 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2894 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
2897 /* The cost of loading values from the constant pool. It should be
2898 larger than the cost of any constant we want to synthesize inline. */
2899 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
2901 /* Return the cost of X when used as an operand to the MIPS16 instruction
2902 that implements CODE. Return -1 if there is no such instruction, or if
2903 X is not a valid immediate operand for it. */
2906 mips16_constant_cost (int code, HOST_WIDE_INT x)
2913 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
2914 other shifts are extended. The shift patterns truncate the shift
2915 count to the right size, so there are no out-of-range values. */
2916 if (IN_RANGE (x, 1, 8))
2918 return COSTS_N_INSNS (1);
2921 if (IN_RANGE (x, -128, 127))
2923 if (SMALL_OPERAND (x))
2924 return COSTS_N_INSNS (1);
2928 /* Like LE, but reject the always-true case. */
2932 /* We add 1 to the immediate and use SLT. */
2935 /* We can use CMPI for an xor with an unsigned 16-bit X. */
2938 if (IN_RANGE (x, 0, 255))
2940 if (SMALL_OPERAND_UNSIGNED (x))
2941 return COSTS_N_INSNS (1);
2946 /* Equality comparisons with 0 are cheap. */
2956 /* Return true if there is a non-MIPS16 instruction that implements CODE
2957 and if that instruction accepts X as an immediate operand. */
2960 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
2967 /* All shift counts are truncated to a valid constant. */
2972 /* Likewise rotates, if the target supports rotates at all. */
2978 /* These instructions take 16-bit unsigned immediates. */
2979 return SMALL_OPERAND_UNSIGNED (x);
2984 /* These instructions take 16-bit signed immediates. */
2985 return SMALL_OPERAND (x);
2991 /* The "immediate" forms of these instructions are really
2992 implemented as comparisons with register 0. */
2997 /* Likewise, meaning that the only valid immediate operand is 1. */
3001 /* We add 1 to the immediate and use SLT. */
3002 return SMALL_OPERAND (x + 1);
3005 /* Likewise SLTU, but reject the always-true case. */
3006 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3010 /* The bit position and size are immediate operands. */
3011 return ISA_HAS_EXT_INS;
3014 /* By default assume that $0 can be used for 0. */
3019 /* Return the cost of binary operation X, given that the instruction
3020 sequence for a word-sized or smaller operation has cost SINGLE_COST
3021 and that the sequence of a double-word operation has cost DOUBLE_COST. */
3024 mips_binary_cost (rtx x, int single_cost, int double_cost)
3028 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3033 + rtx_cost (XEXP (x, 0), 0)
3034 + rtx_cost (XEXP (x, 1), GET_CODE (x)));
3037 /* Return the cost of floating-point multiplications of mode MODE. */
3040 mips_fp_mult_cost (enum machine_mode mode)
3042 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3045 /* Return the cost of floating-point divisions of mode MODE. */
3048 mips_fp_div_cost (enum machine_mode mode)
3050 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3053 /* Return the cost of sign-extending OP to mode MODE, not including the
3054 cost of OP itself. */
3057 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3060 /* Extended loads are as cheap as unextended ones. */
3063 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3064 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3067 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3068 /* We can use SEB or SEH. */
3069 return COSTS_N_INSNS (1);
3071 /* We need to use a shift left and a shift right. */
3072 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3075 /* Return the cost of zero-extending OP to mode MODE, not including the
3076 cost of OP itself. */
3079 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3082 /* Extended loads are as cheap as unextended ones. */
3085 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3086 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3087 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3089 if (GENERATE_MIPS16E)
3090 /* We can use ZEB or ZEH. */
3091 return COSTS_N_INSNS (1);
3094 /* We need to load 0xff or 0xffff into a register and use AND. */
3095 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3097 /* We can use ANDI. */
3098 return COSTS_N_INSNS (1);
3101 /* Implement TARGET_RTX_COSTS. */
3104 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
3106 enum machine_mode mode = GET_MODE (x);
3107 bool float_mode_p = FLOAT_MODE_P (mode);
3111 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3112 appear in the instruction stream, and the cost of a comparison is
3113 really the cost of the branch or scc condition. At the time of
3114 writing, GCC only uses an explicit outer COMPARE code when optabs
3115 is testing whether a constant is expensive enough to force into a
3116 register. We want optabs to pass such constants through the MIPS
3117 expanders instead, so make all constants very cheap here. */
3118 if (outer_code == COMPARE)
3120 gcc_assert (CONSTANT_P (x));
3128 /* Treat *clear_upper32-style ANDs as having zero cost in the
3129 second operand. The cost is entirely in the first operand.
3131 ??? This is needed because we would otherwise try to CSE
3132 the constant operand. Although that's the right thing for
3133 instructions that continue to be a register operation throughout
3134 compilation, it is disastrous for instructions that could
3135 later be converted into a memory operation. */
3137 && outer_code == AND
3138 && UINTVAL (x) == 0xffffffff)
3146 cost = mips16_constant_cost (outer_code, INTVAL (x));
3155 /* When not optimizing for size, we care more about the cost
3156 of hot code, and hot code is often in a loop. If a constant
3157 operand needs to be forced into a register, we will often be
3158 able to hoist the constant load out of the loop, so the load
3159 should not contribute to the cost. */
3161 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3173 if (force_to_mem_operand (x, VOIDmode))
3175 *total = COSTS_N_INSNS (1);
3178 cost = mips_const_insns (x);
3181 /* If the constant is likely to be stored in a GPR, SETs of
3182 single-insn constants are as cheap as register sets; we
3183 never want to CSE them.
3185 Don't reduce the cost of storing a floating-point zero in
3186 FPRs. If we have a zero in an FPR for other reasons, we
3187 can get better cfg-cleanup and delayed-branch results by
3188 using it consistently, rather than using $0 sometimes and
3189 an FPR at other times. Also, moves between floating-point
3190 registers are sometimes cheaper than (D)MTC1 $0. */
3192 && outer_code == SET
3193 && !(float_mode_p && TARGET_HARD_FLOAT))
3195 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3196 want to CSE the constant itself. It is usually better to
3197 have N copies of the last operation in the sequence and one
3198 shared copy of the other operations. (Note that this is
3199 not true for MIPS16 code, where the final operation in the
3200 sequence is often an extended instruction.)
3202 Also, if we have a CONST_INT, we don't know whether it is
3203 for a word or doubleword operation, so we cannot rely on
3204 the result of mips_build_integer. */
3205 else if (!TARGET_MIPS16
3206 && (outer_code == SET || mode == VOIDmode))
3208 *total = COSTS_N_INSNS (cost);
3211 /* The value will need to be fetched from the constant pool. */
3212 *total = CONSTANT_POOL_COST;
3216 /* If the address is legitimate, return the number of
3217 instructions it needs. */
3219 cost = mips_address_insns (addr, mode, true);
3222 *total = COSTS_N_INSNS (cost + 1);
3225 /* Check for a scaled indexed address. */
3226 if (mips_lwxs_address_p (addr))
3228 *total = COSTS_N_INSNS (2);
3231 /* Otherwise use the default handling. */
3235 *total = COSTS_N_INSNS (6);
3239 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3243 /* Check for a *clear_upper32 pattern and treat it like a zero
3244 extension. See the pattern's comment for details. */
3247 && CONST_INT_P (XEXP (x, 1))
3248 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3250 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3251 + rtx_cost (XEXP (x, 0), 0));
3258 /* Double-word operations use two single-word operations. */
3259 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3267 if (CONSTANT_P (XEXP (x, 1)))
3268 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3270 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3275 *total = mips_cost->fp_add;
3277 *total = COSTS_N_INSNS (4);
3281 /* Low-part immediates need an extended MIPS16 instruction. */
3282 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3283 + rtx_cost (XEXP (x, 0), 0));
3298 /* Branch comparisons have VOIDmode, so use the first operand's
3300 mode = GET_MODE (XEXP (x, 0));
3301 if (FLOAT_MODE_P (mode))
3303 *total = mips_cost->fp_add;
3306 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3311 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3312 && TARGET_FUSED_MADD
3313 && !HONOR_NANS (mode)
3314 && !HONOR_SIGNED_ZEROS (mode))
3316 /* See if we can use NMADD or NMSUB. See mips.md for the
3317 associated patterns. */
3318 rtx op0 = XEXP (x, 0);
3319 rtx op1 = XEXP (x, 1);
3320 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3322 *total = (mips_fp_mult_cost (mode)
3323 + rtx_cost (XEXP (XEXP (op0, 0), 0), 0)
3324 + rtx_cost (XEXP (op0, 1), 0)
3325 + rtx_cost (op1, 0));
3328 if (GET_CODE (op1) == MULT)
3330 *total = (mips_fp_mult_cost (mode)
3332 + rtx_cost (XEXP (op1, 0), 0)
3333 + rtx_cost (XEXP (op1, 1), 0));
3342 /* If this is part of a MADD or MSUB, treat the PLUS as
3345 && TARGET_FUSED_MADD
3346 && GET_CODE (XEXP (x, 0)) == MULT)
3349 *total = mips_cost->fp_add;
3353 /* Double-word operations require three single-word operations and
3354 an SLTU. The MIPS16 version then needs to move the result of
3355 the SLTU from $24 to a MIPS16 register. */
3356 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3357 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3362 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3363 && TARGET_FUSED_MADD
3364 && !HONOR_NANS (mode)
3365 && HONOR_SIGNED_ZEROS (mode))
3367 /* See if we can use NMADD or NMSUB. See mips.md for the
3368 associated patterns. */
3369 rtx op = XEXP (x, 0);
3370 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3371 && GET_CODE (XEXP (op, 0)) == MULT)
3373 *total = (mips_fp_mult_cost (mode)
3374 + rtx_cost (XEXP (XEXP (op, 0), 0), 0)
3375 + rtx_cost (XEXP (XEXP (op, 0), 1), 0)
3376 + rtx_cost (XEXP (op, 1), 0));
3382 *total = mips_cost->fp_add;
3384 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3389 *total = mips_fp_mult_cost (mode);
3390 else if (mode == DImode && !TARGET_64BIT)
3391 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3392 where the mulsidi3 always includes an MFHI and an MFLO. */
3393 *total = (optimize_size
3394 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3395 : mips_cost->int_mult_si * 3 + 6);
3396 else if (optimize_size)
3397 *total = (ISA_HAS_MUL3 ? 1 : 2);
3398 else if (mode == DImode)
3399 *total = mips_cost->int_mult_di;
3401 *total = mips_cost->int_mult_si;
3405 /* Check for a reciprocal. */
3408 && flag_unsafe_math_optimizations
3409 && XEXP (x, 0) == CONST1_RTX (mode))
3411 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3412 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3413 division as being free. */
3414 *total = rtx_cost (XEXP (x, 1), 0);
3416 *total = mips_fp_div_cost (mode) + rtx_cost (XEXP (x, 1), 0);
3425 *total = mips_fp_div_cost (mode);
3434 /* It is our responsibility to make division by a power of 2
3435 as cheap as 2 register additions if we want the division
3436 expanders to be used for such operations; see the setting
3437 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3438 should always produce shorter code than using
3439 expand_sdiv2_pow2. */
3441 && CONST_INT_P (XEXP (x, 1))
3442 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3444 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), 0);
3447 *total = COSTS_N_INSNS (mips_idiv_insns ());
3449 else if (mode == DImode)
3450 *total = mips_cost->int_div_di;
3452 *total = mips_cost->int_div_si;
3456 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3460 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3464 case UNSIGNED_FLOAT:
3467 case FLOAT_TRUNCATE:
3468 *total = mips_cost->fp_add;
3476 /* Implement TARGET_ADDRESS_COST. */
3479 mips_address_cost (rtx addr)
3481 return mips_address_insns (addr, SImode, false);
3484 /* Return one word of double-word value OP, taking into account the fixed
3485 endianness of certain registers. HIGH_P is true to select the high part,
3486 false to select the low part. */
3489 mips_subword (rtx op, bool high_p)
3491 unsigned int byte, offset;
3492 enum machine_mode mode;
3494 mode = GET_MODE (op);
3495 if (mode == VOIDmode)
3496 mode = TARGET_64BIT ? TImode : DImode;
3498 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3499 byte = UNITS_PER_WORD;
3503 if (FP_REG_RTX_P (op))
3505 /* Paired FPRs are always ordered little-endian. */
3506 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3507 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3511 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3513 return simplify_gen_subreg (word_mode, op, mode, byte);
3516 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3519 mips_split_64bit_move_p (rtx dest, rtx src)
3524 /* FPR-to-FPR moves can be done in a single instruction, if they're
3526 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3529 /* Check for floating-point loads and stores. */
3530 if (ISA_HAS_LDC1_SDC1)
3532 if (FP_REG_RTX_P (dest) && MEM_P (src))
3534 if (FP_REG_RTX_P (src) && MEM_P (dest))
3540 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3541 this function handles 64-bit moves for which mips_split_64bit_move_p
3542 holds. For 64-bit targets, this function handles 128-bit moves. */
3545 mips_split_doubleword_move (rtx dest, rtx src)
3549 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3551 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3552 emit_insn (gen_move_doubleword_fprdi (dest, src));
3553 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3554 emit_insn (gen_move_doubleword_fprdf (dest, src));
3555 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
3556 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
3557 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
3558 emit_insn (gen_move_doubleword_fprv2si (dest, src));
3559 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
3560 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
3561 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
3562 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
3563 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3564 emit_insn (gen_move_doubleword_fprtf (dest, src));
3568 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
3570 low_dest = mips_subword (dest, false);
3571 mips_emit_move (low_dest, mips_subword (src, false));
3573 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
3575 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
3577 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
3579 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
3581 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
3583 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
3587 /* The operation can be split into two normal moves. Decide in
3588 which order to do them. */
3589 low_dest = mips_subword (dest, false);
3590 if (REG_P (low_dest)
3591 && reg_overlap_mentioned_p (low_dest, src))
3593 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3594 mips_emit_move (low_dest, mips_subword (src, false));
3598 mips_emit_move (low_dest, mips_subword (src, false));
3599 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3604 /* Return the appropriate instructions to move SRC into DEST. Assume
3605 that SRC is operand 1 and DEST is operand 0. */
3608 mips_output_move (rtx dest, rtx src)
3610 enum rtx_code dest_code, src_code;
3611 enum machine_mode mode;
3612 enum mips_symbol_type symbol_type;
3615 dest_code = GET_CODE (dest);
3616 src_code = GET_CODE (src);
3617 mode = GET_MODE (dest);
3618 dbl_p = (GET_MODE_SIZE (mode) == 8);
3620 if (dbl_p && mips_split_64bit_move_p (dest, src))
3623 if ((src_code == REG && GP_REG_P (REGNO (src)))
3624 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
3626 if (dest_code == REG)
3628 if (GP_REG_P (REGNO (dest)))
3629 return "move\t%0,%z1";
3631 /* Moves to HI are handled by special .md insns. */
3632 if (REGNO (dest) == LO_REGNUM)
3635 if (DSP_ACC_REG_P (REGNO (dest)))
3637 static char retval[] = "mt__\t%z1,%q0";
3639 retval[2] = reg_names[REGNO (dest)][4];
3640 retval[3] = reg_names[REGNO (dest)][5];
3644 if (FP_REG_P (REGNO (dest)))
3645 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
3647 if (ALL_COP_REG_P (REGNO (dest)))
3649 static char retval[] = "dmtc_\t%z1,%0";
3651 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3652 return dbl_p ? retval : retval + 1;
3655 if (dest_code == MEM)
3656 switch (GET_MODE_SIZE (mode))
3658 case 1: return "sb\t%z1,%0";
3659 case 2: return "sh\t%z1,%0";
3660 case 4: return "sw\t%z1,%0";
3661 case 8: return "sd\t%z1,%0";
3664 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3666 if (src_code == REG)
3668 /* Moves from HI are handled by special .md insns. */
3669 if (REGNO (src) == LO_REGNUM)
3671 /* When generating VR4120 or VR4130 code, we use MACC and
3672 DMACC instead of MFLO. This avoids both the normal
3673 MIPS III HI/LO hazards and the errata related to
3676 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
3680 if (DSP_ACC_REG_P (REGNO (src)))
3682 static char retval[] = "mf__\t%0,%q1";
3684 retval[2] = reg_names[REGNO (src)][4];
3685 retval[3] = reg_names[REGNO (src)][5];
3689 if (FP_REG_P (REGNO (src)))
3690 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
3692 if (ALL_COP_REG_P (REGNO (src)))
3694 static char retval[] = "dmfc_\t%0,%1";
3696 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3697 return dbl_p ? retval : retval + 1;
3700 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3701 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3704 if (src_code == MEM)
3705 switch (GET_MODE_SIZE (mode))
3707 case 1: return "lbu\t%0,%1";
3708 case 2: return "lhu\t%0,%1";
3709 case 4: return "lw\t%0,%1";
3710 case 8: return "ld\t%0,%1";
3713 if (src_code == CONST_INT)
3715 /* Don't use the X format for the operand itself, because that
3716 will give out-of-range numbers for 64-bit hosts and 32-bit
3719 return "li\t%0,%1\t\t\t# %X1";
3721 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
3724 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
3728 if (src_code == HIGH)
3729 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
3731 if (CONST_GP_P (src))
3732 return "move\t%0,%1";
3734 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
3735 && mips_lo_relocs[symbol_type] != 0)
3737 /* A signed 16-bit constant formed by applying a relocation
3738 operator to a symbolic address. */
3739 gcc_assert (!mips_split_p[symbol_type]);
3740 return "li\t%0,%R1";
3743 if (symbolic_operand (src, VOIDmode))
3745 gcc_assert (TARGET_MIPS16
3746 ? TARGET_MIPS16_TEXT_LOADS
3747 : !TARGET_EXPLICIT_RELOCS);
3748 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
3751 if (src_code == REG && FP_REG_P (REGNO (src)))
3753 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3755 if (GET_MODE (dest) == V2SFmode)
3756 return "mov.ps\t%0,%1";
3758 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
3761 if (dest_code == MEM)
3762 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
3764 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3766 if (src_code == MEM)
3767 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
3769 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3771 static char retval[] = "l_c_\t%0,%1";
3773 retval[1] = (dbl_p ? 'd' : 'w');
3774 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3777 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3779 static char retval[] = "s_c_\t%1,%0";
3781 retval[1] = (dbl_p ? 'd' : 'w');
3782 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3788 /* Return true if CMP1 is a suitable second operand for integer ordering
3789 test CODE. See also the *sCC patterns in mips.md. */
3792 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
3798 return reg_or_0_operand (cmp1, VOIDmode);
3802 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3806 return arith_operand (cmp1, VOIDmode);
3809 return sle_operand (cmp1, VOIDmode);
3812 return sleu_operand (cmp1, VOIDmode);
3819 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
3820 integer ordering test *CODE, or if an equivalent combination can
3821 be formed by adjusting *CODE and *CMP1. When returning true, update
3822 *CODE and *CMP1 with the chosen code and operand, otherwise leave
3826 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
3827 enum machine_mode mode)
3829 HOST_WIDE_INT plus_one;
3831 if (mips_int_order_operand_ok_p (*code, *cmp1))
3834 if (GET_CODE (*cmp1) == CONST_INT)
3838 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3839 if (INTVAL (*cmp1) < plus_one)
3842 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3848 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3852 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3863 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
3864 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
3865 is nonnull, it's OK to set TARGET to the inverse of the result and
3866 flip *INVERT_PTR instead. */
3869 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
3870 rtx target, rtx cmp0, rtx cmp1)
3872 enum machine_mode mode;
3874 /* First see if there is a MIPS instruction that can do this operation.
3875 If not, try doing the same for the inverse operation. If that also
3876 fails, force CMP1 into a register and try again. */
3877 mode = GET_MODE (cmp0);
3878 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
3879 mips_emit_binary (code, target, cmp0, cmp1);
3882 enum rtx_code inv_code = reverse_condition (code);
3883 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
3885 cmp1 = force_reg (mode, cmp1);
3886 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
3888 else if (invert_ptr == 0)
3892 inv_target = mips_force_binary (GET_MODE (target),
3893 inv_code, cmp0, cmp1);
3894 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3898 *invert_ptr = !*invert_ptr;
3899 mips_emit_binary (inv_code, target, cmp0, cmp1);
3904 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3905 The register will have the same mode as CMP0. */
3908 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3910 if (cmp1 == const0_rtx)
3913 if (uns_arith_operand (cmp1, VOIDmode))
3914 return expand_binop (GET_MODE (cmp0), xor_optab,
3915 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3917 return expand_binop (GET_MODE (cmp0), sub_optab,
3918 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3921 /* Convert *CODE into a code that can be used in a floating-point
3922 scc instruction (C.cond.fmt). Return true if the values of
3923 the condition code registers will be inverted, with 0 indicating
3924 that the condition holds. */
3927 mips_reversed_fp_cond (enum rtx_code *code)
3934 *code = reverse_condition_maybe_unordered (*code);
3942 /* Convert a comparison into something that can be used in a branch or
3943 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3944 being compared and *CODE is the code used to compare them.
3946 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3947 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
3948 otherwise any standard branch condition can be used. The standard branch
3951 - EQ or NE between two registers.
3952 - any comparison between a register and zero. */
3955 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3957 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3959 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3961 *op0 = cmp_operands[0];
3962 *op1 = cmp_operands[1];
3964 else if (*code == EQ || *code == NE)
3968 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3973 *op0 = cmp_operands[0];
3974 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3979 /* The comparison needs a separate scc instruction. Store the
3980 result of the scc in *OP0 and compare it against zero. */
3981 bool invert = false;
3982 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3983 mips_emit_int_order_test (*code, &invert, *op0,
3984 cmp_operands[0], cmp_operands[1]);
3985 *code = (invert ? EQ : NE);
3989 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands[0])))
3991 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
3992 mips_emit_binary (*code, *op0, cmp_operands[0], cmp_operands[1]);
3998 enum rtx_code cmp_code;
4000 /* Floating-point tests use a separate C.cond.fmt comparison to
4001 set a condition code register. The branch or conditional move
4002 will then compare that register against zero.
4004 Set CMP_CODE to the code of the comparison instruction and
4005 *CODE to the code that the branch or move should use. */
4007 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4009 ? gen_reg_rtx (CCmode)
4010 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4012 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
4016 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
4017 Store the result in TARGET and return true if successful.
4019 On 64-bit targets, TARGET may be narrower than cmp_operands[0]. */
4022 mips_expand_scc (enum rtx_code code, rtx target)
4024 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
4027 if (code == EQ || code == NE)
4029 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
4030 mips_emit_binary (code, target, zie, const0_rtx);
4033 mips_emit_int_order_test (code, 0, target,
4034 cmp_operands[0], cmp_operands[1]);
4038 /* Compare cmp_operands[0] with cmp_operands[1] using comparison code
4039 CODE and jump to OPERANDS[0] if the condition holds. */
4042 mips_expand_conditional_branch (rtx *operands, enum rtx_code code)
4044 rtx op0, op1, condition;
4046 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4047 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4048 emit_jump_insn (gen_condjump (condition, operands[0]));
4053 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4054 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4057 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4058 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4063 reversed_p = mips_reversed_fp_cond (&cond);
4064 cmp_result = gen_reg_rtx (CCV2mode);
4065 emit_insn (gen_scc_ps (cmp_result,
4066 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4068 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4071 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4075 /* Compare cmp_operands[0] with cmp_operands[1] using the code of
4076 OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition
4077 holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4080 mips_expand_conditional_move (rtx *operands)
4085 code = GET_CODE (operands[1]);
4086 mips_emit_compare (&code, &op0, &op1, true);
4087 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1),
4088 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4089 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4090 operands[2], operands[3])));
4093 /* Compare cmp_operands[0] with cmp_operands[1] using rtl code CODE,
4094 then trap if the condition holds. */
4097 mips_expand_conditional_trap (enum rtx_code code)
4100 enum machine_mode mode;
4102 /* MIPS conditional trap instructions don't have GT or LE flavors,
4103 so we must swap the operands and convert to LT and GE respectively. */
4110 code = swap_condition (code);
4111 op0 = cmp_operands[1];
4112 op1 = cmp_operands[0];
4116 op0 = cmp_operands[0];
4117 op1 = cmp_operands[1];
4121 mode = GET_MODE (cmp_operands[0]);
4122 op0 = force_reg (mode, op0);
4123 if (!arith_operand (op1, mode))
4124 op1 = force_reg (mode, op1);
4126 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4127 gen_rtx_fmt_ee (code, mode, op0, op1),
4131 /* Initialize *CUM for a call to a function of type FNTYPE. */
4134 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4136 memset (cum, 0, sizeof (*cum));
4137 cum->prototype = (fntype && prototype_p (fntype));
4138 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4141 /* Fill INFO with information about a single argument. CUM is the
4142 cumulative state for earlier arguments. MODE is the mode of this
4143 argument and TYPE is its type (if known). NAMED is true if this
4144 is a named (fixed) argument rather than a variable one. */
4147 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4148 enum machine_mode mode, tree type, int named)
4150 bool doubleword_aligned_p;
4151 unsigned int num_bytes, num_words, max_regs;
4153 /* Work out the size of the argument. */
4154 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4155 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4157 /* Decide whether it should go in a floating-point register, assuming
4158 one is free. Later code checks for availability.
4160 The checks against UNITS_PER_FPVALUE handle the soft-float and
4161 single-float cases. */
4165 /* The EABI conventions have traditionally been defined in terms
4166 of TYPE_MODE, regardless of the actual type. */
4167 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4168 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4169 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4174 /* Only leading floating-point scalars are passed in
4175 floating-point registers. We also handle vector floats the same
4176 say, which is OK because they are not covered by the standard ABI. */
4177 info->fpr_p = (!cum->gp_reg_found
4178 && cum->arg_number < 2
4180 || SCALAR_FLOAT_TYPE_P (type)
4181 || VECTOR_FLOAT_TYPE_P (type))
4182 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4183 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4184 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4189 /* Scalar, complex and vector floating-point types are passed in
4190 floating-point registers, as long as this is a named rather
4191 than a variable argument. */
4192 info->fpr_p = (named
4193 && (type == 0 || FLOAT_TYPE_P (type))
4194 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4195 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4196 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4197 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4199 /* ??? According to the ABI documentation, the real and imaginary
4200 parts of complex floats should be passed in individual registers.
4201 The real and imaginary parts of stack arguments are supposed
4202 to be contiguous and there should be an extra word of padding
4205 This has two problems. First, it makes it impossible to use a
4206 single "void *" va_list type, since register and stack arguments
4207 are passed differently. (At the time of writing, MIPSpro cannot
4208 handle complex float varargs correctly.) Second, it's unclear
4209 what should happen when there is only one register free.
4211 For now, we assume that named complex floats should go into FPRs
4212 if there are two FPRs free, otherwise they should be passed in the
4213 same way as a struct containing two floats. */
4215 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4216 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4218 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4219 info->fpr_p = false;
4229 /* See whether the argument has doubleword alignment. */
4230 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4232 /* Set REG_OFFSET to the register count we're interested in.
4233 The EABI allocates the floating-point registers separately,
4234 but the other ABIs allocate them like integer registers. */
4235 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4239 /* Advance to an even register if the argument is doubleword-aligned. */
4240 if (doubleword_aligned_p)
4241 info->reg_offset += info->reg_offset & 1;
4243 /* Work out the offset of a stack argument. */
4244 info->stack_offset = cum->stack_words;
4245 if (doubleword_aligned_p)
4246 info->stack_offset += info->stack_offset & 1;
4248 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4250 /* Partition the argument between registers and stack. */
4251 info->reg_words = MIN (num_words, max_regs);
4252 info->stack_words = num_words - info->reg_words;
4255 /* INFO describes a register argument that has the normal format for the
4256 argument's mode. Return the register it uses, assuming that FPRs are
4257 available if HARD_FLOAT_P. */
4260 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4262 if (!info->fpr_p || !hard_float_p)
4263 return GP_ARG_FIRST + info->reg_offset;
4264 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4265 /* In o32, the second argument is always passed in $f14
4266 for TARGET_DOUBLE_FLOAT, regardless of whether the
4267 first argument was a word or doubleword. */
4268 return FP_ARG_FIRST + 2;
4270 return FP_ARG_FIRST + info->reg_offset;
4273 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4276 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4278 return !TARGET_OLDABI;
4281 /* Implement FUNCTION_ARG. */
4284 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4285 tree type, int named)
4287 struct mips_arg_info info;
4289 /* We will be called with a mode of VOIDmode after the last argument
4290 has been seen. Whatever we return will be passed to the call expander.
4291 If we need a MIPS16 fp_code, return a REG with the code stored as
4293 if (mode == VOIDmode)
4295 if (TARGET_MIPS16 && cum->fp_code != 0)
4296 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4301 mips_get_arg_info (&info, cum, mode, type, named);
4303 /* Return straight away if the whole argument is passed on the stack. */
4304 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4307 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4308 contains a double in its entirety, then that 64-bit chunk is passed
4309 in a floating-point register. */
4311 && TARGET_HARD_FLOAT
4314 && TREE_CODE (type) == RECORD_TYPE
4315 && TYPE_SIZE_UNIT (type)
4316 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4320 /* First check to see if there is any such field. */
4321 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4322 if (TREE_CODE (field) == FIELD_DECL
4323 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4324 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4325 && host_integerp (bit_position (field), 0)
4326 && int_bit_position (field) % BITS_PER_WORD == 0)
4331 /* Now handle the special case by returning a PARALLEL
4332 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4333 chunks are passed in registers. */
4335 HOST_WIDE_INT bitpos;
4338 /* assign_parms checks the mode of ENTRY_PARM, so we must
4339 use the actual mode here. */
4340 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4343 field = TYPE_FIELDS (type);
4344 for (i = 0; i < info.reg_words; i++)
4348 for (; field; field = TREE_CHAIN (field))
4349 if (TREE_CODE (field) == FIELD_DECL
4350 && int_bit_position (field) >= bitpos)
4354 && int_bit_position (field) == bitpos
4355 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4356 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4357 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4359 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4362 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4363 GEN_INT (bitpos / BITS_PER_UNIT));
4365 bitpos += BITS_PER_WORD;
4371 /* Handle the n32/n64 conventions for passing complex floating-point
4372 arguments in FPR pairs. The real part goes in the lower register
4373 and the imaginary part goes in the upper register. */
4376 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4379 enum machine_mode inner;
4382 inner = GET_MODE_INNER (mode);
4383 regno = FP_ARG_FIRST + info.reg_offset;
4384 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4386 /* Real part in registers, imaginary part on stack. */
4387 gcc_assert (info.stack_words == info.reg_words);
4388 return gen_rtx_REG (inner, regno);
4392 gcc_assert (info.stack_words == 0);
4393 real = gen_rtx_EXPR_LIST (VOIDmode,
4394 gen_rtx_REG (inner, regno),
4396 imag = gen_rtx_EXPR_LIST (VOIDmode,
4398 regno + info.reg_words / 2),
4399 GEN_INT (GET_MODE_SIZE (inner)));
4400 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4404 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4407 /* Implement FUNCTION_ARG_ADVANCE. */
4410 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4411 tree type, int named)
4413 struct mips_arg_info info;
4415 mips_get_arg_info (&info, cum, mode, type, named);
4418 cum->gp_reg_found = true;
4420 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4421 an explanation of what this code does. It assumes that we're using
4422 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4424 if (cum->arg_number < 2 && info.fpr_p)
4425 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4427 /* Advance the register count. This has the effect of setting
4428 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4429 argument required us to skip the final GPR and pass the whole
4430 argument on the stack. */
4431 if (mips_abi != ABI_EABI || !info.fpr_p)
4432 cum->num_gprs = info.reg_offset + info.reg_words;
4433 else if (info.reg_words > 0)
4434 cum->num_fprs += MAX_FPRS_PER_FMT;
4436 /* Advance the stack word count. */
4437 if (info.stack_words > 0)
4438 cum->stack_words = info.stack_offset + info.stack_words;
4443 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4446 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4447 enum machine_mode mode, tree type, bool named)
4449 struct mips_arg_info info;
4451 mips_get_arg_info (&info, cum, mode, type, named);
4452 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4455 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4456 PARM_BOUNDARY bits of alignment, but will be given anything up
4457 to STACK_BOUNDARY bits if the type requires it. */
4460 mips_function_arg_boundary (enum machine_mode mode, tree type)
4462 unsigned int alignment;
4464 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4465 if (alignment < PARM_BOUNDARY)
4466 alignment = PARM_BOUNDARY;
4467 if (alignment > STACK_BOUNDARY)
4468 alignment = STACK_BOUNDARY;
4472 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4473 upward rather than downward. In other words, return true if the
4474 first byte of the stack slot has useful data, false if the last
4478 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4480 /* On little-endian targets, the first byte of every stack argument
4481 is passed in the first byte of the stack slot. */
4482 if (!BYTES_BIG_ENDIAN)
4485 /* Otherwise, integral types are padded downward: the last byte of a
4486 stack argument is passed in the last byte of the stack slot. */
4488 ? (INTEGRAL_TYPE_P (type)
4489 || POINTER_TYPE_P (type)
4490 || FIXED_POINT_TYPE_P (type))
4491 : (SCALAR_INT_MODE_P (mode)
4492 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4495 /* Big-endian o64 pads floating-point arguments downward. */
4496 if (mips_abi == ABI_O64)
4497 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4500 /* Other types are padded upward for o32, o64, n32 and n64. */
4501 if (mips_abi != ABI_EABI)
4504 /* Arguments smaller than a stack slot are padded downward. */
4505 if (mode != BLKmode)
4506 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4508 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4511 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4512 if the least significant byte of the register has useful data. Return
4513 the opposite if the most significant byte does. */
4516 mips_pad_reg_upward (enum machine_mode mode, tree type)
4518 /* No shifting is required for floating-point arguments. */
4519 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4520 return !BYTES_BIG_ENDIAN;
4522 /* Otherwise, apply the same padding to register arguments as we do
4523 to stack arguments. */
4524 return mips_pad_arg_upward (mode, type);
4527 /* Return nonzero when an argument must be passed by reference. */
4530 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4531 enum machine_mode mode, const_tree type,
4532 bool named ATTRIBUTE_UNUSED)
4534 if (mips_abi == ABI_EABI)
4538 /* ??? How should SCmode be handled? */
4539 if (mode == DImode || mode == DFmode
4540 || mode == DQmode || mode == UDQmode
4541 || mode == DAmode || mode == UDAmode)
4544 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4545 return size == -1 || size > UNITS_PER_WORD;
4549 /* If we have a variable-sized parameter, we have no choice. */
4550 return targetm.calls.must_pass_in_stack (mode, type);
4554 /* Implement TARGET_CALLEE_COPIES. */
4557 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4558 enum machine_mode mode ATTRIBUTE_UNUSED,
4559 const_tree type ATTRIBUTE_UNUSED, bool named)
4561 return mips_abi == ABI_EABI && named;
4564 /* See whether VALTYPE is a record whose fields should be returned in
4565 floating-point registers. If so, return the number of fields and
4566 list them in FIELDS (which should have two elements). Return 0
4569 For n32 & n64, a structure with one or two fields is returned in
4570 floating-point registers as long as every field has a floating-point
4574 mips_fpr_return_fields (const_tree valtype, tree *fields)
4582 if (TREE_CODE (valtype) != RECORD_TYPE)
4586 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
4588 if (TREE_CODE (field) != FIELD_DECL)
4591 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
4597 fields[i++] = field;
4602 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4603 a value in the most significant part of $2/$3 if:
4605 - the target is big-endian;
4607 - the value has a structure or union type (we generalize this to
4608 cover aggregates from other languages too); and
4610 - the structure is not returned in floating-point registers. */
4613 mips_return_in_msb (const_tree valtype)
4617 return (TARGET_NEWABI
4618 && TARGET_BIG_ENDIAN
4619 && AGGREGATE_TYPE_P (valtype)
4620 && mips_fpr_return_fields (valtype, fields) == 0);
4623 /* Return true if the function return value MODE will get returned in a
4624 floating-point register. */
4627 mips_return_mode_in_fpr_p (enum machine_mode mode)
4629 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
4630 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
4631 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4632 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
4635 /* Return the representation of an FPR return register when the
4636 value being returned in FP_RETURN has mode VALUE_MODE and the
4637 return type itself has mode TYPE_MODE. On NewABI targets,
4638 the two modes may be different for structures like:
4640 struct __attribute__((packed)) foo { float f; }
4642 where we return the SFmode value of "f" in FP_RETURN, but where
4643 the structure itself has mode BLKmode. */
4646 mips_return_fpr_single (enum machine_mode type_mode,
4647 enum machine_mode value_mode)
4651 x = gen_rtx_REG (value_mode, FP_RETURN);
4652 if (type_mode != value_mode)
4654 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
4655 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
4660 /* Return a composite value in a pair of floating-point registers.
4661 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4662 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4665 For n32 & n64, $f0 always holds the first value and $f2 the second.
4666 Otherwise the values are packed together as closely as possible. */
4669 mips_return_fpr_pair (enum machine_mode mode,
4670 enum machine_mode mode1, HOST_WIDE_INT offset1,
4671 enum machine_mode mode2, HOST_WIDE_INT offset2)
4675 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
4676 return gen_rtx_PARALLEL
4679 gen_rtx_EXPR_LIST (VOIDmode,
4680 gen_rtx_REG (mode1, FP_RETURN),
4682 gen_rtx_EXPR_LIST (VOIDmode,
4683 gen_rtx_REG (mode2, FP_RETURN + inc),
4684 GEN_INT (offset2))));
4688 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4689 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4690 VALTYPE is null and MODE is the mode of the return value. */
4693 mips_function_value (const_tree valtype, enum machine_mode mode)
4700 mode = TYPE_MODE (valtype);
4701 unsigned_p = TYPE_UNSIGNED (valtype);
4703 /* Since TARGET_PROMOTE_FUNCTION_RETURN unconditionally returns true,
4704 we must promote the mode just as PROMOTE_MODE does. */
4705 mode = promote_mode (valtype, mode, &unsigned_p, 1);
4707 /* Handle structures whose fields are returned in $f0/$f2. */
4708 switch (mips_fpr_return_fields (valtype, fields))
4711 return mips_return_fpr_single (mode,
4712 TYPE_MODE (TREE_TYPE (fields[0])));
4715 return mips_return_fpr_pair (mode,
4716 TYPE_MODE (TREE_TYPE (fields[0])),
4717 int_byte_position (fields[0]),
4718 TYPE_MODE (TREE_TYPE (fields[1])),
4719 int_byte_position (fields[1]));
4722 /* If a value is passed in the most significant part of a register, see
4723 whether we have to round the mode up to a whole number of words. */
4724 if (mips_return_in_msb (valtype))
4726 HOST_WIDE_INT size = int_size_in_bytes (valtype);
4727 if (size % UNITS_PER_WORD != 0)
4729 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
4730 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4734 /* For EABI, the class of return register depends entirely on MODE.
4735 For example, "struct { some_type x; }" and "union { some_type x; }"
4736 are returned in the same way as a bare "some_type" would be.
4737 Other ABIs only use FPRs for scalar, complex or vector types. */
4738 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
4739 return gen_rtx_REG (mode, GP_RETURN);
4744 /* Handle long doubles for n32 & n64. */
4746 return mips_return_fpr_pair (mode,
4748 DImode, GET_MODE_SIZE (mode) / 2);
4750 if (mips_return_mode_in_fpr_p (mode))
4752 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4753 return mips_return_fpr_pair (mode,
4754 GET_MODE_INNER (mode), 0,
4755 GET_MODE_INNER (mode),
4756 GET_MODE_SIZE (mode) / 2);
4758 return gen_rtx_REG (mode, FP_RETURN);
4762 return gen_rtx_REG (mode, GP_RETURN);
4765 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
4766 all BLKmode objects are returned in memory. Under the n32, n64
4767 and embedded ABIs, small structures are returned in a register.
4768 Objects with varying size must still be returned in memory, of
4772 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
4774 return (TARGET_OLDABI
4775 ? TYPE_MODE (type) == BLKmode
4776 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
4779 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
4782 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4783 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4786 CUMULATIVE_ARGS local_cum;
4787 int gp_saved, fp_saved;
4789 /* The caller has advanced CUM up to, but not beyond, the last named
4790 argument. Advance a local copy of CUM past the last "real" named
4791 argument, to find out how many registers are left over. */
4793 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
4795 /* Found out how many registers we need to save. */
4796 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4797 fp_saved = (EABI_FLOAT_VARARGS_P
4798 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4807 ptr = plus_constant (virtual_incoming_args_rtx,
4808 REG_PARM_STACK_SPACE (cfun->decl)
4809 - gp_saved * UNITS_PER_WORD);
4810 mem = gen_frame_mem (BLKmode, ptr);
4811 set_mem_alias_set (mem, get_varargs_alias_set ());
4813 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4818 /* We can't use move_block_from_reg, because it will use
4820 enum machine_mode mode;
4823 /* Set OFF to the offset from virtual_incoming_args_rtx of
4824 the first float register. The FP save area lies below
4825 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4826 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
4827 off -= fp_saved * UNITS_PER_FPREG;
4829 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4831 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
4832 i += MAX_FPRS_PER_FMT)
4836 ptr = plus_constant (virtual_incoming_args_rtx, off);
4837 mem = gen_frame_mem (mode, ptr);
4838 set_mem_alias_set (mem, get_varargs_alias_set ());
4839 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4840 off += UNITS_PER_HWFPVALUE;
4844 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4845 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4846 + fp_saved * UNITS_PER_FPREG);
4849 /* Implement TARGET_BUILTIN_VA_LIST. */
4852 mips_build_builtin_va_list (void)
4854 if (EABI_FLOAT_VARARGS_P)
4856 /* We keep 3 pointers, and two offsets.
4858 Two pointers are to the overflow area, which starts at the CFA.
4859 One of these is constant, for addressing into the GPR save area
4860 below it. The other is advanced up the stack through the
4863 The third pointer is to the bottom of the GPR save area.
4864 Since the FPR save area is just below it, we can address
4865 FPR slots off this pointer.
4867 We also keep two one-byte offsets, which are to be subtracted
4868 from the constant pointers to yield addresses in the GPR and
4869 FPR save areas. These are downcounted as float or non-float
4870 arguments are used, and when they get to zero, the argument
4871 must be obtained from the overflow region. */
4872 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4875 record = lang_hooks.types.make_type (RECORD_TYPE);
4877 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4879 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4881 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4883 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4884 unsigned_char_type_node);
4885 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4886 unsigned_char_type_node);
4887 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4888 warn on every user file. */
4889 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4890 array = build_array_type (unsigned_char_type_node,
4891 build_index_type (index));
4892 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4894 DECL_FIELD_CONTEXT (f_ovfl) = record;
4895 DECL_FIELD_CONTEXT (f_gtop) = record;
4896 DECL_FIELD_CONTEXT (f_ftop) = record;
4897 DECL_FIELD_CONTEXT (f_goff) = record;
4898 DECL_FIELD_CONTEXT (f_foff) = record;
4899 DECL_FIELD_CONTEXT (f_res) = record;
4901 TYPE_FIELDS (record) = f_ovfl;
4902 TREE_CHAIN (f_ovfl) = f_gtop;
4903 TREE_CHAIN (f_gtop) = f_ftop;
4904 TREE_CHAIN (f_ftop) = f_goff;
4905 TREE_CHAIN (f_goff) = f_foff;
4906 TREE_CHAIN (f_foff) = f_res;
4908 layout_type (record);
4911 else if (TARGET_IRIX && TARGET_IRIX6)
4912 /* On IRIX 6, this type is 'char *'. */
4913 return build_pointer_type (char_type_node);
4915 /* Otherwise, we use 'void *'. */
4916 return ptr_type_node;
4919 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
4922 mips_va_start (tree valist, rtx nextarg)
4924 if (EABI_FLOAT_VARARGS_P)
4926 const CUMULATIVE_ARGS *cum;
4927 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4928 tree ovfl, gtop, ftop, goff, foff;
4930 int gpr_save_area_size;
4931 int fpr_save_area_size;
4934 cum = &crtl->args.info;
4936 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4938 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4940 f_ovfl = TYPE_FIELDS (va_list_type_node);
4941 f_gtop = TREE_CHAIN (f_ovfl);
4942 f_ftop = TREE_CHAIN (f_gtop);
4943 f_goff = TREE_CHAIN (f_ftop);
4944 f_foff = TREE_CHAIN (f_goff);
4946 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4948 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4950 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4952 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4954 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4957 /* Emit code to initialize OVFL, which points to the next varargs
4958 stack argument. CUM->STACK_WORDS gives the number of stack
4959 words used by named arguments. */
4960 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4961 if (cum->stack_words > 0)
4962 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
4963 size_int (cum->stack_words * UNITS_PER_WORD));
4964 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4965 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4967 /* Emit code to initialize GTOP, the top of the GPR save area. */
4968 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4969 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4970 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4972 /* Emit code to initialize FTOP, the top of the FPR save area.
4973 This address is gpr_save_area_bytes below GTOP, rounded
4974 down to the next fp-aligned boundary. */
4975 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4976 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4977 fpr_offset &= -UNITS_PER_FPVALUE;
4979 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
4980 size_int (-fpr_offset));
4981 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4982 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4984 /* Emit code to initialize GOFF, the offset from GTOP of the
4985 next GPR argument. */
4986 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
4987 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
4988 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4990 /* Likewise emit code to initialize FOFF, the offset from FTOP
4991 of the next FPR argument. */
4992 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
4993 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
4994 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4998 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4999 std_expand_builtin_va_start (valist, nextarg);
5003 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5006 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5012 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5014 type = build_pointer_type (type);
5016 if (!EABI_FLOAT_VARARGS_P)
5017 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5020 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5021 tree ovfl, top, off, align;
5022 HOST_WIDE_INT size, rsize, osize;
5025 f_ovfl = TYPE_FIELDS (va_list_type_node);
5026 f_gtop = TREE_CHAIN (f_ovfl);
5027 f_ftop = TREE_CHAIN (f_gtop);
5028 f_goff = TREE_CHAIN (f_ftop);
5029 f_foff = TREE_CHAIN (f_goff);
5033 TOP be the top of the GPR or FPR save area;
5034 OFF be the offset from TOP of the next register;
5035 ADDR_RTX be the address of the argument;
5036 SIZE be the number of bytes in the argument type;
5037 RSIZE be the number of bytes used to store the argument
5038 when it's in the register save area; and
5039 OSIZE be the number of bytes used to store it when it's
5040 in the stack overflow area.
5042 The code we want is:
5044 1: off &= -rsize; // round down
5047 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5052 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5053 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5057 [1] and [9] can sometimes be optimized away. */
5059 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5061 size = int_size_in_bytes (type);
5063 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5064 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5066 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5068 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5071 /* When va_start saves FPR arguments to the stack, each slot
5072 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5073 argument's precision. */
5074 rsize = UNITS_PER_HWFPVALUE;
5076 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5077 (= PARM_BOUNDARY bits). This can be different from RSIZE
5080 (1) On 32-bit targets when TYPE is a structure such as:
5082 struct s { float f; };
5084 Such structures are passed in paired FPRs, so RSIZE
5085 will be 8 bytes. However, the structure only takes
5086 up 4 bytes of memory, so OSIZE will only be 4.
5088 (2) In combinations such as -mgp64 -msingle-float
5089 -fshort-double. Doubles passed in registers will then take
5090 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5091 stack take up UNITS_PER_WORD bytes. */
5092 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5096 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5098 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5100 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5101 if (rsize > UNITS_PER_WORD)
5103 /* [1] Emit code for: off &= -rsize. */
5104 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
5105 build_int_cst (NULL_TREE, -rsize));
5106 gimplify_assign (off, t, pre_p);
5111 /* [2] Emit code to branch if off == 0. */
5112 t = build2 (NE_EXPR, boolean_type_node, off,
5113 build_int_cst (TREE_TYPE (off), 0));
5114 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5116 /* [5] Emit code for: off -= rsize. We do this as a form of
5117 post-decrement not available to C. */
5118 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5119 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5121 /* [4] Emit code for:
5122 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5123 t = fold_convert (sizetype, t);
5124 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5125 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5126 if (BYTES_BIG_ENDIAN && rsize > size)
5128 u = size_int (rsize - size);
5129 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5131 COND_EXPR_THEN (addr) = t;
5133 if (osize > UNITS_PER_WORD)
5135 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5136 u = size_int (osize - 1);
5137 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
5138 t = fold_convert (sizetype, t);
5139 u = size_int (-osize);
5140 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5141 t = fold_convert (TREE_TYPE (ovfl), t);
5142 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5147 /* [10, 11] Emit code for:
5148 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5150 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5151 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5152 if (BYTES_BIG_ENDIAN && osize > size)
5154 u = size_int (osize - size);
5155 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5158 /* String [9] and [10, 11] together. */
5160 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5161 COND_EXPR_ELSE (addr) = t;
5163 addr = fold_convert (build_pointer_type (type), addr);
5164 addr = build_va_arg_indirect_ref (addr);
5168 addr = build_va_arg_indirect_ref (addr);
5173 /* Start a definition of function NAME. MIPS16_P indicates whether the
5174 function contains MIPS16 code. */
5177 mips_start_function_definition (const char *name, bool mips16_p)
5180 fprintf (asm_out_file, "\t.set\tmips16\n");
5182 fprintf (asm_out_file, "\t.set\tnomips16\n");
5184 if (!flag_inhibit_size_directive)
5186 fputs ("\t.ent\t", asm_out_file);
5187 assemble_name (asm_out_file, name);
5188 fputs ("\n", asm_out_file);
5191 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5193 /* Start the definition proper. */
5194 assemble_name (asm_out_file, name);
5195 fputs (":\n", asm_out_file);
5198 /* End a function definition started by mips_start_function_definition. */
5201 mips_end_function_definition (const char *name)
5203 if (!flag_inhibit_size_directive)
5205 fputs ("\t.end\t", asm_out_file);
5206 assemble_name (asm_out_file, name);
5207 fputs ("\n", asm_out_file);
5211 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5214 mips_ok_for_lazy_binding_p (rtx x)
5216 return (TARGET_USE_GOT
5217 && GET_CODE (x) == SYMBOL_REF
5218 && !mips_symbol_binds_local_p (x));
5221 /* Load function address ADDR into register DEST. SIBCALL_P is true
5222 if the address is needed for a sibling call. Return true if we
5223 used an explicit lazy-binding sequence. */
5226 mips_load_call_address (rtx dest, rtx addr, bool sibcall_p)
5228 /* If we're generating PIC, and this call is to a global function,
5229 try to allow its address to be resolved lazily. This isn't
5230 possible for sibcalls when $gp is call-saved because the value
5231 of $gp on entry to the stub would be our caller's gp, not ours. */
5232 if (TARGET_EXPLICIT_RELOCS
5233 && !(sibcall_p && TARGET_CALL_SAVED_GP)
5234 && mips_ok_for_lazy_binding_p (addr))
5236 rtx high, lo_sum_symbol;
5238 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
5239 addr, SYMBOL_GOTOFF_CALL);
5240 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
5241 if (Pmode == SImode)
5242 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
5244 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
5249 mips_emit_move (dest, addr);
5254 /* A chained list of functions for which mips16_build_call_stub has already
5255 generated a stub. NAME is the name of the function and FP_RET_P is true
5256 if the function returns a value in floating-point registers. */
5257 struct mips16_stub {
5258 struct mips16_stub *next;
5262 static struct mips16_stub *mips16_stubs;
5264 /* Return the two-character string that identifies floating-point
5265 return mode MODE in the name of a MIPS16 function stub. */
5268 mips16_call_stub_mode_suffix (enum machine_mode mode)
5272 else if (mode == DFmode)
5274 else if (mode == SCmode)
5276 else if (mode == DCmode)
5278 else if (mode == V2SFmode)
5284 /* Write instructions to move a 32-bit value between general register
5285 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5286 from GPREG to FPREG and 'f' to move in the opposite direction. */
5289 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5291 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5292 reg_names[gpreg], reg_names[fpreg]);
5295 /* Likewise for 64-bit values. */
5298 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5301 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5302 reg_names[gpreg], reg_names[fpreg]);
5303 else if (TARGET_FLOAT64)
5305 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5306 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5307 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5308 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5312 /* Move the least-significant word. */
5313 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5314 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5315 /* ...then the most significant word. */
5316 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5317 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5321 /* Write out code to move floating-point arguments into or out of
5322 general registers. FP_CODE is the code describing which arguments
5323 are present (see the comment above the definition of CUMULATIVE_ARGS
5324 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5327 mips_output_args_xfer (int fp_code, char direction)
5329 unsigned int gparg, fparg, f;
5330 CUMULATIVE_ARGS cum;
5332 /* This code only works for o32 and o64. */
5333 gcc_assert (TARGET_OLDABI);
5335 mips_init_cumulative_args (&cum, NULL);
5337 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5339 enum machine_mode mode;
5340 struct mips_arg_info info;
5344 else if ((f & 3) == 2)
5349 mips_get_arg_info (&info, &cum, mode, NULL, true);
5350 gparg = mips_arg_regno (&info, false);
5351 fparg = mips_arg_regno (&info, true);
5354 mips_output_32bit_xfer (direction, gparg, fparg);
5356 mips_output_64bit_xfer (direction, gparg, fparg);
5358 mips_function_arg_advance (&cum, mode, NULL, true);
5362 /* Write a MIPS16 stub for the current function. This stub is used
5363 for functions which take arguments in the floating-point registers.
5364 It is normal-mode code that moves the floating-point arguments
5365 into the general registers and then jumps to the MIPS16 code. */
5368 mips16_build_function_stub (void)
5370 const char *fnname, *separator;
5371 char *secname, *stubname;
5375 /* Create the name of the stub, and its unique section. */
5376 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5377 fnname = targetm.strip_name_encoding (fnname);
5378 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5379 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5381 /* Build a decl for the stub. */
5382 stubdecl = build_decl (FUNCTION_DECL, get_identifier (stubname),
5383 build_function_type (void_type_node, NULL_TREE));
5384 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5385 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
5387 /* Output a comment. */
5388 fprintf (asm_out_file, "\t# Stub function for %s (",
5389 current_function_name ());
5391 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5393 fprintf (asm_out_file, "%s%s", separator,
5394 (f & 3) == 1 ? "float" : "double");
5397 fprintf (asm_out_file, ")\n");
5399 /* Start the function definition. */
5400 assemble_start_function (stubdecl, stubname);
5401 mips_start_function_definition (stubname, false);
5403 /* Load the address of the MIPS16 function into $at. Do this first so
5404 that targets with coprocessor interlocks can use an MFC1 to fill the
5406 fprintf (asm_out_file, "\t.set\tnoat\n");
5407 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
5408 assemble_name (asm_out_file, fnname);
5409 fprintf (asm_out_file, "\n");
5411 /* Move the arguments from floating-point registers to general registers. */
5412 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
5414 /* Jump to the MIPS16 function. */
5415 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5416 fprintf (asm_out_file, "\t.set\tat\n");
5418 mips_end_function_definition (stubname);
5420 switch_to_section (function_section (current_function_decl));
5423 /* The current function is a MIPS16 function that returns a value in an FPR.
5424 Copy the return value from its soft-float to its hard-float location.
5425 libgcc2 has special non-MIPS16 helper functions for each case. */
5428 mips16_copy_fpr_return_value (void)
5430 rtx fn, insn, arg, call;
5431 tree id, return_type;
5432 enum machine_mode return_mode;
5434 return_type = DECL_RESULT (current_function_decl);
5435 return_mode = DECL_MODE (return_type);
5437 id = get_identifier (ACONCAT (("__mips16_ret_",
5438 mips16_call_stub_mode_suffix (return_mode),
5440 fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5441 arg = gen_rtx_REG (return_mode, GP_RETURN);
5442 call = gen_call_value_internal (arg, fn, const0_rtx);
5443 insn = mips_emit_call_insn (call, false);
5444 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), arg);
5447 /* Consider building a stub for a MIPS16 call to function FN.
5448 RETVAL is the location of the return value, or null if this is
5449 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5450 arguments and FP_CODE is the code built by mips_function_arg;
5451 see the comment above CUMULATIVE_ARGS for details.
5453 If a stub was needed, emit the call and return the call insn itself.
5454 Return null otherwise.
5456 A stub is needed for calls to functions that, in normal mode,
5457 receive arguments in FPRs or return values in FPRs. The stub
5458 copies the arguments from their soft-float positions to their
5459 hard-float positions, calls the real function, then copies the
5460 return value from its hard-float position to its soft-float
5463 We emit a JAL to FN even when FN might need a stub. If FN turns out
5464 to be to a non-MIPS16 function, the linker automatically redirects
5465 the JAL to the stub, otherwise the JAL continues to call FN directly. */
5468 mips16_build_call_stub (rtx retval, rtx fn, rtx args_size, int fp_code)
5472 struct mips16_stub *l;
5475 /* We don't need to do anything if we aren't in MIPS16 mode, or if
5476 we were invoked with the -msoft-float option. */
5477 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
5480 /* Figure out whether the value might come back in a floating-point
5482 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
5484 /* We don't need to do anything if there were no floating-point
5485 arguments and the value will not be returned in a floating-point
5487 if (fp_code == 0 && !fp_ret_p)
5490 /* We don't need to do anything if this is a call to a special
5491 MIPS16 support function. */
5492 if (GET_CODE (fn) == SYMBOL_REF
5493 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
5496 /* This code will only work for o32 and o64 abis. The other ABI's
5497 require more sophisticated support. */
5498 gcc_assert (TARGET_OLDABI);
5500 /* If we're calling via a function pointer, use one of the magic
5501 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
5502 Each stub expects the function address to arrive in register $2. */
5503 if (GET_CODE (fn) != SYMBOL_REF)
5509 /* Create a SYMBOL_REF for the libgcc.a function. */
5511 sprintf (buf, "__mips16_call_stub_%s_%d",
5512 mips16_call_stub_mode_suffix (GET_MODE (retval)),
5515 sprintf (buf, "__mips16_call_stub_%d", fp_code);
5516 id = get_identifier (buf);
5517 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5519 /* Load the target function into $2. */
5520 mips_emit_move (gen_rtx_REG (Pmode, 2), fn);
5522 /* Emit the call. */
5523 if (retval == NULL_RTX)
5524 insn = gen_call_internal (stub_fn, args_size);
5526 insn = gen_call_value_internal (retval, stub_fn, args_size);
5527 insn = mips_emit_call_insn (insn, false);
5529 /* Tell GCC that this call does indeed use the value of $2. */
5530 CALL_INSN_FUNCTION_USAGE (insn) =
5531 gen_rtx_EXPR_LIST (VOIDmode,
5532 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
5533 CALL_INSN_FUNCTION_USAGE (insn));
5535 /* If we are handling a floating-point return value, we need to
5536 save $18 in the function prologue. Putting a note on the
5537 call will mean that df_regs_ever_live_p ($18) will be true if the
5538 call is not eliminated, and we can check that in the prologue
5541 CALL_INSN_FUNCTION_USAGE (insn) =
5542 gen_rtx_EXPR_LIST (VOIDmode,
5543 gen_rtx_USE (VOIDmode,
5544 gen_rtx_REG (word_mode, 18)),
5545 CALL_INSN_FUNCTION_USAGE (insn));
5550 /* We know the function we are going to call. If we have already
5551 built a stub, we don't need to do anything further. */
5552 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
5553 for (l = mips16_stubs; l != NULL; l = l->next)
5554 if (strcmp (l->name, fnname) == 0)
5559 const char *separator;
5560 char *secname, *stubname;
5561 tree stubid, stubdecl;
5564 /* If the function does not return in FPRs, the special stub
5568 If the function does return in FPRs, the stub section is named
5569 .mips16.call.fp.FNNAME
5571 Build a decl for the stub. */
5572 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
5574 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
5576 stubid = get_identifier (stubname);
5577 stubdecl = build_decl (FUNCTION_DECL, stubid,
5578 build_function_type (void_type_node, NULL_TREE));
5579 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5580 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE,
5583 /* Output a comment. */
5584 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
5586 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
5590 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5592 fprintf (asm_out_file, "%s%s", separator,
5593 (f & 3) == 1 ? "float" : "double");
5596 fprintf (asm_out_file, ")\n");
5598 /* Start the function definition. */
5599 assemble_start_function (stubdecl, stubname);
5600 mips_start_function_definition (stubname, false);
5604 /* Load the address of the MIPS16 function into $at. Do this
5605 first so that targets with coprocessor interlocks can use
5606 an MFC1 to fill the delay slot. */
5607 fprintf (asm_out_file, "\t.set\tnoat\n");
5608 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
5612 /* Move the arguments from general registers to floating-point
5614 mips_output_args_xfer (fp_code, 't');
5618 /* Jump to the previously-loaded address. */
5619 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5620 fprintf (asm_out_file, "\t.set\tat\n");
5624 /* Save the return address in $18 and call the non-MIPS16 function.
5625 The stub's caller knows that $18 might be clobbered, even though
5626 $18 is usually a call-saved register. */
5627 fprintf (asm_out_file, "\tmove\t%s,%s\n",
5628 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
5629 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
5631 /* Move the result from floating-point registers to
5632 general registers. */
5633 switch (GET_MODE (retval))
5636 mips_output_32bit_xfer ('f', GP_RETURN + 1,
5637 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5640 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5641 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
5643 /* On 64-bit targets, complex floats are returned in
5644 a single GPR, such that "sd" on a suitably-aligned
5645 target would store the value correctly. */
5646 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
5647 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
5648 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
5649 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
5650 reg_names[GP_RETURN],
5651 reg_names[GP_RETURN],
5652 reg_names[GP_RETURN + 1]);
5657 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
5658 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5662 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5668 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
5671 #ifdef ASM_DECLARE_FUNCTION_SIZE
5672 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
5675 mips_end_function_definition (stubname);
5677 /* Record this stub. */
5678 l = XNEW (struct mips16_stub);
5679 l->name = xstrdup (fnname);
5680 l->fp_ret_p = fp_ret_p;
5681 l->next = mips16_stubs;
5685 /* If we expect a floating-point return value, but we've built a
5686 stub which does not expect one, then we're in trouble. We can't
5687 use the existing stub, because it won't handle the floating-point
5688 value. We can't build a new stub, because the linker won't know
5689 which stub to use for the various calls in this object file.
5690 Fortunately, this case is illegal, since it means that a function
5691 was declared in two different ways in a single compilation. */
5692 if (fp_ret_p && !l->fp_ret_p)
5693 error ("cannot handle inconsistent calls to %qs", fnname);
5695 if (retval == NULL_RTX)
5696 insn = gen_call_internal_direct (fn, args_size);
5698 insn = gen_call_value_internal_direct (retval, fn, args_size);
5699 insn = mips_emit_call_insn (insn, false);
5701 /* If we are calling a stub which handles a floating-point return
5702 value, we need to arrange to save $18 in the prologue. We do this
5703 by marking the function call as using the register. The prologue
5704 will later see that it is used, and emit code to save it. */
5706 CALL_INSN_FUNCTION_USAGE (insn) =
5707 gen_rtx_EXPR_LIST (VOIDmode,
5708 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
5709 CALL_INSN_FUNCTION_USAGE (insn));
5714 /* Expand a "call", "sibcall", "call_value" or "sibcall_value" instruction.
5715 RESULT is where the result will go (null for "call"s and "sibcall"s),
5716 ADDR is the address of the function, ARGS_SIZE is the size of the
5717 arguments and AUX is the value passed to us by mips_function_arg.
5718 SIBCALL_P is true if we are expanding a sibling call, false if we're
5719 expanding a normal call.
5721 Return the call itself. */
5724 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, bool sibcall_p)
5726 rtx orig_addr, pattern, insn;
5731 if (!call_insn_operand (addr, VOIDmode))
5733 addr = gen_reg_rtx (Pmode);
5734 lazy_p = mips_load_call_address (addr, orig_addr, sibcall_p);
5737 insn = mips16_build_call_stub (result, addr, args_size,
5738 aux == 0 ? 0 : (int) GET_MODE (aux));
5741 gcc_assert (!sibcall_p && !lazy_p);
5746 pattern = (sibcall_p
5747 ? gen_sibcall_internal (addr, args_size)
5748 : gen_call_internal (addr, args_size));
5749 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
5751 /* Handle return values created by mips_return_fpr_pair. */
5754 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
5755 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
5758 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
5759 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
5763 /* Handle return values created by mips_return_fpr_single. */
5764 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
5765 result = XEXP (XVECEXP (result, 0, 0), 0);
5766 pattern = (sibcall_p
5767 ? gen_sibcall_value_internal (result, addr, args_size)
5768 : gen_call_value_internal (result, addr, args_size));
5771 return mips_emit_call_insn (pattern, lazy_p);
5774 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
5777 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5779 if (!TARGET_SIBCALLS)
5782 /* We can't do a sibcall if the called function is a MIPS16 function
5783 because there is no direct "jx" instruction equivalent to "jalx" to
5784 switch the ISA mode. We only care about cases where the sibling
5785 and normal calls would both be direct. */
5786 if (mips_use_mips16_mode_p (decl)
5787 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
5790 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
5791 functions could be MIPS16 ones unless an attribute explicitly tells
5793 if (TARGET_INTERLINK_MIPS16
5795 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
5796 && !mips_nomips16_decl_p (decl)
5797 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
5804 /* Emit code to move general operand SRC into condition-code
5805 register DEST given that SCRATCH is a scratch TFmode FPR.
5812 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
5815 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
5819 /* Change the source to SFmode. */
5821 src = adjust_address (src, SFmode, 0);
5822 else if (REG_P (src) || GET_CODE (src) == SUBREG)
5823 src = gen_rtx_REG (SFmode, true_regnum (src));
5825 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
5826 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
5828 mips_emit_move (copy_rtx (fp1), src);
5829 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
5830 emit_insn (gen_slt_sf (dest, fp2, fp1));
5833 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
5834 Assume that the areas do not overlap. */
5837 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
5839 HOST_WIDE_INT offset, delta;
5840 unsigned HOST_WIDE_INT bits;
5842 enum machine_mode mode;
5845 /* Work out how many bits to move at a time. If both operands have
5846 half-word alignment, it is usually better to move in half words.
5847 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
5848 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
5849 Otherwise move word-sized chunks. */
5850 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
5851 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
5852 bits = BITS_PER_WORD / 2;
5854 bits = BITS_PER_WORD;
5856 mode = mode_for_size (bits, MODE_INT, 0);
5857 delta = bits / BITS_PER_UNIT;
5859 /* Allocate a buffer for the temporary registers. */
5860 regs = XALLOCAVEC (rtx, length / delta);
5862 /* Load as many BITS-sized chunks as possible. Use a normal load if
5863 the source has enough alignment, otherwise use left/right pairs. */
5864 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5866 regs[i] = gen_reg_rtx (mode);
5867 if (MEM_ALIGN (src) >= bits)
5868 mips_emit_move (regs[i], adjust_address (src, mode, offset));
5871 rtx part = adjust_address (src, BLKmode, offset);
5872 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
5877 /* Copy the chunks to the destination. */
5878 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5879 if (MEM_ALIGN (dest) >= bits)
5880 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
5883 rtx part = adjust_address (dest, BLKmode, offset);
5884 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
5888 /* Mop up any left-over bytes. */
5889 if (offset < length)
5891 src = adjust_address (src, BLKmode, offset);
5892 dest = adjust_address (dest, BLKmode, offset);
5893 move_by_pieces (dest, src, length - offset,
5894 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
5898 /* Helper function for doing a loop-based block operation on memory
5899 reference MEM. Each iteration of the loop will operate on LENGTH
5902 Create a new base register for use within the loop and point it to
5903 the start of MEM. Create a new memory reference that uses this
5904 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
5907 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
5908 rtx *loop_reg, rtx *loop_mem)
5910 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
5912 /* Although the new mem does not refer to a known location,
5913 it does keep up to LENGTH bytes of alignment. */
5914 *loop_mem = change_address (mem, BLKmode, *loop_reg);
5915 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
5918 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
5919 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
5920 the memory regions do not overlap. */
5923 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
5924 HOST_WIDE_INT bytes_per_iter)
5926 rtx label, src_reg, dest_reg, final_src;
5927 HOST_WIDE_INT leftover;
5929 leftover = length % bytes_per_iter;
5932 /* Create registers and memory references for use within the loop. */
5933 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
5934 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
5936 /* Calculate the value that SRC_REG should have after the last iteration
5938 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
5941 /* Emit the start of the loop. */
5942 label = gen_label_rtx ();
5945 /* Emit the loop body. */
5946 mips_block_move_straight (dest, src, bytes_per_iter);
5948 /* Move on to the next block. */
5949 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
5950 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
5952 /* Emit the loop condition. */
5953 if (Pmode == DImode)
5954 emit_insn (gen_cmpdi (src_reg, final_src));
5956 emit_insn (gen_cmpsi (src_reg, final_src));
5957 emit_jump_insn (gen_bne (label));
5959 /* Mop up any left-over bytes. */
5961 mips_block_move_straight (dest, src, leftover);
5964 /* Expand a movmemsi instruction, which copies LENGTH bytes from
5965 memory reference SRC to memory reference DEST. */
5968 mips_expand_block_move (rtx dest, rtx src, rtx length)
5970 if (GET_CODE (length) == CONST_INT)
5972 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
5974 mips_block_move_straight (dest, src, INTVAL (length));
5979 mips_block_move_loop (dest, src, INTVAL (length),
5980 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
5987 /* Expand a loop of synci insns for the address range [BEGIN, END). */
5990 mips_expand_synci_loop (rtx begin, rtx end)
5992 rtx inc, label, cmp, cmp_result;
5994 /* Load INC with the cache line size (rdhwr INC,$1). */
5995 inc = gen_reg_rtx (SImode);
5996 emit_insn (gen_rdhwr (inc, const1_rtx));
5998 /* Loop back to here. */
5999 label = gen_label_rtx ();
6002 emit_insn (gen_synci (begin));
6004 cmp = mips_force_binary (Pmode, GTU, begin, end);
6006 mips_emit_binary (PLUS, begin, begin, inc);
6008 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
6009 emit_jump_insn (gen_condjump (cmp_result, label));
6012 /* Expand a QI or HI mode atomic memory operation.
6014 GENERATOR contains a pointer to the gen_* function that generates
6015 the SI mode underlying atomic operation using masks that we
6018 RESULT is the return register for the operation. Its value is NULL
6021 MEM is the location of the atomic access.
6023 OLDVAL is the first operand for the operation.
6025 NEWVAL is the optional second operand for the operation. Its value
6026 is NULL if unused. */
6029 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6030 rtx result, rtx mem, rtx oldval, rtx newval)
6032 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6033 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6035 enum machine_mode mode;
6037 mode = GET_MODE (mem);
6039 /* Compute the address of the containing SImode value. */
6040 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6041 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6042 force_reg (Pmode, GEN_INT (-4)));
6044 /* Create a memory reference for it. */
6045 memsi = gen_rtx_MEM (SImode, memsi_addr);
6046 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6047 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6049 /* Work out the byte offset of the QImode or HImode value,
6050 counting from the least significant byte. */
6051 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6052 if (TARGET_BIG_ENDIAN)
6053 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6055 /* Multiply by eight to convert the shift value from bytes to bits. */
6056 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6058 /* Make the final shift an SImode value, so that it can be used in
6059 SImode operations. */
6060 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6062 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6063 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6064 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6065 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6067 /* Compute the equivalent exclusive mask. */
6068 inverted_mask = gen_reg_rtx (SImode);
6069 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6070 gen_rtx_NOT (SImode, mask)));
6072 /* Shift the old value into place. */
6073 if (oldval != const0_rtx)
6075 oldval = convert_modes (SImode, mode, oldval, true);
6076 oldval = force_reg (SImode, oldval);
6077 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6080 /* Do the same for the new value. */
6081 if (newval && newval != const0_rtx)
6083 newval = convert_modes (SImode, mode, newval, true);
6084 newval = force_reg (SImode, newval);
6085 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6088 /* Do the SImode atomic access. */
6090 res = gen_reg_rtx (SImode);
6092 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6094 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6096 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6102 /* Shift and convert the result. */
6103 mips_emit_binary (AND, res, res, mask);
6104 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6105 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6109 /* Return true if it is possible to use left/right accesses for a
6110 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6111 returning true, update *OP, *LEFT and *RIGHT as follows:
6113 *OP is a BLKmode reference to the whole field.
6115 *LEFT is a QImode reference to the first byte if big endian or
6116 the last byte if little endian. This address can be used in the
6117 left-side instructions (LWL, SWL, LDL, SDL).
6119 *RIGHT is a QImode reference to the opposite end of the field and
6120 can be used in the patterning right-side instruction. */
6123 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6124 rtx *left, rtx *right)
6128 /* Check that the operand really is a MEM. Not all the extv and
6129 extzv predicates are checked. */
6133 /* Check that the size is valid. */
6134 if (width != 32 && (!TARGET_64BIT || width != 64))
6137 /* We can only access byte-aligned values. Since we are always passed
6138 a reference to the first byte of the field, it is not necessary to
6139 do anything with BITPOS after this check. */
6140 if (bitpos % BITS_PER_UNIT != 0)
6143 /* Reject aligned bitfields: we want to use a normal load or store
6144 instead of a left/right pair. */
6145 if (MEM_ALIGN (*op) >= width)
6148 /* Adjust *OP to refer to the whole field. This also has the effect
6149 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6150 *op = adjust_address (*op, BLKmode, 0);
6151 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6153 /* Get references to both ends of the field. We deliberately don't
6154 use the original QImode *OP for FIRST since the new BLKmode one
6155 might have a simpler address. */
6156 first = adjust_address (*op, QImode, 0);
6157 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6159 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6160 correspond to the MSB and RIGHT to the LSB. */
6161 if (TARGET_BIG_ENDIAN)
6162 *left = first, *right = last;
6164 *left = last, *right = first;
6169 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6170 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6171 the operation is the equivalent of:
6173 (set DEST (*_extract SRC WIDTH BITPOS))
6175 Return true on success. */
6178 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6179 HOST_WIDE_INT bitpos)
6181 rtx left, right, temp;
6183 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6184 be a paradoxical word_mode subreg. This is the only case in which
6185 we allow the destination to be larger than the source. */
6186 if (GET_CODE (dest) == SUBREG
6187 && GET_MODE (dest) == DImode
6188 && GET_MODE (SUBREG_REG (dest)) == SImode)
6189 dest = SUBREG_REG (dest);
6191 /* After the above adjustment, the destination must be the same
6192 width as the source. */
6193 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6196 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6199 temp = gen_reg_rtx (GET_MODE (dest));
6200 if (GET_MODE (dest) == DImode)
6202 emit_insn (gen_mov_ldl (temp, src, left));
6203 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6207 emit_insn (gen_mov_lwl (temp, src, left));
6208 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6213 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6214 BITPOS and SRC are the operands passed to the expander; the operation
6215 is the equivalent of:
6217 (set (zero_extract DEST WIDTH BITPOS) SRC)
6219 Return true on success. */
6222 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6223 HOST_WIDE_INT bitpos)
6226 enum machine_mode mode;
6228 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6231 mode = mode_for_size (width, MODE_INT, 0);
6232 src = gen_lowpart (mode, src);
6235 emit_insn (gen_mov_sdl (dest, src, left));
6236 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6240 emit_insn (gen_mov_swl (dest, src, left));
6241 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6246 /* Return true if X is a MEM with the same size as MODE. */
6249 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6256 size = MEM_SIZE (x);
6257 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6260 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6261 source of an "ext" instruction or the destination of an "ins"
6262 instruction. OP must be a register operand and the following
6263 conditions must hold:
6265 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6266 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6267 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6269 Also reject lengths equal to a word as they are better handled
6270 by the move patterns. */
6273 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6275 if (!ISA_HAS_EXT_INS
6276 || !register_operand (op, VOIDmode)
6277 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6280 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6283 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
6289 /* Return true if -msplit-addresses is selected and should be honored.
6291 -msplit-addresses is a half-way house between explicit relocations
6292 and the traditional assembler macros. It can split absolute 32-bit
6293 symbolic constants into a high/lo_sum pair but uses macros for other
6296 Like explicit relocation support for REL targets, it relies
6297 on GNU extensions in the assembler and the linker.
6299 Although this code should work for -O0, it has traditionally
6300 been treated as an optimization. */
6303 mips_split_addresses_p (void)
6305 return (TARGET_SPLIT_ADDRESSES
6309 && !ABI_HAS_64BIT_SYMBOLS);
6312 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6315 mips_init_relocs (void)
6317 memset (mips_split_p, '\0', sizeof (mips_split_p));
6318 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
6319 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
6321 if (ABI_HAS_64BIT_SYMBOLS)
6323 if (TARGET_EXPLICIT_RELOCS)
6325 mips_split_p[SYMBOL_64_HIGH] = true;
6326 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
6327 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
6329 mips_split_p[SYMBOL_64_MID] = true;
6330 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
6331 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
6333 mips_split_p[SYMBOL_64_LOW] = true;
6334 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
6335 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
6337 mips_split_p[SYMBOL_ABSOLUTE] = true;
6338 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6343 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
6345 mips_split_p[SYMBOL_ABSOLUTE] = true;
6346 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
6347 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6349 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
6355 /* The high part is provided by a pseudo copy of $gp. */
6356 mips_split_p[SYMBOL_GP_RELATIVE] = true;
6357 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
6360 if (TARGET_EXPLICIT_RELOCS)
6362 /* Small data constants are kept whole until after reload,
6363 then lowered by mips_rewrite_small_data. */
6364 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
6366 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
6369 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
6370 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
6374 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
6375 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
6380 /* The HIGH and LO_SUM are matched by special .md patterns. */
6381 mips_split_p[SYMBOL_GOT_DISP] = true;
6383 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
6384 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
6385 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
6387 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
6388 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
6389 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
6394 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
6396 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
6397 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
6403 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
6404 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
6405 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
6408 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
6409 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
6411 mips_split_p[SYMBOL_DTPREL] = true;
6412 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
6413 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
6415 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
6417 mips_split_p[SYMBOL_TPREL] = true;
6418 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
6419 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
6421 mips_lo_relocs[SYMBOL_HALF] = "%half(";
6424 /* If OP is an UNSPEC address, return the address to which it refers,
6425 otherwise return OP itself. */
6428 mips_strip_unspec_address (rtx op)
6432 split_const (op, &base, &offset);
6433 if (UNSPEC_ADDRESS_P (base))
6434 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6438 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6439 in context CONTEXT. RELOCS is the array of relocations to use. */
6442 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
6443 const char **relocs)
6445 enum mips_symbol_type symbol_type;
6448 symbol_type = mips_classify_symbolic_expression (op, context);
6449 gcc_assert (relocs[symbol_type]);
6451 fputs (relocs[symbol_type], file);
6452 output_addr_const (file, mips_strip_unspec_address (op));
6453 for (p = relocs[symbol_type]; *p != 0; p++)
6458 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6459 The punctuation characters are:
6461 '(' Start a nested ".set noreorder" block.
6462 ')' End a nested ".set noreorder" block.
6463 '[' Start a nested ".set noat" block.
6464 ']' End a nested ".set noat" block.
6465 '<' Start a nested ".set nomacro" block.
6466 '>' End a nested ".set nomacro" block.
6467 '*' Behave like %(%< if generating a delayed-branch sequence.
6468 '#' Print a nop if in a ".set noreorder" block.
6469 '/' Like '#', but do nothing within a delayed-branch sequence.
6470 '?' Print "l" if mips_branch_likely is true
6471 '.' Print the name of the register with a hard-wired zero (zero or $0).
6472 '@' Print the name of the assembler temporary register (at or $1).
6473 '^' Print the name of the pic call-through register (t9 or $25).
6474 '+' Print the name of the gp register (usually gp or $28).
6475 '$' Print the name of the stack pointer register (sp or $29).
6476 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6477 '-' Print ".set pop" under the same conditions for '|'.
6479 See also mips_init_print_operand_pucnt. */
6482 mips_print_operand_punctuation (FILE *file, int ch)
6487 if (set_noreorder++ == 0)
6488 fputs (".set\tnoreorder\n\t", file);
6492 gcc_assert (set_noreorder > 0);
6493 if (--set_noreorder == 0)
6494 fputs ("\n\t.set\treorder", file);
6498 if (set_noat++ == 0)
6499 fputs (".set\tnoat\n\t", file);
6503 gcc_assert (set_noat > 0);
6504 if (--set_noat == 0)
6505 fputs ("\n\t.set\tat", file);
6509 if (set_nomacro++ == 0)
6510 fputs (".set\tnomacro\n\t", file);
6514 gcc_assert (set_nomacro > 0);
6515 if (--set_nomacro == 0)
6516 fputs ("\n\t.set\tmacro", file);
6520 if (final_sequence != 0)
6522 mips_print_operand_punctuation (file, '(');
6523 mips_print_operand_punctuation (file, '<');
6528 if (set_noreorder != 0)
6529 fputs ("\n\tnop", file);
6533 /* Print an extra newline so that the delayed insn is separated
6534 from the following ones. This looks neater and is consistent
6535 with non-nop delayed sequences. */
6536 if (set_noreorder != 0 && final_sequence == 0)
6537 fputs ("\n\tnop\n", file);
6541 if (mips_branch_likely)
6546 fputs (reg_names[GP_REG_FIRST + 0], file);
6550 fputs (reg_names[GP_REG_FIRST + 1], file);
6554 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
6558 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
6562 fputs (reg_names[STACK_POINTER_REGNUM], file);
6567 fputs (".set\tpush\n\t.set\tmips2\n\t", file);
6572 fputs ("\n\t.set\tpop", file);
6581 /* Initialize mips_print_operand_punct. */
6584 mips_init_print_operand_punct (void)
6588 for (p = "()[]<>*#/?.@^+$|-"; *p; p++)
6589 mips_print_operand_punct[(unsigned char) *p] = true;
6592 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
6593 associated with condition CODE. Print the condition part of the
6597 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
6611 /* Conveniently, the MIPS names for these conditions are the same
6612 as their RTL equivalents. */
6613 fputs (GET_RTX_NAME (code), file);
6617 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6622 /* Likewise floating-point branches. */
6625 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
6630 fputs ("c1f", file);
6634 fputs ("c1t", file);
6638 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6643 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
6645 'X' Print CONST_INT OP in hexadecimal format.
6646 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
6647 'd' Print CONST_INT OP in decimal.
6648 'h' Print the high-part relocation associated with OP, after stripping
6650 'R' Print the low-part relocation associated with OP.
6651 'C' Print the integer branch condition for comparison OP.
6652 'N' Print the inverse of the integer branch condition for comparison OP.
6653 'F' Print the FPU branch condition for comparison OP.
6654 'W' Print the inverse of the FPU branch condition for comparison OP.
6655 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
6656 'z' for (eq:?I ...), 'n' for (ne:?I ...).
6657 't' Like 'T', but with the EQ/NE cases reversed
6658 'Y' Print mips_fp_conditions[INTVAL (OP)]
6659 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
6660 'q' Print a DSP accumulator register.
6661 'D' Print the second part of a double-word register or memory operand.
6662 'L' Print the low-order register in a double-word register operand.
6663 'M' Print high-order register in a double-word register operand.
6664 'z' Print $0 if OP is zero, otherwise print OP normally. */
6667 mips_print_operand (FILE *file, rtx op, int letter)
6671 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
6673 mips_print_operand_punctuation (file, letter);
6678 code = GET_CODE (op);
6683 if (GET_CODE (op) == CONST_INT)
6684 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
6686 output_operand_lossage ("invalid use of '%%%c'", letter);
6690 if (GET_CODE (op) == CONST_INT)
6691 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
6693 output_operand_lossage ("invalid use of '%%%c'", letter);
6697 if (GET_CODE (op) == CONST_INT)
6698 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
6700 output_operand_lossage ("invalid use of '%%%c'", letter);
6706 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
6710 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
6714 mips_print_int_branch_condition (file, code, letter);
6718 mips_print_int_branch_condition (file, reverse_condition (code), letter);
6722 mips_print_float_branch_condition (file, code, letter);
6726 mips_print_float_branch_condition (file, reverse_condition (code),
6733 int truth = (code == NE) == (letter == 'T');
6734 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
6739 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
6740 fputs (mips_fp_conditions[UINTVAL (op)], file);
6742 output_operand_lossage ("'%%%c' is not a valid operand prefix",
6749 mips_print_operand (file, op, 0);
6755 if (code == REG && MD_REG_P (REGNO (op)))
6756 fprintf (file, "$ac0");
6757 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
6758 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
6760 output_operand_lossage ("invalid use of '%%%c'", letter);
6768 unsigned int regno = REGNO (op);
6769 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
6770 || (letter == 'L' && TARGET_BIG_ENDIAN)
6773 fprintf (file, "%s", reg_names[regno]);
6779 output_address (plus_constant (XEXP (op, 0), 4));
6781 output_address (XEXP (op, 0));
6785 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
6786 fputs (reg_names[GP_REG_FIRST], file);
6787 else if (CONST_GP_P (op))
6788 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
6790 output_addr_const (file, mips_strip_unspec_address (op));
6796 /* Output address operand X to FILE. */
6799 mips_print_operand_address (FILE *file, rtx x)
6801 struct mips_address_info addr;
6803 if (mips_classify_address (&addr, x, word_mode, true))
6807 mips_print_operand (file, addr.offset, 0);
6808 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6811 case ADDRESS_LO_SUM:
6812 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
6814 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6817 case ADDRESS_CONST_INT:
6818 output_addr_const (file, x);
6819 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
6822 case ADDRESS_SYMBOLIC:
6823 output_addr_const (file, mips_strip_unspec_address (x));
6829 /* Implement TARGET_ENCODE_SECTION_INFO. */
6832 mips_encode_section_info (tree decl, rtx rtl, int first)
6834 default_encode_section_info (decl, rtl, first);
6836 if (TREE_CODE (decl) == FUNCTION_DECL)
6838 rtx symbol = XEXP (rtl, 0);
6839 tree type = TREE_TYPE (decl);
6841 /* Encode whether the symbol is short or long. */
6842 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
6843 || mips_far_type_p (type))
6844 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
6848 /* Implement TARGET_SELECT_RTX_SECTION. */
6851 mips_select_rtx_section (enum machine_mode mode, rtx x,
6852 unsigned HOST_WIDE_INT align)
6854 /* ??? Consider using mergeable small data sections. */
6855 if (mips_rtx_constant_in_small_data_p (mode))
6856 return get_named_section (NULL, ".sdata", 0);
6858 return default_elf_select_rtx_section (mode, x, align);
6861 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6863 The complication here is that, with the combination TARGET_ABICALLS
6864 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6865 therefore not be included in the read-only part of a DSO. Handle such
6866 cases by selecting a normal data section instead of a read-only one.
6867 The logic apes that in default_function_rodata_section. */
6870 mips_function_rodata_section (tree decl)
6872 if (!TARGET_ABICALLS || TARGET_GPWORD)
6873 return default_function_rodata_section (decl);
6875 if (decl && DECL_SECTION_NAME (decl))
6877 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6878 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
6880 char *rname = ASTRDUP (name);
6882 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
6884 else if (flag_function_sections
6885 && flag_data_sections
6886 && strncmp (name, ".text.", 6) == 0)
6888 char *rname = ASTRDUP (name);
6889 memcpy (rname + 1, "data", 4);
6890 return get_section (rname, SECTION_WRITE, decl);
6893 return data_section;
6896 /* Implement TARGET_IN_SMALL_DATA_P. */
6899 mips_in_small_data_p (const_tree decl)
6901 unsigned HOST_WIDE_INT size;
6903 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
6906 /* We don't yet generate small-data references for -mabicalls
6907 or VxWorks RTP code. See the related -G handling in
6908 mips_override_options. */
6909 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
6912 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
6916 /* Reject anything that isn't in a known small-data section. */
6917 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6918 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
6921 /* If a symbol is defined externally, the assembler will use the
6922 usual -G rules when deciding how to implement macros. */
6923 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
6926 else if (TARGET_EMBEDDED_DATA)
6928 /* Don't put constants into the small data section: we want them
6929 to be in ROM rather than RAM. */
6930 if (TREE_CODE (decl) != VAR_DECL)
6933 if (TREE_READONLY (decl)
6934 && !TREE_SIDE_EFFECTS (decl)
6935 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
6939 /* Enforce -mlocal-sdata. */
6940 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
6943 /* Enforce -mextern-sdata. */
6944 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
6946 if (DECL_EXTERNAL (decl))
6948 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
6952 /* We have traditionally not treated zero-sized objects as small data,
6953 so this is now effectively part of the ABI. */
6954 size = int_size_in_bytes (TREE_TYPE (decl));
6955 return size > 0 && size <= mips_small_data_threshold;
6958 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
6959 anchors for small data: the GP register acts as an anchor in that
6960 case. We also don't want to use them for PC-relative accesses,
6961 where the PC acts as an anchor. */
6964 mips_use_anchors_for_symbol_p (const_rtx symbol)
6966 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
6968 case SYMBOL_PC_RELATIVE:
6969 case SYMBOL_GP_RELATIVE:
6973 return default_use_anchors_for_symbol_p (symbol);
6977 /* The MIPS debug format wants all automatic variables and arguments
6978 to be in terms of the virtual frame pointer (stack pointer before
6979 any adjustment in the function), while the MIPS 3.0 linker wants
6980 the frame pointer to be the stack pointer after the initial
6981 adjustment. So, we do the adjustment here. The arg pointer (which
6982 is eliminated) points to the virtual frame pointer, while the frame
6983 pointer (which may be eliminated) points to the stack pointer after
6984 the initial adjustments. */
6987 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
6989 rtx offset2 = const0_rtx;
6990 rtx reg = eliminate_constant_term (addr, &offset2);
6993 offset = INTVAL (offset2);
6995 if (reg == stack_pointer_rtx
6996 || reg == frame_pointer_rtx
6997 || reg == hard_frame_pointer_rtx)
6999 offset -= cfun->machine->frame.total_size;
7000 if (reg == hard_frame_pointer_rtx)
7001 offset += cfun->machine->frame.hard_frame_pointer_offset;
7004 /* sdbout_parms does not want this to crash for unrecognized cases. */
7006 else if (reg != arg_pointer_rtx)
7007 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7014 /* Implement ASM_OUTPUT_EXTERNAL. */
7017 mips_output_external (FILE *file, tree decl, const char *name)
7019 default_elf_asm_output_external (file, decl, name);
7021 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7022 set in order to avoid putting out names that are never really
7024 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7026 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7028 /* When using assembler macros, emit .extern directives for
7029 all small-data externs so that the assembler knows how
7032 In most cases it would be safe (though pointless) to emit
7033 .externs for other symbols too. One exception is when an
7034 object is within the -G limit but declared by the user to
7035 be in a section other than .sbss or .sdata. */
7036 fputs ("\t.extern\t", file);
7037 assemble_name (file, name);
7038 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7039 int_size_in_bytes (TREE_TYPE (decl)));
7041 else if (TARGET_IRIX
7042 && mips_abi == ABI_32
7043 && TREE_CODE (decl) == FUNCTION_DECL)
7045 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
7046 `.global name .text' directive for every used but
7047 undefined function. If we don't, the linker may perform
7048 an optimization (skipping over the insns that set $gp)
7049 when it is unsafe. */
7050 fputs ("\t.globl ", file);
7051 assemble_name (file, name);
7052 fputs (" .text\n", file);
7057 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7060 mips_output_filename (FILE *stream, const char *name)
7062 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7064 if (write_symbols == DWARF2_DEBUG)
7066 else if (mips_output_filename_first_time)
7068 mips_output_filename_first_time = 0;
7069 num_source_filenames += 1;
7070 current_function_file = name;
7071 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7072 output_quoted_string (stream, name);
7073 putc ('\n', stream);
7075 /* If we are emitting stabs, let dbxout.c handle this (except for
7076 the mips_output_filename_first_time case). */
7077 else if (write_symbols == DBX_DEBUG)
7079 else if (name != current_function_file
7080 && strcmp (name, current_function_file) != 0)
7082 num_source_filenames += 1;
7083 current_function_file = name;
7084 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7085 output_quoted_string (stream, name);
7086 putc ('\n', stream);
7090 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7092 static void ATTRIBUTE_UNUSED
7093 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7098 fputs ("\t.dtprelword\t", file);
7102 fputs ("\t.dtpreldword\t", file);
7108 output_addr_const (file, x);
7109 fputs ("+0x8000", file);
7112 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7115 mips_dwarf_register_span (rtx reg)
7118 enum machine_mode mode;
7120 /* By default, GCC maps increasing register numbers to increasing
7121 memory locations, but paired FPRs are always little-endian,
7122 regardless of the prevailing endianness. */
7123 mode = GET_MODE (reg);
7124 if (FP_REG_P (REGNO (reg))
7125 && TARGET_BIG_ENDIAN
7126 && MAX_FPRS_PER_FMT > 1
7127 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7129 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7130 high = mips_subword (reg, true);
7131 low = mips_subword (reg, false);
7132 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7138 /* Implement ASM_OUTPUT_ASCII. */
7141 mips_output_ascii (FILE *stream, const char *string, size_t len)
7147 fprintf (stream, "\t.ascii\t\"");
7148 for (i = 0; i < len; i++)
7152 c = (unsigned char) string[i];
7155 if (c == '\\' || c == '\"')
7157 putc ('\\', stream);
7165 fprintf (stream, "\\%03o", c);
7169 if (cur_pos > 72 && i+1 < len)
7172 fprintf (stream, "\"\n\t.ascii\t\"");
7175 fprintf (stream, "\"\n");
7178 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7179 macros, mark the symbol as written so that mips_asm_output_external
7180 won't emit an .extern for it. STREAM is the output file, NAME is the
7181 name of the symbol, INIT_STRING is the string that should be written
7182 before the symbol and FINAL_STRING is the string that should be
7183 written after it. FINAL_STRING is a printf format that consumes the
7184 remaining arguments. */
7187 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7188 const char *final_string, ...)
7192 fputs (init_string, stream);
7193 assemble_name (stream, name);
7194 va_start (ap, final_string);
7195 vfprintf (stream, final_string, ap);
7198 if (!TARGET_EXPLICIT_RELOCS)
7200 tree name_tree = get_identifier (name);
7201 TREE_ASM_WRITTEN (name_tree) = 1;
7205 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7206 NAME is the name of the object and ALIGN is the required alignment
7207 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7208 alignment argument. */
7211 mips_declare_common_object (FILE *stream, const char *name,
7212 const char *init_string,
7213 unsigned HOST_WIDE_INT size,
7214 unsigned int align, bool takes_alignment_p)
7216 if (!takes_alignment_p)
7218 size += (align / BITS_PER_UNIT) - 1;
7219 size -= size % (align / BITS_PER_UNIT);
7220 mips_declare_object (stream, name, init_string,
7221 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
7224 mips_declare_object (stream, name, init_string,
7225 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
7226 size, align / BITS_PER_UNIT);
7229 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7230 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7233 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
7234 unsigned HOST_WIDE_INT size,
7237 /* If the target wants uninitialized const declarations in
7238 .rdata then don't put them in .comm. */
7239 if (TARGET_EMBEDDED_DATA
7240 && TARGET_UNINIT_CONST_IN_RODATA
7241 && TREE_CODE (decl) == VAR_DECL
7242 && TREE_READONLY (decl)
7243 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
7245 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
7246 targetm.asm_out.globalize_label (stream, name);
7248 switch_to_section (readonly_data_section);
7249 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
7250 mips_declare_object (stream, name, "",
7251 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
7255 mips_declare_common_object (stream, name, "\n\t.comm\t",
7259 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7260 extern int size_directive_output;
7262 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7263 definitions except that it uses mips_declare_object to emit the label. */
7266 mips_declare_object_name (FILE *stream, const char *name,
7267 tree decl ATTRIBUTE_UNUSED)
7269 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7270 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7273 size_directive_output = 0;
7274 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
7278 size_directive_output = 1;
7279 size = int_size_in_bytes (TREE_TYPE (decl));
7280 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7283 mips_declare_object (stream, name, "", ":\n");
7286 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7289 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
7293 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
7294 if (!flag_inhibit_size_directive
7295 && DECL_SIZE (decl) != 0
7298 && DECL_INITIAL (decl) == error_mark_node
7299 && !size_directive_output)
7303 size_directive_output = 1;
7304 size = int_size_in_bytes (TREE_TYPE (decl));
7305 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7310 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7311 with the current ABI. */
7314 mips_mdebug_abi_name (void)
7327 return TARGET_64BIT ? "eabi64" : "eabi32";
7333 /* Implement TARGET_ASM_FILE_START. */
7336 mips_file_start (void)
7338 default_file_start ();
7340 /* Generate a special section to describe the ABI switches used to
7341 produce the resultant binary. This is unnecessary on IRIX and
7342 causes unwanted warnings from the native linker. */
7345 /* Record the ABI itself. Modern versions of binutils encode
7346 this information in the ELF header flags, but GDB needs the
7347 information in order to correctly debug binaries produced by
7348 older binutils. See the function mips_gdbarch_init in
7350 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
7351 mips_mdebug_abi_name ());
7353 /* There is no ELF header flag to distinguish long32 forms of the
7354 EABI from long64 forms. Emit a special section to help tools
7355 such as GDB. Do the same for o64, which is sometimes used with
7357 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
7358 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
7359 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
7361 #ifdef HAVE_AS_GNU_ATTRIBUTE
7362 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
7363 (TARGET_HARD_FLOAT_ABI
7364 ? (TARGET_DOUBLE_FLOAT
7365 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
7369 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
7370 if (TARGET_ABICALLS)
7371 fprintf (asm_out_file, "\t.abicalls\n");
7373 if (flag_verbose_asm)
7374 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7376 mips_small_data_threshold, mips_arch_info->name, mips_isa);
7379 /* Make the last instruction frame-related and note that it performs
7380 the operation described by FRAME_PATTERN. */
7383 mips_set_frame_expr (rtx frame_pattern)
7387 insn = get_last_insn ();
7388 RTX_FRAME_RELATED_P (insn) = 1;
7389 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7394 /* Return a frame-related rtx that stores REG at MEM.
7395 REG must be a single register. */
7398 mips_frame_set (rtx mem, rtx reg)
7402 /* If we're saving the return address register and the DWARF return
7403 address column differs from the hard register number, adjust the
7404 note reg to refer to the former. */
7405 if (REGNO (reg) == GP_REG_FIRST + 31
7406 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7407 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7409 set = gen_rtx_SET (VOIDmode, mem, reg);
7410 RTX_FRAME_RELATED_P (set) = 1;
7415 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7416 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7417 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7418 static const unsigned char mips16e_s2_s8_regs[] = {
7419 30, 23, 22, 21, 20, 19, 18
7421 static const unsigned char mips16e_a0_a3_regs[] = {
7425 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7426 ordered from the uppermost in memory to the lowest in memory. */
7427 static const unsigned char mips16e_save_restore_regs[] = {
7428 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7431 /* Return the index of the lowest X in the range [0, SIZE) for which
7432 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7435 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
7440 for (i = 0; i < size; i++)
7441 if (BITSET_P (mask, regs[i]))
7447 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7448 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7449 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7450 is true for all indexes (X, SIZE). */
7453 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
7454 unsigned int size, unsigned int *num_regs_ptr)
7458 i = mips16e_find_first_register (*mask_ptr, regs, size);
7459 for (i++; i < size; i++)
7460 if (!BITSET_P (*mask_ptr, regs[i]))
7463 *mask_ptr |= 1 << regs[i];
7467 /* Return a simplified form of X using the register values in REG_VALUES.
7468 REG_VALUES[R] is the last value assigned to hard register R, or null
7469 if R has not been modified.
7471 This function is rather limited, but is good enough for our purposes. */
7474 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7476 x = avoid_constant_pool_reference (x);
7480 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7481 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7482 x0, GET_MODE (XEXP (x, 0)));
7485 if (ARITHMETIC_P (x))
7487 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7488 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7489 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7493 && reg_values[REGNO (x)]
7494 && !rtx_unstable_p (reg_values[REGNO (x)]))
7495 return reg_values[REGNO (x)];
7500 /* Return true if (set DEST SRC) stores an argument register into its
7501 caller-allocated save slot, storing the number of that argument
7502 register in *REGNO_PTR if so. REG_VALUES is as for
7503 mips16e_collect_propagate_value. */
7506 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7507 unsigned int *regno_ptr)
7509 unsigned int argno, regno;
7510 HOST_WIDE_INT offset, required_offset;
7513 /* Check that this is a word-mode store. */
7514 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7517 /* Check that the register being saved is an unmodified argument
7519 regno = REGNO (src);
7520 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
7522 argno = regno - GP_ARG_FIRST;
7524 /* Check whether the address is an appropriate stack-pointer or
7525 frame-pointer access. */
7526 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7527 mips_split_plus (addr, &base, &offset);
7528 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7529 if (base == hard_frame_pointer_rtx)
7530 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
7531 else if (base != stack_pointer_rtx)
7533 if (offset != required_offset)
7540 /* A subroutine of mips_expand_prologue, called only when generating
7541 MIPS16e SAVE instructions. Search the start of the function for any
7542 instructions that save argument registers into their caller-allocated
7543 save slots. Delete such instructions and return a value N such that
7544 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7545 instructions redundant. */
7548 mips16e_collect_argument_saves (void)
7550 rtx reg_values[FIRST_PSEUDO_REGISTER];
7551 rtx insn, next, set, dest, src;
7552 unsigned int nargs, regno;
7554 push_topmost_sequence ();
7556 memset (reg_values, 0, sizeof (reg_values));
7557 for (insn = get_insns (); insn; insn = next)
7559 next = NEXT_INSN (insn);
7566 set = PATTERN (insn);
7567 if (GET_CODE (set) != SET)
7570 dest = SET_DEST (set);
7571 src = SET_SRC (set);
7572 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
7574 if (!BITSET_P (cfun->machine->frame.mask, regno))
7577 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
7580 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
7581 reg_values[REGNO (dest)]
7582 = mips16e_collect_propagate_value (src, reg_values);
7586 pop_topmost_sequence ();
7591 /* Return a move between register REGNO and memory location SP + OFFSET.
7592 Make the move a load if RESTORE_P, otherwise make it a frame-related
7596 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
7601 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
7602 reg = gen_rtx_REG (SImode, regno);
7604 ? gen_rtx_SET (VOIDmode, reg, mem)
7605 : mips_frame_set (mem, reg));
7608 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7609 The instruction must:
7611 - Allocate or deallocate SIZE bytes in total; SIZE is known
7614 - Save or restore as many registers in *MASK_PTR as possible.
7615 The instruction saves the first registers at the top of the
7616 allocated area, with the other registers below it.
7618 - Save NARGS argument registers above the allocated area.
7620 (NARGS is always zero if RESTORE_P.)
7622 The SAVE and RESTORE instructions cannot save and restore all general
7623 registers, so there may be some registers left over for the caller to
7624 handle. Destructively modify *MASK_PTR so that it contains the registers
7625 that still need to be saved or restored. The caller can save these
7626 registers in the memory immediately below *OFFSET_PTR, which is a
7627 byte offset from the bottom of the allocated stack area. */
7630 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
7631 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
7635 HOST_WIDE_INT offset, top_offset;
7636 unsigned int i, regno;
7639 gcc_assert (cfun->machine->frame.num_fp == 0);
7641 /* Calculate the number of elements in the PARALLEL. We need one element
7642 for the stack adjustment, one for each argument register save, and one
7643 for each additional register move. */
7645 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7646 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
7649 /* Create the final PARALLEL. */
7650 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
7653 /* Add the stack pointer adjustment. */
7654 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7655 plus_constant (stack_pointer_rtx,
7656 restore_p ? size : -size));
7657 RTX_FRAME_RELATED_P (set) = 1;
7658 XVECEXP (pattern, 0, n++) = set;
7660 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7661 top_offset = restore_p ? size : 0;
7663 /* Save the arguments. */
7664 for (i = 0; i < nargs; i++)
7666 offset = top_offset + i * UNITS_PER_WORD;
7667 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
7668 XVECEXP (pattern, 0, n++) = set;
7671 /* Then fill in the other register moves. */
7672 offset = top_offset;
7673 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7675 regno = mips16e_save_restore_regs[i];
7676 if (BITSET_P (*mask_ptr, regno))
7678 offset -= UNITS_PER_WORD;
7679 set = mips16e_save_restore_reg (restore_p, offset, regno);
7680 XVECEXP (pattern, 0, n++) = set;
7681 *mask_ptr &= ~(1 << regno);
7685 /* Tell the caller what offset it should use for the remaining registers. */
7686 *offset_ptr = size + (offset - top_offset);
7688 gcc_assert (n == XVECLEN (pattern, 0));
7693 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7694 pointer. Return true if PATTERN matches the kind of instruction
7695 generated by mips16e_build_save_restore. If INFO is nonnull,
7696 initialize it when returning true. */
7699 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
7700 struct mips16e_save_restore_info *info)
7702 unsigned int i, nargs, mask, extra;
7703 HOST_WIDE_INT top_offset, save_offset, offset;
7704 rtx set, reg, mem, base;
7707 if (!GENERATE_MIPS16E_SAVE_RESTORE)
7710 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7711 top_offset = adjust > 0 ? adjust : 0;
7713 /* Interpret all other members of the PARALLEL. */
7714 save_offset = top_offset - UNITS_PER_WORD;
7718 for (n = 1; n < XVECLEN (pattern, 0); n++)
7720 /* Check that we have a SET. */
7721 set = XVECEXP (pattern, 0, n);
7722 if (GET_CODE (set) != SET)
7725 /* Check that the SET is a load (if restoring) or a store
7727 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
7731 /* Check that the address is the sum of the stack pointer and a
7732 possibly-zero constant offset. */
7733 mips_split_plus (XEXP (mem, 0), &base, &offset);
7734 if (base != stack_pointer_rtx)
7737 /* Check that SET's other operand is a register. */
7738 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
7742 /* Check for argument saves. */
7743 if (offset == top_offset + nargs * UNITS_PER_WORD
7744 && REGNO (reg) == GP_ARG_FIRST + nargs)
7746 else if (offset == save_offset)
7748 while (mips16e_save_restore_regs[i++] != REGNO (reg))
7749 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
7752 mask |= 1 << REGNO (reg);
7753 save_offset -= UNITS_PER_WORD;
7759 /* Check that the restrictions on register ranges are met. */
7761 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
7762 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
7763 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
7764 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
7768 /* Make sure that the topmost argument register is not saved twice.
7769 The checks above ensure that the same is then true for the other
7770 argument registers. */
7771 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
7774 /* Pass back information, if requested. */
7777 info->nargs = nargs;
7779 info->size = (adjust > 0 ? adjust : -adjust);
7785 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7786 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7787 the null terminator. */
7790 mips16e_add_register_range (char *s, unsigned int min_reg,
7791 unsigned int max_reg)
7793 if (min_reg != max_reg)
7794 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
7796 s += sprintf (s, ",%s", reg_names[min_reg]);
7800 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7801 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7804 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
7806 static char buffer[300];
7808 struct mips16e_save_restore_info info;
7809 unsigned int i, end;
7812 /* Parse the pattern. */
7813 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
7816 /* Add the mnemonic. */
7817 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
7820 /* Save the arguments. */
7822 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
7823 reg_names[GP_ARG_FIRST + info.nargs - 1]);
7824 else if (info.nargs == 1)
7825 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
7827 /* Emit the amount of stack space to allocate or deallocate. */
7828 s += sprintf (s, "%d", (int) info.size);
7830 /* Save or restore $16. */
7831 if (BITSET_P (info.mask, 16))
7832 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
7834 /* Save or restore $17. */
7835 if (BITSET_P (info.mask, 17))
7836 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
7838 /* Save or restore registers in the range $s2...$s8, which
7839 mips16e_s2_s8_regs lists in decreasing order. Note that this
7840 is a software register range; the hardware registers are not
7841 numbered consecutively. */
7842 end = ARRAY_SIZE (mips16e_s2_s8_regs);
7843 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
7845 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
7846 mips16e_s2_s8_regs[i]);
7848 /* Save or restore registers in the range $a0...$a3. */
7849 end = ARRAY_SIZE (mips16e_a0_a3_regs);
7850 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
7852 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
7853 mips16e_a0_a3_regs[end - 1]);
7855 /* Save or restore $31. */
7856 if (BITSET_P (info.mask, 31))
7857 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
7862 /* Return true if the current function has an insn that implicitly
7866 mips_function_has_gp_insn (void)
7868 /* Don't bother rechecking if we found one last time. */
7869 if (!cfun->machine->has_gp_insn_p)
7873 push_topmost_sequence ();
7874 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7875 if (USEFUL_INSN_P (insn)
7876 && (get_attr_got (insn) != GOT_UNSET
7877 || mips_small_data_pattern_p (PATTERN (insn))))
7879 cfun->machine->has_gp_insn_p = true;
7882 pop_topmost_sequence ();
7884 return cfun->machine->has_gp_insn_p;
7887 /* Return true if the current function returns its value in a floating-point
7888 register in MIPS16 mode. */
7891 mips16_cfun_returns_in_fpr_p (void)
7893 tree return_type = DECL_RESULT (current_function_decl);
7894 return (TARGET_MIPS16
7895 && TARGET_HARD_FLOAT_ABI
7896 && !aggregate_value_p (return_type, current_function_decl)
7897 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
7900 /* Return the register that should be used as the global pointer
7901 within this function. Return 0 if the function doesn't need
7902 a global pointer. */
7905 mips_global_pointer (void)
7909 /* $gp is always available unless we're using a GOT. */
7910 if (!TARGET_USE_GOT)
7911 return GLOBAL_POINTER_REGNUM;
7913 /* We must always provide $gp when it is used implicitly. */
7914 if (!TARGET_EXPLICIT_RELOCS)
7915 return GLOBAL_POINTER_REGNUM;
7917 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
7920 return GLOBAL_POINTER_REGNUM;
7922 /* If the function has a nonlocal goto, $gp must hold the correct
7923 global pointer for the target function. */
7924 if (crtl->has_nonlocal_goto)
7925 return GLOBAL_POINTER_REGNUM;
7927 /* If the gp is never referenced, there's no need to initialize it.
7928 Note that reload can sometimes introduce constant pool references
7929 into a function that otherwise didn't need them. For example,
7930 suppose we have an instruction like:
7932 (set (reg:DF R1) (float:DF (reg:SI R2)))
7934 If R2 turns out to be constant such as 1, the instruction may have a
7935 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
7936 using this constant if R2 doesn't get allocated to a register.
7938 In cases like these, reload will have added the constant to the pool
7939 but no instruction will yet refer to it. */
7940 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
7941 && !crtl->uses_const_pool
7942 && !mips_function_has_gp_insn ())
7945 /* We need a global pointer, but perhaps we can use a call-clobbered
7946 register instead of $gp. */
7947 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
7948 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
7949 if (!df_regs_ever_live_p (regno)
7950 && call_really_used_regs[regno]
7951 && !fixed_regs[regno]
7952 && regno != PIC_FUNCTION_ADDR_REGNUM)
7955 return GLOBAL_POINTER_REGNUM;
7958 /* Return true if the current function must save register REGNO. */
7961 mips_save_reg_p (unsigned int regno)
7963 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
7964 if we have not chosen a call-clobbered substitute. */
7965 if (regno == GLOBAL_POINTER_REGNUM)
7966 return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
7968 /* Check call-saved registers. */
7969 if ((crtl->saves_all_registers || df_regs_ever_live_p (regno))
7970 && !call_really_used_regs[regno])
7973 /* Save both registers in an FPR pair if either one is used. This is
7974 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
7975 register to be used without the even register. */
7976 if (FP_REG_P (regno)
7977 && MAX_FPRS_PER_FMT == 2
7978 && df_regs_ever_live_p (regno + 1)
7979 && !call_really_used_regs[regno + 1])
7982 /* We need to save the old frame pointer before setting up a new one. */
7983 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7986 /* Check for registers that must be saved for FUNCTION_PROFILER. */
7987 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
7990 /* We need to save the incoming return address if it is ever clobbered
7991 within the function, if __builtin_eh_return is being used to set a
7992 different return address, or if a stub is being used to return a
7994 if (regno == GP_REG_FIRST + 31
7995 && (df_regs_ever_live_p (regno)
7996 || crtl->calls_eh_return
7997 || mips16_cfun_returns_in_fpr_p ()))
8003 /* Populate the current function's mips_frame_info structure.
8005 MIPS stack frames look like:
8007 +-------------------------------+
8009 | incoming stack arguments |
8011 +-------------------------------+
8013 | caller-allocated save area |
8014 A | for register arguments |
8016 +-------------------------------+ <-- incoming stack pointer
8018 | callee-allocated save area |
8019 B | for arguments that are |
8020 | split between registers and |
8023 +-------------------------------+ <-- arg_pointer_rtx
8025 C | callee-allocated save area |
8026 | for register varargs |
8028 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
8029 | | + UNITS_PER_HWFPVALUE
8032 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
8033 | | + UNITS_PER_WORD
8036 +-------------------------------+
8038 | local variables | | var_size
8040 +-------------------------------+
8042 | $gp save area | | cprestore_size
8044 P +-------------------------------+ <-- hard_frame_pointer_rtx for
8046 | outgoing stack arguments |
8048 +-------------------------------+
8050 | caller-allocated save area |
8051 | for register arguments |
8053 +-------------------------------+ <-- stack_pointer_rtx
8055 hard_frame_pointer_rtx for
8058 At least two of A, B and C will be empty.
8060 Dynamic stack allocations such as alloca insert data at point P.
8061 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
8062 hard_frame_pointer_rtx unchanged. */
8065 mips_compute_frame_info (void)
8067 struct mips_frame_info *frame;
8068 HOST_WIDE_INT offset, size;
8069 unsigned int regno, i;
8071 frame = &cfun->machine->frame;
8072 memset (frame, 0, sizeof (*frame));
8073 size = get_frame_size ();
8075 cfun->machine->global_pointer = mips_global_pointer ();
8077 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
8078 area and the $gp save slot. This area isn't needed in leaf functions,
8079 but if the target-independent frame size is nonzero, we're committed
8080 to allocating it anyway. */
8081 if (size == 0 && current_function_is_leaf)
8083 /* The MIPS 3.0 linker does not like functions that dynamically
8084 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
8085 looks like we are trying to create a second frame pointer to the
8086 function, so allocate some stack space to make it happy. */
8087 if (cfun->calls_alloca)
8088 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
8090 frame->args_size = 0;
8091 frame->cprestore_size = 0;
8095 frame->args_size = crtl->outgoing_args_size;
8096 frame->cprestore_size = STARTING_FRAME_OFFSET - frame->args_size;
8098 offset = frame->args_size + frame->cprestore_size;
8100 /* Move above the local variables. */
8101 frame->var_size = MIPS_STACK_ALIGN (size);
8102 offset += frame->var_size;
8104 /* Find out which GPRs we need to save. */
8105 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8106 if (mips_save_reg_p (regno))
8109 frame->mask |= 1 << (regno - GP_REG_FIRST);
8112 /* If this function calls eh_return, we must also save and restore the
8113 EH data registers. */
8114 if (crtl->calls_eh_return)
8115 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
8118 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
8121 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
8122 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
8123 save all later registers too. */
8124 if (GENERATE_MIPS16E_SAVE_RESTORE)
8126 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
8127 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
8128 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
8129 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
8132 /* Move above the GPR save area. */
8133 if (frame->num_gp > 0)
8135 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
8136 frame->gp_sp_offset = offset - UNITS_PER_WORD;
8139 /* Find out which FPRs we need to save. This loop must iterate over
8140 the same space as its companion in mips_for_each_saved_reg. */
8141 if (TARGET_HARD_FLOAT)
8142 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
8143 if (mips_save_reg_p (regno))
8145 frame->num_fp += MAX_FPRS_PER_FMT;
8146 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
8149 /* Move above the FPR save area. */
8150 if (frame->num_fp > 0)
8152 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
8153 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
8156 /* Move above the callee-allocated varargs save area. */
8157 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
8158 frame->arg_pointer_offset = offset;
8160 /* Move above the callee-allocated area for pretend stack arguments. */
8161 offset += crtl->args.pretend_args_size;
8162 frame->total_size = offset;
8164 /* Work out the offsets of the save areas from the top of the frame. */
8165 if (frame->gp_sp_offset > 0)
8166 frame->gp_save_offset = frame->gp_sp_offset - offset;
8167 if (frame->fp_sp_offset > 0)
8168 frame->fp_save_offset = frame->fp_sp_offset - offset;
8170 /* MIPS16 code offsets the frame pointer by the size of the outgoing
8171 arguments. This tends to increase the chances of using unextended
8172 instructions for local variables and incoming arguments. */
8174 frame->hard_frame_pointer_offset = frame->args_size;
8177 /* Return the style of GP load sequence that is being used for the
8178 current function. */
8180 enum mips_loadgp_style
8181 mips_current_loadgp_style (void)
8183 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
8189 if (TARGET_ABSOLUTE_ABICALLS)
8190 return LOADGP_ABSOLUTE;
8192 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
8195 /* Implement FRAME_POINTER_REQUIRED. */
8198 mips_frame_pointer_required (void)
8200 /* If the function contains dynamic stack allocations, we need to
8201 use the frame pointer to access the static parts of the frame. */
8202 if (cfun->calls_alloca)
8205 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8206 reload may be unable to compute the address of a local variable,
8207 since there is no way to add a large constant to the stack pointer
8208 without using a second temporary register. */
8211 mips_compute_frame_info ();
8212 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
8219 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
8220 or argument pointer. TO is either the stack pointer or hard frame
8224 mips_initial_elimination_offset (int from, int to)
8226 HOST_WIDE_INT offset;
8228 mips_compute_frame_info ();
8230 /* Set OFFSET to the offset from the soft frame pointer, which is also
8231 the offset from the end-of-prologue stack pointer. */
8234 case FRAME_POINTER_REGNUM:
8238 case ARG_POINTER_REGNUM:
8239 offset = cfun->machine->frame.arg_pointer_offset;
8246 if (to == HARD_FRAME_POINTER_REGNUM)
8247 offset -= cfun->machine->frame.hard_frame_pointer_offset;
8252 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
8255 mips_extra_live_on_entry (bitmap regs)
8259 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
8260 the global pointer. */
8261 if (!TARGET_ABSOLUTE_ABICALLS)
8262 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
8264 /* See the comment above load_call<mode> for details. */
8265 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
8269 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
8273 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
8278 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
8281 /* Emit code to change the current function's return address to
8282 ADDRESS. SCRATCH is available as a scratch register, if needed.
8283 ADDRESS and SCRATCH are both word-mode GPRs. */
8286 mips_set_return_address (rtx address, rtx scratch)
8290 gcc_assert (BITSET_P (cfun->machine->frame.mask, 31));
8291 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
8292 cfun->machine->frame.gp_sp_offset);
8293 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
8296 /* Restore $gp from its save slot. Valid only when using o32 or
8300 mips_restore_gp (void)
8304 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
8306 base = frame_pointer_needed ? hard_frame_pointer_rtx : stack_pointer_rtx;
8307 address = mips_add_offset (pic_offset_table_rtx, base,
8308 crtl->outgoing_args_size);
8309 mips_emit_move (pic_offset_table_rtx, gen_frame_mem (Pmode, address));
8310 if (!TARGET_EXPLICIT_RELOCS)
8311 emit_insn (gen_blockage ());
8314 /* A function to save or store a register. The first argument is the
8315 register and the second is the stack slot. */
8316 typedef void (*mips_save_restore_fn) (rtx, rtx);
8318 /* Use FN to save or restore register REGNO. MODE is the register's
8319 mode and OFFSET is the offset of its save slot from the current
8323 mips_save_restore_reg (enum machine_mode mode, int regno,
8324 HOST_WIDE_INT offset, mips_save_restore_fn fn)
8328 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
8329 fn (gen_rtx_REG (mode, regno), mem);
8332 /* Call FN for each register that is saved by the current function.
8333 SP_OFFSET is the offset of the current stack pointer from the start
8337 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
8339 enum machine_mode fpr_mode;
8340 HOST_WIDE_INT offset;
8343 /* Save registers starting from high to low. The debuggers prefer at least
8344 the return register be stored at func+4, and also it allows us not to
8345 need a nop in the epilogue if at least one register is reloaded in
8346 addition to return address. */
8347 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
8348 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
8349 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
8351 mips_save_restore_reg (word_mode, regno, offset, fn);
8352 offset -= UNITS_PER_WORD;
8355 /* This loop must iterate over the same space as its companion in
8356 mips_compute_frame_info. */
8357 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
8358 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
8359 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
8360 regno >= FP_REG_FIRST;
8361 regno -= MAX_FPRS_PER_FMT)
8362 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
8364 mips_save_restore_reg (fpr_mode, regno, offset, fn);
8365 offset -= GET_MODE_SIZE (fpr_mode);
8369 /* If we're generating n32 or n64 abicalls, and the current function
8370 does not use $28 as its global pointer, emit a cplocal directive.
8371 Use pic_offset_table_rtx as the argument to the directive. */
8374 mips_output_cplocal (void)
8376 if (!TARGET_EXPLICIT_RELOCS
8377 && cfun->machine->global_pointer > 0
8378 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
8379 output_asm_insn (".cplocal %+", 0);
8382 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
8385 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8389 #ifdef SDB_DEBUGGING_INFO
8390 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
8391 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
8394 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
8395 floating-point arguments. */
8397 && TARGET_HARD_FLOAT_ABI
8398 && crtl->args.info.fp_code != 0)
8399 mips16_build_function_stub ();
8401 /* Get the function name the same way that toplev.c does before calling
8402 assemble_start_function. This is needed so that the name used here
8403 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8404 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8405 mips_start_function_definition (fnname, TARGET_MIPS16);
8407 /* Stop mips_file_end from treating this function as external. */
8408 if (TARGET_IRIX && mips_abi == ABI_32)
8409 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
8411 /* Output MIPS-specific frame information. */
8412 if (!flag_inhibit_size_directive)
8414 const struct mips_frame_info *frame;
8416 frame = &cfun->machine->frame;
8418 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
8420 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
8421 "# vars= " HOST_WIDE_INT_PRINT_DEC
8423 ", args= " HOST_WIDE_INT_PRINT_DEC
8424 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
8425 reg_names[frame_pointer_needed
8426 ? HARD_FRAME_POINTER_REGNUM
8427 : STACK_POINTER_REGNUM],
8428 (frame_pointer_needed
8429 ? frame->total_size - frame->hard_frame_pointer_offset
8430 : frame->total_size),
8431 reg_names[GP_REG_FIRST + 31],
8433 frame->num_gp, frame->num_fp,
8435 frame->cprestore_size);
8437 /* .mask MASK, OFFSET. */
8438 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8439 frame->mask, frame->gp_save_offset);
8441 /* .fmask MASK, OFFSET. */
8442 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8443 frame->fmask, frame->fp_save_offset);
8446 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
8447 Also emit the ".set noreorder; .set nomacro" sequence for functions
8449 if (mips_current_loadgp_style () == LOADGP_OLDABI)
8451 /* .cpload must be in a .set noreorder but not a .set nomacro block. */
8452 if (!cfun->machine->all_noreorder_p)
8453 output_asm_insn ("%(.cpload\t%^%)", 0);
8455 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
8457 else if (cfun->machine->all_noreorder_p)
8458 output_asm_insn ("%(%<", 0);
8460 /* Tell the assembler which register we're using as the global
8461 pointer. This is needed for thunks, since they can use either
8462 explicit relocs or assembler macros. */
8463 mips_output_cplocal ();
8466 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
8469 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8470 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8474 /* Reinstate the normal $gp. */
8475 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
8476 mips_output_cplocal ();
8478 if (cfun->machine->all_noreorder_p)
8480 /* Avoid using %>%) since it adds excess whitespace. */
8481 output_asm_insn (".set\tmacro", 0);
8482 output_asm_insn (".set\treorder", 0);
8483 set_noreorder = set_nomacro = 0;
8486 /* Get the function name the same way that toplev.c does before calling
8487 assemble_start_function. This is needed so that the name used here
8488 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8489 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8490 mips_end_function_definition (fnname);
8493 /* Save register REG to MEM. Make the instruction frame-related. */
8496 mips_save_reg (rtx reg, rtx mem)
8498 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
8502 if (mips_split_64bit_move_p (mem, reg))
8503 mips_split_doubleword_move (mem, reg);
8505 mips_emit_move (mem, reg);
8507 x1 = mips_frame_set (mips_subword (mem, false),
8508 mips_subword (reg, false));
8509 x2 = mips_frame_set (mips_subword (mem, true),
8510 mips_subword (reg, true));
8511 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
8516 && REGNO (reg) != GP_REG_FIRST + 31
8517 && !M16_REG_P (REGNO (reg)))
8519 /* Save a non-MIPS16 register by moving it through a temporary.
8520 We don't need to do this for $31 since there's a special
8521 instruction for it. */
8522 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
8523 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
8526 mips_emit_move (mem, reg);
8528 mips_set_frame_expr (mips_frame_set (mem, reg));
8532 /* The __gnu_local_gp symbol. */
8534 static GTY(()) rtx mips_gnu_local_gp;
8536 /* If we're generating n32 or n64 abicalls, emit instructions
8537 to set up the global pointer. */
8540 mips_emit_loadgp (void)
8542 rtx addr, offset, incoming_address, base, index, pic_reg;
8544 pic_reg = pic_offset_table_rtx;
8545 switch (mips_current_loadgp_style ())
8547 case LOADGP_ABSOLUTE:
8548 if (mips_gnu_local_gp == NULL)
8550 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
8551 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
8553 emit_insn (Pmode == SImode
8554 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
8555 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
8559 addr = XEXP (DECL_RTL (current_function_decl), 0);
8560 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
8561 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
8562 emit_insn (Pmode == SImode
8563 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
8564 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
8568 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
8569 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
8570 emit_insn (Pmode == SImode
8571 ? gen_loadgp_rtp_si (pic_reg, base, index)
8572 : gen_loadgp_rtp_di (pic_reg, base, index));
8578 /* Emit a blockage if there are implicit uses of the GP register.
8579 This includes profiled functions, because FUNCTION_PROFILE uses
8581 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
8582 emit_insn (gen_loadgp_blockage ());
8585 /* Expand the "prologue" pattern. */
8588 mips_expand_prologue (void)
8590 const struct mips_frame_info *frame;
8595 if (cfun->machine->global_pointer > 0)
8596 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
8598 frame = &cfun->machine->frame;
8599 size = frame->total_size;
8601 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
8602 bytes beforehand; this is enough to cover the register save area
8603 without going out of range. */
8604 if ((frame->mask | frame->fmask) != 0)
8606 HOST_WIDE_INT step1;
8608 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
8609 if (GENERATE_MIPS16E_SAVE_RESTORE)
8611 HOST_WIDE_INT offset;
8612 unsigned int mask, regno;
8614 /* Try to merge argument stores into the save instruction. */
8615 nargs = mips16e_collect_argument_saves ();
8617 /* Build the save instruction. */
8619 insn = mips16e_build_save_restore (false, &mask, &offset,
8621 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8624 /* Check if we need to save other registers. */
8625 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8626 if (BITSET_P (mask, regno - GP_REG_FIRST))
8628 offset -= UNITS_PER_WORD;
8629 mips_save_restore_reg (word_mode, regno,
8630 offset, mips_save_reg);
8635 insn = gen_add3_insn (stack_pointer_rtx,
8638 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8640 mips_for_each_saved_reg (size, mips_save_reg);
8644 /* Allocate the rest of the frame. */
8647 if (SMALL_OPERAND (-size))
8648 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
8650 GEN_INT (-size)))) = 1;
8653 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
8656 /* There are no instructions to add or subtract registers
8657 from the stack pointer, so use the frame pointer as a
8658 temporary. We should always be using a frame pointer
8659 in this case anyway. */
8660 gcc_assert (frame_pointer_needed);
8661 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8662 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
8663 hard_frame_pointer_rtx,
8664 MIPS_PROLOGUE_TEMP (Pmode)));
8665 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
8668 emit_insn (gen_sub3_insn (stack_pointer_rtx,
8670 MIPS_PROLOGUE_TEMP (Pmode)));
8672 /* Describe the combined effect of the previous instructions. */
8674 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8675 plus_constant (stack_pointer_rtx, -size)));
8679 /* Set up the frame pointer, if we're using one. */
8680 if (frame_pointer_needed)
8682 HOST_WIDE_INT offset;
8684 offset = frame->hard_frame_pointer_offset;
8687 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8688 RTX_FRAME_RELATED_P (insn) = 1;
8690 else if (SMALL_OPERAND (offset))
8692 insn = gen_add3_insn (hard_frame_pointer_rtx,
8693 stack_pointer_rtx, GEN_INT (offset));
8694 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8698 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
8699 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8700 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
8701 hard_frame_pointer_rtx,
8702 MIPS_PROLOGUE_TEMP (Pmode)));
8704 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
8705 plus_constant (stack_pointer_rtx, offset)));
8709 mips_emit_loadgp ();
8711 /* Initialize the $gp save slot. */
8712 if (frame->cprestore_size > 0)
8713 emit_insn (gen_cprestore (GEN_INT (crtl->outgoing_args_size)));
8715 /* If we are profiling, make sure no instructions are scheduled before
8716 the call to mcount. */
8718 emit_insn (gen_blockage ());
8721 /* Emit instructions to restore register REG from slot MEM. */
8724 mips_restore_reg (rtx reg, rtx mem)
8726 /* There's no MIPS16 instruction to load $31 directly. Load into
8727 $7 instead and adjust the return insn appropriately. */
8728 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
8729 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
8731 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
8733 /* Can't restore directly; move through a temporary. */
8734 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
8735 mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
8738 mips_emit_move (reg, mem);
8741 /* Emit any instructions needed before a return. */
8744 mips_expand_before_return (void)
8746 /* When using a call-clobbered gp, we start out with unified call
8747 insns that include instructions to restore the gp. We then split
8748 these unified calls after reload. These split calls explicitly
8749 clobber gp, so there is no need to define
8750 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
8752 For consistency, we should also insert an explicit clobber of $28
8753 before return insns, so that the post-reload optimizers know that
8754 the register is not live on exit. */
8755 if (TARGET_CALL_CLOBBERED_GP)
8756 emit_clobber (pic_offset_table_rtx);
8759 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
8763 mips_expand_epilogue (bool sibcall_p)
8765 const struct mips_frame_info *frame;
8766 HOST_WIDE_INT step1, step2;
8769 if (!sibcall_p && mips_can_use_return_insn ())
8771 emit_jump_insn (gen_return ());
8775 /* In MIPS16 mode, if the return value should go into a floating-point
8776 register, we need to call a helper routine to copy it over. */
8777 if (mips16_cfun_returns_in_fpr_p ())
8778 mips16_copy_fpr_return_value ();
8780 /* Split the frame into two. STEP1 is the amount of stack we should
8781 deallocate before restoring the registers. STEP2 is the amount we
8782 should deallocate afterwards.
8784 Start off by assuming that no registers need to be restored. */
8785 frame = &cfun->machine->frame;
8786 step1 = frame->total_size;
8789 /* Work out which register holds the frame address. */
8790 if (!frame_pointer_needed)
8791 base = stack_pointer_rtx;
8794 base = hard_frame_pointer_rtx;
8795 step1 -= frame->hard_frame_pointer_offset;
8798 /* If we need to restore registers, deallocate as much stack as
8799 possible in the second step without going out of range. */
8800 if ((frame->mask | frame->fmask) != 0)
8802 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
8806 /* Set TARGET to BASE + STEP1. */
8812 /* Get an rtx for STEP1 that we can add to BASE. */
8813 adjust = GEN_INT (step1);
8814 if (!SMALL_OPERAND (step1))
8816 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
8817 adjust = MIPS_EPILOGUE_TEMP (Pmode);
8820 /* Normal mode code can copy the result straight into $sp. */
8822 target = stack_pointer_rtx;
8824 emit_insn (gen_add3_insn (target, base, adjust));
8827 /* Copy TARGET into the stack pointer. */
8828 if (target != stack_pointer_rtx)
8829 mips_emit_move (stack_pointer_rtx, target);
8831 /* If we're using addressing macros, $gp is implicitly used by all
8832 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
8834 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
8835 emit_insn (gen_blockage ());
8837 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
8839 unsigned int regno, mask;
8840 HOST_WIDE_INT offset;
8843 /* Generate the restore instruction. */
8845 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
8847 /* Restore any other registers manually. */
8848 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8849 if (BITSET_P (mask, regno - GP_REG_FIRST))
8851 offset -= UNITS_PER_WORD;
8852 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
8855 /* Restore the remaining registers and deallocate the final bit
8857 emit_insn (restore);
8861 /* Restore the registers. */
8862 mips_for_each_saved_reg (frame->total_size - step2, mips_restore_reg);
8864 /* Deallocate the final bit of the frame. */
8866 emit_insn (gen_add3_insn (stack_pointer_rtx,
8871 /* Add in the __builtin_eh_return stack adjustment. We need to
8872 use a temporary in MIPS16 code. */
8873 if (crtl->calls_eh_return)
8877 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
8878 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
8879 MIPS_EPILOGUE_TEMP (Pmode),
8880 EH_RETURN_STACKADJ_RTX));
8881 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
8884 emit_insn (gen_add3_insn (stack_pointer_rtx,
8886 EH_RETURN_STACKADJ_RTX));
8893 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
8894 path will restore the return address into $7 rather than $31. */
8896 && !GENERATE_MIPS16E_SAVE_RESTORE
8897 && BITSET_P (frame->mask, 31))
8898 regno = GP_REG_FIRST + 7;
8900 regno = GP_REG_FIRST + 31;
8901 mips_expand_before_return ();
8902 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
8906 /* Return nonzero if this function is known to have a null epilogue.
8907 This allows the optimizer to omit jumps to jumps if no stack
8911 mips_can_use_return_insn (void)
8913 if (!reload_completed)
8919 /* In MIPS16 mode, a function that returns a floating-point value
8920 needs to arrange to copy the return value into the floating-point
8922 if (mips16_cfun_returns_in_fpr_p ())
8925 return cfun->machine->frame.total_size == 0;
8928 /* Return true if register REGNO can store a value of mode MODE.
8929 The result of this function is cached in mips_hard_regno_mode_ok. */
8932 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
8935 enum mode_class mclass;
8937 if (mode == CCV2mode)
8940 && (regno - ST_REG_FIRST) % 2 == 0);
8942 if (mode == CCV4mode)
8945 && (regno - ST_REG_FIRST) % 4 == 0);
8950 return regno == FPSW_REGNUM;
8952 return (ST_REG_P (regno)
8954 || FP_REG_P (regno));
8957 size = GET_MODE_SIZE (mode);
8958 mclass = GET_MODE_CLASS (mode);
8960 if (GP_REG_P (regno))
8961 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
8963 if (FP_REG_P (regno)
8964 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
8965 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
8967 /* Allow TFmode for CCmode reloads. */
8968 if (mode == TFmode && ISA_HAS_8CC)
8971 /* Allow 64-bit vector modes for Loongson-2E/2F. */
8972 if (TARGET_LOONGSON_VECTORS
8973 && (mode == V2SImode
8979 if (mclass == MODE_FLOAT
8980 || mclass == MODE_COMPLEX_FLOAT
8981 || mclass == MODE_VECTOR_FLOAT)
8982 return size <= UNITS_PER_FPVALUE;
8984 /* Allow integer modes that fit into a single register. We need
8985 to put integers into FPRs when using instructions like CVT
8986 and TRUNC. There's no point allowing sizes smaller than a word,
8987 because the FPU has no appropriate load/store instructions. */
8988 if (mclass == MODE_INT)
8989 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
8992 if (ACC_REG_P (regno)
8993 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
8995 if (MD_REG_P (regno))
8997 /* After a multiplication or division, clobbering HI makes
8998 the value of LO unpredictable, and vice versa. This means
8999 that, for all interesting cases, HI and LO are effectively
9002 We model this by requiring that any value that uses HI
9004 if (size <= UNITS_PER_WORD * 2)
9005 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
9009 /* DSP accumulators do not have the same restrictions as
9010 HI and LO, so we can treat them as normal doubleword
9012 if (size <= UNITS_PER_WORD)
9015 if (size <= UNITS_PER_WORD * 2
9016 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
9021 if (ALL_COP_REG_P (regno))
9022 return mclass == MODE_INT && size <= UNITS_PER_WORD;
9024 if (regno == GOT_VERSION_REGNUM)
9025 return mode == SImode;
9030 /* Implement HARD_REGNO_NREGS. */
9033 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9035 if (ST_REG_P (regno))
9036 /* The size of FP status registers is always 4, because they only hold
9037 CCmode values, and CCmode is always considered to be 4 bytes wide. */
9038 return (GET_MODE_SIZE (mode) + 3) / 4;
9040 if (FP_REG_P (regno))
9041 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
9043 /* All other registers are word-sized. */
9044 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
9047 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
9048 in mips_hard_regno_nregs. */
9051 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
9057 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
9058 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
9060 size = MIN (size, 4);
9061 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
9063 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
9065 size = MIN (size, UNITS_PER_FPREG);
9066 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
9068 if (!hard_reg_set_empty_p (left))
9069 size = MIN (size, UNITS_PER_WORD);
9070 return (GET_MODE_SIZE (mode) + size - 1) / size;
9073 /* Implement CANNOT_CHANGE_MODE_CLASS. */
9076 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
9077 enum machine_mode to ATTRIBUTE_UNUSED,
9078 enum reg_class rclass)
9080 /* There are several problems with changing the modes of values
9081 in floating-point registers:
9083 - When a multi-word value is stored in paired floating-point
9084 registers, the first register always holds the low word.
9085 We therefore can't allow FPRs to change between single-word
9086 and multi-word modes on big-endian targets.
9088 - GCC assumes that each word of a multiword register can be accessed
9089 individually using SUBREGs. This is not true for floating-point
9090 registers if they are bigger than a word.
9092 - Loading a 32-bit value into a 64-bit floating-point register
9093 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
9094 We can't allow FPRs to change from SImode to to a wider mode on
9097 - If the FPU has already interpreted a value in one format, we must
9098 not ask it to treat the value as having a different format.
9100 We therefore disallow all mode changes involving FPRs. */
9101 return reg_classes_intersect_p (FP_REGS, rclass);
9104 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
9107 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
9112 return TARGET_HARD_FLOAT;
9115 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
9118 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
9125 /* Implement MODES_TIEABLE_P. */
9128 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
9130 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
9131 prefer to put one of them in FPRs. */
9132 return (mode1 == mode2
9133 || (!mips_mode_ok_for_mov_fmt_p (mode1)
9134 && !mips_mode_ok_for_mov_fmt_p (mode2)));
9137 /* Implement PREFERRED_RELOAD_CLASS. */
9140 mips_preferred_reload_class (rtx x, enum reg_class rclass)
9142 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
9145 if (reg_class_subset_p (FP_REGS, rclass)
9146 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
9149 if (reg_class_subset_p (GR_REGS, rclass))
9152 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
9158 /* Implement REGISTER_MOVE_COST. */
9161 mips_register_move_cost (enum machine_mode mode,
9162 enum reg_class to, enum reg_class from)
9166 /* ??? We cannot move general registers into HI and LO because
9167 MIPS16 has no MTHI and MTLO instructions. Make the cost of
9168 moves in the opposite direction just as high, which stops the
9169 register allocators from using HI and LO for pseudos. */
9170 if (reg_class_subset_p (from, GENERAL_REGS)
9171 && reg_class_subset_p (to, GENERAL_REGS))
9173 if (reg_class_subset_p (from, M16_REGS)
9174 || reg_class_subset_p (to, M16_REGS))
9180 else if (reg_class_subset_p (from, GENERAL_REGS))
9182 if (reg_class_subset_p (to, GENERAL_REGS))
9184 if (reg_class_subset_p (to, FP_REGS))
9186 if (reg_class_subset_p (to, ALL_COP_AND_GR_REGS))
9188 if (reg_class_subset_p (to, ACC_REGS))
9191 else if (reg_class_subset_p (to, GENERAL_REGS))
9193 if (reg_class_subset_p (from, FP_REGS))
9195 if (reg_class_subset_p (from, ST_REGS))
9196 /* LUI followed by MOVF. */
9198 if (reg_class_subset_p (from, ALL_COP_AND_GR_REGS))
9200 if (reg_class_subset_p (from, ACC_REGS))
9203 else if (reg_class_subset_p (from, FP_REGS))
9205 if (reg_class_subset_p (to, FP_REGS)
9206 && mips_mode_ok_for_mov_fmt_p (mode))
9208 if (reg_class_subset_p (to, ST_REGS))
9209 /* An expensive sequence. */
9216 /* Return the register class required for a secondary register when
9217 copying between one of the registers in RCLASS and value X, which
9218 has mode MODE. X is the source of the move if IN_P, otherwise it
9219 is the destination. Return NO_REGS if no secondary register is
9223 mips_secondary_reload_class (enum reg_class rclass,
9224 enum machine_mode mode, rtx x, bool in_p)
9228 /* If X is a constant that cannot be loaded into $25, it must be loaded
9229 into some other GPR. No other register class allows a direct move. */
9230 if (mips_dangerous_for_la25_p (x))
9231 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
9233 regno = true_regnum (x);
9236 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
9237 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
9240 /* We can't really copy to HI or LO at all in MIPS16 mode. */
9241 if (in_p ? reg_classes_intersect_p (rclass, ACC_REGS) : ACC_REG_P (regno))
9247 /* Copying from accumulator registers to anywhere other than a general
9248 register requires a temporary general register. */
9249 if (reg_class_subset_p (rclass, ACC_REGS))
9250 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9251 if (ACC_REG_P (regno))
9252 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
9254 /* We can only copy a value to a condition code register from a
9255 floating-point register, and even then we require a scratch
9256 floating-point register. We can only copy a value out of a
9257 condition-code register into a general register. */
9258 if (reg_class_subset_p (rclass, ST_REGS))
9262 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9264 if (ST_REG_P (regno))
9268 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
9271 if (reg_class_subset_p (rclass, FP_REGS))
9274 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
9275 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
9276 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
9279 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
9280 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
9283 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
9284 /* We can force the constant to memory and use lwc1
9285 and ldc1. As above, we will use pairs of lwc1s if
9286 ldc1 is not supported. */
9289 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
9290 /* In this case we can use mov.fmt. */
9293 /* Otherwise, we need to reload through an integer register. */
9296 if (FP_REG_P (regno))
9297 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
9302 /* Implement TARGET_MODE_REP_EXTENDED. */
9305 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
9307 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
9308 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
9314 /* Implement TARGET_VALID_POINTER_MODE. */
9317 mips_valid_pointer_mode (enum machine_mode mode)
9319 return mode == SImode || (TARGET_64BIT && mode == DImode);
9322 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
9325 mips_vector_mode_supported_p (enum machine_mode mode)
9330 return TARGET_PAIRED_SINGLE_FLOAT;
9345 return TARGET_LOONGSON_VECTORS;
9352 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
9355 mips_scalar_mode_supported_p (enum machine_mode mode)
9357 if (ALL_FIXED_POINT_MODE_P (mode)
9358 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
9361 return default_scalar_mode_supported_p (mode);
9364 /* Implement TARGET_INIT_LIBFUNCS. */
9366 #include "config/gofast.h"
9369 mips_init_libfuncs (void)
9371 if (TARGET_FIX_VR4120)
9373 /* Register the special divsi3 and modsi3 functions needed to work
9374 around VR4120 division errata. */
9375 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9376 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9379 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
9381 /* Register the MIPS16 -mhard-float stubs. */
9382 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9383 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9384 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9385 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9387 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9388 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9389 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9390 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9391 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9392 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9393 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
9395 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9396 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9397 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
9399 if (TARGET_DOUBLE_FLOAT)
9401 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9402 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9403 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9404 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9406 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9407 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9408 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9409 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9410 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9411 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9412 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
9414 set_conv_libfunc (sext_optab, DFmode, SFmode,
9415 "__mips16_extendsfdf2");
9416 set_conv_libfunc (trunc_optab, SFmode, DFmode,
9417 "__mips16_truncdfsf2");
9418 set_conv_libfunc (sfix_optab, SImode, DFmode,
9419 "__mips16_fix_truncdfsi");
9420 set_conv_libfunc (sfloat_optab, DFmode, SImode,
9421 "__mips16_floatsidf");
9422 set_conv_libfunc (ufloat_optab, DFmode, SImode,
9423 "__mips16_floatunsidf");
9427 /* Register the gofast functions if selected using --enable-gofast. */
9428 gofast_maybe_init_libfuncs ();
9430 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
9431 on an external non-MIPS16 routine to implement __sync_synchronize. */
9433 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
9436 /* Return the length of INSN. LENGTH is the initial length computed by
9437 attributes in the machine-description file. */
9440 mips_adjust_insn_length (rtx insn, int length)
9442 /* A unconditional jump has an unfilled delay slot if it is not part
9443 of a sequence. A conditional jump normally has a delay slot, but
9444 does not on MIPS16. */
9445 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9448 /* See how many nops might be needed to avoid hardware hazards. */
9449 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9450 switch (get_attr_hazard (insn))
9464 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
9465 the .md file length attributes are 4-based for both modes.
9466 Adjust the MIPS16 ones here. */
9473 /* Return an asm sequence to start a noat block and load the address
9474 of a label into $1. */
9477 mips_output_load_label (void)
9479 if (TARGET_EXPLICIT_RELOCS)
9483 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9486 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9489 if (ISA_HAS_LOAD_DELAY)
9490 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9491 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9495 if (Pmode == DImode)
9496 return "%[dla\t%@,%0";
9498 return "%[la\t%@,%0";
9502 /* Return the assembly code for INSN, which has the operands given by
9503 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9504 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9505 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9506 version of BRANCH_IF_TRUE. */
9509 mips_output_conditional_branch (rtx insn, rtx *operands,
9510 const char *branch_if_true,
9511 const char *branch_if_false)
9513 unsigned int length;
9514 rtx taken, not_taken;
9516 length = get_attr_length (insn);
9519 /* Just a simple conditional branch. */
9520 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9521 return branch_if_true;
9524 /* Generate a reversed branch around a direct jump. This fallback does
9525 not use branch-likely instructions. */
9526 mips_branch_likely = false;
9527 not_taken = gen_label_rtx ();
9528 taken = operands[1];
9530 /* Generate the reversed branch to NOT_TAKEN. */
9531 operands[1] = not_taken;
9532 output_asm_insn (branch_if_false, operands);
9534 /* If INSN has a delay slot, we must provide delay slots for both the
9535 branch to NOT_TAKEN and the conditional jump. We must also ensure
9536 that INSN's delay slot is executed in the appropriate cases. */
9539 /* This first delay slot will always be executed, so use INSN's
9540 delay slot if is not annulled. */
9541 if (!INSN_ANNULLED_BRANCH_P (insn))
9543 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9544 asm_out_file, optimize, 1, NULL);
9545 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9548 output_asm_insn ("nop", 0);
9549 fprintf (asm_out_file, "\n");
9552 /* Output the unconditional branch to TAKEN. */
9554 output_asm_insn ("j\t%0%/", &taken);
9557 output_asm_insn (mips_output_load_label (), &taken);
9558 output_asm_insn ("jr\t%@%]%/", 0);
9561 /* Now deal with its delay slot; see above. */
9564 /* This delay slot will only be executed if the branch is taken.
9565 Use INSN's delay slot if is annulled. */
9566 if (INSN_ANNULLED_BRANCH_P (insn))
9568 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9569 asm_out_file, optimize, 1, NULL);
9570 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9573 output_asm_insn ("nop", 0);
9574 fprintf (asm_out_file, "\n");
9577 /* Output NOT_TAKEN. */
9578 targetm.asm_out.internal_label (asm_out_file, "L",
9579 CODE_LABEL_NUMBER (not_taken));
9583 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9584 if some ordering condition is true. The condition is given by
9585 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9586 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9587 its second is always zero. */
9590 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9592 const char *branch[2];
9594 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9595 Make BRANCH[0] branch on the inverse condition. */
9596 switch (GET_CODE (operands[0]))
9598 /* These cases are equivalent to comparisons against zero. */
9600 inverted_p = !inverted_p;
9603 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9604 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9607 /* These cases are always true or always false. */
9609 inverted_p = !inverted_p;
9612 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9613 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9617 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9618 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9621 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9624 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
9625 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
9627 When working around R4000 and R4400 errata, we need to make sure that
9628 the division is not immediately followed by a shift[1][2]. We also
9629 need to stop the division from being put into a branch delay slot[3].
9630 The easiest way to avoid both problems is to add a nop after the
9631 division. When a divide-by-zero check is needed, this nop can be
9632 used to fill the branch delay slot.
9634 [1] If a double-word or a variable shift executes immediately
9635 after starting an integer division, the shift may give an
9636 incorrect result. See quotations of errata #16 and #28 from
9637 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9638 in mips.md for details.
9640 [2] A similar bug to [1] exists for all revisions of the
9641 R4000 and the R4400 when run in an MC configuration.
9642 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9644 "19. In this following sequence:
9646 ddiv (or ddivu or div or divu)
9647 dsll32 (or dsrl32, dsra32)
9649 if an MPT stall occurs, while the divide is slipping the cpu
9650 pipeline, then the following double shift would end up with an
9653 Workaround: The compiler needs to avoid generating any
9654 sequence with divide followed by extended double shift."
9656 This erratum is also present in "MIPS R4400MC Errata, Processor
9657 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9658 & 3.0" as errata #10 and #4, respectively.
9660 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9661 (also valid for MIPS R4000MC processors):
9663 "52. R4000SC: This bug does not apply for the R4000PC.
9665 There are two flavors of this bug:
9667 1) If the instruction just after divide takes an RF exception
9668 (tlb-refill, tlb-invalid) and gets an instruction cache
9669 miss (both primary and secondary) and the line which is
9670 currently in secondary cache at this index had the first
9671 data word, where the bits 5..2 are set, then R4000 would
9672 get a wrong result for the div.
9677 ------------------- # end-of page. -tlb-refill
9682 ------------------- # end-of page. -tlb-invalid
9685 2) If the divide is in the taken branch delay slot, where the
9686 target takes RF exception and gets an I-cache miss for the
9687 exception vector or where I-cache miss occurs for the
9688 target address, under the above mentioned scenarios, the
9689 div would get wrong results.
9692 j r2 # to next page mapped or unmapped
9693 div r8,r9 # this bug would be there as long
9694 # as there is an ICache miss and
9695 nop # the "data pattern" is present
9698 beq r0, r0, NextPage # to Next page
9702 This bug is present for div, divu, ddiv, and ddivu
9705 Workaround: For item 1), OS could make sure that the next page
9706 after the divide instruction is also mapped. For item 2), the
9707 compiler could make sure that the divide instruction is not in
9708 the branch delay slot."
9710 These processors have PRId values of 0x00004220 and 0x00004300 for
9711 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9714 mips_output_division (const char *division, rtx *operands)
9719 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9721 output_asm_insn (s, operands);
9724 if (TARGET_CHECK_ZERO_DIV)
9728 output_asm_insn (s, operands);
9729 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9731 else if (GENERATE_DIVIDE_TRAPS)
9733 output_asm_insn (s, operands);
9738 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9739 output_asm_insn (s, operands);
9740 s = "break\t7%)\n1:";
9746 /* Return true if IN_INSN is a multiply-add or multiply-subtract
9747 instruction and if OUT_INSN assigns to the accumulator operand. */
9750 mips_linked_madd_p (rtx out_insn, rtx in_insn)
9754 x = single_set (in_insn);
9760 if (GET_CODE (x) == PLUS
9761 && GET_CODE (XEXP (x, 0)) == MULT
9762 && reg_set_p (XEXP (x, 1), out_insn))
9765 if (GET_CODE (x) == MINUS
9766 && GET_CODE (XEXP (x, 1)) == MULT
9767 && reg_set_p (XEXP (x, 0), out_insn))
9773 /* True if the dependency between OUT_INSN and IN_INSN is on the store
9774 data rather than the address. We need this because the cprestore
9775 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
9776 which causes the default routine to abort. We just return false
9780 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
9782 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
9785 return !store_data_bypass_p (out_insn, in_insn);
9789 /* Variables and flags used in scheduler hooks when tuning for
9793 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
9796 /* If true, then next ALU1/2 instruction will go to ALU1. */
9799 /* If true, then next FALU1/2 unstruction will go to FALU1. */
9802 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
9803 int alu1_core_unit_code;
9804 int alu2_core_unit_code;
9805 int falu1_core_unit_code;
9806 int falu2_core_unit_code;
9808 /* True if current cycle has a multi instruction.
9809 This flag is used in mips_ls2_dfa_post_advance_cycle. */
9810 bool cycle_has_multi_p;
9812 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
9813 These are used in mips_ls2_dfa_post_advance_cycle to initialize
9815 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
9816 instruction to go ALU1. */
9817 rtx alu1_turn_enabled_insn;
9818 rtx alu2_turn_enabled_insn;
9819 rtx falu1_turn_enabled_insn;
9820 rtx falu2_turn_enabled_insn;
9823 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9824 dependencies have no cost, except on the 20Kc where output-dependence
9825 is treated like input-dependence. */
9828 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9829 rtx dep ATTRIBUTE_UNUSED, int cost)
9831 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
9834 if (REG_NOTE_KIND (link) != 0)
9839 /* Return the number of instructions that can be issued per cycle. */
9842 mips_issue_rate (void)
9846 case PROCESSOR_74KC:
9847 case PROCESSOR_74KF2_1:
9848 case PROCESSOR_74KF1_1:
9849 case PROCESSOR_74KF3_2:
9850 /* The 74k is not strictly quad-issue cpu, but can be seen as one
9851 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
9852 but in reality only a maximum of 3 insns can be issued as
9853 floating-point loads and stores also require a slot in the
9857 case PROCESSOR_20KC:
9858 case PROCESSOR_R4130:
9859 case PROCESSOR_R5400:
9860 case PROCESSOR_R5500:
9861 case PROCESSOR_R7000:
9862 case PROCESSOR_R9000:
9866 case PROCESSOR_SB1A:
9867 /* This is actually 4, but we get better performance if we claim 3.
9868 This is partly because of unwanted speculative code motion with the
9869 larger number, and partly because in most common cases we can't
9870 reach the theoretical max of 4. */
9873 case PROCESSOR_LOONGSON_2E:
9874 case PROCESSOR_LOONGSON_2F:
9882 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
9885 mips_ls2_init_dfa_post_cycle_insn (void)
9888 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
9889 mips_ls2.alu1_turn_enabled_insn = get_insns ();
9893 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
9894 mips_ls2.alu2_turn_enabled_insn = get_insns ();
9898 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
9899 mips_ls2.falu1_turn_enabled_insn = get_insns ();
9903 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
9904 mips_ls2.falu2_turn_enabled_insn = get_insns ();
9907 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
9908 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
9909 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
9910 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
9913 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
9914 Init data used in mips_dfa_post_advance_cycle. */
9917 mips_init_dfa_post_cycle_insn (void)
9919 if (TUNE_LOONGSON_2EF)
9920 mips_ls2_init_dfa_post_cycle_insn ();
9923 /* Initialize STATE when scheduling for Loongson 2E/2F.
9924 Support round-robin dispatch scheme by enabling only one of
9925 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
9929 mips_ls2_dfa_post_advance_cycle (state_t state)
9931 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
9933 /* Though there are no non-pipelined ALU1 insns,
9934 we can get an instruction of type 'multi' before reload. */
9935 gcc_assert (mips_ls2.cycle_has_multi_p);
9936 mips_ls2.alu1_turn_p = false;
9939 mips_ls2.cycle_has_multi_p = false;
9941 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
9942 /* We have a non-pipelined alu instruction in the core,
9943 adjust round-robin counter. */
9944 mips_ls2.alu1_turn_p = true;
9946 if (mips_ls2.alu1_turn_p)
9948 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
9953 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
9957 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
9959 /* There are no non-pipelined FALU1 insns. */
9961 mips_ls2.falu1_turn_p = false;
9964 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
9965 /* We have a non-pipelined falu instruction in the core,
9966 adjust round-robin counter. */
9967 mips_ls2.falu1_turn_p = true;
9969 if (mips_ls2.falu1_turn_p)
9971 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
9976 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
9981 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
9982 This hook is being called at the start of each cycle. */
9985 mips_dfa_post_advance_cycle (void)
9987 if (TUNE_LOONGSON_2EF)
9988 mips_ls2_dfa_post_advance_cycle (curr_state);
9991 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9992 be as wide as the scheduling freedom in the DFA. */
9995 mips_multipass_dfa_lookahead (void)
9997 /* Can schedule up to 4 of the 6 function units in any one cycle. */
10001 if (TUNE_LOONGSON_2EF)
10007 /* Remove the instruction at index LOWER from ready queue READY and
10008 reinsert it in front of the instruction at index HIGHER. LOWER must
10012 mips_promote_ready (rtx *ready, int lower, int higher)
10017 new_head = ready[lower];
10018 for (i = lower; i < higher; i++)
10019 ready[i] = ready[i + 1];
10020 ready[i] = new_head;
10023 /* If the priority of the instruction at POS2 in the ready queue READY
10024 is within LIMIT units of that of the instruction at POS1, swap the
10025 instructions if POS2 is not already less than POS1. */
10028 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
10031 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
10035 temp = ready[pos1];
10036 ready[pos1] = ready[pos2];
10037 ready[pos2] = temp;
10041 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
10042 that may clobber hi or lo. */
10043 static rtx mips_macc_chains_last_hilo;
10045 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
10046 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
10049 mips_macc_chains_record (rtx insn)
10051 if (get_attr_may_clobber_hilo (insn))
10052 mips_macc_chains_last_hilo = insn;
10055 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
10056 has NREADY elements, looking for a multiply-add or multiply-subtract
10057 instruction that is cumulative with mips_macc_chains_last_hilo.
10058 If there is one, promote it ahead of anything else that might
10059 clobber hi or lo. */
10062 mips_macc_chains_reorder (rtx *ready, int nready)
10066 if (mips_macc_chains_last_hilo != 0)
10067 for (i = nready - 1; i >= 0; i--)
10068 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
10070 for (j = nready - 1; j > i; j--)
10071 if (recog_memoized (ready[j]) >= 0
10072 && get_attr_may_clobber_hilo (ready[j]))
10074 mips_promote_ready (ready, i, j);
10081 /* The last instruction to be scheduled. */
10082 static rtx vr4130_last_insn;
10084 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
10085 points to an rtx that is initially an instruction. Nullify the rtx
10086 if the instruction uses the value of register X. */
10089 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
10094 insn_ptr = (rtx *) data;
10097 && reg_referenced_p (x, PATTERN (*insn_ptr)))
10101 /* Return true if there is true register dependence between vr4130_last_insn
10105 vr4130_true_reg_dependence_p (rtx insn)
10107 note_stores (PATTERN (vr4130_last_insn),
10108 vr4130_true_reg_dependence_p_1, &insn);
10112 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
10113 the ready queue and that INSN2 is the instruction after it, return
10114 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
10115 in which INSN1 and INSN2 can probably issue in parallel, but for
10116 which (INSN2, INSN1) should be less sensitive to instruction
10117 alignment than (INSN1, INSN2). See 4130.md for more details. */
10120 vr4130_swap_insns_p (rtx insn1, rtx insn2)
10122 sd_iterator_def sd_it;
10125 /* Check for the following case:
10127 1) there is some other instruction X with an anti dependence on INSN1;
10128 2) X has a higher priority than INSN2; and
10129 3) X is an arithmetic instruction (and thus has no unit restrictions).
10131 If INSN1 is the last instruction blocking X, it would better to
10132 choose (INSN1, X) over (INSN2, INSN1). */
10133 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
10134 if (DEP_TYPE (dep) == REG_DEP_ANTI
10135 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
10136 && recog_memoized (DEP_CON (dep)) >= 0
10137 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
10140 if (vr4130_last_insn != 0
10141 && recog_memoized (insn1) >= 0
10142 && recog_memoized (insn2) >= 0)
10144 /* See whether INSN1 and INSN2 use different execution units,
10145 or if they are both ALU-type instructions. If so, they can
10146 probably execute in parallel. */
10147 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
10148 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
10149 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
10151 /* If only one of the instructions has a dependence on
10152 vr4130_last_insn, prefer to schedule the other one first. */
10153 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
10154 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
10155 if (dep1_p != dep2_p)
10158 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
10159 is not an ALU-type instruction and if INSN1 uses the same
10160 execution unit. (Note that if this condition holds, we already
10161 know that INSN2 uses a different execution unit.) */
10162 if (class1 != VR4130_CLASS_ALU
10163 && recog_memoized (vr4130_last_insn) >= 0
10164 && class1 == get_attr_vr4130_class (vr4130_last_insn))
10171 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
10172 queue with at least two instructions. Swap the first two if
10173 vr4130_swap_insns_p says that it could be worthwhile. */
10176 vr4130_reorder (rtx *ready, int nready)
10178 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
10179 mips_promote_ready (ready, nready - 2, nready - 1);
10182 /* Record whether last 74k AGEN instruction was a load or store. */
10183 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
10185 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
10186 resets to TYPE_UNKNOWN state. */
10189 mips_74k_agen_init (rtx insn)
10191 if (!insn || !NONJUMP_INSN_P (insn))
10192 mips_last_74k_agen_insn = TYPE_UNKNOWN;
10195 enum attr_type type = get_attr_type (insn);
10196 if (type == TYPE_LOAD || type == TYPE_STORE)
10197 mips_last_74k_agen_insn = type;
10201 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
10202 loads to be grouped together, and multiple stores to be grouped
10203 together. Swap things around in the ready queue to make this happen. */
10206 mips_74k_agen_reorder (rtx *ready, int nready)
10209 int store_pos, load_pos;
10214 for (i = nready - 1; i >= 0; i--)
10216 rtx insn = ready[i];
10217 if (USEFUL_INSN_P (insn))
10218 switch (get_attr_type (insn))
10221 if (store_pos == -1)
10226 if (load_pos == -1)
10235 if (load_pos == -1 || store_pos == -1)
10238 switch (mips_last_74k_agen_insn)
10241 /* Prefer to schedule loads since they have a higher latency. */
10243 /* Swap loads to the front of the queue. */
10244 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
10247 /* Swap stores to the front of the queue. */
10248 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
10255 /* Implement TARGET_SCHED_INIT. */
10258 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10259 int max_ready ATTRIBUTE_UNUSED)
10261 mips_macc_chains_last_hilo = 0;
10262 vr4130_last_insn = 0;
10263 mips_74k_agen_init (NULL_RTX);
10265 /* When scheduling for Loongson2, branch instructions go to ALU1,
10266 therefore basic block is most likely to start with round-robin counter
10267 pointed to ALU2. */
10268 mips_ls2.alu1_turn_p = false;
10269 mips_ls2.falu1_turn_p = true;
10272 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
10275 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10276 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
10278 if (!reload_completed
10279 && TUNE_MACC_CHAINS
10281 mips_macc_chains_reorder (ready, *nreadyp);
10283 if (reload_completed
10285 && !TARGET_VR4130_ALIGN
10287 vr4130_reorder (ready, *nreadyp);
10290 mips_74k_agen_reorder (ready, *nreadyp);
10292 return mips_issue_rate ();
10295 /* Update round-robin counters for ALU1/2 and FALU1/2. */
10298 mips_ls2_variable_issue (rtx insn)
10300 if (mips_ls2.alu1_turn_p)
10302 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
10303 mips_ls2.alu1_turn_p = false;
10307 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
10308 mips_ls2.alu1_turn_p = true;
10311 if (mips_ls2.falu1_turn_p)
10313 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
10314 mips_ls2.falu1_turn_p = false;
10318 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
10319 mips_ls2.falu1_turn_p = true;
10322 if (recog_memoized (insn) >= 0)
10323 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
10326 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
10329 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10330 rtx insn, int more)
10332 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
10333 if (USEFUL_INSN_P (insn))
10336 if (!reload_completed && TUNE_MACC_CHAINS)
10337 mips_macc_chains_record (insn);
10338 vr4130_last_insn = insn;
10340 mips_74k_agen_init (insn);
10341 else if (TUNE_LOONGSON_2EF)
10342 mips_ls2_variable_issue (insn);
10345 /* Instructions of type 'multi' should all be split before
10346 the second scheduling pass. */
10347 gcc_assert (!reload_completed
10348 || recog_memoized (insn) < 0
10349 || get_attr_type (insn) != TYPE_MULTI);
10354 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10355 return the first operand of the associated PREF or PREFX insn. */
10358 mips_prefetch_cookie (rtx write, rtx locality)
10360 /* store_streamed / load_streamed. */
10361 if (INTVAL (locality) <= 0)
10362 return GEN_INT (INTVAL (write) + 4);
10364 /* store / load. */
10365 if (INTVAL (locality) <= 2)
10368 /* store_retained / load_retained. */
10369 return GEN_INT (INTVAL (write) + 6);
10372 /* Flags that indicate when a built-in function is available.
10374 BUILTIN_AVAIL_NON_MIPS16
10375 The function is available on the current target, but only
10376 in non-MIPS16 mode. */
10377 #define BUILTIN_AVAIL_NON_MIPS16 1
10379 /* Declare an availability predicate for built-in functions that
10380 require non-MIPS16 mode and also require COND to be true.
10381 NAME is the main part of the predicate's name. */
10382 #define AVAIL_NON_MIPS16(NAME, COND) \
10383 static unsigned int \
10384 mips_builtin_avail_##NAME (void) \
10386 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
10389 /* This structure describes a single built-in function. */
10390 struct mips_builtin_description {
10391 /* The code of the main .md file instruction. See mips_builtin_type
10392 for more information. */
10393 enum insn_code icode;
10395 /* The floating-point comparison code to use with ICODE, if any. */
10396 enum mips_fp_condition cond;
10398 /* The name of the built-in function. */
10401 /* Specifies how the function should be expanded. */
10402 enum mips_builtin_type builtin_type;
10404 /* The function's prototype. */
10405 enum mips_function_type function_type;
10407 /* Whether the function is available. */
10408 unsigned int (*avail) (void);
10411 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
10412 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
10413 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
10414 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
10415 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
10416 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
10417 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
10418 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
10420 /* Construct a mips_builtin_description from the given arguments.
10422 INSN is the name of the associated instruction pattern, without the
10423 leading CODE_FOR_mips_.
10425 CODE is the floating-point condition code associated with the
10426 function. It can be 'f' if the field is not applicable.
10428 NAME is the name of the function itself, without the leading
10431 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
10433 AVAIL is the name of the availability predicate, without the leading
10434 mips_builtin_avail_. */
10435 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
10436 FUNCTION_TYPE, AVAIL) \
10437 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
10438 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
10439 mips_builtin_avail_ ## AVAIL }
10441 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
10442 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
10443 are as for MIPS_BUILTIN. */
10444 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
10445 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
10447 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
10448 are subject to mips_builtin_avail_<AVAIL>. */
10449 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
10450 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
10451 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
10452 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
10453 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
10455 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10456 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
10457 while the any and all forms are subject to mips_builtin_avail_mips3d. */
10458 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
10459 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
10460 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
10462 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
10463 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
10465 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
10466 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
10468 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
10469 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
10472 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10473 are subject to mips_builtin_avail_mips3d. */
10474 #define CMP_4S_BUILTINS(INSN, COND) \
10475 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
10476 MIPS_BUILTIN_CMP_ANY, \
10477 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
10478 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
10479 MIPS_BUILTIN_CMP_ALL, \
10480 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
10482 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10483 instruction requires mips_builtin_avail_<AVAIL>. */
10484 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
10485 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
10486 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10488 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
10489 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10492 /* Define all the built-in functions related to C.cond.fmt condition COND. */
10493 #define CMP_BUILTINS(COND) \
10494 MOVTF_BUILTINS (c, COND, paired_single), \
10495 MOVTF_BUILTINS (cabs, COND, mips3d), \
10496 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
10497 CMP_PS_BUILTINS (c, COND, paired_single), \
10498 CMP_PS_BUILTINS (cabs, COND, mips3d), \
10499 CMP_4S_BUILTINS (c, COND), \
10500 CMP_4S_BUILTINS (cabs, COND)
10502 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
10503 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
10504 and AVAIL are as for MIPS_BUILTIN. */
10505 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
10506 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
10507 FUNCTION_TYPE, AVAIL)
10509 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10510 branch instruction. AVAIL is as for MIPS_BUILTIN. */
10511 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
10512 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
10513 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
10515 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
10516 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
10517 builtin_description field. */
10518 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
10519 { CODE_FOR_loongson_ ## INSN, 0, "__builtin_loongson_" #FN_NAME, \
10520 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_loongson }
10522 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
10523 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
10524 builtin_description field. */
10525 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
10526 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
10528 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
10529 We use functions of this form when the same insn can be usefully applied
10530 to more than one datatype. */
10531 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
10532 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
10534 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10535 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10536 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10537 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10538 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10539 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
10541 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
10542 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
10543 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
10544 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
10545 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
10546 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
10547 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
10548 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
10549 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
10550 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
10551 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
10552 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
10553 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
10554 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
10555 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
10556 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
10557 #define CODE_FOR_loongson_biadd CODE_FOR_reduc_uplus_v8qi
10558 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
10559 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
10560 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
10561 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
10562 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
10563 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
10564 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
10565 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
10566 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
10567 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
10568 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
10569 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
10570 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
10572 static const struct mips_builtin_description mips_builtins[] = {
10573 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
10574 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
10575 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
10576 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
10577 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
10578 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
10579 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
10580 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
10582 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
10583 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
10584 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
10585 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
10586 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
10588 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
10589 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
10590 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
10591 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
10592 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
10593 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
10595 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
10596 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
10597 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
10598 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
10599 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
10600 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
10602 MIPS_FP_CONDITIONS (CMP_BUILTINS),
10604 /* Built-in functions for the SB-1 processor. */
10605 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
10607 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
10608 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10609 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10610 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
10611 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
10612 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
10613 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10614 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10615 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
10616 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
10617 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
10618 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
10619 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
10620 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
10621 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
10622 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
10623 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
10624 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
10625 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
10626 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
10627 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
10628 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
10629 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
10630 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
10631 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
10632 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
10633 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
10634 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
10635 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
10636 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
10637 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
10638 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
10639 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
10640 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
10641 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
10642 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
10643 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
10644 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
10645 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
10646 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
10647 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
10648 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10649 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
10650 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
10651 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
10652 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
10653 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
10654 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
10655 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
10656 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
10657 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
10658 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
10659 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
10660 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
10661 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
10662 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
10663 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
10664 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
10665 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10666 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10667 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
10668 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
10669 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
10670 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
10671 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
10672 BPOSGE_BUILTIN (32, dsp),
10674 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
10675 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
10676 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10677 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10678 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
10679 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
10680 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
10681 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
10682 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
10683 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
10684 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
10685 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10686 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10687 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10688 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10689 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10690 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
10691 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
10692 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
10693 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
10694 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
10695 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
10696 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
10697 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10698 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10699 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
10700 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
10701 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10702 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10703 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10704 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10705 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10706 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10707 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10708 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10710 /* Built-in functions for the DSP ASE (32-bit only). */
10711 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
10712 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
10713 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
10714 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
10715 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10716 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10717 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10718 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
10719 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
10720 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10721 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10722 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10723 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10724 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
10725 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
10726 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
10727 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
10728 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
10729 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
10730 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
10731 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
10733 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
10734 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10735 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10736 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
10737 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
10738 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
10739 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
10740 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10741 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32),
10742 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32),
10743 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10744 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10745 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10746 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10747 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10748 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10750 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
10751 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
10752 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
10753 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
10754 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10755 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10756 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10757 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
10758 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10759 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10760 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
10761 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
10762 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10763 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
10764 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10765 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10766 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
10767 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10768 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10769 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10770 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
10771 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
10772 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10773 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
10774 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10775 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10776 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10777 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10778 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10779 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
10780 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10781 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10782 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10783 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10784 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10785 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
10786 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10787 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10788 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
10789 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
10790 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10791 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10792 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10793 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10794 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10795 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10796 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10797 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10798 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
10799 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10800 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10801 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10802 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10803 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
10804 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
10805 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10806 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10807 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10808 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
10809 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10810 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
10811 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
10812 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
10813 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
10814 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
10815 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
10816 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
10817 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
10818 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
10819 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
10820 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
10821 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
10822 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
10823 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
10824 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
10825 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
10826 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10827 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10828 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10829 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
10830 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10831 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10832 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
10833 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
10834 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10835 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
10836 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10837 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10838 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10839 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10840 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10841 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10842 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10843 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
10844 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10845 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10846 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10847 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10848 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10849 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI)
10852 /* MODE is a vector mode whose elements have type TYPE. Return the type
10853 of the vector itself. */
10856 mips_builtin_vector_type (tree type, enum machine_mode mode)
10858 static tree types[2 * (int) MAX_MACHINE_MODE];
10861 mode_index = (int) mode;
10863 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
10864 mode_index += MAX_MACHINE_MODE;
10866 if (types[mode_index] == NULL_TREE)
10867 types[mode_index] = build_vector_type_for_mode (type, mode);
10868 return types[mode_index];
10871 /* Source-level argument types. */
10872 #define MIPS_ATYPE_VOID void_type_node
10873 #define MIPS_ATYPE_INT integer_type_node
10874 #define MIPS_ATYPE_POINTER ptr_type_node
10876 /* Standard mode-based argument types. */
10877 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
10878 #define MIPS_ATYPE_SI intSI_type_node
10879 #define MIPS_ATYPE_USI unsigned_intSI_type_node
10880 #define MIPS_ATYPE_DI intDI_type_node
10881 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
10882 #define MIPS_ATYPE_SF float_type_node
10883 #define MIPS_ATYPE_DF double_type_node
10885 /* Vector argument types. */
10886 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
10887 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
10888 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
10889 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
10890 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
10891 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
10892 #define MIPS_ATYPE_UV2SI \
10893 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
10894 #define MIPS_ATYPE_UV4HI \
10895 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
10896 #define MIPS_ATYPE_UV8QI \
10897 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
10899 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
10900 their associated MIPS_ATYPEs. */
10901 #define MIPS_FTYPE_ATYPES1(A, B) \
10902 MIPS_ATYPE_##A, MIPS_ATYPE_##B
10904 #define MIPS_FTYPE_ATYPES2(A, B, C) \
10905 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
10907 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
10908 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
10910 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
10911 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
10914 /* Return the function type associated with function prototype TYPE. */
10917 mips_build_function_type (enum mips_function_type type)
10919 static tree types[(int) MIPS_MAX_FTYPE_MAX];
10921 if (types[(int) type] == NULL_TREE)
10924 #define DEF_MIPS_FTYPE(NUM, ARGS) \
10925 case MIPS_FTYPE_NAME##NUM ARGS: \
10926 types[(int) type] \
10927 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
10930 #include "config/mips/mips-ftypes.def"
10931 #undef DEF_MIPS_FTYPE
10933 gcc_unreachable ();
10936 return types[(int) type];
10939 /* Implement TARGET_INIT_BUILTINS. */
10942 mips_init_builtins (void)
10944 const struct mips_builtin_description *d;
10947 /* Iterate through all of the bdesc arrays, initializing all of the
10948 builtin functions. */
10949 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
10951 d = &mips_builtins[i];
10953 add_builtin_function (d->name,
10954 mips_build_function_type (d->function_type),
10955 i, BUILT_IN_MD, NULL, NULL);
10959 /* Take argument ARGNO from EXP's argument list and convert it into a
10960 form suitable for input operand OPNO of instruction ICODE. Return the
10964 mips_prepare_builtin_arg (enum insn_code icode,
10965 unsigned int opno, tree exp, unsigned int argno)
10968 enum machine_mode mode;
10970 value = expand_normal (CALL_EXPR_ARG (exp, argno));
10971 mode = insn_data[icode].operand[opno].mode;
10972 if (!insn_data[icode].operand[opno].predicate (value, mode))
10974 value = copy_to_mode_reg (mode, value);
10975 /* Check the predicate again. */
10976 if (!insn_data[icode].operand[opno].predicate (value, mode))
10978 error ("invalid argument to built-in function");
10986 /* Return an rtx suitable for output operand OP of instruction ICODE.
10987 If TARGET is non-null, try to use it where possible. */
10990 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10992 enum machine_mode mode;
10994 mode = insn_data[icode].operand[op].mode;
10995 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10996 target = gen_reg_rtx (mode);
11001 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
11002 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
11003 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
11004 suggests a good place to put the result. */
11007 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
11010 rtx ops[MAX_RECOG_OPERANDS];
11013 /* Map any target to operand 0. */
11017 ops[opno] = mips_prepare_builtin_target (icode, opno, target);
11021 /* Map the arguments to the other operands. The n_operands value
11022 for an expander includes match_dups and match_scratches as well as
11023 match_operands, so n_operands is only an upper bound on the number
11024 of arguments to the expander function. */
11025 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
11026 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
11027 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
11032 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
11036 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
11040 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
11044 gcc_unreachable ();
11049 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
11050 function; TYPE says which. EXP is the CALL_EXPR that calls the
11051 function, ICODE is the instruction that should be used to compare
11052 the first two arguments, and COND is the condition it should test.
11053 TARGET, if nonnull, suggests a good place to put the result. */
11056 mips_expand_builtin_movtf (enum mips_builtin_type type,
11057 enum insn_code icode, enum mips_fp_condition cond,
11058 rtx target, tree exp)
11060 rtx cmp_result, op0, op1;
11062 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11063 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
11064 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
11065 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
11067 icode = CODE_FOR_mips_cond_move_tf_ps;
11068 target = mips_prepare_builtin_target (icode, 0, target);
11069 if (type == MIPS_BUILTIN_MOVT)
11071 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
11072 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
11076 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
11077 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
11079 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
11083 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
11084 into TARGET otherwise. Return TARGET. */
11087 mips_builtin_branch_and_move (rtx condition, rtx target,
11088 rtx value_if_true, rtx value_if_false)
11090 rtx true_label, done_label;
11092 true_label = gen_label_rtx ();
11093 done_label = gen_label_rtx ();
11095 /* First assume that CONDITION is false. */
11096 mips_emit_move (target, value_if_false);
11098 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
11099 emit_jump_insn (gen_condjump (condition, true_label));
11100 emit_jump_insn (gen_jump (done_label));
11103 /* Fix TARGET if CONDITION is true. */
11104 emit_label (true_label);
11105 mips_emit_move (target, value_if_true);
11107 emit_label (done_label);
11111 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
11112 the CALL_EXPR that calls the function, ICODE is the code of the
11113 comparison instruction, and COND is the condition it should test.
11114 TARGET, if nonnull, suggests a good place to put the boolean result. */
11117 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
11118 enum insn_code icode, enum mips_fp_condition cond,
11119 rtx target, tree exp)
11121 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
11124 if (target == 0 || GET_MODE (target) != SImode)
11125 target = gen_reg_rtx (SImode);
11127 /* The instruction should have a target operand, an operand for each
11128 argument, and an operand for COND. */
11129 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
11131 /* Prepare the operands to the comparison. */
11132 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11133 for (argno = 0; argno < call_expr_nargs (exp); argno++)
11134 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
11136 switch (insn_data[icode].n_operands)
11139 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
11144 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
11145 args[2], args[3], GEN_INT (cond)));
11149 gcc_unreachable ();
11152 /* If the comparison sets more than one register, we define the result
11153 to be 0 if all registers are false and -1 if all registers are true.
11154 The value of the complete result is indeterminate otherwise. */
11155 switch (builtin_type)
11157 case MIPS_BUILTIN_CMP_ALL:
11158 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
11159 return mips_builtin_branch_and_move (condition, target,
11160 const0_rtx, const1_rtx);
11162 case MIPS_BUILTIN_CMP_UPPER:
11163 case MIPS_BUILTIN_CMP_LOWER:
11164 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
11165 condition = gen_single_cc (cmp_result, offset);
11166 return mips_builtin_branch_and_move (condition, target,
11167 const1_rtx, const0_rtx);
11170 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
11171 return mips_builtin_branch_and_move (condition, target,
11172 const1_rtx, const0_rtx);
11176 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
11177 if nonnull, suggests a good place to put the boolean result. */
11180 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
11182 rtx condition, cmp_result;
11185 if (target == 0 || GET_MODE (target) != SImode)
11186 target = gen_reg_rtx (SImode);
11188 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
11190 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
11195 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
11196 return mips_builtin_branch_and_move (condition, target,
11197 const1_rtx, const0_rtx);
11200 /* Implement TARGET_EXPAND_BUILTIN. */
11203 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11204 enum machine_mode mode ATTRIBUTE_UNUSED,
11205 int ignore ATTRIBUTE_UNUSED)
11208 unsigned int fcode, avail;
11209 const struct mips_builtin_description *d;
11211 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11212 fcode = DECL_FUNCTION_CODE (fndecl);
11213 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
11214 d = &mips_builtins[fcode];
11215 avail = d->avail ();
11216 gcc_assert (avail != 0);
11219 error ("built-in function %qs not supported for MIPS16",
11220 IDENTIFIER_POINTER (DECL_NAME (fndecl)));
11223 switch (d->builtin_type)
11225 case MIPS_BUILTIN_DIRECT:
11226 return mips_expand_builtin_direct (d->icode, target, exp, true);
11228 case MIPS_BUILTIN_DIRECT_NO_TARGET:
11229 return mips_expand_builtin_direct (d->icode, target, exp, false);
11231 case MIPS_BUILTIN_MOVT:
11232 case MIPS_BUILTIN_MOVF:
11233 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
11234 d->cond, target, exp);
11236 case MIPS_BUILTIN_CMP_ANY:
11237 case MIPS_BUILTIN_CMP_ALL:
11238 case MIPS_BUILTIN_CMP_UPPER:
11239 case MIPS_BUILTIN_CMP_LOWER:
11240 case MIPS_BUILTIN_CMP_SINGLE:
11241 return mips_expand_builtin_compare (d->builtin_type, d->icode,
11242 d->cond, target, exp);
11244 case MIPS_BUILTIN_BPOSGE32:
11245 return mips_expand_builtin_bposge (d->builtin_type, target);
11247 gcc_unreachable ();
11250 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
11251 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
11252 struct mips16_constant {
11253 struct mips16_constant *next;
11256 enum machine_mode mode;
11259 /* Information about an incomplete MIPS16 constant pool. FIRST is the
11260 first constant, HIGHEST_ADDRESS is the highest address that the first
11261 byte of the pool can have, and INSN_ADDRESS is the current instruction
11263 struct mips16_constant_pool {
11264 struct mips16_constant *first;
11265 int highest_address;
11269 /* Add constant VALUE to POOL and return its label. MODE is the
11270 value's mode (used for CONST_INTs, etc.). */
11273 mips16_add_constant (struct mips16_constant_pool *pool,
11274 rtx value, enum machine_mode mode)
11276 struct mips16_constant **p, *c;
11277 bool first_of_size_p;
11279 /* See whether the constant is already in the pool. If so, return the
11280 existing label, otherwise leave P pointing to the place where the
11281 constant should be added.
11283 Keep the pool sorted in increasing order of mode size so that we can
11284 reduce the number of alignments needed. */
11285 first_of_size_p = true;
11286 for (p = &pool->first; *p != 0; p = &(*p)->next)
11288 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
11289 return (*p)->label;
11290 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
11292 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
11293 first_of_size_p = false;
11296 /* In the worst case, the constant needed by the earliest instruction
11297 will end up at the end of the pool. The entire pool must then be
11298 accessible from that instruction.
11300 When adding the first constant, set the pool's highest address to
11301 the address of the first out-of-range byte. Adjust this address
11302 downwards each time a new constant is added. */
11303 if (pool->first == 0)
11304 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
11305 of the instruction with the lowest two bits clear. The base PC
11306 value for LDPC has the lowest three bits clear. Assume the worst
11307 case here; namely that the PC-relative instruction occupies the
11308 last 2 bytes in an aligned word. */
11309 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
11310 pool->highest_address -= GET_MODE_SIZE (mode);
11311 if (first_of_size_p)
11312 /* Take into account the worst possible padding due to alignment. */
11313 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
11315 /* Create a new entry. */
11316 c = XNEW (struct mips16_constant);
11319 c->label = gen_label_rtx ();
11326 /* Output constant VALUE after instruction INSN and return the last
11327 instruction emitted. MODE is the mode of the constant. */
11330 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
11332 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
11334 rtx size = GEN_INT (GET_MODE_SIZE (mode));
11335 return emit_insn_after (gen_consttable_int (value, size), insn);
11338 if (SCALAR_FLOAT_MODE_P (mode))
11339 return emit_insn_after (gen_consttable_float (value), insn);
11341 if (VECTOR_MODE_P (mode))
11345 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
11346 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
11347 CONST_VECTOR_ELT (value, i), insn);
11351 gcc_unreachable ();
11354 /* Dump out the constants in CONSTANTS after INSN. */
11357 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
11359 struct mips16_constant *c, *next;
11363 for (c = constants; c != NULL; c = next)
11365 /* If necessary, increase the alignment of PC. */
11366 if (align < GET_MODE_SIZE (c->mode))
11368 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
11369 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
11371 align = GET_MODE_SIZE (c->mode);
11373 insn = emit_label_after (c->label, insn);
11374 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
11380 emit_barrier_after (insn);
11383 /* Return the length of instruction INSN. */
11386 mips16_insn_length (rtx insn)
11390 rtx body = PATTERN (insn);
11391 if (GET_CODE (body) == ADDR_VEC)
11392 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
11393 if (GET_CODE (body) == ADDR_DIFF_VEC)
11394 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
11396 return get_attr_length (insn);
11399 /* If *X is a symbolic constant that refers to the constant pool, add
11400 the constant to POOL and rewrite *X to use the constant's label. */
11403 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
11405 rtx base, offset, label;
11407 split_const (*x, &base, &offset);
11408 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
11410 label = mips16_add_constant (pool, get_pool_constant (base),
11411 get_pool_mode (base));
11412 base = gen_rtx_LABEL_REF (Pmode, label);
11413 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
11417 /* This structure is used to communicate with mips16_rewrite_pool_refs.
11418 INSN is the instruction we're rewriting and POOL points to the current
11420 struct mips16_rewrite_pool_refs_info {
11422 struct mips16_constant_pool *pool;
11425 /* Rewrite *X so that constant pool references refer to the constant's
11426 label instead. DATA points to a mips16_rewrite_pool_refs_info
11430 mips16_rewrite_pool_refs (rtx *x, void *data)
11432 struct mips16_rewrite_pool_refs_info *info =
11433 (struct mips16_rewrite_pool_refs_info *) data;
11435 if (force_to_mem_operand (*x, Pmode))
11437 rtx mem = force_const_mem (GET_MODE (*x), *x);
11438 validate_change (info->insn, x, mem, false);
11443 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
11447 if (TARGET_MIPS16_TEXT_LOADS)
11448 mips16_rewrite_pool_constant (info->pool, x);
11450 return GET_CODE (*x) == CONST ? -1 : 0;
11453 /* Build MIPS16 constant pools. */
11456 mips16_lay_out_constants (void)
11458 struct mips16_constant_pool pool;
11459 struct mips16_rewrite_pool_refs_info info;
11462 if (!TARGET_MIPS16_PCREL_LOADS)
11466 memset (&pool, 0, sizeof (pool));
11467 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11469 /* Rewrite constant pool references in INSN. */
11474 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
11477 pool.insn_address += mips16_insn_length (insn);
11479 if (pool.first != NULL)
11481 /* If there are no natural barriers between the first user of
11482 the pool and the highest acceptable address, we'll need to
11483 create a new instruction to jump around the constant pool.
11484 In the worst case, this instruction will be 4 bytes long.
11486 If it's too late to do this transformation after INSN,
11487 do it immediately before INSN. */
11488 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
11492 label = gen_label_rtx ();
11494 jump = emit_jump_insn_before (gen_jump (label), insn);
11495 JUMP_LABEL (jump) = label;
11496 LABEL_NUSES (label) = 1;
11497 barrier = emit_barrier_after (jump);
11499 emit_label_after (label, barrier);
11500 pool.insn_address += 4;
11503 /* See whether the constant pool is now out of range of the first
11504 user. If so, output the constants after the previous barrier.
11505 Note that any instructions between BARRIER and INSN (inclusive)
11506 will use negative offsets to refer to the pool. */
11507 if (pool.insn_address > pool.highest_address)
11509 mips16_emit_constants (pool.first, barrier);
11513 else if (BARRIER_P (insn))
11517 mips16_emit_constants (pool.first, get_last_insn ());
11520 /* A temporary variable used by for_each_rtx callbacks, etc. */
11521 static rtx mips_sim_insn;
11523 /* A structure representing the state of the processor pipeline.
11524 Used by the mips_sim_* family of functions. */
11526 /* The maximum number of instructions that can be issued in a cycle.
11527 (Caches mips_issue_rate.) */
11528 unsigned int issue_rate;
11530 /* The current simulation time. */
11533 /* How many more instructions can be issued in the current cycle. */
11534 unsigned int insns_left;
11536 /* LAST_SET[X].INSN is the last instruction to set register X.
11537 LAST_SET[X].TIME is the time at which that instruction was issued.
11538 INSN is null if no instruction has yet set register X. */
11542 } last_set[FIRST_PSEUDO_REGISTER];
11544 /* The pipeline's current DFA state. */
11548 /* Reset STATE to the initial simulation state. */
11551 mips_sim_reset (struct mips_sim *state)
11554 state->insns_left = state->issue_rate;
11555 memset (&state->last_set, 0, sizeof (state->last_set));
11556 state_reset (state->dfa_state);
11559 /* Initialize STATE before its first use. DFA_STATE points to an
11560 allocated but uninitialized DFA state. */
11563 mips_sim_init (struct mips_sim *state, state_t dfa_state)
11565 state->issue_rate = mips_issue_rate ();
11566 state->dfa_state = dfa_state;
11567 mips_sim_reset (state);
11570 /* Advance STATE by one clock cycle. */
11573 mips_sim_next_cycle (struct mips_sim *state)
11576 state->insns_left = state->issue_rate;
11577 state_transition (state->dfa_state, 0);
11580 /* Advance simulation state STATE until instruction INSN can read
11584 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
11586 unsigned int regno, end_regno;
11588 end_regno = END_REGNO (reg);
11589 for (regno = REGNO (reg); regno < end_regno; regno++)
11590 if (state->last_set[regno].insn != 0)
11594 t = (state->last_set[regno].time
11595 + insn_latency (state->last_set[regno].insn, insn));
11596 while (state->time < t)
11597 mips_sim_next_cycle (state);
11601 /* A for_each_rtx callback. If *X is a register, advance simulation state
11602 DATA until mips_sim_insn can read the register's value. */
11605 mips_sim_wait_regs_2 (rtx *x, void *data)
11608 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
11612 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
11615 mips_sim_wait_regs_1 (rtx *x, void *data)
11617 for_each_rtx (x, mips_sim_wait_regs_2, data);
11620 /* Advance simulation state STATE until all of INSN's register
11621 dependencies are satisfied. */
11624 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
11626 mips_sim_insn = insn;
11627 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
11630 /* Advance simulation state STATE until the units required by
11631 instruction INSN are available. */
11634 mips_sim_wait_units (struct mips_sim *state, rtx insn)
11638 tmp_state = alloca (state_size ());
11639 while (state->insns_left == 0
11640 || (memcpy (tmp_state, state->dfa_state, state_size ()),
11641 state_transition (tmp_state, insn) >= 0))
11642 mips_sim_next_cycle (state);
11645 /* Advance simulation state STATE until INSN is ready to issue. */
11648 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
11650 mips_sim_wait_regs (state, insn);
11651 mips_sim_wait_units (state, insn);
11654 /* mips_sim_insn has just set X. Update the LAST_SET array
11655 in simulation state DATA. */
11658 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
11660 struct mips_sim *state;
11662 state = (struct mips_sim *) data;
11665 unsigned int regno, end_regno;
11667 end_regno = END_REGNO (x);
11668 for (regno = REGNO (x); regno < end_regno; regno++)
11670 state->last_set[regno].insn = mips_sim_insn;
11671 state->last_set[regno].time = state->time;
11676 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
11677 can issue immediately (i.e., that mips_sim_wait_insn has already
11681 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
11683 state_transition (state->dfa_state, insn);
11684 state->insns_left--;
11686 mips_sim_insn = insn;
11687 note_stores (PATTERN (insn), mips_sim_record_set, state);
11690 /* Simulate issuing a NOP in state STATE. */
11693 mips_sim_issue_nop (struct mips_sim *state)
11695 if (state->insns_left == 0)
11696 mips_sim_next_cycle (state);
11697 state->insns_left--;
11700 /* Update simulation state STATE so that it's ready to accept the instruction
11701 after INSN. INSN should be part of the main rtl chain, not a member of a
11705 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
11707 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
11709 mips_sim_issue_nop (state);
11711 switch (GET_CODE (SEQ_BEGIN (insn)))
11715 /* We can't predict the processor state after a call or label. */
11716 mips_sim_reset (state);
11720 /* The delay slots of branch likely instructions are only executed
11721 when the branch is taken. Therefore, if the caller has simulated
11722 the delay slot instruction, STATE does not really reflect the state
11723 of the pipeline for the instruction after the delay slot. Also,
11724 branch likely instructions tend to incur a penalty when not taken,
11725 so there will probably be an extra delay between the branch and
11726 the instruction after the delay slot. */
11727 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
11728 mips_sim_reset (state);
11736 /* The VR4130 pipeline issues aligned pairs of instructions together,
11737 but it stalls the second instruction if it depends on the first.
11738 In order to cut down the amount of logic required, this dependence
11739 check is not based on a full instruction decode. Instead, any non-SPECIAL
11740 instruction is assumed to modify the register specified by bits 20-16
11741 (which is usually the "rt" field).
11743 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
11744 input, so we can end up with a false dependence between the branch
11745 and its delay slot. If this situation occurs in instruction INSN,
11746 try to avoid it by swapping rs and rt. */
11749 vr4130_avoid_branch_rt_conflict (rtx insn)
11753 first = SEQ_BEGIN (insn);
11754 second = SEQ_END (insn);
11756 && NONJUMP_INSN_P (second)
11757 && GET_CODE (PATTERN (first)) == SET
11758 && GET_CODE (SET_DEST (PATTERN (first))) == PC
11759 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
11761 /* Check for the right kind of condition. */
11762 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
11763 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
11764 && REG_P (XEXP (cond, 0))
11765 && REG_P (XEXP (cond, 1))
11766 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
11767 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
11769 /* SECOND mentions the rt register but not the rs register. */
11770 rtx tmp = XEXP (cond, 0);
11771 XEXP (cond, 0) = XEXP (cond, 1);
11772 XEXP (cond, 1) = tmp;
11777 /* Implement -mvr4130-align. Go through each basic block and simulate the
11778 processor pipeline. If we find that a pair of instructions could execute
11779 in parallel, and the first of those instructions is not 8-byte aligned,
11780 insert a nop to make it aligned. */
11783 vr4130_align_insns (void)
11785 struct mips_sim state;
11786 rtx insn, subinsn, last, last2, next;
11791 /* LAST is the last instruction before INSN to have a nonzero length.
11792 LAST2 is the last such instruction before LAST. */
11796 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
11799 mips_sim_init (&state, alloca (state_size ()));
11800 for (insn = get_insns (); insn != 0; insn = next)
11802 unsigned int length;
11804 next = NEXT_INSN (insn);
11806 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
11807 This isn't really related to the alignment pass, but we do it on
11808 the fly to avoid a separate instruction walk. */
11809 vr4130_avoid_branch_rt_conflict (insn);
11811 if (USEFUL_INSN_P (insn))
11812 FOR_EACH_SUBINSN (subinsn, insn)
11814 mips_sim_wait_insn (&state, subinsn);
11816 /* If we want this instruction to issue in parallel with the
11817 previous one, make sure that the previous instruction is
11818 aligned. There are several reasons why this isn't worthwhile
11819 when the second instruction is a call:
11821 - Calls are less likely to be performance critical,
11822 - There's a good chance that the delay slot can execute
11823 in parallel with the call.
11824 - The return address would then be unaligned.
11826 In general, if we're going to insert a nop between instructions
11827 X and Y, it's better to insert it immediately after X. That
11828 way, if the nop makes Y aligned, it will also align any labels
11829 between X and Y. */
11830 if (state.insns_left != state.issue_rate
11831 && !CALL_P (subinsn))
11833 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
11835 /* SUBINSN is the first instruction in INSN and INSN is
11836 aligned. We want to align the previous instruction
11837 instead, so insert a nop between LAST2 and LAST.
11839 Note that LAST could be either a single instruction
11840 or a branch with a delay slot. In the latter case,
11841 LAST, like INSN, is already aligned, but the delay
11842 slot must have some extra delay that stops it from
11843 issuing at the same time as the branch. We therefore
11844 insert a nop before the branch in order to align its
11846 emit_insn_after (gen_nop (), last2);
11849 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
11851 /* SUBINSN is the delay slot of INSN, but INSN is
11852 currently unaligned. Insert a nop between
11853 LAST and INSN to align it. */
11854 emit_insn_after (gen_nop (), last);
11858 mips_sim_issue_insn (&state, subinsn);
11860 mips_sim_finish_insn (&state, insn);
11862 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
11863 length = get_attr_length (insn);
11866 /* If the instruction is an asm statement or multi-instruction
11867 mips.md patern, the length is only an estimate. Insert an
11868 8 byte alignment after it so that the following instructions
11869 can be handled correctly. */
11870 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
11871 && (recog_memoized (insn) < 0 || length >= 8))
11873 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
11874 next = NEXT_INSN (next);
11875 mips_sim_next_cycle (&state);
11878 else if (length & 4)
11879 aligned_p = !aligned_p;
11884 /* See whether INSN is an aligned label. */
11885 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
11891 /* This structure records that the current function has a LO_SUM
11892 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
11893 the largest offset applied to BASE by all such LO_SUMs. */
11894 struct mips_lo_sum_offset {
11896 HOST_WIDE_INT offset;
11899 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
11902 mips_hash_base (rtx base)
11904 int do_not_record_p;
11906 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
11909 /* Hash-table callbacks for mips_lo_sum_offsets. */
11912 mips_lo_sum_offset_hash (const void *entry)
11914 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
11918 mips_lo_sum_offset_eq (const void *entry, const void *value)
11920 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
11921 (const_rtx) value);
11924 /* Look up symbolic constant X in HTAB, which is a hash table of
11925 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
11926 paired with a recorded LO_SUM, otherwise record X in the table. */
11929 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
11933 struct mips_lo_sum_offset *entry;
11935 /* Split X into a base and offset. */
11936 split_const (x, &base, &offset);
11937 if (UNSPEC_ADDRESS_P (base))
11938 base = UNSPEC_ADDRESS (base);
11940 /* Look up the base in the hash table. */
11941 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
11945 entry = (struct mips_lo_sum_offset *) *slot;
11946 if (option == INSERT)
11950 entry = XNEW (struct mips_lo_sum_offset);
11951 entry->base = base;
11952 entry->offset = INTVAL (offset);
11957 if (INTVAL (offset) > entry->offset)
11958 entry->offset = INTVAL (offset);
11961 return INTVAL (offset) <= entry->offset;
11964 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
11965 Record every LO_SUM in *LOC. */
11968 mips_record_lo_sum (rtx *loc, void *data)
11970 if (GET_CODE (*loc) == LO_SUM)
11971 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
11975 /* Return true if INSN is a SET of an orphaned high-part relocation.
11976 HTAB is a hash table of mips_lo_sum_offsets that describes all the
11977 LO_SUMs in the current function. */
11980 mips_orphaned_high_part_p (htab_t htab, rtx insn)
11982 enum mips_symbol_type type;
11985 set = single_set (insn);
11988 /* Check for %his. */
11990 if (GET_CODE (x) == HIGH
11991 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
11992 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
11994 /* Check for local %gots (and %got_pages, which is redundant but OK). */
11995 if (GET_CODE (x) == UNSPEC
11996 && XINT (x, 1) == UNSPEC_LOAD_GOT
11997 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
11998 SYMBOL_CONTEXT_LEA, &type)
11999 && type == SYMBOL_GOTOFF_PAGE)
12000 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
12005 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
12006 INSN and a previous instruction, avoid it by inserting nops after
12009 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
12010 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
12011 before using the value of that register. *HILO_DELAY counts the
12012 number of instructions since the last hilo hazard (that is,
12013 the number of instructions since the last MFLO or MFHI).
12015 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
12016 for the next instruction.
12018 LO_REG is an rtx for the LO register, used in dependence checking. */
12021 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
12022 rtx *delayed_reg, rtx lo_reg)
12027 pattern = PATTERN (insn);
12029 /* Do not put the whole function in .set noreorder if it contains
12030 an asm statement. We don't know whether there will be hazards
12031 between the asm statement and the gcc-generated code. */
12032 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
12033 cfun->machine->all_noreorder_p = false;
12035 /* Ignore zero-length instructions (barriers and the like). */
12036 ninsns = get_attr_length (insn) / 4;
12040 /* Work out how many nops are needed. Note that we only care about
12041 registers that are explicitly mentioned in the instruction's pattern.
12042 It doesn't matter that calls use the argument registers or that they
12043 clobber hi and lo. */
12044 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
12045 nops = 2 - *hilo_delay;
12046 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
12051 /* Insert the nops between this instruction and the previous one.
12052 Each new nop takes us further from the last hilo hazard. */
12053 *hilo_delay += nops;
12055 emit_insn_after (gen_hazard_nop (), after);
12057 /* Set up the state for the next instruction. */
12058 *hilo_delay += ninsns;
12060 if (INSN_CODE (insn) >= 0)
12061 switch (get_attr_hazard (insn))
12071 set = single_set (insn);
12073 *delayed_reg = SET_DEST (set);
12078 /* Go through the instruction stream and insert nops where necessary.
12079 Also delete any high-part relocations whose partnering low parts
12080 are now all dead. See if the whole function can then be put into
12081 .set noreorder and .set nomacro. */
12084 mips_reorg_process_insns (void)
12086 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
12090 /* Force all instructions to be split into their final form. */
12091 split_all_insns_noflow ();
12093 /* Recalculate instruction lengths without taking nops into account. */
12094 cfun->machine->ignore_hazard_length_p = true;
12095 shorten_branches (get_insns ());
12097 cfun->machine->all_noreorder_p = true;
12099 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
12100 if (!TARGET_EXPLICIT_RELOCS)
12101 cfun->machine->all_noreorder_p = false;
12103 /* Profiled functions can't be all noreorder because the profiler
12104 support uses assembler macros. */
12106 cfun->machine->all_noreorder_p = false;
12108 /* Code compiled with -mfix-vr4120 can't be all noreorder because
12109 we rely on the assembler to work around some errata. */
12110 if (TARGET_FIX_VR4120)
12111 cfun->machine->all_noreorder_p = false;
12113 /* The same is true for -mfix-vr4130 if we might generate MFLO or
12114 MFHI instructions. Note that we avoid using MFLO and MFHI if
12115 the VR4130 MACC and DMACC instructions are available instead;
12116 see the *mfhilo_{si,di}_macc patterns. */
12117 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
12118 cfun->machine->all_noreorder_p = false;
12120 htab = htab_create (37, mips_lo_sum_offset_hash,
12121 mips_lo_sum_offset_eq, free);
12123 /* Make a first pass over the instructions, recording all the LO_SUMs. */
12124 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12125 FOR_EACH_SUBINSN (subinsn, insn)
12126 if (INSN_P (subinsn))
12127 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
12132 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
12134 /* Make a second pass over the instructions. Delete orphaned
12135 high-part relocations or turn them into NOPs. Avoid hazards
12136 by inserting NOPs. */
12137 for (insn = get_insns (); insn != 0; insn = next_insn)
12139 next_insn = NEXT_INSN (insn);
12142 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
12144 /* If we find an orphaned high-part relocation in a delay
12145 slot, it's easier to turn that instruction into a NOP than
12146 to delete it. The delay slot will be a NOP either way. */
12147 FOR_EACH_SUBINSN (subinsn, insn)
12148 if (INSN_P (subinsn))
12150 if (mips_orphaned_high_part_p (htab, subinsn))
12152 PATTERN (subinsn) = gen_nop ();
12153 INSN_CODE (subinsn) = CODE_FOR_nop;
12155 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
12156 &delayed_reg, lo_reg);
12162 /* INSN is a single instruction. Delete it if it's an
12163 orphaned high-part relocation. */
12164 if (mips_orphaned_high_part_p (htab, insn))
12165 delete_insn (insn);
12168 mips_avoid_hazard (last_insn, insn, &hilo_delay,
12169 &delayed_reg, lo_reg);
12176 htab_delete (htab);
12179 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
12184 mips16_lay_out_constants ();
12185 if (mips_base_delayed_branch)
12186 dbr_schedule (get_insns ());
12187 mips_reorg_process_insns ();
12188 if (TARGET_EXPLICIT_RELOCS && TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
12189 vr4130_align_insns ();
12192 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
12193 in order to avoid duplicating too much logic from elsewhere. */
12196 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
12197 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
12200 rtx this_rtx, temp1, temp2, insn, fnaddr;
12201 bool use_sibcall_p;
12203 /* Pretend to be a post-reload pass while generating rtl. */
12204 reload_completed = 1;
12206 /* Mark the end of the (empty) prologue. */
12207 emit_note (NOTE_INSN_PROLOGUE_END);
12209 /* Determine if we can use a sibcall to call FUNCTION directly. */
12210 fnaddr = XEXP (DECL_RTL (function), 0);
12211 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
12212 && const_call_insn_operand (fnaddr, Pmode));
12214 /* Determine if we need to load FNADDR from the GOT. */
12215 if (!use_sibcall_p)
12216 switch (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))
12218 case SYMBOL_GOT_PAGE_OFST:
12219 case SYMBOL_GOT_DISP:
12220 /* Pick a global pointer. Use a call-clobbered register if
12221 TARGET_CALL_SAVED_GP. */
12222 cfun->machine->global_pointer =
12223 TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
12224 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
12226 /* Set up the global pointer for n32 or n64 abicalls. */
12227 mips_emit_loadgp ();
12234 /* We need two temporary registers in some cases. */
12235 temp1 = gen_rtx_REG (Pmode, 2);
12236 temp2 = gen_rtx_REG (Pmode, 3);
12238 /* Find out which register contains the "this" pointer. */
12239 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
12240 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
12242 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
12244 /* Add DELTA to THIS_RTX. */
12247 rtx offset = GEN_INT (delta);
12248 if (!SMALL_OPERAND (delta))
12250 mips_emit_move (temp1, offset);
12253 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
12256 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
12257 if (vcall_offset != 0)
12261 /* Set TEMP1 to *THIS_RTX. */
12262 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
12264 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
12265 addr = mips_add_offset (temp2, temp1, vcall_offset);
12267 /* Load the offset and add it to THIS_RTX. */
12268 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
12269 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
12272 /* Jump to the target function. Use a sibcall if direct jumps are
12273 allowed, otherwise load the address into a register first. */
12276 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
12277 SIBLING_CALL_P (insn) = 1;
12281 /* This is messy. GAS treats "la $25,foo" as part of a call
12282 sequence and may allow a global "foo" to be lazily bound.
12283 The general move patterns therefore reject this combination.
12285 In this context, lazy binding would actually be OK
12286 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
12287 TARGET_CALL_SAVED_GP; see mips_load_call_address.
12288 We must therefore load the address via a temporary
12289 register if mips_dangerous_for_la25_p.
12291 If we jump to the temporary register rather than $25, the assembler
12292 can use the move insn to fill the jump's delay slot. */
12293 if (TARGET_USE_PIC_FN_ADDR_REG
12294 && !mips_dangerous_for_la25_p (fnaddr))
12295 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
12296 mips_load_call_address (temp1, fnaddr, true);
12298 if (TARGET_USE_PIC_FN_ADDR_REG
12299 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
12300 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
12301 emit_jump_insn (gen_indirect_jump (temp1));
12304 /* Run just enough of rest_of_compilation. This sequence was
12305 "borrowed" from alpha.c. */
12306 insn = get_insns ();
12307 insn_locators_alloc ();
12308 split_all_insns_noflow ();
12309 mips16_lay_out_constants ();
12310 shorten_branches (insn);
12311 final_start_function (insn, file, 1);
12312 final (insn, file, 1);
12313 final_end_function ();
12314 free_after_compilation (cfun);
12316 /* Clean up the vars set above. Note that final_end_function resets
12317 the global pointer for us. */
12318 reload_completed = 0;
12321 /* The last argument passed to mips_set_mips16_mode, or negative if the
12322 function hasn't been called yet.
12324 There are two copies of this information. One is saved and restored
12325 by the PCH process while the other is specific to this compiler
12326 invocation. The information calculated by mips_set_mips16_mode
12327 is invalid unless the two variables are the same. */
12328 static int was_mips16_p = -1;
12329 static GTY(()) int was_mips16_pch_p = -1;
12331 /* Set up the target-dependent global state so that it matches the
12332 current function's ISA mode. */
12335 mips_set_mips16_mode (int mips16_p)
12337 if (mips16_p == was_mips16_p
12338 && mips16_p == was_mips16_pch_p)
12341 /* Restore base settings of various flags. */
12342 target_flags = mips_base_target_flags;
12343 flag_schedule_insns = mips_base_schedule_insns;
12344 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
12345 flag_move_loop_invariants = mips_base_move_loop_invariants;
12346 align_loops = mips_base_align_loops;
12347 align_jumps = mips_base_align_jumps;
12348 align_functions = mips_base_align_functions;
12352 /* Switch to MIPS16 mode. */
12353 target_flags |= MASK_MIPS16;
12355 /* Don't run the scheduler before reload, since it tends to
12356 increase register pressure. */
12357 flag_schedule_insns = 0;
12359 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
12360 the whole function to be in a single section. */
12361 flag_reorder_blocks_and_partition = 0;
12363 /* Don't move loop invariants, because it tends to increase
12364 register pressure. It also introduces an extra move in cases
12365 where the constant is the first operand in a two-operand binary
12366 instruction, or when it forms a register argument to a functon
12368 flag_move_loop_invariants = 0;
12370 /* Silently disable -mexplicit-relocs since it doesn't apply
12371 to MIPS16 code. Even so, it would overly pedantic to warn
12372 about "-mips16 -mexplicit-relocs", especially given that
12373 we use a %gprel() operator. */
12374 target_flags &= ~MASK_EXPLICIT_RELOCS;
12376 /* Experiments suggest we get the best overall section-anchor
12377 results from using the range of an unextended LW or SW. Code
12378 that makes heavy use of byte or short accesses can do better
12379 with ranges of 0...31 and 0...63 respectively, but most code is
12380 sensitive to the range of LW and SW instead. */
12381 targetm.min_anchor_offset = 0;
12382 targetm.max_anchor_offset = 127;
12384 if (flag_pic || TARGET_ABICALLS)
12385 sorry ("MIPS16 PIC");
12387 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
12388 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
12392 /* Switch to normal (non-MIPS16) mode. */
12393 target_flags &= ~MASK_MIPS16;
12395 /* Provide default values for align_* for 64-bit targets. */
12398 if (align_loops == 0)
12400 if (align_jumps == 0)
12402 if (align_functions == 0)
12403 align_functions = 8;
12406 targetm.min_anchor_offset = -32768;
12407 targetm.max_anchor_offset = 32767;
12410 /* (Re)initialize MIPS target internals for new ISA. */
12411 mips_init_relocs ();
12413 if (was_mips16_p >= 0 || was_mips16_pch_p >= 0)
12414 /* Reinitialize target-dependent state. */
12417 was_mips16_p = mips16_p;
12418 was_mips16_pch_p = mips16_p;
12421 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
12422 function should use the MIPS16 ISA and switch modes accordingly. */
12425 mips_set_current_function (tree fndecl)
12427 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
12430 /* Allocate a chunk of memory for per-function machine-dependent data. */
12432 static struct machine_function *
12433 mips_init_machine_status (void)
12435 return ((struct machine_function *)
12436 ggc_alloc_cleared (sizeof (struct machine_function)));
12439 /* Return the processor associated with the given ISA level, or null
12440 if the ISA isn't valid. */
12442 static const struct mips_cpu_info *
12443 mips_cpu_info_from_isa (int isa)
12447 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
12448 if (mips_cpu_info_table[i].isa == isa)
12449 return mips_cpu_info_table + i;
12454 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
12455 with a final "000" replaced by "k". Ignore case.
12457 Note: this function is shared between GCC and GAS. */
12460 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
12462 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
12463 given++, canonical++;
12465 return ((*given == 0 && *canonical == 0)
12466 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
12469 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
12470 CPU name. We've traditionally allowed a lot of variation here.
12472 Note: this function is shared between GCC and GAS. */
12475 mips_matching_cpu_name_p (const char *canonical, const char *given)
12477 /* First see if the name matches exactly, or with a final "000"
12478 turned into "k". */
12479 if (mips_strict_matching_cpu_name_p (canonical, given))
12482 /* If not, try comparing based on numerical designation alone.
12483 See if GIVEN is an unadorned number, or 'r' followed by a number. */
12484 if (TOLOWER (*given) == 'r')
12486 if (!ISDIGIT (*given))
12489 /* Skip over some well-known prefixes in the canonical name,
12490 hoping to find a number there too. */
12491 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
12493 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
12495 else if (TOLOWER (canonical[0]) == 'r')
12498 return mips_strict_matching_cpu_name_p (canonical, given);
12501 /* Return the mips_cpu_info entry for the processor or ISA given
12502 by CPU_STRING. Return null if the string isn't recognized.
12504 A similar function exists in GAS. */
12506 static const struct mips_cpu_info *
12507 mips_parse_cpu (const char *cpu_string)
12512 /* In the past, we allowed upper-case CPU names, but it doesn't
12513 work well with the multilib machinery. */
12514 for (s = cpu_string; *s != 0; s++)
12517 warning (0, "CPU names must be lower case");
12521 /* 'from-abi' selects the most compatible architecture for the given
12522 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
12523 EABIs, we have to decide whether we're using the 32-bit or 64-bit
12525 if (strcasecmp (cpu_string, "from-abi") == 0)
12526 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
12527 : ABI_NEEDS_64BIT_REGS ? 3
12528 : (TARGET_64BIT ? 3 : 1));
12530 /* 'default' has traditionally been a no-op. Probably not very useful. */
12531 if (strcasecmp (cpu_string, "default") == 0)
12534 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
12535 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
12536 return mips_cpu_info_table + i;
12541 /* Set up globals to generate code for the ISA or processor
12542 described by INFO. */
12545 mips_set_architecture (const struct mips_cpu_info *info)
12549 mips_arch_info = info;
12550 mips_arch = info->cpu;
12551 mips_isa = info->isa;
12555 /* Likewise for tuning. */
12558 mips_set_tune (const struct mips_cpu_info *info)
12562 mips_tune_info = info;
12563 mips_tune = info->cpu;
12567 /* Implement TARGET_HANDLE_OPTION. */
12570 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
12575 if (strcmp (arg, "32") == 0)
12577 else if (strcmp (arg, "o64") == 0)
12578 mips_abi = ABI_O64;
12579 else if (strcmp (arg, "n32") == 0)
12580 mips_abi = ABI_N32;
12581 else if (strcmp (arg, "64") == 0)
12583 else if (strcmp (arg, "eabi") == 0)
12584 mips_abi = ABI_EABI;
12591 return mips_parse_cpu (arg) != 0;
12594 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
12595 return mips_isa_option_info != 0;
12597 case OPT_mno_flush_func:
12598 mips_cache_flush_func = NULL;
12601 case OPT_mcode_readable_:
12602 if (strcmp (arg, "yes") == 0)
12603 mips_code_readable = CODE_READABLE_YES;
12604 else if (strcmp (arg, "pcrel") == 0)
12605 mips_code_readable = CODE_READABLE_PCREL;
12606 else if (strcmp (arg, "no") == 0)
12607 mips_code_readable = CODE_READABLE_NO;
12617 /* Implement OVERRIDE_OPTIONS. */
12620 mips_override_options (void)
12622 int i, start, regno, mode;
12624 /* Process flags as though we were generating non-MIPS16 code. */
12625 mips_base_mips16 = TARGET_MIPS16;
12626 target_flags &= ~MASK_MIPS16;
12628 #ifdef SUBTARGET_OVERRIDE_OPTIONS
12629 SUBTARGET_OVERRIDE_OPTIONS;
12632 /* Set the small data limit. */
12633 mips_small_data_threshold = (g_switch_set
12635 : MIPS_DEFAULT_GVALUE);
12637 /* The following code determines the architecture and register size.
12638 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
12639 The GAS and GCC code should be kept in sync as much as possible. */
12641 if (mips_arch_string != 0)
12642 mips_set_architecture (mips_parse_cpu (mips_arch_string));
12644 if (mips_isa_option_info != 0)
12646 if (mips_arch_info == 0)
12647 mips_set_architecture (mips_isa_option_info);
12648 else if (mips_arch_info->isa != mips_isa_option_info->isa)
12649 error ("%<-%s%> conflicts with the other architecture options, "
12650 "which specify a %s processor",
12651 mips_isa_option_info->name,
12652 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
12655 if (mips_arch_info == 0)
12657 #ifdef MIPS_CPU_STRING_DEFAULT
12658 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
12660 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
12664 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
12665 error ("%<-march=%s%> is not compatible with the selected ABI",
12666 mips_arch_info->name);
12668 /* Optimize for mips_arch, unless -mtune selects a different processor. */
12669 if (mips_tune_string != 0)
12670 mips_set_tune (mips_parse_cpu (mips_tune_string));
12672 if (mips_tune_info == 0)
12673 mips_set_tune (mips_arch_info);
12675 if ((target_flags_explicit & MASK_64BIT) != 0)
12677 /* The user specified the size of the integer registers. Make sure
12678 it agrees with the ABI and ISA. */
12679 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
12680 error ("%<-mgp64%> used with a 32-bit processor");
12681 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
12682 error ("%<-mgp32%> used with a 64-bit ABI");
12683 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
12684 error ("%<-mgp64%> used with a 32-bit ABI");
12688 /* Infer the integer register size from the ABI and processor.
12689 Restrict ourselves to 32-bit registers if that's all the
12690 processor has, or if the ABI cannot handle 64-bit registers. */
12691 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
12692 target_flags &= ~MASK_64BIT;
12694 target_flags |= MASK_64BIT;
12697 if ((target_flags_explicit & MASK_FLOAT64) != 0)
12699 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
12700 error ("unsupported combination: %s", "-mfp64 -msingle-float");
12701 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
12702 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
12703 else if (!TARGET_64BIT && TARGET_FLOAT64)
12705 if (!ISA_HAS_MXHC1)
12706 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
12707 " the target supports the mfhc1 and mthc1 instructions");
12708 else if (mips_abi != ABI_32)
12709 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
12715 /* -msingle-float selects 32-bit float registers. Otherwise the
12716 float registers should be the same size as the integer ones. */
12717 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
12718 target_flags |= MASK_FLOAT64;
12720 target_flags &= ~MASK_FLOAT64;
12723 /* End of code shared with GAS. */
12725 /* If no -mlong* option was given, infer it from the other options. */
12726 if ((target_flags_explicit & MASK_LONG64) == 0)
12728 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
12729 target_flags |= MASK_LONG64;
12731 target_flags &= ~MASK_LONG64;
12734 if (!TARGET_OLDABI)
12735 flag_pcc_struct_return = 0;
12737 /* Decide which rtx_costs structure to use. */
12739 mips_cost = &mips_rtx_cost_optimize_size;
12741 mips_cost = &mips_rtx_cost_data[mips_tune];
12743 /* If the user hasn't specified a branch cost, use the processor's
12745 if (mips_branch_cost == 0)
12746 mips_branch_cost = mips_cost->branch_cost;
12748 /* If neither -mbranch-likely nor -mno-branch-likely was given
12749 on the command line, set MASK_BRANCHLIKELY based on the target
12750 architecture and tuning flags. Annulled delay slots are a
12751 size win, so we only consider the processor-specific tuning
12752 for !optimize_size. */
12753 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
12755 if (ISA_HAS_BRANCHLIKELY
12757 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
12758 target_flags |= MASK_BRANCHLIKELY;
12760 target_flags &= ~MASK_BRANCHLIKELY;
12762 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
12763 warning (0, "the %qs architecture does not support branch-likely"
12764 " instructions", mips_arch_info->name);
12766 /* The effect of -mabicalls isn't defined for the EABI. */
12767 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
12769 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
12770 target_flags &= ~MASK_ABICALLS;
12773 if (TARGET_ABICALLS)
12774 /* We need to set flag_pic for executables as well as DSOs
12775 because we may reference symbols that are not defined in
12776 the final executable. (MIPS does not use things like
12777 copy relocs, for example.)
12779 Also, there is a body of code that uses __PIC__ to distinguish
12780 between -mabicalls and -mno-abicalls code. */
12783 /* -mvr4130-align is a "speed over size" optimization: it usually produces
12784 faster code, but at the expense of more nops. Enable it at -O3 and
12786 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
12787 target_flags |= MASK_VR4130_ALIGN;
12789 /* Prefer a call to memcpy over inline code when optimizing for size,
12790 though see MOVE_RATIO in mips.h. */
12791 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
12792 target_flags |= MASK_MEMCPY;
12794 /* If we have a nonzero small-data limit, check that the -mgpopt
12795 setting is consistent with the other target flags. */
12796 if (mips_small_data_threshold > 0)
12800 if (!TARGET_EXPLICIT_RELOCS)
12801 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
12803 TARGET_LOCAL_SDATA = false;
12804 TARGET_EXTERN_SDATA = false;
12808 if (TARGET_VXWORKS_RTP)
12809 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
12811 if (TARGET_ABICALLS)
12812 warning (0, "cannot use small-data accesses for %qs",
12817 #ifdef MIPS_TFMODE_FORMAT
12818 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
12821 /* Make sure that the user didn't turn off paired single support when
12822 MIPS-3D support is requested. */
12824 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
12825 && !TARGET_PAIRED_SINGLE_FLOAT)
12826 error ("%<-mips3d%> requires %<-mpaired-single%>");
12828 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
12830 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
12832 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
12833 and TARGET_HARD_FLOAT_ABI are both true. */
12834 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
12835 error ("%qs must be used with %qs",
12836 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
12837 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
12839 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
12841 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
12842 warning (0, "the %qs architecture does not support paired-single"
12843 " instructions", mips_arch_info->name);
12845 /* If TARGET_DSPR2, enable MASK_DSP. */
12847 target_flags |= MASK_DSP;
12849 mips_init_print_operand_punct ();
12851 /* Set up array to map GCC register number to debug register number.
12852 Ignore the special purpose register numbers. */
12854 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12856 mips_dbx_regno[i] = INVALID_REGNUM;
12857 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
12858 mips_dwarf_regno[i] = i;
12860 mips_dwarf_regno[i] = INVALID_REGNUM;
12863 start = GP_DBX_FIRST - GP_REG_FIRST;
12864 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
12865 mips_dbx_regno[i] = i + start;
12867 start = FP_DBX_FIRST - FP_REG_FIRST;
12868 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
12869 mips_dbx_regno[i] = i + start;
12871 /* Accumulator debug registers use big-endian ordering. */
12872 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
12873 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
12874 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
12875 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
12876 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
12878 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
12879 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
12882 /* Set up mips_hard_regno_mode_ok. */
12883 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
12884 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
12885 mips_hard_regno_mode_ok[(int)mode][regno]
12886 = mips_hard_regno_mode_ok_p (regno, mode);
12888 /* Function to allocate machine-dependent function status. */
12889 init_machine_status = &mips_init_machine_status;
12891 /* Default to working around R4000 errata only if the processor
12892 was selected explicitly. */
12893 if ((target_flags_explicit & MASK_FIX_R4000) == 0
12894 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
12895 target_flags |= MASK_FIX_R4000;
12897 /* Default to working around R4400 errata only if the processor
12898 was selected explicitly. */
12899 if ((target_flags_explicit & MASK_FIX_R4400) == 0
12900 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
12901 target_flags |= MASK_FIX_R4400;
12903 /* Save base state of options. */
12904 mips_base_target_flags = target_flags;
12905 mips_base_delayed_branch = flag_delayed_branch;
12906 mips_base_schedule_insns = flag_schedule_insns;
12907 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
12908 mips_base_move_loop_invariants = flag_move_loop_invariants;
12909 mips_base_align_loops = align_loops;
12910 mips_base_align_jumps = align_jumps;
12911 mips_base_align_functions = align_functions;
12913 /* Now select the ISA mode.
12915 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
12916 MIPS16 mode afterwards if need be. */
12917 mips_set_mips16_mode (false);
12919 /* We call dbr_schedule from within mips_reorg. */
12920 flag_delayed_branch = 0;
12923 /* Swap the register information for registers I and I + 1, which
12924 currently have the wrong endianness. Note that the registers'
12925 fixedness and call-clobberedness might have been set on the
12929 mips_swap_registers (unsigned int i)
12934 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
12935 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
12937 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
12938 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
12939 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
12940 SWAP_STRING (reg_names[i], reg_names[i + 1]);
12946 /* Implement CONDITIONAL_REGISTER_USAGE. */
12949 mips_conditional_register_usage (void)
12955 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
12956 fixed_regs[regno] = call_used_regs[regno] = 1;
12958 if (!TARGET_HARD_FLOAT)
12962 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
12963 fixed_regs[regno] = call_used_regs[regno] = 1;
12964 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12965 fixed_regs[regno] = call_used_regs[regno] = 1;
12967 else if (! ISA_HAS_8CC)
12971 /* We only have a single condition-code register. We implement
12972 this by fixing all the condition-code registers and generating
12973 RTL that refers directly to ST_REG_FIRST. */
12974 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12975 fixed_regs[regno] = call_used_regs[regno] = 1;
12977 /* In MIPS16 mode, we permit the $t temporary registers to be used
12978 for reload. We prohibit the unused $s registers, since they
12979 are call-saved, and saving them via a MIPS16 register would
12980 probably waste more time than just reloading the value. */
12983 fixed_regs[18] = call_used_regs[18] = 1;
12984 fixed_regs[19] = call_used_regs[19] = 1;
12985 fixed_regs[20] = call_used_regs[20] = 1;
12986 fixed_regs[21] = call_used_regs[21] = 1;
12987 fixed_regs[22] = call_used_regs[22] = 1;
12988 fixed_regs[23] = call_used_regs[23] = 1;
12989 fixed_regs[26] = call_used_regs[26] = 1;
12990 fixed_regs[27] = call_used_regs[27] = 1;
12991 fixed_regs[30] = call_used_regs[30] = 1;
12993 /* $f20-$f23 are call-clobbered for n64. */
12994 if (mips_abi == ABI_64)
12997 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
12998 call_really_used_regs[regno] = call_used_regs[regno] = 1;
13000 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
13002 if (mips_abi == ABI_N32)
13005 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
13006 call_really_used_regs[regno] = call_used_regs[regno] = 1;
13008 /* Make sure that double-register accumulator values are correctly
13009 ordered for the current endianness. */
13010 if (TARGET_LITTLE_ENDIAN)
13012 unsigned int regno;
13014 mips_swap_registers (MD_REG_FIRST);
13015 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
13016 mips_swap_registers (regno);
13020 /* Initialize vector TARGET to VALS. */
13023 mips_expand_vector_init (rtx target, rtx vals)
13025 enum machine_mode mode;
13026 enum machine_mode inner;
13027 unsigned int i, n_elts;
13030 mode = GET_MODE (target);
13031 inner = GET_MODE_INNER (mode);
13032 n_elts = GET_MODE_NUNITS (mode);
13034 gcc_assert (VECTOR_MODE_P (mode));
13036 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
13037 for (i = 0; i < n_elts; i++)
13038 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
13039 XVECEXP (vals, 0, i));
13041 emit_move_insn (target, mem);
13044 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
13045 other registers for instructions for which it is possible. This
13046 encourages the compiler to use CMP in cases where an XOR would
13047 require some register shuffling. */
13050 mips_order_regs_for_local_alloc (void)
13054 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
13055 reg_alloc_order[i] = i;
13059 /* It really doesn't matter where we put register 0, since it is
13060 a fixed register anyhow. */
13061 reg_alloc_order[0] = 24;
13062 reg_alloc_order[24] = 0;
13066 /* Initialize the GCC target structure. */
13067 #undef TARGET_ASM_ALIGNED_HI_OP
13068 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
13069 #undef TARGET_ASM_ALIGNED_SI_OP
13070 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
13071 #undef TARGET_ASM_ALIGNED_DI_OP
13072 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
13074 #undef TARGET_ASM_FUNCTION_PROLOGUE
13075 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
13076 #undef TARGET_ASM_FUNCTION_EPILOGUE
13077 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
13078 #undef TARGET_ASM_SELECT_RTX_SECTION
13079 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
13080 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
13081 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
13083 #undef TARGET_SCHED_INIT
13084 #define TARGET_SCHED_INIT mips_sched_init
13085 #undef TARGET_SCHED_REORDER
13086 #define TARGET_SCHED_REORDER mips_sched_reorder
13087 #undef TARGET_SCHED_REORDER2
13088 #define TARGET_SCHED_REORDER2 mips_sched_reorder
13089 #undef TARGET_SCHED_VARIABLE_ISSUE
13090 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
13091 #undef TARGET_SCHED_ADJUST_COST
13092 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
13093 #undef TARGET_SCHED_ISSUE_RATE
13094 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
13095 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
13096 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
13097 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
13098 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
13099 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
13100 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
13101 mips_multipass_dfa_lookahead
13103 #undef TARGET_DEFAULT_TARGET_FLAGS
13104 #define TARGET_DEFAULT_TARGET_FLAGS \
13106 | TARGET_CPU_DEFAULT \
13107 | TARGET_ENDIAN_DEFAULT \
13108 | TARGET_FP_EXCEPTIONS_DEFAULT \
13109 | MASK_CHECK_ZERO_DIV \
13111 #undef TARGET_HANDLE_OPTION
13112 #define TARGET_HANDLE_OPTION mips_handle_option
13114 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
13115 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
13117 #undef TARGET_INSERT_ATTRIBUTES
13118 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
13119 #undef TARGET_MERGE_DECL_ATTRIBUTES
13120 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
13121 #undef TARGET_SET_CURRENT_FUNCTION
13122 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
13124 #undef TARGET_VALID_POINTER_MODE
13125 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
13126 #undef TARGET_RTX_COSTS
13127 #define TARGET_RTX_COSTS mips_rtx_costs
13128 #undef TARGET_ADDRESS_COST
13129 #define TARGET_ADDRESS_COST mips_address_cost
13131 #undef TARGET_IN_SMALL_DATA_P
13132 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
13134 #undef TARGET_MACHINE_DEPENDENT_REORG
13135 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
13137 #undef TARGET_ASM_FILE_START
13138 #define TARGET_ASM_FILE_START mips_file_start
13139 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
13140 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
13142 #undef TARGET_INIT_LIBFUNCS
13143 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
13145 #undef TARGET_BUILD_BUILTIN_VA_LIST
13146 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
13147 #undef TARGET_EXPAND_BUILTIN_VA_START
13148 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
13149 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
13150 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
13152 #undef TARGET_PROMOTE_FUNCTION_ARGS
13153 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
13154 #undef TARGET_PROMOTE_FUNCTION_RETURN
13155 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
13156 #undef TARGET_PROMOTE_PROTOTYPES
13157 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
13159 #undef TARGET_RETURN_IN_MEMORY
13160 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
13161 #undef TARGET_RETURN_IN_MSB
13162 #define TARGET_RETURN_IN_MSB mips_return_in_msb
13164 #undef TARGET_ASM_OUTPUT_MI_THUNK
13165 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
13166 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
13167 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
13169 #undef TARGET_SETUP_INCOMING_VARARGS
13170 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
13171 #undef TARGET_STRICT_ARGUMENT_NAMING
13172 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
13173 #undef TARGET_MUST_PASS_IN_STACK
13174 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
13175 #undef TARGET_PASS_BY_REFERENCE
13176 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
13177 #undef TARGET_CALLEE_COPIES
13178 #define TARGET_CALLEE_COPIES mips_callee_copies
13179 #undef TARGET_ARG_PARTIAL_BYTES
13180 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
13182 #undef TARGET_MODE_REP_EXTENDED
13183 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
13185 #undef TARGET_VECTOR_MODE_SUPPORTED_P
13186 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
13188 #undef TARGET_SCALAR_MODE_SUPPORTED_P
13189 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
13191 #undef TARGET_INIT_BUILTINS
13192 #define TARGET_INIT_BUILTINS mips_init_builtins
13193 #undef TARGET_EXPAND_BUILTIN
13194 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
13196 #undef TARGET_HAVE_TLS
13197 #define TARGET_HAVE_TLS HAVE_AS_TLS
13199 #undef TARGET_CANNOT_FORCE_CONST_MEM
13200 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
13202 #undef TARGET_ENCODE_SECTION_INFO
13203 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
13205 #undef TARGET_ATTRIBUTE_TABLE
13206 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
13207 /* All our function attributes are related to how out-of-line copies should
13208 be compiled or called. They don't in themselves prevent inlining. */
13209 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
13210 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
13212 #undef TARGET_EXTRA_LIVE_ON_ENTRY
13213 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
13215 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
13216 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
13217 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
13218 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
13220 #undef TARGET_COMP_TYPE_ATTRIBUTES
13221 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
13223 #ifdef HAVE_AS_DTPRELWORD
13224 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
13225 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
13227 #undef TARGET_DWARF_REGISTER_SPAN
13228 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
13230 struct gcc_target targetm = TARGET_INITIALIZER;
13232 #include "gt-mips.h"