1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
61 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save & restore registers.
78 Use a maximum gap of 0x100 in the mips16 case. We can then use
79 unextended instructions to save and restore registers, and to
80 allocate and deallocate the top part of the frame.
82 The value in the !mips16 case must be a SMALL_OPERAND and must
83 preserve the maximum stack alignment. */
84 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
86 /* True if INSN is a mips.md pattern or asm statement. */
87 #define USEFUL_INSN_P(INSN) \
89 && GET_CODE (PATTERN (INSN)) != USE \
90 && GET_CODE (PATTERN (INSN)) != CLOBBER \
91 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
92 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
94 /* If INSN is a delayed branch sequence, return the first instruction
95 in the sequence, otherwise return INSN itself. */
96 #define SEQ_BEGIN(INSN) \
97 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
98 ? XVECEXP (PATTERN (INSN), 0, 0) \
101 /* Likewise for the last instruction in a delayed branch sequence. */
102 #define SEQ_END(INSN) \
103 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
104 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
107 /* Execute the following loop body with SUBINSN set to each instruction
108 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
109 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
110 for ((SUBINSN) = SEQ_BEGIN (INSN); \
111 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
112 (SUBINSN) = NEXT_INSN (SUBINSN))
114 /* Classifies an address.
117 A natural register + offset address. The register satisfies
118 mips_valid_base_register_p and the offset is a const_arith_operand.
121 A LO_SUM rtx. The first operand is a valid base register and
122 the second operand is a symbolic address.
125 A signed 16-bit constant address.
128 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
129 enum mips_address_type {
136 /* Classifies the prototype of a builtin function. */
137 enum mips_function_type
139 MIPS_V2SF_FTYPE_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
142 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
143 MIPS_V2SF_FTYPE_SF_SF,
144 MIPS_INT_FTYPE_V2SF_V2SF,
145 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
146 MIPS_INT_FTYPE_SF_SF,
147 MIPS_INT_FTYPE_DF_DF,
154 /* For MIPS DSP ASE */
156 MIPS_DI_FTYPE_DI_SI_SI,
157 MIPS_DI_FTYPE_DI_V2HI_V2HI,
158 MIPS_DI_FTYPE_DI_V4QI_V4QI,
160 MIPS_SI_FTYPE_PTR_SI,
164 MIPS_SI_FTYPE_V2HI_V2HI,
166 MIPS_SI_FTYPE_V4QI_V4QI,
169 MIPS_V2HI_FTYPE_SI_SI,
170 MIPS_V2HI_FTYPE_V2HI,
171 MIPS_V2HI_FTYPE_V2HI_SI,
172 MIPS_V2HI_FTYPE_V2HI_V2HI,
173 MIPS_V2HI_FTYPE_V4QI,
174 MIPS_V2HI_FTYPE_V4QI_V2HI,
176 MIPS_V4QI_FTYPE_V2HI_V2HI,
177 MIPS_V4QI_FTYPE_V4QI_SI,
178 MIPS_V4QI_FTYPE_V4QI_V4QI,
179 MIPS_VOID_FTYPE_SI_SI,
180 MIPS_VOID_FTYPE_V2HI_V2HI,
181 MIPS_VOID_FTYPE_V4QI_V4QI,
187 /* Specifies how a builtin function should be converted into rtl. */
188 enum mips_builtin_type
190 /* The builtin corresponds directly to an .md pattern. The return
191 value is mapped to operand 0 and the arguments are mapped to
192 operands 1 and above. */
195 /* The builtin corresponds directly to an .md pattern. There is no return
196 value and the arguments are mapped to operands 0 and above. */
197 MIPS_BUILTIN_DIRECT_NO_TARGET,
199 /* The builtin corresponds to a comparison instruction followed by
200 a mips_cond_move_tf_ps pattern. The first two arguments are the
201 values to compare and the second two arguments are the vector
202 operands for the movt.ps or movf.ps instruction (in assembly order). */
206 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
207 of this instruction is the result of the comparison, which has mode
208 CCV2 or CCV4. The function arguments are mapped to operands 1 and
209 above. The function's return value is an SImode boolean that is
210 true under the following conditions:
212 MIPS_BUILTIN_CMP_ANY: one of the registers is true
213 MIPS_BUILTIN_CMP_ALL: all of the registers are true
214 MIPS_BUILTIN_CMP_LOWER: the first register is true
215 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
216 MIPS_BUILTIN_CMP_ANY,
217 MIPS_BUILTIN_CMP_ALL,
218 MIPS_BUILTIN_CMP_UPPER,
219 MIPS_BUILTIN_CMP_LOWER,
221 /* As above, but the instruction only sets a single $fcc register. */
222 MIPS_BUILTIN_CMP_SINGLE,
224 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
225 MIPS_BUILTIN_BPOSGE32
228 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
229 #define MIPS_FP_CONDITIONS(MACRO) \
247 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
248 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
249 enum mips_fp_condition {
250 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
253 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
254 #define STRINGIFY(X) #X
255 static const char *const mips_fp_conditions[] = {
256 MIPS_FP_CONDITIONS (STRINGIFY)
259 /* A function to save or store a register. The first argument is the
260 register and the second is the stack slot. */
261 typedef void (*mips_save_restore_fn) (rtx, rtx);
263 struct mips16_constant;
264 struct mips_arg_info;
265 struct mips_address_info;
266 struct mips_integer_op;
269 static enum mips_symbol_type mips_classify_symbol (rtx);
270 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
271 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
272 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
273 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
274 static bool mips_classify_address (struct mips_address_info *, rtx,
275 enum machine_mode, int);
276 static bool mips_cannot_force_const_mem (rtx);
277 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
278 static int mips_symbol_insns (enum mips_symbol_type);
279 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
280 static rtx mips_force_temporary (rtx, rtx);
281 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
282 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
283 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
284 static unsigned int mips_build_lower (struct mips_integer_op *,
285 unsigned HOST_WIDE_INT);
286 static unsigned int mips_build_integer (struct mips_integer_op *,
287 unsigned HOST_WIDE_INT);
288 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
289 static int m16_check_op (rtx, int, int, int);
290 static bool mips_rtx_costs (rtx, int, int, int *);
291 static int mips_address_cost (rtx);
292 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
293 static void mips_load_call_address (rtx, rtx, int);
294 static bool mips_function_ok_for_sibcall (tree, tree);
295 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
296 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
297 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
298 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
299 tree, int, struct mips_arg_info *);
300 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
301 static void mips_set_architecture (const struct mips_cpu_info *);
302 static void mips_set_tune (const struct mips_cpu_info *);
303 static bool mips_handle_option (size_t, const char *, int);
304 static struct machine_function *mips_init_machine_status (void);
305 static void print_operand_reloc (FILE *, rtx, const char **);
307 static void irix_output_external_libcall (rtx);
309 static void mips_file_start (void);
310 static void mips_file_end (void);
311 static bool mips_rewrite_small_data_p (rtx);
312 static int mips_small_data_pattern_1 (rtx *, void *);
313 static int mips_rewrite_small_data_1 (rtx *, void *);
314 static bool mips_function_has_gp_insn (void);
315 static unsigned int mips_global_pointer (void);
316 static bool mips_save_reg_p (unsigned int);
317 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
318 mips_save_restore_fn);
319 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
320 static void mips_output_cplocal (void);
321 static void mips_emit_loadgp (void);
322 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
323 static void mips_set_frame_expr (rtx);
324 static rtx mips_frame_set (rtx, rtx);
325 static void mips_save_reg (rtx, rtx);
326 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
327 static void mips_restore_reg (rtx, rtx);
328 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
329 HOST_WIDE_INT, tree);
330 static int symbolic_expression_p (rtx);
331 static section *mips_select_rtx_section (enum machine_mode, rtx,
332 unsigned HOST_WIDE_INT);
333 static section *mips_function_rodata_section (tree);
334 static bool mips_in_small_data_p (tree);
335 static bool mips_use_anchors_for_symbol_p (rtx);
336 static int mips_fpr_return_fields (tree, tree *);
337 static bool mips_return_in_msb (tree);
338 static rtx mips_return_fpr_pair (enum machine_mode mode,
339 enum machine_mode mode1, HOST_WIDE_INT,
340 enum machine_mode mode2, HOST_WIDE_INT);
341 static rtx mips16_gp_pseudo_reg (void);
342 static void mips16_fp_args (FILE *, int, int);
343 static void build_mips16_function_stub (FILE *);
344 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
345 static void dump_constants (struct mips16_constant *, rtx);
346 static int mips16_insn_length (rtx);
347 static int mips16_rewrite_pool_refs (rtx *, void *);
348 static void mips16_lay_out_constants (void);
349 static void mips_sim_reset (struct mips_sim *);
350 static void mips_sim_init (struct mips_sim *, state_t);
351 static void mips_sim_next_cycle (struct mips_sim *);
352 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
353 static int mips_sim_wait_regs_2 (rtx *, void *);
354 static void mips_sim_wait_regs_1 (rtx *, void *);
355 static void mips_sim_wait_regs (struct mips_sim *, rtx);
356 static void mips_sim_wait_units (struct mips_sim *, rtx);
357 static void mips_sim_wait_insn (struct mips_sim *, rtx);
358 static void mips_sim_record_set (rtx, rtx, void *);
359 static void mips_sim_issue_insn (struct mips_sim *, rtx);
360 static void mips_sim_issue_nop (struct mips_sim *);
361 static void mips_sim_finish_insn (struct mips_sim *, rtx);
362 static void vr4130_avoid_branch_rt_conflict (rtx);
363 static void vr4130_align_insns (void);
364 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
365 static void mips_avoid_hazards (void);
366 static void mips_reorg (void);
367 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
368 static bool mips_matching_cpu_name_p (const char *, const char *);
369 static const struct mips_cpu_info *mips_parse_cpu (const char *);
370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
371 static bool mips_return_in_memory (tree, tree);
372 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
373 static void mips_macc_chains_record (rtx);
374 static void mips_macc_chains_reorder (rtx *, int);
375 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
376 static bool vr4130_true_reg_dependence_p (rtx);
377 static bool vr4130_swap_insns_p (rtx, rtx);
378 static void vr4130_reorder (rtx *, int);
379 static void mips_promote_ready (rtx *, int, int);
380 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
381 static int mips_variable_issue (FILE *, int, rtx, int);
382 static int mips_adjust_cost (rtx, rtx, rtx, int);
383 static int mips_issue_rate (void);
384 static int mips_multipass_dfa_lookahead (void);
385 static void mips_init_libfuncs (void);
386 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
388 static tree mips_build_builtin_va_list (void);
389 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
390 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
392 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
394 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
396 static bool mips_valid_pointer_mode (enum machine_mode);
397 static bool mips_vector_mode_supported_p (enum machine_mode);
398 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
399 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
400 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
401 static void mips_init_builtins (void);
402 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
403 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
404 enum insn_code, enum mips_fp_condition,
406 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
407 enum insn_code, enum mips_fp_condition,
409 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
410 static void mips_encode_section_info (tree, rtx, int);
411 static void mips_extra_live_on_entry (bitmap);
412 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
414 /* Structure to be filled in by compute_frame_size with register
415 save masks, and offsets for the current function. */
417 struct mips_frame_info GTY(())
419 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
420 HOST_WIDE_INT var_size; /* # bytes that variables take up */
421 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
422 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
423 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
424 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
425 unsigned int mask; /* mask of saved gp registers */
426 unsigned int fmask; /* mask of saved fp registers */
427 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
428 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
429 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
430 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
431 bool initialized; /* true if frame size already calculated */
432 int num_gp; /* number of gp registers saved */
433 int num_fp; /* number of fp registers saved */
436 struct machine_function GTY(()) {
437 /* Pseudo-reg holding the value of $28 in a mips16 function which
438 refers to GP relative global variables. */
439 rtx mips16_gp_pseudo_rtx;
441 /* The number of extra stack bytes taken up by register varargs.
442 This area is allocated by the callee at the very top of the frame. */
445 /* Current frame information, calculated by compute_frame_size. */
446 struct mips_frame_info frame;
448 /* The register to use as the global pointer within this function. */
449 unsigned int global_pointer;
451 /* True if mips_adjust_insn_length should ignore an instruction's
453 bool ignore_hazard_length_p;
455 /* True if the whole function is suitable for .set noreorder and
457 bool all_noreorder_p;
459 /* True if the function is known to have an instruction that needs $gp. */
463 /* Information about a single argument. */
466 /* True if the argument is passed in a floating-point register, or
467 would have been if we hadn't run out of registers. */
470 /* The number of words passed in registers, rounded up. */
471 unsigned int reg_words;
473 /* For EABI, the offset of the first register from GP_ARG_FIRST or
474 FP_ARG_FIRST. For other ABIs, the offset of the first register from
475 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
476 comment for details).
478 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
480 unsigned int reg_offset;
482 /* The number of words that must be passed on the stack, rounded up. */
483 unsigned int stack_words;
485 /* The offset from the start of the stack overflow area of the argument's
486 first stack word. Only meaningful when STACK_WORDS is nonzero. */
487 unsigned int stack_offset;
491 /* Information about an address described by mips_address_type.
497 REG is the base register and OFFSET is the constant offset.
500 REG is the register that contains the high part of the address,
501 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
502 is the type of OFFSET's symbol.
505 SYMBOL_TYPE is the type of symbol being referenced. */
507 struct mips_address_info
509 enum mips_address_type type;
512 enum mips_symbol_type symbol_type;
516 /* One stage in a constant building sequence. These sequences have
520 A = A CODE[1] VALUE[1]
521 A = A CODE[2] VALUE[2]
524 where A is an accumulator, each CODE[i] is a binary rtl operation
525 and each VALUE[i] is a constant integer. */
526 struct mips_integer_op {
528 unsigned HOST_WIDE_INT value;
532 /* The largest number of operations needed to load an integer constant.
533 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
534 When the lowest bit is clear, we can try, but reject a sequence with
535 an extra SLL at the end. */
536 #define MIPS_MAX_INTEGER_OPS 7
539 /* Global variables for machine-dependent things. */
541 /* Threshold for data being put into the small data/bss area, instead
542 of the normal data area. */
543 int mips_section_threshold = -1;
545 /* Count the number of .file directives, so that .loc is up to date. */
546 int num_source_filenames = 0;
548 /* Count the number of sdb related labels are generated (to find block
549 start and end boundaries). */
550 int sdb_label_count = 0;
552 /* Next label # for each statement for Silicon Graphics IRIS systems. */
555 /* Linked list of all externals that are to be emitted when optimizing
556 for the global pointer if they haven't been declared by the end of
557 the program with an appropriate .comm or initialization. */
559 struct extern_list GTY (())
561 struct extern_list *next; /* next external */
562 const char *name; /* name of the external */
563 int size; /* size in bytes */
566 static GTY (()) struct extern_list *extern_head = 0;
568 /* Name of the file containing the current function. */
569 const char *current_function_file = "";
571 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
577 /* The next branch instruction is a branch likely, not branch normal. */
578 int mips_branch_likely;
580 /* The operands passed to the last cmpMM expander. */
583 /* The target cpu for code generation. */
584 enum processor_type mips_arch;
585 const struct mips_cpu_info *mips_arch_info;
587 /* The target cpu for optimization and scheduling. */
588 enum processor_type mips_tune;
589 const struct mips_cpu_info *mips_tune_info;
591 /* Which instruction set architecture to use. */
594 /* Which ABI to use. */
595 int mips_abi = MIPS_ABI_DEFAULT;
597 /* Cost information to use. */
598 const struct mips_rtx_cost_data *mips_cost;
600 /* Whether we are generating mips16 hard float code. In mips16 mode
601 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
602 -msoft-float was not specified by the user, which means that we
603 should arrange to call mips32 hard floating point code. */
604 int mips16_hard_float;
606 /* The architecture selected by -mipsN. */
607 static const struct mips_cpu_info *mips_isa_info;
609 /* If TRUE, we split addresses into their high and low parts in the RTL. */
610 int mips_split_addresses;
612 /* Mode used for saving/restoring general purpose registers. */
613 static enum machine_mode gpr_mode;
615 /* Array giving truth value on whether or not a given hard register
616 can support a given mode. */
617 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
619 /* List of all MIPS punctuation characters used by print_operand. */
620 char mips_print_operand_punct[256];
622 /* Map GCC register number to debugger register number. */
623 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
625 /* A copy of the original flag_delayed_branch: see override_options. */
626 static int mips_flag_delayed_branch;
628 static GTY (()) int mips_output_filename_first_time = 1;
630 /* mips_split_p[X] is true if symbols of type X can be split by
631 mips_split_symbol(). */
632 bool mips_split_p[NUM_SYMBOL_TYPES];
634 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
635 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
636 if they are matched by a special .md file pattern. */
637 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
639 /* Likewise for HIGHs. */
640 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
642 /* Map hard register number to register class */
643 const enum reg_class mips_regno_to_class[] =
645 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
646 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
647 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
648 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
649 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
650 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
651 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
652 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
653 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
654 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
655 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
657 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
658 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
659 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
660 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
661 HI_REG, LO_REG, NO_REGS, ST_REGS,
662 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
663 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
664 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
665 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
666 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
667 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
668 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
669 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
670 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
671 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
672 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
673 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
674 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
675 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
676 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
677 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
678 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
679 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
680 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
681 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
682 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
683 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
684 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
685 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
686 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
687 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
688 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
689 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
690 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
691 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
694 /* Table of machine dependent attributes. */
695 const struct attribute_spec mips_attribute_table[] =
697 { "long_call", 0, 0, false, true, true, NULL },
698 { NULL, 0, 0, false, false, false, NULL }
701 /* A table describing all the processors gcc knows about. Names are
702 matched in the order listed. The first mention of an ISA level is
703 taken as the canonical name for that ISA.
705 To ease comparison, please keep this table in the same order as
706 gas's mips_cpu_info_table[]. */
707 const struct mips_cpu_info mips_cpu_info_table[] = {
708 /* Entries for generic ISAs */
709 { "mips1", PROCESSOR_R3000, 1 },
710 { "mips2", PROCESSOR_R6000, 2 },
711 { "mips3", PROCESSOR_R4000, 3 },
712 { "mips4", PROCESSOR_R8000, 4 },
713 { "mips32", PROCESSOR_4KC, 32 },
714 { "mips32r2", PROCESSOR_M4K, 33 },
715 { "mips64", PROCESSOR_5KC, 64 },
718 { "r3000", PROCESSOR_R3000, 1 },
719 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
720 { "r3900", PROCESSOR_R3900, 1 },
723 { "r6000", PROCESSOR_R6000, 2 },
726 { "r4000", PROCESSOR_R4000, 3 },
727 { "vr4100", PROCESSOR_R4100, 3 },
728 { "vr4111", PROCESSOR_R4111, 3 },
729 { "vr4120", PROCESSOR_R4120, 3 },
730 { "vr4130", PROCESSOR_R4130, 3 },
731 { "vr4300", PROCESSOR_R4300, 3 },
732 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
733 { "r4600", PROCESSOR_R4600, 3 },
734 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
735 { "r4650", PROCESSOR_R4650, 3 },
738 { "r8000", PROCESSOR_R8000, 4 },
739 { "vr5000", PROCESSOR_R5000, 4 },
740 { "vr5400", PROCESSOR_R5400, 4 },
741 { "vr5500", PROCESSOR_R5500, 4 },
742 { "rm7000", PROCESSOR_R7000, 4 },
743 { "rm9000", PROCESSOR_R9000, 4 },
746 { "4kc", PROCESSOR_4KC, 32 },
747 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
748 { "4kp", PROCESSOR_4KP, 32 },
750 /* MIPS32 Release 2 */
751 { "m4k", PROCESSOR_M4K, 33 },
752 { "24k", PROCESSOR_24K, 33 },
753 { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
754 { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
755 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
758 { "5kc", PROCESSOR_5KC, 64 },
759 { "5kf", PROCESSOR_5KF, 64 },
760 { "20kc", PROCESSOR_20KC, 64 },
761 { "sb1", PROCESSOR_SB1, 64 },
762 { "sr71000", PROCESSOR_SR71000, 64 },
768 /* Default costs. If these are used for a processor we should look
769 up the actual costs. */
770 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
771 COSTS_N_INSNS (7), /* fp_mult_sf */ \
772 COSTS_N_INSNS (8), /* fp_mult_df */ \
773 COSTS_N_INSNS (23), /* fp_div_sf */ \
774 COSTS_N_INSNS (36), /* fp_div_df */ \
775 COSTS_N_INSNS (10), /* int_mult_si */ \
776 COSTS_N_INSNS (10), /* int_mult_di */ \
777 COSTS_N_INSNS (69), /* int_div_si */ \
778 COSTS_N_INSNS (69), /* int_div_di */ \
779 2, /* branch_cost */ \
780 4 /* memory_latency */
782 /* Need to replace these with the costs of calling the appropriate
784 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
785 COSTS_N_INSNS (256), /* fp_mult_sf */ \
786 COSTS_N_INSNS (256), /* fp_mult_df */ \
787 COSTS_N_INSNS (256), /* fp_div_sf */ \
788 COSTS_N_INSNS (256) /* fp_div_df */
790 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
793 COSTS_N_INSNS (2), /* fp_add */
794 COSTS_N_INSNS (4), /* fp_mult_sf */
795 COSTS_N_INSNS (5), /* fp_mult_df */
796 COSTS_N_INSNS (12), /* fp_div_sf */
797 COSTS_N_INSNS (19), /* fp_div_df */
798 COSTS_N_INSNS (12), /* int_mult_si */
799 COSTS_N_INSNS (12), /* int_mult_di */
800 COSTS_N_INSNS (35), /* int_div_si */
801 COSTS_N_INSNS (35), /* int_div_di */
803 4 /* memory_latency */
808 COSTS_N_INSNS (6), /* int_mult_si */
809 COSTS_N_INSNS (6), /* int_mult_di */
810 COSTS_N_INSNS (36), /* int_div_si */
811 COSTS_N_INSNS (36), /* int_div_di */
813 4 /* memory_latency */
817 COSTS_N_INSNS (36), /* int_mult_si */
818 COSTS_N_INSNS (36), /* int_mult_di */
819 COSTS_N_INSNS (37), /* int_div_si */
820 COSTS_N_INSNS (37), /* int_div_di */
822 4 /* memory_latency */
826 COSTS_N_INSNS (4), /* int_mult_si */
827 COSTS_N_INSNS (11), /* int_mult_di */
828 COSTS_N_INSNS (36), /* int_div_si */
829 COSTS_N_INSNS (68), /* int_div_di */
831 4 /* memory_latency */
834 COSTS_N_INSNS (4), /* fp_add */
835 COSTS_N_INSNS (4), /* fp_mult_sf */
836 COSTS_N_INSNS (5), /* fp_mult_df */
837 COSTS_N_INSNS (17), /* fp_div_sf */
838 COSTS_N_INSNS (32), /* fp_div_df */
839 COSTS_N_INSNS (4), /* int_mult_si */
840 COSTS_N_INSNS (11), /* int_mult_di */
841 COSTS_N_INSNS (36), /* int_div_si */
842 COSTS_N_INSNS (68), /* int_div_di */
844 4 /* memory_latency */
850 COSTS_N_INSNS (8), /* fp_add */
851 COSTS_N_INSNS (8), /* fp_mult_sf */
852 COSTS_N_INSNS (10), /* fp_mult_df */
853 COSTS_N_INSNS (34), /* fp_div_sf */
854 COSTS_N_INSNS (64), /* fp_div_df */
855 COSTS_N_INSNS (5), /* int_mult_si */
856 COSTS_N_INSNS (5), /* int_mult_di */
857 COSTS_N_INSNS (41), /* int_div_si */
858 COSTS_N_INSNS (41), /* int_div_di */
860 4 /* memory_latency */
863 COSTS_N_INSNS (4), /* fp_add */
864 COSTS_N_INSNS (4), /* fp_mult_sf */
865 COSTS_N_INSNS (5), /* fp_mult_df */
866 COSTS_N_INSNS (17), /* fp_div_sf */
867 COSTS_N_INSNS (32), /* fp_div_df */
868 COSTS_N_INSNS (5), /* int_mult_si */
869 COSTS_N_INSNS (5), /* int_mult_di */
870 COSTS_N_INSNS (41), /* int_div_si */
871 COSTS_N_INSNS (41), /* int_div_di */
873 4 /* memory_latency */
879 COSTS_N_INSNS (2), /* fp_add */
880 COSTS_N_INSNS (4), /* fp_mult_sf */
881 COSTS_N_INSNS (5), /* fp_mult_df */
882 COSTS_N_INSNS (12), /* fp_div_sf */
883 COSTS_N_INSNS (19), /* fp_div_df */
884 COSTS_N_INSNS (2), /* int_mult_si */
885 COSTS_N_INSNS (2), /* int_mult_di */
886 COSTS_N_INSNS (35), /* int_div_si */
887 COSTS_N_INSNS (35), /* int_div_di */
889 4 /* memory_latency */
892 COSTS_N_INSNS (3), /* fp_add */
893 COSTS_N_INSNS (5), /* fp_mult_sf */
894 COSTS_N_INSNS (6), /* fp_mult_df */
895 COSTS_N_INSNS (15), /* fp_div_sf */
896 COSTS_N_INSNS (16), /* fp_div_df */
897 COSTS_N_INSNS (17), /* int_mult_si */
898 COSTS_N_INSNS (17), /* int_mult_di */
899 COSTS_N_INSNS (38), /* int_div_si */
900 COSTS_N_INSNS (38), /* int_div_di */
902 6 /* memory_latency */
905 COSTS_N_INSNS (6), /* fp_add */
906 COSTS_N_INSNS (7), /* fp_mult_sf */
907 COSTS_N_INSNS (8), /* fp_mult_df */
908 COSTS_N_INSNS (23), /* fp_div_sf */
909 COSTS_N_INSNS (36), /* fp_div_df */
910 COSTS_N_INSNS (10), /* int_mult_si */
911 COSTS_N_INSNS (10), /* int_mult_di */
912 COSTS_N_INSNS (69), /* int_div_si */
913 COSTS_N_INSNS (69), /* int_div_di */
915 6 /* memory_latency */
927 /* The only costs that appear to be updated here are
928 integer multiplication. */
930 COSTS_N_INSNS (4), /* int_mult_si */
931 COSTS_N_INSNS (6), /* int_mult_di */
932 COSTS_N_INSNS (69), /* int_div_si */
933 COSTS_N_INSNS (69), /* int_div_di */
935 4 /* memory_latency */
947 COSTS_N_INSNS (6), /* fp_add */
948 COSTS_N_INSNS (4), /* fp_mult_sf */
949 COSTS_N_INSNS (5), /* fp_mult_df */
950 COSTS_N_INSNS (23), /* fp_div_sf */
951 COSTS_N_INSNS (36), /* fp_div_df */
952 COSTS_N_INSNS (5), /* int_mult_si */
953 COSTS_N_INSNS (5), /* int_mult_di */
954 COSTS_N_INSNS (36), /* int_div_si */
955 COSTS_N_INSNS (36), /* int_div_di */
957 4 /* memory_latency */
960 COSTS_N_INSNS (6), /* fp_add */
961 COSTS_N_INSNS (5), /* fp_mult_sf */
962 COSTS_N_INSNS (6), /* fp_mult_df */
963 COSTS_N_INSNS (30), /* fp_div_sf */
964 COSTS_N_INSNS (59), /* fp_div_df */
965 COSTS_N_INSNS (3), /* int_mult_si */
966 COSTS_N_INSNS (4), /* int_mult_di */
967 COSTS_N_INSNS (42), /* int_div_si */
968 COSTS_N_INSNS (74), /* int_div_di */
970 4 /* memory_latency */
973 COSTS_N_INSNS (6), /* fp_add */
974 COSTS_N_INSNS (5), /* fp_mult_sf */
975 COSTS_N_INSNS (6), /* fp_mult_df */
976 COSTS_N_INSNS (30), /* fp_div_sf */
977 COSTS_N_INSNS (59), /* fp_div_df */
978 COSTS_N_INSNS (5), /* int_mult_si */
979 COSTS_N_INSNS (9), /* int_mult_di */
980 COSTS_N_INSNS (42), /* int_div_si */
981 COSTS_N_INSNS (74), /* int_div_di */
983 4 /* memory_latency */
986 /* The only costs that are changed here are
987 integer multiplication. */
988 COSTS_N_INSNS (6), /* fp_add */
989 COSTS_N_INSNS (7), /* fp_mult_sf */
990 COSTS_N_INSNS (8), /* fp_mult_df */
991 COSTS_N_INSNS (23), /* fp_div_sf */
992 COSTS_N_INSNS (36), /* fp_div_df */
993 COSTS_N_INSNS (5), /* int_mult_si */
994 COSTS_N_INSNS (9), /* int_mult_di */
995 COSTS_N_INSNS (69), /* int_div_si */
996 COSTS_N_INSNS (69), /* int_div_di */
998 4 /* memory_latency */
1004 /* The only costs that are changed here are
1005 integer multiplication. */
1006 COSTS_N_INSNS (6), /* fp_add */
1007 COSTS_N_INSNS (7), /* fp_mult_sf */
1008 COSTS_N_INSNS (8), /* fp_mult_df */
1009 COSTS_N_INSNS (23), /* fp_div_sf */
1010 COSTS_N_INSNS (36), /* fp_div_df */
1011 COSTS_N_INSNS (3), /* int_mult_si */
1012 COSTS_N_INSNS (8), /* int_mult_di */
1013 COSTS_N_INSNS (69), /* int_div_si */
1014 COSTS_N_INSNS (69), /* int_div_di */
1015 1, /* branch_cost */
1016 4 /* memory_latency */
1019 COSTS_N_INSNS (4), /* fp_add */
1020 COSTS_N_INSNS (4), /* fp_mult_sf */
1021 COSTS_N_INSNS (4), /* fp_mult_df */
1022 COSTS_N_INSNS (24), /* fp_div_sf */
1023 COSTS_N_INSNS (32), /* fp_div_df */
1024 COSTS_N_INSNS (3), /* int_mult_si */
1025 COSTS_N_INSNS (4), /* int_mult_di */
1026 COSTS_N_INSNS (36), /* int_div_si */
1027 COSTS_N_INSNS (68), /* int_div_di */
1028 1, /* branch_cost */
1029 4 /* memory_latency */
1037 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1038 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1039 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1042 /* Initialize the GCC target structure. */
1043 #undef TARGET_ASM_ALIGNED_HI_OP
1044 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1045 #undef TARGET_ASM_ALIGNED_SI_OP
1046 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1047 #undef TARGET_ASM_ALIGNED_DI_OP
1048 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1050 #undef TARGET_ASM_FUNCTION_PROLOGUE
1051 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1052 #undef TARGET_ASM_FUNCTION_EPILOGUE
1053 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1054 #undef TARGET_ASM_SELECT_RTX_SECTION
1055 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1056 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1057 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1059 #undef TARGET_SCHED_REORDER
1060 #define TARGET_SCHED_REORDER mips_sched_reorder
1061 #undef TARGET_SCHED_VARIABLE_ISSUE
1062 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1063 #undef TARGET_SCHED_ADJUST_COST
1064 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1065 #undef TARGET_SCHED_ISSUE_RATE
1066 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1067 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1068 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1069 mips_multipass_dfa_lookahead
1071 #undef TARGET_DEFAULT_TARGET_FLAGS
1072 #define TARGET_DEFAULT_TARGET_FLAGS \
1074 | TARGET_CPU_DEFAULT \
1075 | TARGET_ENDIAN_DEFAULT \
1076 | TARGET_FP_EXCEPTIONS_DEFAULT \
1077 | MASK_CHECK_ZERO_DIV \
1079 #undef TARGET_HANDLE_OPTION
1080 #define TARGET_HANDLE_OPTION mips_handle_option
1082 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1083 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1085 #undef TARGET_VALID_POINTER_MODE
1086 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1087 #undef TARGET_RTX_COSTS
1088 #define TARGET_RTX_COSTS mips_rtx_costs
1089 #undef TARGET_ADDRESS_COST
1090 #define TARGET_ADDRESS_COST mips_address_cost
1092 #undef TARGET_IN_SMALL_DATA_P
1093 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1095 #undef TARGET_MACHINE_DEPENDENT_REORG
1096 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1098 #undef TARGET_ASM_FILE_START
1099 #undef TARGET_ASM_FILE_END
1100 #define TARGET_ASM_FILE_START mips_file_start
1101 #define TARGET_ASM_FILE_END mips_file_end
1102 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1103 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1105 #undef TARGET_INIT_LIBFUNCS
1106 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1108 #undef TARGET_BUILD_BUILTIN_VA_LIST
1109 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1110 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1111 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1113 #undef TARGET_PROMOTE_FUNCTION_ARGS
1114 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1115 #undef TARGET_PROMOTE_FUNCTION_RETURN
1116 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1117 #undef TARGET_PROMOTE_PROTOTYPES
1118 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1120 #undef TARGET_RETURN_IN_MEMORY
1121 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1122 #undef TARGET_RETURN_IN_MSB
1123 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1125 #undef TARGET_ASM_OUTPUT_MI_THUNK
1126 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1127 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1128 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1130 #undef TARGET_SETUP_INCOMING_VARARGS
1131 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1132 #undef TARGET_STRICT_ARGUMENT_NAMING
1133 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1134 #undef TARGET_MUST_PASS_IN_STACK
1135 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1136 #undef TARGET_PASS_BY_REFERENCE
1137 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1138 #undef TARGET_CALLEE_COPIES
1139 #define TARGET_CALLEE_COPIES mips_callee_copies
1140 #undef TARGET_ARG_PARTIAL_BYTES
1141 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1143 #undef TARGET_MODE_REP_EXTENDED
1144 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1146 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1147 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1149 #undef TARGET_INIT_BUILTINS
1150 #define TARGET_INIT_BUILTINS mips_init_builtins
1151 #undef TARGET_EXPAND_BUILTIN
1152 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1154 #undef TARGET_HAVE_TLS
1155 #define TARGET_HAVE_TLS HAVE_AS_TLS
1157 #undef TARGET_CANNOT_FORCE_CONST_MEM
1158 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1160 #undef TARGET_ENCODE_SECTION_INFO
1161 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1163 #undef TARGET_ATTRIBUTE_TABLE
1164 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1166 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1167 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1169 #undef TARGET_MIN_ANCHOR_OFFSET
1170 #define TARGET_MIN_ANCHOR_OFFSET -32768
1171 #undef TARGET_MAX_ANCHOR_OFFSET
1172 #define TARGET_MAX_ANCHOR_OFFSET 32767
1173 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1174 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1175 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1176 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1178 struct gcc_target targetm = TARGET_INITIALIZER;
1180 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1182 static enum mips_symbol_type
1183 mips_classify_symbol (rtx x)
1185 if (GET_CODE (x) == LABEL_REF)
1188 return SYMBOL_CONSTANT_POOL;
1189 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1190 return SYMBOL_GOT_LOCAL;
1191 return SYMBOL_GENERAL;
1194 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1196 if (SYMBOL_REF_TLS_MODEL (x))
1199 if (CONSTANT_POOL_ADDRESS_P (x))
1202 return SYMBOL_CONSTANT_POOL;
1204 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1205 return SYMBOL_SMALL_DATA;
1208 if (SYMBOL_REF_SMALL_P (x))
1209 return SYMBOL_SMALL_DATA;
1211 if (TARGET_ABICALLS)
1213 if (SYMBOL_REF_DECL (x) == 0)
1215 if (!SYMBOL_REF_LOCAL_P (x))
1216 return SYMBOL_GOT_GLOBAL;
1220 /* Don't use GOT accesses for locally-binding symbols if
1221 TARGET_ABSOLUTE_ABICALLS. Otherwise, there are three
1224 - o32 PIC (either with or without explicit relocs)
1225 - n32/n64 PIC without explicit relocs
1226 - n32/n64 PIC with explicit relocs
1228 In the first case, both local and global accesses will use an
1229 R_MIPS_GOT16 relocation. We must correctly predict which of
1230 the two semantics (local or global) the assembler and linker
1231 will apply. The choice doesn't depend on the symbol's
1232 visibility, so we deliberately ignore decl_visibility and
1235 In the second case, the assembler will not use R_MIPS_GOT16
1236 relocations, but it chooses between local and global accesses
1237 in the same way as for o32 PIC.
1239 In the third case we have more freedom since both forms of
1240 access will work for any kind of symbol. However, there seems
1241 little point in doing things differently. */
1242 if (DECL_P (SYMBOL_REF_DECL (x))
1243 && TREE_PUBLIC (SYMBOL_REF_DECL (x))
1244 && !(TARGET_ABSOLUTE_ABICALLS
1245 && targetm.binds_local_p (SYMBOL_REF_DECL (x))))
1246 return SYMBOL_GOT_GLOBAL;
1249 if (!TARGET_ABSOLUTE_ABICALLS)
1250 return SYMBOL_GOT_LOCAL;
1253 return SYMBOL_GENERAL;
1257 /* Split X into a base and a constant offset, storing them in *BASE
1258 and *OFFSET respectively. */
1261 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
1265 if (GET_CODE (x) == CONST)
1268 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1270 *offset += INTVAL (XEXP (x, 1));
1277 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1278 to the same object as SYMBOL, or to the same object_block. */
1281 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
1283 if (GET_CODE (symbol) != SYMBOL_REF)
1286 if (CONSTANT_POOL_ADDRESS_P (symbol)
1288 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
1291 if (SYMBOL_REF_DECL (symbol) != 0
1293 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
1296 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol)
1297 && SYMBOL_REF_BLOCK (symbol)
1298 && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0
1299 && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol)
1300 < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size))
1307 /* Return true if X is a symbolic constant that can be calculated in
1308 the same way as a bare symbol. If it is, store the type of the
1309 symbol in *SYMBOL_TYPE. */
1312 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1314 HOST_WIDE_INT offset;
1316 mips_split_const (x, &x, &offset);
1317 if (UNSPEC_ADDRESS_P (x))
1318 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1319 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1321 *symbol_type = mips_classify_symbol (x);
1322 if (*symbol_type == SYMBOL_TLS)
1331 /* Check whether a nonzero offset is valid for the underlying
1333 switch (*symbol_type)
1335 case SYMBOL_GENERAL:
1336 case SYMBOL_64_HIGH:
1339 /* If the target has 64-bit pointers and the object file only
1340 supports 32-bit symbols, the values of those symbols will be
1341 sign-extended. In this case we can't allow an arbitrary offset
1342 in case the 32-bit value X + OFFSET has a different sign from X. */
1343 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1344 return mips_offset_within_object_p (x, offset);
1346 /* In other cases the relocations can handle any offset. */
1349 case SYMBOL_CONSTANT_POOL:
1350 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1351 In this case, we no longer have access to the underlying constant,
1352 but the original symbol-based access was known to be valid. */
1353 if (GET_CODE (x) == LABEL_REF)
1358 case SYMBOL_SMALL_DATA:
1359 /* Make sure that the offset refers to something within the
1360 underlying object. This should guarantee that the final
1361 PC- or GP-relative offset is within the 16-bit limit. */
1362 return mips_offset_within_object_p (x, offset);
1364 case SYMBOL_GOT_LOCAL:
1365 case SYMBOL_GOTOFF_PAGE:
1366 /* The linker should provide enough local GOT entries for a
1367 16-bit offset. Larger offsets may lead to GOT overflow. */
1368 return SMALL_OPERAND (offset);
1370 case SYMBOL_GOT_GLOBAL:
1371 case SYMBOL_GOTOFF_GLOBAL:
1372 case SYMBOL_GOTOFF_CALL:
1373 case SYMBOL_GOTOFF_LOADGP:
1378 case SYMBOL_GOTTPREL:
1386 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1389 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1391 if (regno >= FIRST_PSEUDO_REGISTER)
1395 regno = reg_renumber[regno];
1398 /* These fake registers will be eliminated to either the stack or
1399 hard frame pointer, both of which are usually valid base registers.
1400 Reload deals with the cases where the eliminated form isn't valid. */
1401 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1404 /* In mips16 mode, the stack pointer can only address word and doubleword
1405 values, nothing smaller. There are two problems here:
1407 (a) Instantiating virtual registers can introduce new uses of the
1408 stack pointer. If these virtual registers are valid addresses,
1409 the stack pointer should be too.
1411 (b) Most uses of the stack pointer are not made explicit until
1412 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1413 We don't know until that stage whether we'll be eliminating to the
1414 stack pointer (which needs the restriction) or the hard frame
1415 pointer (which doesn't).
1417 All in all, it seems more consistent to only enforce this restriction
1418 during and after reload. */
1419 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1420 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1422 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1426 /* Return true if X is a valid base register for the given mode.
1427 Allow only hard registers if STRICT. */
1430 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1432 if (!strict && GET_CODE (x) == SUBREG)
1436 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1440 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1441 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1444 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1445 enum machine_mode mode)
1447 switch (symbol_type)
1449 case SYMBOL_GENERAL:
1450 return !TARGET_MIPS16;
1452 case SYMBOL_SMALL_DATA:
1455 case SYMBOL_CONSTANT_POOL:
1456 /* PC-relative addressing is only available for lw and ld. */
1457 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1459 case SYMBOL_GOT_LOCAL:
1462 case SYMBOL_GOT_GLOBAL:
1463 /* The address will have to be loaded from the GOT first. */
1466 case SYMBOL_GOTOFF_PAGE:
1467 case SYMBOL_GOTOFF_GLOBAL:
1468 case SYMBOL_GOTOFF_CALL:
1469 case SYMBOL_GOTOFF_LOADGP:
1474 case SYMBOL_GOTTPREL:
1476 case SYMBOL_64_HIGH:
1485 /* Return true if X is a valid address for machine mode MODE. If it is,
1486 fill in INFO appropriately. STRICT is true if we should only accept
1487 hard base registers. */
1490 mips_classify_address (struct mips_address_info *info, rtx x,
1491 enum machine_mode mode, int strict)
1493 switch (GET_CODE (x))
1497 info->type = ADDRESS_REG;
1499 info->offset = const0_rtx;
1500 return mips_valid_base_register_p (info->reg, mode, strict);
1503 info->type = ADDRESS_REG;
1504 info->reg = XEXP (x, 0);
1505 info->offset = XEXP (x, 1);
1506 return (mips_valid_base_register_p (info->reg, mode, strict)
1507 && const_arith_operand (info->offset, VOIDmode));
1510 info->type = ADDRESS_LO_SUM;
1511 info->reg = XEXP (x, 0);
1512 info->offset = XEXP (x, 1);
1513 return (mips_valid_base_register_p (info->reg, mode, strict)
1514 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1515 && mips_symbolic_address_p (info->symbol_type, mode)
1516 && mips_lo_relocs[info->symbol_type] != 0);
1519 /* Small-integer addresses don't occur very often, but they
1520 are legitimate if $0 is a valid base register. */
1521 info->type = ADDRESS_CONST_INT;
1522 return !TARGET_MIPS16 && SMALL_INT (x);
1527 info->type = ADDRESS_SYMBOLIC;
1528 return (mips_symbolic_constant_p (x, &info->symbol_type)
1529 && mips_symbolic_address_p (info->symbol_type, mode)
1530 && !mips_split_p[info->symbol_type]);
1537 /* Return true if X is a thread-local symbol. */
1540 mips_tls_operand_p (rtx x)
1542 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1545 /* Return true if X can not be forced into a constant pool. */
1548 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1550 return mips_tls_operand_p (*x);
1553 /* Return true if X can not be forced into a constant pool. */
1556 mips_cannot_force_const_mem (rtx x)
1559 HOST_WIDE_INT offset;
1563 /* As an optimization, reject constants that mips_legitimize_move
1566 Suppose we have a multi-instruction sequence that loads constant C
1567 into register R. If R does not get allocated a hard register, and
1568 R is used in an operand that allows both registers and memory
1569 references, reload will consider forcing C into memory and using
1570 one of the instruction's memory alternatives. Returning false
1571 here will force it to use an input reload instead. */
1572 if (GET_CODE (x) == CONST_INT)
1575 mips_split_const (x, &base, &offset);
1576 if (symbolic_operand (base, VOIDmode) && SMALL_OPERAND (offset))
1580 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1586 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1587 constant pools, but normal-mode code doesn't need to. */
1590 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1591 rtx x ATTRIBUTE_UNUSED)
1593 return !TARGET_MIPS16;
1596 /* Return the number of instructions needed to load a symbol of the
1597 given type into a register. If valid in an address, the same number
1598 of instructions are needed for loads and stores. Treat extended
1599 mips16 instructions as two instructions. */
1602 mips_symbol_insns (enum mips_symbol_type type)
1606 case SYMBOL_GENERAL:
1607 /* In mips16 code, general symbols must be fetched from the
1612 /* When using 64-bit symbols, we need 5 preparatory instructions,
1615 lui $at,%highest(symbol)
1616 daddiu $at,$at,%higher(symbol)
1618 daddiu $at,$at,%hi(symbol)
1621 The final address is then $at + %lo(symbol). With 32-bit
1622 symbols we just need a preparatory lui. */
1623 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1625 case SYMBOL_SMALL_DATA:
1628 case SYMBOL_CONSTANT_POOL:
1629 /* This case is for mips16 only. Assume we'll need an
1630 extended instruction. */
1633 case SYMBOL_GOT_LOCAL:
1634 case SYMBOL_GOT_GLOBAL:
1635 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1636 the local/global classification is accurate. See override_options
1639 The worst cases are:
1641 (1) For local symbols when generating o32 or o64 code. The assembler
1647 ...and the final address will be $at + %lo(symbol).
1649 (2) For global symbols when -mxgot. The assembler will use:
1651 lui $at,%got_hi(symbol)
1654 ...and the final address will be $at + %got_lo(symbol). */
1657 case SYMBOL_GOTOFF_PAGE:
1658 case SYMBOL_GOTOFF_GLOBAL:
1659 case SYMBOL_GOTOFF_CALL:
1660 case SYMBOL_GOTOFF_LOADGP:
1661 case SYMBOL_64_HIGH:
1667 case SYMBOL_GOTTPREL:
1669 /* Check whether the offset is a 16- or 32-bit value. */
1670 return mips_split_p[type] ? 2 : 1;
1673 /* We don't treat a bare TLS symbol as a constant. */
1679 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1682 mips_stack_address_p (rtx x, enum machine_mode mode)
1684 struct mips_address_info addr;
1686 return (mips_classify_address (&addr, x, mode, false)
1687 && addr.type == ADDRESS_REG
1688 && addr.reg == stack_pointer_rtx);
1691 /* Return true if a value at OFFSET bytes from BASE can be accessed
1692 using an unextended mips16 instruction. MODE is the mode of the
1695 Usually the offset in an unextended instruction is a 5-bit field.
1696 The offset is unsigned and shifted left once for HIs, twice
1697 for SIs, and so on. An exception is SImode accesses off the
1698 stack pointer, which have an 8-bit immediate field. */
1701 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1704 && GET_CODE (offset) == CONST_INT
1705 && INTVAL (offset) >= 0
1706 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1708 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1709 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1710 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1716 /* Return the number of instructions needed to load or store a value
1717 of mode MODE at X. Return 0 if X isn't valid for MODE.
1719 For mips16 code, count extended instructions as two instructions. */
1722 mips_address_insns (rtx x, enum machine_mode mode)
1724 struct mips_address_info addr;
1727 if (mode == BLKmode)
1728 /* BLKmode is used for single unaligned loads and stores. */
1731 /* Each word of a multi-word value will be accessed individually. */
1732 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1734 if (mips_classify_address (&addr, x, mode, false))
1739 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1743 case ADDRESS_LO_SUM:
1744 return (TARGET_MIPS16 ? factor * 2 : factor);
1746 case ADDRESS_CONST_INT:
1749 case ADDRESS_SYMBOLIC:
1750 return factor * mips_symbol_insns (addr.symbol_type);
1756 /* Likewise for constant X. */
1759 mips_const_insns (rtx x)
1761 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1762 enum mips_symbol_type symbol_type;
1763 HOST_WIDE_INT offset;
1765 switch (GET_CODE (x))
1769 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1770 || !mips_split_p[symbol_type])
1777 /* Unsigned 8-bit constants can be loaded using an unextended
1778 LI instruction. Unsigned 16-bit constants can be loaded
1779 using an extended LI. Negative constants must be loaded
1780 using LI and then negated. */
1781 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1782 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1783 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1784 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1787 return mips_build_integer (codes, INTVAL (x));
1791 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1797 /* See if we can refer to X directly. */
1798 if (mips_symbolic_constant_p (x, &symbol_type))
1799 return mips_symbol_insns (symbol_type);
1801 /* Otherwise try splitting the constant into a base and offset.
1802 16-bit offsets can be added using an extra addiu. Larger offsets
1803 must be calculated separately and then added to the base. */
1804 mips_split_const (x, &x, &offset);
1807 int n = mips_const_insns (x);
1810 if (SMALL_OPERAND (offset))
1813 return n + 1 + mips_build_integer (codes, offset);
1820 return mips_symbol_insns (mips_classify_symbol (x));
1828 /* Return the number of instructions needed for memory reference X.
1829 Count extended mips16 instructions as two instructions. */
1832 mips_fetch_insns (rtx x)
1834 gcc_assert (MEM_P (x));
1835 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1839 /* Return the number of instructions needed for an integer division. */
1842 mips_idiv_insns (void)
1847 if (TARGET_CHECK_ZERO_DIV)
1849 if (GENERATE_DIVIDE_TRAPS)
1855 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1860 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1861 returns a nonzero value if X is a legitimate address for a memory
1862 operand of the indicated MODE. STRICT is nonzero if this function
1863 is called during reload. */
1866 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1868 struct mips_address_info addr;
1870 return mips_classify_address (&addr, x, mode, strict);
1874 /* Copy VALUE to a register and return that register. If new psuedos
1875 are allowed, copy it into a new register, otherwise use DEST. */
1878 mips_force_temporary (rtx dest, rtx value)
1880 if (!no_new_pseudos)
1881 return force_reg (Pmode, value);
1884 emit_move_insn (copy_rtx (dest), value);
1890 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1891 and is used to load the high part into a register. */
1894 mips_split_symbol (rtx temp, rtx addr)
1899 high = mips16_gp_pseudo_reg ();
1901 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1902 return gen_rtx_LO_SUM (Pmode, high, addr);
1906 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1907 type SYMBOL_TYPE. */
1910 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1913 HOST_WIDE_INT offset;
1915 mips_split_const (address, &base, &offset);
1916 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1917 UNSPEC_ADDRESS_FIRST + symbol_type);
1918 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1922 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1923 high part to BASE and return the result. Just return BASE otherwise.
1924 TEMP is available as a temporary register if needed.
1926 The returned expression can be used as the first operand to a LO_SUM. */
1929 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1930 enum mips_symbol_type symbol_type)
1932 if (mips_split_p[symbol_type])
1934 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1935 addr = mips_force_temporary (temp, addr);
1936 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1942 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1943 mips_force_temporary; it is only needed when OFFSET is not a
1947 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1949 if (!SMALL_OPERAND (offset))
1954 /* Load the full offset into a register so that we can use
1955 an unextended instruction for the address itself. */
1956 high = GEN_INT (offset);
1961 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1962 high = GEN_INT (CONST_HIGH_PART (offset));
1963 offset = CONST_LOW_PART (offset);
1965 high = mips_force_temporary (temp, high);
1966 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1968 return plus_constant (reg, offset);
1971 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1972 referencing, and TYPE is the symbol type to use (either global
1973 dynamic or local dynamic). V0 is an RTX for the return value
1974 location. The entire insn sequence is returned. */
1976 static GTY(()) rtx mips_tls_symbol;
1979 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
1981 rtx insn, loc, tga, a0;
1983 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
1985 if (!mips_tls_symbol)
1986 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
1988 loc = mips_unspec_address (sym, type);
1992 emit_insn (gen_rtx_SET (Pmode, a0,
1993 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
1994 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
1995 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
1996 CONST_OR_PURE_CALL_P (insn) = 1;
1997 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
1998 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
1999 insn = get_insns ();
2006 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2007 return value will be a valid address and move_operand (either a REG
2011 mips_legitimize_tls_address (rtx loc)
2013 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2014 enum tls_model model;
2016 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2017 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2019 model = SYMBOL_REF_TLS_MODEL (loc);
2023 case TLS_MODEL_GLOBAL_DYNAMIC:
2024 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2025 dest = gen_reg_rtx (Pmode);
2026 emit_libcall_block (insn, dest, v0, loc);
2029 case TLS_MODEL_LOCAL_DYNAMIC:
2030 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2031 tmp1 = gen_reg_rtx (Pmode);
2033 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2034 share the LDM result with other LD model accesses. */
2035 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2037 emit_libcall_block (insn, tmp1, v0, eqv);
2039 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2040 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2041 mips_unspec_address (loc, SYMBOL_DTPREL));
2044 case TLS_MODEL_INITIAL_EXEC:
2045 tmp1 = gen_reg_rtx (Pmode);
2046 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2047 if (Pmode == DImode)
2049 emit_insn (gen_tls_get_tp_di (v1));
2050 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2054 emit_insn (gen_tls_get_tp_si (v1));
2055 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2057 dest = gen_reg_rtx (Pmode);
2058 emit_insn (gen_add3_insn (dest, tmp1, v1));
2061 case TLS_MODEL_LOCAL_EXEC:
2063 if (Pmode == DImode)
2064 emit_insn (gen_tls_get_tp_di (v1));
2066 emit_insn (gen_tls_get_tp_si (v1));
2068 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2069 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2070 mips_unspec_address (loc, SYMBOL_TPREL));
2080 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2081 be legitimized in a way that the generic machinery might not expect,
2082 put the new address in *XLOC and return true. MODE is the mode of
2083 the memory being accessed. */
2086 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2088 enum mips_symbol_type symbol_type;
2090 if (mips_tls_operand_p (*xloc))
2092 *xloc = mips_legitimize_tls_address (*xloc);
2096 /* See if the address can split into a high part and a LO_SUM. */
2097 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2098 && mips_symbolic_address_p (symbol_type, mode)
2099 && mips_split_p[symbol_type])
2101 *xloc = mips_split_symbol (0, *xloc);
2105 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2107 /* Handle REG + CONSTANT using mips_add_offset. */
2110 reg = XEXP (*xloc, 0);
2111 if (!mips_valid_base_register_p (reg, mode, 0))
2112 reg = copy_to_mode_reg (Pmode, reg);
2113 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2121 /* Subroutine of mips_build_integer (with the same interface).
2122 Assume that the final action in the sequence should be a left shift. */
2125 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2127 unsigned int i, shift;
2129 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2130 since signed numbers are easier to load than unsigned ones. */
2132 while ((value & 1) == 0)
2133 value /= 2, shift++;
2135 i = mips_build_integer (codes, value);
2136 codes[i].code = ASHIFT;
2137 codes[i].value = shift;
2142 /* As for mips_build_shift, but assume that the final action will be
2143 an IOR or PLUS operation. */
2146 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2148 unsigned HOST_WIDE_INT high;
2151 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2152 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2154 /* The constant is too complex to load with a simple lui/ori pair
2155 so our goal is to clear as many trailing zeros as possible.
2156 In this case, we know bit 16 is set and that the low 16 bits
2157 form a negative number. If we subtract that number from VALUE,
2158 we will clear at least the lowest 17 bits, maybe more. */
2159 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2160 codes[i].code = PLUS;
2161 codes[i].value = CONST_LOW_PART (value);
2165 i = mips_build_integer (codes, high);
2166 codes[i].code = IOR;
2167 codes[i].value = value & 0xffff;
2173 /* Fill CODES with a sequence of rtl operations to load VALUE.
2174 Return the number of operations needed. */
2177 mips_build_integer (struct mips_integer_op *codes,
2178 unsigned HOST_WIDE_INT value)
2180 if (SMALL_OPERAND (value)
2181 || SMALL_OPERAND_UNSIGNED (value)
2182 || LUI_OPERAND (value))
2184 /* The value can be loaded with a single instruction. */
2185 codes[0].code = UNKNOWN;
2186 codes[0].value = value;
2189 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2191 /* Either the constant is a simple LUI/ORI combination or its
2192 lowest bit is set. We don't want to shift in this case. */
2193 return mips_build_lower (codes, value);
2195 else if ((value & 0xffff) == 0)
2197 /* The constant will need at least three actions. The lowest
2198 16 bits are clear, so the final action will be a shift. */
2199 return mips_build_shift (codes, value);
2203 /* The final action could be a shift, add or inclusive OR.
2204 Rather than use a complex condition to select the best
2205 approach, try both mips_build_shift and mips_build_lower
2206 and pick the one that gives the shortest sequence.
2207 Note that this case is only used once per constant. */
2208 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2209 unsigned int cost, alt_cost;
2211 cost = mips_build_shift (codes, value);
2212 alt_cost = mips_build_lower (alt_codes, value);
2213 if (alt_cost < cost)
2215 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2223 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2226 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2228 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2229 enum machine_mode mode;
2230 unsigned int i, cost;
2233 mode = GET_MODE (dest);
2234 cost = mips_build_integer (codes, value);
2236 /* Apply each binary operation to X. Invariant: X is a legitimate
2237 source operand for a SET pattern. */
2238 x = GEN_INT (codes[0].value);
2239 for (i = 1; i < cost; i++)
2243 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2247 x = force_reg (mode, x);
2248 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2251 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2255 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2256 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2260 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2263 HOST_WIDE_INT offset;
2265 /* Split moves of big integers into smaller pieces. */
2266 if (splittable_const_int_operand (src, mode))
2268 mips_move_integer (dest, dest, INTVAL (src));
2272 /* Split moves of symbolic constants into high/low pairs. */
2273 if (splittable_symbolic_operand (src, mode))
2275 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2279 if (mips_tls_operand_p (src))
2281 emit_move_insn (dest, mips_legitimize_tls_address (src));
2285 /* If we have (const (plus symbol offset)), load the symbol first
2286 and then add in the offset. This is usually better than forcing
2287 the constant into memory, at least in non-mips16 code. */
2288 mips_split_const (src, &base, &offset);
2291 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2293 base = mips_force_temporary (dest, base);
2294 emit_move_insn (dest, mips_add_offset (0, base, offset));
2298 src = force_const_mem (mode, src);
2300 /* When using explicit relocs, constant pool references are sometimes
2301 not legitimate addresses. */
2302 if (!memory_operand (src, VOIDmode))
2303 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2304 emit_move_insn (dest, src);
2308 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2309 sequence that is valid. */
2312 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2314 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2316 emit_move_insn (dest, force_reg (mode, src));
2320 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2321 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2322 && REG_P (src) && MD_REG_P (REGNO (src))
2323 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2325 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2326 if (GET_MODE_SIZE (mode) <= 4)
2327 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2328 gen_rtx_REG (SImode, REGNO (src)),
2329 gen_rtx_REG (SImode, other_regno)));
2331 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2332 gen_rtx_REG (DImode, REGNO (src)),
2333 gen_rtx_REG (DImode, other_regno)));
2337 /* We need to deal with constants that would be legitimate
2338 immediate_operands but not legitimate move_operands. */
2339 if (CONSTANT_P (src) && !move_operand (src, mode))
2341 mips_legitimize_const_move (mode, dest, src);
2342 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2348 /* We need a lot of little routines to check constant values on the
2349 mips16. These are used to figure out how long the instruction will
2350 be. It would be much better to do this using constraints, but
2351 there aren't nearly enough letters available. */
2354 m16_check_op (rtx op, int low, int high, int mask)
2356 return (GET_CODE (op) == CONST_INT
2357 && INTVAL (op) >= low
2358 && INTVAL (op) <= high
2359 && (INTVAL (op) & mask) == 0);
2363 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2365 return m16_check_op (op, 0x1, 0x8, 0);
2369 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2371 return m16_check_op (op, - 0x8, 0x7, 0);
2375 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2377 return m16_check_op (op, - 0x7, 0x8, 0);
2381 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2383 return m16_check_op (op, - 0x10, 0xf, 0);
2387 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2389 return m16_check_op (op, - 0xf, 0x10, 0);
2393 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2395 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2399 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2401 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2405 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2407 return m16_check_op (op, - 0x80, 0x7f, 0);
2411 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2413 return m16_check_op (op, - 0x7f, 0x80, 0);
2417 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2419 return m16_check_op (op, 0x0, 0xff, 0);
2423 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2425 return m16_check_op (op, - 0xff, 0x0, 0);
2429 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2431 return m16_check_op (op, - 0x1, 0xfe, 0);
2435 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2437 return m16_check_op (op, 0x0, 0xff << 2, 3);
2441 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2443 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2447 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2449 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2453 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2455 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2459 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2461 enum machine_mode mode = GET_MODE (x);
2462 bool float_mode_p = FLOAT_MODE_P (mode);
2469 /* A number between 1 and 8 inclusive is efficient for a shift.
2470 Otherwise, we will need an extended instruction. */
2471 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2472 || (outer_code) == LSHIFTRT)
2474 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2477 *total = COSTS_N_INSNS (1);
2481 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2482 if ((outer_code) == XOR
2483 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2489 /* We may be able to use slt or sltu for a comparison with a
2490 signed 16 bit value. (The boundary conditions aren't quite
2491 right, but this is just a heuristic anyhow.) */
2492 if (((outer_code) == LT || (outer_code) == LE
2493 || (outer_code) == GE || (outer_code) == GT
2494 || (outer_code) == LTU || (outer_code) == LEU
2495 || (outer_code) == GEU || (outer_code) == GTU)
2496 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2502 /* Equality comparisons with 0 are cheap. */
2503 if (((outer_code) == EQ || (outer_code) == NE)
2510 /* Constants in the range 0...255 can be loaded with an unextended
2511 instruction. They are therefore as cheap as a register move.
2513 Given the choice between "li R1,0...255" and "move R1,R2"
2514 (where R2 is a known constant), it is usually better to use "li",
2515 since we do not want to unnecessarily extend the lifetime
2517 if (outer_code == SET
2519 && INTVAL (x) < 256)
2527 /* These can be used anywhere. */
2532 /* Otherwise fall through to the handling below because
2533 we'll need to construct the constant. */
2539 if (LEGITIMATE_CONSTANT_P (x))
2541 *total = COSTS_N_INSNS (1);
2546 /* The value will need to be fetched from the constant pool. */
2547 *total = CONSTANT_POOL_COST;
2553 /* If the address is legitimate, return the number of
2554 instructions it needs, otherwise use the default handling. */
2555 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2558 *total = COSTS_N_INSNS (n + 1);
2565 *total = COSTS_N_INSNS (6);
2569 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2575 if (mode == DImode && !TARGET_64BIT)
2577 *total = COSTS_N_INSNS (2);
2585 if (mode == DImode && !TARGET_64BIT)
2587 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2595 *total = COSTS_N_INSNS (1);
2597 *total = COSTS_N_INSNS (4);
2601 *total = COSTS_N_INSNS (1);
2608 *total = mips_cost->fp_add;
2612 else if (mode == DImode && !TARGET_64BIT)
2614 *total = COSTS_N_INSNS (4);
2620 if (mode == DImode && !TARGET_64BIT)
2622 *total = COSTS_N_INSNS (4);
2629 *total = mips_cost->fp_mult_sf;
2631 else if (mode == DFmode)
2632 *total = mips_cost->fp_mult_df;
2634 else if (mode == SImode)
2635 *total = mips_cost->int_mult_si;
2638 *total = mips_cost->int_mult_di;
2647 *total = mips_cost->fp_div_sf;
2649 *total = mips_cost->fp_div_df;
2658 *total = mips_cost->int_div_di;
2660 *total = mips_cost->int_div_si;
2665 /* A sign extend from SImode to DImode in 64 bit mode is often
2666 zero instructions, because the result can often be used
2667 directly by another instruction; we'll call it one. */
2668 if (TARGET_64BIT && mode == DImode
2669 && GET_MODE (XEXP (x, 0)) == SImode)
2670 *total = COSTS_N_INSNS (1);
2672 *total = COSTS_N_INSNS (2);
2676 if (TARGET_64BIT && mode == DImode
2677 && GET_MODE (XEXP (x, 0)) == SImode)
2678 *total = COSTS_N_INSNS (2);
2680 *total = COSTS_N_INSNS (1);
2684 case UNSIGNED_FLOAT:
2687 case FLOAT_TRUNCATE:
2689 *total = mips_cost->fp_add;
2697 /* Provide the costs of an addressing mode that contains ADDR.
2698 If ADDR is not a valid address, its cost is irrelevant. */
2701 mips_address_cost (rtx addr)
2703 return mips_address_insns (addr, SImode);
2706 /* Return one word of double-word value OP, taking into account the fixed
2707 endianness of certain registers. HIGH_P is true to select the high part,
2708 false to select the low part. */
2711 mips_subword (rtx op, int high_p)
2714 enum machine_mode mode;
2716 mode = GET_MODE (op);
2717 if (mode == VOIDmode)
2720 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2721 byte = UNITS_PER_WORD;
2727 if (FP_REG_P (REGNO (op)))
2728 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2729 if (ACC_HI_REG_P (REGNO (op)))
2730 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2734 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2736 return simplify_gen_subreg (word_mode, op, mode, byte);
2740 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2743 mips_split_64bit_move_p (rtx dest, rtx src)
2748 /* FP->FP moves can be done in a single instruction. */
2749 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2752 /* Check for floating-point loads and stores. They can be done using
2753 ldc1 and sdc1 on MIPS II and above. */
2756 if (FP_REG_RTX_P (dest) && MEM_P (src))
2758 if (FP_REG_RTX_P (src) && MEM_P (dest))
2765 /* Split a 64-bit move from SRC to DEST assuming that
2766 mips_split_64bit_move_p holds.
2768 Moves into and out of FPRs cause some difficulty here. Such moves
2769 will always be DFmode, since paired FPRs are not allowed to store
2770 DImode values. The most natural representation would be two separate
2771 32-bit moves, such as:
2773 (set (reg:SI $f0) (mem:SI ...))
2774 (set (reg:SI $f1) (mem:SI ...))
2776 However, the second insn is invalid because odd-numbered FPRs are
2777 not allowed to store independent values. Use the patterns load_df_low,
2778 load_df_high and store_df_high instead. */
2781 mips_split_64bit_move (rtx dest, rtx src)
2783 if (FP_REG_RTX_P (dest))
2785 /* Loading an FPR from memory or from GPRs. */
2786 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2787 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2790 else if (FP_REG_RTX_P (src))
2792 /* Storing an FPR into memory or GPRs. */
2793 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2794 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2798 /* The operation can be split into two normal moves. Decide in
2799 which order to do them. */
2802 low_dest = mips_subword (dest, 0);
2803 if (REG_P (low_dest)
2804 && reg_overlap_mentioned_p (low_dest, src))
2806 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2807 emit_move_insn (low_dest, mips_subword (src, 0));
2811 emit_move_insn (low_dest, mips_subword (src, 0));
2812 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2817 /* Return the appropriate instructions to move SRC into DEST. Assume
2818 that SRC is operand 1 and DEST is operand 0. */
2821 mips_output_move (rtx dest, rtx src)
2823 enum rtx_code dest_code, src_code;
2826 dest_code = GET_CODE (dest);
2827 src_code = GET_CODE (src);
2828 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2830 if (dbl_p && mips_split_64bit_move_p (dest, src))
2833 if ((src_code == REG && GP_REG_P (REGNO (src)))
2834 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2836 if (dest_code == REG)
2838 if (GP_REG_P (REGNO (dest)))
2839 return "move\t%0,%z1";
2841 if (MD_REG_P (REGNO (dest)))
2844 if (DSP_ACC_REG_P (REGNO (dest)))
2846 static char retval[] = "mt__\t%z1,%q0";
2847 retval[2] = reg_names[REGNO (dest)][4];
2848 retval[3] = reg_names[REGNO (dest)][5];
2852 if (FP_REG_P (REGNO (dest)))
2853 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2855 if (ALL_COP_REG_P (REGNO (dest)))
2857 static char retval[] = "dmtc_\t%z1,%0";
2859 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2860 return (dbl_p ? retval : retval + 1);
2863 if (dest_code == MEM)
2864 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2866 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2868 if (src_code == REG)
2870 if (DSP_ACC_REG_P (REGNO (src)))
2872 static char retval[] = "mf__\t%0,%q1";
2873 retval[2] = reg_names[REGNO (src)][4];
2874 retval[3] = reg_names[REGNO (src)][5];
2878 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2879 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2881 if (FP_REG_P (REGNO (src)))
2882 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2884 if (ALL_COP_REG_P (REGNO (src)))
2886 static char retval[] = "dmfc_\t%0,%1";
2888 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2889 return (dbl_p ? retval : retval + 1);
2893 if (src_code == MEM)
2894 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2896 if (src_code == CONST_INT)
2898 /* Don't use the X format, because that will give out of
2899 range numbers for 64 bit hosts and 32 bit targets. */
2901 return "li\t%0,%1\t\t\t# %X1";
2903 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2906 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2910 if (src_code == HIGH)
2911 return "lui\t%0,%h1";
2913 if (CONST_GP_P (src))
2914 return "move\t%0,%1";
2916 if (symbolic_operand (src, VOIDmode))
2917 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2919 if (src_code == REG && FP_REG_P (REGNO (src)))
2921 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2923 if (GET_MODE (dest) == V2SFmode)
2924 return "mov.ps\t%0,%1";
2926 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2929 if (dest_code == MEM)
2930 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2932 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2934 if (src_code == MEM)
2935 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2937 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2939 static char retval[] = "l_c_\t%0,%1";
2941 retval[1] = (dbl_p ? 'd' : 'w');
2942 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2945 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2947 static char retval[] = "s_c_\t%1,%0";
2949 retval[1] = (dbl_p ? 'd' : 'w');
2950 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2956 /* Restore $gp from its save slot. Valid only when using o32 or
2960 mips_restore_gp (void)
2964 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2966 address = mips_add_offset (pic_offset_table_rtx,
2967 frame_pointer_needed
2968 ? hard_frame_pointer_rtx
2969 : stack_pointer_rtx,
2970 current_function_outgoing_args_size);
2971 slot = gen_rtx_MEM (Pmode, address);
2973 emit_move_insn (pic_offset_table_rtx, slot);
2974 if (!TARGET_EXPLICIT_RELOCS)
2975 emit_insn (gen_blockage ());
2978 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2981 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2983 emit_insn (gen_rtx_SET (VOIDmode, target,
2984 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2987 /* Return true if CMP1 is a suitable second operand for relational
2988 operator CODE. See also the *sCC patterns in mips.md. */
2991 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
2997 return reg_or_0_operand (cmp1, VOIDmode);
3001 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3005 return arith_operand (cmp1, VOIDmode);
3008 return sle_operand (cmp1, VOIDmode);
3011 return sleu_operand (cmp1, VOIDmode);
3018 /* Canonicalize LE or LEU comparisons into LT comparisons when
3019 possible to avoid extra instructions or inverting the
3023 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3024 enum machine_mode mode)
3026 HOST_WIDE_INT original, plus_one;
3028 if (GET_CODE (*cmp1) != CONST_INT)
3031 original = INTVAL (*cmp1);
3032 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3037 if (original < plus_one)
3040 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3049 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3062 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3063 result in TARGET. CMP0 and TARGET are register_operands that have
3064 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3065 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3068 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3069 rtx target, rtx cmp0, rtx cmp1)
3071 /* First see if there is a MIPS instruction that can do this operation
3072 with CMP1 in its current form. If not, try to canonicalize the
3073 comparison to LT. If that fails, try doing the same for the
3074 inverse operation. If that also fails, force CMP1 into a register
3076 if (mips_relational_operand_ok_p (code, cmp1))
3077 mips_emit_binary (code, target, cmp0, cmp1);
3078 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3079 mips_emit_binary (code, target, cmp0, cmp1);
3082 enum rtx_code inv_code = reverse_condition (code);
3083 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3085 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3086 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3088 else if (invert_ptr == 0)
3090 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3091 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3092 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3096 *invert_ptr = !*invert_ptr;
3097 mips_emit_binary (inv_code, target, cmp0, cmp1);
3102 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3103 The register will have the same mode as CMP0. */
3106 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3108 if (cmp1 == const0_rtx)
3111 if (uns_arith_operand (cmp1, VOIDmode))
3112 return expand_binop (GET_MODE (cmp0), xor_optab,
3113 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3115 return expand_binop (GET_MODE (cmp0), sub_optab,
3116 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3119 /* Convert *CODE into a code that can be used in a floating-point
3120 scc instruction (c.<cond>.<fmt>). Return true if the values of
3121 the condition code registers will be inverted, with 0 indicating
3122 that the condition holds. */
3125 mips_reverse_fp_cond_p (enum rtx_code *code)
3132 *code = reverse_condition_maybe_unordered (*code);
3140 /* Convert a comparison into something that can be used in a branch or
3141 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3142 being compared and *CODE is the code used to compare them.
3144 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3145 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3146 otherwise any standard branch condition can be used. The standard branch
3149 - EQ/NE between two registers.
3150 - any comparison between a register and zero. */
3153 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3155 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3157 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3159 *op0 = cmp_operands[0];
3160 *op1 = cmp_operands[1];
3162 else if (*code == EQ || *code == NE)
3166 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3171 *op0 = cmp_operands[0];
3172 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3177 /* The comparison needs a separate scc instruction. Store the
3178 result of the scc in *OP0 and compare it against zero. */
3179 bool invert = false;
3180 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3182 mips_emit_int_relational (*code, &invert, *op0,
3183 cmp_operands[0], cmp_operands[1]);
3184 *code = (invert ? EQ : NE);
3189 enum rtx_code cmp_code;
3191 /* Floating-point tests use a separate c.cond.fmt comparison to
3192 set a condition code register. The branch or conditional move
3193 will then compare that register against zero.
3195 Set CMP_CODE to the code of the comparison instruction and
3196 *CODE to the code that the branch or move should use. */
3198 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3200 ? gen_reg_rtx (CCmode)
3201 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3203 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3207 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3208 Store the result in TARGET and return true if successful.
3210 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3213 mips_emit_scc (enum rtx_code code, rtx target)
3215 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3218 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3219 if (code == EQ || code == NE)
3221 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3222 mips_emit_binary (code, target, zie, const0_rtx);
3225 mips_emit_int_relational (code, 0, target,
3226 cmp_operands[0], cmp_operands[1]);
3230 /* Emit the common code for doing conditional branches.
3231 operand[0] is the label to jump to.
3232 The comparison operands are saved away by cmp{si,di,sf,df}. */
3235 gen_conditional_branch (rtx *operands, enum rtx_code code)
3237 rtx op0, op1, condition;
3239 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3240 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3241 emit_jump_insn (gen_condjump (condition, operands[0]));
3246 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3247 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3250 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3251 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3256 reversed_p = mips_reverse_fp_cond_p (&cond);
3257 cmp_result = gen_reg_rtx (CCV2mode);
3258 emit_insn (gen_scc_ps (cmp_result,
3259 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3261 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3264 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3268 /* Emit the common code for conditional moves. OPERANDS is the array
3269 of operands passed to the conditional move define_expand. */
3272 gen_conditional_move (rtx *operands)
3277 code = GET_CODE (operands[1]);
3278 mips_emit_compare (&code, &op0, &op1, true);
3279 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3280 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3281 gen_rtx_fmt_ee (code,
3284 operands[2], operands[3])));
3287 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3288 the conditional_trap expander. */
3291 mips_gen_conditional_trap (rtx *operands)
3294 enum rtx_code cmp_code = GET_CODE (operands[0]);
3295 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3297 /* MIPS conditional trap machine instructions don't have GT or LE
3298 flavors, so we must invert the comparison and convert to LT and
3299 GE, respectively. */
3302 case GT: cmp_code = LT; break;
3303 case LE: cmp_code = GE; break;
3304 case GTU: cmp_code = LTU; break;
3305 case LEU: cmp_code = GEU; break;
3308 if (cmp_code == GET_CODE (operands[0]))
3310 op0 = cmp_operands[0];
3311 op1 = cmp_operands[1];
3315 op0 = cmp_operands[1];
3316 op1 = cmp_operands[0];
3318 op0 = force_reg (mode, op0);
3319 if (!arith_operand (op1, mode))
3320 op1 = force_reg (mode, op1);
3322 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3323 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3327 /* Load function address ADDR into register DEST. SIBCALL_P is true
3328 if the address is needed for a sibling call. */
3331 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3333 /* If we're generating PIC, and this call is to a global function,
3334 try to allow its address to be resolved lazily. This isn't
3335 possible for NewABI sibcalls since the value of $gp on entry
3336 to the stub would be our caller's gp, not ours. */
3337 if (TARGET_EXPLICIT_RELOCS
3338 && !(sibcall_p && TARGET_NEWABI)
3339 && global_got_operand (addr, VOIDmode))
3341 rtx high, lo_sum_symbol;
3343 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3344 addr, SYMBOL_GOTOFF_CALL);
3345 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3346 if (Pmode == SImode)
3347 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3349 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3352 emit_move_insn (dest, addr);
3356 /* Expand a call or call_value instruction. RESULT is where the
3357 result will go (null for calls), ADDR is the address of the
3358 function, ARGS_SIZE is the size of the arguments and AUX is
3359 the value passed to us by mips_function_arg. SIBCALL_P is true
3360 if we are expanding a sibling call, false if we're expanding
3364 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3366 rtx orig_addr, pattern, insn;
3369 if (!call_insn_operand (addr, VOIDmode))
3371 addr = gen_reg_rtx (Pmode);
3372 mips_load_call_address (addr, orig_addr, sibcall_p);
3376 && mips16_hard_float
3377 && build_mips16_call_stub (result, addr, args_size,
3378 aux == 0 ? 0 : (int) GET_MODE (aux)))
3382 pattern = (sibcall_p
3383 ? gen_sibcall_internal (addr, args_size)
3384 : gen_call_internal (addr, args_size));
3385 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3389 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3390 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3393 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3394 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3397 pattern = (sibcall_p
3398 ? gen_sibcall_value_internal (result, addr, args_size)
3399 : gen_call_value_internal (result, addr, args_size));
3401 insn = emit_call_insn (pattern);
3403 /* Lazy-binding stubs require $gp to be valid on entry. */
3404 if (global_got_operand (orig_addr, VOIDmode))
3405 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3409 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3412 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3413 tree exp ATTRIBUTE_UNUSED)
3415 return TARGET_SIBCALLS;
3418 /* Emit code to move general operand SRC into condition-code
3419 register DEST. SCRATCH is a scratch TFmode float register.
3426 where FP1 and FP2 are single-precision float registers
3427 taken from SCRATCH. */
3430 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3434 /* Change the source to SFmode. */
3436 src = adjust_address (src, SFmode, 0);
3437 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3438 src = gen_rtx_REG (SFmode, true_regnum (src));
3440 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3441 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3443 emit_move_insn (copy_rtx (fp1), src);
3444 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3445 emit_insn (gen_slt_sf (dest, fp2, fp1));
3448 /* Emit code to change the current function's return address to
3449 ADDRESS. SCRATCH is available as a scratch register, if needed.
3450 ADDRESS and SCRATCH are both word-mode GPRs. */
3453 mips_set_return_address (rtx address, rtx scratch)
3457 compute_frame_size (get_frame_size ());
3458 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3459 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3460 cfun->machine->frame.gp_sp_offset);
3462 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3465 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3466 Assume that the areas do not overlap. */
3469 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3471 HOST_WIDE_INT offset, delta;
3472 unsigned HOST_WIDE_INT bits;
3474 enum machine_mode mode;
3477 /* Work out how many bits to move at a time. If both operands have
3478 half-word alignment, it is usually better to move in half words.
3479 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3480 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3481 Otherwise move word-sized chunks. */
3482 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3483 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3484 bits = BITS_PER_WORD / 2;
3486 bits = BITS_PER_WORD;
3488 mode = mode_for_size (bits, MODE_INT, 0);
3489 delta = bits / BITS_PER_UNIT;
3491 /* Allocate a buffer for the temporary registers. */
3492 regs = alloca (sizeof (rtx) * length / delta);
3494 /* Load as many BITS-sized chunks as possible. Use a normal load if
3495 the source has enough alignment, otherwise use left/right pairs. */
3496 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3498 regs[i] = gen_reg_rtx (mode);
3499 if (MEM_ALIGN (src) >= bits)
3500 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3503 rtx part = adjust_address (src, BLKmode, offset);
3504 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3509 /* Copy the chunks to the destination. */
3510 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3511 if (MEM_ALIGN (dest) >= bits)
3512 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3515 rtx part = adjust_address (dest, BLKmode, offset);
3516 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3520 /* Mop up any left-over bytes. */
3521 if (offset < length)
3523 src = adjust_address (src, BLKmode, offset);
3524 dest = adjust_address (dest, BLKmode, offset);
3525 move_by_pieces (dest, src, length - offset,
3526 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3530 #define MAX_MOVE_REGS 4
3531 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3534 /* Helper function for doing a loop-based block operation on memory
3535 reference MEM. Each iteration of the loop will operate on LENGTH
3538 Create a new base register for use within the loop and point it to
3539 the start of MEM. Create a new memory reference that uses this
3540 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3543 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3544 rtx *loop_reg, rtx *loop_mem)
3546 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3548 /* Although the new mem does not refer to a known location,
3549 it does keep up to LENGTH bytes of alignment. */
3550 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3551 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3555 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3556 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3557 memory regions do not overlap. */
3560 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3562 rtx label, src_reg, dest_reg, final_src;
3563 HOST_WIDE_INT leftover;
3565 leftover = length % MAX_MOVE_BYTES;
3568 /* Create registers and memory references for use within the loop. */
3569 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3570 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3572 /* Calculate the value that SRC_REG should have after the last iteration
3574 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3577 /* Emit the start of the loop. */
3578 label = gen_label_rtx ();
3581 /* Emit the loop body. */
3582 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3584 /* Move on to the next block. */
3585 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3586 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3588 /* Emit the loop condition. */
3589 if (Pmode == DImode)
3590 emit_insn (gen_cmpdi (src_reg, final_src));
3592 emit_insn (gen_cmpsi (src_reg, final_src));
3593 emit_jump_insn (gen_bne (label));
3595 /* Mop up any left-over bytes. */
3597 mips_block_move_straight (dest, src, leftover);
3600 /* Expand a movmemsi instruction. */
3603 mips_expand_block_move (rtx dest, rtx src, rtx length)
3605 if (GET_CODE (length) == CONST_INT)
3607 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3609 mips_block_move_straight (dest, src, INTVAL (length));
3614 mips_block_move_loop (dest, src, INTVAL (length));
3621 /* Argument support functions. */
3623 /* Initialize CUMULATIVE_ARGS for a function. */
3626 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3627 rtx libname ATTRIBUTE_UNUSED)
3629 static CUMULATIVE_ARGS zero_cum;
3630 tree param, next_param;
3633 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3635 /* Determine if this function has variable arguments. This is
3636 indicated by the last argument being 'void_type_mode' if there
3637 are no variable arguments. The standard MIPS calling sequence
3638 passes all arguments in the general purpose registers in this case. */
3640 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3641 param != 0; param = next_param)
3643 next_param = TREE_CHAIN (param);
3644 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3645 cum->gp_reg_found = 1;
3650 /* Fill INFO with information about a single argument. CUM is the
3651 cumulative state for earlier arguments. MODE is the mode of this
3652 argument and TYPE is its type (if known). NAMED is true if this
3653 is a named (fixed) argument rather than a variable one. */
3656 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3657 tree type, int named, struct mips_arg_info *info)
3659 bool doubleword_aligned_p;
3660 unsigned int num_bytes, num_words, max_regs;
3662 /* Work out the size of the argument. */
3663 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3664 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3666 /* Decide whether it should go in a floating-point register, assuming
3667 one is free. Later code checks for availability.
3669 The checks against UNITS_PER_FPVALUE handle the soft-float and
3670 single-float cases. */
3674 /* The EABI conventions have traditionally been defined in terms
3675 of TYPE_MODE, regardless of the actual type. */
3676 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3677 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3678 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3683 /* Only leading floating-point scalars are passed in
3684 floating-point registers. We also handle vector floats the same
3685 say, which is OK because they are not covered by the standard ABI. */
3686 info->fpr_p = (!cum->gp_reg_found
3687 && cum->arg_number < 2
3688 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3689 || VECTOR_FLOAT_TYPE_P (type))
3690 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3691 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3692 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3697 /* Scalar and complex floating-point types are passed in
3698 floating-point registers. */
3699 info->fpr_p = (named
3700 && (type == 0 || FLOAT_TYPE_P (type))
3701 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3702 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3703 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3704 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3706 /* ??? According to the ABI documentation, the real and imaginary
3707 parts of complex floats should be passed in individual registers.
3708 The real and imaginary parts of stack arguments are supposed
3709 to be contiguous and there should be an extra word of padding
3712 This has two problems. First, it makes it impossible to use a
3713 single "void *" va_list type, since register and stack arguments
3714 are passed differently. (At the time of writing, MIPSpro cannot
3715 handle complex float varargs correctly.) Second, it's unclear
3716 what should happen when there is only one register free.
3718 For now, we assume that named complex floats should go into FPRs
3719 if there are two FPRs free, otherwise they should be passed in the
3720 same way as a struct containing two floats. */
3722 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3723 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3725 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3726 info->fpr_p = false;
3736 /* See whether the argument has doubleword alignment. */
3737 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3739 /* Set REG_OFFSET to the register count we're interested in.
3740 The EABI allocates the floating-point registers separately,
3741 but the other ABIs allocate them like integer registers. */
3742 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3746 /* Advance to an even register if the argument is doubleword-aligned. */
3747 if (doubleword_aligned_p)
3748 info->reg_offset += info->reg_offset & 1;
3750 /* Work out the offset of a stack argument. */
3751 info->stack_offset = cum->stack_words;
3752 if (doubleword_aligned_p)
3753 info->stack_offset += info->stack_offset & 1;
3755 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3757 /* Partition the argument between registers and stack. */
3758 info->reg_words = MIN (num_words, max_regs);
3759 info->stack_words = num_words - info->reg_words;
3763 /* Implement FUNCTION_ARG_ADVANCE. */
3766 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3767 tree type, int named)
3769 struct mips_arg_info info;
3771 mips_arg_info (cum, mode, type, named, &info);
3774 cum->gp_reg_found = true;
3776 /* See the comment above the cumulative args structure in mips.h
3777 for an explanation of what this code does. It assumes the O32
3778 ABI, which passes at most 2 arguments in float registers. */
3779 if (cum->arg_number < 2 && info.fpr_p)
3780 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3782 if (mips_abi != ABI_EABI || !info.fpr_p)
3783 cum->num_gprs = info.reg_offset + info.reg_words;
3784 else if (info.reg_words > 0)
3785 cum->num_fprs += FP_INC;
3787 if (info.stack_words > 0)
3788 cum->stack_words = info.stack_offset + info.stack_words;
3793 /* Implement FUNCTION_ARG. */
3796 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3797 tree type, int named)
3799 struct mips_arg_info info;
3801 /* We will be called with a mode of VOIDmode after the last argument
3802 has been seen. Whatever we return will be passed to the call
3803 insn. If we need a mips16 fp_code, return a REG with the code
3804 stored as the mode. */
3805 if (mode == VOIDmode)
3807 if (TARGET_MIPS16 && cum->fp_code != 0)
3808 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3814 mips_arg_info (cum, mode, type, named, &info);
3816 /* Return straight away if the whole argument is passed on the stack. */
3817 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3821 && TREE_CODE (type) == RECORD_TYPE
3823 && TYPE_SIZE_UNIT (type)
3824 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3827 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3828 structure contains a double in its entirety, then that 64 bit
3829 chunk is passed in a floating point register. */
3832 /* First check to see if there is any such field. */
3833 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3834 if (TREE_CODE (field) == FIELD_DECL
3835 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3836 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3837 && host_integerp (bit_position (field), 0)
3838 && int_bit_position (field) % BITS_PER_WORD == 0)
3843 /* Now handle the special case by returning a PARALLEL
3844 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3845 chunks are passed in registers. */
3847 HOST_WIDE_INT bitpos;
3850 /* assign_parms checks the mode of ENTRY_PARM, so we must
3851 use the actual mode here. */
3852 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3855 field = TYPE_FIELDS (type);
3856 for (i = 0; i < info.reg_words; i++)
3860 for (; field; field = TREE_CHAIN (field))
3861 if (TREE_CODE (field) == FIELD_DECL
3862 && int_bit_position (field) >= bitpos)
3866 && int_bit_position (field) == bitpos
3867 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3868 && !TARGET_SOFT_FLOAT
3869 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3870 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3872 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3875 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3876 GEN_INT (bitpos / BITS_PER_UNIT));
3878 bitpos += BITS_PER_WORD;
3884 /* Handle the n32/n64 conventions for passing complex floating-point
3885 arguments in FPR pairs. The real part goes in the lower register
3886 and the imaginary part goes in the upper register. */
3889 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3892 enum machine_mode inner;
3895 inner = GET_MODE_INNER (mode);
3896 reg = FP_ARG_FIRST + info.reg_offset;
3897 real = gen_rtx_EXPR_LIST (VOIDmode,
3898 gen_rtx_REG (inner, reg),
3900 imag = gen_rtx_EXPR_LIST (VOIDmode,
3901 gen_rtx_REG (inner, reg + info.reg_words / 2),
3902 GEN_INT (GET_MODE_SIZE (inner)));
3903 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3907 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3908 else if (info.reg_offset == 1)
3909 /* This code handles the special o32 case in which the second word
3910 of the argument structure is passed in floating-point registers. */
3911 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3913 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3917 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3920 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3921 enum machine_mode mode, tree type, bool named)
3923 struct mips_arg_info info;
3925 mips_arg_info (cum, mode, type, named, &info);
3926 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3930 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3931 PARM_BOUNDARY bits of alignment, but will be given anything up
3932 to STACK_BOUNDARY bits if the type requires it. */
3935 function_arg_boundary (enum machine_mode mode, tree type)
3937 unsigned int alignment;
3939 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3940 if (alignment < PARM_BOUNDARY)
3941 alignment = PARM_BOUNDARY;
3942 if (alignment > STACK_BOUNDARY)
3943 alignment = STACK_BOUNDARY;
3947 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3948 upward rather than downward. In other words, return true if the
3949 first byte of the stack slot has useful data, false if the last
3953 mips_pad_arg_upward (enum machine_mode mode, tree type)
3955 /* On little-endian targets, the first byte of every stack argument
3956 is passed in the first byte of the stack slot. */
3957 if (!BYTES_BIG_ENDIAN)
3960 /* Otherwise, integral types are padded downward: the last byte of a
3961 stack argument is passed in the last byte of the stack slot. */
3963 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3964 : GET_MODE_CLASS (mode) == MODE_INT)
3967 /* Big-endian o64 pads floating-point arguments downward. */
3968 if (mips_abi == ABI_O64)
3969 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3972 /* Other types are padded upward for o32, o64, n32 and n64. */
3973 if (mips_abi != ABI_EABI)
3976 /* Arguments smaller than a stack slot are padded downward. */
3977 if (mode != BLKmode)
3978 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3980 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3984 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3985 if the least significant byte of the register has useful data. Return
3986 the opposite if the most significant byte does. */
3989 mips_pad_reg_upward (enum machine_mode mode, tree type)
3991 /* No shifting is required for floating-point arguments. */
3992 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3993 return !BYTES_BIG_ENDIAN;
3995 /* Otherwise, apply the same padding to register arguments as we do
3996 to stack arguments. */
3997 return mips_pad_arg_upward (mode, type);
4001 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4002 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4005 CUMULATIVE_ARGS local_cum;
4006 int gp_saved, fp_saved;
4008 /* The caller has advanced CUM up to, but not beyond, the last named
4009 argument. Advance a local copy of CUM past the last "real" named
4010 argument, to find out how many registers are left over. */
4013 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4015 /* Found out how many registers we need to save. */
4016 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4017 fp_saved = (EABI_FLOAT_VARARGS_P
4018 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4027 ptr = plus_constant (virtual_incoming_args_rtx,
4028 REG_PARM_STACK_SPACE (cfun->decl)
4029 - gp_saved * UNITS_PER_WORD);
4030 mem = gen_rtx_MEM (BLKmode, ptr);
4031 set_mem_alias_set (mem, get_varargs_alias_set ());
4033 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4038 /* We can't use move_block_from_reg, because it will use
4040 enum machine_mode mode;
4043 /* Set OFF to the offset from virtual_incoming_args_rtx of
4044 the first float register. The FP save area lies below
4045 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4046 off = -gp_saved * UNITS_PER_WORD;
4047 off &= ~(UNITS_PER_FPVALUE - 1);
4048 off -= fp_saved * UNITS_PER_FPREG;
4050 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4052 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4056 ptr = plus_constant (virtual_incoming_args_rtx, off);
4057 mem = gen_rtx_MEM (mode, ptr);
4058 set_mem_alias_set (mem, get_varargs_alias_set ());
4059 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4060 off += UNITS_PER_HWFPVALUE;
4064 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4065 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4066 + fp_saved * UNITS_PER_FPREG);
4069 /* Create the va_list data type.
4070 We keep 3 pointers, and two offsets.
4071 Two pointers are to the overflow area, which starts at the CFA.
4072 One of these is constant, for addressing into the GPR save area below it.
4073 The other is advanced up the stack through the overflow region.
4074 The third pointer is to the GPR save area. Since the FPR save area
4075 is just below it, we can address FPR slots off this pointer.
4076 We also keep two one-byte offsets, which are to be subtracted from the
4077 constant pointers to yield addresses in the GPR and FPR save areas.
4078 These are downcounted as float or non-float arguments are used,
4079 and when they get to zero, the argument must be obtained from the
4081 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4082 pointer is enough. It's started at the GPR save area, and is
4084 Note that the GPR save area is not constant size, due to optimization
4085 in the prologue. Hence, we can't use a design with two pointers
4086 and two offsets, although we could have designed this with two pointers
4087 and three offsets. */
4090 mips_build_builtin_va_list (void)
4092 if (EABI_FLOAT_VARARGS_P)
4094 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4097 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4099 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4101 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4103 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4105 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4106 unsigned_char_type_node);
4107 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4108 unsigned_char_type_node);
4109 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4110 warn on every user file. */
4111 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4112 array = build_array_type (unsigned_char_type_node,
4113 build_index_type (index));
4114 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4116 DECL_FIELD_CONTEXT (f_ovfl) = record;
4117 DECL_FIELD_CONTEXT (f_gtop) = record;
4118 DECL_FIELD_CONTEXT (f_ftop) = record;
4119 DECL_FIELD_CONTEXT (f_goff) = record;
4120 DECL_FIELD_CONTEXT (f_foff) = record;
4121 DECL_FIELD_CONTEXT (f_res) = record;
4123 TYPE_FIELDS (record) = f_ovfl;
4124 TREE_CHAIN (f_ovfl) = f_gtop;
4125 TREE_CHAIN (f_gtop) = f_ftop;
4126 TREE_CHAIN (f_ftop) = f_goff;
4127 TREE_CHAIN (f_goff) = f_foff;
4128 TREE_CHAIN (f_foff) = f_res;
4130 layout_type (record);
4133 else if (TARGET_IRIX && TARGET_IRIX6)
4134 /* On IRIX 6, this type is 'char *'. */
4135 return build_pointer_type (char_type_node);
4137 /* Otherwise, we use 'void *'. */
4138 return ptr_type_node;
4141 /* Implement va_start. */
4144 mips_va_start (tree valist, rtx nextarg)
4146 if (EABI_FLOAT_VARARGS_P)
4148 const CUMULATIVE_ARGS *cum;
4149 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4150 tree ovfl, gtop, ftop, goff, foff;
4152 int gpr_save_area_size;
4153 int fpr_save_area_size;
4156 cum = ¤t_function_args_info;
4158 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4160 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4162 f_ovfl = TYPE_FIELDS (va_list_type_node);
4163 f_gtop = TREE_CHAIN (f_ovfl);
4164 f_ftop = TREE_CHAIN (f_gtop);
4165 f_goff = TREE_CHAIN (f_ftop);
4166 f_foff = TREE_CHAIN (f_goff);
4168 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4170 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4172 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4174 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4176 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4179 /* Emit code to initialize OVFL, which points to the next varargs
4180 stack argument. CUM->STACK_WORDS gives the number of stack
4181 words used by named arguments. */
4182 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4183 if (cum->stack_words > 0)
4184 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t,
4185 build_int_cst (NULL_TREE,
4186 cum->stack_words * UNITS_PER_WORD));
4187 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4188 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4190 /* Emit code to initialize GTOP, the top of the GPR save area. */
4191 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4192 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4193 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4195 /* Emit code to initialize FTOP, the top of the FPR save area.
4196 This address is gpr_save_area_bytes below GTOP, rounded
4197 down to the next fp-aligned boundary. */
4198 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4199 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4200 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4202 t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t,
4203 build_int_cst (NULL_TREE, -fpr_offset));
4204 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4205 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4207 /* Emit code to initialize GOFF, the offset from GTOP of the
4208 next GPR argument. */
4209 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
4210 build_int_cst (NULL_TREE, gpr_save_area_size));
4211 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4213 /* Likewise emit code to initialize FOFF, the offset from FTOP
4214 of the next FPR argument. */
4215 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
4216 build_int_cst (NULL_TREE, fpr_save_area_size));
4217 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4221 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4222 std_expand_builtin_va_start (valist, nextarg);
4226 /* Implement va_arg. */
4229 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4231 HOST_WIDE_INT size, rsize;
4235 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4238 type = build_pointer_type (type);
4240 size = int_size_in_bytes (type);
4241 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4243 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4244 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4247 /* Not a simple merged stack. */
4249 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4250 tree ovfl, top, off, align;
4251 HOST_WIDE_INT osize;
4254 f_ovfl = TYPE_FIELDS (va_list_type_node);
4255 f_gtop = TREE_CHAIN (f_ovfl);
4256 f_ftop = TREE_CHAIN (f_gtop);
4257 f_goff = TREE_CHAIN (f_ftop);
4258 f_foff = TREE_CHAIN (f_goff);
4260 /* We maintain separate pointers and offsets for floating-point
4261 and integer arguments, but we need similar code in both cases.
4264 TOP be the top of the register save area;
4265 OFF be the offset from TOP of the next register;
4266 ADDR_RTX be the address of the argument;
4267 RSIZE be the number of bytes used to store the argument
4268 when it's in the register save area;
4269 OSIZE be the number of bytes used to store it when it's
4270 in the stack overflow area; and
4271 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4273 The code we want is:
4275 1: off &= -rsize; // round down
4278 4: addr_rtx = top - off;
4283 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4284 10: addr_rtx = ovfl + PADDING;
4288 [1] and [9] can sometimes be optimized away. */
4290 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4293 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4294 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4296 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4298 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4301 /* When floating-point registers are saved to the stack,
4302 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4303 of the float's precision. */
4304 rsize = UNITS_PER_HWFPVALUE;
4306 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4307 (= PARM_BOUNDARY bits). This can be different from RSIZE
4310 (1) On 32-bit targets when TYPE is a structure such as:
4312 struct s { float f; };
4314 Such structures are passed in paired FPRs, so RSIZE
4315 will be 8 bytes. However, the structure only takes
4316 up 4 bytes of memory, so OSIZE will only be 4.
4318 (2) In combinations such as -mgp64 -msingle-float
4319 -fshort-double. Doubles passed in registers
4320 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4321 but those passed on the stack take up
4322 UNITS_PER_WORD bytes. */
4323 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4327 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4329 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4331 if (rsize > UNITS_PER_WORD)
4333 /* [1] Emit code for: off &= -rsize. */
4334 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4335 build_int_cst (NULL_TREE, -rsize));
4336 t = build2 (MODIFY_EXPR, TREE_TYPE (off), off, t);
4337 gimplify_and_add (t, pre_p);
4342 /* [2] Emit code to branch if off == 0. */
4343 t = build2 (NE_EXPR, boolean_type_node, off,
4344 build_int_cst (TREE_TYPE (off), 0));
4345 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4347 /* [5] Emit code for: off -= rsize. We do this as a form of
4348 post-increment not available to C. Also widen for the
4349 coming pointer arithmetic. */
4350 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4351 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4352 t = fold_convert (sizetype, t);
4353 t = fold_convert (TREE_TYPE (top), t);
4355 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4356 the argument has RSIZE - SIZE bytes of leading padding. */
4357 t = build2 (MINUS_EXPR, TREE_TYPE (top), top, t);
4358 if (BYTES_BIG_ENDIAN && rsize > size)
4360 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4362 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4364 COND_EXPR_THEN (addr) = t;
4366 if (osize > UNITS_PER_WORD)
4368 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4369 u = fold_convert (TREE_TYPE (ovfl),
4370 build_int_cst (NULL_TREE, osize - 1));
4371 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4372 u = fold_convert (TREE_TYPE (ovfl),
4373 build_int_cst (NULL_TREE, -osize));
4374 t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4375 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4380 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4381 post-increment ovfl by osize. On big-endian machines,
4382 the argument has OSIZE - SIZE bytes of leading padding. */
4383 u = fold_convert (TREE_TYPE (ovfl),
4384 build_int_cst (NULL_TREE, osize));
4385 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4386 if (BYTES_BIG_ENDIAN && osize > size)
4388 u = fold_convert (TREE_TYPE (t),
4389 build_int_cst (NULL_TREE, osize - size));
4390 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4393 /* String [9] and [10,11] together. */
4395 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4396 COND_EXPR_ELSE (addr) = t;
4398 addr = fold_convert (build_pointer_type (type), addr);
4399 addr = build_va_arg_indirect_ref (addr);
4403 addr = build_va_arg_indirect_ref (addr);
4408 /* Return true if it is possible to use left/right accesses for a
4409 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4410 returning true, update *OP, *LEFT and *RIGHT as follows:
4412 *OP is a BLKmode reference to the whole field.
4414 *LEFT is a QImode reference to the first byte if big endian or
4415 the last byte if little endian. This address can be used in the
4416 left-side instructions (lwl, swl, ldl, sdl).
4418 *RIGHT is a QImode reference to the opposite end of the field and
4419 can be used in the patterning right-side instruction. */
4422 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4423 rtx *left, rtx *right)
4427 /* Check that the operand really is a MEM. Not all the extv and
4428 extzv predicates are checked. */
4432 /* Check that the size is valid. */
4433 if (width != 32 && (!TARGET_64BIT || width != 64))
4436 /* We can only access byte-aligned values. Since we are always passed
4437 a reference to the first byte of the field, it is not necessary to
4438 do anything with BITPOS after this check. */
4439 if (bitpos % BITS_PER_UNIT != 0)
4442 /* Reject aligned bitfields: we want to use a normal load or store
4443 instead of a left/right pair. */
4444 if (MEM_ALIGN (*op) >= width)
4447 /* Adjust *OP to refer to the whole field. This also has the effect
4448 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4449 *op = adjust_address (*op, BLKmode, 0);
4450 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4452 /* Get references to both ends of the field. We deliberately don't
4453 use the original QImode *OP for FIRST since the new BLKmode one
4454 might have a simpler address. */
4455 first = adjust_address (*op, QImode, 0);
4456 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4458 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4459 be the upper word and RIGHT the lower word. */
4460 if (TARGET_BIG_ENDIAN)
4461 *left = first, *right = last;
4463 *left = last, *right = first;
4469 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4470 Return true on success. We only handle cases where zero_extract is
4471 equivalent to sign_extract. */
4474 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4476 rtx left, right, temp;
4478 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4479 paradoxical word_mode subreg. This is the only case in which
4480 we allow the destination to be larger than the source. */
4481 if (GET_CODE (dest) == SUBREG
4482 && GET_MODE (dest) == DImode
4483 && SUBREG_BYTE (dest) == 0
4484 && GET_MODE (SUBREG_REG (dest)) == SImode)
4485 dest = SUBREG_REG (dest);
4487 /* After the above adjustment, the destination must be the same
4488 width as the source. */
4489 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4492 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4495 temp = gen_reg_rtx (GET_MODE (dest));
4496 if (GET_MODE (dest) == DImode)
4498 emit_insn (gen_mov_ldl (temp, src, left));
4499 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4503 emit_insn (gen_mov_lwl (temp, src, left));
4504 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4510 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4514 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4518 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4521 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4523 if (GET_MODE (src) == DImode)
4525 emit_insn (gen_mov_sdl (dest, src, left));
4526 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4530 emit_insn (gen_mov_swl (dest, src, left));
4531 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4536 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4537 source of an "ext" instruction or the destination of an "ins"
4538 instruction. OP must be a register operand and the following
4539 conditions must hold:
4541 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4542 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4543 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4545 Also reject lengths equal to a word as they are better handled
4546 by the move patterns. */
4549 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4551 HOST_WIDE_INT len, pos;
4553 if (!ISA_HAS_EXT_INS
4554 || !register_operand (op, VOIDmode)
4555 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4558 len = INTVAL (size);
4559 pos = INTVAL (position);
4561 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4562 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4568 /* Set up globals to generate code for the ISA or processor
4569 described by INFO. */
4572 mips_set_architecture (const struct mips_cpu_info *info)
4576 mips_arch_info = info;
4577 mips_arch = info->cpu;
4578 mips_isa = info->isa;
4583 /* Likewise for tuning. */
4586 mips_set_tune (const struct mips_cpu_info *info)
4590 mips_tune_info = info;
4591 mips_tune = info->cpu;
4595 /* Implement TARGET_HANDLE_OPTION. */
4598 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4603 if (strcmp (arg, "32") == 0)
4605 else if (strcmp (arg, "o64") == 0)
4607 else if (strcmp (arg, "n32") == 0)
4609 else if (strcmp (arg, "64") == 0)
4611 else if (strcmp (arg, "eabi") == 0)
4612 mips_abi = ABI_EABI;
4619 return mips_parse_cpu (arg) != 0;
4622 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4623 return mips_isa_info != 0;
4625 case OPT_mno_flush_func:
4626 mips_cache_flush_func = NULL;
4634 /* Set up the threshold for data to go into the small data area, instead
4635 of the normal data area, and detect any conflicts in the switches. */
4638 override_options (void)
4640 int i, start, regno;
4641 enum machine_mode mode;
4643 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4645 /* The following code determines the architecture and register size.
4646 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4647 The GAS and GCC code should be kept in sync as much as possible. */
4649 if (mips_arch_string != 0)
4650 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4652 if (mips_isa_info != 0)
4654 if (mips_arch_info == 0)
4655 mips_set_architecture (mips_isa_info);
4656 else if (mips_arch_info->isa != mips_isa_info->isa)
4657 error ("-%s conflicts with the other architecture options, "
4658 "which specify a %s processor",
4659 mips_isa_info->name,
4660 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4663 if (mips_arch_info == 0)
4665 #ifdef MIPS_CPU_STRING_DEFAULT
4666 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4668 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4672 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4673 error ("-march=%s is not compatible with the selected ABI",
4674 mips_arch_info->name);
4676 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4677 if (mips_tune_string != 0)
4678 mips_set_tune (mips_parse_cpu (mips_tune_string));
4680 if (mips_tune_info == 0)
4681 mips_set_tune (mips_arch_info);
4683 /* Set cost structure for the processor. */
4684 mips_cost = &mips_rtx_cost_data[mips_tune];
4686 if ((target_flags_explicit & MASK_64BIT) != 0)
4688 /* The user specified the size of the integer registers. Make sure
4689 it agrees with the ABI and ISA. */
4690 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4691 error ("-mgp64 used with a 32-bit processor");
4692 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4693 error ("-mgp32 used with a 64-bit ABI");
4694 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4695 error ("-mgp64 used with a 32-bit ABI");
4699 /* Infer the integer register size from the ABI and processor.
4700 Restrict ourselves to 32-bit registers if that's all the
4701 processor has, or if the ABI cannot handle 64-bit registers. */
4702 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4703 target_flags &= ~MASK_64BIT;
4705 target_flags |= MASK_64BIT;
4708 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4710 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4711 only one right answer here. */
4712 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4713 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4714 else if (!TARGET_64BIT && TARGET_FLOAT64)
4715 error ("unsupported combination: %s", "-mgp32 -mfp64");
4716 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4717 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4721 /* -msingle-float selects 32-bit float registers. Otherwise the
4722 float registers should be the same size as the integer ones. */
4723 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4724 target_flags |= MASK_FLOAT64;
4726 target_flags &= ~MASK_FLOAT64;
4729 /* End of code shared with GAS. */
4731 if ((target_flags_explicit & MASK_LONG64) == 0)
4733 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4734 target_flags |= MASK_LONG64;
4736 target_flags &= ~MASK_LONG64;
4739 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4740 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4742 /* For some configurations, it is useful to have -march control
4743 the default setting of MASK_SOFT_FLOAT. */
4744 switch ((int) mips_arch)
4746 case PROCESSOR_R4100:
4747 case PROCESSOR_R4111:
4748 case PROCESSOR_R4120:
4749 case PROCESSOR_R4130:
4750 target_flags |= MASK_SOFT_FLOAT;
4754 target_flags &= ~MASK_SOFT_FLOAT;
4760 flag_pcc_struct_return = 0;
4762 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4764 /* If neither -mbranch-likely nor -mno-branch-likely was given
4765 on the command line, set MASK_BRANCHLIKELY based on the target
4768 By default, we enable use of Branch Likely instructions on
4769 all architectures which support them with the following
4770 exceptions: when creating MIPS32 or MIPS64 code, and when
4771 tuning for architectures where their use tends to hurt
4774 The MIPS32 and MIPS64 architecture specifications say "Software
4775 is strongly encouraged to avoid use of Branch Likely
4776 instructions, as they will be removed from a future revision
4777 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4778 issue those instructions unless instructed to do so by
4780 if (ISA_HAS_BRANCHLIKELY
4781 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4782 && !(TUNE_MIPS5500 || TUNE_SB1))
4783 target_flags |= MASK_BRANCHLIKELY;
4785 target_flags &= ~MASK_BRANCHLIKELY;
4787 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4788 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4790 /* The effect of -mabicalls isn't defined for the EABI. */
4791 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4793 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4794 target_flags &= ~MASK_ABICALLS;
4797 if (TARGET_ABICALLS)
4799 /* We need to set flag_pic for executables as well as DSOs
4800 because we may reference symbols that are not defined in
4801 the final executable. (MIPS does not use things like
4802 copy relocs, for example.)
4804 Also, there is a body of code that uses __PIC__ to distinguish
4805 between -mabicalls and -mno-abicalls code. */
4807 if (mips_section_threshold > 0)
4808 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
4811 /* mips_split_addresses is a half-way house between explicit
4812 relocations and the traditional assembler macros. It can
4813 split absolute 32-bit symbolic constants into a high/lo_sum
4814 pair but uses macros for other sorts of access.
4816 Like explicit relocation support for REL targets, it relies
4817 on GNU extensions in the assembler and the linker.
4819 Although this code should work for -O0, it has traditionally
4820 been treated as an optimization. */
4821 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4822 && optimize && !flag_pic
4823 && !ABI_HAS_64BIT_SYMBOLS)
4824 mips_split_addresses = 1;
4826 mips_split_addresses = 0;
4828 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4829 faster code, but at the expense of more nops. Enable it at -O3 and
4831 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4832 target_flags |= MASK_VR4130_ALIGN;
4834 /* When compiling for the mips16, we cannot use floating point. We
4835 record the original hard float value in mips16_hard_float. */
4838 if (TARGET_SOFT_FLOAT)
4839 mips16_hard_float = 0;
4841 mips16_hard_float = 1;
4842 target_flags |= MASK_SOFT_FLOAT;
4844 /* Don't run the scheduler before reload, since it tends to
4845 increase register pressure. */
4846 flag_schedule_insns = 0;
4848 /* Don't do hot/cold partitioning. The constant layout code expects
4849 the whole function to be in a single section. */
4850 flag_reorder_blocks_and_partition = 0;
4852 /* Silently disable -mexplicit-relocs since it doesn't apply
4853 to mips16 code. Even so, it would overly pedantic to warn
4854 about "-mips16 -mexplicit-relocs", especially given that
4855 we use a %gprel() operator. */
4856 target_flags &= ~MASK_EXPLICIT_RELOCS;
4859 /* When using explicit relocs, we call dbr_schedule from within
4861 if (TARGET_EXPLICIT_RELOCS)
4863 mips_flag_delayed_branch = flag_delayed_branch;
4864 flag_delayed_branch = 0;
4867 #ifdef MIPS_TFMODE_FORMAT
4868 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4871 /* Make sure that the user didn't turn off paired single support when
4872 MIPS-3D support is requested. */
4873 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4874 && !TARGET_PAIRED_SINGLE_FLOAT)
4875 error ("-mips3d requires -mpaired-single");
4877 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4879 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4881 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4882 and TARGET_HARD_FLOAT are both true. */
4883 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4884 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4886 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4888 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4889 error ("-mips3d/-mpaired-single must be used with -mips64");
4891 if (TARGET_MIPS16 && TARGET_DSP)
4892 error ("-mips16 and -mdsp cannot be used together");
4894 mips_print_operand_punct['?'] = 1;
4895 mips_print_operand_punct['#'] = 1;
4896 mips_print_operand_punct['/'] = 1;
4897 mips_print_operand_punct['&'] = 1;
4898 mips_print_operand_punct['!'] = 1;
4899 mips_print_operand_punct['*'] = 1;
4900 mips_print_operand_punct['@'] = 1;
4901 mips_print_operand_punct['.'] = 1;
4902 mips_print_operand_punct['('] = 1;
4903 mips_print_operand_punct[')'] = 1;
4904 mips_print_operand_punct['['] = 1;
4905 mips_print_operand_punct[']'] = 1;
4906 mips_print_operand_punct['<'] = 1;
4907 mips_print_operand_punct['>'] = 1;
4908 mips_print_operand_punct['{'] = 1;
4909 mips_print_operand_punct['}'] = 1;
4910 mips_print_operand_punct['^'] = 1;
4911 mips_print_operand_punct['$'] = 1;
4912 mips_print_operand_punct['+'] = 1;
4913 mips_print_operand_punct['~'] = 1;
4915 /* Set up array to map GCC register number to debug register number.
4916 Ignore the special purpose register numbers. */
4918 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4919 mips_dbx_regno[i] = -1;
4921 start = GP_DBX_FIRST - GP_REG_FIRST;
4922 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4923 mips_dbx_regno[i] = i + start;
4925 start = FP_DBX_FIRST - FP_REG_FIRST;
4926 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4927 mips_dbx_regno[i] = i + start;
4929 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4930 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4932 /* Set up array giving whether a given register can hold a given mode. */
4934 for (mode = VOIDmode;
4935 mode != MAX_MACHINE_MODE;
4936 mode = (enum machine_mode) ((int)mode + 1))
4938 register int size = GET_MODE_SIZE (mode);
4939 register enum mode_class class = GET_MODE_CLASS (mode);
4941 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4945 if (mode == CCV2mode)
4948 && (regno - ST_REG_FIRST) % 2 == 0);
4950 else if (mode == CCV4mode)
4953 && (regno - ST_REG_FIRST) % 4 == 0);
4955 else if (mode == CCmode)
4958 temp = (regno == FPSW_REGNUM);
4960 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4961 || FP_REG_P (regno));
4964 else if (GP_REG_P (regno))
4965 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4967 else if (FP_REG_P (regno))
4968 temp = ((regno % FP_INC) == 0)
4969 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
4970 || class == MODE_VECTOR_FLOAT)
4971 && size <= UNITS_PER_FPVALUE)
4972 /* Allow integer modes that fit into a single
4973 register. We need to put integers into FPRs
4974 when using instructions like cvt and trunc.
4975 We can't allow sizes smaller than a word,
4976 the FPU has no appropriate load/store
4977 instructions for those. */
4978 || (class == MODE_INT
4979 && size >= MIN_UNITS_PER_WORD
4980 && size <= UNITS_PER_FPREG)
4981 /* Allow TFmode for CCmode reloads. */
4982 || (ISA_HAS_8CC && mode == TFmode));
4984 else if (ACC_REG_P (regno))
4985 temp = (INTEGRAL_MODE_P (mode)
4986 && (size <= UNITS_PER_WORD
4987 || (ACC_HI_REG_P (regno)
4988 && size == 2 * UNITS_PER_WORD)));
4990 else if (ALL_COP_REG_P (regno))
4991 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
4995 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4999 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5000 initialized yet, so we can't use that here. */
5001 gpr_mode = TARGET_64BIT ? DImode : SImode;
5003 /* Provide default values for align_* for 64-bit targets. */
5004 if (TARGET_64BIT && !TARGET_MIPS16)
5006 if (align_loops == 0)
5008 if (align_jumps == 0)
5010 if (align_functions == 0)
5011 align_functions = 8;
5014 /* Function to allocate machine-dependent function status. */
5015 init_machine_status = &mips_init_machine_status;
5017 if (ABI_HAS_64BIT_SYMBOLS)
5019 if (TARGET_EXPLICIT_RELOCS)
5021 mips_split_p[SYMBOL_64_HIGH] = true;
5022 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5023 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5025 mips_split_p[SYMBOL_64_MID] = true;
5026 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5027 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5029 mips_split_p[SYMBOL_64_LOW] = true;
5030 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5031 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5033 mips_split_p[SYMBOL_GENERAL] = true;
5034 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5039 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5041 mips_split_p[SYMBOL_GENERAL] = true;
5042 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5043 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5049 /* The high part is provided by a pseudo copy of $gp. */
5050 mips_split_p[SYMBOL_SMALL_DATA] = true;
5051 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5054 if (TARGET_EXPLICIT_RELOCS)
5056 /* Small data constants are kept whole until after reload,
5057 then lowered by mips_rewrite_small_data. */
5058 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5060 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5063 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5064 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5068 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5069 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5074 /* The HIGH and LO_SUM are matched by special .md patterns. */
5075 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5077 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5078 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5079 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5081 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5082 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5083 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5088 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5090 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5091 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5097 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5098 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5099 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5102 /* Thread-local relocation operators. */
5103 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5104 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5105 mips_split_p[SYMBOL_DTPREL] = 1;
5106 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5107 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5108 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5109 mips_split_p[SYMBOL_TPREL] = 1;
5110 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5111 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5113 /* We don't have a thread pointer access instruction on MIPS16, or
5114 appropriate TLS relocations. */
5116 targetm.have_tls = false;
5118 /* Default to working around R4000 errata only if the processor
5119 was selected explicitly. */
5120 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5121 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5122 target_flags |= MASK_FIX_R4000;
5124 /* Default to working around R4400 errata only if the processor
5125 was selected explicitly. */
5126 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5127 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5128 target_flags |= MASK_FIX_R4400;
5131 /* Implement CONDITIONAL_REGISTER_USAGE. */
5134 mips_conditional_register_usage (void)
5140 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5141 fixed_regs[regno] = call_used_regs[regno] = 1;
5143 if (!TARGET_HARD_FLOAT)
5147 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5148 fixed_regs[regno] = call_used_regs[regno] = 1;
5149 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5150 fixed_regs[regno] = call_used_regs[regno] = 1;
5152 else if (! ISA_HAS_8CC)
5156 /* We only have a single condition code register. We
5157 implement this by hiding all the condition code registers,
5158 and generating RTL that refers directly to ST_REG_FIRST. */
5159 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5160 fixed_regs[regno] = call_used_regs[regno] = 1;
5162 /* In mips16 mode, we permit the $t temporary registers to be used
5163 for reload. We prohibit the unused $s registers, since they
5164 are caller saved, and saving them via a mips16 register would
5165 probably waste more time than just reloading the value. */
5168 fixed_regs[18] = call_used_regs[18] = 1;
5169 fixed_regs[19] = call_used_regs[19] = 1;
5170 fixed_regs[20] = call_used_regs[20] = 1;
5171 fixed_regs[21] = call_used_regs[21] = 1;
5172 fixed_regs[22] = call_used_regs[22] = 1;
5173 fixed_regs[23] = call_used_regs[23] = 1;
5174 fixed_regs[26] = call_used_regs[26] = 1;
5175 fixed_regs[27] = call_used_regs[27] = 1;
5176 fixed_regs[30] = call_used_regs[30] = 1;
5178 /* fp20-23 are now caller saved. */
5179 if (mips_abi == ABI_64)
5182 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5183 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5185 /* Odd registers from fp21 to fp31 are now caller saved. */
5186 if (mips_abi == ABI_N32)
5189 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5190 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5194 /* Allocate a chunk of memory for per-function machine-dependent data. */
5195 static struct machine_function *
5196 mips_init_machine_status (void)
5198 return ((struct machine_function *)
5199 ggc_alloc_cleared (sizeof (struct machine_function)));
5202 /* On the mips16, we want to allocate $24 (T_REG) before other
5203 registers for instructions for which it is possible. This helps
5204 avoid shuffling registers around in order to set up for an xor,
5205 encouraging the compiler to use a cmp instead. */
5208 mips_order_regs_for_local_alloc (void)
5212 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5213 reg_alloc_order[i] = i;
5217 /* It really doesn't matter where we put register 0, since it is
5218 a fixed register anyhow. */
5219 reg_alloc_order[0] = 24;
5220 reg_alloc_order[24] = 0;
5225 /* The MIPS debug format wants all automatic variables and arguments
5226 to be in terms of the virtual frame pointer (stack pointer before
5227 any adjustment in the function), while the MIPS 3.0 linker wants
5228 the frame pointer to be the stack pointer after the initial
5229 adjustment. So, we do the adjustment here. The arg pointer (which
5230 is eliminated) points to the virtual frame pointer, while the frame
5231 pointer (which may be eliminated) points to the stack pointer after
5232 the initial adjustments. */
5235 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5237 rtx offset2 = const0_rtx;
5238 rtx reg = eliminate_constant_term (addr, &offset2);
5241 offset = INTVAL (offset2);
5243 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5244 || reg == hard_frame_pointer_rtx)
5246 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5247 ? compute_frame_size (get_frame_size ())
5248 : cfun->machine->frame.total_size;
5250 /* MIPS16 frame is smaller */
5251 if (frame_pointer_needed && TARGET_MIPS16)
5252 frame_size -= cfun->machine->frame.args_size;
5254 offset = offset - frame_size;
5257 /* sdbout_parms does not want this to crash for unrecognized cases. */
5259 else if (reg != arg_pointer_rtx)
5260 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5267 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5269 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5270 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5271 'h' OP is HIGH, prints %hi(X),
5272 'd' output integer constant in decimal,
5273 'z' if the operand is 0, use $0 instead of normal operand.
5274 'D' print second part of double-word register or memory operand.
5275 'L' print low-order register of double-word register operand.
5276 'M' print high-order register of double-word register operand.
5277 'C' print part of opcode for a branch condition.
5278 'F' print part of opcode for a floating-point branch condition.
5279 'N' print part of opcode for a branch condition, inverted.
5280 'W' print part of opcode for a floating-point branch condition, inverted.
5281 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5282 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5283 't' like 'T', but with the EQ/NE cases reversed
5284 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5285 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5286 'R' print the reloc associated with LO_SUM
5287 'q' print DSP accumulator registers
5289 The punctuation characters are:
5291 '(' Turn on .set noreorder
5292 ')' Turn on .set reorder
5293 '[' Turn on .set noat
5295 '<' Turn on .set nomacro
5296 '>' Turn on .set macro
5297 '{' Turn on .set volatile (not GAS)
5298 '}' Turn on .set novolatile (not GAS)
5299 '&' Turn on .set noreorder if filling delay slots
5300 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5301 '!' Turn on .set nomacro if filling delay slots
5302 '#' Print nop if in a .set noreorder section.
5303 '/' Like '#', but does nothing within a delayed branch sequence
5304 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5305 '@' Print the name of the assembler temporary register (at or $1).
5306 '.' Print the name of the register with a hard-wired zero (zero or $0).
5307 '^' Print the name of the pic call-through register (t9 or $25).
5308 '$' Print the name of the stack pointer register (sp or $29).
5309 '+' Print the name of the gp register (usually gp or $28).
5310 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5313 print_operand (FILE *file, rtx op, int letter)
5315 register enum rtx_code code;
5317 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5322 if (mips_branch_likely)
5327 fputs (reg_names [GP_REG_FIRST + 1], file);
5331 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5335 fputs (reg_names [GP_REG_FIRST + 0], file);
5339 fputs (reg_names[STACK_POINTER_REGNUM], file);
5343 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5347 if (final_sequence != 0 && set_noreorder++ == 0)
5348 fputs (".set\tnoreorder\n\t", file);
5352 if (final_sequence != 0)
5354 if (set_noreorder++ == 0)
5355 fputs (".set\tnoreorder\n\t", file);
5357 if (set_nomacro++ == 0)
5358 fputs (".set\tnomacro\n\t", file);
5363 if (final_sequence != 0 && set_nomacro++ == 0)
5364 fputs ("\n\t.set\tnomacro", file);
5368 if (set_noreorder != 0)
5369 fputs ("\n\tnop", file);
5373 /* Print an extra newline so that the delayed insn is separated
5374 from the following ones. This looks neater and is consistent
5375 with non-nop delayed sequences. */
5376 if (set_noreorder != 0 && final_sequence == 0)
5377 fputs ("\n\tnop\n", file);
5381 if (set_noreorder++ == 0)
5382 fputs (".set\tnoreorder\n\t", file);
5386 if (set_noreorder == 0)
5387 error ("internal error: %%) found without a %%( in assembler pattern");
5389 else if (--set_noreorder == 0)
5390 fputs ("\n\t.set\treorder", file);
5395 if (set_noat++ == 0)
5396 fputs (".set\tnoat\n\t", file);
5401 error ("internal error: %%] found without a %%[ in assembler pattern");
5402 else if (--set_noat == 0)
5403 fputs ("\n\t.set\tat", file);
5408 if (set_nomacro++ == 0)
5409 fputs (".set\tnomacro\n\t", file);
5413 if (set_nomacro == 0)
5414 error ("internal error: %%> found without a %%< in assembler pattern");
5415 else if (--set_nomacro == 0)
5416 fputs ("\n\t.set\tmacro", file);
5421 if (set_volatile++ == 0)
5422 fputs ("#.set\tvolatile\n\t", file);
5426 if (set_volatile == 0)
5427 error ("internal error: %%} found without a %%{ in assembler pattern");
5428 else if (--set_volatile == 0)
5429 fputs ("\n\t#.set\tnovolatile", file);
5435 if (align_labels_log > 0)
5436 ASM_OUTPUT_ALIGN (file, align_labels_log);
5441 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5450 error ("PRINT_OPERAND null pointer");
5454 code = GET_CODE (op);
5459 case EQ: fputs ("eq", file); break;
5460 case NE: fputs ("ne", file); break;
5461 case GT: fputs ("gt", file); break;
5462 case GE: fputs ("ge", file); break;
5463 case LT: fputs ("lt", file); break;
5464 case LE: fputs ("le", file); break;
5465 case GTU: fputs ("gtu", file); break;
5466 case GEU: fputs ("geu", file); break;
5467 case LTU: fputs ("ltu", file); break;
5468 case LEU: fputs ("leu", file); break;
5470 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5473 else if (letter == 'N')
5476 case EQ: fputs ("ne", file); break;
5477 case NE: fputs ("eq", file); break;
5478 case GT: fputs ("le", file); break;
5479 case GE: fputs ("lt", file); break;
5480 case LT: fputs ("ge", file); break;
5481 case LE: fputs ("gt", file); break;
5482 case GTU: fputs ("leu", file); break;
5483 case GEU: fputs ("ltu", file); break;
5484 case LTU: fputs ("geu", file); break;
5485 case LEU: fputs ("gtu", file); break;
5487 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5490 else if (letter == 'F')
5493 case EQ: fputs ("c1f", file); break;
5494 case NE: fputs ("c1t", file); break;
5496 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5499 else if (letter == 'W')
5502 case EQ: fputs ("c1t", file); break;
5503 case NE: fputs ("c1f", file); break;
5505 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5508 else if (letter == 'h')
5510 if (GET_CODE (op) == HIGH)
5513 print_operand_reloc (file, op, mips_hi_relocs);
5516 else if (letter == 'R')
5517 print_operand_reloc (file, op, mips_lo_relocs);
5519 else if (letter == 'Y')
5521 if (GET_CODE (op) == CONST_INT
5522 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5523 < ARRAY_SIZE (mips_fp_conditions)))
5524 fputs (mips_fp_conditions[INTVAL (op)], file);
5526 output_operand_lossage ("invalid %%Y value");
5529 else if (letter == 'Z')
5533 print_operand (file, op, 0);
5538 else if (letter == 'q')
5543 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5545 regnum = REGNO (op);
5546 if (MD_REG_P (regnum))
5547 fprintf (file, "$ac0");
5548 else if (DSP_ACC_REG_P (regnum))
5549 fprintf (file, "$ac%c", reg_names[regnum][3]);
5551 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5554 else if (code == REG || code == SUBREG)
5556 register int regnum;
5559 regnum = REGNO (op);
5561 regnum = true_regnum (op);
5563 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5564 || (letter == 'L' && WORDS_BIG_ENDIAN)
5568 fprintf (file, "%s", reg_names[regnum]);
5571 else if (code == MEM)
5574 output_address (plus_constant (XEXP (op, 0), 4));
5576 output_address (XEXP (op, 0));
5579 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5580 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5582 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5583 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5585 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5586 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5588 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5589 fputs (reg_names[GP_REG_FIRST], file);
5591 else if (letter == 'd' || letter == 'x' || letter == 'X')
5592 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5594 else if (letter == 'T' || letter == 't')
5596 int truth = (code == NE) == (letter == 'T');
5597 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5600 else if (CONST_GP_P (op))
5601 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5604 output_addr_const (file, op);
5608 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5609 RELOCS is the array of relocations to use. */
5612 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5614 enum mips_symbol_type symbol_type;
5617 HOST_WIDE_INT offset;
5619 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5620 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5622 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5623 mips_split_const (op, &base, &offset);
5624 if (UNSPEC_ADDRESS_P (base))
5625 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5627 fputs (relocs[symbol_type], file);
5628 output_addr_const (file, op);
5629 for (p = relocs[symbol_type]; *p != 0; p++)
5634 /* Output address operand X to FILE. */
5637 print_operand_address (FILE *file, rtx x)
5639 struct mips_address_info addr;
5641 if (mips_classify_address (&addr, x, word_mode, true))
5645 print_operand (file, addr.offset, 0);
5646 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5649 case ADDRESS_LO_SUM:
5650 print_operand (file, addr.offset, 'R');
5651 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5654 case ADDRESS_CONST_INT:
5655 output_addr_const (file, x);
5656 fprintf (file, "(%s)", reg_names[0]);
5659 case ADDRESS_SYMBOLIC:
5660 output_addr_const (file, x);
5666 /* When using assembler macros, keep track of all of small-data externs
5667 so that mips_file_end can emit the appropriate declarations for them.
5669 In most cases it would be safe (though pointless) to emit .externs
5670 for other symbols too. One exception is when an object is within
5671 the -G limit but declared by the user to be in a section other
5672 than .sbss or .sdata. */
5675 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5677 register struct extern_list *p;
5679 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5681 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5682 p->next = extern_head;
5684 p->size = int_size_in_bytes (TREE_TYPE (decl));
5688 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5690 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5691 p->next = extern_head;
5702 irix_output_external_libcall (rtx fun)
5704 register struct extern_list *p;
5706 if (mips_abi == ABI_32)
5708 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5709 p->next = extern_head;
5710 p->name = XSTR (fun, 0);
5717 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5718 put out a MIPS ECOFF file and a stab. */
5721 mips_output_filename (FILE *stream, const char *name)
5724 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5726 if (write_symbols == DWARF2_DEBUG)
5728 else if (mips_output_filename_first_time)
5730 mips_output_filename_first_time = 0;
5731 num_source_filenames += 1;
5732 current_function_file = name;
5733 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5734 output_quoted_string (stream, name);
5735 putc ('\n', stream);
5738 /* If we are emitting stabs, let dbxout.c handle this (except for
5739 the mips_output_filename_first_time case). */
5740 else if (write_symbols == DBX_DEBUG)
5743 else if (name != current_function_file
5744 && strcmp (name, current_function_file) != 0)
5746 num_source_filenames += 1;
5747 current_function_file = name;
5748 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5749 output_quoted_string (stream, name);
5750 putc ('\n', stream);
5754 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5755 that should be written before the opening quote, such as "\t.ascii\t"
5756 for real string data or "\t# " for a comment. */
5759 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5764 register const unsigned char *string =
5765 (const unsigned char *)string_param;
5767 fprintf (stream, "%s\"", prefix);
5768 for (i = 0; i < len; i++)
5770 register int c = string[i];
5774 if (c == '\\' || c == '\"')
5776 putc ('\\', stream);
5784 fprintf (stream, "\\%03o", c);
5788 if (cur_pos > 72 && i+1 < len)
5791 fprintf (stream, "\"\n%s\"", prefix);
5794 fprintf (stream, "\"\n");
5797 /* Implement TARGET_ASM_FILE_START. */
5800 mips_file_start (void)
5802 default_file_start ();
5806 /* Generate a special section to describe the ABI switches used to
5807 produce the resultant binary. This used to be done by the assembler
5808 setting bits in the ELF header's flags field, but we have run out of
5809 bits. GDB needs this information in order to be able to correctly
5810 debug these binaries. See the function mips_gdbarch_init() in
5811 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5812 causes unnecessary IRIX 6 ld warnings. */
5813 const char * abi_string = NULL;
5817 case ABI_32: abi_string = "abi32"; break;
5818 case ABI_N32: abi_string = "abiN32"; break;
5819 case ABI_64: abi_string = "abi64"; break;
5820 case ABI_O64: abi_string = "abiO64"; break;
5821 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5825 /* Note - we use fprintf directly rather than calling switch_to_section
5826 because in this way we can avoid creating an allocated section. We
5827 do not want this section to take up any space in the running
5829 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5831 /* There is no ELF header flag to distinguish long32 forms of the
5832 EABI from long64 forms. Emit a special section to help tools
5834 if (mips_abi == ABI_EABI)
5835 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5836 TARGET_LONG64 ? 64 : 32);
5838 /* Restore the default section. */
5839 fprintf (asm_out_file, "\t.previous\n");
5842 /* Generate the pseudo ops that System V.4 wants. */
5843 if (TARGET_ABICALLS)
5844 fprintf (asm_out_file, "\t.abicalls\n");
5847 fprintf (asm_out_file, "\t.set\tmips16\n");
5849 if (flag_verbose_asm)
5850 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5852 mips_section_threshold, mips_arch_info->name, mips_isa);
5855 #ifdef BSS_SECTION_ASM_OP
5856 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5857 in the use of sbss. */
5860 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5861 unsigned HOST_WIDE_INT size, int align)
5863 extern tree last_assemble_variable_decl;
5865 if (mips_in_small_data_p (decl))
5866 switch_to_section (get_named_section (NULL, ".sbss", 0));
5868 switch_to_section (bss_section);
5869 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5870 last_assemble_variable_decl = decl;
5871 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5872 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5876 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5877 .externs for any small-data variables that turned out to be external. */
5880 mips_file_end (void)
5883 struct extern_list *p;
5887 fputs ("\n", asm_out_file);
5889 for (p = extern_head; p != 0; p = p->next)
5891 name_tree = get_identifier (p->name);
5893 /* Positively ensure only one .extern for any given symbol. */
5894 if (!TREE_ASM_WRITTEN (name_tree)
5895 && TREE_SYMBOL_REFERENCED (name_tree))
5897 TREE_ASM_WRITTEN (name_tree) = 1;
5898 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5899 `.global name .text' directive for every used but
5900 undefined function. If we don't, the linker may perform
5901 an optimization (skipping over the insns that set $gp)
5902 when it is unsafe. */
5903 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5905 fputs ("\t.globl ", asm_out_file);
5906 assemble_name (asm_out_file, p->name);
5907 fputs (" .text\n", asm_out_file);
5911 fputs ("\t.extern\t", asm_out_file);
5912 assemble_name (asm_out_file, p->name);
5913 fprintf (asm_out_file, ", %d\n", p->size);
5920 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5921 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5924 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5925 unsigned HOST_WIDE_INT size,
5928 /* If the target wants uninitialized const declarations in
5929 .rdata then don't put them in .comm. */
5930 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5931 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5932 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5934 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5935 targetm.asm_out.globalize_label (stream, name);
5937 switch_to_section (readonly_data_section);
5938 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5939 mips_declare_object (stream, name, "",
5940 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5944 mips_declare_common_object (stream, name, "\n\t.comm\t",
5948 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5949 NAME is the name of the object and ALIGN is the required alignment
5950 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5951 alignment argument. */
5954 mips_declare_common_object (FILE *stream, const char *name,
5955 const char *init_string,
5956 unsigned HOST_WIDE_INT size,
5957 unsigned int align, bool takes_alignment_p)
5959 if (!takes_alignment_p)
5961 size += (align / BITS_PER_UNIT) - 1;
5962 size -= size % (align / BITS_PER_UNIT);
5963 mips_declare_object (stream, name, init_string,
5964 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
5967 mips_declare_object (stream, name, init_string,
5968 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
5969 size, align / BITS_PER_UNIT);
5972 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5973 macros, mark the symbol as written so that mips_file_end won't emit an
5974 .extern for it. STREAM is the output file, NAME is the name of the
5975 symbol, INIT_STRING is the string that should be written before the
5976 symbol and FINAL_STRING is the string that should be written after it.
5977 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5980 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5981 const char *final_string, ...)
5985 fputs (init_string, stream);
5986 assemble_name (stream, name);
5987 va_start (ap, final_string);
5988 vfprintf (stream, final_string, ap);
5991 if (!TARGET_EXPLICIT_RELOCS)
5993 tree name_tree = get_identifier (name);
5994 TREE_ASM_WRITTEN (name_tree) = 1;
5998 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5999 extern int size_directive_output;
6001 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6002 definitions except that it uses mips_declare_object() to emit the label. */
6005 mips_declare_object_name (FILE *stream, const char *name,
6006 tree decl ATTRIBUTE_UNUSED)
6008 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6009 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6012 size_directive_output = 0;
6013 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6017 size_directive_output = 1;
6018 size = int_size_in_bytes (TREE_TYPE (decl));
6019 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6022 mips_declare_object (stream, name, "", ":\n");
6025 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6028 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6032 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6033 if (!flag_inhibit_size_directive
6034 && DECL_SIZE (decl) != 0
6035 && !at_end && top_level
6036 && DECL_INITIAL (decl) == error_mark_node
6037 && !size_directive_output)
6041 size_directive_output = 1;
6042 size = int_size_in_bytes (TREE_TYPE (decl));
6043 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6048 /* Return true if X is a small data address that can be rewritten
6052 mips_rewrite_small_data_p (rtx x)
6054 enum mips_symbol_type symbol_type;
6056 return (TARGET_EXPLICIT_RELOCS
6057 && mips_symbolic_constant_p (x, &symbol_type)
6058 && symbol_type == SYMBOL_SMALL_DATA);
6062 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6065 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6067 if (GET_CODE (*loc) == LO_SUM)
6070 return mips_rewrite_small_data_p (*loc);
6073 /* Return true if OP refers to small data symbols directly, not through
6077 mips_small_data_pattern_p (rtx op)
6079 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6082 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6085 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6087 if (mips_rewrite_small_data_p (*loc))
6088 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6090 if (GET_CODE (*loc) == LO_SUM)
6096 /* If possible, rewrite OP so that it refers to small data using
6097 explicit relocations. */
6100 mips_rewrite_small_data (rtx op)
6102 op = copy_insn (op);
6103 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6107 /* Return true if the current function has an insn that implicitly
6111 mips_function_has_gp_insn (void)
6113 /* Don't bother rechecking if we found one last time. */
6114 if (!cfun->machine->has_gp_insn_p)
6118 push_topmost_sequence ();
6119 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6121 && GET_CODE (PATTERN (insn)) != USE
6122 && GET_CODE (PATTERN (insn)) != CLOBBER
6123 && (get_attr_got (insn) != GOT_UNSET
6124 || small_data_pattern (PATTERN (insn), VOIDmode)))
6126 pop_topmost_sequence ();
6128 cfun->machine->has_gp_insn_p = (insn != 0);
6130 return cfun->machine->has_gp_insn_p;
6134 /* Return the register that should be used as the global pointer
6135 within this function. Return 0 if the function doesn't need
6136 a global pointer. */
6139 mips_global_pointer (void)
6143 /* $gp is always available in non-abicalls code. */
6144 if (!TARGET_ABICALLS)
6145 return GLOBAL_POINTER_REGNUM;
6147 /* We must always provide $gp when it is used implicitly. */
6148 if (!TARGET_EXPLICIT_RELOCS)
6149 return GLOBAL_POINTER_REGNUM;
6151 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6153 if (current_function_profile)
6154 return GLOBAL_POINTER_REGNUM;
6156 /* If the function has a nonlocal goto, $gp must hold the correct
6157 global pointer for the target function. */
6158 if (current_function_has_nonlocal_goto)
6159 return GLOBAL_POINTER_REGNUM;
6161 /* If the gp is never referenced, there's no need to initialize it.
6162 Note that reload can sometimes introduce constant pool references
6163 into a function that otherwise didn't need them. For example,
6164 suppose we have an instruction like:
6166 (set (reg:DF R1) (float:DF (reg:SI R2)))
6168 If R2 turns out to be constant such as 1, the instruction may have a
6169 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6170 using this constant if R2 doesn't get allocated to a register.
6172 In cases like these, reload will have added the constant to the pool
6173 but no instruction will yet refer to it. */
6174 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6175 && !current_function_uses_const_pool
6176 && !mips_function_has_gp_insn ())
6179 /* We need a global pointer, but perhaps we can use a call-clobbered
6180 register instead of $gp. */
6181 if (TARGET_NEWABI && current_function_is_leaf)
6182 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6183 if (!regs_ever_live[regno]
6184 && call_used_regs[regno]
6185 && !fixed_regs[regno]
6186 && regno != PIC_FUNCTION_ADDR_REGNUM)
6189 return GLOBAL_POINTER_REGNUM;
6193 /* Return true if the current function must save REGNO. */
6196 mips_save_reg_p (unsigned int regno)
6198 /* We only need to save $gp for NewABI PIC. */
6199 if (regno == GLOBAL_POINTER_REGNUM)
6200 return (TARGET_ABICALLS && TARGET_NEWABI
6201 && cfun->machine->global_pointer == regno);
6203 /* Check call-saved registers. */
6204 if (regs_ever_live[regno] && !call_used_regs[regno])
6207 /* We need to save the old frame pointer before setting up a new one. */
6208 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6211 /* We need to save the incoming return address if it is ever clobbered
6212 within the function. */
6213 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6220 return_type = DECL_RESULT (current_function_decl);
6222 /* $18 is a special case in mips16 code. It may be used to call
6223 a function which returns a floating point value, but it is
6224 marked in call_used_regs. */
6225 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6228 /* $31 is also a special case. It will be used to copy a return
6229 value into the floating point registers if the return value is
6231 if (regno == GP_REG_FIRST + 31
6232 && mips16_hard_float
6233 && !aggregate_value_p (return_type, current_function_decl)
6234 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6235 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6243 /* Return the bytes needed to compute the frame pointer from the current
6244 stack pointer. SIZE is the size (in bytes) of the local variables.
6246 MIPS stack frames look like:
6248 Before call After call
6249 +-----------------------+ +-----------------------+
6252 | caller's temps. | | caller's temps. |
6254 +-----------------------+ +-----------------------+
6256 | arguments on stack. | | arguments on stack. |
6258 +-----------------------+ +-----------------------+
6259 | 4 words to save | | 4 words to save |
6260 | arguments passed | | arguments passed |
6261 | in registers, even | | in registers, even |
6262 SP->| if not passed. | VFP->| if not passed. |
6263 +-----------------------+ +-----------------------+
6265 | fp register save |
6267 +-----------------------+
6269 | gp register save |
6271 +-----------------------+
6275 +-----------------------+
6277 | alloca allocations |
6279 +-----------------------+
6281 | GP save for V.4 abi |
6283 +-----------------------+
6285 | arguments on stack |
6287 +-----------------------+
6289 | arguments passed |
6290 | in registers, even |
6291 low SP->| if not passed. |
6292 memory +-----------------------+
6297 compute_frame_size (HOST_WIDE_INT size)
6300 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6301 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6302 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6303 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6304 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6305 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6306 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6307 unsigned int mask; /* mask of saved gp registers */
6308 unsigned int fmask; /* mask of saved fp registers */
6310 cfun->machine->global_pointer = mips_global_pointer ();
6316 var_size = MIPS_STACK_ALIGN (size);
6317 args_size = current_function_outgoing_args_size;
6318 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6320 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6321 functions. If the function has local variables, we're committed
6322 to allocating it anyway. Otherwise reclaim it here. */
6323 if (var_size == 0 && current_function_is_leaf)
6324 cprestore_size = args_size = 0;
6326 /* The MIPS 3.0 linker does not like functions that dynamically
6327 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6328 looks like we are trying to create a second frame pointer to the
6329 function, so allocate some stack space to make it happy. */
6331 if (args_size == 0 && current_function_calls_alloca)
6332 args_size = 4 * UNITS_PER_WORD;
6334 total_size = var_size + args_size + cprestore_size;
6336 /* Calculate space needed for gp registers. */
6337 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6338 if (mips_save_reg_p (regno))
6340 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6341 mask |= 1 << (regno - GP_REG_FIRST);
6344 /* We need to restore these for the handler. */
6345 if (current_function_calls_eh_return)
6350 regno = EH_RETURN_DATA_REGNO (i);
6351 if (regno == INVALID_REGNUM)
6353 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6354 mask |= 1 << (regno - GP_REG_FIRST);
6358 /* This loop must iterate over the same space as its companion in
6359 save_restore_insns. */
6360 for (regno = (FP_REG_LAST - FP_INC + 1);
6361 regno >= FP_REG_FIRST;
6364 if (mips_save_reg_p (regno))
6366 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6367 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6371 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6372 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6374 /* Add in the space required for saving incoming register arguments. */
6375 total_size += current_function_pretend_args_size;
6376 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6378 /* Save other computed information. */
6379 cfun->machine->frame.total_size = total_size;
6380 cfun->machine->frame.var_size = var_size;
6381 cfun->machine->frame.args_size = args_size;
6382 cfun->machine->frame.cprestore_size = cprestore_size;
6383 cfun->machine->frame.gp_reg_size = gp_reg_size;
6384 cfun->machine->frame.fp_reg_size = fp_reg_size;
6385 cfun->machine->frame.mask = mask;
6386 cfun->machine->frame.fmask = fmask;
6387 cfun->machine->frame.initialized = reload_completed;
6388 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6389 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6393 HOST_WIDE_INT offset;
6395 offset = (args_size + cprestore_size + var_size
6396 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6397 cfun->machine->frame.gp_sp_offset = offset;
6398 cfun->machine->frame.gp_save_offset = offset - total_size;
6402 cfun->machine->frame.gp_sp_offset = 0;
6403 cfun->machine->frame.gp_save_offset = 0;
6408 HOST_WIDE_INT offset;
6410 offset = (args_size + cprestore_size + var_size
6411 + gp_reg_rounded + fp_reg_size
6412 - FP_INC * UNITS_PER_FPREG);
6413 cfun->machine->frame.fp_sp_offset = offset;
6414 cfun->machine->frame.fp_save_offset = offset - total_size;
6418 cfun->machine->frame.fp_sp_offset = 0;
6419 cfun->machine->frame.fp_save_offset = 0;
6422 /* Ok, we're done. */
6426 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6427 pointer or argument pointer. TO is either the stack pointer or
6428 hard frame pointer. */
6431 mips_initial_elimination_offset (int from, int to)
6433 HOST_WIDE_INT offset;
6435 compute_frame_size (get_frame_size ());
6437 /* Set OFFSET to the offset from the stack pointer. */
6440 case FRAME_POINTER_REGNUM:
6444 case ARG_POINTER_REGNUM:
6445 offset = (cfun->machine->frame.total_size
6446 - current_function_pretend_args_size);
6453 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6454 offset -= cfun->machine->frame.args_size;
6459 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6460 back to a previous frame. */
6462 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6467 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6470 /* Use FN to save or restore register REGNO. MODE is the register's
6471 mode and OFFSET is the offset of its save slot from the current
6475 mips_save_restore_reg (enum machine_mode mode, int regno,
6476 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6480 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6482 fn (gen_rtx_REG (mode, regno), mem);
6486 /* Call FN for each register that is saved by the current function.
6487 SP_OFFSET is the offset of the current stack pointer from the start
6491 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6493 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6495 enum machine_mode fpr_mode;
6496 HOST_WIDE_INT offset;
6499 /* Save registers starting from high to low. The debuggers prefer at least
6500 the return register be stored at func+4, and also it allows us not to
6501 need a nop in the epilog if at least one register is reloaded in
6502 addition to return address. */
6503 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6504 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6505 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6507 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6508 offset -= GET_MODE_SIZE (gpr_mode);
6511 /* This loop must iterate over the same space as its companion in
6512 compute_frame_size. */
6513 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6514 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6515 for (regno = (FP_REG_LAST - FP_INC + 1);
6516 regno >= FP_REG_FIRST;
6518 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6520 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6521 offset -= GET_MODE_SIZE (fpr_mode);
6526 /* If we're generating n32 or n64 abicalls, and the current function
6527 does not use $28 as its global pointer, emit a cplocal directive.
6528 Use pic_offset_table_rtx as the argument to the directive. */
6531 mips_output_cplocal (void)
6533 if (!TARGET_EXPLICIT_RELOCS
6534 && cfun->machine->global_pointer > 0
6535 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6536 output_asm_insn (".cplocal %+", 0);
6539 /* Return the style of GP load sequence that is being used for the
6540 current function. */
6542 enum mips_loadgp_style
6543 mips_current_loadgp_style (void)
6545 if (!TARGET_ABICALLS || cfun->machine->global_pointer == 0)
6548 if (TARGET_ABSOLUTE_ABICALLS)
6549 return LOADGP_ABSOLUTE;
6551 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6554 /* The __gnu_local_gp symbol. */
6556 static GTY(()) rtx mips_gnu_local_gp;
6558 /* If we're generating n32 or n64 abicalls, emit instructions
6559 to set up the global pointer. */
6562 mips_emit_loadgp (void)
6564 rtx addr, offset, incoming_address;
6566 switch (mips_current_loadgp_style ())
6568 case LOADGP_ABSOLUTE:
6569 if (mips_gnu_local_gp == NULL)
6571 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
6572 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
6574 emit_insn (gen_loadgp_noshared (mips_gnu_local_gp));
6578 addr = XEXP (DECL_RTL (current_function_decl), 0);
6579 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6580 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6581 emit_insn (gen_loadgp (offset, incoming_address));
6582 if (!TARGET_EXPLICIT_RELOCS)
6583 emit_insn (gen_loadgp_blockage ());
6591 /* Set up the stack and frame (if desired) for the function. */
6594 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6597 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6599 #ifdef SDB_DEBUGGING_INFO
6600 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6601 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6604 /* In mips16 mode, we may need to generate a 32 bit to handle
6605 floating point arguments. The linker will arrange for any 32 bit
6606 functions to call this stub, which will then jump to the 16 bit
6608 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6609 && current_function_args_info.fp_code != 0)
6610 build_mips16_function_stub (file);
6612 if (!FUNCTION_NAME_ALREADY_DECLARED)
6614 /* Get the function name the same way that toplev.c does before calling
6615 assemble_start_function. This is needed so that the name used here
6616 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6617 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6619 if (!flag_inhibit_size_directive)
6621 fputs ("\t.ent\t", file);
6622 assemble_name (file, fnname);
6626 assemble_name (file, fnname);
6627 fputs (":\n", file);
6630 /* Stop mips_file_end from treating this function as external. */
6631 if (TARGET_IRIX && mips_abi == ABI_32)
6632 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6634 if (!flag_inhibit_size_directive)
6636 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6638 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6639 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6640 ", args= " HOST_WIDE_INT_PRINT_DEC
6641 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6642 (reg_names[(frame_pointer_needed)
6643 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6644 ((frame_pointer_needed && TARGET_MIPS16)
6645 ? tsize - cfun->machine->frame.args_size
6647 reg_names[GP_REG_FIRST + 31],
6648 cfun->machine->frame.var_size,
6649 cfun->machine->frame.num_gp,
6650 cfun->machine->frame.num_fp,
6651 cfun->machine->frame.args_size,
6652 cfun->machine->frame.cprestore_size);
6654 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6655 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6656 cfun->machine->frame.mask,
6657 cfun->machine->frame.gp_save_offset);
6658 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6659 cfun->machine->frame.fmask,
6660 cfun->machine->frame.fp_save_offset);
6663 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6664 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6667 if (mips_current_loadgp_style () == LOADGP_OLDABI)
6669 /* Handle the initialization of $gp for SVR4 PIC. */
6670 if (!cfun->machine->all_noreorder_p)
6671 output_asm_insn ("%(.cpload\t%^%)", 0);
6673 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6675 else if (cfun->machine->all_noreorder_p)
6676 output_asm_insn ("%(%<", 0);
6678 /* Tell the assembler which register we're using as the global
6679 pointer. This is needed for thunks, since they can use either
6680 explicit relocs or assembler macros. */
6681 mips_output_cplocal ();
6684 /* Make the last instruction frame related and note that it performs
6685 the operation described by FRAME_PATTERN. */
6688 mips_set_frame_expr (rtx frame_pattern)
6692 insn = get_last_insn ();
6693 RTX_FRAME_RELATED_P (insn) = 1;
6694 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6700 /* Return a frame-related rtx that stores REG at MEM.
6701 REG must be a single register. */
6704 mips_frame_set (rtx mem, rtx reg)
6708 /* If we're saving the return address register and the dwarf return
6709 address column differs from the hard register number, adjust the
6710 note reg to refer to the former. */
6711 if (REGNO (reg) == GP_REG_FIRST + 31
6712 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6713 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6715 set = gen_rtx_SET (VOIDmode, mem, reg);
6716 RTX_FRAME_RELATED_P (set) = 1;
6722 /* Save register REG to MEM. Make the instruction frame-related. */
6725 mips_save_reg (rtx reg, rtx mem)
6727 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6731 if (mips_split_64bit_move_p (mem, reg))
6732 mips_split_64bit_move (mem, reg);
6734 emit_move_insn (mem, reg);
6736 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6737 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6738 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6743 && REGNO (reg) != GP_REG_FIRST + 31
6744 && !M16_REG_P (REGNO (reg)))
6746 /* Save a non-mips16 register by moving it through a temporary.
6747 We don't need to do this for $31 since there's a special
6748 instruction for it. */
6749 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6750 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6753 emit_move_insn (mem, reg);
6755 mips_set_frame_expr (mips_frame_set (mem, reg));
6760 /* Expand the prologue into a bunch of separate insns. */
6763 mips_expand_prologue (void)
6767 if (cfun->machine->global_pointer > 0)
6768 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6770 size = compute_frame_size (get_frame_size ());
6772 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6773 bytes beforehand; this is enough to cover the register save area
6774 without going out of range. */
6775 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6777 HOST_WIDE_INT step1;
6779 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6780 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6782 GEN_INT (-step1)))) = 1;
6784 mips_for_each_saved_reg (size, mips_save_reg);
6787 /* Allocate the rest of the frame. */
6790 if (SMALL_OPERAND (-size))
6791 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6793 GEN_INT (-size)))) = 1;
6796 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6799 /* There are no instructions to add or subtract registers
6800 from the stack pointer, so use the frame pointer as a
6801 temporary. We should always be using a frame pointer
6802 in this case anyway. */
6803 gcc_assert (frame_pointer_needed);
6804 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6805 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6806 hard_frame_pointer_rtx,
6807 MIPS_PROLOGUE_TEMP (Pmode)));
6808 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6811 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6813 MIPS_PROLOGUE_TEMP (Pmode)));
6815 /* Describe the combined effect of the previous instructions. */
6817 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6818 plus_constant (stack_pointer_rtx, -size)));
6822 /* Set up the frame pointer, if we're using one. In mips16 code,
6823 we point the frame pointer ahead of the outgoing argument area.
6824 This should allow more variables & incoming arguments to be
6825 accessed with unextended instructions. */
6826 if (frame_pointer_needed)
6828 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6830 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6831 if (SMALL_OPERAND (cfun->machine->frame.args_size))
6833 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6838 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
6839 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6840 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6841 hard_frame_pointer_rtx,
6842 MIPS_PROLOGUE_TEMP (Pmode)));
6844 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
6845 plus_constant (stack_pointer_rtx,
6846 cfun->machine->frame.args_size)));
6850 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6851 stack_pointer_rtx)) = 1;
6854 mips_emit_loadgp ();
6856 /* If generating o32/o64 abicalls, save $gp on the stack. */
6857 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6858 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6860 /* If we are profiling, make sure no instructions are scheduled before
6861 the call to mcount. */
6863 if (current_function_profile)
6864 emit_insn (gen_blockage ());
6867 /* Do any necessary cleanup after a function to restore stack, frame,
6870 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6873 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6874 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6876 /* Reinstate the normal $gp. */
6877 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6878 mips_output_cplocal ();
6880 if (cfun->machine->all_noreorder_p)
6882 /* Avoid using %>%) since it adds excess whitespace. */
6883 output_asm_insn (".set\tmacro", 0);
6884 output_asm_insn (".set\treorder", 0);
6885 set_noreorder = set_nomacro = 0;
6888 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6892 /* Get the function name the same way that toplev.c does before calling
6893 assemble_start_function. This is needed so that the name used here
6894 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6895 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6896 fputs ("\t.end\t", file);
6897 assemble_name (file, fnname);
6902 /* Emit instructions to restore register REG from slot MEM. */
6905 mips_restore_reg (rtx reg, rtx mem)
6907 /* There's no mips16 instruction to load $31 directly. Load into
6908 $7 instead and adjust the return insn appropriately. */
6909 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6910 reg = gen_rtx_REG (GET_MODE (reg), 7);
6912 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6914 /* Can't restore directly; move through a temporary. */
6915 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6916 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6919 emit_move_insn (reg, mem);
6923 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6924 if this epilogue precedes a sibling call, false if it is for a normal
6925 "epilogue" pattern. */
6928 mips_expand_epilogue (int sibcall_p)
6930 HOST_WIDE_INT step1, step2;
6933 if (!sibcall_p && mips_can_use_return_insn ())
6935 emit_jump_insn (gen_return ());
6939 /* Split the frame into two. STEP1 is the amount of stack we should
6940 deallocate before restoring the registers. STEP2 is the amount we
6941 should deallocate afterwards.
6943 Start off by assuming that no registers need to be restored. */
6944 step1 = cfun->machine->frame.total_size;
6947 /* Work out which register holds the frame address. Account for the
6948 frame pointer offset used by mips16 code. */
6949 if (!frame_pointer_needed)
6950 base = stack_pointer_rtx;
6953 base = hard_frame_pointer_rtx;
6955 step1 -= cfun->machine->frame.args_size;
6958 /* If we need to restore registers, deallocate as much stack as
6959 possible in the second step without going out of range. */
6960 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6962 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6966 /* Set TARGET to BASE + STEP1. */
6972 /* Get an rtx for STEP1 that we can add to BASE. */
6973 adjust = GEN_INT (step1);
6974 if (!SMALL_OPERAND (step1))
6976 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6977 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6980 /* Normal mode code can copy the result straight into $sp. */
6982 target = stack_pointer_rtx;
6984 emit_insn (gen_add3_insn (target, base, adjust));
6987 /* Copy TARGET into the stack pointer. */
6988 if (target != stack_pointer_rtx)
6989 emit_move_insn (stack_pointer_rtx, target);
6991 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6992 implicitly used by all SYMBOL_REFs. We must emit a blockage
6993 insn before restoring it. */
6994 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6995 emit_insn (gen_blockage ());
6997 /* Restore the registers. */
6998 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7001 /* Deallocate the final bit of the frame. */
7003 emit_insn (gen_add3_insn (stack_pointer_rtx,
7007 /* Add in the __builtin_eh_return stack adjustment. We need to
7008 use a temporary in mips16 code. */
7009 if (current_function_calls_eh_return)
7013 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7014 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7015 MIPS_EPILOGUE_TEMP (Pmode),
7016 EH_RETURN_STACKADJ_RTX));
7017 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7020 emit_insn (gen_add3_insn (stack_pointer_rtx,
7022 EH_RETURN_STACKADJ_RTX));
7027 /* The mips16 loads the return address into $7, not $31. */
7028 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7029 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7030 GP_REG_FIRST + 7)));
7032 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7033 GP_REG_FIRST + 31)));
7037 /* Return nonzero if this function is known to have a null epilogue.
7038 This allows the optimizer to omit jumps to jumps if no stack
7042 mips_can_use_return_insn (void)
7046 if (! reload_completed)
7049 if (regs_ever_live[31] || current_function_profile)
7052 return_type = DECL_RESULT (current_function_decl);
7054 /* In mips16 mode, a function which returns a floating point value
7055 needs to arrange to copy the return value into the floating point
7058 && mips16_hard_float
7059 && ! aggregate_value_p (return_type, current_function_decl)
7060 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7061 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7064 if (cfun->machine->frame.initialized)
7065 return cfun->machine->frame.total_size == 0;
7067 return compute_frame_size (get_frame_size ()) == 0;
7070 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7071 in order to avoid duplicating too much logic from elsewhere. */
7074 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7075 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7078 rtx this, temp1, temp2, insn, fnaddr;
7080 /* Pretend to be a post-reload pass while generating rtl. */
7082 reload_completed = 1;
7083 reset_block_changes ();
7085 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7086 for TARGET_NEWABI since the latter is a call-saved register. */
7087 if (TARGET_ABICALLS)
7088 cfun->machine->global_pointer
7089 = REGNO (pic_offset_table_rtx)
7090 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7092 /* Set up the global pointer for n32 or n64 abicalls. */
7093 mips_emit_loadgp ();
7095 /* We need two temporary registers in some cases. */
7096 temp1 = gen_rtx_REG (Pmode, 2);
7097 temp2 = gen_rtx_REG (Pmode, 3);
7099 /* Find out which register contains the "this" pointer. */
7100 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7101 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7103 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7105 /* Add DELTA to THIS. */
7108 rtx offset = GEN_INT (delta);
7109 if (!SMALL_OPERAND (delta))
7111 emit_move_insn (temp1, offset);
7114 emit_insn (gen_add3_insn (this, this, offset));
7117 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7118 if (vcall_offset != 0)
7122 /* Set TEMP1 to *THIS. */
7123 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7125 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7126 addr = mips_add_offset (temp2, temp1, vcall_offset);
7128 /* Load the offset and add it to THIS. */
7129 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7130 emit_insn (gen_add3_insn (this, this, temp1));
7133 /* Jump to the target function. Use a sibcall if direct jumps are
7134 allowed, otherwise load the address into a register first. */
7135 fnaddr = XEXP (DECL_RTL (function), 0);
7136 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7138 /* This is messy. gas treats "la $25,foo" as part of a call
7139 sequence and may allow a global "foo" to be lazily bound.
7140 The general move patterns therefore reject this combination.
7142 In this context, lazy binding would actually be OK for o32 and o64,
7143 but it's still wrong for n32 and n64; see mips_load_call_address.
7144 We must therefore load the address via a temporary register if
7145 mips_dangerous_for_la25_p.
7147 If we jump to the temporary register rather than $25, the assembler
7148 can use the move insn to fill the jump's delay slot. */
7149 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7150 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7151 mips_load_call_address (temp1, fnaddr, true);
7153 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7154 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7155 emit_jump_insn (gen_indirect_jump (temp1));
7159 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7160 SIBLING_CALL_P (insn) = 1;
7163 /* Run just enough of rest_of_compilation. This sequence was
7164 "borrowed" from alpha.c. */
7165 insn = get_insns ();
7166 insn_locators_initialize ();
7167 split_all_insns_noflow ();
7169 mips16_lay_out_constants ();
7170 shorten_branches (insn);
7171 final_start_function (insn, file, 1);
7172 final (insn, file, 1);
7173 final_end_function ();
7175 /* Clean up the vars set above. Note that final_end_function resets
7176 the global pointer for us. */
7177 reload_completed = 0;
7181 /* Returns nonzero if X contains a SYMBOL_REF. */
7184 symbolic_expression_p (rtx x)
7186 if (GET_CODE (x) == SYMBOL_REF)
7189 if (GET_CODE (x) == CONST)
7190 return symbolic_expression_p (XEXP (x, 0));
7193 return symbolic_expression_p (XEXP (x, 0));
7195 if (ARITHMETIC_P (x))
7196 return (symbolic_expression_p (XEXP (x, 0))
7197 || symbolic_expression_p (XEXP (x, 1)));
7202 /* Choose the section to use for the constant rtx expression X that has
7206 mips_select_rtx_section (enum machine_mode mode, rtx x,
7207 unsigned HOST_WIDE_INT align)
7211 /* In mips16 mode, the constant table always goes in the same section
7212 as the function, so that constants can be loaded using PC relative
7214 return function_section (current_function_decl);
7216 else if (TARGET_EMBEDDED_DATA)
7218 /* For embedded applications, always put constants in read-only data,
7219 in order to reduce RAM usage. */
7220 return mergeable_constant_section (mode, align, 0);
7224 /* For hosted applications, always put constants in small data if
7225 possible, as this gives the best performance. */
7226 /* ??? Consider using mergeable small data sections. */
7228 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7229 && mips_section_threshold > 0)
7230 return get_named_section (NULL, ".sdata", 0);
7231 else if (flag_pic && symbolic_expression_p (x))
7232 return get_named_section (NULL, ".data.rel.ro", 3);
7234 return mergeable_constant_section (mode, align, 0);
7238 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7240 The complication here is that, with the combination TARGET_ABICALLS
7241 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7242 therefore not be included in the read-only part of a DSO. Handle such
7243 cases by selecting a normal data section instead of a read-only one.
7244 The logic apes that in default_function_rodata_section. */
7247 mips_function_rodata_section (tree decl)
7249 if (!TARGET_ABICALLS || TARGET_GPWORD)
7250 return default_function_rodata_section (decl);
7252 if (decl && DECL_SECTION_NAME (decl))
7254 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7255 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7257 char *rname = ASTRDUP (name);
7259 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7261 else if (flag_function_sections && flag_data_sections
7262 && strncmp (name, ".text.", 6) == 0)
7264 char *rname = ASTRDUP (name);
7265 memcpy (rname + 1, "data", 4);
7266 return get_section (rname, SECTION_WRITE, decl);
7269 return data_section;
7272 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7273 access DECL using %gp_rel(...)($gp). */
7276 mips_in_small_data_p (tree decl)
7280 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7283 /* We don't yet generate small-data references for -mabicalls. See related
7284 -G handling in override_options. */
7285 if (TARGET_ABICALLS)
7288 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7292 /* Reject anything that isn't in a known small-data section. */
7293 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7294 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7297 /* If a symbol is defined externally, the assembler will use the
7298 usual -G rules when deciding how to implement macros. */
7299 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7302 else if (TARGET_EMBEDDED_DATA)
7304 /* Don't put constants into the small data section: we want them
7305 to be in ROM rather than RAM. */
7306 if (TREE_CODE (decl) != VAR_DECL)
7309 if (TREE_READONLY (decl)
7310 && !TREE_SIDE_EFFECTS (decl)
7311 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7315 size = int_size_in_bytes (TREE_TYPE (decl));
7316 return (size > 0 && size <= mips_section_threshold);
7319 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7320 anchors for small data: the GP register acts as an anchor in that
7321 case. We also don't want to use them for PC-relative accesses,
7322 where the PC acts as an anchor. */
7325 mips_use_anchors_for_symbol_p (rtx symbol)
7327 switch (mips_classify_symbol (symbol))
7329 case SYMBOL_CONSTANT_POOL:
7330 case SYMBOL_SMALL_DATA:
7338 /* See whether VALTYPE is a record whose fields should be returned in
7339 floating-point registers. If so, return the number of fields and
7340 list them in FIELDS (which should have two elements). Return 0
7343 For n32 & n64, a structure with one or two fields is returned in
7344 floating-point registers as long as every field has a floating-point
7348 mips_fpr_return_fields (tree valtype, tree *fields)
7356 if (TREE_CODE (valtype) != RECORD_TYPE)
7360 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7362 if (TREE_CODE (field) != FIELD_DECL)
7365 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7371 fields[i++] = field;
7377 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7378 a value in the most significant part of $2/$3 if:
7380 - the target is big-endian;
7382 - the value has a structure or union type (we generalize this to
7383 cover aggregates from other languages too); and
7385 - the structure is not returned in floating-point registers. */
7388 mips_return_in_msb (tree valtype)
7392 return (TARGET_NEWABI
7393 && TARGET_BIG_ENDIAN
7394 && AGGREGATE_TYPE_P (valtype)
7395 && mips_fpr_return_fields (valtype, fields) == 0);
7399 /* Return a composite value in a pair of floating-point registers.
7400 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7401 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7404 For n32 & n64, $f0 always holds the first value and $f2 the second.
7405 Otherwise the values are packed together as closely as possible. */
7408 mips_return_fpr_pair (enum machine_mode mode,
7409 enum machine_mode mode1, HOST_WIDE_INT offset1,
7410 enum machine_mode mode2, HOST_WIDE_INT offset2)
7414 inc = (TARGET_NEWABI ? 2 : FP_INC);
7415 return gen_rtx_PARALLEL
7418 gen_rtx_EXPR_LIST (VOIDmode,
7419 gen_rtx_REG (mode1, FP_RETURN),
7421 gen_rtx_EXPR_LIST (VOIDmode,
7422 gen_rtx_REG (mode2, FP_RETURN + inc),
7423 GEN_INT (offset2))));
7428 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7429 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7430 VALTYPE is null and MODE is the mode of the return value. */
7433 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7434 enum machine_mode mode)
7441 mode = TYPE_MODE (valtype);
7442 unsignedp = TYPE_UNSIGNED (valtype);
7444 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7445 true, we must promote the mode just as PROMOTE_MODE does. */
7446 mode = promote_mode (valtype, mode, &unsignedp, 1);
7448 /* Handle structures whose fields are returned in $f0/$f2. */
7449 switch (mips_fpr_return_fields (valtype, fields))
7452 return gen_rtx_REG (mode, FP_RETURN);
7455 return mips_return_fpr_pair (mode,
7456 TYPE_MODE (TREE_TYPE (fields[0])),
7457 int_byte_position (fields[0]),
7458 TYPE_MODE (TREE_TYPE (fields[1])),
7459 int_byte_position (fields[1]));
7462 /* If a value is passed in the most significant part of a register, see
7463 whether we have to round the mode up to a whole number of words. */
7464 if (mips_return_in_msb (valtype))
7466 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7467 if (size % UNITS_PER_WORD != 0)
7469 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7470 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7474 /* For EABI, the class of return register depends entirely on MODE.
7475 For example, "struct { some_type x; }" and "union { some_type x; }"
7476 are returned in the same way as a bare "some_type" would be.
7477 Other ABIs only use FPRs for scalar, complex or vector types. */
7478 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7479 return gen_rtx_REG (mode, GP_RETURN);
7482 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7483 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7484 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7485 return gen_rtx_REG (mode, FP_RETURN);
7487 /* Handle long doubles for n32 & n64. */
7489 return mips_return_fpr_pair (mode,
7491 DImode, GET_MODE_SIZE (mode) / 2);
7493 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7494 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7495 return mips_return_fpr_pair (mode,
7496 GET_MODE_INNER (mode), 0,
7497 GET_MODE_INNER (mode),
7498 GET_MODE_SIZE (mode) / 2);
7500 return gen_rtx_REG (mode, GP_RETURN);
7503 /* Return nonzero when an argument must be passed by reference. */
7506 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7507 enum machine_mode mode, tree type,
7508 bool named ATTRIBUTE_UNUSED)
7510 if (mips_abi == ABI_EABI)
7514 /* ??? How should SCmode be handled? */
7515 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7518 size = int_size_in_bytes (type);
7519 return size == -1 || size > UNITS_PER_WORD;
7523 /* If we have a variable-sized parameter, we have no choice. */
7524 return targetm.calls.must_pass_in_stack (mode, type);
7529 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7530 enum machine_mode mode ATTRIBUTE_UNUSED,
7531 tree type ATTRIBUTE_UNUSED, bool named)
7533 return mips_abi == ABI_EABI && named;
7536 /* Return true if registers of class CLASS cannot change from mode FROM
7540 mips_cannot_change_mode_class (enum machine_mode from,
7541 enum machine_mode to, enum reg_class class)
7543 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7544 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7546 if (TARGET_BIG_ENDIAN)
7548 /* When a multi-word value is stored in paired floating-point
7549 registers, the first register always holds the low word.
7550 We therefore can't allow FPRs to change between single-word
7551 and multi-word modes. */
7552 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7557 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7558 in LO and HI, the high word always comes first. We therefore
7559 can't allow values stored in HI to change between single-word
7560 and multi-word modes.
7561 This rule applies to both the original HI/LO pair and the new
7562 DSP accumulators. */
7563 if (reg_classes_intersect_p (ACC_REGS, class))
7567 /* Loading a 32-bit value into a 64-bit floating-point register
7568 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7569 We can't allow 64-bit float registers to change from SImode to
7573 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7574 && reg_classes_intersect_p (FP_REGS, class))
7579 /* Return true if X should not be moved directly into register $25.
7580 We need this because many versions of GAS will treat "la $25,foo" as
7581 part of a call sequence and so allow a global "foo" to be lazily bound. */
7584 mips_dangerous_for_la25_p (rtx x)
7586 HOST_WIDE_INT offset;
7588 if (TARGET_EXPLICIT_RELOCS)
7591 mips_split_const (x, &x, &offset);
7592 return global_got_operand (x, VOIDmode);
7595 /* Implement PREFERRED_RELOAD_CLASS. */
7598 mips_preferred_reload_class (rtx x, enum reg_class class)
7600 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7603 if (TARGET_HARD_FLOAT
7604 && FLOAT_MODE_P (GET_MODE (x))
7605 && reg_class_subset_p (FP_REGS, class))
7608 if (reg_class_subset_p (GR_REGS, class))
7611 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7617 /* This function returns the register class required for a secondary
7618 register when copying between one of the registers in CLASS, and X,
7619 using MODE. If IN_P is nonzero, the copy is going from X to the
7620 register, otherwise the register is the source. A return value of
7621 NO_REGS means that no secondary register is required. */
7624 mips_secondary_reload_class (enum reg_class class,
7625 enum machine_mode mode, rtx x, int in_p)
7627 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7631 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7632 regno = true_regnum (x);
7634 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7636 if (mips_dangerous_for_la25_p (x))
7639 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7643 /* Copying from HI or LO to anywhere other than a general register
7644 requires a general register.
7645 This rule applies to both the original HI/LO pair and the new
7646 DSP accumulators. */
7647 if (reg_class_subset_p (class, ACC_REGS))
7649 if (TARGET_MIPS16 && in_p)
7651 /* We can't really copy to HI or LO at all in mips16 mode. */
7654 return gp_reg_p ? NO_REGS : gr_regs;
7656 if (ACC_REG_P (regno))
7658 if (TARGET_MIPS16 && ! in_p)
7660 /* We can't really copy to HI or LO at all in mips16 mode. */
7663 return class == gr_regs ? NO_REGS : gr_regs;
7666 /* We can only copy a value to a condition code register from a
7667 floating point register, and even then we require a scratch
7668 floating point register. We can only copy a value out of a
7669 condition code register into a general register. */
7670 if (class == ST_REGS)
7674 return gp_reg_p ? NO_REGS : gr_regs;
7676 if (ST_REG_P (regno))
7680 return class == gr_regs ? NO_REGS : gr_regs;
7683 if (class == FP_REGS)
7687 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7690 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7692 /* We can use the l.s and l.d macros to load floating-point
7693 constants. ??? For l.s, we could probably get better
7694 code by returning GR_REGS here. */
7697 else if (gp_reg_p || x == CONST0_RTX (mode))
7699 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7702 else if (FP_REG_P (regno))
7704 /* In this case we can use mov.s or mov.d. */
7709 /* Otherwise, we need to reload through an integer register. */
7714 /* In mips16 mode, going between memory and anything but M16_REGS
7715 requires an M16_REG. */
7718 if (class != M16_REGS && class != M16_NA_REGS)
7726 if (class == M16_REGS || class == M16_NA_REGS)
7735 /* Implement CLASS_MAX_NREGS.
7737 Usually all registers are word-sized. The only supported exception
7738 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7739 registers. A word-based calculation is correct even in that case,
7740 since -msingle-float disallows multi-FPR values.
7742 The FP status registers are an exception to this rule. They are always
7743 4 bytes wide as they only hold condition code modes, and CCmode is always
7744 considered to be 4 bytes wide. */
7747 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7748 enum machine_mode mode)
7750 if (class == ST_REGS)
7751 return (GET_MODE_SIZE (mode) + 3) / 4;
7753 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7757 mips_valid_pointer_mode (enum machine_mode mode)
7759 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7762 /* Target hook for vector_mode_supported_p. */
7765 mips_vector_mode_supported_p (enum machine_mode mode)
7770 return TARGET_PAIRED_SINGLE_FLOAT;
7781 /* If we can access small data directly (using gp-relative relocation
7782 operators) return the small data pointer, otherwise return null.
7784 For each mips16 function which refers to GP relative symbols, we
7785 use a pseudo register, initialized at the start of the function, to
7786 hold the $gp value. */
7789 mips16_gp_pseudo_reg (void)
7791 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7796 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7798 /* We want to initialize this to a value which gcc will believe
7801 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7802 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7803 gen_rtx_CONST (Pmode, unspec));
7804 insn = get_insns ();
7807 push_topmost_sequence ();
7808 /* We need to emit the initialization after the FUNCTION_BEG
7809 note, so that it will be integrated. */
7810 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7812 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7814 if (scan == NULL_RTX)
7815 scan = get_insns ();
7816 insn = emit_insn_after (insn, scan);
7817 pop_topmost_sequence ();
7820 return cfun->machine->mips16_gp_pseudo_rtx;
7823 /* Write out code to move floating point arguments in or out of
7824 general registers. Output the instructions to FILE. FP_CODE is
7825 the code describing which arguments are present (see the comment at
7826 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7827 we are copying from the floating point registers. */
7830 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7836 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7837 gcc_assert (TARGET_OLDABI);
7843 gparg = GP_ARG_FIRST;
7844 fparg = FP_ARG_FIRST;
7845 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7849 if ((fparg & 1) != 0)
7851 fprintf (file, "\t%s\t%s,%s\n", s,
7852 reg_names[gparg], reg_names[fparg]);
7854 else if ((f & 3) == 2)
7857 fprintf (file, "\td%s\t%s,%s\n", s,
7858 reg_names[gparg], reg_names[fparg]);
7861 if ((fparg & 1) != 0)
7863 if (TARGET_BIG_ENDIAN)
7864 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7865 reg_names[gparg], reg_names[fparg + 1], s,
7866 reg_names[gparg + 1], reg_names[fparg]);
7868 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7869 reg_names[gparg], reg_names[fparg], s,
7870 reg_names[gparg + 1], reg_names[fparg + 1]);
7883 /* Build a mips16 function stub. This is used for functions which
7884 take arguments in the floating point registers. It is 32 bit code
7885 that moves the floating point args into the general registers, and
7886 then jumps to the 16 bit code. */
7889 build_mips16_function_stub (FILE *file)
7892 char *secname, *stubname;
7893 tree stubid, stubdecl;
7897 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7898 secname = (char *) alloca (strlen (fnname) + 20);
7899 sprintf (secname, ".mips16.fn.%s", fnname);
7900 stubname = (char *) alloca (strlen (fnname) + 20);
7901 sprintf (stubname, "__fn_stub_%s", fnname);
7902 stubid = get_identifier (stubname);
7903 stubdecl = build_decl (FUNCTION_DECL, stubid,
7904 build_function_type (void_type_node, NULL_TREE));
7905 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7907 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7909 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7911 fprintf (file, "%s%s",
7912 need_comma ? ", " : "",
7913 (f & 3) == 1 ? "float" : "double");
7916 fprintf (file, ")\n");
7918 fprintf (file, "\t.set\tnomips16\n");
7919 switch_to_section (function_section (stubdecl));
7920 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7922 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7923 within a .ent, and we cannot emit another .ent. */
7924 if (!FUNCTION_NAME_ALREADY_DECLARED)
7926 fputs ("\t.ent\t", file);
7927 assemble_name (file, stubname);
7931 assemble_name (file, stubname);
7932 fputs (":\n", file);
7934 /* We don't want the assembler to insert any nops here. */
7935 fprintf (file, "\t.set\tnoreorder\n");
7937 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7939 fprintf (asm_out_file, "\t.set\tnoat\n");
7940 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7941 assemble_name (file, fnname);
7942 fprintf (file, "\n");
7943 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7944 fprintf (asm_out_file, "\t.set\tat\n");
7946 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7947 with one of the mfc1 instructions, because the result is not
7948 available for one instruction, so if the very first instruction
7949 in the function refers to the register, it will see the wrong
7951 fprintf (file, "\tnop\n");
7953 fprintf (file, "\t.set\treorder\n");
7955 if (!FUNCTION_NAME_ALREADY_DECLARED)
7957 fputs ("\t.end\t", file);
7958 assemble_name (file, stubname);
7962 fprintf (file, "\t.set\tmips16\n");
7964 switch_to_section (function_section (current_function_decl));
7967 /* We keep a list of functions for which we have already built stubs
7968 in build_mips16_call_stub. */
7972 struct mips16_stub *next;
7977 static struct mips16_stub *mips16_stubs;
7979 /* Build a call stub for a mips16 call. A stub is needed if we are
7980 passing any floating point values which should go into the floating
7981 point registers. If we are, and the call turns out to be to a 32
7982 bit function, the stub will be used to move the values into the
7983 floating point registers before calling the 32 bit function. The
7984 linker will magically adjust the function call to either the 16 bit
7985 function or the 32 bit stub, depending upon where the function call
7986 is actually defined.
7988 Similarly, we need a stub if the return value might come back in a
7989 floating point register.
7991 RETVAL is the location of the return value, or null if this is
7992 a call rather than a call_value. FN is the address of the
7993 function and ARG_SIZE is the size of the arguments. FP_CODE
7994 is the code built by function_arg. This function returns a nonzero
7995 value if it builds the call instruction itself. */
7998 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8002 char *secname, *stubname;
8003 struct mips16_stub *l;
8004 tree stubid, stubdecl;
8008 /* We don't need to do anything if we aren't in mips16 mode, or if
8009 we were invoked with the -msoft-float option. */
8010 if (! TARGET_MIPS16 || ! mips16_hard_float)
8013 /* Figure out whether the value might come back in a floating point
8015 fpret = (retval != 0
8016 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8017 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8019 /* We don't need to do anything if there were no floating point
8020 arguments and the value will not be returned in a floating point
8022 if (fp_code == 0 && ! fpret)
8025 /* We don't need to do anything if this is a call to a special
8026 mips16 support function. */
8027 if (GET_CODE (fn) == SYMBOL_REF
8028 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8031 /* This code will only work for o32 and o64 abis. The other ABI's
8032 require more sophisticated support. */
8033 gcc_assert (TARGET_OLDABI);
8035 /* We can only handle SFmode and DFmode floating point return
8038 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
8040 /* If we're calling via a function pointer, then we must always call
8041 via a stub. There are magic stubs provided in libgcc.a for each
8042 of the required cases. Each of them expects the function address
8043 to arrive in register $2. */
8045 if (GET_CODE (fn) != SYMBOL_REF)
8051 /* ??? If this code is modified to support other ABI's, we need
8052 to handle PARALLEL return values here. */
8054 sprintf (buf, "__mips16_call_stub_%s%d",
8056 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8059 id = get_identifier (buf);
8060 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8062 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8064 if (retval == NULL_RTX)
8065 insn = gen_call_internal (stub_fn, arg_size);
8067 insn = gen_call_value_internal (retval, stub_fn, arg_size);
8068 insn = emit_call_insn (insn);
8070 /* Put the register usage information on the CALL. */
8071 CALL_INSN_FUNCTION_USAGE (insn) =
8072 gen_rtx_EXPR_LIST (VOIDmode,
8073 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8074 CALL_INSN_FUNCTION_USAGE (insn));
8076 /* If we are handling a floating point return value, we need to
8077 save $18 in the function prologue. Putting a note on the
8078 call will mean that regs_ever_live[$18] will be true if the
8079 call is not eliminated, and we can check that in the prologue
8082 CALL_INSN_FUNCTION_USAGE (insn) =
8083 gen_rtx_EXPR_LIST (VOIDmode,
8084 gen_rtx_USE (VOIDmode,
8085 gen_rtx_REG (word_mode, 18)),
8086 CALL_INSN_FUNCTION_USAGE (insn));
8088 /* Return 1 to tell the caller that we've generated the call
8093 /* We know the function we are going to call. If we have already
8094 built a stub, we don't need to do anything further. */
8096 fnname = XSTR (fn, 0);
8097 for (l = mips16_stubs; l != NULL; l = l->next)
8098 if (strcmp (l->name, fnname) == 0)
8103 /* Build a special purpose stub. When the linker sees a
8104 function call in mips16 code, it will check where the target
8105 is defined. If the target is a 32 bit call, the linker will
8106 search for the section defined here. It can tell which
8107 symbol this section is associated with by looking at the
8108 relocation information (the name is unreliable, since this
8109 might be a static function). If such a section is found, the
8110 linker will redirect the call to the start of the magic
8113 If the function does not return a floating point value, the
8114 special stub section is named
8117 If the function does return a floating point value, the stub
8119 .mips16.call.fp.FNNAME
8122 secname = (char *) alloca (strlen (fnname) + 40);
8123 sprintf (secname, ".mips16.call.%s%s",
8126 stubname = (char *) alloca (strlen (fnname) + 20);
8127 sprintf (stubname, "__call_stub_%s%s",
8130 stubid = get_identifier (stubname);
8131 stubdecl = build_decl (FUNCTION_DECL, stubid,
8132 build_function_type (void_type_node, NULL_TREE));
8133 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8135 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8137 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8141 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8143 fprintf (asm_out_file, "%s%s",
8144 need_comma ? ", " : "",
8145 (f & 3) == 1 ? "float" : "double");
8148 fprintf (asm_out_file, ")\n");
8150 fprintf (asm_out_file, "\t.set\tnomips16\n");
8151 assemble_start_function (stubdecl, stubname);
8153 if (!FUNCTION_NAME_ALREADY_DECLARED)
8155 fputs ("\t.ent\t", asm_out_file);
8156 assemble_name (asm_out_file, stubname);
8157 fputs ("\n", asm_out_file);
8159 assemble_name (asm_out_file, stubname);
8160 fputs (":\n", asm_out_file);
8163 /* We build the stub code by hand. That's the only way we can
8164 do it, since we can't generate 32 bit code during a 16 bit
8167 /* We don't want the assembler to insert any nops here. */
8168 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8170 mips16_fp_args (asm_out_file, fp_code, 0);
8174 fprintf (asm_out_file, "\t.set\tnoat\n");
8175 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8177 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8178 fprintf (asm_out_file, "\t.set\tat\n");
8179 /* Unfortunately, we can't fill the jump delay slot. We
8180 can't fill with one of the mtc1 instructions, because the
8181 result is not available for one instruction, so if the
8182 very first instruction in the function refers to the
8183 register, it will see the wrong value. */
8184 fprintf (asm_out_file, "\tnop\n");
8188 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8189 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8190 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8191 /* As above, we can't fill the delay slot. */
8192 fprintf (asm_out_file, "\tnop\n");
8193 if (GET_MODE (retval) == SFmode)
8194 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8195 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8198 if (TARGET_BIG_ENDIAN)
8200 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8201 reg_names[GP_REG_FIRST + 2],
8202 reg_names[FP_REG_FIRST + 1]);
8203 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8204 reg_names[GP_REG_FIRST + 3],
8205 reg_names[FP_REG_FIRST + 0]);
8209 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8210 reg_names[GP_REG_FIRST + 2],
8211 reg_names[FP_REG_FIRST + 0]);
8212 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8213 reg_names[GP_REG_FIRST + 3],
8214 reg_names[FP_REG_FIRST + 1]);
8217 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8218 /* As above, we can't fill the delay slot. */
8219 fprintf (asm_out_file, "\tnop\n");
8222 fprintf (asm_out_file, "\t.set\treorder\n");
8224 #ifdef ASM_DECLARE_FUNCTION_SIZE
8225 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8228 if (!FUNCTION_NAME_ALREADY_DECLARED)
8230 fputs ("\t.end\t", asm_out_file);
8231 assemble_name (asm_out_file, stubname);
8232 fputs ("\n", asm_out_file);
8235 fprintf (asm_out_file, "\t.set\tmips16\n");
8237 /* Record this stub. */
8238 l = (struct mips16_stub *) xmalloc (sizeof *l);
8239 l->name = xstrdup (fnname);
8241 l->next = mips16_stubs;
8245 /* If we expect a floating point return value, but we've built a
8246 stub which does not expect one, then we're in trouble. We can't
8247 use the existing stub, because it won't handle the floating point
8248 value. We can't build a new stub, because the linker won't know
8249 which stub to use for the various calls in this object file.
8250 Fortunately, this case is illegal, since it means that a function
8251 was declared in two different ways in a single compilation. */
8252 if (fpret && ! l->fpret)
8253 error ("cannot handle inconsistent calls to %qs", fnname);
8255 /* If we are calling a stub which handles a floating point return
8256 value, we need to arrange to save $18 in the prologue. We do
8257 this by marking the function call as using the register. The
8258 prologue will later see that it is used, and emit code to save
8265 if (retval == NULL_RTX)
8266 insn = gen_call_internal (fn, arg_size);
8268 insn = gen_call_value_internal (retval, fn, arg_size);
8269 insn = emit_call_insn (insn);
8271 CALL_INSN_FUNCTION_USAGE (insn) =
8272 gen_rtx_EXPR_LIST (VOIDmode,
8273 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8274 CALL_INSN_FUNCTION_USAGE (insn));
8276 /* Return 1 to tell the caller that we've generated the call
8281 /* Return 0 to let the caller generate the call insn. */
8285 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8286 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8288 struct mips16_constant {
8289 struct mips16_constant *next;
8292 enum machine_mode mode;
8295 /* Information about an incomplete mips16 constant pool. FIRST is the
8296 first constant, HIGHEST_ADDRESS is the highest address that the first
8297 byte of the pool can have, and INSN_ADDRESS is the current instruction
8300 struct mips16_constant_pool {
8301 struct mips16_constant *first;
8302 int highest_address;
8306 /* Add constant VALUE to POOL and return its label. MODE is the
8307 value's mode (used for CONST_INTs, etc.). */
8310 add_constant (struct mips16_constant_pool *pool,
8311 rtx value, enum machine_mode mode)
8313 struct mips16_constant **p, *c;
8314 bool first_of_size_p;
8316 /* See whether the constant is already in the pool. If so, return the
8317 existing label, otherwise leave P pointing to the place where the
8318 constant should be added.
8320 Keep the pool sorted in increasing order of mode size so that we can
8321 reduce the number of alignments needed. */
8322 first_of_size_p = true;
8323 for (p = &pool->first; *p != 0; p = &(*p)->next)
8325 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8327 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8329 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8330 first_of_size_p = false;
8333 /* In the worst case, the constant needed by the earliest instruction
8334 will end up at the end of the pool. The entire pool must then be
8335 accessible from that instruction.
8337 When adding the first constant, set the pool's highest address to
8338 the address of the first out-of-range byte. Adjust this address
8339 downwards each time a new constant is added. */
8340 if (pool->first == 0)
8341 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8342 is the address of the instruction with the lowest two bits clear.
8343 The base PC value for ld has the lowest three bits clear. Assume
8344 the worst case here. */
8345 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8346 pool->highest_address -= GET_MODE_SIZE (mode);
8347 if (first_of_size_p)
8348 /* Take into account the worst possible padding due to alignment. */
8349 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8351 /* Create a new entry. */
8352 c = (struct mips16_constant *) xmalloc (sizeof *c);
8355 c->label = gen_label_rtx ();
8362 /* Output constant VALUE after instruction INSN and return the last
8363 instruction emitted. MODE is the mode of the constant. */
8366 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8368 switch (GET_MODE_CLASS (mode))
8372 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8373 return emit_insn_after (gen_consttable_int (value, size), insn);
8377 return emit_insn_after (gen_consttable_float (value), insn);
8379 case MODE_VECTOR_FLOAT:
8380 case MODE_VECTOR_INT:
8383 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8384 insn = dump_constants_1 (GET_MODE_INNER (mode),
8385 CONST_VECTOR_ELT (value, i), insn);
8395 /* Dump out the constants in CONSTANTS after INSN. */
8398 dump_constants (struct mips16_constant *constants, rtx insn)
8400 struct mips16_constant *c, *next;
8404 for (c = constants; c != NULL; c = next)
8406 /* If necessary, increase the alignment of PC. */
8407 if (align < GET_MODE_SIZE (c->mode))
8409 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8410 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8412 align = GET_MODE_SIZE (c->mode);
8414 insn = emit_label_after (c->label, insn);
8415 insn = dump_constants_1 (c->mode, c->value, insn);
8421 emit_barrier_after (insn);
8424 /* Return the length of instruction INSN. */
8427 mips16_insn_length (rtx insn)
8431 rtx body = PATTERN (insn);
8432 if (GET_CODE (body) == ADDR_VEC)
8433 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8434 if (GET_CODE (body) == ADDR_DIFF_VEC)
8435 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8437 return get_attr_length (insn);
8440 /* Rewrite *X so that constant pool references refer to the constant's
8441 label instead. DATA points to the constant pool structure. */
8444 mips16_rewrite_pool_refs (rtx *x, void *data)
8446 struct mips16_constant_pool *pool = data;
8447 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8448 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8449 get_pool_constant (*x),
8450 get_pool_mode (*x)));
8454 /* Build MIPS16 constant pools. */
8457 mips16_lay_out_constants (void)
8459 struct mips16_constant_pool pool;
8463 memset (&pool, 0, sizeof (pool));
8464 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8466 /* Rewrite constant pool references in INSN. */
8468 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8470 pool.insn_address += mips16_insn_length (insn);
8472 if (pool.first != NULL)
8474 /* If there are no natural barriers between the first user of
8475 the pool and the highest acceptable address, we'll need to
8476 create a new instruction to jump around the constant pool.
8477 In the worst case, this instruction will be 4 bytes long.
8479 If it's too late to do this transformation after INSN,
8480 do it immediately before INSN. */
8481 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8485 label = gen_label_rtx ();
8487 jump = emit_jump_insn_before (gen_jump (label), insn);
8488 JUMP_LABEL (jump) = label;
8489 LABEL_NUSES (label) = 1;
8490 barrier = emit_barrier_after (jump);
8492 emit_label_after (label, barrier);
8493 pool.insn_address += 4;
8496 /* See whether the constant pool is now out of range of the first
8497 user. If so, output the constants after the previous barrier.
8498 Note that any instructions between BARRIER and INSN (inclusive)
8499 will use negative offsets to refer to the pool. */
8500 if (pool.insn_address > pool.highest_address)
8502 dump_constants (pool.first, barrier);
8506 else if (BARRIER_P (insn))
8510 dump_constants (pool.first, get_last_insn ());
8513 /* A temporary variable used by for_each_rtx callbacks, etc. */
8514 static rtx mips_sim_insn;
8516 /* A structure representing the state of the processor pipeline.
8517 Used by the mips_sim_* family of functions. */
8519 /* The maximum number of instructions that can be issued in a cycle.
8520 (Caches mips_issue_rate.) */
8521 unsigned int issue_rate;
8523 /* The current simulation time. */
8526 /* How many more instructions can be issued in the current cycle. */
8527 unsigned int insns_left;
8529 /* LAST_SET[X].INSN is the last instruction to set register X.
8530 LAST_SET[X].TIME is the time at which that instruction was issued.
8531 INSN is null if no instruction has yet set register X. */
8535 } last_set[FIRST_PSEUDO_REGISTER];
8537 /* The pipeline's current DFA state. */
8541 /* Reset STATE to the initial simulation state. */
8544 mips_sim_reset (struct mips_sim *state)
8547 state->insns_left = state->issue_rate;
8548 memset (&state->last_set, 0, sizeof (state->last_set));
8549 state_reset (state->dfa_state);
8552 /* Initialize STATE before its first use. DFA_STATE points to an
8553 allocated but uninitialized DFA state. */
8556 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8558 state->issue_rate = mips_issue_rate ();
8559 state->dfa_state = dfa_state;
8560 mips_sim_reset (state);
8563 /* Advance STATE by one clock cycle. */
8566 mips_sim_next_cycle (struct mips_sim *state)
8569 state->insns_left = state->issue_rate;
8570 state_transition (state->dfa_state, 0);
8573 /* Advance simulation state STATE until instruction INSN can read
8577 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8581 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8582 if (state->last_set[REGNO (reg) + i].insn != 0)
8586 t = state->last_set[REGNO (reg) + i].time;
8587 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8588 while (state->time < t)
8589 mips_sim_next_cycle (state);
8593 /* A for_each_rtx callback. If *X is a register, advance simulation state
8594 DATA until mips_sim_insn can read the register's value. */
8597 mips_sim_wait_regs_2 (rtx *x, void *data)
8600 mips_sim_wait_reg (data, mips_sim_insn, *x);
8604 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8607 mips_sim_wait_regs_1 (rtx *x, void *data)
8609 for_each_rtx (x, mips_sim_wait_regs_2, data);
8612 /* Advance simulation state STATE until all of INSN's register
8613 dependencies are satisfied. */
8616 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8618 mips_sim_insn = insn;
8619 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8622 /* Advance simulation state STATE until the units required by
8623 instruction INSN are available. */
8626 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8630 tmp_state = alloca (state_size ());
8631 while (state->insns_left == 0
8632 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8633 state_transition (tmp_state, insn) >= 0))
8634 mips_sim_next_cycle (state);
8637 /* Advance simulation state STATE until INSN is ready to issue. */
8640 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8642 mips_sim_wait_regs (state, insn);
8643 mips_sim_wait_units (state, insn);
8646 /* mips_sim_insn has just set X. Update the LAST_SET array
8647 in simulation state DATA. */
8650 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8652 struct mips_sim *state;
8657 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8659 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8660 state->last_set[REGNO (x) + i].time = state->time;
8664 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8665 can issue immediately (i.e., that mips_sim_wait_insn has already
8669 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8671 state_transition (state->dfa_state, insn);
8672 state->insns_left--;
8674 mips_sim_insn = insn;
8675 note_stores (PATTERN (insn), mips_sim_record_set, state);
8678 /* Simulate issuing a NOP in state STATE. */
8681 mips_sim_issue_nop (struct mips_sim *state)
8683 if (state->insns_left == 0)
8684 mips_sim_next_cycle (state);
8685 state->insns_left--;
8688 /* Update simulation state STATE so that it's ready to accept the instruction
8689 after INSN. INSN should be part of the main rtl chain, not a member of a
8693 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8695 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8697 mips_sim_issue_nop (state);
8699 switch (GET_CODE (SEQ_BEGIN (insn)))
8703 /* We can't predict the processor state after a call or label. */
8704 mips_sim_reset (state);
8708 /* The delay slots of branch likely instructions are only executed
8709 when the branch is taken. Therefore, if the caller has simulated
8710 the delay slot instruction, STATE does not really reflect the state
8711 of the pipeline for the instruction after the delay slot. Also,
8712 branch likely instructions tend to incur a penalty when not taken,
8713 so there will probably be an extra delay between the branch and
8714 the instruction after the delay slot. */
8715 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8716 mips_sim_reset (state);
8724 /* The VR4130 pipeline issues aligned pairs of instructions together,
8725 but it stalls the second instruction if it depends on the first.
8726 In order to cut down the amount of logic required, this dependence
8727 check is not based on a full instruction decode. Instead, any non-SPECIAL
8728 instruction is assumed to modify the register specified by bits 20-16
8729 (which is usually the "rt" field).
8731 In beq, beql, bne and bnel instructions, the rt field is actually an
8732 input, so we can end up with a false dependence between the branch
8733 and its delay slot. If this situation occurs in instruction INSN,
8734 try to avoid it by swapping rs and rt. */
8737 vr4130_avoid_branch_rt_conflict (rtx insn)
8741 first = SEQ_BEGIN (insn);
8742 second = SEQ_END (insn);
8744 && NONJUMP_INSN_P (second)
8745 && GET_CODE (PATTERN (first)) == SET
8746 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8747 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8749 /* Check for the right kind of condition. */
8750 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8751 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8752 && REG_P (XEXP (cond, 0))
8753 && REG_P (XEXP (cond, 1))
8754 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8755 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8757 /* SECOND mentions the rt register but not the rs register. */
8758 rtx tmp = XEXP (cond, 0);
8759 XEXP (cond, 0) = XEXP (cond, 1);
8760 XEXP (cond, 1) = tmp;
8765 /* Implement -mvr4130-align. Go through each basic block and simulate the
8766 processor pipeline. If we find that a pair of instructions could execute
8767 in parallel, and the first of those instruction is not 8-byte aligned,
8768 insert a nop to make it aligned. */
8771 vr4130_align_insns (void)
8773 struct mips_sim state;
8774 rtx insn, subinsn, last, last2, next;
8779 /* LAST is the last instruction before INSN to have a nonzero length.
8780 LAST2 is the last such instruction before LAST. */
8784 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8787 mips_sim_init (&state, alloca (state_size ()));
8788 for (insn = get_insns (); insn != 0; insn = next)
8790 unsigned int length;
8792 next = NEXT_INSN (insn);
8794 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8795 This isn't really related to the alignment pass, but we do it on
8796 the fly to avoid a separate instruction walk. */
8797 vr4130_avoid_branch_rt_conflict (insn);
8799 if (USEFUL_INSN_P (insn))
8800 FOR_EACH_SUBINSN (subinsn, insn)
8802 mips_sim_wait_insn (&state, subinsn);
8804 /* If we want this instruction to issue in parallel with the
8805 previous one, make sure that the previous instruction is
8806 aligned. There are several reasons why this isn't worthwhile
8807 when the second instruction is a call:
8809 - Calls are less likely to be performance critical,
8810 - There's a good chance that the delay slot can execute
8811 in parallel with the call.
8812 - The return address would then be unaligned.
8814 In general, if we're going to insert a nop between instructions
8815 X and Y, it's better to insert it immediately after X. That
8816 way, if the nop makes Y aligned, it will also align any labels
8818 if (state.insns_left != state.issue_rate
8819 && !CALL_P (subinsn))
8821 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8823 /* SUBINSN is the first instruction in INSN and INSN is
8824 aligned. We want to align the previous instruction
8825 instead, so insert a nop between LAST2 and LAST.
8827 Note that LAST could be either a single instruction
8828 or a branch with a delay slot. In the latter case,
8829 LAST, like INSN, is already aligned, but the delay
8830 slot must have some extra delay that stops it from
8831 issuing at the same time as the branch. We therefore
8832 insert a nop before the branch in order to align its
8834 emit_insn_after (gen_nop (), last2);
8837 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8839 /* SUBINSN is the delay slot of INSN, but INSN is
8840 currently unaligned. Insert a nop between
8841 LAST and INSN to align it. */
8842 emit_insn_after (gen_nop (), last);
8846 mips_sim_issue_insn (&state, subinsn);
8848 mips_sim_finish_insn (&state, insn);
8850 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8851 length = get_attr_length (insn);
8854 /* If the instruction is an asm statement or multi-instruction
8855 mips.md patern, the length is only an estimate. Insert an
8856 8 byte alignment after it so that the following instructions
8857 can be handled correctly. */
8858 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8859 && (recog_memoized (insn) < 0 || length >= 8))
8861 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8862 next = NEXT_INSN (next);
8863 mips_sim_next_cycle (&state);
8866 else if (length & 4)
8867 aligned_p = !aligned_p;
8872 /* See whether INSN is an aligned label. */
8873 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8879 /* Subroutine of mips_reorg. If there is a hazard between INSN
8880 and a previous instruction, avoid it by inserting nops after
8883 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8884 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8885 before using the value of that register. *HILO_DELAY counts the
8886 number of instructions since the last hilo hazard (that is,
8887 the number of instructions since the last mflo or mfhi).
8889 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8890 for the next instruction.
8892 LO_REG is an rtx for the LO register, used in dependence checking. */
8895 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8896 rtx *delayed_reg, rtx lo_reg)
8904 pattern = PATTERN (insn);
8906 /* Do not put the whole function in .set noreorder if it contains
8907 an asm statement. We don't know whether there will be hazards
8908 between the asm statement and the gcc-generated code. */
8909 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8910 cfun->machine->all_noreorder_p = false;
8912 /* Ignore zero-length instructions (barriers and the like). */
8913 ninsns = get_attr_length (insn) / 4;
8917 /* Work out how many nops are needed. Note that we only care about
8918 registers that are explicitly mentioned in the instruction's pattern.
8919 It doesn't matter that calls use the argument registers or that they
8920 clobber hi and lo. */
8921 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8922 nops = 2 - *hilo_delay;
8923 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8928 /* Insert the nops between this instruction and the previous one.
8929 Each new nop takes us further from the last hilo hazard. */
8930 *hilo_delay += nops;
8932 emit_insn_after (gen_hazard_nop (), after);
8934 /* Set up the state for the next instruction. */
8935 *hilo_delay += ninsns;
8937 if (INSN_CODE (insn) >= 0)
8938 switch (get_attr_hazard (insn))
8948 set = single_set (insn);
8949 gcc_assert (set != 0);
8950 *delayed_reg = SET_DEST (set);
8956 /* Go through the instruction stream and insert nops where necessary.
8957 See if the whole function can then be put into .set noreorder &
8961 mips_avoid_hazards (void)
8963 rtx insn, last_insn, lo_reg, delayed_reg;
8966 /* Force all instructions to be split into their final form. */
8967 split_all_insns_noflow ();
8969 /* Recalculate instruction lengths without taking nops into account. */
8970 cfun->machine->ignore_hazard_length_p = true;
8971 shorten_branches (get_insns ());
8973 cfun->machine->all_noreorder_p = true;
8975 /* Profiled functions can't be all noreorder because the profiler
8976 support uses assembler macros. */
8977 if (current_function_profile)
8978 cfun->machine->all_noreorder_p = false;
8980 /* Code compiled with -mfix-vr4120 can't be all noreorder because
8981 we rely on the assembler to work around some errata. */
8982 if (TARGET_FIX_VR4120)
8983 cfun->machine->all_noreorder_p = false;
8985 /* The same is true for -mfix-vr4130 if we might generate mflo or
8986 mfhi instructions. Note that we avoid using mflo and mfhi if
8987 the VR4130 macc and dmacc instructions are available instead;
8988 see the *mfhilo_{si,di}_macc patterns. */
8989 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
8990 cfun->machine->all_noreorder_p = false;
8995 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8997 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9000 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9001 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9002 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
9003 &hilo_delay, &delayed_reg, lo_reg);
9005 mips_avoid_hazard (last_insn, insn, &hilo_delay,
9006 &delayed_reg, lo_reg);
9013 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
9019 mips16_lay_out_constants ();
9020 else if (TARGET_EXPLICIT_RELOCS)
9022 if (mips_flag_delayed_branch)
9023 dbr_schedule (get_insns ());
9024 mips_avoid_hazards ();
9025 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
9026 vr4130_align_insns ();
9030 /* This function does three things:
9032 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9033 - Register the mips16 hardware floating point stubs.
9034 - Register the gofast functions if selected using --enable-gofast. */
9036 #include "config/gofast.h"
9039 mips_init_libfuncs (void)
9041 if (TARGET_FIX_VR4120)
9043 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9044 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9047 if (TARGET_MIPS16 && mips16_hard_float)
9049 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9050 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9051 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9052 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9054 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9055 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9056 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9057 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9058 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9059 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9061 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9062 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9064 if (TARGET_DOUBLE_FLOAT)
9066 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9067 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9068 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9069 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9071 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9072 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9073 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9074 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9075 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9076 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9078 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
9079 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
9081 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
9082 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
9086 gofast_maybe_init_libfuncs ();
9089 /* Return a number assessing the cost of moving a register in class
9090 FROM to class TO. The classes are expressed using the enumeration
9091 values such as `GENERAL_REGS'. A value of 2 is the default; other
9092 values are interpreted relative to that.
9094 It is not required that the cost always equal 2 when FROM is the
9095 same as TO; on some machines it is expensive to move between
9096 registers if they are not general registers.
9098 If reload sees an insn consisting of a single `set' between two
9099 hard registers, and if `REGISTER_MOVE_COST' applied to their
9100 classes returns a value of 2, reload does not check to ensure that
9101 the constraints of the insn are met. Setting a cost of other than
9102 2 will allow reload to verify that the constraints are met. You
9103 should do this if the `movM' pattern's constraints do not allow
9106 ??? We make the cost of moving from HI/LO into general
9107 registers the same as for one of moving general registers to
9108 HI/LO for TARGET_MIPS16 in order to prevent allocating a
9109 pseudo to HI/LO. This might hurt optimizations though, it
9110 isn't clear if it is wise. And it might not work in all cases. We
9111 could solve the DImode LO reg problem by using a multiply, just
9112 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9113 problem by using divide instructions. divu puts the remainder in
9114 the HI reg, so doing a divide by -1 will move the value in the HI
9115 reg for all values except -1. We could handle that case by using a
9116 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9117 a compare/branch to test the input value to see which instruction
9118 we need to use. This gets pretty messy, but it is feasible. */
9121 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9122 enum reg_class to, enum reg_class from)
9124 if (from == M16_REGS && GR_REG_CLASS_P (to))
9126 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9128 else if (GR_REG_CLASS_P (from))
9132 else if (to == M16_NA_REGS)
9134 else if (GR_REG_CLASS_P (to))
9141 else if (to == FP_REGS)
9143 else if (reg_class_subset_p (to, ACC_REGS))
9150 else if (COP_REG_CLASS_P (to))
9155 else if (from == FP_REGS)
9157 if (GR_REG_CLASS_P (to))
9159 else if (to == FP_REGS)
9161 else if (to == ST_REGS)
9164 else if (reg_class_subset_p (from, ACC_REGS))
9166 if (GR_REG_CLASS_P (to))
9174 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9176 else if (COP_REG_CLASS_P (from))
9182 ??? What cases are these? Shouldn't we return 2 here? */
9187 /* Return the length of INSN. LENGTH is the initial length computed by
9188 attributes in the machine-description file. */
9191 mips_adjust_insn_length (rtx insn, int length)
9193 /* A unconditional jump has an unfilled delay slot if it is not part
9194 of a sequence. A conditional jump normally has a delay slot, but
9195 does not on MIPS16. */
9196 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9199 /* See how many nops might be needed to avoid hardware hazards. */
9200 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9201 switch (get_attr_hazard (insn))
9215 /* All MIPS16 instructions are a measly two bytes. */
9223 /* Return an asm sequence to start a noat block and load the address
9224 of a label into $1. */
9227 mips_output_load_label (void)
9229 if (TARGET_EXPLICIT_RELOCS)
9233 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9236 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9239 if (ISA_HAS_LOAD_DELAY)
9240 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9241 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9245 if (Pmode == DImode)
9246 return "%[dla\t%@,%0";
9248 return "%[la\t%@,%0";
9252 /* Return the assembly code for INSN, which has the operands given by
9253 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9254 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9255 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9256 version of BRANCH_IF_TRUE. */
9259 mips_output_conditional_branch (rtx insn, rtx *operands,
9260 const char *branch_if_true,
9261 const char *branch_if_false)
9263 unsigned int length;
9264 rtx taken, not_taken;
9266 length = get_attr_length (insn);
9269 /* Just a simple conditional branch. */
9270 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9271 return branch_if_true;
9274 /* Generate a reversed branch around a direct jump. This fallback does
9275 not use branch-likely instructions. */
9276 mips_branch_likely = false;
9277 not_taken = gen_label_rtx ();
9278 taken = operands[1];
9280 /* Generate the reversed branch to NOT_TAKEN. */
9281 operands[1] = not_taken;
9282 output_asm_insn (branch_if_false, operands);
9284 /* If INSN has a delay slot, we must provide delay slots for both the
9285 branch to NOT_TAKEN and the conditional jump. We must also ensure
9286 that INSN's delay slot is executed in the appropriate cases. */
9289 /* This first delay slot will always be executed, so use INSN's
9290 delay slot if is not annulled. */
9291 if (!INSN_ANNULLED_BRANCH_P (insn))
9293 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9294 asm_out_file, optimize, 1, NULL);
9295 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9298 output_asm_insn ("nop", 0);
9299 fprintf (asm_out_file, "\n");
9302 /* Output the unconditional branch to TAKEN. */
9304 output_asm_insn ("j\t%0%/", &taken);
9307 output_asm_insn (mips_output_load_label (), &taken);
9308 output_asm_insn ("jr\t%@%]%/", 0);
9311 /* Now deal with its delay slot; see above. */
9314 /* This delay slot will only be executed if the branch is taken.
9315 Use INSN's delay slot if is annulled. */
9316 if (INSN_ANNULLED_BRANCH_P (insn))
9318 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9319 asm_out_file, optimize, 1, NULL);
9320 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9323 output_asm_insn ("nop", 0);
9324 fprintf (asm_out_file, "\n");
9327 /* Output NOT_TAKEN. */
9328 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9329 CODE_LABEL_NUMBER (not_taken));
9333 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9334 if some ordered condition is true. The condition is given by
9335 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9336 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9337 its second is always zero. */
9340 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9342 const char *branch[2];
9344 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9345 Make BRANCH[0] branch on the inverse condition. */
9346 switch (GET_CODE (operands[0]))
9348 /* These cases are equivalent to comparisons against zero. */
9350 inverted_p = !inverted_p;
9353 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9354 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9357 /* These cases are always true or always false. */
9359 inverted_p = !inverted_p;
9362 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9363 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9367 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9368 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9371 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9374 /* Used to output div or ddiv instruction DIVISION, which has the operands
9375 given by OPERANDS. Add in a divide-by-zero check if needed.
9377 When working around R4000 and R4400 errata, we need to make sure that
9378 the division is not immediately followed by a shift[1][2]. We also
9379 need to stop the division from being put into a branch delay slot[3].
9380 The easiest way to avoid both problems is to add a nop after the
9381 division. When a divide-by-zero check is needed, this nop can be
9382 used to fill the branch delay slot.
9384 [1] If a double-word or a variable shift executes immediately
9385 after starting an integer division, the shift may give an
9386 incorrect result. See quotations of errata #16 and #28 from
9387 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9388 in mips.md for details.
9390 [2] A similar bug to [1] exists for all revisions of the
9391 R4000 and the R4400 when run in an MC configuration.
9392 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9394 "19. In this following sequence:
9396 ddiv (or ddivu or div or divu)
9397 dsll32 (or dsrl32, dsra32)
9399 if an MPT stall occurs, while the divide is slipping the cpu
9400 pipeline, then the following double shift would end up with an
9403 Workaround: The compiler needs to avoid generating any
9404 sequence with divide followed by extended double shift."
9406 This erratum is also present in "MIPS R4400MC Errata, Processor
9407 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9408 & 3.0" as errata #10 and #4, respectively.
9410 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9411 (also valid for MIPS R4000MC processors):
9413 "52. R4000SC: This bug does not apply for the R4000PC.
9415 There are two flavors of this bug:
9417 1) If the instruction just after divide takes an RF exception
9418 (tlb-refill, tlb-invalid) and gets an instruction cache
9419 miss (both primary and secondary) and the line which is
9420 currently in secondary cache at this index had the first
9421 data word, where the bits 5..2 are set, then R4000 would
9422 get a wrong result for the div.
9427 ------------------- # end-of page. -tlb-refill
9432 ------------------- # end-of page. -tlb-invalid
9435 2) If the divide is in the taken branch delay slot, where the
9436 target takes RF exception and gets an I-cache miss for the
9437 exception vector or where I-cache miss occurs for the
9438 target address, under the above mentioned scenarios, the
9439 div would get wrong results.
9442 j r2 # to next page mapped or unmapped
9443 div r8,r9 # this bug would be there as long
9444 # as there is an ICache miss and
9445 nop # the "data pattern" is present
9448 beq r0, r0, NextPage # to Next page
9452 This bug is present for div, divu, ddiv, and ddivu
9455 Workaround: For item 1), OS could make sure that the next page
9456 after the divide instruction is also mapped. For item 2), the
9457 compiler could make sure that the divide instruction is not in
9458 the branch delay slot."
9460 These processors have PRId values of 0x00004220 and 0x00004300 for
9461 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9464 mips_output_division (const char *division, rtx *operands)
9469 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9471 output_asm_insn (s, operands);
9474 if (TARGET_CHECK_ZERO_DIV)
9478 output_asm_insn (s, operands);
9479 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9481 else if (GENERATE_DIVIDE_TRAPS)
9483 output_asm_insn (s, operands);
9488 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9489 output_asm_insn (s, operands);
9490 s = "break\t7%)\n1:";
9496 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9497 with a final "000" replaced by "k". Ignore case.
9499 Note: this function is shared between GCC and GAS. */
9502 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9504 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9505 given++, canonical++;
9507 return ((*given == 0 && *canonical == 0)
9508 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9512 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9513 CPU name. We've traditionally allowed a lot of variation here.
9515 Note: this function is shared between GCC and GAS. */
9518 mips_matching_cpu_name_p (const char *canonical, const char *given)
9520 /* First see if the name matches exactly, or with a final "000"
9522 if (mips_strict_matching_cpu_name_p (canonical, given))
9525 /* If not, try comparing based on numerical designation alone.
9526 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9527 if (TOLOWER (*given) == 'r')
9529 if (!ISDIGIT (*given))
9532 /* Skip over some well-known prefixes in the canonical name,
9533 hoping to find a number there too. */
9534 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9536 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9538 else if (TOLOWER (canonical[0]) == 'r')
9541 return mips_strict_matching_cpu_name_p (canonical, given);
9545 /* Return the mips_cpu_info entry for the processor or ISA given
9546 by CPU_STRING. Return null if the string isn't recognized.
9548 A similar function exists in GAS. */
9550 static const struct mips_cpu_info *
9551 mips_parse_cpu (const char *cpu_string)
9553 const struct mips_cpu_info *p;
9556 /* In the past, we allowed upper-case CPU names, but it doesn't
9557 work well with the multilib machinery. */
9558 for (s = cpu_string; *s != 0; s++)
9561 warning (0, "the cpu name must be lower case");
9565 /* 'from-abi' selects the most compatible architecture for the given
9566 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9567 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9568 version. Look first at the -mgp options, if given, otherwise base
9569 the choice on MASK_64BIT in TARGET_DEFAULT. */
9570 if (strcasecmp (cpu_string, "from-abi") == 0)
9571 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9572 : ABI_NEEDS_64BIT_REGS ? 3
9573 : (TARGET_64BIT ? 3 : 1));
9575 /* 'default' has traditionally been a no-op. Probably not very useful. */
9576 if (strcasecmp (cpu_string, "default") == 0)
9579 for (p = mips_cpu_info_table; p->name != 0; p++)
9580 if (mips_matching_cpu_name_p (p->name, cpu_string))
9587 /* Return the processor associated with the given ISA level, or null
9588 if the ISA isn't valid. */
9590 static const struct mips_cpu_info *
9591 mips_cpu_info_from_isa (int isa)
9593 const struct mips_cpu_info *p;
9595 for (p = mips_cpu_info_table; p->name != 0; p++)
9602 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9603 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9604 they only hold condition code modes, and CCmode is always considered to
9605 be 4 bytes wide. All other registers are word sized. */
9608 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9610 if (ST_REG_P (regno))
9611 return ((GET_MODE_SIZE (mode) + 3) / 4);
9612 else if (! FP_REG_P (regno))
9613 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9615 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9618 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9619 all BLKmode objects are returned in memory. Under the new (N32 and
9620 64-bit MIPS ABIs) small structures are returned in a register.
9621 Objects with varying size must still be returned in memory, of
9625 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9628 return (TYPE_MODE (type) == BLKmode);
9630 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9631 || (int_size_in_bytes (type) == -1));
9635 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9637 return !TARGET_OLDABI;
9640 /* Return true if INSN is a multiply-add or multiply-subtract
9641 instruction and PREV assigns to the accumulator operand. */
9644 mips_linked_madd_p (rtx prev, rtx insn)
9648 x = single_set (insn);
9654 if (GET_CODE (x) == PLUS
9655 && GET_CODE (XEXP (x, 0)) == MULT
9656 && reg_set_p (XEXP (x, 1), prev))
9659 if (GET_CODE (x) == MINUS
9660 && GET_CODE (XEXP (x, 1)) == MULT
9661 && reg_set_p (XEXP (x, 0), prev))
9667 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9668 that may clobber hi or lo. */
9670 static rtx mips_macc_chains_last_hilo;
9672 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9673 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9676 mips_macc_chains_record (rtx insn)
9678 if (get_attr_may_clobber_hilo (insn))
9679 mips_macc_chains_last_hilo = insn;
9682 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9683 has NREADY elements, looking for a multiply-add or multiply-subtract
9684 instruction that is cumulative with mips_macc_chains_last_hilo.
9685 If there is one, promote it ahead of anything else that might
9686 clobber hi or lo. */
9689 mips_macc_chains_reorder (rtx *ready, int nready)
9693 if (mips_macc_chains_last_hilo != 0)
9694 for (i = nready - 1; i >= 0; i--)
9695 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9697 for (j = nready - 1; j > i; j--)
9698 if (recog_memoized (ready[j]) >= 0
9699 && get_attr_may_clobber_hilo (ready[j]))
9701 mips_promote_ready (ready, i, j);
9708 /* The last instruction to be scheduled. */
9710 static rtx vr4130_last_insn;
9712 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9713 points to an rtx that is initially an instruction. Nullify the rtx
9714 if the instruction uses the value of register X. */
9717 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9719 rtx *insn_ptr = data;
9722 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9726 /* Return true if there is true register dependence between vr4130_last_insn
9730 vr4130_true_reg_dependence_p (rtx insn)
9732 note_stores (PATTERN (vr4130_last_insn),
9733 vr4130_true_reg_dependence_p_1, &insn);
9737 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9738 the ready queue and that INSN2 is the instruction after it, return
9739 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9740 in which INSN1 and INSN2 can probably issue in parallel, but for
9741 which (INSN2, INSN1) should be less sensitive to instruction
9742 alignment than (INSN1, INSN2). See 4130.md for more details. */
9745 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9749 /* Check for the following case:
9751 1) there is some other instruction X with an anti dependence on INSN1;
9752 2) X has a higher priority than INSN2; and
9753 3) X is an arithmetic instruction (and thus has no unit restrictions).
9755 If INSN1 is the last instruction blocking X, it would better to
9756 choose (INSN1, X) over (INSN2, INSN1). */
9757 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9758 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9759 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9760 && recog_memoized (XEXP (dep, 0)) >= 0
9761 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9764 if (vr4130_last_insn != 0
9765 && recog_memoized (insn1) >= 0
9766 && recog_memoized (insn2) >= 0)
9768 /* See whether INSN1 and INSN2 use different execution units,
9769 or if they are both ALU-type instructions. If so, they can
9770 probably execute in parallel. */
9771 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9772 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9773 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9775 /* If only one of the instructions has a dependence on
9776 vr4130_last_insn, prefer to schedule the other one first. */
9777 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9778 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9782 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9783 is not an ALU-type instruction and if INSN1 uses the same
9784 execution unit. (Note that if this condition holds, we already
9785 know that INSN2 uses a different execution unit.) */
9786 if (class1 != VR4130_CLASS_ALU
9787 && recog_memoized (vr4130_last_insn) >= 0
9788 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9795 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9796 queue with at least two instructions. Swap the first two if
9797 vr4130_swap_insns_p says that it could be worthwhile. */
9800 vr4130_reorder (rtx *ready, int nready)
9802 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9803 mips_promote_ready (ready, nready - 2, nready - 1);
9806 /* Remove the instruction at index LOWER from ready queue READY and
9807 reinsert it in front of the instruction at index HIGHER. LOWER must
9811 mips_promote_ready (rtx *ready, int lower, int higher)
9816 new_head = ready[lower];
9817 for (i = lower; i < higher; i++)
9818 ready[i] = ready[i + 1];
9819 ready[i] = new_head;
9822 /* Implement TARGET_SCHED_REORDER. */
9825 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9826 rtx *ready, int *nreadyp, int cycle)
9828 if (!reload_completed && TUNE_MACC_CHAINS)
9831 mips_macc_chains_last_hilo = 0;
9833 mips_macc_chains_reorder (ready, *nreadyp);
9835 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9838 vr4130_last_insn = 0;
9840 vr4130_reorder (ready, *nreadyp);
9842 return mips_issue_rate ();
9845 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9848 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9851 switch (GET_CODE (PATTERN (insn)))
9855 /* Don't count USEs and CLOBBERs against the issue rate. */
9860 if (!reload_completed && TUNE_MACC_CHAINS)
9861 mips_macc_chains_record (insn);
9862 vr4130_last_insn = insn;
9868 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9869 dependencies have no cost. */
9872 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9873 rtx dep ATTRIBUTE_UNUSED, int cost)
9875 if (REG_NOTE_KIND (link) != 0)
9880 /* Return the number of instructions that can be issued per cycle. */
9883 mips_issue_rate (void)
9887 case PROCESSOR_R4130:
9888 case PROCESSOR_R5400:
9889 case PROCESSOR_R5500:
9890 case PROCESSOR_R7000:
9891 case PROCESSOR_R9000:
9895 /* This is actually 4, but we get better performance if we claim 3.
9896 This is partly because of unwanted speculative code motion with the
9897 larger number, and partly because in most common cases we can't
9898 reach the theoretical max of 4. */
9906 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9907 be as wide as the scheduling freedom in the DFA. */
9910 mips_multipass_dfa_lookahead (void)
9912 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9913 if (mips_tune == PROCESSOR_SB1)
9919 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9920 return the first operand of the associated "pref" or "prefx" insn. */
9923 mips_prefetch_cookie (rtx write, rtx locality)
9925 /* store_streamed / load_streamed. */
9926 if (INTVAL (locality) <= 0)
9927 return GEN_INT (INTVAL (write) + 4);
9930 if (INTVAL (locality) <= 2)
9933 /* store_retained / load_retained. */
9934 return GEN_INT (INTVAL (write) + 6);
9937 /* MIPS builtin function support. */
9939 struct builtin_description
9941 /* The code of the main .md file instruction. See mips_builtin_type
9942 for more information. */
9943 enum insn_code icode;
9945 /* The floating-point comparison code to use with ICODE, if any. */
9946 enum mips_fp_condition cond;
9948 /* The name of the builtin function. */
9951 /* Specifies how the function should be expanded. */
9952 enum mips_builtin_type builtin_type;
9954 /* The function's prototype. */
9955 enum mips_function_type function_type;
9957 /* The target flags required for this function. */
9961 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9962 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9963 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9964 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9965 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9967 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9969 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9970 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9971 "__builtin_mips_" #INSN "_" #COND "_s", \
9972 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9973 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9974 "__builtin_mips_" #INSN "_" #COND "_d", \
9975 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9977 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9978 The lower and upper forms require TARGET_FLAGS while the any and all
9979 forms require MASK_MIPS3D. */
9980 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9981 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9982 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9983 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9984 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9985 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
9986 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9987 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9988 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
9989 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9990 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9991 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
9992 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
9994 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
9995 require MASK_MIPS3D. */
9996 #define CMP_4S_BUILTINS(INSN, COND) \
9997 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9998 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
9999 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10001 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10002 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10003 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10006 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10007 instruction requires TARGET_FLAGS. */
10008 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10009 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10010 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10011 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10013 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10014 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10015 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10018 /* Define all the builtins related to c.cond.fmt condition COND. */
10019 #define CMP_BUILTINS(COND) \
10020 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10021 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10022 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10023 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10024 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10025 CMP_4S_BUILTINS (c, COND), \
10026 CMP_4S_BUILTINS (cabs, COND)
10028 /* __builtin_mips_abs_ps() maps to the standard absM2 pattern. */
10029 #define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
10031 static const struct builtin_description mips_bdesc[] =
10033 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10034 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10035 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10036 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10037 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10038 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10039 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10040 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10042 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10043 MASK_PAIRED_SINGLE_FLOAT),
10044 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10045 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10046 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10047 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10049 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10050 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10051 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10052 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10053 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10054 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10056 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10057 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10058 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10059 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10060 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10061 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10063 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10066 /* Builtin functions for the SB-1 processor. */
10068 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10070 static const struct builtin_description sb1_bdesc[] =
10072 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10075 /* Builtin functions for DSP ASE. */
10077 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10078 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10079 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10080 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10082 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10083 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10084 builtin_description fields. */
10085 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10086 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10087 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10089 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10090 branch instruction. TARGET_FLAGS is a builtin_description field. */
10091 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10092 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10093 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10095 static const struct builtin_description dsp_bdesc[] =
10097 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10098 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10099 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10100 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10101 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10102 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10103 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10104 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10105 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10106 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10107 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10108 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10109 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10110 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10111 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10112 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10113 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10114 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10115 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10116 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10117 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10118 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10119 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10120 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10121 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10122 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10123 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10124 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10125 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10126 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10127 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10128 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10129 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10130 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10131 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10132 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10133 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10134 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10135 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10136 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10137 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10138 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10139 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10140 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10141 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10142 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10143 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10144 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10145 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10146 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10147 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10148 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10149 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10150 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10151 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10152 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10153 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10154 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10155 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10156 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10157 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10158 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10159 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10160 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10161 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10162 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10163 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10164 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10165 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10166 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10167 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10168 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10169 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10170 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10171 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10172 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10173 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10174 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10175 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10176 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10177 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10178 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10179 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10180 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10181 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10182 BPOSGE_BUILTIN (32, MASK_DSP)
10185 /* This helps provide a mapping from builtin function codes to bdesc
10190 /* The builtin function table that this entry describes. */
10191 const struct builtin_description *bdesc;
10193 /* The number of entries in the builtin function table. */
10196 /* The target processor that supports these builtin functions.
10197 PROCESSOR_MAX means we enable them for all processors. */
10198 enum processor_type proc;
10201 static const struct bdesc_map bdesc_arrays[] =
10203 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
10204 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
10205 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
10208 /* Take the head of argument list *ARGLIST and convert it into a form
10209 suitable for input operand OP of instruction ICODE. Return the value
10210 and point *ARGLIST at the next element of the list. */
10213 mips_prepare_builtin_arg (enum insn_code icode,
10214 unsigned int op, tree *arglist)
10217 enum machine_mode mode;
10219 value = expand_normal (TREE_VALUE (*arglist));
10220 mode = insn_data[icode].operand[op].mode;
10221 if (!insn_data[icode].operand[op].predicate (value, mode))
10223 value = copy_to_mode_reg (mode, value);
10224 /* Check the predicate again. */
10225 if (!insn_data[icode].operand[op].predicate (value, mode))
10227 error ("invalid argument to builtin function");
10232 *arglist = TREE_CHAIN (*arglist);
10236 /* Return an rtx suitable for output operand OP of instruction ICODE.
10237 If TARGET is non-null, try to use it where possible. */
10240 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10242 enum machine_mode mode;
10244 mode = insn_data[icode].operand[op].mode;
10245 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10246 target = gen_reg_rtx (mode);
10251 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10254 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10255 enum machine_mode mode ATTRIBUTE_UNUSED,
10256 int ignore ATTRIBUTE_UNUSED)
10258 enum insn_code icode;
10259 enum mips_builtin_type type;
10260 tree fndecl, arglist;
10261 unsigned int fcode;
10262 const struct builtin_description *bdesc;
10263 const struct bdesc_map *m;
10265 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10266 arglist = TREE_OPERAND (exp, 1);
10267 fcode = DECL_FUNCTION_CODE (fndecl);
10270 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10272 if (fcode < m->size)
10275 icode = bdesc[fcode].icode;
10276 type = bdesc[fcode].builtin_type;
10286 case MIPS_BUILTIN_DIRECT:
10287 return mips_expand_builtin_direct (icode, target, arglist, true);
10289 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10290 return mips_expand_builtin_direct (icode, target, arglist, false);
10292 case MIPS_BUILTIN_MOVT:
10293 case MIPS_BUILTIN_MOVF:
10294 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10297 case MIPS_BUILTIN_CMP_ANY:
10298 case MIPS_BUILTIN_CMP_ALL:
10299 case MIPS_BUILTIN_CMP_UPPER:
10300 case MIPS_BUILTIN_CMP_LOWER:
10301 case MIPS_BUILTIN_CMP_SINGLE:
10302 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10305 case MIPS_BUILTIN_BPOSGE32:
10306 return mips_expand_builtin_bposge (type, target);
10313 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10316 mips_init_builtins (void)
10318 const struct builtin_description *d;
10319 const struct bdesc_map *m;
10320 tree types[(int) MIPS_MAX_FTYPE_MAX];
10321 tree V2SF_type_node;
10322 tree V2HI_type_node;
10323 tree V4QI_type_node;
10324 unsigned int offset;
10326 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10327 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10330 if (TARGET_PAIRED_SINGLE_FLOAT)
10332 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10334 types[MIPS_V2SF_FTYPE_V2SF]
10335 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10337 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10338 = build_function_type_list (V2SF_type_node,
10339 V2SF_type_node, V2SF_type_node, NULL_TREE);
10341 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10342 = build_function_type_list (V2SF_type_node,
10343 V2SF_type_node, V2SF_type_node,
10344 integer_type_node, NULL_TREE);
10346 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10347 = build_function_type_list (V2SF_type_node,
10348 V2SF_type_node, V2SF_type_node,
10349 V2SF_type_node, V2SF_type_node, NULL_TREE);
10351 types[MIPS_V2SF_FTYPE_SF_SF]
10352 = build_function_type_list (V2SF_type_node,
10353 float_type_node, float_type_node, NULL_TREE);
10355 types[MIPS_INT_FTYPE_V2SF_V2SF]
10356 = build_function_type_list (integer_type_node,
10357 V2SF_type_node, V2SF_type_node, NULL_TREE);
10359 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10360 = build_function_type_list (integer_type_node,
10361 V2SF_type_node, V2SF_type_node,
10362 V2SF_type_node, V2SF_type_node, NULL_TREE);
10364 types[MIPS_INT_FTYPE_SF_SF]
10365 = build_function_type_list (integer_type_node,
10366 float_type_node, float_type_node, NULL_TREE);
10368 types[MIPS_INT_FTYPE_DF_DF]
10369 = build_function_type_list (integer_type_node,
10370 double_type_node, double_type_node, NULL_TREE);
10372 types[MIPS_SF_FTYPE_V2SF]
10373 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10375 types[MIPS_SF_FTYPE_SF]
10376 = build_function_type_list (float_type_node,
10377 float_type_node, NULL_TREE);
10379 types[MIPS_SF_FTYPE_SF_SF]
10380 = build_function_type_list (float_type_node,
10381 float_type_node, float_type_node, NULL_TREE);
10383 types[MIPS_DF_FTYPE_DF]
10384 = build_function_type_list (double_type_node,
10385 double_type_node, NULL_TREE);
10387 types[MIPS_DF_FTYPE_DF_DF]
10388 = build_function_type_list (double_type_node,
10389 double_type_node, double_type_node, NULL_TREE);
10394 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10395 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10397 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10398 = build_function_type_list (V2HI_type_node,
10399 V2HI_type_node, V2HI_type_node,
10402 types[MIPS_SI_FTYPE_SI_SI]
10403 = build_function_type_list (intSI_type_node,
10404 intSI_type_node, intSI_type_node,
10407 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10408 = build_function_type_list (V4QI_type_node,
10409 V4QI_type_node, V4QI_type_node,
10412 types[MIPS_SI_FTYPE_V4QI]
10413 = build_function_type_list (intSI_type_node,
10417 types[MIPS_V2HI_FTYPE_V2HI]
10418 = build_function_type_list (V2HI_type_node,
10422 types[MIPS_SI_FTYPE_SI]
10423 = build_function_type_list (intSI_type_node,
10427 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10428 = build_function_type_list (V4QI_type_node,
10429 V2HI_type_node, V2HI_type_node,
10432 types[MIPS_V2HI_FTYPE_SI_SI]
10433 = build_function_type_list (V2HI_type_node,
10434 intSI_type_node, intSI_type_node,
10437 types[MIPS_SI_FTYPE_V2HI]
10438 = build_function_type_list (intSI_type_node,
10442 types[MIPS_V2HI_FTYPE_V4QI]
10443 = build_function_type_list (V2HI_type_node,
10447 types[MIPS_V4QI_FTYPE_V4QI_SI]
10448 = build_function_type_list (V4QI_type_node,
10449 V4QI_type_node, intSI_type_node,
10452 types[MIPS_V2HI_FTYPE_V2HI_SI]
10453 = build_function_type_list (V2HI_type_node,
10454 V2HI_type_node, intSI_type_node,
10457 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10458 = build_function_type_list (V2HI_type_node,
10459 V4QI_type_node, V2HI_type_node,
10462 types[MIPS_SI_FTYPE_V2HI_V2HI]
10463 = build_function_type_list (intSI_type_node,
10464 V2HI_type_node, V2HI_type_node,
10467 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10468 = build_function_type_list (intDI_type_node,
10469 intDI_type_node, V4QI_type_node, V4QI_type_node,
10472 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10473 = build_function_type_list (intDI_type_node,
10474 intDI_type_node, V2HI_type_node, V2HI_type_node,
10477 types[MIPS_DI_FTYPE_DI_SI_SI]
10478 = build_function_type_list (intDI_type_node,
10479 intDI_type_node, intSI_type_node, intSI_type_node,
10482 types[MIPS_V4QI_FTYPE_SI]
10483 = build_function_type_list (V4QI_type_node,
10487 types[MIPS_V2HI_FTYPE_SI]
10488 = build_function_type_list (V2HI_type_node,
10492 types[MIPS_VOID_FTYPE_V4QI_V4QI]
10493 = build_function_type_list (void_type_node,
10494 V4QI_type_node, V4QI_type_node,
10497 types[MIPS_SI_FTYPE_V4QI_V4QI]
10498 = build_function_type_list (intSI_type_node,
10499 V4QI_type_node, V4QI_type_node,
10502 types[MIPS_VOID_FTYPE_V2HI_V2HI]
10503 = build_function_type_list (void_type_node,
10504 V2HI_type_node, V2HI_type_node,
10507 types[MIPS_SI_FTYPE_DI_SI]
10508 = build_function_type_list (intSI_type_node,
10509 intDI_type_node, intSI_type_node,
10512 types[MIPS_DI_FTYPE_DI_SI]
10513 = build_function_type_list (intDI_type_node,
10514 intDI_type_node, intSI_type_node,
10517 types[MIPS_VOID_FTYPE_SI_SI]
10518 = build_function_type_list (void_type_node,
10519 intSI_type_node, intSI_type_node,
10522 types[MIPS_SI_FTYPE_PTR_SI]
10523 = build_function_type_list (intSI_type_node,
10524 ptr_type_node, intSI_type_node,
10527 types[MIPS_SI_FTYPE_VOID]
10528 = build_function_type (intSI_type_node, void_list_node);
10531 /* Iterate through all of the bdesc arrays, initializing all of the
10532 builtin functions. */
10535 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10537 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10538 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10539 if ((d->target_flags & target_flags) == d->target_flags)
10540 lang_hooks.builtin_function (d->name, types[d->function_type],
10541 d - m->bdesc + offset,
10542 BUILT_IN_MD, NULL, NULL);
10547 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10548 .md pattern and ARGLIST is the list of function arguments. TARGET,
10549 if nonnull, suggests a good place to put the result.
10550 HAS_TARGET indicates the function must return something. */
10553 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,
10556 rtx ops[MAX_RECOG_OPERANDS];
10561 /* We save target to ops[0]. */
10562 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10566 /* We need to test if arglist is not zero. Some instructions have extra
10567 clobber registers. */
10568 for (; i < insn_data[icode].n_operands && arglist != 0; i++)
10569 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10574 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10578 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10582 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10586 gcc_unreachable ();
10591 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10592 function (TYPE says which). ARGLIST is the list of arguments to the
10593 function, ICODE is the instruction that should be used to compare
10594 the first two arguments, and COND is the condition it should test.
10595 TARGET, if nonnull, suggests a good place to put the result. */
10598 mips_expand_builtin_movtf (enum mips_builtin_type type,
10599 enum insn_code icode, enum mips_fp_condition cond,
10600 rtx target, tree arglist)
10602 rtx cmp_result, op0, op1;
10604 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10605 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10606 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10607 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10609 icode = CODE_FOR_mips_cond_move_tf_ps;
10610 target = mips_prepare_builtin_target (icode, 0, target);
10611 if (type == MIPS_BUILTIN_MOVT)
10613 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10614 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10618 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10619 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10621 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10625 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10626 into TARGET otherwise. Return TARGET. */
10629 mips_builtin_branch_and_move (rtx condition, rtx target,
10630 rtx value_if_true, rtx value_if_false)
10632 rtx true_label, done_label;
10634 true_label = gen_label_rtx ();
10635 done_label = gen_label_rtx ();
10637 /* First assume that CONDITION is false. */
10638 emit_move_insn (target, value_if_false);
10640 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10641 emit_jump_insn (gen_condjump (condition, true_label));
10642 emit_jump_insn (gen_jump (done_label));
10645 /* Fix TARGET if CONDITION is true. */
10646 emit_label (true_label);
10647 emit_move_insn (target, value_if_true);
10649 emit_label (done_label);
10653 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10654 of the comparison instruction and COND is the condition it should test.
10655 ARGLIST is the list of function arguments and TARGET, if nonnull,
10656 suggests a good place to put the boolean result. */
10659 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10660 enum insn_code icode, enum mips_fp_condition cond,
10661 rtx target, tree arglist)
10663 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10666 if (target == 0 || GET_MODE (target) != SImode)
10667 target = gen_reg_rtx (SImode);
10669 /* Prepare the operands to the comparison. */
10670 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10671 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
10672 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10674 switch (insn_data[icode].n_operands)
10677 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10681 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10682 ops[3], ops[4], GEN_INT (cond)));
10686 gcc_unreachable ();
10689 /* If the comparison sets more than one register, we define the result
10690 to be 0 if all registers are false and -1 if all registers are true.
10691 The value of the complete result is indeterminate otherwise. */
10692 switch (builtin_type)
10694 case MIPS_BUILTIN_CMP_ALL:
10695 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10696 return mips_builtin_branch_and_move (condition, target,
10697 const0_rtx, const1_rtx);
10699 case MIPS_BUILTIN_CMP_UPPER:
10700 case MIPS_BUILTIN_CMP_LOWER:
10701 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10702 condition = gen_single_cc (cmp_result, offset);
10703 return mips_builtin_branch_and_move (condition, target,
10704 const1_rtx, const0_rtx);
10707 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10708 return mips_builtin_branch_and_move (condition, target,
10709 const1_rtx, const0_rtx);
10713 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10714 suggests a good place to put the boolean result. */
10717 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10719 rtx condition, cmp_result;
10722 if (target == 0 || GET_MODE (target) != SImode)
10723 target = gen_reg_rtx (SImode);
10725 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10727 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10732 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10733 return mips_builtin_branch_and_move (condition, target,
10734 const1_rtx, const0_rtx);
10737 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10738 FIRST is true if this is the first time handling this decl. */
10741 mips_encode_section_info (tree decl, rtx rtl, int first)
10743 default_encode_section_info (decl, rtl, first);
10745 if (TREE_CODE (decl) == FUNCTION_DECL
10746 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
10748 rtx symbol = XEXP (rtl, 0);
10749 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
10753 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. PIC_FUNCTION_ADDR_REGNUM is live
10754 on entry to a function when generating -mshared abicalls code. */
10757 mips_extra_live_on_entry (bitmap regs)
10759 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
10760 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10763 /* SImode values are represented as sign-extended to DImode. */
10766 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10768 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10769 return SIGN_EXTEND;
10774 #include "gt-mips.h"