1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
58 /* Enumeration for all of the relational tests, so that we can build
59 arrays indexed by the test type, and not worry about the order
76 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
77 #define UNSPEC_ADDRESS_P(X) \
78 (GET_CODE (X) == UNSPEC \
79 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
80 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
82 /* Extract the symbol or label from UNSPEC wrapper X. */
83 #define UNSPEC_ADDRESS(X) \
86 /* Extract the symbol type from UNSPEC wrapper X. */
87 #define UNSPEC_ADDRESS_TYPE(X) \
88 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
90 /* True if X is (const $gp). This is used to initialize the mips16
91 gp pseudo register. */
92 #define CONST_GP_P(X) \
93 (GET_CODE (X) == CONST && XEXP (X, 0) == pic_offset_table_rtx)
95 /* The maximum distance between the top of the stack frame and the
96 value $sp has when we save & restore registers.
98 Use a maximum gap of 0x100 in the mips16 case. We can then use
99 unextended instructions to save and restore registers, and to
100 allocate and deallocate the top part of the frame.
102 The value in the !mips16 case must be a SMALL_OPERAND and must
103 preserve the maximum stack alignment. It could really be 0x7ff0,
104 but SGI's assemblers implement daddiu $sp,$sp,-0x7ff0 as a
105 multi-instruction addu sequence. Use 0x7fe0 to work around this. */
106 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7fe0)
108 /* Classifies a SYMBOL_REF, LABEL_REF or UNSPEC address.
111 Used when none of the below apply.
114 The symbol refers to something in a small data section.
117 The symbol refers to something in the mips16 constant pool.
120 The symbol refers to local data that will be found using
121 the global offset table.
124 Likewise non-local data.
127 An UNSPEC wrapper around a SYMBOL_GOT_LOCAL. It represents the
128 offset from _gp of a GOT page entry.
131 An UNSPEC wrapper around a SYMBOL_GOT_GLOBAL. It represents the
132 the offset from _gp of the symbol's GOT entry.
135 Like SYMBOL_GOTOFF_GLOBAL, but used when calling a global function.
136 The GOT entry is allowed to point to a stub rather than to the
140 An UNSPEC wrapper around a function's address. It represents the
141 offset of _gp from the start of the function. */
142 enum mips_symbol_type {
145 SYMBOL_CONSTANT_POOL,
149 SYMBOL_GOTOFF_GLOBAL,
153 #define NUM_SYMBOL_TYPES (SYMBOL_GOTOFF_LOADGP + 1)
156 /* Classifies an address.
159 A natural register + offset address. The register satisfies
160 mips_valid_base_register_p and the offset is a const_arith_operand.
163 A LO_SUM rtx. The first operand is a valid base register and
164 the second operand is a symbolic address.
167 A signed 16-bit constant address.
170 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
171 enum mips_address_type {
178 /* A function to save or store a register. The first argument is the
179 register and the second is the stack slot. */
180 typedef void (*mips_save_restore_fn) (rtx, rtx);
183 struct mips_arg_info;
184 struct mips_address_info;
185 struct mips_integer_op;
187 static enum mips_symbol_type mips_classify_symbol (rtx);
188 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
189 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
190 static bool mips_symbolic_constant_p (rtx, enum mips_symbol_type *);
191 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
192 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
193 static bool mips_classify_address (struct mips_address_info *, rtx,
194 enum machine_mode, int);
195 static int mips_symbol_insns (enum mips_symbol_type);
196 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
197 static rtx mips_force_temporary (rtx, rtx);
198 static rtx mips_split_symbol (rtx, rtx);
199 static rtx mips_unspec_address (rtx, enum mips_symbol_type);
200 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
201 static rtx mips_add_offset (rtx, HOST_WIDE_INT);
202 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
203 static unsigned int mips_build_lower (struct mips_integer_op *,
204 unsigned HOST_WIDE_INT);
205 static unsigned int mips_build_integer (struct mips_integer_op *,
206 unsigned HOST_WIDE_INT);
207 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
208 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
209 static int m16_check_op (rtx, int, int, int);
210 static bool mips_rtx_costs (rtx, int, int, int *);
211 static int mips_address_cost (rtx);
212 static enum internal_test map_test_to_internal_test (enum rtx_code);
213 static void get_float_compare_codes (enum rtx_code, enum rtx_code *,
215 static void mips_load_call_address (rtx, rtx, int);
216 static bool mips_function_ok_for_sibcall (tree, tree);
217 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
218 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
219 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
220 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
221 tree, int, struct mips_arg_info *);
222 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
223 static void mips_set_architecture (const struct mips_cpu_info *);
224 static void mips_set_tune (const struct mips_cpu_info *);
225 static struct machine_function *mips_init_machine_status (void);
226 static void print_operand_reloc (FILE *, rtx, const char **);
227 static bool mips_assemble_integer (rtx, unsigned int, int);
228 static void mips_file_start (void);
229 static void mips_file_end (void);
230 static bool mips_rewrite_small_data_p (rtx);
231 static int small_data_pattern_1 (rtx *, void *);
232 static int mips_rewrite_small_data_1 (rtx *, void *);
233 static bool mips_function_has_gp_insn (void);
234 static unsigned int mips_global_pointer (void);
235 static bool mips_save_reg_p (unsigned int);
236 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
237 mips_save_restore_fn);
238 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
239 static void mips_output_cplocal (void);
240 static void mips_emit_loadgp (void);
241 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
242 static void mips_set_frame_expr (rtx);
243 static rtx mips_frame_set (rtx, rtx);
244 static void mips_save_reg (rtx, rtx);
245 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
246 static void mips_restore_reg (rtx, rtx);
247 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
248 HOST_WIDE_INT, tree);
249 static int symbolic_expression_p (rtx);
250 static void mips_select_rtx_section (enum machine_mode, rtx,
251 unsigned HOST_WIDE_INT);
252 static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
254 static bool mips_in_small_data_p (tree);
255 static void mips_encode_section_info (tree, rtx, int);
256 static int mips_fpr_return_fields (tree, tree *);
257 static bool mips_return_in_msb (tree);
258 static rtx mips_return_fpr_pair (enum machine_mode mode,
259 enum machine_mode mode1, HOST_WIDE_INT,
260 enum machine_mode mode2, HOST_WIDE_INT);
261 static rtx mips16_gp_pseudo_reg (void);
262 static void mips16_fp_args (FILE *, int, int);
263 static void build_mips16_function_stub (FILE *);
264 static rtx add_constant (struct constant **, rtx, enum machine_mode);
265 static void dump_constants (struct constant *, rtx);
266 static rtx mips_find_symbol (rtx);
267 static void mips16_lay_out_constants (void);
268 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
269 static void mips_avoid_hazards (void);
270 static void mips_reorg (void);
271 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
272 static bool mips_matching_cpu_name_p (const char *, const char *);
273 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
274 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
275 static int mips_adjust_cost (rtx, rtx, rtx, int);
276 static bool mips_return_in_memory (tree, tree);
277 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
278 static int mips_issue_rate (void);
279 static int mips_use_dfa_pipeline_interface (void);
280 static void mips_init_libfuncs (void);
281 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
283 static tree mips_build_builtin_va_list (void);
286 static void irix_asm_named_section_1 (const char *, unsigned int,
288 static void irix_asm_named_section (const char *, unsigned int);
289 static int irix_section_align_entry_eq (const void *, const void *);
290 static hashval_t irix_section_align_entry_hash (const void *);
291 static void irix_file_start (void);
292 static int irix_section_align_1 (void **, void *);
293 static void copy_file_data (FILE *, FILE *);
294 static void irix_file_end (void);
295 static unsigned int irix_section_type_flags (tree, const char *, int);
298 /* Structure to be filled in by compute_frame_size with register
299 save masks, and offsets for the current function. */
301 struct mips_frame_info GTY(())
303 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
304 HOST_WIDE_INT var_size; /* # bytes that variables take up */
305 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
306 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
307 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
308 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
309 unsigned int mask; /* mask of saved gp registers */
310 unsigned int fmask; /* mask of saved fp registers */
311 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
312 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
313 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
314 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
315 bool initialized; /* true if frame size already calculated */
316 int num_gp; /* number of gp registers saved */
317 int num_fp; /* number of fp registers saved */
320 struct machine_function GTY(()) {
321 /* Pseudo-reg holding the address of the current function when
322 generating embedded PIC code. */
323 rtx embedded_pic_fnaddr_rtx;
325 /* Pseudo-reg holding the value of $28 in a mips16 function which
326 refers to GP relative global variables. */
327 rtx mips16_gp_pseudo_rtx;
329 /* Current frame information, calculated by compute_frame_size. */
330 struct mips_frame_info frame;
332 /* Length of instructions in function; mips16 only. */
335 /* The register to use as the global pointer within this function. */
336 unsigned int global_pointer;
338 /* True if mips_adjust_insn_length should ignore an instruction's
340 bool ignore_hazard_length_p;
342 /* True if the whole function is suitable for .set noreorder and
344 bool all_noreorder_p;
346 /* True if the function is known to have an instruction that needs $gp. */
350 /* Information about a single argument. */
353 /* True if the argument is passed in a floating-point register, or
354 would have been if we hadn't run out of registers. */
357 /* The argument's size, in bytes. */
358 unsigned int num_bytes;
360 /* The number of words passed in registers, rounded up. */
361 unsigned int reg_words;
363 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
364 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
366 unsigned int reg_offset;
368 /* The number of words that must be passed on the stack, rounded up. */
369 unsigned int stack_words;
371 /* The offset from the start of the stack overflow area of the argument's
372 first stack word. Only meaningful when STACK_WORDS is nonzero. */
373 unsigned int stack_offset;
377 /* Information about an address described by mips_address_type.
383 REG is the base register and OFFSET is the constant offset.
386 REG is the register that contains the high part of the address,
387 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
388 is the type of OFFSET's symbol.
391 SYMBOL_TYPE is the type of symbol being referenced. */
393 struct mips_address_info
395 enum mips_address_type type;
398 enum mips_symbol_type symbol_type;
402 /* One stage in a constant building sequence. These sequences have
406 A = A CODE[1] VALUE[1]
407 A = A CODE[2] VALUE[2]
410 where A is an accumulator, each CODE[i] is a binary rtl operation
411 and each VALUE[i] is a constant integer. */
412 struct mips_integer_op {
414 unsigned HOST_WIDE_INT value;
418 /* The largest number of operations needed to load an integer constant.
419 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
420 When the lowest bit is clear, we can try, but reject a sequence with
421 an extra SLL at the end. */
422 #define MIPS_MAX_INTEGER_OPS 7
425 /* Global variables for machine-dependent things. */
427 /* Threshold for data being put into the small data/bss area, instead
428 of the normal data area. */
429 int mips_section_threshold = -1;
431 /* Count the number of .file directives, so that .loc is up to date. */
432 int num_source_filenames = 0;
434 /* Count the number of sdb related labels are generated (to find block
435 start and end boundaries). */
436 int sdb_label_count = 0;
438 /* Next label # for each statement for Silicon Graphics IRIS systems. */
441 /* Linked list of all externals that are to be emitted when optimizing
442 for the global pointer if they haven't been declared by the end of
443 the program with an appropriate .comm or initialization. */
445 struct extern_list GTY (())
447 struct extern_list *next; /* next external */
448 const char *name; /* name of the external */
449 int size; /* size in bytes */
452 static GTY (()) struct extern_list *extern_head = 0;
454 /* Name of the file containing the current function. */
455 const char *current_function_file = "";
457 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
463 /* The next branch instruction is a branch likely, not branch normal. */
464 int mips_branch_likely;
466 /* Cached operands, and operator to compare for use in set/branch/trap
467 on condition codes. */
470 /* what type of branch to use */
471 enum cmp_type branch_type;
473 /* The target cpu for code generation. */
474 enum processor_type mips_arch;
475 const struct mips_cpu_info *mips_arch_info;
477 /* The target cpu for optimization and scheduling. */
478 enum processor_type mips_tune;
479 const struct mips_cpu_info *mips_tune_info;
481 /* Which instruction set architecture to use. */
484 /* Which ABI to use. */
487 /* Strings to hold which cpu and instruction set architecture to use. */
488 const char *mips_arch_string; /* for -march=<xxx> */
489 const char *mips_tune_string; /* for -mtune=<xxx> */
490 const char *mips_isa_string; /* for -mips{1,2,3,4} */
491 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
493 /* Whether we are generating mips16 hard float code. In mips16 mode
494 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
495 -msoft-float was not specified by the user, which means that we
496 should arrange to call mips32 hard floating point code. */
497 int mips16_hard_float;
499 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
501 /* If TRUE, we split addresses into their high and low parts in the RTL. */
502 int mips_split_addresses;
504 /* Mode used for saving/restoring general purpose registers. */
505 static enum machine_mode gpr_mode;
507 /* Array giving truth value on whether or not a given hard register
508 can support a given mode. */
509 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
511 /* The length of all strings seen when compiling for the mips16. This
512 is used to tell how many strings are in the constant pool, so that
513 we can see if we may have an overflow. This is reset each time the
514 constant pool is output. */
515 int mips_string_length;
517 /* When generating mips16 code, a list of all strings that are to be
518 output after the current function. */
520 static GTY(()) rtx mips16_strings;
522 /* In mips16 mode, we build a list of all the string constants we see
523 in a particular function. */
525 struct string_constant
527 struct string_constant *next;
531 static struct string_constant *string_constants;
533 /* List of all MIPS punctuation characters used by print_operand. */
534 char mips_print_operand_punct[256];
536 /* Map GCC register number to debugger register number. */
537 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
539 /* A copy of the original flag_delayed_branch: see override_options. */
540 static int mips_flag_delayed_branch;
542 static GTY (()) int mips_output_filename_first_time = 1;
544 /* mips_split_p[X] is true if symbols of type X can be split by
545 mips_split_symbol(). */
546 static bool mips_split_p[NUM_SYMBOL_TYPES];
548 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
549 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
550 if they are matched by a special .md file pattern. */
551 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
553 /* Likewise for HIGHs. */
554 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
556 /* Hardware names for the registers. If -mrnames is used, this
557 will be overwritten with mips_sw_reg_names. */
559 char mips_reg_names[][8] =
561 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
562 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
563 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
564 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
565 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
566 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
567 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
568 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
569 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
570 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec",
571 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
572 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
573 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
574 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
575 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
576 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
577 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
578 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
579 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
580 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
581 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
582 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
585 /* Mips software names for the registers, used to overwrite the
586 mips_reg_names array. */
588 char mips_sw_reg_names[][8] =
590 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
591 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
592 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
593 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
594 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
595 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
596 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
597 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
598 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
599 "$fcc5","$fcc6","$fcc7","$rap", "", "$arg", "$frame", "$fakec",
600 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
601 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
602 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
603 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
604 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
605 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
606 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
607 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
608 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
609 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
610 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
611 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
614 /* Map hard register number to register class */
615 const enum reg_class mips_regno_to_class[] =
617 LEA_REGS, LEA_REGS, M16_NA_REGS, M16_NA_REGS,
618 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
619 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
620 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
621 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
622 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
623 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
624 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
625 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
626 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
627 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
628 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
629 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
630 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
631 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
632 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
633 HI_REG, LO_REG, NO_REGS, ST_REGS,
634 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
635 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
636 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
637 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
638 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
639 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
640 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
641 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
642 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
643 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
644 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
645 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
646 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
647 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
648 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
649 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
650 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
651 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
652 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
653 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
654 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
655 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
656 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
657 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
658 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
659 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
660 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
663 /* Map register constraint character to register class. */
664 enum reg_class mips_char_to_class[256];
666 /* A table describing all the processors gcc knows about. Names are
667 matched in the order listed. The first mention of an ISA level is
668 taken as the canonical name for that ISA.
670 To ease comparison, please keep this table in the same order as
671 gas's mips_cpu_info_table[]. */
672 const struct mips_cpu_info mips_cpu_info_table[] = {
673 /* Entries for generic ISAs */
674 { "mips1", PROCESSOR_R3000, 1 },
675 { "mips2", PROCESSOR_R6000, 2 },
676 { "mips3", PROCESSOR_R4000, 3 },
677 { "mips4", PROCESSOR_R8000, 4 },
678 { "mips32", PROCESSOR_4KC, 32 },
679 { "mips32r2", PROCESSOR_M4K, 33 },
680 { "mips64", PROCESSOR_5KC, 64 },
683 { "r3000", PROCESSOR_R3000, 1 },
684 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
685 { "r3900", PROCESSOR_R3900, 1 },
688 { "r6000", PROCESSOR_R6000, 2 },
691 { "r4000", PROCESSOR_R4000, 3 },
692 { "vr4100", PROCESSOR_R4100, 3 },
693 { "vr4111", PROCESSOR_R4111, 3 },
694 { "vr4120", PROCESSOR_R4120, 3 },
695 { "vr4300", PROCESSOR_R4300, 3 },
696 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
697 { "r4600", PROCESSOR_R4600, 3 },
698 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
699 { "r4650", PROCESSOR_R4650, 3 },
702 { "r8000", PROCESSOR_R8000, 4 },
703 { "vr5000", PROCESSOR_R5000, 4 },
704 { "vr5400", PROCESSOR_R5400, 4 },
705 { "vr5500", PROCESSOR_R5500, 4 },
706 { "rm7000", PROCESSOR_R7000, 4 },
707 { "rm9000", PROCESSOR_R9000, 4 },
710 { "4kc", PROCESSOR_4KC, 32 },
711 { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
713 /* MIPS32 Release 2 */
714 { "m4k", PROCESSOR_M4K, 33 },
717 { "5kc", PROCESSOR_5KC, 64 },
718 { "20kc", PROCESSOR_20KC, 64 },
719 { "sb1", PROCESSOR_SB1, 64 },
720 { "sr71000", PROCESSOR_SR71000, 64 },
726 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
727 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
728 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
731 /* Initialize the GCC target structure. */
732 #undef TARGET_ASM_ALIGNED_HI_OP
733 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
734 #undef TARGET_ASM_ALIGNED_SI_OP
735 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
736 #undef TARGET_ASM_INTEGER
737 #define TARGET_ASM_INTEGER mips_assemble_integer
739 #undef TARGET_ASM_FUNCTION_PROLOGUE
740 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
741 #undef TARGET_ASM_FUNCTION_EPILOGUE
742 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
743 #undef TARGET_ASM_SELECT_RTX_SECTION
744 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
746 #undef TARGET_SCHED_ADJUST_COST
747 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
748 #undef TARGET_SCHED_ISSUE_RATE
749 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
750 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
751 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
753 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
754 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
756 #undef TARGET_VALID_POINTER_MODE
757 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
758 #undef TARGET_RTX_COSTS
759 #define TARGET_RTX_COSTS mips_rtx_costs
760 #undef TARGET_ADDRESS_COST
761 #define TARGET_ADDRESS_COST mips_address_cost
763 #undef TARGET_ENCODE_SECTION_INFO
764 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
765 #undef TARGET_IN_SMALL_DATA_P
766 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
768 #undef TARGET_MACHINE_DEPENDENT_REORG
769 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
771 #undef TARGET_ASM_FILE_START
772 #undef TARGET_ASM_FILE_END
774 #define TARGET_ASM_FILE_START irix_file_start
775 #define TARGET_ASM_FILE_END irix_file_end
777 #define TARGET_ASM_FILE_START mips_file_start
778 #define TARGET_ASM_FILE_END mips_file_end
780 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
781 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
784 #undef TARGET_SECTION_TYPE_FLAGS
785 #define TARGET_SECTION_TYPE_FLAGS irix_section_type_flags
788 #undef TARGET_INIT_LIBFUNCS
789 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
791 #undef TARGET_BUILD_BUILTIN_VA_LIST
792 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
794 #undef TARGET_PROMOTE_FUNCTION_ARGS
795 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
796 #undef TARGET_PROMOTE_FUNCTION_RETURN
797 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
798 #undef TARGET_PROMOTE_PROTOTYPES
799 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
801 #undef TARGET_RETURN_IN_MEMORY
802 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
803 #undef TARGET_RETURN_IN_MSB
804 #define TARGET_RETURN_IN_MSB mips_return_in_msb
806 #undef TARGET_ASM_OUTPUT_MI_THUNK
807 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
808 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
809 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
811 #undef TARGET_SETUP_INCOMING_VARARGS
812 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
813 #undef TARGET_STRICT_ARGUMENT_NAMING
814 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
816 struct gcc_target targetm = TARGET_INITIALIZER;
818 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
820 static enum mips_symbol_type
821 mips_classify_symbol (rtx x)
823 if (GET_CODE (x) == LABEL_REF)
824 return (TARGET_ABICALLS ? SYMBOL_GOT_LOCAL : SYMBOL_GENERAL);
826 if (GET_CODE (x) != SYMBOL_REF)
829 if (CONSTANT_POOL_ADDRESS_P (x))
832 return SYMBOL_CONSTANT_POOL;
835 return SYMBOL_GOT_LOCAL;
837 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
838 return SYMBOL_SMALL_DATA;
840 return SYMBOL_GENERAL;
843 if (SYMBOL_REF_SMALL_P (x))
844 return SYMBOL_SMALL_DATA;
846 /* When generating mips16 code, SYMBOL_REF_FLAG indicates a string
847 in the current function's constant pool. */
848 if (TARGET_MIPS16 && SYMBOL_REF_FLAG (x))
849 return SYMBOL_CONSTANT_POOL;
853 if (SYMBOL_REF_DECL (x) == 0)
854 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
856 /* There are three cases to consider:
858 - o32 PIC (either with or without explicit relocs)
859 - n32/n64 PIC without explicit relocs
860 - n32/n64 PIC with explicit relocs
862 In the first case, both local and global accesses will use an
863 R_MIPS_GOT16 relocation. We must correctly predict which of
864 the two semantics (local or global) the assembler and linker
865 will apply. The choice doesn't depend on the symbol's
866 visibility, so we deliberately ignore decl_visibility and
869 In the second case, the assembler will not use R_MIPS_GOT16
870 relocations, but it chooses between local and global accesses
871 in the same way as for o32 PIC.
873 In the third case we have more freedom since both forms of
874 access will work for any kind of symbol. However, there seems
875 little point in doing things differently. */
876 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
877 return SYMBOL_GOT_GLOBAL;
879 return SYMBOL_GOT_LOCAL;
882 return SYMBOL_GENERAL;
886 /* Split X into a base and a constant offset, storing them in *BASE
887 and *OFFSET respectively. */
890 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
894 if (GET_CODE (x) == CONST)
897 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
899 *offset += INTVAL (XEXP (x, 1));
906 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
907 to the same object as SYMBOL. */
910 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
912 if (GET_CODE (symbol) != SYMBOL_REF)
915 if (CONSTANT_POOL_ADDRESS_P (symbol)
917 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
920 if (SYMBOL_REF_DECL (symbol) != 0
922 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
929 /* Return true if X is a symbolic constant that can be calculated in
930 the same way as a bare symbol. If it is, store the type of the
931 symbol in *SYMBOL_TYPE. */
934 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
936 HOST_WIDE_INT offset;
938 mips_split_const (x, &x, &offset);
939 if (UNSPEC_ADDRESS_P (x))
940 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
941 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
942 *symbol_type = mips_classify_symbol (x);
949 /* Check whether a nonzero offset is valid for the underlying
951 switch (*symbol_type)
954 /* If the target has 64-bit pointers and the object file only
955 supports 32-bit symbols, the values of those symbols will be
956 sign-extended. In this case we can't allow an arbitrary offset
957 in case the 32-bit value X + OFFSET has a different sign from X. */
958 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
959 return mips_offset_within_object_p (x, offset);
961 /* In other cases the relocations can handle any offset. */
964 case SYMBOL_SMALL_DATA:
965 case SYMBOL_CONSTANT_POOL:
966 /* Make sure that the offset refers to something within the
967 underlying object. This should guarantee that the final
968 PC- or GP-relative offset is within the 16-bit limit. */
969 return mips_offset_within_object_p (x, offset);
971 case SYMBOL_GOT_LOCAL:
972 case SYMBOL_GOTOFF_PAGE:
973 /* The linker should provide enough local GOT entries for a
974 16-bit offset. Larger offsets may lead to GOT overflow. */
975 return SMALL_OPERAND (offset);
977 case SYMBOL_GOT_GLOBAL:
978 case SYMBOL_GOTOFF_GLOBAL:
979 case SYMBOL_GOTOFF_CALL:
980 case SYMBOL_GOTOFF_LOADGP:
987 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
990 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
992 if (regno >= FIRST_PSEUDO_REGISTER)
996 regno = reg_renumber[regno];
999 /* These fake registers will be eliminated to either the stack or
1000 hard frame pointer, both of which are usually valid base registers.
1001 Reload deals with the cases where the eliminated form isn't valid. */
1002 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1005 /* In mips16 mode, the stack pointer can only address word and doubleword
1006 values, nothing smaller. There are two problems here:
1008 (a) Instantiating virtual registers can introduce new uses of the
1009 stack pointer. If these virtual registers are valid addresses,
1010 the stack pointer should be too.
1012 (b) Most uses of the stack pointer are not made explicit until
1013 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1014 We don't know until that stage whether we'll be eliminating to the
1015 stack pointer (which needs the restriction) or the hard frame
1016 pointer (which doesn't).
1018 All in all, it seems more consistent to only enforce this restriction
1019 during and after reload. */
1020 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1021 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1023 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1027 /* Return true if X is a valid base register for the given mode.
1028 Allow only hard registers if STRICT. */
1031 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1033 if (!strict && GET_CODE (x) == SUBREG)
1036 return (GET_CODE (x) == REG
1037 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1041 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1042 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1045 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1046 enum machine_mode mode)
1048 switch (symbol_type)
1050 case SYMBOL_GENERAL:
1051 return !TARGET_MIPS16;
1053 case SYMBOL_SMALL_DATA:
1056 case SYMBOL_CONSTANT_POOL:
1057 /* PC-relative addressing is only available for lw, sw, ld and sd. */
1058 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1060 case SYMBOL_GOT_LOCAL:
1063 case SYMBOL_GOT_GLOBAL:
1064 /* The address will have to be loaded from the GOT first. */
1067 case SYMBOL_GOTOFF_PAGE:
1068 case SYMBOL_GOTOFF_GLOBAL:
1069 case SYMBOL_GOTOFF_CALL:
1070 case SYMBOL_GOTOFF_LOADGP:
1077 /* Return true if X is a valid address for machine mode MODE. If it is,
1078 fill in INFO appropriately. STRICT is true if we should only accept
1079 hard base registers. */
1082 mips_classify_address (struct mips_address_info *info, rtx x,
1083 enum machine_mode mode, int strict)
1085 switch (GET_CODE (x))
1089 info->type = ADDRESS_REG;
1091 info->offset = const0_rtx;
1092 return mips_valid_base_register_p (info->reg, mode, strict);
1095 info->type = ADDRESS_REG;
1096 info->reg = XEXP (x, 0);
1097 info->offset = XEXP (x, 1);
1098 return (mips_valid_base_register_p (info->reg, mode, strict)
1099 && const_arith_operand (info->offset, VOIDmode));
1102 info->type = ADDRESS_LO_SUM;
1103 info->reg = XEXP (x, 0);
1104 info->offset = XEXP (x, 1);
1105 return (mips_valid_base_register_p (info->reg, mode, strict)
1106 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1107 && mips_symbolic_address_p (info->symbol_type, mode)
1108 && mips_lo_relocs[info->symbol_type] != 0);
1111 /* Small-integer addresses don't occur very often, but they
1112 are legitimate if $0 is a valid base register. */
1113 info->type = ADDRESS_CONST_INT;
1114 return !TARGET_MIPS16 && SMALL_INT (x);
1119 info->type = ADDRESS_SYMBOLIC;
1120 return (mips_symbolic_constant_p (x, &info->symbol_type)
1121 && mips_symbolic_address_p (info->symbol_type, mode)
1122 && !mips_split_p[info->symbol_type]);
1129 /* Return the number of instructions needed to load a symbol of the
1130 given type into a register. If valid in an address, the same number
1131 of instructions are needed for loads and stores. Treat extended
1132 mips16 instructions as two instructions. */
1135 mips_symbol_insns (enum mips_symbol_type type)
1139 case SYMBOL_GENERAL:
1140 /* In mips16 code, general symbols must be fetched from the
1145 /* When using 64-bit symbols, we need 5 preparatory instructions,
1148 lui $at,%highest(symbol)
1149 daddiu $at,$at,%higher(symbol)
1151 daddiu $at,$at,%hi(symbol)
1154 The final address is then $at + %lo(symbol). With 32-bit
1155 symbols we just need a preparatory lui. */
1156 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1158 case SYMBOL_SMALL_DATA:
1161 case SYMBOL_CONSTANT_POOL:
1162 /* This case is for mips16 only. Assume we'll need an
1163 extended instruction. */
1166 case SYMBOL_GOT_LOCAL:
1167 case SYMBOL_GOT_GLOBAL:
1168 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1169 the local/global classification is accurate. See override_options
1172 The worst cases are:
1174 (1) For local symbols when generating o32 or o64 code. The assembler
1180 ...and the final address will be $at + %lo(symbol).
1182 (2) For global symbols when -mxgot. The assembler will use:
1184 lui $at,%got_hi(symbol)
1187 ...and the final address will be $at + %got_lo(symbol). */
1190 case SYMBOL_GOTOFF_PAGE:
1191 case SYMBOL_GOTOFF_GLOBAL:
1192 case SYMBOL_GOTOFF_CALL:
1193 case SYMBOL_GOTOFF_LOADGP:
1194 /* Check whether the offset is a 16- or 32-bit value. */
1195 return mips_split_p[type] ? 2 : 1;
1201 /* Return true if a value at OFFSET bytes from BASE can be accessed
1202 using an unextended mips16 instruction. MODE is the mode of the
1205 Usually the offset in an unextended instruction is a 5-bit field.
1206 The offset is unsigned and shifted left once for HIs, twice
1207 for SIs, and so on. An exception is SImode accesses off the
1208 stack pointer, which have an 8-bit immediate field. */
1211 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1214 && GET_CODE (offset) == CONST_INT
1215 && INTVAL (offset) >= 0
1216 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1218 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1219 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1220 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1226 /* Return the number of instructions needed to load or store a value
1227 of mode MODE at X. Return 0 if X isn't valid for MODE.
1229 For mips16 code, count extended instructions as two instructions. */
1232 mips_address_insns (rtx x, enum machine_mode mode)
1234 struct mips_address_info addr;
1237 if (mode == BLKmode)
1238 /* BLKmode is used for single unaligned loads and stores. */
1241 /* Each word of a multi-word value will be accessed individually. */
1242 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1244 if (mips_classify_address (&addr, x, mode, false))
1249 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1253 case ADDRESS_LO_SUM:
1254 return (TARGET_MIPS16 ? factor * 2 : factor);
1256 case ADDRESS_CONST_INT:
1259 case ADDRESS_SYMBOLIC:
1260 return factor * mips_symbol_insns (addr.symbol_type);
1266 /* Likewise for constant X. */
1269 mips_const_insns (rtx x)
1271 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1272 enum mips_symbol_type symbol_type;
1273 HOST_WIDE_INT offset;
1275 switch (GET_CODE (x))
1277 case CONSTANT_P_RTX:
1282 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1283 || !mips_split_p[symbol_type])
1290 /* Unsigned 8-bit constants can be loaded using an unextended
1291 LI instruction. Unsigned 16-bit constants can be loaded
1292 using an extended LI. Negative constants must be loaded
1293 using LI and then negated. */
1294 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1295 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1296 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1297 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1300 return mips_build_integer (codes, INTVAL (x));
1303 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1309 /* See if we can refer to X directly. */
1310 if (mips_symbolic_constant_p (x, &symbol_type))
1311 return mips_symbol_insns (symbol_type);
1313 /* Otherwise try splitting the constant into a base and offset.
1314 16-bit offsets can be added using an extra addiu. Larger offsets
1315 must be calculated separately and then added to the base. */
1316 mips_split_const (x, &x, &offset);
1319 int n = mips_const_insns (x);
1322 if (SMALL_OPERAND (offset))
1325 return n + 1 + mips_build_integer (codes, offset);
1332 return mips_symbol_insns (mips_classify_symbol (x));
1340 /* Return the number of instructions needed for memory reference X.
1341 Count extended mips16 instructions as two instructions. */
1344 mips_fetch_insns (rtx x)
1346 if (GET_CODE (x) != MEM)
1349 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1353 /* Return the number of instructions needed for an integer division. */
1356 mips_idiv_insns (void)
1361 if (TARGET_CHECK_ZERO_DIV)
1368 if (TARGET_FIX_R4000)
1374 /* Return truth value of whether OP can be used as an operands
1375 where a register or 16 bit unsigned integer is needed. */
1378 uns_arith_operand (rtx op, enum machine_mode mode)
1380 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
1383 return register_operand (op, mode);
1387 /* True if OP can be treated as a signed 16-bit constant. */
1390 const_arith_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1392 return GET_CODE (op) == CONST_INT && SMALL_INT (op);
1396 /* Return true if OP is a register operand or a signed 16-bit constant. */
1399 arith_operand (rtx op, enum machine_mode mode)
1401 return const_arith_operand (op, mode) || register_operand (op, mode);
1404 /* Return truth value of whether OP is an integer which fits in 16 bits. */
1407 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1409 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1412 /* Return truth value of whether OP is a register or the constant 0.
1413 Do not accept 0 in mips16 mode since $0 is not one of the core 8
1417 reg_or_0_operand (rtx op, enum machine_mode mode)
1419 switch (GET_CODE (op))
1424 return INTVAL (op) == 0;
1429 return op == CONST0_RTX (mode);
1432 return register_operand (op, mode);
1436 /* Accept a register or the floating point constant 1 in the appropriate mode. */
1439 reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
1443 switch (GET_CODE (op))
1446 if (mode != GET_MODE (op)
1447 || (mode != DFmode && mode != SFmode))
1450 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1451 return REAL_VALUES_EQUAL (d, dconst1);
1454 return register_operand (op, mode);
1458 /* Accept the floating point constant 1 in the appropriate mode. */
1461 const_float_1_operand (rtx op, enum machine_mode mode)
1465 if (GET_CODE (op) != CONST_DOUBLE
1466 || mode != GET_MODE (op)
1467 || (mode != DFmode && mode != SFmode))
1470 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1472 return REAL_VALUES_EQUAL (d, dconst1);
1475 /* Return true if OP is either the HI or LO register. */
1478 hilo_operand (rtx op, enum machine_mode mode)
1480 return ((mode == VOIDmode || mode == GET_MODE (op))
1481 && REG_P (op) && MD_REG_P (REGNO (op)));
1484 /* Return true if OP is an extension operator. */
1487 extend_operator (rtx op, enum machine_mode mode)
1489 return ((mode == VOIDmode || mode == GET_MODE (op))
1490 && (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
1493 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1496 equality_op (rtx op, enum machine_mode mode)
1498 if (mode != GET_MODE (op))
1501 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
1504 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1507 cmp_op (rtx op, enum machine_mode mode)
1509 if (mode != GET_MODE (op))
1512 return GET_RTX_CLASS (GET_CODE (op)) == '<';
1515 /* Return nonzero if the code is a relational operation suitable for a
1516 conditional trap instruction (only EQ, NE, LT, LTU, GE, GEU).
1517 We need this in the insn that expands `trap_if' in order to prevent
1518 combine from erroneously altering the condition. */
1521 trap_cmp_op (rtx op, enum machine_mode mode)
1523 if (mode != GET_MODE (op))
1526 switch (GET_CODE (op))
1541 /* Return nonzero if the operand is either the PC or a label_ref. */
1544 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1549 if (GET_CODE (op) == LABEL_REF)
1555 /* Test for a valid call address. */
1558 call_insn_operand (rtx op, enum machine_mode mode)
1560 enum mips_symbol_type symbol_type;
1562 if (mips_symbolic_constant_p (op, &symbol_type))
1563 switch (symbol_type)
1565 case SYMBOL_GENERAL:
1566 /* If -mlong-calls, force all calls to use register addressing. */
1567 return !TARGET_LONG_CALLS;
1569 case SYMBOL_GOT_GLOBAL:
1570 /* Without explicit relocs, there is no special syntax for
1571 loading the address of a call destination into a register.
1572 Using "la $25,foo; jal $25" would prevent the lazy binding
1573 of "foo", so keep the address of global symbols with the
1575 return !TARGET_EXPLICIT_RELOCS;
1580 return register_operand (op, mode);
1584 /* Return nonzero if OP is valid as a source operand for a move
1588 move_operand (rtx op, enum machine_mode mode)
1590 enum mips_symbol_type symbol_type;
1592 if (!general_operand (op, mode))
1595 switch (GET_CODE (op))
1598 /* When generating mips16 code, LEGITIMATE_CONSTANT_P rejects
1599 CONST_INTs that can't be loaded using simple insns. */
1603 /* Otherwise check whether the constant can be loaded in a single
1605 return LUI_INT (op) || SMALL_INT (op) || SMALL_INT_UNSIGNED (op);
1610 if (CONST_GP_P (op))
1613 return (mips_symbolic_constant_p (op, &symbol_type)
1614 && !mips_split_p[symbol_type]);
1622 /* Accept any operand that can appear in a mips16 constant table
1623 instruction. We can't use any of the standard operand functions
1624 because for these instructions we accept values that are not
1625 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1628 consttable_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1630 return CONSTANT_P (op);
1633 /* Return 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1634 possibly with an offset. */
1637 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1639 enum mips_symbol_type symbol_type;
1641 return mips_symbolic_constant_p (op, &symbol_type);
1645 /* Return true if we're generating PIC and OP is a global symbol. */
1648 global_got_operand (rtx op, enum machine_mode mode)
1650 enum mips_symbol_type symbol_type;
1652 return ((mode == VOIDmode || mode == GET_MODE (op))
1653 && mips_symbolic_constant_p (op, &symbol_type)
1654 && symbol_type == SYMBOL_GOT_GLOBAL);
1658 /* Likewise for local symbols. */
1661 local_got_operand (rtx op, enum machine_mode mode)
1663 enum mips_symbol_type symbol_type;
1665 return ((mode == VOIDmode || mode == GET_MODE (op))
1666 && mips_symbolic_constant_p (op, &symbol_type)
1667 && symbol_type == SYMBOL_GOT_LOCAL);
1671 /* Return true if OP is a memory reference that uses the stack pointer
1672 as a base register. */
1675 stack_operand (rtx op, enum machine_mode mode)
1677 struct mips_address_info addr;
1679 return ((mode == VOIDmode || mode == GET_MODE (op))
1680 && GET_CODE (op) == MEM
1681 && mips_classify_address (&addr, XEXP (op, 0), GET_MODE (op), false)
1682 && addr.type == ADDRESS_REG
1683 && addr.reg == stack_pointer_rtx);
1687 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1688 returns a nonzero value if X is a legitimate address for a memory
1689 operand of the indicated MODE. STRICT is nonzero if this function
1690 is called during reload. */
1693 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1695 struct mips_address_info addr;
1697 return mips_classify_address (&addr, x, mode, strict);
1701 /* Copy VALUE to a register and return that register. If new psuedos
1702 are allowed, copy it into a new register, otherwise use DEST. */
1705 mips_force_temporary (rtx dest, rtx value)
1707 if (!no_new_pseudos)
1708 return force_reg (Pmode, value);
1711 emit_move_insn (copy_rtx (dest), value);
1717 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1718 and is used to load the high part into a register. */
1721 mips_split_symbol (rtx temp, rtx addr)
1726 high = mips16_gp_pseudo_reg ();
1728 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1729 return gen_rtx_LO_SUM (Pmode, high, addr);
1733 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1734 type SYMBOL_TYPE. */
1737 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1740 HOST_WIDE_INT offset;
1742 mips_split_const (address, &base, &offset);
1743 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1744 UNSPEC_ADDRESS_FIRST + symbol_type);
1745 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1749 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1750 high part to BASE and return the result. Just return BASE otherwise.
1751 TEMP is available as a temporary register if needed.
1753 The returned expression can be used as the first operand to a LO_SUM. */
1756 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1757 enum mips_symbol_type symbol_type)
1759 if (mips_split_p[symbol_type])
1761 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1762 addr = mips_force_temporary (temp, addr);
1763 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1769 /* Return the offset of a GOT page entry for local address ADDR. */
1772 mips_gotoff_page (rtx addr)
1774 return mips_unspec_address (addr, SYMBOL_GOTOFF_PAGE);
1778 /* Return the offset of ADDR's GOT entry from _gp. ADDR is a
1779 global_got_operand. */
1782 mips_gotoff_global (rtx addr)
1784 return mips_unspec_address (addr, SYMBOL_GOTOFF_GLOBAL);
1788 /* Return a legitimate address for REG + OFFSET. This function will
1789 create a temporary register if OFFSET is not a SMALL_OPERAND. */
1792 mips_add_offset (rtx reg, HOST_WIDE_INT offset)
1794 if (!SMALL_OPERAND (offset))
1795 reg = expand_simple_binop (GET_MODE (reg), PLUS,
1796 GEN_INT (CONST_HIGH_PART (offset)),
1797 reg, NULL, 0, OPTAB_WIDEN);
1799 return plus_constant (reg, CONST_LOW_PART (offset));
1803 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1804 be legitimized in a way that the generic machinery might not expect,
1805 put the new address in *XLOC and return true. MODE is the mode of
1806 the memory being accessed. */
1809 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
1811 enum mips_symbol_type symbol_type;
1813 /* See if the address can split into a high part and a LO_SUM. */
1814 if (mips_symbolic_constant_p (*xloc, &symbol_type)
1815 && mips_symbolic_address_p (symbol_type, mode)
1816 && mips_split_p[symbol_type])
1818 *xloc = mips_split_symbol (0, *xloc);
1822 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1824 /* Handle REG + CONSTANT using mips_add_offset. */
1827 reg = XEXP (*xloc, 0);
1828 if (!mips_valid_base_register_p (reg, mode, 0))
1829 reg = copy_to_mode_reg (Pmode, reg);
1830 *xloc = mips_add_offset (reg, INTVAL (XEXP (*xloc, 1)));
1838 /* Subroutine of mips_build_integer (with the same interface).
1839 Assume that the final action in the sequence should be a left shift. */
1842 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1844 unsigned int i, shift;
1846 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1847 since signed numbers are easier to load than unsigned ones. */
1849 while ((value & 1) == 0)
1850 value /= 2, shift++;
1852 i = mips_build_integer (codes, value);
1853 codes[i].code = ASHIFT;
1854 codes[i].value = shift;
1859 /* As for mips_build_shift, but assume that the final action will be
1860 an IOR or PLUS operation. */
1863 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1865 unsigned HOST_WIDE_INT high;
1868 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1869 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1871 /* The constant is too complex to load with a simple lui/ori pair
1872 so our goal is to clear as many trailing zeros as possible.
1873 In this case, we know bit 16 is set and that the low 16 bits
1874 form a negative number. If we subtract that number from VALUE,
1875 we will clear at least the lowest 17 bits, maybe more. */
1876 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1877 codes[i].code = PLUS;
1878 codes[i].value = CONST_LOW_PART (value);
1882 i = mips_build_integer (codes, high);
1883 codes[i].code = IOR;
1884 codes[i].value = value & 0xffff;
1890 /* Fill CODES with a sequence of rtl operations to load VALUE.
1891 Return the number of operations needed. */
1894 mips_build_integer (struct mips_integer_op *codes,
1895 unsigned HOST_WIDE_INT value)
1897 if (SMALL_OPERAND (value)
1898 || SMALL_OPERAND_UNSIGNED (value)
1899 || LUI_OPERAND (value))
1901 /* The value can be loaded with a single instruction. */
1902 codes[0].code = NIL;
1903 codes[0].value = value;
1906 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1908 /* Either the constant is a simple LUI/ORI combination or its
1909 lowest bit is set. We don't want to shift in this case. */
1910 return mips_build_lower (codes, value);
1912 else if ((value & 0xffff) == 0)
1914 /* The constant will need at least three actions. The lowest
1915 16 bits are clear, so the final action will be a shift. */
1916 return mips_build_shift (codes, value);
1920 /* The final action could be a shift, add or inclusive OR.
1921 Rather than use a complex condition to select the best
1922 approach, try both mips_build_shift and mips_build_lower
1923 and pick the one that gives the shortest sequence.
1924 Note that this case is only used once per constant. */
1925 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1926 unsigned int cost, alt_cost;
1928 cost = mips_build_shift (codes, value);
1929 alt_cost = mips_build_lower (alt_codes, value);
1930 if (alt_cost < cost)
1932 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1940 /* Move VALUE into register DEST. */
1943 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
1945 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1946 enum machine_mode mode;
1947 unsigned int i, cost;
1950 mode = GET_MODE (dest);
1951 cost = mips_build_integer (codes, value);
1953 /* Apply each binary operation to X. Invariant: X is a legitimate
1954 source operand for a SET pattern. */
1955 x = GEN_INT (codes[0].value);
1956 for (i = 1; i < cost; i++)
1959 emit_move_insn (dest, x), x = dest;
1961 x = force_reg (mode, x);
1962 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
1965 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1969 /* Subroutine of mips_legitimize_move. Move constant SRC into register
1970 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1974 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
1977 HOST_WIDE_INT offset;
1978 enum mips_symbol_type symbol_type;
1980 /* Split moves of big integers into smaller pieces. In mips16 code,
1981 it's better to force the constant into memory instead. */
1982 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
1984 mips_move_integer (dest, INTVAL (src));
1988 /* See if the symbol can be split. For mips16, this is often worse than
1989 forcing it in the constant pool since it needs the single-register form
1990 of addiu or daddiu. */
1992 && mips_symbolic_constant_p (src, &symbol_type)
1993 && mips_split_p[symbol_type])
1995 emit_move_insn (dest, mips_split_symbol (dest, src));
1999 /* If we have (const (plus symbol offset)), load the symbol first
2000 and then add in the offset. This is usually better than forcing
2001 the constant into memory, at least in non-mips16 code. */
2002 mips_split_const (src, &base, &offset);
2005 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2007 base = mips_force_temporary (dest, base);
2008 emit_move_insn (dest, mips_add_offset (base, offset));
2012 src = force_const_mem (mode, src);
2014 /* When using explicit relocs, constant pool references are sometimes
2015 not legitimate addresses. */
2016 if (!memory_operand (src, VOIDmode))
2017 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2018 emit_move_insn (dest, src);
2022 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2023 sequence that is valid. */
2026 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2028 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2030 emit_move_insn (dest, force_reg (mode, src));
2034 /* The source of an SImode move must be a move_operand. Likewise
2035 DImode moves on 64-bit targets. We need to deal with constants
2036 that would be legitimate immediate_operands but not legitimate
2038 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2040 && !move_operand (src, mode))
2042 mips_legitimize_const_move (mode, dest, src);
2043 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2049 /* We need a lot of little routines to check constant values on the
2050 mips16. These are used to figure out how long the instruction will
2051 be. It would be much better to do this using constraints, but
2052 there aren't nearly enough letters available. */
2055 m16_check_op (rtx op, int low, int high, int mask)
2057 return (GET_CODE (op) == CONST_INT
2058 && INTVAL (op) >= low
2059 && INTVAL (op) <= high
2060 && (INTVAL (op) & mask) == 0);
2064 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2066 return m16_check_op (op, 0x1, 0x8, 0);
2070 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2072 return m16_check_op (op, - 0x8, 0x7, 0);
2076 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2078 return m16_check_op (op, - 0x7, 0x8, 0);
2082 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2084 return m16_check_op (op, - 0x10, 0xf, 0);
2088 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2090 return m16_check_op (op, - 0xf, 0x10, 0);
2094 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2096 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2100 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2102 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2106 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2108 return m16_check_op (op, - 0x80, 0x7f, 0);
2112 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2114 return m16_check_op (op, - 0x7f, 0x80, 0);
2118 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2120 return m16_check_op (op, 0x0, 0xff, 0);
2124 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2126 return m16_check_op (op, - 0xff, 0x0, 0);
2130 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2132 return m16_check_op (op, - 0x1, 0xfe, 0);
2136 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2138 return m16_check_op (op, 0x0, 0xff << 2, 3);
2142 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2144 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2148 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2150 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2154 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2156 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2159 /* References to the string table on the mips16 only use a small
2160 offset if the function is small. We can't check for LABEL_REF here,
2161 because the offset is always large if the label is before the
2162 referencing instruction. */
2165 m16_usym8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2167 if (GET_CODE (op) == SYMBOL_REF
2168 && SYMBOL_REF_FLAG (op)
2169 && cfun->machine->insns_len > 0
2170 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2173 struct string_constant *l;
2175 /* Make sure this symbol is on thelist of string constants to be
2176 output for this function. It is possible that it has already
2177 been output, in which case this requires a large offset. */
2178 for (l = string_constants; l != NULL; l = l->next)
2179 if (strcmp (l->label, XSTR (op, 0)) == 0)
2187 m16_usym5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2189 if (GET_CODE (op) == SYMBOL_REF
2190 && SYMBOL_REF_FLAG (op)
2191 && cfun->machine->insns_len > 0
2192 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2195 struct string_constant *l;
2197 /* Make sure this symbol is on thelist of string constants to be
2198 output for this function. It is possible that it has already
2199 been output, in which case this requires a large offset. */
2200 for (l = string_constants; l != NULL; l = l->next)
2201 if (strcmp (l->label, XSTR (op, 0)) == 0)
2209 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2211 enum machine_mode mode = GET_MODE (x);
2218 /* Always return 0, since we don't have different sized
2219 instructions, hence different costs according to Richard
2225 /* A number between 1 and 8 inclusive is efficient for a shift.
2226 Otherwise, we will need an extended instruction. */
2227 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2228 || (outer_code) == LSHIFTRT)
2230 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2233 *total = COSTS_N_INSNS (1);
2237 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2238 if ((outer_code) == XOR
2239 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2245 /* We may be able to use slt or sltu for a comparison with a
2246 signed 16 bit value. (The boundary conditions aren't quite
2247 right, but this is just a heuristic anyhow.) */
2248 if (((outer_code) == LT || (outer_code) == LE
2249 || (outer_code) == GE || (outer_code) == GT
2250 || (outer_code) == LTU || (outer_code) == LEU
2251 || (outer_code) == GEU || (outer_code) == GTU)
2252 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2258 /* Equality comparisons with 0 are cheap. */
2259 if (((outer_code) == EQ || (outer_code) == NE)
2266 /* Otherwise fall through to the handling below. */
2272 if (LEGITIMATE_CONSTANT_P (x))
2274 *total = COSTS_N_INSNS (1);
2279 /* The value will need to be fetched from the constant pool. */
2280 *total = CONSTANT_POOL_COST;
2286 /* If the address is legitimate, return the number of
2287 instructions it needs, otherwise use the default handling. */
2288 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2291 *total = COSTS_N_INSNS (1 + n);
2298 *total = COSTS_N_INSNS (6);
2302 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2308 if (mode == DImode && !TARGET_64BIT)
2310 *total = COSTS_N_INSNS (2);
2318 if (mode == DImode && !TARGET_64BIT)
2320 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2327 if (mode == SFmode || mode == DFmode)
2328 *total = COSTS_N_INSNS (1);
2330 *total = COSTS_N_INSNS (4);
2334 *total = COSTS_N_INSNS (1);
2339 if (mode == SFmode || mode == DFmode)
2341 if (TUNE_MIPS3000 || TUNE_MIPS3900)
2342 *total = COSTS_N_INSNS (2);
2343 else if (TUNE_MIPS6000)
2344 *total = COSTS_N_INSNS (3);
2346 *total = COSTS_N_INSNS (6);
2349 if (mode == DImode && !TARGET_64BIT)
2351 *total = COSTS_N_INSNS (4);
2357 if (mode == DImode && !TARGET_64BIT)
2370 *total = COSTS_N_INSNS (4);
2371 else if (TUNE_MIPS6000
2374 *total = COSTS_N_INSNS (5);
2376 *total = COSTS_N_INSNS (7);
2385 *total = COSTS_N_INSNS (5);
2386 else if (TUNE_MIPS6000
2389 *total = COSTS_N_INSNS (6);
2391 *total = COSTS_N_INSNS (8);
2396 *total = COSTS_N_INSNS (12);
2397 else if (TUNE_MIPS3900)
2398 *total = COSTS_N_INSNS (2);
2399 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2400 *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
2401 else if (TUNE_MIPS7000)
2402 *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
2403 else if (TUNE_MIPS9000)
2404 *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
2405 else if (TUNE_MIPS6000)
2406 *total = COSTS_N_INSNS (17);
2407 else if (TUNE_MIPS5000)
2408 *total = COSTS_N_INSNS (5);
2410 *total = COSTS_N_INSNS (10);
2419 *total = COSTS_N_INSNS (12);
2420 else if (TUNE_MIPS6000)
2421 *total = COSTS_N_INSNS (15);
2422 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2423 *total = COSTS_N_INSNS (30);
2425 *total = COSTS_N_INSNS (23);
2433 *total = COSTS_N_INSNS (19);
2434 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2435 *total = COSTS_N_INSNS (59);
2436 else if (TUNE_MIPS6000)
2437 *total = COSTS_N_INSNS (16);
2439 *total = COSTS_N_INSNS (36);
2448 *total = COSTS_N_INSNS (35);
2449 else if (TUNE_MIPS6000)
2450 *total = COSTS_N_INSNS (38);
2451 else if (TUNE_MIPS5000)
2452 *total = COSTS_N_INSNS (36);
2453 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2454 *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
2456 *total = COSTS_N_INSNS (69);
2460 /* A sign extend from SImode to DImode in 64 bit mode is often
2461 zero instructions, because the result can often be used
2462 directly by another instruction; we'll call it one. */
2463 if (TARGET_64BIT && mode == DImode
2464 && GET_MODE (XEXP (x, 0)) == SImode)
2465 *total = COSTS_N_INSNS (1);
2467 *total = COSTS_N_INSNS (2);
2471 if (TARGET_64BIT && mode == DImode
2472 && GET_MODE (XEXP (x, 0)) == SImode)
2473 *total = COSTS_N_INSNS (2);
2475 *total = COSTS_N_INSNS (1);
2483 /* Provide the costs of an addressing mode that contains ADDR.
2484 If ADDR is not a valid address, its cost is irrelevant. */
2487 mips_address_cost (rtx addr)
2489 return mips_address_insns (addr, SImode);
2492 /* Return a pseudo that points to the address of the current function.
2493 The first time it is called for a function, an initializer for the
2494 pseudo is emitted in the beginning of the function. */
2497 embedded_pic_fnaddr_reg (void)
2499 if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
2503 cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
2505 /* Output code at function start to initialize the pseudo-reg. */
2506 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
2507 inline functions, because it is called after RTL for the function
2508 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
2509 does not get copied, and ends up not matching the rest of the RTL.
2510 This solution works, but means that we get unnecessary code to
2511 initialize this value every time a function is inlined into another
2514 emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
2515 XEXP (DECL_RTL (current_function_decl), 0)));
2518 push_topmost_sequence ();
2519 emit_insn_after (seq, get_insns ());
2520 pop_topmost_sequence ();
2523 return cfun->machine->embedded_pic_fnaddr_rtx;
2526 /* Return RTL for the offset from the current function to the argument.
2527 X is the symbol whose offset from the current function we want. */
2530 embedded_pic_offset (rtx x)
2532 /* Make sure it is emitted. */
2533 embedded_pic_fnaddr_reg ();
2536 gen_rtx_CONST (Pmode,
2537 gen_rtx_MINUS (Pmode, x,
2538 XEXP (DECL_RTL (current_function_decl), 0)));
2541 /* Return one word of double-word value OP, taking into account the fixed
2542 endianness of certain registers. HIGH_P is true to select the high part,
2543 false to select the low part. */
2546 mips_subword (rtx op, int high_p)
2549 enum machine_mode mode;
2551 mode = GET_MODE (op);
2552 if (mode == VOIDmode)
2555 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2556 byte = UNITS_PER_WORD;
2560 if (GET_CODE (op) == REG)
2562 if (FP_REG_P (REGNO (op)))
2563 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2564 if (REGNO (op) == HI_REGNUM)
2565 return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
2568 if (GET_CODE (op) == MEM)
2569 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2571 return simplify_gen_subreg (word_mode, op, mode, byte);
2575 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2578 mips_split_64bit_move_p (rtx dest, rtx src)
2583 /* FP->FP moves can be done in a single instruction. */
2584 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2587 /* Check for floating-point loads and stores. They can be done using
2588 ldc1 and sdc1 on MIPS II and above. */
2591 if (FP_REG_RTX_P (dest) && GET_CODE (src) == MEM)
2593 if (FP_REG_RTX_P (src) && GET_CODE (dest) == MEM)
2600 /* Split a 64-bit move from SRC to DEST assuming that
2601 mips_split_64bit_move_p holds.
2603 Moves into and out of FPRs cause some difficulty here. Such moves
2604 will always be DFmode, since paired FPRs are not allowed to store
2605 DImode values. The most natural representation would be two separate
2606 32-bit moves, such as:
2608 (set (reg:SI $f0) (mem:SI ...))
2609 (set (reg:SI $f1) (mem:SI ...))
2611 However, the second insn is invalid because odd-numbered FPRs are
2612 not allowed to store independent values. Use the patterns load_df_low,
2613 load_df_high and store_df_high instead. */
2616 mips_split_64bit_move (rtx dest, rtx src)
2618 if (FP_REG_RTX_P (dest))
2620 /* Loading an FPR from memory or from GPRs. */
2621 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2622 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2625 else if (FP_REG_RTX_P (src))
2627 /* Storing an FPR into memory or GPRs. */
2628 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2629 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2633 /* The operation can be split into two normal moves. Decide in
2634 which order to do them. */
2637 low_dest = mips_subword (dest, 0);
2638 if (GET_CODE (low_dest) == REG
2639 && reg_overlap_mentioned_p (low_dest, src))
2641 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2642 emit_move_insn (low_dest, mips_subword (src, 0));
2646 emit_move_insn (low_dest, mips_subword (src, 0));
2647 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2652 /* Return the appropriate instructions to move SRC into DEST. Assume
2653 that SRC is operand 1 and DEST is operand 0. */
2656 mips_output_move (rtx dest, rtx src)
2658 enum rtx_code dest_code, src_code;
2661 dest_code = GET_CODE (dest);
2662 src_code = GET_CODE (src);
2663 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2665 if (dbl_p && mips_split_64bit_move_p (dest, src))
2668 if ((src_code == REG && GP_REG_P (REGNO (src)))
2669 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2671 if (dest_code == REG)
2673 if (GP_REG_P (REGNO (dest)))
2674 return "move\t%0,%z1";
2676 if (MD_REG_P (REGNO (dest)))
2679 if (FP_REG_P (REGNO (dest)))
2680 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2682 if (ALL_COP_REG_P (REGNO (dest)))
2684 static char retval[] = "dmtc_\t%z1,%0";
2686 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2687 return (dbl_p ? retval : retval + 1);
2690 if (dest_code == MEM)
2691 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2693 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2695 if (src_code == REG)
2697 if (MD_REG_P (REGNO (src)))
2700 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2701 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2703 if (FP_REG_P (REGNO (src)))
2704 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2706 if (ALL_COP_REG_P (REGNO (src)))
2708 static char retval[] = "dmfc_\t%0,%1";
2710 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2711 return (dbl_p ? retval : retval + 1);
2715 if (src_code == MEM)
2716 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2718 if (src_code == CONST_INT)
2720 /* Don't use the X format, because that will give out of
2721 range numbers for 64 bit hosts and 32 bit targets. */
2723 return "li\t%0,%1\t\t\t# %X1";
2725 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2728 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2729 return "li\t%0,%n1\n\tneg\t%0";
2732 if (src_code == HIGH)
2733 return "lui\t%0,%h1";
2735 if (CONST_GP_P (src))
2736 return "move\t%0,%1";
2738 if (symbolic_operand (src, VOIDmode))
2739 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2741 if (src_code == REG && FP_REG_P (REGNO (src)))
2743 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2744 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2746 if (dest_code == MEM)
2747 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2749 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2751 if (src_code == MEM)
2752 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2754 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2756 static char retval[] = "l_c_\t%0,%1";
2758 retval[1] = (dbl_p ? 'd' : 'w');
2759 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2762 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2764 static char retval[] = "s_c_\t%1,%0";
2766 retval[1] = (dbl_p ? 'd' : 'w');
2767 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2773 /* Return an rtx for the gp save slot. Valid only when using o32 or
2777 mips_gp_save_slot (void)
2781 if (!TARGET_ABICALLS || TARGET_NEWABI)
2784 if (frame_pointer_needed)
2785 loc = hard_frame_pointer_rtx;
2787 loc = stack_pointer_rtx;
2788 loc = plus_constant (loc, current_function_outgoing_args_size);
2789 loc = gen_rtx_MEM (Pmode, loc);
2790 RTX_UNCHANGING_P (loc) = 1;
2794 /* Make normal rtx_code into something we can index from an array */
2796 static enum internal_test
2797 map_test_to_internal_test (enum rtx_code test_code)
2799 enum internal_test test = ITEST_MAX;
2803 case EQ: test = ITEST_EQ; break;
2804 case NE: test = ITEST_NE; break;
2805 case GT: test = ITEST_GT; break;
2806 case GE: test = ITEST_GE; break;
2807 case LT: test = ITEST_LT; break;
2808 case LE: test = ITEST_LE; break;
2809 case GTU: test = ITEST_GTU; break;
2810 case GEU: test = ITEST_GEU; break;
2811 case LTU: test = ITEST_LTU; break;
2812 case LEU: test = ITEST_LEU; break;
2820 /* Generate the code to compare two integer values. The return value is:
2821 (reg:SI xx) The pseudo register the comparison is in
2822 0 No register, generate a simple branch.
2824 ??? This is called with result nonzero by the Scond patterns in
2825 mips.md. These patterns are called with a target in the mode of
2826 the Scond instruction pattern. Since this must be a constant, we
2827 must use SImode. This means that if RESULT is nonzero, it will
2828 always be an SImode register, even if TARGET_64BIT is true. We
2829 cope with this by calling convert_move rather than emit_move_insn.
2830 This will sometimes lead to an unnecessary extension of the result;
2839 TEST_CODE is the rtx code for the comparison.
2840 CMP0 and CMP1 are the two operands to compare.
2841 RESULT is the register in which the result should be stored (null for
2843 For branches, P_INVERT points to an integer that is nonzero on return
2844 if the branch should be inverted. */
2847 gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0,
2848 rtx cmp1, int *p_invert)
2852 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2853 int const_low; /* low bound of constant we can accept */
2854 int const_high; /* high bound of constant we can accept */
2855 int const_add; /* constant to add (convert LE -> LT) */
2856 int reverse_regs; /* reverse registers in test */
2857 int invert_const; /* != 0 if invert value if cmp1 is constant */
2858 int invert_reg; /* != 0 if invert value if cmp1 is register */
2859 int unsignedp; /* != 0 for unsigned comparisons. */
2862 static const struct cmp_info info[ (int)ITEST_MAX ] = {
2864 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2865 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2866 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2867 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2868 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2869 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2870 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2871 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2872 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2873 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2876 enum internal_test test;
2877 enum machine_mode mode;
2878 const struct cmp_info *p_info;
2885 test = map_test_to_internal_test (test_code);
2886 if (test == ITEST_MAX)
2889 p_info = &info[(int) test];
2890 eqne_p = (p_info->test_code == XOR);
2892 mode = GET_MODE (cmp0);
2893 if (mode == VOIDmode)
2894 mode = GET_MODE (cmp1);
2896 /* Eliminate simple branches. */
2897 branch_p = (result == 0);
2900 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2902 /* Comparisons against zero are simple branches. */
2903 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2904 && (! TARGET_MIPS16 || eqne_p))
2907 /* Test for beq/bne. */
2908 if (eqne_p && ! TARGET_MIPS16)
2912 /* Allocate a pseudo to calculate the value in. */
2913 result = gen_reg_rtx (mode);
2916 /* Make sure we can handle any constants given to us. */
2917 if (GET_CODE (cmp0) == CONST_INT)
2918 cmp0 = force_reg (mode, cmp0);
2920 if (GET_CODE (cmp1) == CONST_INT)
2922 HOST_WIDE_INT value = INTVAL (cmp1);
2924 if (value < p_info->const_low
2925 || value > p_info->const_high
2926 /* ??? Why? And why wasn't the similar code below modified too? */
2928 && HOST_BITS_PER_WIDE_INT < 64
2929 && p_info->const_add != 0
2930 && ((p_info->unsignedp
2931 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2932 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2933 : (value + p_info->const_add) > INTVAL (cmp1))
2934 != (p_info->const_add > 0))))
2935 cmp1 = force_reg (mode, cmp1);
2938 /* See if we need to invert the result. */
2939 invert = (GET_CODE (cmp1) == CONST_INT
2940 ? p_info->invert_const : p_info->invert_reg);
2942 if (p_invert != (int *)0)
2948 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2949 Comparison between two registers, may involve switching operands. */
2950 if (GET_CODE (cmp1) == CONST_INT)
2952 if (p_info->const_add != 0)
2954 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2956 /* If modification of cmp1 caused overflow,
2957 we would get the wrong answer if we follow the usual path;
2958 thus, x > 0xffffffffU would turn into x > 0U. */
2959 if ((p_info->unsignedp
2960 ? (unsigned HOST_WIDE_INT) new >
2961 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2962 : new > INTVAL (cmp1))
2963 != (p_info->const_add > 0))
2965 /* This test is always true, but if INVERT is true then
2966 the result of the test needs to be inverted so 0 should
2967 be returned instead. */
2968 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2972 cmp1 = GEN_INT (new);
2976 else if (p_info->reverse_regs)
2983 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2987 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2988 convert_move (reg, gen_rtx_fmt_ee (p_info->test_code,
2989 mode, cmp0, cmp1), 0);
2992 if (test == ITEST_NE)
2994 if (! TARGET_MIPS16)
2996 convert_move (result, gen_rtx_GTU (mode, reg, const0_rtx), 0);
2997 if (p_invert != NULL)
3003 reg2 = invert ? gen_reg_rtx (mode) : result;
3004 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
3009 else if (test == ITEST_EQ)
3011 reg2 = invert ? gen_reg_rtx (mode) : result;
3012 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
3020 if (! TARGET_MIPS16)
3024 /* The value is in $24. Copy it to another register, so
3025 that reload doesn't think it needs to store the $24 and
3026 the input to the XOR in the same location. */
3027 reg2 = gen_reg_rtx (mode);
3028 emit_move_insn (reg2, reg);
3030 one = force_reg (mode, const1_rtx);
3032 convert_move (result, gen_rtx_XOR (mode, reg, one), 0);
3038 /* Work out how to check a floating-point condition. We need a
3039 separate comparison instruction (C.cond.fmt), followed by a
3040 branch or conditional move. Given that IN_CODE is the
3041 required condition, set *CMP_CODE to the C.cond.fmt code
3042 and *action_code to the branch or move code. */
3045 get_float_compare_codes (enum rtx_code in_code, enum rtx_code *cmp_code,
3046 enum rtx_code *action_code)
3055 *cmp_code = reverse_condition_maybe_unordered (in_code);
3060 *cmp_code = in_code;
3066 /* Emit the common code for doing conditional branches.
3067 operand[0] is the label to jump to.
3068 The comparison operands are saved away by cmp{si,di,sf,df}. */
3071 gen_conditional_branch (rtx *operands, enum rtx_code test_code)
3073 enum cmp_type type = branch_type;
3074 rtx cmp0 = branch_cmp[0];
3075 rtx cmp1 = branch_cmp[1];
3076 enum machine_mode mode;
3077 enum rtx_code cmp_code;
3086 mode = type == CMP_SI ? SImode : DImode;
3088 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3096 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3097 /* We don't want to build a comparison against a nonzero
3099 cmp1 = force_reg (mode, cmp1);
3106 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3108 reg = gen_reg_rtx (CCmode);
3110 get_float_compare_codes (test_code, &cmp_code, &test_code);
3111 emit_insn (gen_rtx_SET (VOIDmode, reg,
3112 gen_rtx_fmt_ee (cmp_code, CCmode, cmp0, cmp1)));
3121 fatal_insn ("bad test",
3122 gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
3125 /* Generate the branch. */
3127 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3137 (gen_rtx_SET (VOIDmode, pc_rtx,
3138 gen_rtx_IF_THEN_ELSE (VOIDmode,
3139 gen_rtx_fmt_ee (test_code, mode,
3144 /* Emit the common code for conditional moves. OPERANDS is the array
3145 of operands passed to the conditional move define_expand. */
3148 gen_conditional_move (rtx *operands)
3150 rtx op0 = branch_cmp[0];
3151 rtx op1 = branch_cmp[1];
3152 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3153 enum rtx_code cmp_code = GET_CODE (operands[1]);
3154 enum rtx_code move_code = NE;
3155 enum machine_mode op_mode = GET_MODE (operands[0]);
3156 enum machine_mode cmp_mode;
3159 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3178 op0 = force_reg (mode, branch_cmp[1]);
3179 op1 = branch_cmp[0];
3183 op0 = force_reg (mode, branch_cmp[1]);
3184 op1 = branch_cmp[0];
3195 op0 = force_reg (mode, branch_cmp[1]);
3196 op1 = branch_cmp[0];
3200 op0 = force_reg (mode, branch_cmp[1]);
3201 op1 = branch_cmp[0];
3209 get_float_compare_codes (cmp_code, &cmp_code, &move_code);
3211 if (mode == SImode || mode == DImode)
3213 else if (mode == SFmode || mode == DFmode)
3218 cmp_reg = gen_reg_rtx (cmp_mode);
3219 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3220 gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1)));
3222 emit_insn (gen_rtx_SET (op_mode, operands[0],
3223 gen_rtx_IF_THEN_ELSE (op_mode,
3224 gen_rtx_fmt_ee (move_code,
3228 operands[2], operands[3])));
3231 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3232 the conditional_trap expander. */
3235 mips_gen_conditional_trap (rtx *operands)
3238 enum rtx_code cmp_code = GET_CODE (operands[0]);
3239 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3241 /* MIPS conditional trap machine instructions don't have GT or LE
3242 flavors, so we must invert the comparison and convert to LT and
3243 GE, respectively. */
3246 case GT: cmp_code = LT; break;
3247 case LE: cmp_code = GE; break;
3248 case GTU: cmp_code = LTU; break;
3249 case LEU: cmp_code = GEU; break;
3252 if (cmp_code == GET_CODE (operands[0]))
3254 op0 = force_reg (mode, branch_cmp[0]);
3255 op1 = branch_cmp[1];
3259 op0 = force_reg (mode, branch_cmp[1]);
3260 op1 = branch_cmp[0];
3262 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3263 op1 = force_reg (mode, op1);
3265 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3266 gen_rtx_fmt_ee (cmp_code, GET_MODE (operands[0]),
3271 /* Load function address ADDR into register DEST. SIBCALL_P is true
3272 if the address is needed for a sibling call. */
3275 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3277 /* If we're generating PIC, and this call is to a global function,
3278 try to allow its address to be resolved lazily. This isn't
3279 possible for NewABI sibcalls since the value of $gp on entry
3280 to the stub would be our caller's gp, not ours. */
3281 if (TARGET_EXPLICIT_RELOCS
3282 && !(sibcall_p && TARGET_NEWABI)
3283 && global_got_operand (addr, VOIDmode))
3285 rtx high, lo_sum_symbol;
3287 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3288 addr, SYMBOL_GOTOFF_CALL);
3289 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3290 if (Pmode == SImode)
3291 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3293 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3296 emit_move_insn (dest, addr);
3300 /* Expand a call or call_value instruction. RESULT is where the
3301 result will go (null for calls), ADDR is the address of the
3302 function, ARGS_SIZE is the size of the arguments and AUX is
3303 the value passed to us by mips_function_arg. SIBCALL_P is true
3304 if we are expanding a sibling call, false if we're expanding
3308 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3310 rtx orig_addr, pattern, insn;
3313 if (!call_insn_operand (addr, VOIDmode))
3315 addr = gen_reg_rtx (Pmode);
3316 mips_load_call_address (addr, orig_addr, sibcall_p);
3320 && mips16_hard_float
3321 && build_mips16_call_stub (result, addr, args_size,
3322 aux == 0 ? 0 : (int) GET_MODE (aux)))
3326 pattern = (sibcall_p
3327 ? gen_sibcall_internal (addr, args_size)
3328 : gen_call_internal (addr, args_size));
3329 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3333 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3334 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3337 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3338 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3341 pattern = (sibcall_p
3342 ? gen_sibcall_value_internal (result, addr, args_size)
3343 : gen_call_value_internal (result, addr, args_size));
3345 insn = emit_call_insn (pattern);
3347 /* Lazy-binding stubs require $gp to be valid on entry. */
3348 if (global_got_operand (orig_addr, VOIDmode))
3349 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3353 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3356 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3357 tree exp ATTRIBUTE_UNUSED)
3359 return TARGET_SIBCALLS;
3362 /* Return true if operand OP is a condition code register.
3363 Only for use during or after reload. */
3366 fcc_register_operand (rtx op, enum machine_mode mode)
3368 return ((mode == VOIDmode || mode == GET_MODE (op))
3369 && (reload_in_progress || reload_completed)
3370 && (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
3371 && ST_REG_P (true_regnum (op)));
3374 /* Emit code to move general operand SRC into condition-code
3375 register DEST. SCRATCH is a scratch TFmode float register.
3382 where FP1 and FP2 are single-precision float registers
3383 taken from SCRATCH. */
3386 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3390 /* Change the source to SFmode. */
3391 if (GET_CODE (src) == MEM)
3392 src = adjust_address (src, SFmode, 0);
3393 else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
3394 src = gen_rtx_REG (SFmode, true_regnum (src));
3396 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3397 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3399 emit_move_insn (copy_rtx (fp1), src);
3400 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3401 emit_insn (gen_slt_sf (dest, fp2, fp1));
3404 /* Emit code to change the current function's return address to
3405 ADDRESS. SCRATCH is available as a scratch register, if needed.
3406 ADDRESS and SCRATCH are both word-mode GPRs. */
3409 mips_set_return_address (rtx address, rtx scratch)
3411 HOST_WIDE_INT gp_offset;
3413 compute_frame_size (get_frame_size ());
3414 if (((cfun->machine->frame.mask >> 31) & 1) == 0)
3416 gp_offset = cfun->machine->frame.gp_sp_offset;
3418 /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH. */
3419 if (gp_offset < 32768)
3420 scratch = plus_constant (stack_pointer_rtx, gp_offset);
3423 emit_move_insn (scratch, GEN_INT (gp_offset));
3424 if (Pmode == DImode)
3425 emit_insn (gen_adddi3 (scratch, scratch, stack_pointer_rtx));
3427 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
3430 emit_move_insn (gen_rtx_MEM (GET_MODE (address), scratch), address);
3433 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3434 Assume that the areas do not overlap. */
3437 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3439 HOST_WIDE_INT offset, delta;
3440 unsigned HOST_WIDE_INT bits;
3442 enum machine_mode mode;
3445 /* Work out how many bits to move at a time. If both operands have
3446 half-word alignment, it is usually better to move in half words.
3447 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3448 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3449 Otherwise move word-sized chunks. */
3450 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3451 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3452 bits = BITS_PER_WORD / 2;
3454 bits = BITS_PER_WORD;
3456 mode = mode_for_size (bits, MODE_INT, 0);
3457 delta = bits / BITS_PER_UNIT;
3459 /* Allocate a buffer for the temporary registers. */
3460 regs = alloca (sizeof (rtx) * length / delta);
3462 /* Load as many BITS-sized chunks as possible. Use a normal load if
3463 the source has enough alignment, otherwise use left/right pairs. */
3464 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3468 regs[i] = gen_reg_rtx (mode);
3469 part = adjust_address (src, mode, offset);
3470 if (MEM_ALIGN (part) >= bits)
3471 emit_move_insn (regs[i], part);
3472 else if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3476 /* Copy the chunks to the destination. */
3477 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3481 part = adjust_address (dest, mode, offset);
3482 if (MEM_ALIGN (part) >= bits)
3483 emit_move_insn (part, regs[i]);
3484 else if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3488 /* Mop up any left-over bytes. */
3489 if (offset < length)
3491 src = adjust_address (src, mode, offset);
3492 dest = adjust_address (dest, mode, offset);
3493 move_by_pieces (dest, src, length - offset,
3494 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3498 #define MAX_MOVE_REGS 4
3499 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3502 /* Helper function for doing a loop-based block operation on memory
3503 reference MEM. Each iteration of the loop will operate on LENGTH
3506 Create a new base register for use within the loop and point it to
3507 the start of MEM. Create a new memory reference that uses this
3508 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3511 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3512 rtx *loop_reg, rtx *loop_mem)
3514 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3516 /* Although the new mem does not refer to a known location,
3517 it does keep up to LENGTH bytes of alignment. */
3518 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3519 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3523 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3524 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3525 memory regions do not overlap. */
3528 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3530 rtx label, src_reg, dest_reg, final_src;
3531 HOST_WIDE_INT leftover;
3533 leftover = length % MAX_MOVE_BYTES;
3536 /* Create registers and memory references for use within the loop. */
3537 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3538 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3540 /* Calculate the value that SRC_REG should have after the last iteration
3542 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3545 /* Emit the start of the loop. */
3546 label = gen_label_rtx ();
3549 /* Emit the loop body. */
3550 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3552 /* Move on to the next block. */
3553 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3554 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3556 /* Emit the loop condition. */
3557 if (Pmode == DImode)
3558 emit_insn (gen_cmpdi (src_reg, final_src));
3560 emit_insn (gen_cmpsi (src_reg, final_src));
3561 emit_jump_insn (gen_bne (label));
3563 /* Mop up any left-over bytes. */
3565 mips_block_move_straight (dest, src, leftover);
3568 /* Expand a movstrsi instruction. */
3571 mips_expand_block_move (rtx dest, rtx src, rtx length)
3573 if (GET_CODE (length) == CONST_INT)
3575 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3577 mips_block_move_straight (dest, src, INTVAL (length));
3582 mips_block_move_loop (dest, src, INTVAL (length));
3589 /* Argument support functions. */
3591 /* Initialize CUMULATIVE_ARGS for a function. */
3594 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3595 rtx libname ATTRIBUTE_UNUSED)
3597 static CUMULATIVE_ARGS zero_cum;
3598 tree param, next_param;
3601 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3603 /* Determine if this function has variable arguments. This is
3604 indicated by the last argument being 'void_type_mode' if there
3605 are no variable arguments. The standard MIPS calling sequence
3606 passes all arguments in the general purpose registers in this case. */
3608 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3609 param != 0; param = next_param)
3611 next_param = TREE_CHAIN (param);
3612 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3613 cum->gp_reg_found = 1;
3618 /* Fill INFO with information about a single argument. CUM is the
3619 cumulative state for earlier arguments. MODE is the mode of this
3620 argument and TYPE is its type (if known). NAMED is true if this
3621 is a named (fixed) argument rather than a variable one. */
3624 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3625 tree type, int named, struct mips_arg_info *info)
3628 unsigned int num_words, max_regs;
3630 /* Decide whether this argument should go in a floating-point register,
3631 assuming one is free. Later code checks for availability. */
3633 info->fpr_p = (GET_MODE_CLASS (mode) == MODE_FLOAT
3634 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3641 info->fpr_p = (!cum->gp_reg_found
3642 && cum->arg_number < 2
3643 && (type == 0 || FLOAT_TYPE_P (type)));
3648 info->fpr_p = (named && (type == 0 || FLOAT_TYPE_P (type)));
3652 /* Now decide whether the argument must go in an even-numbered register. */
3657 /* Under the O64 ABI, the second float argument goes in $f13 if it
3658 is a double, but $f14 if it is a single. Otherwise, on a
3659 32-bit double-float machine, each FP argument must start in a
3660 new register pair. */
3661 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_HWFPVALUE
3662 || (mips_abi == ABI_O64 && mode == SFmode)
3665 else if (!TARGET_64BIT || LONG_DOUBLE_TYPE_SIZE == 128)
3667 if (GET_MODE_CLASS (mode) == MODE_INT
3668 || GET_MODE_CLASS (mode) == MODE_FLOAT)
3669 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
3671 else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
3675 if (mips_abi != ABI_EABI && MUST_PASS_IN_STACK (mode, type))
3676 /* This argument must be passed on the stack. Eat up all the
3677 remaining registers. */
3678 info->reg_offset = MAX_ARGS_IN_REGISTERS;
3681 /* Set REG_OFFSET to the register count we're interested in.
3682 The EABI allocates the floating-point registers separately,
3683 but the other ABIs allocate them like integer registers. */
3684 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3689 info->reg_offset += info->reg_offset & 1;
3692 /* The alignment applied to registers is also applied to stack arguments. */
3693 info->stack_offset = cum->stack_words;
3695 info->stack_offset += info->stack_offset & 1;
3697 if (mode == BLKmode)
3698 info->num_bytes = int_size_in_bytes (type);
3700 info->num_bytes = GET_MODE_SIZE (mode);
3702 num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3703 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3705 /* Partition the argument between registers and stack. */
3706 info->reg_words = MIN (num_words, max_regs);
3707 info->stack_words = num_words - info->reg_words;
3711 /* Implement FUNCTION_ARG_ADVANCE. */
3714 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3715 tree type, int named)
3717 struct mips_arg_info info;
3719 mips_arg_info (cum, mode, type, named, &info);
3722 cum->gp_reg_found = true;
3724 /* See the comment above the cumulative args structure in mips.h
3725 for an explanation of what this code does. It assumes the O32
3726 ABI, which passes at most 2 arguments in float registers. */
3727 if (cum->arg_number < 2 && info.fpr_p)
3728 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3730 if (mips_abi != ABI_EABI || !info.fpr_p)
3731 cum->num_gprs = info.reg_offset + info.reg_words;
3732 else if (info.reg_words > 0)
3733 cum->num_fprs += FP_INC;
3735 if (info.stack_words > 0)
3736 cum->stack_words = info.stack_offset + info.stack_words;
3741 /* Implement FUNCTION_ARG. */
3744 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3745 tree type, int named)
3747 struct mips_arg_info info;
3749 /* We will be called with a mode of VOIDmode after the last argument
3750 has been seen. Whatever we return will be passed to the call
3751 insn. If we need a mips16 fp_code, return a REG with the code
3752 stored as the mode. */
3753 if (mode == VOIDmode)
3755 if (TARGET_MIPS16 && cum->fp_code != 0)
3756 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3762 mips_arg_info (cum, mode, type, named, &info);
3764 /* Return straight away if the whole argument is passed on the stack. */
3765 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3769 && TREE_CODE (type) == RECORD_TYPE
3771 && TYPE_SIZE_UNIT (type)
3772 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3775 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3776 structure contains a double in its entirety, then that 64 bit
3777 chunk is passed in a floating point register. */
3780 /* First check to see if there is any such field. */
3781 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3782 if (TREE_CODE (field) == FIELD_DECL
3783 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3784 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3785 && host_integerp (bit_position (field), 0)
3786 && int_bit_position (field) % BITS_PER_WORD == 0)
3791 /* Now handle the special case by returning a PARALLEL
3792 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3793 chunks are passed in registers. */
3795 HOST_WIDE_INT bitpos;
3798 /* assign_parms checks the mode of ENTRY_PARM, so we must
3799 use the actual mode here. */
3800 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3803 field = TYPE_FIELDS (type);
3804 for (i = 0; i < info.reg_words; i++)
3808 for (; field; field = TREE_CHAIN (field))
3809 if (TREE_CODE (field) == FIELD_DECL
3810 && int_bit_position (field) >= bitpos)
3814 && int_bit_position (field) == bitpos
3815 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3816 && !TARGET_SOFT_FLOAT
3817 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3818 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3820 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3823 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3824 GEN_INT (bitpos / BITS_PER_UNIT));
3826 bitpos += BITS_PER_WORD;
3833 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3835 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3839 /* Implement FUNCTION_ARG_PARTIAL_NREGS. */
3842 function_arg_partial_nregs (const CUMULATIVE_ARGS *cum,
3843 enum machine_mode mode, tree type, int named)
3845 struct mips_arg_info info;
3847 mips_arg_info (cum, mode, type, named, &info);
3848 return info.stack_words > 0 ? info.reg_words : 0;
3852 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3853 upward rather than downward. In other words, return true if the
3854 first byte of the stack slot has useful data, false if the last
3858 mips_pad_arg_upward (enum machine_mode mode, tree type)
3860 /* On little-endian targets, the first byte of every stack argument
3861 is passed in the first byte of the stack slot. */
3862 if (!BYTES_BIG_ENDIAN)
3865 /* Otherwise, integral types are padded downward: the last byte of a
3866 stack argument is passed in the last byte of the stack slot. */
3868 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3869 : GET_MODE_CLASS (mode) == MODE_INT)
3872 /* Big-endian o64 pads floating-point arguments downward. */
3873 if (mips_abi == ABI_O64)
3874 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3877 /* Other types are padded upward for o32, o64, n32 and n64. */
3878 if (mips_abi != ABI_EABI)
3881 /* Arguments smaller than a stack slot are padded downward. */
3882 if (mode != BLKmode)
3883 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3885 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3889 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3890 if the least significant byte of the register has useful data. Return
3891 the opposite if the most significant byte does. */
3894 mips_pad_reg_upward (enum machine_mode mode, tree type)
3896 /* No shifting is required for floating-point arguments. */
3897 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3898 return !BYTES_BIG_ENDIAN;
3900 /* Otherwise, apply the same padding to register arguments as we do
3901 to stack arguments. */
3902 return mips_pad_arg_upward (mode, type);
3906 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3907 tree type, int *pretend_size, int no_rtl)
3909 CUMULATIVE_ARGS local_cum;
3910 int gp_saved, fp_saved;
3912 /* The caller has advanced CUM up to, but not beyond, the last named
3913 argument. Advance a local copy of CUM past the last "real" named
3914 argument, to find out how many registers are left over. */
3917 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3919 /* Found out how many registers we need to save. */
3920 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3921 fp_saved = (EABI_FLOAT_VARARGS_P
3922 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3931 ptr = virtual_incoming_args_rtx;
3936 ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
3940 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
3943 mem = gen_rtx_MEM (BLKmode, ptr);
3944 set_mem_alias_set (mem, get_varargs_alias_set ());
3946 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3951 /* We can't use move_block_from_reg, because it will use
3953 enum machine_mode mode;
3956 /* Set OFF to the offset from virtual_incoming_args_rtx of
3957 the first float register. The FP save area lies below
3958 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3959 off = -gp_saved * UNITS_PER_WORD;
3960 off &= ~(UNITS_PER_FPVALUE - 1);
3961 off -= fp_saved * UNITS_PER_FPREG;
3963 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3965 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3969 ptr = plus_constant (virtual_incoming_args_rtx, off);
3970 mem = gen_rtx_MEM (mode, ptr);
3971 set_mem_alias_set (mem, get_varargs_alias_set ());
3972 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3973 off += UNITS_PER_HWFPVALUE;
3979 /* No need for pretend arguments: the register parameter area was
3980 allocated by the caller. */
3984 *pretend_size = (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
3987 /* Create the va_list data type.
3988 We keep 3 pointers, and two offsets.
3989 Two pointers are to the overflow area, which starts at the CFA.
3990 One of these is constant, for addressing into the GPR save area below it.
3991 The other is advanced up the stack through the overflow region.
3992 The third pointer is to the GPR save area. Since the FPR save area
3993 is just below it, we can address FPR slots off this pointer.
3994 We also keep two one-byte offsets, which are to be subtracted from the
3995 constant pointers to yield addresses in the GPR and FPR save areas.
3996 These are downcounted as float or non-float arguments are used,
3997 and when they get to zero, the argument must be obtained from the
3999 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4000 pointer is enough. It's started at the GPR save area, and is
4002 Note that the GPR save area is not constant size, due to optimization
4003 in the prologue. Hence, we can't use a design with two pointers
4004 and two offsets, although we could have designed this with two pointers
4005 and three offsets. */
4008 mips_build_builtin_va_list (void)
4010 if (EABI_FLOAT_VARARGS_P)
4012 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4015 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4017 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4019 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4021 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4023 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4024 unsigned_char_type_node);
4025 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4026 unsigned_char_type_node);
4027 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4028 warn on every user file. */
4029 index = build_int_2 (GET_MODE_SIZE (ptr_mode) - 2 - 1, 0);
4030 array = build_array_type (unsigned_char_type_node,
4031 build_index_type (index));
4032 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4034 DECL_FIELD_CONTEXT (f_ovfl) = record;
4035 DECL_FIELD_CONTEXT (f_gtop) = record;
4036 DECL_FIELD_CONTEXT (f_ftop) = record;
4037 DECL_FIELD_CONTEXT (f_goff) = record;
4038 DECL_FIELD_CONTEXT (f_foff) = record;
4039 DECL_FIELD_CONTEXT (f_res) = record;
4041 TYPE_FIELDS (record) = f_ovfl;
4042 TREE_CHAIN (f_ovfl) = f_gtop;
4043 TREE_CHAIN (f_gtop) = f_ftop;
4044 TREE_CHAIN (f_ftop) = f_goff;
4045 TREE_CHAIN (f_goff) = f_foff;
4046 TREE_CHAIN (f_foff) = f_res;
4048 layout_type (record);
4051 else if (TARGET_IRIX && !TARGET_IRIX5)
4052 /* On IRIX 6, this type is 'char *'. */
4053 return build_pointer_type (char_type_node);
4055 /* Otherwise, we use 'void *'. */
4056 return ptr_type_node;
4059 /* Implement va_start. */
4062 mips_va_start (tree valist, rtx nextarg)
4064 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
4066 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
4067 since the stack is aligned for a pair of argument-passing slots,
4068 and the beginning of a variable argument list may be an odd slot,
4069 we have to decrease its alignment. */
4070 if (cfun && cfun->emit->regno_pointer_align)
4071 while (((current_function_pretend_args_size * BITS_PER_UNIT)
4072 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
4073 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
4075 if (mips_abi == ABI_EABI)
4077 int gpr_save_area_size;
4080 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4082 if (EABI_FLOAT_VARARGS_P)
4084 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4085 tree ovfl, gtop, ftop, goff, foff;
4088 int fpr_save_area_size;
4090 f_ovfl = TYPE_FIELDS (va_list_type_node);
4091 f_gtop = TREE_CHAIN (f_ovfl);
4092 f_ftop = TREE_CHAIN (f_gtop);
4093 f_goff = TREE_CHAIN (f_ftop);
4094 f_foff = TREE_CHAIN (f_goff);
4096 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4097 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4098 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4099 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4100 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4102 /* Emit code to initialize OVFL, which points to the next varargs
4103 stack argument. CUM->STACK_WORDS gives the number of stack
4104 words used by named arguments. */
4105 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4106 if (cum->stack_words > 0)
4107 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4108 build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
4109 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4110 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4112 /* Emit code to initialize GTOP, the top of the GPR save area. */
4113 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4114 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4115 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4117 /* Emit code to initialize FTOP, the top of the FPR save area.
4118 This address is gpr_save_area_bytes below GTOP, rounded
4119 down to the next fp-aligned boundary. */
4120 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4121 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4122 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4124 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4125 build_int_2 (-fpr_offset, -1));
4126 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4127 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4129 /* Emit code to initialize GOFF, the offset from GTOP of the
4130 next GPR argument. */
4131 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4132 build_int_2 (gpr_save_area_size, 0));
4133 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4135 /* Likewise emit code to initialize FOFF, the offset from FTOP
4136 of the next FPR argument. */
4138 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4139 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4140 build_int_2 (fpr_save_area_size, 0));
4141 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4145 /* Everything is in the GPR save area, or in the overflow
4146 area which is contiguous with it. */
4147 nextarg = plus_constant (nextarg, -gpr_save_area_size);
4148 std_expand_builtin_va_start (valist, nextarg);
4152 std_expand_builtin_va_start (valist, nextarg);
4155 /* Implement va_arg. */
4158 mips_va_arg (tree valist, tree type)
4160 HOST_WIDE_INT size, rsize;
4164 size = int_size_in_bytes (type);
4165 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4167 if (mips_abi == ABI_EABI)
4173 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4177 size = POINTER_SIZE / BITS_PER_UNIT;
4178 rsize = UNITS_PER_WORD;
4181 addr_rtx = gen_reg_rtx (Pmode);
4183 if (!EABI_FLOAT_VARARGS_P)
4185 /* Case of all args in a merged stack. No need to check bounds,
4186 just advance valist along the stack. */
4191 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4193 /* Align the pointer using: ap = (ap + align - 1) & -align,
4194 where align is 2 * UNITS_PER_WORD. */
4195 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4196 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4197 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4198 build_int_2 (-2 * UNITS_PER_WORD, -1));
4199 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4200 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4203 /* Emit code to set addr_rtx to the valist, and postincrement
4204 the valist by the size of the argument, rounded up to the
4206 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4208 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4210 emit_move_insn (addr_rtx, r);
4212 /* Flush the POSTINCREMENT. */
4217 /* Not a simple merged stack. */
4219 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4220 tree ovfl, top, off;
4221 rtx lab_over = NULL_RTX, lab_false;
4222 HOST_WIDE_INT osize;
4224 f_ovfl = TYPE_FIELDS (va_list_type_node);
4225 f_gtop = TREE_CHAIN (f_ovfl);
4226 f_ftop = TREE_CHAIN (f_gtop);
4227 f_goff = TREE_CHAIN (f_ftop);
4228 f_foff = TREE_CHAIN (f_goff);
4230 /* We maintain separate pointers and offsets for floating-point
4231 and integer arguments, but we need similar code in both cases.
4234 TOP be the top of the register save area;
4235 OFF be the offset from TOP of the next register;
4236 ADDR_RTX be the address of the argument;
4237 RSIZE be the number of bytes used to store the argument
4238 when it's in the register save area;
4239 OSIZE be the number of bytes used to store it when it's
4240 in the stack overflow area; and
4241 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4243 The code we want is:
4245 1: off &= -rsize; // round down
4248 4: addr_rtx = top - off;
4253 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4254 10: addr_rtx = ovfl + PADDING;
4258 [1] and [9] can sometimes be optimized away. */
4260 lab_false = gen_label_rtx ();
4261 lab_over = gen_label_rtx ();
4263 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4264 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4265 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4267 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4268 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4270 /* When floating-point registers are saved to the stack,
4271 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4272 of the float's precision. */
4273 rsize = UNITS_PER_HWFPVALUE;
4277 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4278 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4279 if (rsize > UNITS_PER_WORD)
4281 /* [1] Emit code for: off &= -rsize. */
4282 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4283 build_int_2 (-rsize, -1));
4284 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4285 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4288 /* Every overflow argument must take up at least UNITS_PER_WORD
4289 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
4290 than that, such as in the combination -mgp64 -msingle-float
4291 -fshort-double. Doubles passed in registers will then take
4292 up UNITS_PER_HWFPVALUE bytes, but those passed on the stack
4293 take up UNITS_PER_WORD bytes. */
4294 osize = MAX (rsize, UNITS_PER_WORD);
4296 /* [2] Emit code to branch if off == 0. */
4297 r = expand_expr (off, NULL_RTX, TYPE_MODE (TREE_TYPE (off)),
4299 emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
4302 /* [4] Emit code for: addr_rtx = top - off. */
4303 t = build (MINUS_EXPR, TREE_TYPE (top), top, off);
4304 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4306 emit_move_insn (addr_rtx, r);
4308 /* [5] Emit code for: off -= rsize. */
4309 t = build (MINUS_EXPR, TREE_TYPE (off), off, build_int_2 (rsize, 0));
4310 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4311 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4313 /* [7] Emit code to jump over the else clause, then the label
4316 emit_jump (lab_over);
4318 emit_label (lab_false);
4320 if (osize > UNITS_PER_WORD)
4322 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4323 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl,
4324 build_int_2 (osize - 1, 0));
4325 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t,
4326 build_int_2 (-osize, -1));
4327 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4328 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4331 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4332 post-increment ovfl by osize. On big-endian machines,
4333 the argument has OSIZE - RSIZE bytes of leading padding. */
4334 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl,
4336 if (BYTES_BIG_ENDIAN && osize > rsize)
4337 t = build (PLUS_EXPR, TREE_TYPE (t), t,
4338 build_int_2 (osize - rsize, 0));
4339 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4341 emit_move_insn (addr_rtx, r);
4344 emit_label (lab_over);
4346 if (BYTES_BIG_ENDIAN && rsize != size)
4347 addr_rtx = plus_constant (addr_rtx, rsize - size);
4350 addr_rtx = force_reg (Pmode, addr_rtx);
4351 r = gen_rtx_MEM (Pmode, addr_rtx);
4352 set_mem_alias_set (r, get_varargs_alias_set ());
4353 emit_move_insn (addr_rtx, r);
4361 HOST_WIDE_INT min_offset;
4363 /* ??? The original va-mips.h did always align, despite the fact
4364 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4365 increment mechanism. */
4367 if (TARGET_NEWABI && TYPE_ALIGN (type) > 64)
4369 else if (TARGET_64BIT)
4371 else if (TYPE_ALIGN (type) > 32)
4376 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4377 build_int_2 (align - 1, 0));
4378 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4380 /* If arguments of type TYPE must be passed on the stack,
4381 set MIN_OFFSET to the offset of the first stack parameter. */
4382 if (!MUST_PASS_IN_STACK (TYPE_MODE (type), type))
4384 else if (TARGET_NEWABI)
4385 min_offset = current_function_pretend_args_size;
4387 min_offset = REG_PARM_STACK_SPACE (current_function_decl);
4389 /* Make sure the new address is at least MIN_OFFSET bytes from
4390 the incoming argument pointer. */
4392 t = build (MAX_EXPR, TREE_TYPE (valist), t,
4393 make_tree (TREE_TYPE (valist),
4394 plus_constant (virtual_incoming_args_rtx,
4397 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4398 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4400 /* Everything past the alignment is standard. */
4401 return std_expand_builtin_va_arg (valist, type);
4405 /* Return true if it is possible to use left/right accesses for a
4406 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4407 returning true, update *OP, *LEFT and *RIGHT as follows:
4409 *OP is a BLKmode reference to the whole field.
4411 *LEFT is a QImode reference to the first byte if big endian or
4412 the last byte if little endian. This address can be used in the
4413 left-side instructions (lwl, swl, ldl, sdl).
4415 *RIGHT is a QImode reference to the opposite end of the field and
4416 can be used in the parterning right-side instruction. */
4419 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4420 rtx *left, rtx *right)
4424 /* Check that the operand really is a MEM. Not all the extv and
4425 extzv predicates are checked. */
4426 if (GET_CODE (*op) != MEM)
4429 /* Check that the size is valid. */
4430 if (width != 32 && (!TARGET_64BIT || width != 64))
4433 /* We can only access byte-aligned values. Since we are always passed
4434 a reference to the first byte of the field, it is not necessary to
4435 do anything with BITPOS after this check. */
4436 if (bitpos % BITS_PER_UNIT != 0)
4439 /* Reject aligned bitfields: we want to use a normal load or store
4440 instead of a left/right pair. */
4441 if (MEM_ALIGN (*op) >= width)
4444 /* Adjust *OP to refer to the whole field. This also has the effect
4445 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4446 *op = adjust_address (*op, BLKmode, 0);
4447 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4449 /* Get references to both ends of the field. We deliberately don't
4450 use the original QImode *OP for FIRST since the new BLKmode one
4451 might have a simpler address. */
4452 first = adjust_address (*op, QImode, 0);
4453 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4455 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4456 be the upper word and RIGHT the lower word. */
4457 if (TARGET_BIG_ENDIAN)
4458 *left = first, *right = last;
4460 *left = last, *right = first;
4466 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4467 Return true on success. We only handle cases where zero_extract is
4468 equivalent to sign_extract. */
4471 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4475 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4476 paradoxical word_mode subreg. This is the only case in which
4477 we allow the destination to be larger than the source. */
4478 if (GET_CODE (dest) == SUBREG
4479 && GET_MODE (dest) == DImode
4480 && SUBREG_BYTE (dest) == 0
4481 && GET_MODE (SUBREG_REG (dest)) == SImode)
4482 dest = SUBREG_REG (dest);
4484 /* After the above adjustment, the destination must be the same
4485 width as the source. */
4486 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4489 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4492 if (GET_MODE (dest) == DImode)
4494 emit_insn (gen_mov_ldl (dest, src, left));
4495 emit_insn (gen_mov_ldr (copy_rtx (dest), copy_rtx (src),
4496 right, copy_rtx (dest)));
4500 emit_insn (gen_mov_lwl (dest, src, left));
4501 emit_insn (gen_mov_lwr (copy_rtx (dest), copy_rtx (src),
4502 right, copy_rtx (dest)));
4508 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4512 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4516 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4519 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4521 if (GET_MODE (src) == DImode)
4523 emit_insn (gen_mov_sdl (dest, src, left));
4524 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4528 emit_insn (gen_mov_swl (dest, src, left));
4529 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4534 /* Set up globals to generate code for the ISA or processor
4535 described by INFO. */
4538 mips_set_architecture (const struct mips_cpu_info *info)
4542 mips_arch_info = info;
4543 mips_arch = info->cpu;
4544 mips_isa = info->isa;
4549 /* Likewise for tuning. */
4552 mips_set_tune (const struct mips_cpu_info *info)
4556 mips_tune_info = info;
4557 mips_tune = info->cpu;
4562 /* Set up the threshold for data to go into the small data area, instead
4563 of the normal data area, and detect any conflicts in the switches. */
4566 override_options (void)
4568 int i, start, regno;
4569 enum machine_mode mode;
4571 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4573 /* Interpret -mabi. */
4574 mips_abi = MIPS_ABI_DEFAULT;
4575 if (mips_abi_string != 0)
4577 if (strcmp (mips_abi_string, "32") == 0)
4579 else if (strcmp (mips_abi_string, "o64") == 0)
4581 else if (strcmp (mips_abi_string, "n32") == 0)
4583 else if (strcmp (mips_abi_string, "64") == 0)
4585 else if (strcmp (mips_abi_string, "eabi") == 0)
4586 mips_abi = ABI_EABI;
4588 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
4591 /* The following code determines the architecture and register size.
4592 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4593 The GAS and GCC code should be kept in sync as much as possible. */
4595 if (mips_arch_string != 0)
4596 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
4598 if (mips_isa_string != 0)
4600 /* Handle -mipsN. */
4601 char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
4602 const struct mips_cpu_info *isa_info;
4604 isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
4605 free (whole_isa_str);
4607 /* -march takes precedence over -mipsN, since it is more descriptive.
4608 There's no harm in specifying both as long as the ISA levels
4610 if (mips_arch_info != 0 && mips_isa != isa_info->isa)
4611 error ("-mips%s conflicts with the other architecture options, "
4612 "which specify a MIPS%d processor",
4613 mips_isa_string, mips_isa);
4615 /* Set architecture based on the given option. */
4616 mips_set_architecture (isa_info);
4619 if (mips_arch_info == 0)
4621 #ifdef MIPS_CPU_STRING_DEFAULT
4622 mips_set_architecture (mips_parse_cpu ("default CPU",
4623 MIPS_CPU_STRING_DEFAULT));
4625 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4629 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4630 error ("-march=%s is not compatible with the selected ABI",
4631 mips_arch_info->name);
4633 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4634 if (mips_tune_string != 0)
4635 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
4637 if (mips_tune_info == 0)
4638 mips_set_tune (mips_arch_info);
4640 if ((target_flags_explicit & MASK_64BIT) != 0)
4642 /* The user specified the size of the integer registers. Make sure
4643 it agrees with the ABI and ISA. */
4644 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4645 error ("-mgp64 used with a 32-bit processor");
4646 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4647 error ("-mgp32 used with a 64-bit ABI");
4648 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4649 error ("-mgp64 used with a 32-bit ABI");
4653 /* Infer the integer register size from the ABI and processor.
4654 Restrict ourselves to 32-bit registers if that's all the
4655 processor has, or if the ABI cannot handle 64-bit registers. */
4656 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4657 target_flags &= ~MASK_64BIT;
4659 target_flags |= MASK_64BIT;
4662 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4664 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4665 only one right answer here. */
4666 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4667 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4668 else if (!TARGET_64BIT && TARGET_FLOAT64)
4669 error ("unsupported combination: %s", "-mgp32 -mfp64");
4670 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4671 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4675 /* -msingle-float selects 32-bit float registers. Otherwise the
4676 float registers should be the same size as the integer ones. */
4677 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4678 target_flags |= MASK_FLOAT64;
4680 target_flags &= ~MASK_FLOAT64;
4683 /* End of code shared with GAS. */
4685 if ((target_flags_explicit & MASK_LONG64) == 0)
4687 /* If no type size setting options (-mlong64,-mint64,-mlong32)
4688 were used, then set the type sizes. In the EABI in 64 bit mode,
4689 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
4691 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4692 target_flags |= MASK_LONG64;
4694 target_flags &= ~MASK_LONG64;
4697 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4698 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4700 /* For some configurations, it is useful to have -march control
4701 the default setting of MASK_SOFT_FLOAT. */
4702 switch ((int) mips_arch)
4704 case PROCESSOR_R4100:
4705 case PROCESSOR_R4111:
4706 case PROCESSOR_R4120:
4707 target_flags |= MASK_SOFT_FLOAT;
4711 target_flags &= ~MASK_SOFT_FLOAT;
4717 flag_pcc_struct_return = 0;
4719 #if defined(USE_COLLECT2)
4720 /* For IRIX 5 or IRIX 6 with integrated O32 ABI support, USE_COLLECT2 is
4721 always defined when GNU as is not in use, but collect2 is only used
4722 for the O32 ABI, so override the toplev.c and target-def.h defaults
4723 for flag_gnu_linker, TARGET_ASM_{CONSTRUCTOR, DESTRUCTOR} and
4724 TARGET_HAVE_CTORS_DTORS.
4726 Since the IRIX 5 and IRIX 6 O32 assemblers cannot handle named
4727 sections, constructor/destructor handling depends on the ABI in use.
4729 Since USE_COLLECT2 is defined, we only need to restore the non-collect2
4730 defaults for the N32/N64 ABIs. */
4731 if (TARGET_IRIX && !TARGET_SGI_O32_AS)
4733 targetm.have_ctors_dtors = true;
4734 targetm.asm_out.constructor = default_named_section_asm_out_constructor;
4735 targetm.asm_out.destructor = default_named_section_asm_out_destructor;
4739 /* Handle some quirks of the IRIX 5 and IRIX 6 O32 assemblers. */
4741 if (TARGET_SGI_O32_AS)
4743 /* They don't recognize `.[248]byte'. */
4744 targetm.asm_out.unaligned_op.hi = "\t.align 0\n\t.half\t";
4745 targetm.asm_out.unaligned_op.si = "\t.align 0\n\t.word\t";
4746 /* The IRIX 6 O32 assembler gives an error for `align 0; .dword',
4747 contrary to the documentation, so disable it. */
4748 targetm.asm_out.unaligned_op.di = NULL;
4750 /* They cannot handle named sections. */
4751 targetm.have_named_sections = false;
4752 /* Therefore, EH_FRAME_SECTION_NAME isn't defined and we must use
4754 targetm.terminate_dw2_eh_frame_info = true;
4755 targetm.asm_out.eh_frame_section = collect2_eh_frame_section;
4757 /* They cannot handle debug information. */
4758 if (write_symbols != NO_DEBUG)
4760 /* Adapt wording to IRIX version: IRIX 5 only had a single ABI,
4761 so -mabi=32 isn't usually specified. */
4763 inform ("-g is only supported using GNU as,");
4765 inform ("-g is only supported using GNU as with -mabi=32,");
4766 inform ("-g option disabled");
4767 write_symbols = NO_DEBUG;
4771 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4773 /* If neither -mbranch-likely nor -mno-branch-likely was given
4774 on the command line, set MASK_BRANCHLIKELY based on the target
4777 By default, we enable use of Branch Likely instructions on
4778 all architectures which support them except for MIPS32 and MIPS64
4779 (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
4782 The MIPS32 and MIPS64 architecture specifications say "Software
4783 is strongly encouraged to avoid use of Branch Likely
4784 instructions, as they will be removed from a future revision
4785 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4786 issue those instructions unless instructed to do so by
4788 if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64))
4789 target_flags |= MASK_BRANCHLIKELY;
4791 target_flags &= ~MASK_BRANCHLIKELY;
4793 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4794 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
4796 /* The effect of -mabicalls isn't defined for the EABI. */
4797 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4799 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4800 target_flags &= ~MASK_ABICALLS;
4803 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4804 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4805 /* ??? -non_shared turns off pic code generation, but this is not
4807 if (TARGET_ABICALLS)
4810 if (mips_section_threshold > 0)
4811 warning ("-G is incompatible with PIC code which is the default");
4814 /* The MIPS and SGI o32 assemblers expect small-data variables to
4815 be declared before they are used. Although we once had code to
4816 do this, it was very invasive and fragile. It no longer seems
4817 worth the effort. */
4818 if (!TARGET_EXPLICIT_RELOCS && !TARGET_GAS)
4819 mips_section_threshold = 0;
4821 /* We switch to small data sections using ".section", which the native
4822 o32 irix assemblers don't understand. Disable -G accordingly.
4823 We must do this regardless of command-line options since otherwise
4824 the compiler would abort. */
4825 if (!targetm.have_named_sections)
4826 mips_section_threshold = 0;
4828 /* -membedded-pic is a form of PIC code suitable for embedded
4829 systems. All calls are made using PC relative addressing, and
4830 all data is addressed using the $gp register. This requires gas,
4831 which does most of the work, and GNU ld, which automatically
4832 expands PC relative calls which are out of range into a longer
4833 instruction sequence. All gcc really does differently is
4834 generate a different sequence for a switch. */
4835 if (TARGET_EMBEDDED_PIC)
4838 if (TARGET_ABICALLS)
4839 warning ("-membedded-pic and -mabicalls are incompatible");
4842 warning ("-G and -membedded-pic are incompatible");
4844 /* Setting mips_section_threshold is not required, because gas
4845 will force everything to be GP addressable anyhow, but
4846 setting it will cause gcc to make better estimates of the
4847 number of instructions required to access a particular data
4849 mips_section_threshold = 0x7fffffff;
4852 /* mips_split_addresses is a half-way house between explicit
4853 relocations and the traditional assembler macros. It can
4854 split absolute 32-bit symbolic constants into a high/lo_sum
4855 pair but uses macros for other sorts of access.
4857 Like explicit relocation support for REL targets, it relies
4858 on GNU extensions in the assembler and the linker.
4860 Although this code should work for -O0, it has traditionally
4861 been treated as an optimization. */
4862 if (TARGET_GAS && !TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4863 && optimize && !flag_pic
4864 && !ABI_HAS_64BIT_SYMBOLS)
4865 mips_split_addresses = 1;
4867 mips_split_addresses = 0;
4869 /* -mexplicit-relocs doesn't yet support non-PIC n64. We don't know
4870 how to generate %highest/%higher/%hi/%lo sequences. */
4871 if (mips_abi == ABI_64 && !TARGET_ABICALLS)
4873 if ((target_flags_explicit & target_flags & MASK_EXPLICIT_RELOCS) != 0)
4874 sorry ("non-PIC n64 with explicit relocations");
4875 target_flags &= ~MASK_EXPLICIT_RELOCS;
4878 /* Explicit relocations for "old" ABIs are a GNU extension. Unless
4879 the user has said otherwise, assume that they are not available
4880 with assemblers other than gas. */
4881 if (!TARGET_NEWABI && !TARGET_GAS
4882 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4883 target_flags &= ~MASK_EXPLICIT_RELOCS;
4885 /* Make -mabicalls -fno-unit-at-a-time imply -mno-explicit-relocs
4886 unless the user says otherwise.
4888 There are two problems here:
4890 (1) The value of an R_MIPS_GOT16 relocation depends on whether
4891 the symbol is local or global. We therefore need to know
4892 a symbol's binding before refering to it using %got().
4894 (2) R_MIPS_CALL16 can only be applied to global symbols.
4896 When not using -funit-at-a-time, a symbol's binding may change
4897 after it has been used. For example, the C++ front-end will
4898 initially assume that the typeinfo for an incomplete type will be
4899 comdat, on the basis that the type could be completed later in the
4900 file. But if the type never is completed, the typeinfo will become
4902 if (!flag_unit_at_a_time
4904 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4905 target_flags &= ~MASK_EXPLICIT_RELOCS;
4907 /* -mrnames says to use the MIPS software convention for register
4908 names instead of the hardware names (ie, $a0 instead of $4).
4909 We do this by switching the names in mips_reg_names, which the
4910 reg_names points into via the REGISTER_NAMES macro. */
4912 if (TARGET_NAME_REGS)
4913 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
4915 /* When compiling for the mips16, we can not use floating point. We
4916 record the original hard float value in mips16_hard_float. */
4919 if (TARGET_SOFT_FLOAT)
4920 mips16_hard_float = 0;
4922 mips16_hard_float = 1;
4923 target_flags |= MASK_SOFT_FLOAT;
4925 /* Don't run the scheduler before reload, since it tends to
4926 increase register pressure. */
4927 flag_schedule_insns = 0;
4929 /* Silently disable -mexplicit-relocs since it doesn't apply
4930 to mips16 code. Even so, it would overly pedantic to warn
4931 about "-mips16 -mexplicit-relocs", especially given that
4932 we use a %gprel() operator. */
4933 target_flags &= ~MASK_EXPLICIT_RELOCS;
4936 /* When using explicit relocs, we call dbr_schedule from within
4938 if (TARGET_EXPLICIT_RELOCS)
4940 mips_flag_delayed_branch = flag_delayed_branch;
4941 flag_delayed_branch = 0;
4944 #ifdef MIPS_TFMODE_FORMAT
4945 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4948 mips_print_operand_punct['?'] = 1;
4949 mips_print_operand_punct['#'] = 1;
4950 mips_print_operand_punct['/'] = 1;
4951 mips_print_operand_punct['&'] = 1;
4952 mips_print_operand_punct['!'] = 1;
4953 mips_print_operand_punct['*'] = 1;
4954 mips_print_operand_punct['@'] = 1;
4955 mips_print_operand_punct['.'] = 1;
4956 mips_print_operand_punct['('] = 1;
4957 mips_print_operand_punct[')'] = 1;
4958 mips_print_operand_punct['['] = 1;
4959 mips_print_operand_punct[']'] = 1;
4960 mips_print_operand_punct['<'] = 1;
4961 mips_print_operand_punct['>'] = 1;
4962 mips_print_operand_punct['{'] = 1;
4963 mips_print_operand_punct['}'] = 1;
4964 mips_print_operand_punct['^'] = 1;
4965 mips_print_operand_punct['$'] = 1;
4966 mips_print_operand_punct['+'] = 1;
4967 mips_print_operand_punct['~'] = 1;
4969 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4970 mips_char_to_class['t'] = T_REG;
4971 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4972 mips_char_to_class['h'] = HI_REG;
4973 mips_char_to_class['l'] = LO_REG;
4974 mips_char_to_class['x'] = MD_REGS;
4975 mips_char_to_class['b'] = ALL_REGS;
4976 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4977 TARGET_MIPS16 ? M16_NA_REGS :
4979 mips_char_to_class['e'] = LEA_REGS;
4980 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4981 mips_char_to_class['y'] = GR_REGS;
4982 mips_char_to_class['z'] = ST_REGS;
4983 mips_char_to_class['B'] = COP0_REGS;
4984 mips_char_to_class['C'] = COP2_REGS;
4985 mips_char_to_class['D'] = COP3_REGS;
4987 /* Set up array to map GCC register number to debug register number.
4988 Ignore the special purpose register numbers. */
4990 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4991 mips_dbx_regno[i] = -1;
4993 start = GP_DBX_FIRST - GP_REG_FIRST;
4994 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4995 mips_dbx_regno[i] = i + start;
4997 start = FP_DBX_FIRST - FP_REG_FIRST;
4998 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4999 mips_dbx_regno[i] = i + start;
5001 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
5002 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
5004 /* Set up array giving whether a given register can hold a given mode. */
5006 for (mode = VOIDmode;
5007 mode != MAX_MACHINE_MODE;
5008 mode = (enum machine_mode) ((int)mode + 1))
5010 register int size = GET_MODE_SIZE (mode);
5011 register enum mode_class class = GET_MODE_CLASS (mode);
5013 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5020 temp = (regno == FPSW_REGNUM);
5022 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5023 || FP_REG_P (regno));
5026 else if (GP_REG_P (regno))
5027 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5029 else if (FP_REG_P (regno))
5030 temp = ((regno % FP_INC) == 0)
5031 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
5032 && size <= UNITS_PER_FPVALUE)
5033 /* Allow integer modes that fit into a single
5034 register. We need to put integers into FPRs
5035 when using instructions like cvt and trunc. */
5036 || (class == MODE_INT && size <= UNITS_PER_FPREG)
5037 /* Allow TFmode for CCmode reloads. */
5038 || (ISA_HAS_8CC && mode == TFmode));
5040 else if (MD_REG_P (regno))
5041 temp = (class == MODE_INT
5042 && (size <= UNITS_PER_WORD
5043 || (regno == MD_REG_FIRST
5044 && size == 2 * UNITS_PER_WORD)));
5046 else if (ALL_COP_REG_P (regno))
5047 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5051 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5055 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5056 initialized yet, so we can't use that here. */
5057 gpr_mode = TARGET_64BIT ? DImode : SImode;
5059 /* Provide default values for align_* for 64-bit targets. */
5060 if (TARGET_64BIT && !TARGET_MIPS16)
5062 if (align_loops == 0)
5064 if (align_jumps == 0)
5066 if (align_functions == 0)
5067 align_functions = 8;
5070 /* Function to allocate machine-dependent function status. */
5071 init_machine_status = &mips_init_machine_status;
5073 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5075 mips_split_p[SYMBOL_GENERAL] = true;
5076 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5077 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5082 /* The high part is provided by a pseudo copy of $gp. */
5083 mips_split_p[SYMBOL_SMALL_DATA] = true;
5084 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5087 if (TARGET_EXPLICIT_RELOCS)
5089 /* Small data constants are kept whole until after reload,
5090 then lowered by mips_rewrite_small_data. */
5091 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5093 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5096 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5097 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5101 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5102 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5107 /* The HIGH and LO_SUM are matched by special .md patterns. */
5108 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5110 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5111 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5112 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5114 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5115 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5116 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5121 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5123 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5124 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5130 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5131 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5132 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5135 /* Default to working around R4000 errata only if the processor
5136 was selected explicitly. */
5137 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5138 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5139 target_flags |= MASK_FIX_R4000;
5142 /* Implement CONDITIONAL_REGISTER_USAGE. */
5145 mips_conditional_register_usage (void)
5147 if (!TARGET_HARD_FLOAT)
5151 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5152 fixed_regs[regno] = call_used_regs[regno] = 1;
5153 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5154 fixed_regs[regno] = call_used_regs[regno] = 1;
5156 else if (! ISA_HAS_8CC)
5160 /* We only have a single condition code register. We
5161 implement this by hiding all the condition code registers,
5162 and generating RTL that refers directly to ST_REG_FIRST. */
5163 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5164 fixed_regs[regno] = call_used_regs[regno] = 1;
5166 /* In mips16 mode, we permit the $t temporary registers to be used
5167 for reload. We prohibit the unused $s registers, since they
5168 are caller saved, and saving them via a mips16 register would
5169 probably waste more time than just reloading the value. */
5172 fixed_regs[18] = call_used_regs[18] = 1;
5173 fixed_regs[19] = call_used_regs[19] = 1;
5174 fixed_regs[20] = call_used_regs[20] = 1;
5175 fixed_regs[21] = call_used_regs[21] = 1;
5176 fixed_regs[22] = call_used_regs[22] = 1;
5177 fixed_regs[23] = call_used_regs[23] = 1;
5178 fixed_regs[26] = call_used_regs[26] = 1;
5179 fixed_regs[27] = call_used_regs[27] = 1;
5180 fixed_regs[30] = call_used_regs[30] = 1;
5182 /* fp20-23 are now caller saved. */
5183 if (mips_abi == ABI_64)
5186 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5187 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5189 /* Odd registers from fp21 to fp31 are now caller saved. */
5190 if (mips_abi == ABI_N32)
5193 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5194 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5198 /* Allocate a chunk of memory for per-function machine-dependent data. */
5199 static struct machine_function *
5200 mips_init_machine_status (void)
5202 return ((struct machine_function *)
5203 ggc_alloc_cleared (sizeof (struct machine_function)));
5206 /* On the mips16, we want to allocate $24 (T_REG) before other
5207 registers for instructions for which it is possible. This helps
5208 avoid shuffling registers around in order to set up for an xor,
5209 encouraging the compiler to use a cmp instead. */
5212 mips_order_regs_for_local_alloc (void)
5216 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5217 reg_alloc_order[i] = i;
5221 /* It really doesn't matter where we put register 0, since it is
5222 a fixed register anyhow. */
5223 reg_alloc_order[0] = 24;
5224 reg_alloc_order[24] = 0;
5229 /* The MIPS debug format wants all automatic variables and arguments
5230 to be in terms of the virtual frame pointer (stack pointer before
5231 any adjustment in the function), while the MIPS 3.0 linker wants
5232 the frame pointer to be the stack pointer after the initial
5233 adjustment. So, we do the adjustment here. The arg pointer (which
5234 is eliminated) points to the virtual frame pointer, while the frame
5235 pointer (which may be eliminated) points to the stack pointer after
5236 the initial adjustments. */
5239 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5241 rtx offset2 = const0_rtx;
5242 rtx reg = eliminate_constant_term (addr, &offset2);
5245 offset = INTVAL (offset2);
5247 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5248 || reg == hard_frame_pointer_rtx)
5250 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5251 ? compute_frame_size (get_frame_size ())
5252 : cfun->machine->frame.total_size;
5254 /* MIPS16 frame is smaller */
5255 if (frame_pointer_needed && TARGET_MIPS16)
5256 frame_size -= cfun->machine->frame.args_size;
5258 offset = offset - frame_size;
5261 /* sdbout_parms does not want this to crash for unrecognized cases. */
5263 else if (reg != arg_pointer_rtx)
5264 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5271 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5273 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5274 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5275 'h' OP is HIGH, prints %hi(X),
5276 'd' output integer constant in decimal,
5277 'z' if the operand is 0, use $0 instead of normal operand.
5278 'D' print second part of double-word register or memory operand.
5279 'L' print low-order register of double-word register operand.
5280 'M' print high-order register of double-word register operand.
5281 'C' print part of opcode for a branch condition.
5282 'F' print part of opcode for a floating-point branch condition.
5283 'N' print part of opcode for a branch condition, inverted.
5284 'W' print part of opcode for a floating-point branch condition, inverted.
5285 'S' OP is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5286 'B' print 'z' for EQ, 'n' for NE
5287 'b' print 'n' for EQ, 'z' for NE
5288 'T' print 'f' for EQ, 't' for NE
5289 't' print 't' for EQ, 'f' for NE
5290 'Z' print register and a comma, but print nothing for $fcc0
5291 'R' print the reloc associated with LO_SUM
5293 The punctuation characters are:
5295 '(' Turn on .set noreorder
5296 ')' Turn on .set reorder
5297 '[' Turn on .set noat
5299 '<' Turn on .set nomacro
5300 '>' Turn on .set macro
5301 '{' Turn on .set volatile (not GAS)
5302 '}' Turn on .set novolatile (not GAS)
5303 '&' Turn on .set noreorder if filling delay slots
5304 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5305 '!' Turn on .set nomacro if filling delay slots
5306 '#' Print nop if in a .set noreorder section.
5307 '/' Like '#', but does nothing within a delayed branch sequence
5308 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5309 '@' Print the name of the assembler temporary register (at or $1).
5310 '.' Print the name of the register with a hard-wired zero (zero or $0).
5311 '^' Print the name of the pic call-through register (t9 or $25).
5312 '$' Print the name of the stack pointer register (sp or $29).
5313 '+' Print the name of the gp register (usually gp or $28).
5314 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5317 print_operand (FILE *file, rtx op, int letter)
5319 register enum rtx_code code;
5321 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5326 if (mips_branch_likely)
5331 fputs (reg_names [GP_REG_FIRST + 1], file);
5335 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5339 fputs (reg_names [GP_REG_FIRST + 0], file);
5343 fputs (reg_names[STACK_POINTER_REGNUM], file);
5347 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5351 if (final_sequence != 0 && set_noreorder++ == 0)
5352 fputs (".set\tnoreorder\n\t", file);
5356 if (final_sequence != 0)
5358 if (set_noreorder++ == 0)
5359 fputs (".set\tnoreorder\n\t", file);
5361 if (set_nomacro++ == 0)
5362 fputs (".set\tnomacro\n\t", file);
5367 if (final_sequence != 0 && set_nomacro++ == 0)
5368 fputs ("\n\t.set\tnomacro", file);
5372 if (set_noreorder != 0)
5373 fputs ("\n\tnop", file);
5377 /* Print an extra newline so that the delayed insn is separated
5378 from the following ones. This looks neater and is consistent
5379 with non-nop delayed sequences. */
5380 if (set_noreorder != 0 && final_sequence == 0)
5381 fputs ("\n\tnop\n", file);
5385 if (set_noreorder++ == 0)
5386 fputs (".set\tnoreorder\n\t", file);
5390 if (set_noreorder == 0)
5391 error ("internal error: %%) found without a %%( in assembler pattern");
5393 else if (--set_noreorder == 0)
5394 fputs ("\n\t.set\treorder", file);
5399 if (set_noat++ == 0)
5400 fputs (".set\tnoat\n\t", file);
5405 error ("internal error: %%] found without a %%[ in assembler pattern");
5406 else if (--set_noat == 0)
5407 fputs ("\n\t.set\tat", file);
5412 if (set_nomacro++ == 0)
5413 fputs (".set\tnomacro\n\t", file);
5417 if (set_nomacro == 0)
5418 error ("internal error: %%> found without a %%< in assembler pattern");
5419 else if (--set_nomacro == 0)
5420 fputs ("\n\t.set\tmacro", file);
5425 if (set_volatile++ == 0)
5426 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5430 if (set_volatile == 0)
5431 error ("internal error: %%} found without a %%{ in assembler pattern");
5432 else if (--set_volatile == 0)
5433 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5439 if (align_labels_log > 0)
5440 ASM_OUTPUT_ALIGN (file, align_labels_log);
5445 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5454 error ("PRINT_OPERAND null pointer");
5458 code = GET_CODE (op);
5463 case EQ: fputs ("eq", file); break;
5464 case NE: fputs ("ne", file); break;
5465 case GT: fputs ("gt", file); break;
5466 case GE: fputs ("ge", file); break;
5467 case LT: fputs ("lt", file); break;
5468 case LE: fputs ("le", file); break;
5469 case GTU: fputs ("gtu", file); break;
5470 case GEU: fputs ("geu", file); break;
5471 case LTU: fputs ("ltu", file); break;
5472 case LEU: fputs ("leu", file); break;
5474 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5477 else if (letter == 'N')
5480 case EQ: fputs ("ne", file); break;
5481 case NE: fputs ("eq", file); break;
5482 case GT: fputs ("le", file); break;
5483 case GE: fputs ("lt", file); break;
5484 case LT: fputs ("ge", file); break;
5485 case LE: fputs ("gt", file); break;
5486 case GTU: fputs ("leu", file); break;
5487 case GEU: fputs ("ltu", file); break;
5488 case LTU: fputs ("geu", file); break;
5489 case LEU: fputs ("gtu", file); break;
5491 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5494 else if (letter == 'F')
5497 case EQ: fputs ("c1f", file); break;
5498 case NE: fputs ("c1t", file); break;
5500 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5503 else if (letter == 'W')
5506 case EQ: fputs ("c1t", file); break;
5507 case NE: fputs ("c1f", file); break;
5509 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5512 else if (letter == 'h')
5514 if (GET_CODE (op) == HIGH)
5517 print_operand_reloc (file, op, mips_hi_relocs);
5520 else if (letter == 'R')
5521 print_operand_reloc (file, op, mips_lo_relocs);
5523 else if (letter == 'S')
5527 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5528 assemble_name (file, buffer);
5531 else if (letter == 'Z')
5533 register int regnum;
5538 regnum = REGNO (op);
5539 if (! ST_REG_P (regnum))
5542 if (regnum != ST_REG_FIRST)
5543 fprintf (file, "%s,", reg_names[regnum]);
5546 else if (code == REG || code == SUBREG)
5548 register int regnum;
5551 regnum = REGNO (op);
5553 regnum = true_regnum (op);
5555 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5556 || (letter == 'L' && WORDS_BIG_ENDIAN)
5560 fprintf (file, "%s", reg_names[regnum]);
5563 else if (code == MEM)
5566 output_address (plus_constant (XEXP (op, 0), 4));
5568 output_address (XEXP (op, 0));
5571 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5572 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5574 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5575 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5577 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5578 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5580 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5581 fputs (reg_names[GP_REG_FIRST], file);
5583 else if (letter == 'd' || letter == 'x' || letter == 'X')
5584 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5586 else if (letter == 'B')
5587 fputs (code == EQ ? "z" : "n", file);
5588 else if (letter == 'b')
5589 fputs (code == EQ ? "n" : "z", file);
5590 else if (letter == 'T')
5591 fputs (code == EQ ? "f" : "t", file);
5592 else if (letter == 't')
5593 fputs (code == EQ ? "t" : "f", file);
5595 else if (CONST_GP_P (op))
5596 print_operand (file, XEXP (op, 0), letter);
5599 output_addr_const (file, op);
5603 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5604 RELOCS is the array of relocations to use. */
5607 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5609 enum mips_symbol_type symbol_type;
5612 HOST_WIDE_INT offset;
5614 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5615 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5617 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5618 mips_split_const (op, &base, &offset);
5619 if (UNSPEC_ADDRESS_P (base))
5620 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5622 fputs (relocs[symbol_type], file);
5623 output_addr_const (file, op);
5624 for (p = relocs[symbol_type]; *p != 0; p++)
5629 /* Output address operand X to FILE. */
5632 print_operand_address (FILE *file, rtx x)
5634 struct mips_address_info addr;
5636 if (mips_classify_address (&addr, x, word_mode, true))
5640 print_operand (file, addr.offset, 0);
5641 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5644 case ADDRESS_LO_SUM:
5645 print_operand (file, addr.offset, 'R');
5646 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5649 case ADDRESS_CONST_INT:
5650 case ADDRESS_SYMBOLIC:
5651 output_addr_const (file, x);
5657 /* Target hook for assembling integer objects. It appears that the Irix
5658 6 assembler can't handle 64-bit decimal integers, so avoid printing
5659 such an integer here. */
5662 mips_assemble_integer (rtx x, unsigned int size, int aligned_p)
5664 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
5666 fputs ("\t.dword\t", asm_out_file);
5667 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
5668 output_addr_const (asm_out_file, x);
5670 print_operand (asm_out_file, x, 'X');
5671 fputc ('\n', asm_out_file);
5674 return default_assemble_integer (x, size, aligned_p);
5677 /* When using assembler macros, keep track of all of small-data externs
5678 so that mips_file_end can emit the appropriate declarations for them.
5680 In most cases it would be safe (though pointless) to emit .externs
5681 for other symbols too. One exception is when an object is within
5682 the -G limit but declared by the user to be in a section other
5683 than .sbss or .sdata. */
5686 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5688 register struct extern_list *p;
5690 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5692 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5693 p->next = extern_head;
5695 p->size = int_size_in_bytes (TREE_TYPE (decl));
5699 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5701 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5702 p->next = extern_head;
5713 irix_output_external_libcall (rtx fun)
5715 register struct extern_list *p;
5717 if (mips_abi == ABI_32)
5719 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5720 p->next = extern_head;
5721 p->name = XSTR (fun, 0);
5728 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5729 put out a MIPS ECOFF file and a stab. */
5732 mips_output_filename (FILE *stream, const char *name)
5734 char ltext_label_name[100];
5736 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5738 if (write_symbols == DWARF2_DEBUG)
5740 else if (mips_output_filename_first_time)
5742 mips_output_filename_first_time = 0;
5744 current_function_file = name;
5745 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5746 /* This tells mips-tfile that stabs will follow. */
5747 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5748 fprintf (stream, "\t#@stabs\n");
5751 else if (write_symbols == DBX_DEBUG)
5753 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5754 fprintf (stream, "%s", ASM_STABS_OP);
5755 output_quoted_string (stream, name);
5756 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5759 else if (name != current_function_file
5760 && strcmp (name, current_function_file) != 0)
5763 current_function_file = name;
5764 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5768 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5769 as well as a .loc, since it is possible that MIPS ECOFF might not be
5770 able to represent the location for inlines that come from a different
5774 mips_output_lineno (FILE *stream, int line)
5776 if (write_symbols == DBX_DEBUG)
5779 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5780 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5781 LOCAL_LABEL_PREFIX, sym_lineno);
5785 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
5786 LABEL_AFTER_LOC (stream);
5790 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5791 that should be written before the opening quote, such as "\t.ascii\t"
5792 for real string data or "\t# " for a comment. */
5795 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5800 register const unsigned char *string =
5801 (const unsigned char *)string_param;
5803 fprintf (stream, "%s\"", prefix);
5804 for (i = 0; i < len; i++)
5806 register int c = string[i];
5812 putc ('\\', stream);
5817 case TARGET_NEWLINE:
5818 fputs ("\\n", stream);
5820 && (((c = string[i+1]) >= '\040' && c <= '~')
5821 || c == TARGET_TAB))
5822 cur_pos = 32767; /* break right here */
5828 fputs ("\\t", stream);
5833 fputs ("\\f", stream);
5838 fputs ("\\b", stream);
5843 fputs ("\\r", stream);
5848 if (c >= ' ' && c < 0177)
5855 fprintf (stream, "\\%03o", c);
5860 if (cur_pos > 72 && i+1 < len)
5863 fprintf (stream, "\"\n%s\"", prefix);
5866 fprintf (stream, "\"\n");
5869 /* Implement TARGET_ASM_FILE_START. */
5872 mips_file_start (void)
5874 default_file_start ();
5876 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5877 inside of a .set noreorder section jumps to a label outside of the .set
5878 noreorder section. Revision 2.20 just set nobopt silently rather than
5881 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5882 fprintf (asm_out_file, "\t.set\tnobopt\n");
5886 #if defined(OBJECT_FORMAT_ELF) && !TARGET_IRIX
5887 /* Generate a special section to describe the ABI switches used to
5888 produce the resultant binary. This used to be done by the assembler
5889 setting bits in the ELF header's flags field, but we have run out of
5890 bits. GDB needs this information in order to be able to correctly
5891 debug these binaries. See the function mips_gdbarch_init() in
5892 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5893 causes unnecessary IRIX 6 ld warnings. */
5894 const char * abi_string = NULL;
5898 case ABI_32: abi_string = "abi32"; break;
5899 case ABI_N32: abi_string = "abiN32"; break;
5900 case ABI_64: abi_string = "abi64"; break;
5901 case ABI_O64: abi_string = "abiO64"; break;
5902 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5906 /* Note - we use fprintf directly rather than called named_section()
5907 because in this way we can avoid creating an allocated section. We
5908 do not want this section to take up any space in the running
5910 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5912 /* Restore the default section. */
5913 fprintf (asm_out_file, "\t.previous\n");
5917 /* Generate the pseudo ops that System V.4 wants. */
5918 #ifndef ABICALLS_ASM_OP
5919 #define ABICALLS_ASM_OP "\t.abicalls"
5921 if (TARGET_ABICALLS)
5922 /* ??? but do not want this (or want pic0) if -non-shared? */
5923 fprintf (asm_out_file, "%s\n", ABICALLS_ASM_OP);
5926 fprintf (asm_out_file, "\t.set\tmips16\n");
5928 if (flag_verbose_asm)
5929 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5931 mips_section_threshold, mips_arch_info->name, mips_isa);
5934 #ifdef BSS_SECTION_ASM_OP
5935 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5936 in the use of sbss. */
5939 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5940 unsigned HOST_WIDE_INT size, int align)
5942 extern tree last_assemble_variable_decl;
5944 if (mips_in_small_data_p (decl))
5945 named_section (0, ".sbss", 0);
5948 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5949 last_assemble_variable_decl = decl;
5950 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5951 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5955 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5956 .externs for any small-data variables that turned out to be external. */
5959 mips_file_end (void)
5962 struct extern_list *p;
5966 fputs ("\n", asm_out_file);
5968 for (p = extern_head; p != 0; p = p->next)
5970 name_tree = get_identifier (p->name);
5972 /* Positively ensure only one .extern for any given symbol. */
5973 if (!TREE_ASM_WRITTEN (name_tree)
5974 && TREE_SYMBOL_REFERENCED (name_tree))
5976 TREE_ASM_WRITTEN (name_tree) = 1;
5977 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5978 `.global name .text' directive for every used but
5979 undefined function. If we don't, the linker may perform
5980 an optimization (skipping over the insns that set $gp)
5981 when it is unsafe. */
5982 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5984 fputs ("\t.globl ", asm_out_file);
5985 assemble_name (asm_out_file, p->name);
5986 fputs (" .text\n", asm_out_file);
5990 fputs ("\t.extern\t", asm_out_file);
5991 assemble_name (asm_out_file, p->name);
5992 fprintf (asm_out_file, ", %d\n", p->size);
5999 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as
6000 the elfos.h version, but we also need to handle -muninit-const-in-rodata
6001 and the limitations of the SGI o32 assembler. */
6004 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
6005 unsigned HOST_WIDE_INT size,
6008 /* If the target wants uninitialized const declarations in
6009 .rdata then don't put them in .comm. */
6010 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
6011 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
6012 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
6014 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
6015 targetm.asm_out.globalize_label (stream, name);
6017 readonly_data_section ();
6018 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6019 mips_declare_object (stream, name, "",
6020 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
6023 else if (TARGET_SGI_O32_AS)
6025 /* The SGI o32 assembler doesn't accept an alignment, so round up
6026 the size instead. */
6027 size += (align / BITS_PER_UNIT) - 1;
6028 size -= size % (align / BITS_PER_UNIT);
6029 mips_declare_object (stream, name, "\n\t.comm\t",
6030 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6033 mips_declare_object (stream, name, "\n\t.comm\t",
6034 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6035 size, align / BITS_PER_UNIT);
6038 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6039 macros, mark the symbol as written so that mips_file_end won't emit an
6040 .extern for it. STREAM is the output file, NAME is the name of the
6041 symbol, INIT_STRING is the string that should be written before the
6042 symbol and FINAL_STRING is the string that should be written after it.
6043 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6046 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6047 const char *final_string, ...)
6051 fputs (init_string, stream);
6052 assemble_name (stream, name);
6053 va_start (ap, final_string);
6054 vfprintf (stream, final_string, ap);
6057 if (!TARGET_EXPLICIT_RELOCS)
6059 tree name_tree = get_identifier (name);
6060 TREE_ASM_WRITTEN (name_tree) = 1;
6064 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6065 extern int size_directive_output;
6067 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6068 definitions except that it uses mips_declare_object() to emit the label. */
6071 mips_declare_object_name (FILE *stream, const char *name,
6072 tree decl ATTRIBUTE_UNUSED)
6074 if (!TARGET_SGI_O32_AS)
6076 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6077 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6080 size_directive_output = 0;
6081 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6085 size_directive_output = 1;
6086 size = int_size_in_bytes (TREE_TYPE (decl));
6087 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6091 mips_declare_object (stream, name, "", ":\n", 0);
6094 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6097 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6101 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6102 if (!TARGET_SGI_O32_AS
6103 && !flag_inhibit_size_directive
6104 && DECL_SIZE (decl) != 0
6105 && !at_end && top_level
6106 && DECL_INITIAL (decl) == error_mark_node
6107 && !size_directive_output)
6111 size_directive_output = 1;
6112 size = int_size_in_bytes (TREE_TYPE (decl));
6113 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6118 /* Return true if X is a small data address that can be rewritten
6122 mips_rewrite_small_data_p (rtx x)
6124 enum mips_symbol_type symbol_type;
6126 return (TARGET_EXPLICIT_RELOCS
6127 && mips_symbolic_constant_p (x, &symbol_type)
6128 && symbol_type == SYMBOL_SMALL_DATA);
6132 /* A for_each_rtx callback for small_data_pattern. */
6135 small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6137 if (GET_CODE (*loc) == LO_SUM)
6140 return mips_rewrite_small_data_p (*loc);
6143 /* Return true if OP refers to small data symbols directly, not through
6147 small_data_pattern (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
6149 return (GET_CODE (op) != SEQUENCE
6150 && for_each_rtx (&op, small_data_pattern_1, 0));
6153 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6156 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6158 if (mips_rewrite_small_data_p (*loc))
6159 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6161 if (GET_CODE (*loc) == LO_SUM)
6167 /* If possible, rewrite OP so that it refers to small data using
6168 explicit relocations. */
6171 mips_rewrite_small_data (rtx op)
6173 op = copy_insn (op);
6174 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6178 /* Return true if the current function has an insn that implicitly
6182 mips_function_has_gp_insn (void)
6184 /* Don't bother rechecking if we found one last time. */
6185 if (!cfun->machine->has_gp_insn_p)
6189 push_topmost_sequence ();
6190 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6192 && GET_CODE (PATTERN (insn)) != USE
6193 && GET_CODE (PATTERN (insn)) != CLOBBER
6194 && (get_attr_got (insn) != GOT_UNSET
6195 || small_data_pattern (PATTERN (insn), VOIDmode)))
6197 pop_topmost_sequence ();
6199 cfun->machine->has_gp_insn_p = (insn != 0);
6201 return cfun->machine->has_gp_insn_p;
6205 /* Return the register that should be used as the global pointer
6206 within this function. Return 0 if the function doesn't need
6207 a global pointer. */
6210 mips_global_pointer (void)
6214 /* $gp is always available in non-abicalls code. */
6215 if (!TARGET_ABICALLS)
6216 return GLOBAL_POINTER_REGNUM;
6218 /* We must always provide $gp when it is used implicitly. */
6219 if (!TARGET_EXPLICIT_RELOCS)
6220 return GLOBAL_POINTER_REGNUM;
6222 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6224 if (current_function_profile)
6225 return GLOBAL_POINTER_REGNUM;
6227 /* If the function has a nonlocal goto, $gp must hold the correct
6228 global pointer for the target function. */
6229 if (current_function_has_nonlocal_goto)
6230 return GLOBAL_POINTER_REGNUM;
6232 /* If the gp is never referenced, there's no need to initialize it.
6233 Note that reload can sometimes introduce constant pool references
6234 into a function that otherwise didn't need them. For example,
6235 suppose we have an instruction like:
6237 (set (reg:DF R1) (float:DF (reg:SI R2)))
6239 If R2 turns out to be constant such as 1, the instruction may have a
6240 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6241 using this constant if R2 doesn't get allocated to a register.
6243 In cases like these, reload will have added the constant to the pool
6244 but no instruction will yet refer to it. */
6245 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6246 && !current_function_uses_const_pool
6247 && !mips_function_has_gp_insn ())
6250 /* We need a global pointer, but perhaps we can use a call-clobbered
6251 register instead of $gp. */
6252 if (TARGET_NEWABI && current_function_is_leaf)
6253 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6254 if (!regs_ever_live[regno]
6255 && call_used_regs[regno]
6256 && !fixed_regs[regno]
6257 && regno != PIC_FUNCTION_ADDR_REGNUM)
6260 return GLOBAL_POINTER_REGNUM;
6264 /* Return true if the current function must save REGNO. */
6267 mips_save_reg_p (unsigned int regno)
6269 /* We only need to save $gp for NewABI PIC. */
6270 if (regno == GLOBAL_POINTER_REGNUM)
6271 return (TARGET_ABICALLS && TARGET_NEWABI
6272 && cfun->machine->global_pointer == regno);
6274 /* Check call-saved registers. */
6275 if (regs_ever_live[regno] && !call_used_regs[regno])
6278 /* We need to save the old frame pointer before setting up a new one. */
6279 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6282 /* We need to save the incoming return address if it is ever clobbered
6283 within the function. */
6284 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6291 return_type = DECL_RESULT (current_function_decl);
6293 /* $18 is a special case in mips16 code. It may be used to call
6294 a function which returns a floating point value, but it is
6295 marked in call_used_regs. */
6296 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6299 /* $31 is also a special case. It will be used to copy a return
6300 value into the floating point registers if the return value is
6302 if (regno == GP_REG_FIRST + 31
6303 && mips16_hard_float
6304 && !aggregate_value_p (return_type, current_function_decl)
6305 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6306 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6314 /* Return the bytes needed to compute the frame pointer from the current
6315 stack pointer. SIZE is the size (in bytes) of the local variables.
6317 Mips stack frames look like:
6319 Before call After call
6320 +-----------------------+ +-----------------------+
6323 | caller's temps. | | caller's temps. |
6325 +-----------------------+ +-----------------------+
6327 | arguments on stack. | | arguments on stack. |
6329 +-----------------------+ +-----------------------+
6330 | 4 words to save | | 4 words to save |
6331 | arguments passed | | arguments passed |
6332 | in registers, even | | in registers, even |
6333 SP->| if not passed. | VFP->| if not passed. |
6334 +-----------------------+ +-----------------------+
6336 | fp register save |
6338 +-----------------------+
6340 | gp register save |
6342 +-----------------------+
6346 +-----------------------+
6348 | alloca allocations |
6350 +-----------------------+
6352 | GP save for V.4 abi |
6354 +-----------------------+
6356 | arguments on stack |
6358 +-----------------------+
6360 | arguments passed |
6361 | in registers, even |
6362 low SP->| if not passed. |
6363 memory +-----------------------+
6368 compute_frame_size (HOST_WIDE_INT size)
6371 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6372 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6373 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6374 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6375 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6376 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6377 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6378 unsigned int mask; /* mask of saved gp registers */
6379 unsigned int fmask; /* mask of saved fp registers */
6381 cfun->machine->global_pointer = mips_global_pointer ();
6387 var_size = MIPS_STACK_ALIGN (size);
6388 args_size = current_function_outgoing_args_size;
6389 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6391 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6392 functions. If the function has local variables, we're committed
6393 to allocating it anyway. Otherwise reclaim it here. */
6394 if (var_size == 0 && current_function_is_leaf)
6395 cprestore_size = args_size = 0;
6397 /* The MIPS 3.0 linker does not like functions that dynamically
6398 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6399 looks like we are trying to create a second frame pointer to the
6400 function, so allocate some stack space to make it happy. */
6402 if (args_size == 0 && current_function_calls_alloca)
6403 args_size = 4 * UNITS_PER_WORD;
6405 total_size = var_size + args_size + cprestore_size;
6407 /* Calculate space needed for gp registers. */
6408 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6409 if (mips_save_reg_p (regno))
6411 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6412 mask |= 1 << (regno - GP_REG_FIRST);
6415 /* We need to restore these for the handler. */
6416 if (current_function_calls_eh_return)
6421 regno = EH_RETURN_DATA_REGNO (i);
6422 if (regno == INVALID_REGNUM)
6424 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6425 mask |= 1 << (regno - GP_REG_FIRST);
6429 /* This loop must iterate over the same space as its companion in
6430 save_restore_insns. */
6431 for (regno = (FP_REG_LAST - FP_INC + 1);
6432 regno >= FP_REG_FIRST;
6435 if (mips_save_reg_p (regno))
6437 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6438 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6442 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6443 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6445 /* Add in space reserved on the stack by the callee for storing arguments
6446 passed in registers. */
6448 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6450 /* Save other computed information. */
6451 cfun->machine->frame.total_size = total_size;
6452 cfun->machine->frame.var_size = var_size;
6453 cfun->machine->frame.args_size = args_size;
6454 cfun->machine->frame.cprestore_size = cprestore_size;
6455 cfun->machine->frame.gp_reg_size = gp_reg_size;
6456 cfun->machine->frame.fp_reg_size = fp_reg_size;
6457 cfun->machine->frame.mask = mask;
6458 cfun->machine->frame.fmask = fmask;
6459 cfun->machine->frame.initialized = reload_completed;
6460 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6461 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6465 HOST_WIDE_INT offset;
6467 offset = (args_size + cprestore_size + var_size
6468 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6469 cfun->machine->frame.gp_sp_offset = offset;
6470 cfun->machine->frame.gp_save_offset = offset - total_size;
6474 cfun->machine->frame.gp_sp_offset = 0;
6475 cfun->machine->frame.gp_save_offset = 0;
6480 HOST_WIDE_INT offset;
6482 offset = (args_size + cprestore_size + var_size
6483 + gp_reg_rounded + fp_reg_size
6484 - FP_INC * UNITS_PER_FPREG);
6485 cfun->machine->frame.fp_sp_offset = offset;
6486 cfun->machine->frame.fp_save_offset = offset - total_size;
6490 cfun->machine->frame.fp_sp_offset = 0;
6491 cfun->machine->frame.fp_save_offset = 0;
6494 /* Ok, we're done. */
6498 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6499 pointer or argument pointer. TO is either the stack pointer or
6500 hard frame pointer. */
6503 mips_initial_elimination_offset (int from, int to)
6505 HOST_WIDE_INT offset;
6507 compute_frame_size (get_frame_size ());
6509 /* Set OFFSET to the offset from the stack pointer. */
6512 case FRAME_POINTER_REGNUM:
6516 case ARG_POINTER_REGNUM:
6517 offset = cfun->machine->frame.total_size;
6519 offset -= current_function_pretend_args_size;
6526 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6527 offset -= cfun->machine->frame.args_size;
6532 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6533 back to a previous frame. */
6535 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6540 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6543 /* Use FN to save or restore register REGNO. MODE is the register's
6544 mode and OFFSET is the offset of its save slot from the current
6548 mips_save_restore_reg (enum machine_mode mode, int regno,
6549 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6553 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6554 if (!current_function_calls_eh_return)
6555 RTX_UNCHANGING_P (mem) = 1;
6557 fn (gen_rtx_REG (mode, regno), mem);
6561 /* Call FN for each register that is saved by the current function.
6562 SP_OFFSET is the offset of the current stack pointer from the start
6566 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6568 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6570 enum machine_mode fpr_mode;
6571 HOST_WIDE_INT offset;
6574 /* Save registers starting from high to low. The debuggers prefer at least
6575 the return register be stored at func+4, and also it allows us not to
6576 need a nop in the epilog if at least one register is reloaded in
6577 addition to return address. */
6578 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6579 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6580 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6582 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6583 offset -= GET_MODE_SIZE (gpr_mode);
6586 /* This loop must iterate over the same space as its companion in
6587 compute_frame_size. */
6588 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6589 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6590 for (regno = (FP_REG_LAST - FP_INC + 1);
6591 regno >= FP_REG_FIRST;
6593 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6595 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6596 offset -= GET_MODE_SIZE (fpr_mode);
6601 /* If we're generating n32 or n64 abicalls, and the current function
6602 does not use $28 as its global pointer, emit a cplocal directive.
6603 Use pic_offset_table_rtx as the argument to the directive. */
6606 mips_output_cplocal (void)
6608 if (!TARGET_EXPLICIT_RELOCS
6609 && cfun->machine->global_pointer > 0
6610 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6611 output_asm_insn (".cplocal %+", 0);
6614 /* If we're generating n32 or n64 abicalls, emit instructions
6615 to set up the global pointer. */
6618 mips_emit_loadgp (void)
6620 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6622 rtx addr, offset, incoming_address;
6624 addr = XEXP (DECL_RTL (current_function_decl), 0);
6625 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6626 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6627 emit_insn (gen_loadgp (offset, incoming_address));
6628 if (!TARGET_EXPLICIT_RELOCS)
6629 emit_insn (gen_loadgp_blockage ());
6633 /* Set up the stack and frame (if desired) for the function. */
6636 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6639 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6641 /* ??? When is this really needed? At least the GNU assembler does not
6642 need the source filename more than once in the file, beyond what is
6643 emitted by the debug information. */
6645 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6647 #ifdef SDB_DEBUGGING_INFO
6648 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6649 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl), 0);
6652 /* In mips16 mode, we may need to generate a 32 bit to handle
6653 floating point arguments. The linker will arrange for any 32 bit
6654 functions to call this stub, which will then jump to the 16 bit
6656 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6657 && current_function_args_info.fp_code != 0)
6658 build_mips16_function_stub (file);
6660 if (!FUNCTION_NAME_ALREADY_DECLARED)
6662 /* Get the function name the same way that toplev.c does before calling
6663 assemble_start_function. This is needed so that the name used here
6664 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6665 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6667 if (!flag_inhibit_size_directive)
6669 fputs ("\t.ent\t", file);
6670 assemble_name (file, fnname);
6674 assemble_name (file, fnname);
6675 fputs (":\n", file);
6678 if (!flag_inhibit_size_directive)
6680 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6682 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6683 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6684 ", args= " HOST_WIDE_INT_PRINT_DEC
6685 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6686 (reg_names[(frame_pointer_needed)
6687 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6688 ((frame_pointer_needed && TARGET_MIPS16)
6689 ? tsize - cfun->machine->frame.args_size
6691 reg_names[GP_REG_FIRST + 31],
6692 cfun->machine->frame.var_size,
6693 cfun->machine->frame.num_gp,
6694 cfun->machine->frame.num_fp,
6695 cfun->machine->frame.args_size,
6696 cfun->machine->frame.cprestore_size);
6698 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6699 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6700 cfun->machine->frame.mask,
6701 cfun->machine->frame.gp_save_offset);
6702 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6703 cfun->machine->frame.fmask,
6704 cfun->machine->frame.fp_save_offset);
6707 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6708 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6711 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6713 /* Handle the initialization of $gp for SVR4 PIC. */
6714 if (!cfun->machine->all_noreorder_p)
6715 output_asm_insn ("%(.cpload\t%^%)", 0);
6717 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6719 else if (cfun->machine->all_noreorder_p)
6720 output_asm_insn ("%(%<", 0);
6722 /* Tell the assembler which register we're using as the global
6723 pointer. This is needed for thunks, since they can use either
6724 explicit relocs or assembler macros. */
6725 mips_output_cplocal ();
6728 /* Make the last instruction frame related and note that it performs
6729 the operation described by FRAME_PATTERN. */
6732 mips_set_frame_expr (rtx frame_pattern)
6736 insn = get_last_insn ();
6737 RTX_FRAME_RELATED_P (insn) = 1;
6738 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6744 /* Return a frame-related rtx that stores REG at MEM.
6745 REG must be a single register. */
6748 mips_frame_set (rtx mem, rtx reg)
6750 rtx set = gen_rtx_SET (VOIDmode, mem, reg);
6751 RTX_FRAME_RELATED_P (set) = 1;
6756 /* Save register REG to MEM. Make the instruction frame-related. */
6759 mips_save_reg (rtx reg, rtx mem)
6761 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6765 if (mips_split_64bit_move_p (mem, reg))
6766 mips_split_64bit_move (mem, reg);
6768 emit_move_insn (mem, reg);
6770 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6771 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6772 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6777 && REGNO (reg) != GP_REG_FIRST + 31
6778 && !M16_REG_P (REGNO (reg)))
6780 /* Save a non-mips16 register by moving it through a temporary.
6781 We don't need to do this for $31 since there's a special
6782 instruction for it. */
6783 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6784 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6787 emit_move_insn (mem, reg);
6789 mips_set_frame_expr (mips_frame_set (mem, reg));
6794 /* Expand the prologue into a bunch of separate insns. */
6797 mips_expand_prologue (void)
6801 if (cfun->machine->global_pointer > 0)
6802 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6804 size = compute_frame_size (get_frame_size ());
6806 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6807 bytes beforehand; this is enough to cover the register save area
6808 without going out of range. */
6809 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6811 HOST_WIDE_INT step1;
6813 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6814 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6816 GEN_INT (-step1)))) = 1;
6818 mips_for_each_saved_reg (size, mips_save_reg);
6821 /* Allocate the rest of the frame. */
6824 if (SMALL_OPERAND (-size))
6825 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6827 GEN_INT (-size)))) = 1;
6830 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6833 /* There are no instructions to add or subtract registers
6834 from the stack pointer, so use the frame pointer as a
6835 temporary. We should always be using a frame pointer
6836 in this case anyway. */
6837 if (!frame_pointer_needed)
6840 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6841 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6842 hard_frame_pointer_rtx,
6843 MIPS_PROLOGUE_TEMP (Pmode)));
6844 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6847 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6849 MIPS_PROLOGUE_TEMP (Pmode)));
6851 /* Describe the combined effect of the previous instructions. */
6853 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6854 plus_constant (stack_pointer_rtx, -size)));
6858 /* Set up the frame pointer, if we're using one. In mips16 code,
6859 we point the frame pointer ahead of the outgoing argument area.
6860 This should allow more variables & incoming arguments to be
6861 accessed with unextended instructions. */
6862 if (frame_pointer_needed)
6864 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6866 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6868 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6873 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6874 stack_pointer_rtx)) = 1;
6877 /* If generating o32/o64 abicalls, save $gp on the stack. */
6878 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6879 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6881 mips_emit_loadgp ();
6883 /* If we are profiling, make sure no instructions are scheduled before
6884 the call to mcount. */
6886 if (current_function_profile)
6887 emit_insn (gen_blockage ());
6890 /* Do any necessary cleanup after a function to restore stack, frame,
6893 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6896 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6897 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6901 /* Reinstate the normal $gp. */
6902 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6903 mips_output_cplocal ();
6905 if (cfun->machine->all_noreorder_p)
6907 /* Avoid using %>%) since it adds excess whitespace. */
6908 output_asm_insn (".set\tmacro", 0);
6909 output_asm_insn (".set\treorder", 0);
6910 set_noreorder = set_nomacro = 0;
6913 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6917 /* Get the function name the same way that toplev.c does before calling
6918 assemble_start_function. This is needed so that the name used here
6919 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6920 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6921 fputs ("\t.end\t", file);
6922 assemble_name (file, fnname);
6926 while (string_constants != NULL)
6928 struct string_constant *next;
6930 next = string_constants->next;
6931 free (string_constants);
6932 string_constants = next;
6935 /* If any following function uses the same strings as this one, force
6936 them to refer those strings indirectly. Nearby functions could
6937 refer them using pc-relative addressing, but it isn't safe in
6938 general. For instance, some functions may be placed in sections
6939 other than .text, and we don't know whether they be close enough
6940 to this one. In large files, even other .text functions can be
6942 for (string = mips16_strings; string != 0; string = XEXP (string, 1))
6943 SYMBOL_REF_FLAG (XEXP (string, 0)) = 0;
6944 free_EXPR_LIST_list (&mips16_strings);
6947 /* Emit instructions to restore register REG from slot MEM. */
6950 mips_restore_reg (rtx reg, rtx mem)
6952 /* There's no mips16 instruction to load $31 directly. Load into
6953 $7 instead and adjust the return insn appropriately. */
6954 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6955 reg = gen_rtx_REG (GET_MODE (reg), 7);
6957 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6959 /* Can't restore directly; move through a temporary. */
6960 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6961 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6964 emit_move_insn (reg, mem);
6968 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6969 if this epilogue precedes a sibling call, false if it is for a normal
6970 "epilogue" pattern. */
6973 mips_expand_epilogue (int sibcall_p)
6975 HOST_WIDE_INT step1, step2;
6978 if (!sibcall_p && mips_can_use_return_insn ())
6980 emit_jump_insn (gen_return ());
6984 /* Split the frame into two. STEP1 is the amount of stack we should
6985 deallocate before restoring the registers. STEP2 is the amount we
6986 should deallocate afterwards.
6988 Start off by assuming that no registers need to be restored. */
6989 step1 = cfun->machine->frame.total_size;
6992 /* Work out which register holds the frame address. Account for the
6993 frame pointer offset used by mips16 code. */
6994 if (!frame_pointer_needed)
6995 base = stack_pointer_rtx;
6998 base = hard_frame_pointer_rtx;
7000 step1 -= cfun->machine->frame.args_size;
7003 /* If we need to restore registers, deallocate as much stack as
7004 possible in the second step without going out of range. */
7005 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7007 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7011 /* Set TARGET to BASE + STEP1. */
7017 /* Get an rtx for STEP1 that we can add to BASE. */
7018 adjust = GEN_INT (step1);
7019 if (!SMALL_OPERAND (step1))
7021 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7022 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7025 /* Normal mode code can copy the result straight into $sp. */
7027 target = stack_pointer_rtx;
7029 emit_insn (gen_add3_insn (target, base, adjust));
7032 /* Copy TARGET into the stack pointer. */
7033 if (target != stack_pointer_rtx)
7034 emit_move_insn (stack_pointer_rtx, target);
7036 /* If we're using addressing macros for n32/n64 abicalls, $gp is
7037 implicitly used by all SYMBOL_REFs. We must emit a blockage
7038 insn before restoring it. */
7039 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
7040 emit_insn (gen_blockage ());
7042 /* Restore the registers. */
7043 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7046 /* Deallocate the final bit of the frame. */
7048 emit_insn (gen_add3_insn (stack_pointer_rtx,
7052 /* Add in the __builtin_eh_return stack adjustment. We need to
7053 use a temporary in mips16 code. */
7054 if (current_function_calls_eh_return)
7058 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7059 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7060 MIPS_EPILOGUE_TEMP (Pmode),
7061 EH_RETURN_STACKADJ_RTX));
7062 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7065 emit_insn (gen_add3_insn (stack_pointer_rtx,
7067 EH_RETURN_STACKADJ_RTX));
7072 /* The mips16 loads the return address into $7, not $31. */
7073 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7074 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7075 GP_REG_FIRST + 7)));
7077 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7078 GP_REG_FIRST + 31)));
7082 /* Return nonzero if this function is known to have a null epilogue.
7083 This allows the optimizer to omit jumps to jumps if no stack
7087 mips_can_use_return_insn (void)
7091 if (! reload_completed)
7094 if (regs_ever_live[31] || current_function_profile)
7097 return_type = DECL_RESULT (current_function_decl);
7099 /* In mips16 mode, a function which returns a floating point value
7100 needs to arrange to copy the return value into the floating point
7103 && mips16_hard_float
7104 && ! aggregate_value_p (return_type, current_function_decl)
7105 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7106 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7109 if (cfun->machine->frame.initialized)
7110 return cfun->machine->frame.total_size == 0;
7112 return compute_frame_size (get_frame_size ()) == 0;
7115 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7116 in order to avoid duplicating too much logic from elsewhere. */
7119 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7120 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7123 rtx this, temp1, temp2, insn, fnaddr;
7125 /* Pretend to be a post-reload pass while generating rtl. */
7127 reload_completed = 1;
7129 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7130 for TARGET_NEWABI since the latter is a call-saved register. */
7131 if (TARGET_ABICALLS)
7132 cfun->machine->global_pointer
7133 = REGNO (pic_offset_table_rtx)
7134 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7136 /* Set up the global pointer for n32 or n64 abicalls. */
7137 mips_emit_loadgp ();
7139 /* We need two temporary registers in some cases. */
7140 temp1 = gen_rtx_REG (Pmode, 2);
7141 temp2 = gen_rtx_REG (Pmode, 3);
7143 /* Find out which register contains the "this" pointer. */
7144 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7145 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7147 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7149 /* Add DELTA to THIS. */
7152 rtx offset = GEN_INT (delta);
7153 if (!SMALL_OPERAND (delta))
7155 emit_move_insn (temp1, offset);
7158 emit_insn (gen_add3_insn (this, this, offset));
7161 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7162 if (vcall_offset != 0)
7166 /* Set TEMP1 to *THIS. */
7167 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7169 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7170 if (SMALL_OPERAND (vcall_offset))
7171 addr = gen_rtx_PLUS (Pmode, temp1, GEN_INT (vcall_offset));
7172 else if (TARGET_MIPS16)
7174 /* Load the full offset into a register so that we can use
7175 an unextended instruction for the load itself. */
7176 emit_move_insn (temp2, GEN_INT (vcall_offset));
7177 emit_insn (gen_add3_insn (temp1, temp1, temp2));
7182 /* Load the high part of the offset into a register and
7183 leave the low part for the address. */
7184 emit_move_insn (temp2, GEN_INT (CONST_HIGH_PART (vcall_offset)));
7185 emit_insn (gen_add3_insn (temp1, temp1, temp2));
7186 addr = gen_rtx_PLUS (Pmode, temp1,
7187 GEN_INT (CONST_LOW_PART (vcall_offset)));
7190 /* Load the offset and add it to THIS. */
7191 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7192 emit_insn (gen_add3_insn (this, this, temp1));
7195 /* Jump to the target function. Use a sibcall if direct jumps are
7196 allowed, otherwise load the address into a register first. */
7197 fnaddr = XEXP (DECL_RTL (function), 0);
7198 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7200 /* This is messy. gas treats "la $25,foo" as part of a call
7201 sequence and may allow a global "foo" to be lazily bound.
7202 The general move patterns therefore reject this combination.
7204 In this context, lazy binding would actually be OK for o32 and o64,
7205 but it's still wrong for n32 and n64; see mips_load_call_address.
7206 We must therefore load the address via a temporary register if
7207 mips_dangerous_for_la25_p.
7209 If we jump to the temporary register rather than $25, the assembler
7210 can use the move insn to fill the jump's delay slot. */
7211 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7212 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7213 mips_load_call_address (temp1, fnaddr, true);
7215 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7216 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7217 emit_jump_insn (gen_indirect_jump (temp1));
7221 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7222 SIBLING_CALL_P (insn) = 1;
7225 /* Run just enough of rest_of_compilation. This sequence was
7226 "borrowed" from alpha.c. */
7227 insn = get_insns ();
7228 insn_locators_initialize ();
7229 split_all_insns_noflow ();
7230 shorten_branches (insn);
7231 final_start_function (insn, file, 1);
7232 final (insn, file, 1, 0);
7233 final_end_function ();
7235 /* Clean up the vars set above. Note that final_end_function resets
7236 the global pointer for us. */
7237 reload_completed = 0;
7241 /* Returns nonzero if X contains a SYMBOL_REF. */
7244 symbolic_expression_p (rtx x)
7246 if (GET_CODE (x) == SYMBOL_REF)
7249 if (GET_CODE (x) == CONST)
7250 return symbolic_expression_p (XEXP (x, 0));
7252 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7253 return symbolic_expression_p (XEXP (x, 0));
7255 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7256 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7257 return (symbolic_expression_p (XEXP (x, 0))
7258 || symbolic_expression_p (XEXP (x, 1)));
7263 /* Choose the section to use for the constant rtx expression X that has
7267 mips_select_rtx_section (enum machine_mode mode, rtx x,
7268 unsigned HOST_WIDE_INT align)
7272 /* In mips16 mode, the constant table always goes in the same section
7273 as the function, so that constants can be loaded using PC relative
7275 function_section (current_function_decl);
7277 else if (TARGET_EMBEDDED_DATA)
7279 /* For embedded applications, always put constants in read-only data,
7280 in order to reduce RAM usage. */
7281 mergeable_constant_section (mode, align, 0);
7285 /* For hosted applications, always put constants in small data if
7286 possible, as this gives the best performance. */
7287 /* ??? Consider using mergeable small data sections. */
7289 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7290 && mips_section_threshold > 0)
7291 named_section (0, ".sdata", 0);
7292 else if (flag_pic && symbolic_expression_p (x))
7294 if (targetm.have_named_sections)
7295 named_section (0, ".data.rel.ro", 3);
7300 mergeable_constant_section (mode, align, 0);
7304 /* Choose the section to use for DECL. RELOC is true if its value contains
7305 any relocatable expression. */
7308 mips_select_section (tree decl, int reloc,
7309 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
7311 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7312 && TREE_CODE (decl) == STRING_CST)
7313 /* For embedded position independent code, put constant strings in the
7314 text section, because the data section is limited to 64K in size.
7315 For mips16 code, put strings in the text section so that a PC
7316 relative load instruction can be used to get their address. */
7318 else if (targetm.have_named_sections)
7319 default_elf_select_section (decl, reloc, align);
7321 /* The native irix o32 assembler doesn't support named sections. */
7322 default_select_section (decl, reloc, align);
7326 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7327 access DECL using %gp_rel(...)($gp). */
7330 mips_in_small_data_p (tree decl)
7334 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7337 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7341 /* Reject anything that isn't in a known small-data section. */
7342 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7343 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7346 /* If a symbol is defined externally, the assembler will use the
7347 usual -G rules when deciding how to implement macros. */
7348 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7351 else if (TARGET_EMBEDDED_DATA)
7353 /* Don't put constants into the small data section: we want them
7354 to be in ROM rather than RAM. */
7355 if (TREE_CODE (decl) != VAR_DECL)
7358 if (TREE_READONLY (decl)
7359 && !TREE_SIDE_EFFECTS (decl)
7360 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7364 size = int_size_in_bytes (TREE_TYPE (decl));
7365 return (size > 0 && size <= mips_section_threshold);
7369 /* When generating embedded PIC code, SYMBOL_REF_FLAG is set for
7370 symbols which are not in the .text section.
7372 When generating mips16 code, SYMBOL_REF_FLAG is set for string
7373 constants which are put in the .text section. We also record the
7374 total length of all such strings; this total is used to decide
7375 whether we need to split the constant table, and need not be
7376 precisely correct. */
7379 mips_encode_section_info (tree decl, rtx rtl, int first)
7383 if (GET_CODE (rtl) != MEM)
7386 symbol = XEXP (rtl, 0);
7388 if (GET_CODE (symbol) != SYMBOL_REF)
7393 if (first && TREE_CODE (decl) == STRING_CST
7394 /* If this string is from a function, and the function will
7395 go in a gnu linkonce section, then we can't directly
7396 access the string. This gets an assembler error
7397 "unsupported PC relative reference to different section".
7398 If we modify SELECT_SECTION to put it in function_section
7399 instead of text_section, it still fails because
7400 DECL_SECTION_NAME isn't set until assemble_start_function.
7401 If we fix that, it still fails because strings are shared
7402 among multiple functions, and we have cross section
7403 references again. We force it to work by putting string
7404 addresses in the constant pool and indirecting. */
7405 && (! current_function_decl
7406 || ! DECL_ONE_ONLY (current_function_decl)))
7408 mips16_strings = alloc_EXPR_LIST (0, symbol, mips16_strings);
7409 SYMBOL_REF_FLAG (symbol) = 1;
7410 mips_string_length += TREE_STRING_LENGTH (decl);
7414 if (TARGET_EMBEDDED_PIC)
7416 if (TREE_CODE (decl) == VAR_DECL)
7417 SYMBOL_REF_FLAG (symbol) = 1;
7418 else if (TREE_CODE (decl) == FUNCTION_DECL)
7419 SYMBOL_REF_FLAG (symbol) = 0;
7420 else if (TREE_CODE (decl) == STRING_CST)
7421 SYMBOL_REF_FLAG (symbol) = 0;
7423 SYMBOL_REF_FLAG (symbol) = 1;
7426 default_encode_section_info (decl, rtl, first);
7429 /* See whether VALTYPE is a record whose fields should be returned in
7430 floating-point registers. If so, return the number of fields and
7431 list them in FIELDS (which should have two elements). Return 0
7434 For n32 & n64, a structure with one or two fields is returned in
7435 floating-point registers as long as every field has a floating-point
7439 mips_fpr_return_fields (tree valtype, tree *fields)
7447 if (TREE_CODE (valtype) != RECORD_TYPE)
7451 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7453 if (TREE_CODE (field) != FIELD_DECL)
7456 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7462 fields[i++] = field;
7468 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7469 a value in the most significant part of $2/$3 if:
7471 - the target is big-endian;
7473 - the value has a structure or union type (we generalize this to
7474 cover aggregates from other languages too); and
7476 - the structure is not returned in floating-point registers. */
7479 mips_return_in_msb (tree valtype)
7483 return (TARGET_NEWABI
7484 && TARGET_BIG_ENDIAN
7485 && AGGREGATE_TYPE_P (valtype)
7486 && mips_fpr_return_fields (valtype, fields) == 0);
7490 /* Return a composite value in a pair of floating-point registers.
7491 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7492 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7495 For n32 & n64, $f0 always holds the first value and $f2 the second.
7496 Otherwise the values are packed together as closely as possible. */
7499 mips_return_fpr_pair (enum machine_mode mode,
7500 enum machine_mode mode1, HOST_WIDE_INT offset1,
7501 enum machine_mode mode2, HOST_WIDE_INT offset2)
7505 inc = (TARGET_NEWABI ? 2 : FP_INC);
7506 return gen_rtx_PARALLEL
7509 gen_rtx_EXPR_LIST (VOIDmode,
7510 gen_rtx_REG (mode1, FP_RETURN),
7512 gen_rtx_EXPR_LIST (VOIDmode,
7513 gen_rtx_REG (mode2, FP_RETURN + inc),
7514 GEN_INT (offset2))));
7519 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7520 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7521 VALTYPE is null and MODE is the mode of the return value. */
7524 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7525 enum machine_mode mode)
7532 mode = TYPE_MODE (valtype);
7533 unsignedp = TREE_UNSIGNED (valtype);
7535 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7536 true, we must promote the mode just as PROMOTE_MODE does. */
7537 mode = promote_mode (valtype, mode, &unsignedp, 1);
7539 /* Handle structures whose fields are returned in $f0/$f2. */
7540 switch (mips_fpr_return_fields (valtype, fields))
7543 return gen_rtx_REG (mode, FP_RETURN);
7546 return mips_return_fpr_pair (mode,
7547 TYPE_MODE (TREE_TYPE (fields[0])),
7548 int_byte_position (fields[0]),
7549 TYPE_MODE (TREE_TYPE (fields[1])),
7550 int_byte_position (fields[1]));
7553 /* If a value is passed in the most significant part of a register, see
7554 whether we have to round the mode up to a whole number of words. */
7555 if (mips_return_in_msb (valtype))
7557 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7558 if (size % UNITS_PER_WORD != 0)
7560 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7561 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7566 if (GET_MODE_CLASS (mode) == MODE_FLOAT
7567 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7568 return gen_rtx_REG (mode, FP_RETURN);
7570 /* Handle long doubles for n32 & n64. */
7572 return mips_return_fpr_pair (mode,
7574 DImode, GET_MODE_SIZE (mode) / 2);
7576 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7577 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7578 return mips_return_fpr_pair (mode,
7579 GET_MODE_INNER (mode), 0,
7580 GET_MODE_INNER (mode),
7581 GET_MODE_SIZE (mode) / 2);
7583 return gen_rtx_REG (mode, GP_RETURN);
7586 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7587 nonzero when an argument must be passed by reference. */
7590 function_arg_pass_by_reference (const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7591 enum machine_mode mode, tree type,
7592 int named ATTRIBUTE_UNUSED)
7596 /* The EABI is the only one to pass args by reference. */
7597 if (mips_abi != ABI_EABI)
7600 /* ??? How should SCmode be handled? */
7601 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7604 size = int_size_in_bytes (type);
7605 return size == -1 || size > UNITS_PER_WORD;
7608 /* Return the class of registers for which a mode change from FROM to TO
7611 In little-endian mode, the hi-lo registers are numbered backwards,
7612 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
7615 Similarly, when using paired floating-point registers, the first
7616 register holds the low word, regardless of endianness. So in big
7617 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
7620 Also, loading a 32-bit value into a 64-bit floating-point register
7621 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7622 We can't allow 64-bit float registers to change from a 32-bit
7623 mode to a 64-bit mode. */
7626 mips_cannot_change_mode_class (enum machine_mode from,
7627 enum machine_mode to, enum reg_class class)
7629 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
7631 if (TARGET_BIG_ENDIAN)
7632 return reg_classes_intersect_p (FP_REGS, class);
7634 return reg_classes_intersect_p (HI_AND_FP_REGS, class);
7635 return reg_classes_intersect_p (HI_REG, class);
7640 /* Return true if X should not be moved directly into register $25.
7641 We need this because many versions of GAS will treat "la $25,foo" as
7642 part of a call sequence and so allow a global "foo" to be lazily bound. */
7645 mips_dangerous_for_la25_p (rtx x)
7647 HOST_WIDE_INT offset;
7649 if (TARGET_EXPLICIT_RELOCS)
7652 mips_split_const (x, &x, &offset);
7653 return global_got_operand (x, VOIDmode);
7656 /* Implement PREFERRED_RELOAD_CLASS. */
7659 mips_preferred_reload_class (rtx x, enum reg_class class)
7661 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7664 if (TARGET_HARD_FLOAT
7665 && FLOAT_MODE_P (GET_MODE (x))
7666 && reg_class_subset_p (FP_REGS, class))
7669 if (reg_class_subset_p (GR_REGS, class))
7672 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7678 /* This function returns the register class required for a secondary
7679 register when copying between one of the registers in CLASS, and X,
7680 using MODE. If IN_P is nonzero, the copy is going from X to the
7681 register, otherwise the register is the source. A return value of
7682 NO_REGS means that no secondary register is required. */
7685 mips_secondary_reload_class (enum reg_class class,
7686 enum machine_mode mode, rtx x, int in_p)
7688 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7692 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7693 regno = true_regnum (x);
7695 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7697 if (mips_dangerous_for_la25_p (x))
7700 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7704 /* Copying from HI or LO to anywhere other than a general register
7705 requires a general register. */
7706 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7708 if (TARGET_MIPS16 && in_p)
7710 /* We can't really copy to HI or LO at all in mips16 mode. */
7713 return gp_reg_p ? NO_REGS : gr_regs;
7715 if (MD_REG_P (regno))
7717 if (TARGET_MIPS16 && ! in_p)
7719 /* We can't really copy to HI or LO at all in mips16 mode. */
7722 return class == gr_regs ? NO_REGS : gr_regs;
7725 /* We can only copy a value to a condition code register from a
7726 floating point register, and even then we require a scratch
7727 floating point register. We can only copy a value out of a
7728 condition code register into a general register. */
7729 if (class == ST_REGS)
7733 return gp_reg_p ? NO_REGS : gr_regs;
7735 if (ST_REG_P (regno))
7739 return class == gr_regs ? NO_REGS : gr_regs;
7742 if (class == FP_REGS)
7744 if (GET_CODE (x) == MEM)
7746 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7749 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7751 /* We can use the l.s and l.d macros to load floating-point
7752 constants. ??? For l.s, we could probably get better
7753 code by returning GR_REGS here. */
7756 else if (gp_reg_p || x == CONST0_RTX (mode))
7758 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7761 else if (FP_REG_P (regno))
7763 /* In this case we can use mov.s or mov.d. */
7768 /* Otherwise, we need to reload through an integer register. */
7773 /* In mips16 mode, going between memory and anything but M16_REGS
7774 requires an M16_REG. */
7777 if (class != M16_REGS && class != M16_NA_REGS)
7785 if (class == M16_REGS || class == M16_NA_REGS)
7794 /* Implement CLASS_MAX_NREGS.
7796 Usually all registers are word-sized. The only supported exception
7797 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7798 registers. A word-based calculation is correct even in that case,
7799 since -msingle-float disallows multi-FPR values. */
7802 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7803 enum machine_mode mode)
7805 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7809 mips_valid_pointer_mode (enum machine_mode mode)
7811 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7815 /* If we can access small data directly (using gp-relative relocation
7816 operators) return the small data pointer, otherwise return null.
7818 For each mips16 function which refers to GP relative symbols, we
7819 use a pseudo register, initialized at the start of the function, to
7820 hold the $gp value. */
7823 mips16_gp_pseudo_reg (void)
7825 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7830 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7831 RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
7833 /* We want to initialize this to a value which gcc will believe
7835 const_gp = gen_rtx_CONST (Pmode, pic_offset_table_rtx);
7837 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7839 insn = get_insns ();
7842 push_topmost_sequence ();
7843 /* We need to emit the initialization after the FUNCTION_BEG
7844 note, so that it will be integrated. */
7845 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7846 if (GET_CODE (scan) == NOTE
7847 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7849 if (scan == NULL_RTX)
7850 scan = get_insns ();
7851 insn = emit_insn_after (insn, scan);
7852 pop_topmost_sequence ();
7855 return cfun->machine->mips16_gp_pseudo_rtx;
7858 /* Write out code to move floating point arguments in or out of
7859 general registers. Output the instructions to FILE. FP_CODE is
7860 the code describing which arguments are present (see the comment at
7861 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7862 we are copying from the floating point registers. */
7865 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7871 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7879 gparg = GP_ARG_FIRST;
7880 fparg = FP_ARG_FIRST;
7881 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7885 if ((fparg & 1) != 0)
7887 fprintf (file, "\t%s\t%s,%s\n", s,
7888 reg_names[gparg], reg_names[fparg]);
7890 else if ((f & 3) == 2)
7893 fprintf (file, "\td%s\t%s,%s\n", s,
7894 reg_names[gparg], reg_names[fparg]);
7897 if ((fparg & 1) != 0)
7899 if (TARGET_BIG_ENDIAN)
7900 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7901 reg_names[gparg], reg_names[fparg + 1], s,
7902 reg_names[gparg + 1], reg_names[fparg]);
7904 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7905 reg_names[gparg], reg_names[fparg], s,
7906 reg_names[gparg + 1], reg_names[fparg + 1]);
7919 /* Build a mips16 function stub. This is used for functions which
7920 take arguments in the floating point registers. It is 32 bit code
7921 that moves the floating point args into the general registers, and
7922 then jumps to the 16 bit code. */
7925 build_mips16_function_stub (FILE *file)
7928 char *secname, *stubname;
7929 tree stubid, stubdecl;
7933 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7934 secname = (char *) alloca (strlen (fnname) + 20);
7935 sprintf (secname, ".mips16.fn.%s", fnname);
7936 stubname = (char *) alloca (strlen (fnname) + 20);
7937 sprintf (stubname, "__fn_stub_%s", fnname);
7938 stubid = get_identifier (stubname);
7939 stubdecl = build_decl (FUNCTION_DECL, stubid,
7940 build_function_type (void_type_node, NULL_TREE));
7941 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7943 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7945 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7947 fprintf (file, "%s%s",
7948 need_comma ? ", " : "",
7949 (f & 3) == 1 ? "float" : "double");
7952 fprintf (file, ")\n");
7954 fprintf (file, "\t.set\tnomips16\n");
7955 function_section (stubdecl);
7956 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7958 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7959 within a .ent, and we can not emit another .ent. */
7960 if (!FUNCTION_NAME_ALREADY_DECLARED)
7962 fputs ("\t.ent\t", file);
7963 assemble_name (file, stubname);
7967 assemble_name (file, stubname);
7968 fputs (":\n", file);
7970 /* We don't want the assembler to insert any nops here. */
7971 fprintf (file, "\t.set\tnoreorder\n");
7973 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7975 fprintf (asm_out_file, "\t.set\tnoat\n");
7976 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7977 assemble_name (file, fnname);
7978 fprintf (file, "\n");
7979 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7980 fprintf (asm_out_file, "\t.set\tat\n");
7982 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7983 with one of the mfc1 instructions, because the result is not
7984 available for one instruction, so if the very first instruction
7985 in the function refers to the register, it will see the wrong
7987 fprintf (file, "\tnop\n");
7989 fprintf (file, "\t.set\treorder\n");
7991 if (!FUNCTION_NAME_ALREADY_DECLARED)
7993 fputs ("\t.end\t", file);
7994 assemble_name (file, stubname);
7998 fprintf (file, "\t.set\tmips16\n");
8000 function_section (current_function_decl);
8003 /* We keep a list of functions for which we have already built stubs
8004 in build_mips16_call_stub. */
8008 struct mips16_stub *next;
8013 static struct mips16_stub *mips16_stubs;
8015 /* Build a call stub for a mips16 call. A stub is needed if we are
8016 passing any floating point values which should go into the floating
8017 point registers. If we are, and the call turns out to be to a 32
8018 bit function, the stub will be used to move the values into the
8019 floating point registers before calling the 32 bit function. The
8020 linker will magically adjust the function call to either the 16 bit
8021 function or the 32 bit stub, depending upon where the function call
8022 is actually defined.
8024 Similarly, we need a stub if the return value might come back in a
8025 floating point register.
8027 RETVAL is the location of the return value, or null if this is
8028 a call rather than a call_value. FN is the address of the
8029 function and ARG_SIZE is the size of the arguments. FP_CODE
8030 is the code built by function_arg. This function returns a nonzero
8031 value if it builds the call instruction itself. */
8034 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8038 char *secname, *stubname;
8039 struct mips16_stub *l;
8040 tree stubid, stubdecl;
8044 /* We don't need to do anything if we aren't in mips16 mode, or if
8045 we were invoked with the -msoft-float option. */
8046 if (! TARGET_MIPS16 || ! mips16_hard_float)
8049 /* Figure out whether the value might come back in a floating point
8051 fpret = (retval != 0
8052 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8053 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8055 /* We don't need to do anything if there were no floating point
8056 arguments and the value will not be returned in a floating point
8058 if (fp_code == 0 && ! fpret)
8061 /* We don't need to do anything if this is a call to a special
8062 mips16 support function. */
8063 if (GET_CODE (fn) == SYMBOL_REF
8064 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8067 /* This code will only work for o32 and o64 abis. The other ABI's
8068 require more sophisticated support. */
8072 /* We can only handle SFmode and DFmode floating point return
8074 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8077 /* If we're calling via a function pointer, then we must always call
8078 via a stub. There are magic stubs provided in libgcc.a for each
8079 of the required cases. Each of them expects the function address
8080 to arrive in register $2. */
8082 if (GET_CODE (fn) != SYMBOL_REF)
8088 /* ??? If this code is modified to support other ABI's, we need
8089 to handle PARALLEL return values here. */
8091 sprintf (buf, "__mips16_call_stub_%s%d",
8093 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8096 id = get_identifier (buf);
8097 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8099 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8101 if (retval == NULL_RTX)
8102 insn = gen_call_internal (stub_fn, arg_size);
8104 insn = gen_call_value_internal (retval, stub_fn, arg_size);
8105 insn = emit_call_insn (insn);
8107 /* Put the register usage information on the CALL. */
8108 if (GET_CODE (insn) != CALL_INSN)
8110 CALL_INSN_FUNCTION_USAGE (insn) =
8111 gen_rtx_EXPR_LIST (VOIDmode,
8112 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8113 CALL_INSN_FUNCTION_USAGE (insn));
8115 /* If we are handling a floating point return value, we need to
8116 save $18 in the function prologue. Putting a note on the
8117 call will mean that regs_ever_live[$18] will be true if the
8118 call is not eliminated, and we can check that in the prologue
8121 CALL_INSN_FUNCTION_USAGE (insn) =
8122 gen_rtx_EXPR_LIST (VOIDmode,
8123 gen_rtx_USE (VOIDmode,
8124 gen_rtx_REG (word_mode, 18)),
8125 CALL_INSN_FUNCTION_USAGE (insn));
8127 /* Return 1 to tell the caller that we've generated the call
8132 /* We know the function we are going to call. If we have already
8133 built a stub, we don't need to do anything further. */
8135 fnname = XSTR (fn, 0);
8136 for (l = mips16_stubs; l != NULL; l = l->next)
8137 if (strcmp (l->name, fnname) == 0)
8142 /* Build a special purpose stub. When the linker sees a
8143 function call in mips16 code, it will check where the target
8144 is defined. If the target is a 32 bit call, the linker will
8145 search for the section defined here. It can tell which
8146 symbol this section is associated with by looking at the
8147 relocation information (the name is unreliable, since this
8148 might be a static function). If such a section is found, the
8149 linker will redirect the call to the start of the magic
8152 If the function does not return a floating point value, the
8153 special stub section is named
8156 If the function does return a floating point value, the stub
8158 .mips16.call.fp.FNNAME
8161 secname = (char *) alloca (strlen (fnname) + 40);
8162 sprintf (secname, ".mips16.call.%s%s",
8165 stubname = (char *) alloca (strlen (fnname) + 20);
8166 sprintf (stubname, "__call_stub_%s%s",
8169 stubid = get_identifier (stubname);
8170 stubdecl = build_decl (FUNCTION_DECL, stubid,
8171 build_function_type (void_type_node, NULL_TREE));
8172 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8174 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8176 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8180 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8182 fprintf (asm_out_file, "%s%s",
8183 need_comma ? ", " : "",
8184 (f & 3) == 1 ? "float" : "double");
8187 fprintf (asm_out_file, ")\n");
8189 fprintf (asm_out_file, "\t.set\tnomips16\n");
8190 assemble_start_function (stubdecl, stubname);
8192 if (!FUNCTION_NAME_ALREADY_DECLARED)
8194 fputs ("\t.ent\t", asm_out_file);
8195 assemble_name (asm_out_file, stubname);
8196 fputs ("\n", asm_out_file);
8198 assemble_name (asm_out_file, stubname);
8199 fputs (":\n", asm_out_file);
8202 /* We build the stub code by hand. That's the only way we can
8203 do it, since we can't generate 32 bit code during a 16 bit
8206 /* We don't want the assembler to insert any nops here. */
8207 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8209 mips16_fp_args (asm_out_file, fp_code, 0);
8213 fprintf (asm_out_file, "\t.set\tnoat\n");
8214 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8216 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8217 fprintf (asm_out_file, "\t.set\tat\n");
8218 /* Unfortunately, we can't fill the jump delay slot. We
8219 can't fill with one of the mtc1 instructions, because the
8220 result is not available for one instruction, so if the
8221 very first instruction in the function refers to the
8222 register, it will see the wrong value. */
8223 fprintf (asm_out_file, "\tnop\n");
8227 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8228 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8229 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8230 /* As above, we can't fill the delay slot. */
8231 fprintf (asm_out_file, "\tnop\n");
8232 if (GET_MODE (retval) == SFmode)
8233 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8234 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8237 if (TARGET_BIG_ENDIAN)
8239 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8240 reg_names[GP_REG_FIRST + 2],
8241 reg_names[FP_REG_FIRST + 1]);
8242 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8243 reg_names[GP_REG_FIRST + 3],
8244 reg_names[FP_REG_FIRST + 0]);
8248 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8249 reg_names[GP_REG_FIRST + 2],
8250 reg_names[FP_REG_FIRST + 0]);
8251 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8252 reg_names[GP_REG_FIRST + 3],
8253 reg_names[FP_REG_FIRST + 1]);
8256 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8257 /* As above, we can't fill the delay slot. */
8258 fprintf (asm_out_file, "\tnop\n");
8261 fprintf (asm_out_file, "\t.set\treorder\n");
8263 #ifdef ASM_DECLARE_FUNCTION_SIZE
8264 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8267 if (!FUNCTION_NAME_ALREADY_DECLARED)
8269 fputs ("\t.end\t", asm_out_file);
8270 assemble_name (asm_out_file, stubname);
8271 fputs ("\n", asm_out_file);
8274 fprintf (asm_out_file, "\t.set\tmips16\n");
8276 /* Record this stub. */
8277 l = (struct mips16_stub *) xmalloc (sizeof *l);
8278 l->name = xstrdup (fnname);
8280 l->next = mips16_stubs;
8284 /* If we expect a floating point return value, but we've built a
8285 stub which does not expect one, then we're in trouble. We can't
8286 use the existing stub, because it won't handle the floating point
8287 value. We can't build a new stub, because the linker won't know
8288 which stub to use for the various calls in this object file.
8289 Fortunately, this case is illegal, since it means that a function
8290 was declared in two different ways in a single compilation. */
8291 if (fpret && ! l->fpret)
8292 error ("can not handle inconsistent calls to `%s'", fnname);
8294 /* If we are calling a stub which handles a floating point return
8295 value, we need to arrange to save $18 in the prologue. We do
8296 this by marking the function call as using the register. The
8297 prologue will later see that it is used, and emit code to save
8304 if (retval == NULL_RTX)
8305 insn = gen_call_internal (fn, arg_size);
8307 insn = gen_call_value_internal (retval, fn, arg_size);
8308 insn = emit_call_insn (insn);
8310 if (GET_CODE (insn) != CALL_INSN)
8313 CALL_INSN_FUNCTION_USAGE (insn) =
8314 gen_rtx_EXPR_LIST (VOIDmode,
8315 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8316 CALL_INSN_FUNCTION_USAGE (insn));
8318 /* Return 1 to tell the caller that we've generated the call
8323 /* Return 0 to let the caller generate the call insn. */
8327 /* We keep a list of constants we which we have to add to internal
8328 constant tables in the middle of large functions. */
8332 struct constant *next;
8335 enum machine_mode mode;
8338 /* Add a constant to the list in *PCONSTANTS. */
8341 add_constant (struct constant **pconstants, rtx val, enum machine_mode mode)
8345 for (c = *pconstants; c != NULL; c = c->next)
8346 if (mode == c->mode && rtx_equal_p (val, c->value))
8349 c = (struct constant *) xmalloc (sizeof *c);
8352 c->label = gen_label_rtx ();
8353 c->next = *pconstants;
8358 /* Dump out the constants in CONSTANTS after INSN. */
8361 dump_constants (struct constant *constants, rtx insn)
8371 struct constant *next;
8373 switch (GET_MODE_SIZE (c->mode))
8380 insn = emit_insn_after (gen_align_2 (), insn);
8385 insn = emit_insn_after (gen_align_4 (), insn);
8390 insn = emit_insn_after (gen_align_8 (), insn);
8395 insn = emit_label_after (c->label, insn);
8400 r = gen_consttable_qi (c->value);
8403 r = gen_consttable_hi (c->value);
8406 r = gen_consttable_si (c->value);
8409 r = gen_consttable_sf (c->value);
8412 r = gen_consttable_di (c->value);
8415 r = gen_consttable_df (c->value);
8421 insn = emit_insn_after (r, insn);
8428 emit_barrier_after (insn);
8431 /* Find the symbol in an address expression. */
8434 mips_find_symbol (rtx addr)
8436 if (GET_CODE (addr) == MEM)
8437 addr = XEXP (addr, 0);
8438 while (GET_CODE (addr) == CONST)
8439 addr = XEXP (addr, 0);
8440 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
8442 if (GET_CODE (addr) == PLUS)
8446 l1 = mips_find_symbol (XEXP (addr, 0));
8447 l2 = mips_find_symbol (XEXP (addr, 1));
8448 if (l1 != NULL_RTX && l2 == NULL_RTX)
8450 else if (l1 == NULL_RTX && l2 != NULL_RTX)
8456 /* In mips16 mode, we need to look through the function to check for
8457 PC relative loads that are out of range. */
8460 mips16_lay_out_constants (void)
8462 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
8464 struct constant *constants;
8466 first = get_insns ();
8468 /* Scan the function looking for PC relative loads which may be out
8469 of range. All such loads will either be from the constant table,
8470 or be getting the address of a constant string. If the size of
8471 the function plus the size of the constant table is less than
8472 0x8000, then all loads are in range. */
8475 for (insn = first; insn; insn = NEXT_INSN (insn))
8477 insns_len += get_attr_length (insn);
8479 /* ??? We put switch tables in .text, but we don't define
8480 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8481 compute their lengths correctly. */
8482 if (GET_CODE (insn) == JUMP_INSN)
8486 body = PATTERN (insn);
8487 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8488 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8489 * GET_MODE_SIZE (GET_MODE (body)));
8490 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
8494 /* Store the original value of insns_len in cfun->machine, so
8495 that m16_usym8_4 and m16_usym5_4 can look at it. */
8496 cfun->machine->insns_len = insns_len;
8498 pool_size = get_pool_size ();
8499 if (insns_len + pool_size + mips_string_length < 0x8000)
8502 /* Loop over the insns and figure out what the maximum internal pool
8504 max_internal_pool_size = 0;
8505 for (insn = first; insn; insn = NEXT_INSN (insn))
8507 if (GET_CODE (insn) == INSN
8508 && GET_CODE (PATTERN (insn)) == SET)
8512 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8513 if (src == NULL_RTX)
8515 if (CONSTANT_POOL_ADDRESS_P (src))
8516 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
8517 else if (SYMBOL_REF_FLAG (src))
8518 max_internal_pool_size += GET_MODE_SIZE (Pmode);
8524 first_constant_ref = -1;
8526 for (insn = first; insn; insn = NEXT_INSN (insn))
8528 if (GET_CODE (insn) == INSN
8529 && GET_CODE (PATTERN (insn)) == SET)
8532 enum machine_mode mode = VOIDmode;
8535 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8536 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
8538 /* ??? This is very conservative, which means that we
8539 will generate too many copies of the constant table.
8540 The only solution would seem to be some form of
8542 if (((insns_len - addr)
8543 + max_internal_pool_size
8544 + get_pool_offset (src))
8547 val = get_pool_constant (src);
8548 mode = get_pool_mode (src);
8550 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
8552 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
8554 /* Including all of mips_string_length is conservative,
8555 and so is including all of max_internal_pool_size. */
8556 if (((insns_len - addr)
8557 + max_internal_pool_size
8559 + mips_string_length)
8565 max_internal_pool_size -= Pmode;
8568 if (val != NULL_RTX)
8572 /* This PC relative load is out of range. ??? In the
8573 case of a string constant, we are only guessing that
8574 it is range, since we don't know the offset of a
8575 particular string constant. */
8577 lab = add_constant (&constants, val, mode);
8578 newsrc = gen_rtx_MEM (mode,
8579 gen_rtx_LABEL_REF (VOIDmode, lab));
8580 RTX_UNCHANGING_P (newsrc) = 1;
8581 PATTERN (insn) = gen_rtx_SET (VOIDmode,
8582 SET_DEST (PATTERN (insn)),
8584 INSN_CODE (insn) = -1;
8586 if (first_constant_ref < 0)
8587 first_constant_ref = addr;
8591 addr += get_attr_length (insn);
8593 /* ??? We put switch tables in .text, but we don't define
8594 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8595 compute their lengths correctly. */
8596 if (GET_CODE (insn) == JUMP_INSN)
8600 body = PATTERN (insn);
8601 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8602 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8603 * GET_MODE_SIZE (GET_MODE (body)));
8604 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
8607 if (GET_CODE (insn) == BARRIER)
8609 /* Output any constants we have accumulated. Note that we
8610 don't need to change ADDR, since its only use is
8611 subtraction from INSNS_LEN, and both would be changed by
8613 ??? If the instructions up to the next barrier reuse a
8614 constant, it would often be better to continue
8616 if (constants != NULL)
8617 dump_constants (constants, insn);
8619 first_constant_ref = -1;
8622 if (constants != NULL
8623 && (NEXT_INSN (insn) == NULL
8624 || (first_constant_ref >= 0
8625 && (((addr - first_constant_ref)
8626 + 2 /* for alignment */
8627 + 2 /* for a short jump insn */
8631 /* If we haven't had a barrier within 0x8000 bytes of a
8632 constant reference or we are at the end of the function,
8633 emit a barrier now. */
8635 rtx label, jump, barrier;
8637 label = gen_label_rtx ();
8638 jump = emit_jump_insn_after (gen_jump (label), insn);
8639 JUMP_LABEL (jump) = label;
8640 LABEL_NUSES (label) = 1;
8641 barrier = emit_barrier_after (jump);
8642 emit_label_after (label, barrier);
8643 first_constant_ref = -1;
8647 /* ??? If we output all references to a constant in internal
8648 constants table, we don't need to output the constant in the real
8649 constant table, but we have no way to prevent that. */
8653 /* Subroutine of mips_reorg. If there is a hazard between INSN
8654 and a previous instruction, avoid it by inserting nops after
8657 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8658 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8659 before using the value of that register. *HILO_DELAY counts the
8660 number of instructions since the last hilo hazard (that is,
8661 the number of instructions since the last mflo or mfhi).
8663 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8664 for the next instruction.
8666 LO_REG is an rtx for the LO register, used in dependence checking. */
8669 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8670 rtx *delayed_reg, rtx lo_reg)
8678 pattern = PATTERN (insn);
8680 /* Do not put the whole function in .set noreorder if it contains
8681 an asm statement. We don't know whether there will be hazards
8682 between the asm statement and the gcc-generated code. */
8683 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8684 cfun->machine->all_noreorder_p = false;
8686 /* Ignore zero-length instructions (barriers and the like). */
8687 ninsns = get_attr_length (insn) / 4;
8691 /* Work out how many nops are needed. Note that we only care about
8692 registers that are explicitly mentioned in the instruction's pattern.
8693 It doesn't matter that calls use the argument registers or that they
8694 clobber hi and lo. */
8695 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8696 nops = 2 - *hilo_delay;
8697 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8702 /* Insert the nops between this instruction and the previous one.
8703 Each new nop takes us further from the last hilo hazard. */
8704 *hilo_delay += nops;
8706 emit_insn_after (gen_hazard_nop (), after);
8708 /* Set up the state for the next instruction. */
8709 *hilo_delay += ninsns;
8711 if (INSN_CODE (insn) >= 0)
8712 switch (get_attr_hazard (insn))
8722 set = single_set (insn);
8725 *delayed_reg = SET_DEST (set);
8731 /* Go through the instruction stream and insert nops where necessary.
8732 See if the whole function can then be put into .set noreorder &
8736 mips_avoid_hazards (void)
8738 rtx insn, last_insn, lo_reg, delayed_reg;
8741 /* Recalculate instruction lengths without taking nops into account. */
8742 cfun->machine->ignore_hazard_length_p = true;
8743 shorten_branches (get_insns ());
8745 /* The profiler code uses assembler macros. */
8746 cfun->machine->all_noreorder_p = !current_function_profile;
8751 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8753 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8756 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8757 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8758 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8759 &hilo_delay, &delayed_reg, lo_reg);
8761 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8762 &delayed_reg, lo_reg);
8769 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8775 mips16_lay_out_constants ();
8776 else if (TARGET_EXPLICIT_RELOCS)
8778 if (mips_flag_delayed_branch)
8779 dbr_schedule (get_insns (), dump_file);
8780 mips_avoid_hazards ();
8784 /* We need to use a special set of functions to handle hard floating
8785 point code in mips16 mode. Also, allow for --enable-gofast. */
8787 #include "config/gofast.h"
8790 mips_init_libfuncs (void)
8792 if (TARGET_MIPS16 && mips16_hard_float)
8794 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8795 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8796 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8797 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8799 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8800 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8801 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8802 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8803 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8804 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8806 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fixsfsi");
8807 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8809 if (TARGET_DOUBLE_FLOAT)
8811 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8812 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8813 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8814 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8816 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8817 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8818 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8819 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8820 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8821 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8823 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8824 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8826 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fixdfsi");
8827 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8831 gofast_maybe_init_libfuncs ();
8834 /* Return a number assessing the cost of moving a register in class
8835 FROM to class TO. The classes are expressed using the enumeration
8836 values such as `GENERAL_REGS'. A value of 2 is the default; other
8837 values are interpreted relative to that.
8839 It is not required that the cost always equal 2 when FROM is the
8840 same as TO; on some machines it is expensive to move between
8841 registers if they are not general registers.
8843 If reload sees an insn consisting of a single `set' between two
8844 hard registers, and if `REGISTER_MOVE_COST' applied to their
8845 classes returns a value of 2, reload does not check to ensure that
8846 the constraints of the insn are met. Setting a cost of other than
8847 2 will allow reload to verify that the constraints are met. You
8848 should do this if the `movM' pattern's constraints do not allow
8851 ??? We make the cost of moving from HI/LO into general
8852 registers the same as for one of moving general registers to
8853 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8854 pseudo to HI/LO. This might hurt optimizations though, it
8855 isn't clear if it is wise. And it might not work in all cases. We
8856 could solve the DImode LO reg problem by using a multiply, just
8857 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8858 problem by using divide instructions. divu puts the remainder in
8859 the HI reg, so doing a divide by -1 will move the value in the HI
8860 reg for all values except -1. We could handle that case by using a
8861 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8862 a compare/branch to test the input value to see which instruction
8863 we need to use. This gets pretty messy, but it is feasible. */
8866 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8867 enum reg_class to, enum reg_class from)
8869 if (from == M16_REGS && GR_REG_CLASS_P (to))
8871 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8873 else if (GR_REG_CLASS_P (from))
8877 else if (to == M16_NA_REGS)
8879 else if (GR_REG_CLASS_P (to))
8886 else if (to == FP_REGS)
8888 else if (to == HI_REG || to == LO_REG || to == MD_REGS)
8895 else if (COP_REG_CLASS_P (to))
8899 } /* GR_REG_CLASS_P (from) */
8900 else if (from == FP_REGS)
8902 if (GR_REG_CLASS_P (to))
8904 else if (to == FP_REGS)
8906 else if (to == ST_REGS)
8908 } /* from == FP_REGS */
8909 else if (from == HI_REG || from == LO_REG || from == MD_REGS)
8911 if (GR_REG_CLASS_P (to))
8918 } /* from == HI_REG, etc. */
8919 else if (from == ST_REGS && GR_REG_CLASS_P (to))
8921 else if (COP_REG_CLASS_P (from))
8924 } /* COP_REG_CLASS_P (from) */
8931 /* Return the length of INSN. LENGTH is the initial length computed by
8932 attributes in the machine-description file. */
8935 mips_adjust_insn_length (rtx insn, int length)
8937 /* A unconditional jump has an unfilled delay slot if it is not part
8938 of a sequence. A conditional jump normally has a delay slot, but
8939 does not on MIPS16. */
8940 if (simplejump_p (insn)
8941 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
8942 || GET_CODE (insn) == CALL_INSN)))
8945 /* See how many nops might be needed to avoid hardware hazards. */
8946 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
8947 switch (get_attr_hazard (insn))
8961 /* All MIPS16 instructions are a measly two bytes. */
8969 /* Return an asm sequence to start a noat block and load the address
8970 of a label into $1. */
8973 mips_output_load_label (void)
8975 if (TARGET_EXPLICIT_RELOCS)
8979 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
8982 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
8985 if (ISA_HAS_LOAD_DELAY)
8986 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
8987 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
8991 if (Pmode == DImode)
8992 return "%[dla\t%@,%0";
8994 return "%[la\t%@,%0";
8999 /* Output assembly instructions to peform a conditional branch.
9001 INSN is the branch instruction. OPERANDS[0] is the condition.
9002 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9003 of the first operand to the condition. If TWO_OPERANDS_P is
9004 nonzero the comparison takes two operands; OPERANDS[3] will be the
9007 If INVERTED_P is nonzero we are to branch if the condition does
9008 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
9010 LENGTH is the length (in bytes) of the sequence we are to generate.
9011 That tells us whether to generate a simple conditional branch, or a
9012 reversed conditional branch around a `jr' instruction. */
9014 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
9015 int float_p, int inverted_p, int length)
9017 static char buffer[200];
9018 /* The kind of comparison we are doing. */
9019 enum rtx_code code = GET_CODE (operands[0]);
9020 /* Nonzero if the opcode for the comparison needs a `z' indicating
9021 that it is a comparison against zero. */
9023 /* A string to use in the assembly output to represent the first
9025 const char *op1 = "%z2";
9026 /* A string to use in the assembly output to represent the second
9027 operand. Use the hard-wired zero register if there's no second
9029 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9030 /* The operand-printing string for the comparison. */
9031 const char *const comp = (float_p ? "%F0" : "%C0");
9032 /* The operand-printing string for the inverted comparison. */
9033 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
9035 /* The MIPS processors (for levels of the ISA at least two), have
9036 "likely" variants of each branch instruction. These instructions
9037 annul the instruction in the delay slot if the branch is not
9039 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9041 if (!two_operands_p)
9043 /* To compute whether than A > B, for example, we normally
9044 subtract B from A and then look at the sign bit. But, if we
9045 are doing an unsigned comparison, and B is zero, we don't
9046 have to do the subtraction. Instead, we can just check to
9047 see if A is nonzero. Thus, we change the CODE here to
9048 reflect the simpler comparison operation. */
9060 /* A condition which will always be true. */
9066 /* A condition which will always be false. */
9072 /* Not a special case. */
9077 /* Relative comparisons are always done against zero. But
9078 equality comparisons are done between two operands, and therefore
9079 do not require a `z' in the assembly language output. */
9080 need_z_p = (!float_p && code != EQ && code != NE);
9081 /* For comparisons against zero, the zero is not provided
9086 /* Begin by terminating the buffer. That way we can always use
9087 strcat to add to it. */
9094 /* Just a simple conditional branch. */
9096 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
9097 inverted_p ? inverted_comp : comp);
9099 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
9100 inverted_p ? inverted_comp : comp,
9101 need_z_p ? "z" : "",
9111 /* Generate a reversed conditional branch around ` j'
9124 If the original branch was a likely branch, the delay slot
9125 must be executed only if the branch is taken, so generate:
9137 When generating non-embedded PIC, instead of:
9150 rtx target = gen_label_rtx ();
9152 orig_target = operands[1];
9153 operands[1] = target;
9154 /* Generate the reversed comparison. This takes four
9157 sprintf (buffer, "%%*b%s\t%%Z2%%1",
9158 inverted_p ? comp : inverted_comp);
9160 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
9161 inverted_p ? comp : inverted_comp,
9162 need_z_p ? "z" : "",
9165 output_asm_insn (buffer, operands);
9167 if (length != 16 && length != 28 && ! mips_branch_likely)
9169 /* Output delay slot instruction. */
9170 rtx insn = final_sequence;
9171 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9172 optimize, 0, 1, NULL);
9173 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9176 output_asm_insn ("%#", 0);
9179 output_asm_insn ("j\t%0", &orig_target);
9182 output_asm_insn (mips_output_load_label (), &orig_target);
9183 output_asm_insn ("jr\t%@%]", 0);
9186 if (length != 16 && length != 28 && mips_branch_likely)
9188 /* Output delay slot instruction. */
9189 rtx insn = final_sequence;
9190 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9191 optimize, 0, 1, NULL);
9192 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9195 output_asm_insn ("%#", 0);
9197 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9198 CODE_LABEL_NUMBER (target));
9211 /* Used to output div or ddiv instruction DIVISION, which has the
9212 operands given by OPERANDS. If we need a divide-by-zero check,
9213 output the instruction and return an asm string that traps if
9216 The original R4000 has a cpu bug. If a double-word or a variable
9217 shift executes immediately after starting an integer division, the
9218 shift may give an incorrect result. Avoid this by adding a nop on
9219 the R4000. See quotations of errata #16 and #28 from "MIPS
9220 R4000PC/SC Errata, Processor Revision 2.2 and 3.0" in mips.md for
9223 Otherwise just return DIVISION itself. */
9226 mips_output_division (const char *division, rtx *operands)
9228 const char *s = division;
9230 if (TARGET_CHECK_ZERO_DIV)
9232 output_asm_insn (s, operands);
9235 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9237 s = "bne\t%2,%.,1f%#\n\tbreak\t7\n1:";
9239 if (TARGET_FIX_R4000)
9241 output_asm_insn (s, operands);
9247 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9248 with a final "000" replaced by "k". Ignore case.
9250 Note: this function is shared between GCC and GAS. */
9253 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9255 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9256 given++, canonical++;
9258 return ((*given == 0 && *canonical == 0)
9259 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9263 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9264 CPU name. We've traditionally allowed a lot of variation here.
9266 Note: this function is shared between GCC and GAS. */
9269 mips_matching_cpu_name_p (const char *canonical, const char *given)
9271 /* First see if the name matches exactly, or with a final "000"
9273 if (mips_strict_matching_cpu_name_p (canonical, given))
9276 /* If not, try comparing based on numerical designation alone.
9277 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9278 if (TOLOWER (*given) == 'r')
9280 if (!ISDIGIT (*given))
9283 /* Skip over some well-known prefixes in the canonical name,
9284 hoping to find a number there too. */
9285 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9287 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9289 else if (TOLOWER (canonical[0]) == 'r')
9292 return mips_strict_matching_cpu_name_p (canonical, given);
9296 /* Parse an option that takes the name of a processor as its argument.
9297 OPTION is the name of the option and CPU_STRING is the argument.
9298 Return the corresponding processor enumeration if the CPU_STRING is
9299 recognized, otherwise report an error and return null.
9301 A similar function exists in GAS. */
9303 static const struct mips_cpu_info *
9304 mips_parse_cpu (const char *option, const char *cpu_string)
9306 const struct mips_cpu_info *p;
9309 /* In the past, we allowed upper-case CPU names, but it doesn't
9310 work well with the multilib machinery. */
9311 for (s = cpu_string; *s != 0; s++)
9314 warning ("the cpu name must be lower case");
9318 /* 'from-abi' selects the most compatible architecture for the given
9319 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9320 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9321 version. Look first at the -mgp options, if given, otherwise base
9322 the choice on MASK_64BIT in TARGET_DEFAULT. */
9323 if (strcasecmp (cpu_string, "from-abi") == 0)
9324 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9325 : ABI_NEEDS_64BIT_REGS ? 3
9326 : (TARGET_64BIT ? 3 : 1));
9328 /* 'default' has traditionally been a no-op. Probably not very useful. */
9329 if (strcasecmp (cpu_string, "default") == 0)
9332 for (p = mips_cpu_info_table; p->name != 0; p++)
9333 if (mips_matching_cpu_name_p (p->name, cpu_string))
9336 error ("bad value (%s) for %s", cpu_string, option);
9341 /* Return the processor associated with the given ISA level, or null
9342 if the ISA isn't valid. */
9344 static const struct mips_cpu_info *
9345 mips_cpu_info_from_isa (int isa)
9347 const struct mips_cpu_info *p;
9349 for (p = mips_cpu_info_table; p->name != 0; p++)
9356 /* Adjust the cost of INSN based on the relationship between INSN that
9357 is dependent on DEP_INSN through the dependence LINK. The default
9358 is to make no adjustment to COST.
9360 On the MIPS, ignore the cost of anti- and output-dependencies. */
9362 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9363 rtx dep ATTRIBUTE_UNUSED, int cost)
9365 if (REG_NOTE_KIND (link) != 0)
9366 return 0; /* Anti or output dependence. */
9370 /* Implement HARD_REGNO_NREGS. The size of FP registers are controlled
9371 by UNITS_PER_FPREG. All other registers are word sized. */
9374 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9376 if (! FP_REG_P (regno))
9377 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9379 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9382 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9383 all BLKmode objects are returned in memory. Under the new (N32 and
9384 64-bit MIPS ABIs) small structures are returned in a register.
9385 Objects with varying size must still be returned in memory, of
9389 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9392 return (TYPE_MODE (type) == BLKmode);
9394 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9395 || (int_size_in_bytes (type) == -1));
9399 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9401 return !TARGET_OLDABI;
9405 mips_issue_rate (void)
9409 case PROCESSOR_R5400:
9410 case PROCESSOR_R5500:
9411 case PROCESSOR_R7000:
9412 case PROCESSOR_R9000:
9423 /* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
9424 processors that have a DFA pipeline description. */
9427 mips_use_dfa_pipeline_interface (void)
9431 case PROCESSOR_R5400:
9432 case PROCESSOR_R5500:
9433 case PROCESSOR_R7000:
9434 case PROCESSOR_R9000:
9435 case PROCESSOR_SR71000:
9445 mips_emit_prefetch (rtx *operands)
9447 int write = INTVAL (operands[1]);
9448 int locality = INTVAL (operands[2]);
9449 int indexed = GET_CODE (operands[3]) == REG;
9454 code = (write ? 5 : 4); /* store_streamed / load_streamed. */
9455 else if (locality <= 2)
9456 code = (write ? 1 : 0); /* store / load. */
9458 code = (write ? 7 : 6); /* store_retained / load_retained. */
9460 sprintf (buffer, "%s\t%d,%%3(%%0)", indexed ? "prefx" : "pref", code);
9461 output_asm_insn (buffer, operands);
9468 /* Output assembly to switch to section NAME with attribute FLAGS. */
9471 irix_asm_named_section_1 (const char *name, unsigned int flags,
9474 unsigned int sh_type, sh_flags, sh_entsize;
9477 if (!(flags & SECTION_DEBUG))
9478 sh_flags |= 2; /* SHF_ALLOC */
9479 if (flags & SECTION_WRITE)
9480 sh_flags |= 1; /* SHF_WRITE */
9481 if (flags & SECTION_CODE)
9482 sh_flags |= 4; /* SHF_EXECINSTR */
9483 if (flags & SECTION_SMALL)
9484 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
9485 if (strcmp (name, ".debug_frame") == 0)
9486 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
9487 if (flags & SECTION_DEBUG)
9488 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
9489 else if (flags & SECTION_BSS)
9490 sh_type = 8; /* SHT_NOBITS */
9492 sh_type = 1; /* SHT_PROGBITS */
9494 if (flags & SECTION_CODE)
9499 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
9500 name, sh_type, sh_flags, sh_entsize, align);
9504 irix_asm_named_section (const char *name, unsigned int flags)
9506 if (TARGET_SGI_O32_AS)
9507 default_no_named_section (name, flags);
9508 else if (mips_abi == ABI_32 && TARGET_GAS)
9509 default_elf_asm_named_section (name, flags);
9511 irix_asm_named_section_1 (name, flags, 0);
9514 /* In addition to emitting a .align directive, record the maximum
9515 alignment requested for the current section. */
9517 struct GTY (()) irix_section_align_entry
9524 static htab_t irix_section_align_htab;
9525 static FILE *irix_orig_asm_out_file;
9528 irix_section_align_entry_eq (const void *p1, const void *p2)
9530 const struct irix_section_align_entry *old = p1;
9531 const char *new = p2;
9533 return strcmp (old->name, new) == 0;
9537 irix_section_align_entry_hash (const void *p)
9539 const struct irix_section_align_entry *old = p;
9540 return htab_hash_string (old->name);
9544 irix_asm_output_align (FILE *file, unsigned int log)
9546 const char *section = current_section_name ();
9547 struct irix_section_align_entry **slot, *entry;
9549 if (mips_abi != ABI_32)
9554 slot = (struct irix_section_align_entry **)
9555 htab_find_slot_with_hash (irix_section_align_htab, section,
9556 htab_hash_string (section), INSERT);
9560 entry = (struct irix_section_align_entry *)
9561 xmalloc (sizeof (struct irix_section_align_entry));
9563 entry->name = section;
9565 entry->flags = current_section_flags ();
9567 else if (entry->log < log)
9571 fprintf (file, "\t.align\t%u\n", log);
9574 /* The IRIX assembler does not record alignment from .align directives,
9575 but takes it from the first .section directive seen. Play file
9576 switching games so that we can emit a .section directive at the
9577 beginning of the file with the proper alignment attached. */
9580 irix_file_start (void)
9584 if (mips_abi == ABI_32)
9587 irix_orig_asm_out_file = asm_out_file;
9588 asm_out_file = tmpfile ();
9590 irix_section_align_htab = htab_create (31, irix_section_align_entry_hash,
9591 irix_section_align_entry_eq, NULL);
9595 irix_section_align_1 (void **slot, void *data ATTRIBUTE_UNUSED)
9597 const struct irix_section_align_entry *entry
9598 = *(const struct irix_section_align_entry **) slot;
9600 irix_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
9605 copy_file_data (FILE *to, FILE *from)
9611 fatal_error ("can't rewind temp file: %m");
9613 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
9614 if (fwrite (buffer, 1, len, to) != len)
9615 fatal_error ("can't write to output file: %m");
9618 fatal_error ("can't read from temp file: %m");
9621 fatal_error ("can't close temp file: %m");
9625 irix_file_end (void)
9627 if (mips_abi != ABI_32)
9629 /* Emit section directives with the proper alignment at the top of the
9630 real output file. */
9631 FILE *temp = asm_out_file;
9632 asm_out_file = irix_orig_asm_out_file;
9633 htab_traverse (irix_section_align_htab, irix_section_align_1, NULL);
9635 /* Copy the data emitted to the temp file to the real output file. */
9636 copy_file_data (asm_out_file, temp);
9643 /* Implement TARGET_SECTION_TYPE_FLAGS. Make sure that .sdata and
9644 .sbss sections get the SECTION_SMALL flag: this isn't set by the
9648 irix_section_type_flags (tree decl, const char *section, int relocs_p)
9652 flags = default_section_type_flags (decl, section, relocs_p);
9654 if (strcmp (section, ".sdata") == 0
9655 || strcmp (section, ".sbss") == 0
9656 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9657 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9658 flags |= SECTION_SMALL;
9663 #endif /* TARGET_IRIX */
9665 #include "gt-mips.h"