1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-attr.h"
55 #include "target-def.h"
62 #define STAB_CODE_TYPE enum __stab_debug_code
64 #define STAB_CODE_TYPE int
67 extern tree lookup_name PARAMS ((tree));
69 /* Enumeration for all of the relational tests, so that we can build
70 arrays indexed by the test type, and not worry about the order
89 static enum internal_test map_test_to_internal_test PARAMS ((enum rtx_code));
90 static int mips16_simple_memory_operand PARAMS ((rtx, rtx,
92 static int m16_check_op PARAMS ((rtx, int, int, int));
93 static void block_move_loop PARAMS ((rtx, rtx,
97 static void block_move_call PARAMS ((rtx, rtx, rtx));
98 static rtx mips_add_large_offset_to_sp PARAMS ((HOST_WIDE_INT,
100 static void mips_annotate_frame_insn PARAMS ((rtx, rtx));
101 static rtx mips_frame_set PARAMS ((enum machine_mode,
103 static void mips_emit_frame_related_store PARAMS ((rtx, rtx,
105 static void save_restore_insns PARAMS ((int, rtx,
107 static void mips16_output_gp_offset PARAMS ((FILE *, rtx));
108 static void mips16_fp_args PARAMS ((FILE *, int, int));
109 static void build_mips16_function_stub PARAMS ((FILE *));
110 static void mips16_optimize_gp PARAMS ((rtx));
111 static rtx add_constant PARAMS ((struct constant **,
114 static void dump_constants PARAMS ((struct constant *,
116 static rtx mips_find_symbol PARAMS ((rtx));
117 static void abort_with_insn PARAMS ((rtx, const char *))
119 static int symbolic_expression_p PARAMS ((rtx));
120 static void mips_add_gc_roots PARAMS ((void));
121 static bool mips_assemble_integer PARAMS ((rtx, unsigned int, int));
122 static void mips_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
123 static void mips_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
124 static enum processor_type mips_parse_cpu PARAMS ((const char *));
125 static void copy_file_data PARAMS ((FILE *, FILE *));
127 static void iris6_asm_named_section_1 PARAMS ((const char *,
130 static void iris6_asm_named_section PARAMS ((const char *,
132 static int iris_section_align_entry_eq PARAMS ((const PTR, const PTR));
133 static hashval_t iris_section_align_entry_hash PARAMS ((const PTR));
134 static int iris6_section_align_1 PARAMS ((void **, void *));
136 static int mips_adjust_cost PARAMS ((rtx, rtx, rtx, int));
138 /* Global variables for machine-dependent things. */
140 /* Threshold for data being put into the small data/bss area, instead
141 of the normal data area (references to the small data/bss area take
142 1 instruction, and use the global pointer, references to the normal
143 data area takes 2 instructions). */
144 int mips_section_threshold = -1;
146 /* Count the number of .file directives, so that .loc is up to date. */
147 int num_source_filenames = 0;
149 /* Count the number of sdb related labels are generated (to find block
150 start and end boundaries). */
151 int sdb_label_count = 0;
153 /* Next label # for each statement for Silicon Graphics IRIS systems. */
156 /* Non-zero if inside of a function, because the stupid MIPS asm can't
157 handle .files inside of functions. */
158 int inside_function = 0;
160 /* Files to separate the text and the data output, so that all of the data
161 can be emitted before the text, which will mean that the assembler will
162 generate smaller code, based on the global pointer. */
163 FILE *asm_out_data_file;
164 FILE *asm_out_text_file;
166 /* Linked list of all externals that are to be emitted when optimizing
167 for the global pointer if they haven't been declared by the end of
168 the program with an appropriate .comm or initialization. */
172 struct extern_list *next; /* next external */
173 const char *name; /* name of the external */
174 int size; /* size in bytes */
177 /* Name of the file containing the current function. */
178 const char *current_function_file = "";
180 /* Warning given that Mips ECOFF can't support changing files
181 within a function. */
182 int file_in_function_warning = FALSE;
184 /* Whether to suppress issuing .loc's because the user attempted
185 to change the filename within a function. */
186 int ignore_line_number = FALSE;
188 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
194 /* The next branch instruction is a branch likely, not branch normal. */
195 int mips_branch_likely;
197 /* Count of delay slots and how many are filled. */
198 int dslots_load_total;
199 int dslots_load_filled;
200 int dslots_jump_total;
201 int dslots_jump_filled;
203 /* # of nops needed by previous insn */
204 int dslots_number_nops;
206 /* Number of 1/2/3 word references to data items (ie, not jal's). */
209 /* registers to check for load delay */
210 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
212 /* Cached operands, and operator to compare for use in set/branch/trap
213 on condition codes. */
216 /* what type of branch to use */
217 enum cmp_type branch_type;
219 /* Number of previously seen half-pic pointers and references. */
220 static int prev_half_pic_ptrs = 0;
221 static int prev_half_pic_refs = 0;
223 /* The target cpu for code generation. */
224 enum processor_type mips_arch;
226 /* The target cpu for optimization and scheduling. */
227 enum processor_type mips_tune;
229 /* which instruction set architecture to use. */
232 /* which abi to use. */
235 /* Strings to hold which cpu and instruction set architecture to use. */
236 const char *mips_cpu_string; /* for -mcpu=<xxx> */
237 const char *mips_arch_string; /* for -march=<xxx> */
238 const char *mips_tune_string; /* for -mtune=<xxx> */
239 const char *mips_isa_string; /* for -mips{1,2,3,4} */
240 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
242 /* Whether we are generating mips16 code. This is a synonym for
243 TARGET_MIPS16, and exists for use as an attribute. */
246 /* This variable is set by -mno-mips16. We only care whether
247 -mno-mips16 appears or not, and using a string in this fashion is
248 just a way to avoid using up another bit in target_flags. */
249 const char *mips_no_mips16_string;
251 /* This is only used to determine if an type size setting option was
252 explicitly specified (-mlong64, -mint64, -mlong32). The specs
253 set this option if such an option is used. */
254 const char *mips_explicit_type_size_string;
256 /* Whether we are generating mips16 hard float code. In mips16 mode
257 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
258 -msoft-float was not specified by the user, which means that we
259 should arrange to call mips32 hard floating point code. */
260 int mips16_hard_float;
262 /* This variable is set by -mentry. We only care whether -mentry
263 appears or not, and using a string in this fashion is just a way to
264 avoid using up another bit in target_flags. */
265 const char *mips_entry_string;
267 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
269 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
272 /* If TRUE, we split addresses into their high and low parts in the RTL. */
273 int mips_split_addresses;
275 /* Generating calls to position independent functions? */
276 enum mips_abicalls_type mips_abicalls;
278 /* High and low marks for floating point values which we will accept
279 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
280 initialized in override_options. */
281 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
283 /* Mode used for saving/restoring general purpose registers. */
284 static enum machine_mode gpr_mode;
286 /* Array giving truth value on whether or not a given hard register
287 can support a given mode. */
288 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
290 /* Current frame information calculated by compute_frame_size. */
291 struct mips_frame_info current_frame_info;
293 /* Zero structure to initialize current_frame_info. */
294 struct mips_frame_info zero_frame_info;
296 /* Pseudo-reg holding the address of the current function when
297 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
298 by mips_finalize_pic if it was created. */
299 rtx embedded_pic_fnaddr_rtx;
301 /* The length of all strings seen when compiling for the mips16. This
302 is used to tell how many strings are in the constant pool, so that
303 we can see if we may have an overflow. This is reset each time the
304 constant pool is output. */
305 int mips_string_length;
307 /* Pseudo-reg holding the value of $28 in a mips16 function which
308 refers to GP relative global variables. */
309 rtx mips16_gp_pseudo_rtx;
311 /* In mips16 mode, we build a list of all the string constants we see
312 in a particular function. */
314 struct string_constant
316 struct string_constant *next;
320 static struct string_constant *string_constants;
322 /* List of all MIPS punctuation characters used by print_operand. */
323 char mips_print_operand_punct[256];
325 /* Map GCC register number to debugger register number. */
326 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
328 /* Buffer to use to enclose a load/store operation with %{ %} to
329 turn on .set volatile. */
330 static char volatile_buffer[60];
332 /* Hardware names for the registers. If -mrnames is used, this
333 will be overwritten with mips_sw_reg_names. */
335 char mips_reg_names[][8] =
337 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
338 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
339 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
340 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
341 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
342 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
343 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
344 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
345 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
346 "$fcc5","$fcc6","$fcc7","$rap"
349 /* Mips software names for the registers, used to overwrite the
350 mips_reg_names array. */
352 static const char mips_sw_reg_names[][8] =
354 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
355 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
356 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
357 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
358 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
359 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
360 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
361 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
362 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
363 "$fcc5","$fcc6","$fcc7","$rap"
366 /* Map hard register number to register class */
367 const enum reg_class mips_regno_to_class[] =
369 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
370 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
371 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
372 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
373 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
374 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
375 T_REG, GR_REGS, GR_REGS, GR_REGS,
376 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
377 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
378 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
379 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
380 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
381 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
382 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
383 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
384 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
385 HI_REG, LO_REG, HILO_REG, ST_REGS,
386 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
387 ST_REGS, ST_REGS, ST_REGS, GR_REGS
390 /* Map register constraint character to register class. */
391 enum reg_class mips_char_to_class[256] =
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
425 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
426 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
427 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
428 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
429 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
430 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
431 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
432 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
433 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
434 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
435 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
436 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
437 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
438 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
439 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
440 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
441 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
442 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
443 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
444 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
445 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
446 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
447 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
448 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
449 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
450 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
451 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
452 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
453 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
454 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
455 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
456 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
459 /* Initialize the GCC target structure. */
460 #undef TARGET_ASM_ALIGNED_HI_OP
461 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
462 #undef TARGET_ASM_ALIGNED_SI_OP
463 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
464 #undef TARGET_ASM_INTEGER
465 #define TARGET_ASM_INTEGER mips_assemble_integer
467 #if TARGET_IRIX5 && !TARGET_IRIX6
468 #undef TARGET_ASM_UNALIGNED_HI_OP
469 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.half\t"
470 #undef TARGET_ASM_UNALIGNED_SI_OP
471 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.word\t"
474 #undef TARGET_ASM_FUNCTION_PROLOGUE
475 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
476 #undef TARGET_ASM_FUNCTION_EPILOGUE
477 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
479 #undef TARGET_SCHED_ADJUST_COST
480 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
482 struct gcc_target targetm = TARGET_INITIALIZER;
484 /* Return truth value of whether OP can be used as an operands
485 where a register or 16 bit unsigned integer is needed. */
488 uns_arith_operand (op, mode)
490 enum machine_mode mode;
492 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
495 return register_operand (op, mode);
498 /* Return truth value of whether OP can be used as an operands
499 where a 16 bit integer is needed */
502 arith_operand (op, mode)
504 enum machine_mode mode;
506 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
509 /* On the mips16, a GP relative value is a signed 16 bit offset. */
510 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
513 return register_operand (op, mode);
516 /* Return truth value of whether OP can be used as an operand in a two
517 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
520 arith32_operand (op, mode)
522 enum machine_mode mode;
524 if (GET_CODE (op) == CONST_INT)
527 return register_operand (op, mode);
530 /* Return truth value of whether OP is an integer which fits in 16 bits. */
535 enum machine_mode mode ATTRIBUTE_UNUSED;
537 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
540 /* Return truth value of whether OP is a 32 bit integer which is too big to
541 be loaded with one instruction. */
546 enum machine_mode mode ATTRIBUTE_UNUSED;
550 if (GET_CODE (op) != CONST_INT)
555 /* ior reg,$r0,value */
556 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
559 /* subu reg,$r0,value */
560 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
563 /* lui reg,value>>16 */
564 if ((value & 0x0000ffff) == 0)
570 /* Return truth value of whether OP is a register or the constant 0.
571 In mips16 mode, we only accept a register, since the mips16 does
575 reg_or_0_operand (op, mode)
577 enum machine_mode mode;
579 switch (GET_CODE (op))
584 return INTVAL (op) == 0;
589 return op == CONST0_RTX (mode);
593 return register_operand (op, mode);
602 /* Return truth value of whether OP is a register or the constant 0,
603 even in mips16 mode. */
606 true_reg_or_0_operand (op, mode)
608 enum machine_mode mode;
610 switch (GET_CODE (op))
613 return INTVAL (op) == 0;
616 return op == CONST0_RTX (mode);
620 return register_operand (op, mode);
629 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
632 mips_const_double_ok (op, mode)
634 enum machine_mode mode;
638 if (GET_CODE (op) != CONST_DOUBLE)
641 if (mode == VOIDmode)
644 if (mode != SFmode && mode != DFmode)
647 if (op == CONST0_RTX (mode))
650 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
651 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
654 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
656 if (REAL_VALUE_ISNAN (d))
659 if (REAL_VALUE_NEGATIVE (d))
660 d = REAL_VALUE_NEGATE (d);
664 if (REAL_VALUES_LESS (d, dfhigh)
665 && REAL_VALUES_LESS (dflow, d))
670 if (REAL_VALUES_LESS (d, sfhigh)
671 && REAL_VALUES_LESS (sflow, d))
678 /* Accept the floating point constant 1 in the appropriate mode. */
681 const_float_1_operand (op, mode)
683 enum machine_mode mode;
686 static REAL_VALUE_TYPE onedf;
687 static REAL_VALUE_TYPE onesf;
688 static int one_initialized;
690 if (GET_CODE (op) != CONST_DOUBLE
691 || mode != GET_MODE (op)
692 || (mode != DFmode && mode != SFmode))
695 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
697 /* We only initialize these values if we need them, since we will
698 never get called unless mips_isa >= 4. */
699 if (! one_initialized)
701 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
702 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
707 return REAL_VALUES_EQUAL (d, onedf);
709 return REAL_VALUES_EQUAL (d, onesf);
712 /* Return true if a memory load or store of REG plus OFFSET in MODE
713 can be represented in a single word on the mips16. */
716 mips16_simple_memory_operand (reg, offset, mode)
719 enum machine_mode mode;
726 /* We can't tell, because we don't know how the value will
727 eventually be accessed. Returning 0 here does no great
728 harm; it just prevents some possible instruction scheduling. */
732 size = GET_MODE_SIZE (mode);
734 if (INTVAL (offset) % size != 0)
736 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
740 if (INTVAL (offset) >= 0 && INTVAL (offset) < (HOST_WIDE_INT)(off * size))
745 /* Return truth value if a memory operand fits in a single instruction
746 (ie, register + small offset). */
749 simple_memory_operand (op, mode)
751 enum machine_mode mode;
753 rtx addr, plus0, plus1;
755 /* Eliminate non-memory operations */
756 if (GET_CODE (op) != MEM)
759 /* dword operations really put out 2 instructions, so eliminate them. */
760 /* ??? This isn't strictly correct. It is OK to accept multiword modes
761 here, since the length attributes are being set correctly, but only
762 if the address is offsettable. LO_SUM is not offsettable. */
763 if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
766 /* Decode the address now. */
768 switch (GET_CODE (addr))
777 return SMALL_INT (addr);
780 plus0 = XEXP (addr, 0);
781 plus1 = XEXP (addr, 1);
782 if (GET_CODE (plus0) == REG
783 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
785 || mips16_simple_memory_operand (plus0, plus1, mode)))
788 else if (GET_CODE (plus1) == REG
789 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
791 || mips16_simple_memory_operand (plus1, plus0, mode)))
798 /* We used to allow small symbol refs here (ie, stuff in .sdata
799 or .sbss), but this causes some bugs in G++. Also, it won't
800 interfere if the MIPS linker rewrites the store instruction
801 because the function is PIC. */
803 case LABEL_REF: /* never gp relative */
807 /* If -G 0, we can never have a GP relative memory operation.
808 Also, save some time if not optimizing. */
813 rtx offset = const0_rtx;
814 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
815 if (GET_CODE (op) != SYMBOL_REF)
818 /* let's be paranoid.... */
819 if (! SMALL_INT (offset))
826 return SYMBOL_REF_FLAG (addr);
829 /* This SYMBOL_REF case is for the mips16. If the above case is
830 reenabled, this one should be merged in. */
832 /* References to the constant pool on the mips16 use a small
833 offset if the function is small. The only time we care about
834 getting this right is during delayed branch scheduling, so
835 don't need to check until then. The machine_dependent_reorg
836 function will set the total length of the instructions used
837 in the function in current_frame_info. If that is small
838 enough, we know for sure that this is a small offset. It
839 would be better if we could take into account the location of
840 the instruction within the function, but we can't, because we
841 don't know where we are. */
843 && CONSTANT_POOL_ADDRESS_P (addr)
844 && current_frame_info.insns_len > 0)
848 size = current_frame_info.insns_len + get_pool_size ();
849 if (GET_MODE_SIZE (mode) == 4)
850 return size < 4 * 0x100;
851 else if (GET_MODE_SIZE (mode) == 8)
852 return size < 8 * 0x20;
866 /* Return nonzero for a memory address that can be used to load or store
870 double_memory_operand (op, mode)
872 enum machine_mode mode;
874 if (GET_CODE (op) != MEM
875 || ! memory_operand (op, mode))
877 /* During reload, we accept a pseudo register if it has an
878 appropriate memory address. If we don't do this, we will
879 wind up reloading into a register, and then reloading that
880 register from memory, when we could just reload directly from
882 if (reload_in_progress
883 && GET_CODE (op) == REG
884 && REGNO (op) >= FIRST_PSEUDO_REGISTER
885 && reg_renumber[REGNO (op)] < 0
886 && reg_equiv_mem[REGNO (op)] != 0
887 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
890 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
891 the same test performed for 'm' in find_reloads. */
893 if (reload_in_progress
895 && (GET_CODE (op) == MEM
896 || (GET_CODE (op) == REG
897 && REGNO (op) >= FIRST_PSEUDO_REGISTER
898 && reg_renumber[REGNO (op)] < 0)))
901 if (reload_in_progress
903 && GET_CODE (op) == MEM)
909 /* During reload on the mips16, we accept a large offset
910 from the frame pointer or the stack pointer. This large
911 address will get reloaded anyhow. */
912 if (GET_CODE (addr) == PLUS
913 && GET_CODE (XEXP (addr, 0)) == REG
914 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
915 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
916 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
917 && ! SMALL_INT (XEXP (addr, 1)))
918 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
919 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
922 /* Similarly, we accept a case where the memory address is
923 itself on the stack, and will be reloaded. */
924 if (GET_CODE (addr) == MEM)
928 maddr = XEXP (addr, 0);
929 if (GET_CODE (maddr) == PLUS
930 && GET_CODE (XEXP (maddr, 0)) == REG
931 && (REGNO (XEXP (maddr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
932 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
933 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
934 && ! SMALL_INT (XEXP (maddr, 1)))
935 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
936 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
940 /* We also accept the same case when we have a 16 bit signed
941 offset mixed in as well. The large address will get
942 reloaded, and the 16 bit offset will be OK. */
943 if (GET_CODE (addr) == PLUS
944 && GET_CODE (XEXP (addr, 0)) == MEM
945 && GET_CODE (XEXP (addr, 1)) == CONST_INT
946 && SMALL_INT (XEXP (addr, 1)))
948 addr = XEXP (XEXP (addr, 0), 0);
949 if (GET_CODE (addr) == PLUS
950 && GET_CODE (XEXP (addr, 0)) == REG
951 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
952 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
953 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
954 && ! SMALL_INT (XEXP (addr, 1)))
955 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
956 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
966 /* In this case we can use an instruction like sd. */
970 /* Make sure that 4 added to the address is a valid memory address.
971 This essentially just checks for overflow in an added constant. */
973 if (CONSTANT_ADDRESS_P (XEXP (op, 0)))
976 op = adjust_address_nv (op, GET_MODE_CLASS (mode) == MODE_INT
977 ? SImode : SFmode, 4);
978 return memory_address_p (GET_MODE (op), XEXP (op, 0));
981 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
984 equality_op (op, mode)
986 enum machine_mode mode;
988 if (mode != GET_MODE (op))
991 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
994 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
999 enum machine_mode mode;
1001 if (mode != GET_MODE (op))
1004 return GET_RTX_CLASS (GET_CODE (op)) == '<';
1007 /* Return nonzero if the code is a relational operation suitable for a
1008 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
1009 We need this in the insn that expands `trap_if' in order to prevent
1010 combine from erroneously altering the condition. */
1013 trap_cmp_op (op, mode)
1015 enum machine_mode mode;
1017 if (mode != GET_MODE (op))
1020 switch (GET_CODE (op))
1035 /* Return nonzero if the operand is either the PC or a label_ref. */
1038 pc_or_label_operand (op, mode)
1040 enum machine_mode mode ATTRIBUTE_UNUSED;
1045 if (GET_CODE (op) == LABEL_REF)
1051 /* Test for a valid operand for a call instruction.
1052 Don't allow the arg pointer register or virtual regs
1053 since they may change into reg + const, which the patterns
1054 can't handle yet. */
1057 call_insn_operand (op, mode)
1059 enum machine_mode mode ATTRIBUTE_UNUSED;
1061 return (CONSTANT_ADDRESS_P (op)
1062 || (GET_CODE (op) == REG && op != arg_pointer_rtx
1063 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
1064 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
1067 /* Return nonzero if OPERAND is valid as a source operand for a move
1071 move_operand (op, mode)
1073 enum machine_mode mode;
1075 /* Accept any general operand after reload has started; doing so
1076 avoids losing if reload does an in-place replacement of a register
1077 with a SYMBOL_REF or CONST. */
1078 return (general_operand (op, mode)
1079 && (! (mips_split_addresses && mips_check_split (op, mode))
1080 || reload_in_progress || reload_completed)
1082 && GET_CODE (op) == SYMBOL_REF
1083 && ! mips16_constant (op, mode, 1, 0)));
1086 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1087 This accepts not only general_operand, but also sign extended
1088 constants and registers. We need to accept sign extended constants
1089 in case a sign extended register which is used in an expression,
1090 and is equivalent to a constant, is spilled. */
1093 movdi_operand (op, mode)
1095 enum machine_mode mode;
1099 && GET_CODE (op) == SIGN_EXTEND
1100 && GET_MODE (op) == DImode
1101 && (GET_MODE (XEXP (op, 0)) == SImode
1102 || (GET_CODE (XEXP (op, 0)) == CONST_INT
1103 && GET_MODE (XEXP (op, 0)) == VOIDmode))
1104 && (register_operand (XEXP (op, 0), SImode)
1105 || immediate_operand (XEXP (op, 0), SImode)))
1108 return (general_operand (op, mode)
1110 && GET_CODE (op) == SYMBOL_REF
1111 && ! mips16_constant (op, mode, 1, 0)));
1114 /* Like register_operand, but when in 64 bit mode also accept a sign
1115 extend of a 32 bit register, since the value is known to be already
1119 se_register_operand (op, mode)
1121 enum machine_mode mode;
1125 && GET_CODE (op) == SIGN_EXTEND
1126 && GET_MODE (op) == DImode
1127 && GET_MODE (XEXP (op, 0)) == SImode
1128 && register_operand (XEXP (op, 0), SImode))
1131 return register_operand (op, mode);
1134 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1135 extend of a 32 bit register, since the value is known to be already
1139 se_reg_or_0_operand (op, mode)
1141 enum machine_mode mode;
1145 && GET_CODE (op) == SIGN_EXTEND
1146 && GET_MODE (op) == DImode
1147 && GET_MODE (XEXP (op, 0)) == SImode
1148 && register_operand (XEXP (op, 0), SImode))
1151 return reg_or_0_operand (op, mode);
1154 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1155 extend of a 32 bit register, since the value is known to be already
1159 se_uns_arith_operand (op, mode)
1161 enum machine_mode mode;
1165 && GET_CODE (op) == SIGN_EXTEND
1166 && GET_MODE (op) == DImode
1167 && GET_MODE (XEXP (op, 0)) == SImode
1168 && register_operand (XEXP (op, 0), SImode))
1171 return uns_arith_operand (op, mode);
1174 /* Like arith_operand, but when in 64 bit mode also accept a sign
1175 extend of a 32 bit register, since the value is known to be already
1179 se_arith_operand (op, mode)
1181 enum machine_mode mode;
1185 && GET_CODE (op) == SIGN_EXTEND
1186 && GET_MODE (op) == DImode
1187 && GET_MODE (XEXP (op, 0)) == SImode
1188 && register_operand (XEXP (op, 0), SImode))
1191 return arith_operand (op, mode);
1194 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1195 extend of a 32 bit register, since the value is known to be already
1199 se_nonmemory_operand (op, mode)
1201 enum machine_mode mode;
1205 && GET_CODE (op) == SIGN_EXTEND
1206 && GET_MODE (op) == DImode
1207 && GET_MODE (XEXP (op, 0)) == SImode
1208 && register_operand (XEXP (op, 0), SImode))
1211 return nonmemory_operand (op, mode);
1214 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1215 sign extend of a 32 bit register, since the value is known to be
1216 already sign extended. */
1219 se_nonimmediate_operand (op, mode)
1221 enum machine_mode mode;
1225 && GET_CODE (op) == SIGN_EXTEND
1226 && GET_MODE (op) == DImode
1227 && GET_MODE (XEXP (op, 0)) == SImode
1228 && register_operand (XEXP (op, 0), SImode))
1231 return nonimmediate_operand (op, mode);
1234 /* Accept any operand that can appear in a mips16 constant table
1235 instruction. We can't use any of the standard operand functions
1236 because for these instructions we accept values that are not
1237 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1240 consttable_operand (op, mode)
1242 enum machine_mode mode ATTRIBUTE_UNUSED;
1244 return CONSTANT_P (op);
1247 /* Return nonzero if we split the address into high and low parts. */
1249 /* ??? We should also handle reg+array somewhere. We get four
1250 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1251 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1252 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1253 out of the address, then we have 4 instructions to combine. Perhaps
1254 add a 3->2 define_split for combine. */
1256 /* ??? We could also split a CONST_INT here if it is a large_int().
1257 However, it doesn't seem to be very useful to have %hi(constant).
1258 We would be better off by doing the masking ourselves and then putting
1259 the explicit high part of the constant in the RTL. This will give better
1260 optimization. Also, %hi(constant) needs assembler changes to work.
1261 There is already a define_split that does this. */
1264 mips_check_split (address, mode)
1266 enum machine_mode mode;
1268 /* ??? This is the same check used in simple_memory_operand.
1269 We use it here because LO_SUM is not offsettable. */
1270 if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
1273 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1274 || (GET_CODE (address) == CONST
1275 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1276 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1277 || GET_CODE (address) == LABEL_REF)
1283 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1286 mips_reg_mode_ok_for_base_p (reg, mode, strict)
1288 enum machine_mode mode;
1292 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
1293 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
1296 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1297 returns a nonzero value if XINSN is a legitimate address for a
1298 memory operand of the indicated MODE. STRICT is non-zero if this
1299 function is called during reload. */
1302 mips_legitimate_address_p (mode, xinsn, strict)
1303 enum machine_mode mode;
1307 if (TARGET_DEBUG_B_MODE)
1309 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1310 strict ? "" : "not ");
1311 GO_DEBUG_RTX (xinsn);
1314 /* Check for constant before stripping off SUBREG, so that we don't
1315 accept (subreg (const_int)) which will fail to reload. */
1316 if (CONSTANT_ADDRESS_P (xinsn)
1317 && ! (mips_split_addresses && mips_check_split (xinsn, mode))
1318 && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
1321 while (GET_CODE (xinsn) == SUBREG)
1322 xinsn = SUBREG_REG (xinsn);
1324 /* The mips16 can only use the stack pointer as a base register when
1325 loading SImode or DImode values. */
1326 if (GET_CODE (xinsn) == REG
1327 && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
1330 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
1332 register rtx xlow0 = XEXP (xinsn, 0);
1333 register rtx xlow1 = XEXP (xinsn, 1);
1335 while (GET_CODE (xlow0) == SUBREG)
1336 xlow0 = SUBREG_REG (xlow0);
1337 if (GET_CODE (xlow0) == REG
1338 && mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
1339 && mips_check_split (xlow1, mode))
1343 if (GET_CODE (xinsn) == PLUS)
1345 register rtx xplus0 = XEXP (xinsn, 0);
1346 register rtx xplus1 = XEXP (xinsn, 1);
1347 register enum rtx_code code0;
1348 register enum rtx_code code1;
1350 while (GET_CODE (xplus0) == SUBREG)
1351 xplus0 = SUBREG_REG (xplus0);
1352 code0 = GET_CODE (xplus0);
1354 while (GET_CODE (xplus1) == SUBREG)
1355 xplus1 = SUBREG_REG (xplus1);
1356 code1 = GET_CODE (xplus1);
1358 /* The mips16 can only use the stack pointer as a base register
1359 when loading SImode or DImode values. */
1361 && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
1363 if (code1 == CONST_INT && SMALL_INT (xplus1))
1366 /* On the mips16, we represent GP relative offsets in RTL.
1367 These are 16 bit signed values, and can serve as register
1370 && mips16_gp_offset_p (xplus1))
1373 /* For some code sequences, you actually get better code by
1374 pretending that the MIPS supports an address mode of a
1375 constant address + a register, even though the real
1376 machine doesn't support it. This is because the
1377 assembler can use $r1 to load just the high 16 bits, add
1378 in the register, and fold the low 16 bits into the memory
1379 reference, whereas the compiler generates a 4 instruction
1380 sequence. On the other hand, CSE is not as effective.
1381 It would be a win to generate the lui directly, but the
1382 MIPS assembler does not have syntax to generate the
1383 appropriate relocation. */
1385 /* Also accept CONST_INT addresses here, so no else. */
1386 /* Reject combining an embedded PIC text segment reference
1387 with a register. That requires an additional
1389 /* ??? Reject combining an address with a register for the MIPS
1390 64 bit ABI, because the SGI assembler can not handle this. */
1391 if (!TARGET_DEBUG_A_MODE
1392 && (mips_abi == ABI_32
1393 || mips_abi == ABI_O64
1394 || mips_abi == ABI_EABI)
1395 && CONSTANT_ADDRESS_P (xplus1)
1396 && ! mips_split_addresses
1397 && (!TARGET_EMBEDDED_PIC
1399 || GET_CODE (XEXP (xplus1, 0)) != MINUS)
1400 /* When assembling for machines with 64 bit registers,
1401 the assembler will sign-extend the constant "foo"
1402 in "la x, foo(x)" yielding the wrong result for:
1403 (set (blah:DI) (plus x y)). */
1405 || (code1 == CONST_INT
1406 && trunc_int_for_mode (INTVAL (xplus1),
1407 SImode) == INTVAL (xplus1)))
1413 if (TARGET_DEBUG_B_MODE)
1414 GO_PRINTF ("Not a legitimate address\n");
1416 /* The address was not legitimate. */
1421 /* We need a lot of little routines to check constant values on the
1422 mips16. These are used to figure out how long the instruction will
1423 be. It would be much better to do this using constraints, but
1424 there aren't nearly enough letters available. */
1427 m16_check_op (op, low, high, mask)
1433 return (GET_CODE (op) == CONST_INT
1434 && INTVAL (op) >= low
1435 && INTVAL (op) <= high
1436 && (INTVAL (op) & mask) == 0);
1440 m16_uimm3_b (op, mode)
1442 enum machine_mode mode ATTRIBUTE_UNUSED;
1444 return m16_check_op (op, 0x1, 0x8, 0);
1448 m16_simm4_1 (op, mode)
1450 enum machine_mode mode ATTRIBUTE_UNUSED;
1452 return m16_check_op (op, - 0x8, 0x7, 0);
1456 m16_nsimm4_1 (op, mode)
1458 enum machine_mode mode ATTRIBUTE_UNUSED;
1460 return m16_check_op (op, - 0x7, 0x8, 0);
1464 m16_simm5_1 (op, mode)
1466 enum machine_mode mode ATTRIBUTE_UNUSED;
1468 return m16_check_op (op, - 0x10, 0xf, 0);
1472 m16_nsimm5_1 (op, mode)
1474 enum machine_mode mode ATTRIBUTE_UNUSED;
1476 return m16_check_op (op, - 0xf, 0x10, 0);
1480 m16_uimm5_4 (op, mode)
1482 enum machine_mode mode ATTRIBUTE_UNUSED;
1484 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1488 m16_nuimm5_4 (op, mode)
1490 enum machine_mode mode ATTRIBUTE_UNUSED;
1492 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1496 m16_simm8_1 (op, mode)
1498 enum machine_mode mode ATTRIBUTE_UNUSED;
1500 return m16_check_op (op, - 0x80, 0x7f, 0);
1504 m16_nsimm8_1 (op, mode)
1506 enum machine_mode mode ATTRIBUTE_UNUSED;
1508 return m16_check_op (op, - 0x7f, 0x80, 0);
1512 m16_uimm8_1 (op, mode)
1514 enum machine_mode mode ATTRIBUTE_UNUSED;
1516 return m16_check_op (op, 0x0, 0xff, 0);
1520 m16_nuimm8_1 (op, mode)
1522 enum machine_mode mode ATTRIBUTE_UNUSED;
1524 return m16_check_op (op, - 0xff, 0x0, 0);
1528 m16_uimm8_m1_1 (op, mode)
1530 enum machine_mode mode ATTRIBUTE_UNUSED;
1532 return m16_check_op (op, - 0x1, 0xfe, 0);
1536 m16_uimm8_4 (op, mode)
1538 enum machine_mode mode ATTRIBUTE_UNUSED;
1540 return m16_check_op (op, 0x0, 0xff << 2, 3);
1544 m16_nuimm8_4 (op, mode)
1546 enum machine_mode mode ATTRIBUTE_UNUSED;
1548 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1552 m16_simm8_8 (op, mode)
1554 enum machine_mode mode ATTRIBUTE_UNUSED;
1556 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1560 m16_nsimm8_8 (op, mode)
1562 enum machine_mode mode ATTRIBUTE_UNUSED;
1564 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1567 /* References to the string table on the mips16 only use a small
1568 offset if the function is small. See the comment in the SYMBOL_REF
1569 case in simple_memory_operand. We can't check for LABEL_REF here,
1570 because the offset is always large if the label is before the
1571 referencing instruction. */
1574 m16_usym8_4 (op, mode)
1576 enum machine_mode mode ATTRIBUTE_UNUSED;
1578 if (GET_CODE (op) == SYMBOL_REF
1579 && SYMBOL_REF_FLAG (op)
1580 && current_frame_info.insns_len > 0
1581 && XSTR (op, 0)[0] == '*'
1582 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1583 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1584 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1587 struct string_constant *l;
1589 /* Make sure this symbol is on thelist of string constants to be
1590 output for this function. It is possible that it has already
1591 been output, in which case this requires a large offset. */
1592 for (l = string_constants; l != NULL; l = l->next)
1593 if (strcmp (l->label, XSTR (op, 0)) == 0)
1601 m16_usym5_4 (op, mode)
1603 enum machine_mode mode ATTRIBUTE_UNUSED;
1605 if (GET_CODE (op) == SYMBOL_REF
1606 && SYMBOL_REF_FLAG (op)
1607 && current_frame_info.insns_len > 0
1608 && XSTR (op, 0)[0] == '*'
1609 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1610 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1611 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1614 struct string_constant *l;
1616 /* Make sure this symbol is on thelist of string constants to be
1617 output for this function. It is possible that it has already
1618 been output, in which case this requires a large offset. */
1619 for (l = string_constants; l != NULL; l = l->next)
1620 if (strcmp (l->label, XSTR (op, 0)) == 0)
1627 /* Returns an operand string for the given instruction's delay slot,
1628 after updating filled delay slot statistics.
1630 We assume that operands[0] is the target register that is set.
1632 In order to check the next insn, most of this functionality is moved
1633 to FINAL_PRESCAN_INSN, and we just set the global variables that
1636 /* ??? This function no longer does anything useful, because final_prescan_insn
1637 now will never emit a nop. */
1640 mips_fill_delay_slot (ret, type, operands, cur_insn)
1641 const char *ret; /* normal string to return */
1642 enum delay_type type; /* type of delay */
1643 rtx operands[]; /* operands to use */
1644 rtx cur_insn; /* current insn */
1646 register rtx set_reg;
1647 register enum machine_mode mode;
1648 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1649 register int num_nops;
1651 if (type == DELAY_LOAD || type == DELAY_FCMP)
1654 else if (type == DELAY_HILO)
1660 /* Make sure that we don't put nop's after labels. */
1661 next_insn = NEXT_INSN (cur_insn);
1662 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1663 next_insn = NEXT_INSN (next_insn);
1665 dslots_load_total += num_nops;
1666 if (TARGET_DEBUG_F_MODE
1668 || type == DELAY_NONE
1672 || GET_CODE (next_insn) == CODE_LABEL
1673 || (set_reg = operands[0]) == 0)
1675 dslots_number_nops = 0;
1683 set_reg = operands[0];
1687 while (GET_CODE (set_reg) == SUBREG)
1688 set_reg = SUBREG_REG (set_reg);
1690 mode = GET_MODE (set_reg);
1691 dslots_number_nops = num_nops;
1692 mips_load_reg = set_reg;
1693 if (GET_MODE_SIZE (mode)
1694 > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1695 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
1699 if (type == DELAY_HILO)
1701 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1702 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
1714 /* Determine whether a memory reference takes one (based off of the GP
1715 pointer), two (normal), or three (label + reg) instructions, and bump the
1716 appropriate counter for -mstats. */
1719 mips_count_memory_refs (op, num)
1725 rtx addr, plus0, plus1;
1726 enum rtx_code code0, code1;
1729 if (TARGET_DEBUG_B_MODE)
1731 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1735 /* Skip MEM if passed, otherwise handle movsi of address. */
1736 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1738 /* Loop, going through the address RTL. */
1742 switch (GET_CODE (addr))
1750 plus0 = XEXP (addr, 0);
1751 plus1 = XEXP (addr, 1);
1752 code0 = GET_CODE (plus0);
1753 code1 = GET_CODE (plus1);
1763 if (code0 == CONST_INT)
1778 if (code1 == CONST_INT)
1785 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1792 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1802 n_words = 2; /* always 2 words */
1806 addr = XEXP (addr, 0);
1811 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1823 n_words += additional;
1827 num_refs[n_words-1] += num;
1831 /* Return RTL for the offset from the current function to the argument.
1833 ??? Which argument is this? */
1836 embedded_pic_offset (x)
1839 if (embedded_pic_fnaddr_rtx == NULL)
1843 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1845 /* Output code at function start to initialize the pseudo-reg. */
1846 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1847 inline functions, because it is called after RTL for the function
1848 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1849 does not get copied, and ends up not matching the rest of the RTL.
1850 This solution works, but means that we get unnecessary code to
1851 initialize this value every time a function is inlined into another
1854 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1855 XEXP (DECL_RTL (current_function_decl), 0)));
1856 seq = gen_sequence ();
1858 push_topmost_sequence ();
1859 emit_insn_after (seq, get_insns ());
1860 pop_topmost_sequence ();
1864 gen_rtx_CONST (Pmode,
1865 gen_rtx_MINUS (Pmode, x,
1866 XEXP (DECL_RTL (current_function_decl), 0)));
1869 /* Return the appropriate instructions to move one operand to another. */
1872 mips_move_1word (operands, insn, unsignedp)
1877 const char *ret = 0;
1878 rtx op0 = operands[0];
1879 rtx op1 = operands[1];
1880 enum rtx_code code0 = GET_CODE (op0);
1881 enum rtx_code code1 = GET_CODE (op1);
1882 enum machine_mode mode = GET_MODE (op0);
1883 int subreg_offset0 = 0;
1884 int subreg_offset1 = 0;
1885 enum delay_type delay = DELAY_NONE;
1887 while (code0 == SUBREG)
1889 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
1890 GET_MODE (SUBREG_REG (op0)),
1893 op0 = SUBREG_REG (op0);
1894 code0 = GET_CODE (op0);
1897 while (code1 == SUBREG)
1899 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
1900 GET_MODE (SUBREG_REG (op1)),
1903 op1 = SUBREG_REG (op1);
1904 code1 = GET_CODE (op1);
1907 /* For our purposes, a condition code mode is the same as SImode. */
1913 int regno0 = REGNO (op0) + subreg_offset0;
1917 int regno1 = REGNO (op1) + subreg_offset1;
1919 /* Just in case, don't do anything for assigning a register
1920 to itself, unless we are filling a delay slot. */
1921 if (regno0 == regno1 && set_nomacro == 0)
1924 else if (GP_REG_P (regno0))
1926 if (GP_REG_P (regno1))
1927 ret = "move\t%0,%1";
1929 else if (MD_REG_P (regno1))
1932 if (regno1 != HILO_REGNUM)
1938 else if (ST_REG_P (regno1) && ISA_HAS_8CC)
1939 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1944 if (FP_REG_P (regno1))
1945 ret = "mfc1\t%0,%1";
1947 else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
1948 ret = "cfc1\t%0,$31";
1952 else if (FP_REG_P (regno0))
1954 if (GP_REG_P (regno1))
1957 ret = "mtc1\t%1,%0";
1960 if (FP_REG_P (regno1))
1961 ret = "mov.s\t%0,%1";
1964 else if (MD_REG_P (regno0))
1966 if (GP_REG_P (regno1))
1969 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
1974 else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
1976 if (GP_REG_P (regno1))
1979 ret = "ctc1\t%0,$31";
1984 else if (code1 == MEM)
1989 mips_count_memory_refs (op1, 1);
1991 if (GP_REG_P (regno0))
1993 /* For loads, use the mode of the memory item, instead of the
1994 target, so zero/sign extend can use this code as well. */
1995 switch (GET_MODE (op1))
2004 ret = ((unsignedp && TARGET_64BIT)
2009 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
2012 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
2017 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
2020 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
2022 size_t i = strlen (ret);
2023 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2026 sprintf (volatile_buffer, "%%{%s%%}", ret);
2027 ret = volatile_buffer;
2031 else if (code1 == CONST_INT
2032 || (code1 == CONST_DOUBLE
2033 && GET_MODE (op1) == VOIDmode))
2035 if (code1 == CONST_DOUBLE)
2037 /* This can happen when storing constants into long long
2038 bitfields. Just store the least significant word of
2040 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2043 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
2045 if (GP_REG_P (regno0))
2046 ret = "move\t%0,%z1";
2048 else if (FP_REG_P (regno0))
2051 ret = "mtc1\t%z1,%0";
2054 else if (MD_REG_P (regno0))
2061 else if (GP_REG_P (regno0))
2063 /* Don't use X format, because that will give out of
2064 range numbers for 64 bit host and 32 bit target. */
2065 if (! TARGET_MIPS16)
2066 ret = "li\t%0,%1\t\t\t# %X1";
2069 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2071 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2072 ret = "li\t%0,%n1\n\tneg\t%0";
2077 else if (code1 == CONST_DOUBLE && mode == SFmode)
2079 if (op1 == CONST0_RTX (SFmode))
2081 if (GP_REG_P (regno0))
2082 ret = "move\t%0,%.";
2084 else if (FP_REG_P (regno0))
2087 ret = "mtc1\t%.,%0";
2094 ret = "li.s\t%0,%1";
2098 else if (code1 == LABEL_REF)
2101 mips_count_memory_refs (op1, 1);
2106 else if (code1 == SYMBOL_REF || code1 == CONST)
2108 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
2110 rtx offset = const0_rtx;
2112 if (GET_CODE (op1) == CONST)
2113 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
2115 if (GET_CODE (op1) == SYMBOL_REF)
2117 operands[2] = HALF_PIC_PTR (op1);
2120 mips_count_memory_refs (operands[2], 1);
2122 if (INTVAL (offset) == 0)
2125 ret = (unsignedp && TARGET_64BIT
2131 dslots_load_total++;
2132 operands[3] = offset;
2133 if (unsignedp && TARGET_64BIT)
2134 ret = (SMALL_INT (offset)
2135 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2136 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2138 ret = (SMALL_INT (offset)
2139 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2140 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2144 else if (TARGET_MIPS16
2146 && GET_CODE (XEXP (op1, 0)) == REG
2147 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2149 /* This case arises on the mips16; see
2150 mips16_gp_pseudo_reg. */
2151 ret = "move\t%0,%+";
2153 else if (TARGET_MIPS16
2154 && code1 == SYMBOL_REF
2155 && SYMBOL_REF_FLAG (op1)
2156 && (XSTR (op1, 0)[0] != '*'
2157 || strncmp (XSTR (op1, 0) + 1,
2159 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2161 /* This can occur when reloading the address of a GP
2162 relative symbol on the mips16. */
2163 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2168 mips_count_memory_refs (op1, 1);
2174 else if (code1 == PLUS)
2176 rtx add_op0 = XEXP (op1, 0);
2177 rtx add_op1 = XEXP (op1, 1);
2179 if (GET_CODE (XEXP (op1, 1)) == REG
2180 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
2181 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
2183 operands[2] = add_op0;
2184 operands[3] = add_op1;
2185 ret = "add%:\t%0,%2,%3";
2188 else if (code1 == HIGH)
2190 operands[1] = XEXP (op1, 0);
2191 ret = "lui\t%0,%%hi(%1)";
2195 else if (code0 == MEM)
2198 mips_count_memory_refs (op0, 1);
2202 int regno1 = REGNO (op1) + subreg_offset1;
2204 if (GP_REG_P (regno1))
2208 case SFmode: ret = "sw\t%1,%0"; break;
2209 case SImode: ret = "sw\t%1,%0"; break;
2210 case HImode: ret = "sh\t%1,%0"; break;
2211 case QImode: ret = "sb\t%1,%0"; break;
2216 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2220 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2224 case SFmode: ret = "sw\t%z1,%0"; break;
2225 case SImode: ret = "sw\t%z1,%0"; break;
2226 case HImode: ret = "sh\t%z1,%0"; break;
2227 case QImode: ret = "sb\t%z1,%0"; break;
2232 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2236 case SFmode: ret = "sw\t%.,%0"; break;
2237 case SImode: ret = "sw\t%.,%0"; break;
2238 case HImode: ret = "sh\t%.,%0"; break;
2239 case QImode: ret = "sb\t%.,%0"; break;
2244 if (ret != 0 && MEM_VOLATILE_P (op0))
2246 size_t i = strlen (ret);
2248 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2251 sprintf (volatile_buffer, "%%{%s%%}", ret);
2252 ret = volatile_buffer;
2258 abort_with_insn (insn, "bad move");
2262 if (delay != DELAY_NONE)
2263 return mips_fill_delay_slot (ret, delay, operands, insn);
2269 /* Return the appropriate instructions to move 2 words */
2272 mips_move_2words (operands, insn)
2276 const char *ret = 0;
2277 rtx op0 = operands[0];
2278 rtx op1 = operands[1];
2279 enum rtx_code code0 = GET_CODE (operands[0]);
2280 enum rtx_code code1 = GET_CODE (operands[1]);
2281 int subreg_offset0 = 0;
2282 int subreg_offset1 = 0;
2283 enum delay_type delay = DELAY_NONE;
2285 while (code0 == SUBREG)
2287 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2288 GET_MODE (SUBREG_REG (op0)),
2291 op0 = SUBREG_REG (op0);
2292 code0 = GET_CODE (op0);
2295 if (code1 == SIGN_EXTEND)
2297 op1 = XEXP (op1, 0);
2298 code1 = GET_CODE (op1);
2301 while (code1 == SUBREG)
2303 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2304 GET_MODE (SUBREG_REG (op1)),
2307 op1 = SUBREG_REG (op1);
2308 code1 = GET_CODE (op1);
2312 if (GET_CODE (operands[1]) == SIGN_EXTEND
2314 && code1 != CONST_INT
2315 /* The following three can happen as the result of a questionable
2317 && code1 != LABEL_REF
2318 && code1 != SYMBOL_REF
2324 int regno0 = REGNO (op0) + subreg_offset0;
2328 int regno1 = REGNO (op1) + subreg_offset1;
2330 /* Just in case, don't do anything for assigning a register
2331 to itself, unless we are filling a delay slot. */
2332 if (regno0 == regno1 && set_nomacro == 0)
2335 else if (FP_REG_P (regno0))
2337 if (FP_REG_P (regno1))
2338 ret = "mov.d\t%0,%1";
2346 abort_with_insn (insn, "bad move");
2348 #ifdef TARGET_FP_CALL_32
2349 if (FP_CALL_GP_REG_P (regno1))
2350 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2353 ret = "dmtc1\t%1,%0";
2356 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2360 else if (FP_REG_P (regno1))
2366 abort_with_insn (insn, "bad move");
2368 #ifdef TARGET_FP_CALL_32
2369 if (FP_CALL_GP_REG_P (regno0))
2370 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2373 ret = "dmfc1\t%0,%1";
2376 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2379 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2384 if (regno0 != HILO_REGNUM)
2386 else if (regno1 == 0)
2387 ret = "mtlo\t%.\n\tmthi\t%.";
2390 ret = "mthi\t%M1\n\tmtlo\t%L1";
2393 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2398 if (regno1 != HILO_REGNUM)
2402 ret = "mfhi\t%M0\n\tmflo\t%L0";
2405 else if (TARGET_64BIT)
2406 ret = "move\t%0,%1";
2408 else if (regno0 != (regno1+1))
2409 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2412 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2415 else if (code1 == CONST_DOUBLE)
2417 /* Move zero from $0 unless !TARGET_64BIT and recipient
2418 is 64-bit fp reg, in which case generate a constant. */
2419 if (op1 != CONST0_RTX (GET_MODE (op1))
2420 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2422 if (GET_MODE (op1) == DFmode)
2426 #ifdef TARGET_FP_CALL_32
2427 if (FP_CALL_GP_REG_P (regno0))
2429 if (TARGET_FLOAT64 && !TARGET_64BIT)
2431 split_double (op1, operands + 2, operands + 3);
2432 ret = "li\t%0,%2\n\tli\t%D0,%3";
2435 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2439 /* GNU as emits 64-bit code for li.d if the ISA is 3
2440 or higher. For !TARGET_64BIT && gp registers we
2441 need to avoid this by using two li instructions
2443 if (ISA_HAS_64BIT_REGS
2445 && ! FP_REG_P (regno0))
2447 split_double (op1, operands + 2, operands + 3);
2448 ret = "li\t%0,%2\n\tli\t%D0,%3";
2451 ret = "li.d\t%0,%1";
2454 else if (TARGET_64BIT)
2456 if (! TARGET_MIPS16)
2462 split_double (op1, operands + 2, operands + 3);
2463 ret = "li\t%0,%2\n\tli\t%D0,%3";
2469 if (GP_REG_P (regno0))
2471 #ifdef TARGET_FP_CALL_32
2472 && ! FP_CALL_GP_REG_P (regno0)
2475 : "move\t%0,%.\n\tmove\t%D0,%.");
2477 else if (FP_REG_P (regno0))
2482 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2487 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2489 if (GP_REG_P (regno0))
2492 : "move\t%0,%.\n\tmove\t%D0,%.");
2494 else if (FP_REG_P (regno0))
2501 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2503 else if (MD_REG_P (regno0))
2506 ret = (regno0 == HILO_REGNUM
2507 ? "mtlo\t%.\n\tmthi\t%."
2512 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2513 && GP_REG_P (regno0))
2519 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2521 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2522 ret = "li\t%0,%n1\n\tneg\t%0";
2524 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2525 ret = "li\t%0,%1\t\t# %X1";
2526 else if (HOST_BITS_PER_WIDE_INT < 64)
2527 /* We can't use 'X' for negative numbers, because then we won't
2528 get the right value for the upper 32 bits. */
2529 ret = (INTVAL (op1) < 0
2530 ? "dli\t%0,%1\t\t\t# %X1"
2531 : "dli\t%0,%X1\t\t# %1");
2533 /* We must use 'X', because otherwise LONG_MIN will print as
2534 a number that the assembler won't accept. */
2535 ret = "dli\t%0,%X1\t\t# %1";
2537 else if (HOST_BITS_PER_WIDE_INT < 64)
2539 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2542 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2543 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2544 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2546 operands[2] = GEN_INT (1);
2547 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2551 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2555 /* We use multiple shifts here, to avoid warnings about out
2556 of range shifts on 32 bit hosts. */
2557 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2559 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2562 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2563 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2564 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2566 operands[2] = GEN_INT (1);
2567 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2571 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2575 else if (code1 == MEM)
2580 mips_count_memory_refs (op1, 2);
2582 if (FP_REG_P (regno0))
2585 else if (TARGET_64BIT)
2588 #ifdef TARGET_FP_CALL_32
2589 if (FP_CALL_GP_REG_P (regno0))
2590 ret = (double_memory_operand (op1, GET_MODE (op1))
2591 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2592 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2598 else if (double_memory_operand (op1, GET_MODE (op1)))
2599 ret = (reg_mentioned_p (op0, op1)
2600 ? "lw\t%D0,%D1\n\tlw\t%0,%1"
2601 : "lw\t%0,%1\n\tlw\t%D0,%D1");
2603 if (ret != 0 && MEM_VOLATILE_P (op1))
2605 size_t i = strlen (ret);
2607 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2610 sprintf (volatile_buffer, "%%{%s%%}", ret);
2611 ret = volatile_buffer;
2615 else if (code1 == LABEL_REF)
2618 mips_count_memory_refs (op1, 2);
2620 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2621 /* We deliberately remove the 'a' from '%1', so that we don't
2622 have to add SIGN_EXTEND support to print_operand_address.
2623 print_operand will just call print_operand_address in this
2624 case, so there is no problem. */
2627 ret = "dla\t%0,%a1";
2629 else if (code1 == SYMBOL_REF || code1 == CONST)
2633 && GET_CODE (XEXP (op1, 0)) == REG
2634 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2636 /* This case arises on the mips16; see
2637 mips16_gp_pseudo_reg. */
2638 ret = "move\t%0,%+";
2640 else if (TARGET_MIPS16
2641 && code1 == SYMBOL_REF
2642 && SYMBOL_REF_FLAG (op1)
2643 && (XSTR (op1, 0)[0] != '*'
2644 || strncmp (XSTR (op1, 0) + 1,
2646 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2648 /* This can occur when reloading the address of a GP
2649 relative symbol on the mips16. */
2650 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2655 mips_count_memory_refs (op1, 2);
2657 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2658 /* We deliberately remove the 'a' from '%1', so that we don't
2659 have to add SIGN_EXTEND support to print_operand_address.
2660 print_operand will just call print_operand_address in this
2661 case, so there is no problem. */
2664 ret = "dla\t%0,%a1";
2669 else if (code0 == MEM)
2673 int regno1 = REGNO (op1) + subreg_offset1;
2675 if (FP_REG_P (regno1))
2678 else if (TARGET_64BIT)
2681 #ifdef TARGET_FP_CALL_32
2682 if (FP_CALL_GP_REG_P (regno1))
2683 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2689 else if (double_memory_operand (op0, GET_MODE (op0)))
2690 ret = "sw\t%1,%0\n\tsw\t%D1,%D0";
2693 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2694 || (code1 == CONST_DOUBLE
2695 && op1 == CONST0_RTX (GET_MODE (op1))))
2697 || double_memory_operand (op0, GET_MODE (op0))))
2702 ret = "sw\t%.,%0\n\tsw\t%.,%D0";
2706 mips_count_memory_refs (op0, 2);
2708 if (ret != 0 && MEM_VOLATILE_P (op0))
2710 size_t i = strlen (ret);
2712 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2715 sprintf (volatile_buffer, "%%{%s%%}", ret);
2716 ret = volatile_buffer;
2722 abort_with_insn (insn, "bad move");
2726 if (delay != DELAY_NONE)
2727 return mips_fill_delay_slot (ret, delay, operands, insn);
2732 /* Provide the costs of an addressing mode that contains ADDR.
2733 If ADDR is not a valid address, its cost is irrelevant. */
2736 mips_address_cost (addr)
2739 switch (GET_CODE (addr))
2749 rtx offset = const0_rtx;
2750 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2751 if (GET_CODE (addr) == LABEL_REF)
2754 if (GET_CODE (addr) != SYMBOL_REF)
2757 if (! SMALL_INT (offset))
2761 /* ... fall through ... */
2764 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2768 register rtx plus0 = XEXP (addr, 0);
2769 register rtx plus1 = XEXP (addr, 1);
2771 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2772 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
2774 if (GET_CODE (plus0) != REG)
2777 switch (GET_CODE (plus1))
2780 return SMALL_INT (plus1) ? 1 : 2;
2787 return mips_address_cost (plus1) + 1;
2801 /* Return nonzero if X is an address which needs a temporary register when
2802 reloaded while generating PIC code. */
2805 pic_address_needs_scratch (x)
2808 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2809 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2810 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2811 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2812 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2818 /* Make normal rtx_code into something we can index from an array */
2820 static enum internal_test
2821 map_test_to_internal_test (test_code)
2822 enum rtx_code test_code;
2824 enum internal_test test = ITEST_MAX;
2828 case EQ: test = ITEST_EQ; break;
2829 case NE: test = ITEST_NE; break;
2830 case GT: test = ITEST_GT; break;
2831 case GE: test = ITEST_GE; break;
2832 case LT: test = ITEST_LT; break;
2833 case LE: test = ITEST_LE; break;
2834 case GTU: test = ITEST_GTU; break;
2835 case GEU: test = ITEST_GEU; break;
2836 case LTU: test = ITEST_LTU; break;
2837 case LEU: test = ITEST_LEU; break;
2845 /* Generate the code to compare two integer values. The return value is:
2846 (reg:SI xx) The pseudo register the comparison is in
2847 0 No register, generate a simple branch.
2849 ??? This is called with result nonzero by the Scond patterns in
2850 mips.md. These patterns are called with a target in the mode of
2851 the Scond instruction pattern. Since this must be a constant, we
2852 must use SImode. This means that if RESULT is non-zero, it will
2853 always be an SImode register, even if TARGET_64BIT is true. We
2854 cope with this by calling convert_move rather than emit_move_insn.
2855 This will sometimes lead to an unnecessary extension of the result;
2867 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2868 enum rtx_code test_code; /* relational test (EQ, etc) */
2869 rtx result; /* result to store comp. or 0 if branch */
2870 rtx cmp0; /* first operand to compare */
2871 rtx cmp1; /* second operand to compare */
2872 int *p_invert; /* NULL or ptr to hold whether branch needs */
2873 /* to reverse its test */
2877 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2878 int const_low; /* low bound of constant we can accept */
2879 int const_high; /* high bound of constant we can accept */
2880 int const_add; /* constant to add (convert LE -> LT) */
2881 int reverse_regs; /* reverse registers in test */
2882 int invert_const; /* != 0 if invert value if cmp1 is constant */
2883 int invert_reg; /* != 0 if invert value if cmp1 is register */
2884 int unsignedp; /* != 0 for unsigned comparisons. */
2887 static struct cmp_info info[ (int)ITEST_MAX ] = {
2889 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2890 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2891 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2892 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2893 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2894 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2895 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2896 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2897 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2898 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2901 enum internal_test test;
2902 enum machine_mode mode;
2903 struct cmp_info *p_info;
2910 test = map_test_to_internal_test (test_code);
2911 if (test == ITEST_MAX)
2914 p_info = &info[(int) test];
2915 eqne_p = (p_info->test_code == XOR);
2917 mode = GET_MODE (cmp0);
2918 if (mode == VOIDmode)
2919 mode = GET_MODE (cmp1);
2921 /* Eliminate simple branches */
2922 branch_p = (result == 0);
2925 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2927 /* Comparisons against zero are simple branches */
2928 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2929 && (! TARGET_MIPS16 || eqne_p))
2932 /* Test for beq/bne. */
2933 if (eqne_p && ! TARGET_MIPS16)
2937 /* allocate a pseudo to calculate the value in. */
2938 result = gen_reg_rtx (mode);
2941 /* Make sure we can handle any constants given to us. */
2942 if (GET_CODE (cmp0) == CONST_INT)
2943 cmp0 = force_reg (mode, cmp0);
2945 if (GET_CODE (cmp1) == CONST_INT)
2947 HOST_WIDE_INT value = INTVAL (cmp1);
2949 if (value < p_info->const_low
2950 || value > p_info->const_high
2951 /* ??? Why? And why wasn't the similar code below modified too? */
2953 && HOST_BITS_PER_WIDE_INT < 64
2954 && p_info->const_add != 0
2955 && ((p_info->unsignedp
2956 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2957 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2958 : (value + p_info->const_add) > INTVAL (cmp1))
2959 != (p_info->const_add > 0))))
2960 cmp1 = force_reg (mode, cmp1);
2963 /* See if we need to invert the result. */
2964 invert = (GET_CODE (cmp1) == CONST_INT
2965 ? p_info->invert_const : p_info->invert_reg);
2967 if (p_invert != (int *)0)
2973 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2974 Comparison between two registers, may involve switching operands. */
2975 if (GET_CODE (cmp1) == CONST_INT)
2977 if (p_info->const_add != 0)
2979 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2981 /* If modification of cmp1 caused overflow,
2982 we would get the wrong answer if we follow the usual path;
2983 thus, x > 0xffffffffU would turn into x > 0U. */
2984 if ((p_info->unsignedp
2985 ? (unsigned HOST_WIDE_INT) new >
2986 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2987 : new > INTVAL (cmp1))
2988 != (p_info->const_add > 0))
2990 /* This test is always true, but if INVERT is true then
2991 the result of the test needs to be inverted so 0 should
2992 be returned instead. */
2993 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2997 cmp1 = GEN_INT (new);
3001 else if (p_info->reverse_regs)
3008 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
3012 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
3013 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
3016 if (test == ITEST_NE)
3018 if (! TARGET_MIPS16)
3020 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
3021 if (p_invert != NULL)
3027 reg2 = invert ? gen_reg_rtx (mode) : result;
3028 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
3033 else if (test == ITEST_EQ)
3035 reg2 = invert ? gen_reg_rtx (mode) : result;
3036 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
3044 if (! TARGET_MIPS16)
3048 /* The value is in $24. Copy it to another register, so
3049 that reload doesn't think it needs to store the $24 and
3050 the input to the XOR in the same location. */
3051 reg2 = gen_reg_rtx (mode);
3052 emit_move_insn (reg2, reg);
3054 one = force_reg (mode, const1_rtx);
3056 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3062 /* Emit the common code for doing conditional branches.
3063 operand[0] is the label to jump to.
3064 The comparison operands are saved away by cmp{si,di,sf,df}. */
3067 gen_conditional_branch (operands, test_code)
3069 enum rtx_code test_code;
3071 enum cmp_type type = branch_type;
3072 rtx cmp0 = branch_cmp[0];
3073 rtx cmp1 = branch_cmp[1];
3074 enum machine_mode mode;
3083 mode = type == CMP_SI ? SImode : DImode;
3085 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3093 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3094 /* We don't want to build a comparison against a non-zero
3096 cmp1 = force_reg (mode, cmp1);
3103 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3105 reg = gen_reg_rtx (CCmode);
3107 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3108 0 in the instruction built below. The MIPS FPU handles
3109 inequality testing by testing for equality and looking for a
3111 emit_insn (gen_rtx_SET (VOIDmode, reg,
3112 gen_rtx (test_code == NE ? EQ : test_code,
3113 CCmode, cmp0, cmp1)));
3115 test_code = test_code == NE ? EQ : NE;
3123 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
3126 /* Generate the branch. */
3128 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3137 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3138 gen_rtx_IF_THEN_ELSE (VOIDmode,
3139 gen_rtx (test_code, mode,
3144 /* Emit the common code for conditional moves. OPERANDS is the array
3145 of operands passed to the conditional move defined_expand. */
3148 gen_conditional_move (operands)
3151 rtx op0 = branch_cmp[0];
3152 rtx op1 = branch_cmp[1];
3153 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3154 enum rtx_code cmp_code = GET_CODE (operands[1]);
3155 enum rtx_code move_code = NE;
3156 enum machine_mode op_mode = GET_MODE (operands[0]);
3157 enum machine_mode cmp_mode;
3160 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3179 op0 = force_reg (mode, branch_cmp[1]);
3180 op1 = branch_cmp[0];
3184 op0 = force_reg (mode, branch_cmp[1]);
3185 op1 = branch_cmp[0];
3196 op0 = force_reg (mode, branch_cmp[1]);
3197 op1 = branch_cmp[0];
3201 op0 = force_reg (mode, branch_cmp[1]);
3202 op1 = branch_cmp[0];
3209 else if (cmp_code == NE)
3210 cmp_code = EQ, move_code = EQ;
3212 if (mode == SImode || mode == DImode)
3214 else if (mode == SFmode || mode == DFmode)
3219 cmp_reg = gen_reg_rtx (cmp_mode);
3220 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3221 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3223 emit_insn (gen_rtx_SET (op_mode, operands[0],
3224 gen_rtx_IF_THEN_ELSE (op_mode,
3225 gen_rtx (move_code, VOIDmode,
3227 CONST0_RTX (SImode)),
3228 operands[2], operands[3])));
3231 /* Emit the common code for conditional moves. OPERANDS is the array
3232 of operands passed to the conditional move defined_expand. */
3235 mips_gen_conditional_trap (operands)
3239 enum rtx_code cmp_code = GET_CODE (operands[0]);
3240 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3242 /* MIPS conditional trap machine instructions don't have GT or LE
3243 flavors, so we must invert the comparison and convert to LT and
3244 GE, respectively. */
3247 case GT: cmp_code = LT; break;
3248 case LE: cmp_code = GE; break;
3249 case GTU: cmp_code = LTU; break;
3250 case LEU: cmp_code = GEU; break;
3253 if (cmp_code == GET_CODE (operands[0]))
3255 op0 = force_reg (mode, branch_cmp[0]);
3256 op1 = branch_cmp[1];
3260 op0 = force_reg (mode, branch_cmp[1]);
3261 op1 = branch_cmp[0];
3263 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3264 op1 = force_reg (mode, op1);
3266 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3267 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3271 /* Write a loop to move a constant number of bytes.
3272 Generate load/stores as follows:
3278 temp<last> = src[MAX_MOVE_REGS-1];
3282 dest[MAX_MOVE_REGS-1] = temp<last>;
3283 src += MAX_MOVE_REGS;
3284 dest += MAX_MOVE_REGS;
3285 } while (src != final);
3287 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3288 registers are needed.
3290 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3291 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3292 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3294 #define MAX_MOVE_REGS 4
3295 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3298 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3299 rtx dest_reg; /* register holding destination address */
3300 rtx src_reg; /* register holding source address */
3301 unsigned int bytes; /* # bytes to move */
3302 int align; /* alignment */
3303 rtx orig_dest; /* original dest */
3304 rtx orig_src; /* original source for making a reg note */
3306 rtx dest_mem = replace_equiv_address (orig_dest, dest_reg);
3307 rtx src_mem = replace_equiv_address (orig_src, src_reg);
3308 rtx align_rtx = GEN_INT (align);
3314 if (bytes < (unsigned)2 * MAX_MOVE_BYTES)
3317 leftover = bytes % MAX_MOVE_BYTES;
3320 label = gen_label_rtx ();
3321 final_src = gen_reg_rtx (Pmode);
3322 bytes_rtx = GEN_INT (bytes);
3326 if (Pmode == DImode)
3328 emit_insn (gen_movdi (final_src, bytes_rtx));
3329 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3333 emit_insn (gen_movsi (final_src, bytes_rtx));
3334 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3339 if (Pmode == DImode)
3340 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3342 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3347 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3348 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3350 if (Pmode == DImode)
3352 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3353 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3354 emit_insn (gen_cmpdi (src_reg, final_src));
3358 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3359 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3360 emit_insn (gen_cmpsi (src_reg, final_src));
3363 emit_jump_insn (gen_bne (label));
3366 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3370 /* Use a library function to move some bytes. */
3373 block_move_call (dest_reg, src_reg, bytes_rtx)
3378 /* We want to pass the size as Pmode, which will normally be SImode
3379 but will be DImode if we are using 64 bit longs and pointers. */
3380 if (GET_MODE (bytes_rtx) != VOIDmode
3381 && GET_MODE (bytes_rtx) != (unsigned) Pmode)
3382 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3384 #ifdef TARGET_MEM_FUNCTIONS
3385 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
3386 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3387 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3388 TREE_UNSIGNED (sizetype)),
3389 TYPE_MODE (sizetype));
3391 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
3392 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3393 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3394 TREE_UNSIGNED (integer_type_node)),
3395 TYPE_MODE (integer_type_node));
3399 /* Expand string/block move operations.
3401 operands[0] is the pointer to the destination.
3402 operands[1] is the pointer to the source.
3403 operands[2] is the number of bytes to move.
3404 operands[3] is the alignment. */
3407 expand_block_move (operands)
3410 rtx bytes_rtx = operands[2];
3411 rtx align_rtx = operands[3];
3412 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3413 unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3414 unsigned int align = INTVAL (align_rtx);
3415 rtx orig_src = operands[1];
3416 rtx orig_dest = operands[0];
3420 if (constp && bytes == 0)
3423 if (align > (unsigned) UNITS_PER_WORD)
3424 align = UNITS_PER_WORD;
3426 /* Move the address into scratch registers. */
3427 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3428 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3431 block_move_call (dest_reg, src_reg, bytes_rtx);
3433 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
3434 && align == (unsigned) UNITS_PER_WORD)
3435 move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
3437 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
3438 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3440 replace_equiv_address (orig_src,
3442 bytes_rtx, align_rtx));
3444 else if (constp && align >= (unsigned) UNITS_PER_WORD && optimize)
3445 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3447 else if (constp && optimize)
3449 /* If the alignment is not word aligned, generate a test at
3450 runtime, to see whether things wound up aligned, and we
3451 can use the faster lw/sw instead ulw/usw. */
3453 rtx temp = gen_reg_rtx (Pmode);
3454 rtx aligned_label = gen_label_rtx ();
3455 rtx join_label = gen_label_rtx ();
3456 int leftover = bytes % MAX_MOVE_BYTES;
3460 if (Pmode == DImode)
3462 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3463 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3464 emit_insn (gen_cmpdi (temp, const0_rtx));
3468 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3469 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3470 emit_insn (gen_cmpsi (temp, const0_rtx));
3473 emit_jump_insn (gen_beq (aligned_label));
3475 /* Unaligned loop. */
3476 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3477 emit_jump_insn (gen_jump (join_label));
3481 emit_label (aligned_label);
3482 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3484 emit_label (join_label);
3486 /* Bytes at the end of the loop. */
3488 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3490 replace_equiv_address (orig_src,
3497 block_move_call (dest_reg, src_reg, bytes_rtx);
3500 /* Emit load/stores for a small constant block_move.
3502 operands[0] is the memory address of the destination.
3503 operands[1] is the memory address of the source.
3504 operands[2] is the number of bytes to move.
3505 operands[3] is the alignment.
3506 operands[4] is a temp register.
3507 operands[5] is a temp register.
3509 operands[3+num_regs] is the last temp register.
3511 The block move type can be one of the following:
3512 BLOCK_MOVE_NORMAL Do all of the block move.
3513 BLOCK_MOVE_NOT_LAST Do all but the last store.
3514 BLOCK_MOVE_LAST Do just the last store. */
3517 output_block_move (insn, operands, num_regs, move_type)
3521 enum block_move_type move_type;
3523 rtx dest_reg = XEXP (operands[0], 0);
3524 rtx src_reg = XEXP (operands[1], 0);
3525 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3526 int align = INTVAL (operands[3]);
3529 int use_lwl_lwr = 0;
3530 int last_operand = num_regs + 4;
3536 const char *load; /* load insn without nop */
3537 const char *load_nop; /* load insn with trailing nop */
3538 const char *store; /* store insn */
3539 const char *final; /* if last_store used: NULL or swr */
3540 const char *last_store; /* last store instruction */
3541 int offset; /* current offset */
3542 enum machine_mode mode; /* mode to use on (MEM) */
3545 /* ??? Detect a bug in GCC, where it can give us a register
3546 the same as one of the addressing registers and reduce
3547 the number of registers available. */
3548 for (i = 4; i < last_operand && safe_regs < (int) ARRAY_SIZE (xoperands); i++)
3549 if (! reg_mentioned_p (operands[i], operands[0])
3550 && ! reg_mentioned_p (operands[i], operands[1]))
3551 xoperands[safe_regs++] = operands[i];
3553 if (safe_regs < last_operand)
3555 xoperands[0] = operands[0];
3556 xoperands[1] = operands[1];
3557 xoperands[2] = operands[2];
3558 xoperands[3] = operands[3];
3559 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3562 /* If we are given global or static addresses, and we would be
3563 emitting a few instructions, try to save time by using a
3564 temporary register for the pointer. */
3565 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3566 an ldl/ldr instruction pair. We play it safe, and always move
3567 constant addresses into registers when generating N32/N64 code, just
3568 in case we might emit an unaligned load instruction. */
3569 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3570 || mips_abi == ABI_MEABI
3571 || mips_abi == ABI_N32
3572 || mips_abi == ABI_64))
3574 if (CONSTANT_P (src_reg))
3577 mips_count_memory_refs (operands[1], 1);
3579 src_reg = operands[3 + num_regs--];
3580 if (move_type != BLOCK_MOVE_LAST)
3582 xoperands[1] = operands[1];
3583 xoperands[0] = src_reg;
3584 if (Pmode == DImode)
3585 output_asm_insn ("dla\t%0,%1", xoperands);
3587 output_asm_insn ("la\t%0,%1", xoperands);
3591 if (CONSTANT_P (dest_reg))
3594 mips_count_memory_refs (operands[0], 1);
3596 dest_reg = operands[3 + num_regs--];
3597 if (move_type != BLOCK_MOVE_LAST)
3599 xoperands[1] = operands[0];
3600 xoperands[0] = dest_reg;
3601 if (Pmode == DImode)
3602 output_asm_insn ("dla\t%0,%1", xoperands);
3604 output_asm_insn ("la\t%0,%1", xoperands);
3609 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3610 are not offsettable, however, offsettable_address_p says they are
3611 offsettable. I think this is a bug in offsettable_address_p.
3612 For expediency, we fix this by just loading the address into a register
3613 if we happen to get one. */
3615 if (GET_CODE (src_reg) == LO_SUM)
3617 src_reg = operands[3 + num_regs--];
3618 if (move_type != BLOCK_MOVE_LAST)
3620 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3621 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3622 xoperands[0] = src_reg;
3623 if (Pmode == DImode)
3624 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3626 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3630 if (GET_CODE (dest_reg) == LO_SUM)
3632 dest_reg = operands[3 + num_regs--];
3633 if (move_type != BLOCK_MOVE_LAST)
3635 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3636 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3637 xoperands[0] = dest_reg;
3638 if (Pmode == DImode)
3639 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3641 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3645 if (num_regs > (int) ARRAY_SIZE (load_store))
3646 num_regs = ARRAY_SIZE (load_store);
3648 else if (num_regs < 1)
3649 abort_with_insn (insn,
3650 "cannot do block move, not enough scratch registers");
3654 load_store[num].offset = offset;
3656 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3658 load_store[num].load = "ld\t%0,%1";
3659 load_store[num].load_nop = "ld\t%0,%1%#";
3660 load_store[num].store = "sd\t%0,%1";
3661 load_store[num].last_store = "sd\t%0,%1";
3662 load_store[num].final = 0;
3663 load_store[num].mode = DImode;
3668 /* ??? Fails because of a MIPS assembler bug? */
3669 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3671 if (BYTES_BIG_ENDIAN)
3673 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3674 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3675 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3676 load_store[num].last_store = "sdr\t%0,%2";
3677 load_store[num].final = "sdl\t%0,%1";
3681 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3682 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3683 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3684 load_store[num].last_store = "sdr\t%0,%1";
3685 load_store[num].final = "sdl\t%0,%2";
3688 load_store[num].mode = DImode;
3694 else if (bytes >= 4 && align >= 4)
3696 load_store[num].load = "lw\t%0,%1";
3697 load_store[num].load_nop = "lw\t%0,%1%#";
3698 load_store[num].store = "sw\t%0,%1";
3699 load_store[num].last_store = "sw\t%0,%1";
3700 load_store[num].final = 0;
3701 load_store[num].mode = SImode;
3706 else if (bytes >= 4 && ! TARGET_MIPS16)
3708 if (BYTES_BIG_ENDIAN)
3710 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3711 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3712 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3713 load_store[num].last_store = "swr\t%0,%2";
3714 load_store[num].final = "swl\t%0,%1";
3718 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3719 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3720 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3721 load_store[num].last_store = "swr\t%0,%1";
3722 load_store[num].final = "swl\t%0,%2";
3725 load_store[num].mode = SImode;
3731 else if (bytes >= 2 && align >= 2)
3733 load_store[num].load = "lh\t%0,%1";
3734 load_store[num].load_nop = "lh\t%0,%1%#";
3735 load_store[num].store = "sh\t%0,%1";
3736 load_store[num].last_store = "sh\t%0,%1";
3737 load_store[num].final = 0;
3738 load_store[num].mode = HImode;
3744 load_store[num].load = "lb\t%0,%1";
3745 load_store[num].load_nop = "lb\t%0,%1%#";
3746 load_store[num].store = "sb\t%0,%1";
3747 load_store[num].last_store = "sb\t%0,%1";
3748 load_store[num].final = 0;
3749 load_store[num].mode = QImode;
3754 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3756 dslots_load_total++;
3757 dslots_load_filled++;
3759 if (CONSTANT_P (src_reg))
3760 mips_count_memory_refs (src_reg, 1);
3762 if (CONSTANT_P (dest_reg))
3763 mips_count_memory_refs (dest_reg, 1);
3766 /* Emit load/stores now if we have run out of registers or are
3767 at the end of the move. */
3769 if (++num == num_regs || bytes == 0)
3771 /* If only load/store, we need a NOP after the load. */
3774 load_store[0].load = load_store[0].load_nop;
3775 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3776 dslots_load_filled--;
3779 if (move_type != BLOCK_MOVE_LAST)
3781 for (i = 0; i < num; i++)
3785 if (!operands[i + 4])
3788 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
3789 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
3790 REGNO (operands[i + 4]));
3792 offset = load_store[i].offset;
3793 xoperands[0] = operands[i + 4];
3794 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3795 plus_constant (src_reg, offset));
3800 = GET_MODE_SIZE (load_store[i].mode) - 1;
3802 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3803 plus_constant (src_reg,
3808 output_asm_insn (load_store[i].load, xoperands);
3812 for (i = 0; i < num; i++)
3814 int last_p = (i == num-1 && bytes == 0);
3815 int offset = load_store[i].offset;
3817 xoperands[0] = operands[i + 4];
3818 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3819 plus_constant (dest_reg, offset));
3824 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3825 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3826 plus_constant (dest_reg,
3831 if (move_type == BLOCK_MOVE_NORMAL)
3832 output_asm_insn (load_store[i].store, xoperands);
3834 else if (move_type == BLOCK_MOVE_NOT_LAST)
3837 output_asm_insn (load_store[i].store, xoperands);
3839 else if (load_store[i].final != 0)
3840 output_asm_insn (load_store[i].final, xoperands);
3844 output_asm_insn (load_store[i].last_store, xoperands);
3847 num = 0; /* reset load_store */
3855 /* Argument support functions. */
3857 /* Initialize CUMULATIVE_ARGS for a function. */
3860 init_cumulative_args (cum, fntype, libname)
3861 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3862 tree fntype; /* tree ptr for function decl */
3863 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
3865 static CUMULATIVE_ARGS zero_cum;
3866 tree param, next_param;
3868 if (TARGET_DEBUG_E_MODE)
3871 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3874 fputc ('\n', stderr);
3878 tree ret_type = TREE_TYPE (fntype);
3879 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3880 tree_code_name[(int)TREE_CODE (fntype)],
3881 tree_code_name[(int)TREE_CODE (ret_type)]);
3886 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3888 /* Determine if this function has variable arguments. This is
3889 indicated by the last argument being 'void_type_mode' if there
3890 are no variable arguments. The standard MIPS calling sequence
3891 passes all arguments in the general purpose registers in this case. */
3893 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3894 param != 0; param = next_param)
3896 next_param = TREE_CHAIN (param);
3897 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3898 cum->gp_reg_found = 1;
3902 /* Advance the argument to the next argument position. */
3905 function_arg_advance (cum, mode, type, named)
3906 CUMULATIVE_ARGS *cum; /* current arg information */
3907 enum machine_mode mode; /* current arg mode */
3908 tree type; /* type of the argument or 0 if lib support */
3909 int named; /* whether or not the argument was named */
3911 if (TARGET_DEBUG_E_MODE)
3914 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3915 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3916 GET_MODE_NAME (mode));
3917 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
3918 fprintf (stderr, ", %d )\n\n", named);
3928 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3929 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3932 cum->gp_reg_found = 1;
3933 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3938 cum->gp_reg_found = 1;
3939 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3944 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3945 cum->fp_arg_words++;
3948 if (! cum->gp_reg_found && cum->arg_number <= 2)
3949 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
3953 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3954 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3956 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3957 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3958 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
3963 cum->gp_reg_found = 1;
3964 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3970 cum->gp_reg_found = 1;
3976 /* Return an RTL expression containing the register for the given mode,
3977 or 0 if the argument is to be passed on the stack. */
3980 function_arg (cum, mode, type, named)
3981 CUMULATIVE_ARGS *cum; /* current arg information */
3982 enum machine_mode mode; /* current arg mode */
3983 tree type; /* type of the argument or 0 if lib support */
3984 int named; /* != 0 for normal args, == 0 for ... args */
3989 unsigned int *arg_words = &cum->arg_words;
3990 int struct_p = (type != 0
3991 && (TREE_CODE (type) == RECORD_TYPE
3992 || TREE_CODE (type) == UNION_TYPE
3993 || TREE_CODE (type) == QUAL_UNION_TYPE));
3995 if (TARGET_DEBUG_E_MODE)
3998 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3999 cum->gp_reg_found, cum->arg_number, cum->arg_words,
4000 GET_MODE_NAME (mode));
4001 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
4002 fprintf (stderr, ", %d ) = ", named);
4006 cum->last_arg_fp = 0;
4010 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
4012 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
4013 regbase = GP_ARG_FIRST;
4016 regbase = FP_ARG_FIRST;
4018 /* If the first arg was a float in a floating point register,
4019 then set bias to align this float arg properly. */
4020 if (cum->arg_words == 1)
4024 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
4027 cum->fp_arg_words += cum->fp_arg_words & 1;
4028 cum->last_arg_fp = 1;
4029 arg_words = &cum->fp_arg_words;
4030 regbase = FP_ARG_FIRST;
4032 /* The MIPS eabi says only structures containing doubles get passed in a
4033 fp register, so force a structure containing a float to be passed in
4034 the integer registers. */
4035 else if (mips_abi == ABI_MEABI && struct_p)
4036 regbase = GP_ARG_FIRST;
4038 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
4044 if (mips_abi == ABI_EABI
4045 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
4046 cum->fp_arg_words += cum->fp_arg_words & 1;
4048 cum->arg_words += cum->arg_words & 1;
4051 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
4052 regbase = ((cum->gp_reg_found
4053 || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
4054 || cum->arg_number >= 2)
4055 ? GP_ARG_FIRST : FP_ARG_FIRST);
4056 else if (mips_abi == ABI_EABI
4057 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
4059 cum->last_arg_fp = 1;
4060 arg_words = &cum->fp_arg_words;
4061 regbase = FP_ARG_FIRST;
4064 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
4065 ? GP_ARG_FIRST : FP_ARG_FIRST);
4069 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4070 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4073 /* Drops through. */
4075 if (type != NULL_TREE && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
4076 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4077 cum->arg_words += (cum->arg_words & 1);
4078 regbase = GP_ARG_FIRST;
4085 regbase = GP_ARG_FIRST;
4091 cum->arg_words += (cum->arg_words & 1);
4092 regbase = GP_ARG_FIRST;
4095 if (*arg_words >= (unsigned) MAX_ARGS_IN_REGISTERS)
4097 if (TARGET_DEBUG_E_MODE)
4098 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
4107 if (! type || TREE_CODE (type) != RECORD_TYPE
4108 || mips_abi == ABI_32 || mips_abi == ABI_EABI
4109 || mips_abi == ABI_O64 || mips_abi == ABI_MEABI
4111 || ! TYPE_SIZE_UNIT (type)
4112 || ! host_integerp (TYPE_SIZE_UNIT (type), 1))
4115 unsigned int arg_reg = (regbase + *arg_words + bias);
4116 ret = gen_rtx_REG (mode, arg_reg);
4117 if (mips_abi == ABI_MEABI
4118 && regbase == FP_ARG_FIRST
4119 && ! cum->prototype)
4121 /* To make K&R varargs work we need to pass floating
4122 point arguments in both integer and FP registers. */
4123 ret = gen_rtx_PARALLEL (mode,
4125 gen_rtx_EXPR_LIST (VOIDmode,
4127 arg_reg + GP_ARG_FIRST - FP_ARG_FIRST),
4128 const0_rtx), gen_rtx_EXPR_LIST (VOIDmode, ret, const0_rtx)));
4133 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4134 structure contains a double in its entirety, then that 64 bit
4135 chunk is passed in a floating point register. */
4138 /* First check to see if there is any such field. */
4139 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4140 if (TREE_CODE (field) == FIELD_DECL
4141 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4142 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4143 && host_integerp (bit_position (field), 0)
4144 && int_bit_position (field) % BITS_PER_WORD == 0)
4147 /* If the whole struct fits a DFmode register,
4148 we don't need the PARALLEL. */
4149 if (! field || mode == DFmode)
4150 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
4153 /* Now handle the special case by returning a PARALLEL
4154 indicating where each 64 bit chunk goes. */
4155 unsigned int chunks;
4156 HOST_WIDE_INT bitpos;
4160 /* ??? If this is a packed structure, then the last hunk won't
4164 = tree_low_cst (TYPE_SIZE_UNIT (type), 1) / UNITS_PER_WORD;
4165 if (chunks + *arg_words + bias > (unsigned) MAX_ARGS_IN_REGISTERS)
4166 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
4168 /* assign_parms checks the mode of ENTRY_PARM, so we must
4169 use the actual mode here. */
4170 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
4173 regno = regbase + *arg_words + bias;
4174 field = TYPE_FIELDS (type);
4175 for (i = 0; i < chunks; i++)
4179 for (; field; field = TREE_CHAIN (field))
4180 if (TREE_CODE (field) == FIELD_DECL
4181 && int_bit_position (field) >= bitpos)
4185 && int_bit_position (field) == bitpos
4186 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4187 && !TARGET_SOFT_FLOAT
4188 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4189 reg = gen_rtx_REG (DFmode,
4190 regno + FP_ARG_FIRST - GP_ARG_FIRST);
4192 reg = gen_rtx_REG (word_mode, regno);
4195 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4196 GEN_INT (bitpos / BITS_PER_UNIT));
4204 if (TARGET_DEBUG_E_MODE)
4205 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
4206 struct_p ? ", [struct]" : "");
4208 /* The following is a hack in order to pass 1 byte structures
4209 the same way that the MIPS compiler does (namely by passing
4210 the structure in the high byte or half word of the register).
4211 This also makes varargs work. If we have such a structure,
4212 we save the adjustment RTL, and the call define expands will
4213 emit them. For the VOIDmode argument (argument after the
4214 last real argument), pass back a parallel vector holding each
4215 of the adjustments. */
4217 /* ??? function_arg can be called more than once for each argument.
4218 As a result, we compute more adjustments than we need here.
4219 See the CUMULATIVE_ARGS definition in mips.h. */
4221 /* ??? This scheme requires everything smaller than the word size to
4222 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4223 that would mean every int needs to be shifted left, which is very
4224 inefficient. Let's not carry this compatibility to the 64 bit
4225 calling convention for now. */
4227 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
4229 && mips_abi != ABI_EABI
4230 && mips_abi != ABI_MEABI)
4232 rtx amount = GEN_INT (BITS_PER_WORD
4233 - int_size_in_bytes (type) * BITS_PER_UNIT);
4234 rtx reg = gen_rtx_REG (word_mode, regbase + *arg_words + bias);
4237 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
4239 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
4243 /* We will be called with a mode of VOIDmode after the last argument
4244 has been seen. Whatever we return will be passed to the call
4245 insn. If we need any shifts for small structures, return them in
4246 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4247 mode. Otherwise, if we have need a mips16 fp_code, return a REG
4248 with the code stored as the mode. */
4249 if (mode == VOIDmode)
4251 if (cum->num_adjusts > 0)
4252 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
4253 gen_rtvec_v (cum->num_adjusts, cum->adjust));
4254 else if (TARGET_MIPS16 && cum->fp_code != 0)
4255 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
4262 function_arg_partial_nregs (cum, mode, type, named)
4263 CUMULATIVE_ARGS *cum; /* current arg information */
4264 enum machine_mode mode; /* current arg mode */
4265 tree type; /* type of the argument or 0 if lib support */
4266 int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
4268 if ((mode == BLKmode
4269 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4270 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4271 && cum->arg_words < (unsigned) MAX_ARGS_IN_REGISTERS
4272 && mips_abi != ABI_EABI)
4275 if (mode == BLKmode)
4276 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
4279 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4281 if (words + cum->arg_words <= (unsigned) MAX_ARGS_IN_REGISTERS)
4282 return 0; /* structure fits in registers */
4284 if (TARGET_DEBUG_E_MODE)
4285 fprintf (stderr, "function_arg_partial_nregs = %d\n",
4286 MAX_ARGS_IN_REGISTERS - cum->arg_words);
4288 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
4291 else if (mode == DImode
4292 && cum->arg_words == MAX_ARGS_IN_REGISTERS - (unsigned)1
4293 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4295 if (TARGET_DEBUG_E_MODE)
4296 fprintf (stderr, "function_arg_partial_nregs = 1\n");
4304 /* Create the va_list data type.
4305 We keep 3 pointers, and two offsets.
4306 Two pointers are to the overflow area, which starts at the CFA.
4307 One of these is constant, for addressing into the GPR save area below it.
4308 The other is advanced up the stack through the overflow region.
4309 The third pointer is to the GPR save area. Since the FPR save area
4310 is just below it, we can address FPR slots off this pointer.
4311 We also keep two one-byte offsets, which are to be subtracted from the
4312 constant pointers to yield addresses in the GPR and FPR save areas.
4313 These are downcounted as float or non-float arguments are used,
4314 and when they get to zero, the argument must be obtained from the
4316 If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT, then no FPR save area exists,
4317 and a single pointer is enough. It's started at the GPR save area,
4318 and is advanced, period.
4319 Note that the GPR save area is not constant size, due to optimization
4320 in the prologue. Hence, we can't use a design with two pointers
4321 and two offsets, although we could have designed this with two pointers
4322 and three offsets. */
4326 mips_build_va_list ()
4328 if (mips_abi == ABI_EABI && !TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4330 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, record;
4332 record = make_node (RECORD_TYPE);
4334 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4336 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4338 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4340 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4341 unsigned_char_type_node);
4342 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4343 unsigned_char_type_node);
4346 DECL_FIELD_CONTEXT (f_ovfl) = record;
4347 DECL_FIELD_CONTEXT (f_gtop) = record;
4348 DECL_FIELD_CONTEXT (f_ftop) = record;
4349 DECL_FIELD_CONTEXT (f_goff) = record;
4350 DECL_FIELD_CONTEXT (f_foff) = record;
4352 TYPE_FIELDS (record) = f_ovfl;
4353 TREE_CHAIN (f_ovfl) = f_gtop;
4354 TREE_CHAIN (f_gtop) = f_ftop;
4355 TREE_CHAIN (f_ftop) = f_goff;
4356 TREE_CHAIN (f_goff) = f_foff;
4358 layout_type (record);
4362 return ptr_type_node;
4365 /* Implement va_start. stdarg_p is 0 if implementing
4366 __builtin_varargs_va_start, 1 if implementing __builtin_stdarg_va_start.
4367 Note that this routine isn't called when compiling e.g. "_vfprintf_r".
4368 (It doesn't have "...", so it inherits the pointers of its caller.) */
4371 mips_va_start (stdarg_p, valist, nextarg)
4379 /* Find out how many non-float named formals */
4380 int_arg_words = current_function_args_info.arg_words;
4382 if (mips_abi == ABI_EABI)
4384 int gpr_save_area_size;
4385 /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
4386 if (int_arg_words < 8 )
4387 /* Adjust for the prologue's economy measure */
4388 gpr_save_area_size = (8 - int_arg_words) * UNITS_PER_WORD;
4390 gpr_save_area_size = 0;
4392 if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4394 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4395 tree ovfl, gtop, ftop, goff, foff;
4397 int float_formals, fpr_offset, size_excess, floats_passed_in_regs;
4398 int fpr_save_offset;
4400 float_formals = current_function_args_info.fp_arg_words;
4401 /* If mips2, the number of formals is half the reported # of words */
4404 floats_passed_in_regs = (TARGET_64BIT ? 8 : 4);
4406 f_ovfl = TYPE_FIELDS (va_list_type_node);
4407 f_gtop = TREE_CHAIN (f_ovfl);
4408 f_ftop = TREE_CHAIN (f_gtop);
4409 f_goff = TREE_CHAIN (f_ftop);
4410 f_foff = TREE_CHAIN (f_goff);
4412 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4413 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4414 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4415 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4416 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4418 /* Emit code setting a pointer into the overflow (shared-stack) area.
4419 If there were more than 8 non-float formals, or more than 8
4420 float formals, then this pointer isn't to the base of the area.
4421 In that case, it must point to where the first vararg is. */
4423 if (float_formals > floats_passed_in_regs)
4424 size_excess += (float_formals-floats_passed_in_regs) * 8;
4425 if (int_arg_words > 8)
4426 size_excess += (int_arg_words-8) * UNITS_PER_WORD;
4428 /* FIXME: for mips2, the above size_excess can be wrong. Because the
4429 overflow stack holds mixed size items, there can be alignments,
4430 so that an 8 byte double following a 4 byte int will be on an
4431 8 byte boundary. This means that the above calculation should
4432 take into account the exact sequence of floats and non-floats
4433 which make up the excess. That calculation should be rolled
4434 into the code which sets the current_function_args_info struct.
4435 The above then reduces to a fetch from that struct. */
4438 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4440 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4441 build_int_2 (size_excess, 0));
4442 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4443 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4445 /* Emit code setting a ptr to the base of the overflow area. */
4446 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4447 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4448 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4450 /* Emit code setting a pointer to the GPR save area.
4451 More precisely, a pointer to off-the-end of the FPR save area.
4452 If mips4, this is gpr_save_area_size below the overflow area.
4453 If mips2, also round down to an 8-byte boundary, since the FPR
4454 save area is 8-byte aligned, and GPR is 4-byte-aligned.
4455 Therefore there can be a 4-byte gap between the save areas. */
4456 gprv = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4457 fpr_save_offset = gpr_save_area_size;
4460 if (fpr_save_offset & 7)
4461 fpr_save_offset += 4;
4463 if (fpr_save_offset)
4464 gprv = build (PLUS_EXPR, TREE_TYPE (ftop), gprv,
4465 build_int_2 (-fpr_save_offset,-1));
4466 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, gprv);
4467 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4469 /* Emit code initting an offset to the size of the GPR save area */
4470 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4471 build_int_2 (gpr_save_area_size,0));
4472 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4474 /* Emit code initting an offset from ftop to the first float
4475 vararg. This varies in size, since any float
4476 varargs are put in the FPR save area after the formals.
4477 Note it's 8 bytes/formal regardless of TARGET_64BIT.
4478 However, mips2 stores 4 GPRs, mips4 stores 8 GPRs.
4479 If there are 8 or more float formals, init to zero.
4480 (In fact, the formals aren't stored in the bottom of the
4481 FPR save area: they are elsewhere, and the size of the FPR
4482 save area is economized by the prologue. But this code doesn't
4483 care. This design is unaffected by that fact.) */
4484 if (float_formals >= floats_passed_in_regs)
4487 fpr_offset = (floats_passed_in_regs - float_formals) * 8;
4488 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4489 build_int_2 (fpr_offset,0));
4490 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4494 /* TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT */
4496 /* Everything is in the GPR save area, or in the overflow
4497 area which is contiguous with it. */
4499 int offset = -gpr_save_area_size;
4500 if (gpr_save_area_size == 0)
4501 offset = (stdarg_p ? 0 : -UNITS_PER_WORD);
4502 nextarg = plus_constant (nextarg, offset);
4503 std_expand_builtin_va_start (1, valist, nextarg);
4515 /* ??? This had been conditional on
4516 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4517 and both iris5.h and iris6.h define _MIPS_SIM. */
4518 if (mips_abi == ABI_N32 || mips_abi == ABI_64)
4519 ofs = (int_arg_words >= 8 ? -UNITS_PER_WORD : 0);
4520 else if (mips_abi == ABI_MEABI)
4521 ofs = (int_arg_words >= 8 ? -UNITS_PER_WORD : 0);
4523 ofs = -UNITS_PER_WORD;
4526 nextarg = plus_constant (nextarg, ofs);
4527 std_expand_builtin_va_start (1, valist, nextarg);
4531 /* Implement va_arg. */
4534 mips_va_arg (valist, type)
4537 HOST_WIDE_INT size, rsize;
4541 size = int_size_in_bytes (type);
4542 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4544 if (mips_abi == ABI_EABI)
4547 rtx r, lab_over = NULL_RTX, lab_false;
4548 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4549 tree ovfl, gtop, ftop, goff, foff;
4552 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4555 size = POINTER_SIZE / BITS_PER_UNIT;
4556 rsize = UNITS_PER_WORD;
4559 addr_rtx = gen_reg_rtx (Pmode);
4561 if (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT)
4563 /* Case of all args in a merged stack. No need to check bounds,
4564 just advance valist along the stack. */
4569 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4571 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4572 build_int_2 (2*UNITS_PER_WORD - 1, 0));
4573 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4574 build_int_2 (-2*UNITS_PER_WORD, -1));
4575 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4576 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4579 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4581 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4583 emit_move_insn (addr_rtx, r);
4585 /* flush the POSTINCREMENT */
4590 r = gen_rtx_MEM (Pmode, addr_rtx);
4591 set_mem_alias_set (r, get_varargs_alias_set ());
4592 emit_move_insn (addr_rtx, r);
4596 if (BYTES_BIG_ENDIAN && rsize != size)
4597 addr_rtx = plus_constant (addr_rtx, rsize - size);
4602 /* Not a simple merged stack. Need ptrs and indexes left by va_start. */
4604 f_ovfl = TYPE_FIELDS (va_list_type_node);
4605 f_gtop = TREE_CHAIN (f_ovfl);
4606 f_ftop = TREE_CHAIN (f_gtop);
4607 f_goff = TREE_CHAIN (f_ftop);
4608 f_foff = TREE_CHAIN (f_goff);
4610 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4611 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4612 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4613 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4614 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4616 lab_false = gen_label_rtx ();
4617 lab_over = gen_label_rtx ();
4619 if (TREE_CODE (type) == REAL_TYPE)
4622 /* Emit code to branch if foff == 0. */
4623 r = expand_expr (foff, NULL_RTX, TYPE_MODE (TREE_TYPE (foff)),
4625 emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
4628 /* Emit code for addr_rtx = ftop - foff */
4629 t = build (MINUS_EXPR, TREE_TYPE (ftop), ftop, foff );
4630 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4632 emit_move_insn (addr_rtx, r);
4634 /* Emit code for foff-=8.
4635 Advances the offset up FPR save area by one double */
4636 t = build (MINUS_EXPR, TREE_TYPE (foff), foff, build_int_2 (8, 0));
4637 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff, t);
4638 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4641 emit_jump (lab_over);
4643 emit_label (lab_false);
4647 /* For mips2, the overflow area contains mixed size items.
4648 If a 4-byte int is followed by an 8-byte float, then
4649 natural alignment causes a 4 byte gap.
4650 So, dynamically adjust ovfl up to a multiple of 8. */
4651 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), ovfl,
4652 build_int_2 (7, 0));
4653 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, t);
4654 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4655 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4658 /* Emit code for addr_rtx = the ovfl pointer into overflow area.
4659 Regardless of mips2, postincrement the ovfl pointer by 8. */
4660 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4662 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4664 emit_move_insn (addr_rtx, r);
4667 emit_label (lab_over);
4676 && TREE_CODE (type) == INTEGER_TYPE
4677 && TYPE_PRECISION (type) == 64)
4679 /* In mips2, int takes 32 bits of the GPR save area, but
4680 longlong takes an aligned 64 bits. So, emit code
4681 to zero the low order bits of goff, thus aligning
4682 the later calculation of (gtop-goff) upwards. */
4683 t = build (BIT_AND_EXPR, TREE_TYPE (goff), goff,
4684 build_int_2 (-8, -1));
4685 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4686 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4689 /* Emit code to branch if goff == 0. */
4690 r = expand_expr (goff, NULL_RTX, TYPE_MODE (TREE_TYPE (goff)),
4692 emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
4695 /* Emit code for addr_rtx = gtop - goff. */
4696 t = build (MINUS_EXPR, TREE_TYPE (gtop), gtop, goff);
4697 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4699 emit_move_insn (addr_rtx, r);
4701 /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
4702 if (! TARGET_64BIT && TYPE_PRECISION (type) == 64)
4705 step_size = UNITS_PER_WORD;
4707 /* Emit code for goff = goff - step_size.
4708 Advances the offset up GPR save area over the item. */
4709 t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
4710 build_int_2 (step_size, 0));
4711 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4712 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4715 emit_jump (lab_over);
4717 emit_label (lab_false);
4719 /* Emit code for addr_rtx -> overflow area, postinc by step_size */
4720 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4721 size_int (step_size));
4722 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4724 emit_move_insn (addr_rtx, r);
4727 emit_label (lab_over);
4731 r = gen_rtx_MEM (Pmode, addr_rtx);
4732 set_mem_alias_set (r, get_varargs_alias_set ());
4733 emit_move_insn (addr_rtx, r);
4737 if (BYTES_BIG_ENDIAN && rsize != size)
4738 addr_rtx = plus_constant (addr_rtx, rsize - size);
4748 /* ??? The original va-mips.h did always align, despite the fact
4749 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4750 increment mechanism. */
4754 else if (TYPE_ALIGN (type) > 32)
4759 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4760 build_int_2 (align - 1, 0));
4761 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4762 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4763 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4765 /* Everything past the alignment is standard. */
4766 return std_expand_builtin_va_arg (valist, type);
4770 /* Abort after printing out a specific insn. */
4773 abort_with_insn (insn, reason)
4782 /* Set up the threshold for data to go into the small data area, instead
4783 of the normal data area, and detect any conflicts in the switches. */
4788 register int i, start;
4790 register enum machine_mode mode;
4791 register enum processor_type mips_cpu;
4793 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4795 if (mips_section_threshold <= 0)
4796 target_flags &= ~MASK_GPOPT;
4798 target_flags |= MASK_GPOPT;
4800 /* If both single-float and soft-float are set, then clear the one that
4801 was set by TARGET_DEFAULT, leaving the one that was set by the
4802 user. We assume here that the specs prevent both being set by the
4804 #ifdef TARGET_DEFAULT
4805 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4806 target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
4809 /* Get the architectural level. */
4810 if (mips_isa_string == 0)
4811 mips_isa = MIPS_ISA_DEFAULT;
4813 else if (mips_isa_string != 0
4814 && mips_arch_string != 0)
4815 warning ("The -march option is incompatible to -mipsN and therefore ignored.");
4817 else if (ISDIGIT (*mips_isa_string))
4819 mips_isa = atoi (mips_isa_string);
4822 /* -mno-mips16 overrides -mips16. */
4823 if (mips_no_mips16_string == NULL)
4825 target_flags |= MASK_MIPS16;
4829 mips_isa = MIPS_ISA_DEFAULT;
4833 mips_isa = MIPS_ISA_DEFAULT;
4836 else if (mips_isa < 1
4841 error ("-mips%d not supported", mips_isa);
4848 error ("bad value (%s) for -mips switch", mips_isa_string);
4852 #ifdef MIPS_ABI_DEFAULT
4853 /* Get the ABI to use. */
4854 if (mips_abi_string == (char *) 0)
4855 mips_abi = MIPS_ABI_DEFAULT;
4856 else if (! strcmp (mips_abi_string, "32"))
4858 else if (! strcmp (mips_abi_string, "o64"))
4860 else if (! strcmp (mips_abi_string, "n32"))
4862 else if (! strcmp (mips_abi_string, "64"))
4864 else if (! strcmp (mips_abi_string, "eabi"))
4865 mips_abi = ABI_EABI;
4866 else if (! strcmp (mips_abi_string, "meabi"))
4867 mips_abi = ABI_MEABI;
4869 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4871 /* A specified ISA defaults the ABI if it was not specified. */
4872 if (mips_abi_string == 0 && mips_isa_string
4873 && mips_abi != ABI_EABI
4874 && mips_abi != ABI_O64
4875 && mips_abi != ABI_MEABI)
4881 if (! ISA_HAS_64BIT_REGS)
4888 #ifdef MIPS_CPU_STRING_DEFAULT
4889 /* A specified ABI defaults the ISA if it was not specified. */
4890 else if (mips_isa_string == 0 && mips_abi_string
4891 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4893 if (mips_abi == ABI_32)
4895 else if (mips_abi == ABI_N32)
4902 /* If both ABI and ISA were specified, check for conflicts. */
4903 else if (mips_isa_string && mips_abi_string)
4905 if (! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64
4906 || mips_abi == ABI_O64))
4907 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4910 /* Override TARGET_DEFAULT if necessary. */
4911 if (mips_abi == ABI_32)
4912 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4914 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4915 then set the type sizes. In the EABI in 64 bit mode, longs and
4916 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4917 if (mips_explicit_type_size_string == NULL
4918 && ((mips_abi == ABI_EABI && TARGET_64BIT)
4919 || mips_abi == ABI_64))
4920 target_flags |= MASK_LONG64;
4923 if (mips_abi_string)
4924 error ("this target does not support the -mabi switch");
4927 #ifdef MIPS_CPU_STRING_DEFAULT
4928 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4929 greater than that supported by the default processor, then the user gets
4930 an error. Normally, the compiler will just default to the base level cpu
4931 for the indicated isa. */
4932 if (mips_arch_string == 0)
4933 mips_arch_string = MIPS_CPU_STRING_DEFAULT;
4934 if (mips_tune_string == 0)
4935 mips_tune_string = MIPS_CPU_STRING_DEFAULT;
4938 /* Identify the processor type. */
4940 if (mips_cpu_string != 0)
4942 mips_cpu = mips_parse_cpu (mips_cpu_string);
4943 if (mips_cpu == PROCESSOR_DEFAULT)
4945 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
4946 mips_cpu_string = "default";
4948 mips_arch = mips_cpu;
4949 mips_tune = mips_cpu;
4952 if (mips_arch_string == 0
4953 || ! strcmp (mips_arch_string, "default")
4954 || ! strcmp (mips_arch_string, "DEFAULT"))
4959 mips_arch_string = "3000";
4960 mips_arch = PROCESSOR_R3000;
4963 mips_arch_string = "6000";
4964 mips_arch = PROCESSOR_R6000;
4967 mips_arch_string = "4000";
4968 mips_arch = PROCESSOR_R4000;
4971 mips_arch_string = "8000";
4972 mips_arch = PROCESSOR_R8000;
4975 mips_arch_string = "4kc";
4976 mips_arch = PROCESSOR_R4KC;
4979 mips_arch_string = "5kc";
4980 mips_arch = PROCESSOR_R5KC;
4986 mips_arch = mips_parse_cpu (mips_arch_string);
4987 if (mips_arch == PROCESSOR_DEFAULT)
4989 error ("bad value (%s) for -march= switch", mips_arch_string);
4990 mips_arch_string = "default";
4993 if (mips_tune_string == 0
4994 || ! strcmp (mips_tune_string, "default")
4995 || ! strcmp (mips_tune_string, "DEFAULT"))
4997 if (mips_arch != PROCESSOR_DEFAULT)
4998 mips_tune = mips_arch;
5003 mips_tune_string = "3000";
5004 mips_tune = PROCESSOR_R3000;
5007 mips_tune_string = "6000";
5008 mips_tune = PROCESSOR_R6000;
5011 mips_tune_string = "4000";
5012 mips_tune = PROCESSOR_R4000;
5015 mips_tune_string = "8000";
5016 mips_tune = PROCESSOR_R8000;
5019 mips_tune_string = "4kc";
5020 mips_tune = PROCESSOR_R4KC;
5023 mips_tune_string = "5kc";
5024 mips_tune = PROCESSOR_R5KC;
5031 mips_tune = mips_parse_cpu (mips_tune_string);
5032 if (mips_tune == PROCESSOR_DEFAULT)
5034 error ("bad value (%s) for -mtune= switch", mips_tune_string);
5035 mips_tune_string = "default";
5039 /* make sure sizes of ints/longs/etc. are ok */
5040 if (! ISA_HAS_64BIT_REGS)
5044 error ("-mips%d does not support 64 bit fp registers", mips_isa);
5045 target_flags &= ~ MASK_FLOAT64;
5048 else if (TARGET_64BIT)
5050 error ("-mips%d does not support 64 bit gp registers", mips_isa);
5051 target_flags &= ~MASK_64BIT;
5055 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
5056 flag_pcc_struct_return = 0;
5058 /* Tell halfpic.c that we have half-pic code if we do. */
5059 if (TARGET_HALF_PIC)
5062 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
5063 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
5064 /* ??? -non_shared turns off pic code generation, but this is not
5066 if (TARGET_ABICALLS)
5068 mips_abicalls = MIPS_ABICALLS_YES;
5070 if (mips_section_threshold > 0)
5071 warning ("-G is incompatible with PIC code which is the default");
5074 mips_abicalls = MIPS_ABICALLS_NO;
5076 /* -membedded-pic is a form of PIC code suitable for embedded
5077 systems. All calls are made using PC relative addressing, and
5078 all data is addressed using the $gp register. This requires gas,
5079 which does most of the work, and GNU ld, which automatically
5080 expands PC relative calls which are out of range into a longer
5081 instruction sequence. All gcc really does differently is
5082 generate a different sequence for a switch. */
5083 if (TARGET_EMBEDDED_PIC)
5086 if (TARGET_ABICALLS)
5087 warning ("-membedded-pic and -mabicalls are incompatible");
5090 warning ("-G and -membedded-pic are incompatible");
5092 /* Setting mips_section_threshold is not required, because gas
5093 will force everything to be GP addressable anyhow, but
5094 setting it will cause gcc to make better estimates of the
5095 number of instructions required to access a particular data
5097 mips_section_threshold = 0x7fffffff;
5100 /* This optimization requires a linker that can support a R_MIPS_LO16
5101 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5102 GNU ld has this support, but not all other MIPS linkers do, so we enable
5103 this optimization only if the user requests it, or if GNU ld is the
5104 standard linker for this configuration. */
5105 /* ??? This does not work when target addresses are DImode.
5106 This is because we are missing DImode high/lo_sum patterns. */
5107 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
5109 mips_split_addresses = 1;
5111 mips_split_addresses = 0;
5113 /* -mrnames says to use the MIPS software convention for register
5114 names instead of the hardware names (ie, $a0 instead of $4).
5115 We do this by switching the names in mips_reg_names, which the
5116 reg_names points into via the REGISTER_NAMES macro. */
5118 if (TARGET_NAME_REGS)
5119 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
5121 /* When compiling for the mips16, we can not use floating point. We
5122 record the original hard float value in mips16_hard_float. */
5125 if (TARGET_SOFT_FLOAT)
5126 mips16_hard_float = 0;
5128 mips16_hard_float = 1;
5129 target_flags |= MASK_SOFT_FLOAT;
5131 /* Don't run the scheduler before reload, since it tends to
5132 increase register pressure. */
5133 flag_schedule_insns = 0;
5136 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5137 to avoid using up another bit in target_flags. */
5138 if (mips_entry_string != NULL)
5140 if (*mips_entry_string != '\0')
5141 error ("invalid option `entry%s'", mips_entry_string);
5143 if (! TARGET_MIPS16)
5144 warning ("-mentry is only meaningful with -mips-16");
5149 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5150 attributes can access it. */
5156 /* Initialize the high and low values for legitimate floating point
5157 constants. Rather than trying to get the accuracy down to the
5158 last bit, just use approximate ranges. */
5159 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
5160 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
5161 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
5162 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
5164 mips_print_operand_punct['?'] = 1;
5165 mips_print_operand_punct['#'] = 1;
5166 mips_print_operand_punct['&'] = 1;
5167 mips_print_operand_punct['!'] = 1;
5168 mips_print_operand_punct['*'] = 1;
5169 mips_print_operand_punct['@'] = 1;
5170 mips_print_operand_punct['.'] = 1;
5171 mips_print_operand_punct['('] = 1;
5172 mips_print_operand_punct[')'] = 1;
5173 mips_print_operand_punct['['] = 1;
5174 mips_print_operand_punct[']'] = 1;
5175 mips_print_operand_punct['<'] = 1;
5176 mips_print_operand_punct['>'] = 1;
5177 mips_print_operand_punct['{'] = 1;
5178 mips_print_operand_punct['}'] = 1;
5179 mips_print_operand_punct['^'] = 1;
5180 mips_print_operand_punct['$'] = 1;
5181 mips_print_operand_punct['+'] = 1;
5182 mips_print_operand_punct['~'] = 1;
5184 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
5185 mips_char_to_class['e'] = M16_NA_REGS;
5186 mips_char_to_class['t'] = T_REG;
5187 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
5188 mips_char_to_class['h'] = HI_REG;
5189 mips_char_to_class['l'] = LO_REG;
5190 mips_char_to_class['a'] = HILO_REG;
5191 mips_char_to_class['x'] = MD_REGS;
5192 mips_char_to_class['b'] = ALL_REGS;
5193 mips_char_to_class['y'] = GR_REGS;
5194 mips_char_to_class['z'] = ST_REGS;
5196 /* Set up array to map GCC register number to debug register number.
5197 Ignore the special purpose register numbers. */
5199 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5200 mips_dbx_regno[i] = -1;
5202 start = GP_DBX_FIRST - GP_REG_FIRST;
5203 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5204 mips_dbx_regno[i] = i + start;
5206 start = FP_DBX_FIRST - FP_REG_FIRST;
5207 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5208 mips_dbx_regno[i] = i + start;
5210 /* Set up array giving whether a given register can hold a given mode.
5211 At present, restrict ints from being in FP registers, because reload
5212 is a little enthusiastic about storing extra values in FP registers,
5213 and this is not good for things like OS kernels. Also, due to the
5214 mandatory delay, it is as fast to load from cached memory as to move
5215 from the FP register. */
5217 for (mode = VOIDmode;
5218 mode != MAX_MACHINE_MODE;
5219 mode = (enum machine_mode) ((int)mode + 1))
5221 register int size = GET_MODE_SIZE (mode);
5222 register enum mode_class class = GET_MODE_CLASS (mode);
5224 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5231 temp = (regno == FPSW_REGNUM);
5233 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5234 || FP_REG_P (regno));
5237 else if (GP_REG_P (regno))
5238 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5240 else if (FP_REG_P (regno))
5241 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0)
5242 /* I think this change is OK regardless of abi, but
5243 I'm being cautions untill I can test this more.
5244 HARD_REGNO_MODE_OK is about whether or not you
5245 can move to and from a register without changing
5246 the value, not about whether math works on the
5248 || (mips_abi == ABI_MEABI && size <= 4))
5249 && (class == MODE_FLOAT
5250 || class == MODE_COMPLEX_FLOAT
5251 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
5252 && (! TARGET_SINGLE_FLOAT || size <= 4));
5254 else if (MD_REG_P (regno))
5255 temp = (class == MODE_INT
5256 && (size <= UNITS_PER_WORD
5257 || (regno == MD_REG_FIRST
5258 && size == 2 * UNITS_PER_WORD)));
5263 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5267 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5268 initialized yet, so we can't use that here. */
5269 gpr_mode = TARGET_64BIT ? DImode : SImode;
5271 /* Provide default values for align_* for 64-bit targets. */
5272 if (TARGET_64BIT && !TARGET_MIPS16)
5274 if (align_loops == 0)
5276 if (align_jumps == 0)
5278 if (align_functions == 0)
5279 align_functions = 8;
5282 /* Register global variables with the garbage collector. */
5283 mips_add_gc_roots ();
5286 /* On the mips16, we want to allocate $24 (T_REG) before other
5287 registers for instructions for which it is possible. This helps
5288 avoid shuffling registers around in order to set up for an xor,
5289 encouraging the compiler to use a cmp instead. */
5292 mips_order_regs_for_local_alloc ()
5296 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5297 reg_alloc_order[i] = i;
5301 /* It really doesn't matter where we put register 0, since it is
5302 a fixed register anyhow. */
5303 reg_alloc_order[0] = 24;
5304 reg_alloc_order[24] = 0;
5309 /* The MIPS debug format wants all automatic variables and arguments
5310 to be in terms of the virtual frame pointer (stack pointer before
5311 any adjustment in the function), while the MIPS 3.0 linker wants
5312 the frame pointer to be the stack pointer after the initial
5313 adjustment. So, we do the adjustment here. The arg pointer (which
5314 is eliminated) points to the virtual frame pointer, while the frame
5315 pointer (which may be eliminated) points to the stack pointer after
5316 the initial adjustments. */
5319 mips_debugger_offset (addr, offset)
5321 HOST_WIDE_INT offset;
5323 rtx offset2 = const0_rtx;
5324 rtx reg = eliminate_constant_term (addr, &offset2);
5327 offset = INTVAL (offset2);
5329 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5330 || reg == hard_frame_pointer_rtx)
5332 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
5333 ? compute_frame_size (get_frame_size ())
5334 : current_frame_info.total_size;
5336 /* MIPS16 frame is smaller */
5337 if (frame_pointer_needed && TARGET_MIPS16)
5338 frame_size -= current_function_outgoing_args_size;
5340 offset = offset - frame_size;
5343 /* sdbout_parms does not want this to crash for unrecognized cases. */
5345 else if (reg != arg_pointer_rtx)
5346 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer");
5352 /* A C compound statement to output to stdio stream STREAM the
5353 assembler syntax for an instruction operand X. X is an RTL
5356 CODE is a value that can be used to specify one of several ways
5357 of printing the operand. It is used when identical operands
5358 must be printed differently depending on the context. CODE
5359 comes from the `%' specification that was used to request
5360 printing of the operand. If the specification was just `%DIGIT'
5361 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5362 is the ASCII code for LTR.
5364 If X is a register, this macro should print the register's name.
5365 The names can be found in an array `reg_names' whose type is
5366 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5368 When the machine description has a specification `%PUNCT' (a `%'
5369 followed by a punctuation character), this macro is called with
5370 a null pointer for X and the punctuation character for CODE.
5372 The MIPS specific codes are:
5374 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5375 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5376 'd' output integer constant in decimal,
5377 'z' if the operand is 0, use $0 instead of normal operand.
5378 'D' print second part of double-word register or memory operand.
5379 'L' print low-order register of double-word register operand.
5380 'M' print high-order register of double-word register operand.
5381 'C' print part of opcode for a branch condition.
5382 'F' print part of opcode for a floating-point branch condition.
5383 'N' print part of opcode for a branch condition, inverted.
5384 'W' print part of opcode for a floating-point branch condition, inverted.
5385 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5386 'B' print 'z' for EQ, 'n' for NE
5387 'b' print 'n' for EQ, 'z' for NE
5388 'T' print 'f' for EQ, 't' for NE
5389 't' print 't' for EQ, 'f' for NE
5390 'Z' print register and a comma, but print nothing for $fcc0
5391 '(' Turn on .set noreorder
5392 ')' Turn on .set reorder
5393 '[' Turn on .set noat
5395 '<' Turn on .set nomacro
5396 '>' Turn on .set macro
5397 '{' Turn on .set volatile (not GAS)
5398 '}' Turn on .set novolatile (not GAS)
5399 '&' Turn on .set noreorder if filling delay slots
5400 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5401 '!' Turn on .set nomacro if filling delay slots
5402 '#' Print nop if in a .set noreorder section.
5403 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5404 '@' Print the name of the assembler temporary register (at or $1).
5405 '.' Print the name of the register with a hard-wired zero (zero or $0).
5406 '^' Print the name of the pic call-through register (t9 or $25).
5407 '$' Print the name of the stack pointer register (sp or $29).
5408 '+' Print the name of the gp register (gp or $28).
5409 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5412 print_operand (file, op, letter)
5413 FILE *file; /* file to write to */
5414 rtx op; /* operand to print */
5415 int letter; /* %<letter> or 0 */
5417 register enum rtx_code code;
5419 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5424 if (mips_branch_likely)
5429 fputs (reg_names [GP_REG_FIRST + 1], file);
5433 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5437 fputs (reg_names [GP_REG_FIRST + 0], file);
5441 fputs (reg_names[STACK_POINTER_REGNUM], file);
5445 fputs (reg_names[GP_REG_FIRST + 28], file);
5449 if (final_sequence != 0 && set_noreorder++ == 0)
5450 fputs (".set\tnoreorder\n\t", file);
5454 if (final_sequence != 0)
5456 if (set_noreorder++ == 0)
5457 fputs (".set\tnoreorder\n\t", file);
5459 if (set_nomacro++ == 0)
5460 fputs (".set\tnomacro\n\t", file);
5465 if (final_sequence != 0 && set_nomacro++ == 0)
5466 fputs ("\n\t.set\tnomacro", file);
5470 if (set_noreorder != 0)
5471 fputs ("\n\tnop", file);
5472 else if (TARGET_STATS)
5473 fputs ("\n\t#nop", file);
5478 if (set_noreorder++ == 0)
5479 fputs (".set\tnoreorder\n\t", file);
5483 if (set_noreorder == 0)
5484 error ("internal error: %%) found without a %%( in assembler pattern");
5486 else if (--set_noreorder == 0)
5487 fputs ("\n\t.set\treorder", file);
5492 if (set_noat++ == 0)
5493 fputs (".set\tnoat\n\t", file);
5498 error ("internal error: %%] found without a %%[ in assembler pattern");
5499 else if (--set_noat == 0)
5500 fputs ("\n\t.set\tat", file);
5505 if (set_nomacro++ == 0)
5506 fputs (".set\tnomacro\n\t", file);
5510 if (set_nomacro == 0)
5511 error ("internal error: %%> found without a %%< in assembler pattern");
5512 else if (--set_nomacro == 0)
5513 fputs ("\n\t.set\tmacro", file);
5518 if (set_volatile++ == 0)
5519 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5523 if (set_volatile == 0)
5524 error ("internal error: %%} found without a %%{ in assembler pattern");
5525 else if (--set_volatile == 0)
5526 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5532 if (align_labels_log > 0)
5533 ASM_OUTPUT_ALIGN (file, align_labels_log);
5538 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5547 error ("PRINT_OPERAND null pointer");
5551 code = GET_CODE (op);
5553 if (code == SIGN_EXTEND)
5554 op = XEXP (op, 0), code = GET_CODE (op);
5559 case EQ: fputs ("eq", file); break;
5560 case NE: fputs ("ne", file); break;
5561 case GT: fputs ("gt", file); break;
5562 case GE: fputs ("ge", file); break;
5563 case LT: fputs ("lt", file); break;
5564 case LE: fputs ("le", file); break;
5565 case GTU: fputs ("gtu", file); break;
5566 case GEU: fputs ("geu", file); break;
5567 case LTU: fputs ("ltu", file); break;
5568 case LEU: fputs ("leu", file); break;
5570 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
5573 else if (letter == 'N')
5576 case EQ: fputs ("ne", file); break;
5577 case NE: fputs ("eq", file); break;
5578 case GT: fputs ("le", file); break;
5579 case GE: fputs ("lt", file); break;
5580 case LT: fputs ("ge", file); break;
5581 case LE: fputs ("gt", file); break;
5582 case GTU: fputs ("leu", file); break;
5583 case GEU: fputs ("ltu", file); break;
5584 case LTU: fputs ("geu", file); break;
5585 case LEU: fputs ("gtu", file); break;
5587 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
5590 else if (letter == 'F')
5593 case EQ: fputs ("c1f", file); break;
5594 case NE: fputs ("c1t", file); break;
5596 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5599 else if (letter == 'W')
5602 case EQ: fputs ("c1t", file); break;
5603 case NE: fputs ("c1f", file); break;
5605 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5608 else if (letter == 'S')
5612 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5613 assemble_name (file, buffer);
5616 else if (letter == 'Z')
5618 register int regnum;
5623 regnum = REGNO (op);
5624 if (! ST_REG_P (regnum))
5627 if (regnum != ST_REG_FIRST)
5628 fprintf (file, "%s,", reg_names[regnum]);
5631 else if (code == REG || code == SUBREG)
5633 register int regnum;
5636 regnum = REGNO (op);
5638 regnum = true_regnum (op);
5640 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5641 || (letter == 'L' && WORDS_BIG_ENDIAN)
5645 fprintf (file, "%s", reg_names[regnum]);
5648 else if (code == MEM)
5651 output_address (plus_constant (XEXP (op, 0), 4));
5653 output_address (XEXP (op, 0));
5656 else if (code == CONST_DOUBLE
5657 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
5662 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
5663 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
5667 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5668 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5670 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5671 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5673 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5674 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5676 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
5677 fputs (reg_names[GP_REG_FIRST], file);
5679 else if (letter == 'd' || letter == 'x' || letter == 'X')
5680 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5682 else if (letter == 'B')
5683 fputs (code == EQ ? "z" : "n", file);
5684 else if (letter == 'b')
5685 fputs (code == EQ ? "n" : "z", file);
5686 else if (letter == 'T')
5687 fputs (code == EQ ? "f" : "t", file);
5688 else if (letter == 't')
5689 fputs (code == EQ ? "t" : "f", file);
5691 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5693 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5694 print_operand (file, XEXP (op, 0), letter);
5697 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5699 fputs ("%gprel(", file);
5700 mips16_output_gp_offset (file, op);
5705 output_addr_const (file, op);
5708 /* A C compound statement to output to stdio stream STREAM the
5709 assembler syntax for an instruction operand that is a memory
5710 reference whose address is ADDR. ADDR is an RTL expression.
5712 On some machines, the syntax for a symbolic address depends on
5713 the section that the address refers to. On these machines,
5714 define the macro `ENCODE_SECTION_INFO' to store the information
5715 into the `symbol_ref', and then check for it here. */
5718 print_operand_address (file, addr)
5723 error ("PRINT_OPERAND_ADDRESS, null pointer");
5726 switch (GET_CODE (addr))
5729 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
5730 abort_with_insn (addr, "arg pointer not eliminated");
5732 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
5737 register rtx arg0 = XEXP (addr, 0);
5738 register rtx arg1 = XEXP (addr, 1);
5740 if (! mips_split_addresses)
5741 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM");
5743 if (GET_CODE (arg0) != REG)
5744 abort_with_insn (addr,
5745 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG");
5747 fprintf (file, "%%lo(");
5748 print_operand_address (file, arg1);
5749 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
5755 register rtx reg = 0;
5756 register rtx offset = 0;
5757 register rtx arg0 = XEXP (addr, 0);
5758 register rtx arg1 = XEXP (addr, 1);
5760 if (GET_CODE (arg0) == REG)
5764 if (GET_CODE (offset) == REG)
5765 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
5768 else if (GET_CODE (arg1) == REG)
5769 reg = arg1, offset = arg0;
5770 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
5772 output_addr_const (file, addr);
5776 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5778 if (! CONSTANT_P (offset))
5779 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5781 if (REGNO (reg) == ARG_POINTER_REGNUM)
5782 abort_with_insn (addr, "arg pointer not eliminated");
5785 && GET_CODE (offset) == CONST
5786 && mips16_gp_offset_p (offset))
5788 fputs ("%gprel(", file);
5789 mips16_output_gp_offset (file, offset);
5793 output_addr_const (file, offset);
5794 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5802 output_addr_const (file, addr);
5806 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5811 /* Target hook for assembling integer objects. It appears that the Irix
5812 6 assembler can't handle 64-bit decimal integers, so avoid printing
5813 such an integer here. */
5816 mips_assemble_integer (x, size, aligned_p)
5821 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
5823 fputs ("\t.dword\t", asm_out_file);
5824 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
5825 output_addr_const (asm_out_file, x);
5827 print_operand (asm_out_file, x, 'X');
5828 fputc ('\n', asm_out_file);
5831 return default_assemble_integer (x, size, aligned_p);
5834 /* If optimizing for the global pointer, keep track of all of the externs, so
5835 that at the end of the file, we can emit the appropriate .extern
5836 declaration for them, before writing out the text section. We assume all
5837 names passed to us are in the permanent obstack, so they will be valid at
5838 the end of the compilation.
5840 If we have -G 0, or the extern size is unknown, or the object is in a user
5841 specified section that is not .sbss/.sdata, don't bother emitting the
5842 .externs. In the case of user specified sections this behaviour is
5843 required as otherwise GAS will think the object lives in .sbss/.sdata. */
5846 mips_output_external (file, decl, name)
5847 FILE *file ATTRIBUTE_UNUSED;
5851 register struct extern_list *p;
5856 && TREE_CODE (decl) != FUNCTION_DECL
5857 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
5858 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
5859 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5860 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
5862 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5863 p->next = extern_head;
5869 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5870 if (TREE_CODE (decl) == FUNCTION_DECL
5871 /* ??? Don't include alloca, since gcc will always expand it
5872 inline. If we don't do this, the C++ library fails to build. */
5873 && strcmp (name, "alloca")
5874 /* ??? Don't include __builtin_next_arg, because then gcc will not
5875 bootstrap under Irix 5.1. */
5876 && strcmp (name, "__builtin_next_arg"))
5878 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5879 p->next = extern_head;
5889 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5891 mips_output_external_libcall (file, name)
5892 FILE *file ATTRIBUTE_UNUSED;
5895 register struct extern_list *p;
5897 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5898 p->next = extern_head;
5907 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5908 for .file's that start within a function. If we are smuggling stabs, try to
5909 put out a MIPS ECOFF file and a stab. */
5912 mips_output_filename (stream, name)
5916 static int first_time = 1;
5917 char ltext_label_name[100];
5923 current_function_file = name;
5924 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5925 /* This tells mips-tfile that stabs will follow. */
5926 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5927 fprintf (stream, "\t#@stabs\n");
5930 else if (write_symbols == DBX_DEBUG)
5932 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5933 fprintf (stream, "%s", ASM_STABS_OP);
5934 output_quoted_string (stream, name);
5935 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5938 else if (name != current_function_file
5939 && strcmp (name, current_function_file) != 0)
5941 if (inside_function && !TARGET_GAS)
5943 if (!file_in_function_warning)
5945 file_in_function_warning = 1;
5946 ignore_line_number = 1;
5947 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5953 current_function_file = name;
5954 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5959 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5960 as well as a .loc, since it is possible that MIPS ECOFF might not be
5961 able to represent the location for inlines that come from a different
5965 mips_output_lineno (stream, line)
5969 if (write_symbols == DBX_DEBUG)
5972 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5973 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5974 LOCAL_LABEL_PREFIX, sym_lineno);
5978 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5979 (ignore_line_number) ? "#" : "",
5980 num_source_filenames, line);
5982 LABEL_AFTER_LOC (stream);
5986 /* Output an ASCII string, in a space-saving way. */
5989 mips_output_ascii (stream, string_param, len)
5991 const char *string_param;
5996 register const unsigned char *string =
5997 (const unsigned char *)string_param;
5999 fprintf (stream, "\t.ascii\t\"");
6000 for (i = 0; i < len; i++)
6002 register int c = string[i];
6008 putc ('\\', stream);
6013 case TARGET_NEWLINE:
6014 fputs ("\\n", stream);
6016 && (((c = string[i+1]) >= '\040' && c <= '~')
6017 || c == TARGET_TAB))
6018 cur_pos = 32767; /* break right here */
6024 fputs ("\\t", stream);
6029 fputs ("\\f", stream);
6034 fputs ("\\b", stream);
6039 fputs ("\\r", stream);
6044 if (c >= ' ' && c < 0177)
6051 fprintf (stream, "\\%03o", c);
6056 if (cur_pos > 72 && i+1 < len)
6059 fprintf (stream, "\"\n\t.ascii\t\"");
6062 fprintf (stream, "\"\n");
6065 /* If defined, a C statement to be executed just prior to the output of
6066 assembler code for INSN, to modify the extracted operands so they will be
6069 Here the argument OPVEC is the vector containing the operands extracted
6070 from INSN, and NOPERANDS is the number of elements of the vector which
6071 contain meaningful data for this insn. The contents of this vector are
6072 what will be used to convert the insn template into assembler code, so you
6073 can change the assembler output by changing the contents of the vector.
6075 We use it to check if the current insn needs a nop in front of it because
6076 of load delays, and also to update the delay slot statistics. */
6078 /* ??? There is no real need for this function, because it never actually
6079 emits a NOP anymore. */
6082 final_prescan_insn (insn, opvec, noperands)
6084 rtx opvec[] ATTRIBUTE_UNUSED;
6085 int noperands ATTRIBUTE_UNUSED;
6087 if (dslots_number_nops > 0)
6089 rtx pattern = PATTERN (insn);
6090 int length = get_attr_length (insn);
6092 /* Do we need to emit a NOP? */
6094 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
6095 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
6096 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
6097 || (mips_load_reg4 != 0
6098 && reg_mentioned_p (mips_load_reg4, pattern)))
6099 fputs ("\t#nop\n", asm_out_file);
6102 dslots_load_filled++;
6104 while (--dslots_number_nops > 0)
6105 fputs ("\t#nop\n", asm_out_file);
6114 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
6115 dslots_jump_total++;
6118 /* Output at beginning of assembler file.
6120 If we are optimizing to use the global pointer, create a temporary file to
6121 hold all of the text stuff, and write it out to the end. This is needed
6122 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6123 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6124 processed, it generates a two instruction sequence. */
6127 mips_asm_file_start (stream)
6130 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
6132 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6133 inside of a .set noreorder section jumps to a label outside of the .set
6134 noreorder section. Revision 2.20 just set nobopt silently rather than
6137 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
6138 fprintf (stream, "\t.set\tnobopt\n");
6142 #if defined(OBJECT_FORMAT_ELF)
6143 /* Generate a special section to describe the ABI switches used to
6144 produce the resultant binary. This used to be done by the assembler
6145 setting bits in the ELF header's flags field, but we have run out of
6146 bits. GDB needs this information in order to be able to correctly
6147 debug these binaries. See the function mips_gdbarch_init() in
6149 const char * abi_string = NULL;
6153 case ABI_32: abi_string = "abi32"; break;
6154 case ABI_N32: abi_string = "abiN32"; break;
6155 case ABI_64: abi_string = "abi64"; break;
6156 case ABI_O64: abi_string = "abiO64"; break;
6157 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
6158 case ABI_MEABI:abi_string = TARGET_64BIT ? "meabi64" : "meabi32"; break;
6162 /* Note - we use fprintf directly rather than called named_section()
6163 because in this way we can avoid creating an allocated section. We
6164 do not want this section to take up any space in the running
6166 fprintf (stream, "\t.section .mdebug.%s\n", abi_string);
6168 /* Restore the default section. */
6169 fprintf (stream, "\t.previous\n");
6175 /* Generate the pseudo ops that System V.4 wants. */
6176 #ifndef ABICALLS_ASM_OP
6177 #define ABICALLS_ASM_OP "\t.abicalls"
6179 if (TARGET_ABICALLS)
6180 /* ??? but do not want this (or want pic0) if -non-shared? */
6181 fprintf (stream, "%s\n", ABICALLS_ASM_OP);
6184 fprintf (stream, "\t.set\tmips16\n");
6186 /* This code exists so that we can put all externs before all symbol
6187 references. This is necessary for the MIPS assembler's global pointer
6188 optimizations to work. */
6189 if (TARGET_FILE_SWITCHING)
6191 asm_out_data_file = stream;
6192 asm_out_text_file = tmpfile ();
6195 asm_out_data_file = asm_out_text_file = stream;
6197 if (flag_verbose_asm)
6198 fprintf (stream, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6200 mips_section_threshold, mips_arch_string, mips_isa);
6203 /* If we are optimizing the global pointer, emit the text section now and any
6204 small externs which did not have .comm, etc that are needed. Also, give a
6205 warning if the data area is more than 32K and -pic because 3 instructions
6206 are needed to reference the data pointers. */
6209 mips_asm_file_end (file)
6213 struct extern_list *p;
6217 HALF_PIC_FINISH (file);
6224 for (p = extern_head; p != 0; p = p->next)
6226 name_tree = get_identifier (p->name);
6228 /* Positively ensure only one .extern for any given symbol. */
6229 if (! TREE_ASM_WRITTEN (name_tree))
6231 TREE_ASM_WRITTEN (name_tree) = 1;
6232 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6234 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
6238 fputs ("\t.extern\t", file);
6239 assemble_name (file, p->name);
6240 fprintf (file, ", %d\n", p->size);
6246 if (TARGET_FILE_SWITCHING)
6248 fprintf (file, "\n\t.text\n");
6249 copy_file_data (file, asm_out_text_file);
6254 copy_file_data (to, from)
6261 fatal_io_error ("can't rewind temp file");
6263 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
6264 if (fwrite (buffer, 1, len, to) != len)
6265 fatal_io_error ("can't write to output file");
6268 fatal_io_error ("can't read from temp file");
6271 fatal_io_error ("can't close temp file");
6274 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6275 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6278 mips_declare_object (stream, name, init_string, final_string, size)
6281 const char *init_string;
6282 const char *final_string;
6285 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
6286 assemble_name (stream, name);
6287 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
6291 tree name_tree = get_identifier (name);
6292 TREE_ASM_WRITTEN (name_tree) = 1;
6296 /* Return the bytes needed to compute the frame pointer from the current
6299 Mips stack frames look like:
6301 Before call After call
6302 +-----------------------+ +-----------------------+
6305 | caller's temps. | | caller's temps. |
6307 +-----------------------+ +-----------------------+
6309 | arguments on stack. | | arguments on stack. |
6311 +-----------------------+ +-----------------------+
6312 | 4 words to save | | 4 words to save |
6313 | arguments passed | | arguments passed |
6314 | in registers, even | | in registers, even |
6315 SP->| if not passed. | VFP->| if not passed. |
6316 +-----------------------+ +-----------------------+
6318 | fp register save |
6320 +-----------------------+
6322 | gp register save |
6324 +-----------------------+
6328 +-----------------------+
6330 | alloca allocations |
6332 +-----------------------+
6334 | GP save for V.4 abi |
6336 +-----------------------+
6338 | arguments on stack |
6340 +-----------------------+
6342 | arguments passed |
6343 | in registers, even |
6344 low SP->| if not passed. |
6345 memory +-----------------------+
6350 compute_frame_size (size)
6351 HOST_WIDE_INT size; /* # of var. bytes allocated */
6354 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6355 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6356 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6357 HOST_WIDE_INT extra_size; /* # extra bytes */
6358 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6359 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6360 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6361 long mask; /* mask of saved gp registers */
6362 long fmask; /* mask of saved fp registers */
6363 int fp_inc; /* 1 or 2 depending on the size of fp regs */
6364 long fp_bits; /* bitmask to use for each fp register */
6370 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
6371 var_size = MIPS_STACK_ALIGN (size);
6372 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
6374 /* The MIPS 3.0 linker does not like functions that dynamically
6375 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6376 looks like we are trying to create a second frame pointer to the
6377 function, so allocate some stack space to make it happy. */
6379 if (args_size == 0 && current_function_calls_alloca)
6380 args_size = 4 * UNITS_PER_WORD;
6382 total_size = var_size + args_size + extra_size;
6384 /* Calculate space needed for gp registers. */
6385 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6387 /* $18 is a special case on the mips16. It may be used to call
6388 a function which returns a floating point value, but it is
6389 marked in call_used_regs. $31 is also a special case. When
6390 not using -mentry, it will be used to copy a return value
6391 into the floating point registers if the return value is
6393 if (MUST_SAVE_REGISTER (regno)
6395 && regno == GP_REG_FIRST + 18
6396 && regs_ever_live[regno])
6398 && regno == GP_REG_FIRST + 31
6399 && mips16_hard_float
6401 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
6402 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6404 && (! TARGET_SINGLE_FLOAT
6405 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6408 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6409 mask |= 1L << (regno - GP_REG_FIRST);
6411 /* The entry and exit pseudo instructions can not save $17
6412 without also saving $16. */
6414 && regno == GP_REG_FIRST + 17
6415 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
6417 gp_reg_size += UNITS_PER_WORD;
6423 /* We need to restore these for the handler. */
6424 if (current_function_calls_eh_return)
6429 regno = EH_RETURN_DATA_REGNO (i);
6430 if (regno == INVALID_REGNUM)
6432 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6433 mask |= 1L << (regno - GP_REG_FIRST);
6437 /* Calculate space needed for fp registers. */
6438 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
6449 /* This loop must iterate over the same space as its companion in
6450 save_restore_insns. */
6451 for (regno = (FP_REG_LAST - fp_inc + 1);
6452 regno >= FP_REG_FIRST;
6455 if (regs_ever_live[regno] && !call_used_regs[regno])
6457 fp_reg_size += fp_inc * UNITS_PER_FPREG;
6458 fmask |= fp_bits << (regno - FP_REG_FIRST);
6462 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6463 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6465 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6466 for leaf routines (total_size == extra_size) to save the gp reg.
6467 The gp reg is callee saved in the 64 bit ABI, so all routines must
6468 save the gp reg. This is not a leaf routine if -p, because of the
6470 if (total_size == extra_size
6471 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
6472 && ! current_function_profile)
6473 total_size = extra_size = 0;
6474 else if (TARGET_ABICALLS)
6476 /* Add the context-pointer to the saved registers. */
6477 gp_reg_size += UNITS_PER_WORD;
6478 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
6479 total_size -= gp_reg_rounded;
6480 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6481 total_size += gp_reg_rounded;
6484 /* Add in space reserved on the stack by the callee for storing arguments
6485 passed in registers. */
6486 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6487 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6489 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6490 if (mips_entry && total_size > 0 && total_size < 32)
6493 /* Save other computed information. */
6494 current_frame_info.total_size = total_size;
6495 current_frame_info.var_size = var_size;
6496 current_frame_info.args_size = args_size;
6497 current_frame_info.extra_size = extra_size;
6498 current_frame_info.gp_reg_size = gp_reg_size;
6499 current_frame_info.fp_reg_size = fp_reg_size;
6500 current_frame_info.mask = mask;
6501 current_frame_info.fmask = fmask;
6502 current_frame_info.initialized = reload_completed;
6503 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
6504 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
6508 unsigned long offset;
6510 /* When using mips_entry, the registers are always saved at the
6511 top of the stack. */
6513 offset = (args_size + extra_size + var_size
6514 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6516 offset = total_size - GET_MODE_SIZE (gpr_mode);
6518 current_frame_info.gp_sp_offset = offset;
6519 current_frame_info.gp_save_offset = offset - total_size;
6523 current_frame_info.gp_sp_offset = 0;
6524 current_frame_info.gp_save_offset = 0;
6529 unsigned long offset = (args_size + extra_size + var_size
6530 + gp_reg_rounded + fp_reg_size
6531 - fp_inc * UNITS_PER_FPREG);
6532 current_frame_info.fp_sp_offset = offset;
6533 current_frame_info.fp_save_offset = offset - total_size;
6537 current_frame_info.fp_sp_offset = 0;
6538 current_frame_info.fp_save_offset = 0;
6541 /* Ok, we're done. */
6545 /* Common code to emit the insns (or to write the instructions to a file)
6546 to save/restore registers.
6548 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6549 is not modified within save_restore_insns. */
6551 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6553 /* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
6554 and return an rtl expression for the register. Write the assembly
6555 instructions directly to FILE if it is not null, otherwise emit them as
6558 This function is a subroutine of save_restore_insns. It is used when
6559 OFFSET is too large to add in a single instruction. */
6562 mips_add_large_offset_to_sp (offset, file)
6563 HOST_WIDE_INT offset;
6566 rtx reg = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6569 rtx offset_rtx = GEN_INT (offset);
6571 emit_move_insn (reg, offset_rtx);
6572 if (Pmode == DImode)
6573 emit_insn (gen_adddi3 (reg, reg, stack_pointer_rtx));
6575 emit_insn (gen_addsi3 (reg, reg, stack_pointer_rtx));
6579 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6580 reg_names[MIPS_TEMP2_REGNUM], (long) offset);
6581 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
6582 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6583 Pmode == DImode ? "daddu" : "addu",
6584 reg_names[MIPS_TEMP2_REGNUM],
6585 reg_names[MIPS_TEMP2_REGNUM],
6586 reg_names[STACK_POINTER_REGNUM]);
6591 /* Make INSN frame related and note that it performs the frame-related
6592 operation DWARF_PATTERN. */
6595 mips_annotate_frame_insn (insn, dwarf_pattern)
6596 rtx insn, dwarf_pattern;
6598 RTX_FRAME_RELATED_P (insn) = 1;
6599 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6604 /* Return a frame-related rtx that stores register REGNO at (SP + OFFSET).
6605 The expression should only be used to store single registers. */
6608 mips_frame_set (mode, regno, offset)
6609 enum machine_mode mode;
6613 rtx address = plus_constant (stack_pointer_rtx, offset);
6614 rtx set = gen_rtx_SET (mode,
6615 gen_rtx_MEM (mode, address),
6616 gen_rtx_REG (mode, regno));
6617 RTX_FRAME_RELATED_P (set) = 1;
6622 /* Emit a move instruction that stores REG in MEM. Make the instruction
6623 frame related and note that it stores REG at (SP + OFFSET). This
6624 function may be asked to store an FPR pair. */
6627 mips_emit_frame_related_store (mem, reg, offset)
6630 HOST_WIDE_INT offset;
6634 if (GET_MODE (reg) == DFmode && ! TARGET_FLOAT64)
6636 /* Two registers are being stored, so the frame-related expression
6637 must be a PARALLEL rtx with one SET for each register. The
6638 higher numbered register is stored in the lower address on
6639 big-endian targets. */
6640 int regno1 = TARGET_BIG_ENDIAN ? REGNO (reg) + 1 : REGNO (reg);
6641 int regno2 = TARGET_BIG_ENDIAN ? REGNO (reg) : REGNO (reg) + 1;
6642 rtx set1 = mips_frame_set (SFmode, regno1, offset);
6643 rtx set2 = mips_frame_set (SFmode, regno2, offset + UNITS_PER_FPREG);
6644 dwarf_expr = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1, set2));
6647 dwarf_expr = mips_frame_set (GET_MODE (reg), REGNO (reg), offset);
6649 mips_annotate_frame_insn (emit_move_insn (mem, reg), dwarf_expr);
6653 save_restore_insns (store_p, large_reg, large_offset, file)
6654 int store_p; /* true if this is prologue */
6655 rtx large_reg; /* register holding large offset constant or NULL */
6656 long large_offset; /* large constant offset value */
6657 FILE *file; /* file to write instructions instead of making RTL */
6659 long mask = current_frame_info.mask;
6660 long fmask = current_frame_info.fmask;
6661 long real_mask = mask;
6664 HOST_WIDE_INT base_offset;
6665 HOST_WIDE_INT gp_offset;
6666 HOST_WIDE_INT fp_offset;
6667 HOST_WIDE_INT end_offset;
6670 if (frame_pointer_needed
6671 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
6674 /* Do not restore GP under certain conditions. */
6677 && (mips_abi == ABI_32 || mips_abi == ABI_O64))
6678 mask &= ~(1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST));
6680 if (mask == 0 && fmask == 0)
6683 /* Save registers starting from high to low. The debuggers prefer at least
6684 the return register be stored at func+4, and also it allows us not to
6685 need a nop in the epilog if at least one register is reloaded in
6686 addition to return address. */
6688 /* Save GP registers if needed. */
6691 /* Pick which pointer to use as a base register. For small frames, just
6692 use the stack pointer. Otherwise, use a temporary register. Save 2
6693 cycles if the save area is near the end of a large frame, by reusing
6694 the constant created in the prologue/epilogue to adjust the stack
6697 gp_offset = current_frame_info.gp_sp_offset;
6699 = gp_offset - (current_frame_info.gp_reg_size
6700 - GET_MODE_SIZE (gpr_mode));
6702 if (gp_offset < 0 || end_offset < 0)
6704 ("gp_offset (%ld) or end_offset (%ld) is less than zero",
6705 (long) gp_offset, (long) end_offset);
6707 /* If we see a large frame in mips16 mode, we save the registers
6708 before adjusting the stack pointer, and load them afterward. */
6709 else if (TARGET_MIPS16 && large_offset > 32767)
6710 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
6712 else if (gp_offset < 32768)
6713 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6715 else if (large_reg != 0
6716 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
6717 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6719 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6720 base_offset = large_offset;
6723 if (Pmode == DImode)
6724 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6725 stack_pointer_rtx));
6727 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6728 stack_pointer_rtx));
6731 fprintf (file, "\t%s\t%s,%s,%s\n",
6732 Pmode == DImode ? "daddu" : "addu",
6733 reg_names[MIPS_TEMP2_REGNUM],
6734 reg_names[REGNO (large_reg)],
6735 reg_names[STACK_POINTER_REGNUM]);
6739 base_offset = gp_offset;
6740 base_reg_rtx = mips_add_large_offset_to_sp (base_offset, file);
6743 /* When we restore the registers in MIPS16 mode, then if we are
6744 using a frame pointer, and this is not a large frame, the
6745 current stack pointer will be offset by
6746 current_function_outgoing_args_size. Doing it this way lets
6747 us avoid offsetting the frame pointer before copying it into
6748 the stack pointer; there is no instruction to set the stack
6749 pointer to the sum of a register and a constant. */
6752 && frame_pointer_needed
6753 && large_offset <= 32767)
6754 base_offset += current_function_outgoing_args_size;
6756 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6757 if (BITSET_P (mask, regno - GP_REG_FIRST))
6763 = gen_rtx (MEM, gpr_mode,
6764 gen_rtx (PLUS, Pmode, base_reg_rtx,
6765 GEN_INT (gp_offset - base_offset)));
6767 if (! current_function_calls_eh_return)
6768 RTX_UNCHANGING_P (mem_rtx) = 1;
6770 /* The mips16 does not have an instruction to load
6771 $31, so we load $7 instead, and work things out
6772 in mips_expand_epilogue. */
6773 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
6774 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
6775 /* The mips16 sometimes needs to save $18. */
6776 else if (TARGET_MIPS16
6777 && regno != GP_REG_FIRST + 31
6778 && ! M16_REG_P (regno))
6781 reg_rtx = gen_rtx (REG, gpr_mode, 6);
6784 reg_rtx = gen_rtx (REG, gpr_mode, 3);
6785 emit_move_insn (reg_rtx,
6786 gen_rtx (REG, gpr_mode, regno));
6790 reg_rtx = gen_rtx (REG, gpr_mode, regno);
6793 mips_emit_frame_related_store (mem_rtx, reg_rtx, gp_offset);
6796 emit_move_insn (reg_rtx, mem_rtx);
6798 && regno != GP_REG_FIRST + 31
6799 && ! M16_REG_P (regno))
6800 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
6808 /* The mips16 does not have an instruction to
6809 load $31, so we load $7 instead, and work
6810 things out in the caller. */
6811 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
6812 r = GP_REG_FIRST + 7;
6813 /* The mips16 sometimes needs to save $18. */
6815 && regno != GP_REG_FIRST + 31
6816 && ! M16_REG_P (regno))
6819 r = GP_REG_FIRST + 6;
6822 r = GP_REG_FIRST + 3;
6823 fprintf (file, "\tmove\t%s,%s\n",
6824 reg_names[r], reg_names[regno]);
6827 fprintf (file, "\t%s\t%s,",
6829 ? (store_p) ? "sd" : "ld"
6830 : (store_p) ? "sw" : "lw"),
6832 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6833 gp_offset - base_offset);
6834 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6837 && regno != GP_REG_FIRST + 31
6838 && ! M16_REG_P (regno))
6839 fprintf (file, "\tmove\t%s,%s\n",
6840 reg_names[regno], reg_names[r]);
6842 gp_offset -= GET_MODE_SIZE (gpr_mode);
6844 /* If the restore is being supressed, still take into account
6845 the offset at which it is stored. */
6846 else if (BITSET_P (real_mask, regno - GP_REG_FIRST))
6848 gp_offset -= GET_MODE_SIZE (gpr_mode);
6852 base_reg_rtx = 0, base_offset = 0;
6854 /* Save floating point registers if needed. */
6857 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
6858 int fp_size = fp_inc * UNITS_PER_FPREG;
6860 /* Pick which pointer to use as a base register. */
6861 fp_offset = current_frame_info.fp_sp_offset;
6862 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
6864 if (fp_offset < 0 || end_offset < 0)
6866 ("fp_offset (%ld) or end_offset (%ld) is less than zero",
6867 (long) fp_offset, (long) end_offset);
6869 else if (fp_offset < 32768)
6870 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6872 else if (base_reg_rtx != 0
6873 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
6874 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
6875 ; /* already set up for gp registers above */
6877 else if (large_reg != 0
6878 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
6879 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6881 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6882 base_offset = large_offset;
6885 if (Pmode == DImode)
6886 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6887 stack_pointer_rtx));
6889 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6890 stack_pointer_rtx));
6894 fprintf (file, "\t%s\t%s,%s,%s\n",
6895 Pmode == DImode ? "daddu" : "addu",
6896 reg_names[MIPS_TEMP2_REGNUM],
6897 reg_names[REGNO (large_reg)],
6898 reg_names[STACK_POINTER_REGNUM]);
6902 base_offset = fp_offset;
6903 base_reg_rtx = mips_add_large_offset_to_sp (fp_offset, file);
6906 /* This loop must iterate over the same space as its companion in
6907 compute_frame_size. */
6908 for (regno = (FP_REG_LAST - fp_inc + 1);
6909 regno >= FP_REG_FIRST;
6911 if (BITSET_P (fmask, regno - FP_REG_FIRST))
6915 enum machine_mode sz
6916 = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6917 rtx reg_rtx = gen_rtx (REG, sz, regno);
6918 rtx mem_rtx = gen_rtx (MEM, sz,
6919 gen_rtx (PLUS, Pmode, base_reg_rtx,
6922 if (! current_function_calls_eh_return)
6923 RTX_UNCHANGING_P (mem_rtx) = 1;
6926 mips_emit_frame_related_store (mem_rtx, reg_rtx, fp_offset);
6928 emit_move_insn (reg_rtx, mem_rtx);
6932 fprintf (file, "\t%s\t%s,",
6933 (TARGET_SINGLE_FLOAT
6934 ? (store_p ? "s.s" : "l.s")
6935 : (store_p ? "s.d" : "l.d")),
6937 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6938 fp_offset - base_offset);
6939 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6942 fp_offset -= fp_size;
6947 /* Set up the stack and frame (if desired) for the function. */
6950 mips_output_function_prologue (file, size)
6952 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6954 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6957 HOST_WIDE_INT tsize = current_frame_info.total_size;
6959 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6961 #ifdef SDB_DEBUGGING_INFO
6962 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6963 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6966 /* In mips16 mode, we may need to generate a 32 bit to handle
6967 floating point arguments. The linker will arrange for any 32 bit
6968 functions to call this stub, which will then jump to the 16 bit
6970 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6971 && current_function_args_info.fp_code != 0)
6972 build_mips16_function_stub (file);
6974 inside_function = 1;
6976 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6977 /* Get the function name the same way that toplev.c does before calling
6978 assemble_start_function. This is needed so that the name used here
6979 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6980 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6982 if (!flag_inhibit_size_directive)
6984 fputs ("\t.ent\t", file);
6985 assemble_name (file, fnname);
6989 assemble_name (file, fnname);
6990 fputs (":\n", file);
6993 if (!flag_inhibit_size_directive)
6995 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6997 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6998 (reg_names[(frame_pointer_needed)
6999 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
7000 ((frame_pointer_needed && TARGET_MIPS16)
7001 ? ((long) tsize - current_function_outgoing_args_size)
7003 reg_names[GP_REG_FIRST + 31],
7004 current_frame_info.var_size,
7005 current_frame_info.num_gp,
7006 current_frame_info.num_fp,
7007 current_function_outgoing_args_size,
7008 current_frame_info.extra_size);
7010 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7011 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
7012 current_frame_info.mask,
7013 current_frame_info.gp_save_offset,
7014 current_frame_info.fmask,
7015 current_frame_info.fp_save_offset);
7018 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7019 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7022 if (mips_entry && ! mips_can_use_return_insn ())
7024 int save16 = BITSET_P (current_frame_info.mask, 16);
7025 int save17 = BITSET_P (current_frame_info.mask, 17);
7026 int save31 = BITSET_P (current_frame_info.mask, 31);
7030 /* Look through the initial insns to see if any of them store
7031 the function parameters into the incoming parameter storage
7032 area. If they do, we delete the insn, and save the register
7033 using the entry pseudo-instruction instead. We don't try to
7034 look past a label, jump, or call. */
7035 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
7037 rtx note, set, src, dest, base, offset;
7040 if (GET_CODE (insn) == CODE_LABEL
7041 || GET_CODE (insn) == JUMP_INSN
7042 || GET_CODE (insn) == CALL_INSN)
7044 if (GET_CODE (insn) != INSN)
7046 set = PATTERN (insn);
7047 if (GET_CODE (set) != SET)
7050 /* An insn storing a function parameter will still have a
7051 REG_EQUIV note on it mentioning the argument pointer. */
7052 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
7053 if (note == NULL_RTX)
7055 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
7058 src = SET_SRC (set);
7059 if (GET_CODE (src) != REG
7060 || REGNO (src) < GP_REG_FIRST + 4
7061 || REGNO (src) > GP_REG_FIRST + 7)
7064 dest = SET_DEST (set);
7065 if (GET_CODE (dest) != MEM)
7067 if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned) UNITS_PER_WORD)
7069 else if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned)2 * UNITS_PER_WORD
7070 && REGNO (src) < GP_REG_FIRST + 7)
7074 offset = const0_rtx;
7075 base = eliminate_constant_term (XEXP (dest, 0), &offset);
7076 if (GET_CODE (base) != REG
7077 || GET_CODE (offset) != CONST_INT)
7079 if (REGNO (base) == (unsigned) STACK_POINTER_REGNUM
7080 && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
7082 else if (REGNO (base) == (unsigned) HARD_FRAME_POINTER_REGNUM
7085 + (REGNO (src) - 4) * UNITS_PER_WORD
7086 - current_function_outgoing_args_size)))
7091 /* This insn stores a parameter onto the stack, in the same
7092 location where the entry pseudo-instruction will put it.
7093 Delete the insn, and arrange to tell the entry
7094 instruction to save the register. */
7095 PUT_CODE (insn, NOTE);
7096 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7097 NOTE_SOURCE_FILE (insn) = 0;
7099 hireg = (REGNO (src)
7100 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
7102 if (hireg > savearg)
7106 /* If this is a varargs function, we need to save all the
7107 registers onto the stack anyhow. */
7108 if (current_function_stdarg || current_function_varargs)
7109 savearg = GP_REG_FIRST + 7;
7111 fprintf (file, "\tentry\t");
7114 if (savearg == GP_REG_FIRST + 4)
7115 fprintf (file, "%s", reg_names[savearg]);
7117 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
7118 reg_names[savearg]);
7120 if (save16 || save17)
7123 fprintf (file, ",");
7124 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
7126 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
7130 if (savearg > 0 || save16 || save17)
7131 fprintf (file, ",");
7132 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
7134 fprintf (file, "\n");
7137 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
7139 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7141 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7142 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
7145 fprintf (file, "\t%s\t%s,%s,%ld\n",
7146 (Pmode == DImode ? "dsubu" : "subu"),
7147 sp_str, sp_str, (long) tsize);
7148 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
7151 if (dwarf2out_do_frame ())
7152 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
7156 /* Expand the prologue into a bunch of separate insns. */
7159 mips_expand_prologue ()
7162 HOST_WIDE_INT tsize;
7164 int last_arg_is_vararg_marker = 0;
7165 tree fndecl = current_function_decl;
7166 tree fntype = TREE_TYPE (fndecl);
7167 tree fnargs = DECL_ARGUMENTS (fndecl);
7172 CUMULATIVE_ARGS args_so_far;
7173 rtx reg_18_save = NULL_RTX;
7174 int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
7175 && (! mips_entry || mips_can_use_return_insn ());
7177 /* If struct value address is treated as the first argument, make it so. */
7178 if (aggregate_value_p (DECL_RESULT (fndecl))
7179 && ! current_function_returns_pcc_struct
7180 && struct_value_incoming_rtx == 0)
7182 tree type = build_pointer_type (fntype);
7183 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
7185 DECL_ARG_TYPE (function_result_decl) = type;
7186 TREE_CHAIN (function_result_decl) = fnargs;
7187 fnargs = function_result_decl;
7190 /* For arguments passed in registers, find the register number
7191 of the first argument in the variable part of the argument list,
7192 otherwise GP_ARG_LAST+1. Note also if the last argument is
7193 the varargs special argument, and treat it as part of the
7196 This is only needed if store_args_on_stack is true. */
7198 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
7199 regno = GP_ARG_FIRST;
7201 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
7203 tree passed_type = DECL_ARG_TYPE (cur_arg);
7204 enum machine_mode passed_mode = TYPE_MODE (passed_type);
7207 if (TREE_ADDRESSABLE (passed_type))
7209 passed_type = build_pointer_type (passed_type);
7210 passed_mode = Pmode;
7213 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
7215 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
7216 next_arg = TREE_CHAIN (cur_arg);
7218 if (entry_parm && store_args_on_stack)
7221 && DECL_NAME (cur_arg)
7222 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7223 "__builtin_va_alist"))
7224 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7227 last_arg_is_vararg_marker = 1;
7234 if (GET_CODE (entry_parm) != REG)
7237 /* passed in a register, so will get homed automatically */
7238 if (GET_MODE (entry_parm) == BLKmode)
7239 words = (int_size_in_bytes (passed_type) + 3) / 4;
7241 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
7243 regno = REGNO (entry_parm) + words - 1;
7248 regno = GP_ARG_LAST+1;
7253 /* In order to pass small structures by value in registers compatibly with
7254 the MIPS compiler, we need to shift the value into the high part of the
7255 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7256 adjustments to be made as the next_arg_reg variable, so we split up the
7257 insns, and emit them separately. */
7259 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
7260 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
7262 rtvec adjust = XVEC (next_arg_reg, 0);
7263 int num = GET_NUM_ELEM (adjust);
7265 for (i = 0; i < num; i++)
7269 pattern = RTVEC_ELT (adjust, i);
7270 if (GET_CODE (pattern) != SET
7271 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
7272 abort_with_insn (pattern, "insn is not a shift");
7273 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
7275 insn = emit_insn (pattern);
7277 /* Global life information isn't valid at this point, so we
7278 can't check whether these shifts are actually used. Mark
7279 them MAYBE_DEAD so that flow2 will remove them, and not
7280 complain about dead code in the prologue. */
7281 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7286 tsize = compute_frame_size (get_frame_size ());
7288 /* If this function is a varargs function, store any registers that
7289 would normally hold arguments ($4 - $7) on the stack. */
7290 if (store_args_on_stack
7291 && ((TYPE_ARG_TYPES (fntype) != 0
7292 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
7294 || last_arg_is_vararg_marker))
7296 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
7297 rtx ptr = stack_pointer_rtx;
7299 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7300 if (TARGET_ABICALLS)
7303 for (; regno <= GP_ARG_LAST; regno++)
7306 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
7307 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
7308 gen_rtx (REG, gpr_mode, regno));
7310 offset += GET_MODE_SIZE (gpr_mode);
7314 /* If we are using the entry pseudo instruction, it will
7315 automatically subtract 32 from the stack pointer, so we don't
7316 need to. The entry pseudo instruction is emitted by
7317 function_prologue. */
7318 if (mips_entry && ! mips_can_use_return_insn ())
7320 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
7324 /* If we are using a frame pointer with a small stack frame,
7325 we need to initialize it here since it won't be done
7327 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7329 rtx incr = GEN_INT (current_function_outgoing_args_size);
7330 if (Pmode == DImode)
7331 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7335 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7339 else if (Pmode == DImode)
7340 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7341 stack_pointer_rtx));
7343 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7344 stack_pointer_rtx));
7346 RTX_FRAME_RELATED_P (insn) = 1;
7349 /* We may need to save $18, if it is used to call a function
7350 which may return a floating point value. Set up a sequence
7351 of instructions to do so. Later on we emit them at the right
7353 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
7355 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
7356 long gp_offset, base_offset;
7358 gp_offset = current_frame_info.gp_sp_offset;
7359 if (BITSET_P (current_frame_info.mask, 16))
7360 gp_offset -= UNITS_PER_WORD;
7361 if (BITSET_P (current_frame_info.mask, 17))
7362 gp_offset -= UNITS_PER_WORD;
7363 if (BITSET_P (current_frame_info.mask, 31))
7364 gp_offset -= UNITS_PER_WORD;
7366 base_offset = tsize;
7370 emit_move_insn (reg_rtx,
7371 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
7372 emit_move_insn (gen_rtx (MEM, gpr_mode,
7373 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
7377 reg_18_save = gen_sequence ();
7386 if (reg_18_save != NULL_RTX)
7387 emit_insn (reg_18_save);
7393 rtx tsize_rtx = GEN_INT (tsize);
7395 /* If we are doing svr4-abi, sp move is done by
7396 function_prologue. In mips16 mode with a large frame, we
7397 save the registers before adjusting the stack. */
7398 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7399 && (!TARGET_MIPS16 || tsize <= 32767))
7401 rtx adjustment_rtx, insn, dwarf_pattern;
7405 adjustment_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
7406 emit_move_insn (adjustment_rtx, tsize_rtx);
7409 adjustment_rtx = tsize_rtx;
7411 if (Pmode == DImode)
7412 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7415 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7418 dwarf_pattern = gen_rtx_SET (Pmode, stack_pointer_rtx,
7419 plus_constant (stack_pointer_rtx,
7422 mips_annotate_frame_insn (insn, dwarf_pattern);
7426 save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
7427 else if (reg_18_save != NULL_RTX)
7428 emit_insn (reg_18_save);
7430 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7436 if (!frame_pointer_needed)
7439 reg_rtx = gen_rtx (REG, Pmode, 3);
7440 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7441 emit_move_insn (reg_rtx, tsize_rtx);
7442 if (Pmode == DImode)
7443 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7444 hard_frame_pointer_rtx,
7447 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7448 hard_frame_pointer_rtx,
7450 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7453 if (frame_pointer_needed)
7457 /* On the mips16, we encourage the use of unextended
7458 instructions when using the frame pointer by pointing the
7459 frame pointer ahead of the argument space allocated on
7461 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7465 /* In this case, we have already copied the stack
7466 pointer into the frame pointer, above. We need only
7467 adjust for the outgoing argument size. */
7468 if (current_function_outgoing_args_size != 0)
7470 rtx incr = GEN_INT (current_function_outgoing_args_size);
7471 if (Pmode == DImode)
7472 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7473 hard_frame_pointer_rtx,
7476 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7477 hard_frame_pointer_rtx,
7481 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7483 rtx incr = GEN_INT (current_function_outgoing_args_size);
7484 if (Pmode == DImode)
7485 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7489 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7493 else if (Pmode == DImode)
7494 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7495 stack_pointer_rtx));
7497 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7498 stack_pointer_rtx));
7501 RTX_FRAME_RELATED_P (insn) = 1;
7504 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
7505 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
7506 gen_rtx_REG (DImode, 25)));
7509 /* If we are profiling, make sure no instructions are scheduled before
7510 the call to mcount. */
7512 if (current_function_profile)
7513 emit_insn (gen_blockage ());
7516 /* Do any necessary cleanup after a function to restore stack, frame,
7519 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7520 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7523 mips_output_function_epilogue (file, size)
7524 FILE *file ATTRIBUTE_UNUSED;
7525 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7527 const char *fnname = ""; /* FIXME: Correct initialisation? */
7529 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7530 /* Get the function name the same way that toplev.c does before calling
7531 assemble_start_function. This is needed so that the name used here
7532 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7533 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7535 if (!flag_inhibit_size_directive)
7537 fputs ("\t.end\t", file);
7538 assemble_name (file, fnname);
7545 int num_gp_regs = current_frame_info.gp_reg_size / 4;
7546 int num_fp_regs = current_frame_info.fp_reg_size / 8;
7547 int num_regs = num_gp_regs + num_fp_regs;
7548 const char *name = fnname;
7553 dslots_load_total += num_regs;
7556 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7557 name, frame_pointer_needed ? 'y' : 'n',
7558 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
7559 current_function_calls_alloca ? 'y' : 'n',
7560 current_function_calls_setjmp ? 'y' : 'n',
7561 current_frame_info.total_size,
7562 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
7563 dslots_load_total, dslots_load_filled,
7564 dslots_jump_total, dslots_jump_filled,
7565 num_refs[0], num_refs[1], num_refs[2]);
7567 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
7570 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
7571 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
7574 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
7577 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
7578 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
7581 fputc ('\n', stderr);
7584 /* Reset state info for each function. */
7585 inside_function = 0;
7586 ignore_line_number = 0;
7587 dslots_load_total = 0;
7588 dslots_jump_total = 0;
7589 dslots_load_filled = 0;
7590 dslots_jump_filled = 0;
7596 current_frame_info = zero_frame_info;
7598 while (string_constants != NULL)
7600 struct string_constant *next;
7602 next = string_constants->next;
7603 free (string_constants);
7604 string_constants = next;
7607 /* Restore the output file if optimizing the GP (optimizing the GP causes
7608 the text to be diverted to a tempfile, so that data decls come before
7609 references to the data). */
7610 if (TARGET_FILE_SWITCHING)
7612 asm_out_file = asm_out_data_file;
7617 /* Expand the epilogue into a bunch of separate insns. */
7620 mips_expand_epilogue ()
7622 HOST_WIDE_INT tsize = current_frame_info.total_size;
7623 rtx tsize_rtx = GEN_INT (tsize);
7624 rtx tmp_rtx = (rtx)0;
7626 if (mips_can_use_return_insn ())
7628 emit_insn (gen_return ());
7632 if (mips_entry && ! mips_can_use_return_insn ())
7635 if (tsize > 32767 && ! TARGET_MIPS16)
7637 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
7638 emit_move_insn (tmp_rtx, tsize_rtx);
7639 tsize_rtx = tmp_rtx;
7644 long orig_tsize = tsize;
7646 if (frame_pointer_needed)
7648 emit_insn (gen_blockage ());
7650 /* On the mips16, the frame pointer is offset from the stack
7651 pointer by current_function_outgoing_args_size. We
7652 account for that by changing tsize. Note that this can
7653 actually make tsize negative. */
7656 tsize -= current_function_outgoing_args_size;
7658 /* If we have a large frame, it's easier to add to $6
7659 than to $sp, since the mips16 has no instruction to
7660 add a register to $sp. */
7661 if (orig_tsize > 32767)
7663 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7665 emit_move_insn (g6_rtx, GEN_INT (tsize));
7666 if (Pmode == DImode)
7667 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7668 hard_frame_pointer_rtx,
7671 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7672 hard_frame_pointer_rtx,
7677 if (tsize && tsize != orig_tsize)
7678 tsize_rtx = GEN_INT (tsize);
7681 if (Pmode == DImode)
7682 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
7684 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
7687 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7688 are going to restore it, then we must emit a blockage insn to
7689 prevent the scheduler from moving the restore out of the epilogue. */
7690 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
7691 && (current_frame_info.mask
7692 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7693 emit_insn (gen_blockage ());
7695 save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
7697 /* In mips16 mode with a large frame, we adjust the stack
7698 pointer before restoring the registers. In this case, we
7699 should always be using a frame pointer, so everything should
7700 have been handled above. */
7701 if (tsize > 32767 && TARGET_MIPS16)
7704 if (current_function_calls_eh_return)
7706 rtx eh_ofs = EH_RETURN_STACKADJ_RTX;
7707 if (Pmode == DImode)
7708 emit_insn (gen_adddi3 (eh_ofs, eh_ofs, tsize_rtx));
7710 emit_insn (gen_addsi3 (eh_ofs, eh_ofs, tsize_rtx));
7714 emit_insn (gen_blockage ());
7716 if (tsize != 0 || current_function_calls_eh_return)
7720 if (Pmode == DImode)
7721 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7724 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7729 /* We need to work around not being able to add a register
7730 to the stack pointer directly. Use register $6 as an
7731 intermediate step. */
7733 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7735 if (Pmode == DImode)
7737 emit_insn (gen_movdi (g6_rtx, stack_pointer_rtx));
7738 emit_insn (gen_adddi3 (g6_rtx, g6_rtx, tsize_rtx));
7739 emit_insn (gen_movdi (stack_pointer_rtx, g6_rtx));
7743 emit_insn (gen_movsi (g6_rtx, stack_pointer_rtx));
7744 emit_insn (gen_addsi3 (g6_rtx, g6_rtx, tsize_rtx));
7745 emit_insn (gen_movsi (stack_pointer_rtx, g6_rtx));
7752 /* The mips16 loads the return address into $7, not $31. */
7753 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
7754 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7755 GP_REG_FIRST + 7)));
7757 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7758 GP_REG_FIRST + 31)));
7761 /* Return nonzero if this function is known to have a null epilogue.
7762 This allows the optimizer to omit jumps to jumps if no stack
7766 mips_can_use_return_insn ()
7768 if (! reload_completed)
7771 if (regs_ever_live[31] || current_function_profile)
7774 /* In mips16 mode, a function which returns a floating point value
7775 needs to arrange to copy the return value into the floating point
7778 && mips16_hard_float
7779 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
7780 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
7782 && (! TARGET_SINGLE_FLOAT
7783 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
7787 if (current_frame_info.initialized)
7788 return current_frame_info.total_size == 0;
7790 return compute_frame_size (get_frame_size ()) == 0;
7793 /* Returns non-zero if X contains a SYMBOL_REF. */
7796 symbolic_expression_p (x)
7799 if (GET_CODE (x) == SYMBOL_REF)
7802 if (GET_CODE (x) == CONST)
7803 return symbolic_expression_p (XEXP (x, 0));
7805 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7806 return symbolic_expression_p (XEXP (x, 0));
7808 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7809 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7810 return (symbolic_expression_p (XEXP (x, 0))
7811 || symbolic_expression_p (XEXP (x, 1)));
7816 /* Choose the section to use for the constant rtx expression X that has
7820 mips_select_rtx_section (mode, x)
7821 enum machine_mode mode;
7822 rtx x ATTRIBUTE_UNUSED;
7826 /* In mips16 mode, the constant table always goes in the same section
7827 as the function, so that constants can be loaded using PC relative
7829 function_section (current_function_decl);
7831 else if (TARGET_EMBEDDED_DATA)
7833 /* For embedded applications, always put constants in read-only data,
7834 in order to reduce RAM usage. */
7835 READONLY_DATA_SECTION ();
7839 /* For hosted applications, always put constants in small data if
7840 possible, as this gives the best performance. */
7842 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7843 && mips_section_threshold > 0)
7844 SMALL_DATA_SECTION ();
7845 else if (flag_pic && symbolic_expression_p (x))
7846 /* Any expression involving a SYMBOL_REF might need a run-time
7847 relocation. (The symbol might be defined in a shared
7848 library loaded at an unexpected base address.) So, we must
7849 put such expressions in the data segment (which is
7850 writable), rather than the text segment (which is
7854 READONLY_DATA_SECTION ();
7858 /* Choose the section to use for DECL. RELOC is true if its value contains
7859 any relocatable expression.
7861 Some of the logic used here needs to be replicated in
7862 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7863 are done correctly. Specifically, at least all symbols assigned
7864 here to rom (.text and/or .rodata) must not be referenced via
7865 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7867 If you need to make a change here, you probably should check
7868 ENCODE_SECTION_INFO to see if it needs a similar change. */
7871 mips_select_section (decl, reloc)
7875 int size = int_size_in_bytes (TREE_TYPE (decl));
7877 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7878 && TREE_CODE (decl) == STRING_CST
7879 && !flag_writable_strings)
7880 /* For embedded position independent code, put constant strings in the
7881 text section, because the data section is limited to 64K in size.
7882 For mips16 code, put strings in the text section so that a PC
7883 relative load instruction can be used to get their address. */
7885 else if (TARGET_EMBEDDED_DATA)
7887 /* For embedded applications, always put an object in read-only data
7888 if possible, in order to reduce RAM usage. */
7890 if (((TREE_CODE (decl) == VAR_DECL
7891 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7892 && DECL_INITIAL (decl)
7893 && (DECL_INITIAL (decl) == error_mark_node
7894 || TREE_CONSTANT (DECL_INITIAL (decl))))
7895 /* Deal with calls from output_constant_def_contents. */
7896 || (TREE_CODE (decl) != VAR_DECL
7897 && (TREE_CODE (decl) != STRING_CST
7898 || !flag_writable_strings)))
7899 && ! (flag_pic && reloc))
7900 READONLY_DATA_SECTION ();
7901 else if (size > 0 && size <= mips_section_threshold)
7902 SMALL_DATA_SECTION ();
7908 /* For hosted applications, always put an object in small data if
7909 possible, as this gives the best performance. */
7911 if (size > 0 && size <= mips_section_threshold)
7912 SMALL_DATA_SECTION ();
7913 else if (((TREE_CODE (decl) == VAR_DECL
7914 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7915 && DECL_INITIAL (decl)
7916 && (DECL_INITIAL (decl) == error_mark_node
7917 || TREE_CONSTANT (DECL_INITIAL (decl))))
7918 /* Deal with calls from output_constant_def_contents. */
7919 || (TREE_CODE (decl) != VAR_DECL
7920 && (TREE_CODE (decl) != STRING_CST
7921 || !flag_writable_strings)))
7922 && ! (flag_pic && reloc))
7923 READONLY_DATA_SECTION ();
7929 #ifdef MIPS_ABI_DEFAULT
7931 /* Support functions for the 64 bit ABI. */
7933 /* Return register to use for a function return value with VALTYPE for function
7937 mips_function_value (valtype, func)
7939 tree func ATTRIBUTE_UNUSED;
7941 int reg = GP_RETURN;
7942 enum machine_mode mode = TYPE_MODE (valtype);
7943 enum mode_class mclass = GET_MODE_CLASS (mode);
7944 int unsignedp = TREE_UNSIGNED (valtype);
7946 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7947 just as PROMOTE_MODE does. */
7948 mode = promote_mode (valtype, mode, &unsignedp, 1);
7950 if (mclass == MODE_FLOAT)
7952 if (TARGET_SINGLE_FLOAT
7953 && (mclass == MODE_FLOAT
7954 ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
7960 else if (mclass == MODE_COMPLEX_FLOAT)
7964 else if (mode == SCmode)
7966 /* When FP registers are 32 bits, we can't directly reference
7967 the odd numbered ones, so let's make a pair of evens. */
7969 enum machine_mode cmode = TYPE_MODE (TREE_TYPE (valtype));
7971 return gen_rtx_PARALLEL
7974 gen_rtx_EXPR_LIST (VOIDmode,
7978 gen_rtx_EXPR_LIST (VOIDmode,
7987 else if (TREE_CODE (valtype) == RECORD_TYPE
7988 && mips_abi != ABI_32
7989 && mips_abi != ABI_O64
7990 && mips_abi != ABI_EABI)
7992 /* A struct with only one or two floating point fields is returned in
7993 the floating point registers. */
7994 tree field, fields[2];
7997 for (i = 0, field = TYPE_FIELDS (valtype); field;
7998 field = TREE_CHAIN (field))
8000 if (TREE_CODE (field) != FIELD_DECL)
8003 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
8006 fields[i++] = field;
8009 /* Must check i, so that we reject structures with no elements. */
8014 /* The structure has DImode, but we don't allow DImode values
8015 in FP registers, so we use a PARALLEL even though it isn't
8016 strictly necessary. */
8017 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
8019 return gen_rtx_PARALLEL
8022 gen_rtx_EXPR_LIST (VOIDmode,
8023 gen_rtx_REG (field_mode,
8030 enum machine_mode first_mode
8031 = TYPE_MODE (TREE_TYPE (fields[0]));
8032 enum machine_mode second_mode
8033 = TYPE_MODE (TREE_TYPE (fields[1]));
8034 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
8035 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
8037 return gen_rtx_PARALLEL
8040 gen_rtx_EXPR_LIST (VOIDmode,
8041 gen_rtx_REG (first_mode,
8043 GEN_INT (first_offset)),
8044 gen_rtx_EXPR_LIST (VOIDmode,
8045 gen_rtx_REG (second_mode,
8047 GEN_INT (second_offset))));
8052 return gen_rtx_REG (mode, reg);
8056 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
8057 nonzero when an argument must be passed by reference. */
8060 function_arg_pass_by_reference (cum, mode, type, named)
8061 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
8062 enum machine_mode mode;
8064 int named ATTRIBUTE_UNUSED;
8068 /* We must pass by reference if we would be both passing in registers
8069 and the stack. This is because any subsequent partial arg would be
8070 handled incorrectly in this case.
8072 ??? This is really a kludge. We should either fix GCC so that such
8073 a situation causes an abort and then do something in the MIPS port
8074 to prevent it, or add code to function.c to properly handle the case. */
8075 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
8076 here hopefully is not relevant to mips_va_arg. */
8077 if (cum && MUST_PASS_IN_STACK (mode, type)
8078 && mips_abi != ABI_MEABI)
8080 /* Don't pass the actual CUM to FUNCTION_ARG, because we would
8081 get double copies of any offsets generated for small structs
8082 passed in registers. */
8083 CUMULATIVE_ARGS temp;
8085 if (FUNCTION_ARG (temp, mode, type, named) != 0)
8089 /* Otherwise, we only do this if EABI is selected. */
8090 if (mips_abi != ABI_EABI)
8093 /* ??? How should SCmode be handled? */
8094 if (type == NULL_TREE || mode == DImode || mode == DFmode)
8097 size = int_size_in_bytes (type);
8098 return size == -1 || size > UNITS_PER_WORD;
8101 /* This function returns the register class required for a secondary
8102 register when copying between one of the registers in CLASS, and X,
8103 using MODE. If IN_P is nonzero, the copy is going from X to the
8104 register, otherwise the register is the source. A return value of
8105 NO_REGS means that no secondary register is required. */
8108 mips_secondary_reload_class (class, mode, x, in_p)
8109 enum reg_class class;
8110 enum machine_mode mode;
8114 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
8118 if (GET_CODE (x) == SIGN_EXTEND)
8124 /* We may be called with reg_renumber NULL from regclass.
8125 ??? This is probably a bug. */
8127 regno = true_regnum (x);
8130 while (GET_CODE (x) == SUBREG)
8132 off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
8133 GET_MODE (SUBREG_REG (x)),
8139 if (GET_CODE (x) == REG)
8140 regno = REGNO (x) + off;
8144 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
8145 regno = true_regnum (x);
8147 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8149 /* We always require a general register when copying anything to
8150 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8151 to a general register, or when copying from register 0. */
8152 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
8155 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8156 ? NO_REGS : gr_regs);
8157 else if (regno == HILO_REGNUM)
8160 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8161 ? NO_REGS : gr_regs);
8163 /* Copying from HI or LO to anywhere other than a general register
8164 requires a general register. */
8165 if (class == HI_REG || class == LO_REG || class == MD_REGS)
8167 if (TARGET_MIPS16 && in_p)
8169 /* We can't really copy to HI or LO at all in mips16 mode. */
8172 return gp_reg_p ? NO_REGS : gr_regs;
8174 if (MD_REG_P (regno))
8176 if (TARGET_MIPS16 && ! in_p)
8178 /* We can't really copy to HI or LO at all in mips16 mode. */
8181 return class == gr_regs ? NO_REGS : gr_regs;
8184 /* We can only copy a value to a condition code register from a
8185 floating point register, and even then we require a scratch
8186 floating point register. We can only copy a value out of a
8187 condition code register into a general register. */
8188 if (class == ST_REGS)
8192 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
8194 if (ST_REG_P (regno))
8198 return class == GR_REGS ? NO_REGS : GR_REGS;
8201 /* In mips16 mode, going between memory and anything but M16_REGS
8202 requires an M16_REG. */
8205 if (class != M16_REGS && class != M16_NA_REGS)
8213 /* The stack pointer isn't a valid operand to an add instruction,
8214 so we need to load it into M16_REGS first. This can happen as
8215 a result of register elimination and form_sum converting
8216 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8217 need an extra register if the dest is the same as the other
8218 register. In that case, we can't fix the problem by loading SP
8219 into the dest first. */
8220 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
8221 && GET_CODE (XEXP (x, 1)) == REG
8222 && (XEXP (x, 0) == stack_pointer_rtx
8223 || XEXP (x, 1) == stack_pointer_rtx))
8224 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
8226 if (class == M16_REGS || class == M16_NA_REGS)
8235 /* For each mips16 function which refers to GP relative symbols, we
8236 use a pseudo register, initialized at the start of the function, to
8237 hold the $gp value. */
8240 mips16_gp_pseudo_reg ()
8242 if (mips16_gp_pseudo_rtx == NULL_RTX)
8247 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8248 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
8250 /* We want to initialize this to a value which gcc will believe
8252 const_gp = gen_rtx (CONST, Pmode,
8253 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
8256 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
8257 insn = gen_sequence ();
8260 push_topmost_sequence ();
8261 /* We need to emit the initialization after the FUNCTION_BEG
8262 note, so that it will be integrated. */
8263 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8264 if (GET_CODE (scan) == NOTE
8265 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
8267 if (scan == NULL_RTX)
8268 scan = get_insns ();
8269 insn = emit_insn_after (insn, scan);
8270 pop_topmost_sequence ();
8273 return mips16_gp_pseudo_rtx;
8276 /* Return an RTX which represents the signed 16 bit offset from the
8277 $gp register for the given symbol. This is only used on the
8281 mips16_gp_offset (sym)
8286 if (GET_CODE (sym) != SYMBOL_REF
8287 || ! SYMBOL_REF_FLAG (sym))
8290 /* We use a special identifier to represent the value of the gp
8292 gp = get_identifier ("__mips16_gp_value");
8294 return gen_rtx (CONST, Pmode,
8295 gen_rtx (MINUS, Pmode, sym,
8296 gen_rtx (SYMBOL_REF, Pmode,
8297 IDENTIFIER_POINTER (gp))));
8300 /* Return nonzero if the given RTX represents a signed 16 bit offset
8301 from the $gp register. */
8304 mips16_gp_offset_p (x)
8307 if (GET_CODE (x) == CONST)
8310 /* It's OK to add a small integer value to a gp offset. */
8311 if (GET_CODE (x) == PLUS)
8313 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8314 && SMALL_INT (XEXP (x, 1)))
8315 return mips16_gp_offset_p (XEXP (x, 0));
8316 if (GET_CODE (XEXP (x, 0)) == CONST_INT
8317 && SMALL_INT (XEXP (x, 0)))
8318 return mips16_gp_offset_p (XEXP (x, 1));
8322 /* Make sure it is in the form SYM - __mips16_gp_value. */
8323 return (GET_CODE (x) == MINUS
8324 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
8325 && SYMBOL_REF_FLAG (XEXP (x, 0))
8326 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8327 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
8330 /* Output a GP offset. We don't want to print the subtraction of
8331 __mips16_gp_value; it is implicitly represented by the %gprel which
8332 should have been printed by the caller. */
8335 mips16_output_gp_offset (file, x)
8339 if (GET_CODE (x) == CONST)
8342 if (GET_CODE (x) == PLUS)
8344 mips16_output_gp_offset (file, XEXP (x, 0));
8346 mips16_output_gp_offset (file, XEXP (x, 1));
8350 if (GET_CODE (x) == MINUS
8351 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8352 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
8354 mips16_output_gp_offset (file, XEXP (x, 0));
8358 output_addr_const (file, x);
8361 /* Return nonzero if a constant should not be output until after the
8362 function. This is true of most string constants, so that we can
8363 use a more efficient PC relative reference. However, a static
8364 inline function may never call assemble_function_end to write out
8365 the constant pool, so don't try to postpone the constant in that
8368 ??? It's really a bug that a static inline function can put stuff
8369 in the constant pool even if the function itself is not output.
8371 We record which string constants we've seen, so that we know which
8372 ones might use the more efficient reference. */
8375 mips16_constant_after_function_p (x)
8378 if (TREE_CODE (x) == STRING_CST
8379 && ! flag_writable_strings
8380 && current_function_decl != 0
8381 && ! DECL_DEFER_OUTPUT (current_function_decl)
8382 && ! (DECL_INLINE (current_function_decl)
8383 && ((! TREE_PUBLIC (current_function_decl)
8384 && ! TREE_ADDRESSABLE (current_function_decl)
8385 && ! flag_keep_inline_functions)
8386 || DECL_EXTERNAL (current_function_decl))))
8388 struct string_constant *n;
8390 n = (struct string_constant *) xmalloc (sizeof *n);
8391 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
8392 n->next = string_constants;
8393 string_constants = n;
8401 /* Validate a constant for the mips16. This rejects general symbolic
8402 addresses, which must be loaded from memory. If ADDR is nonzero,
8403 this should reject anything which is not a legal address. If
8404 ADDEND is nonzero, this is being added to something else. */
8407 mips16_constant (x, mode, addr, addend)
8409 enum machine_mode mode;
8413 while (GET_CODE (x) == CONST)
8416 switch (GET_CODE (x))
8422 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
8423 && mips16_constant (XEXP (x, 1), mode, addr, 1));
8426 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8428 if (CONSTANT_POOL_ADDRESS_P (x))
8431 /* If we aren't looking for a memory address, we can accept a GP
8432 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8433 knows how to handle this. We can always accept a string
8434 constant, which is the other case in which SYMBOL_REF_FLAG
8438 && SYMBOL_REF_FLAG (x)
8439 && mode == (enum machine_mode) Pmode)
8442 /* We can accept a string constant, which will have
8443 SYMBOL_REF_FLAG set but must be recognized by name to
8444 distinguish from a GP accessible symbol. The name of a
8445 string constant will have been generated by
8446 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8447 if (SYMBOL_REF_FLAG (x))
8449 const char *name = XSTR (x, 0);
8451 return (name[0] == '*'
8452 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
8453 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
8459 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8464 if (addr && ! addend)
8466 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
8469 /* We need to treat $gp as a legitimate constant, because
8470 mips16_gp_pseudo_reg assumes that. */
8471 return REGNO (x) == GP_REG_FIRST + 28;
8475 /* Write out code to move floating point arguments in or out of
8476 general registers. Output the instructions to FILE. FP_CODE is
8477 the code describing which arguments are present (see the comment at
8478 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8479 we are copying from the floating point registers. */
8482 mips16_fp_args (file, fp_code, from_fp_p)
8491 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8492 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8499 gparg = GP_ARG_FIRST;
8500 fparg = FP_ARG_FIRST;
8501 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8505 if ((fparg & 1) != 0)
8507 fprintf (file, "\t%s\t%s,%s\n", s,
8508 reg_names[gparg], reg_names[fparg]);
8510 else if ((f & 3) == 2)
8513 fprintf (file, "\td%s\t%s,%s\n", s,
8514 reg_names[gparg], reg_names[fparg]);
8517 if ((fparg & 1) != 0)
8519 if (TARGET_BIG_ENDIAN)
8520 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8521 reg_names[gparg], reg_names[fparg + 1], s,
8522 reg_names[gparg + 1], reg_names[fparg]);
8524 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8525 reg_names[gparg], reg_names[fparg], s,
8526 reg_names[gparg + 1], reg_names[fparg + 1]);
8539 /* Build a mips16 function stub. This is used for functions which
8540 take aruments in the floating point registers. It is 32 bit code
8541 that moves the floating point args into the general registers, and
8542 then jumps to the 16 bit code. */
8545 build_mips16_function_stub (file)
8549 char *secname, *stubname;
8550 tree stubid, stubdecl;
8554 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8555 secname = (char *) alloca (strlen (fnname) + 20);
8556 sprintf (secname, ".mips16.fn.%s", fnname);
8557 stubname = (char *) alloca (strlen (fnname) + 20);
8558 sprintf (stubname, "__fn_stub_%s", fnname);
8559 stubid = get_identifier (stubname);
8560 stubdecl = build_decl (FUNCTION_DECL, stubid,
8561 build_function_type (void_type_node, NULL_TREE));
8562 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8564 fprintf (file, "\t# Stub function for %s (", current_function_name);
8566 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8568 fprintf (file, "%s%s",
8569 need_comma ? ", " : "",
8570 (f & 3) == 1 ? "float" : "double");
8573 fprintf (file, ")\n");
8575 fprintf (file, "\t.set\tnomips16\n");
8576 function_section (stubdecl);
8577 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8579 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8580 within a .ent, and we can not emit another .ent. */
8581 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8582 fputs ("\t.ent\t", file);
8583 assemble_name (file, stubname);
8587 assemble_name (file, stubname);
8588 fputs (":\n", file);
8590 /* We don't want the assembler to insert any nops here. */
8591 fprintf (file, "\t.set\tnoreorder\n");
8593 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8595 fprintf (asm_out_file, "\t.set\tnoat\n");
8596 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8597 assemble_name (file, fnname);
8598 fprintf (file, "\n");
8599 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8600 fprintf (asm_out_file, "\t.set\tat\n");
8602 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8603 with one of the mfc1 instructions, because the result is not
8604 available for one instruction, so if the very first instruction
8605 in the function refers to the register, it will see the wrong
8607 fprintf (file, "\tnop\n");
8609 fprintf (file, "\t.set\treorder\n");
8611 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8612 fputs ("\t.end\t", file);
8613 assemble_name (file, stubname);
8617 fprintf (file, "\t.set\tmips16\n");
8619 function_section (current_function_decl);
8622 /* We keep a list of functions for which we have already built stubs
8623 in build_mips16_call_stub. */
8627 struct mips16_stub *next;
8632 static struct mips16_stub *mips16_stubs;
8634 /* Build a call stub for a mips16 call. A stub is needed if we are
8635 passing any floating point values which should go into the floating
8636 point registers. If we are, and the call turns out to be to a 32
8637 bit function, the stub will be used to move the values into the
8638 floating point registers before calling the 32 bit function. The
8639 linker will magically adjust the function call to either the 16 bit
8640 function or the 32 bit stub, depending upon where the function call
8641 is actually defined.
8643 Similarly, we need a stub if the return value might come back in a
8644 floating point register.
8646 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8647 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8648 is the code built by function_arg. This function returns a nonzero
8649 value if it builds the call instruction itself. */
8652 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
8661 char *secname, *stubname;
8662 struct mips16_stub *l;
8663 tree stubid, stubdecl;
8667 /* We don't need to do anything if we aren't in mips16 mode, or if
8668 we were invoked with the -msoft-float option. */
8669 if (! TARGET_MIPS16 || ! mips16_hard_float)
8672 /* Figure out whether the value might come back in a floating point
8674 fpret = (retval != 0
8675 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8676 && (! TARGET_SINGLE_FLOAT
8677 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
8679 /* We don't need to do anything if there were no floating point
8680 arguments and the value will not be returned in a floating point
8682 if (fp_code == 0 && ! fpret)
8685 if (GET_CODE (fnmem) != MEM)
8687 fn = XEXP (fnmem, 0);
8689 /* We don't need to do anything if this is a call to a special
8690 mips16 support function. */
8691 if (GET_CODE (fn) == SYMBOL_REF
8692 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8695 /* This code will only work for o32 and o64 abis. The other ABI's
8696 require more sophisticated support. */
8697 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8700 /* We can only handle SFmode and DFmode floating point return
8702 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8705 /* If we're calling via a function pointer, then we must always call
8706 via a stub. There are magic stubs provided in libgcc.a for each
8707 of the required cases. Each of them expects the function address
8708 to arrive in register $2. */
8710 if (GET_CODE (fn) != SYMBOL_REF)
8714 rtx stub_fn, stub_mem, insn;
8716 /* ??? If this code is modified to support other ABI's, we need
8717 to handle PARALLEL return values here. */
8719 sprintf (buf, "__mips16_call_stub_%s%d",
8721 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8724 id = get_identifier (buf);
8725 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8726 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
8728 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8730 if (retval == NULL_RTX)
8731 insn = gen_call_internal0 (stub_mem, arg_size,
8732 gen_rtx (REG, SImode,
8733 GP_REG_FIRST + 31));
8735 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
8736 gen_rtx (REG, SImode,
8737 GP_REG_FIRST + 31));
8738 insn = emit_call_insn (insn);
8740 /* Put the register usage information on the CALL. */
8741 if (GET_CODE (insn) != CALL_INSN)
8743 CALL_INSN_FUNCTION_USAGE (insn) =
8744 gen_rtx (EXPR_LIST, VOIDmode,
8745 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
8746 CALL_INSN_FUNCTION_USAGE (insn));
8748 /* If we are handling a floating point return value, we need to
8749 save $18 in the function prologue. Putting a note on the
8750 call will mean that regs_ever_live[$18] will be true if the
8751 call is not eliminated, and we can check that in the prologue
8754 CALL_INSN_FUNCTION_USAGE (insn) =
8755 gen_rtx (EXPR_LIST, VOIDmode,
8756 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8757 CALL_INSN_FUNCTION_USAGE (insn));
8759 /* Return 1 to tell the caller that we've generated the call
8764 /* We know the function we are going to call. If we have already
8765 built a stub, we don't need to do anything further. */
8767 fnname = XSTR (fn, 0);
8768 for (l = mips16_stubs; l != NULL; l = l->next)
8769 if (strcmp (l->name, fnname) == 0)
8774 /* Build a special purpose stub. When the linker sees a
8775 function call in mips16 code, it will check where the target
8776 is defined. If the target is a 32 bit call, the linker will
8777 search for the section defined here. It can tell which
8778 symbol this section is associated with by looking at the
8779 relocation information (the name is unreliable, since this
8780 might be a static function). If such a section is found, the
8781 linker will redirect the call to the start of the magic
8784 If the function does not return a floating point value, the
8785 special stub section is named
8788 If the function does return a floating point value, the stub
8790 .mips16.call.fp.FNNAME
8793 secname = (char *) alloca (strlen (fnname) + 40);
8794 sprintf (secname, ".mips16.call.%s%s",
8797 stubname = (char *) alloca (strlen (fnname) + 20);
8798 sprintf (stubname, "__call_stub_%s%s",
8801 stubid = get_identifier (stubname);
8802 stubdecl = build_decl (FUNCTION_DECL, stubid,
8803 build_function_type (void_type_node, NULL_TREE));
8804 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8806 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8808 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8812 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8814 fprintf (asm_out_file, "%s%s",
8815 need_comma ? ", " : "",
8816 (f & 3) == 1 ? "float" : "double");
8819 fprintf (asm_out_file, ")\n");
8821 fprintf (asm_out_file, "\t.set\tnomips16\n");
8822 assemble_start_function (stubdecl, stubname);
8824 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8825 fputs ("\t.ent\t", asm_out_file);
8826 assemble_name (asm_out_file, stubname);
8827 fputs ("\n", asm_out_file);
8829 assemble_name (asm_out_file, stubname);
8830 fputs (":\n", asm_out_file);
8833 /* We build the stub code by hand. That's the only way we can
8834 do it, since we can't generate 32 bit code during a 16 bit
8837 /* We don't want the assembler to insert any nops here. */
8838 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8840 mips16_fp_args (asm_out_file, fp_code, 0);
8844 fprintf (asm_out_file, "\t.set\tnoat\n");
8845 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8847 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8848 fprintf (asm_out_file, "\t.set\tat\n");
8849 /* Unfortunately, we can't fill the jump delay slot. We
8850 can't fill with one of the mtc1 instructions, because the
8851 result is not available for one instruction, so if the
8852 very first instruction in the function refers to the
8853 register, it will see the wrong value. */
8854 fprintf (asm_out_file, "\tnop\n");
8858 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8859 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8860 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8861 /* As above, we can't fill the delay slot. */
8862 fprintf (asm_out_file, "\tnop\n");
8863 if (GET_MODE (retval) == SFmode)
8864 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8865 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8868 if (TARGET_BIG_ENDIAN)
8870 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8871 reg_names[GP_REG_FIRST + 2],
8872 reg_names[FP_REG_FIRST + 1]);
8873 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8874 reg_names[GP_REG_FIRST + 3],
8875 reg_names[FP_REG_FIRST + 0]);
8879 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8880 reg_names[GP_REG_FIRST + 2],
8881 reg_names[FP_REG_FIRST + 0]);
8882 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8883 reg_names[GP_REG_FIRST + 3],
8884 reg_names[FP_REG_FIRST + 1]);
8887 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8888 /* As above, we can't fill the delay slot. */
8889 fprintf (asm_out_file, "\tnop\n");
8892 fprintf (asm_out_file, "\t.set\treorder\n");
8894 #ifdef ASM_DECLARE_FUNCTION_SIZE
8895 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8898 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8899 fputs ("\t.end\t", asm_out_file);
8900 assemble_name (asm_out_file, stubname);
8901 fputs ("\n", asm_out_file);
8904 fprintf (asm_out_file, "\t.set\tmips16\n");
8906 /* Record this stub. */
8907 l = (struct mips16_stub *) xmalloc (sizeof *l);
8908 l->name = xstrdup (fnname);
8910 l->next = mips16_stubs;
8914 /* If we expect a floating point return value, but we've built a
8915 stub which does not expect one, then we're in trouble. We can't
8916 use the existing stub, because it won't handle the floating point
8917 value. We can't build a new stub, because the linker won't know
8918 which stub to use for the various calls in this object file.
8919 Fortunately, this case is illegal, since it means that a function
8920 was declared in two different ways in a single compilation. */
8921 if (fpret && ! l->fpret)
8922 error ("can not handle inconsistent calls to `%s'", fnname);
8924 /* If we are calling a stub which handles a floating point return
8925 value, we need to arrange to save $18 in the prologue. We do
8926 this by marking the function call as using the register. The
8927 prologue will later see that it is used, and emit code to save
8934 if (retval == NULL_RTX)
8935 insn = gen_call_internal0 (fnmem, arg_size,
8936 gen_rtx (REG, SImode,
8937 GP_REG_FIRST + 31));
8939 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
8940 gen_rtx (REG, SImode,
8941 GP_REG_FIRST + 31));
8942 insn = emit_call_insn (insn);
8944 if (GET_CODE (insn) != CALL_INSN)
8947 CALL_INSN_FUNCTION_USAGE (insn) =
8948 gen_rtx (EXPR_LIST, VOIDmode,
8949 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8950 CALL_INSN_FUNCTION_USAGE (insn));
8952 /* Return 1 to tell the caller that we've generated the call
8957 /* Return 0 to let the caller generate the call insn. */
8961 /* This function looks through the code for a function, and tries to
8962 optimize the usage of the $gp register. We arrange to copy $gp
8963 into a pseudo-register, and then let gcc's normal reload handling
8964 deal with the pseudo-register. Unfortunately, if reload choose to
8965 put the pseudo-register into a call-clobbered register, it will
8966 emit saves and restores for that register around any function
8967 calls. We don't need the saves, and it's faster to copy $gp than
8968 to do an actual restore. ??? This still means that we waste a
8971 This is an optimization, and the code which gcc has actually
8972 generated is correct, so we do not need to catch all cases. */
8975 mips16_optimize_gp (first)
8978 rtx gpcopy, slot, insn;
8980 /* Look through the instructions. Set GPCOPY to the register which
8981 holds a copy of $gp. Set SLOT to the stack slot where it is
8982 saved. If we find an instruction which sets GPCOPY to anything
8983 other than $gp or SLOT, then we can't use it. If we find an
8984 instruction which sets SLOT to anything other than GPCOPY, we
8989 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8993 if (! INSN_P (insn))
8996 set = PATTERN (insn);
8998 /* We know that all references to memory will be inside a SET,
8999 because there is no other way to access memory on the mips16.
9000 We don't have to worry about a PARALLEL here, because the
9001 mips.md file will never generate them for memory references. */
9002 if (GET_CODE (set) != SET)
9005 if (gpcopy == NULL_RTX
9006 && GET_CODE (SET_SRC (set)) == CONST
9007 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
9008 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
9009 && GET_CODE (SET_DEST (set)) == REG
9010 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
9011 gpcopy = SET_DEST (set);
9012 else if (slot == NULL_RTX
9013 && gpcopy != NULL_RTX
9014 && GET_CODE (SET_DEST (set)) == MEM
9015 && GET_CODE (SET_SRC (set)) == REG
9016 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
9017 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
9021 offset = const0_rtx;
9022 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9023 if (GET_CODE (base) == REG
9024 && (REGNO (base) == STACK_POINTER_REGNUM
9025 || REGNO (base) == FRAME_POINTER_REGNUM))
9026 slot = SET_DEST (set);
9028 else if (gpcopy != NULL_RTX
9029 && (GET_CODE (SET_DEST (set)) == REG
9030 || GET_CODE (SET_DEST (set)) == SUBREG)
9031 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
9032 && (GET_CODE (SET_DEST (set)) != REG
9033 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
9034 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode
9035 || ((GET_CODE (SET_SRC (set)) != CONST
9036 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
9037 || (REGNO (XEXP (SET_SRC (set), 0))
9038 != GP_REG_FIRST + 28))
9039 && ! rtx_equal_p (SET_SRC (set), slot))))
9041 else if (slot != NULL_RTX
9042 && GET_CODE (SET_DEST (set)) == MEM
9043 && rtx_equal_p (SET_DEST (set), slot)
9044 && (GET_CODE (SET_SRC (set)) != REG
9045 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
9049 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
9050 different optimization. Any time we find a copy of $28 into a
9051 register, followed by an add of a symbol_ref to that register, we
9052 convert it to load the value from the constant table instead.
9053 The copy and add will take six bytes, just as the load and
9054 constant table entry will take six bytes. However, it is
9055 possible that the constant table entry will be shared.
9057 This could be a peephole optimization, but I don't know if the
9058 peephole code can call force_const_mem.
9060 Using the same register for the copy of $28 and the add of the
9061 symbol_ref is actually pretty likely, since the add instruction
9062 requires the destination and the first addend to be the same
9065 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
9069 /* This optimization is only reasonable if the constant table
9070 entries are only 4 bytes. */
9071 if (Pmode != SImode)
9074 for (insn = first; insn != NULL_RTX; insn = next)
9081 next = NEXT_INSN (next);
9083 while (next != NULL_RTX
9084 && (GET_CODE (next) == NOTE
9085 || (GET_CODE (next) == INSN
9086 && (GET_CODE (PATTERN (next)) == USE
9087 || GET_CODE (PATTERN (next)) == CLOBBER))));
9089 if (next == NULL_RTX)
9092 if (! INSN_P (insn))
9095 if (! INSN_P (next))
9098 set1 = PATTERN (insn);
9099 if (GET_CODE (set1) != SET)
9101 set2 = PATTERN (next);
9102 if (GET_CODE (set2) != SET)
9105 if (GET_CODE (SET_DEST (set1)) == REG
9106 && GET_CODE (SET_SRC (set1)) == CONST
9107 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
9108 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
9109 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
9110 && GET_CODE (SET_SRC (set2)) == PLUS
9111 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
9112 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
9113 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
9117 /* We've found a case we can change to load from the
9120 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
9121 if (GET_CODE (sym) != SYMBOL_REF)
9123 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
9124 force_const_mem (Pmode, sym)),
9127 PUT_CODE (insn, NOTE);
9128 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9129 NOTE_SOURCE_FILE (insn) = 0;
9131 PUT_CODE (next, NOTE);
9132 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
9133 NOTE_SOURCE_FILE (next) = 0;
9140 /* We can safely remove all assignments to SLOT from GPCOPY, and
9141 replace all assignments from SLOT to GPCOPY with assignments from
9144 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9148 if (! INSN_P (insn))
9151 set = PATTERN (insn);
9152 if (GET_CODE (set) != SET
9153 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode)
9156 if (GET_CODE (SET_DEST (set)) == MEM
9157 && rtx_equal_p (SET_DEST (set), slot)
9158 && GET_CODE (SET_SRC (set)) == REG
9159 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
9161 PUT_CODE (insn, NOTE);
9162 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9163 NOTE_SOURCE_FILE (insn) = 0;
9165 else if (GET_CODE (SET_DEST (set)) == REG
9166 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
9167 && GET_CODE (SET_SRC (set)) == MEM
9168 && rtx_equal_p (SET_SRC (set), slot))
9170 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
9171 gen_rtx (CONST, Pmode,
9172 gen_rtx (REG, Pmode,
9173 GP_REG_FIRST + 28))),
9175 PUT_CODE (insn, NOTE);
9176 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9177 NOTE_SOURCE_FILE (insn) = 0;
9182 /* We keep a list of constants we which we have to add to internal
9183 constant tables in the middle of large functions. */
9187 struct constant *next;
9190 enum machine_mode mode;
9193 /* Add a constant to the list in *PCONSTANTS. */
9196 add_constant (pconstants, val, mode)
9197 struct constant **pconstants;
9199 enum machine_mode mode;
9203 for (c = *pconstants; c != NULL; c = c->next)
9204 if (mode == c->mode && rtx_equal_p (val, c->value))
9207 c = (struct constant *) xmalloc (sizeof *c);
9210 c->label = gen_label_rtx ();
9211 c->next = *pconstants;
9216 /* Dump out the constants in CONSTANTS after INSN. */
9219 dump_constants (constants, insn)
9220 struct constant *constants;
9231 struct constant *next;
9233 switch (GET_MODE_SIZE (c->mode))
9240 insn = emit_insn_after (gen_align_2 (), insn);
9245 insn = emit_insn_after (gen_align_4 (), insn);
9250 insn = emit_insn_after (gen_align_8 (), insn);
9255 insn = emit_label_after (c->label, insn);
9260 r = gen_consttable_qi (c->value);
9263 r = gen_consttable_hi (c->value);
9266 r = gen_consttable_si (c->value);
9269 r = gen_consttable_sf (c->value);
9272 r = gen_consttable_di (c->value);
9275 r = gen_consttable_df (c->value);
9281 insn = emit_insn_after (r, insn);
9288 emit_barrier_after (insn);
9291 /* Find the symbol in an address expression. */
9294 mips_find_symbol (addr)
9297 if (GET_CODE (addr) == MEM)
9298 addr = XEXP (addr, 0);
9299 while (GET_CODE (addr) == CONST)
9300 addr = XEXP (addr, 0);
9301 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
9303 if (GET_CODE (addr) == PLUS)
9307 l1 = mips_find_symbol (XEXP (addr, 0));
9308 l2 = mips_find_symbol (XEXP (addr, 1));
9309 if (l1 != NULL_RTX && l2 == NULL_RTX)
9311 else if (l1 == NULL_RTX && l2 != NULL_RTX)
9317 /* Exported to toplev.c.
9319 Do a final pass over the function, just before delayed branch
9323 machine_dependent_reorg (first)
9326 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
9328 struct constant *constants;
9330 if (! TARGET_MIPS16)
9333 /* If $gp is used, try to remove stores, and replace loads with
9336 mips16_optimize_gp (first);
9338 /* Scan the function looking for PC relative loads which may be out
9339 of range. All such loads will either be from the constant table,
9340 or be getting the address of a constant string. If the size of
9341 the function plus the size of the constant table is less than
9342 0x8000, then all loads are in range. */
9345 for (insn = first; insn; insn = NEXT_INSN (insn))
9347 insns_len += get_attr_length (insn);
9349 /* ??? We put switch tables in .text, but we don't define
9350 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9351 compute their lengths correctly. */
9352 if (GET_CODE (insn) == JUMP_INSN)
9356 body = PATTERN (insn);
9357 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9358 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9359 * GET_MODE_SIZE (GET_MODE (body)));
9360 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
9364 /* Store the original value of insns_len in current_frame_info, so
9365 that simple_memory_operand can look at it. */
9366 current_frame_info.insns_len = insns_len;
9368 pool_size = get_pool_size ();
9369 if (insns_len + pool_size + mips_string_length < 0x8000)
9372 /* Loop over the insns and figure out what the maximum internal pool
9374 max_internal_pool_size = 0;
9375 for (insn = first; insn; insn = NEXT_INSN (insn))
9377 if (GET_CODE (insn) == INSN
9378 && GET_CODE (PATTERN (insn)) == SET)
9382 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9383 if (src == NULL_RTX)
9385 if (CONSTANT_POOL_ADDRESS_P (src))
9386 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
9387 else if (SYMBOL_REF_FLAG (src))
9388 max_internal_pool_size += GET_MODE_SIZE (Pmode);
9394 first_constant_ref = -1;
9396 for (insn = first; insn; insn = NEXT_INSN (insn))
9398 if (GET_CODE (insn) == INSN
9399 && GET_CODE (PATTERN (insn)) == SET)
9402 enum machine_mode mode = VOIDmode;
9405 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9406 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
9408 /* ??? This is very conservative, which means that we
9409 will generate too many copies of the constant table.
9410 The only solution would seem to be some form of
9412 if (((insns_len - addr)
9413 + max_internal_pool_size
9414 + get_pool_offset (src))
9417 val = get_pool_constant (src);
9418 mode = get_pool_mode (src);
9420 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
9422 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
9424 /* Including all of mips_string_length is conservative,
9425 and so is including all of max_internal_pool_size. */
9426 if (((insns_len - addr)
9427 + max_internal_pool_size
9429 + mips_string_length)
9435 max_internal_pool_size -= Pmode;
9438 if (val != NULL_RTX)
9442 /* This PC relative load is out of range. ??? In the
9443 case of a string constant, we are only guessing that
9444 it is range, since we don't know the offset of a
9445 particular string constant. */
9447 lab = add_constant (&constants, val, mode);
9448 newsrc = gen_rtx (MEM, mode,
9449 gen_rtx (LABEL_REF, VOIDmode, lab));
9450 RTX_UNCHANGING_P (newsrc) = 1;
9451 PATTERN (insn) = gen_rtx (SET, VOIDmode,
9452 SET_DEST (PATTERN (insn)),
9454 INSN_CODE (insn) = -1;
9456 if (first_constant_ref < 0)
9457 first_constant_ref = addr;
9461 addr += get_attr_length (insn);
9463 /* ??? We put switch tables in .text, but we don't define
9464 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9465 compute their lengths correctly. */
9466 if (GET_CODE (insn) == JUMP_INSN)
9470 body = PATTERN (insn);
9471 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9472 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9473 * GET_MODE_SIZE (GET_MODE (body)));
9474 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
9477 if (GET_CODE (insn) == BARRIER)
9479 /* Output any constants we have accumulated. Note that we
9480 don't need to change ADDR, since its only use is
9481 subtraction from INSNS_LEN, and both would be changed by
9483 ??? If the instructions up to the next barrier reuse a
9484 constant, it would often be better to continue
9486 if (constants != NULL)
9487 dump_constants (constants, insn);
9489 first_constant_ref = -1;
9492 if (constants != NULL
9493 && (NEXT_INSN (insn) == NULL
9494 || (first_constant_ref >= 0
9495 && (((addr - first_constant_ref)
9496 + 2 /* for alignment */
9497 + 2 /* for a short jump insn */
9501 /* If we haven't had a barrier within 0x8000 bytes of a
9502 constant reference or we are at the end of the function,
9503 emit a barrier now. */
9505 rtx label, jump, barrier;
9507 label = gen_label_rtx ();
9508 jump = emit_jump_insn_after (gen_jump (label), insn);
9509 JUMP_LABEL (jump) = label;
9510 LABEL_NUSES (label) = 1;
9511 barrier = emit_barrier_after (jump);
9512 emit_label_after (label, barrier);
9513 first_constant_ref = -1;
9517 /* ??? If we output all references to a constant in internal
9518 constants table, we don't need to output the constant in the real
9519 constant table, but we have no way to prevent that. */
9522 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9524 extend_operator (x, mode)
9526 enum machine_mode mode ATTRIBUTE_UNUSED;
9528 enum rtx_code code = GET_CODE (x);
9529 return code == SIGN_EXTEND || code == ZERO_EXTEND;
9532 /* Accept any operator that can be used to shift the high half of the
9533 input value to the lower half, suitable for truncation. The
9534 remainder (the lower half of the input, and the upper half of the
9535 output) will be discarded. */
9537 highpart_shift_operator (x, mode)
9539 enum machine_mode mode ATTRIBUTE_UNUSED;
9541 enum rtx_code code = GET_CODE (x);
9542 return (code == LSHIFTRT
9548 /* Return the length of INSN. LENGTH is the initial length computed by
9549 attributes in the machine-description file. */
9552 mips_adjust_insn_length (insn, length)
9556 /* A unconditional jump has an unfilled delay slot if it is not part
9557 of a sequence. A conditional jump normally has a delay slot, but
9558 does not on MIPS16. */
9559 if (simplejump_p (insn)
9560 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
9561 || GET_CODE (insn) == CALL_INSN)))
9564 /* All MIPS16 instructions are a measly two bytes. */
9571 /* Output assembly instructions to peform a conditional branch.
9573 INSN is the branch instruction. OPERANDS[0] is the condition.
9574 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9575 of the first operand to the condition. If TWO_OPERANDS_P is
9576 non-zero the comparison takes two operands; OPERANDS[3] will be the
9579 If INVERTED_P is non-zero we are to branch if the condition does
9580 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9582 LENGTH is the length (in bytes) of the sequence we are to generate.
9583 That tells us whether to generate a simple conditional branch, or a
9584 reversed conditional branch around a `jr' instruction. */
9586 mips_output_conditional_branch (insn,
9599 static char buffer[200];
9600 /* The kind of comparison we are doing. */
9601 enum rtx_code code = GET_CODE (operands[0]);
9602 /* Non-zero if the opcode for the comparison needs a `z' indicating
9603 that it is a comparision against zero. */
9605 /* A string to use in the assembly output to represent the first
9607 const char *op1 = "%z2";
9608 /* A string to use in the assembly output to represent the second
9609 operand. Use the hard-wired zero register if there's no second
9611 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9612 /* The operand-printing string for the comparison. */
9613 const char *const comp = (float_p ? "%F0" : "%C0");
9614 /* The operand-printing string for the inverted comparison. */
9615 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
9617 /* The MIPS processors (for levels of the ISA at least two), have
9618 "likely" variants of each branch instruction. These instructions
9619 annul the instruction in the delay slot if the branch is not
9621 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9623 if (!two_operands_p)
9625 /* To compute whether than A > B, for example, we normally
9626 subtract B from A and then look at the sign bit. But, if we
9627 are doing an unsigned comparison, and B is zero, we don't
9628 have to do the subtraction. Instead, we can just check to
9629 see if A is non-zero. Thus, we change the CODE here to
9630 reflect the simpler comparison operation. */
9642 /* A condition which will always be true. */
9648 /* A condition which will always be false. */
9654 /* Not a special case. */
9659 /* Relative comparisons are always done against zero. But
9660 equality comparisons are done between two operands, and therefore
9661 do not require a `z' in the assembly language output. */
9662 need_z_p = (!float_p && code != EQ && code != NE);
9663 /* For comparisons against zero, the zero is not provided
9668 /* Begin by terminating the buffer. That way we can always use
9669 strcat to add to it. */
9676 /* Just a simple conditional branch. */
9678 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
9679 inverted_p ? inverted_comp : comp);
9681 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
9682 inverted_p ? inverted_comp : comp,
9683 need_z_p ? "z" : "",
9691 /* Generate a reversed conditional branch around ` j'
9706 rtx target = gen_label_rtx ();
9708 output_asm_insn ("%(%<", 0);
9709 orig_target = operands[1];
9710 operands[1] = target;
9711 /* Generate the reversed comparison. This takes four
9714 sprintf (buffer, "%%*b%s\t%%Z2%%1",
9715 inverted_p ? comp : inverted_comp);
9717 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
9718 inverted_p ? comp : inverted_comp,
9719 need_z_p ? "z" : "",
9722 output_asm_insn (buffer, operands);
9723 operands[1] = orig_target;
9725 output_asm_insn ("nop\n\tj\t%1", operands);
9728 output_asm_insn ("nop", 0);
9731 /* Output delay slot instruction. */
9732 rtx insn = final_sequence;
9733 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9735 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9737 output_asm_insn ("%>%)", 0);
9738 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
9739 CODE_LABEL_NUMBER (target));
9743 /* We do not currently use this code. It handles jumps to
9744 arbitrary locations, using `jr', even across a 256MB boundary.
9745 We could add a -mhuge switch, and then use this code instead of
9746 the `j' alternative above when -mhuge was used. */
9751 /* Generate a reversed conditional branch around a `jr'
9765 Not pretty, but allows a conditional branch anywhere in the
9766 32-bit address space. If the original branch is annulled,
9767 then the instruction in the delay slot should be executed
9768 only if the branch is taken. The la instruction is really
9769 a macro which will usually take eight bytes, but sometimes
9770 takes only four, if the instruction to which we're jumping
9771 gets its own entry in the global pointer table, which will
9772 happen if its a case label. The assembler will then
9773 generate only a four-byte sequence, rather than eight, and
9774 there seems to be no way to tell it not to. Thus, we can't
9775 just use a `.+x' addressing form; we don't know what value
9778 So, we resort to using the explicit relocation syntax
9779 available in the assembler and do:
9781 lw $at,%got_page(target)($gp)
9782 daddiu $at,$at,%got_ofst(target)
9784 That way, this always takes up eight bytes, and we can use
9785 the `.+x' form. Of course, these explicit machinations
9786 with relocation will not work with old assemblers. Then
9787 again, neither do out-of-range branches, so we haven't lost
9790 /* The target of the reversed branch. */
9791 const char *const target
9792 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
9793 const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
9794 const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
9797 strcpy (buffer, "%(%<%[");
9798 c = strchr (buffer, '\0');
9799 /* Generate the reversed comparision. This takes four
9802 sprintf (c, "%%*b%s\t%%Z2%s",
9803 inverted_p ? comp : inverted_comp,
9806 sprintf (c, "%%*b%s%s\t%s%s,%s",
9807 inverted_p ? comp : inverted_comp,
9808 need_z_p ? "z" : "",
9812 c = strchr (buffer, '\0');
9813 /* Generate the load-address, and jump. This takes twelve
9814 bytes, for a total of 16. */
9816 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9823 /* The delay slot was unfilled. Since we're inside
9824 .noreorder, the assembler will not fill in the NOP for
9825 us, so we must do it ourselves. */
9826 strcat (buffer, "\n\tnop");
9827 strcat (buffer, "%]%>%)");
9840 /* Called to register all of our global variables with the garbage
9844 mips_add_gc_roots ()
9846 ggc_add_rtx_root (&mips_load_reg, 1);
9847 ggc_add_rtx_root (&mips_load_reg2, 1);
9848 ggc_add_rtx_root (&mips_load_reg3, 1);
9849 ggc_add_rtx_root (&mips_load_reg4, 1);
9850 ggc_add_rtx_root (branch_cmp, sizeof (branch_cmp) / sizeof (rtx));
9851 ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
9852 ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);
9855 static enum processor_type
9856 mips_parse_cpu (cpu_string)
9857 const char *cpu_string;
9859 const char *p = cpu_string;
9861 enum processor_type cpu;
9863 /* We need to cope with the various "vr" prefixes for the NEC 4300
9864 and 4100 processors. */
9865 if (*p == 'v' || *p == 'V')
9868 if (*p == 'r' || *p == 'R')
9871 /* Since there is no difference between a R2000 and R3000 in
9872 terms of the scheduler, we collapse them into just an R3000. */
9874 cpu = PROCESSOR_DEFAULT;
9878 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
9879 cpu = PROCESSOR_R3000;
9880 else if (!strcmp (p, "20kc") || !strcmp (p, "20Kc") )
9881 cpu = PROCESSOR_R20KC;
9885 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
9886 cpu = PROCESSOR_R3000;
9887 else if (!strcmp (p, "3900"))
9888 cpu = PROCESSOR_R3900;
9892 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
9893 cpu = PROCESSOR_R4000;
9894 /* The vr4100 is a non-FP ISA III processor with some extra
9896 else if (!strcmp (p, "4100"))
9897 cpu = PROCESSOR_R4100;
9898 /* The vr4300 is a standard ISA III processor, but with a different
9900 else if (!strcmp (p, "4300"))
9901 cpu = PROCESSOR_R4300;
9902 /* The r4400 is exactly the same as the r4000 from the compiler's
9904 else if (!strcmp (p, "4400"))
9905 cpu = PROCESSOR_R4000;
9906 else if (!strcmp (p, "4600"))
9907 cpu = PROCESSOR_R4600;
9908 else if (!strcmp (p, "4650"))
9909 cpu = PROCESSOR_R4650;
9910 /* The 4kc and 4kp processor cores are the same for
9911 scheduling purposes; they both implement the MIPS32
9912 ISA and only differ in their memory management
9914 else if (!strcmp (p, "4kc") || !strcmp (p, "4Kc")
9915 || !strcmp (p, "4kp") || !strcmp (p, "4Kp") )
9916 cpu = PROCESSOR_R4KC;
9920 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
9921 cpu = PROCESSOR_R5000;
9922 else if (!strcmp (p, "5kc") || !strcmp (p, "5Kc") )
9923 cpu = PROCESSOR_R5KC;
9927 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
9928 cpu = PROCESSOR_R6000;
9932 if (!strcmp (p, "8000"))
9933 cpu = PROCESSOR_R8000;
9937 if (!strcmp (p, "orion"))
9938 cpu = PROCESSOR_R4600;
9943 && cpu != PROCESSOR_R4300
9944 && cpu != PROCESSOR_R4100
9945 && cpu != PROCESSOR_R5000)
9946 cpu = PROCESSOR_DEFAULT;
9951 /* Adjust the cost of INSN based on the relationship between INSN that
9952 is dependent on DEP_INSN through the dependence LINK. The default
9953 is to make no adjustment to COST.
9955 On the MIPS, ignore the cost of anti- and output-dependencies. */
9957 mips_adjust_cost (insn, link, dep, cost)
9958 rtx insn ATTRIBUTE_UNUSED;
9960 rtx dep ATTRIBUTE_UNUSED;
9963 if (REG_NOTE_KIND (link) != 0)
9964 return 0; /* Anti or output dependence. */
9968 /* Cover function for UNIQUE_SECTION. */
9971 mips_unique_section (decl, reloc)
9976 const char *name, *prefix;
9978 static const char *const prefixes[4][2] = {
9979 { ".text.", ".gnu.linkonce.t." },
9980 { ".rodata.", ".gnu.linkonce.r." },
9981 { ".data.", ".gnu.linkonce.d." },
9982 { ".sdata.", ".gnu.linkonce.s." }
9985 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9986 size = int_size_in_bytes (TREE_TYPE (decl));
9988 /* Determine the base section we are interested in:
9989 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
9990 if (TREE_CODE (decl) == FUNCTION_DECL)
9992 else if (DECL_INITIAL (decl) == 0
9993 || DECL_INITIAL (decl) == error_mark_node)
9995 else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
9996 && TREE_CODE (decl) == STRING_CST
9997 && !flag_writable_strings)
9999 /* For embedded position independent code, put constant
10000 strings in the text section, because the data section
10001 is limited to 64K in size. For mips16 code, put
10002 strings in the text section so that a PC relative load
10003 instruction can be used to get their address. */
10006 else if (TARGET_EMBEDDED_DATA)
10008 /* For embedded applications, always put an object in
10009 read-only data if possible, in order to reduce RAM
10012 if (DECL_READONLY_SECTION (decl, reloc))
10014 else if (size > 0 && size <= mips_section_threshold)
10021 /* For hosted applications, always put an object in
10022 small data if possible, as this gives the best
10025 if (size > 0 && size <= mips_section_threshold)
10027 else if (DECL_READONLY_SECTION (decl, reloc))
10033 prefix = prefixes[sec][DECL_ONE_ONLY (decl)];
10034 len = strlen (name) + strlen (prefix);
10035 string = alloca (len + 1);
10036 sprintf (string, "%s%s", prefix, name);
10038 DECL_SECTION_NAME (decl) = build_string (len, string);
10042 mips_hard_regno_nregs (regno, mode)
10044 enum machine_mode mode;
10046 if (! FP_REG_P (regno))
10047 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
10049 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
10053 #ifdef TARGET_IRIX6
10054 /* Output assembly to switch to section NAME with attribute FLAGS. */
10057 iris6_asm_named_section_1 (name, flags, align)
10059 unsigned int flags;
10060 unsigned int align;
10062 unsigned int sh_type, sh_flags, sh_entsize;
10065 if (!(flags & SECTION_DEBUG))
10066 sh_flags |= 2; /* SHF_ALLOC */
10067 if (flags & SECTION_WRITE)
10068 sh_flags |= 1; /* SHF_WRITE */
10069 if (flags & SECTION_CODE)
10070 sh_flags |= 4; /* SHF_EXECINSTR */
10071 if (flags & SECTION_SMALL)
10072 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
10073 if (strcmp (name, ".debug_frame") == 0)
10074 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
10075 if (flags & SECTION_DEBUG)
10076 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
10077 else if (flags & SECTION_BSS)
10078 sh_type = 8; /* SHT_NOBITS */
10080 sh_type = 1; /* SHT_PROGBITS */
10082 if (flags & SECTION_CODE)
10087 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
10088 name, sh_type, sh_flags, sh_entsize, align);
10092 iris6_asm_named_section (name, flags)
10094 unsigned int flags;
10096 if (TARGET_FILE_SWITCHING && (flags & SECTION_CODE))
10097 asm_out_file = asm_out_text_file;
10098 iris6_asm_named_section_1 (name, flags, 0);
10101 /* In addition to emitting a .align directive, record the maximum
10102 alignment requested for the current section. */
10104 struct iris_section_align_entry
10108 unsigned int flags;
10111 static htab_t iris_section_align_htab;
10112 static FILE *iris_orig_asm_out_file;
10115 iris_section_align_entry_eq (p1, p2)
10119 const struct iris_section_align_entry *old = p1;
10120 const char *new = p2;
10122 return strcmp (old->name, new) == 0;
10126 iris_section_align_entry_hash (p)
10129 const struct iris_section_align_entry *old = p;
10130 return htab_hash_string (old->name);
10134 iris6_asm_output_align (file, log)
10138 const char *section = current_section_name ();
10139 struct iris_section_align_entry **slot, *entry;
10144 slot = (struct iris_section_align_entry **)
10145 htab_find_slot_with_hash (iris_section_align_htab, section,
10146 htab_hash_string (section), INSERT);
10150 entry = (struct iris_section_align_entry *)
10151 xmalloc (sizeof (struct iris_section_align_entry));
10153 entry->name = section;
10155 entry->flags = current_section_flags ();
10157 else if (entry->log < log)
10160 fprintf (file, "\t.align\t%u\n", log);
10163 /* The Iris assembler does not record alignment from .align directives,
10164 but takes it from the first .section directive seen. Play yet more
10165 file switching games so that we can emit a .section directive at the
10166 beginning of the file with the proper alignment attached. */
10169 iris6_asm_file_start (stream)
10172 mips_asm_file_start (stream);
10174 iris_orig_asm_out_file = asm_out_file;
10175 stream = tmpfile ();
10176 asm_out_file = stream;
10177 asm_out_data_file = stream;
10178 if (! TARGET_FILE_SWITCHING)
10179 asm_out_text_file = stream;
10181 iris_section_align_htab = htab_create (31, iris_section_align_entry_hash,
10182 iris_section_align_entry_eq, NULL);
10186 iris6_section_align_1 (slot, data)
10188 void *data ATTRIBUTE_UNUSED;
10190 const struct iris_section_align_entry *entry
10191 = *(const struct iris_section_align_entry **) slot;
10193 iris6_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
10198 iris6_asm_file_end (stream)
10201 /* Emit section directives with the proper alignment at the top of the
10202 real output file. */
10203 asm_out_file = iris_orig_asm_out_file;
10204 htab_traverse (iris_section_align_htab, iris6_section_align_1, NULL);
10206 /* Copy the data emitted to the temp file to the real output file. */
10207 copy_file_data (asm_out_file, stream);
10209 mips_asm_file_end (stream);
10211 #endif /* TARGET_IRIX6 */