1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
61 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save & restore registers.
78 Use a maximum gap of 0x100 in the mips16 case. We can then use
79 unextended instructions to save and restore registers, and to
80 allocate and deallocate the top part of the frame.
82 The value in the !mips16 case must be a SMALL_OPERAND and must
83 preserve the maximum stack alignment. */
84 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
86 /* True if INSN is a mips.md pattern or asm statement. */
87 #define USEFUL_INSN_P(INSN) \
89 && GET_CODE (PATTERN (INSN)) != USE \
90 && GET_CODE (PATTERN (INSN)) != CLOBBER \
91 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
92 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
94 /* If INSN is a delayed branch sequence, return the first instruction
95 in the sequence, otherwise return INSN itself. */
96 #define SEQ_BEGIN(INSN) \
97 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
98 ? XVECEXP (PATTERN (INSN), 0, 0) \
101 /* Likewise for the last instruction in a delayed branch sequence. */
102 #define SEQ_END(INSN) \
103 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
104 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
107 /* Execute the following loop body with SUBINSN set to each instruction
108 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
109 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
110 for ((SUBINSN) = SEQ_BEGIN (INSN); \
111 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
112 (SUBINSN) = NEXT_INSN (SUBINSN))
114 /* Classifies an address.
117 A natural register + offset address. The register satisfies
118 mips_valid_base_register_p and the offset is a const_arith_operand.
121 A LO_SUM rtx. The first operand is a valid base register and
122 the second operand is a symbolic address.
125 A signed 16-bit constant address.
128 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
129 enum mips_address_type {
136 /* Classifies the prototype of a builtin function. */
137 enum mips_function_type
139 MIPS_V2SF_FTYPE_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
142 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
143 MIPS_V2SF_FTYPE_SF_SF,
144 MIPS_INT_FTYPE_V2SF_V2SF,
145 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
146 MIPS_INT_FTYPE_SF_SF,
147 MIPS_INT_FTYPE_DF_DF,
154 /* For MIPS DSP ASE */
156 MIPS_DI_FTYPE_DI_SI_SI,
157 MIPS_DI_FTYPE_DI_V2HI_V2HI,
158 MIPS_DI_FTYPE_DI_V4QI_V4QI,
160 MIPS_SI_FTYPE_PTR_SI,
164 MIPS_SI_FTYPE_V2HI_V2HI,
166 MIPS_SI_FTYPE_V4QI_V4QI,
169 MIPS_V2HI_FTYPE_SI_SI,
170 MIPS_V2HI_FTYPE_V2HI,
171 MIPS_V2HI_FTYPE_V2HI_SI,
172 MIPS_V2HI_FTYPE_V2HI_V2HI,
173 MIPS_V2HI_FTYPE_V4QI,
174 MIPS_V2HI_FTYPE_V4QI_V2HI,
176 MIPS_V4QI_FTYPE_V2HI_V2HI,
177 MIPS_V4QI_FTYPE_V4QI_SI,
178 MIPS_V4QI_FTYPE_V4QI_V4QI,
179 MIPS_VOID_FTYPE_SI_SI,
180 MIPS_VOID_FTYPE_V2HI_V2HI,
181 MIPS_VOID_FTYPE_V4QI_V4QI,
187 /* Specifies how a builtin function should be converted into rtl. */
188 enum mips_builtin_type
190 /* The builtin corresponds directly to an .md pattern. The return
191 value is mapped to operand 0 and the arguments are mapped to
192 operands 1 and above. */
195 /* The builtin corresponds directly to an .md pattern. There is no return
196 value and the arguments are mapped to operands 0 and above. */
197 MIPS_BUILTIN_DIRECT_NO_TARGET,
199 /* The builtin corresponds to a comparison instruction followed by
200 a mips_cond_move_tf_ps pattern. The first two arguments are the
201 values to compare and the second two arguments are the vector
202 operands for the movt.ps or movf.ps instruction (in assembly order). */
206 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
207 of this instruction is the result of the comparison, which has mode
208 CCV2 or CCV4. The function arguments are mapped to operands 1 and
209 above. The function's return value is an SImode boolean that is
210 true under the following conditions:
212 MIPS_BUILTIN_CMP_ANY: one of the registers is true
213 MIPS_BUILTIN_CMP_ALL: all of the registers are true
214 MIPS_BUILTIN_CMP_LOWER: the first register is true
215 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
216 MIPS_BUILTIN_CMP_ANY,
217 MIPS_BUILTIN_CMP_ALL,
218 MIPS_BUILTIN_CMP_UPPER,
219 MIPS_BUILTIN_CMP_LOWER,
221 /* As above, but the instruction only sets a single $fcc register. */
222 MIPS_BUILTIN_CMP_SINGLE,
224 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
225 MIPS_BUILTIN_BPOSGE32
228 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
229 #define MIPS_FP_CONDITIONS(MACRO) \
247 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
248 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
249 enum mips_fp_condition {
250 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
253 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
254 #define STRINGIFY(X) #X
255 static const char *const mips_fp_conditions[] = {
256 MIPS_FP_CONDITIONS (STRINGIFY)
259 /* A function to save or store a register. The first argument is the
260 register and the second is the stack slot. */
261 typedef void (*mips_save_restore_fn) (rtx, rtx);
263 struct mips16_constant;
264 struct mips_arg_info;
265 struct mips_address_info;
266 struct mips_integer_op;
269 static enum mips_symbol_type mips_classify_symbol (rtx);
270 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
271 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
272 static bool mips_classify_address (struct mips_address_info *, rtx,
273 enum machine_mode, int);
274 static bool mips_cannot_force_const_mem (rtx);
275 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
276 static int mips_symbol_insns (enum mips_symbol_type);
277 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
278 static rtx mips_force_temporary (rtx, rtx);
279 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
280 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
281 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
282 static unsigned int mips_build_lower (struct mips_integer_op *,
283 unsigned HOST_WIDE_INT);
284 static unsigned int mips_build_integer (struct mips_integer_op *,
285 unsigned HOST_WIDE_INT);
286 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
287 static int m16_check_op (rtx, int, int, int);
288 static bool mips_rtx_costs (rtx, int, int, int *);
289 static int mips_address_cost (rtx);
290 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
291 static void mips_load_call_address (rtx, rtx, int);
292 static bool mips_function_ok_for_sibcall (tree, tree);
293 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
294 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
295 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
296 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
297 tree, int, struct mips_arg_info *);
298 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
299 static void mips_set_architecture (const struct mips_cpu_info *);
300 static void mips_set_tune (const struct mips_cpu_info *);
301 static bool mips_handle_option (size_t, const char *, int);
302 static struct machine_function *mips_init_machine_status (void);
303 static void print_operand_reloc (FILE *, rtx, const char **);
304 static void mips_file_start (void);
305 static bool mips_rewrite_small_data_p (rtx);
306 static int mips_small_data_pattern_1 (rtx *, void *);
307 static int mips_rewrite_small_data_1 (rtx *, void *);
308 static bool mips_function_has_gp_insn (void);
309 static unsigned int mips_global_pointer (void);
310 static bool mips_save_reg_p (unsigned int);
311 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
312 mips_save_restore_fn);
313 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
314 static void mips_output_cplocal (void);
315 static void mips_emit_loadgp (void);
316 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
317 static void mips_set_frame_expr (rtx);
318 static rtx mips_frame_set (rtx, rtx);
319 static void mips_save_reg (rtx, rtx);
320 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
321 static void mips_restore_reg (rtx, rtx);
322 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
323 HOST_WIDE_INT, tree);
324 static int symbolic_expression_p (rtx);
325 static section *mips_select_rtx_section (enum machine_mode, rtx,
326 unsigned HOST_WIDE_INT);
327 static section *mips_function_rodata_section (tree);
328 static bool mips_in_small_data_p (tree);
329 static bool mips_use_anchors_for_symbol_p (rtx);
330 static int mips_fpr_return_fields (tree, tree *);
331 static bool mips_return_in_msb (tree);
332 static rtx mips_return_fpr_pair (enum machine_mode mode,
333 enum machine_mode mode1, HOST_WIDE_INT,
334 enum machine_mode mode2, HOST_WIDE_INT);
335 static rtx mips16_gp_pseudo_reg (void);
336 static void mips16_fp_args (FILE *, int, int);
337 static void build_mips16_function_stub (FILE *);
338 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
339 static void dump_constants (struct mips16_constant *, rtx);
340 static int mips16_insn_length (rtx);
341 static int mips16_rewrite_pool_refs (rtx *, void *);
342 static void mips16_lay_out_constants (void);
343 static void mips_sim_reset (struct mips_sim *);
344 static void mips_sim_init (struct mips_sim *, state_t);
345 static void mips_sim_next_cycle (struct mips_sim *);
346 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
347 static int mips_sim_wait_regs_2 (rtx *, void *);
348 static void mips_sim_wait_regs_1 (rtx *, void *);
349 static void mips_sim_wait_regs (struct mips_sim *, rtx);
350 static void mips_sim_wait_units (struct mips_sim *, rtx);
351 static void mips_sim_wait_insn (struct mips_sim *, rtx);
352 static void mips_sim_record_set (rtx, rtx, void *);
353 static void mips_sim_issue_insn (struct mips_sim *, rtx);
354 static void mips_sim_issue_nop (struct mips_sim *);
355 static void mips_sim_finish_insn (struct mips_sim *, rtx);
356 static void vr4130_avoid_branch_rt_conflict (rtx);
357 static void vr4130_align_insns (void);
358 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
359 static void mips_avoid_hazards (void);
360 static void mips_reorg (void);
361 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
362 static bool mips_matching_cpu_name_p (const char *, const char *);
363 static const struct mips_cpu_info *mips_parse_cpu (const char *);
364 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
365 static bool mips_return_in_memory (tree, tree);
366 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
367 static void mips_macc_chains_record (rtx);
368 static void mips_macc_chains_reorder (rtx *, int);
369 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
370 static bool vr4130_true_reg_dependence_p (rtx);
371 static bool vr4130_swap_insns_p (rtx, rtx);
372 static void vr4130_reorder (rtx *, int);
373 static void mips_promote_ready (rtx *, int, int);
374 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
375 static int mips_variable_issue (FILE *, int, rtx, int);
376 static int mips_adjust_cost (rtx, rtx, rtx, int);
377 static int mips_issue_rate (void);
378 static int mips_multipass_dfa_lookahead (void);
379 static void mips_init_libfuncs (void);
380 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
382 static tree mips_build_builtin_va_list (void);
383 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
384 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
386 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
388 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
390 static bool mips_valid_pointer_mode (enum machine_mode);
391 static bool mips_vector_mode_supported_p (enum machine_mode);
392 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree, unsigned int);
393 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
394 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
395 static void mips_init_builtins (void);
396 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
397 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
398 enum insn_code, enum mips_fp_condition,
400 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
401 enum insn_code, enum mips_fp_condition,
403 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
404 static void mips_encode_section_info (tree, rtx, int);
405 static void mips_extra_live_on_entry (bitmap);
406 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
408 /* Structure to be filled in by compute_frame_size with register
409 save masks, and offsets for the current function. */
411 struct mips_frame_info GTY(())
413 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
414 HOST_WIDE_INT var_size; /* # bytes that variables take up */
415 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
416 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
417 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
418 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
419 unsigned int mask; /* mask of saved gp registers */
420 unsigned int fmask; /* mask of saved fp registers */
421 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
422 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
423 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
424 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
425 bool initialized; /* true if frame size already calculated */
426 int num_gp; /* number of gp registers saved */
427 int num_fp; /* number of fp registers saved */
430 struct machine_function GTY(()) {
431 /* Pseudo-reg holding the value of $28 in a mips16 function which
432 refers to GP relative global variables. */
433 rtx mips16_gp_pseudo_rtx;
435 /* The number of extra stack bytes taken up by register varargs.
436 This area is allocated by the callee at the very top of the frame. */
439 /* Current frame information, calculated by compute_frame_size. */
440 struct mips_frame_info frame;
442 /* The register to use as the global pointer within this function. */
443 unsigned int global_pointer;
445 /* True if mips_adjust_insn_length should ignore an instruction's
447 bool ignore_hazard_length_p;
449 /* True if the whole function is suitable for .set noreorder and
451 bool all_noreorder_p;
453 /* True if the function is known to have an instruction that needs $gp. */
457 /* Information about a single argument. */
460 /* True if the argument is passed in a floating-point register, or
461 would have been if we hadn't run out of registers. */
464 /* The number of words passed in registers, rounded up. */
465 unsigned int reg_words;
467 /* For EABI, the offset of the first register from GP_ARG_FIRST or
468 FP_ARG_FIRST. For other ABIs, the offset of the first register from
469 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
470 comment for details).
472 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
474 unsigned int reg_offset;
476 /* The number of words that must be passed on the stack, rounded up. */
477 unsigned int stack_words;
479 /* The offset from the start of the stack overflow area of the argument's
480 first stack word. Only meaningful when STACK_WORDS is nonzero. */
481 unsigned int stack_offset;
485 /* Information about an address described by mips_address_type.
491 REG is the base register and OFFSET is the constant offset.
494 REG is the register that contains the high part of the address,
495 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
496 is the type of OFFSET's symbol.
499 SYMBOL_TYPE is the type of symbol being referenced. */
501 struct mips_address_info
503 enum mips_address_type type;
506 enum mips_symbol_type symbol_type;
510 /* One stage in a constant building sequence. These sequences have
514 A = A CODE[1] VALUE[1]
515 A = A CODE[2] VALUE[2]
518 where A is an accumulator, each CODE[i] is a binary rtl operation
519 and each VALUE[i] is a constant integer. */
520 struct mips_integer_op {
522 unsigned HOST_WIDE_INT value;
526 /* The largest number of operations needed to load an integer constant.
527 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
528 When the lowest bit is clear, we can try, but reject a sequence with
529 an extra SLL at the end. */
530 #define MIPS_MAX_INTEGER_OPS 7
533 /* Global variables for machine-dependent things. */
535 /* Threshold for data being put into the small data/bss area, instead
536 of the normal data area. */
537 int mips_section_threshold = -1;
539 /* Count the number of .file directives, so that .loc is up to date. */
540 int num_source_filenames = 0;
542 /* Count the number of sdb related labels are generated (to find block
543 start and end boundaries). */
544 int sdb_label_count = 0;
546 /* Next label # for each statement for Silicon Graphics IRIS systems. */
549 /* Name of the file containing the current function. */
550 const char *current_function_file = "";
552 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
558 /* The next branch instruction is a branch likely, not branch normal. */
559 int mips_branch_likely;
561 /* The operands passed to the last cmpMM expander. */
564 /* The target cpu for code generation. */
565 enum processor_type mips_arch;
566 const struct mips_cpu_info *mips_arch_info;
568 /* The target cpu for optimization and scheduling. */
569 enum processor_type mips_tune;
570 const struct mips_cpu_info *mips_tune_info;
572 /* Which instruction set architecture to use. */
575 /* Which ABI to use. */
576 int mips_abi = MIPS_ABI_DEFAULT;
578 /* Cost information to use. */
579 const struct mips_rtx_cost_data *mips_cost;
581 /* Whether we are generating mips16 hard float code. In mips16 mode
582 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
583 -msoft-float was not specified by the user, which means that we
584 should arrange to call mips32 hard floating point code. */
585 int mips16_hard_float;
587 /* The architecture selected by -mipsN. */
588 static const struct mips_cpu_info *mips_isa_info;
590 /* If TRUE, we split addresses into their high and low parts in the RTL. */
591 int mips_split_addresses;
593 /* Mode used for saving/restoring general purpose registers. */
594 static enum machine_mode gpr_mode;
596 /* Array giving truth value on whether or not a given hard register
597 can support a given mode. */
598 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
600 /* List of all MIPS punctuation characters used by print_operand. */
601 char mips_print_operand_punct[256];
603 /* Map GCC register number to debugger register number. */
604 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
606 /* A copy of the original flag_delayed_branch: see override_options. */
607 static int mips_flag_delayed_branch;
609 static GTY (()) int mips_output_filename_first_time = 1;
611 /* mips_split_p[X] is true if symbols of type X can be split by
612 mips_split_symbol(). */
613 bool mips_split_p[NUM_SYMBOL_TYPES];
615 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
616 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
617 if they are matched by a special .md file pattern. */
618 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
620 /* Likewise for HIGHs. */
621 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
623 /* Map hard register number to register class */
624 const enum reg_class mips_regno_to_class[] =
626 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
627 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
628 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
629 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
630 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
631 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
632 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
633 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
634 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
635 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
636 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
637 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
638 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
639 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
640 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
641 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
642 HI_REG, LO_REG, NO_REGS, ST_REGS,
643 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
644 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
645 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
646 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
647 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
648 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
649 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
650 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
651 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
652 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
653 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
654 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
655 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
656 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
657 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
658 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
659 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
660 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
661 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
662 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
663 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
664 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
665 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
666 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
667 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
668 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
669 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
670 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
671 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
672 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
675 /* Table of machine dependent attributes. */
676 const struct attribute_spec mips_attribute_table[] =
678 { "long_call", 0, 0, false, true, true, NULL },
679 { NULL, 0, 0, false, false, false, NULL }
682 /* A table describing all the processors gcc knows about. Names are
683 matched in the order listed. The first mention of an ISA level is
684 taken as the canonical name for that ISA.
686 To ease comparison, please keep this table in the same order as
687 gas's mips_cpu_info_table[]. */
688 const struct mips_cpu_info mips_cpu_info_table[] = {
689 /* Entries for generic ISAs */
690 { "mips1", PROCESSOR_R3000, 1 },
691 { "mips2", PROCESSOR_R6000, 2 },
692 { "mips3", PROCESSOR_R4000, 3 },
693 { "mips4", PROCESSOR_R8000, 4 },
694 { "mips32", PROCESSOR_4KC, 32 },
695 { "mips32r2", PROCESSOR_M4K, 33 },
696 { "mips64", PROCESSOR_5KC, 64 },
699 { "r3000", PROCESSOR_R3000, 1 },
700 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
701 { "r3900", PROCESSOR_R3900, 1 },
704 { "r6000", PROCESSOR_R6000, 2 },
707 { "r4000", PROCESSOR_R4000, 3 },
708 { "vr4100", PROCESSOR_R4100, 3 },
709 { "vr4111", PROCESSOR_R4111, 3 },
710 { "vr4120", PROCESSOR_R4120, 3 },
711 { "vr4130", PROCESSOR_R4130, 3 },
712 { "vr4300", PROCESSOR_R4300, 3 },
713 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
714 { "r4600", PROCESSOR_R4600, 3 },
715 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
716 { "r4650", PROCESSOR_R4650, 3 },
719 { "r8000", PROCESSOR_R8000, 4 },
720 { "vr5000", PROCESSOR_R5000, 4 },
721 { "vr5400", PROCESSOR_R5400, 4 },
722 { "vr5500", PROCESSOR_R5500, 4 },
723 { "rm7000", PROCESSOR_R7000, 4 },
724 { "rm9000", PROCESSOR_R9000, 4 },
727 { "4kc", PROCESSOR_4KC, 32 },
728 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
729 { "4kp", PROCESSOR_4KP, 32 },
731 /* MIPS32 Release 2 */
732 { "m4k", PROCESSOR_M4K, 33 },
733 { "4kec", PROCESSOR_4KC, 33 },
734 { "4kem", PROCESSOR_4KC, 33 },
735 { "4kep", PROCESSOR_4KP, 33 },
736 { "24kc", PROCESSOR_24KC, 33 }, /* 24K no FPU */
737 { "24kf", PROCESSOR_24KF, 33 }, /* 24K 1:2 FPU */
738 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
739 { "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
740 { "24kef", PROCESSOR_24KF, 33 },
741 { "24kex", PROCESSOR_24KX, 33 },
742 { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
743 { "34kf", PROCESSOR_24KF, 33 },
744 { "34kx", PROCESSOR_24KX, 33 },
747 { "5kc", PROCESSOR_5KC, 64 },
748 { "5kf", PROCESSOR_5KF, 64 },
749 { "20kc", PROCESSOR_20KC, 64 },
750 { "sb1", PROCESSOR_SB1, 64 },
751 { "sb1a", PROCESSOR_SB1A, 64 },
752 { "sr71000", PROCESSOR_SR71000, 64 },
758 /* Default costs. If these are used for a processor we should look
759 up the actual costs. */
760 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
761 COSTS_N_INSNS (7), /* fp_mult_sf */ \
762 COSTS_N_INSNS (8), /* fp_mult_df */ \
763 COSTS_N_INSNS (23), /* fp_div_sf */ \
764 COSTS_N_INSNS (36), /* fp_div_df */ \
765 COSTS_N_INSNS (10), /* int_mult_si */ \
766 COSTS_N_INSNS (10), /* int_mult_di */ \
767 COSTS_N_INSNS (69), /* int_div_si */ \
768 COSTS_N_INSNS (69), /* int_div_di */ \
769 2, /* branch_cost */ \
770 4 /* memory_latency */
772 /* Need to replace these with the costs of calling the appropriate
774 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
775 COSTS_N_INSNS (256), /* fp_mult_sf */ \
776 COSTS_N_INSNS (256), /* fp_mult_df */ \
777 COSTS_N_INSNS (256), /* fp_div_sf */ \
778 COSTS_N_INSNS (256) /* fp_div_df */
780 static struct mips_rtx_cost_data const mips_rtx_cost_optimize_size =
782 COSTS_N_INSNS (1), /* fp_add */
783 COSTS_N_INSNS (1), /* fp_mult_sf */
784 COSTS_N_INSNS (1), /* fp_mult_df */
785 COSTS_N_INSNS (1), /* fp_div_sf */
786 COSTS_N_INSNS (1), /* fp_div_df */
787 COSTS_N_INSNS (1), /* int_mult_si */
788 COSTS_N_INSNS (1), /* int_mult_di */
789 COSTS_N_INSNS (1), /* int_div_si */
790 COSTS_N_INSNS (1), /* int_div_di */
792 4 /* memory_latency */
795 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
798 COSTS_N_INSNS (2), /* fp_add */
799 COSTS_N_INSNS (4), /* fp_mult_sf */
800 COSTS_N_INSNS (5), /* fp_mult_df */
801 COSTS_N_INSNS (12), /* fp_div_sf */
802 COSTS_N_INSNS (19), /* fp_div_df */
803 COSTS_N_INSNS (12), /* int_mult_si */
804 COSTS_N_INSNS (12), /* int_mult_di */
805 COSTS_N_INSNS (35), /* int_div_si */
806 COSTS_N_INSNS (35), /* int_div_di */
808 4 /* memory_latency */
813 COSTS_N_INSNS (6), /* int_mult_si */
814 COSTS_N_INSNS (6), /* int_mult_di */
815 COSTS_N_INSNS (36), /* int_div_si */
816 COSTS_N_INSNS (36), /* int_div_di */
818 4 /* memory_latency */
822 COSTS_N_INSNS (36), /* int_mult_si */
823 COSTS_N_INSNS (36), /* int_mult_di */
824 COSTS_N_INSNS (37), /* int_div_si */
825 COSTS_N_INSNS (37), /* int_div_di */
827 4 /* memory_latency */
831 COSTS_N_INSNS (4), /* int_mult_si */
832 COSTS_N_INSNS (11), /* int_mult_di */
833 COSTS_N_INSNS (36), /* int_div_si */
834 COSTS_N_INSNS (68), /* int_div_di */
836 4 /* memory_latency */
839 COSTS_N_INSNS (4), /* fp_add */
840 COSTS_N_INSNS (4), /* fp_mult_sf */
841 COSTS_N_INSNS (5), /* fp_mult_df */
842 COSTS_N_INSNS (17), /* fp_div_sf */
843 COSTS_N_INSNS (32), /* fp_div_df */
844 COSTS_N_INSNS (4), /* int_mult_si */
845 COSTS_N_INSNS (11), /* int_mult_di */
846 COSTS_N_INSNS (36), /* int_div_si */
847 COSTS_N_INSNS (68), /* int_div_di */
849 4 /* memory_latency */
856 COSTS_N_INSNS (5), /* int_mult_si */
857 COSTS_N_INSNS (5), /* int_mult_di */
858 COSTS_N_INSNS (41), /* int_div_si */
859 COSTS_N_INSNS (41), /* int_div_di */
861 4 /* memory_latency */
864 COSTS_N_INSNS (8), /* fp_add */
865 COSTS_N_INSNS (8), /* fp_mult_sf */
866 COSTS_N_INSNS (10), /* fp_mult_df */
867 COSTS_N_INSNS (34), /* fp_div_sf */
868 COSTS_N_INSNS (64), /* fp_div_df */
869 COSTS_N_INSNS (5), /* int_mult_si */
870 COSTS_N_INSNS (5), /* int_mult_di */
871 COSTS_N_INSNS (41), /* int_div_si */
872 COSTS_N_INSNS (41), /* int_div_di */
874 4 /* memory_latency */
877 COSTS_N_INSNS (4), /* fp_add */
878 COSTS_N_INSNS (4), /* fp_mult_sf */
879 COSTS_N_INSNS (5), /* fp_mult_df */
880 COSTS_N_INSNS (17), /* fp_div_sf */
881 COSTS_N_INSNS (32), /* fp_div_df */
882 COSTS_N_INSNS (5), /* int_mult_si */
883 COSTS_N_INSNS (5), /* int_mult_di */
884 COSTS_N_INSNS (41), /* int_div_si */
885 COSTS_N_INSNS (41), /* int_div_di */
887 4 /* memory_latency */
893 COSTS_N_INSNS (2), /* fp_add */
894 COSTS_N_INSNS (4), /* fp_mult_sf */
895 COSTS_N_INSNS (5), /* fp_mult_df */
896 COSTS_N_INSNS (12), /* fp_div_sf */
897 COSTS_N_INSNS (19), /* fp_div_df */
898 COSTS_N_INSNS (2), /* int_mult_si */
899 COSTS_N_INSNS (2), /* int_mult_di */
900 COSTS_N_INSNS (35), /* int_div_si */
901 COSTS_N_INSNS (35), /* int_div_di */
903 4 /* memory_latency */
906 COSTS_N_INSNS (3), /* fp_add */
907 COSTS_N_INSNS (5), /* fp_mult_sf */
908 COSTS_N_INSNS (6), /* fp_mult_df */
909 COSTS_N_INSNS (15), /* fp_div_sf */
910 COSTS_N_INSNS (16), /* fp_div_df */
911 COSTS_N_INSNS (17), /* int_mult_si */
912 COSTS_N_INSNS (17), /* int_mult_di */
913 COSTS_N_INSNS (38), /* int_div_si */
914 COSTS_N_INSNS (38), /* int_div_di */
916 6 /* memory_latency */
919 COSTS_N_INSNS (6), /* fp_add */
920 COSTS_N_INSNS (7), /* fp_mult_sf */
921 COSTS_N_INSNS (8), /* fp_mult_df */
922 COSTS_N_INSNS (23), /* fp_div_sf */
923 COSTS_N_INSNS (36), /* fp_div_df */
924 COSTS_N_INSNS (10), /* int_mult_si */
925 COSTS_N_INSNS (10), /* int_mult_di */
926 COSTS_N_INSNS (69), /* int_div_si */
927 COSTS_N_INSNS (69), /* int_div_di */
929 6 /* memory_latency */
941 /* The only costs that appear to be updated here are
942 integer multiplication. */
944 COSTS_N_INSNS (4), /* int_mult_si */
945 COSTS_N_INSNS (6), /* int_mult_di */
946 COSTS_N_INSNS (69), /* int_div_si */
947 COSTS_N_INSNS (69), /* int_div_di */
949 4 /* memory_latency */
961 COSTS_N_INSNS (6), /* fp_add */
962 COSTS_N_INSNS (4), /* fp_mult_sf */
963 COSTS_N_INSNS (5), /* fp_mult_df */
964 COSTS_N_INSNS (23), /* fp_div_sf */
965 COSTS_N_INSNS (36), /* fp_div_df */
966 COSTS_N_INSNS (5), /* int_mult_si */
967 COSTS_N_INSNS (5), /* int_mult_di */
968 COSTS_N_INSNS (36), /* int_div_si */
969 COSTS_N_INSNS (36), /* int_div_di */
971 4 /* memory_latency */
974 COSTS_N_INSNS (6), /* fp_add */
975 COSTS_N_INSNS (5), /* fp_mult_sf */
976 COSTS_N_INSNS (6), /* fp_mult_df */
977 COSTS_N_INSNS (30), /* fp_div_sf */
978 COSTS_N_INSNS (59), /* fp_div_df */
979 COSTS_N_INSNS (3), /* int_mult_si */
980 COSTS_N_INSNS (4), /* int_mult_di */
981 COSTS_N_INSNS (42), /* int_div_si */
982 COSTS_N_INSNS (74), /* int_div_di */
984 4 /* memory_latency */
987 COSTS_N_INSNS (6), /* fp_add */
988 COSTS_N_INSNS (5), /* fp_mult_sf */
989 COSTS_N_INSNS (6), /* fp_mult_df */
990 COSTS_N_INSNS (30), /* fp_div_sf */
991 COSTS_N_INSNS (59), /* fp_div_df */
992 COSTS_N_INSNS (5), /* int_mult_si */
993 COSTS_N_INSNS (9), /* int_mult_di */
994 COSTS_N_INSNS (42), /* int_div_si */
995 COSTS_N_INSNS (74), /* int_div_di */
997 4 /* memory_latency */
1000 /* The only costs that are changed here are
1001 integer multiplication. */
1002 COSTS_N_INSNS (6), /* fp_add */
1003 COSTS_N_INSNS (7), /* fp_mult_sf */
1004 COSTS_N_INSNS (8), /* fp_mult_df */
1005 COSTS_N_INSNS (23), /* fp_div_sf */
1006 COSTS_N_INSNS (36), /* fp_div_df */
1007 COSTS_N_INSNS (5), /* int_mult_si */
1008 COSTS_N_INSNS (9), /* int_mult_di */
1009 COSTS_N_INSNS (69), /* int_div_si */
1010 COSTS_N_INSNS (69), /* int_div_di */
1011 1, /* branch_cost */
1012 4 /* memory_latency */
1018 /* The only costs that are changed here are
1019 integer multiplication. */
1020 COSTS_N_INSNS (6), /* fp_add */
1021 COSTS_N_INSNS (7), /* fp_mult_sf */
1022 COSTS_N_INSNS (8), /* fp_mult_df */
1023 COSTS_N_INSNS (23), /* fp_div_sf */
1024 COSTS_N_INSNS (36), /* fp_div_df */
1025 COSTS_N_INSNS (3), /* int_mult_si */
1026 COSTS_N_INSNS (8), /* int_mult_di */
1027 COSTS_N_INSNS (69), /* int_div_si */
1028 COSTS_N_INSNS (69), /* int_div_di */
1029 1, /* branch_cost */
1030 4 /* memory_latency */
1033 /* These costs are the same as the SB-1A below. */
1034 COSTS_N_INSNS (4), /* fp_add */
1035 COSTS_N_INSNS (4), /* fp_mult_sf */
1036 COSTS_N_INSNS (4), /* fp_mult_df */
1037 COSTS_N_INSNS (24), /* fp_div_sf */
1038 COSTS_N_INSNS (32), /* fp_div_df */
1039 COSTS_N_INSNS (3), /* int_mult_si */
1040 COSTS_N_INSNS (4), /* int_mult_di */
1041 COSTS_N_INSNS (36), /* int_div_si */
1042 COSTS_N_INSNS (68), /* int_div_di */
1043 1, /* branch_cost */
1044 4 /* memory_latency */
1047 /* These costs are the same as the SB-1 above. */
1048 COSTS_N_INSNS (4), /* fp_add */
1049 COSTS_N_INSNS (4), /* fp_mult_sf */
1050 COSTS_N_INSNS (4), /* fp_mult_df */
1051 COSTS_N_INSNS (24), /* fp_div_sf */
1052 COSTS_N_INSNS (32), /* fp_div_df */
1053 COSTS_N_INSNS (3), /* int_mult_si */
1054 COSTS_N_INSNS (4), /* int_mult_di */
1055 COSTS_N_INSNS (36), /* int_div_si */
1056 COSTS_N_INSNS (68), /* int_div_di */
1057 1, /* branch_cost */
1058 4 /* memory_latency */
1066 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1067 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1068 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1071 /* Initialize the GCC target structure. */
1072 #undef TARGET_ASM_ALIGNED_HI_OP
1073 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1074 #undef TARGET_ASM_ALIGNED_SI_OP
1075 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1076 #undef TARGET_ASM_ALIGNED_DI_OP
1077 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1079 #undef TARGET_ASM_FUNCTION_PROLOGUE
1080 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1081 #undef TARGET_ASM_FUNCTION_EPILOGUE
1082 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1083 #undef TARGET_ASM_SELECT_RTX_SECTION
1084 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1085 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1086 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1088 #undef TARGET_SCHED_REORDER
1089 #define TARGET_SCHED_REORDER mips_sched_reorder
1090 #undef TARGET_SCHED_VARIABLE_ISSUE
1091 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1092 #undef TARGET_SCHED_ADJUST_COST
1093 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1094 #undef TARGET_SCHED_ISSUE_RATE
1095 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1096 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1097 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1098 mips_multipass_dfa_lookahead
1100 #undef TARGET_DEFAULT_TARGET_FLAGS
1101 #define TARGET_DEFAULT_TARGET_FLAGS \
1103 | TARGET_CPU_DEFAULT \
1104 | TARGET_ENDIAN_DEFAULT \
1105 | TARGET_FP_EXCEPTIONS_DEFAULT \
1106 | MASK_CHECK_ZERO_DIV \
1108 #undef TARGET_HANDLE_OPTION
1109 #define TARGET_HANDLE_OPTION mips_handle_option
1111 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1112 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1114 #undef TARGET_VALID_POINTER_MODE
1115 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1116 #undef TARGET_RTX_COSTS
1117 #define TARGET_RTX_COSTS mips_rtx_costs
1118 #undef TARGET_ADDRESS_COST
1119 #define TARGET_ADDRESS_COST mips_address_cost
1121 #undef TARGET_IN_SMALL_DATA_P
1122 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1124 #undef TARGET_MACHINE_DEPENDENT_REORG
1125 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1127 #undef TARGET_ASM_FILE_START
1128 #define TARGET_ASM_FILE_START mips_file_start
1129 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1130 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1132 #undef TARGET_INIT_LIBFUNCS
1133 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1135 #undef TARGET_BUILD_BUILTIN_VA_LIST
1136 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1137 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1138 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1140 #undef TARGET_PROMOTE_FUNCTION_ARGS
1141 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1142 #undef TARGET_PROMOTE_FUNCTION_RETURN
1143 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1144 #undef TARGET_PROMOTE_PROTOTYPES
1145 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1147 #undef TARGET_RETURN_IN_MEMORY
1148 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1149 #undef TARGET_RETURN_IN_MSB
1150 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1152 #undef TARGET_ASM_OUTPUT_MI_THUNK
1153 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1154 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1155 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1157 #undef TARGET_SETUP_INCOMING_VARARGS
1158 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1159 #undef TARGET_STRICT_ARGUMENT_NAMING
1160 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1161 #undef TARGET_MUST_PASS_IN_STACK
1162 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1163 #undef TARGET_PASS_BY_REFERENCE
1164 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1165 #undef TARGET_CALLEE_COPIES
1166 #define TARGET_CALLEE_COPIES mips_callee_copies
1167 #undef TARGET_ARG_PARTIAL_BYTES
1168 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1170 #undef TARGET_MODE_REP_EXTENDED
1171 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1173 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1174 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1176 #undef TARGET_INIT_BUILTINS
1177 #define TARGET_INIT_BUILTINS mips_init_builtins
1178 #undef TARGET_EXPAND_BUILTIN
1179 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1181 #undef TARGET_HAVE_TLS
1182 #define TARGET_HAVE_TLS HAVE_AS_TLS
1184 #undef TARGET_CANNOT_FORCE_CONST_MEM
1185 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1187 #undef TARGET_ENCODE_SECTION_INFO
1188 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1190 #undef TARGET_ATTRIBUTE_TABLE
1191 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1193 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1194 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1196 #undef TARGET_MIN_ANCHOR_OFFSET
1197 #define TARGET_MIN_ANCHOR_OFFSET -32768
1198 #undef TARGET_MAX_ANCHOR_OFFSET
1199 #define TARGET_MAX_ANCHOR_OFFSET 32767
1200 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1201 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1202 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1203 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1205 struct gcc_target targetm = TARGET_INITIALIZER;
1207 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1209 static enum mips_symbol_type
1210 mips_classify_symbol (rtx x)
1214 if (GET_CODE (x) == LABEL_REF)
1217 return SYMBOL_CONSTANT_POOL;
1218 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1219 return SYMBOL_GOT_LOCAL;
1220 return SYMBOL_GENERAL;
1223 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1225 if (SYMBOL_REF_TLS_MODEL (x))
1228 if (CONSTANT_POOL_ADDRESS_P (x))
1231 return SYMBOL_CONSTANT_POOL;
1233 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1234 return SYMBOL_SMALL_DATA;
1237 /* Do not use small-data accesses for weak symbols; they may end up
1239 if (SYMBOL_REF_SMALL_P (x)
1240 && !SYMBOL_REF_WEAK (x))
1241 return SYMBOL_SMALL_DATA;
1243 if (TARGET_ABICALLS)
1245 decl = SYMBOL_REF_DECL (x);
1248 if (!SYMBOL_REF_LOCAL_P (x))
1249 return SYMBOL_GOT_GLOBAL;
1253 /* Don't use GOT accesses for locally-binding symbols if
1254 TARGET_ABSOLUTE_ABICALLS. Otherwise, there are three
1257 - o32 PIC (either with or without explicit relocs)
1258 - n32/n64 PIC without explicit relocs
1259 - n32/n64 PIC with explicit relocs
1261 In the first case, both local and global accesses will use an
1262 R_MIPS_GOT16 relocation. We must correctly predict which of
1263 the two semantics (local or global) the assembler and linker
1264 will apply. The choice doesn't depend on the symbol's
1265 visibility, so we deliberately ignore decl_visibility and
1268 In the second case, the assembler will not use R_MIPS_GOT16
1269 relocations, but it chooses between local and global accesses
1270 in the same way as for o32 PIC.
1272 In the third case we have more freedom since both forms of
1273 access will work for any kind of symbol. However, there seems
1274 little point in doing things differently.
1276 Note that weakref symbols are not TREE_PUBLIC, but their
1277 targets are global or weak symbols. Relocations in the
1278 object file will be against the target symbol, so it's
1279 that symbol's binding that matters here. */
1281 && (TREE_PUBLIC (decl) || DECL_WEAK (decl))
1282 && !(TARGET_ABSOLUTE_ABICALLS && targetm.binds_local_p (decl)))
1283 return SYMBOL_GOT_GLOBAL;
1286 if (!TARGET_ABSOLUTE_ABICALLS)
1287 return SYMBOL_GOT_LOCAL;
1290 return SYMBOL_GENERAL;
1293 /* Return true if X is a symbolic constant that can be calculated in
1294 the same way as a bare symbol. If it is, store the type of the
1295 symbol in *SYMBOL_TYPE. */
1298 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1302 split_const (x, &x, &offset);
1303 if (UNSPEC_ADDRESS_P (x))
1304 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1305 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1307 *symbol_type = mips_classify_symbol (x);
1308 if (*symbol_type == SYMBOL_TLS)
1314 if (offset == const0_rtx)
1317 /* Check whether a nonzero offset is valid for the underlying
1319 switch (*symbol_type)
1321 case SYMBOL_GENERAL:
1322 case SYMBOL_64_HIGH:
1325 /* If the target has 64-bit pointers and the object file only
1326 supports 32-bit symbols, the values of those symbols will be
1327 sign-extended. In this case we can't allow an arbitrary offset
1328 in case the 32-bit value X + OFFSET has a different sign from X. */
1329 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1330 return offset_within_block_p (x, INTVAL (offset));
1332 /* In other cases the relocations can handle any offset. */
1335 case SYMBOL_CONSTANT_POOL:
1336 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1337 In this case, we no longer have access to the underlying constant,
1338 but the original symbol-based access was known to be valid. */
1339 if (GET_CODE (x) == LABEL_REF)
1344 case SYMBOL_SMALL_DATA:
1345 /* Make sure that the offset refers to something within the
1346 same object block. This should guarantee that the final
1347 PC- or GP-relative offset is within the 16-bit limit. */
1348 return offset_within_block_p (x, INTVAL (offset));
1350 case SYMBOL_GOT_LOCAL:
1351 case SYMBOL_GOTOFF_PAGE:
1352 /* The linker should provide enough local GOT entries for a
1353 16-bit offset. Larger offsets may lead to GOT overflow. */
1354 return SMALL_INT (offset);
1356 case SYMBOL_GOT_GLOBAL:
1357 case SYMBOL_GOTOFF_GLOBAL:
1358 case SYMBOL_GOTOFF_CALL:
1359 case SYMBOL_GOTOFF_LOADGP:
1364 case SYMBOL_GOTTPREL:
1372 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1375 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1377 if (!HARD_REGISTER_NUM_P (regno))
1381 regno = reg_renumber[regno];
1384 /* These fake registers will be eliminated to either the stack or
1385 hard frame pointer, both of which are usually valid base registers.
1386 Reload deals with the cases where the eliminated form isn't valid. */
1387 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1390 /* In mips16 mode, the stack pointer can only address word and doubleword
1391 values, nothing smaller. There are two problems here:
1393 (a) Instantiating virtual registers can introduce new uses of the
1394 stack pointer. If these virtual registers are valid addresses,
1395 the stack pointer should be too.
1397 (b) Most uses of the stack pointer are not made explicit until
1398 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1399 We don't know until that stage whether we'll be eliminating to the
1400 stack pointer (which needs the restriction) or the hard frame
1401 pointer (which doesn't).
1403 All in all, it seems more consistent to only enforce this restriction
1404 during and after reload. */
1405 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1406 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1408 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1412 /* Return true if X is a valid base register for the given mode.
1413 Allow only hard registers if STRICT. */
1416 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1418 if (!strict && GET_CODE (x) == SUBREG)
1422 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1426 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1427 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1430 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1431 enum machine_mode mode)
1433 switch (symbol_type)
1435 case SYMBOL_GENERAL:
1436 return !TARGET_MIPS16;
1438 case SYMBOL_SMALL_DATA:
1441 case SYMBOL_CONSTANT_POOL:
1442 /* PC-relative addressing is only available for lw and ld. */
1443 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1445 case SYMBOL_GOT_LOCAL:
1448 case SYMBOL_GOT_GLOBAL:
1449 /* The address will have to be loaded from the GOT first. */
1452 case SYMBOL_GOTOFF_PAGE:
1453 case SYMBOL_GOTOFF_GLOBAL:
1454 case SYMBOL_GOTOFF_CALL:
1455 case SYMBOL_GOTOFF_LOADGP:
1460 case SYMBOL_GOTTPREL:
1462 case SYMBOL_64_HIGH:
1471 /* Return true if X is a valid address for machine mode MODE. If it is,
1472 fill in INFO appropriately. STRICT is true if we should only accept
1473 hard base registers. */
1476 mips_classify_address (struct mips_address_info *info, rtx x,
1477 enum machine_mode mode, int strict)
1479 switch (GET_CODE (x))
1483 info->type = ADDRESS_REG;
1485 info->offset = const0_rtx;
1486 return mips_valid_base_register_p (info->reg, mode, strict);
1489 info->type = ADDRESS_REG;
1490 info->reg = XEXP (x, 0);
1491 info->offset = XEXP (x, 1);
1492 return (mips_valid_base_register_p (info->reg, mode, strict)
1493 && const_arith_operand (info->offset, VOIDmode));
1496 info->type = ADDRESS_LO_SUM;
1497 info->reg = XEXP (x, 0);
1498 info->offset = XEXP (x, 1);
1499 return (mips_valid_base_register_p (info->reg, mode, strict)
1500 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1501 && mips_symbolic_address_p (info->symbol_type, mode)
1502 && mips_lo_relocs[info->symbol_type] != 0);
1505 /* Small-integer addresses don't occur very often, but they
1506 are legitimate if $0 is a valid base register. */
1507 info->type = ADDRESS_CONST_INT;
1508 return !TARGET_MIPS16 && SMALL_INT (x);
1513 info->type = ADDRESS_SYMBOLIC;
1514 return (mips_symbolic_constant_p (x, &info->symbol_type)
1515 && mips_symbolic_address_p (info->symbol_type, mode)
1516 && !mips_split_p[info->symbol_type]);
1523 /* Return true if X is a thread-local symbol. */
1526 mips_tls_operand_p (rtx x)
1528 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1531 /* Return true if X can not be forced into a constant pool. */
1534 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1536 return mips_tls_operand_p (*x);
1539 /* Return true if X can not be forced into a constant pool. */
1542 mips_cannot_force_const_mem (rtx x)
1548 /* As an optimization, reject constants that mips_legitimize_move
1551 Suppose we have a multi-instruction sequence that loads constant C
1552 into register R. If R does not get allocated a hard register, and
1553 R is used in an operand that allows both registers and memory
1554 references, reload will consider forcing C into memory and using
1555 one of the instruction's memory alternatives. Returning false
1556 here will force it to use an input reload instead. */
1557 if (GET_CODE (x) == CONST_INT)
1560 split_const (x, &base, &offset);
1561 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1565 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1571 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1572 constant pools, but normal-mode code doesn't need to. */
1575 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1576 rtx x ATTRIBUTE_UNUSED)
1578 return !TARGET_MIPS16;
1581 /* Return the number of instructions needed to load a symbol of the
1582 given type into a register. If valid in an address, the same number
1583 of instructions are needed for loads and stores. Treat extended
1584 mips16 instructions as two instructions. */
1587 mips_symbol_insns (enum mips_symbol_type type)
1591 case SYMBOL_GENERAL:
1592 /* In mips16 code, general symbols must be fetched from the
1597 /* When using 64-bit symbols, we need 5 preparatory instructions,
1600 lui $at,%highest(symbol)
1601 daddiu $at,$at,%higher(symbol)
1603 daddiu $at,$at,%hi(symbol)
1606 The final address is then $at + %lo(symbol). With 32-bit
1607 symbols we just need a preparatory lui. */
1608 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1610 case SYMBOL_SMALL_DATA:
1613 case SYMBOL_CONSTANT_POOL:
1614 /* This case is for mips16 only. Assume we'll need an
1615 extended instruction. */
1618 case SYMBOL_GOT_LOCAL:
1619 case SYMBOL_GOT_GLOBAL:
1620 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1621 the local/global classification is accurate. See override_options
1624 The worst cases are:
1626 (1) For local symbols when generating o32 or o64 code. The assembler
1632 ...and the final address will be $at + %lo(symbol).
1634 (2) For global symbols when -mxgot. The assembler will use:
1636 lui $at,%got_hi(symbol)
1639 ...and the final address will be $at + %got_lo(symbol). */
1642 case SYMBOL_GOTOFF_PAGE:
1643 case SYMBOL_GOTOFF_GLOBAL:
1644 case SYMBOL_GOTOFF_CALL:
1645 case SYMBOL_GOTOFF_LOADGP:
1646 case SYMBOL_64_HIGH:
1652 case SYMBOL_GOTTPREL:
1654 /* Check whether the offset is a 16- or 32-bit value. */
1655 return mips_split_p[type] ? 2 : 1;
1658 /* We don't treat a bare TLS symbol as a constant. */
1664 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1667 mips_stack_address_p (rtx x, enum machine_mode mode)
1669 struct mips_address_info addr;
1671 return (mips_classify_address (&addr, x, mode, false)
1672 && addr.type == ADDRESS_REG
1673 && addr.reg == stack_pointer_rtx);
1676 /* Return true if a value at OFFSET bytes from BASE can be accessed
1677 using an unextended mips16 instruction. MODE is the mode of the
1680 Usually the offset in an unextended instruction is a 5-bit field.
1681 The offset is unsigned and shifted left once for HIs, twice
1682 for SIs, and so on. An exception is SImode accesses off the
1683 stack pointer, which have an 8-bit immediate field. */
1686 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1689 && GET_CODE (offset) == CONST_INT
1690 && INTVAL (offset) >= 0
1691 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1693 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1694 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1695 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1701 /* Return the number of instructions needed to load or store a value
1702 of mode MODE at X. Return 0 if X isn't valid for MODE.
1704 For mips16 code, count extended instructions as two instructions. */
1707 mips_address_insns (rtx x, enum machine_mode mode)
1709 struct mips_address_info addr;
1712 if (mode == BLKmode)
1713 /* BLKmode is used for single unaligned loads and stores. */
1716 /* Each word of a multi-word value will be accessed individually. */
1717 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1719 if (mips_classify_address (&addr, x, mode, false))
1724 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1728 case ADDRESS_LO_SUM:
1729 return (TARGET_MIPS16 ? factor * 2 : factor);
1731 case ADDRESS_CONST_INT:
1734 case ADDRESS_SYMBOLIC:
1735 return factor * mips_symbol_insns (addr.symbol_type);
1741 /* Likewise for constant X. */
1744 mips_const_insns (rtx x)
1746 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1747 enum mips_symbol_type symbol_type;
1750 switch (GET_CODE (x))
1754 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1755 || !mips_split_p[symbol_type])
1762 /* Unsigned 8-bit constants can be loaded using an unextended
1763 LI instruction. Unsigned 16-bit constants can be loaded
1764 using an extended LI. Negative constants must be loaded
1765 using LI and then negated. */
1766 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1767 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1768 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1769 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1772 return mips_build_integer (codes, INTVAL (x));
1776 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1782 /* See if we can refer to X directly. */
1783 if (mips_symbolic_constant_p (x, &symbol_type))
1784 return mips_symbol_insns (symbol_type);
1786 /* Otherwise try splitting the constant into a base and offset.
1787 16-bit offsets can be added using an extra addiu. Larger offsets
1788 must be calculated separately and then added to the base. */
1789 split_const (x, &x, &offset);
1792 int n = mips_const_insns (x);
1795 if (SMALL_INT (offset))
1798 return n + 1 + mips_build_integer (codes, INTVAL (offset));
1805 return mips_symbol_insns (mips_classify_symbol (x));
1813 /* Return the number of instructions needed for memory reference X.
1814 Count extended mips16 instructions as two instructions. */
1817 mips_fetch_insns (rtx x)
1819 gcc_assert (MEM_P (x));
1820 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1824 /* Return the number of instructions needed for an integer division. */
1827 mips_idiv_insns (void)
1832 if (TARGET_CHECK_ZERO_DIV)
1834 if (GENERATE_DIVIDE_TRAPS)
1840 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1845 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1846 returns a nonzero value if X is a legitimate address for a memory
1847 operand of the indicated MODE. STRICT is nonzero if this function
1848 is called during reload. */
1851 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1853 struct mips_address_info addr;
1855 return mips_classify_address (&addr, x, mode, strict);
1859 /* Copy VALUE to a register and return that register. If new psuedos
1860 are allowed, copy it into a new register, otherwise use DEST. */
1863 mips_force_temporary (rtx dest, rtx value)
1865 if (!no_new_pseudos)
1866 return force_reg (Pmode, value);
1869 emit_move_insn (copy_rtx (dest), value);
1875 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1876 and is used to load the high part into a register. */
1879 mips_split_symbol (rtx temp, rtx addr)
1884 high = mips16_gp_pseudo_reg ();
1886 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1887 return gen_rtx_LO_SUM (Pmode, high, addr);
1891 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1892 type SYMBOL_TYPE. */
1895 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1899 split_const (address, &base, &offset);
1900 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1901 UNSPEC_ADDRESS_FIRST + symbol_type);
1902 if (offset != const0_rtx)
1903 base = gen_rtx_PLUS (Pmode, base, offset);
1904 return gen_rtx_CONST (Pmode, base);
1908 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1909 high part to BASE and return the result. Just return BASE otherwise.
1910 TEMP is available as a temporary register if needed.
1912 The returned expression can be used as the first operand to a LO_SUM. */
1915 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1916 enum mips_symbol_type symbol_type)
1918 if (mips_split_p[symbol_type])
1920 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1921 addr = mips_force_temporary (temp, addr);
1922 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1928 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1929 mips_force_temporary; it is only needed when OFFSET is not a
1933 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1935 if (!SMALL_OPERAND (offset))
1940 /* Load the full offset into a register so that we can use
1941 an unextended instruction for the address itself. */
1942 high = GEN_INT (offset);
1947 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1948 high = GEN_INT (CONST_HIGH_PART (offset));
1949 offset = CONST_LOW_PART (offset);
1951 high = mips_force_temporary (temp, high);
1952 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1954 return plus_constant (reg, offset);
1957 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1958 referencing, and TYPE is the symbol type to use (either global
1959 dynamic or local dynamic). V0 is an RTX for the return value
1960 location. The entire insn sequence is returned. */
1962 static GTY(()) rtx mips_tls_symbol;
1965 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
1967 rtx insn, loc, tga, a0;
1969 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
1971 if (!mips_tls_symbol)
1972 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
1974 loc = mips_unspec_address (sym, type);
1978 emit_insn (gen_rtx_SET (Pmode, a0,
1979 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
1980 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
1981 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
1982 CONST_OR_PURE_CALL_P (insn) = 1;
1983 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
1984 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
1985 insn = get_insns ();
1992 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
1993 return value will be a valid address and move_operand (either a REG
1997 mips_legitimize_tls_address (rtx loc)
1999 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2000 enum tls_model model;
2002 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2003 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2005 model = SYMBOL_REF_TLS_MODEL (loc);
2006 /* Only TARGET_ABICALLS code can have more than one module; other
2007 code must be be static and should not use a GOT. All TLS models
2008 reduce to local exec in this situation. */
2009 if (!TARGET_ABICALLS)
2010 model = TLS_MODEL_LOCAL_EXEC;
2014 case TLS_MODEL_GLOBAL_DYNAMIC:
2015 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2016 dest = gen_reg_rtx (Pmode);
2017 emit_libcall_block (insn, dest, v0, loc);
2020 case TLS_MODEL_LOCAL_DYNAMIC:
2021 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2022 tmp1 = gen_reg_rtx (Pmode);
2024 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2025 share the LDM result with other LD model accesses. */
2026 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2028 emit_libcall_block (insn, tmp1, v0, eqv);
2030 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2031 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2032 mips_unspec_address (loc, SYMBOL_DTPREL));
2035 case TLS_MODEL_INITIAL_EXEC:
2036 tmp1 = gen_reg_rtx (Pmode);
2037 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2038 if (Pmode == DImode)
2040 emit_insn (gen_tls_get_tp_di (v1));
2041 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2045 emit_insn (gen_tls_get_tp_si (v1));
2046 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2048 dest = gen_reg_rtx (Pmode);
2049 emit_insn (gen_add3_insn (dest, tmp1, v1));
2052 case TLS_MODEL_LOCAL_EXEC:
2053 if (Pmode == DImode)
2054 emit_insn (gen_tls_get_tp_di (v1));
2056 emit_insn (gen_tls_get_tp_si (v1));
2058 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2059 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2060 mips_unspec_address (loc, SYMBOL_TPREL));
2070 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2071 be legitimized in a way that the generic machinery might not expect,
2072 put the new address in *XLOC and return true. MODE is the mode of
2073 the memory being accessed. */
2076 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2078 enum mips_symbol_type symbol_type;
2080 if (mips_tls_operand_p (*xloc))
2082 *xloc = mips_legitimize_tls_address (*xloc);
2086 /* See if the address can split into a high part and a LO_SUM. */
2087 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2088 && mips_symbolic_address_p (symbol_type, mode)
2089 && mips_split_p[symbol_type])
2091 *xloc = mips_split_symbol (0, *xloc);
2095 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2097 /* Handle REG + CONSTANT using mips_add_offset. */
2100 reg = XEXP (*xloc, 0);
2101 if (!mips_valid_base_register_p (reg, mode, 0))
2102 reg = copy_to_mode_reg (Pmode, reg);
2103 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2111 /* Subroutine of mips_build_integer (with the same interface).
2112 Assume that the final action in the sequence should be a left shift. */
2115 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2117 unsigned int i, shift;
2119 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2120 since signed numbers are easier to load than unsigned ones. */
2122 while ((value & 1) == 0)
2123 value /= 2, shift++;
2125 i = mips_build_integer (codes, value);
2126 codes[i].code = ASHIFT;
2127 codes[i].value = shift;
2132 /* As for mips_build_shift, but assume that the final action will be
2133 an IOR or PLUS operation. */
2136 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2138 unsigned HOST_WIDE_INT high;
2141 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2142 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2144 /* The constant is too complex to load with a simple lui/ori pair
2145 so our goal is to clear as many trailing zeros as possible.
2146 In this case, we know bit 16 is set and that the low 16 bits
2147 form a negative number. If we subtract that number from VALUE,
2148 we will clear at least the lowest 17 bits, maybe more. */
2149 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2150 codes[i].code = PLUS;
2151 codes[i].value = CONST_LOW_PART (value);
2155 i = mips_build_integer (codes, high);
2156 codes[i].code = IOR;
2157 codes[i].value = value & 0xffff;
2163 /* Fill CODES with a sequence of rtl operations to load VALUE.
2164 Return the number of operations needed. */
2167 mips_build_integer (struct mips_integer_op *codes,
2168 unsigned HOST_WIDE_INT value)
2170 if (SMALL_OPERAND (value)
2171 || SMALL_OPERAND_UNSIGNED (value)
2172 || LUI_OPERAND (value))
2174 /* The value can be loaded with a single instruction. */
2175 codes[0].code = UNKNOWN;
2176 codes[0].value = value;
2179 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2181 /* Either the constant is a simple LUI/ORI combination or its
2182 lowest bit is set. We don't want to shift in this case. */
2183 return mips_build_lower (codes, value);
2185 else if ((value & 0xffff) == 0)
2187 /* The constant will need at least three actions. The lowest
2188 16 bits are clear, so the final action will be a shift. */
2189 return mips_build_shift (codes, value);
2193 /* The final action could be a shift, add or inclusive OR.
2194 Rather than use a complex condition to select the best
2195 approach, try both mips_build_shift and mips_build_lower
2196 and pick the one that gives the shortest sequence.
2197 Note that this case is only used once per constant. */
2198 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2199 unsigned int cost, alt_cost;
2201 cost = mips_build_shift (codes, value);
2202 alt_cost = mips_build_lower (alt_codes, value);
2203 if (alt_cost < cost)
2205 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2213 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2216 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2218 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2219 enum machine_mode mode;
2220 unsigned int i, cost;
2223 mode = GET_MODE (dest);
2224 cost = mips_build_integer (codes, value);
2226 /* Apply each binary operation to X. Invariant: X is a legitimate
2227 source operand for a SET pattern. */
2228 x = GEN_INT (codes[0].value);
2229 for (i = 1; i < cost; i++)
2233 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2237 x = force_reg (mode, x);
2238 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2241 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2245 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2246 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2250 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2254 /* Split moves of big integers into smaller pieces. */
2255 if (splittable_const_int_operand (src, mode))
2257 mips_move_integer (dest, dest, INTVAL (src));
2261 /* Split moves of symbolic constants into high/low pairs. */
2262 if (splittable_symbolic_operand (src, mode))
2264 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2268 if (mips_tls_operand_p (src))
2270 emit_move_insn (dest, mips_legitimize_tls_address (src));
2274 /* If we have (const (plus symbol offset)), load the symbol first
2275 and then add in the offset. This is usually better than forcing
2276 the constant into memory, at least in non-mips16 code. */
2277 split_const (src, &base, &offset);
2279 && offset != const0_rtx
2280 && (!no_new_pseudos || SMALL_INT (offset)))
2282 base = mips_force_temporary (dest, base);
2283 emit_move_insn (dest, mips_add_offset (0, base, INTVAL (offset)));
2287 src = force_const_mem (mode, src);
2289 /* When using explicit relocs, constant pool references are sometimes
2290 not legitimate addresses. */
2291 if (!memory_operand (src, VOIDmode))
2292 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2293 emit_move_insn (dest, src);
2297 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2298 sequence that is valid. */
2301 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2303 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2305 emit_move_insn (dest, force_reg (mode, src));
2309 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2310 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2311 && REG_P (src) && MD_REG_P (REGNO (src))
2312 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2314 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2315 if (GET_MODE_SIZE (mode) <= 4)
2316 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2317 gen_rtx_REG (SImode, REGNO (src)),
2318 gen_rtx_REG (SImode, other_regno)));
2320 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2321 gen_rtx_REG (DImode, REGNO (src)),
2322 gen_rtx_REG (DImode, other_regno)));
2326 /* We need to deal with constants that would be legitimate
2327 immediate_operands but not legitimate move_operands. */
2328 if (CONSTANT_P (src) && !move_operand (src, mode))
2330 mips_legitimize_const_move (mode, dest, src);
2331 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2337 /* We need a lot of little routines to check constant values on the
2338 mips16. These are used to figure out how long the instruction will
2339 be. It would be much better to do this using constraints, but
2340 there aren't nearly enough letters available. */
2343 m16_check_op (rtx op, int low, int high, int mask)
2345 return (GET_CODE (op) == CONST_INT
2346 && INTVAL (op) >= low
2347 && INTVAL (op) <= high
2348 && (INTVAL (op) & mask) == 0);
2352 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2354 return m16_check_op (op, 0x1, 0x8, 0);
2358 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2360 return m16_check_op (op, - 0x8, 0x7, 0);
2364 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2366 return m16_check_op (op, - 0x7, 0x8, 0);
2370 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2372 return m16_check_op (op, - 0x10, 0xf, 0);
2376 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2378 return m16_check_op (op, - 0xf, 0x10, 0);
2382 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2384 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2388 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2390 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2394 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2396 return m16_check_op (op, - 0x80, 0x7f, 0);
2400 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2402 return m16_check_op (op, - 0x7f, 0x80, 0);
2406 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2408 return m16_check_op (op, 0x0, 0xff, 0);
2412 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2414 return m16_check_op (op, - 0xff, 0x0, 0);
2418 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2420 return m16_check_op (op, - 0x1, 0xfe, 0);
2424 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2426 return m16_check_op (op, 0x0, 0xff << 2, 3);
2430 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2432 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2436 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2438 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2442 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2444 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2448 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2450 enum machine_mode mode = GET_MODE (x);
2451 bool float_mode_p = FLOAT_MODE_P (mode);
2458 /* A number between 1 and 8 inclusive is efficient for a shift.
2459 Otherwise, we will need an extended instruction. */
2460 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2461 || (outer_code) == LSHIFTRT)
2463 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2466 *total = COSTS_N_INSNS (1);
2470 /* We can use cmpi for an xor with an unsigned 16-bit value. */
2471 if ((outer_code) == XOR
2472 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2478 /* We may be able to use slt or sltu for a comparison with a
2479 signed 16-bit value. (The boundary conditions aren't quite
2480 right, but this is just a heuristic anyhow.) */
2481 if (((outer_code) == LT || (outer_code) == LE
2482 || (outer_code) == GE || (outer_code) == GT
2483 || (outer_code) == LTU || (outer_code) == LEU
2484 || (outer_code) == GEU || (outer_code) == GTU)
2485 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2491 /* Equality comparisons with 0 are cheap. */
2492 if (((outer_code) == EQ || (outer_code) == NE)
2499 /* Constants in the range 0...255 can be loaded with an unextended
2500 instruction. They are therefore as cheap as a register move.
2502 Given the choice between "li R1,0...255" and "move R1,R2"
2503 (where R2 is a known constant), it is usually better to use "li",
2504 since we do not want to unnecessarily extend the lifetime
2506 if (outer_code == SET
2508 && INTVAL (x) < 256)
2516 /* These can be used anywhere. */
2521 /* Otherwise fall through to the handling below because
2522 we'll need to construct the constant. */
2528 if (LEGITIMATE_CONSTANT_P (x))
2530 *total = COSTS_N_INSNS (1);
2535 /* The value will need to be fetched from the constant pool. */
2536 *total = CONSTANT_POOL_COST;
2542 /* If the address is legitimate, return the number of
2543 instructions it needs, otherwise use the default handling. */
2544 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2547 *total = COSTS_N_INSNS (n + 1);
2554 *total = COSTS_N_INSNS (6);
2558 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2564 if (mode == DImode && !TARGET_64BIT)
2566 *total = COSTS_N_INSNS (2);
2574 if (mode == DImode && !TARGET_64BIT)
2576 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2584 *total = COSTS_N_INSNS (1);
2586 *total = COSTS_N_INSNS (4);
2590 *total = COSTS_N_INSNS (1);
2597 *total = mips_cost->fp_add;
2601 else if (mode == DImode && !TARGET_64BIT)
2603 *total = COSTS_N_INSNS (4);
2609 if (mode == DImode && !TARGET_64BIT)
2611 *total = COSTS_N_INSNS (4);
2618 *total = mips_cost->fp_mult_sf;
2620 else if (mode == DFmode)
2621 *total = mips_cost->fp_mult_df;
2623 else if (mode == SImode)
2624 *total = mips_cost->int_mult_si;
2627 *total = mips_cost->int_mult_di;
2636 *total = mips_cost->fp_div_sf;
2638 *total = mips_cost->fp_div_df;
2647 *total = mips_cost->int_div_di;
2649 *total = mips_cost->int_div_si;
2654 /* A sign extend from SImode to DImode in 64-bit mode is often
2655 zero instructions, because the result can often be used
2656 directly by another instruction; we'll call it one. */
2657 if (TARGET_64BIT && mode == DImode
2658 && GET_MODE (XEXP (x, 0)) == SImode)
2659 *total = COSTS_N_INSNS (1);
2661 *total = COSTS_N_INSNS (2);
2665 if (TARGET_64BIT && mode == DImode
2666 && GET_MODE (XEXP (x, 0)) == SImode)
2667 *total = COSTS_N_INSNS (2);
2669 *total = COSTS_N_INSNS (1);
2673 case UNSIGNED_FLOAT:
2676 case FLOAT_TRUNCATE:
2678 *total = mips_cost->fp_add;
2686 /* Provide the costs of an addressing mode that contains ADDR.
2687 If ADDR is not a valid address, its cost is irrelevant. */
2690 mips_address_cost (rtx addr)
2692 return mips_address_insns (addr, SImode);
2695 /* Return one word of double-word value OP, taking into account the fixed
2696 endianness of certain registers. HIGH_P is true to select the high part,
2697 false to select the low part. */
2700 mips_subword (rtx op, int high_p)
2703 enum machine_mode mode;
2705 mode = GET_MODE (op);
2706 if (mode == VOIDmode)
2709 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2710 byte = UNITS_PER_WORD;
2716 if (FP_REG_P (REGNO (op)))
2717 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2718 if (ACC_HI_REG_P (REGNO (op)))
2719 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2723 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2725 return simplify_gen_subreg (word_mode, op, mode, byte);
2729 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2732 mips_split_64bit_move_p (rtx dest, rtx src)
2737 /* FP->FP moves can be done in a single instruction. */
2738 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2741 /* Check for floating-point loads and stores. They can be done using
2742 ldc1 and sdc1 on MIPS II and above. */
2745 if (FP_REG_RTX_P (dest) && MEM_P (src))
2747 if (FP_REG_RTX_P (src) && MEM_P (dest))
2754 /* Split a 64-bit move from SRC to DEST assuming that
2755 mips_split_64bit_move_p holds.
2757 Moves into and out of FPRs cause some difficulty here. Such moves
2758 will always be DFmode, since paired FPRs are not allowed to store
2759 DImode values. The most natural representation would be two separate
2760 32-bit moves, such as:
2762 (set (reg:SI $f0) (mem:SI ...))
2763 (set (reg:SI $f1) (mem:SI ...))
2765 However, the second insn is invalid because odd-numbered FPRs are
2766 not allowed to store independent values. Use the patterns load_df_low,
2767 load_df_high and store_df_high instead. */
2770 mips_split_64bit_move (rtx dest, rtx src)
2772 if (FP_REG_RTX_P (dest))
2774 /* Loading an FPR from memory or from GPRs. */
2777 dest = gen_lowpart (DFmode, dest);
2778 emit_insn (gen_load_df_low (dest, mips_subword (src, 0)));
2779 emit_insn (gen_mthc1 (dest, mips_subword (src, 1),
2784 emit_insn (gen_load_df_low (copy_rtx (dest),
2785 mips_subword (src, 0)));
2786 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2790 else if (FP_REG_RTX_P (src))
2792 /* Storing an FPR into memory or GPRs. */
2795 src = gen_lowpart (DFmode, src);
2796 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2797 emit_insn (gen_mfhc1 (mips_subword (dest, 1), src));
2801 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2802 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2807 /* The operation can be split into two normal moves. Decide in
2808 which order to do them. */
2811 low_dest = mips_subword (dest, 0);
2812 if (REG_P (low_dest)
2813 && reg_overlap_mentioned_p (low_dest, src))
2815 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2816 emit_move_insn (low_dest, mips_subword (src, 0));
2820 emit_move_insn (low_dest, mips_subword (src, 0));
2821 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2826 /* Return the appropriate instructions to move SRC into DEST. Assume
2827 that SRC is operand 1 and DEST is operand 0. */
2830 mips_output_move (rtx dest, rtx src)
2832 enum rtx_code dest_code, src_code;
2835 dest_code = GET_CODE (dest);
2836 src_code = GET_CODE (src);
2837 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2839 if (dbl_p && mips_split_64bit_move_p (dest, src))
2842 if ((src_code == REG && GP_REG_P (REGNO (src)))
2843 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2845 if (dest_code == REG)
2847 if (GP_REG_P (REGNO (dest)))
2848 return "move\t%0,%z1";
2850 if (MD_REG_P (REGNO (dest)))
2853 if (DSP_ACC_REG_P (REGNO (dest)))
2855 static char retval[] = "mt__\t%z1,%q0";
2856 retval[2] = reg_names[REGNO (dest)][4];
2857 retval[3] = reg_names[REGNO (dest)][5];
2861 if (FP_REG_P (REGNO (dest)))
2862 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2864 if (ALL_COP_REG_P (REGNO (dest)))
2866 static char retval[] = "dmtc_\t%z1,%0";
2868 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2869 return (dbl_p ? retval : retval + 1);
2872 if (dest_code == MEM)
2873 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2875 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2877 if (src_code == REG)
2879 if (DSP_ACC_REG_P (REGNO (src)))
2881 static char retval[] = "mf__\t%0,%q1";
2882 retval[2] = reg_names[REGNO (src)][4];
2883 retval[3] = reg_names[REGNO (src)][5];
2887 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2888 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2890 if (FP_REG_P (REGNO (src)))
2891 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2893 if (ALL_COP_REG_P (REGNO (src)))
2895 static char retval[] = "dmfc_\t%0,%1";
2897 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2898 return (dbl_p ? retval : retval + 1);
2902 if (src_code == MEM)
2903 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2905 if (src_code == CONST_INT)
2907 /* Don't use the X format, because that will give out of
2908 range numbers for 64-bit hosts and 32-bit targets. */
2910 return "li\t%0,%1\t\t\t# %X1";
2912 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2915 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2919 if (src_code == HIGH)
2920 return "lui\t%0,%h1";
2922 if (CONST_GP_P (src))
2923 return "move\t%0,%1";
2925 if (symbolic_operand (src, VOIDmode))
2926 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2928 if (src_code == REG && FP_REG_P (REGNO (src)))
2930 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2932 if (GET_MODE (dest) == V2SFmode)
2933 return "mov.ps\t%0,%1";
2935 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2938 if (dest_code == MEM)
2939 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2941 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2943 if (src_code == MEM)
2944 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2946 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2948 static char retval[] = "l_c_\t%0,%1";
2950 retval[1] = (dbl_p ? 'd' : 'w');
2951 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2954 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2956 static char retval[] = "s_c_\t%1,%0";
2958 retval[1] = (dbl_p ? 'd' : 'w');
2959 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2965 /* Restore $gp from its save slot. Valid only when using o32 or
2969 mips_restore_gp (void)
2973 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2975 address = mips_add_offset (pic_offset_table_rtx,
2976 frame_pointer_needed
2977 ? hard_frame_pointer_rtx
2978 : stack_pointer_rtx,
2979 current_function_outgoing_args_size);
2980 slot = gen_rtx_MEM (Pmode, address);
2982 emit_move_insn (pic_offset_table_rtx, slot);
2983 if (!TARGET_EXPLICIT_RELOCS)
2984 emit_insn (gen_blockage ());
2987 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2990 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2992 emit_insn (gen_rtx_SET (VOIDmode, target,
2993 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2996 /* Return true if CMP1 is a suitable second operand for relational
2997 operator CODE. See also the *sCC patterns in mips.md. */
3000 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3006 return reg_or_0_operand (cmp1, VOIDmode);
3010 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3014 return arith_operand (cmp1, VOIDmode);
3017 return sle_operand (cmp1, VOIDmode);
3020 return sleu_operand (cmp1, VOIDmode);
3027 /* Canonicalize LE or LEU comparisons into LT comparisons when
3028 possible to avoid extra instructions or inverting the
3032 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3033 enum machine_mode mode)
3035 HOST_WIDE_INT original, plus_one;
3037 if (GET_CODE (*cmp1) != CONST_INT)
3040 original = INTVAL (*cmp1);
3041 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3046 if (original < plus_one)
3049 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3058 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3071 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3072 result in TARGET. CMP0 and TARGET are register_operands that have
3073 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3074 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3077 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3078 rtx target, rtx cmp0, rtx cmp1)
3080 /* First see if there is a MIPS instruction that can do this operation
3081 with CMP1 in its current form. If not, try to canonicalize the
3082 comparison to LT. If that fails, try doing the same for the
3083 inverse operation. If that also fails, force CMP1 into a register
3085 if (mips_relational_operand_ok_p (code, cmp1))
3086 mips_emit_binary (code, target, cmp0, cmp1);
3087 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3088 mips_emit_binary (code, target, cmp0, cmp1);
3091 enum rtx_code inv_code = reverse_condition (code);
3092 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3094 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3095 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3097 else if (invert_ptr == 0)
3099 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3100 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3101 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3105 *invert_ptr = !*invert_ptr;
3106 mips_emit_binary (inv_code, target, cmp0, cmp1);
3111 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3112 The register will have the same mode as CMP0. */
3115 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3117 if (cmp1 == const0_rtx)
3120 if (uns_arith_operand (cmp1, VOIDmode))
3121 return expand_binop (GET_MODE (cmp0), xor_optab,
3122 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3124 return expand_binop (GET_MODE (cmp0), sub_optab,
3125 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3128 /* Convert *CODE into a code that can be used in a floating-point
3129 scc instruction (c.<cond>.<fmt>). Return true if the values of
3130 the condition code registers will be inverted, with 0 indicating
3131 that the condition holds. */
3134 mips_reverse_fp_cond_p (enum rtx_code *code)
3141 *code = reverse_condition_maybe_unordered (*code);
3149 /* Convert a comparison into something that can be used in a branch or
3150 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3151 being compared and *CODE is the code used to compare them.
3153 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3154 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3155 otherwise any standard branch condition can be used. The standard branch
3158 - EQ/NE between two registers.
3159 - any comparison between a register and zero. */
3162 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3164 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3166 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3168 *op0 = cmp_operands[0];
3169 *op1 = cmp_operands[1];
3171 else if (*code == EQ || *code == NE)
3175 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3180 *op0 = cmp_operands[0];
3181 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3186 /* The comparison needs a separate scc instruction. Store the
3187 result of the scc in *OP0 and compare it against zero. */
3188 bool invert = false;
3189 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3191 mips_emit_int_relational (*code, &invert, *op0,
3192 cmp_operands[0], cmp_operands[1]);
3193 *code = (invert ? EQ : NE);
3198 enum rtx_code cmp_code;
3200 /* Floating-point tests use a separate c.cond.fmt comparison to
3201 set a condition code register. The branch or conditional move
3202 will then compare that register against zero.
3204 Set CMP_CODE to the code of the comparison instruction and
3205 *CODE to the code that the branch or move should use. */
3207 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3209 ? gen_reg_rtx (CCmode)
3210 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3212 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3216 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3217 Store the result in TARGET and return true if successful.
3219 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3222 mips_emit_scc (enum rtx_code code, rtx target)
3224 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3227 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3228 if (code == EQ || code == NE)
3230 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3231 mips_emit_binary (code, target, zie, const0_rtx);
3234 mips_emit_int_relational (code, 0, target,
3235 cmp_operands[0], cmp_operands[1]);
3239 /* Emit the common code for doing conditional branches.
3240 operand[0] is the label to jump to.
3241 The comparison operands are saved away by cmp{si,di,sf,df}. */
3244 gen_conditional_branch (rtx *operands, enum rtx_code code)
3246 rtx op0, op1, condition;
3248 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3249 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3250 emit_jump_insn (gen_condjump (condition, operands[0]));
3255 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3256 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3259 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3260 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3265 reversed_p = mips_reverse_fp_cond_p (&cond);
3266 cmp_result = gen_reg_rtx (CCV2mode);
3267 emit_insn (gen_scc_ps (cmp_result,
3268 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3270 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3273 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3277 /* Emit the common code for conditional moves. OPERANDS is the array
3278 of operands passed to the conditional move define_expand. */
3281 gen_conditional_move (rtx *operands)
3286 code = GET_CODE (operands[1]);
3287 mips_emit_compare (&code, &op0, &op1, true);
3288 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3289 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3290 gen_rtx_fmt_ee (code,
3293 operands[2], operands[3])));
3296 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3297 the conditional_trap expander. */
3300 mips_gen_conditional_trap (rtx *operands)
3303 enum rtx_code cmp_code = GET_CODE (operands[0]);
3304 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3306 /* MIPS conditional trap machine instructions don't have GT or LE
3307 flavors, so we must invert the comparison and convert to LT and
3308 GE, respectively. */
3311 case GT: cmp_code = LT; break;
3312 case LE: cmp_code = GE; break;
3313 case GTU: cmp_code = LTU; break;
3314 case LEU: cmp_code = GEU; break;
3317 if (cmp_code == GET_CODE (operands[0]))
3319 op0 = cmp_operands[0];
3320 op1 = cmp_operands[1];
3324 op0 = cmp_operands[1];
3325 op1 = cmp_operands[0];
3327 op0 = force_reg (mode, op0);
3328 if (!arith_operand (op1, mode))
3329 op1 = force_reg (mode, op1);
3331 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3332 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3336 /* Load function address ADDR into register DEST. SIBCALL_P is true
3337 if the address is needed for a sibling call. */
3340 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3342 /* If we're generating PIC, and this call is to a global function,
3343 try to allow its address to be resolved lazily. This isn't
3344 possible for NewABI sibcalls since the value of $gp on entry
3345 to the stub would be our caller's gp, not ours. */
3346 if (TARGET_EXPLICIT_RELOCS
3347 && !(sibcall_p && TARGET_NEWABI)
3348 && global_got_operand (addr, VOIDmode))
3350 rtx high, lo_sum_symbol;
3352 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3353 addr, SYMBOL_GOTOFF_CALL);
3354 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3355 if (Pmode == SImode)
3356 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3358 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3361 emit_move_insn (dest, addr);
3365 /* Expand a call or call_value instruction. RESULT is where the
3366 result will go (null for calls), ADDR is the address of the
3367 function, ARGS_SIZE is the size of the arguments and AUX is
3368 the value passed to us by mips_function_arg. SIBCALL_P is true
3369 if we are expanding a sibling call, false if we're expanding
3373 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3375 rtx orig_addr, pattern, insn;
3378 if (!call_insn_operand (addr, VOIDmode))
3380 addr = gen_reg_rtx (Pmode);
3381 mips_load_call_address (addr, orig_addr, sibcall_p);
3385 && mips16_hard_float
3386 && build_mips16_call_stub (result, addr, args_size,
3387 aux == 0 ? 0 : (int) GET_MODE (aux)))
3391 pattern = (sibcall_p
3392 ? gen_sibcall_internal (addr, args_size)
3393 : gen_call_internal (addr, args_size));
3394 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3398 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3399 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3402 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3403 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3406 pattern = (sibcall_p
3407 ? gen_sibcall_value_internal (result, addr, args_size)
3408 : gen_call_value_internal (result, addr, args_size));
3410 insn = emit_call_insn (pattern);
3412 /* Lazy-binding stubs require $gp to be valid on entry. */
3413 if (global_got_operand (orig_addr, VOIDmode))
3414 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3418 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3421 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3422 tree exp ATTRIBUTE_UNUSED)
3424 return TARGET_SIBCALLS;
3427 /* Emit code to move general operand SRC into condition-code
3428 register DEST. SCRATCH is a scratch TFmode float register.
3435 where FP1 and FP2 are single-precision float registers
3436 taken from SCRATCH. */
3439 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3443 /* Change the source to SFmode. */
3445 src = adjust_address (src, SFmode, 0);
3446 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3447 src = gen_rtx_REG (SFmode, true_regnum (src));
3449 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3450 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3452 emit_move_insn (copy_rtx (fp1), src);
3453 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3454 emit_insn (gen_slt_sf (dest, fp2, fp1));
3457 /* Emit code to change the current function's return address to
3458 ADDRESS. SCRATCH is available as a scratch register, if needed.
3459 ADDRESS and SCRATCH are both word-mode GPRs. */
3462 mips_set_return_address (rtx address, rtx scratch)
3466 compute_frame_size (get_frame_size ());
3467 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3468 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3469 cfun->machine->frame.gp_sp_offset);
3471 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3474 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3475 Assume that the areas do not overlap. */
3478 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3480 HOST_WIDE_INT offset, delta;
3481 unsigned HOST_WIDE_INT bits;
3483 enum machine_mode mode;
3486 /* Work out how many bits to move at a time. If both operands have
3487 half-word alignment, it is usually better to move in half words.
3488 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3489 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3490 Otherwise move word-sized chunks. */
3491 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3492 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3493 bits = BITS_PER_WORD / 2;
3495 bits = BITS_PER_WORD;
3497 mode = mode_for_size (bits, MODE_INT, 0);
3498 delta = bits / BITS_PER_UNIT;
3500 /* Allocate a buffer for the temporary registers. */
3501 regs = alloca (sizeof (rtx) * length / delta);
3503 /* Load as many BITS-sized chunks as possible. Use a normal load if
3504 the source has enough alignment, otherwise use left/right pairs. */
3505 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3507 regs[i] = gen_reg_rtx (mode);
3508 if (MEM_ALIGN (src) >= bits)
3509 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3512 rtx part = adjust_address (src, BLKmode, offset);
3513 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3518 /* Copy the chunks to the destination. */
3519 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3520 if (MEM_ALIGN (dest) >= bits)
3521 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3524 rtx part = adjust_address (dest, BLKmode, offset);
3525 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3529 /* Mop up any left-over bytes. */
3530 if (offset < length)
3532 src = adjust_address (src, BLKmode, offset);
3533 dest = adjust_address (dest, BLKmode, offset);
3534 move_by_pieces (dest, src, length - offset,
3535 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3539 #define MAX_MOVE_REGS 4
3540 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3543 /* Helper function for doing a loop-based block operation on memory
3544 reference MEM. Each iteration of the loop will operate on LENGTH
3547 Create a new base register for use within the loop and point it to
3548 the start of MEM. Create a new memory reference that uses this
3549 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3552 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3553 rtx *loop_reg, rtx *loop_mem)
3555 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3557 /* Although the new mem does not refer to a known location,
3558 it does keep up to LENGTH bytes of alignment. */
3559 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3560 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3564 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3565 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3566 memory regions do not overlap. */
3569 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3571 rtx label, src_reg, dest_reg, final_src;
3572 HOST_WIDE_INT leftover;
3574 leftover = length % MAX_MOVE_BYTES;
3577 /* Create registers and memory references for use within the loop. */
3578 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3579 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3581 /* Calculate the value that SRC_REG should have after the last iteration
3583 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3586 /* Emit the start of the loop. */
3587 label = gen_label_rtx ();
3590 /* Emit the loop body. */
3591 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3593 /* Move on to the next block. */
3594 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3595 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3597 /* Emit the loop condition. */
3598 if (Pmode == DImode)
3599 emit_insn (gen_cmpdi (src_reg, final_src));
3601 emit_insn (gen_cmpsi (src_reg, final_src));
3602 emit_jump_insn (gen_bne (label));
3604 /* Mop up any left-over bytes. */
3606 mips_block_move_straight (dest, src, leftover);
3609 /* Expand a movmemsi instruction. */
3612 mips_expand_block_move (rtx dest, rtx src, rtx length)
3614 if (GET_CODE (length) == CONST_INT)
3616 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3618 mips_block_move_straight (dest, src, INTVAL (length));
3623 mips_block_move_loop (dest, src, INTVAL (length));
3630 /* Argument support functions. */
3632 /* Initialize CUMULATIVE_ARGS for a function. */
3635 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3636 rtx libname ATTRIBUTE_UNUSED)
3638 static CUMULATIVE_ARGS zero_cum;
3639 tree param, next_param;
3642 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3644 /* Determine if this function has variable arguments. This is
3645 indicated by the last argument being 'void_type_mode' if there
3646 are no variable arguments. The standard MIPS calling sequence
3647 passes all arguments in the general purpose registers in this case. */
3649 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3650 param != 0; param = next_param)
3652 next_param = TREE_CHAIN (param);
3653 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3654 cum->gp_reg_found = 1;
3659 /* Fill INFO with information about a single argument. CUM is the
3660 cumulative state for earlier arguments. MODE is the mode of this
3661 argument and TYPE is its type (if known). NAMED is true if this
3662 is a named (fixed) argument rather than a variable one. */
3665 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3666 tree type, int named, struct mips_arg_info *info)
3668 bool doubleword_aligned_p;
3669 unsigned int num_bytes, num_words, max_regs;
3671 /* Work out the size of the argument. */
3672 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3673 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3675 /* Decide whether it should go in a floating-point register, assuming
3676 one is free. Later code checks for availability.
3678 The checks against UNITS_PER_FPVALUE handle the soft-float and
3679 single-float cases. */
3683 /* The EABI conventions have traditionally been defined in terms
3684 of TYPE_MODE, regardless of the actual type. */
3685 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3686 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3687 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3692 /* Only leading floating-point scalars are passed in
3693 floating-point registers. We also handle vector floats the same
3694 say, which is OK because they are not covered by the standard ABI. */
3695 info->fpr_p = (!cum->gp_reg_found
3696 && cum->arg_number < 2
3697 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3698 || VECTOR_FLOAT_TYPE_P (type))
3699 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3700 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3701 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3706 /* Scalar and complex floating-point types are passed in
3707 floating-point registers. */
3708 info->fpr_p = (named
3709 && (type == 0 || FLOAT_TYPE_P (type))
3710 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3711 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3712 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3713 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3715 /* ??? According to the ABI documentation, the real and imaginary
3716 parts of complex floats should be passed in individual registers.
3717 The real and imaginary parts of stack arguments are supposed
3718 to be contiguous and there should be an extra word of padding
3721 This has two problems. First, it makes it impossible to use a
3722 single "void *" va_list type, since register and stack arguments
3723 are passed differently. (At the time of writing, MIPSpro cannot
3724 handle complex float varargs correctly.) Second, it's unclear
3725 what should happen when there is only one register free.
3727 For now, we assume that named complex floats should go into FPRs
3728 if there are two FPRs free, otherwise they should be passed in the
3729 same way as a struct containing two floats. */
3731 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3732 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3734 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3735 info->fpr_p = false;
3745 /* See whether the argument has doubleword alignment. */
3746 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3748 /* Set REG_OFFSET to the register count we're interested in.
3749 The EABI allocates the floating-point registers separately,
3750 but the other ABIs allocate them like integer registers. */
3751 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3755 /* Advance to an even register if the argument is doubleword-aligned. */
3756 if (doubleword_aligned_p)
3757 info->reg_offset += info->reg_offset & 1;
3759 /* Work out the offset of a stack argument. */
3760 info->stack_offset = cum->stack_words;
3761 if (doubleword_aligned_p)
3762 info->stack_offset += info->stack_offset & 1;
3764 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3766 /* Partition the argument between registers and stack. */
3767 info->reg_words = MIN (num_words, max_regs);
3768 info->stack_words = num_words - info->reg_words;
3772 /* Implement FUNCTION_ARG_ADVANCE. */
3775 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3776 tree type, int named)
3778 struct mips_arg_info info;
3780 mips_arg_info (cum, mode, type, named, &info);
3783 cum->gp_reg_found = true;
3785 /* See the comment above the cumulative args structure in mips.h
3786 for an explanation of what this code does. It assumes the O32
3787 ABI, which passes at most 2 arguments in float registers. */
3788 if (cum->arg_number < 2 && info.fpr_p)
3789 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3791 if (mips_abi != ABI_EABI || !info.fpr_p)
3792 cum->num_gprs = info.reg_offset + info.reg_words;
3793 else if (info.reg_words > 0)
3794 cum->num_fprs += FP_INC;
3796 if (info.stack_words > 0)
3797 cum->stack_words = info.stack_offset + info.stack_words;
3802 /* Implement FUNCTION_ARG. */
3805 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3806 tree type, int named)
3808 struct mips_arg_info info;
3810 /* We will be called with a mode of VOIDmode after the last argument
3811 has been seen. Whatever we return will be passed to the call
3812 insn. If we need a mips16 fp_code, return a REG with the code
3813 stored as the mode. */
3814 if (mode == VOIDmode)
3816 if (TARGET_MIPS16 && cum->fp_code != 0)
3817 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3823 mips_arg_info (cum, mode, type, named, &info);
3825 /* Return straight away if the whole argument is passed on the stack. */
3826 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3830 && TREE_CODE (type) == RECORD_TYPE
3832 && TYPE_SIZE_UNIT (type)
3833 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3836 /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
3837 structure contains a double in its entirety, then that 64-bit
3838 chunk is passed in a floating point register. */
3841 /* First check to see if there is any such field. */
3842 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3843 if (TREE_CODE (field) == FIELD_DECL
3844 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3845 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3846 && host_integerp (bit_position (field), 0)
3847 && int_bit_position (field) % BITS_PER_WORD == 0)
3852 /* Now handle the special case by returning a PARALLEL
3853 indicating where each 64-bit chunk goes. INFO.REG_WORDS
3854 chunks are passed in registers. */
3856 HOST_WIDE_INT bitpos;
3859 /* assign_parms checks the mode of ENTRY_PARM, so we must
3860 use the actual mode here. */
3861 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3864 field = TYPE_FIELDS (type);
3865 for (i = 0; i < info.reg_words; i++)
3869 for (; field; field = TREE_CHAIN (field))
3870 if (TREE_CODE (field) == FIELD_DECL
3871 && int_bit_position (field) >= bitpos)
3875 && int_bit_position (field) == bitpos
3876 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3877 && !TARGET_SOFT_FLOAT
3878 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3879 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3881 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3884 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3885 GEN_INT (bitpos / BITS_PER_UNIT));
3887 bitpos += BITS_PER_WORD;
3893 /* Handle the n32/n64 conventions for passing complex floating-point
3894 arguments in FPR pairs. The real part goes in the lower register
3895 and the imaginary part goes in the upper register. */
3898 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3901 enum machine_mode inner;
3904 inner = GET_MODE_INNER (mode);
3905 reg = FP_ARG_FIRST + info.reg_offset;
3906 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
3908 /* Real part in registers, imaginary part on stack. */
3909 gcc_assert (info.stack_words == info.reg_words);
3910 return gen_rtx_REG (inner, reg);
3914 gcc_assert (info.stack_words == 0);
3915 real = gen_rtx_EXPR_LIST (VOIDmode,
3916 gen_rtx_REG (inner, reg),
3918 imag = gen_rtx_EXPR_LIST (VOIDmode,
3920 reg + info.reg_words / 2),
3921 GEN_INT (GET_MODE_SIZE (inner)));
3922 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3927 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3928 else if (info.reg_offset == 1)
3929 /* This code handles the special o32 case in which the second word
3930 of the argument structure is passed in floating-point registers. */
3931 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3933 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3937 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3940 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3941 enum machine_mode mode, tree type, bool named)
3943 struct mips_arg_info info;
3945 mips_arg_info (cum, mode, type, named, &info);
3946 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3950 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3951 PARM_BOUNDARY bits of alignment, but will be given anything up
3952 to STACK_BOUNDARY bits if the type requires it. */
3955 function_arg_boundary (enum machine_mode mode, tree type)
3957 unsigned int alignment;
3959 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3960 if (alignment < PARM_BOUNDARY)
3961 alignment = PARM_BOUNDARY;
3962 if (alignment > STACK_BOUNDARY)
3963 alignment = STACK_BOUNDARY;
3967 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3968 upward rather than downward. In other words, return true if the
3969 first byte of the stack slot has useful data, false if the last
3973 mips_pad_arg_upward (enum machine_mode mode, tree type)
3975 /* On little-endian targets, the first byte of every stack argument
3976 is passed in the first byte of the stack slot. */
3977 if (!BYTES_BIG_ENDIAN)
3980 /* Otherwise, integral types are padded downward: the last byte of a
3981 stack argument is passed in the last byte of the stack slot. */
3983 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3984 : GET_MODE_CLASS (mode) == MODE_INT)
3987 /* Big-endian o64 pads floating-point arguments downward. */
3988 if (mips_abi == ABI_O64)
3989 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3992 /* Other types are padded upward for o32, o64, n32 and n64. */
3993 if (mips_abi != ABI_EABI)
3996 /* Arguments smaller than a stack slot are padded downward. */
3997 if (mode != BLKmode)
3998 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4000 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4004 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4005 if the least significant byte of the register has useful data. Return
4006 the opposite if the most significant byte does. */
4009 mips_pad_reg_upward (enum machine_mode mode, tree type)
4011 /* No shifting is required for floating-point arguments. */
4012 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4013 return !BYTES_BIG_ENDIAN;
4015 /* Otherwise, apply the same padding to register arguments as we do
4016 to stack arguments. */
4017 return mips_pad_arg_upward (mode, type);
4021 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4022 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4025 CUMULATIVE_ARGS local_cum;
4026 int gp_saved, fp_saved;
4028 /* The caller has advanced CUM up to, but not beyond, the last named
4029 argument. Advance a local copy of CUM past the last "real" named
4030 argument, to find out how many registers are left over. */
4033 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4035 /* Found out how many registers we need to save. */
4036 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4037 fp_saved = (EABI_FLOAT_VARARGS_P
4038 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4047 ptr = plus_constant (virtual_incoming_args_rtx,
4048 REG_PARM_STACK_SPACE (cfun->decl)
4049 - gp_saved * UNITS_PER_WORD);
4050 mem = gen_rtx_MEM (BLKmode, ptr);
4051 set_mem_alias_set (mem, get_varargs_alias_set ());
4053 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4058 /* We can't use move_block_from_reg, because it will use
4060 enum machine_mode mode;
4063 /* Set OFF to the offset from virtual_incoming_args_rtx of
4064 the first float register. The FP save area lies below
4065 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4066 off = -gp_saved * UNITS_PER_WORD;
4067 off &= ~(UNITS_PER_FPVALUE - 1);
4068 off -= fp_saved * UNITS_PER_FPREG;
4070 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4072 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4076 ptr = plus_constant (virtual_incoming_args_rtx, off);
4077 mem = gen_rtx_MEM (mode, ptr);
4078 set_mem_alias_set (mem, get_varargs_alias_set ());
4079 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4080 off += UNITS_PER_HWFPVALUE;
4084 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4085 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4086 + fp_saved * UNITS_PER_FPREG);
4089 /* Create the va_list data type.
4090 We keep 3 pointers, and two offsets.
4091 Two pointers are to the overflow area, which starts at the CFA.
4092 One of these is constant, for addressing into the GPR save area below it.
4093 The other is advanced up the stack through the overflow region.
4094 The third pointer is to the GPR save area. Since the FPR save area
4095 is just below it, we can address FPR slots off this pointer.
4096 We also keep two one-byte offsets, which are to be subtracted from the
4097 constant pointers to yield addresses in the GPR and FPR save areas.
4098 These are downcounted as float or non-float arguments are used,
4099 and when they get to zero, the argument must be obtained from the
4101 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4102 pointer is enough. It's started at the GPR save area, and is
4104 Note that the GPR save area is not constant size, due to optimization
4105 in the prologue. Hence, we can't use a design with two pointers
4106 and two offsets, although we could have designed this with two pointers
4107 and three offsets. */
4110 mips_build_builtin_va_list (void)
4112 if (EABI_FLOAT_VARARGS_P)
4114 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4117 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4119 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4121 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4123 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4125 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4126 unsigned_char_type_node);
4127 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4128 unsigned_char_type_node);
4129 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4130 warn on every user file. */
4131 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4132 array = build_array_type (unsigned_char_type_node,
4133 build_index_type (index));
4134 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4136 DECL_FIELD_CONTEXT (f_ovfl) = record;
4137 DECL_FIELD_CONTEXT (f_gtop) = record;
4138 DECL_FIELD_CONTEXT (f_ftop) = record;
4139 DECL_FIELD_CONTEXT (f_goff) = record;
4140 DECL_FIELD_CONTEXT (f_foff) = record;
4141 DECL_FIELD_CONTEXT (f_res) = record;
4143 TYPE_FIELDS (record) = f_ovfl;
4144 TREE_CHAIN (f_ovfl) = f_gtop;
4145 TREE_CHAIN (f_gtop) = f_ftop;
4146 TREE_CHAIN (f_ftop) = f_goff;
4147 TREE_CHAIN (f_goff) = f_foff;
4148 TREE_CHAIN (f_foff) = f_res;
4150 layout_type (record);
4153 else if (TARGET_IRIX && TARGET_IRIX6)
4154 /* On IRIX 6, this type is 'char *'. */
4155 return build_pointer_type (char_type_node);
4157 /* Otherwise, we use 'void *'. */
4158 return ptr_type_node;
4161 /* Implement va_start. */
4164 mips_va_start (tree valist, rtx nextarg)
4166 if (EABI_FLOAT_VARARGS_P)
4168 const CUMULATIVE_ARGS *cum;
4169 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4170 tree ovfl, gtop, ftop, goff, foff;
4172 int gpr_save_area_size;
4173 int fpr_save_area_size;
4176 cum = ¤t_function_args_info;
4178 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4180 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4182 f_ovfl = TYPE_FIELDS (va_list_type_node);
4183 f_gtop = TREE_CHAIN (f_ovfl);
4184 f_ftop = TREE_CHAIN (f_gtop);
4185 f_goff = TREE_CHAIN (f_ftop);
4186 f_foff = TREE_CHAIN (f_goff);
4188 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4190 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4192 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4194 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4196 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4199 /* Emit code to initialize OVFL, which points to the next varargs
4200 stack argument. CUM->STACK_WORDS gives the number of stack
4201 words used by named arguments. */
4202 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4203 if (cum->stack_words > 0)
4204 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t,
4205 build_int_cst (NULL_TREE,
4206 cum->stack_words * UNITS_PER_WORD));
4207 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4208 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4210 /* Emit code to initialize GTOP, the top of the GPR save area. */
4211 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4212 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
4213 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4215 /* Emit code to initialize FTOP, the top of the FPR save area.
4216 This address is gpr_save_area_bytes below GTOP, rounded
4217 down to the next fp-aligned boundary. */
4218 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4219 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4220 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4222 t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t,
4223 build_int_cst (NULL_TREE, -fpr_offset));
4224 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
4225 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4227 /* Emit code to initialize GOFF, the offset from GTOP of the
4228 next GPR argument. */
4229 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
4230 build_int_cst (NULL_TREE, gpr_save_area_size));
4231 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4233 /* Likewise emit code to initialize FOFF, the offset from FTOP
4234 of the next FPR argument. */
4235 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
4236 build_int_cst (NULL_TREE, fpr_save_area_size));
4237 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4241 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4242 std_expand_builtin_va_start (valist, nextarg);
4246 /* Implement va_arg. */
4249 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4251 HOST_WIDE_INT size, rsize;
4255 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4258 type = build_pointer_type (type);
4260 size = int_size_in_bytes (type);
4261 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4263 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4264 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4267 /* Not a simple merged stack. */
4269 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4270 tree ovfl, top, off, align;
4271 HOST_WIDE_INT osize;
4274 f_ovfl = TYPE_FIELDS (va_list_type_node);
4275 f_gtop = TREE_CHAIN (f_ovfl);
4276 f_ftop = TREE_CHAIN (f_gtop);
4277 f_goff = TREE_CHAIN (f_ftop);
4278 f_foff = TREE_CHAIN (f_goff);
4280 /* We maintain separate pointers and offsets for floating-point
4281 and integer arguments, but we need similar code in both cases.
4284 TOP be the top of the register save area;
4285 OFF be the offset from TOP of the next register;
4286 ADDR_RTX be the address of the argument;
4287 RSIZE be the number of bytes used to store the argument
4288 when it's in the register save area;
4289 OSIZE be the number of bytes used to store it when it's
4290 in the stack overflow area; and
4291 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4293 The code we want is:
4295 1: off &= -rsize; // round down
4298 4: addr_rtx = top - off;
4303 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4304 10: addr_rtx = ovfl + PADDING;
4308 [1] and [9] can sometimes be optimized away. */
4310 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4313 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4314 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4316 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4318 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4321 /* When floating-point registers are saved to the stack,
4322 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4323 of the float's precision. */
4324 rsize = UNITS_PER_HWFPVALUE;
4326 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4327 (= PARM_BOUNDARY bits). This can be different from RSIZE
4330 (1) On 32-bit targets when TYPE is a structure such as:
4332 struct s { float f; };
4334 Such structures are passed in paired FPRs, so RSIZE
4335 will be 8 bytes. However, the structure only takes
4336 up 4 bytes of memory, so OSIZE will only be 4.
4338 (2) In combinations such as -mgp64 -msingle-float
4339 -fshort-double. Doubles passed in registers
4340 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4341 but those passed on the stack take up
4342 UNITS_PER_WORD bytes. */
4343 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4347 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4349 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4351 if (rsize > UNITS_PER_WORD)
4353 /* [1] Emit code for: off &= -rsize. */
4354 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4355 build_int_cst (NULL_TREE, -rsize));
4356 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
4357 gimplify_and_add (t, pre_p);
4362 /* [2] Emit code to branch if off == 0. */
4363 t = build2 (NE_EXPR, boolean_type_node, off,
4364 build_int_cst (TREE_TYPE (off), 0));
4365 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4367 /* [5] Emit code for: off -= rsize. We do this as a form of
4368 post-increment not available to C. Also widen for the
4369 coming pointer arithmetic. */
4370 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4371 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4372 t = fold_convert (sizetype, t);
4373 t = fold_convert (TREE_TYPE (top), t);
4375 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4376 the argument has RSIZE - SIZE bytes of leading padding. */
4377 t = build2 (MINUS_EXPR, TREE_TYPE (top), top, t);
4378 if (BYTES_BIG_ENDIAN && rsize > size)
4380 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4382 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4384 COND_EXPR_THEN (addr) = t;
4386 if (osize > UNITS_PER_WORD)
4388 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4389 u = fold_convert (TREE_TYPE (ovfl),
4390 build_int_cst (NULL_TREE, osize - 1));
4391 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4392 u = fold_convert (TREE_TYPE (ovfl),
4393 build_int_cst (NULL_TREE, -osize));
4394 t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4395 align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4400 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4401 post-increment ovfl by osize. On big-endian machines,
4402 the argument has OSIZE - SIZE bytes of leading padding. */
4403 u = fold_convert (TREE_TYPE (ovfl),
4404 build_int_cst (NULL_TREE, osize));
4405 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4406 if (BYTES_BIG_ENDIAN && osize > size)
4408 u = fold_convert (TREE_TYPE (t),
4409 build_int_cst (NULL_TREE, osize - size));
4410 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4413 /* String [9] and [10,11] together. */
4415 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4416 COND_EXPR_ELSE (addr) = t;
4418 addr = fold_convert (build_pointer_type (type), addr);
4419 addr = build_va_arg_indirect_ref (addr);
4423 addr = build_va_arg_indirect_ref (addr);
4428 /* Return true if it is possible to use left/right accesses for a
4429 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4430 returning true, update *OP, *LEFT and *RIGHT as follows:
4432 *OP is a BLKmode reference to the whole field.
4434 *LEFT is a QImode reference to the first byte if big endian or
4435 the last byte if little endian. This address can be used in the
4436 left-side instructions (lwl, swl, ldl, sdl).
4438 *RIGHT is a QImode reference to the opposite end of the field and
4439 can be used in the patterning right-side instruction. */
4442 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4443 rtx *left, rtx *right)
4447 /* Check that the operand really is a MEM. Not all the extv and
4448 extzv predicates are checked. */
4452 /* Check that the size is valid. */
4453 if (width != 32 && (!TARGET_64BIT || width != 64))
4456 /* We can only access byte-aligned values. Since we are always passed
4457 a reference to the first byte of the field, it is not necessary to
4458 do anything with BITPOS after this check. */
4459 if (bitpos % BITS_PER_UNIT != 0)
4462 /* Reject aligned bitfields: we want to use a normal load or store
4463 instead of a left/right pair. */
4464 if (MEM_ALIGN (*op) >= width)
4467 /* Adjust *OP to refer to the whole field. This also has the effect
4468 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4469 *op = adjust_address (*op, BLKmode, 0);
4470 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4472 /* Get references to both ends of the field. We deliberately don't
4473 use the original QImode *OP for FIRST since the new BLKmode one
4474 might have a simpler address. */
4475 first = adjust_address (*op, QImode, 0);
4476 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4478 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4479 be the upper word and RIGHT the lower word. */
4480 if (TARGET_BIG_ENDIAN)
4481 *left = first, *right = last;
4483 *left = last, *right = first;
4489 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4490 Return true on success. We only handle cases where zero_extract is
4491 equivalent to sign_extract. */
4494 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4496 rtx left, right, temp;
4498 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4499 paradoxical word_mode subreg. This is the only case in which
4500 we allow the destination to be larger than the source. */
4501 if (GET_CODE (dest) == SUBREG
4502 && GET_MODE (dest) == DImode
4503 && SUBREG_BYTE (dest) == 0
4504 && GET_MODE (SUBREG_REG (dest)) == SImode)
4505 dest = SUBREG_REG (dest);
4507 /* After the above adjustment, the destination must be the same
4508 width as the source. */
4509 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4512 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4515 temp = gen_reg_rtx (GET_MODE (dest));
4516 if (GET_MODE (dest) == DImode)
4518 emit_insn (gen_mov_ldl (temp, src, left));
4519 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4523 emit_insn (gen_mov_lwl (temp, src, left));
4524 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4530 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4534 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4537 enum machine_mode mode;
4539 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4542 mode = mode_for_size (width, MODE_INT, 0);
4543 src = gen_lowpart (mode, src);
4547 emit_insn (gen_mov_sdl (dest, src, left));
4548 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4552 emit_insn (gen_mov_swl (dest, src, left));
4553 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4558 /* Return true if X is a MEM with the same size as MODE. */
4561 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4568 size = MEM_SIZE (x);
4569 return size && INTVAL (size) == GET_MODE_SIZE (mode);
4572 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4573 source of an "ext" instruction or the destination of an "ins"
4574 instruction. OP must be a register operand and the following
4575 conditions must hold:
4577 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4578 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4579 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4581 Also reject lengths equal to a word as they are better handled
4582 by the move patterns. */
4585 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4587 HOST_WIDE_INT len, pos;
4589 if (!ISA_HAS_EXT_INS
4590 || !register_operand (op, VOIDmode)
4591 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4594 len = INTVAL (size);
4595 pos = INTVAL (position);
4597 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4598 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4604 /* Set up globals to generate code for the ISA or processor
4605 described by INFO. */
4608 mips_set_architecture (const struct mips_cpu_info *info)
4612 mips_arch_info = info;
4613 mips_arch = info->cpu;
4614 mips_isa = info->isa;
4619 /* Likewise for tuning. */
4622 mips_set_tune (const struct mips_cpu_info *info)
4626 mips_tune_info = info;
4627 mips_tune = info->cpu;
4631 /* Implement TARGET_HANDLE_OPTION. */
4634 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4639 if (strcmp (arg, "32") == 0)
4641 else if (strcmp (arg, "o64") == 0)
4643 else if (strcmp (arg, "n32") == 0)
4645 else if (strcmp (arg, "64") == 0)
4647 else if (strcmp (arg, "eabi") == 0)
4648 mips_abi = ABI_EABI;
4655 return mips_parse_cpu (arg) != 0;
4658 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4659 return mips_isa_info != 0;
4661 case OPT_mno_flush_func:
4662 mips_cache_flush_func = NULL;
4670 /* Set up the threshold for data to go into the small data area, instead
4671 of the normal data area, and detect any conflicts in the switches. */
4674 override_options (void)
4676 int i, start, regno;
4677 enum machine_mode mode;
4679 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4681 /* The following code determines the architecture and register size.
4682 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4683 The GAS and GCC code should be kept in sync as much as possible. */
4685 if (mips_arch_string != 0)
4686 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4688 if (mips_isa_info != 0)
4690 if (mips_arch_info == 0)
4691 mips_set_architecture (mips_isa_info);
4692 else if (mips_arch_info->isa != mips_isa_info->isa)
4693 error ("-%s conflicts with the other architecture options, "
4694 "which specify a %s processor",
4695 mips_isa_info->name,
4696 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4699 if (mips_arch_info == 0)
4701 #ifdef MIPS_CPU_STRING_DEFAULT
4702 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4704 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4708 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4709 error ("-march=%s is not compatible with the selected ABI",
4710 mips_arch_info->name);
4712 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4713 if (mips_tune_string != 0)
4714 mips_set_tune (mips_parse_cpu (mips_tune_string));
4716 if (mips_tune_info == 0)
4717 mips_set_tune (mips_arch_info);
4719 /* Set cost structure for the processor. */
4721 mips_cost = &mips_rtx_cost_optimize_size;
4723 mips_cost = &mips_rtx_cost_data[mips_tune];
4725 if ((target_flags_explicit & MASK_64BIT) != 0)
4727 /* The user specified the size of the integer registers. Make sure
4728 it agrees with the ABI and ISA. */
4729 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4730 error ("-mgp64 used with a 32-bit processor");
4731 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4732 error ("-mgp32 used with a 64-bit ABI");
4733 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4734 error ("-mgp64 used with a 32-bit ABI");
4738 /* Infer the integer register size from the ABI and processor.
4739 Restrict ourselves to 32-bit registers if that's all the
4740 processor has, or if the ABI cannot handle 64-bit registers. */
4741 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4742 target_flags &= ~MASK_64BIT;
4744 target_flags |= MASK_64BIT;
4747 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4749 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4750 only one right answer here. */
4751 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4752 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4753 else if (!TARGET_64BIT && TARGET_FLOAT64
4754 && !(ISA_HAS_MXHC1 && mips_abi == ABI_32))
4755 error ("-mgp32 and -mfp64 can only be combined if the target"
4756 " supports the mfhc1 and mthc1 instructions");
4757 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4758 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4762 /* -msingle-float selects 32-bit float registers. Otherwise the
4763 float registers should be the same size as the integer ones. */
4764 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4765 target_flags |= MASK_FLOAT64;
4767 target_flags &= ~MASK_FLOAT64;
4770 /* End of code shared with GAS. */
4772 if ((target_flags_explicit & MASK_LONG64) == 0)
4774 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4775 target_flags |= MASK_LONG64;
4777 target_flags &= ~MASK_LONG64;
4780 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4781 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4783 /* For some configurations, it is useful to have -march control
4784 the default setting of MASK_SOFT_FLOAT. */
4785 switch ((int) mips_arch)
4787 case PROCESSOR_R4100:
4788 case PROCESSOR_R4111:
4789 case PROCESSOR_R4120:
4790 case PROCESSOR_R4130:
4791 target_flags |= MASK_SOFT_FLOAT;
4795 target_flags &= ~MASK_SOFT_FLOAT;
4801 flag_pcc_struct_return = 0;
4803 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4805 /* If neither -mbranch-likely nor -mno-branch-likely was given
4806 on the command line, set MASK_BRANCHLIKELY based on the target
4809 By default, we enable use of Branch Likely instructions on
4810 all architectures which support them with the following
4811 exceptions: when creating MIPS32 or MIPS64 code, and when
4812 tuning for architectures where their use tends to hurt
4815 The MIPS32 and MIPS64 architecture specifications say "Software
4816 is strongly encouraged to avoid use of Branch Likely
4817 instructions, as they will be removed from a future revision
4818 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4819 issue those instructions unless instructed to do so by
4821 if (ISA_HAS_BRANCHLIKELY
4822 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4823 && !(TUNE_MIPS5500 || TUNE_SB1))
4824 target_flags |= MASK_BRANCHLIKELY;
4826 target_flags &= ~MASK_BRANCHLIKELY;
4828 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4829 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4831 /* The effect of -mabicalls isn't defined for the EABI. */
4832 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4834 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4835 target_flags &= ~MASK_ABICALLS;
4838 if (TARGET_ABICALLS)
4840 /* We need to set flag_pic for executables as well as DSOs
4841 because we may reference symbols that are not defined in
4842 the final executable. (MIPS does not use things like
4843 copy relocs, for example.)
4845 Also, there is a body of code that uses __PIC__ to distinguish
4846 between -mabicalls and -mno-abicalls code. */
4848 if (mips_section_threshold > 0)
4849 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
4852 /* mips_split_addresses is a half-way house between explicit
4853 relocations and the traditional assembler macros. It can
4854 split absolute 32-bit symbolic constants into a high/lo_sum
4855 pair but uses macros for other sorts of access.
4857 Like explicit relocation support for REL targets, it relies
4858 on GNU extensions in the assembler and the linker.
4860 Although this code should work for -O0, it has traditionally
4861 been treated as an optimization. */
4862 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4863 && optimize && !flag_pic
4864 && !ABI_HAS_64BIT_SYMBOLS)
4865 mips_split_addresses = 1;
4867 mips_split_addresses = 0;
4869 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4870 faster code, but at the expense of more nops. Enable it at -O3 and
4872 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4873 target_flags |= MASK_VR4130_ALIGN;
4875 /* When compiling for the mips16, we cannot use floating point. We
4876 record the original hard float value in mips16_hard_float. */
4879 if (TARGET_SOFT_FLOAT)
4880 mips16_hard_float = 0;
4882 mips16_hard_float = 1;
4883 target_flags |= MASK_SOFT_FLOAT;
4885 /* Don't run the scheduler before reload, since it tends to
4886 increase register pressure. */
4887 flag_schedule_insns = 0;
4889 /* Don't do hot/cold partitioning. The constant layout code expects
4890 the whole function to be in a single section. */
4891 flag_reorder_blocks_and_partition = 0;
4893 /* Silently disable -mexplicit-relocs since it doesn't apply
4894 to mips16 code. Even so, it would overly pedantic to warn
4895 about "-mips16 -mexplicit-relocs", especially given that
4896 we use a %gprel() operator. */
4897 target_flags &= ~MASK_EXPLICIT_RELOCS;
4900 /* When using explicit relocs, we call dbr_schedule from within
4902 if (TARGET_EXPLICIT_RELOCS)
4904 mips_flag_delayed_branch = flag_delayed_branch;
4905 flag_delayed_branch = 0;
4908 #ifdef MIPS_TFMODE_FORMAT
4909 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4912 /* Make sure that the user didn't turn off paired single support when
4913 MIPS-3D support is requested. */
4914 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4915 && !TARGET_PAIRED_SINGLE_FLOAT)
4916 error ("-mips3d requires -mpaired-single");
4918 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4920 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4922 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4923 and TARGET_HARD_FLOAT are both true. */
4924 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4925 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4927 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4929 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4930 error ("-mips3d/-mpaired-single must be used with -mips64");
4932 if (TARGET_MIPS16 && TARGET_DSP)
4933 error ("-mips16 and -mdsp cannot be used together");
4935 mips_print_operand_punct['?'] = 1;
4936 mips_print_operand_punct['#'] = 1;
4937 mips_print_operand_punct['/'] = 1;
4938 mips_print_operand_punct['&'] = 1;
4939 mips_print_operand_punct['!'] = 1;
4940 mips_print_operand_punct['*'] = 1;
4941 mips_print_operand_punct['@'] = 1;
4942 mips_print_operand_punct['.'] = 1;
4943 mips_print_operand_punct['('] = 1;
4944 mips_print_operand_punct[')'] = 1;
4945 mips_print_operand_punct['['] = 1;
4946 mips_print_operand_punct[']'] = 1;
4947 mips_print_operand_punct['<'] = 1;
4948 mips_print_operand_punct['>'] = 1;
4949 mips_print_operand_punct['{'] = 1;
4950 mips_print_operand_punct['}'] = 1;
4951 mips_print_operand_punct['^'] = 1;
4952 mips_print_operand_punct['$'] = 1;
4953 mips_print_operand_punct['+'] = 1;
4954 mips_print_operand_punct['~'] = 1;
4956 /* Set up array to map GCC register number to debug register number.
4957 Ignore the special purpose register numbers. */
4959 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4960 mips_dbx_regno[i] = -1;
4962 start = GP_DBX_FIRST - GP_REG_FIRST;
4963 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4964 mips_dbx_regno[i] = i + start;
4966 start = FP_DBX_FIRST - FP_REG_FIRST;
4967 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4968 mips_dbx_regno[i] = i + start;
4970 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4971 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4973 /* Set up array giving whether a given register can hold a given mode. */
4975 for (mode = VOIDmode;
4976 mode != MAX_MACHINE_MODE;
4977 mode = (enum machine_mode) ((int)mode + 1))
4979 register int size = GET_MODE_SIZE (mode);
4980 register enum mode_class class = GET_MODE_CLASS (mode);
4982 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4986 if (mode == CCV2mode)
4989 && (regno - ST_REG_FIRST) % 2 == 0);
4991 else if (mode == CCV4mode)
4994 && (regno - ST_REG_FIRST) % 4 == 0);
4996 else if (mode == CCmode)
4999 temp = (regno == FPSW_REGNUM);
5001 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5002 || FP_REG_P (regno));
5005 else if (GP_REG_P (regno))
5006 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5008 else if (FP_REG_P (regno))
5009 temp = ((regno % FP_INC) == 0)
5010 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5011 || class == MODE_VECTOR_FLOAT)
5012 && size <= UNITS_PER_FPVALUE)
5013 /* Allow integer modes that fit into a single
5014 register. We need to put integers into FPRs
5015 when using instructions like cvt and trunc.
5016 We can't allow sizes smaller than a word,
5017 the FPU has no appropriate load/store
5018 instructions for those. */
5019 || (class == MODE_INT
5020 && size >= MIN_UNITS_PER_WORD
5021 && size <= UNITS_PER_FPREG)
5022 /* Allow TFmode for CCmode reloads. */
5023 || (ISA_HAS_8CC && mode == TFmode));
5025 else if (ACC_REG_P (regno))
5026 temp = (INTEGRAL_MODE_P (mode)
5027 && (size <= UNITS_PER_WORD
5028 || (ACC_HI_REG_P (regno)
5029 && size == 2 * UNITS_PER_WORD)));
5031 else if (ALL_COP_REG_P (regno))
5032 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5036 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5040 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5041 initialized yet, so we can't use that here. */
5042 gpr_mode = TARGET_64BIT ? DImode : SImode;
5044 /* Provide default values for align_* for 64-bit targets. */
5045 if (TARGET_64BIT && !TARGET_MIPS16)
5047 if (align_loops == 0)
5049 if (align_jumps == 0)
5051 if (align_functions == 0)
5052 align_functions = 8;
5055 /* Function to allocate machine-dependent function status. */
5056 init_machine_status = &mips_init_machine_status;
5058 if (ABI_HAS_64BIT_SYMBOLS)
5060 if (TARGET_EXPLICIT_RELOCS)
5062 mips_split_p[SYMBOL_64_HIGH] = true;
5063 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5064 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5066 mips_split_p[SYMBOL_64_MID] = true;
5067 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5068 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5070 mips_split_p[SYMBOL_64_LOW] = true;
5071 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5072 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5074 mips_split_p[SYMBOL_GENERAL] = true;
5075 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5080 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5082 mips_split_p[SYMBOL_GENERAL] = true;
5083 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5084 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5090 /* The high part is provided by a pseudo copy of $gp. */
5091 mips_split_p[SYMBOL_SMALL_DATA] = true;
5092 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5095 if (TARGET_EXPLICIT_RELOCS)
5097 /* Small data constants are kept whole until after reload,
5098 then lowered by mips_rewrite_small_data. */
5099 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5101 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5104 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5105 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5109 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5110 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5115 /* The HIGH and LO_SUM are matched by special .md patterns. */
5116 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5118 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5119 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5120 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5122 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5123 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5124 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5129 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5131 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5132 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5138 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5139 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5140 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5143 /* Thread-local relocation operators. */
5144 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5145 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5146 mips_split_p[SYMBOL_DTPREL] = 1;
5147 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5148 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5149 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5150 mips_split_p[SYMBOL_TPREL] = 1;
5151 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5152 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5154 /* We don't have a thread pointer access instruction on MIPS16, or
5155 appropriate TLS relocations. */
5157 targetm.have_tls = false;
5159 /* Default to working around R4000 errata only if the processor
5160 was selected explicitly. */
5161 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5162 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5163 target_flags |= MASK_FIX_R4000;
5165 /* Default to working around R4400 errata only if the processor
5166 was selected explicitly. */
5167 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5168 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5169 target_flags |= MASK_FIX_R4400;
5172 /* Implement CONDITIONAL_REGISTER_USAGE. */
5175 mips_conditional_register_usage (void)
5181 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5182 fixed_regs[regno] = call_used_regs[regno] = 1;
5184 if (!TARGET_HARD_FLOAT)
5188 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5189 fixed_regs[regno] = call_used_regs[regno] = 1;
5190 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5191 fixed_regs[regno] = call_used_regs[regno] = 1;
5193 else if (! ISA_HAS_8CC)
5197 /* We only have a single condition code register. We
5198 implement this by hiding all the condition code registers,
5199 and generating RTL that refers directly to ST_REG_FIRST. */
5200 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5201 fixed_regs[regno] = call_used_regs[regno] = 1;
5203 /* In mips16 mode, we permit the $t temporary registers to be used
5204 for reload. We prohibit the unused $s registers, since they
5205 are caller saved, and saving them via a mips16 register would
5206 probably waste more time than just reloading the value. */
5209 fixed_regs[18] = call_used_regs[18] = 1;
5210 fixed_regs[19] = call_used_regs[19] = 1;
5211 fixed_regs[20] = call_used_regs[20] = 1;
5212 fixed_regs[21] = call_used_regs[21] = 1;
5213 fixed_regs[22] = call_used_regs[22] = 1;
5214 fixed_regs[23] = call_used_regs[23] = 1;
5215 fixed_regs[26] = call_used_regs[26] = 1;
5216 fixed_regs[27] = call_used_regs[27] = 1;
5217 fixed_regs[30] = call_used_regs[30] = 1;
5219 /* fp20-23 are now caller saved. */
5220 if (mips_abi == ABI_64)
5223 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5224 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5226 /* Odd registers from fp21 to fp31 are now caller saved. */
5227 if (mips_abi == ABI_N32)
5230 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5231 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5235 /* Allocate a chunk of memory for per-function machine-dependent data. */
5236 static struct machine_function *
5237 mips_init_machine_status (void)
5239 return ((struct machine_function *)
5240 ggc_alloc_cleared (sizeof (struct machine_function)));
5243 /* On the mips16, we want to allocate $24 (T_REG) before other
5244 registers for instructions for which it is possible. This helps
5245 avoid shuffling registers around in order to set up for an xor,
5246 encouraging the compiler to use a cmp instead. */
5249 mips_order_regs_for_local_alloc (void)
5253 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5254 reg_alloc_order[i] = i;
5258 /* It really doesn't matter where we put register 0, since it is
5259 a fixed register anyhow. */
5260 reg_alloc_order[0] = 24;
5261 reg_alloc_order[24] = 0;
5266 /* The MIPS debug format wants all automatic variables and arguments
5267 to be in terms of the virtual frame pointer (stack pointer before
5268 any adjustment in the function), while the MIPS 3.0 linker wants
5269 the frame pointer to be the stack pointer after the initial
5270 adjustment. So, we do the adjustment here. The arg pointer (which
5271 is eliminated) points to the virtual frame pointer, while the frame
5272 pointer (which may be eliminated) points to the stack pointer after
5273 the initial adjustments. */
5276 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5278 rtx offset2 = const0_rtx;
5279 rtx reg = eliminate_constant_term (addr, &offset2);
5282 offset = INTVAL (offset2);
5284 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5285 || reg == hard_frame_pointer_rtx)
5287 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5288 ? compute_frame_size (get_frame_size ())
5289 : cfun->machine->frame.total_size;
5291 /* MIPS16 frame is smaller */
5292 if (frame_pointer_needed && TARGET_MIPS16)
5293 frame_size -= cfun->machine->frame.args_size;
5295 offset = offset - frame_size;
5298 /* sdbout_parms does not want this to crash for unrecognized cases. */
5300 else if (reg != arg_pointer_rtx)
5301 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5308 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5310 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5311 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5312 'h' OP is HIGH, prints %hi(X),
5313 'd' output integer constant in decimal,
5314 'z' if the operand is 0, use $0 instead of normal operand.
5315 'D' print second part of double-word register or memory operand.
5316 'L' print low-order register of double-word register operand.
5317 'M' print high-order register of double-word register operand.
5318 'C' print part of opcode for a branch condition.
5319 'F' print part of opcode for a floating-point branch condition.
5320 'N' print part of opcode for a branch condition, inverted.
5321 'W' print part of opcode for a floating-point branch condition, inverted.
5322 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5323 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5324 't' like 'T', but with the EQ/NE cases reversed
5325 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5326 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5327 'R' print the reloc associated with LO_SUM
5328 'q' print DSP accumulator registers
5330 The punctuation characters are:
5332 '(' Turn on .set noreorder
5333 ')' Turn on .set reorder
5334 '[' Turn on .set noat
5336 '<' Turn on .set nomacro
5337 '>' Turn on .set macro
5338 '{' Turn on .set volatile (not GAS)
5339 '}' Turn on .set novolatile (not GAS)
5340 '&' Turn on .set noreorder if filling delay slots
5341 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5342 '!' Turn on .set nomacro if filling delay slots
5343 '#' Print nop if in a .set noreorder section.
5344 '/' Like '#', but does nothing within a delayed branch sequence
5345 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5346 '@' Print the name of the assembler temporary register (at or $1).
5347 '.' Print the name of the register with a hard-wired zero (zero or $0).
5348 '^' Print the name of the pic call-through register (t9 or $25).
5349 '$' Print the name of the stack pointer register (sp or $29).
5350 '+' Print the name of the gp register (usually gp or $28).
5351 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5354 print_operand (FILE *file, rtx op, int letter)
5356 register enum rtx_code code;
5358 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5363 if (mips_branch_likely)
5368 fputs (reg_names [GP_REG_FIRST + 1], file);
5372 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5376 fputs (reg_names [GP_REG_FIRST + 0], file);
5380 fputs (reg_names[STACK_POINTER_REGNUM], file);
5384 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5388 if (final_sequence != 0 && set_noreorder++ == 0)
5389 fputs (".set\tnoreorder\n\t", file);
5393 if (final_sequence != 0)
5395 if (set_noreorder++ == 0)
5396 fputs (".set\tnoreorder\n\t", file);
5398 if (set_nomacro++ == 0)
5399 fputs (".set\tnomacro\n\t", file);
5404 if (final_sequence != 0 && set_nomacro++ == 0)
5405 fputs ("\n\t.set\tnomacro", file);
5409 if (set_noreorder != 0)
5410 fputs ("\n\tnop", file);
5414 /* Print an extra newline so that the delayed insn is separated
5415 from the following ones. This looks neater and is consistent
5416 with non-nop delayed sequences. */
5417 if (set_noreorder != 0 && final_sequence == 0)
5418 fputs ("\n\tnop\n", file);
5422 if (set_noreorder++ == 0)
5423 fputs (".set\tnoreorder\n\t", file);
5427 if (set_noreorder == 0)
5428 error ("internal error: %%) found without a %%( in assembler pattern");
5430 else if (--set_noreorder == 0)
5431 fputs ("\n\t.set\treorder", file);
5436 if (set_noat++ == 0)
5437 fputs (".set\tnoat\n\t", file);
5442 error ("internal error: %%] found without a %%[ in assembler pattern");
5443 else if (--set_noat == 0)
5444 fputs ("\n\t.set\tat", file);
5449 if (set_nomacro++ == 0)
5450 fputs (".set\tnomacro\n\t", file);
5454 if (set_nomacro == 0)
5455 error ("internal error: %%> found without a %%< in assembler pattern");
5456 else if (--set_nomacro == 0)
5457 fputs ("\n\t.set\tmacro", file);
5462 if (set_volatile++ == 0)
5463 fputs ("#.set\tvolatile\n\t", file);
5467 if (set_volatile == 0)
5468 error ("internal error: %%} found without a %%{ in assembler pattern");
5469 else if (--set_volatile == 0)
5470 fputs ("\n\t#.set\tnovolatile", file);
5476 if (align_labels_log > 0)
5477 ASM_OUTPUT_ALIGN (file, align_labels_log);
5482 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5491 error ("PRINT_OPERAND null pointer");
5495 code = GET_CODE (op);
5500 case EQ: fputs ("eq", file); break;
5501 case NE: fputs ("ne", file); break;
5502 case GT: fputs ("gt", file); break;
5503 case GE: fputs ("ge", file); break;
5504 case LT: fputs ("lt", file); break;
5505 case LE: fputs ("le", file); break;
5506 case GTU: fputs ("gtu", file); break;
5507 case GEU: fputs ("geu", file); break;
5508 case LTU: fputs ("ltu", file); break;
5509 case LEU: fputs ("leu", file); break;
5511 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5514 else if (letter == 'N')
5517 case EQ: fputs ("ne", file); break;
5518 case NE: fputs ("eq", file); break;
5519 case GT: fputs ("le", file); break;
5520 case GE: fputs ("lt", file); break;
5521 case LT: fputs ("ge", file); break;
5522 case LE: fputs ("gt", file); break;
5523 case GTU: fputs ("leu", file); break;
5524 case GEU: fputs ("ltu", file); break;
5525 case LTU: fputs ("geu", file); break;
5526 case LEU: fputs ("gtu", file); break;
5528 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5531 else if (letter == 'F')
5534 case EQ: fputs ("c1f", file); break;
5535 case NE: fputs ("c1t", file); break;
5537 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5540 else if (letter == 'W')
5543 case EQ: fputs ("c1t", file); break;
5544 case NE: fputs ("c1f", file); break;
5546 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5549 else if (letter == 'h')
5551 if (GET_CODE (op) == HIGH)
5554 print_operand_reloc (file, op, mips_hi_relocs);
5557 else if (letter == 'R')
5558 print_operand_reloc (file, op, mips_lo_relocs);
5560 else if (letter == 'Y')
5562 if (GET_CODE (op) == CONST_INT
5563 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5564 < ARRAY_SIZE (mips_fp_conditions)))
5565 fputs (mips_fp_conditions[INTVAL (op)], file);
5567 output_operand_lossage ("invalid %%Y value");
5570 else if (letter == 'Z')
5574 print_operand (file, op, 0);
5579 else if (letter == 'q')
5584 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5586 regnum = REGNO (op);
5587 if (MD_REG_P (regnum))
5588 fprintf (file, "$ac0");
5589 else if (DSP_ACC_REG_P (regnum))
5590 fprintf (file, "$ac%c", reg_names[regnum][3]);
5592 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5595 else if (code == REG || code == SUBREG)
5597 register int regnum;
5600 regnum = REGNO (op);
5602 regnum = true_regnum (op);
5604 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5605 || (letter == 'L' && WORDS_BIG_ENDIAN)
5609 fprintf (file, "%s", reg_names[regnum]);
5612 else if (code == MEM)
5615 output_address (plus_constant (XEXP (op, 0), 4));
5617 output_address (XEXP (op, 0));
5620 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5621 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5623 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5624 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5626 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5627 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5629 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5630 fputs (reg_names[GP_REG_FIRST], file);
5632 else if (letter == 'd' || letter == 'x' || letter == 'X')
5633 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5635 else if (letter == 'T' || letter == 't')
5637 int truth = (code == NE) == (letter == 'T');
5638 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5641 else if (CONST_GP_P (op))
5642 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5645 output_addr_const (file, op);
5649 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5650 RELOCS is the array of relocations to use. */
5653 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5655 enum mips_symbol_type symbol_type;
5659 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5660 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5662 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5663 split_const (op, &base, &offset);
5664 if (UNSPEC_ADDRESS_P (base))
5665 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
5667 fputs (relocs[symbol_type], file);
5668 output_addr_const (file, op);
5669 for (p = relocs[symbol_type]; *p != 0; p++)
5674 /* Output address operand X to FILE. */
5677 print_operand_address (FILE *file, rtx x)
5679 struct mips_address_info addr;
5681 if (mips_classify_address (&addr, x, word_mode, true))
5685 print_operand (file, addr.offset, 0);
5686 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5689 case ADDRESS_LO_SUM:
5690 print_operand (file, addr.offset, 'R');
5691 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5694 case ADDRESS_CONST_INT:
5695 output_addr_const (file, x);
5696 fprintf (file, "(%s)", reg_names[0]);
5699 case ADDRESS_SYMBOLIC:
5700 output_addr_const (file, x);
5706 /* When using assembler macros, keep track of all of small-data externs
5707 so that mips_file_end can emit the appropriate declarations for them.
5709 In most cases it would be safe (though pointless) to emit .externs
5710 for other symbols too. One exception is when an object is within
5711 the -G limit but declared by the user to be in a section other
5712 than .sbss or .sdata. */
5715 mips_output_external (FILE *file, tree decl, const char *name)
5717 default_elf_asm_output_external (file, decl, name);
5719 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
5720 set in order to avoid putting out names that are never really
5722 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
5724 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5726 fputs ("\t.extern\t", file);
5727 assemble_name (file, name);
5728 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
5729 int_size_in_bytes (TREE_TYPE (decl)));
5731 else if (TARGET_IRIX
5732 && mips_abi == ABI_32
5733 && TREE_CODE (decl) == FUNCTION_DECL)
5735 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5736 `.global name .text' directive for every used but
5737 undefined function. If we don't, the linker may perform
5738 an optimization (skipping over the insns that set $gp)
5739 when it is unsafe. */
5740 fputs ("\t.globl ", file);
5741 assemble_name (file, name);
5742 fputs (" .text\n", file);
5747 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5748 put out a MIPS ECOFF file and a stab. */
5751 mips_output_filename (FILE *stream, const char *name)
5754 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5756 if (write_symbols == DWARF2_DEBUG)
5758 else if (mips_output_filename_first_time)
5760 mips_output_filename_first_time = 0;
5761 num_source_filenames += 1;
5762 current_function_file = name;
5763 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5764 output_quoted_string (stream, name);
5765 putc ('\n', stream);
5768 /* If we are emitting stabs, let dbxout.c handle this (except for
5769 the mips_output_filename_first_time case). */
5770 else if (write_symbols == DBX_DEBUG)
5773 else if (name != current_function_file
5774 && strcmp (name, current_function_file) != 0)
5776 num_source_filenames += 1;
5777 current_function_file = name;
5778 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5779 output_quoted_string (stream, name);
5780 putc ('\n', stream);
5784 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5785 that should be written before the opening quote, such as "\t.ascii\t"
5786 for real string data or "\t# " for a comment. */
5789 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5794 register const unsigned char *string =
5795 (const unsigned char *)string_param;
5797 fprintf (stream, "%s\"", prefix);
5798 for (i = 0; i < len; i++)
5800 register int c = string[i];
5804 if (c == '\\' || c == '\"')
5806 putc ('\\', stream);
5814 fprintf (stream, "\\%03o", c);
5818 if (cur_pos > 72 && i+1 < len)
5821 fprintf (stream, "\"\n%s\"", prefix);
5824 fprintf (stream, "\"\n");
5827 /* Implement TARGET_ASM_FILE_START. */
5830 mips_file_start (void)
5832 default_file_start ();
5836 /* Generate a special section to describe the ABI switches used to
5837 produce the resultant binary. This used to be done by the assembler
5838 setting bits in the ELF header's flags field, but we have run out of
5839 bits. GDB needs this information in order to be able to correctly
5840 debug these binaries. See the function mips_gdbarch_init() in
5841 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5842 causes unnecessary IRIX 6 ld warnings. */
5843 const char * abi_string = NULL;
5847 case ABI_32: abi_string = "abi32"; break;
5848 case ABI_N32: abi_string = "abiN32"; break;
5849 case ABI_64: abi_string = "abi64"; break;
5850 case ABI_O64: abi_string = "abiO64"; break;
5851 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5855 /* Note - we use fprintf directly rather than calling switch_to_section
5856 because in this way we can avoid creating an allocated section. We
5857 do not want this section to take up any space in the running
5859 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5861 /* There is no ELF header flag to distinguish long32 forms of the
5862 EABI from long64 forms. Emit a special section to help tools
5863 such as GDB. Do the same for o64, which is sometimes used with
5865 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
5866 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5867 TARGET_LONG64 ? 64 : 32);
5869 /* Restore the default section. */
5870 fprintf (asm_out_file, "\t.previous\n");
5873 /* Generate the pseudo ops that System V.4 wants. */
5874 if (TARGET_ABICALLS)
5875 fprintf (asm_out_file, "\t.abicalls\n");
5878 fprintf (asm_out_file, "\t.set\tmips16\n");
5880 if (flag_verbose_asm)
5881 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5883 mips_section_threshold, mips_arch_info->name, mips_isa);
5886 #ifdef BSS_SECTION_ASM_OP
5887 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5888 in the use of sbss. */
5891 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5892 unsigned HOST_WIDE_INT size, int align)
5894 extern tree last_assemble_variable_decl;
5896 if (mips_in_small_data_p (decl))
5897 switch_to_section (get_named_section (NULL, ".sbss", 0));
5899 switch_to_section (bss_section);
5900 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5901 last_assemble_variable_decl = decl;
5902 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5903 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5907 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5908 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5911 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5912 unsigned HOST_WIDE_INT size,
5915 /* If the target wants uninitialized const declarations in
5916 .rdata then don't put them in .comm. */
5917 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5918 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5919 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5921 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5922 targetm.asm_out.globalize_label (stream, name);
5924 switch_to_section (readonly_data_section);
5925 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5926 mips_declare_object (stream, name, "",
5927 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5931 mips_declare_common_object (stream, name, "\n\t.comm\t",
5935 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5936 NAME is the name of the object and ALIGN is the required alignment
5937 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5938 alignment argument. */
5941 mips_declare_common_object (FILE *stream, const char *name,
5942 const char *init_string,
5943 unsigned HOST_WIDE_INT size,
5944 unsigned int align, bool takes_alignment_p)
5946 if (!takes_alignment_p)
5948 size += (align / BITS_PER_UNIT) - 1;
5949 size -= size % (align / BITS_PER_UNIT);
5950 mips_declare_object (stream, name, init_string,
5951 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
5954 mips_declare_object (stream, name, init_string,
5955 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
5956 size, align / BITS_PER_UNIT);
5959 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5960 macros, mark the symbol as written so that mips_file_end won't emit an
5961 .extern for it. STREAM is the output file, NAME is the name of the
5962 symbol, INIT_STRING is the string that should be written before the
5963 symbol and FINAL_STRING is the string that should be written after it.
5964 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5967 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5968 const char *final_string, ...)
5972 fputs (init_string, stream);
5973 assemble_name (stream, name);
5974 va_start (ap, final_string);
5975 vfprintf (stream, final_string, ap);
5978 if (!TARGET_EXPLICIT_RELOCS)
5980 tree name_tree = get_identifier (name);
5981 TREE_ASM_WRITTEN (name_tree) = 1;
5985 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5986 extern int size_directive_output;
5988 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5989 definitions except that it uses mips_declare_object() to emit the label. */
5992 mips_declare_object_name (FILE *stream, const char *name,
5993 tree decl ATTRIBUTE_UNUSED)
5995 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5996 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
5999 size_directive_output = 0;
6000 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6004 size_directive_output = 1;
6005 size = int_size_in_bytes (TREE_TYPE (decl));
6006 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6009 mips_declare_object (stream, name, "", ":\n");
6012 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6015 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6019 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6020 if (!flag_inhibit_size_directive
6021 && DECL_SIZE (decl) != 0
6022 && !at_end && top_level
6023 && DECL_INITIAL (decl) == error_mark_node
6024 && !size_directive_output)
6028 size_directive_output = 1;
6029 size = int_size_in_bytes (TREE_TYPE (decl));
6030 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6035 /* Return true if X is a small data address that can be rewritten
6039 mips_rewrite_small_data_p (rtx x)
6041 enum mips_symbol_type symbol_type;
6043 return (TARGET_EXPLICIT_RELOCS
6044 && mips_symbolic_constant_p (x, &symbol_type)
6045 && symbol_type == SYMBOL_SMALL_DATA);
6049 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6052 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6054 if (GET_CODE (*loc) == LO_SUM)
6057 return mips_rewrite_small_data_p (*loc);
6060 /* Return true if OP refers to small data symbols directly, not through
6064 mips_small_data_pattern_p (rtx op)
6066 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6069 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6072 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6074 if (mips_rewrite_small_data_p (*loc))
6075 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6077 if (GET_CODE (*loc) == LO_SUM)
6083 /* If possible, rewrite OP so that it refers to small data using
6084 explicit relocations. */
6087 mips_rewrite_small_data (rtx op)
6089 op = copy_insn (op);
6090 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6094 /* Return true if the current function has an insn that implicitly
6098 mips_function_has_gp_insn (void)
6100 /* Don't bother rechecking if we found one last time. */
6101 if (!cfun->machine->has_gp_insn_p)
6105 push_topmost_sequence ();
6106 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6108 && GET_CODE (PATTERN (insn)) != USE
6109 && GET_CODE (PATTERN (insn)) != CLOBBER
6110 && (get_attr_got (insn) != GOT_UNSET
6111 || small_data_pattern (PATTERN (insn), VOIDmode)))
6113 pop_topmost_sequence ();
6115 cfun->machine->has_gp_insn_p = (insn != 0);
6117 return cfun->machine->has_gp_insn_p;
6121 /* Return the register that should be used as the global pointer
6122 within this function. Return 0 if the function doesn't need
6123 a global pointer. */
6126 mips_global_pointer (void)
6130 /* $gp is always available in non-abicalls code. */
6131 if (!TARGET_ABICALLS)
6132 return GLOBAL_POINTER_REGNUM;
6134 /* We must always provide $gp when it is used implicitly. */
6135 if (!TARGET_EXPLICIT_RELOCS)
6136 return GLOBAL_POINTER_REGNUM;
6138 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6140 if (current_function_profile)
6141 return GLOBAL_POINTER_REGNUM;
6143 /* If the function has a nonlocal goto, $gp must hold the correct
6144 global pointer for the target function. */
6145 if (current_function_has_nonlocal_goto)
6146 return GLOBAL_POINTER_REGNUM;
6148 /* If the gp is never referenced, there's no need to initialize it.
6149 Note that reload can sometimes introduce constant pool references
6150 into a function that otherwise didn't need them. For example,
6151 suppose we have an instruction like:
6153 (set (reg:DF R1) (float:DF (reg:SI R2)))
6155 If R2 turns out to be constant such as 1, the instruction may have a
6156 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6157 using this constant if R2 doesn't get allocated to a register.
6159 In cases like these, reload will have added the constant to the pool
6160 but no instruction will yet refer to it. */
6161 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6162 && !current_function_uses_const_pool
6163 && !mips_function_has_gp_insn ())
6166 /* We need a global pointer, but perhaps we can use a call-clobbered
6167 register instead of $gp. */
6168 if (TARGET_NEWABI && current_function_is_leaf)
6169 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6170 if (!regs_ever_live[regno]
6171 && call_used_regs[regno]
6172 && !fixed_regs[regno]
6173 && regno != PIC_FUNCTION_ADDR_REGNUM)
6176 return GLOBAL_POINTER_REGNUM;
6180 /* Return true if the current function must save REGNO. */
6183 mips_save_reg_p (unsigned int regno)
6185 /* We only need to save $gp for NewABI PIC. */
6186 if (regno == GLOBAL_POINTER_REGNUM)
6187 return (TARGET_ABICALLS && TARGET_NEWABI
6188 && cfun->machine->global_pointer == regno);
6190 /* Check call-saved registers. */
6191 if (regs_ever_live[regno] && !call_used_regs[regno])
6194 /* We need to save the old frame pointer before setting up a new one. */
6195 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6198 /* We need to save the incoming return address if it is ever clobbered
6199 within the function. */
6200 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6207 return_type = DECL_RESULT (current_function_decl);
6209 /* $18 is a special case in mips16 code. It may be used to call
6210 a function which returns a floating point value, but it is
6211 marked in call_used_regs. */
6212 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6215 /* $31 is also a special case. It will be used to copy a return
6216 value into the floating point registers if the return value is
6218 if (regno == GP_REG_FIRST + 31
6219 && mips16_hard_float
6220 && !aggregate_value_p (return_type, current_function_decl)
6221 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6222 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6230 /* Return the bytes needed to compute the frame pointer from the current
6231 stack pointer. SIZE is the size (in bytes) of the local variables.
6233 MIPS stack frames look like:
6235 Before call After call
6236 +-----------------------+ +-----------------------+
6239 | caller's temps. | | caller's temps. |
6241 +-----------------------+ +-----------------------+
6243 | arguments on stack. | | arguments on stack. |
6245 +-----------------------+ +-----------------------+
6246 | 4 words to save | | 4 words to save |
6247 | arguments passed | | arguments passed |
6248 | in registers, even | | in registers, even |
6249 SP->| if not passed. | VFP->| if not passed. |
6250 +-----------------------+ +-----------------------+
6252 | fp register save |
6254 +-----------------------+
6256 | gp register save |
6258 +-----------------------+
6262 +-----------------------+
6264 | alloca allocations |
6266 +-----------------------+
6268 | GP save for V.4 abi |
6270 +-----------------------+
6272 | arguments on stack |
6274 +-----------------------+
6276 | arguments passed |
6277 | in registers, even |
6278 low SP->| if not passed. |
6279 memory +-----------------------+
6284 compute_frame_size (HOST_WIDE_INT size)
6287 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6288 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6289 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6290 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6291 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6292 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6293 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6294 unsigned int mask; /* mask of saved gp registers */
6295 unsigned int fmask; /* mask of saved fp registers */
6297 cfun->machine->global_pointer = mips_global_pointer ();
6303 var_size = MIPS_STACK_ALIGN (size);
6304 args_size = current_function_outgoing_args_size;
6305 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6307 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6308 functions. If the function has local variables, we're committed
6309 to allocating it anyway. Otherwise reclaim it here. */
6310 if (var_size == 0 && current_function_is_leaf)
6311 cprestore_size = args_size = 0;
6313 /* The MIPS 3.0 linker does not like functions that dynamically
6314 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6315 looks like we are trying to create a second frame pointer to the
6316 function, so allocate some stack space to make it happy. */
6318 if (args_size == 0 && current_function_calls_alloca)
6319 args_size = 4 * UNITS_PER_WORD;
6321 total_size = var_size + args_size + cprestore_size;
6323 /* Calculate space needed for gp registers. */
6324 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6325 if (mips_save_reg_p (regno))
6327 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6328 mask |= 1 << (regno - GP_REG_FIRST);
6331 /* We need to restore these for the handler. */
6332 if (current_function_calls_eh_return)
6337 regno = EH_RETURN_DATA_REGNO (i);
6338 if (regno == INVALID_REGNUM)
6340 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6341 mask |= 1 << (regno - GP_REG_FIRST);
6345 /* This loop must iterate over the same space as its companion in
6346 save_restore_insns. */
6347 for (regno = (FP_REG_LAST - FP_INC + 1);
6348 regno >= FP_REG_FIRST;
6351 if (mips_save_reg_p (regno))
6353 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6354 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6358 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6359 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6361 /* Add in the space required for saving incoming register arguments. */
6362 total_size += current_function_pretend_args_size;
6363 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6365 /* Save other computed information. */
6366 cfun->machine->frame.total_size = total_size;
6367 cfun->machine->frame.var_size = var_size;
6368 cfun->machine->frame.args_size = args_size;
6369 cfun->machine->frame.cprestore_size = cprestore_size;
6370 cfun->machine->frame.gp_reg_size = gp_reg_size;
6371 cfun->machine->frame.fp_reg_size = fp_reg_size;
6372 cfun->machine->frame.mask = mask;
6373 cfun->machine->frame.fmask = fmask;
6374 cfun->machine->frame.initialized = reload_completed;
6375 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6376 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6380 HOST_WIDE_INT offset;
6382 offset = (args_size + cprestore_size + var_size
6383 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6384 cfun->machine->frame.gp_sp_offset = offset;
6385 cfun->machine->frame.gp_save_offset = offset - total_size;
6389 cfun->machine->frame.gp_sp_offset = 0;
6390 cfun->machine->frame.gp_save_offset = 0;
6395 HOST_WIDE_INT offset;
6397 offset = (args_size + cprestore_size + var_size
6398 + gp_reg_rounded + fp_reg_size
6399 - FP_INC * UNITS_PER_FPREG);
6400 cfun->machine->frame.fp_sp_offset = offset;
6401 cfun->machine->frame.fp_save_offset = offset - total_size;
6405 cfun->machine->frame.fp_sp_offset = 0;
6406 cfun->machine->frame.fp_save_offset = 0;
6409 /* Ok, we're done. */
6413 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6414 pointer or argument pointer. TO is either the stack pointer or
6415 hard frame pointer. */
6418 mips_initial_elimination_offset (int from, int to)
6420 HOST_WIDE_INT offset;
6422 compute_frame_size (get_frame_size ());
6424 /* Set OFFSET to the offset from the stack pointer. */
6427 case FRAME_POINTER_REGNUM:
6431 case ARG_POINTER_REGNUM:
6432 offset = (cfun->machine->frame.total_size
6433 - current_function_pretend_args_size);
6440 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6441 offset -= cfun->machine->frame.args_size;
6446 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6447 back to a previous frame. */
6449 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6454 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6457 /* Use FN to save or restore register REGNO. MODE is the register's
6458 mode and OFFSET is the offset of its save slot from the current
6462 mips_save_restore_reg (enum machine_mode mode, int regno,
6463 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6467 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
6469 fn (gen_rtx_REG (mode, regno), mem);
6473 /* Call FN for each register that is saved by the current function.
6474 SP_OFFSET is the offset of the current stack pointer from the start
6478 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6480 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6482 enum machine_mode fpr_mode;
6483 HOST_WIDE_INT offset;
6486 /* Save registers starting from high to low. The debuggers prefer at least
6487 the return register be stored at func+4, and also it allows us not to
6488 need a nop in the epilogue if at least one register is reloaded in
6489 addition to return address. */
6490 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6491 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6492 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6494 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6495 offset -= GET_MODE_SIZE (gpr_mode);
6498 /* This loop must iterate over the same space as its companion in
6499 compute_frame_size. */
6500 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6501 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6502 for (regno = (FP_REG_LAST - FP_INC + 1);
6503 regno >= FP_REG_FIRST;
6505 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6507 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6508 offset -= GET_MODE_SIZE (fpr_mode);
6513 /* If we're generating n32 or n64 abicalls, and the current function
6514 does not use $28 as its global pointer, emit a cplocal directive.
6515 Use pic_offset_table_rtx as the argument to the directive. */
6518 mips_output_cplocal (void)
6520 if (!TARGET_EXPLICIT_RELOCS
6521 && cfun->machine->global_pointer > 0
6522 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6523 output_asm_insn (".cplocal %+", 0);
6526 /* Return the style of GP load sequence that is being used for the
6527 current function. */
6529 enum mips_loadgp_style
6530 mips_current_loadgp_style (void)
6532 if (!TARGET_ABICALLS || cfun->machine->global_pointer == 0)
6535 if (TARGET_ABSOLUTE_ABICALLS)
6536 return LOADGP_ABSOLUTE;
6538 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6541 /* The __gnu_local_gp symbol. */
6543 static GTY(()) rtx mips_gnu_local_gp;
6545 /* If we're generating n32 or n64 abicalls, emit instructions
6546 to set up the global pointer. */
6549 mips_emit_loadgp (void)
6551 rtx addr, offset, incoming_address;
6553 switch (mips_current_loadgp_style ())
6555 case LOADGP_ABSOLUTE:
6556 if (mips_gnu_local_gp == NULL)
6558 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
6559 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
6561 emit_insn (gen_loadgp_noshared (mips_gnu_local_gp));
6565 addr = XEXP (DECL_RTL (current_function_decl), 0);
6566 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6567 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6568 emit_insn (gen_loadgp (offset, incoming_address));
6569 if (!TARGET_EXPLICIT_RELOCS)
6570 emit_insn (gen_loadgp_blockage ());
6578 /* Set up the stack and frame (if desired) for the function. */
6581 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6584 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6586 #ifdef SDB_DEBUGGING_INFO
6587 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6588 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6591 /* In mips16 mode, we may need to generate a 32 bit to handle
6592 floating point arguments. The linker will arrange for any 32-bit
6593 functions to call this stub, which will then jump to the 16-bit
6595 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6596 && current_function_args_info.fp_code != 0)
6597 build_mips16_function_stub (file);
6599 if (!FUNCTION_NAME_ALREADY_DECLARED)
6601 /* Get the function name the same way that toplev.c does before calling
6602 assemble_start_function. This is needed so that the name used here
6603 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6604 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6606 if (!flag_inhibit_size_directive)
6608 fputs ("\t.ent\t", file);
6609 assemble_name (file, fnname);
6613 assemble_name (file, fnname);
6614 fputs (":\n", file);
6617 /* Stop mips_file_end from treating this function as external. */
6618 if (TARGET_IRIX && mips_abi == ABI_32)
6619 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6621 if (!flag_inhibit_size_directive)
6623 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6625 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6626 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6627 ", args= " HOST_WIDE_INT_PRINT_DEC
6628 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6629 (reg_names[(frame_pointer_needed)
6630 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6631 ((frame_pointer_needed && TARGET_MIPS16)
6632 ? tsize - cfun->machine->frame.args_size
6634 reg_names[GP_REG_FIRST + 31],
6635 cfun->machine->frame.var_size,
6636 cfun->machine->frame.num_gp,
6637 cfun->machine->frame.num_fp,
6638 cfun->machine->frame.args_size,
6639 cfun->machine->frame.cprestore_size);
6641 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6642 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6643 cfun->machine->frame.mask,
6644 cfun->machine->frame.gp_save_offset);
6645 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6646 cfun->machine->frame.fmask,
6647 cfun->machine->frame.fp_save_offset);
6650 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6651 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6654 if (mips_current_loadgp_style () == LOADGP_OLDABI)
6656 /* Handle the initialization of $gp for SVR4 PIC. */
6657 if (!cfun->machine->all_noreorder_p)
6658 output_asm_insn ("%(.cpload\t%^%)", 0);
6660 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6662 else if (cfun->machine->all_noreorder_p)
6663 output_asm_insn ("%(%<", 0);
6665 /* Tell the assembler which register we're using as the global
6666 pointer. This is needed for thunks, since they can use either
6667 explicit relocs or assembler macros. */
6668 mips_output_cplocal ();
6671 /* Make the last instruction frame related and note that it performs
6672 the operation described by FRAME_PATTERN. */
6675 mips_set_frame_expr (rtx frame_pattern)
6679 insn = get_last_insn ();
6680 RTX_FRAME_RELATED_P (insn) = 1;
6681 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6687 /* Return a frame-related rtx that stores REG at MEM.
6688 REG must be a single register. */
6691 mips_frame_set (rtx mem, rtx reg)
6695 /* If we're saving the return address register and the dwarf return
6696 address column differs from the hard register number, adjust the
6697 note reg to refer to the former. */
6698 if (REGNO (reg) == GP_REG_FIRST + 31
6699 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6700 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6702 set = gen_rtx_SET (VOIDmode, mem, reg);
6703 RTX_FRAME_RELATED_P (set) = 1;
6709 /* Save register REG to MEM. Make the instruction frame-related. */
6712 mips_save_reg (rtx reg, rtx mem)
6714 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6718 if (mips_split_64bit_move_p (mem, reg))
6719 mips_split_64bit_move (mem, reg);
6721 emit_move_insn (mem, reg);
6723 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6724 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6725 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6730 && REGNO (reg) != GP_REG_FIRST + 31
6731 && !M16_REG_P (REGNO (reg)))
6733 /* Save a non-mips16 register by moving it through a temporary.
6734 We don't need to do this for $31 since there's a special
6735 instruction for it. */
6736 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6737 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6740 emit_move_insn (mem, reg);
6742 mips_set_frame_expr (mips_frame_set (mem, reg));
6747 /* Expand the prologue into a bunch of separate insns. */
6750 mips_expand_prologue (void)
6754 if (cfun->machine->global_pointer > 0)
6755 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6757 size = compute_frame_size (get_frame_size ());
6759 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6760 bytes beforehand; this is enough to cover the register save area
6761 without going out of range. */
6762 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6764 HOST_WIDE_INT step1;
6766 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6767 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6769 GEN_INT (-step1)))) = 1;
6771 mips_for_each_saved_reg (size, mips_save_reg);
6774 /* Allocate the rest of the frame. */
6777 if (SMALL_OPERAND (-size))
6778 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6780 GEN_INT (-size)))) = 1;
6783 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6786 /* There are no instructions to add or subtract registers
6787 from the stack pointer, so use the frame pointer as a
6788 temporary. We should always be using a frame pointer
6789 in this case anyway. */
6790 gcc_assert (frame_pointer_needed);
6791 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6792 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6793 hard_frame_pointer_rtx,
6794 MIPS_PROLOGUE_TEMP (Pmode)));
6795 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6798 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6800 MIPS_PROLOGUE_TEMP (Pmode)));
6802 /* Describe the combined effect of the previous instructions. */
6804 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6805 plus_constant (stack_pointer_rtx, -size)));
6809 /* Set up the frame pointer, if we're using one. In mips16 code,
6810 we point the frame pointer ahead of the outgoing argument area.
6811 This should allow more variables & incoming arguments to be
6812 accessed with unextended instructions. */
6813 if (frame_pointer_needed)
6815 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6817 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6818 if (SMALL_OPERAND (cfun->machine->frame.args_size))
6820 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6825 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
6826 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6827 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6828 hard_frame_pointer_rtx,
6829 MIPS_PROLOGUE_TEMP (Pmode)));
6831 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
6832 plus_constant (stack_pointer_rtx,
6833 cfun->machine->frame.args_size)));
6837 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6838 stack_pointer_rtx)) = 1;
6841 mips_emit_loadgp ();
6843 /* If generating o32/o64 abicalls, save $gp on the stack. */
6844 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6845 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6847 /* If we are profiling, make sure no instructions are scheduled before
6848 the call to mcount. */
6850 if (current_function_profile)
6851 emit_insn (gen_blockage ());
6854 /* Do any necessary cleanup after a function to restore stack, frame,
6857 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6860 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6861 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6863 /* Reinstate the normal $gp. */
6864 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6865 mips_output_cplocal ();
6867 if (cfun->machine->all_noreorder_p)
6869 /* Avoid using %>%) since it adds excess whitespace. */
6870 output_asm_insn (".set\tmacro", 0);
6871 output_asm_insn (".set\treorder", 0);
6872 set_noreorder = set_nomacro = 0;
6875 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6879 /* Get the function name the same way that toplev.c does before calling
6880 assemble_start_function. This is needed so that the name used here
6881 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6882 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6883 fputs ("\t.end\t", file);
6884 assemble_name (file, fnname);
6889 /* Emit instructions to restore register REG from slot MEM. */
6892 mips_restore_reg (rtx reg, rtx mem)
6894 /* There's no mips16 instruction to load $31 directly. Load into
6895 $7 instead and adjust the return insn appropriately. */
6896 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6897 reg = gen_rtx_REG (GET_MODE (reg), 7);
6899 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6901 /* Can't restore directly; move through a temporary. */
6902 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6903 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6906 emit_move_insn (reg, mem);
6910 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6911 if this epilogue precedes a sibling call, false if it is for a normal
6912 "epilogue" pattern. */
6915 mips_expand_epilogue (int sibcall_p)
6917 HOST_WIDE_INT step1, step2;
6920 if (!sibcall_p && mips_can_use_return_insn ())
6922 emit_jump_insn (gen_return ());
6926 /* Split the frame into two. STEP1 is the amount of stack we should
6927 deallocate before restoring the registers. STEP2 is the amount we
6928 should deallocate afterwards.
6930 Start off by assuming that no registers need to be restored. */
6931 step1 = cfun->machine->frame.total_size;
6934 /* Work out which register holds the frame address. Account for the
6935 frame pointer offset used by mips16 code. */
6936 if (!frame_pointer_needed)
6937 base = stack_pointer_rtx;
6940 base = hard_frame_pointer_rtx;
6942 step1 -= cfun->machine->frame.args_size;
6945 /* If we need to restore registers, deallocate as much stack as
6946 possible in the second step without going out of range. */
6947 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6949 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6953 /* Set TARGET to BASE + STEP1. */
6959 /* Get an rtx for STEP1 that we can add to BASE. */
6960 adjust = GEN_INT (step1);
6961 if (!SMALL_OPERAND (step1))
6963 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6964 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6967 /* Normal mode code can copy the result straight into $sp. */
6969 target = stack_pointer_rtx;
6971 emit_insn (gen_add3_insn (target, base, adjust));
6974 /* Copy TARGET into the stack pointer. */
6975 if (target != stack_pointer_rtx)
6976 emit_move_insn (stack_pointer_rtx, target);
6978 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6979 implicitly used by all SYMBOL_REFs. We must emit a blockage
6980 insn before restoring it. */
6981 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6982 emit_insn (gen_blockage ());
6984 /* Restore the registers. */
6985 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
6988 /* Deallocate the final bit of the frame. */
6990 emit_insn (gen_add3_insn (stack_pointer_rtx,
6994 /* Add in the __builtin_eh_return stack adjustment. We need to
6995 use a temporary in mips16 code. */
6996 if (current_function_calls_eh_return)
7000 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7001 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7002 MIPS_EPILOGUE_TEMP (Pmode),
7003 EH_RETURN_STACKADJ_RTX));
7004 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7007 emit_insn (gen_add3_insn (stack_pointer_rtx,
7009 EH_RETURN_STACKADJ_RTX));
7014 /* The mips16 loads the return address into $7, not $31. */
7015 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7016 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7017 GP_REG_FIRST + 7)));
7019 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7020 GP_REG_FIRST + 31)));
7024 /* Return nonzero if this function is known to have a null epilogue.
7025 This allows the optimizer to omit jumps to jumps if no stack
7029 mips_can_use_return_insn (void)
7033 if (! reload_completed)
7036 if (regs_ever_live[31] || current_function_profile)
7039 return_type = DECL_RESULT (current_function_decl);
7041 /* In mips16 mode, a function which returns a floating point value
7042 needs to arrange to copy the return value into the floating point
7045 && mips16_hard_float
7046 && ! aggregate_value_p (return_type, current_function_decl)
7047 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7048 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7051 if (cfun->machine->frame.initialized)
7052 return cfun->machine->frame.total_size == 0;
7054 return compute_frame_size (get_frame_size ()) == 0;
7057 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7058 in order to avoid duplicating too much logic from elsewhere. */
7061 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7062 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7065 rtx this, temp1, temp2, insn, fnaddr;
7067 /* Pretend to be a post-reload pass while generating rtl. */
7069 reload_completed = 1;
7070 reset_block_changes ();
7072 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7073 for TARGET_NEWABI since the latter is a call-saved register. */
7074 if (TARGET_ABICALLS)
7075 cfun->machine->global_pointer
7076 = REGNO (pic_offset_table_rtx)
7077 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7079 /* Set up the global pointer for n32 or n64 abicalls. */
7080 mips_emit_loadgp ();
7082 /* We need two temporary registers in some cases. */
7083 temp1 = gen_rtx_REG (Pmode, 2);
7084 temp2 = gen_rtx_REG (Pmode, 3);
7086 /* Find out which register contains the "this" pointer. */
7087 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7088 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7090 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7092 /* Add DELTA to THIS. */
7095 rtx offset = GEN_INT (delta);
7096 if (!SMALL_OPERAND (delta))
7098 emit_move_insn (temp1, offset);
7101 emit_insn (gen_add3_insn (this, this, offset));
7104 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7105 if (vcall_offset != 0)
7109 /* Set TEMP1 to *THIS. */
7110 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7112 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7113 addr = mips_add_offset (temp2, temp1, vcall_offset);
7115 /* Load the offset and add it to THIS. */
7116 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7117 emit_insn (gen_add3_insn (this, this, temp1));
7120 /* Jump to the target function. Use a sibcall if direct jumps are
7121 allowed, otherwise load the address into a register first. */
7122 fnaddr = XEXP (DECL_RTL (function), 0);
7123 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7125 /* This is messy. gas treats "la $25,foo" as part of a call
7126 sequence and may allow a global "foo" to be lazily bound.
7127 The general move patterns therefore reject this combination.
7129 In this context, lazy binding would actually be OK for o32 and o64,
7130 but it's still wrong for n32 and n64; see mips_load_call_address.
7131 We must therefore load the address via a temporary register if
7132 mips_dangerous_for_la25_p.
7134 If we jump to the temporary register rather than $25, the assembler
7135 can use the move insn to fill the jump's delay slot. */
7136 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7137 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7138 mips_load_call_address (temp1, fnaddr, true);
7140 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7141 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7142 emit_jump_insn (gen_indirect_jump (temp1));
7146 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7147 SIBLING_CALL_P (insn) = 1;
7150 /* Run just enough of rest_of_compilation. This sequence was
7151 "borrowed" from alpha.c. */
7152 insn = get_insns ();
7153 insn_locators_initialize ();
7154 split_all_insns_noflow ();
7156 mips16_lay_out_constants ();
7157 shorten_branches (insn);
7158 final_start_function (insn, file, 1);
7159 final (insn, file, 1);
7160 final_end_function ();
7162 /* Clean up the vars set above. Note that final_end_function resets
7163 the global pointer for us. */
7164 reload_completed = 0;
7168 /* Returns nonzero if X contains a SYMBOL_REF. */
7171 symbolic_expression_p (rtx x)
7173 if (GET_CODE (x) == SYMBOL_REF)
7176 if (GET_CODE (x) == CONST)
7177 return symbolic_expression_p (XEXP (x, 0));
7180 return symbolic_expression_p (XEXP (x, 0));
7182 if (ARITHMETIC_P (x))
7183 return (symbolic_expression_p (XEXP (x, 0))
7184 || symbolic_expression_p (XEXP (x, 1)));
7189 /* Choose the section to use for the constant rtx expression X that has
7193 mips_select_rtx_section (enum machine_mode mode, rtx x,
7194 unsigned HOST_WIDE_INT align)
7198 /* In mips16 mode, the constant table always goes in the same section
7199 as the function, so that constants can be loaded using PC relative
7201 return function_section (current_function_decl);
7203 else if (TARGET_EMBEDDED_DATA)
7205 /* For embedded applications, always put constants in read-only data,
7206 in order to reduce RAM usage. */
7207 return mergeable_constant_section (mode, align, 0);
7211 /* For hosted applications, always put constants in small data if
7212 possible, as this gives the best performance. */
7213 /* ??? Consider using mergeable small data sections. */
7215 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7216 && mips_section_threshold > 0)
7217 return get_named_section (NULL, ".sdata", 0);
7218 else if (flag_pic && symbolic_expression_p (x))
7219 return get_named_section (NULL, ".data.rel.ro", 3);
7221 return mergeable_constant_section (mode, align, 0);
7225 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7227 The complication here is that, with the combination TARGET_ABICALLS
7228 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7229 therefore not be included in the read-only part of a DSO. Handle such
7230 cases by selecting a normal data section instead of a read-only one.
7231 The logic apes that in default_function_rodata_section. */
7234 mips_function_rodata_section (tree decl)
7236 if (!TARGET_ABICALLS || TARGET_GPWORD)
7237 return default_function_rodata_section (decl);
7239 if (decl && DECL_SECTION_NAME (decl))
7241 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7242 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7244 char *rname = ASTRDUP (name);
7246 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7248 else if (flag_function_sections && flag_data_sections
7249 && strncmp (name, ".text.", 6) == 0)
7251 char *rname = ASTRDUP (name);
7252 memcpy (rname + 1, "data", 4);
7253 return get_section (rname, SECTION_WRITE, decl);
7256 return data_section;
7259 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
7260 locally-defined objects go in a small data section. It also controls
7261 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
7262 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
7265 mips_in_small_data_p (tree decl)
7269 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7272 /* We don't yet generate small-data references for -mabicalls. See related
7273 -G handling in override_options. */
7274 if (TARGET_ABICALLS)
7277 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7281 /* Reject anything that isn't in a known small-data section. */
7282 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7283 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7286 /* If a symbol is defined externally, the assembler will use the
7287 usual -G rules when deciding how to implement macros. */
7288 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7291 else if (TARGET_EMBEDDED_DATA)
7293 /* Don't put constants into the small data section: we want them
7294 to be in ROM rather than RAM. */
7295 if (TREE_CODE (decl) != VAR_DECL)
7298 if (TREE_READONLY (decl)
7299 && !TREE_SIDE_EFFECTS (decl)
7300 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7304 size = int_size_in_bytes (TREE_TYPE (decl));
7305 return (size > 0 && size <= mips_section_threshold);
7308 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7309 anchors for small data: the GP register acts as an anchor in that
7310 case. We also don't want to use them for PC-relative accesses,
7311 where the PC acts as an anchor. */
7314 mips_use_anchors_for_symbol_p (rtx symbol)
7316 switch (mips_classify_symbol (symbol))
7318 case SYMBOL_CONSTANT_POOL:
7319 case SYMBOL_SMALL_DATA:
7327 /* See whether VALTYPE is a record whose fields should be returned in
7328 floating-point registers. If so, return the number of fields and
7329 list them in FIELDS (which should have two elements). Return 0
7332 For n32 & n64, a structure with one or two fields is returned in
7333 floating-point registers as long as every field has a floating-point
7337 mips_fpr_return_fields (tree valtype, tree *fields)
7345 if (TREE_CODE (valtype) != RECORD_TYPE)
7349 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7351 if (TREE_CODE (field) != FIELD_DECL)
7354 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7360 fields[i++] = field;
7366 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7367 a value in the most significant part of $2/$3 if:
7369 - the target is big-endian;
7371 - the value has a structure or union type (we generalize this to
7372 cover aggregates from other languages too); and
7374 - the structure is not returned in floating-point registers. */
7377 mips_return_in_msb (tree valtype)
7381 return (TARGET_NEWABI
7382 && TARGET_BIG_ENDIAN
7383 && AGGREGATE_TYPE_P (valtype)
7384 && mips_fpr_return_fields (valtype, fields) == 0);
7388 /* Return a composite value in a pair of floating-point registers.
7389 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7390 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7393 For n32 & n64, $f0 always holds the first value and $f2 the second.
7394 Otherwise the values are packed together as closely as possible. */
7397 mips_return_fpr_pair (enum machine_mode mode,
7398 enum machine_mode mode1, HOST_WIDE_INT offset1,
7399 enum machine_mode mode2, HOST_WIDE_INT offset2)
7403 inc = (TARGET_NEWABI ? 2 : FP_INC);
7404 return gen_rtx_PARALLEL
7407 gen_rtx_EXPR_LIST (VOIDmode,
7408 gen_rtx_REG (mode1, FP_RETURN),
7410 gen_rtx_EXPR_LIST (VOIDmode,
7411 gen_rtx_REG (mode2, FP_RETURN + inc),
7412 GEN_INT (offset2))));
7417 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7418 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7419 VALTYPE is null and MODE is the mode of the return value. */
7422 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7423 enum machine_mode mode)
7430 mode = TYPE_MODE (valtype);
7431 unsignedp = TYPE_UNSIGNED (valtype);
7433 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7434 true, we must promote the mode just as PROMOTE_MODE does. */
7435 mode = promote_mode (valtype, mode, &unsignedp, 1);
7437 /* Handle structures whose fields are returned in $f0/$f2. */
7438 switch (mips_fpr_return_fields (valtype, fields))
7441 return gen_rtx_REG (mode, FP_RETURN);
7444 return mips_return_fpr_pair (mode,
7445 TYPE_MODE (TREE_TYPE (fields[0])),
7446 int_byte_position (fields[0]),
7447 TYPE_MODE (TREE_TYPE (fields[1])),
7448 int_byte_position (fields[1]));
7451 /* If a value is passed in the most significant part of a register, see
7452 whether we have to round the mode up to a whole number of words. */
7453 if (mips_return_in_msb (valtype))
7455 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7456 if (size % UNITS_PER_WORD != 0)
7458 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7459 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7463 /* For EABI, the class of return register depends entirely on MODE.
7464 For example, "struct { some_type x; }" and "union { some_type x; }"
7465 are returned in the same way as a bare "some_type" would be.
7466 Other ABIs only use FPRs for scalar, complex or vector types. */
7467 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7468 return gen_rtx_REG (mode, GP_RETURN);
7471 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7472 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7473 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7474 return gen_rtx_REG (mode, FP_RETURN);
7476 /* Handle long doubles for n32 & n64. */
7478 return mips_return_fpr_pair (mode,
7480 DImode, GET_MODE_SIZE (mode) / 2);
7482 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7483 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7484 return mips_return_fpr_pair (mode,
7485 GET_MODE_INNER (mode), 0,
7486 GET_MODE_INNER (mode),
7487 GET_MODE_SIZE (mode) / 2);
7489 return gen_rtx_REG (mode, GP_RETURN);
7492 /* Return nonzero when an argument must be passed by reference. */
7495 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7496 enum machine_mode mode, tree type,
7497 bool named ATTRIBUTE_UNUSED)
7499 if (mips_abi == ABI_EABI)
7503 /* ??? How should SCmode be handled? */
7504 if (mode == DImode || mode == DFmode)
7507 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
7508 return size == -1 || size > UNITS_PER_WORD;
7512 /* If we have a variable-sized parameter, we have no choice. */
7513 return targetm.calls.must_pass_in_stack (mode, type);
7518 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7519 enum machine_mode mode ATTRIBUTE_UNUSED,
7520 tree type ATTRIBUTE_UNUSED, bool named)
7522 return mips_abi == ABI_EABI && named;
7525 /* Return true if registers of class CLASS cannot change from mode FROM
7529 mips_cannot_change_mode_class (enum machine_mode from,
7530 enum machine_mode to, enum reg_class class)
7532 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7533 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7535 if (TARGET_BIG_ENDIAN)
7537 /* When a multi-word value is stored in paired floating-point
7538 registers, the first register always holds the low word.
7539 We therefore can't allow FPRs to change between single-word
7540 and multi-word modes. */
7541 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7546 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7547 in LO and HI, the high word always comes first. We therefore
7548 can't allow values stored in HI to change between single-word
7549 and multi-word modes.
7550 This rule applies to both the original HI/LO pair and the new
7551 DSP accumulators. */
7552 if (reg_classes_intersect_p (ACC_REGS, class))
7557 /* gcc assumes that each word of a multiword register can be accessed
7558 individually using SUBREGs. This is not true for floating-point
7559 registers if they are bigger than a word. */
7560 if (UNITS_PER_FPREG > UNITS_PER_WORD
7561 && GET_MODE_SIZE (from) > UNITS_PER_WORD
7562 && GET_MODE_SIZE (to) < UNITS_PER_FPREG
7563 && reg_classes_intersect_p (FP_REGS, class))
7566 /* Loading a 32-bit value into a 64-bit floating-point register
7567 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7568 We can't allow 64-bit float registers to change from SImode to
7573 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7574 && reg_classes_intersect_p (FP_REGS, class))
7580 /* Return true if X should not be moved directly into register $25.
7581 We need this because many versions of GAS will treat "la $25,foo" as
7582 part of a call sequence and so allow a global "foo" to be lazily bound. */
7585 mips_dangerous_for_la25_p (rtx x)
7589 if (TARGET_EXPLICIT_RELOCS)
7592 split_const (x, &x, &offset);
7593 return global_got_operand (x, VOIDmode);
7596 /* Implement PREFERRED_RELOAD_CLASS. */
7599 mips_preferred_reload_class (rtx x, enum reg_class class)
7601 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7604 if (TARGET_HARD_FLOAT
7605 && FLOAT_MODE_P (GET_MODE (x))
7606 && reg_class_subset_p (FP_REGS, class))
7609 if (reg_class_subset_p (GR_REGS, class))
7612 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7618 /* This function returns the register class required for a secondary
7619 register when copying between one of the registers in CLASS, and X,
7620 using MODE. If IN_P is nonzero, the copy is going from X to the
7621 register, otherwise the register is the source. A return value of
7622 NO_REGS means that no secondary register is required. */
7625 mips_secondary_reload_class (enum reg_class class,
7626 enum machine_mode mode, rtx x, int in_p)
7628 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7632 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7633 regno = true_regnum (x);
7635 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7637 if (mips_dangerous_for_la25_p (x))
7640 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7644 /* Copying from HI or LO to anywhere other than a general register
7645 requires a general register.
7646 This rule applies to both the original HI/LO pair and the new
7647 DSP accumulators. */
7648 if (reg_class_subset_p (class, ACC_REGS))
7650 if (TARGET_MIPS16 && in_p)
7652 /* We can't really copy to HI or LO at all in mips16 mode. */
7655 return gp_reg_p ? NO_REGS : gr_regs;
7657 if (ACC_REG_P (regno))
7659 if (TARGET_MIPS16 && ! in_p)
7661 /* We can't really copy to HI or LO at all in mips16 mode. */
7664 return class == gr_regs ? NO_REGS : gr_regs;
7667 /* We can only copy a value to a condition code register from a
7668 floating point register, and even then we require a scratch
7669 floating point register. We can only copy a value out of a
7670 condition code register into a general register. */
7671 if (class == ST_REGS)
7675 return gp_reg_p ? NO_REGS : gr_regs;
7677 if (ST_REG_P (regno))
7681 return class == gr_regs ? NO_REGS : gr_regs;
7684 if (class == FP_REGS)
7688 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7691 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7693 /* We can use the l.s and l.d macros to load floating-point
7694 constants. ??? For l.s, we could probably get better
7695 code by returning GR_REGS here. */
7698 else if (gp_reg_p || x == CONST0_RTX (mode))
7700 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7703 else if (FP_REG_P (regno))
7705 /* In this case we can use mov.s or mov.d. */
7710 /* Otherwise, we need to reload through an integer register. */
7715 /* In mips16 mode, going between memory and anything but M16_REGS
7716 requires an M16_REG. */
7719 if (class != M16_REGS && class != M16_NA_REGS)
7727 if (class == M16_REGS || class == M16_NA_REGS)
7736 /* Implement CLASS_MAX_NREGS.
7738 - UNITS_PER_FPREG controls the number of registers needed by FP_REGS.
7740 - ST_REGS are always hold CCmode values, and CCmode values are
7741 considered to be 4 bytes wide.
7743 All other register classes are covered by UNITS_PER_WORD. Note that
7744 this is true even for unions of integer and float registers when the
7745 latter are smaller than the former. The only supported combination
7746 in which case this occurs is -mgp64 -msingle-float, which has 64-bit
7747 words but 32-bit float registers. A word-based calculation is correct
7748 in that case since -msingle-float disallows multi-FPR values. */
7751 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7752 enum machine_mode mode)
7754 if (class == ST_REGS)
7755 return (GET_MODE_SIZE (mode) + 3) / 4;
7756 else if (class == FP_REGS)
7757 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
7759 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7763 mips_valid_pointer_mode (enum machine_mode mode)
7765 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7768 /* Target hook for vector_mode_supported_p. */
7771 mips_vector_mode_supported_p (enum machine_mode mode)
7776 return TARGET_PAIRED_SINGLE_FLOAT;
7787 /* If we can access small data directly (using gp-relative relocation
7788 operators) return the small data pointer, otherwise return null.
7790 For each mips16 function which refers to GP relative symbols, we
7791 use a pseudo register, initialized at the start of the function, to
7792 hold the $gp value. */
7795 mips16_gp_pseudo_reg (void)
7797 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7802 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7804 /* We want to initialize this to a value which gcc will believe
7807 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7808 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7809 gen_rtx_CONST (Pmode, unspec));
7810 insn = get_insns ();
7813 push_topmost_sequence ();
7814 /* We need to emit the initialization after the FUNCTION_BEG
7815 note, so that it will be integrated. */
7816 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7818 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7820 if (scan == NULL_RTX)
7821 scan = get_insns ();
7822 insn = emit_insn_after (insn, scan);
7823 pop_topmost_sequence ();
7826 return cfun->machine->mips16_gp_pseudo_rtx;
7829 /* Write out code to move floating point arguments in or out of
7830 general registers. Output the instructions to FILE. FP_CODE is
7831 the code describing which arguments are present (see the comment at
7832 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7833 we are copying from the floating point registers. */
7836 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7842 /* This code only works for the original 32-bit ABI and the O64 ABI. */
7843 gcc_assert (TARGET_OLDABI);
7849 gparg = GP_ARG_FIRST;
7850 fparg = FP_ARG_FIRST;
7851 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7855 if ((fparg & 1) != 0)
7857 fprintf (file, "\t%s\t%s,%s\n", s,
7858 reg_names[gparg], reg_names[fparg]);
7860 else if ((f & 3) == 2)
7863 fprintf (file, "\td%s\t%s,%s\n", s,
7864 reg_names[gparg], reg_names[fparg]);
7867 if ((fparg & 1) != 0)
7869 if (TARGET_BIG_ENDIAN)
7870 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7871 reg_names[gparg], reg_names[fparg + 1], s,
7872 reg_names[gparg + 1], reg_names[fparg]);
7874 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7875 reg_names[gparg], reg_names[fparg], s,
7876 reg_names[gparg + 1], reg_names[fparg + 1]);
7889 /* Build a mips16 function stub. This is used for functions which
7890 take arguments in the floating point registers. It is 32-bit code
7891 that moves the floating point args into the general registers, and
7892 then jumps to the 16-bit code. */
7895 build_mips16_function_stub (FILE *file)
7898 char *secname, *stubname;
7899 tree stubid, stubdecl;
7903 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7904 secname = (char *) alloca (strlen (fnname) + 20);
7905 sprintf (secname, ".mips16.fn.%s", fnname);
7906 stubname = (char *) alloca (strlen (fnname) + 20);
7907 sprintf (stubname, "__fn_stub_%s", fnname);
7908 stubid = get_identifier (stubname);
7909 stubdecl = build_decl (FUNCTION_DECL, stubid,
7910 build_function_type (void_type_node, NULL_TREE));
7911 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7913 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7915 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7917 fprintf (file, "%s%s",
7918 need_comma ? ", " : "",
7919 (f & 3) == 1 ? "float" : "double");
7922 fprintf (file, ")\n");
7924 fprintf (file, "\t.set\tnomips16\n");
7925 switch_to_section (function_section (stubdecl));
7926 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7928 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7929 within a .ent, and we cannot emit another .ent. */
7930 if (!FUNCTION_NAME_ALREADY_DECLARED)
7932 fputs ("\t.ent\t", file);
7933 assemble_name (file, stubname);
7937 assemble_name (file, stubname);
7938 fputs (":\n", file);
7940 /* We don't want the assembler to insert any nops here. */
7941 fprintf (file, "\t.set\tnoreorder\n");
7943 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7945 fprintf (asm_out_file, "\t.set\tnoat\n");
7946 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7947 assemble_name (file, fnname);
7948 fprintf (file, "\n");
7949 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7950 fprintf (asm_out_file, "\t.set\tat\n");
7952 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7953 with one of the mfc1 instructions, because the result is not
7954 available for one instruction, so if the very first instruction
7955 in the function refers to the register, it will see the wrong
7957 fprintf (file, "\tnop\n");
7959 fprintf (file, "\t.set\treorder\n");
7961 if (!FUNCTION_NAME_ALREADY_DECLARED)
7963 fputs ("\t.end\t", file);
7964 assemble_name (file, stubname);
7968 fprintf (file, "\t.set\tmips16\n");
7970 switch_to_section (function_section (current_function_decl));
7973 /* We keep a list of functions for which we have already built stubs
7974 in build_mips16_call_stub. */
7978 struct mips16_stub *next;
7983 static struct mips16_stub *mips16_stubs;
7985 /* Build a call stub for a mips16 call. A stub is needed if we are
7986 passing any floating point values which should go into the floating
7987 point registers. If we are, and the call turns out to be to a
7988 32-bit function, the stub will be used to move the values into the
7989 floating point registers before calling the 32-bit function. The
7990 linker will magically adjust the function call to either the 16-bit
7991 function or the 32-bit stub, depending upon where the function call
7992 is actually defined.
7994 Similarly, we need a stub if the return value might come back in a
7995 floating point register.
7997 RETVAL is the location of the return value, or null if this is
7998 a call rather than a call_value. FN is the address of the
7999 function and ARG_SIZE is the size of the arguments. FP_CODE
8000 is the code built by function_arg. This function returns a nonzero
8001 value if it builds the call instruction itself. */
8004 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8008 char *secname, *stubname;
8009 struct mips16_stub *l;
8010 tree stubid, stubdecl;
8014 /* We don't need to do anything if we aren't in mips16 mode, or if
8015 we were invoked with the -msoft-float option. */
8016 if (! TARGET_MIPS16 || ! mips16_hard_float)
8019 /* Figure out whether the value might come back in a floating point
8021 fpret = (retval != 0
8022 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8023 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8025 /* We don't need to do anything if there were no floating point
8026 arguments and the value will not be returned in a floating point
8028 if (fp_code == 0 && ! fpret)
8031 /* We don't need to do anything if this is a call to a special
8032 mips16 support function. */
8033 if (GET_CODE (fn) == SYMBOL_REF
8034 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8037 /* This code will only work for o32 and o64 abis. The other ABI's
8038 require more sophisticated support. */
8039 gcc_assert (TARGET_OLDABI);
8041 /* We can only handle SFmode and DFmode floating point return
8044 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
8046 /* If we're calling via a function pointer, then we must always call
8047 via a stub. There are magic stubs provided in libgcc.a for each
8048 of the required cases. Each of them expects the function address
8049 to arrive in register $2. */
8051 if (GET_CODE (fn) != SYMBOL_REF)
8057 /* ??? If this code is modified to support other ABI's, we need
8058 to handle PARALLEL return values here. */
8060 sprintf (buf, "__mips16_call_stub_%s%d",
8062 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8065 id = get_identifier (buf);
8066 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8068 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8070 if (retval == NULL_RTX)
8071 insn = gen_call_internal (stub_fn, arg_size);
8073 insn = gen_call_value_internal (retval, stub_fn, arg_size);
8074 insn = emit_call_insn (insn);
8076 /* Put the register usage information on the CALL. */
8077 CALL_INSN_FUNCTION_USAGE (insn) =
8078 gen_rtx_EXPR_LIST (VOIDmode,
8079 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8080 CALL_INSN_FUNCTION_USAGE (insn));
8082 /* If we are handling a floating point return value, we need to
8083 save $18 in the function prologue. Putting a note on the
8084 call will mean that regs_ever_live[$18] will be true if the
8085 call is not eliminated, and we can check that in the prologue
8088 CALL_INSN_FUNCTION_USAGE (insn) =
8089 gen_rtx_EXPR_LIST (VOIDmode,
8090 gen_rtx_USE (VOIDmode,
8091 gen_rtx_REG (word_mode, 18)),
8092 CALL_INSN_FUNCTION_USAGE (insn));
8094 /* Return 1 to tell the caller that we've generated the call
8099 /* We know the function we are going to call. If we have already
8100 built a stub, we don't need to do anything further. */
8102 fnname = XSTR (fn, 0);
8103 for (l = mips16_stubs; l != NULL; l = l->next)
8104 if (strcmp (l->name, fnname) == 0)
8109 /* Build a special purpose stub. When the linker sees a
8110 function call in mips16 code, it will check where the target
8111 is defined. If the target is a 32-bit call, the linker will
8112 search for the section defined here. It can tell which
8113 symbol this section is associated with by looking at the
8114 relocation information (the name is unreliable, since this
8115 might be a static function). If such a section is found, the
8116 linker will redirect the call to the start of the magic
8119 If the function does not return a floating point value, the
8120 special stub section is named
8123 If the function does return a floating point value, the stub
8125 .mips16.call.fp.FNNAME
8128 secname = (char *) alloca (strlen (fnname) + 40);
8129 sprintf (secname, ".mips16.call.%s%s",
8132 stubname = (char *) alloca (strlen (fnname) + 20);
8133 sprintf (stubname, "__call_stub_%s%s",
8136 stubid = get_identifier (stubname);
8137 stubdecl = build_decl (FUNCTION_DECL, stubid,
8138 build_function_type (void_type_node, NULL_TREE));
8139 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8141 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8143 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8147 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8149 fprintf (asm_out_file, "%s%s",
8150 need_comma ? ", " : "",
8151 (f & 3) == 1 ? "float" : "double");
8154 fprintf (asm_out_file, ")\n");
8156 fprintf (asm_out_file, "\t.set\tnomips16\n");
8157 assemble_start_function (stubdecl, stubname);
8159 if (!FUNCTION_NAME_ALREADY_DECLARED)
8161 fputs ("\t.ent\t", asm_out_file);
8162 assemble_name (asm_out_file, stubname);
8163 fputs ("\n", asm_out_file);
8165 assemble_name (asm_out_file, stubname);
8166 fputs (":\n", asm_out_file);
8169 /* We build the stub code by hand. That's the only way we can
8170 do it, since we can't generate 32-bit code during a 16-bit
8173 /* We don't want the assembler to insert any nops here. */
8174 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8176 mips16_fp_args (asm_out_file, fp_code, 0);
8180 fprintf (asm_out_file, "\t.set\tnoat\n");
8181 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8183 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8184 fprintf (asm_out_file, "\t.set\tat\n");
8185 /* Unfortunately, we can't fill the jump delay slot. We
8186 can't fill with one of the mtc1 instructions, because the
8187 result is not available for one instruction, so if the
8188 very first instruction in the function refers to the
8189 register, it will see the wrong value. */
8190 fprintf (asm_out_file, "\tnop\n");
8194 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8195 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8196 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8197 /* As above, we can't fill the delay slot. */
8198 fprintf (asm_out_file, "\tnop\n");
8199 if (GET_MODE (retval) == SFmode)
8200 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8201 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8204 if (TARGET_BIG_ENDIAN)
8206 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8207 reg_names[GP_REG_FIRST + 2],
8208 reg_names[FP_REG_FIRST + 1]);
8209 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8210 reg_names[GP_REG_FIRST + 3],
8211 reg_names[FP_REG_FIRST + 0]);
8215 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8216 reg_names[GP_REG_FIRST + 2],
8217 reg_names[FP_REG_FIRST + 0]);
8218 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8219 reg_names[GP_REG_FIRST + 3],
8220 reg_names[FP_REG_FIRST + 1]);
8223 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8224 /* As above, we can't fill the delay slot. */
8225 fprintf (asm_out_file, "\tnop\n");
8228 fprintf (asm_out_file, "\t.set\treorder\n");
8230 #ifdef ASM_DECLARE_FUNCTION_SIZE
8231 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8234 if (!FUNCTION_NAME_ALREADY_DECLARED)
8236 fputs ("\t.end\t", asm_out_file);
8237 assemble_name (asm_out_file, stubname);
8238 fputs ("\n", asm_out_file);
8241 fprintf (asm_out_file, "\t.set\tmips16\n");
8243 /* Record this stub. */
8244 l = (struct mips16_stub *) xmalloc (sizeof *l);
8245 l->name = xstrdup (fnname);
8247 l->next = mips16_stubs;
8251 /* If we expect a floating point return value, but we've built a
8252 stub which does not expect one, then we're in trouble. We can't
8253 use the existing stub, because it won't handle the floating point
8254 value. We can't build a new stub, because the linker won't know
8255 which stub to use for the various calls in this object file.
8256 Fortunately, this case is illegal, since it means that a function
8257 was declared in two different ways in a single compilation. */
8258 if (fpret && ! l->fpret)
8259 error ("cannot handle inconsistent calls to %qs", fnname);
8261 /* If we are calling a stub which handles a floating point return
8262 value, we need to arrange to save $18 in the prologue. We do
8263 this by marking the function call as using the register. The
8264 prologue will later see that it is used, and emit code to save
8271 if (retval == NULL_RTX)
8272 insn = gen_call_internal (fn, arg_size);
8274 insn = gen_call_value_internal (retval, fn, arg_size);
8275 insn = emit_call_insn (insn);
8277 CALL_INSN_FUNCTION_USAGE (insn) =
8278 gen_rtx_EXPR_LIST (VOIDmode,
8279 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8280 CALL_INSN_FUNCTION_USAGE (insn));
8282 /* Return 1 to tell the caller that we've generated the call
8287 /* Return 0 to let the caller generate the call insn. */
8291 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8292 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8294 struct mips16_constant {
8295 struct mips16_constant *next;
8298 enum machine_mode mode;
8301 /* Information about an incomplete mips16 constant pool. FIRST is the
8302 first constant, HIGHEST_ADDRESS is the highest address that the first
8303 byte of the pool can have, and INSN_ADDRESS is the current instruction
8306 struct mips16_constant_pool {
8307 struct mips16_constant *first;
8308 int highest_address;
8312 /* Add constant VALUE to POOL and return its label. MODE is the
8313 value's mode (used for CONST_INTs, etc.). */
8316 add_constant (struct mips16_constant_pool *pool,
8317 rtx value, enum machine_mode mode)
8319 struct mips16_constant **p, *c;
8320 bool first_of_size_p;
8322 /* See whether the constant is already in the pool. If so, return the
8323 existing label, otherwise leave P pointing to the place where the
8324 constant should be added.
8326 Keep the pool sorted in increasing order of mode size so that we can
8327 reduce the number of alignments needed. */
8328 first_of_size_p = true;
8329 for (p = &pool->first; *p != 0; p = &(*p)->next)
8331 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8333 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8335 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8336 first_of_size_p = false;
8339 /* In the worst case, the constant needed by the earliest instruction
8340 will end up at the end of the pool. The entire pool must then be
8341 accessible from that instruction.
8343 When adding the first constant, set the pool's highest address to
8344 the address of the first out-of-range byte. Adjust this address
8345 downwards each time a new constant is added. */
8346 if (pool->first == 0)
8347 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8348 is the address of the instruction with the lowest two bits clear.
8349 The base PC value for ld has the lowest three bits clear. Assume
8350 the worst case here. */
8351 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8352 pool->highest_address -= GET_MODE_SIZE (mode);
8353 if (first_of_size_p)
8354 /* Take into account the worst possible padding due to alignment. */
8355 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8357 /* Create a new entry. */
8358 c = (struct mips16_constant *) xmalloc (sizeof *c);
8361 c->label = gen_label_rtx ();
8368 /* Output constant VALUE after instruction INSN and return the last
8369 instruction emitted. MODE is the mode of the constant. */
8372 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8374 switch (GET_MODE_CLASS (mode))
8378 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8379 return emit_insn_after (gen_consttable_int (value, size), insn);
8383 return emit_insn_after (gen_consttable_float (value), insn);
8385 case MODE_VECTOR_FLOAT:
8386 case MODE_VECTOR_INT:
8389 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8390 insn = dump_constants_1 (GET_MODE_INNER (mode),
8391 CONST_VECTOR_ELT (value, i), insn);
8401 /* Dump out the constants in CONSTANTS after INSN. */
8404 dump_constants (struct mips16_constant *constants, rtx insn)
8406 struct mips16_constant *c, *next;
8410 for (c = constants; c != NULL; c = next)
8412 /* If necessary, increase the alignment of PC. */
8413 if (align < GET_MODE_SIZE (c->mode))
8415 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8416 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8418 align = GET_MODE_SIZE (c->mode);
8420 insn = emit_label_after (c->label, insn);
8421 insn = dump_constants_1 (c->mode, c->value, insn);
8427 emit_barrier_after (insn);
8430 /* Return the length of instruction INSN. */
8433 mips16_insn_length (rtx insn)
8437 rtx body = PATTERN (insn);
8438 if (GET_CODE (body) == ADDR_VEC)
8439 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8440 if (GET_CODE (body) == ADDR_DIFF_VEC)
8441 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8443 return get_attr_length (insn);
8446 /* Rewrite *X so that constant pool references refer to the constant's
8447 label instead. DATA points to the constant pool structure. */
8450 mips16_rewrite_pool_refs (rtx *x, void *data)
8452 struct mips16_constant_pool *pool = data;
8453 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8454 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8455 get_pool_constant (*x),
8456 get_pool_mode (*x)));
8460 /* Build MIPS16 constant pools. */
8463 mips16_lay_out_constants (void)
8465 struct mips16_constant_pool pool;
8469 memset (&pool, 0, sizeof (pool));
8470 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8472 /* Rewrite constant pool references in INSN. */
8474 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8476 pool.insn_address += mips16_insn_length (insn);
8478 if (pool.first != NULL)
8480 /* If there are no natural barriers between the first user of
8481 the pool and the highest acceptable address, we'll need to
8482 create a new instruction to jump around the constant pool.
8483 In the worst case, this instruction will be 4 bytes long.
8485 If it's too late to do this transformation after INSN,
8486 do it immediately before INSN. */
8487 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8491 label = gen_label_rtx ();
8493 jump = emit_jump_insn_before (gen_jump (label), insn);
8494 JUMP_LABEL (jump) = label;
8495 LABEL_NUSES (label) = 1;
8496 barrier = emit_barrier_after (jump);
8498 emit_label_after (label, barrier);
8499 pool.insn_address += 4;
8502 /* See whether the constant pool is now out of range of the first
8503 user. If so, output the constants after the previous barrier.
8504 Note that any instructions between BARRIER and INSN (inclusive)
8505 will use negative offsets to refer to the pool. */
8506 if (pool.insn_address > pool.highest_address)
8508 dump_constants (pool.first, barrier);
8512 else if (BARRIER_P (insn))
8516 dump_constants (pool.first, get_last_insn ());
8519 /* A temporary variable used by for_each_rtx callbacks, etc. */
8520 static rtx mips_sim_insn;
8522 /* A structure representing the state of the processor pipeline.
8523 Used by the mips_sim_* family of functions. */
8525 /* The maximum number of instructions that can be issued in a cycle.
8526 (Caches mips_issue_rate.) */
8527 unsigned int issue_rate;
8529 /* The current simulation time. */
8532 /* How many more instructions can be issued in the current cycle. */
8533 unsigned int insns_left;
8535 /* LAST_SET[X].INSN is the last instruction to set register X.
8536 LAST_SET[X].TIME is the time at which that instruction was issued.
8537 INSN is null if no instruction has yet set register X. */
8541 } last_set[FIRST_PSEUDO_REGISTER];
8543 /* The pipeline's current DFA state. */
8547 /* Reset STATE to the initial simulation state. */
8550 mips_sim_reset (struct mips_sim *state)
8553 state->insns_left = state->issue_rate;
8554 memset (&state->last_set, 0, sizeof (state->last_set));
8555 state_reset (state->dfa_state);
8558 /* Initialize STATE before its first use. DFA_STATE points to an
8559 allocated but uninitialized DFA state. */
8562 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8564 state->issue_rate = mips_issue_rate ();
8565 state->dfa_state = dfa_state;
8566 mips_sim_reset (state);
8569 /* Advance STATE by one clock cycle. */
8572 mips_sim_next_cycle (struct mips_sim *state)
8575 state->insns_left = state->issue_rate;
8576 state_transition (state->dfa_state, 0);
8579 /* Advance simulation state STATE until instruction INSN can read
8583 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8587 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8588 if (state->last_set[REGNO (reg) + i].insn != 0)
8592 t = state->last_set[REGNO (reg) + i].time;
8593 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8594 while (state->time < t)
8595 mips_sim_next_cycle (state);
8599 /* A for_each_rtx callback. If *X is a register, advance simulation state
8600 DATA until mips_sim_insn can read the register's value. */
8603 mips_sim_wait_regs_2 (rtx *x, void *data)
8606 mips_sim_wait_reg (data, mips_sim_insn, *x);
8610 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8613 mips_sim_wait_regs_1 (rtx *x, void *data)
8615 for_each_rtx (x, mips_sim_wait_regs_2, data);
8618 /* Advance simulation state STATE until all of INSN's register
8619 dependencies are satisfied. */
8622 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8624 mips_sim_insn = insn;
8625 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8628 /* Advance simulation state STATE until the units required by
8629 instruction INSN are available. */
8632 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8636 tmp_state = alloca (state_size ());
8637 while (state->insns_left == 0
8638 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8639 state_transition (tmp_state, insn) >= 0))
8640 mips_sim_next_cycle (state);
8643 /* Advance simulation state STATE until INSN is ready to issue. */
8646 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8648 mips_sim_wait_regs (state, insn);
8649 mips_sim_wait_units (state, insn);
8652 /* mips_sim_insn has just set X. Update the LAST_SET array
8653 in simulation state DATA. */
8656 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8658 struct mips_sim *state;
8663 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8665 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8666 state->last_set[REGNO (x) + i].time = state->time;
8670 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8671 can issue immediately (i.e., that mips_sim_wait_insn has already
8675 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8677 state_transition (state->dfa_state, insn);
8678 state->insns_left--;
8680 mips_sim_insn = insn;
8681 note_stores (PATTERN (insn), mips_sim_record_set, state);
8684 /* Simulate issuing a NOP in state STATE. */
8687 mips_sim_issue_nop (struct mips_sim *state)
8689 if (state->insns_left == 0)
8690 mips_sim_next_cycle (state);
8691 state->insns_left--;
8694 /* Update simulation state STATE so that it's ready to accept the instruction
8695 after INSN. INSN should be part of the main rtl chain, not a member of a
8699 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8701 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8703 mips_sim_issue_nop (state);
8705 switch (GET_CODE (SEQ_BEGIN (insn)))
8709 /* We can't predict the processor state after a call or label. */
8710 mips_sim_reset (state);
8714 /* The delay slots of branch likely instructions are only executed
8715 when the branch is taken. Therefore, if the caller has simulated
8716 the delay slot instruction, STATE does not really reflect the state
8717 of the pipeline for the instruction after the delay slot. Also,
8718 branch likely instructions tend to incur a penalty when not taken,
8719 so there will probably be an extra delay between the branch and
8720 the instruction after the delay slot. */
8721 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8722 mips_sim_reset (state);
8730 /* The VR4130 pipeline issues aligned pairs of instructions together,
8731 but it stalls the second instruction if it depends on the first.
8732 In order to cut down the amount of logic required, this dependence
8733 check is not based on a full instruction decode. Instead, any non-SPECIAL
8734 instruction is assumed to modify the register specified by bits 20-16
8735 (which is usually the "rt" field).
8737 In beq, beql, bne and bnel instructions, the rt field is actually an
8738 input, so we can end up with a false dependence between the branch
8739 and its delay slot. If this situation occurs in instruction INSN,
8740 try to avoid it by swapping rs and rt. */
8743 vr4130_avoid_branch_rt_conflict (rtx insn)
8747 first = SEQ_BEGIN (insn);
8748 second = SEQ_END (insn);
8750 && NONJUMP_INSN_P (second)
8751 && GET_CODE (PATTERN (first)) == SET
8752 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8753 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8755 /* Check for the right kind of condition. */
8756 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8757 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8758 && REG_P (XEXP (cond, 0))
8759 && REG_P (XEXP (cond, 1))
8760 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8761 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8763 /* SECOND mentions the rt register but not the rs register. */
8764 rtx tmp = XEXP (cond, 0);
8765 XEXP (cond, 0) = XEXP (cond, 1);
8766 XEXP (cond, 1) = tmp;
8771 /* Implement -mvr4130-align. Go through each basic block and simulate the
8772 processor pipeline. If we find that a pair of instructions could execute
8773 in parallel, and the first of those instruction is not 8-byte aligned,
8774 insert a nop to make it aligned. */
8777 vr4130_align_insns (void)
8779 struct mips_sim state;
8780 rtx insn, subinsn, last, last2, next;
8785 /* LAST is the last instruction before INSN to have a nonzero length.
8786 LAST2 is the last such instruction before LAST. */
8790 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8793 mips_sim_init (&state, alloca (state_size ()));
8794 for (insn = get_insns (); insn != 0; insn = next)
8796 unsigned int length;
8798 next = NEXT_INSN (insn);
8800 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8801 This isn't really related to the alignment pass, but we do it on
8802 the fly to avoid a separate instruction walk. */
8803 vr4130_avoid_branch_rt_conflict (insn);
8805 if (USEFUL_INSN_P (insn))
8806 FOR_EACH_SUBINSN (subinsn, insn)
8808 mips_sim_wait_insn (&state, subinsn);
8810 /* If we want this instruction to issue in parallel with the
8811 previous one, make sure that the previous instruction is
8812 aligned. There are several reasons why this isn't worthwhile
8813 when the second instruction is a call:
8815 - Calls are less likely to be performance critical,
8816 - There's a good chance that the delay slot can execute
8817 in parallel with the call.
8818 - The return address would then be unaligned.
8820 In general, if we're going to insert a nop between instructions
8821 X and Y, it's better to insert it immediately after X. That
8822 way, if the nop makes Y aligned, it will also align any labels
8824 if (state.insns_left != state.issue_rate
8825 && !CALL_P (subinsn))
8827 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8829 /* SUBINSN is the first instruction in INSN and INSN is
8830 aligned. We want to align the previous instruction
8831 instead, so insert a nop between LAST2 and LAST.
8833 Note that LAST could be either a single instruction
8834 or a branch with a delay slot. In the latter case,
8835 LAST, like INSN, is already aligned, but the delay
8836 slot must have some extra delay that stops it from
8837 issuing at the same time as the branch. We therefore
8838 insert a nop before the branch in order to align its
8840 emit_insn_after (gen_nop (), last2);
8843 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8845 /* SUBINSN is the delay slot of INSN, but INSN is
8846 currently unaligned. Insert a nop between
8847 LAST and INSN to align it. */
8848 emit_insn_after (gen_nop (), last);
8852 mips_sim_issue_insn (&state, subinsn);
8854 mips_sim_finish_insn (&state, insn);
8856 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8857 length = get_attr_length (insn);
8860 /* If the instruction is an asm statement or multi-instruction
8861 mips.md patern, the length is only an estimate. Insert an
8862 8 byte alignment after it so that the following instructions
8863 can be handled correctly. */
8864 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8865 && (recog_memoized (insn) < 0 || length >= 8))
8867 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8868 next = NEXT_INSN (next);
8869 mips_sim_next_cycle (&state);
8872 else if (length & 4)
8873 aligned_p = !aligned_p;
8878 /* See whether INSN is an aligned label. */
8879 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8885 /* Subroutine of mips_reorg. If there is a hazard between INSN
8886 and a previous instruction, avoid it by inserting nops after
8889 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8890 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8891 before using the value of that register. *HILO_DELAY counts the
8892 number of instructions since the last hilo hazard (that is,
8893 the number of instructions since the last mflo or mfhi).
8895 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8896 for the next instruction.
8898 LO_REG is an rtx for the LO register, used in dependence checking. */
8901 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8902 rtx *delayed_reg, rtx lo_reg)
8910 pattern = PATTERN (insn);
8912 /* Do not put the whole function in .set noreorder if it contains
8913 an asm statement. We don't know whether there will be hazards
8914 between the asm statement and the gcc-generated code. */
8915 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8916 cfun->machine->all_noreorder_p = false;
8918 /* Ignore zero-length instructions (barriers and the like). */
8919 ninsns = get_attr_length (insn) / 4;
8923 /* Work out how many nops are needed. Note that we only care about
8924 registers that are explicitly mentioned in the instruction's pattern.
8925 It doesn't matter that calls use the argument registers or that they
8926 clobber hi and lo. */
8927 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8928 nops = 2 - *hilo_delay;
8929 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8934 /* Insert the nops between this instruction and the previous one.
8935 Each new nop takes us further from the last hilo hazard. */
8936 *hilo_delay += nops;
8938 emit_insn_after (gen_hazard_nop (), after);
8940 /* Set up the state for the next instruction. */
8941 *hilo_delay += ninsns;
8943 if (INSN_CODE (insn) >= 0)
8944 switch (get_attr_hazard (insn))
8954 set = single_set (insn);
8955 gcc_assert (set != 0);
8956 *delayed_reg = SET_DEST (set);
8962 /* Go through the instruction stream and insert nops where necessary.
8963 See if the whole function can then be put into .set noreorder &
8967 mips_avoid_hazards (void)
8969 rtx insn, last_insn, lo_reg, delayed_reg;
8972 /* Force all instructions to be split into their final form. */
8973 split_all_insns_noflow ();
8975 /* Recalculate instruction lengths without taking nops into account. */
8976 cfun->machine->ignore_hazard_length_p = true;
8977 shorten_branches (get_insns ());
8979 cfun->machine->all_noreorder_p = true;
8981 /* Profiled functions can't be all noreorder because the profiler
8982 support uses assembler macros. */
8983 if (current_function_profile)
8984 cfun->machine->all_noreorder_p = false;
8986 /* Code compiled with -mfix-vr4120 can't be all noreorder because
8987 we rely on the assembler to work around some errata. */
8988 if (TARGET_FIX_VR4120)
8989 cfun->machine->all_noreorder_p = false;
8991 /* The same is true for -mfix-vr4130 if we might generate mflo or
8992 mfhi instructions. Note that we avoid using mflo and mfhi if
8993 the VR4130 macc and dmacc instructions are available instead;
8994 see the *mfhilo_{si,di}_macc patterns. */
8995 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
8996 cfun->machine->all_noreorder_p = false;
9001 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
9003 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9006 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9007 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9008 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
9009 &hilo_delay, &delayed_reg, lo_reg);
9011 mips_avoid_hazard (last_insn, insn, &hilo_delay,
9012 &delayed_reg, lo_reg);
9019 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
9025 mips16_lay_out_constants ();
9026 else if (TARGET_EXPLICIT_RELOCS)
9028 if (mips_flag_delayed_branch)
9029 dbr_schedule (get_insns ());
9030 mips_avoid_hazards ();
9031 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
9032 vr4130_align_insns ();
9036 /* This function does three things:
9038 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9039 - Register the mips16 hardware floating point stubs.
9040 - Register the gofast functions if selected using --enable-gofast. */
9042 #include "config/gofast.h"
9045 mips_init_libfuncs (void)
9047 if (TARGET_FIX_VR4120)
9049 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9050 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9053 if (TARGET_MIPS16 && mips16_hard_float)
9055 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9056 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9057 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9058 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9060 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9061 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9062 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9063 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9064 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9065 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9067 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9068 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9070 if (TARGET_DOUBLE_FLOAT)
9072 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9073 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9074 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9075 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9077 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9078 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9079 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9080 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9081 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9082 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9084 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
9085 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
9087 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
9088 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
9092 gofast_maybe_init_libfuncs ();
9095 /* Return a number assessing the cost of moving a register in class
9096 FROM to class TO. The classes are expressed using the enumeration
9097 values such as `GENERAL_REGS'. A value of 2 is the default; other
9098 values are interpreted relative to that.
9100 It is not required that the cost always equal 2 when FROM is the
9101 same as TO; on some machines it is expensive to move between
9102 registers if they are not general registers.
9104 If reload sees an insn consisting of a single `set' between two
9105 hard registers, and if `REGISTER_MOVE_COST' applied to their
9106 classes returns a value of 2, reload does not check to ensure that
9107 the constraints of the insn are met. Setting a cost of other than
9108 2 will allow reload to verify that the constraints are met. You
9109 should do this if the `movM' pattern's constraints do not allow
9112 ??? We make the cost of moving from HI/LO into general
9113 registers the same as for one of moving general registers to
9114 HI/LO for TARGET_MIPS16 in order to prevent allocating a
9115 pseudo to HI/LO. This might hurt optimizations though, it
9116 isn't clear if it is wise. And it might not work in all cases. We
9117 could solve the DImode LO reg problem by using a multiply, just
9118 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9119 problem by using divide instructions. divu puts the remainder in
9120 the HI reg, so doing a divide by -1 will move the value in the HI
9121 reg for all values except -1. We could handle that case by using a
9122 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9123 a compare/branch to test the input value to see which instruction
9124 we need to use. This gets pretty messy, but it is feasible. */
9127 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9128 enum reg_class to, enum reg_class from)
9130 if (from == M16_REGS && GR_REG_CLASS_P (to))
9132 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9134 else if (GR_REG_CLASS_P (from))
9138 else if (to == M16_NA_REGS)
9140 else if (GR_REG_CLASS_P (to))
9147 else if (to == FP_REGS)
9149 else if (reg_class_subset_p (to, ACC_REGS))
9156 else if (COP_REG_CLASS_P (to))
9161 else if (from == FP_REGS)
9163 if (GR_REG_CLASS_P (to))
9165 else if (to == FP_REGS)
9167 else if (to == ST_REGS)
9170 else if (reg_class_subset_p (from, ACC_REGS))
9172 if (GR_REG_CLASS_P (to))
9180 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9182 else if (COP_REG_CLASS_P (from))
9188 ??? What cases are these? Shouldn't we return 2 here? */
9193 /* Return the length of INSN. LENGTH is the initial length computed by
9194 attributes in the machine-description file. */
9197 mips_adjust_insn_length (rtx insn, int length)
9199 /* A unconditional jump has an unfilled delay slot if it is not part
9200 of a sequence. A conditional jump normally has a delay slot, but
9201 does not on MIPS16. */
9202 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9205 /* See how many nops might be needed to avoid hardware hazards. */
9206 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9207 switch (get_attr_hazard (insn))
9221 /* All MIPS16 instructions are a measly two bytes. */
9229 /* Return an asm sequence to start a noat block and load the address
9230 of a label into $1. */
9233 mips_output_load_label (void)
9235 if (TARGET_EXPLICIT_RELOCS)
9239 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9242 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9245 if (ISA_HAS_LOAD_DELAY)
9246 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9247 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9251 if (Pmode == DImode)
9252 return "%[dla\t%@,%0";
9254 return "%[la\t%@,%0";
9258 /* Return the assembly code for INSN, which has the operands given by
9259 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9260 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9261 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9262 version of BRANCH_IF_TRUE. */
9265 mips_output_conditional_branch (rtx insn, rtx *operands,
9266 const char *branch_if_true,
9267 const char *branch_if_false)
9269 unsigned int length;
9270 rtx taken, not_taken;
9272 length = get_attr_length (insn);
9275 /* Just a simple conditional branch. */
9276 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9277 return branch_if_true;
9280 /* Generate a reversed branch around a direct jump. This fallback does
9281 not use branch-likely instructions. */
9282 mips_branch_likely = false;
9283 not_taken = gen_label_rtx ();
9284 taken = operands[1];
9286 /* Generate the reversed branch to NOT_TAKEN. */
9287 operands[1] = not_taken;
9288 output_asm_insn (branch_if_false, operands);
9290 /* If INSN has a delay slot, we must provide delay slots for both the
9291 branch to NOT_TAKEN and the conditional jump. We must also ensure
9292 that INSN's delay slot is executed in the appropriate cases. */
9295 /* This first delay slot will always be executed, so use INSN's
9296 delay slot if is not annulled. */
9297 if (!INSN_ANNULLED_BRANCH_P (insn))
9299 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9300 asm_out_file, optimize, 1, NULL);
9301 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9304 output_asm_insn ("nop", 0);
9305 fprintf (asm_out_file, "\n");
9308 /* Output the unconditional branch to TAKEN. */
9310 output_asm_insn ("j\t%0%/", &taken);
9313 output_asm_insn (mips_output_load_label (), &taken);
9314 output_asm_insn ("jr\t%@%]%/", 0);
9317 /* Now deal with its delay slot; see above. */
9320 /* This delay slot will only be executed if the branch is taken.
9321 Use INSN's delay slot if is annulled. */
9322 if (INSN_ANNULLED_BRANCH_P (insn))
9324 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9325 asm_out_file, optimize, 1, NULL);
9326 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9329 output_asm_insn ("nop", 0);
9330 fprintf (asm_out_file, "\n");
9333 /* Output NOT_TAKEN. */
9334 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9335 CODE_LABEL_NUMBER (not_taken));
9339 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9340 if some ordered condition is true. The condition is given by
9341 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9342 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9343 its second is always zero. */
9346 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9348 const char *branch[2];
9350 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9351 Make BRANCH[0] branch on the inverse condition. */
9352 switch (GET_CODE (operands[0]))
9354 /* These cases are equivalent to comparisons against zero. */
9356 inverted_p = !inverted_p;
9359 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9360 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9363 /* These cases are always true or always false. */
9365 inverted_p = !inverted_p;
9368 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9369 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9373 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9374 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9377 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9380 /* Used to output div or ddiv instruction DIVISION, which has the operands
9381 given by OPERANDS. Add in a divide-by-zero check if needed.
9383 When working around R4000 and R4400 errata, we need to make sure that
9384 the division is not immediately followed by a shift[1][2]. We also
9385 need to stop the division from being put into a branch delay slot[3].
9386 The easiest way to avoid both problems is to add a nop after the
9387 division. When a divide-by-zero check is needed, this nop can be
9388 used to fill the branch delay slot.
9390 [1] If a double-word or a variable shift executes immediately
9391 after starting an integer division, the shift may give an
9392 incorrect result. See quotations of errata #16 and #28 from
9393 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9394 in mips.md for details.
9396 [2] A similar bug to [1] exists for all revisions of the
9397 R4000 and the R4400 when run in an MC configuration.
9398 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9400 "19. In this following sequence:
9402 ddiv (or ddivu or div or divu)
9403 dsll32 (or dsrl32, dsra32)
9405 if an MPT stall occurs, while the divide is slipping the cpu
9406 pipeline, then the following double shift would end up with an
9409 Workaround: The compiler needs to avoid generating any
9410 sequence with divide followed by extended double shift."
9412 This erratum is also present in "MIPS R4400MC Errata, Processor
9413 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9414 & 3.0" as errata #10 and #4, respectively.
9416 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9417 (also valid for MIPS R4000MC processors):
9419 "52. R4000SC: This bug does not apply for the R4000PC.
9421 There are two flavors of this bug:
9423 1) If the instruction just after divide takes an RF exception
9424 (tlb-refill, tlb-invalid) and gets an instruction cache
9425 miss (both primary and secondary) and the line which is
9426 currently in secondary cache at this index had the first
9427 data word, where the bits 5..2 are set, then R4000 would
9428 get a wrong result for the div.
9433 ------------------- # end-of page. -tlb-refill
9438 ------------------- # end-of page. -tlb-invalid
9441 2) If the divide is in the taken branch delay slot, where the
9442 target takes RF exception and gets an I-cache miss for the
9443 exception vector or where I-cache miss occurs for the
9444 target address, under the above mentioned scenarios, the
9445 div would get wrong results.
9448 j r2 # to next page mapped or unmapped
9449 div r8,r9 # this bug would be there as long
9450 # as there is an ICache miss and
9451 nop # the "data pattern" is present
9454 beq r0, r0, NextPage # to Next page
9458 This bug is present for div, divu, ddiv, and ddivu
9461 Workaround: For item 1), OS could make sure that the next page
9462 after the divide instruction is also mapped. For item 2), the
9463 compiler could make sure that the divide instruction is not in
9464 the branch delay slot."
9466 These processors have PRId values of 0x00004220 and 0x00004300 for
9467 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9470 mips_output_division (const char *division, rtx *operands)
9475 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9477 output_asm_insn (s, operands);
9480 if (TARGET_CHECK_ZERO_DIV)
9484 output_asm_insn (s, operands);
9485 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9487 else if (GENERATE_DIVIDE_TRAPS)
9489 output_asm_insn (s, operands);
9494 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9495 output_asm_insn (s, operands);
9496 s = "break\t7%)\n1:";
9502 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9503 with a final "000" replaced by "k". Ignore case.
9505 Note: this function is shared between GCC and GAS. */
9508 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9510 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9511 given++, canonical++;
9513 return ((*given == 0 && *canonical == 0)
9514 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9518 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9519 CPU name. We've traditionally allowed a lot of variation here.
9521 Note: this function is shared between GCC and GAS. */
9524 mips_matching_cpu_name_p (const char *canonical, const char *given)
9526 /* First see if the name matches exactly, or with a final "000"
9528 if (mips_strict_matching_cpu_name_p (canonical, given))
9531 /* If not, try comparing based on numerical designation alone.
9532 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9533 if (TOLOWER (*given) == 'r')
9535 if (!ISDIGIT (*given))
9538 /* Skip over some well-known prefixes in the canonical name,
9539 hoping to find a number there too. */
9540 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9542 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9544 else if (TOLOWER (canonical[0]) == 'r')
9547 return mips_strict_matching_cpu_name_p (canonical, given);
9551 /* Return the mips_cpu_info entry for the processor or ISA given
9552 by CPU_STRING. Return null if the string isn't recognized.
9554 A similar function exists in GAS. */
9556 static const struct mips_cpu_info *
9557 mips_parse_cpu (const char *cpu_string)
9559 const struct mips_cpu_info *p;
9562 /* In the past, we allowed upper-case CPU names, but it doesn't
9563 work well with the multilib machinery. */
9564 for (s = cpu_string; *s != 0; s++)
9567 warning (0, "the cpu name must be lower case");
9571 /* 'from-abi' selects the most compatible architecture for the given
9572 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9573 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9574 version. Look first at the -mgp options, if given, otherwise base
9575 the choice on MASK_64BIT in TARGET_DEFAULT. */
9576 if (strcasecmp (cpu_string, "from-abi") == 0)
9577 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9578 : ABI_NEEDS_64BIT_REGS ? 3
9579 : (TARGET_64BIT ? 3 : 1));
9581 /* 'default' has traditionally been a no-op. Probably not very useful. */
9582 if (strcasecmp (cpu_string, "default") == 0)
9585 for (p = mips_cpu_info_table; p->name != 0; p++)
9586 if (mips_matching_cpu_name_p (p->name, cpu_string))
9593 /* Return the processor associated with the given ISA level, or null
9594 if the ISA isn't valid. */
9596 static const struct mips_cpu_info *
9597 mips_cpu_info_from_isa (int isa)
9599 const struct mips_cpu_info *p;
9601 for (p = mips_cpu_info_table; p->name != 0; p++)
9608 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9609 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9610 they only hold condition code modes, and CCmode is always considered to
9611 be 4 bytes wide. All other registers are word sized. */
9614 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9616 if (ST_REG_P (regno))
9617 return ((GET_MODE_SIZE (mode) + 3) / 4);
9618 else if (! FP_REG_P (regno))
9619 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9621 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9624 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9625 all BLKmode objects are returned in memory. Under the new (N32 and
9626 64-bit MIPS ABIs) small structures are returned in a register.
9627 Objects with varying size must still be returned in memory, of
9631 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9634 return (TYPE_MODE (type) == BLKmode);
9636 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9637 || (int_size_in_bytes (type) == -1));
9641 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9643 return !TARGET_OLDABI;
9646 /* Return true if INSN is a multiply-add or multiply-subtract
9647 instruction and PREV assigns to the accumulator operand. */
9650 mips_linked_madd_p (rtx prev, rtx insn)
9654 x = single_set (insn);
9660 if (GET_CODE (x) == PLUS
9661 && GET_CODE (XEXP (x, 0)) == MULT
9662 && reg_set_p (XEXP (x, 1), prev))
9665 if (GET_CODE (x) == MINUS
9666 && GET_CODE (XEXP (x, 1)) == MULT
9667 && reg_set_p (XEXP (x, 0), prev))
9673 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9674 that may clobber hi or lo. */
9676 static rtx mips_macc_chains_last_hilo;
9678 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9679 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9682 mips_macc_chains_record (rtx insn)
9684 if (get_attr_may_clobber_hilo (insn))
9685 mips_macc_chains_last_hilo = insn;
9688 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9689 has NREADY elements, looking for a multiply-add or multiply-subtract
9690 instruction that is cumulative with mips_macc_chains_last_hilo.
9691 If there is one, promote it ahead of anything else that might
9692 clobber hi or lo. */
9695 mips_macc_chains_reorder (rtx *ready, int nready)
9699 if (mips_macc_chains_last_hilo != 0)
9700 for (i = nready - 1; i >= 0; i--)
9701 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9703 for (j = nready - 1; j > i; j--)
9704 if (recog_memoized (ready[j]) >= 0
9705 && get_attr_may_clobber_hilo (ready[j]))
9707 mips_promote_ready (ready, i, j);
9714 /* The last instruction to be scheduled. */
9716 static rtx vr4130_last_insn;
9718 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9719 points to an rtx that is initially an instruction. Nullify the rtx
9720 if the instruction uses the value of register X. */
9723 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9725 rtx *insn_ptr = data;
9728 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9732 /* Return true if there is true register dependence between vr4130_last_insn
9736 vr4130_true_reg_dependence_p (rtx insn)
9738 note_stores (PATTERN (vr4130_last_insn),
9739 vr4130_true_reg_dependence_p_1, &insn);
9743 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9744 the ready queue and that INSN2 is the instruction after it, return
9745 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9746 in which INSN1 and INSN2 can probably issue in parallel, but for
9747 which (INSN2, INSN1) should be less sensitive to instruction
9748 alignment than (INSN1, INSN2). See 4130.md for more details. */
9751 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9755 /* Check for the following case:
9757 1) there is some other instruction X with an anti dependence on INSN1;
9758 2) X has a higher priority than INSN2; and
9759 3) X is an arithmetic instruction (and thus has no unit restrictions).
9761 If INSN1 is the last instruction blocking X, it would better to
9762 choose (INSN1, X) over (INSN2, INSN1). */
9763 FOR_EACH_DEP_LINK (dep, INSN_FORW_DEPS (insn1))
9764 if (DEP_LINK_KIND (dep) == REG_DEP_ANTI
9765 && INSN_PRIORITY (DEP_LINK_CON (dep)) > INSN_PRIORITY (insn2)
9766 && recog_memoized (DEP_LINK_CON (dep)) >= 0
9767 && get_attr_vr4130_class (DEP_LINK_CON (dep)) == VR4130_CLASS_ALU)
9770 if (vr4130_last_insn != 0
9771 && recog_memoized (insn1) >= 0
9772 && recog_memoized (insn2) >= 0)
9774 /* See whether INSN1 and INSN2 use different execution units,
9775 or if they are both ALU-type instructions. If so, they can
9776 probably execute in parallel. */
9777 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9778 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9779 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9781 /* If only one of the instructions has a dependence on
9782 vr4130_last_insn, prefer to schedule the other one first. */
9783 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9784 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9788 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9789 is not an ALU-type instruction and if INSN1 uses the same
9790 execution unit. (Note that if this condition holds, we already
9791 know that INSN2 uses a different execution unit.) */
9792 if (class1 != VR4130_CLASS_ALU
9793 && recog_memoized (vr4130_last_insn) >= 0
9794 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9801 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9802 queue with at least two instructions. Swap the first two if
9803 vr4130_swap_insns_p says that it could be worthwhile. */
9806 vr4130_reorder (rtx *ready, int nready)
9808 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9809 mips_promote_ready (ready, nready - 2, nready - 1);
9812 /* Remove the instruction at index LOWER from ready queue READY and
9813 reinsert it in front of the instruction at index HIGHER. LOWER must
9817 mips_promote_ready (rtx *ready, int lower, int higher)
9822 new_head = ready[lower];
9823 for (i = lower; i < higher; i++)
9824 ready[i] = ready[i + 1];
9825 ready[i] = new_head;
9828 /* Implement TARGET_SCHED_REORDER. */
9831 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9832 rtx *ready, int *nreadyp, int cycle)
9834 if (!reload_completed && TUNE_MACC_CHAINS)
9837 mips_macc_chains_last_hilo = 0;
9839 mips_macc_chains_reorder (ready, *nreadyp);
9841 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9844 vr4130_last_insn = 0;
9846 vr4130_reorder (ready, *nreadyp);
9848 return mips_issue_rate ();
9851 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9854 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9857 switch (GET_CODE (PATTERN (insn)))
9861 /* Don't count USEs and CLOBBERs against the issue rate. */
9866 if (!reload_completed && TUNE_MACC_CHAINS)
9867 mips_macc_chains_record (insn);
9868 vr4130_last_insn = insn;
9874 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9875 dependencies have no cost. */
9878 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9879 rtx dep ATTRIBUTE_UNUSED, int cost)
9881 if (REG_NOTE_KIND (link) != 0)
9886 /* Return the number of instructions that can be issued per cycle. */
9889 mips_issue_rate (void)
9893 case PROCESSOR_R4130:
9894 case PROCESSOR_R5400:
9895 case PROCESSOR_R5500:
9896 case PROCESSOR_R7000:
9897 case PROCESSOR_R9000:
9901 case PROCESSOR_SB1A:
9902 /* This is actually 4, but we get better performance if we claim 3.
9903 This is partly because of unwanted speculative code motion with the
9904 larger number, and partly because in most common cases we can't
9905 reach the theoretical max of 4. */
9913 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9914 be as wide as the scheduling freedom in the DFA. */
9917 mips_multipass_dfa_lookahead (void)
9919 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9926 /* Implements a store data bypass check. We need this because the cprestore
9927 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
9928 default routine to abort. We just return false for that case. */
9929 /* ??? Should try to give a better result here than assuming false. */
9932 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
9934 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
9937 return ! store_data_bypass_p (out_insn, in_insn);
9940 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9941 return the first operand of the associated "pref" or "prefx" insn. */
9944 mips_prefetch_cookie (rtx write, rtx locality)
9946 /* store_streamed / load_streamed. */
9947 if (INTVAL (locality) <= 0)
9948 return GEN_INT (INTVAL (write) + 4);
9951 if (INTVAL (locality) <= 2)
9954 /* store_retained / load_retained. */
9955 return GEN_INT (INTVAL (write) + 6);
9958 /* MIPS builtin function support. */
9960 struct builtin_description
9962 /* The code of the main .md file instruction. See mips_builtin_type
9963 for more information. */
9964 enum insn_code icode;
9966 /* The floating-point comparison code to use with ICODE, if any. */
9967 enum mips_fp_condition cond;
9969 /* The name of the builtin function. */
9972 /* Specifies how the function should be expanded. */
9973 enum mips_builtin_type builtin_type;
9975 /* The function's prototype. */
9976 enum mips_function_type function_type;
9978 /* The target flags required for this function. */
9982 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9983 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9984 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9985 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9986 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9988 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9990 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9991 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9992 "__builtin_mips_" #INSN "_" #COND "_s", \
9993 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9994 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9995 "__builtin_mips_" #INSN "_" #COND "_d", \
9996 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9998 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9999 The lower and upper forms require TARGET_FLAGS while the any and all
10000 forms require MASK_MIPS3D. */
10001 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
10002 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10003 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
10004 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10005 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10006 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10007 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10008 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10009 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10010 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10011 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10012 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10013 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10015 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10016 require MASK_MIPS3D. */
10017 #define CMP_4S_BUILTINS(INSN, COND) \
10018 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10019 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10020 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10022 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10023 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10024 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10027 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10028 instruction requires TARGET_FLAGS. */
10029 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10030 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10031 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10032 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10034 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10035 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10036 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10039 /* Define all the builtins related to c.cond.fmt condition COND. */
10040 #define CMP_BUILTINS(COND) \
10041 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10042 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10043 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10044 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10045 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10046 CMP_4S_BUILTINS (c, COND), \
10047 CMP_4S_BUILTINS (cabs, COND)
10049 static const struct builtin_description mips_bdesc[] =
10051 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10052 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10053 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10054 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10055 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10056 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10057 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10058 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10060 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10061 MASK_PAIRED_SINGLE_FLOAT),
10062 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10063 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10064 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10065 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10067 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10068 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10069 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10070 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10071 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10072 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10074 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10075 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10076 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10077 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10078 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10079 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10081 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10084 /* Builtin functions for the SB-1 processor. */
10086 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10088 static const struct builtin_description sb1_bdesc[] =
10090 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10093 /* Builtin functions for DSP ASE. */
10095 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10096 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10097 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10098 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10100 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10101 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10102 builtin_description fields. */
10103 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10104 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10105 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10107 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10108 branch instruction. TARGET_FLAGS is a builtin_description field. */
10109 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10110 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10111 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10113 static const struct builtin_description dsp_bdesc[] =
10115 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10116 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10117 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10118 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10119 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10120 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10121 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10122 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10123 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10124 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10125 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10126 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10127 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10128 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10129 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10130 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10131 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10132 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10133 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10134 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10135 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10136 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10137 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10138 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10139 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10140 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10141 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10142 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10143 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10144 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10145 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10146 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10147 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10148 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10149 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10150 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10151 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10152 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10153 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10154 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10155 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10156 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10157 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10158 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10159 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10160 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10161 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10162 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10163 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10164 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10165 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10166 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10167 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10168 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10169 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10170 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10171 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10172 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10173 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10174 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10175 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10176 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10177 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10178 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10179 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10180 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10181 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10182 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10183 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10184 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10185 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10186 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10187 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10188 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10189 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10190 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10191 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10192 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10193 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10194 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10195 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10196 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10197 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10198 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10199 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10200 BPOSGE_BUILTIN (32, MASK_DSP)
10203 /* This helps provide a mapping from builtin function codes to bdesc
10208 /* The builtin function table that this entry describes. */
10209 const struct builtin_description *bdesc;
10211 /* The number of entries in the builtin function table. */
10214 /* The target processor that supports these builtin functions.
10215 PROCESSOR_MAX means we enable them for all processors. */
10216 enum processor_type proc;
10219 static const struct bdesc_map bdesc_arrays[] =
10221 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
10222 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
10223 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
10226 /* Take the argument ARGNUM of the arglist of EXP and convert it into a form
10227 suitable for input operand OP of instruction ICODE. Return the value. */
10230 mips_prepare_builtin_arg (enum insn_code icode,
10231 unsigned int op, tree exp, unsigned int argnum)
10234 enum machine_mode mode;
10236 value = expand_normal (CALL_EXPR_ARG (exp, argnum));
10237 mode = insn_data[icode].operand[op].mode;
10238 if (!insn_data[icode].operand[op].predicate (value, mode))
10240 value = copy_to_mode_reg (mode, value);
10241 /* Check the predicate again. */
10242 if (!insn_data[icode].operand[op].predicate (value, mode))
10244 error ("invalid argument to builtin function");
10252 /* Return an rtx suitable for output operand OP of instruction ICODE.
10253 If TARGET is non-null, try to use it where possible. */
10256 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10258 enum machine_mode mode;
10260 mode = insn_data[icode].operand[op].mode;
10261 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10262 target = gen_reg_rtx (mode);
10267 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10270 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10271 enum machine_mode mode ATTRIBUTE_UNUSED,
10272 int ignore ATTRIBUTE_UNUSED)
10274 enum insn_code icode;
10275 enum mips_builtin_type type;
10277 unsigned int fcode;
10278 const struct builtin_description *bdesc;
10279 const struct bdesc_map *m;
10281 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10282 fcode = DECL_FUNCTION_CODE (fndecl);
10285 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10287 if (fcode < m->size)
10290 icode = bdesc[fcode].icode;
10291 type = bdesc[fcode].builtin_type;
10301 case MIPS_BUILTIN_DIRECT:
10302 return mips_expand_builtin_direct (icode, target, exp, true);
10304 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10305 return mips_expand_builtin_direct (icode, target, exp, false);
10307 case MIPS_BUILTIN_MOVT:
10308 case MIPS_BUILTIN_MOVF:
10309 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10312 case MIPS_BUILTIN_CMP_ANY:
10313 case MIPS_BUILTIN_CMP_ALL:
10314 case MIPS_BUILTIN_CMP_UPPER:
10315 case MIPS_BUILTIN_CMP_LOWER:
10316 case MIPS_BUILTIN_CMP_SINGLE:
10317 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10320 case MIPS_BUILTIN_BPOSGE32:
10321 return mips_expand_builtin_bposge (type, target);
10328 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10331 mips_init_builtins (void)
10333 const struct builtin_description *d;
10334 const struct bdesc_map *m;
10335 tree types[(int) MIPS_MAX_FTYPE_MAX];
10336 tree V2SF_type_node;
10337 tree V2HI_type_node;
10338 tree V4QI_type_node;
10339 unsigned int offset;
10341 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10342 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10345 if (TARGET_PAIRED_SINGLE_FLOAT)
10347 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10349 types[MIPS_V2SF_FTYPE_V2SF]
10350 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10352 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10353 = build_function_type_list (V2SF_type_node,
10354 V2SF_type_node, V2SF_type_node, NULL_TREE);
10356 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10357 = build_function_type_list (V2SF_type_node,
10358 V2SF_type_node, V2SF_type_node,
10359 integer_type_node, NULL_TREE);
10361 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10362 = build_function_type_list (V2SF_type_node,
10363 V2SF_type_node, V2SF_type_node,
10364 V2SF_type_node, V2SF_type_node, NULL_TREE);
10366 types[MIPS_V2SF_FTYPE_SF_SF]
10367 = build_function_type_list (V2SF_type_node,
10368 float_type_node, float_type_node, NULL_TREE);
10370 types[MIPS_INT_FTYPE_V2SF_V2SF]
10371 = build_function_type_list (integer_type_node,
10372 V2SF_type_node, V2SF_type_node, NULL_TREE);
10374 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10375 = build_function_type_list (integer_type_node,
10376 V2SF_type_node, V2SF_type_node,
10377 V2SF_type_node, V2SF_type_node, NULL_TREE);
10379 types[MIPS_INT_FTYPE_SF_SF]
10380 = build_function_type_list (integer_type_node,
10381 float_type_node, float_type_node, NULL_TREE);
10383 types[MIPS_INT_FTYPE_DF_DF]
10384 = build_function_type_list (integer_type_node,
10385 double_type_node, double_type_node, NULL_TREE);
10387 types[MIPS_SF_FTYPE_V2SF]
10388 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10390 types[MIPS_SF_FTYPE_SF]
10391 = build_function_type_list (float_type_node,
10392 float_type_node, NULL_TREE);
10394 types[MIPS_SF_FTYPE_SF_SF]
10395 = build_function_type_list (float_type_node,
10396 float_type_node, float_type_node, NULL_TREE);
10398 types[MIPS_DF_FTYPE_DF]
10399 = build_function_type_list (double_type_node,
10400 double_type_node, NULL_TREE);
10402 types[MIPS_DF_FTYPE_DF_DF]
10403 = build_function_type_list (double_type_node,
10404 double_type_node, double_type_node, NULL_TREE);
10409 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10410 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10412 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10413 = build_function_type_list (V2HI_type_node,
10414 V2HI_type_node, V2HI_type_node,
10417 types[MIPS_SI_FTYPE_SI_SI]
10418 = build_function_type_list (intSI_type_node,
10419 intSI_type_node, intSI_type_node,
10422 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10423 = build_function_type_list (V4QI_type_node,
10424 V4QI_type_node, V4QI_type_node,
10427 types[MIPS_SI_FTYPE_V4QI]
10428 = build_function_type_list (intSI_type_node,
10432 types[MIPS_V2HI_FTYPE_V2HI]
10433 = build_function_type_list (V2HI_type_node,
10437 types[MIPS_SI_FTYPE_SI]
10438 = build_function_type_list (intSI_type_node,
10442 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10443 = build_function_type_list (V4QI_type_node,
10444 V2HI_type_node, V2HI_type_node,
10447 types[MIPS_V2HI_FTYPE_SI_SI]
10448 = build_function_type_list (V2HI_type_node,
10449 intSI_type_node, intSI_type_node,
10452 types[MIPS_SI_FTYPE_V2HI]
10453 = build_function_type_list (intSI_type_node,
10457 types[MIPS_V2HI_FTYPE_V4QI]
10458 = build_function_type_list (V2HI_type_node,
10462 types[MIPS_V4QI_FTYPE_V4QI_SI]
10463 = build_function_type_list (V4QI_type_node,
10464 V4QI_type_node, intSI_type_node,
10467 types[MIPS_V2HI_FTYPE_V2HI_SI]
10468 = build_function_type_list (V2HI_type_node,
10469 V2HI_type_node, intSI_type_node,
10472 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10473 = build_function_type_list (V2HI_type_node,
10474 V4QI_type_node, V2HI_type_node,
10477 types[MIPS_SI_FTYPE_V2HI_V2HI]
10478 = build_function_type_list (intSI_type_node,
10479 V2HI_type_node, V2HI_type_node,
10482 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10483 = build_function_type_list (intDI_type_node,
10484 intDI_type_node, V4QI_type_node, V4QI_type_node,
10487 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10488 = build_function_type_list (intDI_type_node,
10489 intDI_type_node, V2HI_type_node, V2HI_type_node,
10492 types[MIPS_DI_FTYPE_DI_SI_SI]
10493 = build_function_type_list (intDI_type_node,
10494 intDI_type_node, intSI_type_node, intSI_type_node,
10497 types[MIPS_V4QI_FTYPE_SI]
10498 = build_function_type_list (V4QI_type_node,
10502 types[MIPS_V2HI_FTYPE_SI]
10503 = build_function_type_list (V2HI_type_node,
10507 types[MIPS_VOID_FTYPE_V4QI_V4QI]
10508 = build_function_type_list (void_type_node,
10509 V4QI_type_node, V4QI_type_node,
10512 types[MIPS_SI_FTYPE_V4QI_V4QI]
10513 = build_function_type_list (intSI_type_node,
10514 V4QI_type_node, V4QI_type_node,
10517 types[MIPS_VOID_FTYPE_V2HI_V2HI]
10518 = build_function_type_list (void_type_node,
10519 V2HI_type_node, V2HI_type_node,
10522 types[MIPS_SI_FTYPE_DI_SI]
10523 = build_function_type_list (intSI_type_node,
10524 intDI_type_node, intSI_type_node,
10527 types[MIPS_DI_FTYPE_DI_SI]
10528 = build_function_type_list (intDI_type_node,
10529 intDI_type_node, intSI_type_node,
10532 types[MIPS_VOID_FTYPE_SI_SI]
10533 = build_function_type_list (void_type_node,
10534 intSI_type_node, intSI_type_node,
10537 types[MIPS_SI_FTYPE_PTR_SI]
10538 = build_function_type_list (intSI_type_node,
10539 ptr_type_node, intSI_type_node,
10542 types[MIPS_SI_FTYPE_VOID]
10543 = build_function_type (intSI_type_node, void_list_node);
10546 /* Iterate through all of the bdesc arrays, initializing all of the
10547 builtin functions. */
10550 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10552 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10553 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10554 if ((d->target_flags & target_flags) == d->target_flags)
10555 add_builtin_function (d->name, types[d->function_type],
10556 d - m->bdesc + offset,
10557 BUILT_IN_MD, NULL, NULL);
10562 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10563 .md pattern and CALL is the function expr with arguments. TARGET,
10564 if nonnull, suggests a good place to put the result.
10565 HAS_TARGET indicates the function must return something. */
10568 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
10571 rtx ops[MAX_RECOG_OPERANDS];
10577 /* We save target to ops[0]. */
10578 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10582 /* We need to test if the arglist is not zero. Some instructions have extra
10583 clobber registers. */
10584 for (; i < insn_data[icode].n_operands && i <= call_expr_nargs (exp); i++, j++)
10585 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
10590 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10594 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10598 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10602 gcc_unreachable ();
10607 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10608 function (TYPE says which). EXP is the tree for the function
10609 function, ICODE is the instruction that should be used to compare
10610 the first two arguments, and COND is the condition it should test.
10611 TARGET, if nonnull, suggests a good place to put the result. */
10614 mips_expand_builtin_movtf (enum mips_builtin_type type,
10615 enum insn_code icode, enum mips_fp_condition cond,
10616 rtx target, tree exp)
10618 rtx cmp_result, op0, op1;
10620 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10621 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
10622 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
10623 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10625 icode = CODE_FOR_mips_cond_move_tf_ps;
10626 target = mips_prepare_builtin_target (icode, 0, target);
10627 if (type == MIPS_BUILTIN_MOVT)
10629 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
10630 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
10634 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
10635 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
10637 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10641 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10642 into TARGET otherwise. Return TARGET. */
10645 mips_builtin_branch_and_move (rtx condition, rtx target,
10646 rtx value_if_true, rtx value_if_false)
10648 rtx true_label, done_label;
10650 true_label = gen_label_rtx ();
10651 done_label = gen_label_rtx ();
10653 /* First assume that CONDITION is false. */
10654 emit_move_insn (target, value_if_false);
10656 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10657 emit_jump_insn (gen_condjump (condition, true_label));
10658 emit_jump_insn (gen_jump (done_label));
10661 /* Fix TARGET if CONDITION is true. */
10662 emit_label (true_label);
10663 emit_move_insn (target, value_if_true);
10665 emit_label (done_label);
10669 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10670 of the comparison instruction and COND is the condition it should test.
10671 EXP is the function call and arguments and TARGET, if nonnull,
10672 suggests a good place to put the boolean result. */
10675 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10676 enum insn_code icode, enum mips_fp_condition cond,
10677 rtx target, tree exp)
10679 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10683 if (target == 0 || GET_MODE (target) != SImode)
10684 target = gen_reg_rtx (SImode);
10686 /* Prepare the operands to the comparison. */
10687 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10688 for (i = 1; i < insn_data[icode].n_operands - 1; i++, j++)
10689 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
10691 switch (insn_data[icode].n_operands)
10694 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10698 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10699 ops[3], ops[4], GEN_INT (cond)));
10703 gcc_unreachable ();
10706 /* If the comparison sets more than one register, we define the result
10707 to be 0 if all registers are false and -1 if all registers are true.
10708 The value of the complete result is indeterminate otherwise. */
10709 switch (builtin_type)
10711 case MIPS_BUILTIN_CMP_ALL:
10712 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10713 return mips_builtin_branch_and_move (condition, target,
10714 const0_rtx, const1_rtx);
10716 case MIPS_BUILTIN_CMP_UPPER:
10717 case MIPS_BUILTIN_CMP_LOWER:
10718 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10719 condition = gen_single_cc (cmp_result, offset);
10720 return mips_builtin_branch_and_move (condition, target,
10721 const1_rtx, const0_rtx);
10724 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10725 return mips_builtin_branch_and_move (condition, target,
10726 const1_rtx, const0_rtx);
10730 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10731 suggests a good place to put the boolean result. */
10734 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10736 rtx condition, cmp_result;
10739 if (target == 0 || GET_MODE (target) != SImode)
10740 target = gen_reg_rtx (SImode);
10742 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10744 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10749 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10750 return mips_builtin_branch_and_move (condition, target,
10751 const1_rtx, const0_rtx);
10754 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10755 FIRST is true if this is the first time handling this decl. */
10758 mips_encode_section_info (tree decl, rtx rtl, int first)
10760 default_encode_section_info (decl, rtl, first);
10762 if (TREE_CODE (decl) == FUNCTION_DECL
10763 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
10765 rtx symbol = XEXP (rtl, 0);
10766 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
10770 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. PIC_FUNCTION_ADDR_REGNUM is live
10771 on entry to a function when generating -mshared abicalls code. */
10774 mips_extra_live_on_entry (bitmap regs)
10776 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
10777 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10780 /* SImode values are represented as sign-extended to DImode. */
10783 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10785 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10786 return SIGN_EXTEND;
10791 #include "gt-mips.h"