1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
61 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save & restore registers.
78 Use a maximum gap of 0x100 in the mips16 case. We can then use
79 unextended instructions to save and restore registers, and to
80 allocate and deallocate the top part of the frame.
82 The value in the !mips16 case must be a SMALL_OPERAND and must
83 preserve the maximum stack alignment. */
84 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
86 /* True if INSN is a mips.md pattern or asm statement. */
87 #define USEFUL_INSN_P(INSN) \
89 && GET_CODE (PATTERN (INSN)) != USE \
90 && GET_CODE (PATTERN (INSN)) != CLOBBER \
91 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
92 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
94 /* If INSN is a delayed branch sequence, return the first instruction
95 in the sequence, otherwise return INSN itself. */
96 #define SEQ_BEGIN(INSN) \
97 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
98 ? XVECEXP (PATTERN (INSN), 0, 0) \
101 /* Likewise for the last instruction in a delayed branch sequence. */
102 #define SEQ_END(INSN) \
103 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
104 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
107 /* Execute the following loop body with SUBINSN set to each instruction
108 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
109 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
110 for ((SUBINSN) = SEQ_BEGIN (INSN); \
111 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
112 (SUBINSN) = NEXT_INSN (SUBINSN))
114 /* Classifies an address.
117 A natural register + offset address. The register satisfies
118 mips_valid_base_register_p and the offset is a const_arith_operand.
121 A LO_SUM rtx. The first operand is a valid base register and
122 the second operand is a symbolic address.
125 A signed 16-bit constant address.
128 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
129 enum mips_address_type {
136 /* Classifies the prototype of a builtin function. */
137 enum mips_function_type
139 MIPS_V2SF_FTYPE_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
142 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
143 MIPS_V2SF_FTYPE_SF_SF,
144 MIPS_INT_FTYPE_V2SF_V2SF,
145 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
146 MIPS_INT_FTYPE_SF_SF,
147 MIPS_INT_FTYPE_DF_DF,
154 /* For MIPS DSP ASE */
156 MIPS_DI_FTYPE_DI_SI_SI,
157 MIPS_DI_FTYPE_DI_V2HI_V2HI,
158 MIPS_DI_FTYPE_DI_V4QI_V4QI,
160 MIPS_SI_FTYPE_PTR_SI,
164 MIPS_SI_FTYPE_V2HI_V2HI,
166 MIPS_SI_FTYPE_V4QI_V4QI,
169 MIPS_V2HI_FTYPE_SI_SI,
170 MIPS_V2HI_FTYPE_V2HI,
171 MIPS_V2HI_FTYPE_V2HI_SI,
172 MIPS_V2HI_FTYPE_V2HI_V2HI,
173 MIPS_V2HI_FTYPE_V4QI,
174 MIPS_V2HI_FTYPE_V4QI_V2HI,
176 MIPS_V4QI_FTYPE_V2HI_V2HI,
177 MIPS_V4QI_FTYPE_V4QI_SI,
178 MIPS_V4QI_FTYPE_V4QI_V4QI,
179 MIPS_VOID_FTYPE_SI_SI,
180 MIPS_VOID_FTYPE_V2HI_V2HI,
181 MIPS_VOID_FTYPE_V4QI_V4QI,
187 /* Specifies how a builtin function should be converted into rtl. */
188 enum mips_builtin_type
190 /* The builtin corresponds directly to an .md pattern. The return
191 value is mapped to operand 0 and the arguments are mapped to
192 operands 1 and above. */
195 /* The builtin corresponds directly to an .md pattern. There is no return
196 value and the arguments are mapped to operands 0 and above. */
197 MIPS_BUILTIN_DIRECT_NO_TARGET,
199 /* The builtin corresponds to a comparison instruction followed by
200 a mips_cond_move_tf_ps pattern. The first two arguments are the
201 values to compare and the second two arguments are the vector
202 operands for the movt.ps or movf.ps instruction (in assembly order). */
206 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
207 of this instruction is the result of the comparison, which has mode
208 CCV2 or CCV4. The function arguments are mapped to operands 1 and
209 above. The function's return value is an SImode boolean that is
210 true under the following conditions:
212 MIPS_BUILTIN_CMP_ANY: one of the registers is true
213 MIPS_BUILTIN_CMP_ALL: all of the registers are true
214 MIPS_BUILTIN_CMP_LOWER: the first register is true
215 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
216 MIPS_BUILTIN_CMP_ANY,
217 MIPS_BUILTIN_CMP_ALL,
218 MIPS_BUILTIN_CMP_UPPER,
219 MIPS_BUILTIN_CMP_LOWER,
221 /* As above, but the instruction only sets a single $fcc register. */
222 MIPS_BUILTIN_CMP_SINGLE,
224 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
225 MIPS_BUILTIN_BPOSGE32
228 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
229 #define MIPS_FP_CONDITIONS(MACRO) \
247 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
248 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
249 enum mips_fp_condition {
250 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
253 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
254 #define STRINGIFY(X) #X
255 static const char *const mips_fp_conditions[] = {
256 MIPS_FP_CONDITIONS (STRINGIFY)
259 /* A function to save or store a register. The first argument is the
260 register and the second is the stack slot. */
261 typedef void (*mips_save_restore_fn) (rtx, rtx);
263 struct mips16_constant;
264 struct mips_arg_info;
265 struct mips_address_info;
266 struct mips_integer_op;
269 static enum mips_symbol_type mips_classify_symbol (rtx);
270 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
271 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
272 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
273 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
274 static bool mips_classify_address (struct mips_address_info *, rtx,
275 enum machine_mode, int);
276 static bool mips_cannot_force_const_mem (rtx);
277 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
278 static int mips_symbol_insns (enum mips_symbol_type);
279 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
280 static rtx mips_force_temporary (rtx, rtx);
281 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
282 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
283 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
284 static unsigned int mips_build_lower (struct mips_integer_op *,
285 unsigned HOST_WIDE_INT);
286 static unsigned int mips_build_integer (struct mips_integer_op *,
287 unsigned HOST_WIDE_INT);
288 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
289 static int m16_check_op (rtx, int, int, int);
290 static bool mips_rtx_costs (rtx, int, int, int *);
291 static int mips_address_cost (rtx);
292 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
293 static void mips_load_call_address (rtx, rtx, int);
294 static bool mips_function_ok_for_sibcall (tree, tree);
295 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
296 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
297 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
298 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
299 tree, int, struct mips_arg_info *);
300 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
301 static void mips_set_architecture (const struct mips_cpu_info *);
302 static void mips_set_tune (const struct mips_cpu_info *);
303 static bool mips_handle_option (size_t, const char *, int);
304 static struct machine_function *mips_init_machine_status (void);
305 static void print_operand_reloc (FILE *, rtx, const char **);
307 static void irix_output_external_libcall (rtx);
309 static void mips_file_start (void);
310 static void mips_file_end (void);
311 static bool mips_rewrite_small_data_p (rtx);
312 static int mips_small_data_pattern_1 (rtx *, void *);
313 static int mips_rewrite_small_data_1 (rtx *, void *);
314 static bool mips_function_has_gp_insn (void);
315 static unsigned int mips_global_pointer (void);
316 static bool mips_save_reg_p (unsigned int);
317 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
318 mips_save_restore_fn);
319 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
320 static void mips_output_cplocal (void);
321 static void mips_emit_loadgp (void);
322 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
323 static void mips_set_frame_expr (rtx);
324 static rtx mips_frame_set (rtx, rtx);
325 static void mips_save_reg (rtx, rtx);
326 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
327 static void mips_restore_reg (rtx, rtx);
328 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
329 HOST_WIDE_INT, tree);
330 static int symbolic_expression_p (rtx);
331 static section *mips_select_rtx_section (enum machine_mode, rtx,
332 unsigned HOST_WIDE_INT);
333 static section *mips_function_rodata_section (tree);
334 static bool mips_in_small_data_p (tree);
335 static bool mips_use_anchors_for_symbol_p (rtx);
336 static int mips_fpr_return_fields (tree, tree *);
337 static bool mips_return_in_msb (tree);
338 static rtx mips_return_fpr_pair (enum machine_mode mode,
339 enum machine_mode mode1, HOST_WIDE_INT,
340 enum machine_mode mode2, HOST_WIDE_INT);
341 static rtx mips16_gp_pseudo_reg (void);
342 static void mips16_fp_args (FILE *, int, int);
343 static void build_mips16_function_stub (FILE *);
344 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
345 static void dump_constants (struct mips16_constant *, rtx);
346 static int mips16_insn_length (rtx);
347 static int mips16_rewrite_pool_refs (rtx *, void *);
348 static void mips16_lay_out_constants (void);
349 static void mips_sim_reset (struct mips_sim *);
350 static void mips_sim_init (struct mips_sim *, state_t);
351 static void mips_sim_next_cycle (struct mips_sim *);
352 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
353 static int mips_sim_wait_regs_2 (rtx *, void *);
354 static void mips_sim_wait_regs_1 (rtx *, void *);
355 static void mips_sim_wait_regs (struct mips_sim *, rtx);
356 static void mips_sim_wait_units (struct mips_sim *, rtx);
357 static void mips_sim_wait_insn (struct mips_sim *, rtx);
358 static void mips_sim_record_set (rtx, rtx, void *);
359 static void mips_sim_issue_insn (struct mips_sim *, rtx);
360 static void mips_sim_issue_nop (struct mips_sim *);
361 static void mips_sim_finish_insn (struct mips_sim *, rtx);
362 static void vr4130_avoid_branch_rt_conflict (rtx);
363 static void vr4130_align_insns (void);
364 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
365 static void mips_avoid_hazards (void);
366 static void mips_reorg (void);
367 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
368 static bool mips_matching_cpu_name_p (const char *, const char *);
369 static const struct mips_cpu_info *mips_parse_cpu (const char *);
370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
371 static bool mips_return_in_memory (tree, tree);
372 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
373 static void mips_macc_chains_record (rtx);
374 static void mips_macc_chains_reorder (rtx *, int);
375 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
376 static bool vr4130_true_reg_dependence_p (rtx);
377 static bool vr4130_swap_insns_p (rtx, rtx);
378 static void vr4130_reorder (rtx *, int);
379 static void mips_promote_ready (rtx *, int, int);
380 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
381 static int mips_variable_issue (FILE *, int, rtx, int);
382 static int mips_adjust_cost (rtx, rtx, rtx, int);
383 static int mips_issue_rate (void);
384 static int mips_multipass_dfa_lookahead (void);
385 static void mips_init_libfuncs (void);
386 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
388 static tree mips_build_builtin_va_list (void);
389 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
390 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
392 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
394 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
396 static bool mips_valid_pointer_mode (enum machine_mode);
397 static bool mips_vector_mode_supported_p (enum machine_mode);
398 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
399 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
400 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
401 static void mips_init_builtins (void);
402 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
403 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
404 enum insn_code, enum mips_fp_condition,
406 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
407 enum insn_code, enum mips_fp_condition,
409 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
410 static void mips_encode_section_info (tree, rtx, int);
411 static void mips_extra_live_on_entry (bitmap);
412 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
414 /* Structure to be filled in by compute_frame_size with register
415 save masks, and offsets for the current function. */
417 struct mips_frame_info GTY(())
419 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
420 HOST_WIDE_INT var_size; /* # bytes that variables take up */
421 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
422 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
423 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
424 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
425 unsigned int mask; /* mask of saved gp registers */
426 unsigned int fmask; /* mask of saved fp registers */
427 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
428 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
429 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
430 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
431 bool initialized; /* true if frame size already calculated */
432 int num_gp; /* number of gp registers saved */
433 int num_fp; /* number of fp registers saved */
436 struct machine_function GTY(()) {
437 /* Pseudo-reg holding the value of $28 in a mips16 function which
438 refers to GP relative global variables. */
439 rtx mips16_gp_pseudo_rtx;
441 /* The number of extra stack bytes taken up by register varargs.
442 This area is allocated by the callee at the very top of the frame. */
445 /* Current frame information, calculated by compute_frame_size. */
446 struct mips_frame_info frame;
448 /* The register to use as the global pointer within this function. */
449 unsigned int global_pointer;
451 /* True if mips_adjust_insn_length should ignore an instruction's
453 bool ignore_hazard_length_p;
455 /* True if the whole function is suitable for .set noreorder and
457 bool all_noreorder_p;
459 /* True if the function is known to have an instruction that needs $gp. */
463 /* Information about a single argument. */
466 /* True if the argument is passed in a floating-point register, or
467 would have been if we hadn't run out of registers. */
470 /* The number of words passed in registers, rounded up. */
471 unsigned int reg_words;
473 /* For EABI, the offset of the first register from GP_ARG_FIRST or
474 FP_ARG_FIRST. For other ABIs, the offset of the first register from
475 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
476 comment for details).
478 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
480 unsigned int reg_offset;
482 /* The number of words that must be passed on the stack, rounded up. */
483 unsigned int stack_words;
485 /* The offset from the start of the stack overflow area of the argument's
486 first stack word. Only meaningful when STACK_WORDS is nonzero. */
487 unsigned int stack_offset;
491 /* Information about an address described by mips_address_type.
497 REG is the base register and OFFSET is the constant offset.
500 REG is the register that contains the high part of the address,
501 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
502 is the type of OFFSET's symbol.
505 SYMBOL_TYPE is the type of symbol being referenced. */
507 struct mips_address_info
509 enum mips_address_type type;
512 enum mips_symbol_type symbol_type;
516 /* One stage in a constant building sequence. These sequences have
520 A = A CODE[1] VALUE[1]
521 A = A CODE[2] VALUE[2]
524 where A is an accumulator, each CODE[i] is a binary rtl operation
525 and each VALUE[i] is a constant integer. */
526 struct mips_integer_op {
528 unsigned HOST_WIDE_INT value;
532 /* The largest number of operations needed to load an integer constant.
533 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
534 When the lowest bit is clear, we can try, but reject a sequence with
535 an extra SLL at the end. */
536 #define MIPS_MAX_INTEGER_OPS 7
539 /* Global variables for machine-dependent things. */
541 /* Threshold for data being put into the small data/bss area, instead
542 of the normal data area. */
543 int mips_section_threshold = -1;
545 /* Count the number of .file directives, so that .loc is up to date. */
546 int num_source_filenames = 0;
548 /* Count the number of sdb related labels are generated (to find block
549 start and end boundaries). */
550 int sdb_label_count = 0;
552 /* Next label # for each statement for Silicon Graphics IRIS systems. */
555 /* Linked list of all externals that are to be emitted when optimizing
556 for the global pointer if they haven't been declared by the end of
557 the program with an appropriate .comm or initialization. */
559 struct extern_list GTY (())
561 struct extern_list *next; /* next external */
562 const char *name; /* name of the external */
563 int size; /* size in bytes */
566 static GTY (()) struct extern_list *extern_head = 0;
568 /* Name of the file containing the current function. */
569 const char *current_function_file = "";
571 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
577 /* The next branch instruction is a branch likely, not branch normal. */
578 int mips_branch_likely;
580 /* The operands passed to the last cmpMM expander. */
583 /* The target cpu for code generation. */
584 enum processor_type mips_arch;
585 const struct mips_cpu_info *mips_arch_info;
587 /* The target cpu for optimization and scheduling. */
588 enum processor_type mips_tune;
589 const struct mips_cpu_info *mips_tune_info;
591 /* Which instruction set architecture to use. */
594 /* Which ABI to use. */
595 int mips_abi = MIPS_ABI_DEFAULT;
597 /* Cost information to use. */
598 const struct mips_rtx_cost_data *mips_cost;
600 /* Whether we are generating mips16 hard float code. In mips16 mode
601 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
602 -msoft-float was not specified by the user, which means that we
603 should arrange to call mips32 hard floating point code. */
604 int mips16_hard_float;
606 /* The architecture selected by -mipsN. */
607 static const struct mips_cpu_info *mips_isa_info;
609 /* If TRUE, we split addresses into their high and low parts in the RTL. */
610 int mips_split_addresses;
612 /* Mode used for saving/restoring general purpose registers. */
613 static enum machine_mode gpr_mode;
615 /* Array giving truth value on whether or not a given hard register
616 can support a given mode. */
617 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
619 /* List of all MIPS punctuation characters used by print_operand. */
620 char mips_print_operand_punct[256];
622 /* Map GCC register number to debugger register number. */
623 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
625 /* A copy of the original flag_delayed_branch: see override_options. */
626 static int mips_flag_delayed_branch;
628 static GTY (()) int mips_output_filename_first_time = 1;
630 /* mips_split_p[X] is true if symbols of type X can be split by
631 mips_split_symbol(). */
632 bool mips_split_p[NUM_SYMBOL_TYPES];
634 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
635 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
636 if they are matched by a special .md file pattern. */
637 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
639 /* Likewise for HIGHs. */
640 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
642 /* Map hard register number to register class */
643 const enum reg_class mips_regno_to_class[] =
645 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
646 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
647 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
648 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
649 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
650 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
651 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
652 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
653 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
654 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
655 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
657 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
658 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
659 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
660 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
661 HI_REG, LO_REG, NO_REGS, ST_REGS,
662 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
663 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
664 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
665 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
666 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
667 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
668 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
669 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
670 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
671 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
672 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
673 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
674 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
675 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
676 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
677 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
678 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
679 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
680 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
681 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
682 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
683 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
684 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
685 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
686 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
687 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
688 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
689 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
690 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
691 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
694 /* Table of machine dependent attributes. */
695 const struct attribute_spec mips_attribute_table[] =
697 { "long_call", 0, 0, false, true, true, NULL },
698 { NULL, 0, 0, false, false, false, NULL }
701 /* A table describing all the processors gcc knows about. Names are
702 matched in the order listed. The first mention of an ISA level is
703 taken as the canonical name for that ISA.
705 To ease comparison, please keep this table in the same order as
706 gas's mips_cpu_info_table[]. */
707 const struct mips_cpu_info mips_cpu_info_table[] = {
708 /* Entries for generic ISAs */
709 { "mips1", PROCESSOR_R3000, 1 },
710 { "mips2", PROCESSOR_R6000, 2 },
711 { "mips3", PROCESSOR_R4000, 3 },
712 { "mips4", PROCESSOR_R8000, 4 },
713 { "mips32", PROCESSOR_4KC, 32 },
714 { "mips32r2", PROCESSOR_M4K, 33 },
715 { "mips64", PROCESSOR_5KC, 64 },
718 { "r3000", PROCESSOR_R3000, 1 },
719 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
720 { "r3900", PROCESSOR_R3900, 1 },
723 { "r6000", PROCESSOR_R6000, 2 },
726 { "r4000", PROCESSOR_R4000, 3 },
727 { "vr4100", PROCESSOR_R4100, 3 },
728 { "vr4111", PROCESSOR_R4111, 3 },
729 { "vr4120", PROCESSOR_R4120, 3 },
730 { "vr4130", PROCESSOR_R4130, 3 },
731 { "vr4300", PROCESSOR_R4300, 3 },
732 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
733 { "r4600", PROCESSOR_R4600, 3 },
734 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
735 { "r4650", PROCESSOR_R4650, 3 },
738 { "r8000", PROCESSOR_R8000, 4 },
739 { "vr5000", PROCESSOR_R5000, 4 },
740 { "vr5400", PROCESSOR_R5400, 4 },
741 { "vr5500", PROCESSOR_R5500, 4 },
742 { "rm7000", PROCESSOR_R7000, 4 },
743 { "rm9000", PROCESSOR_R9000, 4 },
746 { "4kc", PROCESSOR_4KC, 32 },
747 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
748 { "4kp", PROCESSOR_4KP, 32 },
750 /* MIPS32 Release 2 */
751 { "m4k", PROCESSOR_M4K, 33 },
752 { "24k", PROCESSOR_24K, 33 },
753 { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
754 { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
755 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
758 { "5kc", PROCESSOR_5KC, 64 },
759 { "5kf", PROCESSOR_5KF, 64 },
760 { "20kc", PROCESSOR_20KC, 64 },
761 { "sb1", PROCESSOR_SB1, 64 },
762 { "sb1a", PROCESSOR_SB1A, 64 },
763 { "sr71000", PROCESSOR_SR71000, 64 },
769 /* Default costs. If these are used for a processor we should look
770 up the actual costs. */
771 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
772 COSTS_N_INSNS (7), /* fp_mult_sf */ \
773 COSTS_N_INSNS (8), /* fp_mult_df */ \
774 COSTS_N_INSNS (23), /* fp_div_sf */ \
775 COSTS_N_INSNS (36), /* fp_div_df */ \
776 COSTS_N_INSNS (10), /* int_mult_si */ \
777 COSTS_N_INSNS (10), /* int_mult_di */ \
778 COSTS_N_INSNS (69), /* int_div_si */ \
779 COSTS_N_INSNS (69), /* int_div_di */ \
780 2, /* branch_cost */ \
781 4 /* memory_latency */
783 /* Need to replace these with the costs of calling the appropriate
785 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
786 COSTS_N_INSNS (256), /* fp_mult_sf */ \
787 COSTS_N_INSNS (256), /* fp_mult_df */ \
788 COSTS_N_INSNS (256), /* fp_div_sf */ \
789 COSTS_N_INSNS (256) /* fp_div_df */
791 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
794 COSTS_N_INSNS (2), /* fp_add */
795 COSTS_N_INSNS (4), /* fp_mult_sf */
796 COSTS_N_INSNS (5), /* fp_mult_df */
797 COSTS_N_INSNS (12), /* fp_div_sf */
798 COSTS_N_INSNS (19), /* fp_div_df */
799 COSTS_N_INSNS (12), /* int_mult_si */
800 COSTS_N_INSNS (12), /* int_mult_di */
801 COSTS_N_INSNS (35), /* int_div_si */
802 COSTS_N_INSNS (35), /* int_div_di */
804 4 /* memory_latency */
809 COSTS_N_INSNS (6), /* int_mult_si */
810 COSTS_N_INSNS (6), /* int_mult_di */
811 COSTS_N_INSNS (36), /* int_div_si */
812 COSTS_N_INSNS (36), /* int_div_di */
814 4 /* memory_latency */
818 COSTS_N_INSNS (36), /* int_mult_si */
819 COSTS_N_INSNS (36), /* int_mult_di */
820 COSTS_N_INSNS (37), /* int_div_si */
821 COSTS_N_INSNS (37), /* int_div_di */
823 4 /* memory_latency */
827 COSTS_N_INSNS (4), /* int_mult_si */
828 COSTS_N_INSNS (11), /* int_mult_di */
829 COSTS_N_INSNS (36), /* int_div_si */
830 COSTS_N_INSNS (68), /* int_div_di */
832 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* fp_add */
836 COSTS_N_INSNS (4), /* fp_mult_sf */
837 COSTS_N_INSNS (5), /* fp_mult_df */
838 COSTS_N_INSNS (17), /* fp_div_sf */
839 COSTS_N_INSNS (32), /* fp_div_df */
840 COSTS_N_INSNS (4), /* int_mult_si */
841 COSTS_N_INSNS (11), /* int_mult_di */
842 COSTS_N_INSNS (36), /* int_div_si */
843 COSTS_N_INSNS (68), /* int_div_di */
845 4 /* memory_latency */
851 COSTS_N_INSNS (8), /* fp_add */
852 COSTS_N_INSNS (8), /* fp_mult_sf */
853 COSTS_N_INSNS (10), /* fp_mult_df */
854 COSTS_N_INSNS (34), /* fp_div_sf */
855 COSTS_N_INSNS (64), /* fp_div_df */
856 COSTS_N_INSNS (5), /* int_mult_si */
857 COSTS_N_INSNS (5), /* int_mult_di */
858 COSTS_N_INSNS (41), /* int_div_si */
859 COSTS_N_INSNS (41), /* int_div_di */
861 4 /* memory_latency */
864 COSTS_N_INSNS (4), /* fp_add */
865 COSTS_N_INSNS (4), /* fp_mult_sf */
866 COSTS_N_INSNS (5), /* fp_mult_df */
867 COSTS_N_INSNS (17), /* fp_div_sf */
868 COSTS_N_INSNS (32), /* fp_div_df */
869 COSTS_N_INSNS (5), /* int_mult_si */
870 COSTS_N_INSNS (5), /* int_mult_di */
871 COSTS_N_INSNS (41), /* int_div_si */
872 COSTS_N_INSNS (41), /* int_div_di */
874 4 /* memory_latency */
880 COSTS_N_INSNS (2), /* fp_add */
881 COSTS_N_INSNS (4), /* fp_mult_sf */
882 COSTS_N_INSNS (5), /* fp_mult_df */
883 COSTS_N_INSNS (12), /* fp_div_sf */
884 COSTS_N_INSNS (19), /* fp_div_df */
885 COSTS_N_INSNS (2), /* int_mult_si */
886 COSTS_N_INSNS (2), /* int_mult_di */
887 COSTS_N_INSNS (35), /* int_div_si */
888 COSTS_N_INSNS (35), /* int_div_di */
890 4 /* memory_latency */
893 COSTS_N_INSNS (3), /* fp_add */
894 COSTS_N_INSNS (5), /* fp_mult_sf */
895 COSTS_N_INSNS (6), /* fp_mult_df */
896 COSTS_N_INSNS (15), /* fp_div_sf */
897 COSTS_N_INSNS (16), /* fp_div_df */
898 COSTS_N_INSNS (17), /* int_mult_si */
899 COSTS_N_INSNS (17), /* int_mult_di */
900 COSTS_N_INSNS (38), /* int_div_si */
901 COSTS_N_INSNS (38), /* int_div_di */
903 6 /* memory_latency */
906 COSTS_N_INSNS (6), /* fp_add */
907 COSTS_N_INSNS (7), /* fp_mult_sf */
908 COSTS_N_INSNS (8), /* fp_mult_df */
909 COSTS_N_INSNS (23), /* fp_div_sf */
910 COSTS_N_INSNS (36), /* fp_div_df */
911 COSTS_N_INSNS (10), /* int_mult_si */
912 COSTS_N_INSNS (10), /* int_mult_di */
913 COSTS_N_INSNS (69), /* int_div_si */
914 COSTS_N_INSNS (69), /* int_div_di */
916 6 /* memory_latency */
928 /* The only costs that appear to be updated here are
929 integer multiplication. */
931 COSTS_N_INSNS (4), /* int_mult_si */
932 COSTS_N_INSNS (6), /* int_mult_di */
933 COSTS_N_INSNS (69), /* int_div_si */
934 COSTS_N_INSNS (69), /* int_div_di */
936 4 /* memory_latency */
948 COSTS_N_INSNS (6), /* fp_add */
949 COSTS_N_INSNS (4), /* fp_mult_sf */
950 COSTS_N_INSNS (5), /* fp_mult_df */
951 COSTS_N_INSNS (23), /* fp_div_sf */
952 COSTS_N_INSNS (36), /* fp_div_df */
953 COSTS_N_INSNS (5), /* int_mult_si */
954 COSTS_N_INSNS (5), /* int_mult_di */
955 COSTS_N_INSNS (36), /* int_div_si */
956 COSTS_N_INSNS (36), /* int_div_di */
958 4 /* memory_latency */
961 COSTS_N_INSNS (6), /* fp_add */
962 COSTS_N_INSNS (5), /* fp_mult_sf */
963 COSTS_N_INSNS (6), /* fp_mult_df */
964 COSTS_N_INSNS (30), /* fp_div_sf */
965 COSTS_N_INSNS (59), /* fp_div_df */
966 COSTS_N_INSNS (3), /* int_mult_si */
967 COSTS_N_INSNS (4), /* int_mult_di */
968 COSTS_N_INSNS (42), /* int_div_si */
969 COSTS_N_INSNS (74), /* int_div_di */
971 4 /* memory_latency */
974 COSTS_N_INSNS (6), /* fp_add */
975 COSTS_N_INSNS (5), /* fp_mult_sf */
976 COSTS_N_INSNS (6), /* fp_mult_df */
977 COSTS_N_INSNS (30), /* fp_div_sf */
978 COSTS_N_INSNS (59), /* fp_div_df */
979 COSTS_N_INSNS (5), /* int_mult_si */
980 COSTS_N_INSNS (9), /* int_mult_di */
981 COSTS_N_INSNS (42), /* int_div_si */
982 COSTS_N_INSNS (74), /* int_div_di */
984 4 /* memory_latency */
987 /* The only costs that are changed here are
988 integer multiplication. */
989 COSTS_N_INSNS (6), /* fp_add */
990 COSTS_N_INSNS (7), /* fp_mult_sf */
991 COSTS_N_INSNS (8), /* fp_mult_df */
992 COSTS_N_INSNS (23), /* fp_div_sf */
993 COSTS_N_INSNS (36), /* fp_div_df */
994 COSTS_N_INSNS (5), /* int_mult_si */
995 COSTS_N_INSNS (9), /* int_mult_di */
996 COSTS_N_INSNS (69), /* int_div_si */
997 COSTS_N_INSNS (69), /* int_div_di */
999 4 /* memory_latency */
1005 /* The only costs that are changed here are
1006 integer multiplication. */
1007 COSTS_N_INSNS (6), /* fp_add */
1008 COSTS_N_INSNS (7), /* fp_mult_sf */
1009 COSTS_N_INSNS (8), /* fp_mult_df */
1010 COSTS_N_INSNS (23), /* fp_div_sf */
1011 COSTS_N_INSNS (36), /* fp_div_df */
1012 COSTS_N_INSNS (3), /* int_mult_si */
1013 COSTS_N_INSNS (8), /* int_mult_di */
1014 COSTS_N_INSNS (69), /* int_div_si */
1015 COSTS_N_INSNS (69), /* int_div_di */
1016 1, /* branch_cost */
1017 4 /* memory_latency */
1020 /* These costs are the same as the SB-1A below. */
1021 COSTS_N_INSNS (4), /* fp_add */
1022 COSTS_N_INSNS (4), /* fp_mult_sf */
1023 COSTS_N_INSNS (4), /* fp_mult_df */
1024 COSTS_N_INSNS (24), /* fp_div_sf */
1025 COSTS_N_INSNS (32), /* fp_div_df */
1026 COSTS_N_INSNS (3), /* int_mult_si */
1027 COSTS_N_INSNS (4), /* int_mult_di */
1028 COSTS_N_INSNS (36), /* int_div_si */
1029 COSTS_N_INSNS (68), /* int_div_di */
1030 1, /* branch_cost */
1031 4 /* memory_latency */
1034 /* These costs are the same as the SB-1 above. */
1035 COSTS_N_INSNS (4), /* fp_add */
1036 COSTS_N_INSNS (4), /* fp_mult_sf */
1037 COSTS_N_INSNS (4), /* fp_mult_df */
1038 COSTS_N_INSNS (24), /* fp_div_sf */
1039 COSTS_N_INSNS (32), /* fp_div_df */
1040 COSTS_N_INSNS (3), /* int_mult_si */
1041 COSTS_N_INSNS (4), /* int_mult_di */
1042 COSTS_N_INSNS (36), /* int_div_si */
1043 COSTS_N_INSNS (68), /* int_div_di */
1044 1, /* branch_cost */
1045 4 /* memory_latency */
1053 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1054 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1055 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1058 /* Initialize the GCC target structure. */
1059 #undef TARGET_ASM_ALIGNED_HI_OP
1060 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1061 #undef TARGET_ASM_ALIGNED_SI_OP
1062 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1063 #undef TARGET_ASM_ALIGNED_DI_OP
1064 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1066 #undef TARGET_ASM_FUNCTION_PROLOGUE
1067 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1068 #undef TARGET_ASM_FUNCTION_EPILOGUE
1069 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1070 #undef TARGET_ASM_SELECT_RTX_SECTION
1071 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1072 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1073 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1075 #undef TARGET_SCHED_REORDER
1076 #define TARGET_SCHED_REORDER mips_sched_reorder
1077 #undef TARGET_SCHED_VARIABLE_ISSUE
1078 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1079 #undef TARGET_SCHED_ADJUST_COST
1080 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1081 #undef TARGET_SCHED_ISSUE_RATE
1082 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1083 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1084 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1085 mips_multipass_dfa_lookahead
1087 #undef TARGET_DEFAULT_TARGET_FLAGS
1088 #define TARGET_DEFAULT_TARGET_FLAGS \
1090 | TARGET_CPU_DEFAULT \
1091 | TARGET_ENDIAN_DEFAULT \
1092 | TARGET_FP_EXCEPTIONS_DEFAULT \
1093 | MASK_CHECK_ZERO_DIV \
1095 #undef TARGET_HANDLE_OPTION
1096 #define TARGET_HANDLE_OPTION mips_handle_option
1098 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1099 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1101 #undef TARGET_VALID_POINTER_MODE
1102 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1103 #undef TARGET_RTX_COSTS
1104 #define TARGET_RTX_COSTS mips_rtx_costs
1105 #undef TARGET_ADDRESS_COST
1106 #define TARGET_ADDRESS_COST mips_address_cost
1108 #undef TARGET_IN_SMALL_DATA_P
1109 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1111 #undef TARGET_MACHINE_DEPENDENT_REORG
1112 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1114 #undef TARGET_ASM_FILE_START
1115 #undef TARGET_ASM_FILE_END
1116 #define TARGET_ASM_FILE_START mips_file_start
1117 #define TARGET_ASM_FILE_END mips_file_end
1118 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1119 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1121 #undef TARGET_INIT_LIBFUNCS
1122 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1124 #undef TARGET_BUILD_BUILTIN_VA_LIST
1125 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1126 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1127 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1129 #undef TARGET_PROMOTE_FUNCTION_ARGS
1130 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1131 #undef TARGET_PROMOTE_FUNCTION_RETURN
1132 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1133 #undef TARGET_PROMOTE_PROTOTYPES
1134 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1136 #undef TARGET_RETURN_IN_MEMORY
1137 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1138 #undef TARGET_RETURN_IN_MSB
1139 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1141 #undef TARGET_ASM_OUTPUT_MI_THUNK
1142 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1143 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1144 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1146 #undef TARGET_SETUP_INCOMING_VARARGS
1147 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1148 #undef TARGET_STRICT_ARGUMENT_NAMING
1149 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1150 #undef TARGET_MUST_PASS_IN_STACK
1151 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1152 #undef TARGET_PASS_BY_REFERENCE
1153 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1154 #undef TARGET_CALLEE_COPIES
1155 #define TARGET_CALLEE_COPIES mips_callee_copies
1156 #undef TARGET_ARG_PARTIAL_BYTES
1157 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1159 #undef TARGET_MODE_REP_EXTENDED
1160 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1162 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1163 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1165 #undef TARGET_INIT_BUILTINS
1166 #define TARGET_INIT_BUILTINS mips_init_builtins
1167 #undef TARGET_EXPAND_BUILTIN
1168 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1170 #undef TARGET_HAVE_TLS
1171 #define TARGET_HAVE_TLS HAVE_AS_TLS
1173 #undef TARGET_CANNOT_FORCE_CONST_MEM
1174 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1176 #undef TARGET_ENCODE_SECTION_INFO
1177 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1179 #undef TARGET_ATTRIBUTE_TABLE
1180 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1182 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1183 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1185 #undef TARGET_MIN_ANCHOR_OFFSET
1186 #define TARGET_MIN_ANCHOR_OFFSET -32768
1187 #undef TARGET_MAX_ANCHOR_OFFSET
1188 #define TARGET_MAX_ANCHOR_OFFSET 32767
1189 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1190 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1191 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1192 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1194 struct gcc_target targetm = TARGET_INITIALIZER;
1196 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1198 static enum mips_symbol_type
1199 mips_classify_symbol (rtx x)
1201 if (GET_CODE (x) == LABEL_REF)
1204 return SYMBOL_CONSTANT_POOL;
1205 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1206 return SYMBOL_GOT_LOCAL;
1207 return SYMBOL_GENERAL;
1210 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1212 if (SYMBOL_REF_TLS_MODEL (x))
1215 if (CONSTANT_POOL_ADDRESS_P (x))
1218 return SYMBOL_CONSTANT_POOL;
1220 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1221 return SYMBOL_SMALL_DATA;
1224 /* Do not use small-data accesses for weak symbols; they may end up
1226 if (SYMBOL_REF_SMALL_P (x)
1227 && !SYMBOL_REF_WEAK (x))
1228 return SYMBOL_SMALL_DATA;
1230 if (TARGET_ABICALLS)
1232 if (SYMBOL_REF_DECL (x) == 0)
1234 if (!SYMBOL_REF_LOCAL_P (x))
1235 return SYMBOL_GOT_GLOBAL;
1239 /* Don't use GOT accesses for locally-binding symbols if
1240 TARGET_ABSOLUTE_ABICALLS. Otherwise, there are three
1243 - o32 PIC (either with or without explicit relocs)
1244 - n32/n64 PIC without explicit relocs
1245 - n32/n64 PIC with explicit relocs
1247 In the first case, both local and global accesses will use an
1248 R_MIPS_GOT16 relocation. We must correctly predict which of
1249 the two semantics (local or global) the assembler and linker
1250 will apply. The choice doesn't depend on the symbol's
1251 visibility, so we deliberately ignore decl_visibility and
1254 In the second case, the assembler will not use R_MIPS_GOT16
1255 relocations, but it chooses between local and global accesses
1256 in the same way as for o32 PIC.
1258 In the third case we have more freedom since both forms of
1259 access will work for any kind of symbol. However, there seems
1260 little point in doing things differently. */
1261 if (DECL_P (SYMBOL_REF_DECL (x))
1262 && TREE_PUBLIC (SYMBOL_REF_DECL (x))
1263 && !(TARGET_ABSOLUTE_ABICALLS
1264 && targetm.binds_local_p (SYMBOL_REF_DECL (x))))
1265 return SYMBOL_GOT_GLOBAL;
1268 if (!TARGET_ABSOLUTE_ABICALLS)
1269 return SYMBOL_GOT_LOCAL;
1272 return SYMBOL_GENERAL;
1276 /* Split X into a base and a constant offset, storing them in *BASE
1277 and *OFFSET respectively. */
1280 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
1284 if (GET_CODE (x) == CONST)
1287 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1289 *offset += INTVAL (XEXP (x, 1));
1296 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1297 to the same object as SYMBOL, or to the same object_block. */
1300 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
1302 if (GET_CODE (symbol) != SYMBOL_REF)
1305 if (CONSTANT_POOL_ADDRESS_P (symbol)
1307 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
1310 if (SYMBOL_REF_DECL (symbol) != 0
1312 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
1315 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol)
1316 && SYMBOL_REF_BLOCK (symbol)
1317 && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0
1318 && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol)
1319 < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size))
1326 /* Return true if X is a symbolic constant that can be calculated in
1327 the same way as a bare symbol. If it is, store the type of the
1328 symbol in *SYMBOL_TYPE. */
1331 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1333 HOST_WIDE_INT offset;
1335 mips_split_const (x, &x, &offset);
1336 if (UNSPEC_ADDRESS_P (x))
1337 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1338 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1340 *symbol_type = mips_classify_symbol (x);
1341 if (*symbol_type == SYMBOL_TLS)
1350 /* Check whether a nonzero offset is valid for the underlying
1352 switch (*symbol_type)
1354 case SYMBOL_GENERAL:
1355 case SYMBOL_64_HIGH:
1358 /* If the target has 64-bit pointers and the object file only
1359 supports 32-bit symbols, the values of those symbols will be
1360 sign-extended. In this case we can't allow an arbitrary offset
1361 in case the 32-bit value X + OFFSET has a different sign from X. */
1362 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1363 return mips_offset_within_object_p (x, offset);
1365 /* In other cases the relocations can handle any offset. */
1368 case SYMBOL_CONSTANT_POOL:
1369 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1370 In this case, we no longer have access to the underlying constant,
1371 but the original symbol-based access was known to be valid. */
1372 if (GET_CODE (x) == LABEL_REF)
1377 case SYMBOL_SMALL_DATA:
1378 /* Make sure that the offset refers to something within the
1379 underlying object. This should guarantee that the final
1380 PC- or GP-relative offset is within the 16-bit limit. */
1381 return mips_offset_within_object_p (x, offset);
1383 case SYMBOL_GOT_LOCAL:
1384 case SYMBOL_GOTOFF_PAGE:
1385 /* The linker should provide enough local GOT entries for a
1386 16-bit offset. Larger offsets may lead to GOT overflow. */
1387 return SMALL_OPERAND (offset);
1389 case SYMBOL_GOT_GLOBAL:
1390 case SYMBOL_GOTOFF_GLOBAL:
1391 case SYMBOL_GOTOFF_CALL:
1392 case SYMBOL_GOTOFF_LOADGP:
1397 case SYMBOL_GOTTPREL:
1405 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1408 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1410 if (regno >= FIRST_PSEUDO_REGISTER)
1414 regno = reg_renumber[regno];
1417 /* These fake registers will be eliminated to either the stack or
1418 hard frame pointer, both of which are usually valid base registers.
1419 Reload deals with the cases where the eliminated form isn't valid. */
1420 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1423 /* In mips16 mode, the stack pointer can only address word and doubleword
1424 values, nothing smaller. There are two problems here:
1426 (a) Instantiating virtual registers can introduce new uses of the
1427 stack pointer. If these virtual registers are valid addresses,
1428 the stack pointer should be too.
1430 (b) Most uses of the stack pointer are not made explicit until
1431 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1432 We don't know until that stage whether we'll be eliminating to the
1433 stack pointer (which needs the restriction) or the hard frame
1434 pointer (which doesn't).
1436 All in all, it seems more consistent to only enforce this restriction
1437 during and after reload. */
1438 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1439 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1441 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1445 /* Return true if X is a valid base register for the given mode.
1446 Allow only hard registers if STRICT. */
1449 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1451 if (!strict && GET_CODE (x) == SUBREG)
1455 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1459 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1460 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1463 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1464 enum machine_mode mode)
1466 switch (symbol_type)
1468 case SYMBOL_GENERAL:
1469 return !TARGET_MIPS16;
1471 case SYMBOL_SMALL_DATA:
1474 case SYMBOL_CONSTANT_POOL:
1475 /* PC-relative addressing is only available for lw and ld. */
1476 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1478 case SYMBOL_GOT_LOCAL:
1481 case SYMBOL_GOT_GLOBAL:
1482 /* The address will have to be loaded from the GOT first. */
1485 case SYMBOL_GOTOFF_PAGE:
1486 case SYMBOL_GOTOFF_GLOBAL:
1487 case SYMBOL_GOTOFF_CALL:
1488 case SYMBOL_GOTOFF_LOADGP:
1493 case SYMBOL_GOTTPREL:
1495 case SYMBOL_64_HIGH:
1504 /* Return true if X is a valid address for machine mode MODE. If it is,
1505 fill in INFO appropriately. STRICT is true if we should only accept
1506 hard base registers. */
1509 mips_classify_address (struct mips_address_info *info, rtx x,
1510 enum machine_mode mode, int strict)
1512 switch (GET_CODE (x))
1516 info->type = ADDRESS_REG;
1518 info->offset = const0_rtx;
1519 return mips_valid_base_register_p (info->reg, mode, strict);
1522 info->type = ADDRESS_REG;
1523 info->reg = XEXP (x, 0);
1524 info->offset = XEXP (x, 1);
1525 return (mips_valid_base_register_p (info->reg, mode, strict)
1526 && const_arith_operand (info->offset, VOIDmode));
1529 info->type = ADDRESS_LO_SUM;
1530 info->reg = XEXP (x, 0);
1531 info->offset = XEXP (x, 1);
1532 return (mips_valid_base_register_p (info->reg, mode, strict)
1533 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1534 && mips_symbolic_address_p (info->symbol_type, mode)
1535 && mips_lo_relocs[info->symbol_type] != 0);
1538 /* Small-integer addresses don't occur very often, but they
1539 are legitimate if $0 is a valid base register. */
1540 info->type = ADDRESS_CONST_INT;
1541 return !TARGET_MIPS16 && SMALL_INT (x);
1546 info->type = ADDRESS_SYMBOLIC;
1547 return (mips_symbolic_constant_p (x, &info->symbol_type)
1548 && mips_symbolic_address_p (info->symbol_type, mode)
1549 && !mips_split_p[info->symbol_type]);
1556 /* Return true if X is a thread-local symbol. */
1559 mips_tls_operand_p (rtx x)
1561 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1564 /* Return true if X can not be forced into a constant pool. */
1567 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1569 return mips_tls_operand_p (*x);
1572 /* Return true if X can not be forced into a constant pool. */
1575 mips_cannot_force_const_mem (rtx x)
1578 HOST_WIDE_INT offset;
1582 /* As an optimization, reject constants that mips_legitimize_move
1585 Suppose we have a multi-instruction sequence that loads constant C
1586 into register R. If R does not get allocated a hard register, and
1587 R is used in an operand that allows both registers and memory
1588 references, reload will consider forcing C into memory and using
1589 one of the instruction's memory alternatives. Returning false
1590 here will force it to use an input reload instead. */
1591 if (GET_CODE (x) == CONST_INT)
1594 mips_split_const (x, &base, &offset);
1595 if (symbolic_operand (base, VOIDmode) && SMALL_OPERAND (offset))
1599 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1605 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1606 constant pools, but normal-mode code doesn't need to. */
1609 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1610 rtx x ATTRIBUTE_UNUSED)
1612 return !TARGET_MIPS16;
1615 /* Return the number of instructions needed to load a symbol of the
1616 given type into a register. If valid in an address, the same number
1617 of instructions are needed for loads and stores. Treat extended
1618 mips16 instructions as two instructions. */
1621 mips_symbol_insns (enum mips_symbol_type type)
1625 case SYMBOL_GENERAL:
1626 /* In mips16 code, general symbols must be fetched from the
1631 /* When using 64-bit symbols, we need 5 preparatory instructions,
1634 lui $at,%highest(symbol)
1635 daddiu $at,$at,%higher(symbol)
1637 daddiu $at,$at,%hi(symbol)
1640 The final address is then $at + %lo(symbol). With 32-bit
1641 symbols we just need a preparatory lui. */
1642 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1644 case SYMBOL_SMALL_DATA:
1647 case SYMBOL_CONSTANT_POOL:
1648 /* This case is for mips16 only. Assume we'll need an
1649 extended instruction. */
1652 case SYMBOL_GOT_LOCAL:
1653 case SYMBOL_GOT_GLOBAL:
1654 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1655 the local/global classification is accurate. See override_options
1658 The worst cases are:
1660 (1) For local symbols when generating o32 or o64 code. The assembler
1666 ...and the final address will be $at + %lo(symbol).
1668 (2) For global symbols when -mxgot. The assembler will use:
1670 lui $at,%got_hi(symbol)
1673 ...and the final address will be $at + %got_lo(symbol). */
1676 case SYMBOL_GOTOFF_PAGE:
1677 case SYMBOL_GOTOFF_GLOBAL:
1678 case SYMBOL_GOTOFF_CALL:
1679 case SYMBOL_GOTOFF_LOADGP:
1680 case SYMBOL_64_HIGH:
1686 case SYMBOL_GOTTPREL:
1688 /* Check whether the offset is a 16- or 32-bit value. */
1689 return mips_split_p[type] ? 2 : 1;
1692 /* We don't treat a bare TLS symbol as a constant. */
1698 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1701 mips_stack_address_p (rtx x, enum machine_mode mode)
1703 struct mips_address_info addr;
1705 return (mips_classify_address (&addr, x, mode, false)
1706 && addr.type == ADDRESS_REG
1707 && addr.reg == stack_pointer_rtx);
1710 /* Return true if a value at OFFSET bytes from BASE can be accessed
1711 using an unextended mips16 instruction. MODE is the mode of the
1714 Usually the offset in an unextended instruction is a 5-bit field.
1715 The offset is unsigned and shifted left once for HIs, twice
1716 for SIs, and so on. An exception is SImode accesses off the
1717 stack pointer, which have an 8-bit immediate field. */
1720 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1723 && GET_CODE (offset) == CONST_INT
1724 && INTVAL (offset) >= 0
1725 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1727 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1728 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1729 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1735 /* Return the number of instructions needed to load or store a value
1736 of mode MODE at X. Return 0 if X isn't valid for MODE.
1738 For mips16 code, count extended instructions as two instructions. */
1741 mips_address_insns (rtx x, enum machine_mode mode)
1743 struct mips_address_info addr;
1746 if (mode == BLKmode)
1747 /* BLKmode is used for single unaligned loads and stores. */
1750 /* Each word of a multi-word value will be accessed individually. */
1751 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1753 if (mips_classify_address (&addr, x, mode, false))
1758 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1762 case ADDRESS_LO_SUM:
1763 return (TARGET_MIPS16 ? factor * 2 : factor);
1765 case ADDRESS_CONST_INT:
1768 case ADDRESS_SYMBOLIC:
1769 return factor * mips_symbol_insns (addr.symbol_type);
1775 /* Likewise for constant X. */
1778 mips_const_insns (rtx x)
1780 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1781 enum mips_symbol_type symbol_type;
1782 HOST_WIDE_INT offset;
1784 switch (GET_CODE (x))
1788 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1789 || !mips_split_p[symbol_type])
1796 /* Unsigned 8-bit constants can be loaded using an unextended
1797 LI instruction. Unsigned 16-bit constants can be loaded
1798 using an extended LI. Negative constants must be loaded
1799 using LI and then negated. */
1800 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1801 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1802 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1803 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1806 return mips_build_integer (codes, INTVAL (x));
1810 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1816 /* See if we can refer to X directly. */
1817 if (mips_symbolic_constant_p (x, &symbol_type))
1818 return mips_symbol_insns (symbol_type);
1820 /* Otherwise try splitting the constant into a base and offset.
1821 16-bit offsets can be added using an extra addiu. Larger offsets
1822 must be calculated separately and then added to the base. */
1823 mips_split_const (x, &x, &offset);
1826 int n = mips_const_insns (x);
1829 if (SMALL_OPERAND (offset))
1832 return n + 1 + mips_build_integer (codes, offset);
1839 return mips_symbol_insns (mips_classify_symbol (x));
1847 /* Return the number of instructions needed for memory reference X.
1848 Count extended mips16 instructions as two instructions. */
1851 mips_fetch_insns (rtx x)
1853 gcc_assert (MEM_P (x));
1854 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1858 /* Return the number of instructions needed for an integer division. */
1861 mips_idiv_insns (void)
1866 if (TARGET_CHECK_ZERO_DIV)
1868 if (GENERATE_DIVIDE_TRAPS)
1874 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1879 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1880 returns a nonzero value if X is a legitimate address for a memory
1881 operand of the indicated MODE. STRICT is nonzero if this function
1882 is called during reload. */
1885 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1887 struct mips_address_info addr;
1889 return mips_classify_address (&addr, x, mode, strict);
1893 /* Copy VALUE to a register and return that register. If new psuedos
1894 are allowed, copy it into a new register, otherwise use DEST. */
1897 mips_force_temporary (rtx dest, rtx value)
1899 if (!no_new_pseudos)
1900 return force_reg (Pmode, value);
1903 emit_move_insn (copy_rtx (dest), value);
1909 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1910 and is used to load the high part into a register. */
1913 mips_split_symbol (rtx temp, rtx addr)
1918 high = mips16_gp_pseudo_reg ();
1920 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1921 return gen_rtx_LO_SUM (Pmode, high, addr);
1925 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1926 type SYMBOL_TYPE. */
1929 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1932 HOST_WIDE_INT offset;
1934 mips_split_const (address, &base, &offset);
1935 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1936 UNSPEC_ADDRESS_FIRST + symbol_type);
1937 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1941 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1942 high part to BASE and return the result. Just return BASE otherwise.
1943 TEMP is available as a temporary register if needed.
1945 The returned expression can be used as the first operand to a LO_SUM. */
1948 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1949 enum mips_symbol_type symbol_type)
1951 if (mips_split_p[symbol_type])
1953 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1954 addr = mips_force_temporary (temp, addr);
1955 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1961 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1962 mips_force_temporary; it is only needed when OFFSET is not a
1966 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1968 if (!SMALL_OPERAND (offset))
1973 /* Load the full offset into a register so that we can use
1974 an unextended instruction for the address itself. */
1975 high = GEN_INT (offset);
1980 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1981 high = GEN_INT (CONST_HIGH_PART (offset));
1982 offset = CONST_LOW_PART (offset);
1984 high = mips_force_temporary (temp, high);
1985 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1987 return plus_constant (reg, offset);
1990 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1991 referencing, and TYPE is the symbol type to use (either global
1992 dynamic or local dynamic). V0 is an RTX for the return value
1993 location. The entire insn sequence is returned. */
1995 static GTY(()) rtx mips_tls_symbol;
1998 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2000 rtx insn, loc, tga, a0;
2002 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2004 if (!mips_tls_symbol)
2005 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2007 loc = mips_unspec_address (sym, type);
2011 emit_insn (gen_rtx_SET (Pmode, a0,
2012 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2013 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2014 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2015 CONST_OR_PURE_CALL_P (insn) = 1;
2016 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2017 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2018 insn = get_insns ();
2025 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2026 return value will be a valid address and move_operand (either a REG
2030 mips_legitimize_tls_address (rtx loc)
2032 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2033 enum tls_model model;
2035 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2036 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2038 model = SYMBOL_REF_TLS_MODEL (loc);
2039 /* Only TARGET_ABICALLS code can have more than one module; other
2040 code must be be static and should not use a GOT. All TLS models
2041 reduce to local exec in this situation. */
2042 if (!TARGET_ABICALLS)
2043 model = TLS_MODEL_LOCAL_EXEC;
2047 case TLS_MODEL_GLOBAL_DYNAMIC:
2048 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2049 dest = gen_reg_rtx (Pmode);
2050 emit_libcall_block (insn, dest, v0, loc);
2053 case TLS_MODEL_LOCAL_DYNAMIC:
2054 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2055 tmp1 = gen_reg_rtx (Pmode);
2057 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2058 share the LDM result with other LD model accesses. */
2059 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2061 emit_libcall_block (insn, tmp1, v0, eqv);
2063 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2064 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2065 mips_unspec_address (loc, SYMBOL_DTPREL));
2068 case TLS_MODEL_INITIAL_EXEC:
2069 tmp1 = gen_reg_rtx (Pmode);
2070 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2071 if (Pmode == DImode)
2073 emit_insn (gen_tls_get_tp_di (v1));
2074 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2078 emit_insn (gen_tls_get_tp_si (v1));
2079 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2081 dest = gen_reg_rtx (Pmode);
2082 emit_insn (gen_add3_insn (dest, tmp1, v1));
2085 case TLS_MODEL_LOCAL_EXEC:
2086 if (Pmode == DImode)
2087 emit_insn (gen_tls_get_tp_di (v1));
2089 emit_insn (gen_tls_get_tp_si (v1));
2091 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2092 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2093 mips_unspec_address (loc, SYMBOL_TPREL));
2103 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2104 be legitimized in a way that the generic machinery might not expect,
2105 put the new address in *XLOC and return true. MODE is the mode of
2106 the memory being accessed. */
2109 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2111 enum mips_symbol_type symbol_type;
2113 if (mips_tls_operand_p (*xloc))
2115 *xloc = mips_legitimize_tls_address (*xloc);
2119 /* See if the address can split into a high part and a LO_SUM. */
2120 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2121 && mips_symbolic_address_p (symbol_type, mode)
2122 && mips_split_p[symbol_type])
2124 *xloc = mips_split_symbol (0, *xloc);
2128 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2130 /* Handle REG + CONSTANT using mips_add_offset. */
2133 reg = XEXP (*xloc, 0);
2134 if (!mips_valid_base_register_p (reg, mode, 0))
2135 reg = copy_to_mode_reg (Pmode, reg);
2136 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2144 /* Subroutine of mips_build_integer (with the same interface).
2145 Assume that the final action in the sequence should be a left shift. */
2148 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2150 unsigned int i, shift;
2152 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2153 since signed numbers are easier to load than unsigned ones. */
2155 while ((value & 1) == 0)
2156 value /= 2, shift++;
2158 i = mips_build_integer (codes, value);
2159 codes[i].code = ASHIFT;
2160 codes[i].value = shift;
2165 /* As for mips_build_shift, but assume that the final action will be
2166 an IOR or PLUS operation. */
2169 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2171 unsigned HOST_WIDE_INT high;
2174 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2175 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2177 /* The constant is too complex to load with a simple lui/ori pair
2178 so our goal is to clear as many trailing zeros as possible.
2179 In this case, we know bit 16 is set and that the low 16 bits
2180 form a negative number. If we subtract that number from VALUE,
2181 we will clear at least the lowest 17 bits, maybe more. */
2182 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2183 codes[i].code = PLUS;
2184 codes[i].value = CONST_LOW_PART (value);
2188 i = mips_build_integer (codes, high);
2189 codes[i].code = IOR;
2190 codes[i].value = value & 0xffff;
2196 /* Fill CODES with a sequence of rtl operations to load VALUE.
2197 Return the number of operations needed. */
2200 mips_build_integer (struct mips_integer_op *codes,
2201 unsigned HOST_WIDE_INT value)
2203 if (SMALL_OPERAND (value)
2204 || SMALL_OPERAND_UNSIGNED (value)
2205 || LUI_OPERAND (value))
2207 /* The value can be loaded with a single instruction. */
2208 codes[0].code = UNKNOWN;
2209 codes[0].value = value;
2212 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2214 /* Either the constant is a simple LUI/ORI combination or its
2215 lowest bit is set. We don't want to shift in this case. */
2216 return mips_build_lower (codes, value);
2218 else if ((value & 0xffff) == 0)
2220 /* The constant will need at least three actions. The lowest
2221 16 bits are clear, so the final action will be a shift. */
2222 return mips_build_shift (codes, value);
2226 /* The final action could be a shift, add or inclusive OR.
2227 Rather than use a complex condition to select the best
2228 approach, try both mips_build_shift and mips_build_lower
2229 and pick the one that gives the shortest sequence.
2230 Note that this case is only used once per constant. */
2231 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2232 unsigned int cost, alt_cost;
2234 cost = mips_build_shift (codes, value);
2235 alt_cost = mips_build_lower (alt_codes, value);
2236 if (alt_cost < cost)
2238 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2246 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2249 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2251 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2252 enum machine_mode mode;
2253 unsigned int i, cost;
2256 mode = GET_MODE (dest);
2257 cost = mips_build_integer (codes, value);
2259 /* Apply each binary operation to X. Invariant: X is a legitimate
2260 source operand for a SET pattern. */
2261 x = GEN_INT (codes[0].value);
2262 for (i = 1; i < cost; i++)
2266 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2270 x = force_reg (mode, x);
2271 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2274 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2278 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2279 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2283 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2286 HOST_WIDE_INT offset;
2288 /* Split moves of big integers into smaller pieces. */
2289 if (splittable_const_int_operand (src, mode))
2291 mips_move_integer (dest, dest, INTVAL (src));
2295 /* Split moves of symbolic constants into high/low pairs. */
2296 if (splittable_symbolic_operand (src, mode))
2298 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2302 if (mips_tls_operand_p (src))
2304 emit_move_insn (dest, mips_legitimize_tls_address (src));
2308 /* If we have (const (plus symbol offset)), load the symbol first
2309 and then add in the offset. This is usually better than forcing
2310 the constant into memory, at least in non-mips16 code. */
2311 mips_split_const (src, &base, &offset);
2314 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2316 base = mips_force_temporary (dest, base);
2317 emit_move_insn (dest, mips_add_offset (0, base, offset));
2321 src = force_const_mem (mode, src);
2323 /* When using explicit relocs, constant pool references are sometimes
2324 not legitimate addresses. */
2325 if (!memory_operand (src, VOIDmode))
2326 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2327 emit_move_insn (dest, src);
2331 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2332 sequence that is valid. */
2335 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2337 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2339 emit_move_insn (dest, force_reg (mode, src));
2343 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2344 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2345 && REG_P (src) && MD_REG_P (REGNO (src))
2346 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2348 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2349 if (GET_MODE_SIZE (mode) <= 4)
2350 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2351 gen_rtx_REG (SImode, REGNO (src)),
2352 gen_rtx_REG (SImode, other_regno)));
2354 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2355 gen_rtx_REG (DImode, REGNO (src)),
2356 gen_rtx_REG (DImode, other_regno)));
2360 /* We need to deal with constants that would be legitimate
2361 immediate_operands but not legitimate move_operands. */
2362 if (CONSTANT_P (src) && !move_operand (src, mode))
2364 mips_legitimize_const_move (mode, dest, src);
2365 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2371 /* We need a lot of little routines to check constant values on the
2372 mips16. These are used to figure out how long the instruction will
2373 be. It would be much better to do this using constraints, but
2374 there aren't nearly enough letters available. */
2377 m16_check_op (rtx op, int low, int high, int mask)
2379 return (GET_CODE (op) == CONST_INT
2380 && INTVAL (op) >= low
2381 && INTVAL (op) <= high
2382 && (INTVAL (op) & mask) == 0);
2386 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2388 return m16_check_op (op, 0x1, 0x8, 0);
2392 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2394 return m16_check_op (op, - 0x8, 0x7, 0);
2398 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2400 return m16_check_op (op, - 0x7, 0x8, 0);
2404 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2406 return m16_check_op (op, - 0x10, 0xf, 0);
2410 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2412 return m16_check_op (op, - 0xf, 0x10, 0);
2416 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2418 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2422 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2424 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2428 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2430 return m16_check_op (op, - 0x80, 0x7f, 0);
2434 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2436 return m16_check_op (op, - 0x7f, 0x80, 0);
2440 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2442 return m16_check_op (op, 0x0, 0xff, 0);
2446 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2448 return m16_check_op (op, - 0xff, 0x0, 0);
2452 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2454 return m16_check_op (op, - 0x1, 0xfe, 0);
2458 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2460 return m16_check_op (op, 0x0, 0xff << 2, 3);
2464 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2466 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2470 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2472 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2476 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2478 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2482 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2484 enum machine_mode mode = GET_MODE (x);
2485 bool float_mode_p = FLOAT_MODE_P (mode);
2492 /* A number between 1 and 8 inclusive is efficient for a shift.
2493 Otherwise, we will need an extended instruction. */
2494 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2495 || (outer_code) == LSHIFTRT)
2497 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2500 *total = COSTS_N_INSNS (1);
2504 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2505 if ((outer_code) == XOR
2506 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2512 /* We may be able to use slt or sltu for a comparison with a
2513 signed 16 bit value. (The boundary conditions aren't quite
2514 right, but this is just a heuristic anyhow.) */
2515 if (((outer_code) == LT || (outer_code) == LE
2516 || (outer_code) == GE || (outer_code) == GT
2517 || (outer_code) == LTU || (outer_code) == LEU
2518 || (outer_code) == GEU || (outer_code) == GTU)
2519 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2525 /* Equality comparisons with 0 are cheap. */
2526 if (((outer_code) == EQ || (outer_code) == NE)
2533 /* Constants in the range 0...255 can be loaded with an unextended
2534 instruction. They are therefore as cheap as a register move.
2536 Given the choice between "li R1,0...255" and "move R1,R2"
2537 (where R2 is a known constant), it is usually better to use "li",
2538 since we do not want to unnecessarily extend the lifetime
2540 if (outer_code == SET
2542 && INTVAL (x) < 256)
2550 /* These can be used anywhere. */
2555 /* Otherwise fall through to the handling below because
2556 we'll need to construct the constant. */
2562 if (LEGITIMATE_CONSTANT_P (x))
2564 *total = COSTS_N_INSNS (1);
2569 /* The value will need to be fetched from the constant pool. */
2570 *total = CONSTANT_POOL_COST;
2576 /* If the address is legitimate, return the number of
2577 instructions it needs, otherwise use the default handling. */
2578 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2581 *total = COSTS_N_INSNS (n + 1);
2588 *total = COSTS_N_INSNS (6);
2592 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2598 if (mode == DImode && !TARGET_64BIT)
2600 *total = COSTS_N_INSNS (2);
2608 if (mode == DImode && !TARGET_64BIT)
2610 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2618 *total = COSTS_N_INSNS (1);
2620 *total = COSTS_N_INSNS (4);
2624 *total = COSTS_N_INSNS (1);
2631 *total = mips_cost->fp_add;
2635 else if (mode == DImode && !TARGET_64BIT)
2637 *total = COSTS_N_INSNS (4);
2643 if (mode == DImode && !TARGET_64BIT)
2645 *total = COSTS_N_INSNS (4);
2652 *total = mips_cost->fp_mult_sf;
2654 else if (mode == DFmode)
2655 *total = mips_cost->fp_mult_df;
2657 else if (mode == SImode)
2658 *total = mips_cost->int_mult_si;
2661 *total = mips_cost->int_mult_di;
2670 *total = mips_cost->fp_div_sf;
2672 *total = mips_cost->fp_div_df;
2681 *total = mips_cost->int_div_di;
2683 *total = mips_cost->int_div_si;
2688 /* A sign extend from SImode to DImode in 64 bit mode is often
2689 zero instructions, because the result can often be used
2690 directly by another instruction; we'll call it one. */
2691 if (TARGET_64BIT && mode == DImode
2692 && GET_MODE (XEXP (x, 0)) == SImode)
2693 *total = COSTS_N_INSNS (1);
2695 *total = COSTS_N_INSNS (2);
2699 if (TARGET_64BIT && mode == DImode
2700 && GET_MODE (XEXP (x, 0)) == SImode)
2701 *total = COSTS_N_INSNS (2);
2703 *total = COSTS_N_INSNS (1);
2707 case UNSIGNED_FLOAT:
2710 case FLOAT_TRUNCATE:
2712 *total = mips_cost->fp_add;
2720 /* Provide the costs of an addressing mode that contains ADDR.
2721 If ADDR is not a valid address, its cost is irrelevant. */
2724 mips_address_cost (rtx addr)
2726 return mips_address_insns (addr, SImode);
2729 /* Return one word of double-word value OP, taking into account the fixed
2730 endianness of certain registers. HIGH_P is true to select the high part,
2731 false to select the low part. */
2734 mips_subword (rtx op, int high_p)
2737 enum machine_mode mode;
2739 mode = GET_MODE (op);
2740 if (mode == VOIDmode)
2743 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2744 byte = UNITS_PER_WORD;
2750 if (FP_REG_P (REGNO (op)))
2751 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2752 if (ACC_HI_REG_P (REGNO (op)))
2753 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2757 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2759 return simplify_gen_subreg (word_mode, op, mode, byte);
2763 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2766 mips_split_64bit_move_p (rtx dest, rtx src)
2771 /* FP->FP moves can be done in a single instruction. */
2772 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2775 /* Check for floating-point loads and stores. They can be done using
2776 ldc1 and sdc1 on MIPS II and above. */
2779 if (FP_REG_RTX_P (dest) && MEM_P (src))
2781 if (FP_REG_RTX_P (src) && MEM_P (dest))
2788 /* Split a 64-bit move from SRC to DEST assuming that
2789 mips_split_64bit_move_p holds.
2791 Moves into and out of FPRs cause some difficulty here. Such moves
2792 will always be DFmode, since paired FPRs are not allowed to store
2793 DImode values. The most natural representation would be two separate
2794 32-bit moves, such as:
2796 (set (reg:SI $f0) (mem:SI ...))
2797 (set (reg:SI $f1) (mem:SI ...))
2799 However, the second insn is invalid because odd-numbered FPRs are
2800 not allowed to store independent values. Use the patterns load_df_low,
2801 load_df_high and store_df_high instead. */
2804 mips_split_64bit_move (rtx dest, rtx src)
2806 if (FP_REG_RTX_P (dest))
2808 /* Loading an FPR from memory or from GPRs. */
2809 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2810 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2813 else if (FP_REG_RTX_P (src))
2815 /* Storing an FPR into memory or GPRs. */
2816 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2817 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2821 /* The operation can be split into two normal moves. Decide in
2822 which order to do them. */
2825 low_dest = mips_subword (dest, 0);
2826 if (REG_P (low_dest)
2827 && reg_overlap_mentioned_p (low_dest, src))
2829 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2830 emit_move_insn (low_dest, mips_subword (src, 0));
2834 emit_move_insn (low_dest, mips_subword (src, 0));
2835 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2840 /* Return the appropriate instructions to move SRC into DEST. Assume
2841 that SRC is operand 1 and DEST is operand 0. */
2844 mips_output_move (rtx dest, rtx src)
2846 enum rtx_code dest_code, src_code;
2849 dest_code = GET_CODE (dest);
2850 src_code = GET_CODE (src);
2851 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2853 if (dbl_p && mips_split_64bit_move_p (dest, src))
2856 if ((src_code == REG && GP_REG_P (REGNO (src)))
2857 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2859 if (dest_code == REG)
2861 if (GP_REG_P (REGNO (dest)))
2862 return "move\t%0,%z1";
2864 if (MD_REG_P (REGNO (dest)))
2867 if (DSP_ACC_REG_P (REGNO (dest)))
2869 static char retval[] = "mt__\t%z1,%q0";
2870 retval[2] = reg_names[REGNO (dest)][4];
2871 retval[3] = reg_names[REGNO (dest)][5];
2875 if (FP_REG_P (REGNO (dest)))
2876 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2878 if (ALL_COP_REG_P (REGNO (dest)))
2880 static char retval[] = "dmtc_\t%z1,%0";
2882 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2883 return (dbl_p ? retval : retval + 1);
2886 if (dest_code == MEM)
2887 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2889 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2891 if (src_code == REG)
2893 if (DSP_ACC_REG_P (REGNO (src)))
2895 static char retval[] = "mf__\t%0,%q1";
2896 retval[2] = reg_names[REGNO (src)][4];
2897 retval[3] = reg_names[REGNO (src)][5];
2901 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2902 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2904 if (FP_REG_P (REGNO (src)))
2905 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2907 if (ALL_COP_REG_P (REGNO (src)))
2909 static char retval[] = "dmfc_\t%0,%1";
2911 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2912 return (dbl_p ? retval : retval + 1);
2916 if (src_code == MEM)
2917 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2919 if (src_code == CONST_INT)
2921 /* Don't use the X format, because that will give out of
2922 range numbers for 64 bit hosts and 32 bit targets. */
2924 return "li\t%0,%1\t\t\t# %X1";
2926 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2929 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2933 if (src_code == HIGH)
2934 return "lui\t%0,%h1";
2936 if (CONST_GP_P (src))
2937 return "move\t%0,%1";
2939 if (symbolic_operand (src, VOIDmode))
2940 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2942 if (src_code == REG && FP_REG_P (REGNO (src)))
2944 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2946 if (GET_MODE (dest) == V2SFmode)
2947 return "mov.ps\t%0,%1";
2949 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2952 if (dest_code == MEM)
2953 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2955 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2957 if (src_code == MEM)
2958 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2960 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2962 static char retval[] = "l_c_\t%0,%1";
2964 retval[1] = (dbl_p ? 'd' : 'w');
2965 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2968 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2970 static char retval[] = "s_c_\t%1,%0";
2972 retval[1] = (dbl_p ? 'd' : 'w');
2973 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2979 /* Restore $gp from its save slot. Valid only when using o32 or
2983 mips_restore_gp (void)
2987 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2989 address = mips_add_offset (pic_offset_table_rtx,
2990 frame_pointer_needed
2991 ? hard_frame_pointer_rtx
2992 : stack_pointer_rtx,
2993 current_function_outgoing_args_size);
2994 slot = gen_rtx_MEM (Pmode, address);
2996 emit_move_insn (pic_offset_table_rtx, slot);
2997 if (!TARGET_EXPLICIT_RELOCS)
2998 emit_insn (gen_blockage ());
3001 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3004 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
3006 emit_insn (gen_rtx_SET (VOIDmode, target,
3007 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
3010 /* Return true if CMP1 is a suitable second operand for relational
3011 operator CODE. See also the *sCC patterns in mips.md. */
3014 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3020 return reg_or_0_operand (cmp1, VOIDmode);
3024 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3028 return arith_operand (cmp1, VOIDmode);
3031 return sle_operand (cmp1, VOIDmode);
3034 return sleu_operand (cmp1, VOIDmode);
3041 /* Canonicalize LE or LEU comparisons into LT comparisons when
3042 possible to avoid extra instructions or inverting the
3046 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3047 enum machine_mode mode)
3049 HOST_WIDE_INT original, plus_one;
3051 if (GET_CODE (*cmp1) != CONST_INT)
3054 original = INTVAL (*cmp1);
3055 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3060 if (original < plus_one)
3063 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3072 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3085 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3086 result in TARGET. CMP0 and TARGET are register_operands that have
3087 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3088 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3091 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3092 rtx target, rtx cmp0, rtx cmp1)
3094 /* First see if there is a MIPS instruction that can do this operation
3095 with CMP1 in its current form. If not, try to canonicalize the
3096 comparison to LT. If that fails, try doing the same for the
3097 inverse operation. If that also fails, force CMP1 into a register
3099 if (mips_relational_operand_ok_p (code, cmp1))
3100 mips_emit_binary (code, target, cmp0, cmp1);
3101 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3102 mips_emit_binary (code, target, cmp0, cmp1);
3105 enum rtx_code inv_code = reverse_condition (code);
3106 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3108 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3109 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3111 else if (invert_ptr == 0)
3113 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3114 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3115 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3119 *invert_ptr = !*invert_ptr;
3120 mips_emit_binary (inv_code, target, cmp0, cmp1);
3125 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3126 The register will have the same mode as CMP0. */
3129 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3131 if (cmp1 == const0_rtx)
3134 if (uns_arith_operand (cmp1, VOIDmode))
3135 return expand_binop (GET_MODE (cmp0), xor_optab,
3136 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3138 return expand_binop (GET_MODE (cmp0), sub_optab,
3139 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3142 /* Convert *CODE into a code that can be used in a floating-point
3143 scc instruction (c.<cond>.<fmt>). Return true if the values of
3144 the condition code registers will be inverted, with 0 indicating
3145 that the condition holds. */
3148 mips_reverse_fp_cond_p (enum rtx_code *code)
3155 *code = reverse_condition_maybe_unordered (*code);
3163 /* Convert a comparison into something that can be used in a branch or
3164 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3165 being compared and *CODE is the code used to compare them.
3167 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3168 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3169 otherwise any standard branch condition can be used. The standard branch
3172 - EQ/NE between two registers.
3173 - any comparison between a register and zero. */
3176 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3178 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3180 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3182 *op0 = cmp_operands[0];
3183 *op1 = cmp_operands[1];
3185 else if (*code == EQ || *code == NE)
3189 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3194 *op0 = cmp_operands[0];
3195 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3200 /* The comparison needs a separate scc instruction. Store the
3201 result of the scc in *OP0 and compare it against zero. */
3202 bool invert = false;
3203 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3205 mips_emit_int_relational (*code, &invert, *op0,
3206 cmp_operands[0], cmp_operands[1]);
3207 *code = (invert ? EQ : NE);
3212 enum rtx_code cmp_code;
3214 /* Floating-point tests use a separate c.cond.fmt comparison to
3215 set a condition code register. The branch or conditional move
3216 will then compare that register against zero.
3218 Set CMP_CODE to the code of the comparison instruction and
3219 *CODE to the code that the branch or move should use. */
3221 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3223 ? gen_reg_rtx (CCmode)
3224 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3226 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3230 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3231 Store the result in TARGET and return true if successful.
3233 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3236 mips_emit_scc (enum rtx_code code, rtx target)
3238 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3241 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3242 if (code == EQ || code == NE)
3244 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3245 mips_emit_binary (code, target, zie, const0_rtx);
3248 mips_emit_int_relational (code, 0, target,
3249 cmp_operands[0], cmp_operands[1]);
3253 /* Emit the common code for doing conditional branches.
3254 operand[0] is the label to jump to.
3255 The comparison operands are saved away by cmp{si,di,sf,df}. */
3258 gen_conditional_branch (rtx *operands, enum rtx_code code)
3260 rtx op0, op1, condition;
3262 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3263 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3264 emit_jump_insn (gen_condjump (condition, operands[0]));
3269 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3270 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3273 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3274 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3279 reversed_p = mips_reverse_fp_cond_p (&cond);
3280 cmp_result = gen_reg_rtx (CCV2mode);
3281 emit_insn (gen_scc_ps (cmp_result,
3282 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3284 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3287 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3291 /* Emit the common code for conditional moves. OPERANDS is the array
3292 of operands passed to the conditional move define_expand. */
3295 gen_conditional_move (rtx *operands)
3300 code = GET_CODE (operands[1]);
3301 mips_emit_compare (&code, &op0, &op1, true);
3302 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3303 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3304 gen_rtx_fmt_ee (code,
3307 operands[2], operands[3])));
3310 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3311 the conditional_trap expander. */
3314 mips_gen_conditional_trap (rtx *operands)
3317 enum rtx_code cmp_code = GET_CODE (operands[0]);
3318 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3320 /* MIPS conditional trap machine instructions don't have GT or LE
3321 flavors, so we must invert the comparison and convert to LT and
3322 GE, respectively. */
3325 case GT: cmp_code = LT; break;
3326 case LE: cmp_code = GE; break;
3327 case GTU: cmp_code = LTU; break;
3328 case LEU: cmp_code = GEU; break;
3331 if (cmp_code == GET_CODE (operands[0]))
3333 op0 = cmp_operands[0];
3334 op1 = cmp_operands[1];
3338 op0 = cmp_operands[1];
3339 op1 = cmp_operands[0];
3341 op0 = force_reg (mode, op0);
3342 if (!arith_operand (op1, mode))
3343 op1 = force_reg (mode, op1);
3345 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3346 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3350 /* Load function address ADDR into register DEST. SIBCALL_P is true
3351 if the address is needed for a sibling call. */
3354 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3356 /* If we're generating PIC, and this call is to a global function,
3357 try to allow its address to be resolved lazily. This isn't
3358 possible for NewABI sibcalls since the value of $gp on entry
3359 to the stub would be our caller's gp, not ours. */
3360 if (TARGET_EXPLICIT_RELOCS
3361 && !(sibcall_p && TARGET_NEWABI)
3362 && global_got_operand (addr, VOIDmode))
3364 rtx high, lo_sum_symbol;
3366 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3367 addr, SYMBOL_GOTOFF_CALL);
3368 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3369 if (Pmode == SImode)
3370 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3372 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3375 emit_move_insn (dest, addr);
3379 /* Expand a call or call_value instruction. RESULT is where the
3380 result will go (null for calls), ADDR is the address of the
3381 function, ARGS_SIZE is the size of the arguments and AUX is
3382 the value passed to us by mips_function_arg. SIBCALL_P is true
3383 if we are expanding a sibling call, false if we're expanding
3387 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3389 rtx orig_addr, pattern, insn;
3392 if (!call_insn_operand (addr, VOIDmode))
3394 addr = gen_reg_rtx (Pmode);
3395 mips_load_call_address (addr, orig_addr, sibcall_p);
3399 && mips16_hard_float
3400 && build_mips16_call_stub (result, addr, args_size,
3401 aux == 0 ? 0 : (int) GET_MODE (aux)))
3405 pattern = (sibcall_p
3406 ? gen_sibcall_internal (addr, args_size)
3407 : gen_call_internal (addr, args_size));
3408 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3412 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3413 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3416 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3417 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3420 pattern = (sibcall_p
3421 ? gen_sibcall_value_internal (result, addr, args_size)
3422 : gen_call_value_internal (result, addr, args_size));
3424 insn = emit_call_insn (pattern);
3426 /* Lazy-binding stubs require $gp to be valid on entry. */
3427 if (global_got_operand (orig_addr, VOIDmode))
3428 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3432 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3435 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3436 tree exp ATTRIBUTE_UNUSED)
3438 return TARGET_SIBCALLS;
3441 /* Emit code to move general operand SRC into condition-code
3442 register DEST. SCRATCH is a scratch TFmode float register.
3449 where FP1 and FP2 are single-precision float registers
3450 taken from SCRATCH. */
3453 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3457 /* Change the source to SFmode. */
3459 src = adjust_address (src, SFmode, 0);
3460 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3461 src = gen_rtx_REG (SFmode, true_regnum (src));
3463 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3464 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3466 emit_move_insn (copy_rtx (fp1), src);
3467 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3468 emit_insn (gen_slt_sf (dest, fp2, fp1));
3471 /* Emit code to change the current function's return address to
3472 ADDRESS. SCRATCH is available as a scratch register, if needed.
3473 ADDRESS and SCRATCH are both word-mode GPRs. */
3476 mips_set_return_address (rtx address, rtx scratch)
3480 compute_frame_size (get_frame_size ());
3481 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3482 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3483 cfun->machine->frame.gp_sp_offset);
3485 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3488 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3489 Assume that the areas do not overlap. */
3492 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3494 HOST_WIDE_INT offset, delta;
3495 unsigned HOST_WIDE_INT bits;
3497 enum machine_mode mode;
3500 /* Work out how many bits to move at a time. If both operands have
3501 half-word alignment, it is usually better to move in half words.
3502 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3503 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3504 Otherwise move word-sized chunks. */
3505 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3506 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3507 bits = BITS_PER_WORD / 2;
3509 bits = BITS_PER_WORD;
3511 mode = mode_for_size (bits, MODE_INT, 0);
3512 delta = bits / BITS_PER_UNIT;
3514 /* Allocate a buffer for the temporary registers. */
3515 regs = alloca (sizeof (rtx) * length / delta);
3517 /* Load as many BITS-sized chunks as possible. Use a normal load if
3518 the source has enough alignment, otherwise use left/right pairs. */
3519 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3521 regs[i] = gen_reg_rtx (mode);
3522 if (MEM_ALIGN (src) >= bits)
3523 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3526 rtx part = adjust_address (src, BLKmode, offset);
3527 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3532 /* Copy the chunks to the destination. */
3533 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3534 if (MEM_ALIGN (dest) >= bits)
3535 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3538 rtx part = adjust_address (dest, BLKmode, offset);
3539 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3543 /* Mop up any left-over bytes. */
3544 if (offset < length)
3546 src = adjust_address (src, BLKmode, offset);
3547 dest = adjust_address (dest, BLKmode, offset);
3548 move_by_pieces (dest, src, length - offset,
3549 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3553 #define MAX_MOVE_REGS 4
3554 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3557 /* Helper function for doing a loop-based block operation on memory
3558 reference MEM. Each iteration of the loop will operate on LENGTH
3561 Create a new base register for use within the loop and point it to
3562 the start of MEM. Create a new memory reference that uses this
3563 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3566 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3567 rtx *loop_reg, rtx *loop_mem)
3569 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3571 /* Although the new mem does not refer to a known location,
3572 it does keep up to LENGTH bytes of alignment. */
3573 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3574 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3578 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3579 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3580 memory regions do not overlap. */
3583 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3585 rtx label, src_reg, dest_reg, final_src;
3586 HOST_WIDE_INT leftover;
3588 leftover = length % MAX_MOVE_BYTES;
3591 /* Create registers and memory references for use within the loop. */
3592 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3593 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3595 /* Calculate the value that SRC_REG should have after the last iteration
3597 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3600 /* Emit the start of the loop. */
3601 label = gen_label_rtx ();
3604 /* Emit the loop body. */
3605 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3607 /* Move on to the next block. */
3608 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3609 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3611 /* Emit the loop condition. */
3612 if (Pmode == DImode)
3613 emit_insn (gen_cmpdi (src_reg, final_src));
3615 emit_insn (gen_cmpsi (src_reg, final_src));
3616 emit_jump_insn (gen_bne (label));
3618 /* Mop up any left-over bytes. */
3620 mips_block_move_straight (dest, src, leftover);
3623 /* Expand a movmemsi instruction. */
3626 mips_expand_block_move (rtx dest, rtx src, rtx length)
3628 if (GET_CODE (length) == CONST_INT)
3630 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3632 mips_block_move_straight (dest, src, INTVAL (length));
3637 mips_block_move_loop (dest, src, INTVAL (length));
3644 /* Argument support functions. */
3646 /* Initialize CUMULATIVE_ARGS for a function. */
3649 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3650 rtx libname ATTRIBUTE_UNUSED)
3652 static CUMULATIVE_ARGS zero_cum;
3653 tree param, next_param;
3656 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3658 /* Determine if this function has variable arguments. This is
3659 indicated by the last argument being 'void_type_mode' if there
3660 are no variable arguments. The standard MIPS calling sequence
3661 passes all arguments in the general purpose registers in this case. */
3663 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3664 param != 0; param = next_param)
3666 next_param = TREE_CHAIN (param);
3667 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3668 cum->gp_reg_found = 1;
3673 /* Fill INFO with information about a single argument. CUM is the
3674 cumulative state for earlier arguments. MODE is the mode of this
3675 argument and TYPE is its type (if known). NAMED is true if this
3676 is a named (fixed) argument rather than a variable one. */
3679 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3680 tree type, int named, struct mips_arg_info *info)
3682 bool doubleword_aligned_p;
3683 unsigned int num_bytes, num_words, max_regs;
3685 /* Work out the size of the argument. */
3686 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3687 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3689 /* Decide whether it should go in a floating-point register, assuming
3690 one is free. Later code checks for availability.
3692 The checks against UNITS_PER_FPVALUE handle the soft-float and
3693 single-float cases. */
3697 /* The EABI conventions have traditionally been defined in terms
3698 of TYPE_MODE, regardless of the actual type. */
3699 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3700 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3701 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3706 /* Only leading floating-point scalars are passed in
3707 floating-point registers. We also handle vector floats the same
3708 say, which is OK because they are not covered by the standard ABI. */
3709 info->fpr_p = (!cum->gp_reg_found
3710 && cum->arg_number < 2
3711 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3712 || VECTOR_FLOAT_TYPE_P (type))
3713 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3714 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3715 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3720 /* Scalar and complex floating-point types are passed in
3721 floating-point registers. */
3722 info->fpr_p = (named
3723 && (type == 0 || FLOAT_TYPE_P (type))
3724 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3725 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3726 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3727 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3729 /* ??? According to the ABI documentation, the real and imaginary
3730 parts of complex floats should be passed in individual registers.
3731 The real and imaginary parts of stack arguments are supposed
3732 to be contiguous and there should be an extra word of padding
3735 This has two problems. First, it makes it impossible to use a
3736 single "void *" va_list type, since register and stack arguments
3737 are passed differently. (At the time of writing, MIPSpro cannot
3738 handle complex float varargs correctly.) Second, it's unclear
3739 what should happen when there is only one register free.
3741 For now, we assume that named complex floats should go into FPRs
3742 if there are two FPRs free, otherwise they should be passed in the
3743 same way as a struct containing two floats. */
3745 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3746 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3748 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3749 info->fpr_p = false;
3759 /* See whether the argument has doubleword alignment. */
3760 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3762 /* Set REG_OFFSET to the register count we're interested in.
3763 The EABI allocates the floating-point registers separately,
3764 but the other ABIs allocate them like integer registers. */
3765 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3769 /* Advance to an even register if the argument is doubleword-aligned. */
3770 if (doubleword_aligned_p)
3771 info->reg_offset += info->reg_offset & 1;
3773 /* Work out the offset of a stack argument. */
3774 info->stack_offset = cum->stack_words;
3775 if (doubleword_aligned_p)
3776 info->stack_offset += info->stack_offset & 1;
3778 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3780 /* Partition the argument between registers and stack. */
3781 info->reg_words = MIN (num_words, max_regs);
3782 info->stack_words = num_words - info->reg_words;
3786 /* Implement FUNCTION_ARG_ADVANCE. */
3789 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3790 tree type, int named)
3792 struct mips_arg_info info;
3794 mips_arg_info (cum, mode, type, named, &info);
3797 cum->gp_reg_found = true;
3799 /* See the comment above the cumulative args structure in mips.h
3800 for an explanation of what this code does. It assumes the O32
3801 ABI, which passes at most 2 arguments in float registers. */
3802 if (cum->arg_number < 2 && info.fpr_p)
3803 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3805 if (mips_abi != ABI_EABI || !info.fpr_p)
3806 cum->num_gprs = info.reg_offset + info.reg_words;
3807 else if (info.reg_words > 0)
3808 cum->num_fprs += FP_INC;
3810 if (info.stack_words > 0)
3811 cum->stack_words = info.stack_offset + info.stack_words;
3816 /* Implement FUNCTION_ARG. */
3819 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3820 tree type, int named)
3822 struct mips_arg_info info;
3824 /* We will be called with a mode of VOIDmode after the last argument
3825 has been seen. Whatever we return will be passed to the call
3826 insn. If we need a mips16 fp_code, return a REG with the code
3827 stored as the mode. */
3828 if (mode == VOIDmode)
3830 if (TARGET_MIPS16 && cum->fp_code != 0)
3831 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3837 mips_arg_info (cum, mode, type, named, &info);
3839 /* Return straight away if the whole argument is passed on the stack. */
3840 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3844 && TREE_CODE (type) == RECORD_TYPE
3846 && TYPE_SIZE_UNIT (type)
3847 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3850 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3851 structure contains a double in its entirety, then that 64 bit
3852 chunk is passed in a floating point register. */
3855 /* First check to see if there is any such field. */
3856 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3857 if (TREE_CODE (field) == FIELD_DECL
3858 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3859 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3860 && host_integerp (bit_position (field), 0)
3861 && int_bit_position (field) % BITS_PER_WORD == 0)
3866 /* Now handle the special case by returning a PARALLEL
3867 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3868 chunks are passed in registers. */
3870 HOST_WIDE_INT bitpos;
3873 /* assign_parms checks the mode of ENTRY_PARM, so we must
3874 use the actual mode here. */
3875 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3878 field = TYPE_FIELDS (type);
3879 for (i = 0; i < info.reg_words; i++)
3883 for (; field; field = TREE_CHAIN (field))
3884 if (TREE_CODE (field) == FIELD_DECL
3885 && int_bit_position (field) >= bitpos)
3889 && int_bit_position (field) == bitpos
3890 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3891 && !TARGET_SOFT_FLOAT
3892 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3893 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3895 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3898 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3899 GEN_INT (bitpos / BITS_PER_UNIT));
3901 bitpos += BITS_PER_WORD;
3907 /* Handle the n32/n64 conventions for passing complex floating-point
3908 arguments in FPR pairs. The real part goes in the lower register
3909 and the imaginary part goes in the upper register. */
3912 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3915 enum machine_mode inner;
3918 inner = GET_MODE_INNER (mode);
3919 reg = FP_ARG_FIRST + info.reg_offset;
3920 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
3922 /* Real part in registers, imaginary part on stack. */
3923 gcc_assert (info.stack_words == info.reg_words);
3924 return gen_rtx_REG (inner, reg);
3928 gcc_assert (info.stack_words == 0);
3929 real = gen_rtx_EXPR_LIST (VOIDmode,
3930 gen_rtx_REG (inner, reg),
3932 imag = gen_rtx_EXPR_LIST (VOIDmode,
3934 reg + info.reg_words / 2),
3935 GEN_INT (GET_MODE_SIZE (inner)));
3936 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3941 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3942 else if (info.reg_offset == 1)
3943 /* This code handles the special o32 case in which the second word
3944 of the argument structure is passed in floating-point registers. */
3945 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3947 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3951 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3954 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3955 enum machine_mode mode, tree type, bool named)
3957 struct mips_arg_info info;
3959 mips_arg_info (cum, mode, type, named, &info);
3960 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3964 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3965 PARM_BOUNDARY bits of alignment, but will be given anything up
3966 to STACK_BOUNDARY bits if the type requires it. */
3969 function_arg_boundary (enum machine_mode mode, tree type)
3971 unsigned int alignment;
3973 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3974 if (alignment < PARM_BOUNDARY)
3975 alignment = PARM_BOUNDARY;
3976 if (alignment > STACK_BOUNDARY)
3977 alignment = STACK_BOUNDARY;
3981 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3982 upward rather than downward. In other words, return true if the
3983 first byte of the stack slot has useful data, false if the last
3987 mips_pad_arg_upward (enum machine_mode mode, tree type)
3989 /* On little-endian targets, the first byte of every stack argument
3990 is passed in the first byte of the stack slot. */
3991 if (!BYTES_BIG_ENDIAN)
3994 /* Otherwise, integral types are padded downward: the last byte of a
3995 stack argument is passed in the last byte of the stack slot. */
3997 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3998 : GET_MODE_CLASS (mode) == MODE_INT)
4001 /* Big-endian o64 pads floating-point arguments downward. */
4002 if (mips_abi == ABI_O64)
4003 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4006 /* Other types are padded upward for o32, o64, n32 and n64. */
4007 if (mips_abi != ABI_EABI)
4010 /* Arguments smaller than a stack slot are padded downward. */
4011 if (mode != BLKmode)
4012 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4014 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4018 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4019 if the least significant byte of the register has useful data. Return
4020 the opposite if the most significant byte does. */
4023 mips_pad_reg_upward (enum machine_mode mode, tree type)
4025 /* No shifting is required for floating-point arguments. */
4026 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4027 return !BYTES_BIG_ENDIAN;
4029 /* Otherwise, apply the same padding to register arguments as we do
4030 to stack arguments. */
4031 return mips_pad_arg_upward (mode, type);
4035 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4036 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4039 CUMULATIVE_ARGS local_cum;
4040 int gp_saved, fp_saved;
4042 /* The caller has advanced CUM up to, but not beyond, the last named
4043 argument. Advance a local copy of CUM past the last "real" named
4044 argument, to find out how many registers are left over. */
4047 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4049 /* Found out how many registers we need to save. */
4050 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4051 fp_saved = (EABI_FLOAT_VARARGS_P
4052 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4061 ptr = plus_constant (virtual_incoming_args_rtx,
4062 REG_PARM_STACK_SPACE (cfun->decl)
4063 - gp_saved * UNITS_PER_WORD);
4064 mem = gen_rtx_MEM (BLKmode, ptr);
4065 set_mem_alias_set (mem, get_varargs_alias_set ());
4067 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4072 /* We can't use move_block_from_reg, because it will use
4074 enum machine_mode mode;
4077 /* Set OFF to the offset from virtual_incoming_args_rtx of
4078 the first float register. The FP save area lies below
4079 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4080 off = -gp_saved * UNITS_PER_WORD;
4081 off &= ~(UNITS_PER_FPVALUE - 1);
4082 off -= fp_saved * UNITS_PER_FPREG;
4084 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4086 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4090 ptr = plus_constant (virtual_incoming_args_rtx, off);
4091 mem = gen_rtx_MEM (mode, ptr);
4092 set_mem_alias_set (mem, get_varargs_alias_set ());
4093 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4094 off += UNITS_PER_HWFPVALUE;
4098 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4099 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4100 + fp_saved * UNITS_PER_FPREG);
4103 /* Create the va_list data type.
4104 We keep 3 pointers, and two offsets.
4105 Two pointers are to the overflow area, which starts at the CFA.
4106 One of these is constant, for addressing into the GPR save area below it.
4107 The other is advanced up the stack through the overflow region.
4108 The third pointer is to the GPR save area. Since the FPR save area
4109 is just below it, we can address FPR slots off this pointer.
4110 We also keep two one-byte offsets, which are to be subtracted from the
4111 constant pointers to yield addresses in the GPR and FPR save areas.
4112 These are downcounted as float or non-float arguments are used,
4113 and when they get to zero, the argument must be obtained from the
4115 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4116 pointer is enough. It's started at the GPR save area, and is
4118 Note that the GPR save area is not constant size, due to optimization
4119 in the prologue. Hence, we can't use a design with two pointers
4120 and two offsets, although we could have designed this with two pointers
4121 and three offsets. */
4124 mips_build_builtin_va_list (void)
4126 if (EABI_FLOAT_VARARGS_P)
4128 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4131 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4133 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4135 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4137 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4139 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4140 unsigned_char_type_node);
4141 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4142 unsigned_char_type_node);
4143 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4144 warn on every user file. */
4145 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4146 array = build_array_type (unsigned_char_type_node,
4147 build_index_type (index));
4148 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4150 DECL_FIELD_CONTEXT (f_ovfl) = record;
4151 DECL_FIELD_CONTEXT (f_gtop) = record;
4152 DECL_FIELD_CONTEXT (f_ftop) = record;
4153 DECL_FIELD_CONTEXT (f_goff) = record;
4154 DECL_FIELD_CONTEXT (f_foff) = record;
4155 DECL_FIELD_CONTEXT (f_res) = record;
4157 TYPE_FIELDS (record) = f_ovfl;
4158 TREE_CHAIN (f_ovfl) = f_gtop;
4159 TREE_CHAIN (f_gtop) = f_ftop;
4160 TREE_CHAIN (f_ftop) = f_goff;
4161 TREE_CHAIN (f_goff) = f_foff;
4162 TREE_CHAIN (f_foff) = f_res;
4164 layout_type (record);
4167 else if (TARGET_IRIX && TARGET_IRIX6)
4168 /* On IRIX 6, this type is 'char *'. */
4169 return build_pointer_type (char_type_node);
4171 /* Otherwise, we use 'void *'. */
4172 return ptr_type_node;
4175 /* Implement va_start. */
4178 mips_va_start (tree valist, rtx nextarg)
4180 if (EABI_FLOAT_VARARGS_P)
4182 const CUMULATIVE_ARGS *cum;
4183 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4184 tree ovfl, gtop, ftop, goff, foff;
4186 int gpr_save_area_size;
4187 int fpr_save_area_size;
4190 cum = ¤t_function_args_info;
4192 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4194 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4196 f_ovfl = TYPE_FIELDS (va_list_type_node);
4197 f_gtop = TREE_CHAIN (f_ovfl);
4198 f_ftop = TREE_CHAIN (f_gtop);
4199 f_goff = TREE_CHAIN (f_ftop);
4200 f_foff = TREE_CHAIN (f_goff);
4202 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4204 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4206 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4208 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4210 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4213 /* Emit code to initialize OVFL, which points to the next varargs
4214 stack argument. CUM->STACK_WORDS gives the number of stack
4215 words used by named arguments. */
4216 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4217 if (cum->stack_words > 0)
4218 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t,
4219 build_int_cst (NULL_TREE,
4220 cum->stack_words * UNITS_PER_WORD));
4221 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4222 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4224 /* Emit code to initialize GTOP, the top of the GPR save area. */
4225 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4226 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4227 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4229 /* Emit code to initialize FTOP, the top of the FPR save area.
4230 This address is gpr_save_area_bytes below GTOP, rounded
4231 down to the next fp-aligned boundary. */
4232 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4233 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4234 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4236 t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t,
4237 build_int_cst (NULL_TREE, -fpr_offset));
4238 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4239 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4241 /* Emit code to initialize GOFF, the offset from GTOP of the
4242 next GPR argument. */
4243 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
4244 build_int_cst (NULL_TREE, gpr_save_area_size));
4245 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4247 /* Likewise emit code to initialize FOFF, the offset from FTOP
4248 of the next FPR argument. */
4249 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
4250 build_int_cst (NULL_TREE, fpr_save_area_size));
4251 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4255 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4256 std_expand_builtin_va_start (valist, nextarg);
4260 /* Implement va_arg. */
4263 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4265 HOST_WIDE_INT size, rsize;
4269 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4272 type = build_pointer_type (type);
4274 size = int_size_in_bytes (type);
4275 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4277 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4278 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4281 /* Not a simple merged stack. */
4283 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4284 tree ovfl, top, off, align;
4285 HOST_WIDE_INT osize;
4288 f_ovfl = TYPE_FIELDS (va_list_type_node);
4289 f_gtop = TREE_CHAIN (f_ovfl);
4290 f_ftop = TREE_CHAIN (f_gtop);
4291 f_goff = TREE_CHAIN (f_ftop);
4292 f_foff = TREE_CHAIN (f_goff);
4294 /* We maintain separate pointers and offsets for floating-point
4295 and integer arguments, but we need similar code in both cases.
4298 TOP be the top of the register save area;
4299 OFF be the offset from TOP of the next register;
4300 ADDR_RTX be the address of the argument;
4301 RSIZE be the number of bytes used to store the argument
4302 when it's in the register save area;
4303 OSIZE be the number of bytes used to store it when it's
4304 in the stack overflow area; and
4305 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4307 The code we want is:
4309 1: off &= -rsize; // round down
4312 4: addr_rtx = top - off;
4317 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4318 10: addr_rtx = ovfl + PADDING;
4322 [1] and [9] can sometimes be optimized away. */
4324 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4327 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4328 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4330 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4332 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4335 /* When floating-point registers are saved to the stack,
4336 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4337 of the float's precision. */
4338 rsize = UNITS_PER_HWFPVALUE;
4340 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4341 (= PARM_BOUNDARY bits). This can be different from RSIZE
4344 (1) On 32-bit targets when TYPE is a structure such as:
4346 struct s { float f; };
4348 Such structures are passed in paired FPRs, so RSIZE
4349 will be 8 bytes. However, the structure only takes
4350 up 4 bytes of memory, so OSIZE will only be 4.
4352 (2) In combinations such as -mgp64 -msingle-float
4353 -fshort-double. Doubles passed in registers
4354 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4355 but those passed on the stack take up
4356 UNITS_PER_WORD bytes. */
4357 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4361 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4363 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4365 if (rsize > UNITS_PER_WORD)
4367 /* [1] Emit code for: off &= -rsize. */
4368 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4369 build_int_cst (NULL_TREE, -rsize));
4370 t = build2 (MODIFY_EXPR, TREE_TYPE (off), off, t);
4371 gimplify_and_add (t, pre_p);
4376 /* [2] Emit code to branch if off == 0. */
4377 t = build2 (NE_EXPR, boolean_type_node, off,
4378 build_int_cst (TREE_TYPE (off), 0));
4379 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4381 /* [5] Emit code for: off -= rsize. We do this as a form of
4382 post-increment not available to C. Also widen for the
4383 coming pointer arithmetic. */
4384 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4385 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4386 t = fold_convert (sizetype, t);
4387 t = fold_convert (TREE_TYPE (top), t);
4389 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4390 the argument has RSIZE - SIZE bytes of leading padding. */
4391 t = build2 (MINUS_EXPR, TREE_TYPE (top), top, t);
4392 if (BYTES_BIG_ENDIAN && rsize > size)
4394 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4396 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4398 COND_EXPR_THEN (addr) = t;
4400 if (osize > UNITS_PER_WORD)
4402 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4403 u = fold_convert (TREE_TYPE (ovfl),
4404 build_int_cst (NULL_TREE, osize - 1));
4405 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4406 u = fold_convert (TREE_TYPE (ovfl),
4407 build_int_cst (NULL_TREE, -osize));
4408 t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4409 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4414 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4415 post-increment ovfl by osize. On big-endian machines,
4416 the argument has OSIZE - SIZE bytes of leading padding. */
4417 u = fold_convert (TREE_TYPE (ovfl),
4418 build_int_cst (NULL_TREE, osize));
4419 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4420 if (BYTES_BIG_ENDIAN && osize > size)
4422 u = fold_convert (TREE_TYPE (t),
4423 build_int_cst (NULL_TREE, osize - size));
4424 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4427 /* String [9] and [10,11] together. */
4429 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4430 COND_EXPR_ELSE (addr) = t;
4432 addr = fold_convert (build_pointer_type (type), addr);
4433 addr = build_va_arg_indirect_ref (addr);
4437 addr = build_va_arg_indirect_ref (addr);
4442 /* Return true if it is possible to use left/right accesses for a
4443 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4444 returning true, update *OP, *LEFT and *RIGHT as follows:
4446 *OP is a BLKmode reference to the whole field.
4448 *LEFT is a QImode reference to the first byte if big endian or
4449 the last byte if little endian. This address can be used in the
4450 left-side instructions (lwl, swl, ldl, sdl).
4452 *RIGHT is a QImode reference to the opposite end of the field and
4453 can be used in the patterning right-side instruction. */
4456 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4457 rtx *left, rtx *right)
4461 /* Check that the operand really is a MEM. Not all the extv and
4462 extzv predicates are checked. */
4466 /* Check that the size is valid. */
4467 if (width != 32 && (!TARGET_64BIT || width != 64))
4470 /* We can only access byte-aligned values. Since we are always passed
4471 a reference to the first byte of the field, it is not necessary to
4472 do anything with BITPOS after this check. */
4473 if (bitpos % BITS_PER_UNIT != 0)
4476 /* Reject aligned bitfields: we want to use a normal load or store
4477 instead of a left/right pair. */
4478 if (MEM_ALIGN (*op) >= width)
4481 /* Adjust *OP to refer to the whole field. This also has the effect
4482 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4483 *op = adjust_address (*op, BLKmode, 0);
4484 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4486 /* Get references to both ends of the field. We deliberately don't
4487 use the original QImode *OP for FIRST since the new BLKmode one
4488 might have a simpler address. */
4489 first = adjust_address (*op, QImode, 0);
4490 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4492 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4493 be the upper word and RIGHT the lower word. */
4494 if (TARGET_BIG_ENDIAN)
4495 *left = first, *right = last;
4497 *left = last, *right = first;
4503 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4504 Return true on success. We only handle cases where zero_extract is
4505 equivalent to sign_extract. */
4508 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4510 rtx left, right, temp;
4512 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4513 paradoxical word_mode subreg. This is the only case in which
4514 we allow the destination to be larger than the source. */
4515 if (GET_CODE (dest) == SUBREG
4516 && GET_MODE (dest) == DImode
4517 && SUBREG_BYTE (dest) == 0
4518 && GET_MODE (SUBREG_REG (dest)) == SImode)
4519 dest = SUBREG_REG (dest);
4521 /* After the above adjustment, the destination must be the same
4522 width as the source. */
4523 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4526 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4529 temp = gen_reg_rtx (GET_MODE (dest));
4530 if (GET_MODE (dest) == DImode)
4532 emit_insn (gen_mov_ldl (temp, src, left));
4533 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4537 emit_insn (gen_mov_lwl (temp, src, left));
4538 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4544 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4548 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4551 enum machine_mode mode;
4553 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4556 mode = mode_for_size (width, MODE_INT, 0);
4557 src = gen_lowpart (mode, src);
4561 emit_insn (gen_mov_sdl (dest, src, left));
4562 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4566 emit_insn (gen_mov_swl (dest, src, left));
4567 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4572 /* Return true if X is a MEM with the same size as MODE. */
4575 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4582 size = MEM_SIZE (x);
4583 return size && INTVAL (size) == GET_MODE_SIZE (mode);
4586 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4587 source of an "ext" instruction or the destination of an "ins"
4588 instruction. OP must be a register operand and the following
4589 conditions must hold:
4591 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4592 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4593 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4595 Also reject lengths equal to a word as they are better handled
4596 by the move patterns. */
4599 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4601 HOST_WIDE_INT len, pos;
4603 if (!ISA_HAS_EXT_INS
4604 || !register_operand (op, VOIDmode)
4605 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4608 len = INTVAL (size);
4609 pos = INTVAL (position);
4611 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4612 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4618 /* Set up globals to generate code for the ISA or processor
4619 described by INFO. */
4622 mips_set_architecture (const struct mips_cpu_info *info)
4626 mips_arch_info = info;
4627 mips_arch = info->cpu;
4628 mips_isa = info->isa;
4633 /* Likewise for tuning. */
4636 mips_set_tune (const struct mips_cpu_info *info)
4640 mips_tune_info = info;
4641 mips_tune = info->cpu;
4645 /* Implement TARGET_HANDLE_OPTION. */
4648 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4653 if (strcmp (arg, "32") == 0)
4655 else if (strcmp (arg, "o64") == 0)
4657 else if (strcmp (arg, "n32") == 0)
4659 else if (strcmp (arg, "64") == 0)
4661 else if (strcmp (arg, "eabi") == 0)
4662 mips_abi = ABI_EABI;
4669 return mips_parse_cpu (arg) != 0;
4672 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4673 return mips_isa_info != 0;
4675 case OPT_mno_flush_func:
4676 mips_cache_flush_func = NULL;
4684 /* Set up the threshold for data to go into the small data area, instead
4685 of the normal data area, and detect any conflicts in the switches. */
4688 override_options (void)
4690 int i, start, regno;
4691 enum machine_mode mode;
4693 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4695 /* The following code determines the architecture and register size.
4696 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4697 The GAS and GCC code should be kept in sync as much as possible. */
4699 if (mips_arch_string != 0)
4700 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4702 if (mips_isa_info != 0)
4704 if (mips_arch_info == 0)
4705 mips_set_architecture (mips_isa_info);
4706 else if (mips_arch_info->isa != mips_isa_info->isa)
4707 error ("-%s conflicts with the other architecture options, "
4708 "which specify a %s processor",
4709 mips_isa_info->name,
4710 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4713 if (mips_arch_info == 0)
4715 #ifdef MIPS_CPU_STRING_DEFAULT
4716 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4718 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4722 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4723 error ("-march=%s is not compatible with the selected ABI",
4724 mips_arch_info->name);
4726 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4727 if (mips_tune_string != 0)
4728 mips_set_tune (mips_parse_cpu (mips_tune_string));
4730 if (mips_tune_info == 0)
4731 mips_set_tune (mips_arch_info);
4733 /* Set cost structure for the processor. */
4734 mips_cost = &mips_rtx_cost_data[mips_tune];
4736 if ((target_flags_explicit & MASK_64BIT) != 0)
4738 /* The user specified the size of the integer registers. Make sure
4739 it agrees with the ABI and ISA. */
4740 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4741 error ("-mgp64 used with a 32-bit processor");
4742 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4743 error ("-mgp32 used with a 64-bit ABI");
4744 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4745 error ("-mgp64 used with a 32-bit ABI");
4749 /* Infer the integer register size from the ABI and processor.
4750 Restrict ourselves to 32-bit registers if that's all the
4751 processor has, or if the ABI cannot handle 64-bit registers. */
4752 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4753 target_flags &= ~MASK_64BIT;
4755 target_flags |= MASK_64BIT;
4758 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4760 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4761 only one right answer here. */
4762 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4763 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4764 else if (!TARGET_64BIT && TARGET_FLOAT64)
4765 error ("unsupported combination: %s", "-mgp32 -mfp64");
4766 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4767 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4771 /* -msingle-float selects 32-bit float registers. Otherwise the
4772 float registers should be the same size as the integer ones. */
4773 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4774 target_flags |= MASK_FLOAT64;
4776 target_flags &= ~MASK_FLOAT64;
4779 /* End of code shared with GAS. */
4781 if ((target_flags_explicit & MASK_LONG64) == 0)
4783 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4784 target_flags |= MASK_LONG64;
4786 target_flags &= ~MASK_LONG64;
4789 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4790 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4792 /* For some configurations, it is useful to have -march control
4793 the default setting of MASK_SOFT_FLOAT. */
4794 switch ((int) mips_arch)
4796 case PROCESSOR_R4100:
4797 case PROCESSOR_R4111:
4798 case PROCESSOR_R4120:
4799 case PROCESSOR_R4130:
4800 target_flags |= MASK_SOFT_FLOAT;
4804 target_flags &= ~MASK_SOFT_FLOAT;
4810 flag_pcc_struct_return = 0;
4812 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4814 /* If neither -mbranch-likely nor -mno-branch-likely was given
4815 on the command line, set MASK_BRANCHLIKELY based on the target
4818 By default, we enable use of Branch Likely instructions on
4819 all architectures which support them with the following
4820 exceptions: when creating MIPS32 or MIPS64 code, and when
4821 tuning for architectures where their use tends to hurt
4824 The MIPS32 and MIPS64 architecture specifications say "Software
4825 is strongly encouraged to avoid use of Branch Likely
4826 instructions, as they will be removed from a future revision
4827 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4828 issue those instructions unless instructed to do so by
4830 if (ISA_HAS_BRANCHLIKELY
4831 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4832 && !(TUNE_MIPS5500 || TUNE_SB1))
4833 target_flags |= MASK_BRANCHLIKELY;
4835 target_flags &= ~MASK_BRANCHLIKELY;
4837 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4838 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4840 /* The effect of -mabicalls isn't defined for the EABI. */
4841 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4843 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4844 target_flags &= ~MASK_ABICALLS;
4847 if (TARGET_ABICALLS)
4849 /* We need to set flag_pic for executables as well as DSOs
4850 because we may reference symbols that are not defined in
4851 the final executable. (MIPS does not use things like
4852 copy relocs, for example.)
4854 Also, there is a body of code that uses __PIC__ to distinguish
4855 between -mabicalls and -mno-abicalls code. */
4857 if (mips_section_threshold > 0)
4858 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
4861 /* mips_split_addresses is a half-way house between explicit
4862 relocations and the traditional assembler macros. It can
4863 split absolute 32-bit symbolic constants into a high/lo_sum
4864 pair but uses macros for other sorts of access.
4866 Like explicit relocation support for REL targets, it relies
4867 on GNU extensions in the assembler and the linker.
4869 Although this code should work for -O0, it has traditionally
4870 been treated as an optimization. */
4871 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4872 && optimize && !flag_pic
4873 && !ABI_HAS_64BIT_SYMBOLS)
4874 mips_split_addresses = 1;
4876 mips_split_addresses = 0;
4878 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4879 faster code, but at the expense of more nops. Enable it at -O3 and
4881 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4882 target_flags |= MASK_VR4130_ALIGN;
4884 /* When compiling for the mips16, we cannot use floating point. We
4885 record the original hard float value in mips16_hard_float. */
4888 if (TARGET_SOFT_FLOAT)
4889 mips16_hard_float = 0;
4891 mips16_hard_float = 1;
4892 target_flags |= MASK_SOFT_FLOAT;
4894 /* Don't run the scheduler before reload, since it tends to
4895 increase register pressure. */
4896 flag_schedule_insns = 0;
4898 /* Don't do hot/cold partitioning. The constant layout code expects
4899 the whole function to be in a single section. */
4900 flag_reorder_blocks_and_partition = 0;
4902 /* Silently disable -mexplicit-relocs since it doesn't apply
4903 to mips16 code. Even so, it would overly pedantic to warn
4904 about "-mips16 -mexplicit-relocs", especially given that
4905 we use a %gprel() operator. */
4906 target_flags &= ~MASK_EXPLICIT_RELOCS;
4909 /* When using explicit relocs, we call dbr_schedule from within
4911 if (TARGET_EXPLICIT_RELOCS)
4913 mips_flag_delayed_branch = flag_delayed_branch;
4914 flag_delayed_branch = 0;
4917 #ifdef MIPS_TFMODE_FORMAT
4918 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4921 /* Make sure that the user didn't turn off paired single support when
4922 MIPS-3D support is requested. */
4923 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4924 && !TARGET_PAIRED_SINGLE_FLOAT)
4925 error ("-mips3d requires -mpaired-single");
4927 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4929 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4931 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4932 and TARGET_HARD_FLOAT are both true. */
4933 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4934 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4936 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4938 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4939 error ("-mips3d/-mpaired-single must be used with -mips64");
4941 if (TARGET_MIPS16 && TARGET_DSP)
4942 error ("-mips16 and -mdsp cannot be used together");
4944 mips_print_operand_punct['?'] = 1;
4945 mips_print_operand_punct['#'] = 1;
4946 mips_print_operand_punct['/'] = 1;
4947 mips_print_operand_punct['&'] = 1;
4948 mips_print_operand_punct['!'] = 1;
4949 mips_print_operand_punct['*'] = 1;
4950 mips_print_operand_punct['@'] = 1;
4951 mips_print_operand_punct['.'] = 1;
4952 mips_print_operand_punct['('] = 1;
4953 mips_print_operand_punct[')'] = 1;
4954 mips_print_operand_punct['['] = 1;
4955 mips_print_operand_punct[']'] = 1;
4956 mips_print_operand_punct['<'] = 1;
4957 mips_print_operand_punct['>'] = 1;
4958 mips_print_operand_punct['{'] = 1;
4959 mips_print_operand_punct['}'] = 1;
4960 mips_print_operand_punct['^'] = 1;
4961 mips_print_operand_punct['$'] = 1;
4962 mips_print_operand_punct['+'] = 1;
4963 mips_print_operand_punct['~'] = 1;
4965 /* Set up array to map GCC register number to debug register number.
4966 Ignore the special purpose register numbers. */
4968 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4969 mips_dbx_regno[i] = -1;
4971 start = GP_DBX_FIRST - GP_REG_FIRST;
4972 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4973 mips_dbx_regno[i] = i + start;
4975 start = FP_DBX_FIRST - FP_REG_FIRST;
4976 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4977 mips_dbx_regno[i] = i + start;
4979 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4980 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4982 /* Set up array giving whether a given register can hold a given mode. */
4984 for (mode = VOIDmode;
4985 mode != MAX_MACHINE_MODE;
4986 mode = (enum machine_mode) ((int)mode + 1))
4988 register int size = GET_MODE_SIZE (mode);
4989 register enum mode_class class = GET_MODE_CLASS (mode);
4991 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4995 if (mode == CCV2mode)
4998 && (regno - ST_REG_FIRST) % 2 == 0);
5000 else if (mode == CCV4mode)
5003 && (regno - ST_REG_FIRST) % 4 == 0);
5005 else if (mode == CCmode)
5008 temp = (regno == FPSW_REGNUM);
5010 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5011 || FP_REG_P (regno));
5014 else if (GP_REG_P (regno))
5015 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5017 else if (FP_REG_P (regno))
5018 temp = ((regno % FP_INC) == 0)
5019 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5020 || class == MODE_VECTOR_FLOAT)
5021 && size <= UNITS_PER_FPVALUE)
5022 /* Allow integer modes that fit into a single
5023 register. We need to put integers into FPRs
5024 when using instructions like cvt and trunc.
5025 We can't allow sizes smaller than a word,
5026 the FPU has no appropriate load/store
5027 instructions for those. */
5028 || (class == MODE_INT
5029 && size >= MIN_UNITS_PER_WORD
5030 && size <= UNITS_PER_FPREG)
5031 /* Allow TFmode for CCmode reloads. */
5032 || (ISA_HAS_8CC && mode == TFmode));
5034 else if (ACC_REG_P (regno))
5035 temp = (INTEGRAL_MODE_P (mode)
5036 && (size <= UNITS_PER_WORD
5037 || (ACC_HI_REG_P (regno)
5038 && size == 2 * UNITS_PER_WORD)));
5040 else if (ALL_COP_REG_P (regno))
5041 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5045 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5049 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5050 initialized yet, so we can't use that here. */
5051 gpr_mode = TARGET_64BIT ? DImode : SImode;
5053 /* Provide default values for align_* for 64-bit targets. */
5054 if (TARGET_64BIT && !TARGET_MIPS16)
5056 if (align_loops == 0)
5058 if (align_jumps == 0)
5060 if (align_functions == 0)
5061 align_functions = 8;
5064 /* Function to allocate machine-dependent function status. */
5065 init_machine_status = &mips_init_machine_status;
5067 if (ABI_HAS_64BIT_SYMBOLS)
5069 if (TARGET_EXPLICIT_RELOCS)
5071 mips_split_p[SYMBOL_64_HIGH] = true;
5072 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5073 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5075 mips_split_p[SYMBOL_64_MID] = true;
5076 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5077 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5079 mips_split_p[SYMBOL_64_LOW] = true;
5080 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5081 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5083 mips_split_p[SYMBOL_GENERAL] = true;
5084 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5089 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5091 mips_split_p[SYMBOL_GENERAL] = true;
5092 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5093 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5099 /* The high part is provided by a pseudo copy of $gp. */
5100 mips_split_p[SYMBOL_SMALL_DATA] = true;
5101 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5104 if (TARGET_EXPLICIT_RELOCS)
5106 /* Small data constants are kept whole until after reload,
5107 then lowered by mips_rewrite_small_data. */
5108 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5110 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5113 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5114 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5118 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5119 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5124 /* The HIGH and LO_SUM are matched by special .md patterns. */
5125 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5127 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5128 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5129 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5131 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5132 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5133 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5138 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5140 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5141 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5147 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5148 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5149 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5152 /* Thread-local relocation operators. */
5153 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5154 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5155 mips_split_p[SYMBOL_DTPREL] = 1;
5156 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5157 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5158 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5159 mips_split_p[SYMBOL_TPREL] = 1;
5160 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5161 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5163 /* We don't have a thread pointer access instruction on MIPS16, or
5164 appropriate TLS relocations. */
5166 targetm.have_tls = false;
5168 /* Default to working around R4000 errata only if the processor
5169 was selected explicitly. */
5170 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5171 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5172 target_flags |= MASK_FIX_R4000;
5174 /* Default to working around R4400 errata only if the processor
5175 was selected explicitly. */
5176 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5177 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5178 target_flags |= MASK_FIX_R4400;
5181 /* Implement CONDITIONAL_REGISTER_USAGE. */
5184 mips_conditional_register_usage (void)
5190 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5191 fixed_regs[regno] = call_used_regs[regno] = 1;
5193 if (!TARGET_HARD_FLOAT)
5197 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5198 fixed_regs[regno] = call_used_regs[regno] = 1;
5199 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5200 fixed_regs[regno] = call_used_regs[regno] = 1;
5202 else if (! ISA_HAS_8CC)
5206 /* We only have a single condition code register. We
5207 implement this by hiding all the condition code registers,
5208 and generating RTL that refers directly to ST_REG_FIRST. */
5209 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5210 fixed_regs[regno] = call_used_regs[regno] = 1;
5212 /* In mips16 mode, we permit the $t temporary registers to be used
5213 for reload. We prohibit the unused $s registers, since they
5214 are caller saved, and saving them via a mips16 register would
5215 probably waste more time than just reloading the value. */
5218 fixed_regs[18] = call_used_regs[18] = 1;
5219 fixed_regs[19] = call_used_regs[19] = 1;
5220 fixed_regs[20] = call_used_regs[20] = 1;
5221 fixed_regs[21] = call_used_regs[21] = 1;
5222 fixed_regs[22] = call_used_regs[22] = 1;
5223 fixed_regs[23] = call_used_regs[23] = 1;
5224 fixed_regs[26] = call_used_regs[26] = 1;
5225 fixed_regs[27] = call_used_regs[27] = 1;
5226 fixed_regs[30] = call_used_regs[30] = 1;
5228 /* fp20-23 are now caller saved. */
5229 if (mips_abi == ABI_64)
5232 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5233 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5235 /* Odd registers from fp21 to fp31 are now caller saved. */
5236 if (mips_abi == ABI_N32)
5239 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5240 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5244 /* Allocate a chunk of memory for per-function machine-dependent data. */
5245 static struct machine_function *
5246 mips_init_machine_status (void)
5248 return ((struct machine_function *)
5249 ggc_alloc_cleared (sizeof (struct machine_function)));
5252 /* On the mips16, we want to allocate $24 (T_REG) before other
5253 registers for instructions for which it is possible. This helps
5254 avoid shuffling registers around in order to set up for an xor,
5255 encouraging the compiler to use a cmp instead. */
5258 mips_order_regs_for_local_alloc (void)
5262 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5263 reg_alloc_order[i] = i;
5267 /* It really doesn't matter where we put register 0, since it is
5268 a fixed register anyhow. */
5269 reg_alloc_order[0] = 24;
5270 reg_alloc_order[24] = 0;
5275 /* The MIPS debug format wants all automatic variables and arguments
5276 to be in terms of the virtual frame pointer (stack pointer before
5277 any adjustment in the function), while the MIPS 3.0 linker wants
5278 the frame pointer to be the stack pointer after the initial
5279 adjustment. So, we do the adjustment here. The arg pointer (which
5280 is eliminated) points to the virtual frame pointer, while the frame
5281 pointer (which may be eliminated) points to the stack pointer after
5282 the initial adjustments. */
5285 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5287 rtx offset2 = const0_rtx;
5288 rtx reg = eliminate_constant_term (addr, &offset2);
5291 offset = INTVAL (offset2);
5293 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5294 || reg == hard_frame_pointer_rtx)
5296 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5297 ? compute_frame_size (get_frame_size ())
5298 : cfun->machine->frame.total_size;
5300 /* MIPS16 frame is smaller */
5301 if (frame_pointer_needed && TARGET_MIPS16)
5302 frame_size -= cfun->machine->frame.args_size;
5304 offset = offset - frame_size;
5307 /* sdbout_parms does not want this to crash for unrecognized cases. */
5309 else if (reg != arg_pointer_rtx)
5310 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5317 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5319 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5320 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5321 'h' OP is HIGH, prints %hi(X),
5322 'd' output integer constant in decimal,
5323 'z' if the operand is 0, use $0 instead of normal operand.
5324 'D' print second part of double-word register or memory operand.
5325 'L' print low-order register of double-word register operand.
5326 'M' print high-order register of double-word register operand.
5327 'C' print part of opcode for a branch condition.
5328 'F' print part of opcode for a floating-point branch condition.
5329 'N' print part of opcode for a branch condition, inverted.
5330 'W' print part of opcode for a floating-point branch condition, inverted.
5331 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5332 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5333 't' like 'T', but with the EQ/NE cases reversed
5334 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5335 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5336 'R' print the reloc associated with LO_SUM
5337 'q' print DSP accumulator registers
5339 The punctuation characters are:
5341 '(' Turn on .set noreorder
5342 ')' Turn on .set reorder
5343 '[' Turn on .set noat
5345 '<' Turn on .set nomacro
5346 '>' Turn on .set macro
5347 '{' Turn on .set volatile (not GAS)
5348 '}' Turn on .set novolatile (not GAS)
5349 '&' Turn on .set noreorder if filling delay slots
5350 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5351 '!' Turn on .set nomacro if filling delay slots
5352 '#' Print nop if in a .set noreorder section.
5353 '/' Like '#', but does nothing within a delayed branch sequence
5354 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5355 '@' Print the name of the assembler temporary register (at or $1).
5356 '.' Print the name of the register with a hard-wired zero (zero or $0).
5357 '^' Print the name of the pic call-through register (t9 or $25).
5358 '$' Print the name of the stack pointer register (sp or $29).
5359 '+' Print the name of the gp register (usually gp or $28).
5360 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5363 print_operand (FILE *file, rtx op, int letter)
5365 register enum rtx_code code;
5367 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5372 if (mips_branch_likely)
5377 fputs (reg_names [GP_REG_FIRST + 1], file);
5381 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5385 fputs (reg_names [GP_REG_FIRST + 0], file);
5389 fputs (reg_names[STACK_POINTER_REGNUM], file);
5393 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5397 if (final_sequence != 0 && set_noreorder++ == 0)
5398 fputs (".set\tnoreorder\n\t", file);
5402 if (final_sequence != 0)
5404 if (set_noreorder++ == 0)
5405 fputs (".set\tnoreorder\n\t", file);
5407 if (set_nomacro++ == 0)
5408 fputs (".set\tnomacro\n\t", file);
5413 if (final_sequence != 0 && set_nomacro++ == 0)
5414 fputs ("\n\t.set\tnomacro", file);
5418 if (set_noreorder != 0)
5419 fputs ("\n\tnop", file);
5423 /* Print an extra newline so that the delayed insn is separated
5424 from the following ones. This looks neater and is consistent
5425 with non-nop delayed sequences. */
5426 if (set_noreorder != 0 && final_sequence == 0)
5427 fputs ("\n\tnop\n", file);
5431 if (set_noreorder++ == 0)
5432 fputs (".set\tnoreorder\n\t", file);
5436 if (set_noreorder == 0)
5437 error ("internal error: %%) found without a %%( in assembler pattern");
5439 else if (--set_noreorder == 0)
5440 fputs ("\n\t.set\treorder", file);
5445 if (set_noat++ == 0)
5446 fputs (".set\tnoat\n\t", file);
5451 error ("internal error: %%] found without a %%[ in assembler pattern");
5452 else if (--set_noat == 0)
5453 fputs ("\n\t.set\tat", file);
5458 if (set_nomacro++ == 0)
5459 fputs (".set\tnomacro\n\t", file);
5463 if (set_nomacro == 0)
5464 error ("internal error: %%> found without a %%< in assembler pattern");
5465 else if (--set_nomacro == 0)
5466 fputs ("\n\t.set\tmacro", file);
5471 if (set_volatile++ == 0)
5472 fputs ("#.set\tvolatile\n\t", file);
5476 if (set_volatile == 0)
5477 error ("internal error: %%} found without a %%{ in assembler pattern");
5478 else if (--set_volatile == 0)
5479 fputs ("\n\t#.set\tnovolatile", file);
5485 if (align_labels_log > 0)
5486 ASM_OUTPUT_ALIGN (file, align_labels_log);
5491 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5500 error ("PRINT_OPERAND null pointer");
5504 code = GET_CODE (op);
5509 case EQ: fputs ("eq", file); break;
5510 case NE: fputs ("ne", file); break;
5511 case GT: fputs ("gt", file); break;
5512 case GE: fputs ("ge", file); break;
5513 case LT: fputs ("lt", file); break;
5514 case LE: fputs ("le", file); break;
5515 case GTU: fputs ("gtu", file); break;
5516 case GEU: fputs ("geu", file); break;
5517 case LTU: fputs ("ltu", file); break;
5518 case LEU: fputs ("leu", file); break;
5520 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5523 else if (letter == 'N')
5526 case EQ: fputs ("ne", file); break;
5527 case NE: fputs ("eq", file); break;
5528 case GT: fputs ("le", file); break;
5529 case GE: fputs ("lt", file); break;
5530 case LT: fputs ("ge", file); break;
5531 case LE: fputs ("gt", file); break;
5532 case GTU: fputs ("leu", file); break;
5533 case GEU: fputs ("ltu", file); break;
5534 case LTU: fputs ("geu", file); break;
5535 case LEU: fputs ("gtu", file); break;
5537 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5540 else if (letter == 'F')
5543 case EQ: fputs ("c1f", file); break;
5544 case NE: fputs ("c1t", file); break;
5546 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5549 else if (letter == 'W')
5552 case EQ: fputs ("c1t", file); break;
5553 case NE: fputs ("c1f", file); break;
5555 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5558 else if (letter == 'h')
5560 if (GET_CODE (op) == HIGH)
5563 print_operand_reloc (file, op, mips_hi_relocs);
5566 else if (letter == 'R')
5567 print_operand_reloc (file, op, mips_lo_relocs);
5569 else if (letter == 'Y')
5571 if (GET_CODE (op) == CONST_INT
5572 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5573 < ARRAY_SIZE (mips_fp_conditions)))
5574 fputs (mips_fp_conditions[INTVAL (op)], file);
5576 output_operand_lossage ("invalid %%Y value");
5579 else if (letter == 'Z')
5583 print_operand (file, op, 0);
5588 else if (letter == 'q')
5593 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5595 regnum = REGNO (op);
5596 if (MD_REG_P (regnum))
5597 fprintf (file, "$ac0");
5598 else if (DSP_ACC_REG_P (regnum))
5599 fprintf (file, "$ac%c", reg_names[regnum][3]);
5601 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5604 else if (code == REG || code == SUBREG)
5606 register int regnum;
5609 regnum = REGNO (op);
5611 regnum = true_regnum (op);
5613 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5614 || (letter == 'L' && WORDS_BIG_ENDIAN)
5618 fprintf (file, "%s", reg_names[regnum]);
5621 else if (code == MEM)
5624 output_address (plus_constant (XEXP (op, 0), 4));
5626 output_address (XEXP (op, 0));
5629 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5630 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5632 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5633 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5635 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5636 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5638 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5639 fputs (reg_names[GP_REG_FIRST], file);
5641 else if (letter == 'd' || letter == 'x' || letter == 'X')
5642 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5644 else if (letter == 'T' || letter == 't')
5646 int truth = (code == NE) == (letter == 'T');
5647 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5650 else if (CONST_GP_P (op))
5651 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5654 output_addr_const (file, op);
5658 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5659 RELOCS is the array of relocations to use. */
5662 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5664 enum mips_symbol_type symbol_type;
5667 HOST_WIDE_INT offset;
5669 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5670 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5672 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5673 mips_split_const (op, &base, &offset);
5674 if (UNSPEC_ADDRESS_P (base))
5675 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5677 fputs (relocs[symbol_type], file);
5678 output_addr_const (file, op);
5679 for (p = relocs[symbol_type]; *p != 0; p++)
5684 /* Output address operand X to FILE. */
5687 print_operand_address (FILE *file, rtx x)
5689 struct mips_address_info addr;
5691 if (mips_classify_address (&addr, x, word_mode, true))
5695 print_operand (file, addr.offset, 0);
5696 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5699 case ADDRESS_LO_SUM:
5700 print_operand (file, addr.offset, 'R');
5701 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5704 case ADDRESS_CONST_INT:
5705 output_addr_const (file, x);
5706 fprintf (file, "(%s)", reg_names[0]);
5709 case ADDRESS_SYMBOLIC:
5710 output_addr_const (file, x);
5716 /* When using assembler macros, keep track of all of small-data externs
5717 so that mips_file_end can emit the appropriate declarations for them.
5719 In most cases it would be safe (though pointless) to emit .externs
5720 for other symbols too. One exception is when an object is within
5721 the -G limit but declared by the user to be in a section other
5722 than .sbss or .sdata. */
5725 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5727 register struct extern_list *p;
5729 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5731 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5732 p->next = extern_head;
5734 p->size = int_size_in_bytes (TREE_TYPE (decl));
5738 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5740 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5741 p->next = extern_head;
5752 irix_output_external_libcall (rtx fun)
5754 register struct extern_list *p;
5756 if (mips_abi == ABI_32)
5758 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5759 p->next = extern_head;
5760 p->name = XSTR (fun, 0);
5767 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5768 put out a MIPS ECOFF file and a stab. */
5771 mips_output_filename (FILE *stream, const char *name)
5774 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5776 if (write_symbols == DWARF2_DEBUG)
5778 else if (mips_output_filename_first_time)
5780 mips_output_filename_first_time = 0;
5781 num_source_filenames += 1;
5782 current_function_file = name;
5783 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5784 output_quoted_string (stream, name);
5785 putc ('\n', stream);
5788 /* If we are emitting stabs, let dbxout.c handle this (except for
5789 the mips_output_filename_first_time case). */
5790 else if (write_symbols == DBX_DEBUG)
5793 else if (name != current_function_file
5794 && strcmp (name, current_function_file) != 0)
5796 num_source_filenames += 1;
5797 current_function_file = name;
5798 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5799 output_quoted_string (stream, name);
5800 putc ('\n', stream);
5804 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5805 that should be written before the opening quote, such as "\t.ascii\t"
5806 for real string data or "\t# " for a comment. */
5809 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5814 register const unsigned char *string =
5815 (const unsigned char *)string_param;
5817 fprintf (stream, "%s\"", prefix);
5818 for (i = 0; i < len; i++)
5820 register int c = string[i];
5824 if (c == '\\' || c == '\"')
5826 putc ('\\', stream);
5834 fprintf (stream, "\\%03o", c);
5838 if (cur_pos > 72 && i+1 < len)
5841 fprintf (stream, "\"\n%s\"", prefix);
5844 fprintf (stream, "\"\n");
5847 /* Implement TARGET_ASM_FILE_START. */
5850 mips_file_start (void)
5852 default_file_start ();
5856 /* Generate a special section to describe the ABI switches used to
5857 produce the resultant binary. This used to be done by the assembler
5858 setting bits in the ELF header's flags field, but we have run out of
5859 bits. GDB needs this information in order to be able to correctly
5860 debug these binaries. See the function mips_gdbarch_init() in
5861 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5862 causes unnecessary IRIX 6 ld warnings. */
5863 const char * abi_string = NULL;
5867 case ABI_32: abi_string = "abi32"; break;
5868 case ABI_N32: abi_string = "abiN32"; break;
5869 case ABI_64: abi_string = "abi64"; break;
5870 case ABI_O64: abi_string = "abiO64"; break;
5871 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5875 /* Note - we use fprintf directly rather than calling switch_to_section
5876 because in this way we can avoid creating an allocated section. We
5877 do not want this section to take up any space in the running
5879 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5881 /* There is no ELF header flag to distinguish long32 forms of the
5882 EABI from long64 forms. Emit a special section to help tools
5883 such as GDB. Do the same for o64, which is sometimes used with
5885 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
5886 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5887 TARGET_LONG64 ? 64 : 32);
5889 /* Restore the default section. */
5890 fprintf (asm_out_file, "\t.previous\n");
5893 /* Generate the pseudo ops that System V.4 wants. */
5894 if (TARGET_ABICALLS)
5895 fprintf (asm_out_file, "\t.abicalls\n");
5898 fprintf (asm_out_file, "\t.set\tmips16\n");
5900 if (flag_verbose_asm)
5901 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5903 mips_section_threshold, mips_arch_info->name, mips_isa);
5906 #ifdef BSS_SECTION_ASM_OP
5907 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5908 in the use of sbss. */
5911 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5912 unsigned HOST_WIDE_INT size, int align)
5914 extern tree last_assemble_variable_decl;
5916 if (mips_in_small_data_p (decl))
5917 switch_to_section (get_named_section (NULL, ".sbss", 0));
5919 switch_to_section (bss_section);
5920 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5921 last_assemble_variable_decl = decl;
5922 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5923 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5927 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5928 .externs for any small-data variables that turned out to be external. */
5931 mips_file_end (void)
5934 struct extern_list *p;
5938 fputs ("\n", asm_out_file);
5940 for (p = extern_head; p != 0; p = p->next)
5942 name_tree = get_identifier (p->name);
5944 /* Positively ensure only one .extern for any given symbol. */
5945 if (!TREE_ASM_WRITTEN (name_tree)
5946 && TREE_SYMBOL_REFERENCED (name_tree))
5948 TREE_ASM_WRITTEN (name_tree) = 1;
5949 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5950 `.global name .text' directive for every used but
5951 undefined function. If we don't, the linker may perform
5952 an optimization (skipping over the insns that set $gp)
5953 when it is unsafe. */
5954 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5956 fputs ("\t.globl ", asm_out_file);
5957 assemble_name (asm_out_file, p->name);
5958 fputs (" .text\n", asm_out_file);
5962 fputs ("\t.extern\t", asm_out_file);
5963 assemble_name (asm_out_file, p->name);
5964 fprintf (asm_out_file, ", %d\n", p->size);
5971 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5972 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5975 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5976 unsigned HOST_WIDE_INT size,
5979 /* If the target wants uninitialized const declarations in
5980 .rdata then don't put them in .comm. */
5981 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5982 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5983 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5985 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5986 targetm.asm_out.globalize_label (stream, name);
5988 switch_to_section (readonly_data_section);
5989 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5990 mips_declare_object (stream, name, "",
5991 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5995 mips_declare_common_object (stream, name, "\n\t.comm\t",
5999 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6000 NAME is the name of the object and ALIGN is the required alignment
6001 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
6002 alignment argument. */
6005 mips_declare_common_object (FILE *stream, const char *name,
6006 const char *init_string,
6007 unsigned HOST_WIDE_INT size,
6008 unsigned int align, bool takes_alignment_p)
6010 if (!takes_alignment_p)
6012 size += (align / BITS_PER_UNIT) - 1;
6013 size -= size % (align / BITS_PER_UNIT);
6014 mips_declare_object (stream, name, init_string,
6015 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6018 mips_declare_object (stream, name, init_string,
6019 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6020 size, align / BITS_PER_UNIT);
6023 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6024 macros, mark the symbol as written so that mips_file_end won't emit an
6025 .extern for it. STREAM is the output file, NAME is the name of the
6026 symbol, INIT_STRING is the string that should be written before the
6027 symbol and FINAL_STRING is the string that should be written after it.
6028 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6031 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6032 const char *final_string, ...)
6036 fputs (init_string, stream);
6037 assemble_name (stream, name);
6038 va_start (ap, final_string);
6039 vfprintf (stream, final_string, ap);
6042 if (!TARGET_EXPLICIT_RELOCS)
6044 tree name_tree = get_identifier (name);
6045 TREE_ASM_WRITTEN (name_tree) = 1;
6049 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6050 extern int size_directive_output;
6052 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6053 definitions except that it uses mips_declare_object() to emit the label. */
6056 mips_declare_object_name (FILE *stream, const char *name,
6057 tree decl ATTRIBUTE_UNUSED)
6059 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6060 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6063 size_directive_output = 0;
6064 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6068 size_directive_output = 1;
6069 size = int_size_in_bytes (TREE_TYPE (decl));
6070 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6073 mips_declare_object (stream, name, "", ":\n");
6076 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6079 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6083 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6084 if (!flag_inhibit_size_directive
6085 && DECL_SIZE (decl) != 0
6086 && !at_end && top_level
6087 && DECL_INITIAL (decl) == error_mark_node
6088 && !size_directive_output)
6092 size_directive_output = 1;
6093 size = int_size_in_bytes (TREE_TYPE (decl));
6094 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6099 /* Return true if X is a small data address that can be rewritten
6103 mips_rewrite_small_data_p (rtx x)
6105 enum mips_symbol_type symbol_type;
6107 return (TARGET_EXPLICIT_RELOCS
6108 && mips_symbolic_constant_p (x, &symbol_type)
6109 && symbol_type == SYMBOL_SMALL_DATA);
6113 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6116 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6118 if (GET_CODE (*loc) == LO_SUM)
6121 return mips_rewrite_small_data_p (*loc);
6124 /* Return true if OP refers to small data symbols directly, not through
6128 mips_small_data_pattern_p (rtx op)
6130 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6133 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6136 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6138 if (mips_rewrite_small_data_p (*loc))
6139 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6141 if (GET_CODE (*loc) == LO_SUM)
6147 /* If possible, rewrite OP so that it refers to small data using
6148 explicit relocations. */
6151 mips_rewrite_small_data (rtx op)
6153 op = copy_insn (op);
6154 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6158 /* Return true if the current function has an insn that implicitly
6162 mips_function_has_gp_insn (void)
6164 /* Don't bother rechecking if we found one last time. */
6165 if (!cfun->machine->has_gp_insn_p)
6169 push_topmost_sequence ();
6170 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6172 && GET_CODE (PATTERN (insn)) != USE
6173 && GET_CODE (PATTERN (insn)) != CLOBBER
6174 && (get_attr_got (insn) != GOT_UNSET
6175 || small_data_pattern (PATTERN (insn), VOIDmode)))
6177 pop_topmost_sequence ();
6179 cfun->machine->has_gp_insn_p = (insn != 0);
6181 return cfun->machine->has_gp_insn_p;
6185 /* Return the register that should be used as the global pointer
6186 within this function. Return 0 if the function doesn't need
6187 a global pointer. */
6190 mips_global_pointer (void)
6194 /* $gp is always available in non-abicalls code. */
6195 if (!TARGET_ABICALLS)
6196 return GLOBAL_POINTER_REGNUM;
6198 /* We must always provide $gp when it is used implicitly. */
6199 if (!TARGET_EXPLICIT_RELOCS)
6200 return GLOBAL_POINTER_REGNUM;
6202 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6204 if (current_function_profile)
6205 return GLOBAL_POINTER_REGNUM;
6207 /* If the function has a nonlocal goto, $gp must hold the correct
6208 global pointer for the target function. */
6209 if (current_function_has_nonlocal_goto)
6210 return GLOBAL_POINTER_REGNUM;
6212 /* If the gp is never referenced, there's no need to initialize it.
6213 Note that reload can sometimes introduce constant pool references
6214 into a function that otherwise didn't need them. For example,
6215 suppose we have an instruction like:
6217 (set (reg:DF R1) (float:DF (reg:SI R2)))
6219 If R2 turns out to be constant such as 1, the instruction may have a
6220 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6221 using this constant if R2 doesn't get allocated to a register.
6223 In cases like these, reload will have added the constant to the pool
6224 but no instruction will yet refer to it. */
6225 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6226 && !current_function_uses_const_pool
6227 && !mips_function_has_gp_insn ())
6230 /* We need a global pointer, but perhaps we can use a call-clobbered
6231 register instead of $gp. */
6232 if (TARGET_NEWABI && current_function_is_leaf)
6233 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6234 if (!regs_ever_live[regno]
6235 && call_used_regs[regno]
6236 && !fixed_regs[regno]
6237 && regno != PIC_FUNCTION_ADDR_REGNUM)
6240 return GLOBAL_POINTER_REGNUM;
6244 /* Return true if the current function must save REGNO. */
6247 mips_save_reg_p (unsigned int regno)
6249 /* We only need to save $gp for NewABI PIC. */
6250 if (regno == GLOBAL_POINTER_REGNUM)
6251 return (TARGET_ABICALLS && TARGET_NEWABI
6252 && cfun->machine->global_pointer == regno);
6254 /* Check call-saved registers. */
6255 if (regs_ever_live[regno] && !call_used_regs[regno])
6258 /* We need to save the old frame pointer before setting up a new one. */
6259 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6262 /* We need to save the incoming return address if it is ever clobbered
6263 within the function. */
6264 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6271 return_type = DECL_RESULT (current_function_decl);
6273 /* $18 is a special case in mips16 code. It may be used to call
6274 a function which returns a floating point value, but it is
6275 marked in call_used_regs. */
6276 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6279 /* $31 is also a special case. It will be used to copy a return
6280 value into the floating point registers if the return value is
6282 if (regno == GP_REG_FIRST + 31
6283 && mips16_hard_float
6284 && !aggregate_value_p (return_type, current_function_decl)
6285 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6286 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6294 /* Return the bytes needed to compute the frame pointer from the current
6295 stack pointer. SIZE is the size (in bytes) of the local variables.
6297 MIPS stack frames look like:
6299 Before call After call
6300 +-----------------------+ +-----------------------+
6303 | caller's temps. | | caller's temps. |
6305 +-----------------------+ +-----------------------+
6307 | arguments on stack. | | arguments on stack. |
6309 +-----------------------+ +-----------------------+
6310 | 4 words to save | | 4 words to save |
6311 | arguments passed | | arguments passed |
6312 | in registers, even | | in registers, even |
6313 SP->| if not passed. | VFP->| if not passed. |
6314 +-----------------------+ +-----------------------+
6316 | fp register save |
6318 +-----------------------+
6320 | gp register save |
6322 +-----------------------+
6326 +-----------------------+
6328 | alloca allocations |
6330 +-----------------------+
6332 | GP save for V.4 abi |
6334 +-----------------------+
6336 | arguments on stack |
6338 +-----------------------+
6340 | arguments passed |
6341 | in registers, even |
6342 low SP->| if not passed. |
6343 memory +-----------------------+
6348 compute_frame_size (HOST_WIDE_INT size)
6351 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6352 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6353 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6354 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6355 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6356 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6357 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6358 unsigned int mask; /* mask of saved gp registers */
6359 unsigned int fmask; /* mask of saved fp registers */
6361 cfun->machine->global_pointer = mips_global_pointer ();
6367 var_size = MIPS_STACK_ALIGN (size);
6368 args_size = current_function_outgoing_args_size;
6369 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6371 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6372 functions. If the function has local variables, we're committed
6373 to allocating it anyway. Otherwise reclaim it here. */
6374 if (var_size == 0 && current_function_is_leaf)
6375 cprestore_size = args_size = 0;
6377 /* The MIPS 3.0 linker does not like functions that dynamically
6378 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6379 looks like we are trying to create a second frame pointer to the
6380 function, so allocate some stack space to make it happy. */
6382 if (args_size == 0 && current_function_calls_alloca)
6383 args_size = 4 * UNITS_PER_WORD;
6385 total_size = var_size + args_size + cprestore_size;
6387 /* Calculate space needed for gp registers. */
6388 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6389 if (mips_save_reg_p (regno))
6391 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6392 mask |= 1 << (regno - GP_REG_FIRST);
6395 /* We need to restore these for the handler. */
6396 if (current_function_calls_eh_return)
6401 regno = EH_RETURN_DATA_REGNO (i);
6402 if (regno == INVALID_REGNUM)
6404 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6405 mask |= 1 << (regno - GP_REG_FIRST);
6409 /* This loop must iterate over the same space as its companion in
6410 save_restore_insns. */
6411 for (regno = (FP_REG_LAST - FP_INC + 1);
6412 regno >= FP_REG_FIRST;
6415 if (mips_save_reg_p (regno))
6417 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6418 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6422 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6423 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6425 /* Add in the space required for saving incoming register arguments. */
6426 total_size += current_function_pretend_args_size;
6427 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6429 /* Save other computed information. */
6430 cfun->machine->frame.total_size = total_size;
6431 cfun->machine->frame.var_size = var_size;
6432 cfun->machine->frame.args_size = args_size;
6433 cfun->machine->frame.cprestore_size = cprestore_size;
6434 cfun->machine->frame.gp_reg_size = gp_reg_size;
6435 cfun->machine->frame.fp_reg_size = fp_reg_size;
6436 cfun->machine->frame.mask = mask;
6437 cfun->machine->frame.fmask = fmask;
6438 cfun->machine->frame.initialized = reload_completed;
6439 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6440 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6444 HOST_WIDE_INT offset;
6446 offset = (args_size + cprestore_size + var_size
6447 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6448 cfun->machine->frame.gp_sp_offset = offset;
6449 cfun->machine->frame.gp_save_offset = offset - total_size;
6453 cfun->machine->frame.gp_sp_offset = 0;
6454 cfun->machine->frame.gp_save_offset = 0;
6459 HOST_WIDE_INT offset;
6461 offset = (args_size + cprestore_size + var_size
6462 + gp_reg_rounded + fp_reg_size
6463 - FP_INC * UNITS_PER_FPREG);
6464 cfun->machine->frame.fp_sp_offset = offset;
6465 cfun->machine->frame.fp_save_offset = offset - total_size;
6469 cfun->machine->frame.fp_sp_offset = 0;
6470 cfun->machine->frame.fp_save_offset = 0;
6473 /* Ok, we're done. */
6477 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6478 pointer or argument pointer. TO is either the stack pointer or
6479 hard frame pointer. */
6482 mips_initial_elimination_offset (int from, int to)
6484 HOST_WIDE_INT offset;
6486 compute_frame_size (get_frame_size ());
6488 /* Set OFFSET to the offset from the stack pointer. */
6491 case FRAME_POINTER_REGNUM:
6495 case ARG_POINTER_REGNUM:
6496 offset = (cfun->machine->frame.total_size
6497 - current_function_pretend_args_size);
6504 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6505 offset -= cfun->machine->frame.args_size;
6510 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6511 back to a previous frame. */
6513 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6518 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6521 /* Use FN to save or restore register REGNO. MODE is the register's
6522 mode and OFFSET is the offset of its save slot from the current
6526 mips_save_restore_reg (enum machine_mode mode, int regno,
6527 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6531 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6533 fn (gen_rtx_REG (mode, regno), mem);
6537 /* Call FN for each register that is saved by the current function.
6538 SP_OFFSET is the offset of the current stack pointer from the start
6542 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6544 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6546 enum machine_mode fpr_mode;
6547 HOST_WIDE_INT offset;
6550 /* Save registers starting from high to low. The debuggers prefer at least
6551 the return register be stored at func+4, and also it allows us not to
6552 need a nop in the epilog if at least one register is reloaded in
6553 addition to return address. */
6554 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6555 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6556 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6558 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6559 offset -= GET_MODE_SIZE (gpr_mode);
6562 /* This loop must iterate over the same space as its companion in
6563 compute_frame_size. */
6564 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6565 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6566 for (regno = (FP_REG_LAST - FP_INC + 1);
6567 regno >= FP_REG_FIRST;
6569 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6571 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6572 offset -= GET_MODE_SIZE (fpr_mode);
6577 /* If we're generating n32 or n64 abicalls, and the current function
6578 does not use $28 as its global pointer, emit a cplocal directive.
6579 Use pic_offset_table_rtx as the argument to the directive. */
6582 mips_output_cplocal (void)
6584 if (!TARGET_EXPLICIT_RELOCS
6585 && cfun->machine->global_pointer > 0
6586 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6587 output_asm_insn (".cplocal %+", 0);
6590 /* Return the style of GP load sequence that is being used for the
6591 current function. */
6593 enum mips_loadgp_style
6594 mips_current_loadgp_style (void)
6596 if (!TARGET_ABICALLS || cfun->machine->global_pointer == 0)
6599 if (TARGET_ABSOLUTE_ABICALLS)
6600 return LOADGP_ABSOLUTE;
6602 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6605 /* The __gnu_local_gp symbol. */
6607 static GTY(()) rtx mips_gnu_local_gp;
6609 /* If we're generating n32 or n64 abicalls, emit instructions
6610 to set up the global pointer. */
6613 mips_emit_loadgp (void)
6615 rtx addr, offset, incoming_address;
6617 switch (mips_current_loadgp_style ())
6619 case LOADGP_ABSOLUTE:
6620 if (mips_gnu_local_gp == NULL)
6622 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
6623 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
6625 emit_insn (gen_loadgp_noshared (mips_gnu_local_gp));
6629 addr = XEXP (DECL_RTL (current_function_decl), 0);
6630 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6631 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6632 emit_insn (gen_loadgp (offset, incoming_address));
6633 if (!TARGET_EXPLICIT_RELOCS)
6634 emit_insn (gen_loadgp_blockage ());
6642 /* Set up the stack and frame (if desired) for the function. */
6645 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6648 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6650 #ifdef SDB_DEBUGGING_INFO
6651 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6652 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6655 /* In mips16 mode, we may need to generate a 32 bit to handle
6656 floating point arguments. The linker will arrange for any 32 bit
6657 functions to call this stub, which will then jump to the 16 bit
6659 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6660 && current_function_args_info.fp_code != 0)
6661 build_mips16_function_stub (file);
6663 if (!FUNCTION_NAME_ALREADY_DECLARED)
6665 /* Get the function name the same way that toplev.c does before calling
6666 assemble_start_function. This is needed so that the name used here
6667 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6668 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6670 if (!flag_inhibit_size_directive)
6672 fputs ("\t.ent\t", file);
6673 assemble_name (file, fnname);
6677 assemble_name (file, fnname);
6678 fputs (":\n", file);
6681 /* Stop mips_file_end from treating this function as external. */
6682 if (TARGET_IRIX && mips_abi == ABI_32)
6683 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6685 if (!flag_inhibit_size_directive)
6687 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6689 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6690 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6691 ", args= " HOST_WIDE_INT_PRINT_DEC
6692 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6693 (reg_names[(frame_pointer_needed)
6694 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6695 ((frame_pointer_needed && TARGET_MIPS16)
6696 ? tsize - cfun->machine->frame.args_size
6698 reg_names[GP_REG_FIRST + 31],
6699 cfun->machine->frame.var_size,
6700 cfun->machine->frame.num_gp,
6701 cfun->machine->frame.num_fp,
6702 cfun->machine->frame.args_size,
6703 cfun->machine->frame.cprestore_size);
6705 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6706 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6707 cfun->machine->frame.mask,
6708 cfun->machine->frame.gp_save_offset);
6709 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6710 cfun->machine->frame.fmask,
6711 cfun->machine->frame.fp_save_offset);
6714 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6715 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6718 if (mips_current_loadgp_style () == LOADGP_OLDABI)
6720 /* Handle the initialization of $gp for SVR4 PIC. */
6721 if (!cfun->machine->all_noreorder_p)
6722 output_asm_insn ("%(.cpload\t%^%)", 0);
6724 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6726 else if (cfun->machine->all_noreorder_p)
6727 output_asm_insn ("%(%<", 0);
6729 /* Tell the assembler which register we're using as the global
6730 pointer. This is needed for thunks, since they can use either
6731 explicit relocs or assembler macros. */
6732 mips_output_cplocal ();
6735 /* Make the last instruction frame related and note that it performs
6736 the operation described by FRAME_PATTERN. */
6739 mips_set_frame_expr (rtx frame_pattern)
6743 insn = get_last_insn ();
6744 RTX_FRAME_RELATED_P (insn) = 1;
6745 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6751 /* Return a frame-related rtx that stores REG at MEM.
6752 REG must be a single register. */
6755 mips_frame_set (rtx mem, rtx reg)
6759 /* If we're saving the return address register and the dwarf return
6760 address column differs from the hard register number, adjust the
6761 note reg to refer to the former. */
6762 if (REGNO (reg) == GP_REG_FIRST + 31
6763 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6764 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6766 set = gen_rtx_SET (VOIDmode, mem, reg);
6767 RTX_FRAME_RELATED_P (set) = 1;
6773 /* Save register REG to MEM. Make the instruction frame-related. */
6776 mips_save_reg (rtx reg, rtx mem)
6778 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6782 if (mips_split_64bit_move_p (mem, reg))
6783 mips_split_64bit_move (mem, reg);
6785 emit_move_insn (mem, reg);
6787 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6788 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6789 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6794 && REGNO (reg) != GP_REG_FIRST + 31
6795 && !M16_REG_P (REGNO (reg)))
6797 /* Save a non-mips16 register by moving it through a temporary.
6798 We don't need to do this for $31 since there's a special
6799 instruction for it. */
6800 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6801 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6804 emit_move_insn (mem, reg);
6806 mips_set_frame_expr (mips_frame_set (mem, reg));
6811 /* Expand the prologue into a bunch of separate insns. */
6814 mips_expand_prologue (void)
6818 if (cfun->machine->global_pointer > 0)
6819 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6821 size = compute_frame_size (get_frame_size ());
6823 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6824 bytes beforehand; this is enough to cover the register save area
6825 without going out of range. */
6826 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6828 HOST_WIDE_INT step1;
6830 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6831 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6833 GEN_INT (-step1)))) = 1;
6835 mips_for_each_saved_reg (size, mips_save_reg);
6838 /* Allocate the rest of the frame. */
6841 if (SMALL_OPERAND (-size))
6842 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6844 GEN_INT (-size)))) = 1;
6847 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6850 /* There are no instructions to add or subtract registers
6851 from the stack pointer, so use the frame pointer as a
6852 temporary. We should always be using a frame pointer
6853 in this case anyway. */
6854 gcc_assert (frame_pointer_needed);
6855 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6856 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6857 hard_frame_pointer_rtx,
6858 MIPS_PROLOGUE_TEMP (Pmode)));
6859 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6862 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6864 MIPS_PROLOGUE_TEMP (Pmode)));
6866 /* Describe the combined effect of the previous instructions. */
6868 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6869 plus_constant (stack_pointer_rtx, -size)));
6873 /* Set up the frame pointer, if we're using one. In mips16 code,
6874 we point the frame pointer ahead of the outgoing argument area.
6875 This should allow more variables & incoming arguments to be
6876 accessed with unextended instructions. */
6877 if (frame_pointer_needed)
6879 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6881 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6882 if (SMALL_OPERAND (cfun->machine->frame.args_size))
6884 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6889 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
6890 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6891 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6892 hard_frame_pointer_rtx,
6893 MIPS_PROLOGUE_TEMP (Pmode)));
6895 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
6896 plus_constant (stack_pointer_rtx,
6897 cfun->machine->frame.args_size)));
6901 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6902 stack_pointer_rtx)) = 1;
6905 mips_emit_loadgp ();
6907 /* If generating o32/o64 abicalls, save $gp on the stack. */
6908 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6909 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6911 /* If we are profiling, make sure no instructions are scheduled before
6912 the call to mcount. */
6914 if (current_function_profile)
6915 emit_insn (gen_blockage ());
6918 /* Do any necessary cleanup after a function to restore stack, frame,
6921 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6924 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6925 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6927 /* Reinstate the normal $gp. */
6928 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6929 mips_output_cplocal ();
6931 if (cfun->machine->all_noreorder_p)
6933 /* Avoid using %>%) since it adds excess whitespace. */
6934 output_asm_insn (".set\tmacro", 0);
6935 output_asm_insn (".set\treorder", 0);
6936 set_noreorder = set_nomacro = 0;
6939 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6943 /* Get the function name the same way that toplev.c does before calling
6944 assemble_start_function. This is needed so that the name used here
6945 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6946 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6947 fputs ("\t.end\t", file);
6948 assemble_name (file, fnname);
6953 /* Emit instructions to restore register REG from slot MEM. */
6956 mips_restore_reg (rtx reg, rtx mem)
6958 /* There's no mips16 instruction to load $31 directly. Load into
6959 $7 instead and adjust the return insn appropriately. */
6960 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6961 reg = gen_rtx_REG (GET_MODE (reg), 7);
6963 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6965 /* Can't restore directly; move through a temporary. */
6966 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6967 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6970 emit_move_insn (reg, mem);
6974 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6975 if this epilogue precedes a sibling call, false if it is for a normal
6976 "epilogue" pattern. */
6979 mips_expand_epilogue (int sibcall_p)
6981 HOST_WIDE_INT step1, step2;
6984 if (!sibcall_p && mips_can_use_return_insn ())
6986 emit_jump_insn (gen_return ());
6990 /* Split the frame into two. STEP1 is the amount of stack we should
6991 deallocate before restoring the registers. STEP2 is the amount we
6992 should deallocate afterwards.
6994 Start off by assuming that no registers need to be restored. */
6995 step1 = cfun->machine->frame.total_size;
6998 /* Work out which register holds the frame address. Account for the
6999 frame pointer offset used by mips16 code. */
7000 if (!frame_pointer_needed)
7001 base = stack_pointer_rtx;
7004 base = hard_frame_pointer_rtx;
7006 step1 -= cfun->machine->frame.args_size;
7009 /* If we need to restore registers, deallocate as much stack as
7010 possible in the second step without going out of range. */
7011 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7013 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7017 /* Set TARGET to BASE + STEP1. */
7023 /* Get an rtx for STEP1 that we can add to BASE. */
7024 adjust = GEN_INT (step1);
7025 if (!SMALL_OPERAND (step1))
7027 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7028 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7031 /* Normal mode code can copy the result straight into $sp. */
7033 target = stack_pointer_rtx;
7035 emit_insn (gen_add3_insn (target, base, adjust));
7038 /* Copy TARGET into the stack pointer. */
7039 if (target != stack_pointer_rtx)
7040 emit_move_insn (stack_pointer_rtx, target);
7042 /* If we're using addressing macros for n32/n64 abicalls, $gp is
7043 implicitly used by all SYMBOL_REFs. We must emit a blockage
7044 insn before restoring it. */
7045 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
7046 emit_insn (gen_blockage ());
7048 /* Restore the registers. */
7049 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7052 /* Deallocate the final bit of the frame. */
7054 emit_insn (gen_add3_insn (stack_pointer_rtx,
7058 /* Add in the __builtin_eh_return stack adjustment. We need to
7059 use a temporary in mips16 code. */
7060 if (current_function_calls_eh_return)
7064 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7065 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7066 MIPS_EPILOGUE_TEMP (Pmode),
7067 EH_RETURN_STACKADJ_RTX));
7068 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7071 emit_insn (gen_add3_insn (stack_pointer_rtx,
7073 EH_RETURN_STACKADJ_RTX));
7078 /* The mips16 loads the return address into $7, not $31. */
7079 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7080 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7081 GP_REG_FIRST + 7)));
7083 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7084 GP_REG_FIRST + 31)));
7088 /* Return nonzero if this function is known to have a null epilogue.
7089 This allows the optimizer to omit jumps to jumps if no stack
7093 mips_can_use_return_insn (void)
7097 if (! reload_completed)
7100 if (regs_ever_live[31] || current_function_profile)
7103 return_type = DECL_RESULT (current_function_decl);
7105 /* In mips16 mode, a function which returns a floating point value
7106 needs to arrange to copy the return value into the floating point
7109 && mips16_hard_float
7110 && ! aggregate_value_p (return_type, current_function_decl)
7111 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7112 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7115 if (cfun->machine->frame.initialized)
7116 return cfun->machine->frame.total_size == 0;
7118 return compute_frame_size (get_frame_size ()) == 0;
7121 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7122 in order to avoid duplicating too much logic from elsewhere. */
7125 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7126 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7129 rtx this, temp1, temp2, insn, fnaddr;
7131 /* Pretend to be a post-reload pass while generating rtl. */
7133 reload_completed = 1;
7134 reset_block_changes ();
7136 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7137 for TARGET_NEWABI since the latter is a call-saved register. */
7138 if (TARGET_ABICALLS)
7139 cfun->machine->global_pointer
7140 = REGNO (pic_offset_table_rtx)
7141 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7143 /* Set up the global pointer for n32 or n64 abicalls. */
7144 mips_emit_loadgp ();
7146 /* We need two temporary registers in some cases. */
7147 temp1 = gen_rtx_REG (Pmode, 2);
7148 temp2 = gen_rtx_REG (Pmode, 3);
7150 /* Find out which register contains the "this" pointer. */
7151 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7152 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7154 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7156 /* Add DELTA to THIS. */
7159 rtx offset = GEN_INT (delta);
7160 if (!SMALL_OPERAND (delta))
7162 emit_move_insn (temp1, offset);
7165 emit_insn (gen_add3_insn (this, this, offset));
7168 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7169 if (vcall_offset != 0)
7173 /* Set TEMP1 to *THIS. */
7174 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7176 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7177 addr = mips_add_offset (temp2, temp1, vcall_offset);
7179 /* Load the offset and add it to THIS. */
7180 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7181 emit_insn (gen_add3_insn (this, this, temp1));
7184 /* Jump to the target function. Use a sibcall if direct jumps are
7185 allowed, otherwise load the address into a register first. */
7186 fnaddr = XEXP (DECL_RTL (function), 0);
7187 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7189 /* This is messy. gas treats "la $25,foo" as part of a call
7190 sequence and may allow a global "foo" to be lazily bound.
7191 The general move patterns therefore reject this combination.
7193 In this context, lazy binding would actually be OK for o32 and o64,
7194 but it's still wrong for n32 and n64; see mips_load_call_address.
7195 We must therefore load the address via a temporary register if
7196 mips_dangerous_for_la25_p.
7198 If we jump to the temporary register rather than $25, the assembler
7199 can use the move insn to fill the jump's delay slot. */
7200 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7201 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7202 mips_load_call_address (temp1, fnaddr, true);
7204 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7205 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7206 emit_jump_insn (gen_indirect_jump (temp1));
7210 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7211 SIBLING_CALL_P (insn) = 1;
7214 /* Run just enough of rest_of_compilation. This sequence was
7215 "borrowed" from alpha.c. */
7216 insn = get_insns ();
7217 insn_locators_initialize ();
7218 split_all_insns_noflow ();
7220 mips16_lay_out_constants ();
7221 shorten_branches (insn);
7222 final_start_function (insn, file, 1);
7223 final (insn, file, 1);
7224 final_end_function ();
7226 /* Clean up the vars set above. Note that final_end_function resets
7227 the global pointer for us. */
7228 reload_completed = 0;
7232 /* Returns nonzero if X contains a SYMBOL_REF. */
7235 symbolic_expression_p (rtx x)
7237 if (GET_CODE (x) == SYMBOL_REF)
7240 if (GET_CODE (x) == CONST)
7241 return symbolic_expression_p (XEXP (x, 0));
7244 return symbolic_expression_p (XEXP (x, 0));
7246 if (ARITHMETIC_P (x))
7247 return (symbolic_expression_p (XEXP (x, 0))
7248 || symbolic_expression_p (XEXP (x, 1)));
7253 /* Choose the section to use for the constant rtx expression X that has
7257 mips_select_rtx_section (enum machine_mode mode, rtx x,
7258 unsigned HOST_WIDE_INT align)
7262 /* In mips16 mode, the constant table always goes in the same section
7263 as the function, so that constants can be loaded using PC relative
7265 return function_section (current_function_decl);
7267 else if (TARGET_EMBEDDED_DATA)
7269 /* For embedded applications, always put constants in read-only data,
7270 in order to reduce RAM usage. */
7271 return mergeable_constant_section (mode, align, 0);
7275 /* For hosted applications, always put constants in small data if
7276 possible, as this gives the best performance. */
7277 /* ??? Consider using mergeable small data sections. */
7279 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7280 && mips_section_threshold > 0)
7281 return get_named_section (NULL, ".sdata", 0);
7282 else if (flag_pic && symbolic_expression_p (x))
7283 return get_named_section (NULL, ".data.rel.ro", 3);
7285 return mergeable_constant_section (mode, align, 0);
7289 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7291 The complication here is that, with the combination TARGET_ABICALLS
7292 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7293 therefore not be included in the read-only part of a DSO. Handle such
7294 cases by selecting a normal data section instead of a read-only one.
7295 The logic apes that in default_function_rodata_section. */
7298 mips_function_rodata_section (tree decl)
7300 if (!TARGET_ABICALLS || TARGET_GPWORD)
7301 return default_function_rodata_section (decl);
7303 if (decl && DECL_SECTION_NAME (decl))
7305 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7306 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7308 char *rname = ASTRDUP (name);
7310 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7312 else if (flag_function_sections && flag_data_sections
7313 && strncmp (name, ".text.", 6) == 0)
7315 char *rname = ASTRDUP (name);
7316 memcpy (rname + 1, "data", 4);
7317 return get_section (rname, SECTION_WRITE, decl);
7320 return data_section;
7323 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
7324 locally-defined objects go in a small data section. It also controls
7325 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
7326 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
7329 mips_in_small_data_p (tree decl)
7333 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7336 /* We don't yet generate small-data references for -mabicalls. See related
7337 -G handling in override_options. */
7338 if (TARGET_ABICALLS)
7341 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7345 /* Reject anything that isn't in a known small-data section. */
7346 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7347 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7350 /* If a symbol is defined externally, the assembler will use the
7351 usual -G rules when deciding how to implement macros. */
7352 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7355 else if (TARGET_EMBEDDED_DATA)
7357 /* Don't put constants into the small data section: we want them
7358 to be in ROM rather than RAM. */
7359 if (TREE_CODE (decl) != VAR_DECL)
7362 if (TREE_READONLY (decl)
7363 && !TREE_SIDE_EFFECTS (decl)
7364 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7368 size = int_size_in_bytes (TREE_TYPE (decl));
7369 return (size > 0 && size <= mips_section_threshold);
7372 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7373 anchors for small data: the GP register acts as an anchor in that
7374 case. We also don't want to use them for PC-relative accesses,
7375 where the PC acts as an anchor. */
7378 mips_use_anchors_for_symbol_p (rtx symbol)
7380 switch (mips_classify_symbol (symbol))
7382 case SYMBOL_CONSTANT_POOL:
7383 case SYMBOL_SMALL_DATA:
7391 /* See whether VALTYPE is a record whose fields should be returned in
7392 floating-point registers. If so, return the number of fields and
7393 list them in FIELDS (which should have two elements). Return 0
7396 For n32 & n64, a structure with one or two fields is returned in
7397 floating-point registers as long as every field has a floating-point
7401 mips_fpr_return_fields (tree valtype, tree *fields)
7409 if (TREE_CODE (valtype) != RECORD_TYPE)
7413 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7415 if (TREE_CODE (field) != FIELD_DECL)
7418 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7424 fields[i++] = field;
7430 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7431 a value in the most significant part of $2/$3 if:
7433 - the target is big-endian;
7435 - the value has a structure or union type (we generalize this to
7436 cover aggregates from other languages too); and
7438 - the structure is not returned in floating-point registers. */
7441 mips_return_in_msb (tree valtype)
7445 return (TARGET_NEWABI
7446 && TARGET_BIG_ENDIAN
7447 && AGGREGATE_TYPE_P (valtype)
7448 && mips_fpr_return_fields (valtype, fields) == 0);
7452 /* Return a composite value in a pair of floating-point registers.
7453 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7454 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7457 For n32 & n64, $f0 always holds the first value and $f2 the second.
7458 Otherwise the values are packed together as closely as possible. */
7461 mips_return_fpr_pair (enum machine_mode mode,
7462 enum machine_mode mode1, HOST_WIDE_INT offset1,
7463 enum machine_mode mode2, HOST_WIDE_INT offset2)
7467 inc = (TARGET_NEWABI ? 2 : FP_INC);
7468 return gen_rtx_PARALLEL
7471 gen_rtx_EXPR_LIST (VOIDmode,
7472 gen_rtx_REG (mode1, FP_RETURN),
7474 gen_rtx_EXPR_LIST (VOIDmode,
7475 gen_rtx_REG (mode2, FP_RETURN + inc),
7476 GEN_INT (offset2))));
7481 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7482 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7483 VALTYPE is null and MODE is the mode of the return value. */
7486 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7487 enum machine_mode mode)
7494 mode = TYPE_MODE (valtype);
7495 unsignedp = TYPE_UNSIGNED (valtype);
7497 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7498 true, we must promote the mode just as PROMOTE_MODE does. */
7499 mode = promote_mode (valtype, mode, &unsignedp, 1);
7501 /* Handle structures whose fields are returned in $f0/$f2. */
7502 switch (mips_fpr_return_fields (valtype, fields))
7505 return gen_rtx_REG (mode, FP_RETURN);
7508 return mips_return_fpr_pair (mode,
7509 TYPE_MODE (TREE_TYPE (fields[0])),
7510 int_byte_position (fields[0]),
7511 TYPE_MODE (TREE_TYPE (fields[1])),
7512 int_byte_position (fields[1]));
7515 /* If a value is passed in the most significant part of a register, see
7516 whether we have to round the mode up to a whole number of words. */
7517 if (mips_return_in_msb (valtype))
7519 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7520 if (size % UNITS_PER_WORD != 0)
7522 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7523 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7527 /* For EABI, the class of return register depends entirely on MODE.
7528 For example, "struct { some_type x; }" and "union { some_type x; }"
7529 are returned in the same way as a bare "some_type" would be.
7530 Other ABIs only use FPRs for scalar, complex or vector types. */
7531 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7532 return gen_rtx_REG (mode, GP_RETURN);
7535 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7536 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7537 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7538 return gen_rtx_REG (mode, FP_RETURN);
7540 /* Handle long doubles for n32 & n64. */
7542 return mips_return_fpr_pair (mode,
7544 DImode, GET_MODE_SIZE (mode) / 2);
7546 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7547 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7548 return mips_return_fpr_pair (mode,
7549 GET_MODE_INNER (mode), 0,
7550 GET_MODE_INNER (mode),
7551 GET_MODE_SIZE (mode) / 2);
7553 return gen_rtx_REG (mode, GP_RETURN);
7556 /* Return nonzero when an argument must be passed by reference. */
7559 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7560 enum machine_mode mode, tree type,
7561 bool named ATTRIBUTE_UNUSED)
7563 if (mips_abi == ABI_EABI)
7567 /* ??? How should SCmode be handled? */
7568 if (mode == DImode || mode == DFmode)
7571 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
7572 return size == -1 || size > UNITS_PER_WORD;
7576 /* If we have a variable-sized parameter, we have no choice. */
7577 return targetm.calls.must_pass_in_stack (mode, type);
7582 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7583 enum machine_mode mode ATTRIBUTE_UNUSED,
7584 tree type ATTRIBUTE_UNUSED, bool named)
7586 return mips_abi == ABI_EABI && named;
7589 /* Return true if registers of class CLASS cannot change from mode FROM
7593 mips_cannot_change_mode_class (enum machine_mode from,
7594 enum machine_mode to, enum reg_class class)
7596 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7597 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7599 if (TARGET_BIG_ENDIAN)
7601 /* When a multi-word value is stored in paired floating-point
7602 registers, the first register always holds the low word.
7603 We therefore can't allow FPRs to change between single-word
7604 and multi-word modes. */
7605 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7610 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7611 in LO and HI, the high word always comes first. We therefore
7612 can't allow values stored in HI to change between single-word
7613 and multi-word modes.
7614 This rule applies to both the original HI/LO pair and the new
7615 DSP accumulators. */
7616 if (reg_classes_intersect_p (ACC_REGS, class))
7620 /* Loading a 32-bit value into a 64-bit floating-point register
7621 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7622 We can't allow 64-bit float registers to change from SImode to
7626 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7627 && reg_classes_intersect_p (FP_REGS, class))
7632 /* Return true if X should not be moved directly into register $25.
7633 We need this because many versions of GAS will treat "la $25,foo" as
7634 part of a call sequence and so allow a global "foo" to be lazily bound. */
7637 mips_dangerous_for_la25_p (rtx x)
7639 HOST_WIDE_INT offset;
7641 if (TARGET_EXPLICIT_RELOCS)
7644 mips_split_const (x, &x, &offset);
7645 return global_got_operand (x, VOIDmode);
7648 /* Implement PREFERRED_RELOAD_CLASS. */
7651 mips_preferred_reload_class (rtx x, enum reg_class class)
7653 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7656 if (TARGET_HARD_FLOAT
7657 && FLOAT_MODE_P (GET_MODE (x))
7658 && reg_class_subset_p (FP_REGS, class))
7661 if (reg_class_subset_p (GR_REGS, class))
7664 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7670 /* This function returns the register class required for a secondary
7671 register when copying between one of the registers in CLASS, and X,
7672 using MODE. If IN_P is nonzero, the copy is going from X to the
7673 register, otherwise the register is the source. A return value of
7674 NO_REGS means that no secondary register is required. */
7677 mips_secondary_reload_class (enum reg_class class,
7678 enum machine_mode mode, rtx x, int in_p)
7680 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7684 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7685 regno = true_regnum (x);
7687 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7689 if (mips_dangerous_for_la25_p (x))
7692 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7696 /* Copying from HI or LO to anywhere other than a general register
7697 requires a general register.
7698 This rule applies to both the original HI/LO pair and the new
7699 DSP accumulators. */
7700 if (reg_class_subset_p (class, ACC_REGS))
7702 if (TARGET_MIPS16 && in_p)
7704 /* We can't really copy to HI or LO at all in mips16 mode. */
7707 return gp_reg_p ? NO_REGS : gr_regs;
7709 if (ACC_REG_P (regno))
7711 if (TARGET_MIPS16 && ! in_p)
7713 /* We can't really copy to HI or LO at all in mips16 mode. */
7716 return class == gr_regs ? NO_REGS : gr_regs;
7719 /* We can only copy a value to a condition code register from a
7720 floating point register, and even then we require a scratch
7721 floating point register. We can only copy a value out of a
7722 condition code register into a general register. */
7723 if (class == ST_REGS)
7727 return gp_reg_p ? NO_REGS : gr_regs;
7729 if (ST_REG_P (regno))
7733 return class == gr_regs ? NO_REGS : gr_regs;
7736 if (class == FP_REGS)
7740 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7743 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7745 /* We can use the l.s and l.d macros to load floating-point
7746 constants. ??? For l.s, we could probably get better
7747 code by returning GR_REGS here. */
7750 else if (gp_reg_p || x == CONST0_RTX (mode))
7752 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7755 else if (FP_REG_P (regno))
7757 /* In this case we can use mov.s or mov.d. */
7762 /* Otherwise, we need to reload through an integer register. */
7767 /* In mips16 mode, going between memory and anything but M16_REGS
7768 requires an M16_REG. */
7771 if (class != M16_REGS && class != M16_NA_REGS)
7779 if (class == M16_REGS || class == M16_NA_REGS)
7788 /* Implement CLASS_MAX_NREGS.
7790 Usually all registers are word-sized. The only supported exception
7791 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7792 registers. A word-based calculation is correct even in that case,
7793 since -msingle-float disallows multi-FPR values.
7795 The FP status registers are an exception to this rule. They are always
7796 4 bytes wide as they only hold condition code modes, and CCmode is always
7797 considered to be 4 bytes wide. */
7800 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7801 enum machine_mode mode)
7803 if (class == ST_REGS)
7804 return (GET_MODE_SIZE (mode) + 3) / 4;
7806 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7810 mips_valid_pointer_mode (enum machine_mode mode)
7812 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7815 /* Target hook for vector_mode_supported_p. */
7818 mips_vector_mode_supported_p (enum machine_mode mode)
7823 return TARGET_PAIRED_SINGLE_FLOAT;
7834 /* If we can access small data directly (using gp-relative relocation
7835 operators) return the small data pointer, otherwise return null.
7837 For each mips16 function which refers to GP relative symbols, we
7838 use a pseudo register, initialized at the start of the function, to
7839 hold the $gp value. */
7842 mips16_gp_pseudo_reg (void)
7844 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7849 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7851 /* We want to initialize this to a value which gcc will believe
7854 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7855 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7856 gen_rtx_CONST (Pmode, unspec));
7857 insn = get_insns ();
7860 push_topmost_sequence ();
7861 /* We need to emit the initialization after the FUNCTION_BEG
7862 note, so that it will be integrated. */
7863 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7865 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7867 if (scan == NULL_RTX)
7868 scan = get_insns ();
7869 insn = emit_insn_after (insn, scan);
7870 pop_topmost_sequence ();
7873 return cfun->machine->mips16_gp_pseudo_rtx;
7876 /* Write out code to move floating point arguments in or out of
7877 general registers. Output the instructions to FILE. FP_CODE is
7878 the code describing which arguments are present (see the comment at
7879 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7880 we are copying from the floating point registers. */
7883 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7889 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7890 gcc_assert (TARGET_OLDABI);
7896 gparg = GP_ARG_FIRST;
7897 fparg = FP_ARG_FIRST;
7898 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7902 if ((fparg & 1) != 0)
7904 fprintf (file, "\t%s\t%s,%s\n", s,
7905 reg_names[gparg], reg_names[fparg]);
7907 else if ((f & 3) == 2)
7910 fprintf (file, "\td%s\t%s,%s\n", s,
7911 reg_names[gparg], reg_names[fparg]);
7914 if ((fparg & 1) != 0)
7916 if (TARGET_BIG_ENDIAN)
7917 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7918 reg_names[gparg], reg_names[fparg + 1], s,
7919 reg_names[gparg + 1], reg_names[fparg]);
7921 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7922 reg_names[gparg], reg_names[fparg], s,
7923 reg_names[gparg + 1], reg_names[fparg + 1]);
7936 /* Build a mips16 function stub. This is used for functions which
7937 take arguments in the floating point registers. It is 32 bit code
7938 that moves the floating point args into the general registers, and
7939 then jumps to the 16 bit code. */
7942 build_mips16_function_stub (FILE *file)
7945 char *secname, *stubname;
7946 tree stubid, stubdecl;
7950 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7951 secname = (char *) alloca (strlen (fnname) + 20);
7952 sprintf (secname, ".mips16.fn.%s", fnname);
7953 stubname = (char *) alloca (strlen (fnname) + 20);
7954 sprintf (stubname, "__fn_stub_%s", fnname);
7955 stubid = get_identifier (stubname);
7956 stubdecl = build_decl (FUNCTION_DECL, stubid,
7957 build_function_type (void_type_node, NULL_TREE));
7958 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7960 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7962 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7964 fprintf (file, "%s%s",
7965 need_comma ? ", " : "",
7966 (f & 3) == 1 ? "float" : "double");
7969 fprintf (file, ")\n");
7971 fprintf (file, "\t.set\tnomips16\n");
7972 switch_to_section (function_section (stubdecl));
7973 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7975 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7976 within a .ent, and we cannot emit another .ent. */
7977 if (!FUNCTION_NAME_ALREADY_DECLARED)
7979 fputs ("\t.ent\t", file);
7980 assemble_name (file, stubname);
7984 assemble_name (file, stubname);
7985 fputs (":\n", file);
7987 /* We don't want the assembler to insert any nops here. */
7988 fprintf (file, "\t.set\tnoreorder\n");
7990 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7992 fprintf (asm_out_file, "\t.set\tnoat\n");
7993 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7994 assemble_name (file, fnname);
7995 fprintf (file, "\n");
7996 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7997 fprintf (asm_out_file, "\t.set\tat\n");
7999 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8000 with one of the mfc1 instructions, because the result is not
8001 available for one instruction, so if the very first instruction
8002 in the function refers to the register, it will see the wrong
8004 fprintf (file, "\tnop\n");
8006 fprintf (file, "\t.set\treorder\n");
8008 if (!FUNCTION_NAME_ALREADY_DECLARED)
8010 fputs ("\t.end\t", file);
8011 assemble_name (file, stubname);
8015 fprintf (file, "\t.set\tmips16\n");
8017 switch_to_section (function_section (current_function_decl));
8020 /* We keep a list of functions for which we have already built stubs
8021 in build_mips16_call_stub. */
8025 struct mips16_stub *next;
8030 static struct mips16_stub *mips16_stubs;
8032 /* Build a call stub for a mips16 call. A stub is needed if we are
8033 passing any floating point values which should go into the floating
8034 point registers. If we are, and the call turns out to be to a 32
8035 bit function, the stub will be used to move the values into the
8036 floating point registers before calling the 32 bit function. The
8037 linker will magically adjust the function call to either the 16 bit
8038 function or the 32 bit stub, depending upon where the function call
8039 is actually defined.
8041 Similarly, we need a stub if the return value might come back in a
8042 floating point register.
8044 RETVAL is the location of the return value, or null if this is
8045 a call rather than a call_value. FN is the address of the
8046 function and ARG_SIZE is the size of the arguments. FP_CODE
8047 is the code built by function_arg. This function returns a nonzero
8048 value if it builds the call instruction itself. */
8051 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8055 char *secname, *stubname;
8056 struct mips16_stub *l;
8057 tree stubid, stubdecl;
8061 /* We don't need to do anything if we aren't in mips16 mode, or if
8062 we were invoked with the -msoft-float option. */
8063 if (! TARGET_MIPS16 || ! mips16_hard_float)
8066 /* Figure out whether the value might come back in a floating point
8068 fpret = (retval != 0
8069 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8070 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8072 /* We don't need to do anything if there were no floating point
8073 arguments and the value will not be returned in a floating point
8075 if (fp_code == 0 && ! fpret)
8078 /* We don't need to do anything if this is a call to a special
8079 mips16 support function. */
8080 if (GET_CODE (fn) == SYMBOL_REF
8081 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8084 /* This code will only work for o32 and o64 abis. The other ABI's
8085 require more sophisticated support. */
8086 gcc_assert (TARGET_OLDABI);
8088 /* We can only handle SFmode and DFmode floating point return
8091 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
8093 /* If we're calling via a function pointer, then we must always call
8094 via a stub. There are magic stubs provided in libgcc.a for each
8095 of the required cases. Each of them expects the function address
8096 to arrive in register $2. */
8098 if (GET_CODE (fn) != SYMBOL_REF)
8104 /* ??? If this code is modified to support other ABI's, we need
8105 to handle PARALLEL return values here. */
8107 sprintf (buf, "__mips16_call_stub_%s%d",
8109 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8112 id = get_identifier (buf);
8113 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8115 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8117 if (retval == NULL_RTX)
8118 insn = gen_call_internal (stub_fn, arg_size);
8120 insn = gen_call_value_internal (retval, stub_fn, arg_size);
8121 insn = emit_call_insn (insn);
8123 /* Put the register usage information on the CALL. */
8124 CALL_INSN_FUNCTION_USAGE (insn) =
8125 gen_rtx_EXPR_LIST (VOIDmode,
8126 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8127 CALL_INSN_FUNCTION_USAGE (insn));
8129 /* If we are handling a floating point return value, we need to
8130 save $18 in the function prologue. Putting a note on the
8131 call will mean that regs_ever_live[$18] will be true if the
8132 call is not eliminated, and we can check that in the prologue
8135 CALL_INSN_FUNCTION_USAGE (insn) =
8136 gen_rtx_EXPR_LIST (VOIDmode,
8137 gen_rtx_USE (VOIDmode,
8138 gen_rtx_REG (word_mode, 18)),
8139 CALL_INSN_FUNCTION_USAGE (insn));
8141 /* Return 1 to tell the caller that we've generated the call
8146 /* We know the function we are going to call. If we have already
8147 built a stub, we don't need to do anything further. */
8149 fnname = XSTR (fn, 0);
8150 for (l = mips16_stubs; l != NULL; l = l->next)
8151 if (strcmp (l->name, fnname) == 0)
8156 /* Build a special purpose stub. When the linker sees a
8157 function call in mips16 code, it will check where the target
8158 is defined. If the target is a 32 bit call, the linker will
8159 search for the section defined here. It can tell which
8160 symbol this section is associated with by looking at the
8161 relocation information (the name is unreliable, since this
8162 might be a static function). If such a section is found, the
8163 linker will redirect the call to the start of the magic
8166 If the function does not return a floating point value, the
8167 special stub section is named
8170 If the function does return a floating point value, the stub
8172 .mips16.call.fp.FNNAME
8175 secname = (char *) alloca (strlen (fnname) + 40);
8176 sprintf (secname, ".mips16.call.%s%s",
8179 stubname = (char *) alloca (strlen (fnname) + 20);
8180 sprintf (stubname, "__call_stub_%s%s",
8183 stubid = get_identifier (stubname);
8184 stubdecl = build_decl (FUNCTION_DECL, stubid,
8185 build_function_type (void_type_node, NULL_TREE));
8186 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8188 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8190 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8194 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8196 fprintf (asm_out_file, "%s%s",
8197 need_comma ? ", " : "",
8198 (f & 3) == 1 ? "float" : "double");
8201 fprintf (asm_out_file, ")\n");
8203 fprintf (asm_out_file, "\t.set\tnomips16\n");
8204 assemble_start_function (stubdecl, stubname);
8206 if (!FUNCTION_NAME_ALREADY_DECLARED)
8208 fputs ("\t.ent\t", asm_out_file);
8209 assemble_name (asm_out_file, stubname);
8210 fputs ("\n", asm_out_file);
8212 assemble_name (asm_out_file, stubname);
8213 fputs (":\n", asm_out_file);
8216 /* We build the stub code by hand. That's the only way we can
8217 do it, since we can't generate 32 bit code during a 16 bit
8220 /* We don't want the assembler to insert any nops here. */
8221 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8223 mips16_fp_args (asm_out_file, fp_code, 0);
8227 fprintf (asm_out_file, "\t.set\tnoat\n");
8228 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8230 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8231 fprintf (asm_out_file, "\t.set\tat\n");
8232 /* Unfortunately, we can't fill the jump delay slot. We
8233 can't fill with one of the mtc1 instructions, because the
8234 result is not available for one instruction, so if the
8235 very first instruction in the function refers to the
8236 register, it will see the wrong value. */
8237 fprintf (asm_out_file, "\tnop\n");
8241 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8242 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8243 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8244 /* As above, we can't fill the delay slot. */
8245 fprintf (asm_out_file, "\tnop\n");
8246 if (GET_MODE (retval) == SFmode)
8247 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8248 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8251 if (TARGET_BIG_ENDIAN)
8253 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8254 reg_names[GP_REG_FIRST + 2],
8255 reg_names[FP_REG_FIRST + 1]);
8256 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8257 reg_names[GP_REG_FIRST + 3],
8258 reg_names[FP_REG_FIRST + 0]);
8262 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8263 reg_names[GP_REG_FIRST + 2],
8264 reg_names[FP_REG_FIRST + 0]);
8265 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8266 reg_names[GP_REG_FIRST + 3],
8267 reg_names[FP_REG_FIRST + 1]);
8270 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8271 /* As above, we can't fill the delay slot. */
8272 fprintf (asm_out_file, "\tnop\n");
8275 fprintf (asm_out_file, "\t.set\treorder\n");
8277 #ifdef ASM_DECLARE_FUNCTION_SIZE
8278 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8281 if (!FUNCTION_NAME_ALREADY_DECLARED)
8283 fputs ("\t.end\t", asm_out_file);
8284 assemble_name (asm_out_file, stubname);
8285 fputs ("\n", asm_out_file);
8288 fprintf (asm_out_file, "\t.set\tmips16\n");
8290 /* Record this stub. */
8291 l = (struct mips16_stub *) xmalloc (sizeof *l);
8292 l->name = xstrdup (fnname);
8294 l->next = mips16_stubs;
8298 /* If we expect a floating point return value, but we've built a
8299 stub which does not expect one, then we're in trouble. We can't
8300 use the existing stub, because it won't handle the floating point
8301 value. We can't build a new stub, because the linker won't know
8302 which stub to use for the various calls in this object file.
8303 Fortunately, this case is illegal, since it means that a function
8304 was declared in two different ways in a single compilation. */
8305 if (fpret && ! l->fpret)
8306 error ("cannot handle inconsistent calls to %qs", fnname);
8308 /* If we are calling a stub which handles a floating point return
8309 value, we need to arrange to save $18 in the prologue. We do
8310 this by marking the function call as using the register. The
8311 prologue will later see that it is used, and emit code to save
8318 if (retval == NULL_RTX)
8319 insn = gen_call_internal (fn, arg_size);
8321 insn = gen_call_value_internal (retval, fn, arg_size);
8322 insn = emit_call_insn (insn);
8324 CALL_INSN_FUNCTION_USAGE (insn) =
8325 gen_rtx_EXPR_LIST (VOIDmode,
8326 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8327 CALL_INSN_FUNCTION_USAGE (insn));
8329 /* Return 1 to tell the caller that we've generated the call
8334 /* Return 0 to let the caller generate the call insn. */
8338 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8339 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8341 struct mips16_constant {
8342 struct mips16_constant *next;
8345 enum machine_mode mode;
8348 /* Information about an incomplete mips16 constant pool. FIRST is the
8349 first constant, HIGHEST_ADDRESS is the highest address that the first
8350 byte of the pool can have, and INSN_ADDRESS is the current instruction
8353 struct mips16_constant_pool {
8354 struct mips16_constant *first;
8355 int highest_address;
8359 /* Add constant VALUE to POOL and return its label. MODE is the
8360 value's mode (used for CONST_INTs, etc.). */
8363 add_constant (struct mips16_constant_pool *pool,
8364 rtx value, enum machine_mode mode)
8366 struct mips16_constant **p, *c;
8367 bool first_of_size_p;
8369 /* See whether the constant is already in the pool. If so, return the
8370 existing label, otherwise leave P pointing to the place where the
8371 constant should be added.
8373 Keep the pool sorted in increasing order of mode size so that we can
8374 reduce the number of alignments needed. */
8375 first_of_size_p = true;
8376 for (p = &pool->first; *p != 0; p = &(*p)->next)
8378 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8380 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8382 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8383 first_of_size_p = false;
8386 /* In the worst case, the constant needed by the earliest instruction
8387 will end up at the end of the pool. The entire pool must then be
8388 accessible from that instruction.
8390 When adding the first constant, set the pool's highest address to
8391 the address of the first out-of-range byte. Adjust this address
8392 downwards each time a new constant is added. */
8393 if (pool->first == 0)
8394 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8395 is the address of the instruction with the lowest two bits clear.
8396 The base PC value for ld has the lowest three bits clear. Assume
8397 the worst case here. */
8398 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8399 pool->highest_address -= GET_MODE_SIZE (mode);
8400 if (first_of_size_p)
8401 /* Take into account the worst possible padding due to alignment. */
8402 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8404 /* Create a new entry. */
8405 c = (struct mips16_constant *) xmalloc (sizeof *c);
8408 c->label = gen_label_rtx ();
8415 /* Output constant VALUE after instruction INSN and return the last
8416 instruction emitted. MODE is the mode of the constant. */
8419 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8421 switch (GET_MODE_CLASS (mode))
8425 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8426 return emit_insn_after (gen_consttable_int (value, size), insn);
8430 return emit_insn_after (gen_consttable_float (value), insn);
8432 case MODE_VECTOR_FLOAT:
8433 case MODE_VECTOR_INT:
8436 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8437 insn = dump_constants_1 (GET_MODE_INNER (mode),
8438 CONST_VECTOR_ELT (value, i), insn);
8448 /* Dump out the constants in CONSTANTS after INSN. */
8451 dump_constants (struct mips16_constant *constants, rtx insn)
8453 struct mips16_constant *c, *next;
8457 for (c = constants; c != NULL; c = next)
8459 /* If necessary, increase the alignment of PC. */
8460 if (align < GET_MODE_SIZE (c->mode))
8462 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8463 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8465 align = GET_MODE_SIZE (c->mode);
8467 insn = emit_label_after (c->label, insn);
8468 insn = dump_constants_1 (c->mode, c->value, insn);
8474 emit_barrier_after (insn);
8477 /* Return the length of instruction INSN. */
8480 mips16_insn_length (rtx insn)
8484 rtx body = PATTERN (insn);
8485 if (GET_CODE (body) == ADDR_VEC)
8486 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8487 if (GET_CODE (body) == ADDR_DIFF_VEC)
8488 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8490 return get_attr_length (insn);
8493 /* Rewrite *X so that constant pool references refer to the constant's
8494 label instead. DATA points to the constant pool structure. */
8497 mips16_rewrite_pool_refs (rtx *x, void *data)
8499 struct mips16_constant_pool *pool = data;
8500 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8501 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8502 get_pool_constant (*x),
8503 get_pool_mode (*x)));
8507 /* Build MIPS16 constant pools. */
8510 mips16_lay_out_constants (void)
8512 struct mips16_constant_pool pool;
8516 memset (&pool, 0, sizeof (pool));
8517 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8519 /* Rewrite constant pool references in INSN. */
8521 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8523 pool.insn_address += mips16_insn_length (insn);
8525 if (pool.first != NULL)
8527 /* If there are no natural barriers between the first user of
8528 the pool and the highest acceptable address, we'll need to
8529 create a new instruction to jump around the constant pool.
8530 In the worst case, this instruction will be 4 bytes long.
8532 If it's too late to do this transformation after INSN,
8533 do it immediately before INSN. */
8534 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8538 label = gen_label_rtx ();
8540 jump = emit_jump_insn_before (gen_jump (label), insn);
8541 JUMP_LABEL (jump) = label;
8542 LABEL_NUSES (label) = 1;
8543 barrier = emit_barrier_after (jump);
8545 emit_label_after (label, barrier);
8546 pool.insn_address += 4;
8549 /* See whether the constant pool is now out of range of the first
8550 user. If so, output the constants after the previous barrier.
8551 Note that any instructions between BARRIER and INSN (inclusive)
8552 will use negative offsets to refer to the pool. */
8553 if (pool.insn_address > pool.highest_address)
8555 dump_constants (pool.first, barrier);
8559 else if (BARRIER_P (insn))
8563 dump_constants (pool.first, get_last_insn ());
8566 /* A temporary variable used by for_each_rtx callbacks, etc. */
8567 static rtx mips_sim_insn;
8569 /* A structure representing the state of the processor pipeline.
8570 Used by the mips_sim_* family of functions. */
8572 /* The maximum number of instructions that can be issued in a cycle.
8573 (Caches mips_issue_rate.) */
8574 unsigned int issue_rate;
8576 /* The current simulation time. */
8579 /* How many more instructions can be issued in the current cycle. */
8580 unsigned int insns_left;
8582 /* LAST_SET[X].INSN is the last instruction to set register X.
8583 LAST_SET[X].TIME is the time at which that instruction was issued.
8584 INSN is null if no instruction has yet set register X. */
8588 } last_set[FIRST_PSEUDO_REGISTER];
8590 /* The pipeline's current DFA state. */
8594 /* Reset STATE to the initial simulation state. */
8597 mips_sim_reset (struct mips_sim *state)
8600 state->insns_left = state->issue_rate;
8601 memset (&state->last_set, 0, sizeof (state->last_set));
8602 state_reset (state->dfa_state);
8605 /* Initialize STATE before its first use. DFA_STATE points to an
8606 allocated but uninitialized DFA state. */
8609 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8611 state->issue_rate = mips_issue_rate ();
8612 state->dfa_state = dfa_state;
8613 mips_sim_reset (state);
8616 /* Advance STATE by one clock cycle. */
8619 mips_sim_next_cycle (struct mips_sim *state)
8622 state->insns_left = state->issue_rate;
8623 state_transition (state->dfa_state, 0);
8626 /* Advance simulation state STATE until instruction INSN can read
8630 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8634 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8635 if (state->last_set[REGNO (reg) + i].insn != 0)
8639 t = state->last_set[REGNO (reg) + i].time;
8640 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8641 while (state->time < t)
8642 mips_sim_next_cycle (state);
8646 /* A for_each_rtx callback. If *X is a register, advance simulation state
8647 DATA until mips_sim_insn can read the register's value. */
8650 mips_sim_wait_regs_2 (rtx *x, void *data)
8653 mips_sim_wait_reg (data, mips_sim_insn, *x);
8657 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8660 mips_sim_wait_regs_1 (rtx *x, void *data)
8662 for_each_rtx (x, mips_sim_wait_regs_2, data);
8665 /* Advance simulation state STATE until all of INSN's register
8666 dependencies are satisfied. */
8669 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8671 mips_sim_insn = insn;
8672 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8675 /* Advance simulation state STATE until the units required by
8676 instruction INSN are available. */
8679 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8683 tmp_state = alloca (state_size ());
8684 while (state->insns_left == 0
8685 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8686 state_transition (tmp_state, insn) >= 0))
8687 mips_sim_next_cycle (state);
8690 /* Advance simulation state STATE until INSN is ready to issue. */
8693 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8695 mips_sim_wait_regs (state, insn);
8696 mips_sim_wait_units (state, insn);
8699 /* mips_sim_insn has just set X. Update the LAST_SET array
8700 in simulation state DATA. */
8703 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8705 struct mips_sim *state;
8710 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8712 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8713 state->last_set[REGNO (x) + i].time = state->time;
8717 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8718 can issue immediately (i.e., that mips_sim_wait_insn has already
8722 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8724 state_transition (state->dfa_state, insn);
8725 state->insns_left--;
8727 mips_sim_insn = insn;
8728 note_stores (PATTERN (insn), mips_sim_record_set, state);
8731 /* Simulate issuing a NOP in state STATE. */
8734 mips_sim_issue_nop (struct mips_sim *state)
8736 if (state->insns_left == 0)
8737 mips_sim_next_cycle (state);
8738 state->insns_left--;
8741 /* Update simulation state STATE so that it's ready to accept the instruction
8742 after INSN. INSN should be part of the main rtl chain, not a member of a
8746 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8748 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8750 mips_sim_issue_nop (state);
8752 switch (GET_CODE (SEQ_BEGIN (insn)))
8756 /* We can't predict the processor state after a call or label. */
8757 mips_sim_reset (state);
8761 /* The delay slots of branch likely instructions are only executed
8762 when the branch is taken. Therefore, if the caller has simulated
8763 the delay slot instruction, STATE does not really reflect the state
8764 of the pipeline for the instruction after the delay slot. Also,
8765 branch likely instructions tend to incur a penalty when not taken,
8766 so there will probably be an extra delay between the branch and
8767 the instruction after the delay slot. */
8768 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8769 mips_sim_reset (state);
8777 /* The VR4130 pipeline issues aligned pairs of instructions together,
8778 but it stalls the second instruction if it depends on the first.
8779 In order to cut down the amount of logic required, this dependence
8780 check is not based on a full instruction decode. Instead, any non-SPECIAL
8781 instruction is assumed to modify the register specified by bits 20-16
8782 (which is usually the "rt" field).
8784 In beq, beql, bne and bnel instructions, the rt field is actually an
8785 input, so we can end up with a false dependence between the branch
8786 and its delay slot. If this situation occurs in instruction INSN,
8787 try to avoid it by swapping rs and rt. */
8790 vr4130_avoid_branch_rt_conflict (rtx insn)
8794 first = SEQ_BEGIN (insn);
8795 second = SEQ_END (insn);
8797 && NONJUMP_INSN_P (second)
8798 && GET_CODE (PATTERN (first)) == SET
8799 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8800 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8802 /* Check for the right kind of condition. */
8803 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8804 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8805 && REG_P (XEXP (cond, 0))
8806 && REG_P (XEXP (cond, 1))
8807 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8808 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8810 /* SECOND mentions the rt register but not the rs register. */
8811 rtx tmp = XEXP (cond, 0);
8812 XEXP (cond, 0) = XEXP (cond, 1);
8813 XEXP (cond, 1) = tmp;
8818 /* Implement -mvr4130-align. Go through each basic block and simulate the
8819 processor pipeline. If we find that a pair of instructions could execute
8820 in parallel, and the first of those instruction is not 8-byte aligned,
8821 insert a nop to make it aligned. */
8824 vr4130_align_insns (void)
8826 struct mips_sim state;
8827 rtx insn, subinsn, last, last2, next;
8832 /* LAST is the last instruction before INSN to have a nonzero length.
8833 LAST2 is the last such instruction before LAST. */
8837 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8840 mips_sim_init (&state, alloca (state_size ()));
8841 for (insn = get_insns (); insn != 0; insn = next)
8843 unsigned int length;
8845 next = NEXT_INSN (insn);
8847 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8848 This isn't really related to the alignment pass, but we do it on
8849 the fly to avoid a separate instruction walk. */
8850 vr4130_avoid_branch_rt_conflict (insn);
8852 if (USEFUL_INSN_P (insn))
8853 FOR_EACH_SUBINSN (subinsn, insn)
8855 mips_sim_wait_insn (&state, subinsn);
8857 /* If we want this instruction to issue in parallel with the
8858 previous one, make sure that the previous instruction is
8859 aligned. There are several reasons why this isn't worthwhile
8860 when the second instruction is a call:
8862 - Calls are less likely to be performance critical,
8863 - There's a good chance that the delay slot can execute
8864 in parallel with the call.
8865 - The return address would then be unaligned.
8867 In general, if we're going to insert a nop between instructions
8868 X and Y, it's better to insert it immediately after X. That
8869 way, if the nop makes Y aligned, it will also align any labels
8871 if (state.insns_left != state.issue_rate
8872 && !CALL_P (subinsn))
8874 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8876 /* SUBINSN is the first instruction in INSN and INSN is
8877 aligned. We want to align the previous instruction
8878 instead, so insert a nop between LAST2 and LAST.
8880 Note that LAST could be either a single instruction
8881 or a branch with a delay slot. In the latter case,
8882 LAST, like INSN, is already aligned, but the delay
8883 slot must have some extra delay that stops it from
8884 issuing at the same time as the branch. We therefore
8885 insert a nop before the branch in order to align its
8887 emit_insn_after (gen_nop (), last2);
8890 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8892 /* SUBINSN is the delay slot of INSN, but INSN is
8893 currently unaligned. Insert a nop between
8894 LAST and INSN to align it. */
8895 emit_insn_after (gen_nop (), last);
8899 mips_sim_issue_insn (&state, subinsn);
8901 mips_sim_finish_insn (&state, insn);
8903 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8904 length = get_attr_length (insn);
8907 /* If the instruction is an asm statement or multi-instruction
8908 mips.md patern, the length is only an estimate. Insert an
8909 8 byte alignment after it so that the following instructions
8910 can be handled correctly. */
8911 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8912 && (recog_memoized (insn) < 0 || length >= 8))
8914 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8915 next = NEXT_INSN (next);
8916 mips_sim_next_cycle (&state);
8919 else if (length & 4)
8920 aligned_p = !aligned_p;
8925 /* See whether INSN is an aligned label. */
8926 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8932 /* Subroutine of mips_reorg. If there is a hazard between INSN
8933 and a previous instruction, avoid it by inserting nops after
8936 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8937 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8938 before using the value of that register. *HILO_DELAY counts the
8939 number of instructions since the last hilo hazard (that is,
8940 the number of instructions since the last mflo or mfhi).
8942 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8943 for the next instruction.
8945 LO_REG is an rtx for the LO register, used in dependence checking. */
8948 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8949 rtx *delayed_reg, rtx lo_reg)
8957 pattern = PATTERN (insn);
8959 /* Do not put the whole function in .set noreorder if it contains
8960 an asm statement. We don't know whether there will be hazards
8961 between the asm statement and the gcc-generated code. */
8962 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8963 cfun->machine->all_noreorder_p = false;
8965 /* Ignore zero-length instructions (barriers and the like). */
8966 ninsns = get_attr_length (insn) / 4;
8970 /* Work out how many nops are needed. Note that we only care about
8971 registers that are explicitly mentioned in the instruction's pattern.
8972 It doesn't matter that calls use the argument registers or that they
8973 clobber hi and lo. */
8974 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8975 nops = 2 - *hilo_delay;
8976 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8981 /* Insert the nops between this instruction and the previous one.
8982 Each new nop takes us further from the last hilo hazard. */
8983 *hilo_delay += nops;
8985 emit_insn_after (gen_hazard_nop (), after);
8987 /* Set up the state for the next instruction. */
8988 *hilo_delay += ninsns;
8990 if (INSN_CODE (insn) >= 0)
8991 switch (get_attr_hazard (insn))
9001 set = single_set (insn);
9002 gcc_assert (set != 0);
9003 *delayed_reg = SET_DEST (set);
9009 /* Go through the instruction stream and insert nops where necessary.
9010 See if the whole function can then be put into .set noreorder &
9014 mips_avoid_hazards (void)
9016 rtx insn, last_insn, lo_reg, delayed_reg;
9019 /* Force all instructions to be split into their final form. */
9020 split_all_insns_noflow ();
9022 /* Recalculate instruction lengths without taking nops into account. */
9023 cfun->machine->ignore_hazard_length_p = true;
9024 shorten_branches (get_insns ());
9026 cfun->machine->all_noreorder_p = true;
9028 /* Profiled functions can't be all noreorder because the profiler
9029 support uses assembler macros. */
9030 if (current_function_profile)
9031 cfun->machine->all_noreorder_p = false;
9033 /* Code compiled with -mfix-vr4120 can't be all noreorder because
9034 we rely on the assembler to work around some errata. */
9035 if (TARGET_FIX_VR4120)
9036 cfun->machine->all_noreorder_p = false;
9038 /* The same is true for -mfix-vr4130 if we might generate mflo or
9039 mfhi instructions. Note that we avoid using mflo and mfhi if
9040 the VR4130 macc and dmacc instructions are available instead;
9041 see the *mfhilo_{si,di}_macc patterns. */
9042 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
9043 cfun->machine->all_noreorder_p = false;
9048 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
9050 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9053 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9054 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9055 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
9056 &hilo_delay, &delayed_reg, lo_reg);
9058 mips_avoid_hazard (last_insn, insn, &hilo_delay,
9059 &delayed_reg, lo_reg);
9066 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
9072 mips16_lay_out_constants ();
9073 else if (TARGET_EXPLICIT_RELOCS)
9075 if (mips_flag_delayed_branch)
9076 dbr_schedule (get_insns ());
9077 mips_avoid_hazards ();
9078 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
9079 vr4130_align_insns ();
9083 /* This function does three things:
9085 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9086 - Register the mips16 hardware floating point stubs.
9087 - Register the gofast functions if selected using --enable-gofast. */
9089 #include "config/gofast.h"
9092 mips_init_libfuncs (void)
9094 if (TARGET_FIX_VR4120)
9096 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9097 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9100 if (TARGET_MIPS16 && mips16_hard_float)
9102 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9103 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9104 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9105 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9107 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9108 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9109 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9110 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9111 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9112 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9114 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9115 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9117 if (TARGET_DOUBLE_FLOAT)
9119 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9120 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9121 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9122 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9124 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9125 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9126 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9127 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9128 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9129 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9131 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
9132 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
9134 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
9135 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
9139 gofast_maybe_init_libfuncs ();
9142 /* Return a number assessing the cost of moving a register in class
9143 FROM to class TO. The classes are expressed using the enumeration
9144 values such as `GENERAL_REGS'. A value of 2 is the default; other
9145 values are interpreted relative to that.
9147 It is not required that the cost always equal 2 when FROM is the
9148 same as TO; on some machines it is expensive to move between
9149 registers if they are not general registers.
9151 If reload sees an insn consisting of a single `set' between two
9152 hard registers, and if `REGISTER_MOVE_COST' applied to their
9153 classes returns a value of 2, reload does not check to ensure that
9154 the constraints of the insn are met. Setting a cost of other than
9155 2 will allow reload to verify that the constraints are met. You
9156 should do this if the `movM' pattern's constraints do not allow
9159 ??? We make the cost of moving from HI/LO into general
9160 registers the same as for one of moving general registers to
9161 HI/LO for TARGET_MIPS16 in order to prevent allocating a
9162 pseudo to HI/LO. This might hurt optimizations though, it
9163 isn't clear if it is wise. And it might not work in all cases. We
9164 could solve the DImode LO reg problem by using a multiply, just
9165 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9166 problem by using divide instructions. divu puts the remainder in
9167 the HI reg, so doing a divide by -1 will move the value in the HI
9168 reg for all values except -1. We could handle that case by using a
9169 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9170 a compare/branch to test the input value to see which instruction
9171 we need to use. This gets pretty messy, but it is feasible. */
9174 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9175 enum reg_class to, enum reg_class from)
9177 if (from == M16_REGS && GR_REG_CLASS_P (to))
9179 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9181 else if (GR_REG_CLASS_P (from))
9185 else if (to == M16_NA_REGS)
9187 else if (GR_REG_CLASS_P (to))
9194 else if (to == FP_REGS)
9196 else if (reg_class_subset_p (to, ACC_REGS))
9203 else if (COP_REG_CLASS_P (to))
9208 else if (from == FP_REGS)
9210 if (GR_REG_CLASS_P (to))
9212 else if (to == FP_REGS)
9214 else if (to == ST_REGS)
9217 else if (reg_class_subset_p (from, ACC_REGS))
9219 if (GR_REG_CLASS_P (to))
9227 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9229 else if (COP_REG_CLASS_P (from))
9235 ??? What cases are these? Shouldn't we return 2 here? */
9240 /* Return the length of INSN. LENGTH is the initial length computed by
9241 attributes in the machine-description file. */
9244 mips_adjust_insn_length (rtx insn, int length)
9246 /* A unconditional jump has an unfilled delay slot if it is not part
9247 of a sequence. A conditional jump normally has a delay slot, but
9248 does not on MIPS16. */
9249 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9252 /* See how many nops might be needed to avoid hardware hazards. */
9253 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9254 switch (get_attr_hazard (insn))
9268 /* All MIPS16 instructions are a measly two bytes. */
9276 /* Return an asm sequence to start a noat block and load the address
9277 of a label into $1. */
9280 mips_output_load_label (void)
9282 if (TARGET_EXPLICIT_RELOCS)
9286 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9289 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9292 if (ISA_HAS_LOAD_DELAY)
9293 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9294 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9298 if (Pmode == DImode)
9299 return "%[dla\t%@,%0";
9301 return "%[la\t%@,%0";
9305 /* Return the assembly code for INSN, which has the operands given by
9306 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9307 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9308 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9309 version of BRANCH_IF_TRUE. */
9312 mips_output_conditional_branch (rtx insn, rtx *operands,
9313 const char *branch_if_true,
9314 const char *branch_if_false)
9316 unsigned int length;
9317 rtx taken, not_taken;
9319 length = get_attr_length (insn);
9322 /* Just a simple conditional branch. */
9323 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9324 return branch_if_true;
9327 /* Generate a reversed branch around a direct jump. This fallback does
9328 not use branch-likely instructions. */
9329 mips_branch_likely = false;
9330 not_taken = gen_label_rtx ();
9331 taken = operands[1];
9333 /* Generate the reversed branch to NOT_TAKEN. */
9334 operands[1] = not_taken;
9335 output_asm_insn (branch_if_false, operands);
9337 /* If INSN has a delay slot, we must provide delay slots for both the
9338 branch to NOT_TAKEN and the conditional jump. We must also ensure
9339 that INSN's delay slot is executed in the appropriate cases. */
9342 /* This first delay slot will always be executed, so use INSN's
9343 delay slot if is not annulled. */
9344 if (!INSN_ANNULLED_BRANCH_P (insn))
9346 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9347 asm_out_file, optimize, 1, NULL);
9348 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9351 output_asm_insn ("nop", 0);
9352 fprintf (asm_out_file, "\n");
9355 /* Output the unconditional branch to TAKEN. */
9357 output_asm_insn ("j\t%0%/", &taken);
9360 output_asm_insn (mips_output_load_label (), &taken);
9361 output_asm_insn ("jr\t%@%]%/", 0);
9364 /* Now deal with its delay slot; see above. */
9367 /* This delay slot will only be executed if the branch is taken.
9368 Use INSN's delay slot if is annulled. */
9369 if (INSN_ANNULLED_BRANCH_P (insn))
9371 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9372 asm_out_file, optimize, 1, NULL);
9373 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9376 output_asm_insn ("nop", 0);
9377 fprintf (asm_out_file, "\n");
9380 /* Output NOT_TAKEN. */
9381 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9382 CODE_LABEL_NUMBER (not_taken));
9386 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9387 if some ordered condition is true. The condition is given by
9388 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9389 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9390 its second is always zero. */
9393 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9395 const char *branch[2];
9397 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9398 Make BRANCH[0] branch on the inverse condition. */
9399 switch (GET_CODE (operands[0]))
9401 /* These cases are equivalent to comparisons against zero. */
9403 inverted_p = !inverted_p;
9406 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9407 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9410 /* These cases are always true or always false. */
9412 inverted_p = !inverted_p;
9415 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9416 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9420 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9421 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9424 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9427 /* Used to output div or ddiv instruction DIVISION, which has the operands
9428 given by OPERANDS. Add in a divide-by-zero check if needed.
9430 When working around R4000 and R4400 errata, we need to make sure that
9431 the division is not immediately followed by a shift[1][2]. We also
9432 need to stop the division from being put into a branch delay slot[3].
9433 The easiest way to avoid both problems is to add a nop after the
9434 division. When a divide-by-zero check is needed, this nop can be
9435 used to fill the branch delay slot.
9437 [1] If a double-word or a variable shift executes immediately
9438 after starting an integer division, the shift may give an
9439 incorrect result. See quotations of errata #16 and #28 from
9440 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9441 in mips.md for details.
9443 [2] A similar bug to [1] exists for all revisions of the
9444 R4000 and the R4400 when run in an MC configuration.
9445 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9447 "19. In this following sequence:
9449 ddiv (or ddivu or div or divu)
9450 dsll32 (or dsrl32, dsra32)
9452 if an MPT stall occurs, while the divide is slipping the cpu
9453 pipeline, then the following double shift would end up with an
9456 Workaround: The compiler needs to avoid generating any
9457 sequence with divide followed by extended double shift."
9459 This erratum is also present in "MIPS R4400MC Errata, Processor
9460 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9461 & 3.0" as errata #10 and #4, respectively.
9463 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9464 (also valid for MIPS R4000MC processors):
9466 "52. R4000SC: This bug does not apply for the R4000PC.
9468 There are two flavors of this bug:
9470 1) If the instruction just after divide takes an RF exception
9471 (tlb-refill, tlb-invalid) and gets an instruction cache
9472 miss (both primary and secondary) and the line which is
9473 currently in secondary cache at this index had the first
9474 data word, where the bits 5..2 are set, then R4000 would
9475 get a wrong result for the div.
9480 ------------------- # end-of page. -tlb-refill
9485 ------------------- # end-of page. -tlb-invalid
9488 2) If the divide is in the taken branch delay slot, where the
9489 target takes RF exception and gets an I-cache miss for the
9490 exception vector or where I-cache miss occurs for the
9491 target address, under the above mentioned scenarios, the
9492 div would get wrong results.
9495 j r2 # to next page mapped or unmapped
9496 div r8,r9 # this bug would be there as long
9497 # as there is an ICache miss and
9498 nop # the "data pattern" is present
9501 beq r0, r0, NextPage # to Next page
9505 This bug is present for div, divu, ddiv, and ddivu
9508 Workaround: For item 1), OS could make sure that the next page
9509 after the divide instruction is also mapped. For item 2), the
9510 compiler could make sure that the divide instruction is not in
9511 the branch delay slot."
9513 These processors have PRId values of 0x00004220 and 0x00004300 for
9514 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9517 mips_output_division (const char *division, rtx *operands)
9522 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9524 output_asm_insn (s, operands);
9527 if (TARGET_CHECK_ZERO_DIV)
9531 output_asm_insn (s, operands);
9532 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9534 else if (GENERATE_DIVIDE_TRAPS)
9536 output_asm_insn (s, operands);
9541 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9542 output_asm_insn (s, operands);
9543 s = "break\t7%)\n1:";
9549 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9550 with a final "000" replaced by "k". Ignore case.
9552 Note: this function is shared between GCC and GAS. */
9555 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9557 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9558 given++, canonical++;
9560 return ((*given == 0 && *canonical == 0)
9561 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9565 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9566 CPU name. We've traditionally allowed a lot of variation here.
9568 Note: this function is shared between GCC and GAS. */
9571 mips_matching_cpu_name_p (const char *canonical, const char *given)
9573 /* First see if the name matches exactly, or with a final "000"
9575 if (mips_strict_matching_cpu_name_p (canonical, given))
9578 /* If not, try comparing based on numerical designation alone.
9579 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9580 if (TOLOWER (*given) == 'r')
9582 if (!ISDIGIT (*given))
9585 /* Skip over some well-known prefixes in the canonical name,
9586 hoping to find a number there too. */
9587 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9589 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9591 else if (TOLOWER (canonical[0]) == 'r')
9594 return mips_strict_matching_cpu_name_p (canonical, given);
9598 /* Return the mips_cpu_info entry for the processor or ISA given
9599 by CPU_STRING. Return null if the string isn't recognized.
9601 A similar function exists in GAS. */
9603 static const struct mips_cpu_info *
9604 mips_parse_cpu (const char *cpu_string)
9606 const struct mips_cpu_info *p;
9609 /* In the past, we allowed upper-case CPU names, but it doesn't
9610 work well with the multilib machinery. */
9611 for (s = cpu_string; *s != 0; s++)
9614 warning (0, "the cpu name must be lower case");
9618 /* 'from-abi' selects the most compatible architecture for the given
9619 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9620 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9621 version. Look first at the -mgp options, if given, otherwise base
9622 the choice on MASK_64BIT in TARGET_DEFAULT. */
9623 if (strcasecmp (cpu_string, "from-abi") == 0)
9624 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9625 : ABI_NEEDS_64BIT_REGS ? 3
9626 : (TARGET_64BIT ? 3 : 1));
9628 /* 'default' has traditionally been a no-op. Probably not very useful. */
9629 if (strcasecmp (cpu_string, "default") == 0)
9632 for (p = mips_cpu_info_table; p->name != 0; p++)
9633 if (mips_matching_cpu_name_p (p->name, cpu_string))
9640 /* Return the processor associated with the given ISA level, or null
9641 if the ISA isn't valid. */
9643 static const struct mips_cpu_info *
9644 mips_cpu_info_from_isa (int isa)
9646 const struct mips_cpu_info *p;
9648 for (p = mips_cpu_info_table; p->name != 0; p++)
9655 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9656 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9657 they only hold condition code modes, and CCmode is always considered to
9658 be 4 bytes wide. All other registers are word sized. */
9661 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9663 if (ST_REG_P (regno))
9664 return ((GET_MODE_SIZE (mode) + 3) / 4);
9665 else if (! FP_REG_P (regno))
9666 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9668 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9671 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9672 all BLKmode objects are returned in memory. Under the new (N32 and
9673 64-bit MIPS ABIs) small structures are returned in a register.
9674 Objects with varying size must still be returned in memory, of
9678 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9681 return (TYPE_MODE (type) == BLKmode);
9683 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9684 || (int_size_in_bytes (type) == -1));
9688 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9690 return !TARGET_OLDABI;
9693 /* Return true if INSN is a multiply-add or multiply-subtract
9694 instruction and PREV assigns to the accumulator operand. */
9697 mips_linked_madd_p (rtx prev, rtx insn)
9701 x = single_set (insn);
9707 if (GET_CODE (x) == PLUS
9708 && GET_CODE (XEXP (x, 0)) == MULT
9709 && reg_set_p (XEXP (x, 1), prev))
9712 if (GET_CODE (x) == MINUS
9713 && GET_CODE (XEXP (x, 1)) == MULT
9714 && reg_set_p (XEXP (x, 0), prev))
9720 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9721 that may clobber hi or lo. */
9723 static rtx mips_macc_chains_last_hilo;
9725 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9726 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9729 mips_macc_chains_record (rtx insn)
9731 if (get_attr_may_clobber_hilo (insn))
9732 mips_macc_chains_last_hilo = insn;
9735 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9736 has NREADY elements, looking for a multiply-add or multiply-subtract
9737 instruction that is cumulative with mips_macc_chains_last_hilo.
9738 If there is one, promote it ahead of anything else that might
9739 clobber hi or lo. */
9742 mips_macc_chains_reorder (rtx *ready, int nready)
9746 if (mips_macc_chains_last_hilo != 0)
9747 for (i = nready - 1; i >= 0; i--)
9748 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9750 for (j = nready - 1; j > i; j--)
9751 if (recog_memoized (ready[j]) >= 0
9752 && get_attr_may_clobber_hilo (ready[j]))
9754 mips_promote_ready (ready, i, j);
9761 /* The last instruction to be scheduled. */
9763 static rtx vr4130_last_insn;
9765 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9766 points to an rtx that is initially an instruction. Nullify the rtx
9767 if the instruction uses the value of register X. */
9770 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9772 rtx *insn_ptr = data;
9775 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9779 /* Return true if there is true register dependence between vr4130_last_insn
9783 vr4130_true_reg_dependence_p (rtx insn)
9785 note_stores (PATTERN (vr4130_last_insn),
9786 vr4130_true_reg_dependence_p_1, &insn);
9790 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9791 the ready queue and that INSN2 is the instruction after it, return
9792 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9793 in which INSN1 and INSN2 can probably issue in parallel, but for
9794 which (INSN2, INSN1) should be less sensitive to instruction
9795 alignment than (INSN1, INSN2). See 4130.md for more details. */
9798 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9802 /* Check for the following case:
9804 1) there is some other instruction X with an anti dependence on INSN1;
9805 2) X has a higher priority than INSN2; and
9806 3) X is an arithmetic instruction (and thus has no unit restrictions).
9808 If INSN1 is the last instruction blocking X, it would better to
9809 choose (INSN1, X) over (INSN2, INSN1). */
9810 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9811 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9812 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9813 && recog_memoized (XEXP (dep, 0)) >= 0
9814 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9817 if (vr4130_last_insn != 0
9818 && recog_memoized (insn1) >= 0
9819 && recog_memoized (insn2) >= 0)
9821 /* See whether INSN1 and INSN2 use different execution units,
9822 or if they are both ALU-type instructions. If so, they can
9823 probably execute in parallel. */
9824 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9825 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9826 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9828 /* If only one of the instructions has a dependence on
9829 vr4130_last_insn, prefer to schedule the other one first. */
9830 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9831 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9835 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9836 is not an ALU-type instruction and if INSN1 uses the same
9837 execution unit. (Note that if this condition holds, we already
9838 know that INSN2 uses a different execution unit.) */
9839 if (class1 != VR4130_CLASS_ALU
9840 && recog_memoized (vr4130_last_insn) >= 0
9841 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9848 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9849 queue with at least two instructions. Swap the first two if
9850 vr4130_swap_insns_p says that it could be worthwhile. */
9853 vr4130_reorder (rtx *ready, int nready)
9855 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9856 mips_promote_ready (ready, nready - 2, nready - 1);
9859 /* Remove the instruction at index LOWER from ready queue READY and
9860 reinsert it in front of the instruction at index HIGHER. LOWER must
9864 mips_promote_ready (rtx *ready, int lower, int higher)
9869 new_head = ready[lower];
9870 for (i = lower; i < higher; i++)
9871 ready[i] = ready[i + 1];
9872 ready[i] = new_head;
9875 /* Implement TARGET_SCHED_REORDER. */
9878 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9879 rtx *ready, int *nreadyp, int cycle)
9881 if (!reload_completed && TUNE_MACC_CHAINS)
9884 mips_macc_chains_last_hilo = 0;
9886 mips_macc_chains_reorder (ready, *nreadyp);
9888 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9891 vr4130_last_insn = 0;
9893 vr4130_reorder (ready, *nreadyp);
9895 return mips_issue_rate ();
9898 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9901 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9904 switch (GET_CODE (PATTERN (insn)))
9908 /* Don't count USEs and CLOBBERs against the issue rate. */
9913 if (!reload_completed && TUNE_MACC_CHAINS)
9914 mips_macc_chains_record (insn);
9915 vr4130_last_insn = insn;
9921 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9922 dependencies have no cost. */
9925 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9926 rtx dep ATTRIBUTE_UNUSED, int cost)
9928 if (REG_NOTE_KIND (link) != 0)
9933 /* Return the number of instructions that can be issued per cycle. */
9936 mips_issue_rate (void)
9940 case PROCESSOR_R4130:
9941 case PROCESSOR_R5400:
9942 case PROCESSOR_R5500:
9943 case PROCESSOR_R7000:
9944 case PROCESSOR_R9000:
9948 case PROCESSOR_SB1A:
9949 /* This is actually 4, but we get better performance if we claim 3.
9950 This is partly because of unwanted speculative code motion with the
9951 larger number, and partly because in most common cases we can't
9952 reach the theoretical max of 4. */
9960 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9961 be as wide as the scheduling freedom in the DFA. */
9964 mips_multipass_dfa_lookahead (void)
9966 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9973 /* Implements a store data bypass check. We need this because the cprestore
9974 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
9975 default routine to abort. We just return false for that case. */
9976 /* ??? Should try to give a better result here than assuming false. */
9979 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
9981 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
9984 return ! store_data_bypass_p (out_insn, in_insn);
9987 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9988 return the first operand of the associated "pref" or "prefx" insn. */
9991 mips_prefetch_cookie (rtx write, rtx locality)
9993 /* store_streamed / load_streamed. */
9994 if (INTVAL (locality) <= 0)
9995 return GEN_INT (INTVAL (write) + 4);
9998 if (INTVAL (locality) <= 2)
10001 /* store_retained / load_retained. */
10002 return GEN_INT (INTVAL (write) + 6);
10005 /* MIPS builtin function support. */
10007 struct builtin_description
10009 /* The code of the main .md file instruction. See mips_builtin_type
10010 for more information. */
10011 enum insn_code icode;
10013 /* The floating-point comparison code to use with ICODE, if any. */
10014 enum mips_fp_condition cond;
10016 /* The name of the builtin function. */
10019 /* Specifies how the function should be expanded. */
10020 enum mips_builtin_type builtin_type;
10022 /* The function's prototype. */
10023 enum mips_function_type function_type;
10025 /* The target flags required for this function. */
10029 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
10030 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
10031 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10032 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10033 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
10035 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
10037 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
10038 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
10039 "__builtin_mips_" #INSN "_" #COND "_s", \
10040 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
10041 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
10042 "__builtin_mips_" #INSN "_" #COND "_d", \
10043 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
10045 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10046 The lower and upper forms require TARGET_FLAGS while the any and all
10047 forms require MASK_MIPS3D. */
10048 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
10049 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10050 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
10051 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10052 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10053 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10054 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10055 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10056 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10057 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10058 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10059 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10060 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10062 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10063 require MASK_MIPS3D. */
10064 #define CMP_4S_BUILTINS(INSN, COND) \
10065 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10066 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10067 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10069 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10070 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10071 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10074 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10075 instruction requires TARGET_FLAGS. */
10076 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10077 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10078 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10079 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10081 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10082 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10083 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10086 /* Define all the builtins related to c.cond.fmt condition COND. */
10087 #define CMP_BUILTINS(COND) \
10088 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10089 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10090 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10091 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10092 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10093 CMP_4S_BUILTINS (c, COND), \
10094 CMP_4S_BUILTINS (cabs, COND)
10096 static const struct builtin_description mips_bdesc[] =
10098 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10099 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10100 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10101 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10102 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10103 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10104 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10105 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10107 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10108 MASK_PAIRED_SINGLE_FLOAT),
10109 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10110 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10111 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10112 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10114 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10115 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10116 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10117 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10118 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10119 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10121 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10122 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10123 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10124 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10125 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10126 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10128 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10131 /* Builtin functions for the SB-1 processor. */
10133 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10135 static const struct builtin_description sb1_bdesc[] =
10137 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10140 /* Builtin functions for DSP ASE. */
10142 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10143 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10144 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10145 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10147 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10148 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10149 builtin_description fields. */
10150 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10151 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10152 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10154 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10155 branch instruction. TARGET_FLAGS is a builtin_description field. */
10156 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10157 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10158 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10160 static const struct builtin_description dsp_bdesc[] =
10162 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10163 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10164 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10165 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10166 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10167 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10168 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10169 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10170 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10171 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10172 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10173 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10174 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10175 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10176 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10177 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10178 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10179 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10180 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10181 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10182 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10183 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10184 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10185 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10186 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10187 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10188 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10189 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10190 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10191 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10192 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10193 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10194 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10195 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10196 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10197 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10198 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10199 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10200 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10201 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10202 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10203 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10204 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10205 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10206 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10207 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10208 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10209 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10210 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10211 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10212 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10213 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10214 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10215 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10216 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10217 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10218 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10219 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10220 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10221 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10222 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10223 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10224 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10225 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10226 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10227 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10228 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10229 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10230 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10231 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10232 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10233 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10234 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10235 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10236 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10237 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10238 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10239 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10240 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10241 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10242 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10243 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10244 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10245 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10246 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10247 BPOSGE_BUILTIN (32, MASK_DSP)
10250 /* This helps provide a mapping from builtin function codes to bdesc
10255 /* The builtin function table that this entry describes. */
10256 const struct builtin_description *bdesc;
10258 /* The number of entries in the builtin function table. */
10261 /* The target processor that supports these builtin functions.
10262 PROCESSOR_MAX means we enable them for all processors. */
10263 enum processor_type proc;
10266 static const struct bdesc_map bdesc_arrays[] =
10268 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
10269 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
10270 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
10273 /* Take the head of argument list *ARGLIST and convert it into a form
10274 suitable for input operand OP of instruction ICODE. Return the value
10275 and point *ARGLIST at the next element of the list. */
10278 mips_prepare_builtin_arg (enum insn_code icode,
10279 unsigned int op, tree *arglist)
10282 enum machine_mode mode;
10284 value = expand_normal (TREE_VALUE (*arglist));
10285 mode = insn_data[icode].operand[op].mode;
10286 if (!insn_data[icode].operand[op].predicate (value, mode))
10288 value = copy_to_mode_reg (mode, value);
10289 /* Check the predicate again. */
10290 if (!insn_data[icode].operand[op].predicate (value, mode))
10292 error ("invalid argument to builtin function");
10297 *arglist = TREE_CHAIN (*arglist);
10301 /* Return an rtx suitable for output operand OP of instruction ICODE.
10302 If TARGET is non-null, try to use it where possible. */
10305 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10307 enum machine_mode mode;
10309 mode = insn_data[icode].operand[op].mode;
10310 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10311 target = gen_reg_rtx (mode);
10316 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10319 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10320 enum machine_mode mode ATTRIBUTE_UNUSED,
10321 int ignore ATTRIBUTE_UNUSED)
10323 enum insn_code icode;
10324 enum mips_builtin_type type;
10325 tree fndecl, arglist;
10326 unsigned int fcode;
10327 const struct builtin_description *bdesc;
10328 const struct bdesc_map *m;
10330 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10331 arglist = TREE_OPERAND (exp, 1);
10332 fcode = DECL_FUNCTION_CODE (fndecl);
10335 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10337 if (fcode < m->size)
10340 icode = bdesc[fcode].icode;
10341 type = bdesc[fcode].builtin_type;
10351 case MIPS_BUILTIN_DIRECT:
10352 return mips_expand_builtin_direct (icode, target, arglist, true);
10354 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10355 return mips_expand_builtin_direct (icode, target, arglist, false);
10357 case MIPS_BUILTIN_MOVT:
10358 case MIPS_BUILTIN_MOVF:
10359 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10362 case MIPS_BUILTIN_CMP_ANY:
10363 case MIPS_BUILTIN_CMP_ALL:
10364 case MIPS_BUILTIN_CMP_UPPER:
10365 case MIPS_BUILTIN_CMP_LOWER:
10366 case MIPS_BUILTIN_CMP_SINGLE:
10367 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10370 case MIPS_BUILTIN_BPOSGE32:
10371 return mips_expand_builtin_bposge (type, target);
10378 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10381 mips_init_builtins (void)
10383 const struct builtin_description *d;
10384 const struct bdesc_map *m;
10385 tree types[(int) MIPS_MAX_FTYPE_MAX];
10386 tree V2SF_type_node;
10387 tree V2HI_type_node;
10388 tree V4QI_type_node;
10389 unsigned int offset;
10391 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10392 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10395 if (TARGET_PAIRED_SINGLE_FLOAT)
10397 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10399 types[MIPS_V2SF_FTYPE_V2SF]
10400 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10402 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10403 = build_function_type_list (V2SF_type_node,
10404 V2SF_type_node, V2SF_type_node, NULL_TREE);
10406 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10407 = build_function_type_list (V2SF_type_node,
10408 V2SF_type_node, V2SF_type_node,
10409 integer_type_node, NULL_TREE);
10411 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10412 = build_function_type_list (V2SF_type_node,
10413 V2SF_type_node, V2SF_type_node,
10414 V2SF_type_node, V2SF_type_node, NULL_TREE);
10416 types[MIPS_V2SF_FTYPE_SF_SF]
10417 = build_function_type_list (V2SF_type_node,
10418 float_type_node, float_type_node, NULL_TREE);
10420 types[MIPS_INT_FTYPE_V2SF_V2SF]
10421 = build_function_type_list (integer_type_node,
10422 V2SF_type_node, V2SF_type_node, NULL_TREE);
10424 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10425 = build_function_type_list (integer_type_node,
10426 V2SF_type_node, V2SF_type_node,
10427 V2SF_type_node, V2SF_type_node, NULL_TREE);
10429 types[MIPS_INT_FTYPE_SF_SF]
10430 = build_function_type_list (integer_type_node,
10431 float_type_node, float_type_node, NULL_TREE);
10433 types[MIPS_INT_FTYPE_DF_DF]
10434 = build_function_type_list (integer_type_node,
10435 double_type_node, double_type_node, NULL_TREE);
10437 types[MIPS_SF_FTYPE_V2SF]
10438 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10440 types[MIPS_SF_FTYPE_SF]
10441 = build_function_type_list (float_type_node,
10442 float_type_node, NULL_TREE);
10444 types[MIPS_SF_FTYPE_SF_SF]
10445 = build_function_type_list (float_type_node,
10446 float_type_node, float_type_node, NULL_TREE);
10448 types[MIPS_DF_FTYPE_DF]
10449 = build_function_type_list (double_type_node,
10450 double_type_node, NULL_TREE);
10452 types[MIPS_DF_FTYPE_DF_DF]
10453 = build_function_type_list (double_type_node,
10454 double_type_node, double_type_node, NULL_TREE);
10459 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10460 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10462 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10463 = build_function_type_list (V2HI_type_node,
10464 V2HI_type_node, V2HI_type_node,
10467 types[MIPS_SI_FTYPE_SI_SI]
10468 = build_function_type_list (intSI_type_node,
10469 intSI_type_node, intSI_type_node,
10472 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10473 = build_function_type_list (V4QI_type_node,
10474 V4QI_type_node, V4QI_type_node,
10477 types[MIPS_SI_FTYPE_V4QI]
10478 = build_function_type_list (intSI_type_node,
10482 types[MIPS_V2HI_FTYPE_V2HI]
10483 = build_function_type_list (V2HI_type_node,
10487 types[MIPS_SI_FTYPE_SI]
10488 = build_function_type_list (intSI_type_node,
10492 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10493 = build_function_type_list (V4QI_type_node,
10494 V2HI_type_node, V2HI_type_node,
10497 types[MIPS_V2HI_FTYPE_SI_SI]
10498 = build_function_type_list (V2HI_type_node,
10499 intSI_type_node, intSI_type_node,
10502 types[MIPS_SI_FTYPE_V2HI]
10503 = build_function_type_list (intSI_type_node,
10507 types[MIPS_V2HI_FTYPE_V4QI]
10508 = build_function_type_list (V2HI_type_node,
10512 types[MIPS_V4QI_FTYPE_V4QI_SI]
10513 = build_function_type_list (V4QI_type_node,
10514 V4QI_type_node, intSI_type_node,
10517 types[MIPS_V2HI_FTYPE_V2HI_SI]
10518 = build_function_type_list (V2HI_type_node,
10519 V2HI_type_node, intSI_type_node,
10522 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10523 = build_function_type_list (V2HI_type_node,
10524 V4QI_type_node, V2HI_type_node,
10527 types[MIPS_SI_FTYPE_V2HI_V2HI]
10528 = build_function_type_list (intSI_type_node,
10529 V2HI_type_node, V2HI_type_node,
10532 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10533 = build_function_type_list (intDI_type_node,
10534 intDI_type_node, V4QI_type_node, V4QI_type_node,
10537 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10538 = build_function_type_list (intDI_type_node,
10539 intDI_type_node, V2HI_type_node, V2HI_type_node,
10542 types[MIPS_DI_FTYPE_DI_SI_SI]
10543 = build_function_type_list (intDI_type_node,
10544 intDI_type_node, intSI_type_node, intSI_type_node,
10547 types[MIPS_V4QI_FTYPE_SI]
10548 = build_function_type_list (V4QI_type_node,
10552 types[MIPS_V2HI_FTYPE_SI]
10553 = build_function_type_list (V2HI_type_node,
10557 types[MIPS_VOID_FTYPE_V4QI_V4QI]
10558 = build_function_type_list (void_type_node,
10559 V4QI_type_node, V4QI_type_node,
10562 types[MIPS_SI_FTYPE_V4QI_V4QI]
10563 = build_function_type_list (intSI_type_node,
10564 V4QI_type_node, V4QI_type_node,
10567 types[MIPS_VOID_FTYPE_V2HI_V2HI]
10568 = build_function_type_list (void_type_node,
10569 V2HI_type_node, V2HI_type_node,
10572 types[MIPS_SI_FTYPE_DI_SI]
10573 = build_function_type_list (intSI_type_node,
10574 intDI_type_node, intSI_type_node,
10577 types[MIPS_DI_FTYPE_DI_SI]
10578 = build_function_type_list (intDI_type_node,
10579 intDI_type_node, intSI_type_node,
10582 types[MIPS_VOID_FTYPE_SI_SI]
10583 = build_function_type_list (void_type_node,
10584 intSI_type_node, intSI_type_node,
10587 types[MIPS_SI_FTYPE_PTR_SI]
10588 = build_function_type_list (intSI_type_node,
10589 ptr_type_node, intSI_type_node,
10592 types[MIPS_SI_FTYPE_VOID]
10593 = build_function_type (intSI_type_node, void_list_node);
10596 /* Iterate through all of the bdesc arrays, initializing all of the
10597 builtin functions. */
10600 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10602 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10603 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10604 if ((d->target_flags & target_flags) == d->target_flags)
10605 lang_hooks.builtin_function (d->name, types[d->function_type],
10606 d - m->bdesc + offset,
10607 BUILT_IN_MD, NULL, NULL);
10612 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10613 .md pattern and ARGLIST is the list of function arguments. TARGET,
10614 if nonnull, suggests a good place to put the result.
10615 HAS_TARGET indicates the function must return something. */
10618 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,
10621 rtx ops[MAX_RECOG_OPERANDS];
10626 /* We save target to ops[0]. */
10627 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10631 /* We need to test if arglist is not zero. Some instructions have extra
10632 clobber registers. */
10633 for (; i < insn_data[icode].n_operands && arglist != 0; i++)
10634 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10639 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10643 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10647 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10651 gcc_unreachable ();
10656 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10657 function (TYPE says which). ARGLIST is the list of arguments to the
10658 function, ICODE is the instruction that should be used to compare
10659 the first two arguments, and COND is the condition it should test.
10660 TARGET, if nonnull, suggests a good place to put the result. */
10663 mips_expand_builtin_movtf (enum mips_builtin_type type,
10664 enum insn_code icode, enum mips_fp_condition cond,
10665 rtx target, tree arglist)
10667 rtx cmp_result, op0, op1;
10669 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10670 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10671 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10672 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10674 icode = CODE_FOR_mips_cond_move_tf_ps;
10675 target = mips_prepare_builtin_target (icode, 0, target);
10676 if (type == MIPS_BUILTIN_MOVT)
10678 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10679 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10683 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10684 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10686 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10690 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10691 into TARGET otherwise. Return TARGET. */
10694 mips_builtin_branch_and_move (rtx condition, rtx target,
10695 rtx value_if_true, rtx value_if_false)
10697 rtx true_label, done_label;
10699 true_label = gen_label_rtx ();
10700 done_label = gen_label_rtx ();
10702 /* First assume that CONDITION is false. */
10703 emit_move_insn (target, value_if_false);
10705 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10706 emit_jump_insn (gen_condjump (condition, true_label));
10707 emit_jump_insn (gen_jump (done_label));
10710 /* Fix TARGET if CONDITION is true. */
10711 emit_label (true_label);
10712 emit_move_insn (target, value_if_true);
10714 emit_label (done_label);
10718 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10719 of the comparison instruction and COND is the condition it should test.
10720 ARGLIST is the list of function arguments and TARGET, if nonnull,
10721 suggests a good place to put the boolean result. */
10724 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10725 enum insn_code icode, enum mips_fp_condition cond,
10726 rtx target, tree arglist)
10728 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10731 if (target == 0 || GET_MODE (target) != SImode)
10732 target = gen_reg_rtx (SImode);
10734 /* Prepare the operands to the comparison. */
10735 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10736 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
10737 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10739 switch (insn_data[icode].n_operands)
10742 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10746 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10747 ops[3], ops[4], GEN_INT (cond)));
10751 gcc_unreachable ();
10754 /* If the comparison sets more than one register, we define the result
10755 to be 0 if all registers are false and -1 if all registers are true.
10756 The value of the complete result is indeterminate otherwise. */
10757 switch (builtin_type)
10759 case MIPS_BUILTIN_CMP_ALL:
10760 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10761 return mips_builtin_branch_and_move (condition, target,
10762 const0_rtx, const1_rtx);
10764 case MIPS_BUILTIN_CMP_UPPER:
10765 case MIPS_BUILTIN_CMP_LOWER:
10766 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10767 condition = gen_single_cc (cmp_result, offset);
10768 return mips_builtin_branch_and_move (condition, target,
10769 const1_rtx, const0_rtx);
10772 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10773 return mips_builtin_branch_and_move (condition, target,
10774 const1_rtx, const0_rtx);
10778 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10779 suggests a good place to put the boolean result. */
10782 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10784 rtx condition, cmp_result;
10787 if (target == 0 || GET_MODE (target) != SImode)
10788 target = gen_reg_rtx (SImode);
10790 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10792 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10797 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10798 return mips_builtin_branch_and_move (condition, target,
10799 const1_rtx, const0_rtx);
10802 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10803 FIRST is true if this is the first time handling this decl. */
10806 mips_encode_section_info (tree decl, rtx rtl, int first)
10808 default_encode_section_info (decl, rtl, first);
10810 if (TREE_CODE (decl) == FUNCTION_DECL
10811 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
10813 rtx symbol = XEXP (rtl, 0);
10814 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
10818 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. PIC_FUNCTION_ADDR_REGNUM is live
10819 on entry to a function when generating -mshared abicalls code. */
10822 mips_extra_live_on_entry (bitmap regs)
10824 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
10825 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10828 /* SImode values are represented as sign-extended to DImode. */
10831 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10833 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10834 return SIGN_EXTEND;
10839 #include "gt-mips.h"